lael-labs/linux

Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt+1−0

@@ -6,6 +6,7 @@ Required properties: · 5 unmodified lines
6	"ti,da830-mcasp-audio" : for both DA830 & DA850 platforms	6	"ti,da830-mcasp-audio" : for both DA830 & DA850 platforms
7	"ti,am33xx-mcasp-audio" : for AM33xx platforms (AM33xx, AM43xx, TI81xx)	7	"ti,am33xx-mcasp-audio" : for AM33xx platforms (AM33xx, AM43xx, TI81xx)
8	"ti,dra7-mcasp-audio" : for DRA7xx platforms	8	"ti,dra7-mcasp-audio" : for DRA7xx platforms
		9	"ti,omap4-mcasp-audio" : for OMAP4
9		10
10	- reg : Should contain reg specifiers for the entries in the reg-names property.	11	- reg : Should contain reg specifiers for the entries in the reg-names property.
11	- reg-names : Should contain:	12	- reg-names : Should contain:

Documentation/devicetree/bindings/sound/ics43432.txt+4−2

@@ -1,4 +1,4 @@
1	Invensense ICS-43432 MEMS microphone with I2S output.	1	Invensense ICS-43432-compatible MEMS microphone with I2S output.
2		2
3	There are no software configuration options for this device, indeed, the only	3	There are no software configuration options for this device, indeed, the only
4	host connection is the I2S interface. Apart from requirements on clock	4	host connection is the I2S interface. Apart from requirements on clock
@@ -8,7 +8,9 @@ contain audio data. A hardware pin determines if the device outputs data · 3 unmodified lines
8	on the left or right channel of the I2S frame.	8	on the left or right channel of the I2S frame.
9		9
10	Required properties:	10	Required properties:
11	- compatible : Must be "invensense,ics43432"	11	- compatible: should be one of the following.
		12	"invensense,ics43432": For the Invensense ICS43432
		13	"cui,cmm-4030d-261": For the CUI CMM-4030D-261-I2S-TR
12		14
13	Example:	15	Example:
14		16

Documentation/devicetree/bindings/sound/mt8195-afe-pcm.yaml+184−0

@@ -0,0 +1,184 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/sound/mt8195-afe-pcm.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Mediatek AFE PCM controller for mt8195
	8
	9	maintainers:
	10	- Trevor Wu <trevor.wu@mediatek.com>
	11
	12	properties:
	13	compatible:
	14	const: mediatek,mt8195-audio
	15
	16	reg:
	17	maxItems: 1
	18
	19	interrupts:
	20	maxItems: 1
	21
	22	mediatek,topckgen:
	23	$ref: "/schemas/types.yaml#/definitions/phandle"
	24	description: The phandle of the mediatek topckgen controller
	25
	26	power-domains:
	27	maxItems: 1
	28
	29	clocks:
	30	items:
	31	- description: 26M clock
	32	- description: audio pll1 clock
	33	- description: audio pll2 clock
	34	- description: clock divider for i2si1_mck
	35	- description: clock divider for i2si2_mck
	36	- description: clock divider for i2so1_mck
	37	- description: clock divider for i2so2_mck
	38	- description: clock divider for dptx_mck
	39	- description: a1sys hoping clock
	40	- description: audio intbus clock
	41	- description: audio hires clock
	42	- description: audio local bus clock
	43	- description: mux for dptx_mck
	44	- description: mux for i2so1_mck
	45	- description: mux for i2so2_mck
	46	- description: mux for i2si1_mck
	47	- description: mux for i2si2_mck
	48	- description: audio infra 26M clock
	49	- description: infra bus clock
	50
	51	clock-names:
	52	items:
	53	- const: clk26m
	54	- const: apll1_ck
	55	- const: apll2_ck
	56	- const: apll12_div0
	57	- const: apll12_div1
	58	- const: apll12_div2
	59	- const: apll12_div3
	60	- const: apll12_div9
	61	- const: a1sys_hp_sel
	62	- const: aud_intbus_sel
	63	- const: audio_h_sel
	64	- const: audio_local_bus_sel
	65	- const: dptx_m_sel
	66	- const: i2so1_m_sel
	67	- const: i2so2_m_sel
	68	- const: i2si1_m_sel
	69	- const: i2si2_m_sel
	70	- const: infra_ao_audio_26m_b
	71	- const: scp_adsp_audiodsp
	72
	73	mediatek,etdm-in1-chn-disabled:
	74	$ref: /schemas/types.yaml#/definitions/uint8-array
	75	maxItems: 24
	76	description: Specify which input channel should be disabled.
	77
	78	mediatek,etdm-in2-chn-disabled:
	79	$ref: /schemas/types.yaml#/definitions/uint8-array
	80	maxItems: 16
	81	description: Specify which input channel should be disabled.
	82
	83	patternProperties:
	84	"^mediatek,etdm-in[1-2]-mclk-always-on-rate-hz$":
	85	description: Specify etdm in mclk output rate for always on case.
	86
	87	"^mediatek,etdm-out[1-3]-mclk-always-on-rate-hz$":
	88	description: Specify etdm out mclk output rate for always on case.
	89
	90	"^mediatek,etdm-in[1-2]-multi-pin-mode$":
	91	type: boolean
	92	description: if present, the etdm data mode is I2S.
	93
	94	"^mediatek,etdm-out[1-3]-multi-pin-mode$":
	95	type: boolean
	96	description: if present, the etdm data mode is I2S.
	97
	98	"^mediatek,etdm-in[1-2]-cowork-source$":
	99	$ref: /schemas/types.yaml#/definitions/uint32
	100	description: \|
	101	etdm modules can share the same external clock pin. Specify
	102	which etdm clock source is required by this etdm in moudule.
	103	enum:
	104	- 0 # etdm1_in
	105	- 1 # etdm2_in
	106	- 2 # etdm1_out
	107	- 3 # etdm2_out
	108
	109	"^mediatek,etdm-out[1-2]-cowork-source$":
	110	$ref: /schemas/types.yaml#/definitions/uint32
	111	description: \|
	112	etdm modules can share the same external clock pin. Specify
	113	which etdm clock source is required by this etdm out moudule.
	114	enum:
	115	- 0 # etdm1_in
	116	- 1 # etdm2_in
	117	- 2 # etdm1_out
	118	- 3 # etdm2_out
	119
	120	required:
	121	- compatible
	122	- reg
	123	- interrupts
	124	- mediatek,topckgen
	125	- power-domains
	126	- clocks
	127	- clock-names
	128
	129	additionalProperties: false
	130
	131	examples:
	132	- \|
	133	#include <dt-bindings/clock/mt8195-clk.h>
	134	#include <dt-bindings/interrupt-controller/arm-gic.h>
	135	#include <dt-bindings/interrupt-controller/irq.h>
	136	#include <dt-bindings/power/mt8195-power.h>
	137
	138	afe: mt8195-afe-pcm@10890000 {
	139	compatible = "mediatek,mt8195-audio";
	140	reg = <0x10890000 0x10000>;
	141	interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
	142	mediatek,topckgen = <&topckgen>;
	143	power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
	144	clocks = <&clk26m>,
	145	<&topckgen CLK_TOP_APLL1>,
	146	<&topckgen CLK_TOP_APLL2>,
	147	<&topckgen CLK_TOP_APLL12_DIV0>,
	148	<&topckgen CLK_TOP_APLL12_DIV1>,
	149	<&topckgen CLK_TOP_APLL12_DIV2>,
	150	<&topckgen CLK_TOP_APLL12_DIV3>,
	151	<&topckgen CLK_TOP_APLL12_DIV9>,
	152	<&topckgen CLK_TOP_A1SYS_HP_SEL>,
	153	<&topckgen CLK_TOP_AUD_INTBUS_SEL>,
	154	<&topckgen CLK_TOP_AUDIO_H_SEL>,
	155	<&topckgen CLK_TOP_AUDIO_LOCAL_BUS_SEL>,
	156	<&topckgen CLK_TOP_DPTX_M_SEL>,
	157	<&topckgen CLK_TOP_I2SO1_M_SEL>,
	158	<&topckgen CLK_TOP_I2SO2_M_SEL>,
	159	<&topckgen CLK_TOP_I2SI1_M_SEL>,
	160	<&topckgen CLK_TOP_I2SI2_M_SEL>,
	161	<&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>,
	162	<&scp_adsp CLK_SCP_ADSP_AUDIODSP>;
	163	clock-names = "clk26m",
	164	"apll1_ck",
	165	"apll2_ck",
	166	"apll12_div0",
	167	"apll12_div1",
	168	"apll12_div2",
	169	"apll12_div3",
	170	"apll12_div9",
	171	"a1sys_hp_sel",
	172	"aud_intbus_sel",
	173	"audio_h_sel",
	174	"audio_local_bus_sel",
	175	"dptx_m_sel",
	176	"i2so1_m_sel",
	177	"i2so2_m_sel",
	178	"i2si1_m_sel",
	179	"i2si2_m_sel",
	180	"infra_ao_audio_26m_b",
	181	"scp_adsp_audiodsp";
	182	};
	183
	184	...

Documentation/devicetree/bindings/sound/mt8195-mt6359-rt1019-rt5682.yaml+47−0

@@ -0,0 +1,47 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/sound/mt8195-mt6359-rt1019-rt5682.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Mediatek MT8195 with MT6359, RT1019 and RT5682 ASoC sound card driver
	8
	9	maintainers:
	10	- Trevor Wu <trevor.wu@mediatek.com>
	11
	12	description:
	13	This binding describes the MT8195 sound card.
	14
	15	properties:
	16	compatible:
	17	const: mediatek,mt8195_mt6359_rt1019_rt5682
	18
	19	mediatek,platform:
	20	$ref: "/schemas/types.yaml#/definitions/phandle"
	21	description: The phandle of MT8195 ASoC platform.
	22
	23	mediatek,dptx-codec:
	24	$ref: "/schemas/types.yaml#/definitions/phandle"
	25	description: The phandle of MT8195 Display Port Tx codec node.
	26
	27	mediatek,hdmi-codec:
	28	$ref: "/schemas/types.yaml#/definitions/phandle"
	29	description: The phandle of MT8195 HDMI codec node.
	30
	31	additionalProperties: false
	32
	33	required:
	34	- compatible
	35	- mediatek,platform
	36
	37	examples:
	38	- \|
	39
	40	sound: mt8195-sound {
	41	compatible = "mediatek,mt8195_mt6359_rt1019_rt5682";
	42	mediatek,platform = <&afe>;
	43	pinctrl-names = "default";
	44	pinctrl-0 = <&aud_pins_default>;
	45	};
	46
	47	...

Documentation/devicetree/bindings/sound/realtek,rt1015p.yaml+3−1

@@ -15,7 +15,9 @@ description: \| · 14 unmodified lines
15		15
16	properties:	16	properties:
17	compatible:	17	compatible:
18	const: realtek,rt1015p	18	enum:
		19	- realtek,rt1015p
		20	- realtek,rt1019p
19		21
20	sdb-gpios:	22	sdb-gpios:
21	description:	23	description:

Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml+118−0

@@ -0,0 +1,118 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/sound/renesas,rz-ssi.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Renesas RZ/G2L ASoC Sound Serial Interface (SSIF-2)
	8
	9	maintainers:
	10	- Biju Das <biju.das.jz@bp.renesas.com>
	11
	12	properties:
	13	compatible:
	14	items:
	15	- enum:
	16	- renesas,r9a07g044-ssi # RZ/G2{L,LC}
	17	- const: renesas,rz-ssi
	18
	19	reg:
	20	maxItems: 1
	21
	22	interrupts:
	23	maxItems: 4
	24
	25	interrupt-names:
	26	items:
	27	- const: int_req
	28	- const: dma_rx
	29	- const: dma_tx
	30	- const: dma_rt
	31
	32	clocks:
	33	maxItems: 4
	34
	35	clock-names:
	36	items:
	37	- const: ssi
	38	- const: ssi_sfr
	39	- const: audio_clk1
	40	- const: audio_clk2
	41
	42	power-domains:
	43	maxItems: 1
	44
	45	resets:
	46	maxItems: 1
	47
	48	dmas:
	49	minItems: 1
	50	maxItems: 2
	51	description:
	52	The first cell represents a phandle to dmac
	53	The second cell specifies the encoded MID/RID values of the SSI port
	54	connected to the DMA client and the slave channel configuration
	55	parameters.
	56	bits[0:9] - Specifies MID/RID value of a SSI channel as below
	57	MID/RID value of SSI rx0 = 0x256
	58	MID/RID value of SSI tx0 = 0x255
	59	MID/RID value of SSI rx1 = 0x25a
	60	MID/RID value of SSI tx1 = 0x259
	61	MID/RID value of SSI rt2 = 0x25f
	62	MID/RID value of SSI rx3 = 0x262
	63	MID/RID value of SSI tx3 = 0x261
	64	bit[10] - HIEN = 1, Detects a request in response to the rising edge
	65	of the signal
	66	bit[11] - LVL = 0, Detects based on the edge
	67	bits[12:14] - AM = 2, Bus cycle mode
	68	bit[15] - TM = 0, Single transfer mode
	69
	70	dma-names:
	71	oneOf:
	72	- items:
	73	- const: tx
	74	- const: rx
	75	- items:
	76	- const: rt
	77
	78	'#sound-dai-cells':
	79	const: 0
	80
	81	required:
	82	- compatible
	83	- reg
	84	- interrupts
	85	- interrupt-names
	86	- clocks
	87	- clock-names
	88	- resets
	89	- '#sound-dai-cells'
	90
	91	additionalProperties: false
	92
	93	examples:
	94	- \|
	95	#include <dt-bindings/interrupt-controller/arm-gic.h>
	96	#include <dt-bindings/clock/r9a07g044-cpg.h>
	97
	98	ssi0: ssi@10049c00 {
	99	compatible = "renesas,r9a07g044-ssi",
	100	"renesas,rz-ssi";
	101	reg = <0x10049c00 0x400>;
	102	interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
	103	<GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
	104	<GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
	105	<GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
	106	interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
	107	clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
	108	<&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
	109	<&audio_clk1>,
	110	<&audio_clk2>;
	111	clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
	112	power-domains = <&cpg>;
	113	resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
	114	dmas = <&dmac 0x2655>,
	115	<&dmac 0x2656>;
	116	dma-names = "tx", "rx";
	117	#sound-dai-cells = <0>;
	118	};

Documentation/devicetree/bindings/sound/rockchip-i2s.yaml+11−0

       - items:
           - enum:
               - rockchip,px30-i2s
+              - rockchip,rk1808-i2s
               - rockchip,rk3036-i2s
+              - rockchip,rk3128-i2s
               - rockchip,rk3188-i2s
               - rockchip,rk3228-i2s
               - rockchip,rk3288-i2s
               - rockchip,rk3366-i2s
               - rockchip,rk3368-i2s
               - rockchip,rk3399-i2s
+              - rockchip,rv1126-i2s
           - const: rockchip,rk3066-i2s
   reg:
   power-domains:
     maxItems: 1
+  reset-names:
+    items:
+      - const: reset-m
+      - const: reset-h
+  resets:
+    maxItems: 2
   rockchip,capture-channels:
     $ref: /schemas/types.yaml#/definitions/uint32
     default: 2

Documentation/devicetree/bindings/sound/rockchip-spdif.yaml+1−0

@@ -23,6 +23,7 @@ properties: · 22 unmodified lines
23	- const: rockchip,rk3366-spdif	23	- const: rockchip,rk3366-spdif
24	- const: rockchip,rk3368-spdif	24	- const: rockchip,rk3368-spdif
25	- const: rockchip,rk3399-spdif	25	- const: rockchip,rk3399-spdif
		26	- const: rockchip,rk3568-spdif
26	- items:	27	- items:
27	- enum:	28	- enum:
28	- rockchip,rk3188-spdif	29	- rockchip,rk3188-spdif

Documentation/devicetree/bindings/vendor-prefixes.yaml+2−0

     description: Shenzen Chuangsiqi Technology Co.,Ltd.
   "^cubietech,.*":
     description: Cubietech, Ltd.
+  "^cui,.*":
+    description: CUI Devices
   "^cypress,.*":
     description: Cypress Semiconductor Corporation
   "^cznic,.*":

drivers/soundwire/intel.c+0−74

@@ -40,80 +40,6 @@ static int md_flags; · 39 unmodified lines
40	module_param_named(sdw_md_flags, md_flags, int, 0444);	40	module_param_named(sdw_md_flags, md_flags, int, 0444);
41	MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)");	41	MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)");
42		42
43	/* Intel SHIM Registers Definition */
44	#define SDW_SHIM_LCAP 0x0
45	#define SDW_SHIM_LCTL 0x4
46	#define SDW_SHIM_IPPTR 0x8
47	#define SDW_SHIM_SYNC 0xC
48
49	#define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
50	#define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
51	#define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
52	#define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
53	#define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
54	#define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
55
56	#define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
57	#define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
58	#define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x))
59	#define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
60	#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
61
62	#define SDW_SHIM_WAKEEN 0x190
63	#define SDW_SHIM_WAKESTS 0x192
64
65	#define SDW_SHIM_LCTL_SPA BIT(0)
66	#define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0)
67	#define SDW_SHIM_LCTL_CPA BIT(8)
68	#define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8)
69
70	#define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
71	#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
72	#define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
73	#define SDW_SHIM_SYNC_SYNCCPU BIT(15)
74	#define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
75	#define SDW_SHIM_SYNC_CMDSYNC BIT(16)
76	#define SDW_SHIM_SYNC_SYNCGO BIT(24)
77
78	#define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
79	#define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
80	#define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
81
82	#define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
83	#define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
84	#define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
85	#define SDW_SHIM_PCMSYCM_DIR BIT(15)
86
87	#define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0)
88	#define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4)
89	#define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8)
90	#define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13)
91
92	#define SDW_SHIM_IOCTL_MIF BIT(0)
93	#define SDW_SHIM_IOCTL_CO BIT(1)
94	#define SDW_SHIM_IOCTL_COE BIT(2)
95	#define SDW_SHIM_IOCTL_DO BIT(3)
96	#define SDW_SHIM_IOCTL_DOE BIT(4)
97	#define SDW_SHIM_IOCTL_BKE BIT(5)
98	#define SDW_SHIM_IOCTL_WPDD BIT(6)
99	#define SDW_SHIM_IOCTL_CIBD BIT(8)
100	#define SDW_SHIM_IOCTL_DIBD BIT(9)
101
102	#define SDW_SHIM_CTMCTL_DACTQE BIT(0)
103	#define SDW_SHIM_CTMCTL_DODS BIT(1)
104	#define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
105
106	#define SDW_SHIM_WAKEEN_ENABLE BIT(0)
107	#define SDW_SHIM_WAKESTS_STATUS BIT(0)
108
109	/* Intel ALH Register definitions */
110	#define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
111	#define SDW_ALH_NUM_STREAMS 64
112
113	#define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
114	#define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
115	#define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
116
117	enum intel_pdi_type {	43	enum intel_pdi_type {
118	INTEL_PDI_IN = 0,	44	INTEL_PDI_IN = 0,
119	INTEL_PDI_OUT = 1,	45	INTEL_PDI_OUT = 1,

drivers/soundwire/intel_init.c+5−9

 #include "cadence_master.h"
 #include "intel.h"
-#define SDW_SHIM_LCAP		0x0
-#define SDW_SHIM_BASE		0x2C000
-#define SDW_ALH_BASE		0x2C800
-#define SDW_LINK_BASE		0x30000
-#define SDW_LINK_SIZE		0x10000
 static void intel_link_dev_release(struct device *dev)
 {
 	struct auxiliary_device *auxdev = to_auxiliary_dev(dev);
 	link->mmio_base = res->mmio_base;
 	link->registers = res->mmio_base + SDW_LINK_BASE
 		+ (SDW_LINK_SIZE * link_id);
-	link->shim = res->mmio_base + SDW_SHIM_BASE;
+	link->shim = res->mmio_base + res->shim_base;
-	link->alh = res->mmio_base + SDW_ALH_BASE;
+	link->alh = res->mmio_base + res->alh_base;
 	link->ops = res->ops;
 	link->dev = res->dev;
 	}
 	ctx->mmio_base = res->mmio_base;
+	ctx->shim_base = res->shim_base;
+	ctx->alh_base = res->alh_base;
 	ctx->link_mask = res->link_mask;
 	ctx->handle = res->handle;
 	mutex_init(&ctx->shim_lock);
 		return -EINVAL;
 	/* Check SNDWLCAP.LCOUNT */
-	caps = ioread32(ctx->mmio_base + SDW_SHIM_BASE + SDW_SHIM_LCAP);
+	caps = ioread32(ctx->mmio_base + ctx->shim_base + SDW_SHIM_LCAP);
 	caps &= GENMASK(2, 0);
 	/* Check HW supported vs property value */

include/linux/platform_data/davinci_asp.h+1−0

@@ -96,6 +96,7 @@ enum { · 95 unmodified lines
96	MCASP_VERSION_2, /* DA8xx/OMAPL1x */	96	MCASP_VERSION_2, /* DA8xx/OMAPL1x */
97	MCASP_VERSION_3, /* TI81xx/AM33xx */	97	MCASP_VERSION_3, /* TI81xx/AM33xx */
98	MCASP_VERSION_4, /* DRA7xxx */	98	MCASP_VERSION_4, /* DRA7xxx */
		99	MCASP_VERSION_OMAP, /* OMAP4/5 */
99	};	100	};
100		101
101	enum mcbsp_clk_input_pin {	102	enum mcbsp_clk_input_pin {

include/linux/soundwire/sdw_intel.h+87−0

@@ -7,6 +7,85 @@ · 6 unmodified lines
7	#include <linux/irqreturn.h>	7	#include <linux/irqreturn.h>
8	#include <linux/soundwire/sdw.h>	8	#include <linux/soundwire/sdw.h>
9		9
		10	#define SDW_SHIM_BASE 0x2C000
		11	#define SDW_ALH_BASE 0x2C800
		12	#define SDW_LINK_BASE 0x30000
		13	#define SDW_LINK_SIZE 0x10000
		14
		15	/* Intel SHIM Registers Definition */
		16	#define SDW_SHIM_LCAP 0x0
		17	#define SDW_SHIM_LCTL 0x4
		18	#define SDW_SHIM_IPPTR 0x8
		19	#define SDW_SHIM_SYNC 0xC
		20
		21	#define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
		22	#define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
		23	#define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
		24	#define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
		25	#define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
		26	#define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
		27
		28	#define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
		29	#define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
		30	#define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x))
		31	#define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
		32	#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
		33
		34	#define SDW_SHIM_WAKEEN 0x190
		35	#define SDW_SHIM_WAKESTS 0x192
		36
		37	#define SDW_SHIM_LCTL_SPA BIT(0)
		38	#define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0)
		39	#define SDW_SHIM_LCTL_CPA BIT(8)
		40	#define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8)
		41
		42	#define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
		43	#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
		44	#define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
		45	#define SDW_SHIM_SYNC_SYNCCPU BIT(15)
		46	#define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
		47	#define SDW_SHIM_SYNC_CMDSYNC BIT(16)
		48	#define SDW_SHIM_SYNC_SYNCGO BIT(24)
		49
		50	#define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
		51	#define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
		52	#define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
		53
		54	#define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
		55	#define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
		56	#define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
		57	#define SDW_SHIM_PCMSYCM_DIR BIT(15)
		58
		59	#define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0)
		60	#define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4)
		61	#define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8)
		62	#define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13)
		63
		64	#define SDW_SHIM_IOCTL_MIF BIT(0)
		65	#define SDW_SHIM_IOCTL_CO BIT(1)
		66	#define SDW_SHIM_IOCTL_COE BIT(2)
		67	#define SDW_SHIM_IOCTL_DO BIT(3)
		68	#define SDW_SHIM_IOCTL_DOE BIT(4)
		69	#define SDW_SHIM_IOCTL_BKE BIT(5)
		70	#define SDW_SHIM_IOCTL_WPDD BIT(6)
		71	#define SDW_SHIM_IOCTL_CIBD BIT(8)
		72	#define SDW_SHIM_IOCTL_DIBD BIT(9)
		73
		74	#define SDW_SHIM_CTMCTL_DACTQE BIT(0)
		75	#define SDW_SHIM_CTMCTL_DODS BIT(1)
		76	#define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
		77
		78	#define SDW_SHIM_WAKEEN_ENABLE BIT(0)
		79	#define SDW_SHIM_WAKESTS_STATUS BIT(0)
		80
		81	/* Intel ALH Register definitions */
		82	#define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
		83	#define SDW_ALH_NUM_STREAMS 64
		84
		85	#define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
		86	#define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
		87	#define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
		88
10	/**	89	/**
11	* struct sdw_intel_stream_params_data: configuration passed during	90	* struct sdw_intel_stream_params_data: configuration passed during
12	* the @params_stream callback, e.g. for interaction with DSP	91	* the @params_stream callback, e.g. for interaction with DSP
@@ -116,6 +195,8 @@ struct sdw_intel_slave_id { · 103 unmodified lines
116	* @link_list: list to handle interrupts across all links	195	* @link_list: list to handle interrupts across all links
117	* @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers.	196	* @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers.
118	* @shim_mask: flags to track initialization of SHIM shared registers	197	* @shim_mask: flags to track initialization of SHIM shared registers
		198	* @shim_base: sdw shim base.
		199	* @alh_base: sdw alh base.
119	*/	200	*/
120	struct sdw_intel_ctx {	201	struct sdw_intel_ctx {
121	int count;	202	int count;
@@ -128,6 +209,8 @@ struct sdw_intel_ctx { · 6 unmodified lines
128	struct list_head link_list;	209	struct list_head link_list;
129	struct mutex shim_lock; /* lock for access to shared SHIM registers */	210	struct mutex shim_lock; /* lock for access to shared SHIM registers */
130	u32 shim_mask;	211	u32 shim_mask;
		212	u32 shim_base;
		213	u32 alh_base;
131	};	214	};
132		215
133	/**	216	/**
@@ -146,6 +229,8 @@ struct sdw_intel_ctx { · 12 unmodified lines
146	* machine-specific quirks are handled in the DSP driver.	229	* machine-specific quirks are handled in the DSP driver.
147	* @clock_stop_quirks: mask array of possible behaviors requested by the	230	* @clock_stop_quirks: mask array of possible behaviors requested by the
148	* DSP driver. The quirks are common for all links for now.	231	* DSP driver. The quirks are common for all links for now.
		232	* @shim_base: sdw shim base.
		233	* @alh_base: sdw alh base.
149	*/	234	*/
150	struct sdw_intel_res {	235	struct sdw_intel_res {
151	int count;	236	int count;
@@ -157,6 +242,8 @@ struct sdw_intel_res { · 5 unmodified lines
157	struct device *dev;	242	struct device *dev;
158	u32 link_mask;	243	u32 link_mask;
159	u32 clock_stop_quirks;	244	u32 clock_stop_quirks;
		245	u32 shim_base;
		246	u32 alh_base;
160	};	247	};
161		248
162	/*	249	/*

include/sound/sof.h+1−0

@@ -101,5 +101,6 @@ struct sof_dev_desc { · 100 unmodified lines
101	};	101	};
102		102
103	int sof_dai_get_mclk(struct snd_soc_pcm_runtime *rtd);	103	int sof_dai_get_mclk(struct snd_soc_pcm_runtime *rtd);
		104	int sof_dai_get_bclk(struct snd_soc_pcm_runtime *rtd);
104		105
105	#endif	106	#endif

include/uapi/sound/snd_sst_tokens.h+5−1

@@ -233,6 +233,8 @@ · 232 unmodified lines
233	*	233	*
234	* %SKL_TKN_U32_ASTATE_CLK_SRC: Clock source for A-State entry	234	* %SKL_TKN_U32_ASTATE_CLK_SRC: Clock source for A-State entry
235	*	235	*
		236	* %SKL_TKN_U32_FMT_CFG_IDX: Format config index
		237	*
236	* module_id and loadable flags dont have tokens as these values will be	238	* module_id and loadable flags dont have tokens as these values will be
237	* read from the DSP FW manifest	239	* read from the DSP FW manifest
238	*	240	*
@@ -324,7 +326,9 @@ enum SKL_TKNS { · 85 unmodified lines
324	SKL_TKN_U32_ASTATE_COUNT,	326	SKL_TKN_U32_ASTATE_COUNT,
325	SKL_TKN_U32_ASTATE_KCPS,	327	SKL_TKN_U32_ASTATE_KCPS,
326	SKL_TKN_U32_ASTATE_CLK_SRC,	328	SKL_TKN_U32_ASTATE_CLK_SRC,
327	SKL_TKN_MAX = SKL_TKN_U32_ASTATE_CLK_SRC,	329
		330	SKL_TKN_U32_FMT_CFG_IDX = 96,
		331	SKL_TKN_MAX = SKL_TKN_U32_FMT_CFG_IDX,
328	};	332	};
329		333
330	#endif	334	#endif

sound/soc/amd/Kconfig+9−0

@@ -52,3 +52,12 @@ config SND_SOC_AMD_RENOIR_MACH · 51 unmodified lines
52	depends on SND_SOC_AMD_RENOIR	52	depends on SND_SOC_AMD_RENOIR
53	help	53	help
54	This option enables machine driver for DMIC	54	This option enables machine driver for DMIC
		55
		56	config SND_SOC_AMD_ACP5x
		57	tristate "AMD Audio Coprocessor-v5.x I2S support"
		58	depends on X86 && PCI
		59	help
		60	This option enables ACP v5.x support on AMD platform
		61
		62	By enabling this flag build will trigger for ACP PCI driver,
		63	ACP DMA driver, CPU DAI driver.

sound/soc/amd/Makefile+1−0

@@ -10,3 +10,4 @@ obj-$(CONFIG_SND_SOC_AMD_CZ_RT5645_MACH) += snd-soc-acp-rt5645-mach.o · 9 unmodified lines
10	obj-$(CONFIG_SND_SOC_AMD_ACP3x) += raven/	10	obj-$(CONFIG_SND_SOC_AMD_ACP3x) += raven/
11	obj-$(CONFIG_SND_SOC_AMD_RV_RT5682_MACH) += snd-soc-acp-rt5682-mach.o	11	obj-$(CONFIG_SND_SOC_AMD_RV_RT5682_MACH) += snd-soc-acp-rt5682-mach.o
12	obj-$(CONFIG_SND_SOC_AMD_RENOIR) += renoir/	12	obj-$(CONFIG_SND_SOC_AMD_RENOIR) += renoir/
		13	obj-$(CONFIG_SND_SOC_AMD_ACP5x) += vangogh/

sound/soc/amd/acp-da7219-max98357a.c+3−9

 	snd_soc_card_set_drvdata(card, machine);
 	ret = devm_snd_soc_register_card(&pdev->dev, card);
 	if (ret) {
-		if (ret != -EPROBE_DEFER)
+		return dev_err_probe(&pdev->dev, ret,
-			dev_err(&pdev->dev,
+				"devm_snd_soc_register_card(%s) failed\n",
-				"devm_snd_soc_register_card(%s) failed: %d\n",
+				card->name);
-				card->name, ret);
-		else
-			dev_dbg(&pdev->dev,
-				"devm_snd_soc_register_card(%s) probe deferred: %d\n",
-				card->name, ret);
-		return ret;
 	}
 	bt_uart_enable = !device_property_read_bool(&pdev->dev,
 						    "bt-pad-enable");

sound/soc/amd/acp-pcm-dma.c+6−14

 	acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num);
 }
-/* Initialize a dma descriptor in SRAM based on descritor information passed */
+/* Initialize a dma descriptor in SRAM based on descriptor information passed */
 static void config_dma_descriptor_in_sram(void __iomem *acp_mmio,
 					  u16 descr_idx,
 					  acp_dma_dscr_transfer_t *descr_info)
 					      &dmadscr[i]);
 	}
 	pre_config_reset(acp_mmio, ch);
-	/* Configure the DMA channel with the above descriptore */
+	/* Configure the DMA channel with the above descriptor */
 	config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1,
 			       NUM_DSCRS_PER_CHANNEL,
 			       ACP_DMA_PRIORITY_LEVEL_NORMAL);
 		high |= BIT(31);
 		acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
-		/* Move to next physically contiguos page */
+		/* Move to next physically contiguous page */
 		addr += PAGE_SIZE;
 	}
 }
 		acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL);
 	}
-	/* initiailize Onion control DAGB register */
+	/* initialize Onion control DAGB register */
 	acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio,
 		      mmACP_AXI2DAGB_ONION_CNTL);
-	/* initiailize Garlic control DAGB registers */
+	/* initialize Garlic control DAGB registers */
 	acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio,
 		      mmACP_AXI2DAGB_GARLIC_CNTL);
 	acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio,
 		      mmACP_DMA_DESC_BASE_ADDR);
-	/* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */
+	/* Num of descriptors in SRAM 0x4, means 256 descriptors;(64 * 4) */
 	acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR);
 	acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK,
 		      acp_mmio, mmACP_EXTERNAL_INTR_CNTL);
 	return bytes_to_frames(runtime, pos);
 }
-static int acp_dma_mmap(struct snd_soc_component *component,
-			struct snd_pcm_substream *substream,
-			struct vm_area_struct *vma)
-{
-	return snd_pcm_lib_default_mmap(substream, vma);
-}
 static int acp_dma_prepare(struct snd_soc_component *component,
 			   struct snd_pcm_substream *substream)
 {
 	.hw_params	= acp_dma_hw_params,
 	.trigger	= acp_dma_trigger,
 	.pointer	= acp_dma_pointer,
-	.mmap		= acp_dma_mmap,
 	.prepare	= acp_dma_prepare,
 	.pcm_construct	= acp_dma_new,
 };

sound/soc/amd/acp3x-rt5682-max9836.c+4−10

@@ -512,17 +512,11 @@ static int acp3x_probe(struct platform_device *pdev) · 511 unmodified lines
512		512
513	ret = devm_snd_soc_register_card(&pdev->dev, card);	513	ret = devm_snd_soc_register_card(&pdev->dev, card);
514	if (ret) {	514	if (ret) {
515	if (ret != -EPROBE_DEFER)	515	return dev_err_probe(&pdev->dev, ret,
516	dev_err(&pdev->dev,	516	"devm_snd_soc_register_card(%s) failed\n",
517	"devm_snd_soc_register_card(%s) failed: %d\n",	517	card->name);
518	card->name, ret);
519	else
520	dev_dbg(&pdev->dev,
521	"devm_snd_soc_register_card(%s) probe deferred: %d\n",
522	card->name, ret);
523	}	518	}
524		519	return 0;
525	return ret;
526	}	520	}
527		521
528	static const struct acpi_device_id acp3x_audio_acpi_match[] = {	522	static const struct acpi_device_id acp3x_audio_acpi_match[] = {

sound/soc/amd/raven/acp3x-pcm-dma.c+1−9

 		high |= BIT(31);
 		rv_writel(high, rtd->acp3x_base + mmACP_SCRATCH_REG_0 + val
 				+ 4);
-		/* Move to next physically contiguos page */
+		/* Move to next physically contiguous page */
 		val += 8;
 		addr += PAGE_SIZE;
 	}
 	return 0;
 }
-static int acp3x_dma_mmap(struct snd_soc_component *component,
-			  struct snd_pcm_substream *substream,
-			  struct vm_area_struct *vma)
-{
-	return snd_pcm_lib_default_mmap(substream, vma);
-}
 static int acp3x_dma_close(struct snd_soc_component *component,
 			   struct snd_pcm_substream *substream)
 {
 	.close		= acp3x_dma_close,
 	.hw_params	= acp3x_dma_hw_params,
 	.pointer	= acp3x_dma_pointer,
-	.mmap		= acp3x_dma_mmap,
 	.pcm_construct	= acp3x_dma_new,
 };

sound/soc/amd/renoir/acp3x-pdm-dma.c+0−8

 	return 0;
 }
-static int acp_pdm_dma_mmap(struct snd_soc_component *component,
-			    struct snd_pcm_substream *substream,
-			    struct vm_area_struct *vma)
-{
-	return snd_pcm_lib_default_mmap(substream, vma);
-}
 static int acp_pdm_dma_close(struct snd_soc_component *component,
 			     struct snd_pcm_substream *substream)
 {
 	.close		= acp_pdm_dma_close,
 	.hw_params	= acp_pdm_dma_hw_params,
 	.pointer	= acp_pdm_dma_pointer,
-	.mmap		= acp_pdm_dma_mmap,
 	.pcm_construct	= acp_pdm_dma_new,
 };

sound/soc/amd/renoir/acp3x-rn.c+3−4

 	snd_soc_card_set_drvdata(card, machine);
 	ret = devm_snd_soc_register_card(&pdev->dev, card);
 	if (ret) {
-		dev_err(&pdev->dev,
+		return dev_err_probe(&pdev->dev, ret,
-			"snd_soc_register_card(%s) failed: %d\n",
+				"snd_soc_register_card(%s) failed\n",
-			acp_card.name, ret);
+				card->name);
-		return ret;
 	}
 	return 0;
 }

sound/soc/amd/vangogh/Makefile+9−0

@@ -0,0 +1,9 @@
	1	# SPDX-License-Identifier: GPL-2.0+
	2	# Vangogh platform Support
	3	snd-pci-acp5x-objs := pci-acp5x.o
	4	snd-acp5x-i2s-objs := acp5x-i2s.o
	5	snd-acp5x-pcm-dma-objs := acp5x-pcm-dma.o
	6
	7	obj-$(CONFIG_SND_SOC_AMD_ACP5x) += snd-pci-acp5x.o
	8	obj-$(CONFIG_SND_SOC_AMD_ACP5x) += snd-acp5x-i2s.o
	9	obj-$(CONFIG_SND_SOC_AMD_ACP5x) += snd-acp5x-pcm-dma.o

sound/soc/amd/vangogh/acp5x-i2s.c+427−0

@@ -0,0 +1,427 @@
	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// AMD ALSA SoC PCM Driver
	4	//
	5	// Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
	6
	7	#include <linux/platform_device.h>
	8	#include <linux/module.h>
	9	#include <linux/err.h>
	10	#include <linux/io.h>
	11	#include <sound/pcm_params.h>
	12	#include <sound/soc.h>
	13	#include <sound/soc-dai.h>
	14	#include <linux/dma-mapping.h>
	15
	16	#include "acp5x.h"
	17
	18	#define DRV_NAME "acp5x_i2s_playcap"
	19
	20	static int acp5x_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
	21	unsigned int fmt)
	22	{
	23	struct i2s_dev_data *adata;
	24	int mode;
	25
	26	adata = snd_soc_dai_get_drvdata(cpu_dai);
	27	mode = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
	28	switch (mode) {
	29	case SND_SOC_DAIFMT_I2S:
	30	adata->tdm_mode = TDM_DISABLE;
	31	break;
	32	case SND_SOC_DAIFMT_DSP_A:
	33	adata->tdm_mode = TDM_ENABLE;
	34	break;
	35	default:
	36	return -EINVAL;
	37	}
	38	mode = fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK;
	39	switch (mode) {
	40	case SND_SOC_DAIFMT_CBC_CFC:
	41	adata->master_mode = I2S_MASTER_MODE_ENABLE;
	42	break;
	43	case SND_SOC_DAIFMT_CBP_CFP:
	44	adata->master_mode = I2S_MASTER_MODE_DISABLE;
	45	break;
	46	}
	47	return 0;
	48	}
	49
	50	static int acp5x_i2s_set_tdm_slot(struct snd_soc_dai *cpu_dai,
	51	u32 tx_mask, u32 rx_mask,
	52	int slots, int slot_width)
	53	{
	54	struct i2s_dev_data *adata;
	55	u32 frm_len;
	56	u16 slot_len;
	57
	58	adata = snd_soc_dai_get_drvdata(cpu_dai);
	59
	60	/* These values are as per Hardware Spec */
	61	switch (slot_width) {
	62	case SLOT_WIDTH_8:
	63	slot_len = 8;
	64	break;
	65	case SLOT_WIDTH_16:
	66	slot_len = 16;
	67	break;
	68	case SLOT_WIDTH_24:
	69	slot_len = 24;
	70	break;
	71	case SLOT_WIDTH_32:
	72	slot_len = 0;
	73	break;
	74	default:
	75	return -EINVAL;
	76	}
	77	frm_len = FRM_LEN \| (slots << 15) \| (slot_len << 18);
	78	adata->tdm_fmt = frm_len;
	79	return 0;
	80	}
	81
	82	static int acp5x_i2s_hwparams(struct snd_pcm_substream *substream,
	83	struct snd_pcm_hw_params *params,
	84	struct snd_soc_dai *dai)
	85	{
	86	struct i2s_stream_instance *rtd;
	87	struct snd_soc_pcm_runtime *prtd;
	88	struct snd_soc_card *card;
	89	struct acp5x_platform_info *pinfo;
	90	struct i2s_dev_data *adata;
	91	union acp_i2stdm_mstrclkgen mclkgen;
	92
	93	u32 val;
	94	u32 reg_val, frmt_reg, master_reg;
	95	u32 lrclk_div_val, bclk_div_val;
	96
	97	lrclk_div_val = 0;
	98	bclk_div_val = 0;
	99	prtd = asoc_substream_to_rtd(substream);
	100	rtd = substream->runtime->private_data;
	101	card = prtd->card;
	102	adata = snd_soc_dai_get_drvdata(dai);
	103	pinfo = snd_soc_card_get_drvdata(card);
	104	if (pinfo) {
	105	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	106	rtd->i2s_instance = pinfo->play_i2s_instance;
	107	else
	108	rtd->i2s_instance = pinfo->cap_i2s_instance;
	109	}
	110
	111	/* These values are as per Hardware Spec */
	112	switch (params_format(params)) {
	113	case SNDRV_PCM_FORMAT_U8:
	114	case SNDRV_PCM_FORMAT_S8:
	115	rtd->xfer_resolution = 0x0;
	116	break;
	117	case SNDRV_PCM_FORMAT_S16_LE:
	118	rtd->xfer_resolution = 0x02;
	119	break;
	120	case SNDRV_PCM_FORMAT_S24_LE:
	121	rtd->xfer_resolution = 0x04;
	122	break;
	123	case SNDRV_PCM_FORMAT_S32_LE:
	124	rtd->xfer_resolution = 0x05;
	125	break;
	126	default:
	127	return -EINVAL;
	128	}
	129	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	130	switch (rtd->i2s_instance) {
	131	case I2S_HS_INSTANCE:
	132	reg_val = ACP_HSTDM_ITER;
	133	frmt_reg = ACP_HSTDM_TXFRMT;
	134	break;
	135	case I2S_SP_INSTANCE:
	136	default:
	137	reg_val = ACP_I2STDM_ITER;
	138	frmt_reg = ACP_I2STDM_TXFRMT;
	139	}
	140	} else {
	141	switch (rtd->i2s_instance) {
	142	case I2S_HS_INSTANCE:
	143	reg_val = ACP_HSTDM_IRER;
	144	frmt_reg = ACP_HSTDM_RXFRMT;
	145	break;
	146	case I2S_SP_INSTANCE:
	147	default:
	148	reg_val = ACP_I2STDM_IRER;
	149	frmt_reg = ACP_I2STDM_RXFRMT;
	150	}
	151	}
	152	if (adata->tdm_mode) {
	153	val = acp_readl(rtd->acp5x_base + reg_val);
	154	acp_writel(val \| 0x2, rtd->acp5x_base + reg_val);
	155	acp_writel(adata->tdm_fmt, rtd->acp5x_base + frmt_reg);
	156	}
	157	val = acp_readl(rtd->acp5x_base + reg_val);
	158	val &= ~ACP5x_ITER_IRER_SAMP_LEN_MASK;
	159	val = val \| (rtd->xfer_resolution << 3);
	160	acp_writel(val, rtd->acp5x_base + reg_val);
	161
	162	if (adata->master_mode) {
	163	switch (rtd->i2s_instance) {
	164	case I2S_HS_INSTANCE:
	165	master_reg = ACP_I2STDM2_MSTRCLKGEN;
	166	break;
	167	case I2S_SP_INSTANCE:
	168	default:
	169	master_reg = ACP_I2STDM0_MSTRCLKGEN;
	170	break;
	171	}
	172	mclkgen.bits.i2stdm_master_mode = 0x1;
	173	if (adata->tdm_mode)
	174	mclkgen.bits.i2stdm_format_mode = 0x01;
	175	else
	176	mclkgen.bits.i2stdm_format_mode = 0x0;
	177	switch (params_format(params)) {
	178	case SNDRV_PCM_FORMAT_S16_LE:
	179	switch (params_rate(params)) {
	180	case 8000:
	181	bclk_div_val = 768;
	182	break;
	183	case 16000:
	184	bclk_div_val = 384;
	185	break;
	186	case 24000:
	187	bclk_div_val = 256;
	188	break;
	189	case 32000:
	190	bclk_div_val = 192;
	191	break;
	192	case 44100:
	193	case 48000:
	194	bclk_div_val = 128;
	195	break;
	196	case 88200:
	197	case 96000:
	198	bclk_div_val = 64;
	199	break;
	200	case 192000:
	201	bclk_div_val = 32;
	202	break;
	203	default:
	204	return -EINVAL;
	205	}
	206	lrclk_div_val = 32;
	207	break;
	208	case SNDRV_PCM_FORMAT_S32_LE:
	209	switch (params_rate(params)) {
	210	case 8000:
	211	bclk_div_val = 384;
	212	break;
	213	case 16000:
	214	bclk_div_val = 192;
	215	break;
	216	case 24000:
	217	bclk_div_val = 128;
	218	break;
	219	case 32000:
	220	bclk_div_val = 96;
	221	break;
	222	case 44100:
	223	case 48000:
	224	bclk_div_val = 64;
	225	break;
	226	case 88200:
	227	case 96000:
	228	bclk_div_val = 32;
	229	break;
	230	case 192000:
	231	bclk_div_val = 16;
	232	break;
	233	default:
	234	return -EINVAL;
	235	}
	236	lrclk_div_val = 64;
	237	break;
	238	default:
	239	return -EINVAL;
	240	}
	241	mclkgen.bits.i2stdm_bclk_div_val = bclk_div_val;
	242	mclkgen.bits.i2stdm_lrclk_div_val = lrclk_div_val;
	243	acp_writel(mclkgen.u32_all, rtd->acp5x_base + master_reg);
	244	}
	245	return 0;
	246	}
	247
	248	static int acp5x_i2s_trigger(struct snd_pcm_substream *substream,
	249	int cmd, struct snd_soc_dai *dai)
	250	{
	251	struct i2s_stream_instance *rtd;
	252	u32 ret, val, period_bytes, reg_val, ier_val, water_val;
	253	u32 buf_size, buf_reg;
	254
	255	rtd = substream->runtime->private_data;
	256	period_bytes = frames_to_bytes(substream->runtime,
	257	substream->runtime->period_size);
	258	buf_size = frames_to_bytes(substream->runtime,
	259	substream->runtime->buffer_size);
	260	switch (cmd) {
	261	case SNDRV_PCM_TRIGGER_START:
	262	case SNDRV_PCM_TRIGGER_RESUME:
	263	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	264	rtd->bytescount = acp_get_byte_count(rtd,
	265	substream->stream);
	266	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	267	switch (rtd->i2s_instance) {
	268	case I2S_HS_INSTANCE:
	269	water_val =
	270	ACP_HS_TX_INTR_WATERMARK_SIZE;
	271	reg_val = ACP_HSTDM_ITER;
	272	ier_val = ACP_HSTDM_IER;
	273	buf_reg = ACP_HS_TX_RINGBUFSIZE;
	274	break;
	275	case I2S_SP_INSTANCE:
	276	default:
	277	water_val =
	278	ACP_I2S_TX_INTR_WATERMARK_SIZE;
	279	reg_val = ACP_I2STDM_ITER;
	280	ier_val = ACP_I2STDM_IER;
	281	buf_reg = ACP_I2S_TX_RINGBUFSIZE;
	282	}
	283	} else {
	284	switch (rtd->i2s_instance) {
	285	case I2S_HS_INSTANCE:
	286	water_val =
	287	ACP_HS_RX_INTR_WATERMARK_SIZE;
	288	reg_val = ACP_HSTDM_IRER;
	289	ier_val = ACP_HSTDM_IER;
	290	buf_reg = ACP_HS_RX_RINGBUFSIZE;
	291	break;
	292	case I2S_SP_INSTANCE:
	293	default:
	294	water_val =
	295	ACP_I2S_RX_INTR_WATERMARK_SIZE;
	296	reg_val = ACP_I2STDM_IRER;
	297	ier_val = ACP_I2STDM_IER;
	298	buf_reg = ACP_I2S_RX_RINGBUFSIZE;
	299	}
	300	}
	301	acp_writel(period_bytes, rtd->acp5x_base + water_val);
	302	acp_writel(buf_size, rtd->acp5x_base + buf_reg);
	303	val = acp_readl(rtd->acp5x_base + reg_val);
	304	val = val \| BIT(0);
	305	acp_writel(val, rtd->acp5x_base + reg_val);
	306	acp_writel(1, rtd->acp5x_base + ier_val);
	307	ret = 0;
	308	break;
	309	case SNDRV_PCM_TRIGGER_STOP:
	310	case SNDRV_PCM_TRIGGER_SUSPEND:
	311	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	312	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	313	switch (rtd->i2s_instance) {
	314	case I2S_HS_INSTANCE:
	315	reg_val = ACP_HSTDM_ITER;
	316	break;
	317	case I2S_SP_INSTANCE:
	318	default:
	319	reg_val = ACP_I2STDM_ITER;
	320	}
	321
	322	} else {
	323	switch (rtd->i2s_instance) {
	324	case I2S_HS_INSTANCE:
	325	reg_val = ACP_HSTDM_IRER;
	326	break;
	327	case I2S_SP_INSTANCE:
	328	default:
	329	reg_val = ACP_I2STDM_IRER;
	330	}
	331	}
	332	val = acp_readl(rtd->acp5x_base + reg_val);
	333	val = val & ~BIT(0);
	334	acp_writel(val, rtd->acp5x_base + reg_val);
	335
	336	if (!(acp_readl(rtd->acp5x_base + ACP_HSTDM_ITER) & BIT(0)) &&
	337	!(acp_readl(rtd->acp5x_base + ACP_HSTDM_IRER) & BIT(0)))
	338	acp_writel(0, rtd->acp5x_base + ACP_HSTDM_IER);
	339	if (!(acp_readl(rtd->acp5x_base + ACP_I2STDM_ITER) & BIT(0)) &&
	340	!(acp_readl(rtd->acp5x_base + ACP_I2STDM_IRER) & BIT(0)))
	341	acp_writel(0, rtd->acp5x_base + ACP_I2STDM_IER);
	342	ret = 0;
	343	break;
	344	default:
	345	ret = -EINVAL;
	346	break;
	347	}
	348	return ret;
	349	}
	350
	351	static struct snd_soc_dai_ops acp5x_i2s_dai_ops = {
	352	.hw_params = acp5x_i2s_hwparams,
	353	.trigger = acp5x_i2s_trigger,
	354	.set_fmt = acp5x_i2s_set_fmt,
	355	.set_tdm_slot = acp5x_i2s_set_tdm_slot,
	356	};
	357
	358	static const struct snd_soc_component_driver acp5x_dai_component = {
	359	.name = "acp5x-i2s",
	360	};
	361
	362	static struct snd_soc_dai_driver acp5x_i2s_dai = {
	363	.playback = {
	364	.rates = SNDRV_PCM_RATE_8000_96000,
	365	.formats = SNDRV_PCM_FMTBIT_S16_LE \| SNDRV_PCM_FMTBIT_S8 \|
	366	SNDRV_PCM_FMTBIT_U8 \| SNDRV_PCM_FMTBIT_S32_LE,
	367	.channels_min = 2,
	368	.channels_max = 2,
	369	.rate_min = 8000,
	370	.rate_max = 96000,
	371	},
	372	.capture = {
	373	.rates = SNDRV_PCM_RATE_8000_96000,
	374	.formats = SNDRV_PCM_FMTBIT_S16_LE \| SNDRV_PCM_FMTBIT_S8 \|
	375	SNDRV_PCM_FMTBIT_U8 \| SNDRV_PCM_FMTBIT_S32_LE,
	376	.channels_min = 2,
	377	.channels_max = 2,
	378	.rate_min = 8000,
	379	.rate_max = 96000,
	380	},
	381	.ops = &acp5x_i2s_dai_ops,
	382	};
	383
	384	static int acp5x_dai_probe(struct platform_device *pdev)
	385	{
	386	struct resource *res;
	387	struct i2s_dev_data *adata;
	388	int ret;
	389
	390	adata = devm_kzalloc(&pdev->dev, sizeof(struct i2s_dev_data),
	391	GFP_KERNEL);
	392	if (!adata)
	393	return -ENOMEM;
	394
	395	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	396	if (!res) {
	397	dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
	398	return -ENOMEM;
	399	}
	400	adata->acp5x_base = devm_ioremap(&pdev->dev, res->start,
	401	resource_size(res));
	402	if (!adata->acp5x_base)
	403	return -ENOMEM;
	404
	405	adata->master_mode = I2S_MASTER_MODE_ENABLE;
	406	dev_set_drvdata(&pdev->dev, adata);
	407	ret = devm_snd_soc_register_component(&pdev->dev,
	408	&acp5x_dai_component,
	409	&acp5x_i2s_dai, 1);
	410	if (ret)
	411	dev_err(&pdev->dev, "Fail to register acp i2s dai\n");
	412	return ret;
	413	}
	414
	415	static struct platform_driver acp5x_dai_driver = {
	416	.probe = acp5x_dai_probe,
	417	.driver = {
	418	.name = "acp5x_i2s_playcap",
	419	},
	420	};
	421
	422	module_platform_driver(acp5x_dai_driver);
	423
	424	MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
	425	MODULE_DESCRIPTION("AMD ACP5.x CPU DAI Driver");
	426	MODULE_ALIAS("platform:" DRV_NAME);
	427	MODULE_LICENSE("GPL v2");

sound/soc/amd/vangogh/acp5x-pcm-dma.c+517−0

@@ -0,0 +1,517 @@
	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// AMD ALSA SoC PCM Driver
	4	//
	5	// Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
	6
	7	#include <linux/platform_device.h>
	8	#include <linux/module.h>
	9	#include <linux/err.h>
	10	#include <linux/io.h>
	11	#include <linux/pm_runtime.h>
	12	#include <sound/pcm.h>
	13	#include <sound/pcm_params.h>
	14	#include <sound/soc.h>
	15	#include <sound/soc-dai.h>
	16
	17	#include "acp5x.h"
	18
	19	#define DRV_NAME "acp5x_i2s_dma"
	20
	21	static const struct snd_pcm_hardware acp5x_pcm_hardware_playback = {
	22	.info = SNDRV_PCM_INFO_INTERLEAVED \|
	23	SNDRV_PCM_INFO_BLOCK_TRANSFER \|
	24	SNDRV_PCM_INFO_MMAP \| SNDRV_PCM_INFO_MMAP_VALID \|
	25	SNDRV_PCM_INFO_PAUSE \| SNDRV_PCM_INFO_RESUME,
	26	.formats = SNDRV_PCM_FMTBIT_S16_LE \| SNDRV_PCM_FMTBIT_S8 \|
	27	SNDRV_PCM_FMTBIT_U8 \| SNDRV_PCM_FMTBIT_S32_LE,
	28	.channels_min = 2,
	29	.channels_max = 2,
	30	.rates = SNDRV_PCM_RATE_8000_96000,
	31	.rate_min = 8000,
	32	.rate_max = 96000,
	33	.buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,
	34	.period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
	35	.period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
	36	.periods_min = PLAYBACK_MIN_NUM_PERIODS,
	37	.periods_max = PLAYBACK_MAX_NUM_PERIODS,
	38	};
	39
	40	static const struct snd_pcm_hardware acp5x_pcm_hardware_capture = {
	41	.info = SNDRV_PCM_INFO_INTERLEAVED \|
	42	SNDRV_PCM_INFO_BLOCK_TRANSFER \|
	43	SNDRV_PCM_INFO_MMAP \| SNDRV_PCM_INFO_MMAP_VALID \|
	44	SNDRV_PCM_INFO_PAUSE \| SNDRV_PCM_INFO_RESUME,
	45	.formats = SNDRV_PCM_FMTBIT_S16_LE \| SNDRV_PCM_FMTBIT_S8 \|
	46	SNDRV_PCM_FMTBIT_U8 \| SNDRV_PCM_FMTBIT_S32_LE,
	47	.channels_min = 2,
	48	.channels_max = 2,
	49	.rates = SNDRV_PCM_RATE_8000_96000,
	50	.rate_min = 8000,
	51	.rate_max = 96000,
	52	.buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
	53	.period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
	54	.period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
	55	.periods_min = CAPTURE_MIN_NUM_PERIODS,
	56	.periods_max = CAPTURE_MAX_NUM_PERIODS,
	57	};
	58
	59	static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
	60	{
	61	struct i2s_dev_data *vg_i2s_data;
	62	u16 irq_flag;
	63	u32 val;
	64
	65	vg_i2s_data = dev_id;
	66	if (!vg_i2s_data)
	67	return IRQ_NONE;
	68
	69	irq_flag = 0;
	70	val = acp_readl(vg_i2s_data->acp5x_base + ACP_EXTERNAL_INTR_STAT);
	71	if ((val & BIT(HS_TX_THRESHOLD)) && vg_i2s_data->play_stream) {
	72	acp_writel(BIT(HS_TX_THRESHOLD), vg_i2s_data->acp5x_base +
	73	ACP_EXTERNAL_INTR_STAT);
	74	snd_pcm_period_elapsed(vg_i2s_data->play_stream);
	75	irq_flag = 1;
	76	}
	77	if ((val & BIT(I2S_TX_THRESHOLD)) && vg_i2s_data->i2ssp_play_stream) {
	78	acp_writel(BIT(I2S_TX_THRESHOLD),
	79	vg_i2s_data->acp5x_base + ACP_EXTERNAL_INTR_STAT);
	80	snd_pcm_period_elapsed(vg_i2s_data->i2ssp_play_stream);
	81	irq_flag = 1;
	82	}
	83
	84	if ((val & BIT(HS_RX_THRESHOLD)) && vg_i2s_data->capture_stream) {
	85	acp_writel(BIT(HS_RX_THRESHOLD), vg_i2s_data->acp5x_base +
	86	ACP_EXTERNAL_INTR_STAT);
	87	snd_pcm_period_elapsed(vg_i2s_data->capture_stream);
	88	irq_flag = 1;
	89	}
	90	if ((val & BIT(I2S_RX_THRESHOLD)) && vg_i2s_data->i2ssp_capture_stream) {
	91	acp_writel(BIT(I2S_RX_THRESHOLD),
	92	vg_i2s_data->acp5x_base + ACP_EXTERNAL_INTR_STAT);
	93	snd_pcm_period_elapsed(vg_i2s_data->i2ssp_capture_stream);
	94	irq_flag = 1;
	95	}
	96
	97	if (irq_flag)
	98	return IRQ_HANDLED;
	99	else
	100	return IRQ_NONE;
	101	}
	102
	103	static void config_acp5x_dma(struct i2s_stream_instance *rtd, int direction)
	104	{
	105	u16 page_idx;
	106	u32 low, high, val, acp_fifo_addr, reg_fifo_addr;
	107	u32 reg_dma_size, reg_fifo_size;
	108	dma_addr_t addr;
	109
	110	addr = rtd->dma_addr;
	111	if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
	112	switch (rtd->i2s_instance) {
	113	case I2S_HS_INSTANCE:
	114	val = ACP_SRAM_HS_PB_PTE_OFFSET;
	115	break;
	116	case I2S_SP_INSTANCE:
	117	default:
	118	val = ACP_SRAM_SP_PB_PTE_OFFSET;
	119	}
	120	} else {
	121	switch (rtd->i2s_instance) {
	122	case I2S_HS_INSTANCE:
	123	val = ACP_SRAM_HS_CP_PTE_OFFSET;
	124	break;
	125	case I2S_SP_INSTANCE:
	126	default:
	127	val = ACP_SRAM_SP_CP_PTE_OFFSET;
	128	}
	129	}
	130	/* Group Enable */
	131	acp_writel(ACP_SRAM_PTE_OFFSET \| BIT(31), rtd->acp5x_base +
	132	ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
	133	acp_writel(PAGE_SIZE_4K_ENABLE, rtd->acp5x_base +
	134	ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
	135
	136	for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) {
	137	/* Load the low address of page int ACP SRAM through SRBM */
	138	low = lower_32_bits(addr);
	139	high = upper_32_bits(addr);
	140
	141	acp_writel(low, rtd->acp5x_base + ACP_SCRATCH_REG_0 + val);
	142	high \|= BIT(31);
	143	acp_writel(high, rtd->acp5x_base + ACP_SCRATCH_REG_0 + val + 4);
	144	/* Move to next physically contiguous page */
	145	val += 8;
	146	addr += PAGE_SIZE;
	147	}
	148
	149	if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
	150	switch (rtd->i2s_instance) {
	151	case I2S_HS_INSTANCE:
	152	reg_dma_size = ACP_HS_TX_DMA_SIZE;
	153	acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
	154	HS_PB_FIFO_ADDR_OFFSET;
	155	reg_fifo_addr = ACP_HS_TX_FIFOADDR;
	156	reg_fifo_size = ACP_HS_TX_FIFOSIZE;
	157	acp_writel(I2S_HS_TX_MEM_WINDOW_START,
	158	rtd->acp5x_base + ACP_HS_TX_RINGBUFADDR);
	159	break;
	160
	161	case I2S_SP_INSTANCE:
	162	default:
	163	reg_dma_size = ACP_I2S_TX_DMA_SIZE;
	164	acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
	165	SP_PB_FIFO_ADDR_OFFSET;
	166	reg_fifo_addr = ACP_I2S_TX_FIFOADDR;
	167	reg_fifo_size = ACP_I2S_TX_FIFOSIZE;
	168	acp_writel(I2S_SP_TX_MEM_WINDOW_START,
	169	rtd->acp5x_base + ACP_I2S_TX_RINGBUFADDR);
	170	}
	171	} else {
	172	switch (rtd->i2s_instance) {
	173	case I2S_HS_INSTANCE:
	174	reg_dma_size = ACP_HS_RX_DMA_SIZE;
	175	acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
	176	HS_CAPT_FIFO_ADDR_OFFSET;
	177	reg_fifo_addr = ACP_HS_RX_FIFOADDR;
	178	reg_fifo_size = ACP_HS_RX_FIFOSIZE;
	179	acp_writel(I2S_HS_RX_MEM_WINDOW_START,
	180	rtd->acp5x_base + ACP_HS_RX_RINGBUFADDR);
	181	break;
	182
	183	case I2S_SP_INSTANCE:
	184	default:
	185	reg_dma_size = ACP_I2S_RX_DMA_SIZE;
	186	acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
	187	SP_CAPT_FIFO_ADDR_OFFSET;
	188	reg_fifo_addr = ACP_I2S_RX_FIFOADDR;
	189	reg_fifo_size = ACP_I2S_RX_FIFOSIZE;
	190	acp_writel(I2S_SP_RX_MEM_WINDOW_START,
	191	rtd->acp5x_base + ACP_I2S_RX_RINGBUFADDR);
	192	}
	193	}
	194	acp_writel(DMA_SIZE, rtd->acp5x_base + reg_dma_size);
	195	acp_writel(acp_fifo_addr, rtd->acp5x_base + reg_fifo_addr);
	196	acp_writel(FIFO_SIZE, rtd->acp5x_base + reg_fifo_size);
	197	acp_writel(BIT(I2S_RX_THRESHOLD) \| BIT(HS_RX_THRESHOLD)
	198	\| BIT(I2S_TX_THRESHOLD) \| BIT(HS_TX_THRESHOLD),
	199	rtd->acp5x_base + ACP_EXTERNAL_INTR_CNTL);
	200	}
	201
	202	static int acp5x_dma_open(struct snd_soc_component *component,
	203	struct snd_pcm_substream *substream)
	204	{
	205	struct snd_pcm_runtime *runtime;
	206	struct snd_soc_pcm_runtime *prtd;
	207	struct i2s_dev_data *adata;
	208	struct i2s_stream_instance *i2s_data;
	209	int ret;
	210
	211	runtime = substream->runtime;
	212	prtd = asoc_substream_to_rtd(substream);
	213	component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);
	214	adata = dev_get_drvdata(component->dev);
	215
	216	i2s_data = kzalloc(sizeof(*i2s_data), GFP_KERNEL);
	217	if (!i2s_data)
	218	return -ENOMEM;
	219
	220	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	221	runtime->hw = acp5x_pcm_hardware_playback;
	222	else
	223	runtime->hw = acp5x_pcm_hardware_capture;
	224
	225	ret = snd_pcm_hw_constraint_integer(runtime,
	226	SNDRV_PCM_HW_PARAM_PERIODS);
	227	if (ret < 0) {
	228	dev_err(component->dev, "set integer constraint failed\n");
	229	kfree(i2s_data);
	230	return ret;
	231	}
	232	i2s_data->acp5x_base = adata->acp5x_base;
	233	runtime->private_data = i2s_data;
	234	return ret;
	235	}
	236
	237	static int acp5x_dma_hw_params(struct snd_soc_component *component,
	238	struct snd_pcm_substream *substream,
	239	struct snd_pcm_hw_params *params)
	240	{
	241	struct i2s_stream_instance *rtd;
	242	struct snd_soc_pcm_runtime *prtd;
	243	struct snd_soc_card *card;
	244	struct acp5x_platform_info *pinfo;
	245	struct i2s_dev_data *adata;
	246	u64 size;
	247
	248	prtd = asoc_substream_to_rtd(substream);
	249	card = prtd->card;
	250	pinfo = snd_soc_card_get_drvdata(card);
	251	adata = dev_get_drvdata(component->dev);
	252	rtd = substream->runtime->private_data;
	253
	254	if (!rtd)
	255	return -EINVAL;
	256
	257	if (pinfo) {
	258	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	259	rtd->i2s_instance = pinfo->play_i2s_instance;
	260	switch (rtd->i2s_instance) {
	261	case I2S_HS_INSTANCE:
	262	adata->play_stream = substream;
	263	break;
	264	case I2S_SP_INSTANCE:
	265	default:
	266	adata->i2ssp_play_stream = substream;
	267	}
	268	} else {
	269	rtd->i2s_instance = pinfo->cap_i2s_instance;
	270	switch (rtd->i2s_instance) {
	271	case I2S_HS_INSTANCE:
	272	adata->capture_stream = substream;
	273	break;
	274	case I2S_SP_INSTANCE:
	275	default:
	276	adata->i2ssp_capture_stream = substream;
	277	}
	278	}
	279	} else {
	280	dev_err(component->dev, "pinfo failed\n");
	281	return -EINVAL;
	282	}
	283	size = params_buffer_bytes(params);
	284	rtd->dma_addr = substream->dma_buffer.addr;
	285	rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);
	286	config_acp5x_dma(rtd, substream->stream);
	287	return 0;
	288	}
	289
	290	static snd_pcm_uframes_t acp5x_dma_pointer(struct snd_soc_component *component,
	291	struct snd_pcm_substream *substream)
	292	{
	293	struct i2s_stream_instance *rtd;
	294	u32 pos;
	295	u32 buffersize;
	296	u64 bytescount;
	297
	298	rtd = substream->runtime->private_data;
	299	buffersize = frames_to_bytes(substream->runtime,
	300	substream->runtime->buffer_size);
	301	bytescount = acp_get_byte_count(rtd, substream->stream);
	302	if (bytescount > rtd->bytescount)
	303	bytescount -= rtd->bytescount;
	304	pos = do_div(bytescount, buffersize);
	305	return bytes_to_frames(substream->runtime, pos);
	306	}
	307
	308	static int acp5x_dma_new(struct snd_soc_component *component,
	309	struct snd_soc_pcm_runtime *rtd)
	310	{
	311	struct device *parent = component->dev->parent;
	312
	313	snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
	314	parent, MIN_BUFFER, MAX_BUFFER);
	315	return 0;
	316	}
	317
	318	static int acp5x_dma_close(struct snd_soc_component *component,
	319	struct snd_pcm_substream *substream)
	320	{
	321	struct snd_soc_pcm_runtime *prtd;
	322	struct i2s_dev_data *adata;
	323	struct i2s_stream_instance *ins;
	324
	325	prtd = asoc_substream_to_rtd(substream);
	326	component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);
	327	adata = dev_get_drvdata(component->dev);
	328	ins = substream->runtime->private_data;
	329	if (!ins)
	330	return -EINVAL;
	331	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	332	switch (ins->i2s_instance) {
	333	case I2S_HS_INSTANCE:
	334	adata->play_stream = NULL;
	335	break;
	336	case I2S_SP_INSTANCE:
	337	default:
	338	adata->i2ssp_play_stream = NULL;
	339	}
	340	} else {
	341	switch (ins->i2s_instance) {
	342	case I2S_HS_INSTANCE:
	343	adata->capture_stream = NULL;
	344	break;
	345	case I2S_SP_INSTANCE:
	346	default:
	347	adata->i2ssp_capture_stream = NULL;
	348	}
	349	}
	350	kfree(ins);
	351	return 0;
	352	}
	353
	354	static const struct snd_soc_component_driver acp5x_i2s_component = {
	355	.name = DRV_NAME,
	356	.open = acp5x_dma_open,
	357	.close = acp5x_dma_close,
	358	.hw_params = acp5x_dma_hw_params,
	359	.pointer = acp5x_dma_pointer,
	360	.pcm_construct = acp5x_dma_new,
	361	};
	362
	363	static int acp5x_audio_probe(struct platform_device *pdev)
	364	{
	365	struct resource *res;
	366	struct i2s_dev_data *adata;
	367	unsigned int irqflags;
	368	int status;
	369
	370	if (!pdev->dev.platform_data) {
	371	dev_err(&pdev->dev, "platform_data not retrieved\n");
	372	return -ENODEV;
	373	}
	374	irqflags = ((unsigned int )(pdev->dev.platform_data));
	375
	376	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	377	if (!res) {
	378	dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
	379	return -ENODEV;
	380	}
	381
	382	adata = devm_kzalloc(&pdev->dev, sizeof(*adata), GFP_KERNEL);
	383	if (!adata)
	384	return -ENOMEM;
	385
	386	adata->acp5x_base = devm_ioremap(&pdev->dev, res->start,
	387	resource_size(res));
	388	if (!adata->acp5x_base)
	389	return -ENOMEM;
	390
	391	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	392	if (!res) {
	393	dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n");
	394	return -ENODEV;
	395	}
	396
	397	adata->i2s_irq = res->start;
	398	dev_set_drvdata(&pdev->dev, adata);
	399	status = devm_snd_soc_register_component(&pdev->dev,
	400	&acp5x_i2s_component,
	401	NULL, 0);
	402	if (status) {
	403	dev_err(&pdev->dev, "Fail to register acp i2s component\n");
	404	return status;
	405	}
	406	status = devm_request_irq(&pdev->dev, adata->i2s_irq, i2s_irq_handler,
	407	irqflags, "ACP5x_I2S_IRQ", adata);
	408	if (status) {
	409	dev_err(&pdev->dev, "ACP5x I2S IRQ request failed\n");
	410	return status;
	411	}
	412	pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
	413	pm_runtime_use_autosuspend(&pdev->dev);
	414	pm_runtime_enable(&pdev->dev);
	415	pm_runtime_allow(&pdev->dev);
	416
	417	return 0;
	418	}
	419
	420	static int acp5x_audio_remove(struct platform_device *pdev)
	421	{
	422	pm_runtime_disable(&pdev->dev);
	423	return 0;
	424	}
	425
	426	static int __maybe_unused acp5x_pcm_resume(struct device *dev)
	427	{
	428	struct i2s_dev_data *adata;
	429	u32 val, reg_val, frmt_val;
	430
	431	reg_val = 0;
	432	frmt_val = 0;
	433	adata = dev_get_drvdata(dev);
	434
	435	if (adata->play_stream && adata->play_stream->runtime) {
	436	struct i2s_stream_instance *rtd =
	437	adata->play_stream->runtime->private_data;
	438	config_acp5x_dma(rtd, SNDRV_PCM_STREAM_PLAYBACK);
	439	switch (rtd->i2s_instance) {
	440	case I2S_HS_INSTANCE:
	441	reg_val = ACP_HSTDM_ITER;
	442	frmt_val = ACP_HSTDM_TXFRMT;
	443	break;
	444	case I2S_SP_INSTANCE:
	445	default:
	446	reg_val = ACP_I2STDM_ITER;
	447	frmt_val = ACP_I2STDM_TXFRMT;
	448	}
	449	acp_writel((rtd->xfer_resolution << 3),
	450	rtd->acp5x_base + reg_val);
	451	}
	452
	453	if (adata->capture_stream && adata->capture_stream->runtime) {
	454	struct i2s_stream_instance *rtd =
	455	adata->capture_stream->runtime->private_data;
	456	config_acp5x_dma(rtd, SNDRV_PCM_STREAM_CAPTURE);
	457	switch (rtd->i2s_instance) {
	458	case I2S_HS_INSTANCE:
	459	reg_val = ACP_HSTDM_IRER;
	460	frmt_val = ACP_HSTDM_RXFRMT;
	461	break;
	462	case I2S_SP_INSTANCE:
	463	default:
	464	reg_val = ACP_I2STDM_IRER;
	465	frmt_val = ACP_I2STDM_RXFRMT;
	466	}
	467	acp_writel((rtd->xfer_resolution << 3),
	468	rtd->acp5x_base + reg_val);
	469	}
	470	if (adata->tdm_mode == TDM_ENABLE) {
	471	acp_writel(adata->tdm_fmt, adata->acp5x_base + frmt_val);
	472	val = acp_readl(adata->acp5x_base + reg_val);
	473	acp_writel(val \| 0x2, adata->acp5x_base + reg_val);
	474	}
	475	acp_writel(1, adata->acp5x_base + ACP_EXTERNAL_INTR_ENB);
	476	return 0;
	477	}
	478
	479	static int __maybe_unused acp5x_pcm_suspend(struct device *dev)
	480	{
	481	struct i2s_dev_data *adata;
	482
	483	adata = dev_get_drvdata(dev);
	484	acp_writel(0, adata->acp5x_base + ACP_EXTERNAL_INTR_ENB);
	485	return 0;
	486	}
	487
	488	static int __maybe_unused acp5x_pcm_runtime_resume(struct device *dev)
	489	{
	490	struct i2s_dev_data *adata;
	491
	492	adata = dev_get_drvdata(dev);
	493	acp_writel(1, adata->acp5x_base + ACP_EXTERNAL_INTR_ENB);
	494	return 0;
	495	}
	496
	497	static const struct dev_pm_ops acp5x_pm_ops = {
	498	SET_RUNTIME_PM_OPS(acp5x_pcm_suspend,
	499	acp5x_pcm_runtime_resume, NULL)
	500	SET_SYSTEM_SLEEP_PM_OPS(acp5x_pcm_suspend, acp5x_pcm_resume)
	501	};
	502
	503	static struct platform_driver acp5x_dma_driver = {
	504	.probe = acp5x_audio_probe,
	505	.remove = acp5x_audio_remove,
	506	.driver = {
	507	.name = "acp5x_i2s_dma",
	508	.pm = &acp5x_pm_ops,
	509	},
	510	};
	511
	512	module_platform_driver(acp5x_dma_driver);
	513
	514	MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
	515	MODULE_DESCRIPTION("AMD ACP 5.x PCM Driver");
	516	MODULE_LICENSE("GPL v2");
	517	MODULE_ALIAS("platform:" DRV_NAME);

sound/soc/amd/vangogh/acp5x.h+193−0

@@ -0,0 +1,193 @@
	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/*
	3	* AMD ALSA SoC PCM Driver
	4	*
	5	* Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
	6	*/
	7
	8	#include "vg_chip_offset_byte.h"
	9	#include <sound/pcm.h>
	10
	11	#define ACP5x_PHY_BASE_ADDRESS 0x1240000
	12	#define ACP_DEVICE_ID 0x15E2
	13	#define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
	14
	15	#define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
	16	#define ACP_PGFSM_CNTL_POWER_OFF_MASK 0x00
	17	#define ACP_PGFSM_STATUS_MASK 0x03
	18	#define ACP_POWERED_ON 0x00
	19	#define ACP_POWER_ON_IN_PROGRESS 0x01
	20	#define ACP_POWERED_OFF 0x02
	21	#define ACP_POWER_OFF_IN_PROGRESS 0x03
	22
	23	#define ACP_ERR_INTR_MASK 0x20000000
	24	#define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
	25
	26	#define ACP5x_DEVS 3
	27	#define ACP5x_REG_START 0x1240000
	28	#define ACP5x_REG_END 0x1250200
	29	#define ACP5x_I2STDM_REG_START 0x1242400
	30	#define ACP5x_I2STDM_REG_END 0x1242410
	31	#define ACP5x_HS_TDM_REG_START 0x1242814
	32	#define ACP5x_HS_TDM_REG_END 0x1242824
	33	#define I2S_MODE 0
	34	#define ACP5x_I2S_MODE 1
	35	#define ACP5x_RES 4
	36	#define I2S_RX_THRESHOLD 27
	37	#define I2S_TX_THRESHOLD 28
	38	#define HS_TX_THRESHOLD 24
	39	#define HS_RX_THRESHOLD 23
	40
	41	#define I2S_SP_INSTANCE 1
	42	#define I2S_HS_INSTANCE 2
	43
	44	#define ACP_SRAM_PTE_OFFSET 0x02050000
	45	#define ACP_SRAM_SP_PB_PTE_OFFSET 0x0
	46	#define ACP_SRAM_SP_CP_PTE_OFFSET 0x100
	47	#define ACP_SRAM_HS_PB_PTE_OFFSET 0x200
	48	#define ACP_SRAM_HS_CP_PTE_OFFSET 0x300
	49	#define PAGE_SIZE_4K_ENABLE 0x2
	50	#define I2S_SP_TX_MEM_WINDOW_START 0x4000000
	51	#define I2S_SP_RX_MEM_WINDOW_START 0x4020000
	52	#define I2S_HS_TX_MEM_WINDOW_START 0x4040000
	53	#define I2S_HS_RX_MEM_WINDOW_START 0x4060000
	54
	55	#define SP_PB_FIFO_ADDR_OFFSET 0x500
	56	#define SP_CAPT_FIFO_ADDR_OFFSET 0x700
	57	#define HS_PB_FIFO_ADDR_OFFSET 0x900
	58	#define HS_CAPT_FIFO_ADDR_OFFSET 0xB00
	59	#define PLAYBACK_MIN_NUM_PERIODS 2
	60	#define PLAYBACK_MAX_NUM_PERIODS 8
	61	#define PLAYBACK_MAX_PERIOD_SIZE 8192
	62	#define PLAYBACK_MIN_PERIOD_SIZE 1024
	63	#define CAPTURE_MIN_NUM_PERIODS 2
	64	#define CAPTURE_MAX_NUM_PERIODS 8
	65	#define CAPTURE_MAX_PERIOD_SIZE 8192
	66	#define CAPTURE_MIN_PERIOD_SIZE 1024
	67
	68	#define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
	69	#define MIN_BUFFER MAX_BUFFER
	70	#define FIFO_SIZE 0x100
	71	#define DMA_SIZE 0x40
	72	#define FRM_LEN 0x100
	73
	74	#define I2S_MASTER_MODE_ENABLE 1
	75	#define I2S_MASTER_MODE_DISABLE 0
	76
	77	#define SLOT_WIDTH_8 8
	78	#define SLOT_WIDTH_16 16
	79	#define SLOT_WIDTH_24 24
	80	#define SLOT_WIDTH_32 32
	81	#define TDM_ENABLE 1
	82	#define TDM_DISABLE 0
	83	#define ACP5x_ITER_IRER_SAMP_LEN_MASK 0x38
	84
	85	struct i2s_dev_data {
	86	bool tdm_mode;
	87	bool master_mode;
	88	unsigned int i2s_irq;
	89	u16 i2s_instance;
	90	u32 tdm_fmt;
	91	void __iomem *acp5x_base;
	92	struct snd_pcm_substream *play_stream;
	93	struct snd_pcm_substream *capture_stream;
	94	struct snd_pcm_substream *i2ssp_play_stream;
	95	struct snd_pcm_substream *i2ssp_capture_stream;
	96	};
	97
	98	struct i2s_stream_instance {
	99	u16 num_pages;
	100	u16 i2s_instance;
	101	u16 direction;
	102	u16 channels;
	103	u32 xfer_resolution;
	104	u32 val;
	105	dma_addr_t dma_addr;
	106	u64 bytescount;
	107	void __iomem *acp5x_base;
	108	};
	109
	110	union acp_dma_count {
	111	struct {
	112	u32 low;
	113	u32 high;
	114	} bcount;
	115	u64 bytescount;
	116	};
	117
	118	struct acp5x_platform_info {
	119	u16 play_i2s_instance;
	120	u16 cap_i2s_instance;
	121	};
	122
	123	union acp_i2stdm_mstrclkgen {
	124	struct {
	125	u32 i2stdm_master_mode : 1;
	126	u32 i2stdm_format_mode : 1;
	127	u32 i2stdm_lrclk_div_val : 9;
	128	u32 i2stdm_bclk_div_val : 11;
	129	u32:10;
	130	} bitfields, bits;
	131	u32 u32_all;
	132	};
	133
	134	/* common header file uses exact offset rather than relative
	135	* offset which requires subtraction logic from base_addr
	136	* for accessing ACP5x MMIO space registers
	137	*/
	138	static inline u32 acp_readl(void __iomem *base_addr)
	139	{
	140	return readl(base_addr - ACP5x_PHY_BASE_ADDRESS);
	141	}
	142
	143	static inline void acp_writel(u32 val, void __iomem *base_addr)
	144	{
	145	writel(val, base_addr - ACP5x_PHY_BASE_ADDRESS);
	146	}
	147
	148	static inline u64 acp_get_byte_count(struct i2s_stream_instance *rtd,
	149	int direction)
	150	{
	151	union acp_dma_count byte_count;
	152
	153	if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
	154	switch (rtd->i2s_instance) {
	155	case I2S_HS_INSTANCE:
	156	byte_count.bcount.high =
	157	acp_readl(rtd->acp5x_base +
	158	ACP_HS_TX_LINEARPOSCNTR_HIGH);
	159	byte_count.bcount.low =
	160	acp_readl(rtd->acp5x_base +
	161	ACP_HS_TX_LINEARPOSCNTR_LOW);
	162	break;
	163	case I2S_SP_INSTANCE:
	164	default:
	165	byte_count.bcount.high =
	166	acp_readl(rtd->acp5x_base +
	167	ACP_I2S_TX_LINEARPOSCNTR_HIGH);
	168	byte_count.bcount.low =
	169	acp_readl(rtd->acp5x_base +
	170	ACP_I2S_TX_LINEARPOSCNTR_LOW);
	171	}
	172	} else {
	173	switch (rtd->i2s_instance) {
	174	case I2S_HS_INSTANCE:
	175	byte_count.bcount.high =
	176	acp_readl(rtd->acp5x_base +
	177	ACP_HS_RX_LINEARPOSCNTR_HIGH);
	178	byte_count.bcount.low =
	179	acp_readl(rtd->acp5x_base +
	180	ACP_HS_RX_LINEARPOSCNTR_LOW);
	181	break;
	182	case I2S_SP_INSTANCE:
	183	default:
	184	byte_count.bcount.high =
	185	acp_readl(rtd->acp5x_base +
	186	ACP_I2S_RX_LINEARPOSCNTR_HIGH);
	187	byte_count.bcount.low =
	188	acp_readl(rtd->acp5x_base +
	189	ACP_I2S_RX_LINEARPOSCNTR_LOW);
	190	}
	191	}
	192	return byte_count.bytescount;
	193	}

sound/soc/amd/vangogh/pci-acp5x.c+326−0

@@ -0,0 +1,326 @@
	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// AMD Vangogh ACP PCI Driver
	4	//
	5	// Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
	6
	7	#include <linux/pci.h>
	8	#include <linux/module.h>
	9	#include <linux/io.h>
	10	#include <linux/delay.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/pm_runtime.h>
	14
	15	#include "acp5x.h"
	16
	17	struct acp5x_dev_data {
	18	void __iomem *acp5x_base;
	19	bool acp5x_audio_mode;
	20	struct resource *res;
	21	struct platform_device *pdev[ACP5x_DEVS];
	22	};
	23
	24	static int acp5x_power_on(void __iomem *acp5x_base)
	25	{
	26	u32 val;
	27	int timeout;
	28
	29	val = acp_readl(acp5x_base + ACP_PGFSM_STATUS);
	30
	31	if (val == 0)
	32	return val;
	33
	34	if ((val & ACP_PGFSM_STATUS_MASK) !=
	35	ACP_POWER_ON_IN_PROGRESS)
	36	acp_writel(ACP_PGFSM_CNTL_POWER_ON_MASK,
	37	acp5x_base + ACP_PGFSM_CONTROL);
	38	timeout = 0;
	39	while (++timeout < 500) {
	40	val = acp_readl(acp5x_base + ACP_PGFSM_STATUS);
	41	if ((val & ACP_PGFSM_STATUS_MASK) == ACP_POWERED_ON)
	42	return 0;
	43	udelay(1);
	44	}
	45	return -ETIMEDOUT;
	46	}
	47
	48	static int acp5x_reset(void __iomem *acp5x_base)
	49	{
	50	u32 val;
	51	int timeout;
	52
	53	acp_writel(1, acp5x_base + ACP_SOFT_RESET);
	54	timeout = 0;
	55	while (++timeout < 500) {
	56	val = acp_readl(acp5x_base + ACP_SOFT_RESET);
	57	if (val & ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK)
	58	break;
	59	cpu_relax();
	60	}
	61	acp_writel(0, acp5x_base + ACP_SOFT_RESET);
	62	timeout = 0;
	63	while (++timeout < 500) {
	64	val = acp_readl(acp5x_base + ACP_SOFT_RESET);
	65	if (!val)
	66	return 0;
	67	cpu_relax();
	68	}
	69	return -ETIMEDOUT;
	70	}
	71
	72	static void acp5x_enable_interrupts(void __iomem *acp5x_base)
	73	{
	74	acp_writel(0x01, acp5x_base + ACP_EXTERNAL_INTR_ENB);
	75	}
	76
	77	static void acp5x_disable_interrupts(void __iomem *acp5x_base)
	78	{
	79	acp_writel(ACP_EXT_INTR_STAT_CLEAR_MASK, acp5x_base +
	80	ACP_EXTERNAL_INTR_STAT);
	81	acp_writel(0x00, acp5x_base + ACP_EXTERNAL_INTR_CNTL);
	82	acp_writel(0x00, acp5x_base + ACP_EXTERNAL_INTR_ENB);
	83	}
	84
	85	static int acp5x_init(void __iomem *acp5x_base)
	86	{
	87	int ret;
	88
	89	/* power on */
	90	ret = acp5x_power_on(acp5x_base);
	91	if (ret) {
	92	pr_err("ACP5x power on failed\n");
	93	return ret;
	94	}
	95	/* Reset */
	96	ret = acp5x_reset(acp5x_base);
	97	if (ret) {
	98	pr_err("ACP5x reset failed\n");
	99	return ret;
	100	}
	101	acp5x_enable_interrupts(acp5x_base);
	102	return 0;
	103	}
	104
	105	static int acp5x_deinit(void __iomem *acp5x_base)
	106	{
	107	int ret;
	108
	109	acp5x_disable_interrupts(acp5x_base);
	110	/* Reset */
	111	ret = acp5x_reset(acp5x_base);
	112	if (ret) {
	113	pr_err("ACP5x reset failed\n");
	114	return ret;
	115	}
	116	return 0;
	117	}
	118
	119	static int snd_acp5x_probe(struct pci_dev *pci,
	120	const struct pci_device_id *pci_id)
	121	{
	122	struct acp5x_dev_data *adata;
	123	struct platform_device_info pdevinfo[ACP5x_DEVS];
	124	unsigned int irqflags;
	125	int ret, i;
	126	u32 addr, val;
	127
	128	irqflags = IRQF_SHARED;
	129	if (pci->revision != 0x50)
	130	return -ENODEV;
	131
	132	if (pci_enable_device(pci)) {
	133	dev_err(&pci->dev, "pci_enable_device failed\n");
	134	return -ENODEV;
	135	}
	136
	137	ret = pci_request_regions(pci, "AMD ACP5x audio");
	138	if (ret < 0) {
	139	dev_err(&pci->dev, "pci_request_regions failed\n");
	140	goto disable_pci;
	141	}
	142
	143	adata = devm_kzalloc(&pci->dev, sizeof(struct acp5x_dev_data),
	144	GFP_KERNEL);
	145	if (!adata) {
	146	ret = -ENOMEM;
	147	goto release_regions;
	148	}
	149	addr = pci_resource_start(pci, 0);
	150	adata->acp5x_base = devm_ioremap(&pci->dev, addr,
	151	pci_resource_len(pci, 0));
	152	if (!adata->acp5x_base) {
	153	ret = -ENOMEM;
	154	goto release_regions;
	155	}
	156	pci_set_master(pci);
	157	pci_set_drvdata(pci, adata);
	158	ret = acp5x_init(adata->acp5x_base);
	159	if (ret)
	160	goto release_regions;
	161
	162	val = acp_readl(adata->acp5x_base + ACP_PIN_CONFIG);
	163	switch (val) {
	164	case I2S_MODE:
	165	adata->res = devm_kzalloc(&pci->dev,
	166	sizeof(struct resource) * ACP5x_RES,
	167	GFP_KERNEL);
	168	if (!adata->res) {
	169	ret = -ENOMEM;
	170	goto de_init;
	171	}
	172
	173	adata->res[0].name = "acp5x_i2s_iomem";
	174	adata->res[0].flags = IORESOURCE_MEM;
	175	adata->res[0].start = addr;
	176	adata->res[0].end = addr + (ACP5x_REG_END - ACP5x_REG_START);
	177
	178	adata->res[1].name = "acp5x_i2s_sp";
	179	adata->res[1].flags = IORESOURCE_MEM;
	180	adata->res[1].start = addr + ACP5x_I2STDM_REG_START;
	181	adata->res[1].end = addr + ACP5x_I2STDM_REG_END;
	182
	183	adata->res[2].name = "acp5x_i2s_hs";
	184	adata->res[2].flags = IORESOURCE_MEM;
	185	adata->res[2].start = addr + ACP5x_HS_TDM_REG_START;
	186	adata->res[2].end = addr + ACP5x_HS_TDM_REG_END;
	187
	188	adata->res[3].name = "acp5x_i2s_irq";
	189	adata->res[3].flags = IORESOURCE_IRQ;
	190	adata->res[3].start = pci->irq;
	191	adata->res[3].end = adata->res[3].start;
	192
	193	adata->acp5x_audio_mode = ACP5x_I2S_MODE;
	194
	195	memset(&pdevinfo, 0, sizeof(pdevinfo));
	196	pdevinfo[0].name = "acp5x_i2s_dma";
	197	pdevinfo[0].id = 0;
	198	pdevinfo[0].parent = &pci->dev;
	199	pdevinfo[0].num_res = 4;
	200	pdevinfo[0].res = &adata->res[0];
	201	pdevinfo[0].data = &irqflags;
	202	pdevinfo[0].size_data = sizeof(irqflags);
	203
	204	pdevinfo[1].name = "acp5x_i2s_playcap";
	205	pdevinfo[1].id = 0;
	206	pdevinfo[1].parent = &pci->dev;
	207	pdevinfo[1].num_res = 1;
	208	pdevinfo[1].res = &adata->res[1];
	209
	210	pdevinfo[2].name = "acp5x_i2s_playcap";
	211	pdevinfo[2].id = 1;
	212	pdevinfo[2].parent = &pci->dev;
	213	pdevinfo[2].num_res = 1;
	214	pdevinfo[2].res = &adata->res[2];
	215
	216	for (i = 0; i < ACP5x_DEVS; i++) {
	217	adata->pdev[i] =
	218	platform_device_register_full(&pdevinfo[i]);
	219	if (IS_ERR(adata->pdev[i])) {
	220	dev_err(&pci->dev, "cannot register %s device\n",
	221	pdevinfo[i].name);
	222	ret = PTR_ERR(adata->pdev[i]);
	223	goto unregister_devs;
	224	}
	225	}
	226	break;
	227	default:
	228	dev_info(&pci->dev, "ACP audio mode : %d\n", val);
	229	}
	230	pm_runtime_set_autosuspend_delay(&pci->dev, 2000);
	231	pm_runtime_use_autosuspend(&pci->dev);
	232	pm_runtime_put_noidle(&pci->dev);
	233	pm_runtime_allow(&pci->dev);
	234	return 0;
	235
	236	unregister_devs:
	237	for (--i; i >= 0; i--)
	238	platform_device_unregister(adata->pdev[i]);
	239	de_init:
	240	if (acp5x_deinit(adata->acp5x_base))
	241	dev_err(&pci->dev, "ACP de-init failed\n");
	242	release_regions:
	243	pci_release_regions(pci);
	244	disable_pci:
	245	pci_disable_device(pci);
	246
	247	return ret;
	248	}
	249
	250	static int __maybe_unused snd_acp5x_suspend(struct device *dev)
	251	{
	252	int ret;
	253	struct acp5x_dev_data *adata;
	254
	255	adata = dev_get_drvdata(dev);
	256	ret = acp5x_deinit(adata->acp5x_base);
	257	if (ret)
	258	dev_err(dev, "ACP de-init failed\n");
	259	else
	260	dev_dbg(dev, "ACP de-initialized\n");
	261
	262	return ret;
	263	}
	264
	265	static int __maybe_unused snd_acp5x_resume(struct device *dev)
	266	{
	267	int ret;
	268	struct acp5x_dev_data *adata;
	269
	270	adata = dev_get_drvdata(dev);
	271	ret = acp5x_init(adata->acp5x_base);
	272	if (ret) {
	273	dev_err(dev, "ACP init failed\n");
	274	return ret;
	275	}
	276	return 0;
	277	}
	278
	279	static const struct dev_pm_ops acp5x_pm = {
	280	SET_RUNTIME_PM_OPS(snd_acp5x_suspend,
	281	snd_acp5x_resume, NULL)
	282	SET_SYSTEM_SLEEP_PM_OPS(snd_acp5x_suspend, snd_acp5x_resume)
	283	};
	284
	285	static void snd_acp5x_remove(struct pci_dev *pci)
	286	{
	287	struct acp5x_dev_data *adata;
	288	int i, ret;
	289
	290	adata = pci_get_drvdata(pci);
	291	if (adata->acp5x_audio_mode == ACP5x_I2S_MODE) {
	292	for (i = 0; i < ACP5x_DEVS; i++)
	293	platform_device_unregister(adata->pdev[i]);
	294	}
	295	ret = acp5x_deinit(adata->acp5x_base);
	296	if (ret)
	297	dev_err(&pci->dev, "ACP de-init failed\n");
	298	pm_runtime_forbid(&pci->dev);
	299	pm_runtime_get_noresume(&pci->dev);
	300	pci_release_regions(pci);
	301	pci_disable_device(pci);
	302	}
	303
	304	static const struct pci_device_id snd_acp5x_ids[] = {
	305	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, ACP_DEVICE_ID),
	306	.class = PCI_CLASS_MULTIMEDIA_OTHER << 8,
	307	.class_mask = 0xffffff },
	308	{ 0, },
	309	};
	310	MODULE_DEVICE_TABLE(pci, snd_acp5x_ids);
	311
	312	static struct pci_driver acp5x_driver = {
	313	.name = KBUILD_MODNAME,
	314	.id_table = snd_acp5x_ids,
	315	.probe = snd_acp5x_probe,
	316	.remove = snd_acp5x_remove,
	317	.driver = {
	318	.pm = &acp5x_pm,
	319	}
	320	};
	321
	322	module_pci_driver(acp5x_driver);
	323
	324	MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
	325	MODULE_DESCRIPTION("AMD Vangogh ACP PCI driver");
	326	MODULE_LICENSE("GPL v2");

sound/soc/amd/vangogh/vg_chip_offset_byte.h+337−0

@@ -0,0 +1,337 @@
	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/*
	3	* AMD ACP 5.x Register Documentation
	4	*
	5	* Copyright 2021 Advanced Micro Devices, Inc.
	6	*/
	7
	8	#ifndef _acp_ip_OFFSET_HEADER
	9	#define _acp_ip_OFFSET_HEADER
	10
	11	/* Registers from ACP_DMA block */
	12	#define ACP_DMA_CNTL_0 0x1240000
	13	#define ACP_DMA_CNTL_1 0x1240004
	14	#define ACP_DMA_CNTL_2 0x1240008
	15	#define ACP_DMA_CNTL_3 0x124000C
	16	#define ACP_DMA_CNTL_4 0x1240010
	17	#define ACP_DMA_CNTL_5 0x1240014
	18	#define ACP_DMA_CNTL_6 0x1240018
	19	#define ACP_DMA_CNTL_7 0x124001C
	20	#define ACP_DMA_DSCR_STRT_IDX_0 0x1240020
	21	#define ACP_DMA_DSCR_STRT_IDX_1 0x1240024
	22	#define ACP_DMA_DSCR_STRT_IDX_2 0x1240028
	23	#define ACP_DMA_DSCR_STRT_IDX_3 0x124002C
	24	#define ACP_DMA_DSCR_STRT_IDX_4 0x1240030
	25	#define ACP_DMA_DSCR_STRT_IDX_5 0x1240034
	26	#define ACP_DMA_DSCR_STRT_IDX_6 0x1240038
	27	#define ACP_DMA_DSCR_STRT_IDX_7 0x124003C
	28	#define ACP_DMA_DSCR_CNT_0 0x1240040
	29	#define ACP_DMA_DSCR_CNT_1 0x1240044
	30	#define ACP_DMA_DSCR_CNT_2 0x1240048
	31	#define ACP_DMA_DSCR_CNT_3 0x124004C
	32	#define ACP_DMA_DSCR_CNT_4 0x1240050
	33	#define ACP_DMA_DSCR_CNT_5 0x1240054
	34	#define ACP_DMA_DSCR_CNT_6 0x1240058
	35	#define ACP_DMA_DSCR_CNT_7 0x124005C
	36	#define ACP_DMA_PRIO_0 0x1240060
	37	#define ACP_DMA_PRIO_1 0x1240064
	38	#define ACP_DMA_PRIO_2 0x1240068
	39	#define ACP_DMA_PRIO_3 0x124006C
	40	#define ACP_DMA_PRIO_4 0x1240070
	41	#define ACP_DMA_PRIO_5 0x1240074
	42	#define ACP_DMA_PRIO_6 0x1240078
	43	#define ACP_DMA_PRIO_7 0x124007C
	44	#define ACP_DMA_CUR_DSCR_0 0x1240080
	45	#define ACP_DMA_CUR_DSCR_1 0x1240084
	46	#define ACP_DMA_CUR_DSCR_2 0x1240088
	47	#define ACP_DMA_CUR_DSCR_3 0x124008C
	48	#define ACP_DMA_CUR_DSCR_4 0x1240090
	49	#define ACP_DMA_CUR_DSCR_5 0x1240094
	50	#define ACP_DMA_CUR_DSCR_6 0x1240098
	51	#define ACP_DMA_CUR_DSCR_7 0x124009C
	52	#define ACP_DMA_CUR_TRANS_CNT_0 0x12400A0
	53	#define ACP_DMA_CUR_TRANS_CNT_1 0x12400A4
	54	#define ACP_DMA_CUR_TRANS_CNT_2 0x12400A8
	55	#define ACP_DMA_CUR_TRANS_CNT_3 0x12400AC
	56	#define ACP_DMA_CUR_TRANS_CNT_4 0x12400B0
	57	#define ACP_DMA_CUR_TRANS_CNT_5 0x12400B4
	58	#define ACP_DMA_CUR_TRANS_CNT_6 0x12400B8
	59	#define ACP_DMA_CUR_TRANS_CNT_7 0x12400BC
	60	#define ACP_DMA_ERR_STS_0 0x12400C0
	61	#define ACP_DMA_ERR_STS_1 0x12400C4
	62	#define ACP_DMA_ERR_STS_2 0x12400C8
	63	#define ACP_DMA_ERR_STS_3 0x12400CC
	64	#define ACP_DMA_ERR_STS_4 0x12400D0
	65	#define ACP_DMA_ERR_STS_5 0x12400D4
	66	#define ACP_DMA_ERR_STS_6 0x12400D8
	67	#define ACP_DMA_ERR_STS_7 0x12400DC
	68	#define ACP_DMA_DESC_BASE_ADDR 0x12400E0
	69	#define ACP_DMA_DESC_MAX_NUM_DSCR 0x12400E4
	70	#define ACP_DMA_CH_STS 0x12400E8
	71	#define ACP_DMA_CH_GROUP 0x12400EC
	72	#define ACP_DMA_CH_RST_STS 0x12400F0
	73
	74	/* Registers from ACP_AXI2AXIATU block */
	75	#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x1240C00
	76	#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x1240C04
	77	#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x1240C08
	78	#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x1240C0C
	79	#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x1240C10
	80	#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x1240C14
	81	#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x1240C18
	82	#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x1240C1C
	83	#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x1240C20
	84	#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x1240C24
	85	#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x1240C28
	86	#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x1240C2C
	87	#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x1240C30
	88	#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x1240C34
	89	#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x1240C38
	90	#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x1240C3C
	91	#define ACPAXI2AXI_ATU_CTRL 0x1240C40
	92
	93	/* Registers from ACP_CLKRST block */
	94	#define ACP_SOFT_RESET 0x1241000
	95	#define ACP_CONTROL 0x1241004
	96	#define ACP_STATUS 0x1241008
	97	#define ACP_DYNAMIC_CG_MASTER_CONTROL 0x1241010
	98
	99	/* Registers from ACP_MISC block */
	100	#define ACP_EXTERNAL_INTR_ENB 0x1241800
	101	#define ACP_EXTERNAL_INTR_CNTL 0x1241804
	102	#define ACP_EXTERNAL_INTR_STAT 0x1241808
	103	#define ACP_ERROR_STATUS 0x12418C4
	104	#define ACP_SW_I2S_ERROR_REASON 0x12418C8
	105	#define ACP_MEM_PG_STS 0x12418CC
	106	#define ACP_PGMEM_DEEP_SLEEP_CTRL 0x12418D0
	107	#define ACP_PGMEM_SHUT_DOWN_CTRL 0x12418D4
	108
	109	/* Registers from ACP_PGFSM block */
	110	#define ACP_PIN_CONFIG 0x1241400
	111	#define ACP_PAD_PULLUP_CTRL 0x1241404
	112	#define ACP_PAD_PULLDOWN_CTRL 0x1241408
	113	#define ACP_PAD_DRIVE_STRENGTH_CTRL 0x124140C
	114	#define ACP_PAD_SCHMEN_CTRL 0x1241410
	115	#define ACP_SW_PAD_KEEPER_EN 0x1241414
	116	#define ACP_SW_WAKE_EN 0x1241418
	117	#define ACP_I2S_WAKE_EN 0x124141C
	118	#define ACP_PME_EN 0x1241420
	119	#define ACP_PGFSM_CONTROL 0x1241424
	120	#define ACP_PGFSM_STATUS 0x1241428
	121	#define ACP_CLKMUX_SEL 0x124142C
	122	#define ACP_DEVICE_STATE 0x1241430
	123	#define AZ_DEVICE_STATE 0x1241434
	124	#define ACP_INTR_URGENCY_TIMER 0x1241438
	125	#define AZ_INTR_URGENCY_TIMER 0x124143C
	126	#define ACP_AON_SW_INTR_TRIG 0x1241440
	127
	128	/* Registers from ACP_SCRATCH block */
	129	#define ACP_SCRATCH_REG_0 0x1250000
	130	#define ACP_SCRATCH_REG_1 0x1250004
	131	#define ACP_SCRATCH_REG_2 0x1250008
	132	#define ACP_SCRATCH_REG_3 0x125000C
	133	#define ACP_SCRATCH_REG_4 0x1250010
	134	#define ACP_SCRATCH_REG_5 0x1250014
	135	#define ACP_SCRATCH_REG_6 0x1250018
	136	#define ACP_SCRATCH_REG_7 0x125001C
	137	#define ACP_SCRATCH_REG_8 0x1250020
	138	#define ACP_SCRATCH_REG_9 0x1250024
	139	#define ACP_SCRATCH_REG_10 0x1250028
	140	#define ACP_SCRATCH_REG_11 0x125002C
	141	#define ACP_SCRATCH_REG_12 0x1250030
	142	#define ACP_SCRATCH_REG_13 0x1250034
	143	#define ACP_SCRATCH_REG_14 0x1250038
	144	#define ACP_SCRATCH_REG_15 0x125003C
	145	#define ACP_SCRATCH_REG_16 0x1250040
	146	#define ACP_SCRATCH_REG_17 0x1250044
	147	#define ACP_SCRATCH_REG_18 0x1250048
	148	#define ACP_SCRATCH_REG_19 0x125004C
	149	#define ACP_SCRATCH_REG_20 0x1250050
	150	#define ACP_SCRATCH_REG_21 0x1250054
	151	#define ACP_SCRATCH_REG_22 0x1250058
	152	#define ACP_SCRATCH_REG_23 0x125005C
	153	#define ACP_SCRATCH_REG_24 0x1250060
	154	#define ACP_SCRATCH_REG_25 0x1250064
	155	#define ACP_SCRATCH_REG_26 0x1250068
	156	#define ACP_SCRATCH_REG_27 0x125006C
	157	#define ACP_SCRATCH_REG_28 0x1250070
	158	#define ACP_SCRATCH_REG_29 0x1250074
	159	#define ACP_SCRATCH_REG_30 0x1250078
	160	#define ACP_SCRATCH_REG_31 0x125007C
	161	#define ACP_SCRATCH_REG_32 0x1250080
	162	#define ACP_SCRATCH_REG_33 0x1250084
	163	#define ACP_SCRATCH_REG_34 0x1250088
	164	#define ACP_SCRATCH_REG_35 0x125008C
	165	#define ACP_SCRATCH_REG_36 0x1250090
	166	#define ACP_SCRATCH_REG_37 0x1250094
	167	#define ACP_SCRATCH_REG_38 0x1250098
	168	#define ACP_SCRATCH_REG_39 0x125009C
	169	#define ACP_SCRATCH_REG_40 0x12500A0
	170	#define ACP_SCRATCH_REG_41 0x12500A4
	171	#define ACP_SCRATCH_REG_42 0x12500A8
	172	#define ACP_SCRATCH_REG_43 0x12500AC
	173	#define ACP_SCRATCH_REG_44 0x12500B0
	174	#define ACP_SCRATCH_REG_45 0x12500B4
	175	#define ACP_SCRATCH_REG_46 0x12500B8
	176	#define ACP_SCRATCH_REG_47 0x12500BC
	177	#define ACP_SCRATCH_REG_48 0x12500C0
	178	#define ACP_SCRATCH_REG_49 0x12500C4
	179	#define ACP_SCRATCH_REG_50 0x12500C8
	180	#define ACP_SCRATCH_REG_51 0x12500CC
	181	#define ACP_SCRATCH_REG_52 0x12500D0
	182	#define ACP_SCRATCH_REG_53 0x12500D4
	183	#define ACP_SCRATCH_REG_54 0x12500D8
	184	#define ACP_SCRATCH_REG_55 0x12500DC
	185	#define ACP_SCRATCH_REG_56 0x12500E0
	186	#define ACP_SCRATCH_REG_57 0x12500E4
	187	#define ACP_SCRATCH_REG_58 0x12500E8
	188	#define ACP_SCRATCH_REG_59 0x12500EC
	189	#define ACP_SCRATCH_REG_60 0x12500F0
	190	#define ACP_SCRATCH_REG_61 0x12500F4
	191	#define ACP_SCRATCH_REG_62 0x12500F8
	192	#define ACP_SCRATCH_REG_63 0x12500FC
	193	#define ACP_SCRATCH_REG_64 0x1250100
	194	#define ACP_SCRATCH_REG_65 0x1250104
	195	#define ACP_SCRATCH_REG_66 0x1250108
	196	#define ACP_SCRATCH_REG_67 0x125010C
	197	#define ACP_SCRATCH_REG_68 0x1250110
	198	#define ACP_SCRATCH_REG_69 0x1250114
	199	#define ACP_SCRATCH_REG_70 0x1250118
	200	#define ACP_SCRATCH_REG_71 0x125011C
	201	#define ACP_SCRATCH_REG_72 0x1250120
	202	#define ACP_SCRATCH_REG_73 0x1250124
	203	#define ACP_SCRATCH_REG_74 0x1250128
	204	#define ACP_SCRATCH_REG_75 0x125012C
	205	#define ACP_SCRATCH_REG_76 0x1250130
	206	#define ACP_SCRATCH_REG_77 0x1250134
	207	#define ACP_SCRATCH_REG_78 0x1250138
	208	#define ACP_SCRATCH_REG_79 0x125013C
	209	#define ACP_SCRATCH_REG_80 0x1250140
	210	#define ACP_SCRATCH_REG_81 0x1250144
	211	#define ACP_SCRATCH_REG_82 0x1250148
	212	#define ACP_SCRATCH_REG_83 0x125014C
	213	#define ACP_SCRATCH_REG_84 0x1250150
	214	#define ACP_SCRATCH_REG_85 0x1250154
	215	#define ACP_SCRATCH_REG_86 0x1250158
	216	#define ACP_SCRATCH_REG_87 0x125015C
	217	#define ACP_SCRATCH_REG_88 0x1250160
	218	#define ACP_SCRATCH_REG_89 0x1250164
	219	#define ACP_SCRATCH_REG_90 0x1250168
	220	#define ACP_SCRATCH_REG_91 0x125016C
	221	#define ACP_SCRATCH_REG_92 0x1250170
	222	#define ACP_SCRATCH_REG_93 0x1250174
	223	#define ACP_SCRATCH_REG_94 0x1250178
	224	#define ACP_SCRATCH_REG_95 0x125017C
	225	#define ACP_SCRATCH_REG_96 0x1250180
	226	#define ACP_SCRATCH_REG_97 0x1250184
	227	#define ACP_SCRATCH_REG_98 0x1250188
	228	#define ACP_SCRATCH_REG_99 0x125018C
	229	#define ACP_SCRATCH_REG_100 0x1250190
	230	#define ACP_SCRATCH_REG_101 0x1250194
	231	#define ACP_SCRATCH_REG_102 0x1250198
	232	#define ACP_SCRATCH_REG_103 0x125019C
	233	#define ACP_SCRATCH_REG_104 0x12501A0
	234	#define ACP_SCRATCH_REG_105 0x12501A4
	235	#define ACP_SCRATCH_REG_106 0x12501A8
	236	#define ACP_SCRATCH_REG_107 0x12501AC
	237	#define ACP_SCRATCH_REG_108 0x12501B0
	238	#define ACP_SCRATCH_REG_109 0x12501B4
	239	#define ACP_SCRATCH_REG_110 0x12501B8
	240	#define ACP_SCRATCH_REG_111 0x12501BC
	241	#define ACP_SCRATCH_REG_112 0x12501C0
	242	#define ACP_SCRATCH_REG_113 0x12501C4
	243	#define ACP_SCRATCH_REG_114 0x12501C8
	244	#define ACP_SCRATCH_REG_115 0x12501CC
	245	#define ACP_SCRATCH_REG_116 0x12501D0
	246	#define ACP_SCRATCH_REG_117 0x12501D4
	247	#define ACP_SCRATCH_REG_118 0x12501D8
	248	#define ACP_SCRATCH_REG_119 0x12501DC
	249	#define ACP_SCRATCH_REG_120 0x12501E0
	250	#define ACP_SCRATCH_REG_121 0x12501E4
	251	#define ACP_SCRATCH_REG_122 0x12501E8
	252	#define ACP_SCRATCH_REG_123 0x12501EC
	253	#define ACP_SCRATCH_REG_124 0x12501F0
	254	#define ACP_SCRATCH_REG_125 0x12501F4
	255	#define ACP_SCRATCH_REG_126 0x12501F8
	256	#define ACP_SCRATCH_REG_127 0x12501FC
	257	#define ACP_SCRATCH_REG_128 0x1250200
	258
	259	/* Registers from ACP_AUDIO_BUFFERS block */
	260	#define ACP_I2S_RX_RINGBUFADDR 0x1242000
	261	#define ACP_I2S_RX_RINGBUFSIZE 0x1242004
	262	#define ACP_I2S_RX_LINKPOSITIONCNTR 0x1242008
	263	#define ACP_I2S_RX_FIFOADDR 0x124200C
	264	#define ACP_I2S_RX_FIFOSIZE 0x1242010
	265	#define ACP_I2S_RX_DMA_SIZE 0x1242014
	266	#define ACP_I2S_RX_LINEARPOSCNTR_HIGH 0x1242018
	267	#define ACP_I2S_RX_LINEARPOSCNTR_LOW 0x124201C
	268	#define ACP_I2S_RX_INTR_WATERMARK_SIZE 0x1242020
	269	#define ACP_I2S_TX_RINGBUFADDR 0x1242024
	270	#define ACP_I2S_TX_RINGBUFSIZE 0x1242028
	271	#define ACP_I2S_TX_LINKPOSITIONCNTR 0x124202C
	272	#define ACP_I2S_TX_FIFOADDR 0x1242030
	273	#define ACP_I2S_TX_FIFOSIZE 0x1242034
	274	#define ACP_I2S_TX_DMA_SIZE 0x1242038
	275	#define ACP_I2S_TX_LINEARPOSCNTR_HIGH 0x124203C
	276	#define ACP_I2S_TX_LINEARPOSCNTR_LOW 0x1242040
	277	#define ACP_I2S_TX_INTR_WATERMARK_SIZE 0x1242044
	278	#define ACP_BT_RX_RINGBUFADDR 0x1242048
	279	#define ACP_BT_RX_RINGBUFSIZE 0x124204C
	280	#define ACP_BT_RX_LINKPOSITIONCNTR 0x1242050
	281	#define ACP_BT_RX_FIFOADDR 0x1242054
	282	#define ACP_BT_RX_FIFOSIZE 0x1242058
	283	#define ACP_BT_RX_DMA_SIZE 0x124205C
	284	#define ACP_BT_RX_LINEARPOSCNTR_HIGH 0x1242060
	285	#define ACP_BT_RX_LINEARPOSCNTR_LOW 0x1242064
	286	#define ACP_BT_RX_INTR_WATERMARK_SIZE 0x1242068
	287	#define ACP_BT_TX_RINGBUFADDR 0x124206C
	288	#define ACP_BT_TX_RINGBUFSIZE 0x1242070
	289	#define ACP_BT_TX_LINKPOSITIONCNTR 0x1242074
	290	#define ACP_BT_TX_FIFOADDR 0x1242078
	291	#define ACP_BT_TX_FIFOSIZE 0x124207C
	292	#define ACP_BT_TX_DMA_SIZE 0x1242080
	293	#define ACP_BT_TX_LINEARPOSCNTR_HIGH 0x1242084
	294	#define ACP_BT_TX_LINEARPOSCNTR_LOW 0x1242088
	295	#define ACP_BT_TX_INTR_WATERMARK_SIZE 0x124208C
	296	#define ACP_HS_RX_RINGBUFADDR 0x1242090
	297	#define ACP_HS_RX_RINGBUFSIZE 0x1242094
	298	#define ACP_HS_RX_LINKPOSITIONCNTR 0x1242098
	299	#define ACP_HS_RX_FIFOADDR 0x124209C
	300	#define ACP_HS_RX_FIFOSIZE 0x12420A0
	301	#define ACP_HS_RX_DMA_SIZE 0x12420A4
	302	#define ACP_HS_RX_LINEARPOSCNTR_HIGH 0x12420A8
	303	#define ACP_HS_RX_LINEARPOSCNTR_LOW 0x12420AC
	304	#define ACP_HS_RX_INTR_WATERMARK_SIZE 0x12420B0
	305	#define ACP_HS_TX_RINGBUFADDR 0x12420B4
	306	#define ACP_HS_TX_RINGBUFSIZE 0x12420B8
	307	#define ACP_HS_TX_LINKPOSITIONCNTR 0x12420BC
	308	#define ACP_HS_TX_FIFOADDR 0x12420C0
	309	#define ACP_HS_TX_FIFOSIZE 0x12420C4
	310	#define ACP_HS_TX_DMA_SIZE 0x12420C8
	311	#define ACP_HS_TX_LINEARPOSCNTR_HIGH 0x12420CC
	312	#define ACP_HS_TX_LINEARPOSCNTR_LOW 0x12420D0
	313	#define ACP_HS_TX_INTR_WATERMARK_SIZE 0x12420D4
	314
	315	/* Registers from ACP_I2S_TDM block */
	316	#define ACP_I2STDM_IER 0x1242400
	317	#define ACP_I2STDM_IRER 0x1242404
	318	#define ACP_I2STDM_RXFRMT 0x1242408
	319	#define ACP_I2STDM_ITER 0x124240C
	320	#define ACP_I2STDM_TXFRMT 0x1242410
	321	#define ACP_I2STDM0_MSTRCLKGEN 0x1242414
	322	#define ACP_I2STDM1_MSTRCLKGEN 0x1242418
	323	#define ACP_I2STDM2_MSTRCLKGEN 0x124241C
	324	#define ACP_I2STDM_REFCLKGEN 0x1242420
	325
	326	/* Registers from ACP_BT_TDM block */
	327	#define ACP_BTTDM_IER 0x1242800
	328	#define ACP_BTTDM_IRER 0x1242804
	329	#define ACP_BTTDM_RXFRMT 0x1242808
	330	#define ACP_BTTDM_ITER 0x124280C
	331	#define ACP_BTTDM_TXFRMT 0x1242810
	332	#define ACP_HSTDM_IER 0x1242814
	333	#define ACP_HSTDM_IRER 0x1242818
	334	#define ACP_HSTDM_RXFRMT 0x124281C
	335	#define ACP_HSTDM_ITER 0x1242820
	336	#define ACP_HSTDM_TXFRMT 0x1242824
	337	#endif

sound/soc/atmel/Kconfig+0−1

@@ -11,7 +11,6 @@ if SND_ATMEL_SOC · 10 unmodified lines
11		11
12	config SND_ATMEL_SOC_PDC	12	config SND_ATMEL_SOC_PDC
13	bool	13	bool
14	depends on HAS_DMA
15		14
16	config SND_ATMEL_SOC_DMA	15	config SND_ATMEL_SOC_DMA
17	bool	16	bool

sound/soc/atmel/mchp-spdifrx.c+3−3

@@ -56,7 +56,7 @@ · 55 unmodified lines
56	/* Validity Bit Mode */	56	/* Validity Bit Mode */
57	#define SPDIFRX_MR_VBMODE_MASK GENAMSK(1, 1)	57	#define SPDIFRX_MR_VBMODE_MASK GENAMSK(1, 1)
58	#define SPDIFRX_MR_VBMODE_ALWAYS_LOAD \	58	#define SPDIFRX_MR_VBMODE_ALWAYS_LOAD \
59	(0 << 1) /* Load sample regardles of validity bit value */	59	(0 << 1) /* Load sample regardless of validity bit value */
60	#define SPDIFRX_MR_VBMODE_DISCARD_IF_VB1 \	60	#define SPDIFRX_MR_VBMODE_DISCARD_IF_VB1 \
61	(1 << 1) /* Load sample only if validity bit is 0 */	61	(1 << 1) /* Load sample only if validity bit is 0 */
62		62
@@ -519,7 +519,7 @@ static int mchp_spdifrx_cs_get(struct mchp_spdifrx_dev *dev, · 456 unmodified lines
519	/* check for new data available */	519	/* check for new data available */
520	ret = wait_for_completion_interruptible_timeout(&ch_stat->done,	520	ret = wait_for_completion_interruptible_timeout(&ch_stat->done,
521	msecs_to_jiffies(100));	521	msecs_to_jiffies(100));
522	/* IP might not be started or valid stream might not be prezent */	522	/* IP might not be started or valid stream might not be present */
523	if (ret < 0) {	523	if (ret < 0) {
524	dev_dbg(dev->dev, "channel status for channel %d timeout\n",	524	dev_dbg(dev->dev, "channel status for channel %d timeout\n",
525	channel);	525	channel);
@@ -571,7 +571,7 @@ static int mchp_spdifrx_subcode_ch_get(struct mchp_spdifrx_dev *dev, · 45 unmodified lines
571	mchp_spdifrx_isr_blockend_en(dev);	571	mchp_spdifrx_isr_blockend_en(dev);
572	ret = wait_for_completion_interruptible_timeout(&user_data->done,	572	ret = wait_for_completion_interruptible_timeout(&user_data->done,
573	msecs_to_jiffies(100));	573	msecs_to_jiffies(100));
574	/* IP might not be started or valid stream might not be prezent */	574	/* IP might not be started or valid stream might not be present */
575	if (ret <= 0) {	575	if (ret <= 0) {
576	dev_dbg(dev->dev, "user data for channel %d timeout\n",	576	dev_dbg(dev->dev, "user data for channel %d timeout\n",
577	channel);	577	channel);

sound/soc/atmel/mchp-spdiftx.c+1−1

@@ -80,7 +80,7 @@ · 79 unmodified lines
80	#define SPDIFTX_MR_VALID1 BIT(24)	80	#define SPDIFTX_MR_VALID1 BIT(24)
81	#define SPDIFTX_MR_VALID2 BIT(25)	81	#define SPDIFTX_MR_VALID2 BIT(25)
82		82
83	/* Disable Null Frame on underrrun */	83	/* Disable Null Frame on underrun */
84	#define SPDIFTX_MR_DNFR_MASK GENMASK(27, 27)	84	#define SPDIFTX_MR_DNFR_MASK GENMASK(27, 27)
85	#define SPDIFTX_MR_DNFR_INVALID (0 << 27)	85	#define SPDIFTX_MR_DNFR_INVALID (0 << 27)
86	#define SPDIFTX_MR_DNFR_VALID (1 << 27)	86	#define SPDIFTX_MR_DNFR_VALID (1 << 27)

sound/soc/atmel/tse850-pcm5142.c+1−1

@@ -23,7 +23,7 @@ · 22 unmodified lines
23	// IN2 +---o--+------------+--o---+ OUT2	23	// IN2 +---o--+------------+--o---+ OUT2
24	// loop2 relays	24	// loop2 relays
25	//	25	//
26	// The 'loop1' gpio pin controlls two relays, which are either in loop	26	// The 'loop1' gpio pin controls two relays, which are either in loop
27	// position, meaning that input and output are directly connected, or	27	// position, meaning that input and output are directly connected, or
28	// they are in mixer position, meaning that the signal is passed through	28	// they are in mixer position, meaning that the signal is passed through
29	// the 'Sum' mixer. Similarly for 'loop2'.	29	// the 'Sum' mixer. Similarly for 'loop2'.

sound/soc/bcm/cygnus-pcm.c+1−1

@@ -729,7 +729,7 @@ static struct snd_soc_component_driver cygnus_soc_platform = { · 728 unmodified lines
729	int cygnus_soc_platform_register(struct device *dev,	729	int cygnus_soc_platform_register(struct device *dev,
730	struct cygnus_audio *cygaud)	730	struct cygnus_audio *cygaud)
731	{	731	{
732	int rc = 0;	732	int rc;
733		733
734	dev_dbg(dev, "%s Enter\n", __func__);	734	dev_dbg(dev, "%s Enter\n", __func__);
735		735

sound/soc/codecs/Kconfig+20−1

 	imply SND_SOC_RT715_SDCA_SDW
 	imply SND_SOC_RT1308_SDW
 	imply SND_SOC_RT1316_SDW
+	imply SND_SOC_SDW_MOCKUP
 	imply SND_SOC_SGTL5000
 	imply SND_SOC_SI476X
 	imply SND_SOC_SIMPLE_AMPLIFIER
 	select SND_HDA
 config SND_SOC_ICS43432
-	tristate
+	tristate "ICS43423 and compatible i2s microphones"
 config SND_SOC_INNO_RK3036
 	tristate "Inno codec driver for RK3036 SoC"
 	select REGMAP_SOUNDWIRE
 	select REGMAP_SOUNDWIRE_MBQ
+config SND_SOC_SDW_MOCKUP
+	tristate "SoundWire mockup codec"
+	depends on EXPERT
+	depends on SOUNDWIRE
+	help
+	  This option enables a SoundWire mockup codec that does not drive the
+	  bus, take part in the command/command protocol or generate data on a
+	  Source port.
+	  This option is only intended to be used for tests on a device
+	  with a connector, in combination with a bus analyzer, or to test new
+	  topologies that differ from the actual hardware layout.
+	  This mockup device could be totally virtual but could also be a
+	  real physical one with one key restriction: it is not allowed by the
+	  SoundWire specification to be configured via a sideband mechanism and
+	  generate audio data for capture. However, nothing prevents such a
+	  peripheral device from snooping the bus.
 #Freescale sgtl5000 codec
 config SND_SOC_SGTL5000
 	tristate "Freescale SGTL5000 CODEC"
 config SND_SOC_WCD938X_SDW
 	tristate "WCD9380/WCD9385 Codec - SDW"
 	select SND_SOC_WCD938X
+	select SND_SOC_WCD_MBHC
 	depends on SOUNDWIRE
 	select REGMAP_SOUNDWIRE
 	help

sound/soc/codecs/Makefile+2−0

 snd-soc-rt711-sdca-objs := rt711-sdca.o rt711-sdca-sdw.o
 snd-soc-rt715-objs := rt715.o rt715-sdw.o
 snd-soc-rt715-sdca-objs := rt715-sdca.o rt715-sdca-sdw.o
+snd-soc-sdw-mockup-objs := sdw-mockup.o
 snd-soc-sgtl5000-objs := sgtl5000.o
 snd-soc-alc5623-objs := alc5623.o
 snd-soc-alc5632-objs := alc5632.o
 obj-$(CONFIG_SND_SOC_RT711_SDCA_SDW)     += snd-soc-rt711-sdca.o
 obj-$(CONFIG_SND_SOC_RT715)     += snd-soc-rt715.o
 obj-$(CONFIG_SND_SOC_RT715_SDCA_SDW)     += snd-soc-rt715-sdca.o
+obj-$(CONFIG_SND_SOC_SDW_MOCKUP)     += snd-soc-sdw-mockup.o
 obj-$(CONFIG_SND_SOC_SGTL5000)  += snd-soc-sgtl5000.o
 obj-$(CONFIG_SND_SOC_SIGMADSP)	+= snd-soc-sigmadsp.o
 obj-$(CONFIG_SND_SOC_SIGMADSP_I2C)	+= snd-soc-sigmadsp-i2c.o

sound/soc/codecs/ad193x.c+28−2

 	int word_len = 0, master_rate = 0;
 	struct snd_soc_component *component = dai->component;
 	struct ad193x_priv *ad193x = snd_soc_component_get_drvdata(component);
+	bool is_playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
+	u8 dacc0;
+	dev_dbg(dai->dev, "%s() rate=%u format=%#x width=%u channels=%u\n",
+		__func__, params_rate(params), params_format(params),
+		params_width(params), params_channels(params));
 	/* bit size */
 	switch (params_width(params)) {
 		break;
 	}
+	if (is_playback) {
+		switch (params_rate(params)) {
+		case 48000:
+			dacc0 = AD193X_DAC_SR_48;
+			break;
+		case 96000:
+			dacc0 = AD193X_DAC_SR_96;
+			break;
+		case 192000:
+			dacc0 = AD193X_DAC_SR_192;
+			break;
+		default:
+			dev_err(dai->dev, "invalid sampling rate: %d\n", params_rate(params));
+			return -EINVAL;
+		}
+		regmap_update_bits(ad193x->regmap, AD193X_DAC_CTRL0, AD193X_DAC_SR_MASK, dacc0);
+	}
 	regmap_update_bits(ad193x->regmap, AD193X_PLL_CLK_CTRL0,
 			    AD193X_PLL_INPUT_MASK, master_rate);
 		.stream_name = "Playback",
 		.channels_min = 2,
 		.channels_max = 8,
-		.rates = SNDRV_PCM_RATE_48000,
+		.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
 		.formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S16_LE |
 			SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE,
 	},
 		.stream_name = "Playback",
 		.channels_min = 2,
 		.channels_max = 8,
-		.rates = SNDRV_PCM_RATE_48000,
+		.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
 		.formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S16_LE |
 			SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE,
 	},

sound/soc/codecs/ad193x.h+4−0

 #define AD193X_PLL_CLK_SRC_MCLK	(1 << 1)
 #define AD193X_DAC_CTRL0        0x02
 #define AD193X_DAC_POWERDOWN           0x01
+#define AD193X_DAC_SR_MASK           0x06
+#define AD193X_DAC_SR_48	(0 << 1)
+#define AD193X_DAC_SR_96	(1 << 1)
+#define AD193X_DAC_SR_192	(2 << 1)
 #define AD193X_DAC_SERFMT_MASK		0xC0
 #define AD193X_DAC_SERFMT_STEREO	(0 << 6)
 #define AD193X_DAC_SERFMT_TDM		(1 << 6)

sound/soc/codecs/cs42l42.c+26−2

  * Table 4-5 from the Datasheet
  */
 static const struct cs42l42_pll_params pll_ratio_table[] = {
+	{ 1411200, 0, 1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2},
 	{ 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2},
 	{ 2304000, 0, 1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000,  85, 2},
 	{ 2400000, 0, 1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000,  80, 2},
 	if (channels == 1)
 		cs42l42->bclk *= 2;
+	/*
+	 * Assume 24-bit samples are in 32-bit slots, to prevent SCLK being
+	 * more than assumed (which would result in overclocking).
+	 */
+	if (params_width(params) == 24)
+		cs42l42->bclk = (cs42l42->bclk / 3) * 4;
 	switch(substream->stream) {
 	case SNDRV_PCM_STREAM_CAPTURE:
 		if (channels == 2) {
 {
 	struct snd_soc_component *component = dai->component;
 	struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
+	int i;
-	cs42l42->sclk = freq;
+	if (freq == 0) {
+		cs42l42->sclk = 0;
+		return 0;
+	}
-	return 0;
+	for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
+		if (pll_ratio_table[i].sclk == freq) {
+			cs42l42->sclk = freq;
+			return 0;
+		}
+	}
+	dev_err(component->dev, "SCLK %u not supported\n", freq);
+	return -EINVAL;
 }
 static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>");
+MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");
+MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
+MODULE_AUTHOR("Vitaly Rodionov <vitalyr@opensource.cirrus.com>");
 MODULE_LICENSE("GPL");

sound/soc/codecs/cx20442.c+1−7

  */
 /* Modem init: echo off, digital speaker off, quiet off, voice mode */
-static const char *v253_init = "ate0m0q0+fclass=8\r";
+static const char v253_init[] = "ate0m0q0+fclass=8\r";
 /* Line discipline .open() */
 static int v253_open(struct tty_struct *tty)
 	}
 }
-/* Line discipline .write_wakeup() */
-static void v253_wakeup(struct tty_struct *tty)
-{
-}
 struct tty_ldisc_ops v253_ops = {
 	.name = "cx20442",
 	.owner = THIS_MODULE,
 	.close = v253_close,
 	.hangup = v253_hangup,
 	.receive_buf = v253_receive,
-	.write_wakeup = v253_wakeup,
 };
 EXPORT_SYMBOL_GPL(v253_ops);

sound/soc/codecs/ics43432.c+3−1

 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * I2S MEMS microphone driver for InvenSense ICS-43432
+ * I2S MEMS microphone driver for InvenSense ICS-43432 and similar
+ * MEMS-based microphones.
  *
  * - Non configurable.
  * - I2S interface, 64 BCLs per frame, 32 bits per channel, 24 bit data
 #ifdef CONFIG_OF
 static const struct of_device_id ics43432_ids[] = {
 	{ .compatible = "invensense,ics43432", },
+	{ .compatible = "cui,cmm-4030d-261", },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, ics43432_ids);

sound/soc/codecs/lpass-rx-macro.c+33−32

@@ -1722,42 +1722,43 @@ static int rx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream) · 1721 unmodified lines
1722	case RX_MACRO_AIF2_PB:	1722	case RX_MACRO_AIF2_PB:
1723	case RX_MACRO_AIF3_PB:	1723	case RX_MACRO_AIF3_PB:
1724	case RX_MACRO_AIF4_PB:	1724	case RX_MACRO_AIF4_PB:
1725	for (j = 0; j < INTERP_MAX; j++) {	1725	for (j = 0; j < INTERP_MAX; j++) {
1726	reg = CDC_RX_RXn_RX_PATH_CTL(j);	1726	reg = CDC_RX_RXn_RX_PATH_CTL(j);
1727	mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(j);	1727	mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(j);
1728	dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(j);	1728	dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(j);
1729		1729
1730	if (mute) {	1730	if (mute) {
1731	snd_soc_component_update_bits(component, reg,	1731	snd_soc_component_update_bits(component, reg,
1732	CDC_RX_PATH_PGA_MUTE_MASK,	1732	CDC_RX_PATH_PGA_MUTE_MASK,
1733	CDC_RX_PATH_PGA_MUTE_ENABLE);	1733	CDC_RX_PATH_PGA_MUTE_ENABLE);
1734	snd_soc_component_update_bits(component, mix_reg,	1734	snd_soc_component_update_bits(component, mix_reg,
1735	CDC_RX_PATH_PGA_MUTE_MASK,	1735	CDC_RX_PATH_PGA_MUTE_MASK,
1736	CDC_RX_PATH_PGA_MUTE_ENABLE);	1736	CDC_RX_PATH_PGA_MUTE_ENABLE);
1737	} else {	1737	} else {
1738	snd_soc_component_update_bits(component, reg,	1738	snd_soc_component_update_bits(component, reg,
1739	CDC_RX_PATH_PGA_MUTE_MASK, 0x0);	1739	CDC_RX_PATH_PGA_MUTE_MASK, 0x0);
1740	snd_soc_component_update_bits(component, mix_reg,	1740	snd_soc_component_update_bits(component, mix_reg,
1741	CDC_RX_PATH_PGA_MUTE_MASK, 0x0);	1741	CDC_RX_PATH_PGA_MUTE_MASK, 0x0);
1742	}	1742	}
1743
1744	if (j == INTERP_AUX)
1745	dsm_reg = CDC_RX_RX2_RX_PATH_DSM_CTL;
1746		1743
1747	int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + j * 8;	1744	if (j == INTERP_AUX)
1748	int_mux_cfg1 = int_mux_cfg0 + 4;	1745	dsm_reg = CDC_RX_RX2_RX_PATH_DSM_CTL;
1749	int_mux_cfg0_val = snd_soc_component_read(component, int_mux_cfg0);
1750	int_mux_cfg1_val = snd_soc_component_read(component, int_mux_cfg1);
1751		1746
1752	if (snd_soc_component_read(component, dsm_reg) & 0x01) {	1747	int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + j * 8;
1753	if (int_mux_cfg0_val \|\| (int_mux_cfg1_val & 0xF0))	1748	int_mux_cfg1 = int_mux_cfg0 + 4;
1754	snd_soc_component_update_bits(component, reg, 0x20, 0x20);	1749	int_mux_cfg0_val = snd_soc_component_read(component, int_mux_cfg0);
1755	if (int_mux_cfg1_val & 0x0F) {	1750	int_mux_cfg1_val = snd_soc_component_read(component, int_mux_cfg1);
1756	snd_soc_component_update_bits(component, reg, 0x20, 0x20);	1751
1757	snd_soc_component_update_bits(component, mix_reg, 0x20, 0x20);	1752	if (snd_soc_component_read(component, dsm_reg) & 0x01) {
		1753	if (int_mux_cfg0_val \|\| (int_mux_cfg1_val & 0xF0))
		1754	snd_soc_component_update_bits(component, reg, 0x20, 0x20);
		1755	if (int_mux_cfg1_val & 0x0F) {
		1756	snd_soc_component_update_bits(component, reg, 0x20, 0x20);
		1757	snd_soc_component_update_bits(component, mix_reg, 0x20,
		1758	0x20);
		1759	}
1758	}	1760	}
1759	}	1761	}
1760	}
1761	break;	1762	break;
1762	default:	1763	default:
1763	break;	1764	break;

sound/soc/codecs/max98090.c+1−3

 		msleep(50);
-		reg = snd_soc_component_read(component, M98090_REG_JACK_STATUS);
+		snd_soc_component_read(component, M98090_REG_JACK_STATUS);
 		/* Weak pull up allows only insertion detection */
 		snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT,
 			M98090_JDWK_MASK, M98090_JDWK_MASK);
-	} else {
-		reg = snd_soc_component_read(component, M98090_REG_JACK_STATUS);
 	}
 	reg = snd_soc_component_read(component, M98090_REG_JACK_STATUS);

sound/soc/codecs/max98390.c+20−6

 	vendor = dmi_get_system_info(DMI_SYS_VENDOR);
 	product = dmi_get_system_info(DMI_PRODUCT_NAME);
-	if (vendor && product) {
+	if (!strcmp(max98390->dsm_param_name, "default")) {
-		snprintf(filename, sizeof(filename), "dsm_param_%s_%s.bin",
+		if (vendor && product) {
-			vendor, product);
+			snprintf(filename, sizeof(filename),
+				"dsm_param_%s_%s.bin", vendor, product);
+		} else {
+			sprintf(filename, "dsm_param.bin");
+		}
 	} else {
-		sprintf(filename, "dsm_param.bin");
+		snprintf(filename, sizeof(filename), "%s",
+			max98390->dsm_param_name);
 	}
 	ret = request_firmware(&fw, filename, component->dev);
 	if (ret) {
 		ret = request_firmware(&fw, "dsm_param.bin", component->dev);
-		if (ret)
+		if (ret) {
-			goto err;
+			ret = request_firmware(&fw, "dsmparam.bin",
+				component->dev);
+			if (ret)
+				goto err;
+		}
 	}
 	dev_dbg(component->dev,
 		__func__, max98390->ref_rdc_value,
 		max98390->ambient_temp_value);
+	ret = device_property_read_string(&i2c->dev, "maxim,dsm_param_name",
+				       &max98390->dsm_param_name);
+	if (ret)
+		max98390->dsm_param_name = "default";
 	/* voltage/current slot configuration */
 	max98390_slot_config(i2c, max98390);

sound/soc/codecs/max98390.h+1−0

@@ -662,5 +662,6 @@ struct max98390_priv { · 661 unmodified lines
662	unsigned int i_l_slot;	662	unsigned int i_l_slot;
663	unsigned int ref_rdc_value;	663	unsigned int ref_rdc_value;
664	unsigned int ambient_temp_value;	664	unsigned int ambient_temp_value;
		665	const char *dsm_param_name;
665	};	666	};
666	#endif	667	#endif

sound/soc/codecs/mt6359-accdet.c+5−20

 static void mt6359_accdet_recover_jd_setting(struct mt6359_accdet *priv)
 {
-	int ret = 0;
+	int ret;
 	unsigned int value = 0;
 	regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
 {
 	struct mt6359_accdet *priv = data;
 	unsigned int irq_val = 0, val = 0, value = 0;
-	int ret = 0;
+	int ret;
 	mutex_lock(&priv->res_lock);
 	regmap_read(priv->regmap, ACCDET_IRQ_ADDR, &irq_val);
 static int mt6359_accdet_parse_dt(struct mt6359_accdet *priv)
 {
-	int ret = 0;
+	int ret;
 	struct device *dev = priv->dev;
 	struct device_node *node = NULL;
 	int pwm_deb[15] = {0};
 {
 	struct mt6359_accdet *priv;
 	struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
-	int ret = 0;
+	int ret;
 	dev_dbg(&pdev->dev, "%s(), dev name %s\n",
 		__func__, dev_name(&pdev->dev));
 	.probe = mt6359_accdet_probe,
 };
-static int __init mt6359_accdet_driver_init(void)
+module_platform_driver(mt6359_accdet_driver)
-{
-	int ret = 0;
-	ret = platform_driver_register(&mt6359_accdet_driver);
-	if (ret)
-		return -ENODEV;
-	return 0;
-}
-static void __exit mt6359_accdet_driver_exit(void)
-{
-	platform_driver_unregister(&mt6359_accdet_driver);
-}
-module_init(mt6359_accdet_driver_init);
-module_exit(mt6359_accdet_driver_exit);
 /* Module information */
 MODULE_DESCRIPTION("MT6359 ALSA SoC codec jack driver");

sound/soc/codecs/rt1015.c+3−43

 	return 0;
 }
-static void rt1015_flush_work(struct work_struct *work)
-{
-	struct rt1015_priv *rt1015 = container_of(work, struct rt1015_priv,
-						flush_work.work);
-	struct snd_soc_component *component = rt1015->component;
-	unsigned int val, i;
-	for (i = 0; i < 200; ++i) {
-		usleep_range(1000, 1500);
-		dev_dbg(component->dev, "Flush DAC (retry:%u)\n", i);
-		regmap_read(rt1015->regmap, RT1015_CLK_DET, &val);
-		if (val & 0x800)
-			break;
-	}
-	regmap_write(rt1015->regmap, RT1015_SYS_RST1, 0x0597);
-	regmap_write(rt1015->regmap, RT1015_SYS_RST1, 0x05f7);
-	regmap_write(rt1015->regmap, RT1015_MAN_I2C, 0x0028);
-	if (val & 0x800)
-		dev_dbg(component->dev, "Flush DAC completed.\n");
-	else
-		dev_warn(component->dev, "Fail to flush DAC data.\n");
-}
 static const struct snd_kcontrol_new rt1015_snd_controls[] = {
 	SOC_SINGLE_TLV("DAC Playback Volume", RT1015_DAC1, RT1015_DAC_VOL_SFT,
 		127, 0, dac_vol_tlv),
 		}
 		break;
-	case SND_SOC_DAPM_POST_PMU:
-		regmap_write(rt1015->regmap, RT1015_MAN_I2C, 0x00a8);
-		break;
 	case SND_SOC_DAPM_POST_PMD:
 		if (rt1015->bypass_boost == RT1015_Enable_Boost) {
 			snd_soc_component_write(component,
 				RT1015_SYS_RST2, 0x0b9a);
 		}
 		rt1015->dac_is_used = 0;
-		cancel_delayed_work_sync(&rt1015->flush_work);
 		break;
 	default:
 		}
 		break;
 	case SND_SOC_DAPM_POST_PMU:
-		if (rt1015->hw_config == RT1015_HW_28)
-			schedule_delayed_work(&rt1015->flush_work, msecs_to_jiffies(10));
 		msleep(rt1015->pdata.power_up_delay_ms);
 		break;
 	default:
 		NULL, 0),
 	SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
 	SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0,
-		r1015_dac_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+		r1015_dac_event, SND_SOC_DAPM_PRE_PMU |
 		SND_SOC_DAPM_POST_PMD),
 	SND_SOC_DAPM_OUT_DRV_E("Amp Drv", SND_SOC_NOPM, 0, 0, NULL, 0,
 			rt1015_amp_drv_event, SND_SOC_DAPM_PRE_PMU |
 {
 	struct snd_soc_component *component = dai->component;
 	struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
-	int pre_div, bclk_ms, frame_size, lrck;
+	int pre_div, frame_size, lrck;
 	unsigned int val_len = 0;
 	lrck = params_rate(params);
 		return -EINVAL;
 	}
-	bclk_ms = frame_size > 32;
+	dev_dbg(component->dev, "pre_div is %d for iis %d\n", pre_div, dai->id);
-	dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
-				bclk_ms, pre_div, dai->id);
 	dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
 				lrck, pre_div, dai->id);
 		snd_soc_component_get_drvdata(component);
 	rt1015->component = component;
-	INIT_DELAYED_WORK(&rt1015->flush_work, rt1015_flush_work);
 	return 0;
 }
 {
 	struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
-	cancel_delayed_work_sync(&rt1015->flush_work);
 	regmap_write(rt1015->regmap, RT1015_RESET, 0);
 }
 		return ret;
 	}
-	rt1015->hw_config = (i2c->addr == 0x29) ? RT1015_HW_29 : RT1015_HW_28;
 	ret = regmap_read(rt1015->regmap, RT1015_DEVICE_ID, &val);
 	if (ret) {
 		dev_err(&i2c->dev,

sound/soc/codecs/rt1015.h+0−2

@@ -444,8 +444,6 @@ struct rt1015_priv { · 443 unmodified lines
444	int bypass_boost;	444	int bypass_boost;
445	int dac_is_used;	445	int dac_is_used;
446	int cali_done;	446	int cali_done;
447	int hw_config;
448	struct delayed_work flush_work;
449	};	447	};
450		448
451	#endif /* __RT1015_H__ */	449	#endif /* __RT1015_H__ */

sound/soc/codecs/rt1015p.c+2−0

 #ifdef CONFIG_OF
 static const struct of_device_id rt1015p_device_id[] = {
 	{ .compatible = "realtek,rt1015p" },
+	{ .compatible = "realtek,rt1019p" },
 	{}
 };
 MODULE_DEVICE_TABLE(of, rt1015p_device_id);
 #ifdef CONFIG_ACPI
 static const struct acpi_device_id rt1015p_acpi_match[] = {
 	{ "RTL1015", 0},
+	{ "RTL1019", 0},
 	{ },
 };
 MODULE_DEVICE_TABLE(acpi, rt1015p_acpi_match);

sound/soc/codecs/rt5514.c+1−1

@@ -494,7 +494,7 @@ static const struct snd_kcontrol_new rt5514_sto2_dmic_mux = · 493 unmodified lines
494	*/	494	*/
495	static int rt5514_calc_dmic_clk(struct snd_soc_component *component, int rate)	495	static int rt5514_calc_dmic_clk(struct snd_soc_component *component, int rate)
496	{	496	{
497	int div[] = {2, 3, 4, 8, 12, 16, 24, 32};	497	static const int div[] = {2, 3, 4, 8, 12, 16, 24, 32};
498	int i;	498	int i;
499		499
500	if (rate < 1000000 * div[0]) {	500	if (rate < 1000000 * div[0]) {

sound/soc/codecs/rt5640.c+74−59

@@ -2093,7 +2093,7 @@ int rt5640_sel_asrc_clk_src(struct snd_soc_component *component, · 2092 unmodified lines
2093	}	2093	}
2094	EXPORT_SYMBOL_GPL(rt5640_sel_asrc_clk_src);	2094	EXPORT_SYMBOL_GPL(rt5640_sel_asrc_clk_src);
2095		2095
2096	static void rt5640_enable_micbias1_for_ovcd(struct snd_soc_component *component)	2096	void rt5640_enable_micbias1_for_ovcd(struct snd_soc_component *component)
2097	{	2097	{
2098	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);	2098	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2099		2099
@@ -2105,8 +2105,9 @@ static void rt5640_enable_micbias1_for_ovcd(struct snd_soc_component *component) · 5 unmodified lines
2105	snd_soc_dapm_sync_unlocked(dapm);	2105	snd_soc_dapm_sync_unlocked(dapm);
2106	snd_soc_dapm_mutex_unlock(dapm);	2106	snd_soc_dapm_mutex_unlock(dapm);
2107	}	2107	}
		2108	EXPORT_SYMBOL_GPL(rt5640_enable_micbias1_for_ovcd);
2108		2109
2109	static void rt5640_disable_micbias1_for_ovcd(struct snd_soc_component *component)	2110	void rt5640_disable_micbias1_for_ovcd(struct snd_soc_component *component)
2110	{	2111	{
2111	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);	2112	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2112		2113
@@ -2117,6 +2118,7 @@ static void rt5640_disable_micbias1_for_ovcd(struct snd_soc_component *component · 4 unmodified lines
2117	snd_soc_dapm_sync_unlocked(dapm);	2118	snd_soc_dapm_sync_unlocked(dapm);
2118	snd_soc_dapm_mutex_unlock(dapm);	2119	snd_soc_dapm_mutex_unlock(dapm);
2119	}	2120	}
		2121	EXPORT_SYMBOL_GPL(rt5640_disable_micbias1_for_ovcd);
2120		2122
2121	static void rt5640_enable_micbias1_ovcd_irq(struct snd_soc_component *component)	2123	static void rt5640_enable_micbias1_ovcd_irq(struct snd_soc_component *component)
2122	{	2124	{
@@ -2241,7 +2243,7 @@ static void rt5640_button_press_work(struct work_struct *work) · 118 unmodified lines
2241	schedule_delayed_work(&rt5640->bp_work, msecs_to_jiffies(BP_POLL_TIME));	2243	schedule_delayed_work(&rt5640->bp_work, msecs_to_jiffies(BP_POLL_TIME));
2242	}	2244	}
2243		2245
2244	static int rt5640_detect_headset(struct snd_soc_component *component)	2246	int rt5640_detect_headset(struct snd_soc_component component, struct gpio_desc hp_det_gpio)
2245	{	2247	{
2246	int i, headset_count = 0, headphone_count = 0;	2248	int i, headset_count = 0, headphone_count = 0;
2247		2249
@@ -2259,8 +2261,13 @@ static int rt5640_detect_headset(struct snd_soc_component *component) · 11 unmodified lines
2259	msleep(JACK_SETTLE_TIME);	2261	msleep(JACK_SETTLE_TIME);
2260		2262
2261	/* Check the jack is still connected before checking ovcd */	2263	/* Check the jack is still connected before checking ovcd */
2262	if (!rt5640_jack_inserted(component))	2264	if (hp_det_gpio) {
2263	return 0;	2265	if (gpiod_get_value_cansleep(hp_det_gpio))
		2266	return 0;
		2267	} else {
		2268	if (!rt5640_jack_inserted(component))
		2269	return 0;
		2270	}
2264		2271
2265	if (rt5640_micbias1_ovcd(component)) {	2272	if (rt5640_micbias1_ovcd(component)) {
2266	/*	2273	/*
@@ -2285,6 +2292,7 @@ static int rt5640_detect_headset(struct snd_soc_component *component) · 18 unmodified lines
2285	dev_err(component->dev, "Error detecting headset vs headphones, bad contact?, assuming headphones\n");	2292	dev_err(component->dev, "Error detecting headset vs headphones, bad contact?, assuming headphones\n");
2286	return SND_JACK_HEADPHONE;	2293	return SND_JACK_HEADPHONE;
2287	}	2294	}
		2295	EXPORT_SYMBOL_GPL(rt5640_detect_headset);
2288		2296
2289	static void rt5640_jack_work(struct work_struct *work)	2297	static void rt5640_jack_work(struct work_struct *work)
2290	{	2298	{
@@ -2309,7 +2317,7 @@ static void rt5640_jack_work(struct work_struct *work) · 18 unmodified lines
2309	/* Jack inserted */	2317	/* Jack inserted */
2310	WARN_ON(rt5640->ovcd_irq_enabled);	2318	WARN_ON(rt5640->ovcd_irq_enabled);
2311	rt5640_enable_micbias1_for_ovcd(component);	2319	rt5640_enable_micbias1_for_ovcd(component);
2312	status = rt5640_detect_headset(component);	2320	status = rt5640_detect_headset(component, NULL);
2313	if (status == SND_JACK_HEADSET) {	2321	if (status == SND_JACK_HEADSET) {
2314	/* Enable ovcd IRQ for button press detect. */	2322	/* Enable ovcd IRQ for button press detect. */
2315	rt5640_enable_micbias1_ovcd_irq(component);	2323	rt5640_enable_micbias1_ovcd_irq(component);
@@ -2362,10 +2370,59 @@ static void rt5640_cancel_work(void *data) · 46 unmodified lines
2362	cancel_delayed_work_sync(&rt5640->bp_work);	2370	cancel_delayed_work_sync(&rt5640->bp_work);
2363	}	2371	}
2364		2372
		2373	void rt5640_set_ovcd_params(struct snd_soc_component *component)
		2374	{
		2375	struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
		2376
		2377	snd_soc_component_write(component, RT5640_PR_BASE + RT5640_BIAS_CUR4,
		2378	0xa800 \| rt5640->ovcd_sf);
		2379
		2380	snd_soc_component_update_bits(component, RT5640_MICBIAS,
		2381	RT5640_MIC1_OVTH_MASK \| RT5640_MIC1_OVCD_MASK,
		2382	rt5640->ovcd_th \| RT5640_MIC1_OVCD_EN);
		2383
		2384	/*
		2385	* The over-current-detect is only reliable in detecting the absence
		2386	* of over-current, when the mic-contact in the jack is short-circuited,
		2387	* the hardware periodically retries if it can apply the bias-current
		2388	* leading to the ovcd status flip-flopping 1-0-1 with it being 0 about
		2389	* 10% of the time, as we poll the ovcd status bit we might hit that
		2390	* 10%, so we enable sticky mode and when checking OVCD we clear the
		2391	* status, msleep() a bit and then check to get a reliable reading.
		2392	*/
		2393	snd_soc_component_update_bits(component, RT5640_IRQ_CTRL2,
		2394	RT5640_MB1_OC_STKY_MASK, RT5640_MB1_OC_STKY_EN);
		2395	}
		2396	EXPORT_SYMBOL_GPL(rt5640_set_ovcd_params);
		2397
		2398	static void rt5640_disable_jack_detect(struct snd_soc_component *component)
		2399	{
		2400	struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
		2401
		2402	/*
		2403	* soc_remove_component() force-disables jack and thus rt5640->jack
		2404	* could be NULL at the time of driver's module unloading.
		2405	*/
		2406	if (!rt5640->jack)
		2407	return;
		2408
		2409	free_irq(rt5640->irq, rt5640);
		2410	rt5640_cancel_work(rt5640);
		2411
		2412	if (rt5640->jack->status & SND_JACK_MICROPHONE) {
		2413	rt5640_disable_micbias1_ovcd_irq(component);
		2414	rt5640_disable_micbias1_for_ovcd(component);
		2415	snd_soc_jack_report(rt5640->jack, 0, SND_JACK_BTN_0);
		2416	}
		2417
		2418	rt5640->jack = NULL;
		2419	}
		2420
2365	static void rt5640_enable_jack_detect(struct snd_soc_component *component,	2421	static void rt5640_enable_jack_detect(struct snd_soc_component *component,
2366	struct snd_soc_jack *jack)	2422	struct snd_soc_jack *jack)
2367	{	2423	{
2368	struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);	2424	struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
		2425	int ret;
2369		2426
2370	/* Select JD-source */	2427	/* Select JD-source */
2371	snd_soc_component_update_bits(component, RT5640_JD_CTRL,	2428	snd_soc_component_update_bits(component, RT5640_JD_CTRL,
@@ -2385,24 +2442,7 @@ static void rt5640_enable_jack_detect(struct snd_soc_component *component, · 13 unmodified lines
2385	/* Enabling jd2 in general control 2 */	2442	/* Enabling jd2 in general control 2 */
2386	snd_soc_component_write(component, RT5640_DUMMY2, 0x4001);	2443	snd_soc_component_write(component, RT5640_DUMMY2, 0x4001);
2387		2444
2388	snd_soc_component_write(component, RT5640_PR_BASE + RT5640_BIAS_CUR4,	2445	rt5640_set_ovcd_params(component);
2389	0xa800 \| rt5640->ovcd_sf);
2390
2391	snd_soc_component_update_bits(component, RT5640_MICBIAS,
2392	RT5640_MIC1_OVTH_MASK \| RT5640_MIC1_OVCD_MASK,
2393	rt5640->ovcd_th \| RT5640_MIC1_OVCD_EN);
2394
2395	/*
2396	* The over-current-detect is only reliable in detecting the absence
2397	* of over-current, when the mic-contact in the jack is short-circuited,
2398	* the hardware periodically retries if it can apply the bias-current
2399	* leading to the ovcd status flip-flopping 1-0-1 with it being 0 about
2400	* 10% of the time, as we poll the ovcd status bit we might hit that
2401	* 10%, so we enable sticky mode and when checking OVCD we clear the
2402	* status, msleep() a bit and then check to get a reliable reading.
2403	*/
2404	snd_soc_component_update_bits(component, RT5640_IRQ_CTRL2,
2405	RT5640_MB1_OC_STKY_MASK, RT5640_MB1_OC_STKY_EN);
2406		2446
2407	/*	2447	/*
2408	* All IRQs get or-ed together, so we need the jack IRQ to report 0	2448	* All IRQs get or-ed together, so we need the jack IRQ to report 0
@@ -2423,32 +2463,19 @@ static void rt5640_enable_jack_detect(struct snd_soc_component *component, · 14 unmodified lines
2423	rt5640_enable_micbias1_ovcd_irq(component);	2463	rt5640_enable_micbias1_ovcd_irq(component);
2424	}	2464	}
2425		2465
2426	enable_irq(rt5640->irq);	2466	ret = request_irq(rt5640->irq, rt5640_irq,
2427	/* sync initial jack state */	2467	IRQF_TRIGGER_RISING \| IRQF_TRIGGER_FALLING \| IRQF_ONESHOT,
2428	queue_work(system_long_wq, &rt5640->jack_work);	2468	"rt5640", rt5640);
2429	}	2469	if (ret) {
2430		2470	dev_warn(component->dev, "Failed to reguest IRQ %d: %d\n", rt5640->irq, ret);
2431	static void rt5640_disable_jack_detect(struct snd_soc_component *component)	2471	rt5640->irq = -ENXIO;
2432	{	2472	/* Undo above settings */
2433	struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);	2473	rt5640_disable_jack_detect(component);
2434
2435	/*
2436	* soc_remove_component() force-disables jack and thus rt5640->jack
2437	* could be NULL at the time of driver's module unloading.
2438	*/
2439	if (!rt5640->jack)
2440	return;	2474	return;
2441
2442	disable_irq(rt5640->irq);
2443	rt5640_cancel_work(rt5640);
2444
2445	if (rt5640->jack->status & SND_JACK_MICROPHONE) {
2446	rt5640_disable_micbias1_ovcd_irq(component);
2447	rt5640_disable_micbias1_for_ovcd(component);
2448	snd_soc_jack_report(rt5640->jack, 0, SND_JACK_BTN_0);
2449	}	2475	}
2450		2476
2451	rt5640->jack = NULL;	2477	/* sync initial jack state */
		2478	queue_work(system_long_wq, &rt5640->jack_work);
2452	}	2479	}
2453		2480
2454	static int rt5640_set_jack(struct snd_soc_component *component,	2481	static int rt5640_set_jack(struct snd_soc_component *component,
@@ -2836,18 +2863,6 @@ static int rt5640_i2c_probe(struct i2c_client *i2c, · 381 unmodified lines
2836	if (ret)	2863	if (ret)
2837	return ret;	2864	return ret;
2838		2865
2839	ret = devm_request_irq(&i2c->dev, rt5640->irq, rt5640_irq,
2840	IRQF_TRIGGER_RISING \| IRQF_TRIGGER_FALLING
2841	\| IRQF_ONESHOT, "rt5640", rt5640);
2842	if (ret == 0) {
2843	/* Gets re-enabled by rt5640_set_jack() */
2844	disable_irq(rt5640->irq);
2845	} else {
2846	dev_warn(&i2c->dev, "Failed to reguest IRQ %d: %d\n",
2847	rt5640->irq, ret);
2848	rt5640->irq = -ENXIO;
2849	}
2850
2851	return devm_snd_soc_register_component(&i2c->dev,	2866	return devm_snd_soc_register_component(&i2c->dev,
2852	&soc_component_dev_rt5640,	2867	&soc_component_dev_rt5640,
2853	rt5640_dai, ARRAY_SIZE(rt5640_dai));	2868	rt5640_dai, ARRAY_SIZE(rt5640_dai));

sound/soc/codecs/rt5640.h+6−0

 #define _RT5640_H
 #include <linux/clk.h>
+#include <linux/gpio/consumer.h>
 #include <linux/workqueue.h>
 #include <dt-bindings/sound/rt5640.h>
 int rt5640_sel_asrc_clk_src(struct snd_soc_component *component,
 		unsigned int filter_mask, unsigned int clk_src);
+void rt5640_set_ovcd_params(struct snd_soc_component *component);
+void rt5640_enable_micbias1_for_ovcd(struct snd_soc_component *component);
+void rt5640_disable_micbias1_for_ovcd(struct snd_soc_component *component);
+int rt5640_detect_headset(struct snd_soc_component *component, struct gpio_desc *hp_det_gpio);
 #endif

sound/soc/codecs/rt5682-i2c.c+12−3

 	},
 };
+static void rt5682_i2c_disable_regulators(void *data)
+{
+	struct rt5682_priv *rt5682 = data;
+	regulator_bulk_disable(ARRAY_SIZE(rt5682->supplies), rt5682->supplies);
+}
 static int rt5682_i2c_probe(struct i2c_client *i2c,
 		const struct i2c_device_id *id)
 {
 		return ret;
 	}
+	ret = devm_add_action_or_reset(&i2c->dev, rt5682_i2c_disable_regulators,
+				       rt5682);
+	if (ret)
+		return ret;
 	ret = regulator_bulk_enable(ARRAY_SIZE(rt5682->supplies),
 				    rt5682->supplies);
 	if (ret) {
 static int rt5682_i2c_remove(struct i2c_client *client)
 {
-	struct rt5682_priv *rt5682 = i2c_get_clientdata(client);
 	rt5682_i2c_shutdown(client);
-	regulator_bulk_disable(ARRAY_SIZE(rt5682->supplies), rt5682->supplies);
 	return 0;
 }

sound/soc/codecs/rt5682.c+51−5

@@ -43,7 +43,9 @@ static const struct reg_sequence patch_list[] = { · 42 unmodified lines
43	{RT5682_DAC_ADC_DIG_VOL1, 0xa020},	43	{RT5682_DAC_ADC_DIG_VOL1, 0xa020},
44	{RT5682_I2C_CTRL, 0x000f},	44	{RT5682_I2C_CTRL, 0x000f},
45	{RT5682_PLL2_INTERNAL, 0x8266},	45	{RT5682_PLL2_INTERNAL, 0x8266},
46	{RT5682_SAR_IL_CMD_3, 0x8365},	46	{RT5682_SAR_IL_CMD_1, 0x22b7},
		47	{RT5682_SAR_IL_CMD_3, 0x0365},
		48	{RT5682_SAR_IL_CMD_6, 0x0110},
47	};	49	};
48		50
49	void rt5682_apply_patch_list(struct rt5682_priv rt5682, struct device dev)	51	void rt5682_apply_patch_list(struct rt5682_priv rt5682, struct device dev)
@@ -1726,8 +1728,6 @@ static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = { · 1676 unmodified lines
1726	SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,	1728	SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1727	RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,	1729	RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1728	ARRAY_SIZE(rt5682_sto1_adc_r_mix)),	1730	ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1729	SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1,
1730	14, 1, NULL, 0),
1731		1731
1732	/* ADC PGA */	1732	/* ADC PGA */
1733	SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),	1733	SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
@@ -1898,8 +1898,6 @@ static const struct snd_soc_dapm_route rt5682_dapm_routes[] = { · 164 unmodified lines
1898	{"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},	1898	{"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1899	{"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},	1899	{"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1900		1900
1901	{"ADC Stereo1 Filter", NULL, "BTN Detection Mode"},
1902
1903	{"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},	1901	{"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1904	{"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},	1902	{"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1905		1903
@@ -2915,10 +2913,47 @@ static void rt5682_remove(struct snd_soc_component *component) · 1009 unmodified lines
2915	static int rt5682_suspend(struct snd_soc_component *component)	2913	static int rt5682_suspend(struct snd_soc_component *component)
2916	{	2914	{
2917	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);	2915	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
		2916	unsigned int val;
2918		2917
2919	if (rt5682->is_sdw)	2918	if (rt5682->is_sdw)
2920	return 0;	2919	return 0;
2921		2920
		2921	cancel_delayed_work_sync(&rt5682->jack_detect_work);
		2922	cancel_delayed_work_sync(&rt5682->jd_check_work);
		2923	if (rt5682->hs_jack && rt5682->jack_type == SND_JACK_HEADSET) {
		2924	snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
		2925	RT5682_MB1_PATH_MASK \| RT5682_MB2_PATH_MASK,
		2926	RT5682_CTRL_MB1_REG \| RT5682_CTRL_MB2_REG);
		2927	val = snd_soc_component_read(component,
		2928	RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
		2929
		2930	switch (val) {
		2931	case 0x1:
		2932	snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
		2933	RT5682_SAR_SEL_MB1_MASK \| RT5682_SAR_SEL_MB2_MASK,
		2934	RT5682_SAR_SEL_MB1_NOSEL \| RT5682_SAR_SEL_MB2_SEL);
		2935	break;
		2936	case 0x2:
		2937	snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
		2938	RT5682_SAR_SEL_MB1_MASK \| RT5682_SAR_SEL_MB2_MASK,
		2939	RT5682_SAR_SEL_MB1_SEL \| RT5682_SAR_SEL_MB2_NOSEL);
		2940	break;
		2941	default:
		2942	break;
		2943	}
		2944
		2945	snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
		2946	RT5682_PWR_CBJ, 0);
		2947
		2948	/* enter SAR ADC power saving mode */
		2949	snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
		2950	RT5682_SAR_BUTT_DET_MASK \| RT5682_SAR_BUTDET_MODE_MASK \|
		2951	RT5682_SAR_BUTDET_RST_MASK \| RT5682_SAR_SEL_MB1_MB2_MASK, 0);
		2952	snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
		2953	RT5682_SAR_BUTT_DET_MASK \| RT5682_SAR_BUTDET_MODE_MASK \| RT5682_SAR_BUTDET_RST_MASK,
		2954	RT5682_SAR_BUTT_DET_EN \| RT5682_SAR_BUTDET_POW_SAV \| RT5682_SAR_BUTDET_RST_NORMAL);
		2955	}
		2956
2922	regcache_cache_only(rt5682->regmap, true);	2957	regcache_cache_only(rt5682->regmap, true);
2923	regcache_mark_dirty(rt5682->regmap);	2958	regcache_mark_dirty(rt5682->regmap);
2924	return 0;	2959	return 0;
@@ -2934,6 +2969,17 @@ static int rt5682_resume(struct snd_soc_component *component) · 9 unmodified lines
2934	regcache_cache_only(rt5682->regmap, false);	2969	regcache_cache_only(rt5682->regmap, false);
2935	regcache_sync(rt5682->regmap);	2970	regcache_sync(rt5682->regmap);
2936		2971
		2972	if (rt5682->hs_jack && rt5682->jack_type == SND_JACK_HEADSET) {
		2973	snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
		2974	RT5682_SAR_BUTDET_MODE_MASK \| RT5682_SAR_SEL_MB1_MB2_MASK,
		2975	RT5682_SAR_BUTDET_POW_NORM \| RT5682_SAR_SEL_MB1_MB2_AUTO);
		2976	snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
		2977	RT5682_MB1_PATH_MASK \| RT5682_MB2_PATH_MASK,
		2978	RT5682_CTRL_MB1_FSM \| RT5682_CTRL_MB2_FSM);
		2979	snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
		2980	RT5682_PWR_CBJ, RT5682_PWR_CBJ);
		2981	}
		2982
2937	mod_delayed_work(system_power_efficient_wq,	2983	mod_delayed_work(system_power_efficient_wq,
2938	&rt5682->jack_detect_work, msecs_to_jiffies(250));	2984	&rt5682->jack_detect_work, msecs_to_jiffies(250));
2939		2985

sound/soc/codecs/sdw-mockup.c+310−0

@@ -0,0 +1,310 @@
	1	// SPDX-License-Identifier: GPL-2.0-only
	2	//
	3	// sdw-mockup.c -- a mockup SoundWire codec for tests where only the host
	4	// drives the bus.
	5	//
	6	// Copyright(c) 2021 Intel Corporation
	7	//
	8	//
	9
	10	#include <linux/device.h>
	11	#include <linux/mod_devicetable.h>
	12	#include <linux/module.h>
	13	#include <linux/soundwire/sdw.h>
	14	#include <linux/soundwire/sdw_type.h>
	15	#include <linux/soundwire/sdw_registers.h>
	16	#include <sound/core.h>
	17	#include <sound/pcm.h>
	18	#include <sound/pcm_params.h>
	19	#include <sound/soc.h>
	20
	21	struct sdw_mockup_priv {
	22	struct sdw_slave *slave;
	23	};
	24
	25	struct sdw_stream_data {
	26	struct sdw_stream_runtime *sdw_stream;
	27	};
	28
	29	static int sdw_mockup_component_probe(struct snd_soc_component *component)
	30	{
	31	return 0;
	32	}
	33
	34	static void sdw_mockup_component_remove(struct snd_soc_component *component)
	35	{
	36	}
	37
	38	static const struct snd_soc_component_driver snd_soc_sdw_mockup_component = {
	39	.probe = sdw_mockup_component_probe,
	40	.remove = sdw_mockup_component_remove,
	41	};
	42
	43	static int sdw_mockup_set_sdw_stream(struct snd_soc_dai dai, void sdw_stream,
	44	int direction)
	45	{
	46	struct sdw_stream_data *stream;
	47
	48	if (!sdw_stream)
	49	return 0;
	50
	51	stream = kzalloc(sizeof(*stream), GFP_KERNEL);
	52	if (!stream)
	53	return -ENOMEM;
	54
	55	stream->sdw_stream = sdw_stream;
	56
	57	/* Use tx_mask or rx_mask to configure stream tag and set dma_data */
	58	if (direction == SNDRV_PCM_STREAM_PLAYBACK)
	59	dai->playback_dma_data = stream;
	60	else
	61	dai->capture_dma_data = stream;
	62
	63	return 0;
	64	}
	65
	66	static void sdw_mockup_shutdown(struct snd_pcm_substream *substream,
	67	struct snd_soc_dai *dai)
	68	{
	69	struct sdw_stream_data *stream;
	70
	71	stream = snd_soc_dai_get_dma_data(dai, substream);
	72	snd_soc_dai_set_dma_data(dai, substream, NULL);
	73	kfree(stream);
	74	}
	75
	76	static int sdw_mockup_pcm_hw_params(struct snd_pcm_substream *substream,
	77	struct snd_pcm_hw_params *params,
	78	struct snd_soc_dai *dai)
	79	{
	80	struct snd_soc_component *component = dai->component;
	81	struct sdw_mockup_priv *sdw_mockup = snd_soc_component_get_drvdata(component);
	82	struct sdw_stream_config stream_config;
	83	struct sdw_port_config port_config;
	84	enum sdw_data_direction direction;
	85	struct sdw_stream_data *stream;
	86	int num_channels;
	87	int port;
	88	int ret;
	89
	90	stream = snd_soc_dai_get_dma_data(dai, substream);
	91	if (!stream)
	92	return -EINVAL;
	93
	94	if (!sdw_mockup->slave)
	95	return -EINVAL;
	96
	97	/* SoundWire specific configuration */
	98	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	99	direction = SDW_DATA_DIR_RX;
	100	port = 1;
	101	} else {
	102	direction = SDW_DATA_DIR_TX;
	103	port = 8;
	104	}
	105
	106	stream_config.frame_rate = params_rate(params);
	107	stream_config.ch_count = params_channels(params);
	108	stream_config.bps = snd_pcm_format_width(params_format(params));
	109	stream_config.direction = direction;
	110
	111	num_channels = params_channels(params);
	112	port_config.ch_mask = (1 << num_channels) - 1;
	113	port_config.num = port;
	114
	115	ret = sdw_stream_add_slave(sdw_mockup->slave, &stream_config,
	116	&port_config, 1, stream->sdw_stream);
	117	if (ret)
	118	dev_err(dai->dev, "Unable to configure port\n");
	119
	120	return ret;
	121	}
	122
	123	static int sdw_mockup_pcm_hw_free(struct snd_pcm_substream *substream,
	124	struct snd_soc_dai *dai)
	125	{
	126	struct snd_soc_component *component = dai->component;
	127	struct sdw_mockup_priv *sdw_mockup = snd_soc_component_get_drvdata(component);
	128	struct sdw_stream_data *stream =
	129	snd_soc_dai_get_dma_data(dai, substream);
	130
	131	if (!sdw_mockup->slave)
	132	return -EINVAL;
	133
	134	sdw_stream_remove_slave(sdw_mockup->slave, stream->sdw_stream);
	135	return 0;
	136	}
	137
	138	static const struct snd_soc_dai_ops sdw_mockup_ops = {
	139	.hw_params = sdw_mockup_pcm_hw_params,
	140	.hw_free = sdw_mockup_pcm_hw_free,
	141	.set_sdw_stream = sdw_mockup_set_sdw_stream,
	142	.shutdown = sdw_mockup_shutdown,
	143	};
	144
	145	static struct snd_soc_dai_driver sdw_mockup_dai[] = {
	146	{
	147	.name = "sdw-mockup-aif1",
	148	.id = 1,
	149	.playback = {
	150	.stream_name = "DP1 Playback",
	151	.channels_min = 1,
	152	.channels_max = 2,
	153	},
	154	.capture = {
	155	.stream_name = "DP8 Capture",
	156	.channels_min = 1,
	157	.channels_max = 2,
	158	},
	159	.ops = &sdw_mockup_ops,
	160	},
	161	};
	162
	163	static int sdw_mockup_update_status(struct sdw_slave *slave,
	164	enum sdw_slave_status status)
	165	{
	166	return 0;
	167	}
	168
	169	static int sdw_mockup_read_prop(struct sdw_slave *slave)
	170	{
	171	struct sdw_slave_prop *prop = &slave->prop;
	172	int nval;
	173	int i, j;
	174	u32 bit;
	175	unsigned long addr;
	176	struct sdw_dpn_prop *dpn;
	177
	178	prop->paging_support = false;
	179
	180	/*
	181	* first we need to allocate memory for set bits in port lists
	182	* the port allocation is completely arbitrary:
	183	* DP0 is not supported
	184	* DP1 is sink
	185	* DP8 is source
	186	*/
	187	prop->source_ports = BIT(8);
	188	prop->sink_ports = BIT(1);
	189
	190	nval = hweight32(prop->source_ports);
	191	prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
	192	sizeof(*prop->src_dpn_prop),
	193	GFP_KERNEL);
	194	if (!prop->src_dpn_prop)
	195	return -ENOMEM;
	196
	197	i = 0;
	198	dpn = prop->src_dpn_prop;
	199	addr = prop->source_ports;
	200	for_each_set_bit(bit, &addr, 32) {
	201	dpn[i].num = bit;
	202	dpn[i].type = SDW_DPN_FULL;
	203	dpn[i].simple_ch_prep_sm = true;
	204	i++;
	205	}
	206
	207	/* do this again for sink now */
	208	nval = hweight32(prop->sink_ports);
	209	prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
	210	sizeof(*prop->sink_dpn_prop),
	211	GFP_KERNEL);
	212	if (!prop->sink_dpn_prop)
	213	return -ENOMEM;
	214
	215	j = 0;
	216	dpn = prop->sink_dpn_prop;
	217	addr = prop->sink_ports;
	218	for_each_set_bit(bit, &addr, 32) {
	219	dpn[j].num = bit;
	220	dpn[j].type = SDW_DPN_FULL;
	221	dpn[j].simple_ch_prep_sm = true;
	222	j++;
	223	}
	224
	225	prop->simple_clk_stop_capable = true;
	226
	227	/* wake-up event */
	228	prop->wake_capable = 0;
	229
	230	return 0;
	231	}
	232
	233	static int sdw_mockup_bus_config(struct sdw_slave *slave,
	234	struct sdw_bus_params *params)
	235	{
	236	return 0;
	237	}
	238
	239	static int sdw_mockup_interrupt_callback(struct sdw_slave *slave,
	240	struct sdw_slave_intr_status *status)
	241	{
	242	return 0;
	243	}
	244
	245	static const struct sdw_slave_ops sdw_mockup_slave_ops = {
	246	.read_prop = sdw_mockup_read_prop,
	247	.interrupt_callback = sdw_mockup_interrupt_callback,
	248	.update_status = sdw_mockup_update_status,
	249	.bus_config = sdw_mockup_bus_config,
	250	};
	251
	252	static int sdw_mockup_sdw_probe(struct sdw_slave *slave,
	253	const struct sdw_device_id *id)
	254	{
	255	struct device *dev = &slave->dev;
	256	struct sdw_mockup_priv *sdw_mockup;
	257	int ret;
	258
	259	sdw_mockup = devm_kzalloc(dev, sizeof(*sdw_mockup), GFP_KERNEL);
	260	if (!sdw_mockup)
	261	return -ENOMEM;
	262
	263	dev_set_drvdata(dev, sdw_mockup);
	264	sdw_mockup->slave = slave;
	265
	266	ret = devm_snd_soc_register_component(dev,
	267	&snd_soc_sdw_mockup_component,
	268	sdw_mockup_dai,
	269	ARRAY_SIZE(sdw_mockup_dai));
	270
	271	return ret;
	272	}
	273
	274	static int sdw_mockup_sdw_remove(struct sdw_slave *slave)
	275	{
	276	return 0;
	277	}
	278
	279	/*
	280	* Intel reserved parts ID with the following mapping expected:
	281	* 0xAAAA: generic full-duplex codec
	282	* 0xAA55: headset codec (mock-up of RT711/RT5682) - full-duplex
	283	* 0x55AA: amplifier (mock-up of RT1308/Maxim 98373) - playback only with
	284	* IV feedback
	285	* 0x5555: mic codec (mock-up of RT715) - capture-only
	286	*/
	287	static const struct sdw_device_id sdw_mockup_id[] = {
	288	SDW_SLAVE_ENTRY_EXT(0x0105, 0xAAAA, 0x0, 0, 0),
	289	SDW_SLAVE_ENTRY_EXT(0x0105, 0xAA55, 0x0, 0, 0),
	290	SDW_SLAVE_ENTRY_EXT(0x0105, 0x55AA, 0x0, 0, 0),
	291	SDW_SLAVE_ENTRY_EXT(0x0105, 0x5555, 0x0, 0, 0),
	292	{},
	293	};
	294	MODULE_DEVICE_TABLE(sdw, sdw_mockup_id);
	295
	296	static struct sdw_driver sdw_mockup_sdw_driver = {
	297	.driver = {
	298	.name = "sdw-mockup",
	299	.owner = THIS_MODULE,
	300	},
	301	.probe = sdw_mockup_sdw_probe,
	302	.remove = sdw_mockup_sdw_remove,
	303	.ops = &sdw_mockup_slave_ops,
	304	.id_table = sdw_mockup_id,
	305	};
	306	module_sdw_driver(sdw_mockup_sdw_driver);
	307
	308	MODULE_DESCRIPTION("ASoC SDW mockup codec driver");
	309	MODULE_AUTHOR("Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>");
	310	MODULE_LICENSE("GPL");

sound/soc/codecs/tlv320aic32x4.c+5−5

@@ -714,7 +714,7 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component, · 713 unmodified lines
714	unsigned long adc_clock_rate, dac_clock_rate;	714	unsigned long adc_clock_rate, dac_clock_rate;
715	int ret;	715	int ret;
716		716
717	struct clk_bulk_data clocks[] = {	717	static struct clk_bulk_data clocks[] = {
718	{ .id = "pll" },	718	{ .id = "pll" },
719	{ .id = "nadc" },	719	{ .id = "nadc" },
720	{ .id = "madc" },	720	{ .id = "madc" },
@@ -878,7 +878,7 @@ static int aic32x4_set_bias_level(struct snd_soc_component *component, · 157 unmodified lines
878	{	878	{
879	int ret;	879	int ret;
880		880
881	struct clk_bulk_data clocks[] = {	881	static struct clk_bulk_data clocks[] = {
882	{ .id = "madc" },	882	{ .id = "madc" },
883	{ .id = "mdac" },	883	{ .id = "mdac" },
884	{ .id = "bdiv" },	884	{ .id = "bdiv" },
@@ -994,7 +994,7 @@ static int aic32x4_component_probe(struct snd_soc_component *component) · 109 unmodified lines
994	u32 tmp_reg;	994	u32 tmp_reg;
995	int ret;	995	int ret;
996		996
997	struct clk_bulk_data clocks[] = {	997	static struct clk_bulk_data clocks[] = {
998	{ .id = "codec_clkin" },	998	{ .id = "codec_clkin" },
999	{ .id = "pll" },	999	{ .id = "pll" },
1000	{ .id = "bdiv" },	1000	{ .id = "bdiv" },
@@ -1131,7 +1131,7 @@ static struct snd_soc_dai_driver aic32x4_tas2505_dai = { · 130 unmodified lines
1131	.playback = {	1131	.playback = {
1132	.stream_name = "Playback",	1132	.stream_name = "Playback",
1133	.channels_min = 1,	1133	.channels_min = 1,
1134	.channels_max = 1,	1134	.channels_max = 2,
1135	.rates = SNDRV_PCM_RATE_8000_96000,	1135	.rates = SNDRV_PCM_RATE_8000_96000,
1136	.formats = AIC32X4_FORMATS,},	1136	.formats = AIC32X4_FORMATS,},
1137	.ops = &aic32x4_ops,	1137	.ops = &aic32x4_ops,
@@ -1144,7 +1144,7 @@ static int aic32x4_tas2505_component_probe(struct snd_soc_component *component) · 6 unmodified lines
1144	u32 tmp_reg;	1144	u32 tmp_reg;
1145	int ret;	1145	int ret;
1146		1146
1147	struct clk_bulk_data clocks[] = {	1147	static struct clk_bulk_data clocks[] = {
1148	{ .id = "codec_clkin" },	1148	{ .id = "codec_clkin" },
1149	{ .id = "pll" },	1149	{ .id = "pll" },
1150	{ .id = "bdiv" },	1150	{ .id = "bdiv" },

sound/soc/codecs/wcd9335.c+21−2

 	return ret;
 }
+static void wcd9335_teardown_irqs(struct wcd9335_codec *wcd)
+{
+	int i;
+	/* disable interrupts on all slave ports */
+	for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++)
+		regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i,
+			     0x00);
+}
 static void wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec *wcd,
 					bool ccl_flag)
 {
 static int wcd9335_codec_probe(struct snd_soc_component *component)
 {
 	struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
+	int ret;
 	int i;
 	snd_soc_component_init_regmap(component, wcd->regmap);
 	for (i = 0; i < NUM_CODEC_DAIS; i++)
 		INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
-	return wcd9335_setup_irqs(wcd);
+	ret = wcd9335_setup_irqs(wcd);
+	if (ret)
+		goto free_clsh_ctrl;
+	return 0;
+free_clsh_ctrl:
+	wcd_clsh_ctrl_free(wcd->clsh_ctrl);
+	return ret;
 }
 static void wcd9335_codec_remove(struct snd_soc_component *comp)
 	struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
 	wcd_clsh_ctrl_free(wcd->clsh_ctrl);
-	free_irq(regmap_irq_get_virq(wcd->irq_data, WCD9335_IRQ_SLIMBUS), wcd);
+	wcd9335_teardown_irqs(wcd);
 }
 static int wcd9335_codec_set_sysclk(struct snd_soc_component *comp,

sound/soc/codecs/wcd938x.c+822−32

@@ -21,6 +21,7 @@ · 20 unmodified lines
21	#include <linux/regulator/consumer.h>	21	#include <linux/regulator/consumer.h>
22		22
23	#include "wcd-clsh-v2.h"	23	#include "wcd-clsh-v2.h"
		24	#include "wcd-mbhc-v2.h"
24	#include "wcd938x.h"	25	#include "wcd938x.h"
25		26
26	#define WCD938X_MAX_MICBIAS (4)	27	#define WCD938X_MAX_MICBIAS (4)
@@ -173,6 +174,11 @@ struct wcd938x_priv { · 146 unmodified lines
173	struct device *rxdev;	174	struct device *rxdev;
174	struct device_node rxnode, txnode;	175	struct device_node rxnode, txnode;
175	struct regmap *regmap;	176	struct regmap *regmap;
		177	struct mutex micb_lock;
		178	/* mbhc module */
		179	struct wcd_mbhc *wcd_mbhc;
		180	struct wcd_mbhc_config mbhc_cfg;
		181	struct wcd_mbhc_intr intr_ids;
176	struct wcd_clsh_ctrl *clsh_info;	182	struct wcd_clsh_ctrl *clsh_info;
177	struct irq_domain *virq;	183	struct irq_domain *virq;
178	struct regmap_irq_chip *wcd_regmap_irq_chip;	184	struct regmap_irq_chip *wcd_regmap_irq_chip;
@@ -201,24 +207,70 @@ struct wcd938x_priv { · 22 unmodified lines
201	bool bcs_dis;	207	bool bcs_dis;
202	};	208	};
203		209
204	enum {
205	MIC_BIAS_1 = 1,
206	MIC_BIAS_2,
207	MIC_BIAS_3,
208	MIC_BIAS_4
209	};
210
211	enum {
212	MICB_PULLUP_ENABLE,
213	MICB_PULLUP_DISABLE,
214	MICB_ENABLE,
215	MICB_DISABLE,
216	};
217
218	static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);	210	static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
219	static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(line_gain, 600, -3000);	211	static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(line_gain, 600, -3000);
220	static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000);	212	static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000);
221		213
		214	struct wcd938x_mbhc_zdet_param {
		215	u16 ldo_ctl;
		216	u16 noff;
		217	u16 nshift;
		218	u16 btn5;
		219	u16 btn6;
		220	u16 btn7;
		221	};
		222
		223	static struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = {
		224	WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD938X_ANA_MBHC_MECH, 0x80),
		225	WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD938X_ANA_MBHC_MECH, 0x40),
		226	WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD938X_ANA_MBHC_MECH, 0x20),
		227	WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x30),
		228	WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD938X_ANA_MBHC_ELECT, 0x08),
		229	WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F),
		230	WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD938X_ANA_MBHC_MECH, 0x04),
		231	WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x10),
		232	WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x08),
		233	WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD938X_ANA_MBHC_MECH, 0x01),
		234	WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD938X_ANA_MBHC_ELECT, 0x06),
		235	WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD938X_ANA_MBHC_ELECT, 0x80),
		236	WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F),
		237	WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD938X_MBHC_NEW_CTL_1, 0x03),
		238	WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD938X_MBHC_NEW_CTL_2, 0x03),
		239	WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x08),
		240	WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD938X_ANA_MBHC_RESULT_3, 0x10),
		241	WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x20),
		242	WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x80),
		243	WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x40),
		244	WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD938X_HPH_OCP_CTL, 0x10),
		245	WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x07),
		246	WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD938X_ANA_MBHC_ELECT, 0x70),
		247	WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0xFF),
		248	WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD938X_ANA_MICB2, 0xC0),
		249	WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD938X_HPH_CNP_WG_TIME, 0xFF),
		250	WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD938X_ANA_HPH, 0x40),
		251	WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD938X_ANA_HPH, 0x80),
		252	WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD938X_ANA_HPH, 0xC0),
		253	WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD938X_ANA_MBHC_RESULT_3, 0x10),
		254	WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD938X_MBHC_CTL_BCS, 0x02),
		255	WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x01),
		256	WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD938X_MBHC_NEW_CTL_2, 0x70),
		257	WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x20),
		258	WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD938X_HPH_PA_CTL2, 0x40),
		259	WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD938X_HPH_PA_CTL2, 0x10),
		260	WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD938X_HPH_L_TEST, 0x01),
		261	WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD938X_HPH_R_TEST, 0x01),
		262	WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x80),
		263	WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x20),
		264	WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD938X_MBHC_NEW_CTL_1, 0x08),
		265	WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD938X_MBHC_NEW_FSM_STATUS, 0x40),
		266	WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD938X_MBHC_NEW_FSM_STATUS, 0x80),
		267	WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD938X_MBHC_NEW_ADC_RESULT, 0xFF),
		268	WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD938X_ANA_MICB2, 0x3F),
		269	WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD938X_MBHC_NEW_CTL_1, 0x10),
		270	WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD938X_MBHC_NEW_CTL_1, 0x04),
		271	WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD938X_ANA_MBHC_ZDET, 0x02),
		272	};
		273
222	static const struct reg_default wcd938x_defaults[] = {	274	static const struct reg_default wcd938x_defaults[] = {
223	{WCD938X_ANA_PAGE_REGISTER, 0x00},	275	{WCD938X_ANA_PAGE_REGISTER, 0x00},
224	{WCD938X_ANA_BIAS, 0x00},	276	{WCD938X_ANA_BIAS, 0x00},
@@ -1360,7 +1412,6 @@ static int wcd938x_io_init(struct wcd938x_priv *wcd938x) · 1135 unmodified lines
1360		1412
1361	static int wcd938x_sdw_connect_port(struct wcd938x_sdw_ch_info *ch_info,	1413	static int wcd938x_sdw_connect_port(struct wcd938x_sdw_ch_info *ch_info,
1362	struct sdw_port_config *port_config,	1414	struct sdw_port_config *port_config,
1363	u32 mstr_port_num,
1364	u8 enable)	1415	u8 enable)
1365	{	1416	{
1366	u8 ch_mask, port_num;	1417	u8 ch_mask, port_num;
@@ -1380,14 +1431,12 @@ static int wcd938x_sdw_connect_port(struct wcd938x_sdw_ch_info *ch_info, · 13 unmodified lines
1380		1431
1381	static int wcd938x_connect_port(struct wcd938x_sdw_priv *wcd, u8 ch_id, u8 enable)	1432	static int wcd938x_connect_port(struct wcd938x_sdw_priv *wcd, u8 ch_id, u8 enable)
1382	{	1433	{
1383	u8 port_num, mstr_port_num;	1434	u8 port_num;
1384		1435
1385	port_num = wcd->ch_info[ch_id].port_num;	1436	port_num = wcd->ch_info[ch_id].port_num;
1386	mstr_port_num = wcd->port_map[port_num - 1];
1387		1437
1388	return wcd938x_sdw_connect_port(&wcd->ch_info[ch_id],	1438	return wcd938x_sdw_connect_port(&wcd->ch_info[ch_id],
1389	&wcd->port_config[port_num],	1439	&wcd->port_config[port_num],
1390	mstr_port_num,
1391	enable);	1440	enable);
1392	}	1441	}
1393		1442
@@ -1623,7 +1672,6 @@ static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w, · 229 unmodified lines
1623	{	1672	{
1624	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);	1673	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1625	struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);	1674	struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1626	int ret = 0;
1627		1675
1628	switch (event) {	1676	switch (event) {
1629	case SND_SOC_DAPM_PRE_PMU:	1677	case SND_SOC_DAPM_PRE_PMU:
@@ -1651,7 +1699,7 @@ static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w, · 21 unmodified lines
1651	WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 0);	1699	WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 0);
1652	break;	1700	break;
1653	}	1701	}
1654	return ret;	1702	return 0;
1655		1703
1656	}	1704	}
1657		1705
@@ -1728,6 +1776,8 @@ static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, · 70 unmodified lines
1728	usleep_range(7000, 7100);	1776	usleep_range(7000, 7100);
1729	snd_soc_component_write_field(component, WCD938X_ANA_HPH,	1777	snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1730	WCD938X_HPHR_EN_MASK, 0);	1778	WCD938X_HPHR_EN_MASK, 0);
		1779	wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
		1780	WCD_EVENT_PRE_HPHR_PA_OFF);
1731	set_bit(HPH_PA_DELAY, &wcd938x->status_mask);	1781	set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1732	break;	1782	break;
1733	case SND_SOC_DAPM_POST_PMD:	1783	case SND_SOC_DAPM_POST_PMD:
@@ -1743,6 +1793,8 @@ static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, · 9 unmodified lines
1743	usleep_range(7000, 7100);	1793	usleep_range(7000, 7100);
1744	clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);	1794	clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1745	}	1795	}
		1796	wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
		1797	WCD_EVENT_POST_HPHR_PA_OFF);
1746	snd_soc_component_write_field(component, WCD938X_ANA_HPH,	1798	snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1747	WCD938X_HPHR_REF_EN_MASK, 0);	1799	WCD938X_HPHR_REF_EN_MASK, 0);
1748	snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL1,	1800	snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL1,
@@ -1830,6 +1882,7 @@ static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, · 81 unmodified lines
1830	usleep_range(7000, 7100);	1882	usleep_range(7000, 7100);
1831	snd_soc_component_write_field(component, WCD938X_ANA_HPH,	1883	snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1832	WCD938X_HPHL_EN_MASK, 0);	1884	WCD938X_HPHL_EN_MASK, 0);
		1885	wcd_mbhc_event_notify(wcd938x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF);
1833	set_bit(HPH_PA_DELAY, &wcd938x->status_mask);	1886	set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1834	break;	1887	break;
1835	case SND_SOC_DAPM_POST_PMD:	1888	case SND_SOC_DAPM_POST_PMD:
@@ -1845,6 +1898,8 @@ static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, · 9 unmodified lines
1845	usleep_range(7000, 7100);	1898	usleep_range(7000, 7100);
1846	clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);	1899	clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1847	}	1900	}
		1901	wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
		1902	WCD_EVENT_POST_HPHL_PA_OFF);
1848	snd_soc_component_write_field(component, WCD938X_ANA_HPH,	1903	snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1849	WCD938X_HPHL_REF_EN_MASK, 0);	1904	WCD938X_HPHL_REF_EN_MASK, 0);
1850	snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0,	1905	snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0,
@@ -1866,7 +1921,6 @@ static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w, · 15 unmodified lines
1866	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);	1921	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1867	struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);	1922	struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1868	int hph_mode = wcd938x->hph_mode;	1923	int hph_mode = wcd938x->hph_mode;
1869	int ret = 0;
1870		1924
1871	switch (event) {	1925	switch (event) {
1872	case SND_SOC_DAPM_PRE_PMU:	1926	case SND_SOC_DAPM_PRE_PMU:
@@ -1902,7 +1956,7 @@ static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w, · 29 unmodified lines
1902	WCD938X_EN_CUR_DET_MASK, 1);	1956	WCD938X_EN_CUR_DET_MASK, 1);
1903	break;	1957	break;
1904	}	1958	}
1905	return ret;	1959	return 0;
1906	}	1960	}
1907		1961
1908	static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,	1962	static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
@@ -2355,7 +2409,14 @@ static int wcd938x_micbias_control(struct snd_soc_component *component, · 446 unmodified lines
2355	snd_soc_component_write_field(component, micb_reg,	2409	snd_soc_component_write_field(component, micb_reg,
2356	WCD938X_MICB_EN_MASK,	2410	WCD938X_MICB_EN_MASK,
2357	WCD938X_MICB_ENABLE);	2411	WCD938X_MICB_ENABLE);
		2412	if (micb_num == MIC_BIAS_2)
		2413	wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
		2414	WCD_EVENT_POST_MICBIAS_2_ON);
2358	}	2415	}
		2416	if (micb_num == MIC_BIAS_2 && is_dapm)
		2417	wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
		2418	WCD_EVENT_POST_DAPM_MICBIAS_2_ON);
		2419
2359		2420
2360	break;	2421	break;
2361	case MICB_DISABLE:	2422	case MICB_DISABLE:
@@ -2369,10 +2430,19 @@ static int wcd938x_micbias_control(struct snd_soc_component *component, · 7 unmodified lines
2369	WCD938X_MICB_PULL_UP);	2430	WCD938X_MICB_PULL_UP);
2370	else if ((wcd938x->micb_ref[micb_index] == 0) &&	2431	else if ((wcd938x->micb_ref[micb_index] == 0) &&
2371	(wcd938x->pullup_ref[micb_index] == 0)) {	2432	(wcd938x->pullup_ref[micb_index] == 0)) {
		2433	if (micb_num == MIC_BIAS_2)
		2434	wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
		2435	WCD_EVENT_PRE_MICBIAS_2_OFF);
2372		2436
2373	snd_soc_component_write_field(component, micb_reg,	2437	snd_soc_component_write_field(component, micb_reg,
2374	WCD938X_MICB_EN_MASK, 0);	2438	WCD938X_MICB_EN_MASK, 0);
		2439	if (micb_num == MIC_BIAS_2)
		2440	wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
		2441	WCD_EVENT_POST_MICBIAS_2_OFF);
2375	}	2442	}
		2443	if (is_dapm && micb_num == MIC_BIAS_2)
		2444	wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
		2445	WCD_EVENT_POST_DAPM_MICBIAS_2_OFF);
2376	break;	2446	break;
2377	}	2447	}
2378		2448
@@ -2845,6 +2915,704 @@ static int wcd938x_set_swr_port(struct snd_kcontrol *kcontrol, · 466 unmodified lines
2845		2915
2846	}	2916	}
2847		2917
		2918	/* MBHC related */
		2919	static void wcd938x_mbhc_clk_setup(struct snd_soc_component *component,
		2920	bool enable)
		2921	{
		2922	snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_1,
		2923	WCD938X_MBHC_CTL_RCO_EN_MASK, enable);
		2924	}
		2925
		2926	static void wcd938x_mbhc_mbhc_bias_control(struct snd_soc_component *component,
		2927	bool enable)
		2928	{
		2929	snd_soc_component_write_field(component, WCD938X_ANA_MBHC_ELECT,
		2930	WCD938X_ANA_MBHC_BIAS_EN, enable);
		2931	}
		2932
		2933	static void wcd938x_mbhc_program_btn_thr(struct snd_soc_component *component,
		2934	int btn_low, int btn_high,
		2935	int num_btn, bool is_micbias)
		2936	{
		2937	int i, vth;
		2938
		2939	if (num_btn > WCD_MBHC_DEF_BUTTONS) {
		2940	dev_err(component->dev, "%s: invalid number of buttons: %d\n",
		2941	__func__, num_btn);
		2942	return;
		2943	}
		2944
		2945	for (i = 0; i < num_btn; i++) {
		2946	vth = ((btn_high[i] * 2) / 25) & 0x3F;
		2947	snd_soc_component_write_field(component, WCD938X_ANA_MBHC_BTN0 + i,
		2948	WCD938X_MBHC_BTN_VTH_MASK, vth);
		2949	dev_dbg(component->dev, "%s: btn_high[%d]: %d, vth: %d\n",
		2950	__func__, i, btn_high[i], vth);
		2951	}
		2952	}
		2953
		2954	static bool wcd938x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num)
		2955	{
		2956	u8 val;
		2957
		2958	if (micb_num == MIC_BIAS_2) {
		2959	val = snd_soc_component_read_field(component,
		2960	WCD938X_ANA_MICB2,
		2961	WCD938X_ANA_MICB2_ENABLE_MASK);
		2962	if (val == WCD938X_MICB_ENABLE)
		2963	return true;
		2964	}
		2965	return false;
		2966	}
		2967
		2968	static void wcd938x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component,
		2969	int pull_up_cur)
		2970	{
		2971	/* Default pull up current to 2uA */
		2972	if (pull_up_cur > HS_PULLUP_I_OFF \|\| pull_up_cur < HS_PULLUP_I_3P0_UA)
		2973	pull_up_cur = HS_PULLUP_I_2P0_UA;
		2974
		2975	snd_soc_component_write_field(component,
		2976	WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT,
		2977	WCD938X_HSDET_PULLUP_C_MASK, pull_up_cur);
		2978	}
		2979
		2980	static int wcd938x_mbhc_request_micbias(struct snd_soc_component *component,
		2981	int micb_num, int req)
		2982	{
		2983	return wcd938x_micbias_control(component, micb_num, req, false);
		2984	}
		2985
		2986	static void wcd938x_mbhc_micb_ramp_control(struct snd_soc_component *component,
		2987	bool enable)
		2988	{
		2989	if (enable) {
		2990	snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
		2991	WCD938X_RAMP_SHIFT_CTRL_MASK, 0x0C);
		2992	snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
		2993	WCD938X_RAMP_EN_MASK, 1);
		2994	} else {
		2995	snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
		2996	WCD938X_RAMP_EN_MASK, 0);
		2997	snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
		2998	WCD938X_RAMP_SHIFT_CTRL_MASK, 0);
		2999	}
		3000	}
		3001
		3002	static int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
		3003	{
		3004	/* min micbias voltage is 1V and maximum is 2.85V */
		3005	if (micb_mv < 1000 \|\| micb_mv > 2850)
		3006	return -EINVAL;
		3007
		3008	return (micb_mv - 1000) / 50;
		3009	}
		3010
		3011	static int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
		3012	int req_volt, int micb_num)
		3013	{
		3014	struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
		3015	int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0;
		3016
		3017	switch (micb_num) {
		3018	case MIC_BIAS_1:
		3019	micb_reg = WCD938X_ANA_MICB1;
		3020	break;
		3021	case MIC_BIAS_2:
		3022	micb_reg = WCD938X_ANA_MICB2;
		3023	break;
		3024	case MIC_BIAS_3:
		3025	micb_reg = WCD938X_ANA_MICB3;
		3026	break;
		3027	case MIC_BIAS_4:
		3028	micb_reg = WCD938X_ANA_MICB4;
		3029	break;
		3030	default:
		3031	return -EINVAL;
		3032	}
		3033	mutex_lock(&wcd938x->micb_lock);
		3034	/*
		3035	* If requested micbias voltage is same as current micbias
		3036	* voltage, then just return. Otherwise, adjust voltage as
		3037	* per requested value. If micbias is already enabled, then
		3038	* to avoid slow micbias ramp-up or down enable pull-up
		3039	* momentarily, change the micbias value and then re-enable
		3040	* micbias.
		3041	*/
		3042	micb_en = snd_soc_component_read_field(component, micb_reg,
		3043	WCD938X_MICB_EN_MASK);
		3044	cur_vout_ctl = snd_soc_component_read_field(component, micb_reg,
		3045	WCD938X_MICB_VOUT_MASK);
		3046
		3047	req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
		3048	if (req_vout_ctl < 0) {
		3049	ret = -EINVAL;
		3050	goto exit;
		3051	}
		3052
		3053	if (cur_vout_ctl == req_vout_ctl) {
		3054	ret = 0;
		3055	goto exit;
		3056	}
		3057
		3058	if (micb_en == WCD938X_MICB_ENABLE)
		3059	snd_soc_component_write_field(component, micb_reg,
		3060	WCD938X_MICB_EN_MASK,
		3061	WCD938X_MICB_PULL_UP);
		3062
		3063	snd_soc_component_write_field(component, micb_reg,
		3064	WCD938X_MICB_VOUT_MASK,
		3065	req_vout_ctl);
		3066
		3067	if (micb_en == WCD938X_MICB_ENABLE) {
		3068	snd_soc_component_write_field(component, micb_reg,
		3069	WCD938X_MICB_EN_MASK,
		3070	WCD938X_MICB_ENABLE);
		3071	/*
		3072	* Add 2ms delay as per HW requirement after enabling
		3073	* micbias
		3074	*/
		3075	usleep_range(2000, 2100);
		3076	}
		3077	exit:
		3078	mutex_unlock(&wcd938x->micb_lock);
		3079	return ret;
		3080	}
		3081
		3082	static int wcd938x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component,
		3083	int micb_num, bool req_en)
		3084	{
		3085	struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
		3086	int rc, micb_mv;
		3087
		3088	if (micb_num != MIC_BIAS_2)
		3089	return -EINVAL;
		3090	/*
		3091	* If device tree micbias level is already above the minimum
		3092	* voltage needed to detect threshold microphone, then do
		3093	* not change the micbias, just return.
		3094	*/
		3095	if (wcd938x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
		3096	return 0;
		3097
		3098	micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd938x->micb2_mv;
		3099
		3100	rc = wcd938x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2);
		3101
		3102	return rc;
		3103	}
		3104
		3105	static inline void wcd938x_mbhc_get_result_params(struct wcd938x_priv *wcd938x,
		3106	s16 *d1_a, u16 noff,
		3107	int32_t *zdet)
		3108	{
		3109	int i;
		3110	int val, val1;
		3111	s16 c1;
		3112	s32 x1, d1;
		3113	int32_t denom;
		3114	int minCode_param[] = {
		3115	3277, 1639, 820, 410, 205, 103, 52, 26
		3116	};
		3117
		3118	regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x20);
		3119	for (i = 0; i < WCD938X_ZDET_NUM_MEASUREMENTS; i++) {
		3120	regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_2, &val);
		3121	if (val & 0x80)
		3122	break;
		3123	}
		3124	val = val << 0x8;
		3125	regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_1, &val1);
		3126	val \|= val1;
		3127	regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x00);
		3128	x1 = WCD938X_MBHC_GET_X1(val);
		3129	c1 = WCD938X_MBHC_GET_C1(val);
		3130	/* If ramp is not complete, give additional 5ms */
		3131	if ((c1 < 2) && x1)
		3132	usleep_range(5000, 5050);
		3133
		3134	if (!c1 \|\| !x1) {
		3135	pr_err("%s: Impedance detect ramp error, c1=%d, x1=0x%x\n",
		3136	__func__, c1, x1);
		3137	goto ramp_down;
		3138	}
		3139	d1 = d1_a[c1];
		3140	denom = (x1 * d1) - (1 << (14 - noff));
		3141	if (denom > 0)
		3142	zdet = (WCD938X_MBHC_ZDET_CONST 1000) / denom;
		3143	else if (x1 < minCode_param[noff])
		3144	*zdet = WCD938X_ZDET_FLOATING_IMPEDANCE;
		3145
		3146	pr_err("%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n",
		3147	__func__, d1, c1, x1, *zdet);
		3148	ramp_down:
		3149	i = 0;
		3150	while (x1) {
		3151	regmap_read(wcd938x->regmap,
		3152	WCD938X_ANA_MBHC_RESULT_1, &val);
		3153	regmap_read(wcd938x->regmap,
		3154	WCD938X_ANA_MBHC_RESULT_2, &val1);
		3155	val = val << 0x08;
		3156	val \|= val1;
		3157	x1 = WCD938X_MBHC_GET_X1(val);
		3158	i++;
		3159	if (i == WCD938X_ZDET_NUM_MEASUREMENTS)
		3160	break;
		3161	}
		3162	}
		3163
		3164	static void wcd938x_mbhc_zdet_ramp(struct snd_soc_component *component,
		3165	struct wcd938x_mbhc_zdet_param *zdet_param,
		3166	int32_t zl, int32_t zr, s16 *d1_a)
		3167	{
		3168	struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
		3169	int32_t zdet = 0;
		3170
		3171	snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL,
		3172	WCD938X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl);
		3173	snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN5,
		3174	WCD938X_VTH_MASK, zdet_param->btn5);
		3175	snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN6,
		3176	WCD938X_VTH_MASK, zdet_param->btn6);
		3177	snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN7,
		3178	WCD938X_VTH_MASK, zdet_param->btn7);
		3179	snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL,
		3180	WCD938X_ZDET_RANGE_CTL_MASK, zdet_param->noff);
		3181	snd_soc_component_update_bits(component, WCD938X_MBHC_NEW_ZDET_RAMP_CTL,
		3182	0x0F, zdet_param->nshift);
		3183
		3184	if (!zl)
		3185	goto z_right;
		3186	/* Start impedance measurement for HPH_L */
		3187	regmap_update_bits(wcd938x->regmap,
		3188	WCD938X_ANA_MBHC_ZDET, 0x80, 0x80);
		3189	dev_dbg(component->dev, "%s: ramp for HPH_L, noff = %d\n",
		3190	__func__, zdet_param->noff);
		3191	wcd938x_mbhc_get_result_params(wcd938x, d1_a, zdet_param->noff, &zdet);
		3192	regmap_update_bits(wcd938x->regmap,
		3193	WCD938X_ANA_MBHC_ZDET, 0x80, 0x00);
		3194
		3195	*zl = zdet;
		3196
		3197	z_right:
		3198	if (!zr)
		3199	return;
		3200	/* Start impedance measurement for HPH_R */
		3201	regmap_update_bits(wcd938x->regmap,
		3202	WCD938X_ANA_MBHC_ZDET, 0x40, 0x40);
		3203	dev_dbg(component->dev, "%s: ramp for HPH_R, noff = %d\n",
		3204	__func__, zdet_param->noff);
		3205	wcd938x_mbhc_get_result_params(wcd938x, d1_a, zdet_param->noff, &zdet);
		3206	regmap_update_bits(wcd938x->regmap,
		3207	WCD938X_ANA_MBHC_ZDET, 0x40, 0x00);
		3208
		3209	*zr = zdet;
		3210	}
		3211
		3212	static inline void wcd938x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component,
		3213	int32_t *z_val, int flag_l_r)
		3214	{
		3215	s16 q1;
		3216	int q1_cal;
		3217
		3218	if (*z_val < (WCD938X_ZDET_VAL_400/1000))
		3219	q1 = snd_soc_component_read(component,
		3220	WCD938X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r));
		3221	else
		3222	q1 = snd_soc_component_read(component,
		3223	WCD938X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r));
		3224	if (q1 & 0x80)
		3225	q1_cal = (10000 - ((q1 & 0x7F) * 25));
		3226	else
		3227	q1_cal = (10000 + (q1 * 25));
		3228	if (q1_cal > 0)
		3229	z_val = ((z_val) * 10000) / q1_cal;
		3230	}
		3231
		3232	static void wcd938x_wcd_mbhc_calc_impedance(struct snd_soc_component *component,
		3233	uint32_t zl, uint32_t zr)
		3234	{
		3235	struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
		3236	s16 reg0, reg1, reg2, reg3, reg4;
		3237	int32_t z1L, z1R, z1Ls;
		3238	int zMono, z_diff1, z_diff2;
		3239	bool is_fsm_disable = false;
		3240	struct wcd938x_mbhc_zdet_param zdet_param[] = {
		3241	{4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */
		3242	{2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */
		3243	{1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */
		3244	{1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */
		3245	};
		3246	struct wcd938x_mbhc_zdet_param *zdet_param_ptr = NULL;
		3247	s16 d1_a[][4] = {
		3248	{0, 30, 90, 30},
		3249	{0, 30, 30, 5},
		3250	{0, 30, 30, 5},
		3251	{0, 30, 30, 5},
		3252	};
		3253	s16 *d1 = NULL;
		3254
		3255	reg0 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN5);
		3256	reg1 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN6);
		3257	reg2 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN7);
		3258	reg3 = snd_soc_component_read(component, WCD938X_MBHC_CTL_CLK);
		3259	reg4 = snd_soc_component_read(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL);
		3260
		3261	if (snd_soc_component_read(component, WCD938X_ANA_MBHC_ELECT) & 0x80) {
		3262	is_fsm_disable = true;
		3263	regmap_update_bits(wcd938x->regmap,
		3264	WCD938X_ANA_MBHC_ELECT, 0x80, 0x00);
		3265	}
		3266
		3267	/* For NO-jack, disable L_DET_EN before Z-det measurements */
		3268	if (wcd938x->mbhc_cfg.hphl_swh)
		3269	regmap_update_bits(wcd938x->regmap,
		3270	WCD938X_ANA_MBHC_MECH, 0x80, 0x00);
		3271
		3272	/* Turn off 100k pull down on HPHL */
		3273	regmap_update_bits(wcd938x->regmap,
		3274	WCD938X_ANA_MBHC_MECH, 0x01, 0x00);
		3275
		3276	/* Disable surge protection before impedance detection.
		3277	* This is done to give correct value for high impedance.
		3278	*/
		3279	regmap_update_bits(wcd938x->regmap,
		3280	WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00);
		3281	/* 1ms delay needed after disable surge protection */
		3282	usleep_range(1000, 1010);
		3283
		3284	/* First get impedance on Left */
		3285	d1 = d1_a[1];
		3286	zdet_param_ptr = &zdet_param[1];
		3287	wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
		3288
		3289	if (!WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L))
		3290	goto left_ch_impedance;
		3291
		3292	/* Second ramp for left ch */
		3293	if (z1L < WCD938X_ZDET_VAL_32) {
		3294	zdet_param_ptr = &zdet_param[0];
		3295	d1 = d1_a[0];
		3296	} else if ((z1L > WCD938X_ZDET_VAL_400) &&
		3297	(z1L <= WCD938X_ZDET_VAL_1200)) {
		3298	zdet_param_ptr = &zdet_param[2];
		3299	d1 = d1_a[2];
		3300	} else if (z1L > WCD938X_ZDET_VAL_1200) {
		3301	zdet_param_ptr = &zdet_param[3];
		3302	d1 = d1_a[3];
		3303	}
		3304	wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
		3305
		3306	left_ch_impedance:
		3307	if ((z1L == WCD938X_ZDET_FLOATING_IMPEDANCE) \|\|
		3308	(z1L > WCD938X_ZDET_VAL_100K)) {
		3309	*zl = WCD938X_ZDET_FLOATING_IMPEDANCE;
		3310	zdet_param_ptr = &zdet_param[1];
		3311	d1 = d1_a[1];
		3312	} else {
		3313	*zl = z1L/1000;
		3314	wcd938x_wcd_mbhc_qfuse_cal(component, zl, 0);
		3315	}
		3316	dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n",
		3317	__func__, *zl);
		3318
		3319	/* Start of right impedance ramp and calculation */
		3320	wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
		3321	if (WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) {
		3322	if (((z1R > WCD938X_ZDET_VAL_1200) &&
		3323	(zdet_param_ptr->noff == 0x6)) \|\|
		3324	((*zl) != WCD938X_ZDET_FLOATING_IMPEDANCE))
		3325	goto right_ch_impedance;
		3326	/* Second ramp for right ch */
		3327	if (z1R < WCD938X_ZDET_VAL_32) {
		3328	zdet_param_ptr = &zdet_param[0];
		3329	d1 = d1_a[0];
		3330	} else if ((z1R > WCD938X_ZDET_VAL_400) &&
		3331	(z1R <= WCD938X_ZDET_VAL_1200)) {
		3332	zdet_param_ptr = &zdet_param[2];
		3333	d1 = d1_a[2];
		3334	} else if (z1R > WCD938X_ZDET_VAL_1200) {
		3335	zdet_param_ptr = &zdet_param[3];
		3336	d1 = d1_a[3];
		3337	}
		3338	wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
		3339	}
		3340	right_ch_impedance:
		3341	if ((z1R == WCD938X_ZDET_FLOATING_IMPEDANCE) \|\|
		3342	(z1R > WCD938X_ZDET_VAL_100K)) {
		3343	*zr = WCD938X_ZDET_FLOATING_IMPEDANCE;
		3344	} else {
		3345	*zr = z1R/1000;
		3346	wcd938x_wcd_mbhc_qfuse_cal(component, zr, 1);
		3347	}
		3348	dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n",
		3349	__func__, *zr);
		3350
		3351	/* Mono/stereo detection */
		3352	if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) &&
		3353	(*zr == WCD938X_ZDET_FLOATING_IMPEDANCE)) {
		3354	dev_dbg(component->dev,
		3355	"%s: plug type is invalid or extension cable\n",
		3356	__func__);
		3357	goto zdet_complete;
		3358	}
		3359	if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) \|\|
		3360	(*zr == WCD938X_ZDET_FLOATING_IMPEDANCE) \|\|
		3361	((zl < WCD_MONO_HS_MIN_THR) && (zr > WCD_MONO_HS_MIN_THR)) \|\|
		3362	((zl > WCD_MONO_HS_MIN_THR) && (zr < WCD_MONO_HS_MIN_THR))) {
		3363	dev_dbg(component->dev,
		3364	"%s: Mono plug type with one ch floating or shorted to GND\n",
		3365	__func__);
		3366	wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO);
		3367	goto zdet_complete;
		3368	}
		3369	snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST,
		3370	WCD938X_HPHPA_GND_OVR_MASK, 1);
		3371	snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
		3372	WCD938X_HPHPA_GND_R_MASK, 1);
		3373	if (*zl < (WCD938X_ZDET_VAL_32/1000))
		3374	wcd938x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1);
		3375	else
		3376	wcd938x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1);
		3377	snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
		3378	WCD938X_HPHPA_GND_R_MASK, 0);
		3379	snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST,
		3380	WCD938X_HPHPA_GND_OVR_MASK, 0);
		3381	z1Ls /= 1000;
		3382	wcd938x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0);
		3383	/* Parallel of left Z and 9 ohm pull down resistor */
		3384	zMono = ((zl) 9) / ((*zl) + 9);
		3385	z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls);
		3386	z_diff2 = ((zl) > z1Ls) ? ((zl) - z1Ls) : (z1Ls - (*zl));
		3387	if ((z_diff1 * (zl + z1Ls)) > (z_diff2 (z1Ls + zMono))) {
		3388	dev_dbg(component->dev, "%s: stereo plug type detected\n",
		3389	__func__);
		3390	wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_STEREO);
		3391	} else {
		3392	dev_dbg(component->dev, "%s: MONO plug type detected\n",
		3393	__func__);
		3394	wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO);
		3395	}
		3396
		3397	/* Enable surge protection again after impedance detection */
		3398	regmap_update_bits(wcd938x->regmap,
		3399	WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
		3400	zdet_complete:
		3401	snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN5, reg0);
		3402	snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN6, reg1);
		3403	snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN7, reg2);
		3404	/* Turn on 100k pull down on HPHL */
		3405	regmap_update_bits(wcd938x->regmap,
		3406	WCD938X_ANA_MBHC_MECH, 0x01, 0x01);
		3407
		3408	/* For NO-jack, re-enable L_DET_EN after Z-det measurements */
		3409	if (wcd938x->mbhc_cfg.hphl_swh)
		3410	regmap_update_bits(wcd938x->regmap,
		3411	WCD938X_ANA_MBHC_MECH, 0x80, 0x80);
		3412
		3413	snd_soc_component_write(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, reg4);
		3414	snd_soc_component_write(component, WCD938X_MBHC_CTL_CLK, reg3);
		3415	if (is_fsm_disable)
		3416	regmap_update_bits(wcd938x->regmap,
		3417	WCD938X_ANA_MBHC_ELECT, 0x80, 0x80);
		3418	}
		3419
		3420	static void wcd938x_mbhc_gnd_det_ctrl(struct snd_soc_component *component,
		3421	bool enable)
		3422	{
		3423	if (enable) {
		3424	snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
		3425	WCD938X_MBHC_HSG_PULLUP_COMP_EN, 1);
		3426	snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
		3427	WCD938X_MBHC_GND_DET_EN_MASK, 1);
		3428	} else {
		3429	snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
		3430	WCD938X_MBHC_GND_DET_EN_MASK, 0);
		3431	snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
		3432	WCD938X_MBHC_HSG_PULLUP_COMP_EN, 0);
		3433	}
		3434	}
		3435
		3436	static void wcd938x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component,
		3437	bool enable)
		3438	{
		3439	snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
		3440	WCD938X_HPHPA_GND_R_MASK, enable);
		3441	snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
		3442	WCD938X_HPHPA_GND_L_MASK, enable);
		3443	}
		3444
		3445	static void wcd938x_mbhc_moisture_config(struct snd_soc_component *component)
		3446	{
		3447	struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
		3448
		3449	if (wcd938x->mbhc_cfg.moist_rref == R_OFF) {
		3450	snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
		3451	WCD938X_M_RTH_CTL_MASK, R_OFF);
		3452	return;
		3453	}
		3454
		3455	/* Do not enable moisture detection if jack type is NC */
		3456	if (!wcd938x->mbhc_cfg.hphl_swh) {
		3457	dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
		3458	__func__);
		3459	snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
		3460	WCD938X_M_RTH_CTL_MASK, R_OFF);
		3461	return;
		3462	}
		3463
		3464	snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
		3465	WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref);
		3466	}
		3467
		3468	static void wcd938x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable)
		3469	{
		3470	struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
		3471
		3472	if (enable)
		3473	snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
		3474	WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref);
		3475	else
		3476	snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
		3477	WCD938X_M_RTH_CTL_MASK, R_OFF);
		3478	}
		3479
		3480	static bool wcd938x_mbhc_get_moisture_status(struct snd_soc_component *component)
		3481	{
		3482	struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
		3483	bool ret = false;
		3484
		3485	if (wcd938x->mbhc_cfg.moist_rref == R_OFF) {
		3486	snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
		3487	WCD938X_M_RTH_CTL_MASK, R_OFF);
		3488	goto done;
		3489	}
		3490
		3491	/* Do not enable moisture detection if jack type is NC */
		3492	if (!wcd938x->mbhc_cfg.hphl_swh) {
		3493	dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
		3494	__func__);
		3495	snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
		3496	WCD938X_M_RTH_CTL_MASK, R_OFF);
		3497	goto done;
		3498	}
		3499
		3500	/*
		3501	* If moisture_en is already enabled, then skip to plug type
		3502	* detection.
		3503	*/
		3504	if (snd_soc_component_read_field(component, WCD938X_MBHC_NEW_CTL_2, WCD938X_M_RTH_CTL_MASK))
		3505	goto done;
		3506
		3507	wcd938x_mbhc_moisture_detect_en(component, true);
		3508	/* Read moisture comparator status */
		3509	ret = ((snd_soc_component_read(component, WCD938X_MBHC_NEW_FSM_STATUS)
		3510	& 0x20) ? 0 : 1);
		3511
		3512	done:
		3513	return ret;
		3514
		3515	}
		3516
		3517	static void wcd938x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component,
		3518	bool enable)
		3519	{
		3520	snd_soc_component_write_field(component,
		3521	WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL,
		3522	WCD938X_MOISTURE_EN_POLLING_MASK, enable);
		3523	}
		3524
		3525	static const struct wcd_mbhc_cb mbhc_cb = {
		3526	.clk_setup = wcd938x_mbhc_clk_setup,
		3527	.mbhc_bias = wcd938x_mbhc_mbhc_bias_control,
		3528	.set_btn_thr = wcd938x_mbhc_program_btn_thr,
		3529	.micbias_enable_status = wcd938x_mbhc_micb_en_status,
		3530	.hph_pull_up_control_v2 = wcd938x_mbhc_hph_l_pull_up_control,
		3531	.mbhc_micbias_control = wcd938x_mbhc_request_micbias,
		3532	.mbhc_micb_ramp_control = wcd938x_mbhc_micb_ramp_control,
		3533	.mbhc_micb_ctrl_thr_mic = wcd938x_mbhc_micb_ctrl_threshold_mic,
		3534	.compute_impedance = wcd938x_wcd_mbhc_calc_impedance,
		3535	.mbhc_gnd_det_ctrl = wcd938x_mbhc_gnd_det_ctrl,
		3536	.hph_pull_down_ctrl = wcd938x_mbhc_hph_pull_down_ctrl,
		3537	.mbhc_moisture_config = wcd938x_mbhc_moisture_config,
		3538	.mbhc_get_moisture_status = wcd938x_mbhc_get_moisture_status,
		3539	.mbhc_moisture_polling_ctrl = wcd938x_mbhc_moisture_polling_ctrl,
		3540	.mbhc_moisture_detect_en = wcd938x_mbhc_moisture_detect_en,
		3541	};
		3542
		3543	static int wcd938x_get_hph_type(struct snd_kcontrol *kcontrol,
		3544	struct snd_ctl_elem_value *ucontrol)
		3545	{
		3546	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
		3547	struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
		3548
		3549	ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd938x->wcd_mbhc);
		3550
		3551	return 0;
		3552	}
		3553
		3554	static int wcd938x_hph_impedance_get(struct snd_kcontrol *kcontrol,
		3555	struct snd_ctl_elem_value *ucontrol)
		3556	{
		3557	uint32_t zl, zr;
		3558	bool hphr;
		3559	struct soc_mixer_control *mc;
		3560	struct snd_soc_component *component =
		3561	snd_soc_kcontrol_component(kcontrol);
		3562	struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
		3563
		3564	mc = (struct soc_mixer_control *)(kcontrol->private_value);
		3565	hphr = mc->shift;
		3566	wcd_mbhc_get_impedance(wcd938x->wcd_mbhc, &zl, &zr);
		3567	dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr);
		3568	ucontrol->value.integer.value[0] = hphr ? zr : zl;
		3569
		3570	return 0;
		3571	}
		3572
		3573	static const struct snd_kcontrol_new hph_type_detect_controls[] = {
		3574	SOC_SINGLE_EXT("HPH Type", 0, 0, UINT_MAX, 0,
		3575	wcd938x_get_hph_type, NULL),
		3576	};
		3577
		3578	static const struct snd_kcontrol_new impedance_detect_controls[] = {
		3579	SOC_SINGLE_EXT("HPHL Impedance", 0, 0, UINT_MAX, 0,
		3580	wcd938x_hph_impedance_get, NULL),
		3581	SOC_SINGLE_EXT("HPHR Impedance", 0, 1, UINT_MAX, 0,
		3582	wcd938x_hph_impedance_get, NULL),
		3583	};
		3584
		3585	static int wcd938x_mbhc_init(struct snd_soc_component *component)
		3586	{
		3587	struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
		3588	struct wcd_mbhc_intr *intr_ids = &wcd938x->intr_ids;
		3589
		3590	intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd938x->irq_chip,
		3591	WCD938X_IRQ_MBHC_SW_DET);
		3592	intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd938x->irq_chip,
		3593	WCD938X_IRQ_MBHC_BUTTON_PRESS_DET);
		3594	intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd938x->irq_chip,
		3595	WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET);
		3596	intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd938x->irq_chip,
		3597	WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET);
		3598	intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd938x->irq_chip,
		3599	WCD938X_IRQ_MBHC_ELECT_INS_REM_DET);
		3600	intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd938x->irq_chip,
		3601	WCD938X_IRQ_HPHL_OCP_INT);
		3602	intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd938x->irq_chip,
		3603	WCD938X_IRQ_HPHR_OCP_INT);
		3604
		3605	wcd938x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true);
		3606
		3607	snd_soc_add_component_controls(component, impedance_detect_controls,
		3608	ARRAY_SIZE(impedance_detect_controls));
		3609	snd_soc_add_component_controls(component, hph_type_detect_controls,
		3610	ARRAY_SIZE(hph_type_detect_controls));
		3611
		3612	return 0;
		3613	}
		3614	/* END MBHC */
		3615
2848	static const struct snd_kcontrol_new wcd938x_snd_controls[] = {	3616	static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
2849	SOC_SINGLE_EXT("HPHL_COMP Switch", WCD938X_COMP_L, 0, 1, 0,	3617	SOC_SINGLE_EXT("HPHL_COMP Switch", WCD938X_COMP_L, 0, 1, 0,
2850	wcd938x_get_compander, wcd938x_set_compander),	3618	wcd938x_get_compander, wcd938x_set_compander),
@@ -3225,15 +3993,6 @@ static const struct snd_soc_dapm_route wcd938x_audio_map[] = { · 374 unmodified lines
3225	{"EAR", NULL, "EAR PGA"},	3993	{"EAR", NULL, "EAR PGA"},
3226	};	3994	};
3227		3995
3228	static int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
3229	{
3230	/* min micbias voltage is 1V and maximum is 2.85V */
3231	if (micb_mv < 1000 \|\| micb_mv > 2850)
3232	return -EINVAL;
3233
3234	return (micb_mv - 1000) / 50;
3235	}
3236
3237	static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x)	3996	static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x)
3238	{	3997	{
3239	int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;	3998	int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
@@ -3372,10 +4131,27 @@ static int wcd938x_soc_codec_probe(struct snd_soc_component *component) · 132 unmodified lines
3372	default:	4131	default:
3373	break;	4132	break;
3374	}	4133	}
		4134
		4135	ret = wcd938x_mbhc_init(component);
		4136	if (ret)
		4137	dev_err(component->dev, "mbhc initialization failed\n");
3375	err:	4138	err:
3376	return ret;	4139	return ret;
3377	}	4140	}
3378		4141
		4142	static int wcd938x_codec_set_jack(struct snd_soc_component *comp,
		4143	struct snd_soc_jack jack, void data)
		4144	{
		4145	struct wcd938x_priv *wcd = dev_get_drvdata(comp->dev);
		4146
		4147	if (!jack)
		4148	return wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack);
		4149
		4150	wcd_mbhc_stop(wcd->wcd_mbhc);
		4151
		4152	return 0;
		4153	}
		4154
3379	static const struct snd_soc_component_driver soc_codec_dev_wcd938x = {	4155	static const struct snd_soc_component_driver soc_codec_dev_wcd938x = {
3380	.name = "wcd938x_codec",	4156	.name = "wcd938x_codec",
3381	.probe = wcd938x_soc_codec_probe,	4157	.probe = wcd938x_soc_codec_probe,
@@ -3385,6 +4161,7 @@ static const struct snd_soc_component_driver soc_codec_dev_wcd938x = { · 3 unmodified lines
3385	.num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),	4161	.num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
3386	.dapm_routes = wcd938x_audio_map,	4162	.dapm_routes = wcd938x_audio_map,
3387	.num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),	4163	.num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
		4164	.set_jack = wcd938x_codec_set_jack,
3388	};	4165	};
3389		4166
3390	static void wcd938x_dt_parse_micbias_info(struct device dev, struct wcd938x_priv wcd)	4167	static void wcd938x_dt_parse_micbias_info(struct device dev, struct wcd938x_priv wcd)
@@ -3420,6 +4197,7 @@ static void wcd938x_dt_parse_micbias_info(struct device *dev, struct wcd938x_pri · 29 unmodified lines
3420		4197
3421	static int wcd938x_populate_dt_data(struct wcd938x_priv wcd938x, struct device dev)	4198	static int wcd938x_populate_dt_data(struct wcd938x_priv wcd938x, struct device dev)
3422	{	4199	{
		4200	struct wcd_mbhc_config *cfg = &wcd938x->mbhc_cfg;
3423	int ret;	4201	int ret;
3424		4202
3425	wcd938x->reset_gpio = of_get_named_gpio(dev->of_node, "reset-gpios", 0);	4203	wcd938x->reset_gpio = of_get_named_gpio(dev->of_node, "reset-gpios", 0);
@@ -3448,6 +4226,17 @@ static int wcd938x_populate_dt_data(struct wcd938x_priv *wcd938x, struct device · 22 unmodified lines
3448		4226
3449	wcd938x_dt_parse_micbias_info(dev, wcd938x);	4227	wcd938x_dt_parse_micbias_info(dev, wcd938x);
3450		4228
		4229	cfg->mbhc_micbias = MIC_BIAS_2;
		4230	cfg->anc_micbias = MIC_BIAS_2;
		4231	cfg->v_hs_max = WCD_MBHC_HS_V_MAX;
		4232	cfg->num_btn = WCD938X_MBHC_MAX_BUTTONS;
		4233	cfg->micb_mv = wcd938x->micb2_mv;
		4234	cfg->linein_th = 5000;
		4235	cfg->hs_thr = 1700;
		4236	cfg->hph_thr = 50;
		4237
		4238	wcd_dt_parse_mbhc_data(dev, cfg);
		4239
3451	return 0;	4240	return 0;
3452	}	4241	}
3453		4242
@@ -3679,6 +4468,7 @@ static int wcd938x_probe(struct platform_device *pdev) · 225 unmodified lines
3679	return -ENOMEM;	4468	return -ENOMEM;
3680		4469
3681	dev_set_drvdata(dev, wcd938x);	4470	dev_set_drvdata(dev, wcd938x);
		4471	mutex_init(&wcd938x->micb_lock);
3682		4472
3683	ret = wcd938x_populate_dt_data(wcd938x, dev);	4473	ret = wcd938x_populate_dt_data(wcd938x, dev);
3684	if (ret) {	4474	if (ret) {
@@ -3703,7 +4493,7 @@ static int wcd938x_probe(struct platform_device *pdev) · 18 unmodified lines
3703	pm_runtime_enable(dev);	4493	pm_runtime_enable(dev);
3704	pm_runtime_idle(dev);	4494	pm_runtime_idle(dev);
3705		4495
3706	return ret;	4496	return 0;
3707	}	4497	}
3708		4498
3709	static int wcd938x_remove(struct platform_device *pdev)	4499	static int wcd938x_remove(struct platform_device *pdev)

sound/soc/codecs/wcd938x.h+0−1

@@ -658,7 +658,6 @@ struct wcd938x_sdw_priv { · 657 unmodified lines
658	struct sdw_port_config port_config[WCD938X_MAX_SWR_PORTS];	658	struct sdw_port_config port_config[WCD938X_MAX_SWR_PORTS];
659	struct wcd938x_sdw_ch_info *ch_info;	659	struct wcd938x_sdw_ch_info *ch_info;
660	bool port_enable[WCD938X_MAX_SWR_CH_IDS];	660	bool port_enable[WCD938X_MAX_SWR_CH_IDS];
661	int port_map[WCD938X_MAX_SWR_PORTS];
662	int active_ports;	661	int active_ports;
663	int num_ports;	662	int num_ports;
664	bool is_tx;	663	bool is_tx;

sound/soc/codecs/wm_adsp.c+3−4

 		if (!pos->subname)
 			continue;
 		if (strncmp(pos->subname, name, pos->subname_len) == 0 &&
-		    strncmp(pos->fw_name, fw_txt,
+		    pos->fw_name == fw_txt &&
-			    SNDRV_CTL_ELEM_ID_NAME_MAXLEN) == 0 &&
+		    pos->alg_region.alg == alg &&
-				pos->alg_region.alg == alg &&
+		    pos->alg_region.type == type) {
-				pos->alg_region.type == type) {
 			rslt = pos;
 			break;
 		}

sound/soc/dwc/dwc-i2s.c+1−1

@@ -642,7 +642,7 @@ static int dw_i2s_probe(struct platform_device *pdev) · 641 unmodified lines
642		642
643	dev->dev = &pdev->dev;	643	dev->dev = &pdev->dev;
644		644
645	irq = platform_get_irq(pdev, 0);	645	irq = platform_get_irq_optional(pdev, 0);
646	if (irq >= 0) {	646	if (irq >= 0) {
647	ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0,	647	ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0,
648	pdev->name, dev);	648	pdev->name, dev);

sound/soc/fsl/fsl_rpmsg.c+10−10

@@ -165,25 +165,25 @@ static int fsl_rpmsg_probe(struct platform_device *pdev) · 164 unmodified lines
165	}	165	}
166		166
167	/* Get the optional clocks */	167	/* Get the optional clocks */
168	rpmsg->ipg = devm_clk_get(&pdev->dev, "ipg");	168	rpmsg->ipg = devm_clk_get_optional(&pdev->dev, "ipg");
169	if (IS_ERR(rpmsg->ipg))	169	if (IS_ERR(rpmsg->ipg))
170	rpmsg->ipg = NULL;	170	return PTR_ERR(rpmsg->ipg);
171		171
172	rpmsg->mclk = devm_clk_get(&pdev->dev, "mclk");	172	rpmsg->mclk = devm_clk_get_optional(&pdev->dev, "mclk");
173	if (IS_ERR(rpmsg->mclk))	173	if (IS_ERR(rpmsg->mclk))
174	rpmsg->mclk = NULL;	174	return PTR_ERR(rpmsg->mclk);
175		175
176	rpmsg->dma = devm_clk_get(&pdev->dev, "dma");	176	rpmsg->dma = devm_clk_get_optional(&pdev->dev, "dma");
177	if (IS_ERR(rpmsg->dma))	177	if (IS_ERR(rpmsg->dma))
178	rpmsg->dma = NULL;	178	return PTR_ERR(rpmsg->dma);
179		179
180	rpmsg->pll8k = devm_clk_get(&pdev->dev, "pll8k");	180	rpmsg->pll8k = devm_clk_get_optional(&pdev->dev, "pll8k");
181	if (IS_ERR(rpmsg->pll8k))	181	if (IS_ERR(rpmsg->pll8k))
182	rpmsg->pll8k = NULL;	182	return PTR_ERR(rpmsg->pll8k);
183		183
184	rpmsg->pll11k = devm_clk_get(&pdev->dev, "pll11k");	184	rpmsg->pll11k = devm_clk_get_optional(&pdev->dev, "pll11k");
185	if (IS_ERR(rpmsg->pll11k))	185	if (IS_ERR(rpmsg->pll11k))
186	rpmsg->pll11k = NULL;	186	return PTR_ERR(rpmsg->pll11k);
187		187
188	platform_set_drvdata(pdev, rpmsg);	188	platform_set_drvdata(pdev, rpmsg);
189	pm_runtime_enable(&pdev->dev);	189	pm_runtime_enable(&pdev->dev);

sound/soc/fsl/fsl_xcvr.c+1−3

 	/* get IRQs */
 	irq = platform_get_irq(pdev, 0);
-	if (irq < 0) {
+	if (irq < 0)
-		dev_err(dev, "no irq[0]: %d\n", irq);
 		return irq;
-	}
 	ret = devm_request_irq(dev, irq, irq0_isr, 0, pdev->name, xcvr);
 	if (ret) {

sound/soc/fsl/imx-rpmsg.c+1−1

@@ -125,7 +125,7 @@ static int imx_rpmsg_probe(struct platform_device *pdev) · 124 unmodified lines
125	snd_soc_card_set_drvdata(&data->card, data);	125	snd_soc_card_set_drvdata(&data->card, data);
126	ret = devm_snd_soc_register_card(&pdev->dev, &data->card);	126	ret = devm_snd_soc_register_card(&pdev->dev, &data->card);
127	if (ret) {	127	if (ret) {
128	dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);	128	dev_err_probe(&pdev->dev, ret, "snd_soc_register_card failed\n");
129	goto fail;	129	goto fail;
130	}	130	}
131		131

sound/soc/generic/simple-card-utils.c+2−2

@@ -640,8 +640,8 @@ int asoc_simple_init_priv(struct asoc_simple_priv *priv, · 639 unmodified lines
640	cnf_num += li->num[i].codecs;	640	cnf_num += li->num[i].codecs;
641	}	641	}
642		642
643	dais = devm_kcalloc(dev, dai_num, sizeof(*dais), GFP_KERNEL);	643	dais = devm_kcalloc(dev, dai_num, sizeof(*dais), GFP_KERNEL);
644	dlcs = devm_kcalloc(dev, dlc_num, sizeof(*dai_props), GFP_KERNEL);	644	dlcs = devm_kcalloc(dev, dlc_num, sizeof(*dlcs), GFP_KERNEL);
645	if (!dais \|\| !dlcs)	645	if (!dais \|\| !dlcs)
646	return -ENOMEM;	646	return -ENOMEM;
647		647

sound/soc/intel/atom/sst/sst_ipc.c+1−1

@@ -128,7 +128,7 @@ int sst_post_message_mrfld(struct intel_sst_drv *sst_drv_ctx, · 127 unmodified lines
128	while (header.p.header_high.part.busy) {	128	while (header.p.header_high.part.busy) {
129	if (loop_count > 25) {	129	if (loop_count > 25) {
130	dev_err(sst_drv_ctx->dev,	130	dev_err(sst_drv_ctx->dev,
131	"sst: Busy wait failed, cant send this msg\n");	131	"sst: Busy wait failed, can't send this msg\n");
132	retval = -EBUSY;	132	retval = -EBUSY;
133	goto out;	133	goto out;
134	}	134	}

sound/soc/intel/boards/Kconfig+1−0

@@ -602,6 +602,7 @@ config SND_SOC_INTEL_SOUNDWIRE_SOF_MACH · 601 unmodified lines
602	select SND_SOC_DMIC	602	select SND_SOC_DMIC
603	select SND_SOC_INTEL_HDA_DSP_COMMON	603	select SND_SOC_INTEL_HDA_DSP_COMMON
604	select SND_SOC_INTEL_SOF_MAXIM_COMMON	604	select SND_SOC_INTEL_SOF_MAXIM_COMMON
		605	select SND_SOC_SDW_MOCKUP
605	help	606	help
606	Add support for Intel SoundWire-based platforms connected to	607	Add support for Intel SoundWire-based platforms connected to
607	MAX98373, RT700, RT711, RT1308 and RT715	608	MAX98373, RT700, RT711, RT1308 and RT715

sound/soc/intel/boards/bytcht_es8316.c+26−5

 	struct clk *mclk;
 	struct snd_soc_jack jack;
 	struct gpio_desc *speaker_en_gpio;
+	struct device *codec_dev;
 	bool speaker_en;
 };
 	const struct dmi_system_id *dmi_id;
 	struct device *dev = &pdev->dev;
 	struct snd_soc_acpi_mach *mach;
+	struct fwnode_handle *fwnode;
 	const char *platform_name;
 	struct acpi_device *adev;
 	struct device *codec_dev;
 			 "i2c-%s", acpi_dev_name(adev));
 		put_device(&adev->dev);
 		byt_cht_es8316_dais[dai_index].codecs->name = codec_name;
+	} else {
+		dev_err(&pdev->dev, "Error cannot find '%s' dev\n", mach->id);
+		return -ENXIO;
 	}
 	/* override plaform name, if required */
 	}
 	/* get speaker enable GPIO */
-	codec_dev = bus_find_device_by_name(&i2c_bus_type, NULL, codec_name);
+	codec_dev = acpi_get_first_physical_node(adev);
 	if (!codec_dev)
 		return -EPROBE_DEFER;
+	priv->codec_dev = get_device(codec_dev);
 	if (quirk & BYT_CHT_ES8316_JD_INVERTED)
 		props[cnt++] = PROPERTY_ENTRY_BOOL("everest,jack-detect-inverted");
 	if (cnt) {
-		ret = device_add_properties(codec_dev, props);
+		fwnode = fwnode_create_software_node(props, NULL);
+		if (IS_ERR(fwnode)) {
+			put_device(codec_dev);
+			return PTR_ERR(fwnode);
+		}
+		ret = device_add_software_node(codec_dev, to_software_node(fwnode));
+		fwnode_handle_put(fwnode);
 		if (ret) {
 			put_device(codec_dev);
 			return ret;
 		gpiod_get_index(codec_dev, "speaker-enable", 0,
 				/* see comment in byt_cht_es8316_resume */
 				GPIOD_OUT_LOW | GPIOD_FLAGS_BIT_NONEXCLUSIVE);
-	put_device(codec_dev);
 	if (IS_ERR(priv->speaker_en_gpio)) {
 		ret = PTR_ERR(priv->speaker_en_gpio);
 			dev_err(dev, "get speaker GPIO failed: %d\n", ret);
 			fallthrough;
 		case -EPROBE_DEFER:
-			return ret;
+			goto err_put_codec;
 		}
 	}
 	if (ret) {
 		gpiod_put(priv->speaker_en_gpio);
 		dev_err(dev, "snd_soc_register_card failed: %d\n", ret);
-		return ret;
+		goto err_put_codec;
 	}
 	platform_set_drvdata(pdev, &byt_cht_es8316_card);
 	return 0;
+err_put_codec:
+	device_remove_software_node(priv->codec_dev);
+	put_device(priv->codec_dev);
+	return ret;
 }
 static int snd_byt_cht_es8316_mc_remove(struct platform_device *pdev)
 	struct byt_cht_es8316_private *priv = snd_soc_card_get_drvdata(card);
 	gpiod_put(priv->speaker_en_gpio);
+	device_remove_software_node(priv->codec_dev);
+	put_device(priv->codec_dev);
 	return 0;
 }

sound/soc/intel/boards/bytcr_rt5640.c+298−30

@@ -18,6 +18,8 @@ · 17 unmodified lines
18	#include <linux/clk.h>	18	#include <linux/clk.h>
19	#include <linux/device.h>	19	#include <linux/device.h>
20	#include <linux/dmi.h>	20	#include <linux/dmi.h>
		21	#include <linux/gpio/consumer.h>
		22	#include <linux/gpio/machine.h>
21	#include <linux/input.h>	23	#include <linux/input.h>
22	#include <linux/slab.h>	24	#include <linux/slab.h>
23	#include <sound/pcm.h>	25	#include <sound/pcm.h>
@@ -73,6 +75,10 @@ enum { · 49 unmodified lines
73	#define BYT_RT5640_MCLK_EN BIT(22)	75	#define BYT_RT5640_MCLK_EN BIT(22)
74	#define BYT_RT5640_MCLK_25MHZ BIT(23)	76	#define BYT_RT5640_MCLK_25MHZ BIT(23)
75	#define BYT_RT5640_NO_SPEAKERS BIT(24)	77	#define BYT_RT5640_NO_SPEAKERS BIT(24)
		78	#define BYT_RT5640_LINEOUT BIT(25)
		79	#define BYT_RT5640_LINEOUT_AS_HP2 BIT(26)
		80	#define BYT_RT5640_HSMIC2_ON_IN1 BIT(27)
		81	#define BYT_RT5640_JD_HP_ELITEP_1000G2 BIT(28)
76		82
77	#define BYTCR_INPUT_DEFAULTS \	83	#define BYTCR_INPUT_DEFAULTS \
78	(BYT_RT5640_IN3_MAP \| \	84	(BYT_RT5640_IN3_MAP \| \
@@ -86,7 +92,10 @@ enum { · 7 unmodified lines
86		92
87	struct byt_rt5640_private {	93	struct byt_rt5640_private {
88	struct snd_soc_jack jack;	94	struct snd_soc_jack jack;
		95	struct snd_soc_jack jack2;
		96	struct gpio_desc *hsmic_detect;
89	struct clk *mclk;	97	struct clk *mclk;
		98	struct device *codec_dev;
90	};	99	};
91	static bool is_bytcr;	100	static bool is_bytcr;
92		101
@@ -125,6 +134,8 @@ static void log_quirks(struct device *dev) · 32 unmodified lines
125	dev_err(dev, "quirk map 0x%x is not supported, microphone input will not work\n", map);	134	dev_err(dev, "quirk map 0x%x is not supported, microphone input will not work\n", map);
126	break;	135	break;
127	}	136	}
		137	if (byt_rt5640_quirk & BYT_RT5640_HSMIC2_ON_IN1)
		138	dev_info(dev, "quirk HSMIC2_ON_IN1 enabled\n");
128	if (BYT_RT5640_JDSRC(byt_rt5640_quirk)) {	139	if (BYT_RT5640_JDSRC(byt_rt5640_quirk)) {
129	dev_info(dev, "quirk realtek,jack-detect-source %ld\n",	140	dev_info(dev, "quirk realtek,jack-detect-source %ld\n",
130	BYT_RT5640_JDSRC(byt_rt5640_quirk));	141	BYT_RT5640_JDSRC(byt_rt5640_quirk));
@@ -135,10 +146,16 @@ static void log_quirks(struct device *dev) · 4 unmodified lines
135	}	146	}
136	if (byt_rt5640_quirk & BYT_RT5640_JD_NOT_INV)	147	if (byt_rt5640_quirk & BYT_RT5640_JD_NOT_INV)
137	dev_info(dev, "quirk JD_NOT_INV enabled\n");	148	dev_info(dev, "quirk JD_NOT_INV enabled\n");
		149	if (byt_rt5640_quirk & BYT_RT5640_JD_HP_ELITEP_1000G2)
		150	dev_info(dev, "quirk JD_HP_ELITEPAD_1000G2 enabled\n");
138	if (byt_rt5640_quirk & BYT_RT5640_MONO_SPEAKER)	151	if (byt_rt5640_quirk & BYT_RT5640_MONO_SPEAKER)
139	dev_info(dev, "quirk MONO_SPEAKER enabled\n");	152	dev_info(dev, "quirk MONO_SPEAKER enabled\n");
140	if (byt_rt5640_quirk & BYT_RT5640_NO_SPEAKERS)	153	if (byt_rt5640_quirk & BYT_RT5640_NO_SPEAKERS)
141	dev_info(dev, "quirk NO_SPEAKERS enabled\n");	154	dev_info(dev, "quirk NO_SPEAKERS enabled\n");
		155	if (byt_rt5640_quirk & BYT_RT5640_LINEOUT)
		156	dev_info(dev, "quirk LINEOUT enabled\n");
		157	if (byt_rt5640_quirk & BYT_RT5640_LINEOUT_AS_HP2)
		158	dev_info(dev, "quirk LINEOUT_AS_HP2 enabled\n");
142	if (byt_rt5640_quirk & BYT_RT5640_DIFF_MIC)	159	if (byt_rt5640_quirk & BYT_RT5640_DIFF_MIC)
143	dev_info(dev, "quirk DIFF_MIC enabled\n");	160	dev_info(dev, "quirk DIFF_MIC enabled\n");
144	if (byt_rt5640_quirk & BYT_RT5640_SSP0_AIF1) {	161	if (byt_rt5640_quirk & BYT_RT5640_SSP0_AIF1) {
@@ -224,6 +241,20 @@ static int byt_rt5640_prepare_and_enable_pll1(struct snd_soc_dai *codec_dai, · 79 unmodified lines
224	#define BYT_CODEC_DAI1 "rt5640-aif1"	241	#define BYT_CODEC_DAI1 "rt5640-aif1"
225	#define BYT_CODEC_DAI2 "rt5640-aif2"	242	#define BYT_CODEC_DAI2 "rt5640-aif2"
226		243
		244	static struct snd_soc_dai byt_rt5640_get_codec_dai(struct snd_soc_dapm_context dapm)
		245	{
		246	struct snd_soc_card *card = dapm->card;
		247	struct snd_soc_dai *codec_dai;
		248
		249	codec_dai = snd_soc_card_get_codec_dai(card, BYT_CODEC_DAI1);
		250	if (!codec_dai)
		251	codec_dai = snd_soc_card_get_codec_dai(card, BYT_CODEC_DAI2);
		252	if (!codec_dai)
		253	dev_err(card->dev, "Error codec dai not found\n");
		254
		255	return codec_dai;
		256	}
		257
227	static int platform_clock_control(struct snd_soc_dapm_widget *w,	258	static int platform_clock_control(struct snd_soc_dapm_widget *w,
228	struct snd_kcontrol *k, int event)	259	struct snd_kcontrol *k, int event)
229	{	260	{
@@ -233,15 +264,9 @@ static int platform_clock_control(struct snd_soc_dapm_widget *w, · 3 unmodified lines
233	struct byt_rt5640_private *priv = snd_soc_card_get_drvdata(card);	264	struct byt_rt5640_private *priv = snd_soc_card_get_drvdata(card);
234	int ret;	265	int ret;
235		266
236	codec_dai = snd_soc_card_get_codec_dai(card, BYT_CODEC_DAI1);	267	codec_dai = byt_rt5640_get_codec_dai(dapm);
237	if (!codec_dai)	268	if (!codec_dai)
238	codec_dai = snd_soc_card_get_codec_dai(card, BYT_CODEC_DAI2);
239
240	if (!codec_dai) {
241	dev_err(card->dev,
242	"Codec dai not found; Unable to set platform clock\n");
243	return -EIO;	269	return -EIO;
244	}
245		270
246	if (SND_SOC_DAPM_EVENT_ON(event)) {	271	if (SND_SOC_DAPM_EVENT_ON(event)) {
247	if (byt_rt5640_quirk & BYT_RT5640_MCLK_EN) {	272	if (byt_rt5640_quirk & BYT_RT5640_MCLK_EN) {
@@ -276,23 +301,48 @@ static int platform_clock_control(struct snd_soc_dapm_widget *w, · 28 unmodified lines
276	return 0;	301	return 0;
277	}	302	}
278		303
		304	static int byt_rt5640_event_lineout(struct snd_soc_dapm_widget *w,
		305	struct snd_kcontrol *k, int event)
		306	{
		307	unsigned int gpio_ctrl3_val = RT5640_GP1_PF_OUT;
		308	struct snd_soc_dai *codec_dai;
		309
		310	if (!(byt_rt5640_quirk & BYT_RT5640_LINEOUT_AS_HP2))
		311	return 0;
		312
		313	/*
		314	* On devices which use line-out as a second headphones output,
		315	* the codec's GPIO1 pin is used to enable an external HP-amp.
		316	*/
		317
		318	codec_dai = byt_rt5640_get_codec_dai(w->dapm);
		319	if (!codec_dai)
		320	return -EIO;
		321
		322	if (SND_SOC_DAPM_EVENT_ON(event))
		323	gpio_ctrl3_val \|= RT5640_GP1_OUT_HI;
		324
		325	snd_soc_component_update_bits(codec_dai->component, RT5640_GPIO_CTRL3,
		326	RT5640_GP1_PF_MASK \| RT5640_GP1_OUT_MASK, gpio_ctrl3_val);
		327
		328	return 0;
		329	}
		330
279	static const struct snd_soc_dapm_widget byt_rt5640_widgets[] = {	331	static const struct snd_soc_dapm_widget byt_rt5640_widgets[] = {
280	SND_SOC_DAPM_HP("Headphone", NULL),	332	SND_SOC_DAPM_HP("Headphone", NULL),
281	SND_SOC_DAPM_MIC("Headset Mic", NULL),	333	SND_SOC_DAPM_MIC("Headset Mic", NULL),
		334	SND_SOC_DAPM_MIC("Headset Mic 2", NULL),
282	SND_SOC_DAPM_MIC("Internal Mic", NULL),	335	SND_SOC_DAPM_MIC("Internal Mic", NULL),
283	SND_SOC_DAPM_SPK("Speaker", NULL),	336	SND_SOC_DAPM_SPK("Speaker", NULL),
		337	SND_SOC_DAPM_LINE("Line Out", byt_rt5640_event_lineout),
284	SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0,	338	SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0,
285	platform_clock_control, SND_SOC_DAPM_PRE_PMU \|	339	platform_clock_control, SND_SOC_DAPM_PRE_PMU \|
286	SND_SOC_DAPM_POST_PMD),	340	SND_SOC_DAPM_POST_PMD),
287
288	};	341	};
289		342
290	static const struct snd_soc_dapm_route byt_rt5640_audio_map[] = {	343	static const struct snd_soc_dapm_route byt_rt5640_audio_map[] = {
291	{"Headphone", NULL, "Platform Clock"},	344	{"Headphone", NULL, "Platform Clock"},
292	{"Headset Mic", NULL, "Platform Clock"},	345	{"Headset Mic", NULL, "Platform Clock"},
293	{"Internal Mic", NULL, "Platform Clock"},
294	{"Speaker", NULL, "Platform Clock"},
295
296	{"Headset Mic", NULL, "MICBIAS1"},	346	{"Headset Mic", NULL, "MICBIAS1"},
297	{"IN2P", NULL, "Headset Mic"},	347	{"IN2P", NULL, "Headset Mic"},
298	{"Headphone", NULL, "HPOL"},	348	{"Headphone", NULL, "HPOL"},
@@ -300,23 +350,33 @@ static const struct snd_soc_dapm_route byt_rt5640_audio_map[] = { · 1 unmodified line
300	};	350	};
301		351
302	static const struct snd_soc_dapm_route byt_rt5640_intmic_dmic1_map[] = {	352	static const struct snd_soc_dapm_route byt_rt5640_intmic_dmic1_map[] = {
		353	{"Internal Mic", NULL, "Platform Clock"},
303	{"DMIC1", NULL, "Internal Mic"},	354	{"DMIC1", NULL, "Internal Mic"},
304	};	355	};
305		356
306	static const struct snd_soc_dapm_route byt_rt5640_intmic_dmic2_map[] = {	357	static const struct snd_soc_dapm_route byt_rt5640_intmic_dmic2_map[] = {
		358	{"Internal Mic", NULL, "Platform Clock"},
307	{"DMIC2", NULL, "Internal Mic"},	359	{"DMIC2", NULL, "Internal Mic"},
308	};	360	};
309		361
310	static const struct snd_soc_dapm_route byt_rt5640_intmic_in1_map[] = {	362	static const struct snd_soc_dapm_route byt_rt5640_intmic_in1_map[] = {
		363	{"Internal Mic", NULL, "Platform Clock"},
311	{"Internal Mic", NULL, "MICBIAS1"},	364	{"Internal Mic", NULL, "MICBIAS1"},
312	{"IN1P", NULL, "Internal Mic"},	365	{"IN1P", NULL, "Internal Mic"},
313	};	366	};
314		367
315	static const struct snd_soc_dapm_route byt_rt5640_intmic_in3_map[] = {	368	static const struct snd_soc_dapm_route byt_rt5640_intmic_in3_map[] = {
		369	{"Internal Mic", NULL, "Platform Clock"},
316	{"Internal Mic", NULL, "MICBIAS1"},	370	{"Internal Mic", NULL, "MICBIAS1"},
317	{"IN3P", NULL, "Internal Mic"},	371	{"IN3P", NULL, "Internal Mic"},
318	};	372	};
319		373
		374	static const struct snd_soc_dapm_route byt_rt5640_hsmic2_in1_map[] = {
		375	{"Headset Mic 2", NULL, "Platform Clock"},
		376	{"Headset Mic 2", NULL, "MICBIAS1"},
		377	{"IN1P", NULL, "Headset Mic 2"},
		378	};
		379
320	static const struct snd_soc_dapm_route byt_rt5640_ssp2_aif1_map[] = {	380	static const struct snd_soc_dapm_route byt_rt5640_ssp2_aif1_map[] = {
321	{"ssp2 Tx", NULL, "codec_out0"},	381	{"ssp2 Tx", NULL, "codec_out0"},
322	{"ssp2 Tx", NULL, "codec_out1"},	382	{"ssp2 Tx", NULL, "codec_out1"},
@@ -354,6 +414,7 @@ static const struct snd_soc_dapm_route byt_rt5640_ssp0_aif2_map[] = { · 31 unmodified lines
354	};	414	};
355		415
356	static const struct snd_soc_dapm_route byt_rt5640_stereo_spk_map[] = {	416	static const struct snd_soc_dapm_route byt_rt5640_stereo_spk_map[] = {
		417	{"Speaker", NULL, "Platform Clock"},
357	{"Speaker", NULL, "SPOLP"},	418	{"Speaker", NULL, "SPOLP"},
358	{"Speaker", NULL, "SPOLN"},	419	{"Speaker", NULL, "SPOLN"},
359	{"Speaker", NULL, "SPORP"},	420	{"Speaker", NULL, "SPORP"},
@@ -361,15 +422,24 @@ static const struct snd_soc_dapm_route byt_rt5640_stereo_spk_map[] = { · 1 unmodified line
361	};	422	};
362		423
363	static const struct snd_soc_dapm_route byt_rt5640_mono_spk_map[] = {	424	static const struct snd_soc_dapm_route byt_rt5640_mono_spk_map[] = {
		425	{"Speaker", NULL, "Platform Clock"},
364	{"Speaker", NULL, "SPOLP"},	426	{"Speaker", NULL, "SPOLP"},
365	{"Speaker", NULL, "SPOLN"},	427	{"Speaker", NULL, "SPOLN"},
366	};	428	};
367		429
		430	static const struct snd_soc_dapm_route byt_rt5640_lineout_map[] = {
		431	{"Line Out", NULL, "Platform Clock"},
		432	{"Line Out", NULL, "LOUTR"},
		433	{"Line Out", NULL, "LOUTL"},
		434	};
		435
368	static const struct snd_kcontrol_new byt_rt5640_controls[] = {	436	static const struct snd_kcontrol_new byt_rt5640_controls[] = {
369	SOC_DAPM_PIN_SWITCH("Headphone"),	437	SOC_DAPM_PIN_SWITCH("Headphone"),
370	SOC_DAPM_PIN_SWITCH("Headset Mic"),	438	SOC_DAPM_PIN_SWITCH("Headset Mic"),
		439	SOC_DAPM_PIN_SWITCH("Headset Mic 2"),
371	SOC_DAPM_PIN_SWITCH("Internal Mic"),	440	SOC_DAPM_PIN_SWITCH("Internal Mic"),
372	SOC_DAPM_PIN_SWITCH("Speaker"),	441	SOC_DAPM_PIN_SWITCH("Speaker"),
		442	SOC_DAPM_PIN_SWITCH("Line Out"),
373	};	443	};
374		444
375	static struct snd_soc_jack_pin rt5640_pins[] = {	445	static struct snd_soc_jack_pin rt5640_pins[] = {
@@ -383,6 +453,75 @@ static struct snd_soc_jack_pin rt5640_pins[] = { · 7 unmodified lines
383	},	453	},
384	};	454	};
385		455
		456	static struct snd_soc_jack_pin rt5640_pins2[] = {
		457	{
		458	/* The 2nd headset jack uses lineout with an external HP-amp */
		459	.pin = "Line Out",
		460	.mask = SND_JACK_HEADPHONE,
		461	},
		462	{
		463	.pin = "Headset Mic 2",
		464	.mask = SND_JACK_MICROPHONE,
		465	},
		466	};
		467
		468	static struct snd_soc_jack_gpio rt5640_jack_gpio = {
		469	.name = "hp-detect",
		470	.report = SND_JACK_HEADSET,
		471	.invert = true,
		472	.debounce_time = 200,
		473	};
		474
		475	static struct snd_soc_jack_gpio rt5640_jack2_gpio = {
		476	.name = "hp2-detect",
		477	.report = SND_JACK_HEADSET,
		478	.invert = true,
		479	.debounce_time = 200,
		480	};
		481
		482	static const struct acpi_gpio_params acpi_gpio0 = { 0, 0, false };
		483	static const struct acpi_gpio_params acpi_gpio1 = { 1, 0, false };
		484	static const struct acpi_gpio_params acpi_gpio2 = { 2, 0, false };
		485
		486	static const struct acpi_gpio_mapping byt_rt5640_hp_elitepad_1000g2_gpios[] = {
		487	{ "hp-detect-gpios", &acpi_gpio0, 1, },
		488	{ "headset-mic-detect-gpios", &acpi_gpio1, 1, },
		489	{ "hp2-detect-gpios", &acpi_gpio2, 1, },
		490	{ },
		491	};
		492
		493	static int byt_rt5640_hp_elitepad_1000g2_jack1_check(void *data)
		494	{
		495	struct byt_rt5640_private *priv = data;
		496	int jack_status, mic_status;
		497
		498	jack_status = gpiod_get_value_cansleep(rt5640_jack_gpio.desc);
		499	if (jack_status)
		500	return 0;
		501
		502	mic_status = gpiod_get_value_cansleep(priv->hsmic_detect);
		503	if (mic_status)
		504	return SND_JACK_HEADPHONE;
		505	else
		506	return SND_JACK_HEADSET;
		507	}
		508
		509	static int byt_rt5640_hp_elitepad_1000g2_jack2_check(void *data)
		510	{
		511	struct snd_soc_component *component = data;
		512	int jack_status, report;
		513
		514	jack_status = gpiod_get_value_cansleep(rt5640_jack2_gpio.desc);
		515	if (jack_status)
		516	return 0;
		517
		518	rt5640_enable_micbias1_for_ovcd(component);
		519	report = rt5640_detect_headset(component, rt5640_jack2_gpio.desc);
		520	rt5640_disable_micbias1_for_ovcd(component);
		521
		522	return report;
		523	}
		524
386	static int byt_rt5640_aif1_hw_params(struct snd_pcm_substream *substream,	525	static int byt_rt5640_aif1_hw_params(struct snd_pcm_substream *substream,
387	struct snd_pcm_hw_params *params)	526	struct snd_pcm_hw_params *params)
388	{	527	{
@@ -590,8 +729,12 @@ static const struct dmi_system_id byt_rt5640_quirk_table[] = { · 201 unmodified lines
590	DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),	729	DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
591	DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "HP ElitePad 1000 G2"),	730	DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "HP ElitePad 1000 G2"),
592	},	731	},
593	.driver_data = (void *)(BYT_RT5640_IN1_MAP \|	732	.driver_data = (void *)(BYT_RT5640_DMIC2_MAP \|
594	BYT_RT5640_MCLK_EN),	733	BYT_RT5640_MCLK_EN \|
		734	BYT_RT5640_LINEOUT \|
		735	BYT_RT5640_LINEOUT_AS_HP2 \|
		736	BYT_RT5640_HSMIC2_ON_IN1 \|
		737	BYT_RT5640_JD_HP_ELITEP_1000G2),
595	},	738	},
596	{ /* HP Pavilion x2 10-k0XX, 10-n0XX */	739	{ /* HP Pavilion x2 10-k0XX, 10-n0XX */
597	.matches = {	740	.matches = {
@@ -912,15 +1055,13 @@ static const struct dmi_system_id byt_rt5640_quirk_table[] = { · 314 unmodified lines
912	* Note this MUST be called before snd_soc_register_card(), so that the props	1055	* Note this MUST be called before snd_soc_register_card(), so that the props
913	* are in place before the codec component driver's probe function parses them.	1056	* are in place before the codec component driver's probe function parses them.
914	*/	1057	*/
915	static int byt_rt5640_add_codec_device_props(const char *i2c_dev_name)	1058	static int byt_rt5640_add_codec_device_props(struct device *i2c_dev,
		1059	struct byt_rt5640_private *priv)
916	{	1060	{
917	struct property_entry props[MAX_NO_PROPS] = {};	1061	struct property_entry props[MAX_NO_PROPS] = {};
918	struct device *i2c_dev;	1062	struct fwnode_handle *fwnode;
919	int ret, cnt = 0;	1063	int cnt = 0;
920		1064	int ret;
921	i2c_dev = bus_find_device_by_name(&i2c_bus_type, NULL, i2c_dev_name);
922	if (!i2c_dev)
923	return -EPROBE_DEFER;
924		1065
925	switch (BYT_RT5640_MAP(byt_rt5640_quirk)) {	1066	switch (BYT_RT5640_MAP(byt_rt5640_quirk)) {
926	case BYT_RT5640_DMIC1_MAP:	1067	case BYT_RT5640_DMIC1_MAP:
@@ -960,8 +1101,15 @@ static int byt_rt5640_add_codec_device_props(const char *i2c_dev_name) · 33 unmodified lines
960	if (byt_rt5640_quirk & BYT_RT5640_JD_NOT_INV)	1101	if (byt_rt5640_quirk & BYT_RT5640_JD_NOT_INV)
961	props[cnt++] = PROPERTY_ENTRY_BOOL("realtek,jack-detect-not-inverted");	1102	props[cnt++] = PROPERTY_ENTRY_BOOL("realtek,jack-detect-not-inverted");
962		1103
963	ret = device_add_properties(i2c_dev, props);	1104	fwnode = fwnode_create_software_node(props, NULL);
964	put_device(i2c_dev);	1105	if (IS_ERR(fwnode)) {
		1106	/* put_device() is handled in caller */
		1107	return PTR_ERR(fwnode);
		1108	}
		1109
		1110	ret = device_add_software_node(i2c_dev, to_software_node(fwnode));
		1111
		1112	fwnode_handle_put(fwnode);
965		1113
966	return ret;	1114	return ret;
967	}	1115	}
@@ -1021,6 +1169,14 @@ static int byt_rt5640_init(struct snd_soc_pcm_runtime *runtime) · 53 unmodified lines
1021	if (ret)	1169	if (ret)
1022	return ret;	1170	return ret;
1023		1171
		1172	if (byt_rt5640_quirk & BYT_RT5640_HSMIC2_ON_IN1) {
		1173	ret = snd_soc_dapm_add_routes(&card->dapm,
		1174	byt_rt5640_hsmic2_in1_map,
		1175	ARRAY_SIZE(byt_rt5640_hsmic2_in1_map));
		1176	if (ret)
		1177	return ret;
		1178	}
		1179
1024	if (byt_rt5640_quirk & BYT_RT5640_SSP2_AIF2) {	1180	if (byt_rt5640_quirk & BYT_RT5640_SSP2_AIF2) {
1025	ret = snd_soc_dapm_add_routes(&card->dapm,	1181	ret = snd_soc_dapm_add_routes(&card->dapm,
1026	byt_rt5640_ssp2_aif2_map,	1182	byt_rt5640_ssp2_aif2_map,
@@ -1053,6 +1209,14 @@ static int byt_rt5640_init(struct snd_soc_pcm_runtime *runtime) · 26 unmodified lines
1053	if (ret)	1209	if (ret)
1054	return ret;	1210	return ret;
1055		1211
		1212	if (byt_rt5640_quirk & BYT_RT5640_LINEOUT) {
		1213	ret = snd_soc_dapm_add_routes(&card->dapm,
		1214	byt_rt5640_lineout_map,
		1215	ARRAY_SIZE(byt_rt5640_lineout_map));
		1216	if (ret)
		1217	return ret;
		1218	}
		1219
1056	if (byt_rt5640_quirk & BYT_RT5640_MCLK_EN) {	1220	if (byt_rt5640_quirk & BYT_RT5640_MCLK_EN) {
1057	/*	1221	/*
1058	* The firmware might enable the clock at	1222	* The firmware might enable the clock at
@@ -1093,9 +1257,53 @@ static int byt_rt5640_init(struct snd_soc_pcm_runtime *runtime) · 34 unmodified lines
1093	snd_soc_component_set_jack(component, &priv->jack, NULL);	1257	snd_soc_component_set_jack(component, &priv->jack, NULL);
1094	}	1258	}
1095		1259
		1260	if (byt_rt5640_quirk & BYT_RT5640_JD_HP_ELITEP_1000G2) {
		1261	ret = snd_soc_card_jack_new(card, "Headset",
		1262	SND_JACK_HEADSET,
		1263	&priv->jack, rt5640_pins,
		1264	ARRAY_SIZE(rt5640_pins));
		1265	if (ret)
		1266	return ret;
		1267
		1268	ret = snd_soc_card_jack_new(card, "Headset 2",
		1269	SND_JACK_HEADSET,
		1270	&priv->jack2, rt5640_pins2,
		1271	ARRAY_SIZE(rt5640_pins2));
		1272	if (ret)
		1273	return ret;
		1274
		1275	rt5640_jack_gpio.data = priv;
		1276	rt5640_jack_gpio.gpiod_dev = priv->codec_dev;
		1277	rt5640_jack_gpio.jack_status_check = byt_rt5640_hp_elitepad_1000g2_jack1_check;
		1278	ret = snd_soc_jack_add_gpios(&priv->jack, 1, &rt5640_jack_gpio);
		1279	if (ret)
		1280	return ret;
		1281
		1282	rt5640_set_ovcd_params(component);
		1283	rt5640_jack2_gpio.data = component;
		1284	rt5640_jack2_gpio.gpiod_dev = priv->codec_dev;
		1285	rt5640_jack2_gpio.jack_status_check = byt_rt5640_hp_elitepad_1000g2_jack2_check;
		1286	ret = snd_soc_jack_add_gpios(&priv->jack2, 1, &rt5640_jack2_gpio);
		1287	if (ret) {
		1288	snd_soc_jack_free_gpios(&priv->jack, 1, &rt5640_jack_gpio);
		1289	return ret;
		1290	}
		1291	}
		1292
1096	return 0;	1293	return 0;
1097	}	1294	}
1098		1295
		1296	static void byt_rt5640_exit(struct snd_soc_pcm_runtime *runtime)
		1297	{
		1298	struct snd_soc_card *card = runtime->card;
		1299	struct byt_rt5640_private *priv = snd_soc_card_get_drvdata(card);
		1300
		1301	if (byt_rt5640_quirk & BYT_RT5640_JD_HP_ELITEP_1000G2) {
		1302	snd_soc_jack_free_gpios(&priv->jack2, 1, &rt5640_jack2_gpio);
		1303	snd_soc_jack_free_gpios(&priv->jack, 1, &rt5640_jack_gpio);
		1304	}
		1305	}
		1306
1099	static int byt_rt5640_codec_fixup(struct snd_soc_pcm_runtime *rtd,	1307	static int byt_rt5640_codec_fixup(struct snd_soc_pcm_runtime *rtd,
1100	struct snd_pcm_hw_params *params)	1308	struct snd_pcm_hw_params *params)
1101	{	1309	{
@@ -1208,6 +1416,7 @@ static struct snd_soc_dai_link byt_rt5640_dais[] = { · 106 unmodified lines
1208	.dpcm_playback = 1,	1416	.dpcm_playback = 1,
1209	.dpcm_capture = 1,	1417	.dpcm_capture = 1,
1210	.init = byt_rt5640_init,	1418	.init = byt_rt5640_init,
		1419	.exit = byt_rt5640_exit,
1211	.ops = &byt_rt5640_be_ssp2_ops,	1420	.ops = &byt_rt5640_be_ssp2_ops,
1212	SND_SOC_DAILINK_REG(ssp2_port, ssp2_codec, platform),	1421	SND_SOC_DAILINK_REG(ssp2_port, ssp2_codec, platform),
1213	},	1422	},
@@ -1218,7 +1427,7 @@ static char byt_rt5640_codec_name[SND_ACPI_I2C_ID_LEN]; · 4 unmodified lines
1218	#if !IS_ENABLED(CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES)	1427	#if !IS_ENABLED(CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES)
1219	static char byt_rt5640_long_name[40]; /* = "bytcr-rt5640--spk--mic" */	1428	static char byt_rt5640_long_name[40]; /* = "bytcr-rt5640--spk--mic" */
1220	#endif	1429	#endif
1221	static char byt_rt5640_components[32]; /* = "cfg-spk:* cfg-mic:" /	1430	static char byt_rt5640_components[64]; /* = "cfg-spk:* cfg-mic:* ..." */
1222		1431
1223	static int byt_rt5640_suspend(struct snd_soc_card *card)	1432	static int byt_rt5640_suspend(struct snd_soc_card *card)
1224	{	1433	{
@@ -1288,10 +1497,13 @@ static int snd_byt_rt5640_mc_probe(struct platform_device *pdev) · 63 unmodified lines
1288	static const char * const map_name[] = { "dmic1", "dmic2", "in1", "in3", "none" };	1497	static const char * const map_name[] = { "dmic1", "dmic2", "in1", "in3", "none" };
1289	__maybe_unused const char *spk_type;	1498	__maybe_unused const char *spk_type;
1290	const struct dmi_system_id *dmi_id;	1499	const struct dmi_system_id *dmi_id;
		1500	const char *headset2_string = "";
		1501	const char *lineout_string = "";
1291	struct byt_rt5640_private *priv;	1502	struct byt_rt5640_private *priv;
1292	struct snd_soc_acpi_mach *mach;	1503	struct snd_soc_acpi_mach *mach;
1293	const char *platform_name;	1504	const char *platform_name;
1294	struct acpi_device *adev;	1505	struct acpi_device *adev;
		1506	struct device *codec_dev;
1295	bool sof_parent;	1507	bool sof_parent;
1296	int ret_val = 0;	1508	int ret_val = 0;
1297	int dai_index = 0;	1509	int dai_index = 0;
@@ -1324,6 +1536,9 @@ static int snd_byt_rt5640_mc_probe(struct platform_device *pdev) · 26 unmodified lines
1324	"i2c-%s", acpi_dev_name(adev));	1536	"i2c-%s", acpi_dev_name(adev));
1325	put_device(&adev->dev);	1537	put_device(&adev->dev);
1326	byt_rt5640_dais[dai_index].codecs->name = byt_rt5640_codec_name;	1538	byt_rt5640_dais[dai_index].codecs->name = byt_rt5640_codec_name;
		1539	} else {
		1540	dev_err(&pdev->dev, "Error cannot find '%s' dev\n", mach->id);
		1541	return -ENXIO;
1327	}	1542	}
1328		1543
1329	/*	1544	/*
@@ -1400,10 +1615,29 @@ static int snd_byt_rt5640_mc_probe(struct platform_device *pdev) · 70 unmodified lines
1400	byt_rt5640_quirk = quirk_override;	1615	byt_rt5640_quirk = quirk_override;
1401	}	1616	}
1402		1617
		1618	codec_dev = acpi_get_first_physical_node(adev);
		1619	if (!codec_dev)
		1620	return -EPROBE_DEFER;
		1621	priv->codec_dev = get_device(codec_dev);
		1622
		1623	if (byt_rt5640_quirk & BYT_RT5640_JD_HP_ELITEP_1000G2) {
		1624	acpi_dev_add_driver_gpios(ACPI_COMPANION(priv->codec_dev),
		1625	byt_rt5640_hp_elitepad_1000g2_gpios);
		1626
		1627	priv->hsmic_detect = devm_fwnode_gpiod_get(&pdev->dev, codec_dev->fwnode,
		1628	"headset-mic-detect", GPIOD_IN,
		1629	"headset-mic-detect");
		1630	if (IS_ERR(priv->hsmic_detect)) {
		1631	ret_val = PTR_ERR(priv->hsmic_detect);
		1632	dev_err_probe(&pdev->dev, ret_val, "getting hsmic-detect GPIO\n");
		1633	goto err_device;
		1634	}
		1635	}
		1636
1403	/* Must be called before register_card, also see declaration comment. */	1637	/* Must be called before register_card, also see declaration comment. */
1404	ret_val = byt_rt5640_add_codec_device_props(byt_rt5640_codec_name);	1638	ret_val = byt_rt5640_add_codec_device_props(codec_dev, priv);
1405	if (ret_val)	1639	if (ret_val)
1406	return ret_val;	1640	goto err_remove_gpios;
1407		1641
1408	log_quirks(&pdev->dev);	1642	log_quirks(&pdev->dev);
1409		1643
@@ -1434,7 +1668,7 @@ static int snd_byt_rt5640_mc_probe(struct platform_device *pdev) · 24 unmodified lines
1434	* for all other errors, including -EPROBE_DEFER	1668	* for all other errors, including -EPROBE_DEFER
1435	*/	1669	*/
1436	if (ret_val != -ENOENT)	1670	if (ret_val != -ENOENT)
1437	return ret_val;	1671	goto err;
1438	byt_rt5640_quirk &= ~BYT_RT5640_MCLK_EN;	1672	byt_rt5640_quirk &= ~BYT_RT5640_MCLK_EN;
1439	}	1673	}
1440	}	1674	}
@@ -1450,9 +1684,20 @@ static int snd_byt_rt5640_mc_probe(struct platform_device *pdev) · 9 unmodified lines
1450	spk_type = "stereo";	1684	spk_type = "stereo";
1451	}	1685	}
1452		1686
		1687	if (byt_rt5640_quirk & BYT_RT5640_LINEOUT) {
		1688	if (byt_rt5640_quirk & BYT_RT5640_LINEOUT_AS_HP2)
		1689	lineout_string = " cfg-hp2:lineout";
		1690	else
		1691	lineout_string = " cfg-lineout:2";
		1692	}
		1693
		1694	if (byt_rt5640_quirk & BYT_RT5640_HSMIC2_ON_IN1)
		1695	headset2_string = " cfg-hs2:in1";
		1696
1453	snprintf(byt_rt5640_components, sizeof(byt_rt5640_components),	1697	snprintf(byt_rt5640_components, sizeof(byt_rt5640_components),
1454	"cfg-spk:%d cfg-mic:%s aif:%d", cfg_spk,	1698	"cfg-spk:%d cfg-mic:%s aif:%d%s%s", cfg_spk,
1455	map_name[BYT_RT5640_MAP(byt_rt5640_quirk)], aif);	1699	map_name[BYT_RT5640_MAP(byt_rt5640_quirk)], aif,
		1700	lineout_string, headset2_string);
1456	byt_rt5640_card.components = byt_rt5640_components;	1701	byt_rt5640_card.components = byt_rt5640_components;
1457	#if !IS_ENABLED(CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES)	1702	#if !IS_ENABLED(CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES)
1458	snprintf(byt_rt5640_long_name, sizeof(byt_rt5640_long_name),	1703	snprintf(byt_rt5640_long_name, sizeof(byt_rt5640_long_name),
@@ -1467,7 +1712,7 @@ static int snd_byt_rt5640_mc_probe(struct platform_device *pdev) · 8 unmodified lines
1467	ret_val = snd_soc_fixup_dai_links_platform_name(&byt_rt5640_card,	1712	ret_val = snd_soc_fixup_dai_links_platform_name(&byt_rt5640_card,
1468	platform_name);	1713	platform_name);
1469	if (ret_val)	1714	if (ret_val)
1470	return ret_val;	1715	goto err;
1471		1716
1472	sof_parent = snd_soc_acpi_sof_parent(&pdev->dev);	1717	sof_parent = snd_soc_acpi_sof_parent(&pdev->dev);
1473		1718
@@ -1489,10 +1734,32 @@ static int snd_byt_rt5640_mc_probe(struct platform_device *pdev) · 15 unmodified lines
1489	if (ret_val) {	1734	if (ret_val) {
1490	dev_err(&pdev->dev, "devm_snd_soc_register_card failed %d\n",	1735	dev_err(&pdev->dev, "devm_snd_soc_register_card failed %d\n",
1491	ret_val);	1736	ret_val);
1492	return ret_val;	1737	goto err;
1493	}	1738	}
1494	platform_set_drvdata(pdev, &byt_rt5640_card);	1739	platform_set_drvdata(pdev, &byt_rt5640_card);
1495	return ret_val;	1740	return ret_val;
		1741
		1742	err:
		1743	device_remove_software_node(priv->codec_dev);
		1744	err_remove_gpios:
		1745	if (byt_rt5640_quirk & BYT_RT5640_JD_HP_ELITEP_1000G2)
		1746	acpi_dev_remove_driver_gpios(ACPI_COMPANION(priv->codec_dev));
		1747	err_device:
		1748	put_device(priv->codec_dev);
		1749	return ret_val;
		1750	}
		1751
		1752	static int snd_byt_rt5640_mc_remove(struct platform_device *pdev)
		1753	{
		1754	struct snd_soc_card *card = platform_get_drvdata(pdev);
		1755	struct byt_rt5640_private *priv = snd_soc_card_get_drvdata(card);
		1756
		1757	if (byt_rt5640_quirk & BYT_RT5640_JD_HP_ELITEP_1000G2)
		1758	acpi_dev_remove_driver_gpios(ACPI_COMPANION(priv->codec_dev));
		1759
		1760	device_remove_software_node(priv->codec_dev);
		1761	put_device(priv->codec_dev);
		1762	return 0;
1496	}	1763	}
1497		1764
1498	static struct platform_driver snd_byt_rt5640_mc_driver = {	1765	static struct platform_driver snd_byt_rt5640_mc_driver = {
@@ -1500,6 +1767,7 @@ static struct platform_driver snd_byt_rt5640_mc_driver = { · 1 unmodified line
1500	.name = "bytcr_rt5640",	1767	.name = "bytcr_rt5640",
1501	},	1768	},
1502	.probe = snd_byt_rt5640_mc_probe,	1769	.probe = snd_byt_rt5640_mc_probe,
		1770	.remove = snd_byt_rt5640_mc_remove,
1503	};	1771	};
1504		1772
1505	module_platform_driver(snd_byt_rt5640_mc_driver);	1773	module_platform_driver(snd_byt_rt5640_mc_driver);

sound/soc/intel/boards/bytcr_rt5651.c+44−19

 	struct gpio_desc *ext_amp_gpio;
 	struct gpio_desc *hp_detect;
 	struct snd_soc_jack jack;
+	struct device *codec_dev;
 };
 static const struct acpi_gpio_mapping *byt_rt5651_gpios;
  * Note this MUST be called before snd_soc_register_card(), so that the props
  * are in place before the codec component driver's probe function parses them.
  */
-static int byt_rt5651_add_codec_device_props(struct device *i2c_dev)
+static int byt_rt5651_add_codec_device_props(struct device *i2c_dev,
+					     struct byt_rt5651_private *priv)
 {
 	struct property_entry props[MAX_NO_PROPS] = {};
+	struct fwnode_handle *fwnode;
 	int cnt = 0;
+	int ret;
 	props[cnt++] = PROPERTY_ENTRY_U32("realtek,jack-detect-source",
 				BYT_RT5651_JDSRC(byt_rt5651_quirk));
 	if (byt_rt5651_quirk & BYT_RT5651_JD_NOT_INV)
 		props[cnt++] = PROPERTY_ENTRY_BOOL("realtek,jack-detect-not-inverted");
-	return device_add_properties(i2c_dev, props);
+	fwnode = fwnode_create_software_node(props, NULL);
+	if (IS_ERR(fwnode)) {
+		/* put_device(i2c_dev) is handled in caller */
+		return PTR_ERR(fwnode);
+	}
+	ret = device_add_software_node(i2c_dev, to_software_node(fwnode));
+	fwnode_handle_put(fwnode);
+	return ret;
 }
 static int byt_rt5651_init(struct snd_soc_pcm_runtime *runtime)
 		byt_rt5651_dais[dai_index].codecs->name = byt_rt5651_codec_name;
 	} else {
 		dev_err(&pdev->dev, "Error cannot find '%s' dev\n", mach->id);
-		return -ENODEV;
+		return -ENXIO;
 	}
-	codec_dev = bus_find_device_by_name(&i2c_bus_type, NULL,
+	codec_dev = acpi_get_first_physical_node(adev);
-					    byt_rt5651_codec_name);
 	if (!codec_dev)
 		return -EPROBE_DEFER;
+	priv->codec_dev = get_device(codec_dev);
 	/*
 	 * swap SSP0 if bytcr is detected
 	}
 	/* Must be called before register_card, also see declaration comment. */
-	ret_val = byt_rt5651_add_codec_device_props(codec_dev);
+	ret_val = byt_rt5651_add_codec_device_props(codec_dev, priv);
-	if (ret_val) {
+	if (ret_val)
-		put_device(codec_dev);
+		goto err_device;
-		return ret_val;
-	}
 	/* Cherry Trail devices use an external amplifier enable gpio */
 	if (soc_intel_is_cht() && !byt_rt5651_gpios)
 					ret_val);
 				fallthrough;
 			case -EPROBE_DEFER:
-				put_device(codec_dev);
+				goto err;
-				return ret_val;
 			}
 		}
 		priv->hp_detect = devm_fwnode_gpiod_get(&pdev->dev,
 					ret_val);
 				fallthrough;
 			case -EPROBE_DEFER:
-				put_device(codec_dev);
+				goto err;
-				return ret_val;
 			}
 		}
 	}
-	put_device(codec_dev);
 	log_quirks(&pdev->dev);
 	if ((byt_rt5651_quirk & BYT_RT5651_SSP2_AIF2) ||
 			 * for all other errors, including -EPROBE_DEFER
 			 */
 			if (ret_val != -ENOENT)
-				return ret_val;
+				goto err;
 			byt_rt5651_quirk &= ~BYT_RT5651_MCLK_EN;
 		}
 	}
 	ret_val = snd_soc_fixup_dai_links_platform_name(&byt_rt5651_card,
 							platform_name);
 	if (ret_val)
-		return ret_val;
+		goto err;
 	sof_parent = snd_soc_acpi_sof_parent(&pdev->dev);
 	if (ret_val) {
 		dev_err(&pdev->dev, "devm_snd_soc_register_card failed %d\n",
 			ret_val);
-		return ret_val;
+		goto err;
 	}
 	platform_set_drvdata(pdev, &byt_rt5651_card);
 	return ret_val;
+err:
+	device_remove_software_node(priv->codec_dev);
+err_device:
+	put_device(priv->codec_dev);
+	return ret_val;
+}
+static int snd_byt_rt5651_mc_remove(struct platform_device *pdev)
+{
+	struct snd_soc_card *card = platform_get_drvdata(pdev);
+	struct byt_rt5651_private *priv = snd_soc_card_get_drvdata(card);
+	device_remove_software_node(priv->codec_dev);
+	put_device(priv->codec_dev);
+	return 0;
 }
 static struct platform_driver snd_byt_rt5651_mc_driver = {
 		.name = "bytcr_rt5651",
 	},
 	.probe = snd_byt_rt5651_mc_probe,
+	.remove = snd_byt_rt5651_mc_remove,
 };
 module_platform_driver(snd_byt_rt5651_mc_driver);

sound/soc/intel/boards/kbl_da7219_max98927.c+7−48

@@ -199,7 +199,7 @@ static int kabylake_ssp0_hw_params(struct snd_pcm_substream *substream, · 198 unmodified lines
199	}	199	}
200	if (!strcmp(codec_dai->component->name, MAX98373_DEV0_NAME)) {	200	if (!strcmp(codec_dai->component->name, MAX98373_DEV0_NAME)) {
201	ret = snd_soc_dai_set_tdm_slot(codec_dai,	201	ret = snd_soc_dai_set_tdm_slot(codec_dai,
202	0x03, 3, 8, 24);	202	0x30, 3, 8, 16);
203	if (ret < 0) {	203	if (ret < 0) {
204	dev_err(runtime->dev,	204	dev_err(runtime->dev,
205	"DEV0 TDM slot err:%d\n", ret);	205	"DEV0 TDM slot err:%d\n", ret);
@@ -208,10 +208,10 @@ static int kabylake_ssp0_hw_params(struct snd_pcm_substream *substream, · 2 unmodified lines
208	}	208	}
209	if (!strcmp(codec_dai->component->name, MAX98373_DEV1_NAME)) {	209	if (!strcmp(codec_dai->component->name, MAX98373_DEV1_NAME)) {
210	ret = snd_soc_dai_set_tdm_slot(codec_dai,	210	ret = snd_soc_dai_set_tdm_slot(codec_dai,
211	0x0C, 3, 8, 24);	211	0xC0, 3, 8, 16);
212	if (ret < 0) {	212	if (ret < 0) {
213	dev_err(runtime->dev,	213	dev_err(runtime->dev,
214	"DEV0 TDM slot err:%d\n", ret);	214	"DEV1 TDM slot err:%d\n", ret);
215	return ret;	215	return ret;
216	}	216	}
217	}	217	}
@@ -311,24 +311,6 @@ static int kabylake_ssp_fixup(struct snd_soc_pcm_runtime *rtd, · 93 unmodified lines
311	* The above 2 loops are mutually exclusive based on the stream direction,	311	* The above 2 loops are mutually exclusive based on the stream direction,
312	* thus rtd_dpcm variable will never be overwritten	312	* thus rtd_dpcm variable will never be overwritten
313	*/	313	*/
314	/*
315	* Topology for kblda7219m98373 & kblmax98373 supports only S24_LE,
316	* where as kblda7219m98927 & kblmax98927 supports S16_LE by default.
317	* Skipping the port wise FE and BE configuration for kblda7219m98373 &
318	* kblmax98373 as the topology (FE & BE) supports S24_LE only.
319	*/
320
321	if (!strcmp(rtd->card->name, "kblda7219m98373") \|\|
322	!strcmp(rtd->card->name, "kblmax98373")) {
323	/* The ADSP will convert the FE rate to 48k, stereo */
324	rate->min = rate->max = 48000;
325	chan->min = chan->max = DUAL_CHANNEL;
326
327	/* set SSP to 24 bit */
328	snd_mask_none(fmt);
329	snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S24_LE);
330	return 0;
331	}
332		314
333	/*	315	/*
334	* The ADSP will convert the FE rate to 48k, stereo, 24 bit	316	* The ADSP will convert the FE rate to 48k, stereo, 24 bit
@@ -479,31 +461,20 @@ static struct snd_pcm_hw_constraint_list constraints_channels_quad = { · 144 unmodified lines
479	static int kbl_fe_startup(struct snd_pcm_substream *substream)	461	static int kbl_fe_startup(struct snd_pcm_substream *substream)
480	{	462	{
481	struct snd_pcm_runtime *runtime = substream->runtime;	463	struct snd_pcm_runtime *runtime = substream->runtime;
482	struct snd_soc_pcm_runtime *soc_rt = asoc_substream_to_rtd(substream);
483		464
484	/*	465	/*
485	* On this platform for PCM device we support,	466	* On this platform for PCM device we support,
486	* 48Khz	467	* 48Khz
487	* stereo	468	* stereo
		469	* 16 bit audio
488	*/	470	*/
489		471
490	runtime->hw.channels_max = DUAL_CHANNEL;	472	runtime->hw.channels_max = DUAL_CHANNEL;
491	snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,	473	snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
492	&constraints_channels);	474	&constraints_channels);
493	/*	475
494	* Setup S24_LE (32 bit container and 24 bit valid data) for	476	runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE;
495	* kblda7219m98373 & kblmax98373. For kblda7219m98927 &	477	snd_pcm_hw_constraint_msbits(runtime, 0, 16, 16);
496	* kblmax98927 keeping it as 16/16 due to topology FW dependency.
497	*/
498	if (!strcmp(soc_rt->card->name, "kblda7219m98373") \|\|
499	!strcmp(soc_rt->card->name, "kblmax98373")) {
500	runtime->hw.formats = SNDRV_PCM_FMTBIT_S24_LE;
501	snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
502
503	} else {
504	runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE;
505	snd_pcm_hw_constraint_msbits(runtime, 0, 16, 16);
506	}
507		478
508	snd_pcm_hw_constraint_list(runtime, 0,	479	snd_pcm_hw_constraint_list(runtime, 0,
509	SNDRV_PCM_HW_PARAM_RATE, &constraints_rates);	480	SNDRV_PCM_HW_PARAM_RATE, &constraints_rates);
@@ -536,23 +507,11 @@ static int kabylake_dmic_fixup(struct snd_soc_pcm_runtime *rtd, · 26 unmodified lines
536	static int kabylake_dmic_startup(struct snd_pcm_substream *substream)	507	static int kabylake_dmic_startup(struct snd_pcm_substream *substream)
537	{	508	{
538	struct snd_pcm_runtime *runtime = substream->runtime;	509	struct snd_pcm_runtime *runtime = substream->runtime;
539	struct snd_soc_pcm_runtime *soc_rt = asoc_substream_to_rtd(substream);
540		510
541	runtime->hw.channels_min = runtime->hw.channels_max = QUAD_CHANNEL;	511	runtime->hw.channels_min = runtime->hw.channels_max = QUAD_CHANNEL;
542	snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,	512	snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
543	&constraints_channels_quad);	513	&constraints_channels_quad);
544		514
545	/*
546	* Topology for kblda7219m98373 & kblmax98373 supports only S24_LE.
547	* The DMIC also configured for S24_LE. Forcing the DMIC format to
548	* S24_LE due to the topology FW dependency.
549	*/
550	if (!strcmp(soc_rt->card->name, "kblda7219m98373") \|\|
551	!strcmp(soc_rt->card->name, "kblmax98373")) {
552	runtime->hw.formats = SNDRV_PCM_FMTBIT_S24_LE;
553	snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
554	}
555
556	return snd_pcm_hw_constraint_list(substream->runtime, 0,	515	return snd_pcm_hw_constraint_list(substream->runtime, 0,
557	SNDRV_PCM_HW_PARAM_RATE, &constraints_rates);	516	SNDRV_PCM_HW_PARAM_RATE, &constraints_rates);
558	}	517	}

sound/soc/intel/boards/sof_cs42l42.c+248−113

@@ -16,6 +16,7 @@ · 15 unmodified lines
16	#include <sound/pcm.h>	16	#include <sound/pcm.h>
17	#include <sound/pcm_params.h>	17	#include <sound/pcm_params.h>
18	#include <sound/soc.h>	18	#include <sound/soc.h>
		19	#include <sound/sof.h>
19	#include <sound/soc-acpi.h>	20	#include <sound/soc-acpi.h>
20	#include <dt-bindings/sound/cs42l42.h>	21	#include <dt-bindings/sound/cs42l42.h>
21	#include "../../codecs/hdac_hdmi.h"	22	#include "../../codecs/hdac_hdmi.h"
@@ -36,7 +37,20 @@ · 14 unmodified lines
36	#define SOF_CS42L42_NUM_HDMIDEV_MASK (GENMASK(9, 7))	37	#define SOF_CS42L42_NUM_HDMIDEV_MASK (GENMASK(9, 7))
37	#define SOF_CS42L42_NUM_HDMIDEV(quirk) \	38	#define SOF_CS42L42_NUM_HDMIDEV(quirk) \
38	(((quirk) << SOF_CS42L42_NUM_HDMIDEV_SHIFT) & SOF_CS42L42_NUM_HDMIDEV_MASK)	39	(((quirk) << SOF_CS42L42_NUM_HDMIDEV_SHIFT) & SOF_CS42L42_NUM_HDMIDEV_MASK)
39	#define SOF_MAX98357A_SPEAKER_AMP_PRESENT BIT(10)	40	#define SOF_CS42L42_DAILINK_SHIFT 10
		41	#define SOF_CS42L42_DAILINK_MASK (GENMASK(24, 10))
		42	#define SOF_CS42L42_DAILINK(link1, link2, link3, link4, link5) \
		43	((((link1) \| ((link2) << 3) \| ((link3) << 6) \| ((link4) << 9) \| ((link5) << 12)) << SOF_CS42L42_DAILINK_SHIFT) & SOF_CS42L42_DAILINK_MASK)
		44	#define SOF_MAX98357A_SPEAKER_AMP_PRESENT BIT(25)
		45	#define SOF_MAX98360A_SPEAKER_AMP_PRESENT BIT(26)
		46
		47	enum {
		48	LINK_NONE = 0,
		49	LINK_HP = 1,
		50	LINK_SPK = 2,
		51	LINK_DMIC = 3,
		52	LINK_HDMI = 4,
		53	};
40		54
41	/* Default: SSP2 */	55	/* Default: SSP2 */
42	static unsigned long sof_cs42l42_quirk = SOF_CS42L42_SSP_CODEC(2);	56	static unsigned long sof_cs42l42_quirk = SOF_CS42L42_SSP_CODEC(2);
@@ -122,7 +136,12 @@ static int sof_cs42l42_hw_params(struct snd_pcm_substream *substream, · 79 unmodified lines
122	struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);	136	struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
123	int clk_freq, ret;	137	int clk_freq, ret;
124		138
125	clk_freq = 3072000; /* BCLK freq */	139	clk_freq = sof_dai_get_bclk(rtd); /* BCLK freq */
		140
		141	if (clk_freq <= 0) {
		142	dev_err(rtd->dev, "get bclk freq failed: %d\n", clk_freq);
		143	return -EINVAL;
		144	}
126		145
127	/* Configure sysclk for codec */	146	/* Configure sysclk for codec */
128	ret = snd_soc_dai_set_sysclk(codec_dai, 0,	147	ret = snd_soc_dai_set_sysclk(codec_dai, 0,
@@ -259,133 +278,168 @@ static struct snd_soc_dai_link_component dmic_component[] = { · 130 unmodified lines
259	}	278	}
260	};	279	};
261		280
262	static struct snd_soc_dai_link sof_card_dai_links_create(struct device dev,	281	static int create_spk_amp_dai_links(struct device *dev,
263	int ssp_codec,	282	struct snd_soc_dai_link *links,
264	int ssp_amp,	283	struct snd_soc_dai_link_component *cpus,
265	int dmic_be_num,	284	int *id, int ssp_amp)
266	int hdmi_num)
267	{	285	{
268	struct snd_soc_dai_link_component *idisp_components;	286	int ret = 0;
269	struct snd_soc_dai_link_component *cpus;
270	struct snd_soc_dai_link *links;
271	int i, id = 0;
272
273	links = devm_kzalloc(dev, sizeof(struct snd_soc_dai_link) *
274	sof_audio_card_cs42l42.num_links, GFP_KERNEL);
275	cpus = devm_kzalloc(dev, sizeof(struct snd_soc_dai_link_component) *
276	sof_audio_card_cs42l42.num_links, GFP_KERNEL);
277	if (!links \|\| !cpus)
278	goto devm_err;
279		287
280	/* speaker amp */	288	/* speaker amp */
281	if (sof_cs42l42_quirk & SOF_SPEAKER_AMP_PRESENT) {	289	if (!(sof_cs42l42_quirk & SOF_SPEAKER_AMP_PRESENT))
282	links[id].name = devm_kasprintf(dev, GFP_KERNEL,	290	return 0;
283	"SSP%d-Codec", ssp_amp);
284	if (!links[id].name)
285	goto devm_err;
286		291
287	links[id].id = id;	292	links[*id].name = devm_kasprintf(dev, GFP_KERNEL, "SSP%d-Codec",
		293	ssp_amp);
		294	if (!links[*id].name) {
		295	ret = -ENOMEM;
		296	goto devm_err;
		297	}
288		298
289	if (sof_cs42l42_quirk & SOF_MAX98357A_SPEAKER_AMP_PRESENT) {	299	links[id].id = id;
290	max_98357a_dai_link(&links[id]);
291	} else {
292	dev_err(dev, "no amp defined\n");
293	goto devm_err;
294	}
295		300
296	links[id].platforms = platform_component;	301	if (sof_cs42l42_quirk & SOF_MAX98357A_SPEAKER_AMP_PRESENT) {
297	links[id].num_platforms = ARRAY_SIZE(platform_component);	302	max_98357a_dai_link(&links[*id]);
298	links[id].dpcm_playback = 1;	303	} else if (sof_cs42l42_quirk & SOF_MAX98360A_SPEAKER_AMP_PRESENT) {
299	links[id].no_pcm = 1;	304	max_98360a_dai_link(&links[*id]);
300	links[id].cpus = &cpus[id];	305	} else {
301	links[id].num_cpus = 1;	306	dev_err(dev, "no amp defined\n");
302		307	ret = -EINVAL;
303	links[id].cpus->dai_name = devm_kasprintf(dev, GFP_KERNEL,	308	goto devm_err;
304	"SSP%d Pin",	309	}
305	ssp_amp);
306	if (!links[id].cpus->dai_name)
307	goto devm_err;
308		310
309	id++;	311	links[*id].platforms = platform_component;
		312	links[*id].num_platforms = ARRAY_SIZE(platform_component);
		313	links[*id].dpcm_playback = 1;
		314	links[*id].no_pcm = 1;
		315	links[id].cpus = &cpus[id];
		316	links[*id].num_cpus = 1;
		317
		318	links[*id].cpus->dai_name = devm_kasprintf(dev, GFP_KERNEL,
		319	"SSP%d Pin", ssp_amp);
		320	if (!links[*id].cpus->dai_name) {
		321	ret = -ENOMEM;
		322	goto devm_err;
310	}	323	}
311		324
		325	(*id)++;
		326
		327	devm_err:
		328	return ret;
		329	}
		330
		331	static int create_hp_codec_dai_links(struct device *dev,
		332	struct snd_soc_dai_link *links,
		333	struct snd_soc_dai_link_component *cpus,
		334	int *id, int ssp_codec)
		335	{
312	/* codec SSP */	336	/* codec SSP */
313	links[id].name = devm_kasprintf(dev, GFP_KERNEL,	337	links[*id].name = devm_kasprintf(dev, GFP_KERNEL, "SSP%d-Codec",
314	"SSP%d-Codec", ssp_codec);	338	ssp_codec);
315	if (!links[id].name)	339	if (!links[*id].name)
316	goto devm_err;	340	goto devm_err;
317		341
318	links[id].id = id;	342	links[id].id = id;
319	links[id].codecs = cs42l42_component;	343	links[*id].codecs = cs42l42_component;
320	links[id].num_codecs = ARRAY_SIZE(cs42l42_component);	344	links[*id].num_codecs = ARRAY_SIZE(cs42l42_component);
321	links[id].platforms = platform_component;	345	links[*id].platforms = platform_component;
322	links[id].num_platforms = ARRAY_SIZE(platform_component);	346	links[*id].num_platforms = ARRAY_SIZE(platform_component);
323	links[id].init = sof_cs42l42_init;	347	links[*id].init = sof_cs42l42_init;
324	links[id].exit = sof_cs42l42_exit;	348	links[*id].exit = sof_cs42l42_exit;
325	links[id].ops = &sof_cs42l42_ops;	349	links[*id].ops = &sof_cs42l42_ops;
326	links[id].dpcm_playback = 1;	350	links[*id].dpcm_playback = 1;
327	links[id].dpcm_capture = 1;	351	links[*id].dpcm_capture = 1;
328	links[id].no_pcm = 1;	352	links[*id].no_pcm = 1;
329	links[id].cpus = &cpus[id];	353	links[id].cpus = &cpus[id];
330	links[id].num_cpus = 1;	354	links[*id].num_cpus = 1;
331		355
332	links[id].cpus->dai_name = devm_kasprintf(dev, GFP_KERNEL,	356	links[*id].cpus->dai_name = devm_kasprintf(dev, GFP_KERNEL,
333	"SSP%d Pin",	357	"SSP%d Pin",
334	ssp_codec);	358	ssp_codec);
335	if (!links[id].cpus->dai_name)	359	if (!links[*id].cpus->dai_name)
336	goto devm_err;	360	goto devm_err;
337		361
338	id++;	362	(*id)++;
		363
		364	return 0;
		365
		366	devm_err:
		367	return -ENOMEM;
		368	}
		369
		370	static int create_dmic_dai_links(struct device *dev,
		371	struct snd_soc_dai_link *links,
		372	struct snd_soc_dai_link_component *cpus,
		373	int *id, int dmic_be_num)
		374	{
		375	int i;
339		376
340	/* dmic */	377	/* dmic */
341	if (dmic_be_num > 0) {	378	if (dmic_be_num <= 0)
342	/* at least we have dmic01 */	379	return 0;
343	links[id].name = "dmic01";	380
344	links[id].cpus = &cpus[id];	381	/* at least we have dmic01 */
345	links[id].cpus->dai_name = "DMIC01 Pin";	382	links[*id].name = "dmic01";
346	links[id].init = dmic_init;	383	links[id].cpus = &cpus[id];
347	if (dmic_be_num > 1) {	384	links[*id].cpus->dai_name = "DMIC01 Pin";
348	/* set up 2 BE links at most */	385	links[*id].init = dmic_init;
349	links[id + 1].name = "dmic16k";	386	if (dmic_be_num > 1) {
350	links[id + 1].cpus = &cpus[id + 1];	387	/* set up 2 BE links at most */
351	links[id + 1].cpus->dai_name = "DMIC16k Pin";	388	links[*id + 1].name = "dmic16k";
352	dmic_be_num = 2;	389	links[id + 1].cpus = &cpus[id + 1];
353	}	390	links[*id + 1].cpus->dai_name = "DMIC16k Pin";
		391	dmic_be_num = 2;
354	}	392	}
355		393
356	for (i = 0; i < dmic_be_num; i++) {	394	for (i = 0; i < dmic_be_num; i++) {
357	links[id].id = id;	395	links[id].id = id;
358	links[id].num_cpus = 1;	396	links[*id].num_cpus = 1;
359	links[id].codecs = dmic_component;	397	links[*id].codecs = dmic_component;
360	links[id].num_codecs = ARRAY_SIZE(dmic_component);	398	links[*id].num_codecs = ARRAY_SIZE(dmic_component);
361	links[id].platforms = platform_component;	399	links[*id].platforms = platform_component;
362	links[id].num_platforms = ARRAY_SIZE(platform_component);	400	links[*id].num_platforms = ARRAY_SIZE(platform_component);
363	links[id].ignore_suspend = 1;	401	links[*id].ignore_suspend = 1;
364	links[id].dpcm_capture = 1;	402	links[*id].dpcm_capture = 1;
365	links[id].no_pcm = 1;	403	links[*id].no_pcm = 1;
366	id++;	404
		405	(*id)++;
367	}	406	}
368		407
		408	return 0;
		409	}
		410
		411	static int create_hdmi_dai_links(struct device *dev,
		412	struct snd_soc_dai_link *links,
		413	struct snd_soc_dai_link_component *cpus,
		414	int *id, int hdmi_num)
		415	{
		416	struct snd_soc_dai_link_component *idisp_components;
		417	int i;
		418
369	/* HDMI */	419	/* HDMI */
370	if (hdmi_num > 0) {	420	if (hdmi_num <= 0)
371	idisp_components = devm_kzalloc(dev,	421	return 0;
372	sizeof(struct snd_soc_dai_link_component) *	422
373	hdmi_num, GFP_KERNEL);	423	idisp_components = devm_kzalloc(dev,
374	if (!idisp_components)	424	sizeof(struct snd_soc_dai_link_component) *
375	goto devm_err;	425	hdmi_num, GFP_KERNEL);
376	}	426	if (!idisp_components)
		427	goto devm_err;
		428
377	for (i = 1; i <= hdmi_num; i++) {	429	for (i = 1; i <= hdmi_num; i++) {
378	links[id].name = devm_kasprintf(dev, GFP_KERNEL,	430	links[*id].name = devm_kasprintf(dev, GFP_KERNEL,
379	"iDisp%d", i);	431	"iDisp%d", i);
380	if (!links[id].name)	432	if (!links[*id].name)
381	goto devm_err;	433	goto devm_err;
382		434
383	links[id].id = id;	435	links[id].id = id;
384	links[id].cpus = &cpus[id];	436	links[id].cpus = &cpus[id];
385	links[id].num_cpus = 1;	437	links[*id].num_cpus = 1;
386	links[id].cpus->dai_name = devm_kasprintf(dev, GFP_KERNEL,	438	links[*id].cpus->dai_name = devm_kasprintf(dev,
387	"iDisp%d Pin", i);	439	GFP_KERNEL,
388	if (!links[id].cpus->dai_name)	440	"iDisp%d Pin",
		441	i);
		442	if (!links[*id].cpus->dai_name)
389	goto devm_err;	443	goto devm_err;
390		444
391	idisp_components[i - 1].name = "ehdaudio0D2";	445	idisp_components[i - 1].name = "ehdaudio0D2";
@@ -396,14 +450,86 @@ static struct snd_soc_dai_link sof_card_dai_links_create(struct device dev, · 4 unmodified lines
396	if (!idisp_components[i - 1].dai_name)	450	if (!idisp_components[i - 1].dai_name)
397	goto devm_err;	451	goto devm_err;
398		452
399	links[id].codecs = &idisp_components[i - 1];	453	links[*id].codecs = &idisp_components[i - 1];
400	links[id].num_codecs = 1;	454	links[*id].num_codecs = 1;
401	links[id].platforms = platform_component;	455	links[*id].platforms = platform_component;
402	links[id].num_platforms = ARRAY_SIZE(platform_component);	456	links[*id].num_platforms = ARRAY_SIZE(platform_component);
403	links[id].init = sof_hdmi_init;	457	links[*id].init = sof_hdmi_init;
404	links[id].dpcm_playback = 1;	458	links[*id].dpcm_playback = 1;
405	links[id].no_pcm = 1;	459	links[*id].no_pcm = 1;
406	id++;	460
		461	(*id)++;
		462	}
		463
		464	return 0;
		465
		466	devm_err:
		467	return -ENOMEM;
		468	}
		469
		470	static struct snd_soc_dai_link sof_card_dai_links_create(struct device dev,
		471	int ssp_codec,
		472	int ssp_amp,
		473	int dmic_be_num,
		474	int hdmi_num)
		475	{
		476	struct snd_soc_dai_link_component *cpus;
		477	struct snd_soc_dai_link *links;
		478	int ret, id = 0, link_seq;
		479
		480	links = devm_kzalloc(dev, sizeof(struct snd_soc_dai_link) *
		481	sof_audio_card_cs42l42.num_links, GFP_KERNEL);
		482	cpus = devm_kzalloc(dev, sizeof(struct snd_soc_dai_link_component) *
		483	sof_audio_card_cs42l42.num_links, GFP_KERNEL);
		484	if (!links \|\| !cpus)
		485	goto devm_err;
		486
		487	link_seq = (sof_cs42l42_quirk & SOF_CS42L42_DAILINK_MASK) >> SOF_CS42L42_DAILINK_SHIFT;
		488
		489	while (link_seq) {
		490	int link_type = link_seq & 0x07;
		491
		492	switch (link_type) {
		493	case LINK_HP:
		494	ret = create_hp_codec_dai_links(dev, links, cpus, &id, ssp_codec);
		495	if (ret < 0) {
		496	dev_err(dev, "fail to create hp codec dai links, ret %d\n",
		497	ret);
		498	goto devm_err;
		499	}
		500	break;
		501	case LINK_SPK:
		502	ret = create_spk_amp_dai_links(dev, links, cpus, &id, ssp_amp);
		503	if (ret < 0) {
		504	dev_err(dev, "fail to create spk amp dai links, ret %d\n",
		505	ret);
		506	goto devm_err;
		507	}
		508	break;
		509	case LINK_DMIC:
		510	ret = create_dmic_dai_links(dev, links, cpus, &id, dmic_be_num);
		511	if (ret < 0) {
		512	dev_err(dev, "fail to create dmic dai links, ret %d\n",
		513	ret);
		514	goto devm_err;
		515	}
		516	break;
		517	case LINK_HDMI:
		518	ret = create_hdmi_dai_links(dev, links, cpus, &id, hdmi_num);
		519	if (ret < 0) {
		520	dev_err(dev, "fail to create hdmi dai links, ret %d\n",
		521	ret);
		522	goto devm_err;
		523	}
		524	break;
		525	case LINK_NONE:
		526	/* caught here if it's not used as terminator in macro */
		527	default:
		528	dev_err(dev, "invalid link type %d\n", link_type);
		529	goto devm_err;
		530	}
		531
		532	link_seq >>= 3;
407	}	533	}
408		534
409	return links;	535	return links;
@@ -484,7 +610,16 @@ static const struct platform_device_id board_ids[] = { · 74 unmodified lines
484	.driver_data = (kernel_ulong_t)(SOF_CS42L42_SSP_CODEC(2) \|	610	.driver_data = (kernel_ulong_t)(SOF_CS42L42_SSP_CODEC(2) \|
485	SOF_SPEAKER_AMP_PRESENT \|	611	SOF_SPEAKER_AMP_PRESENT \|
486	SOF_MAX98357A_SPEAKER_AMP_PRESENT \|	612	SOF_MAX98357A_SPEAKER_AMP_PRESENT \|
487	SOF_CS42L42_SSP_AMP(1)),	613	SOF_CS42L42_SSP_AMP(1)) \|
		614	SOF_CS42L42_DAILINK(LINK_SPK, LINK_HP, LINK_DMIC, LINK_HDMI, LINK_NONE),
		615	},
		616	{
		617	.name = "jsl_cs4242_mx98360a",
		618	.driver_data = (kernel_ulong_t)(SOF_CS42L42_SSP_CODEC(0) \|
		619	SOF_SPEAKER_AMP_PRESENT \|
		620	SOF_MAX98360A_SPEAKER_AMP_PRESENT \|
		621	SOF_CS42L42_SSP_AMP(1)) \|
		622	SOF_CS42L42_DAILINK(LINK_HP, LINK_DMIC, LINK_HDMI, LINK_SPK, LINK_NONE),
488	},	623	},
489	{ }	624	{ }
490	};	625	};

sound/soc/intel/boards/sof_maxim_common.c+16−1

 EXPORT_SYMBOL_NS(max_98373_set_codec_conf, SND_SOC_INTEL_SOF_MAXIM_COMMON);
 /*
- * Maxim MAX98357A
+ * Maxim MAX98357A/MAX98360A
  */
 static const struct snd_kcontrol_new max_98357a_kcontrols[] = {
 	SOC_DAPM_PIN_SWITCH("Spk"),
 	}
 };
+static struct snd_soc_dai_link_component max_98360a_components[] = {
+	{
+		.name = MAX_98360A_DEV0_NAME,
+		.dai_name = MAX_98357A_CODEC_DAI,
+	}
+};
 static int max_98357a_init(struct snd_soc_pcm_runtime *rtd)
 {
 	struct snd_soc_card *card = rtd->card;
 }
 EXPORT_SYMBOL_NS(max_98357a_dai_link, SND_SOC_INTEL_SOF_MAXIM_COMMON);
+void max_98360a_dai_link(struct snd_soc_dai_link *link)
+{
+	link->codecs = max_98360a_components;
+	link->num_codecs = ARRAY_SIZE(max_98360a_components);
+	link->init = max_98357a_init;
+}
+EXPORT_SYMBOL_NS(max_98360a_dai_link, SND_SOC_INTEL_SOF_MAXIM_COMMON);
 MODULE_DESCRIPTION("ASoC Intel SOF Maxim helpers");
 MODULE_LICENSE("GPL");

sound/soc/intel/boards/sof_maxim_common.h+3−1

 int max_98373_trigger(struct snd_pcm_substream *substream, int cmd);
 /*
- * Maxim MAX98357A
+ * Maxim MAX98357A/MAX98360A
  */
 #define MAX_98357A_CODEC_DAI	"HiFi"
 #define MAX_98357A_DEV0_NAME	"MX98357A:00"
+#define MAX_98360A_DEV0_NAME	"MX98360A:00"
 void max_98357a_dai_link(struct snd_soc_dai_link *link);
+void max_98360a_dai_link(struct snd_soc_dai_link *link);
 #endif /* __SOF_MAXIM_COMMON_H */

sound/soc/intel/boards/sof_pcm512x.c+11−2

 #define SOF_PCM512X_SSP_CODEC(quirk)		((quirk) & GENMASK(3, 0))
 #define SOF_PCM512X_SSP_CODEC_MASK			(GENMASK(3, 0))
+#define SOF_PCM512X_ENABLE_SSP_CAPTURE		BIT(4)
+#define SOF_PCM512X_ENABLE_DMIC			BIT(5)
 #define IDISP_CODEC_MASK	0x4
 /* Default: SSP5 */
-static unsigned long sof_pcm512x_quirk = SOF_PCM512X_SSP_CODEC(5);
+static unsigned long sof_pcm512x_quirk =
+	SOF_PCM512X_SSP_CODEC(5) |
+	SOF_PCM512X_ENABLE_SSP_CAPTURE |
+	SOF_PCM512X_ENABLE_DMIC;
 static bool is_legacy_cpu;
 	links[id].dpcm_playback = 1;
 	/*
 	 * capture only supported with specific versions of the Hifiberry DAC+
-	 * links[id].dpcm_capture = 1;
 	 */
+	if (sof_pcm512x_quirk & SOF_PCM512X_ENABLE_SSP_CAPTURE)
+		links[id].dpcm_capture = 1;
 	links[id].no_pcm = 1;
 	links[id].cpus = &cpus[id];
 	links[id].num_cpus = 1;
 	ssp_codec = sof_pcm512x_quirk & SOF_PCM512X_SSP_CODEC_MASK;
+	if (!(sof_pcm512x_quirk & SOF_PCM512X_ENABLE_DMIC))
+		dmic_be_num = 0;
 	/* compute number of dai links */
 	sof_audio_card_pcm512x.num_links = 1 + dmic_be_num + hdmi_num;

sound/soc/intel/boards/sof_rt5682.c+15−51

 					SOF_RT5682_SSP_AMP(2) |
 					SOF_RT5682_NUM_HDMIDEV(4)),
 	},
+	{
+		.callback = sof_rt5682_quirk_cb,
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "Alder Lake Client Platform"),
+			DMI_MATCH(DMI_OEM_STRING, "AUDIO-ADL_MAX98373_ALC5682I_I2S"),
+		},
+		.driver_data = (void *)(SOF_RT5682_MCLK_EN |
+					SOF_RT5682_SSP_CODEC(0) |
+					SOF_SPEAKER_AMP_PRESENT |
+					SOF_MAX98373_SPEAKER_AMP_PRESENT |
+					SOF_RT5682_SSP_AMP(2) |
+					SOF_RT5682_NUM_HDMIDEV(4)),
+	},
 	{}
 };
 };
-static const struct snd_kcontrol_new speaker_controls[] = {
-	SOC_DAPM_PIN_SWITCH("Spk"),
-};
 static const struct snd_soc_dapm_widget sof_widgets[] = {
 	SND_SOC_DAPM_HP("Headphone Jack", NULL),
 	SND_SOC_DAPM_MIC("Headset Mic", NULL),
 	SND_SOC_DAPM_SPK("Right Spk", NULL),
 };
-static const struct snd_soc_dapm_widget speaker_widgets[] = {
-	SND_SOC_DAPM_SPK("Spk", NULL),
-};
 static const struct snd_soc_dapm_widget dmic_widgets[] = {
 	SND_SOC_DAPM_MIC("SoC DMIC", NULL),
 };
 	{ "IN1P", NULL, "Headset Mic" },
 };
-static const struct snd_soc_dapm_route speaker_map[] = {
-	/* speaker */
-	{ "Spk", NULL, "Speaker" },
-};
 static const struct snd_soc_dapm_route speaker_map_lr[] = {
 	{ "Left Spk", NULL, "Left SPO" },
 	{ "Right Spk", NULL, "Right SPO" },
 				       ARRAY_SIZE(speaker_map_lr));
 }
-static int speaker_codec_init(struct snd_soc_pcm_runtime *rtd)
-{
-	struct snd_soc_card *card = rtd->card;
-	int ret;
-	ret = snd_soc_dapm_new_controls(&card->dapm, speaker_widgets,
-					ARRAY_SIZE(speaker_widgets));
-	if (ret) {
-		dev_err(rtd->dev, "unable to add dapm controls, ret %d\n", ret);
-		/* Don't need to add routes if widget addition failed */
-		return ret;
-	}
-	ret = snd_soc_add_card_controls(card, speaker_controls,
-					ARRAY_SIZE(speaker_controls));
-	if (ret) {
-		dev_err(rtd->dev, "unable to add card controls, ret %d\n", ret);
-		return ret;
-	}
-	ret = snd_soc_dapm_add_routes(&card->dapm, speaker_map,
-				      ARRAY_SIZE(speaker_map));
-	if (ret)
-		dev_err(rtd->dev, "Speaker map addition failed: %d\n", ret);
-	return ret;
-}
 static int dmic_init(struct snd_soc_pcm_runtime *rtd)
 {
 	struct snd_soc_card *card = rtd->card;
 	}
 };
-static struct snd_soc_dai_link_component max98360a_component[] = {
-	{
-		.name = "MX98360A:00",
-		.dai_name = "HiFi",
-	}
-};
 static struct snd_soc_dai_link_component rt1015_components[] = {
 	{
 		.name = "i2c-10EC1015:00",
 			links[id].dpcm_capture = 1;
 		} else if (sof_rt5682_quirk &
 				SOF_MAX98360A_SPEAKER_AMP_PRESENT) {
-			links[id].codecs = max98360a_component;
+			max_98360a_dai_link(&links[id]);
-			links[id].num_codecs = ARRAY_SIZE(max98360a_component);
-			links[id].init = speaker_codec_init;
 		} else if (sof_rt5682_quirk &
 				SOF_RT1011_SPEAKER_AMP_PRESENT) {
 			sof_rt1011_dai_link(&links[id]);

sound/soc/intel/boards/sof_sdw.c+87−18

 #include <sound/soc.h>
 #include <sound/soc-acpi.h>
 #include "sof_sdw_common.h"
+#include "../../codecs/rt711.h"
-unsigned long sof_sdw_quirk = SOF_RT711_JD_SRC_JD1;
+unsigned long sof_sdw_quirk = RT711_JD1;
 static int quirk_override = -1;
 module_param_named(quirk, quirk_override, int, 0444);
 MODULE_PARM_DESC(quirk, "Board-specific quirk override");
 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
 			DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "09C6")
 		},
-		.driver_data = (void *)(SOF_RT711_JD_SRC_JD2 |
+		.driver_data = (void *)(RT711_JD2 |
 					SOF_RT715_DAI_ID_FIX),
 	},
 	{
 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
 			DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0983")
 		},
-		.driver_data = (void *)(SOF_RT711_JD_SRC_JD2 |
+		.driver_data = (void *)(RT711_JD2 |
 					SOF_RT715_DAI_ID_FIX),
 	},
 	{
 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
 			DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "098F"),
 		},
-		.driver_data = (void *)(SOF_RT711_JD_SRC_JD2 |
+		.driver_data = (void *)(RT711_JD2 |
 					SOF_RT715_DAI_ID_FIX |
 					SOF_SDW_FOUR_SPK),
 	},
 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
 			DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0990"),
 		},
-		.driver_data = (void *)(SOF_RT711_JD_SRC_JD2 |
+		.driver_data = (void *)(RT711_JD2 |
 					SOF_RT715_DAI_ID_FIX |
 					SOF_SDW_FOUR_SPK),
 	},
 				  "Tiger Lake Client Platform"),
 		},
 		.driver_data = (void *)(SOF_SDW_TGL_HDMI |
-					SOF_RT711_JD_SRC_JD1 |
+					RT711_JD1 |
 					SOF_SDW_PCH_DMIC |
 					SOF_SSP_PORT(SOF_I2S_SSP2)),
 	},
 			DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0A3E")
 		},
 		.driver_data = (void *)(SOF_SDW_TGL_HDMI |
-					SOF_RT711_JD_SRC_JD2 |
+					RT711_JD2 |
 					SOF_RT715_DAI_ID_FIX),
 	},
+	{
+		/* Dell XPS 9710 */
+		.callback = sof_sdw_quirk_cb,
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
+			DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0A5D")
+		},
+		.driver_data = (void *)(SOF_SDW_TGL_HDMI |
+					RT711_JD2 |
+					SOF_RT715_DAI_ID_FIX |
+					SOF_SDW_FOUR_SPK),
+	},
 	{
 		.callback = sof_sdw_quirk_cb,
 		.matches = {
 			DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0A5E")
 		},
 		.driver_data = (void *)(SOF_SDW_TGL_HDMI |
-					SOF_RT711_JD_SRC_JD2 |
+					RT711_JD2 |
 					SOF_RT715_DAI_ID_FIX |
 					SOF_SDW_FOUR_SPK),
 	},
 		},
 		.driver_data = (void *)(SOF_SDW_TGL_HDMI |
 					SOF_SDW_PCH_DMIC |
-					SOF_RT711_JD_SRC_JD2),
+					RT711_JD2),
+	},
+	{
+		/* NUC15 'Bishop County' LAPBC510 and LAPBC710 skews */
+		.callback = sof_sdw_quirk_cb,
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Intel(R) Client Systems"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "LAPBC"),
+		},
+		.driver_data = (void *)(SOF_SDW_TGL_HDMI |
+					SOF_SDW_PCH_DMIC |
+					RT711_JD1),
 	},
 	/* TigerLake-SDCA devices */
 	{
 			DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0A32")
 		},
 		.driver_data = (void *)(SOF_SDW_TGL_HDMI |
-					SOF_RT711_JD_SRC_JD2 |
+					RT711_JD2 |
 					SOF_RT715_DAI_ID_FIX |
 					SOF_SDW_FOUR_SPK),
 	},
 			DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
 			DMI_MATCH(DMI_PRODUCT_NAME, "Alder Lake Client Platform"),
 		},
-		.driver_data = (void *)(SOF_RT711_JD_SRC_JD1 |
+		.driver_data = (void *)(RT711_JD2_100K |
 					SOF_SDW_TGL_HDMI |
 					SOF_RT715_DAI_ID_FIX |
 					SOF_BT_OFFLOAD_SSP(2) |
 	.shutdown = sdw_shutdown,
 };
+static int sof_sdw_mic_codec_mockup_init(struct snd_soc_card *card,
+					 const struct snd_soc_acpi_link_adr *link,
+					 struct snd_soc_dai_link *dai_links,
+					 struct sof_sdw_codec_info *info,
+					 bool playback)
+{
+	/*
+	 * force DAI link to use same ID as RT715 and DMIC
+	 * to reuse topologies
+	 */
+	dai_links->id = SDW_DMIC_DAI_ID;
+	return 0;
+}
 static struct sof_sdw_codec_info codec_info_list[] = {
 	{
 		.part_id = 0x700,
 		.dai_name = "rt5682-sdw",
 		.init = sof_sdw_rt5682_init,
 	},
+	{
+		.part_id = 0xaaaa, /* generic codec mockup */
+		.version_id = 0,
+		.direction = {true, true},
+		.dai_name = "sdw-mockup-aif1",
+		.init = NULL,
+	},
+	{
+		.part_id = 0xaa55, /* headset codec mockup */
+		.version_id = 0,
+		.direction = {true, true},
+		.dai_name = "sdw-mockup-aif1",
+		.init = NULL,
+	},
+	{
+		.part_id = 0x55aa, /* amplifier mockup */
+		.version_id = 0,
+		.direction = {true, false},
+		.dai_name = "sdw-mockup-aif1",
+		.init = NULL,
+	},
+	{
+		.part_id = 0x5555,
+		.version_id = 0,
+		.direction = {false, true},
+		.dai_name = "sdw-mockup-aif1",
+		.init = sof_sdw_mic_codec_mockup_init,
+	},
 };
 static inline int find_codec_info_part(u64 adr)
 	return 0;
 }
-static int set_codec_init_func(const struct snd_soc_acpi_link_adr *link,
+static int set_codec_init_func(struct snd_soc_card *card,
+			       const struct snd_soc_acpi_link_adr *link,
 			       struct snd_soc_dai_link *dai_links,
 			       bool playback, int group_id)
 {
 			if (link->adr_d[i].endpoints->group_id != group_id)
 				continue;
 			if (codec_info_list[codec_index].init)
-				codec_info_list[codec_index].init(link,
+				codec_info_list[codec_index].init(card,
+						link,
 						dai_links,
 						&codec_info_list[codec_index],
 						playback);
 	return 0;
 }
-static int create_sdw_dailink(struct device *dev, int *be_index,
+static int create_sdw_dailink(struct snd_soc_card *card,
+			      struct device *dev, int *be_index,
 			      struct snd_soc_dai_link *dai_links,
 			      int sdw_be_num, int sdw_cpu_dai_num,
 			      struct snd_soc_dai_link_component *cpus,
 			      codecs, codec_num,
 			      NULL, &sdw_ops);
-		ret = set_codec_init_func(link, dai_links + (*be_index)++,
+		ret = set_codec_init_func(card, link, dai_links + (*be_index)++,
 					  playback, group_id);
 		if (ret < 0) {
 			dev_err(dev, "failed to init codec %d", codec_index);
 		    group_generated[endpoint->group_id])
 			continue;
-		ret = create_sdw_dailink(dev, &be_id, links, sdw_be_num,
+		ret = create_sdw_dailink(card, dev, &be_id, links, sdw_be_num,
 					 sdw_cpu_dai_num, cpus, adr_link,
 					 &cpu_id, group_generated,
 					 codec_conf, codec_conf_count,
 			      ssp_components, 1,
 			      NULL, info->ops);
-		ret = info->init(NULL, links + link_id, info, 0);
+		ret = info->init(card, NULL, links + link_id, info, 0);
 		if (ret < 0)
 			return ret;
 		for_each_card_prelinks(card, j, link) {
 			if (!strcmp(link->codecs[0].dai_name,
 				    codec_info_list[i].dai_name)) {
-				ret = codec_info_list[i].exit(&pdev->dev, link);
+				ret = codec_info_list[i].exit(card, link);
 				if (ret)
 					dev_warn(&pdev->dev,
 						 "codec exit failed %d\n",

sound/soc/intel/boards/sof_sdw_common.h+35−29

 /* 8 combinations with 4 links + unused group 0 */
 #define SDW_MAX_GROUPS 9
-enum {
-	SOF_RT711_JD_SRC_JD1 = 1,
-	SOF_RT711_JD_SRC_JD2 = 2,
-};
 enum {
 	SOF_PRE_TGL_HDMI_COUNT = 3,
 	SOF_TGL_HDMI_COUNT = 4,
 	SOF_I2S_SSP5 = BIT(5),
 };
-#define SOF_RT711_JDSRC(quirk)		((quirk) & GENMASK(1, 0))
+#define SOF_RT711_JDSRC(quirk)		((quirk) & GENMASK(3, 0))
-#define SOF_SDW_FOUR_SPK		BIT(2)
+#define SOF_SDW_FOUR_SPK		BIT(4)
-#define SOF_SDW_TGL_HDMI		BIT(3)
+#define SOF_SDW_TGL_HDMI		BIT(5)
-#define SOF_SDW_PCH_DMIC		BIT(4)
+#define SOF_SDW_PCH_DMIC		BIT(6)
-#define SOF_SSP_PORT(x)		(((x) & GENMASK(5, 0)) << 5)
+#define SOF_SSP_PORT(x)		(((x) & GENMASK(5, 0)) << 7)
-#define SOF_SSP_GET_PORT(quirk)	(((quirk) >> 5) & GENMASK(5, 0))
+#define SOF_SSP_GET_PORT(quirk)	(((quirk) >> 7) & GENMASK(5, 0))
-#define SOF_RT715_DAI_ID_FIX		BIT(11)
+#define SOF_RT715_DAI_ID_FIX		BIT(13)
-#define SOF_SDW_NO_AGGREGATION		BIT(12)
+#define SOF_SDW_NO_AGGREGATION		BIT(14)
 /* BT audio offload: reserve 3 bits for future */
-#define SOF_BT_OFFLOAD_SSP_SHIFT	13
+#define SOF_BT_OFFLOAD_SSP_SHIFT	15
-#define SOF_BT_OFFLOAD_SSP_MASK	(GENMASK(15, 13))
+#define SOF_BT_OFFLOAD_SSP_MASK	(GENMASK(17, 15))
 #define SOF_BT_OFFLOAD_SSP(quirk)	\
 	(((quirk) << SOF_BT_OFFLOAD_SSP_SHIFT) & SOF_BT_OFFLOAD_SSP_MASK)
-#define SOF_SSP_BT_OFFLOAD_PRESENT	BIT(16)
+#define SOF_SSP_BT_OFFLOAD_PRESENT	BIT(18)
 struct sof_sdw_codec_info {
 	const int part_id;
 	const char *dai_name;
 	const struct snd_soc_ops *ops;
-	int  (*init)(const struct snd_soc_acpi_link_adr *link,
+	int  (*init)(struct snd_soc_card *card,
+		     const struct snd_soc_acpi_link_adr *link,
 		     struct snd_soc_dai_link *dai_links,
 		     struct sof_sdw_codec_info *info,
 		     bool playback);
-	int (*exit)(struct device *dev, struct snd_soc_dai_link *dai_link);
+	int (*exit)(struct snd_soc_card *card, struct snd_soc_dai_link *dai_link);
 	bool late_probe;
 	int (*codec_card_late_probe)(struct snd_soc_card *card);
 };
 	struct list_head hdmi_pcm_list;
 	bool idisp_codec;
 	struct snd_soc_jack sdw_headset;
+	struct device *headset_codec_dev; /* only one headset per card */
 };
 extern unsigned long sof_sdw_quirk;
 int sof_sdw_dmic_init(struct snd_soc_pcm_runtime *rtd);
 /* RT711 support */
-int sof_sdw_rt711_init(const struct snd_soc_acpi_link_adr *link,
+int sof_sdw_rt711_init(struct snd_soc_card *card,
+		       const struct snd_soc_acpi_link_adr *link,
 		       struct snd_soc_dai_link *dai_links,
 		       struct sof_sdw_codec_info *info,
 		       bool playback);
-int sof_sdw_rt711_exit(struct device *dev, struct snd_soc_dai_link *dai_link);
+int sof_sdw_rt711_exit(struct snd_soc_card *card, struct snd_soc_dai_link *dai_link);
 /* RT711-SDCA support */
-int sof_sdw_rt711_sdca_init(const struct snd_soc_acpi_link_adr *link,
+int sof_sdw_rt711_sdca_init(struct snd_soc_card *card,
+			    const struct snd_soc_acpi_link_adr *link,
 			    struct snd_soc_dai_link *dai_links,
 			    struct sof_sdw_codec_info *info,
 			    bool playback);
-int sof_sdw_rt711_sdca_exit(struct device *dev, struct snd_soc_dai_link *dai_link);
+int sof_sdw_rt711_sdca_exit(struct snd_soc_card *card, struct snd_soc_dai_link *dai_link);
 /* RT700 support */
-int sof_sdw_rt700_init(const struct snd_soc_acpi_link_adr *link,
+int sof_sdw_rt700_init(struct snd_soc_card *card,
+		       const struct snd_soc_acpi_link_adr *link,
 		       struct snd_soc_dai_link *dai_links,
 		       struct sof_sdw_codec_info *info,
 		       bool playback);
 /* RT1308 support */
 extern struct snd_soc_ops sof_sdw_rt1308_i2s_ops;
-int sof_sdw_rt1308_init(const struct snd_soc_acpi_link_adr *link,
+int sof_sdw_rt1308_init(struct snd_soc_card *card,
+			const struct snd_soc_acpi_link_adr *link,
 			struct snd_soc_dai_link *dai_links,
 			struct sof_sdw_codec_info *info,
 			bool playback);
 /* RT1316 support */
-int sof_sdw_rt1316_init(const struct snd_soc_acpi_link_adr *link,
+int sof_sdw_rt1316_init(struct snd_soc_card *card,
+			const struct snd_soc_acpi_link_adr *link,
 			struct snd_soc_dai_link *dai_links,
 			struct sof_sdw_codec_info *info,
 			bool playback);
 /* RT715 support */
-int sof_sdw_rt715_init(const struct snd_soc_acpi_link_adr *link,
+int sof_sdw_rt715_init(struct snd_soc_card *card,
+		       const struct snd_soc_acpi_link_adr *link,
 		       struct snd_soc_dai_link *dai_links,
 		       struct sof_sdw_codec_info *info,
 		       bool playback);
 /* RT715-SDCA support */
-int sof_sdw_rt715_sdca_init(const struct snd_soc_acpi_link_adr *link,
+int sof_sdw_rt715_sdca_init(struct snd_soc_card *card,
+			    const struct snd_soc_acpi_link_adr *link,
 			    struct snd_soc_dai_link *dai_links,
 			    struct sof_sdw_codec_info *info,
 			    bool playback);
 /* MAX98373 support */
-int sof_sdw_mx8373_init(const struct snd_soc_acpi_link_adr *link,
+int sof_sdw_mx8373_init(struct snd_soc_card *card,
+			const struct snd_soc_acpi_link_adr *link,
 			struct snd_soc_dai_link *dai_links,
 			struct sof_sdw_codec_info *info,
 			bool playback);
 int sof_sdw_mx8373_late_probe(struct snd_soc_card *card);
 /* RT5682 support */
-int sof_sdw_rt5682_init(const struct snd_soc_acpi_link_adr *link,
+int sof_sdw_rt5682_init(struct snd_soc_card *card,
+			const struct snd_soc_acpi_link_adr *link,
 			struct snd_soc_dai_link *dai_links,
 			struct sof_sdw_codec_info *info,
 			bool playback);

sound/soc/intel/boards/sof_sdw_max98373.c+4−3

 static int mx8373_sdw_prepare(struct snd_pcm_substream *substream)
 {
-	int ret = 0;
+	int ret;
 	/* according to soc_pcm_prepare dai link prepare is called first */
 	ret = sdw_prepare(substream);
 static int mx8373_sdw_hw_free(struct snd_pcm_substream *substream)
 {
-	int ret = 0;
+	int ret;
 	/* according to soc_pcm_hw_free dai link free is called first */
 	ret = sdw_hw_free(substream);
 	.shutdown = sdw_shutdown,
 };
-int sof_sdw_mx8373_init(const struct snd_soc_acpi_link_adr *link,
+int sof_sdw_mx8373_init(struct snd_soc_card *card,
+			const struct snd_soc_acpi_link_adr *link,
 			struct snd_soc_dai_link *dai_links,
 			struct sof_sdw_codec_info *info,
 			bool playback)

sound/soc/intel/boards/sof_sdw_rt1308.c+2−1

@@ -127,7 +127,8 @@ struct snd_soc_ops sof_sdw_rt1308_i2s_ops = { · 126 unmodified lines
127	.hw_params = rt1308_i2s_hw_params,	127	.hw_params = rt1308_i2s_hw_params,
128	};	128	};
129		129
130	int sof_sdw_rt1308_init(const struct snd_soc_acpi_link_adr *link,	130	int sof_sdw_rt1308_init(struct snd_soc_card *card,
		131	const struct snd_soc_acpi_link_adr *link,
131	struct snd_soc_dai_link *dai_links,	132	struct snd_soc_dai_link *dai_links,
132	struct sof_sdw_codec_info *info,	133	struct sof_sdw_codec_info *info,
133	bool playback)	134	bool playback)

sound/soc/intel/boards/sof_sdw_rt1316.c+2−1

@@ -89,7 +89,8 @@ static int all_spk_init(struct snd_soc_pcm_runtime *rtd) · 88 unmodified lines
89	return second_spk_init(rtd);	89	return second_spk_init(rtd);
90	}	90	}
91		91
92	int sof_sdw_rt1316_init(const struct snd_soc_acpi_link_adr *link,	92	int sof_sdw_rt1316_init(struct snd_soc_card *card,
		93	const struct snd_soc_acpi_link_adr *link,
93	struct snd_soc_dai_link *dai_links,	94	struct snd_soc_dai_link *dai_links,
94	struct sof_sdw_codec_info *info,	95	struct sof_sdw_codec_info *info,
95	bool playback)	96	bool playback)

sound/soc/intel/boards/sof_sdw_rt5682.c+2−1

@@ -111,7 +111,8 @@ static int rt5682_rtd_init(struct snd_soc_pcm_runtime *rtd) · 110 unmodified lines
111	return ret;	111	return ret;
112	}	112	}
113		113
114	int sof_sdw_rt5682_init(const struct snd_soc_acpi_link_adr *link,	114	int sof_sdw_rt5682_init(struct snd_soc_card *card,
		115	const struct snd_soc_acpi_link_adr *link,
115	struct snd_soc_dai_link *dai_links,	116	struct snd_soc_dai_link *dai_links,
116	struct sof_sdw_codec_info *info,	117	struct sof_sdw_codec_info *info,
117	bool playback)	118	bool playback)

sound/soc/intel/boards/sof_sdw_rt700.c+2−1

@@ -110,7 +110,8 @@ static int rt700_rtd_init(struct snd_soc_pcm_runtime *rtd) · 109 unmodified lines
110	return ret;	110	return ret;
111	}	111	}
112		112
113	int sof_sdw_rt700_init(const struct snd_soc_acpi_link_adr *link,	113	int sof_sdw_rt700_init(struct snd_soc_card *card,
		114	const struct snd_soc_acpi_link_adr *link,
114	struct snd_soc_dai_link *dai_links,	115	struct snd_soc_dai_link *dai_links,
115	struct sof_sdw_codec_info *info,	116	struct sof_sdw_codec_info *info,
116	bool playback)	117	bool playback)

sound/soc/intel/boards/sof_sdw_rt711.c+28−23

@@ -21,23 +21,23 @@ · 20 unmodified lines
21	* Note this MUST be called before snd_soc_register_card(), so that the props	21	* Note this MUST be called before snd_soc_register_card(), so that the props
22	* are in place before the codec component driver's probe function parses them.	22	* are in place before the codec component driver's probe function parses them.
23	*/	23	*/
24	static int rt711_add_codec_device_props(const char *sdw_dev_name)	24	static int rt711_add_codec_device_props(struct device *sdw_dev)
25	{	25	{
26	struct property_entry props[MAX_NO_PROPS] = {};	26	struct property_entry props[MAX_NO_PROPS] = {};
27	struct device *sdw_dev;	27	struct fwnode_handle *fwnode;
28	int ret;	28	int ret;
29		29
30	sdw_dev = bus_find_device_by_name(&sdw_bus_type, NULL, sdw_dev_name);	30	if (!SOF_RT711_JDSRC(sof_sdw_quirk))
31	if (!sdw_dev)	31	return 0;
32	return -EPROBE_DEFER;	32	props[0] = PROPERTY_ENTRY_U32("realtek,jd-src", SOF_RT711_JDSRC(sof_sdw_quirk));
33		33
34	if (SOF_RT711_JDSRC(sof_sdw_quirk)) {	34	fwnode = fwnode_create_software_node(props, NULL);
35	props[0] = PROPERTY_ENTRY_U32("realtek,jd-src",	35	if (IS_ERR(fwnode))
36	SOF_RT711_JDSRC(sof_sdw_quirk));	36	return PTR_ERR(fwnode);
37	}	37
		38	ret = device_add_software_node(sdw_dev, to_software_node(fwnode));
38		39
39	ret = device_add_properties(sdw_dev, props);	40	fwnode_handle_put(fwnode);
40	put_device(sdw_dev);
41		41
42	return ret;	42	return ret;
43	}	43	}
@@ -135,26 +135,24 @@ static int rt711_rtd_init(struct snd_soc_pcm_runtime *rtd) · 91 unmodified lines
135	return ret;	135	return ret;
136	}	136	}
137		137
138	int sof_sdw_rt711_exit(struct device dev, struct snd_soc_dai_link dai_link)	138	int sof_sdw_rt711_exit(struct snd_soc_card card, struct snd_soc_dai_link dai_link)
139	{	139	{
140	struct device *sdw_dev;	140	struct mc_private *ctx = snd_soc_card_get_drvdata(card);
141
142	sdw_dev = bus_find_device_by_name(&sdw_bus_type, NULL,
143	dai_link->codecs[0].name);
144	if (!sdw_dev)
145	return -EINVAL;
146		141
147	device_remove_properties(sdw_dev);	142	device_remove_software_node(ctx->headset_codec_dev);
148	put_device(sdw_dev);	143	put_device(ctx->headset_codec_dev);
149		144
150	return 0;	145	return 0;
151	}	146	}
152		147
153	int sof_sdw_rt711_init(const struct snd_soc_acpi_link_adr *link,	148	int sof_sdw_rt711_init(struct snd_soc_card *card,
		149	const struct snd_soc_acpi_link_adr *link,
154	struct snd_soc_dai_link *dai_links,	150	struct snd_soc_dai_link *dai_links,
155	struct sof_sdw_codec_info *info,	151	struct sof_sdw_codec_info *info,
156	bool playback)	152	bool playback)
157	{	153	{
		154	struct mc_private *ctx = snd_soc_card_get_drvdata(card);
		155	struct device *sdw_dev;
158	int ret;	156	int ret;
159		157
160	/*	158	/*
@@ -164,9 +162,16 @@ int sof_sdw_rt711_init(const struct snd_soc_acpi_link_adr *link, · 3 unmodified lines
164	if (!playback)	162	if (!playback)
165	return 0;	163	return 0;
166		164
167	ret = rt711_add_codec_device_props(dai_links->codecs[0].name);	165	sdw_dev = bus_find_device_by_name(&sdw_bus_type, NULL, dai_links->codecs[0].name);
168	if (ret < 0)	166	if (!sdw_dev)
		167	return -EPROBE_DEFER;
		168
		169	ret = rt711_add_codec_device_props(sdw_dev);
		170	if (ret < 0) {
		171	put_device(sdw_dev);
169	return ret;	172	return ret;
		173	}
		174	ctx->headset_codec_dev = sdw_dev;
170		175
171	dai_links->init = rt711_rtd_init;	176	dai_links->init = rt711_rtd_init;
172		177

sound/soc/intel/boards/sof_sdw_rt711_sdca.c+29−23

  * Note this MUST be called before snd_soc_register_card(), so that the props
  * are in place before the codec component driver's probe function parses them.
  */
-static int rt711_sdca_add_codec_device_props(const char *sdw_dev_name)
+static int rt711_sdca_add_codec_device_props(struct device *sdw_dev)
 {
 	struct property_entry props[MAX_NO_PROPS] = {};
-	struct device *sdw_dev;
+	struct fwnode_handle *fwnode;
 	int ret;
-	sdw_dev = bus_find_device_by_name(&sdw_bus_type, NULL, sdw_dev_name);
+	if (!SOF_RT711_JDSRC(sof_sdw_quirk))
-	if (!sdw_dev)
+		return 0;
-		return -EPROBE_DEFER;
-	if (SOF_RT711_JDSRC(sof_sdw_quirk)) {
+	props[0] = PROPERTY_ENTRY_U32("realtek,jd-src", SOF_RT711_JDSRC(sof_sdw_quirk));
-		props[0] = PROPERTY_ENTRY_U32("realtek,jd-src",
-					      SOF_RT711_JDSRC(sof_sdw_quirk));
-	}
-	ret = device_add_properties(sdw_dev, props);
+	fwnode = fwnode_create_software_node(props, NULL);
-	put_device(sdw_dev);
+	if (IS_ERR(fwnode))
+		return PTR_ERR(fwnode);
+	ret = device_add_software_node(sdw_dev, to_software_node(fwnode));
+	fwnode_handle_put(fwnode);
 	return ret;
 }
 	return ret;
 }
-int sof_sdw_rt711_sdca_exit(struct device *dev, struct snd_soc_dai_link *dai_link)
+int sof_sdw_rt711_sdca_exit(struct snd_soc_card *card, struct snd_soc_dai_link *dai_link)
 {
-	struct device *sdw_dev;
+	struct mc_private *ctx = snd_soc_card_get_drvdata(card);
-	sdw_dev = bus_find_device_by_name(&sdw_bus_type, NULL,
-					  dai_link->codecs[0].name);
-	if (!sdw_dev)
-		return -EINVAL;
-	device_remove_properties(sdw_dev);
+	device_remove_software_node(ctx->headset_codec_dev);
-	put_device(sdw_dev);
+	put_device(ctx->headset_codec_dev);
 	return 0;
 }
-int sof_sdw_rt711_sdca_init(const struct snd_soc_acpi_link_adr *link,
+int sof_sdw_rt711_sdca_init(struct snd_soc_card *card,
+			    const struct snd_soc_acpi_link_adr *link,
 			    struct snd_soc_dai_link *dai_links,
 			    struct sof_sdw_codec_info *info,
 			    bool playback)
 {
+	struct mc_private *ctx = snd_soc_card_get_drvdata(card);
+	struct device *sdw_dev;
 	int ret;
 	/*
 	if (!playback)
 		return 0;
-	ret = rt711_sdca_add_codec_device_props(dai_links->codecs[0].name);
+	sdw_dev = bus_find_device_by_name(&sdw_bus_type, NULL, dai_links->codecs[0].name);
-	if (ret < 0)
+	if (!sdw_dev)
+		return -EPROBE_DEFER;
+	ret = rt711_sdca_add_codec_device_props(sdw_dev);
+	if (ret < 0) {
+		put_device(sdw_dev);
 		return ret;
+	}
+	ctx->headset_codec_dev = sdw_dev;
 	dai_links->init = rt711_sdca_rtd_init;

sound/soc/intel/boards/sof_sdw_rt715.c+2−1

@@ -24,7 +24,8 @@ static int rt715_rtd_init(struct snd_soc_pcm_runtime *rtd) · 23 unmodified lines
24	return 0;	24	return 0;
25	}	25	}
26		26
27	int sof_sdw_rt715_init(const struct snd_soc_acpi_link_adr *link,	27	int sof_sdw_rt715_init(struct snd_soc_card *card,
		28	const struct snd_soc_acpi_link_adr *link,
28	struct snd_soc_dai_link *dai_links,	29	struct snd_soc_dai_link *dai_links,
29	struct sof_sdw_codec_info *info,	30	struct sof_sdw_codec_info *info,
30	bool playback)	31	bool playback)

sound/soc/intel/boards/sof_sdw_rt715_sdca.c+2−1

@@ -24,7 +24,8 @@ static int rt715_sdca_rtd_init(struct snd_soc_pcm_runtime *rtd) · 23 unmodified lines
24	return 0;	24	return 0;
25	}	25	}
26		26
27	int sof_sdw_rt715_sdca_init(const struct snd_soc_acpi_link_adr *link,	27	int sof_sdw_rt715_sdca_init(struct snd_soc_card *card,
		28	const struct snd_soc_acpi_link_adr *link,
28	struct snd_soc_dai_link *dai_links,	29	struct snd_soc_dai_link *dai_links,
29	struct sof_sdw_codec_info *info,	30	struct sof_sdw_codec_info *info,
30	bool playback)	31	bool playback)

sound/soc/intel/common/Makefile+2−1

@@ -9,7 +9,8 @@ snd-soc-acpi-intel-match-objs := soc-acpi-intel-byt-match.o soc-acpi-intel-cht-m · 8 unmodified lines
9	soc-acpi-intel-cml-match.o soc-acpi-intel-icl-match.o \	9	soc-acpi-intel-cml-match.o soc-acpi-intel-icl-match.o \
10	soc-acpi-intel-tgl-match.o soc-acpi-intel-ehl-match.o \	10	soc-acpi-intel-tgl-match.o soc-acpi-intel-ehl-match.o \
11	soc-acpi-intel-jsl-match.o soc-acpi-intel-adl-match.o \	11	soc-acpi-intel-jsl-match.o soc-acpi-intel-adl-match.o \
12	soc-acpi-intel-hda-match.o	12	soc-acpi-intel-hda-match.o \
		13	soc-acpi-intel-sdw-mockup-match.o
13		14
14	obj-$(CONFIG_SND_SOC_INTEL_SST) += snd-soc-sst-dsp.o snd-soc-sst-ipc.o	15	obj-$(CONFIG_SND_SOC_INTEL_SST) += snd-soc-sst-dsp.o snd-soc-sst-ipc.o
15	obj-$(CONFIG_SND_SOC_ACPI_INTEL_MATCH) += snd-soc-acpi-intel-match.o	16	obj-$(CONFIG_SND_SOC_ACPI_INTEL_MATCH) += snd-soc-acpi-intel-match.o

sound/soc/intel/common/soc-acpi-intel-cnl-match.c+15−0

@@ -9,6 +9,7 @@ · 8 unmodified lines
9	#include <sound/soc-acpi.h>	9	#include <sound/soc-acpi.h>
10	#include <sound/soc-acpi-intel-match.h>	10	#include <sound/soc-acpi-intel-match.h>
11	#include "../skylake/skl.h"	11	#include "../skylake/skl.h"
		12	#include "soc-acpi-intel-sdw-mockup-match.h"
12		13
13	static struct skl_machine_pdata cnl_pdata = {	14	static struct skl_machine_pdata cnl_pdata = {
14	.use_tplg_pcm = true,	15	.use_tplg_pcm = true,
@@ -60,6 +61,20 @@ struct snd_soc_acpi_mach snd_soc_acpi_intel_cnl_sdw_machines[] = { · 45 unmodified lines
60	.sof_fw_filename = "sof-cnl.ri",	61	.sof_fw_filename = "sof-cnl.ri",
61	.sof_tplg_filename = "sof-cnl-rt5682-sdw2.tplg"	62	.sof_tplg_filename = "sof-cnl-rt5682-sdw2.tplg"
62	},	63	},
		64	{
		65	.link_mask = GENMASK(3, 0),
		66	.links = sdw_mockup_headset_2amps_mic,
		67	.drv_name = "sof_sdw",
		68	.sof_fw_filename = "sof-cnl.ri",
		69	.sof_tplg_filename = "sof-cml-rt711-rt1308-rt715.tplg",
		70	},
		71	{
		72	.link_mask = BIT(0) \| BIT(1) \| BIT(3),
		73	.links = sdw_mockup_headset_1amp_mic,
		74	.drv_name = "sof_sdw",
		75	.sof_fw_filename = "sof-cnl.ri",
		76	.sof_tplg_filename = "sof-cml-rt711-rt1308-mono-rt715.tplg",
		77	},
63	{}	78	{}
64	};	79	};
65	EXPORT_SYMBOL_GPL(snd_soc_acpi_intel_cnl_sdw_machines);	80	EXPORT_SYMBOL_GPL(snd_soc_acpi_intel_cnl_sdw_machines);

sound/soc/intel/common/soc-acpi-intel-jsl-match.c+8−0

@@ -73,6 +73,14 @@ struct snd_soc_acpi_mach snd_soc_acpi_intel_jsl_machines[] = { · 72 unmodified lines
73	.quirk_data = &mx98360a_spk,	73	.quirk_data = &mx98360a_spk,
74	.sof_tplg_filename = "sof-jsl-rt5682-mx98360a.tplg",	74	.sof_tplg_filename = "sof-jsl-rt5682-mx98360a.tplg",
75	},	75	},
		76	{
		77	.id = "10134242",
		78	.drv_name = "jsl_cs4242_mx98360a",
		79	.sof_fw_filename = "sof-jsl.ri",
		80	.machine_quirk = snd_soc_acpi_codec_list,
		81	.quirk_data = &mx98360a_spk,
		82	.sof_tplg_filename = "sof-jsl-cs42l42-mx98360a.tplg",
		83	},
76	{},	84	{},
77	};	85	};
78	EXPORT_SYMBOL_GPL(snd_soc_acpi_intel_jsl_machines);	86	EXPORT_SYMBOL_GPL(snd_soc_acpi_intel_jsl_machines);

sound/soc/intel/common/soc-acpi-intel-sdw-mockup-match.c+166−0

@@ -0,0 +1,166 @@
	1	// SPDX-License-Identifier: GPL-2.0-only
	2	//
	3	// soc-acpi-intel-sdw-mockup-match.c - tables and support for SoundWire
	4	// mockup device ACPI enumeration.
	5	//
	6	// Copyright (c) 2021, Intel Corporation.
	7	//
	8
	9	#include <sound/soc-acpi.h>
	10	#include <sound/soc-acpi-intel-match.h>
	11	#include "soc-acpi-intel-sdw-mockup-match.h"
	12
	13	static const struct snd_soc_acpi_endpoint sdw_mockup_single_endpoint = {
	14	.num = 0,
	15	.aggregated = 0,
	16	.group_position = 0,
	17	.group_id = 0,
	18	};
	19
	20	static const struct snd_soc_acpi_endpoint sdw_mockup_l_endpoint = {
	21	.num = 0,
	22	.aggregated = 1,
	23	.group_position = 0,
	24	.group_id = 1,
	25	};
	26
	27	static const struct snd_soc_acpi_endpoint sdw_mockup_r_endpoint = {
	28	.num = 0,
	29	.aggregated = 1,
	30	.group_position = 1,
	31	.group_id = 1,
	32	};
	33
	34	static const struct snd_soc_acpi_adr_device sdw_mockup_headset_0_adr[] = {
	35	{
	36	.adr = 0x0000000105AA5500ull,
	37	.num_endpoints = 1,
	38	.endpoints = &sdw_mockup_single_endpoint,
	39	.name_prefix = "sdw_mockup_headset0"
	40	}
	41	};
	42
	43	static const struct snd_soc_acpi_adr_device sdw_mockup_headset_1_adr[] = {
	44	{
	45	.adr = 0x0001000105AA5500ull,
	46	.num_endpoints = 1,
	47	.endpoints = &sdw_mockup_single_endpoint,
	48	.name_prefix = "sdw_mockup_headset1"
	49	}
	50	};
	51
	52	static const struct snd_soc_acpi_adr_device sdw_mockup_amp_1_adr[] = {
	53	{
	54	.adr = 0x000100010555AA00ull,
	55	.num_endpoints = 1,
	56	.endpoints = &sdw_mockup_single_endpoint,
	57	.name_prefix = "sdw_mockup_amp1"
	58	}
	59	};
	60
	61	static const struct snd_soc_acpi_adr_device sdw_mockup_amp_2_adr[] = {
	62	{
	63	.adr = 0x000200010555AA00ull,
	64	.num_endpoints = 1,
	65	.endpoints = &sdw_mockup_single_endpoint,
	66	.name_prefix = "sdw_mockup_amp2"
	67	}
	68	};
	69
	70	static const struct snd_soc_acpi_adr_device sdw_mockup_mic_0_adr[] = {
	71	{
	72	.adr = 0x0000000105555500ull,
	73	.num_endpoints = 1,
	74	.endpoints = &sdw_mockup_single_endpoint,
	75	.name_prefix = "sdw_mockup_mic0"
	76	}
	77	};
	78
	79	static const struct snd_soc_acpi_adr_device sdw_mockup_mic_3_adr[] = {
	80	{
	81	.adr = 0x0003000105555500ull,
	82	.num_endpoints = 1,
	83	.endpoints = &sdw_mockup_single_endpoint,
	84	.name_prefix = "sdw_mockup_mic3"
	85	}
	86	};
	87
	88	static const struct snd_soc_acpi_adr_device sdw_mockup_amp_1_group1_adr[] = {
	89	{
	90	.adr = 0x000100010555AA00ull,
	91	.num_endpoints = 1,
	92	.endpoints = &sdw_mockup_l_endpoint,
	93	.name_prefix = "sdw_mockup_amp1_l"
	94	}
	95	};
	96
	97	static const struct snd_soc_acpi_adr_device sdw_mockup_amp_2_group1_adr[] = {
	98	{
	99	.adr = 0x000200010555AA00ull,
	100	.num_endpoints = 1,
	101	.endpoints = &sdw_mockup_r_endpoint,
	102	.name_prefix = "sdw_mockup_amp2_r"
	103	}
	104	};
	105
	106	const struct snd_soc_acpi_link_adr sdw_mockup_headset_1amp_mic[] = {
	107	{
	108	.mask = BIT(0),
	109	.num_adr = ARRAY_SIZE(sdw_mockup_headset_0_adr),
	110	.adr_d = sdw_mockup_headset_0_adr,
	111	},
	112	{
	113	.mask = BIT(1),
	114	.num_adr = ARRAY_SIZE(sdw_mockup_amp_1_adr),
	115	.adr_d = sdw_mockup_amp_1_adr,
	116	},
	117	{
	118	.mask = BIT(3),
	119	.num_adr = ARRAY_SIZE(sdw_mockup_mic_3_adr),
	120	.adr_d = sdw_mockup_mic_3_adr,
	121	},
	122	{}
	123	};
	124
	125	const struct snd_soc_acpi_link_adr sdw_mockup_headset_2amps_mic[] = {
	126	{
	127	.mask = BIT(0),
	128	.num_adr = ARRAY_SIZE(sdw_mockup_headset_0_adr),
	129	.adr_d = sdw_mockup_headset_0_adr,
	130	},
	131	{
	132	.mask = BIT(1),
	133	.num_adr = ARRAY_SIZE(sdw_mockup_amp_1_group1_adr),
	134	.adr_d = sdw_mockup_amp_1_group1_adr,
	135	},
	136	{
	137	.mask = BIT(2),
	138	.num_adr = ARRAY_SIZE(sdw_mockup_amp_2_group1_adr),
	139	.adr_d = sdw_mockup_amp_2_group1_adr,
	140	},
	141	{
	142	.mask = BIT(3),
	143	.num_adr = ARRAY_SIZE(sdw_mockup_mic_3_adr),
	144	.adr_d = sdw_mockup_mic_3_adr,
	145	},
	146	{}
	147	};
	148
	149	const struct snd_soc_acpi_link_adr sdw_mockup_mic_headset_1amp[] = {
	150	{
	151	.mask = BIT(1),
	152	.num_adr = ARRAY_SIZE(sdw_mockup_headset_1_adr),
	153	.adr_d = sdw_mockup_headset_1_adr,
	154	},
	155	{
	156	.mask = BIT(2),
	157	.num_adr = ARRAY_SIZE(sdw_mockup_amp_2_adr),
	158	.adr_d = sdw_mockup_amp_2_adr,
	159	},
	160	{
	161	.mask = BIT(0),
	162	.num_adr = ARRAY_SIZE(sdw_mockup_mic_0_adr),
	163	.adr_d = sdw_mockup_mic_0_adr,
	164	},
	165	{}
	166	};

sound/soc/intel/common/soc-acpi-intel-sdw-mockup-match.h+17−0

@@ -0,0 +1,17 @@
	1	/* SPDX-License-Identifier: GPL-2.0-only */
	2	/*
	3	* soc-acpi-intel-sdw-mockup-match.h - tables and support for SoundWire
	4	* mockup device ACPI enumeration.
	5	*
	6	* Copyright (c) 2021, Intel Corporation.
	7	*
	8	*/
	9
	10	#ifndef _SND_SOC_ACPI_INTEL_SDW_MOCKUP_MATCH
	11	#define _SND_SOC_ACPI_INTEL_SDW_MOCKUP_MATCH
	12
	13	extern const struct snd_soc_acpi_link_adr sdw_mockup_headset_1amp_mic[];
	14	extern const struct snd_soc_acpi_link_adr sdw_mockup_headset_2amps_mic[];
	15	extern const struct snd_soc_acpi_link_adr sdw_mockup_mic_headset_1amp[];
	16
	17	#endif

sound/soc/intel/common/soc-acpi-intel-tgl-match.c+38−0

@@ -8,6 +8,7 @@ · 7 unmodified lines
8		8
9	#include <sound/soc-acpi.h>	9	#include <sound/soc-acpi.h>
10	#include <sound/soc-acpi-intel-match.h>	10	#include <sound/soc-acpi-intel-match.h>
		11	#include "soc-acpi-intel-sdw-mockup-match.h"
11		12
12	static const struct snd_soc_acpi_codecs tgl_codecs = {	13	static const struct snd_soc_acpi_codecs tgl_codecs = {
13	.num_codecs = 1,	14	.num_codecs = 1,
@@ -196,6 +197,15 @@ static const struct snd_soc_acpi_link_adr tgl_rvp[] = { · 182 unmodified lines
196	{}	197	{}
197	};	198	};
198		199
		200	static const struct snd_soc_acpi_link_adr tgl_rvp_headset_only[] = {
		201	{
		202	.mask = BIT(0),
		203	.num_adr = ARRAY_SIZE(rt711_0_adr),
		204	.adr_d = rt711_0_adr,
		205	},
		206	{}
		207	};
		208
199	static const struct snd_soc_acpi_link_adr tgl_hp[] = {	209	static const struct snd_soc_acpi_link_adr tgl_hp[] = {
200	{	210	{
201	.mask = BIT(0),	211	.mask = BIT(0),
@@ -351,6 +361,28 @@ EXPORT_SYMBOL_GPL(snd_soc_acpi_intel_tgl_machines); · 149 unmodified lines
351		361
352	/* this table is used when there is no I2S codec present */	362	/* this table is used when there is no I2S codec present */
353	struct snd_soc_acpi_mach snd_soc_acpi_intel_tgl_sdw_machines[] = {	363	struct snd_soc_acpi_mach snd_soc_acpi_intel_tgl_sdw_machines[] = {
		364	/* mockup tests need to be first */
		365	{
		366	.link_mask = GENMASK(3, 0),
		367	.links = sdw_mockup_headset_2amps_mic,
		368	.drv_name = "sof_sdw",
		369	.sof_fw_filename = "sof-tgl.ri",
		370	.sof_tplg_filename = "sof-tgl-rt711-rt1308-rt715.tplg",
		371	},
		372	{
		373	.link_mask = BIT(0) \| BIT(1) \| BIT(3),
		374	.links = sdw_mockup_headset_1amp_mic,
		375	.drv_name = "sof_sdw",
		376	.sof_fw_filename = "sof-tgl.ri",
		377	.sof_tplg_filename = "sof-tgl-rt711-rt1308-mono-rt715.tplg",
		378	},
		379	{
		380	.link_mask = BIT(0) \| BIT(1) \| BIT(2),
		381	.links = sdw_mockup_mic_headset_1amp,
		382	.drv_name = "sof_sdw",
		383	.sof_fw_filename = "sof-tgl.ri",
		384	.sof_tplg_filename = "sof-tgl-rt715-rt711-rt1308-mono.tplg",
		385	},
354	{	386	{
355	.link_mask = 0x7,	387	.link_mask = 0x7,
356	.links = tgl_sdw_rt711_link1_rt1308_link2_rt715_link0,	388	.links = tgl_sdw_rt711_link1_rt1308_link2_rt715_link0,
@@ -398,6 +430,12 @@ struct snd_soc_acpi_mach snd_soc_acpi_intel_tgl_sdw_machines[] = { · 41 unmodified lines
398	.drv_name = "sof_sdw",	430	.drv_name = "sof_sdw",
399	.sof_tplg_filename = "sof-tgl-sdw-max98373-rt5682.tplg",	431	.sof_tplg_filename = "sof-tgl-sdw-max98373-rt5682.tplg",
400	},	432	},
		433	{
		434	.link_mask = 0x1, /* rt711 on link 0 */
		435	.links = tgl_rvp_headset_only,
		436	.drv_name = "sof_sdw",
		437	.sof_tplg_filename = "sof-tgl-rt711.tplg",
		438	},
401	{},	439	{},
402	};	440	};
403	EXPORT_SYMBOL_GPL(snd_soc_acpi_intel_tgl_sdw_machines);	441	EXPORT_SYMBOL_GPL(snd_soc_acpi_intel_tgl_sdw_machines);

sound/soc/intel/skylake/skl-messages.c+98−57

 	base_cfg->is_pages = res->is_pages;
 }
+static void fill_pin_params(struct skl_audio_data_format *pin_fmt,
+			    struct skl_module_fmt *format)
+{
+	pin_fmt->number_of_channels = format->channels;
+	pin_fmt->s_freq = format->s_freq;
+	pin_fmt->bit_depth = format->bit_depth;
+	pin_fmt->valid_bit_depth = format->valid_bit_depth;
+	pin_fmt->ch_cfg = format->ch_cfg;
+	pin_fmt->sample_type = format->sample_type;
+	pin_fmt->channel_map = format->ch_map;
+	pin_fmt->interleaving = format->interleaving_style;
+}
+/*
+ * Any module configuration begins with a base module configuration but
+ * can be followed by a generic extension containing audio format for all
+ * module's pins that are in use.
+ */
+static void skl_set_base_ext_module_format(struct skl_dev *skl,
+					   struct skl_module_cfg *mconfig,
+					   struct skl_base_cfg_ext *base_cfg_ext)
+{
+	struct skl_module *module = mconfig->module;
+	struct skl_module_pin_resources *pin_res;
+	struct skl_module_iface *fmt = &module->formats[mconfig->fmt_idx];
+	struct skl_module_res *res = &module->resources[mconfig->res_idx];
+	struct skl_module_fmt *format;
+	struct skl_pin_format *pin_fmt;
+	char *params;
+	int i;
+	base_cfg_ext->nr_input_pins = res->nr_input_pins;
+	base_cfg_ext->nr_output_pins = res->nr_output_pins;
+	base_cfg_ext->priv_param_length =
+		mconfig->formats_config[SKL_PARAM_INIT].caps_size;
+	for (i = 0; i < res->nr_input_pins; i++) {
+		pin_res = &res->input[i];
+		pin_fmt = &base_cfg_ext->pins_fmt[i];
+		pin_fmt->pin_idx = pin_res->pin_index;
+		pin_fmt->buf_size = pin_res->buf_size;
+		format = &fmt->inputs[pin_res->pin_index].fmt;
+		fill_pin_params(&pin_fmt->audio_fmt, format);
+	}
+	for (i = 0; i < res->nr_output_pins; i++) {
+		pin_res = &res->output[i];
+		pin_fmt = &base_cfg_ext->pins_fmt[res->nr_input_pins + i];
+		pin_fmt->pin_idx = pin_res->pin_index;
+		pin_fmt->buf_size = pin_res->buf_size;
+		format = &fmt->outputs[pin_res->pin_index].fmt;
+		fill_pin_params(&pin_fmt->audio_fmt, format);
+	}
+	if (!base_cfg_ext->priv_param_length)
+		return;
+	params = (char *)base_cfg_ext + sizeof(struct skl_base_cfg_ext);
+	params += (base_cfg_ext->nr_input_pins + base_cfg_ext->nr_output_pins) *
+		  sizeof(struct skl_pin_format);
+	memcpy(params, mconfig->formats_config[SKL_PARAM_INIT].caps,
+	       mconfig->formats_config[SKL_PARAM_INIT].caps_size);
+}
 /*
  * Copies copier capabilities into copier module and updates copier module
  * config size.
 static void skl_copy_copier_caps(struct skl_module_cfg *mconfig,
 				struct skl_cpr_cfg *cpr_mconfig)
 {
-	if (mconfig->formats_config.caps_size == 0)
+	if (mconfig->formats_config[SKL_PARAM_INIT].caps_size == 0)
 		return;
 	memcpy(cpr_mconfig->gtw_cfg.config_data,
-			mconfig->formats_config.caps,
+			mconfig->formats_config[SKL_PARAM_INIT].caps,
-			mconfig->formats_config.caps_size);
+			mconfig->formats_config[SKL_PARAM_INIT].caps_size);
 	cpr_mconfig->gtw_cfg.config_length =
-			(mconfig->formats_config.caps_size) / 4;
+			(mconfig->formats_config[SKL_PARAM_INIT].caps_size) / 4;
 }
 #define SKL_NON_GATEWAY_CPR_NODE_ID 0xFFFFFFFF
 	skl_setup_cpr_gateway_cfg(skl, mconfig, cpr_mconfig);
 }
-/*
- * Algo module are DSP pre processing modules. Algo module take base module
- * configuration and params
- */
-static void skl_set_algo_format(struct skl_dev *skl,
-			struct skl_module_cfg *mconfig,
-			struct skl_algo_cfg *algo_mcfg)
-{
-	struct skl_base_cfg *base_cfg = (struct skl_base_cfg *)algo_mcfg;
-	skl_set_base_module_format(skl, mconfig, base_cfg);
-	if (mconfig->formats_config.caps_size == 0)
-		return;
-	memcpy(algo_mcfg->params,
-			mconfig->formats_config.caps,
-			mconfig->formats_config.caps_size);
-}
 /*
  * Mic select module allows selecting one or many input channels, thus
  * acting as a demux.
 static u16 skl_get_module_param_size(struct skl_dev *skl,
 			struct skl_module_cfg *mconfig)
 {
+	struct skl_module_res *res;
+	struct skl_module *module = mconfig->module;
 	u16 param_size;
 	switch (mconfig->m_type) {
 	case SKL_MODULE_TYPE_COPIER:
 		param_size = sizeof(struct skl_cpr_cfg);
-		param_size += mconfig->formats_config.caps_size;
+		param_size += mconfig->formats_config[SKL_PARAM_INIT].caps_size;
 		return param_size;
 	case SKL_MODULE_TYPE_SRCINT:
 	case SKL_MODULE_TYPE_UPDWMIX:
 		return sizeof(struct skl_up_down_mixer_cfg);
-	case SKL_MODULE_TYPE_ALGO:
-		param_size = sizeof(struct skl_base_cfg);
-		param_size += mconfig->formats_config.caps_size;
-		return param_size;
 	case SKL_MODULE_TYPE_BASE_OUTFMT:
 	case SKL_MODULE_TYPE_MIC_SELECT:
-	case SKL_MODULE_TYPE_KPB:
 		return sizeof(struct skl_base_outfmt_cfg);
-	default:
+	case SKL_MODULE_TYPE_MIXER:
-		/*
+	case SKL_MODULE_TYPE_KPB:
-		 * return only base cfg when no specific module type is
-		 * specified
-		 */
 		return sizeof(struct skl_base_cfg);
+	case SKL_MODULE_TYPE_ALGO:
+	default:
+		res = &module->resources[mconfig->res_idx];
+		param_size = sizeof(struct skl_base_cfg) + sizeof(struct skl_base_cfg_ext);
+		param_size += (res->nr_input_pins + res->nr_output_pins) *
+			      sizeof(struct skl_pin_format);
+		param_size += mconfig->formats_config[SKL_PARAM_INIT].caps_size;
+		return param_size;
 	}
 	return 0;
 		skl_set_updown_mixer_format(skl, module_config, *param_data);
 		break;
-	case SKL_MODULE_TYPE_ALGO:
-		skl_set_algo_format(skl, module_config, *param_data);
-		break;
 	case SKL_MODULE_TYPE_BASE_OUTFMT:
 	case SKL_MODULE_TYPE_MIC_SELECT:
-	case SKL_MODULE_TYPE_KPB:
 		skl_set_base_outfmt_format(skl, module_config, *param_data);
 		break;
-	default:
+	case SKL_MODULE_TYPE_MIXER:
+	case SKL_MODULE_TYPE_KPB:
 		skl_set_base_module_format(skl, module_config, *param_data);
 		break;
+	case SKL_MODULE_TYPE_ALGO:
+	default:
+		skl_set_base_module_format(skl, module_config, *param_data);
+		skl_set_base_ext_module_format(skl, module_config,
+					       *param_data +
+					       sizeof(struct skl_base_cfg));
+		break;
 	}
 	dev_dbg(skl->dev, "Module type=%d id=%d config size: %d bytes\n",
 	return ret;
 }
-static void fill_pin_params(struct skl_audio_data_format *pin_fmt,
-				struct skl_module_fmt *format)
-{
-	pin_fmt->number_of_channels = format->channels;
-	pin_fmt->s_freq = format->s_freq;
-	pin_fmt->bit_depth = format->bit_depth;
-	pin_fmt->valid_bit_depth = format->valid_bit_depth;
-	pin_fmt->ch_cfg = format->ch_cfg;
-	pin_fmt->sample_type = format->sample_type;
-	pin_fmt->channel_map = format->ch_map;
-	pin_fmt->interleaving = format->interleaving_style;
-}
 #define CPR_SINK_FMT_PARAM_ID 2
 /*

sound/soc/intel/skylake/skl-pcm.c+9−24

 	return bytes_to_frames(substream->runtime, pos);
 }
-static int skl_platform_soc_mmap(struct snd_soc_component *component,
-				 struct snd_pcm_substream *substream,
-				 struct vm_area_struct *area)
-{
-	return snd_pcm_lib_default_mmap(substream, area);
-}
 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
 				u64 nsec)
 {
 		return -EIO;
 	}
-	list_for_each_entry(module, &skl->uuid_list, list) {
-		if (guid_equal(uuid_mod, &module->uuid)) {
-			mconfig->id.module_id = module->id;
-			if (mconfig->module)
-				mconfig->module->loadable = module->is_loadable;
-			ret = 0;
-			break;
-		}
-	}
-	if (ret)
-		return ret;
-	uuid_mod = &module->uuid;
-	ret = -EIO;
 	for (i = 0; i < skl->nr_modules; i++) {
 		skl_module = skl->modules[i];
 		uuid_tplg = &skl_module->uuid;
 			break;
 		}
 	}
 	if (skl->nr_modules && ret)
 		return ret;
+	ret = -EIO;
 	list_for_each_entry(module, &skl->uuid_list, list) {
+		if (guid_equal(uuid_mod, &module->uuid)) {
+			mconfig->id.module_id = module->id;
+			mconfig->module->loadable = module->is_loadable;
+			ret = 0;
+		}
 		for (i = 0; i < MAX_IN_QUEUE; i++) {
 			pin_id = &mconfig->m_in_pin[i].id;
 			if (guid_equal(&pin_id->mod_uuid, &module->uuid))
 		}
 	}
-	return 0;
+	return ret;
 }
 static int skl_populate_modules(struct skl_dev *skl)
 	.trigger	= skl_platform_soc_trigger,
 	.pointer	= skl_platform_soc_pointer,
 	.get_time_info	= skl_platform_soc_get_time_info,
-	.mmap		= skl_platform_soc_mmap,
 	.pcm_construct	= skl_platform_soc_new,
 	.module_get_upon_open = 1, /* increment refcount when a pcm is opened */
 };

sound/soc/intel/skylake/skl-topology.c+91−64

 static void skl_dump_mconfig(struct skl_dev *skl, struct skl_module_cfg *mcfg)
 {
-	struct skl_module_iface *iface = &mcfg->module->formats[0];
+	struct skl_module_iface *iface = &mcfg->module->formats[mcfg->fmt_idx];
 	dev_dbg(skl->dev, "Dumping config\n");
 	dev_dbg(skl->dev, "Input Format:\n");
 	struct skl_module_fmt *in_fmt, *out_fmt;
 	/* Fixups will be applied to pin 0 only */
-	in_fmt = &m_cfg->module->formats[0].inputs[0].fmt;
+	in_fmt = &m_cfg->module->formats[m_cfg->fmt_idx].inputs[0].fmt;
-	out_fmt = &m_cfg->module->formats[0].outputs[0].fmt;
+	out_fmt = &m_cfg->module->formats[m_cfg->fmt_idx].outputs[0].fmt;
 	if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 		if (is_fe) {
 	/* Since fixups is applied to pin 0 only, ibs, obs needs
 	 * change for pin 0 only
 	 */
-	res = &mcfg->module->resources[0];
+	res = &mcfg->module->resources[mcfg->res_idx];
-	in_fmt = &mcfg->module->formats[0].inputs[0].fmt;
+	in_fmt = &mcfg->module->formats[mcfg->fmt_idx].inputs[0].fmt;
-	out_fmt = &mcfg->module->formats[0].outputs[0].fmt;
+	out_fmt = &mcfg->module->formats[mcfg->fmt_idx].outputs[0].fmt;
 	if (mcfg->m_type == SKL_MODULE_TYPE_SRCINT)
 		multiplier = 5;
 	struct skl_module_iface *m_iface = &m_cfg->module->formats[fmt_idx];
 	/* check if we already have blob */
-	if (m_cfg->formats_config.caps_size > 0)
+	if (m_cfg->formats_config[SKL_PARAM_INIT].caps_size > 0)
 		return 0;
 	dev_dbg(skl->dev, "Applying default cfg blob\n");
 	cfg = skl_get_ep_blob(skl, m_cfg->vbus_id, link_type,
 					s_fmt, ch, s_freq, dir, dev_type);
 	if (cfg) {
-		m_cfg->formats_config.caps_size = cfg->size;
+		m_cfg->formats_config[SKL_PARAM_INIT].caps_size = cfg->size;
-		m_cfg->formats_config.caps = (u32 *) &cfg->caps;
+		m_cfg->formats_config[SKL_PARAM_INIT].caps = (u32 *)&cfg->caps;
 	} else {
 		dev_err(skl->dev, "Blob NULL for id %x type %d dirn %d\n",
 					m_cfg->vbus_id, link_type, dir);
 	struct skl_algo_data *bc;
 	struct skl_specific_cfg *sp_cfg;
-	if (mconfig->formats_config.caps_size > 0 &&
+	if (mconfig->formats_config[SKL_PARAM_SET].caps_size > 0 &&
-		mconfig->formats_config.set_params == SKL_PARAM_SET) {
+	    mconfig->formats_config[SKL_PARAM_SET].set_params == SKL_PARAM_SET) {
-		sp_cfg = &mconfig->formats_config;
+		sp_cfg = &mconfig->formats_config[SKL_PARAM_SET];
 		ret = skl_set_module_params(skl, sp_cfg->caps,
 					sp_cfg->caps_size,
 					sp_cfg->param_id, mconfig);
 			if (bc->set_params != SKL_PARAM_INIT)
 				continue;
-			mconfig->formats_config.caps = (u32 *)bc->params;
+			mconfig->formats_config[SKL_PARAM_INIT].caps =
-			mconfig->formats_config.caps_size = bc->size;
+							(u32 *)bc->params;
+			mconfig->formats_config[SKL_PARAM_INIT].caps_size =
+								bc->size;
 			break;
 		}
 				mconfig->id.module_id, mconfig->guid);
 			if (ret < 0)
 				return ret;
-			mconfig->m_state = SKL_MODULE_LOADED;
 		}
 		/* prepare the DMA if the module is gateway cpr */
 		mconfig  = w_module->w->priv;
 		uuid_mod = (guid_t *)mconfig->guid;
-		if (mconfig->module->loadable && skl->dsp->fw_ops.unload_mod &&
+		if (mconfig->module->loadable && skl->dsp->fw_ops.unload_mod) {
-			mconfig->m_state > SKL_MODULE_UNINIT) {
 			ret = skl->dsp->fw_ops.unload_mod(skl->dsp,
 						mconfig->id.module_id);
 			if (ret < 0)
 		return 0;
 	}
-	if (pipe->conn_type == SKL_PIPE_CONN_TYPE_NONE) {
+	if (pipe->conn_type == SKL_PIPE_CONN_TYPE_NONE || pipe->nr_cfgs == 1) {
-		dev_dbg(skl->dev, "No conn_type detected, take 0th config\n");
+		dev_dbg(skl->dev, "No conn_type or just 1 pathcfg, taking 0th for %d\n",
+			pipe->ppl_id);
 		pipe->cur_config_idx = 0;
 		pipe->memory_pages = pconfig->mem_pages;
 			return 0;
 	}
-	if (mconfig->formats_config.caps_size > 0 &&
+	if (mconfig->formats_config[SKL_PARAM_BIND].caps_size > 0 &&
-		mconfig->formats_config.set_params == SKL_PARAM_BIND) {
+	    mconfig->formats_config[SKL_PARAM_BIND].set_params ==
-		sp_cfg = &mconfig->formats_config;
+								SKL_PARAM_BIND) {
+		sp_cfg = &mconfig->formats_config[SKL_PARAM_BIND];
 		ret = skl_set_module_params(skl, sp_cfg->caps,
 					sp_cfg->caps_size,
 					sp_cfg->param_id, mconfig);
 	struct skl_dev *skl = get_skl_ctx(w->dapm->dev);
 	if (ac->params) {
-		/*
-		 * Widget data is expected to be stripped of T and L
-		 */
-		size -= 2 * sizeof(unsigned int);
-		data += 2;
 		if (size > ac->max)
 			return -EINVAL;
 		ac->size = size;
 static int skl_fill_mic_sel_params(struct skl_module_cfg *mconfig,
 	struct skl_mic_sel_config *mic_cfg, struct device *dev)
 {
-	struct skl_specific_cfg *sp_cfg = &mconfig->formats_config;
+	struct skl_specific_cfg *sp_cfg =
+				&mconfig->formats_config[SKL_PARAM_INIT];
 	sp_cfg->caps_size = sizeof(struct skl_mic_sel_config);
 	sp_cfg->set_params = SKL_PARAM_SET;
 			struct skl_module_cfg *mconfig,
 			struct skl_pipe_params *params)
 {
-	struct skl_module_res *res = &mconfig->module->resources[0];
+	struct skl_module_res *res;
 	struct skl_dev *skl = get_skl_ctx(dev);
 	struct skl_module_fmt *format = NULL;
 	u8 cfg_idx = mconfig->pipe->cur_config_idx;
+	res = &mconfig->module->resources[mconfig->res_idx];
 	skl_tplg_fill_dma_id(mconfig, params);
 	mconfig->fmt_idx = mconfig->mod_cfg[cfg_idx].fmt_idx;
 	mconfig->res_idx = mconfig->mod_cfg[cfg_idx].res_idx;
 		return 0;
 	if (params->stream == SNDRV_PCM_STREAM_PLAYBACK)
-		format = &mconfig->module->formats[0].inputs[0].fmt;
+		format = &mconfig->module->formats[mconfig->fmt_idx].inputs[0].fmt;
 	else
-		format = &mconfig->module->formats[0].outputs[0].fmt;
+		format = &mconfig->module->formats[mconfig->fmt_idx].outputs[0].fmt;
 	/* set the hw_params */
 	format->s_freq = params->s_freq;
  * Fill the BE gateway parameters
  * The BE gateway expects a blob of parameters which are kept in the ACPI
  * NHLT blob, so query the blob for interface type (i2s/pdm) and instance.
- * The port can have multiple settings so pick based on the PCM
+ * The port can have multiple settings so pick based on the pipeline
  * parameters
  */
 static int skl_tplg_be_fill_pipe_params(struct snd_soc_dai *dai,
 				struct skl_pipe_params *params)
 {
 	struct nhlt_specific_cfg *cfg;
+	struct skl_pipe *pipe = mconfig->pipe;
+	struct skl_pipe_fmt *pipe_fmt;
 	struct skl_dev *skl = get_skl_ctx(dai->dev);
 	int link_type = skl_tplg_be_link_type(mconfig->dev_type);
 	u8 dev_type = skl_tplg_be_dev_type(mconfig->dev_type);
 	if (link_type == NHLT_LINK_HDA)
 		return 0;
+	if (pipe->direction == SNDRV_PCM_STREAM_PLAYBACK)
+		pipe_fmt = &pipe->configs[pipe->pipe_config_idx].out_fmt;
+	else
+		pipe_fmt = &pipe->configs[pipe->pipe_config_idx].in_fmt;
 	/* update the blob based on virtual bus_id*/
 	cfg = skl_get_ep_blob(skl, mconfig->vbus_id, link_type,
-					params->s_fmt, params->ch,
+					pipe_fmt->bps, pipe_fmt->channels,
-					params->s_freq, params->stream,
+					pipe_fmt->freq, pipe->direction,
 					dev_type);
 	if (cfg) {
-		mconfig->formats_config.caps_size = cfg->size;
+		mconfig->formats_config[SKL_PARAM_INIT].caps_size = cfg->size;
-		mconfig->formats_config.caps = (u32 *) &cfg->caps;
+		mconfig->formats_config[SKL_PARAM_INIT].caps = (u32 *)&cfg->caps;
 	} else {
-		dev_err(dai->dev, "Blob NULL for id %x type %d dirn %d\n",
+		dev_err(dai->dev, "Blob NULL for id:%d type:%d dirn:%d ch:%d, freq:%d, fmt:%d\n",
-					mconfig->vbus_id, link_type,
+			mconfig->vbus_id, link_type, params->stream,
-					params->stream);
+			params->ch, params->s_freq, params->s_fmt);
-		dev_err(dai->dev, "PCM: ch %d, freq %d, fmt %d\n",
-				 params->ch, params->s_freq, params->s_fmt);
 		return -EINVAL;
 	}
 		break;
+	case SKL_TKN_U32_FMT_CFG_IDX:
+		if (tkn_elem->value > SKL_MAX_PARAMS_TYPES)
+			return -EINVAL;
+		mconfig->fmt_cfg_idx = tkn_elem->value;
+		break;
 	case SKL_TKN_U32_CAPS_SIZE:
-		mconfig->formats_config.caps_size =
+		mconfig->formats_config[mconfig->fmt_cfg_idx].caps_size =
 			tkn_elem->value;
 		break;
 	case SKL_TKN_U32_CAPS_SET_PARAMS:
-		mconfig->formats_config.set_params =
+		mconfig->formats_config[mconfig->fmt_cfg_idx].set_params =
 				tkn_elem->value;
 		break;
 	case SKL_TKN_U32_CAPS_PARAMS_ID:
-		mconfig->formats_config.param_id =
+		mconfig->formats_config[mconfig->fmt_cfg_idx].param_id =
 				tkn_elem->value;
 		break;
 	struct skl_dfw_v4_module *dfw =
 				(struct skl_dfw_v4_module *)tplg_w->priv.data;
 	int ret;
+	int idx = mconfig->fmt_cfg_idx;
 	dev_dbg(dev, "Parsing Skylake v4 widget topology data\n");
 	mconfig->dev_type = dfw->dev_type;
 	mconfig->hw_conn_type = dfw->hw_conn_type;
 	mconfig->time_slot = dfw->time_slot;
-	mconfig->formats_config.caps_size = dfw->caps.caps_size;
+	mconfig->formats_config[idx].caps_size = dfw->caps.caps_size;
 	mconfig->m_in_pin = devm_kcalloc(dev,
 				MAX_IN_QUEUE, sizeof(*mconfig->m_in_pin),
 				    dfw->is_dynamic_out_pin,
 				    mconfig->module->max_output_pins);
-	if (mconfig->formats_config.caps_size) {
+	if (mconfig->formats_config[idx].caps_size) {
-		mconfig->formats_config.set_params = dfw->caps.set_params;
+		mconfig->formats_config[idx].set_params = dfw->caps.set_params;
-		mconfig->formats_config.param_id = dfw->caps.param_id;
+		mconfig->formats_config[idx].param_id = dfw->caps.param_id;
-		mconfig->formats_config.caps =
+		mconfig->formats_config[idx].caps =
-		devm_kzalloc(dev, mconfig->formats_config.caps_size,
+		devm_kzalloc(dev, mconfig->formats_config[idx].caps_size,
 			     GFP_KERNEL);
-		if (!mconfig->formats_config.caps)
+		if (!mconfig->formats_config[idx].caps)
 			return -ENOMEM;
-		memcpy(mconfig->formats_config.caps, dfw->caps.caps,
+		memcpy(mconfig->formats_config[idx].caps, dfw->caps.caps,
 		       dfw->caps.caps_size);
 	}
 	return 0;
 }
+static int skl_tplg_get_caps_data(struct device *dev, char *data,
+				  struct skl_module_cfg *mconfig)
+{
+	int idx = mconfig->fmt_cfg_idx;
+	if (mconfig->formats_config[idx].caps_size > 0) {
+		mconfig->formats_config[idx].caps =
+			devm_kzalloc(dev, mconfig->formats_config[idx].caps_size,
+				     GFP_KERNEL);
+		if (!mconfig->formats_config[idx].caps)
+			return -ENOMEM;
+		memcpy(mconfig->formats_config[idx].caps, data,
+		       mconfig->formats_config[idx].caps_size);
+	}
+	return mconfig->formats_config[idx].caps_size;
+}
 /*
  * Parse the private data for the token and corresponding value.
  * The private data can have multiple data blocks. So, a data block
 		if (block_type == SKL_TYPE_TUPLE) {
 			ret = skl_tplg_get_tokens(dev, data,
 					skl, mconfig, block_size);
-			if (ret < 0)
-				return ret;
-			--num_blocks;
 		} else {
-			if (mconfig->formats_config.caps_size > 0)
+			ret = skl_tplg_get_caps_data(dev, data, mconfig);
-				memcpy(mconfig->formats_config.caps, data,
-					mconfig->formats_config.caps_size);
-			--num_blocks;
-			ret = mconfig->formats_config.caps_size;
 		}
+		if (ret < 0)
+			return ret;
+		--num_blocks;
 		off += ret;
 	}
 	 */
 	mconfig->id.module_id = -1;
+	/* To provide backward compatibility, set default as SKL_PARAM_INIT */
+	mconfig->fmt_cfg_idx = SKL_PARAM_INIT;
 	/* Parse private data for tuples */
 	ret = skl_tplg_get_pvt_data(tplg_w, skl, bus->dev, mconfig);
 	if (ret < 0)

sound/soc/intel/skylake/skl-topology.h+21−5

 	SKL_FS_INVALID
 };
+#define SKL_MAX_PARAMS_TYPES	4
 enum skl_widget_type {
 	SKL_WIDGET_VMIXER = 1,
 	SKL_WIDGET_MIXER = 2,
 	u32 ch_map;
 } __packed;
+struct skl_pin_format {
+	u32 pin_idx;
+	u32 buf_size;
+	struct skl_audio_data_format audio_fmt;
+} __packed;
+struct skl_base_cfg_ext {
+	u16 nr_input_pins;
+	u16 nr_output_pins;
+	u8 reserved[8];
+	u32 priv_param_length;
+	/* Input pin formats followed by output ones. */
+	struct skl_pin_format pins_fmt[0];
+} __packed;
 struct skl_algo_cfg {
 	struct skl_base_cfg  base_cfg;
 	char params[];
 enum skl_module_state {
 	SKL_MODULE_UNINIT = 0,
-	SKL_MODULE_LOADED = 1,
+	SKL_MODULE_INIT_DONE = 1,
-	SKL_MODULE_INIT_DONE = 2,
+	SKL_MODULE_BIND_DONE = 2,
-	SKL_MODULE_BIND_DONE = 3,
-	SKL_MODULE_UNLOADED = 4,
 };
 enum d0i3_capability {
 	struct skl_module *module;
 	int res_idx;
 	int fmt_idx;
+	int fmt_cfg_idx;
 	u8 domain;
 	bool homogenous_inputs;
 	bool homogenous_outputs;
 	enum skl_hw_conn_type  hw_conn_type;
 	enum skl_module_state m_state;
 	struct skl_pipe *pipe;
-	struct skl_specific_cfg formats_config;
+	struct skl_specific_cfg formats_config[SKL_MAX_PARAMS_TYPES];
 	struct skl_pipe_mcfg mod_cfg[SKL_MAX_MODULES_IN_PIPE];
 };

sound/soc/mediatek/Kconfig+24−0

@@ -184,3 +184,27 @@ config SND_SOC_MT8192_MT6359_RT1015_RT5682 · 183 unmodified lines
184	with the MT6359 RT1015 RT5682 audio codec.	184	with the MT6359 RT1015 RT5682 audio codec.
185	Select Y if you have such device.	185	Select Y if you have such device.
186	If unsure select "N".	186	If unsure select "N".
		187
		188	config SND_SOC_MT8195
		189	tristate "ASoC support for Mediatek MT8195 chip"
		190	select SND_SOC_MEDIATEK
		191	help
		192	This adds ASoC platform driver support for Mediatek MT8195 chip
		193	that can be used with other codecs.
		194	Select Y if you have such device.
		195	If unsure select "N".
		196
		197	config SND_SOC_MT8195_MT6359_RT1019_RT5682
		198	tristate "ASoC Audio driver for MT8195 with MT6359 RT1019 RT5682 codec"
		199	depends on I2C
		200	depends on SND_SOC_MT8195
		201	select SND_SOC_MT6359
		202	select SND_SOC_RT1015P
		203	select SND_SOC_RT5682_I2C
		204	select SND_SOC_DMIC
		205	select SND_SOC_HDMI_CODEC
		206	help
		207	This adds ASoC driver for Mediatek MT8195 boards
		208	with the MT6359 RT1019 RT5682 audio codec.
		209	Select Y if you have such device.
		210	If unsure select "N".

sound/soc/mediatek/Makefile+1−0

@@ -5,3 +5,4 @@ obj-$(CONFIG_SND_SOC_MT6797) += mt6797/ · 4 unmodified lines
5	obj-$(CONFIG_SND_SOC_MT8173) += mt8173/	5	obj-$(CONFIG_SND_SOC_MT8173) += mt8173/
6	obj-$(CONFIG_SND_SOC_MT8183) += mt8183/	6	obj-$(CONFIG_SND_SOC_MT8183) += mt8183/
7	obj-$(CONFIG_SND_SOC_MT8192) += mt8192/	7	obj-$(CONFIG_SND_SOC_MT8192) += mt8192/
		8	obj-$(CONFIG_SND_SOC_MT8195) += mt8195/

sound/soc/mediatek/common/mtk-afe-fe-dai.c+19−3

 		substream->runtime->dma_area,
 		substream->runtime->dma_bytes);
-	memset_io(substream->runtime->dma_area, 0,
+	memset_io((void __force __iomem *)substream->runtime->dma_area, 0,
 		  substream->runtime->dma_bytes);
 	/* set addr */
 				 phys_buf_addr_upper_32);
 	}
-	/* set MSB to 33-bit */
+	/*
-	if (memif->data->msb_reg >= 0)
+	 * set MSB to 33-bit, for memif address
+	 * only for memif base address, if msb_end_reg exists
+	 */
+	if (memif->data->msb_reg)
 		mtk_regmap_update_bits(afe->regmap, memif->data->msb_reg,
 				       1, msb_at_bit33, memif->data->msb_shift);
+	/* set MSB to 33-bit, for memif end address */
+	if (memif->data->msb_end_reg)
+		mtk_regmap_update_bits(afe->regmap, memif->data->msb_end_reg,
+				       1, msb_at_bit33,
+				       memif->data->msb_end_shift);
 	return 0;
 }
 EXPORT_SYMBOL_GPL(mtk_memif_set_addr);
 	else
 		mono = (channel == 1) ? 1 : 0;
+	/* for specific configuration of memif mono mode */
+	if (memif->data->int_odd_flag_reg)
+		mtk_regmap_update_bits(afe->regmap,
+				       memif->data->int_odd_flag_reg,
+				       1, mono,
+				       memif->data->int_odd_flag_shift);
 	return mtk_regmap_update_bits(afe->regmap, memif->data->mono_reg,
 				      1, mono, memif->data->mono_shift);
 }

sound/soc/mediatek/common/mtk-base-afe.h+8−2

 	int quad_ch_reg;
 	int quad_ch_mask;
 	int quad_ch_shift;
+	int int_odd_flag_reg;
+	int int_odd_flag_shift;
 	int enable_reg;
 	int enable_shift;
 	int hd_reg;
 	int hd_align_mshift;
 	int msb_reg;
 	int msb_shift;
-	int msb2_reg;
+	int msb_end_reg;
-	int msb2_shift;
+	int msb_end_shift;
 	int agent_disable_reg;
 	int agent_disable_shift;
+	int ch_num_reg;
+	int ch_num_shift;
+	int ch_num_maskbit;
 	/* playback memif only */
 	int pbuf_reg;
 	int pbuf_mask;
 	int irq_en_shift;
 	int irq_clr_reg;
 	int irq_clr_shift;
+	int irq_status_shift;
 };
 struct device;

sound/soc/mediatek/mt8183/mt8183-afe-pcm.c+27−16

 	afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
 	if (IS_ERR(afe->regmap)) {
 		dev_err(dev, "could not get regmap from parent\n");
-		return PTR_ERR(afe->regmap);
+		ret = PTR_ERR(afe->regmap);
+		goto err_pm_disable;
 	}
 	ret = regmap_attach_dev(dev, afe->regmap, &mt8183_afe_regmap_config);
 	if (ret) {
 		dev_warn(dev, "regmap_attach_dev fail, ret %d\n", ret);
-		return ret;
+		goto err_pm_disable;
 	}
 	rstc = devm_reset_control_get(dev, "audiosys");
 	if (IS_ERR(rstc)) {
 		ret = PTR_ERR(rstc);
 		dev_err(dev, "could not get audiosys reset:%d\n", ret);
-		return ret;
+		goto err_pm_disable;
 	}
 	ret = reset_control_reset(rstc);
 	if (ret) {
 		dev_err(dev, "failed to trigger audio reset:%d\n", ret);
-		return ret;
+		goto err_pm_disable;
 	}
 	/* enable clock for regcache get default value from hw */
 	ret = regmap_reinit_cache(afe->regmap, &mt8183_afe_regmap_config);
 	if (ret) {
 		dev_err(dev, "regmap_reinit_cache fail, ret %d\n", ret);
-		return ret;
+		goto err_pm_disable;
 	}
 	pm_runtime_put_sync(&pdev->dev);
 	afe->memif_size = MT8183_MEMIF_NUM;
 	afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
 				  GFP_KERNEL);
-	if (!afe->memif)
+	if (!afe->memif) {
-		return -ENOMEM;
+		ret = -ENOMEM;
+		goto err_pm_disable;
+	}
 	for (i = 0; i < afe->memif_size; i++) {
 		afe->memif[i].data = &memif_data[i];
 	afe->irqs_size = MT8183_IRQ_NUM;
 	afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
 				 GFP_KERNEL);
-	if (!afe->irqs)
+	if (!afe->irqs) {
-		return -ENOMEM;
+		ret = -ENOMEM;
+		goto err_pm_disable;
+	}
 	for (i = 0; i < afe->irqs_size; i++)
 		afe->irqs[i].irq_data = &irq_data[i];
 	/* request irq */
 	irq_id = platform_get_irq(pdev, 0);
-	if (irq_id < 0)
+	if (irq_id < 0) {
-		return irq_id;
+		ret = irq_id;
+		goto err_pm_disable;
+	}
 	ret = devm_request_irq(dev, irq_id, mt8183_afe_irq_handler,
 			       IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
 	if (ret) {
 		dev_err(dev, "could not request_irq for asys-isr\n");
-		return ret;
+		goto err_pm_disable;
 	}
 	/* init sub_dais */
 		if (ret) {
 			dev_warn(afe->dev, "dai register i %d fail, ret %d\n",
 				 i, ret);
-			return ret;
+			goto err_pm_disable;
 		}
 	}
 	if (ret) {
 		dev_warn(afe->dev, "mtk_afe_combine_sub_dai fail, ret %d\n",
 			 ret);
-		return ret;
+		goto err_pm_disable;
 	}
 	afe->mtk_afe_hardware = &mt8183_afe_hardware;
 					      NULL, 0);
 	if (ret) {
 		dev_warn(dev, "err_platform\n");
-		return ret;
+		goto err_pm_disable;
 	}
 	ret = devm_snd_soc_register_component(afe->dev,
 					      afe->num_dai_drivers);
 	if (ret) {
 		dev_warn(dev, "err_dai_component\n");
-		return ret;
+		goto err_pm_disable;
 	}
 	return ret;
+err_pm_disable:
+	pm_runtime_disable(&pdev->dev);
+	return ret;
 }
 static int mt8183_afe_pcm_dev_remove(struct platform_device *pdev)

sound/soc/mediatek/mt8192/mt8192-afe-pcm.c+17−10

 	afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
 	if (IS_ERR(afe->regmap)) {
 		dev_err(dev, "could not get regmap from parent\n");
-		return PTR_ERR(afe->regmap);
+		ret = PTR_ERR(afe->regmap);
+		goto err_pm_disable;
 	}
 	ret = regmap_attach_dev(dev, afe->regmap, &mt8192_afe_regmap_config);
 	if (ret) {
 		dev_warn(dev, "regmap_attach_dev fail, ret %d\n", ret);
-		return ret;
+		goto err_pm_disable;
 	}
 	/* enable clock for regcache get default value from hw */
 	ret = regmap_reinit_cache(afe->regmap, &mt8192_afe_regmap_config);
 	if (ret) {
 		dev_err(dev, "regmap_reinit_cache fail, ret %d\n", ret);
-		return ret;
+		goto err_pm_disable;
 	}
 	pm_runtime_put_sync(&pdev->dev);
 	afe->memif_size = MT8192_MEMIF_NUM;
 	afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
 				  GFP_KERNEL);
-	if (!afe->memif)
+	if (!afe->memif) {
-		return -ENOMEM;
+		ret = -ENOMEM;
+		goto err_pm_disable;
+	}
 	for (i = 0; i < afe->memif_size; i++) {
 		afe->memif[i].data = &memif_data[i];
 	afe->irqs_size = MT8192_IRQ_NUM;
 	afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
 				 GFP_KERNEL);
-	if (!afe->irqs)
+	if (!afe->irqs) {
-		return -ENOMEM;
+		ret = -ENOMEM;
+		goto err_pm_disable;
+	}
 	for (i = 0; i < afe->irqs_size; i++)
 		afe->irqs[i].irq_data = &irq_data[i];
 	/* request irq */
 	irq_id = platform_get_irq(pdev, 0);
-	if (irq_id < 0)
+	if (irq_id < 0) {
-		return irq_id;
+		ret = irq_id;
+		goto err_pm_disable;
+	}
 	ret = devm_request_irq(dev, irq_id, mt8192_afe_irq_handler,
 			       IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
 	if (ret) {
 		dev_err(dev, "could not request_irq for Afe_ISR_Handle\n");
-		return ret;
+		goto err_pm_disable;
 	}
 	/* init sub_dais */

sound/soc/mediatek/mt8195/Makefile+15−0

@@ -0,0 +1,15 @@
	1	# SPDX-License-Identifier: GPL-2.0
	2
	3	# platform driver
	4	snd-soc-mt8195-afe-objs := \
	5	mt8195-audsys-clk.o \
	6	mt8195-afe-clk.o \
	7	mt8195-afe-pcm.o \
	8	mt8195-dai-adda.o \
	9	mt8195-dai-etdm.o \
	10	mt8195-dai-pcm.o
	11
	12	obj-$(CONFIG_SND_SOC_MT8195) += snd-soc-mt8195-afe.o
	13
	14	# machine driver
	15	obj-$(CONFIG_SND_SOC_MT8195_MT6359_RT1019_RT5682) += mt8195-mt6359-rt1019-rt5682.o

sound/soc/mediatek/mt8195/mt8195-afe-clk.c+441−0

@@ -0,0 +1,441 @@
	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* mt8195-afe-clk.c -- Mediatek 8195 afe clock ctrl
	4	*
	5	* Copyright (c) 2021 MediaTek Inc.
	6	* Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
	7	* Trevor Wu <trevor.wu@mediatek.com>
	8	*/
	9
	10	#include <linux/clk.h>
	11
	12	#include "mt8195-afe-common.h"
	13	#include "mt8195-afe-clk.h"
	14	#include "mt8195-reg.h"
	15	#include "mt8195-audsys-clk.h"
	16
	17	static const char *aud_clks[MT8195_CLK_NUM] = {
	18	/* xtal */
	19	[MT8195_CLK_XTAL_26M] = "clk26m",
	20	/* divider */
	21	[MT8195_CLK_TOP_APLL1] = "apll1_ck",
	22	[MT8195_CLK_TOP_APLL2] = "apll2_ck",
	23	[MT8195_CLK_TOP_APLL12_DIV0] = "apll12_div0",
	24	[MT8195_CLK_TOP_APLL12_DIV1] = "apll12_div1",
	25	[MT8195_CLK_TOP_APLL12_DIV2] = "apll12_div2",
	26	[MT8195_CLK_TOP_APLL12_DIV3] = "apll12_div3",
	27	[MT8195_CLK_TOP_APLL12_DIV9] = "apll12_div9",
	28	/* mux */
	29	[MT8195_CLK_TOP_A1SYS_HP_SEL] = "a1sys_hp_sel",
	30	[MT8195_CLK_TOP_AUD_INTBUS_SEL] = "aud_intbus_sel",
	31	[MT8195_CLK_TOP_AUDIO_H_SEL] = "audio_h_sel",
	32	[MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "audio_local_bus_sel",
	33	[MT8195_CLK_TOP_DPTX_M_SEL] = "dptx_m_sel",
	34	[MT8195_CLK_TOP_I2SO1_M_SEL] = "i2so1_m_sel",
	35	[MT8195_CLK_TOP_I2SO2_M_SEL] = "i2so2_m_sel",
	36	[MT8195_CLK_TOP_I2SI1_M_SEL] = "i2si1_m_sel",
	37	[MT8195_CLK_TOP_I2SI2_M_SEL] = "i2si2_m_sel",
	38	/* clock gate */
	39	[MT8195_CLK_INFRA_AO_AUDIO_26M_B] = "infra_ao_audio_26m_b",
	40	[MT8195_CLK_SCP_ADSP_AUDIODSP] = "scp_adsp_audiodsp",
	41	/* afe clock gate */
	42	[MT8195_CLK_AUD_AFE] = "aud_afe",
	43	[MT8195_CLK_AUD_APLL] = "aud_apll",
	44	[MT8195_CLK_AUD_APLL2] = "aud_apll2",
	45	[MT8195_CLK_AUD_DAC] = "aud_dac",
	46	[MT8195_CLK_AUD_ADC] = "aud_adc",
	47	[MT8195_CLK_AUD_DAC_HIRES] = "aud_dac_hires",
	48	[MT8195_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp",
	49	[MT8195_CLK_AUD_ADC_HIRES] = "aud_adc_hires",
	50	[MT8195_CLK_AUD_ADDA6_ADC] = "aud_adda6_adc",
	51	[MT8195_CLK_AUD_ADDA6_ADC_HIRES] = "aud_adda6_adc_hires",
	52	[MT8195_CLK_AUD_I2SIN] = "aud_i2sin",
	53	[MT8195_CLK_AUD_TDM_IN] = "aud_tdm_in",
	54	[MT8195_CLK_AUD_I2S_OUT] = "aud_i2s_out",
	55	[MT8195_CLK_AUD_TDM_OUT] = "aud_tdm_out",
	56	[MT8195_CLK_AUD_HDMI_OUT] = "aud_hdmi_out",
	57	[MT8195_CLK_AUD_ASRC11] = "aud_asrc11",
	58	[MT8195_CLK_AUD_ASRC12] = "aud_asrc12",
	59	[MT8195_CLK_AUD_A1SYS] = "aud_a1sys",
	60	[MT8195_CLK_AUD_A2SYS] = "aud_a2sys",
	61	[MT8195_CLK_AUD_PCMIF] = "aud_pcmif",
	62	[MT8195_CLK_AUD_MEMIF_UL1] = "aud_memif_ul1",
	63	[MT8195_CLK_AUD_MEMIF_UL2] = "aud_memif_ul2",
	64	[MT8195_CLK_AUD_MEMIF_UL3] = "aud_memif_ul3",
	65	[MT8195_CLK_AUD_MEMIF_UL4] = "aud_memif_ul4",
	66	[MT8195_CLK_AUD_MEMIF_UL5] = "aud_memif_ul5",
	67	[MT8195_CLK_AUD_MEMIF_UL6] = "aud_memif_ul6",
	68	[MT8195_CLK_AUD_MEMIF_UL8] = "aud_memif_ul8",
	69	[MT8195_CLK_AUD_MEMIF_UL9] = "aud_memif_ul9",
	70	[MT8195_CLK_AUD_MEMIF_UL10] = "aud_memif_ul10",
	71	[MT8195_CLK_AUD_MEMIF_DL2] = "aud_memif_dl2",
	72	[MT8195_CLK_AUD_MEMIF_DL3] = "aud_memif_dl3",
	73	[MT8195_CLK_AUD_MEMIF_DL6] = "aud_memif_dl6",
	74	[MT8195_CLK_AUD_MEMIF_DL7] = "aud_memif_dl7",
	75	[MT8195_CLK_AUD_MEMIF_DL8] = "aud_memif_dl8",
	76	[MT8195_CLK_AUD_MEMIF_DL10] = "aud_memif_dl10",
	77	[MT8195_CLK_AUD_MEMIF_DL11] = "aud_memif_dl11",
	78	};
	79
	80	int mt8195_afe_get_mclk_source_clk_id(int sel)
	81	{
	82	switch (sel) {
	83	case MT8195_MCK_SEL_26M:
	84	return MT8195_CLK_XTAL_26M;
	85	case MT8195_MCK_SEL_APLL1:
	86	return MT8195_CLK_TOP_APLL1;
	87	case MT8195_MCK_SEL_APLL2:
	88	return MT8195_CLK_TOP_APLL2;
	89	default:
	90	return -EINVAL;
	91	}
	92	}
	93
	94	int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll)
	95	{
	96	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	97	int clk_id = mt8195_afe_get_mclk_source_clk_id(apll);
	98
	99	if (clk_id < 0) {
	100	dev_dbg(afe->dev, "invalid clk id\n");
	101	return 0;
	102	}
	103
	104	return clk_get_rate(afe_priv->clk[clk_id]);
	105	}
	106
	107	int mt8195_afe_get_default_mclk_source_by_rate(int rate)
	108	{
	109	return ((rate % 8000) == 0) ?
	110	MT8195_MCK_SEL_APLL1 : MT8195_MCK_SEL_APLL2;
	111	}
	112
	113	int mt8195_afe_init_clock(struct mtk_base_afe *afe)
	114	{
	115	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	116	int i;
	117
	118	mt8195_audsys_clk_register(afe);
	119
	120	afe_priv->clk =
	121	devm_kcalloc(afe->dev, MT8195_CLK_NUM, sizeof(*afe_priv->clk),
	122	GFP_KERNEL);
	123	if (!afe_priv->clk)
	124	return -ENOMEM;
	125
	126	for (i = 0; i < MT8195_CLK_NUM; i++) {
	127	afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
	128	if (IS_ERR(afe_priv->clk[i])) {
	129	dev_dbg(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
	130	__func__, aud_clks[i],
	131	PTR_ERR(afe_priv->clk[i]));
	132	return PTR_ERR(afe_priv->clk[i]);
	133	}
	134	}
	135
	136	return 0;
	137	}
	138
	139	void mt8195_afe_deinit_clock(struct mtk_base_afe *afe)
	140	{
	141	mt8195_audsys_clk_unregister(afe);
	142	}
	143
	144	int mt8195_afe_enable_clk(struct mtk_base_afe afe, struct clk clk)
	145	{
	146	int ret;
	147
	148	if (clk) {
	149	ret = clk_prepare_enable(clk);
	150	if (ret) {
	151	dev_dbg(afe->dev, "%s(), failed to enable clk\n",
	152	__func__);
	153	return ret;
	154	}
	155	} else {
	156	dev_dbg(afe->dev, "NULL clk\n");
	157	}
	158	return 0;
	159	}
	160	EXPORT_SYMBOL_GPL(mt8195_afe_enable_clk);
	161
	162	void mt8195_afe_disable_clk(struct mtk_base_afe afe, struct clk clk)
	163	{
	164	if (clk)
	165	clk_disable_unprepare(clk);
	166	else
	167	dev_dbg(afe->dev, "NULL clk\n");
	168	}
	169	EXPORT_SYMBOL_GPL(mt8195_afe_disable_clk);
	170
	171	int mt8195_afe_prepare_clk(struct mtk_base_afe afe, struct clk clk)
	172	{
	173	int ret;
	174
	175	if (clk) {
	176	ret = clk_prepare(clk);
	177	if (ret) {
	178	dev_dbg(afe->dev, "%s(), failed to prepare clk\n",
	179	__func__);
	180	return ret;
	181	}
	182	} else {
	183	dev_dbg(afe->dev, "NULL clk\n");
	184	}
	185	return 0;
	186	}
	187
	188	void mt8195_afe_unprepare_clk(struct mtk_base_afe afe, struct clk clk)
	189	{
	190	if (clk)
	191	clk_unprepare(clk);
	192	else
	193	dev_dbg(afe->dev, "NULL clk\n");
	194	}
	195
	196	int mt8195_afe_enable_clk_atomic(struct mtk_base_afe afe, struct clk clk)
	197	{
	198	int ret;
	199
	200	if (clk) {
	201	ret = clk_enable(clk);
	202	if (ret) {
	203	dev_dbg(afe->dev, "%s(), failed to clk enable\n",
	204	__func__);
	205	return ret;
	206	}
	207	} else {
	208	dev_dbg(afe->dev, "NULL clk\n");
	209	}
	210	return 0;
	211	}
	212
	213	void mt8195_afe_disable_clk_atomic(struct mtk_base_afe afe, struct clk clk)
	214	{
	215	if (clk)
	216	clk_disable(clk);
	217	else
	218	dev_dbg(afe->dev, "NULL clk\n");
	219	}
	220
	221	int mt8195_afe_set_clk_rate(struct mtk_base_afe afe, struct clk clk,
	222	unsigned int rate)
	223	{
	224	int ret;
	225
	226	if (clk) {
	227	ret = clk_set_rate(clk, rate);
	228	if (ret) {
	229	dev_dbg(afe->dev, "%s(), failed to set clk rate\n",
	230	__func__);
	231	return ret;
	232	}
	233	}
	234
	235	return 0;
	236	}
	237
	238	int mt8195_afe_set_clk_parent(struct mtk_base_afe afe, struct clk clk,
	239	struct clk *parent)
	240	{
	241	int ret;
	242
	243	if (clk && parent) {
	244	ret = clk_set_parent(clk, parent);
	245	if (ret) {
	246	dev_dbg(afe->dev, "%s(), failed to set clk parent\n",
	247	__func__);
	248	return ret;
	249	}
	250	}
	251
	252	return 0;
	253	}
	254
	255	static unsigned int get_top_cg_reg(unsigned int cg_type)
	256	{
	257	switch (cg_type) {
	258	case MT8195_TOP_CG_A1SYS_TIMING:
	259	case MT8195_TOP_CG_A2SYS_TIMING:
	260	case MT8195_TOP_CG_26M_TIMING:
	261	return ASYS_TOP_CON;
	262	default:
	263	return 0;
	264	}
	265	}
	266
	267	static unsigned int get_top_cg_mask(unsigned int cg_type)
	268	{
	269	switch (cg_type) {
	270	case MT8195_TOP_CG_A1SYS_TIMING:
	271	return ASYS_TOP_CON_A1SYS_TIMING_ON;
	272	case MT8195_TOP_CG_A2SYS_TIMING:
	273	return ASYS_TOP_CON_A2SYS_TIMING_ON;
	274	case MT8195_TOP_CG_26M_TIMING:
	275	return ASYS_TOP_CON_26M_TIMING_ON;
	276	default:
	277	return 0;
	278	}
	279	}
	280
	281	static unsigned int get_top_cg_on_val(unsigned int cg_type)
	282	{
	283	switch (cg_type) {
	284	case MT8195_TOP_CG_A1SYS_TIMING:
	285	case MT8195_TOP_CG_A2SYS_TIMING:
	286	case MT8195_TOP_CG_26M_TIMING:
	287	return get_top_cg_mask(cg_type);
	288	default:
	289	return 0;
	290	}
	291	}
	292
	293	static unsigned int get_top_cg_off_val(unsigned int cg_type)
	294	{
	295	switch (cg_type) {
	296	case MT8195_TOP_CG_A1SYS_TIMING:
	297	case MT8195_TOP_CG_A2SYS_TIMING:
	298	case MT8195_TOP_CG_26M_TIMING:
	299	return 0;
	300	default:
	301	return get_top_cg_mask(cg_type);
	302	}
	303	}
	304
	305	static int mt8195_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
	306	{
	307	unsigned int reg = get_top_cg_reg(cg_type);
	308	unsigned int mask = get_top_cg_mask(cg_type);
	309	unsigned int val = get_top_cg_on_val(cg_type);
	310
	311	regmap_update_bits(afe->regmap, reg, mask, val);
	312	return 0;
	313	}
	314
	315	static int mt8195_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
	316	{
	317	unsigned int reg = get_top_cg_reg(cg_type);
	318	unsigned int mask = get_top_cg_mask(cg_type);
	319	unsigned int val = get_top_cg_off_val(cg_type);
	320
	321	regmap_update_bits(afe->regmap, reg, mask, val);
	322	return 0;
	323	}
	324
	325	int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)
	326	{
	327	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	328	int i;
	329	unsigned int clk_array[] = {
	330	MT8195_CLK_SCP_ADSP_AUDIODSP, /* bus clock for infra */
	331	MT8195_CLK_TOP_AUDIO_H_SEL, /* clock for ADSP bus */
	332	MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL, /* bus clock for DRAM access */
	333	MT8195_CLK_TOP_AUD_INTBUS_SEL, /* bus clock for AFE SRAM access */
	334	MT8195_CLK_INFRA_AO_AUDIO_26M_B, /* audio 26M clock */
	335	MT8195_CLK_AUD_AFE, /* AFE HW master switch */
	336	MT8195_CLK_AUD_A1SYS_HP, /* AFE HW clock*/
	337	MT8195_CLK_AUD_A1SYS, /* AFE HW clock */
	338	};
	339
	340	for (i = 0; i < ARRAY_SIZE(clk_array); i++)
	341	mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]);
	342
	343	return 0;
	344	}
	345
	346	int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)
	347	{
	348	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	349	int i;
	350	unsigned int clk_array[] = {
	351	MT8195_CLK_AUD_A1SYS,
	352	MT8195_CLK_AUD_A1SYS_HP,
	353	MT8195_CLK_AUD_AFE,
	354	MT8195_CLK_INFRA_AO_AUDIO_26M_B,
	355	MT8195_CLK_TOP_AUD_INTBUS_SEL,
	356	MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL,
	357	MT8195_CLK_TOP_AUDIO_H_SEL,
	358	MT8195_CLK_SCP_ADSP_AUDIODSP,
	359	};
	360
	361	for (i = 0; i < ARRAY_SIZE(clk_array); i++)
	362	mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]);
	363
	364	return 0;
	365	}
	366
	367	static int mt8195_afe_enable_afe_on(struct mtk_base_afe *afe)
	368	{
	369	regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
	370	return 0;
	371	}
	372
	373	static int mt8195_afe_disable_afe_on(struct mtk_base_afe *afe)
	374	{
	375	regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);
	376	return 0;
	377	}
	378
	379	static int mt8195_afe_enable_timing_sys(struct mtk_base_afe *afe)
	380	{
	381	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	382	int i;
	383	unsigned int clk_array[] = {
	384	MT8195_CLK_AUD_A1SYS,
	385	MT8195_CLK_AUD_A2SYS,
	386	};
	387	unsigned int cg_array[] = {
	388	MT8195_TOP_CG_A1SYS_TIMING,
	389	MT8195_TOP_CG_A2SYS_TIMING,
	390	MT8195_TOP_CG_26M_TIMING,
	391	};
	392
	393	for (i = 0; i < ARRAY_SIZE(clk_array); i++)
	394	mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]);
	395
	396	for (i = 0; i < ARRAY_SIZE(cg_array); i++)
	397	mt8195_afe_enable_top_cg(afe, cg_array[i]);
	398
	399	return 0;
	400	}
	401
	402	static int mt8195_afe_disable_timing_sys(struct mtk_base_afe *afe)
	403	{
	404	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	405	int i;
	406	unsigned int clk_array[] = {
	407	MT8195_CLK_AUD_A2SYS,
	408	MT8195_CLK_AUD_A1SYS,
	409	};
	410	unsigned int cg_array[] = {
	411	MT8195_TOP_CG_26M_TIMING,
	412	MT8195_TOP_CG_A2SYS_TIMING,
	413	MT8195_TOP_CG_A1SYS_TIMING,
	414	};
	415
	416	for (i = 0; i < ARRAY_SIZE(cg_array); i++)
	417	mt8195_afe_disable_top_cg(afe, cg_array[i]);
	418
	419	for (i = 0; i < ARRAY_SIZE(clk_array); i++)
	420	mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]);
	421
	422	return 0;
	423	}
	424
	425	int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe)
	426	{
	427	mt8195_afe_enable_timing_sys(afe);
	428
	429	mt8195_afe_enable_afe_on(afe);
	430
	431	return 0;
	432	}
	433
	434	int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe)
	435	{
	436	mt8195_afe_disable_afe_on(afe);
	437
	438	mt8195_afe_disable_timing_sys(afe);
	439
	440	return 0;
	441	}

sound/soc/mediatek/mt8195/mt8195-afe-clk.h+109−0

@@ -0,0 +1,109 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* mt8195-afe-clk.h -- Mediatek 8195 afe clock ctrl definition
	4	*
	5	* Copyright (c) 2021 MediaTek Inc.
	6	* Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
	7	* Trevor Wu <trevor.wu@mediatek.com>
	8	*/
	9
	10	#ifndef _MT8195_AFE_CLK_H_
	11	#define _MT8195_AFE_CLK_H_
	12
	13	enum {
	14	/* xtal */
	15	MT8195_CLK_XTAL_26M,
	16	/* divider */
	17	MT8195_CLK_TOP_APLL1,
	18	MT8195_CLK_TOP_APLL2,
	19	MT8195_CLK_TOP_APLL12_DIV0,
	20	MT8195_CLK_TOP_APLL12_DIV1,
	21	MT8195_CLK_TOP_APLL12_DIV2,
	22	MT8195_CLK_TOP_APLL12_DIV3,
	23	MT8195_CLK_TOP_APLL12_DIV9,
	24	/* mux */
	25	MT8195_CLK_TOP_A1SYS_HP_SEL,
	26	MT8195_CLK_TOP_AUD_INTBUS_SEL,
	27	MT8195_CLK_TOP_AUDIO_H_SEL,
	28	MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL,
	29	MT8195_CLK_TOP_DPTX_M_SEL,
	30	MT8195_CLK_TOP_I2SO1_M_SEL,
	31	MT8195_CLK_TOP_I2SO2_M_SEL,
	32	MT8195_CLK_TOP_I2SI1_M_SEL,
	33	MT8195_CLK_TOP_I2SI2_M_SEL,
	34	/* clock gate */
	35	MT8195_CLK_INFRA_AO_AUDIO_26M_B,
	36	MT8195_CLK_SCP_ADSP_AUDIODSP,
	37	MT8195_CLK_AUD_AFE,
	38	MT8195_CLK_AUD_APLL,
	39	MT8195_CLK_AUD_APLL2,
	40	MT8195_CLK_AUD_DAC,
	41	MT8195_CLK_AUD_ADC,
	42	MT8195_CLK_AUD_DAC_HIRES,
	43	MT8195_CLK_AUD_A1SYS_HP,
	44	MT8195_CLK_AUD_ADC_HIRES,
	45	MT8195_CLK_AUD_ADDA6_ADC,
	46	MT8195_CLK_AUD_ADDA6_ADC_HIRES,
	47	MT8195_CLK_AUD_I2SIN,
	48	MT8195_CLK_AUD_TDM_IN,
	49	MT8195_CLK_AUD_I2S_OUT,
	50	MT8195_CLK_AUD_TDM_OUT,
	51	MT8195_CLK_AUD_HDMI_OUT,
	52	MT8195_CLK_AUD_ASRC11,
	53	MT8195_CLK_AUD_ASRC12,
	54	MT8195_CLK_AUD_A1SYS,
	55	MT8195_CLK_AUD_A2SYS,
	56	MT8195_CLK_AUD_PCMIF,
	57	MT8195_CLK_AUD_MEMIF_UL1,
	58	MT8195_CLK_AUD_MEMIF_UL2,
	59	MT8195_CLK_AUD_MEMIF_UL3,
	60	MT8195_CLK_AUD_MEMIF_UL4,
	61	MT8195_CLK_AUD_MEMIF_UL5,
	62	MT8195_CLK_AUD_MEMIF_UL6,
	63	MT8195_CLK_AUD_MEMIF_UL8,
	64	MT8195_CLK_AUD_MEMIF_UL9,
	65	MT8195_CLK_AUD_MEMIF_UL10,
	66	MT8195_CLK_AUD_MEMIF_DL2,
	67	MT8195_CLK_AUD_MEMIF_DL3,
	68	MT8195_CLK_AUD_MEMIF_DL6,
	69	MT8195_CLK_AUD_MEMIF_DL7,
	70	MT8195_CLK_AUD_MEMIF_DL8,
	71	MT8195_CLK_AUD_MEMIF_DL10,
	72	MT8195_CLK_AUD_MEMIF_DL11,
	73	MT8195_CLK_NUM,
	74	};
	75
	76	enum {
	77	MT8195_MCK_SEL_26M,
	78	MT8195_MCK_SEL_APLL1,
	79	MT8195_MCK_SEL_APLL2,
	80	MT8195_MCK_SEL_APLL3,
	81	MT8195_MCK_SEL_APLL4,
	82	MT8195_MCK_SEL_APLL5,
	83	MT8195_MCK_SEL_HDMIRX_APLL,
	84	MT8195_MCK_SEL_NUM,
	85	};
	86
	87	struct mtk_base_afe;
	88
	89	int mt8195_afe_get_mclk_source_clk_id(int sel);
	90	int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll);
	91	int mt8195_afe_get_default_mclk_source_by_rate(int rate);
	92	int mt8195_afe_init_clock(struct mtk_base_afe *afe);
	93	void mt8195_afe_deinit_clock(struct mtk_base_afe *afe);
	94	int mt8195_afe_enable_clk(struct mtk_base_afe afe, struct clk clk);
	95	void mt8195_afe_disable_clk(struct mtk_base_afe afe, struct clk clk);
	96	int mt8195_afe_prepare_clk(struct mtk_base_afe afe, struct clk clk);
	97	void mt8195_afe_unprepare_clk(struct mtk_base_afe afe, struct clk clk);
	98	int mt8195_afe_enable_clk_atomic(struct mtk_base_afe afe, struct clk clk);
	99	void mt8195_afe_disable_clk_atomic(struct mtk_base_afe afe, struct clk clk);
	100	int mt8195_afe_set_clk_rate(struct mtk_base_afe afe, struct clk clk,
	101	unsigned int rate);
	102	int mt8195_afe_set_clk_parent(struct mtk_base_afe afe, struct clk clk,
	103	struct clk *parent);
	104	int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe);
	105	int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe);
	106	int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe);
	107	int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe);
	108
	109	#endif

sound/soc/mediatek/mt8195/mt8195-afe-common.h+158−0

@@ -0,0 +1,158 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* mt8195-afe-common.h -- Mediatek 8195 audio driver definitions
	4	*
	5	* Copyright (c) 2021 MediaTek Inc.
	6	* Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
	7	* Trevor Wu <trevor.wu@mediatek.com>
	8	*/
	9
	10	#ifndef _MT_8195_AFE_COMMON_H_
	11	#define _MT_8195_AFE_COMMON_H_
	12
	13	#include <sound/soc.h>
	14	#include <linux/list.h>
	15	#include <linux/regmap.h>
	16	#include "../common/mtk-base-afe.h"
	17
	18	enum {
	19	MT8195_DAI_START,
	20	MT8195_AFE_MEMIF_START = MT8195_DAI_START,
	21	MT8195_AFE_MEMIF_DL2 = MT8195_AFE_MEMIF_START,
	22	MT8195_AFE_MEMIF_DL3,
	23	MT8195_AFE_MEMIF_DL6,
	24	MT8195_AFE_MEMIF_DL7,
	25	MT8195_AFE_MEMIF_DL8,
	26	MT8195_AFE_MEMIF_DL10,
	27	MT8195_AFE_MEMIF_DL11,
	28	MT8195_AFE_MEMIF_UL_START,
	29	MT8195_AFE_MEMIF_UL1 = MT8195_AFE_MEMIF_UL_START,
	30	MT8195_AFE_MEMIF_UL2,
	31	MT8195_AFE_MEMIF_UL3,
	32	MT8195_AFE_MEMIF_UL4,
	33	MT8195_AFE_MEMIF_UL5,
	34	MT8195_AFE_MEMIF_UL6,
	35	MT8195_AFE_MEMIF_UL8,
	36	MT8195_AFE_MEMIF_UL9,
	37	MT8195_AFE_MEMIF_UL10,
	38	MT8195_AFE_MEMIF_END,
	39	MT8195_AFE_MEMIF_NUM = (MT8195_AFE_MEMIF_END - MT8195_AFE_MEMIF_START),
	40	MT8195_AFE_IO_START = MT8195_AFE_MEMIF_END,
	41	MT8195_AFE_IO_DL_SRC = MT8195_AFE_IO_START,
	42	MT8195_AFE_IO_DPTX,
	43	MT8195_AFE_IO_ETDM_START,
	44	MT8195_AFE_IO_ETDM1_IN = MT8195_AFE_IO_ETDM_START,
	45	MT8195_AFE_IO_ETDM2_IN,
	46	MT8195_AFE_IO_ETDM1_OUT,
	47	MT8195_AFE_IO_ETDM2_OUT,
	48	MT8195_AFE_IO_ETDM3_OUT,
	49	MT8195_AFE_IO_ETDM_END,
	50	MT8195_AFE_IO_ETDM_NUM =
	51	(MT8195_AFE_IO_ETDM_END - MT8195_AFE_IO_ETDM_START),
	52	MT8195_AFE_IO_PCM = MT8195_AFE_IO_ETDM_END,
	53	MT8195_AFE_IO_UL_SRC1,
	54	MT8195_AFE_IO_UL_SRC2,
	55	MT8195_AFE_IO_END,
	56	MT8195_AFE_IO_NUM = (MT8195_AFE_IO_END - MT8195_AFE_IO_START),
	57	MT8195_DAI_END = MT8195_AFE_IO_END,
	58	MT8195_DAI_NUM = (MT8195_DAI_END - MT8195_DAI_START),
	59	};
	60
	61	enum {
	62	MT8195_TOP_CG_A1SYS_TIMING,
	63	MT8195_TOP_CG_A2SYS_TIMING,
	64	MT8195_TOP_CG_26M_TIMING,
	65	MT8195_TOP_CG_NUM,
	66	};
	67
	68	enum {
	69	MT8195_AFE_IRQ_1,
	70	MT8195_AFE_IRQ_2,
	71	MT8195_AFE_IRQ_3,
	72	MT8195_AFE_IRQ_8,
	73	MT8195_AFE_IRQ_9,
	74	MT8195_AFE_IRQ_10,
	75	MT8195_AFE_IRQ_13,
	76	MT8195_AFE_IRQ_14,
	77	MT8195_AFE_IRQ_15,
	78	MT8195_AFE_IRQ_16,
	79	MT8195_AFE_IRQ_17,
	80	MT8195_AFE_IRQ_18,
	81	MT8195_AFE_IRQ_19,
	82	MT8195_AFE_IRQ_20,
	83	MT8195_AFE_IRQ_21,
	84	MT8195_AFE_IRQ_22,
	85	MT8195_AFE_IRQ_23,
	86	MT8195_AFE_IRQ_24,
	87	MT8195_AFE_IRQ_25,
	88	MT8195_AFE_IRQ_26,
	89	MT8195_AFE_IRQ_27,
	90	MT8195_AFE_IRQ_28,
	91	MT8195_AFE_IRQ_NUM,
	92	};
	93
	94	enum {
	95	MT8195_ETDM_OUT1_1X_EN = 9,
	96	MT8195_ETDM_OUT2_1X_EN = 10,
	97	MT8195_ETDM_OUT3_1X_EN = 11,
	98	MT8195_ETDM_IN1_1X_EN = 12,
	99	MT8195_ETDM_IN2_1X_EN = 13,
	100	MT8195_ETDM_IN1_NX_EN = 25,
	101	MT8195_ETDM_IN2_NX_EN = 26,
	102	};
	103
	104	enum {
	105	MT8195_MTKAIF_MISO_0,
	106	MT8195_MTKAIF_MISO_1,
	107	MT8195_MTKAIF_MISO_2,
	108	MT8195_MTKAIF_MISO_NUM,
	109	};
	110
	111	struct mtk_dai_memif_irq_priv {
	112	unsigned int asys_timing_sel;
	113	};
	114
	115	struct mtkaif_param {
	116	bool mtkaif_calibration_ok;
	117	int mtkaif_chosen_phase[MT8195_MTKAIF_MISO_NUM];
	118	int mtkaif_phase_cycle[MT8195_MTKAIF_MISO_NUM];
	119	int mtkaif_dmic_on;
	120	int mtkaif_adda6_only;
	121	};
	122
	123	struct clk;
	124
	125	struct mt8195_afe_private {
	126	struct clk **clk;
	127	struct clk_lookup **lookup;
	128	struct regmap *topckgen;
	129	int pm_runtime_bypass_reg_ctl;
	130	#ifdef CONFIG_DEBUG_FS
	131	struct dentry **debugfs_dentry;
	132	#endif
	133	int afe_on_ref_cnt;
	134	int top_cg_ref_cnt[MT8195_TOP_CG_NUM];
	135	spinlock_t afe_ctrl_lock; /* Lock for afe control */
	136	struct mtk_dai_memif_irq_priv irq_priv[MT8195_AFE_IRQ_NUM];
	137	struct mtkaif_param mtkaif_params;
	138
	139	/* dai */
	140	void *dai_priv[MT8195_DAI_NUM];
	141	};
	142
	143	int mt8195_afe_fs_timing(unsigned int rate);
	144	/* dai register */
	145	int mt8195_dai_adda_register(struct mtk_base_afe *afe);
	146	int mt8195_dai_etdm_register(struct mtk_base_afe *afe);
	147	int mt8195_dai_pcm_register(struct mtk_base_afe *afe);
	148
	149	#define MT8195_SOC_ENUM_EXT(xname, xenum, xhandler_get, xhandler_put, id) \
	150	{ \
	151	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
	152	.info = snd_soc_info_enum_double, \
	153	.get = xhandler_get, .put = xhandler_put, \
	154	.device = id, \
	155	.private_value = (unsigned long)&xenum, \
	156	}
	157
	158	#endif

sound/soc/mediatek/mt8195/mt8195-afe-pcm.c+3281−0

@@ -0,0 +1,3281 @@
	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Mediatek ALSA SoC AFE platform driver for 8195
	4	*
	5	* Copyright (c) 2021 MediaTek Inc.
	6	* Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
	7	* Trevor Wu <trevor.wu@mediatek.com>
	8	*/
	9
	10	#include <linux/delay.h>
	11	#include <linux/dma-mapping.h>
	12	#include <linux/module.h>
	13	#include <linux/mfd/syscon.h>
	14	#include <linux/of.h>
	15	#include <linux/of_address.h>
	16	#include <linux/of_platform.h>
	17	#include <linux/pm_runtime.h>
	18	#include "mt8195-afe-common.h"
	19	#include "mt8195-afe-clk.h"
	20	#include "mt8195-reg.h"
	21	#include "../common/mtk-afe-platform-driver.h"
	22	#include "../common/mtk-afe-fe-dai.h"
	23
	24	#define MT8195_MEMIF_BUFFER_BYTES_ALIGN (0x40)
	25	#define MT8195_MEMIF_DL7_MAX_PERIOD_SIZE (0x3fff)
	26
	27	struct mtk_dai_memif_priv {
	28	unsigned int asys_timing_sel;
	29	};
	30
	31	static const struct snd_pcm_hardware mt8195_afe_hardware = {
	32	.info = SNDRV_PCM_INFO_MMAP \|
	33	SNDRV_PCM_INFO_INTERLEAVED \|
	34	SNDRV_PCM_INFO_MMAP_VALID,
	35	.formats = SNDRV_PCM_FMTBIT_S16_LE \|
	36	SNDRV_PCM_FMTBIT_S24_LE \|
	37	SNDRV_PCM_FMTBIT_S32_LE,
	38	.period_bytes_min = 64,
	39	.period_bytes_max = 256 * 1024,
	40	.periods_min = 2,
	41	.periods_max = 256,
	42	.buffer_bytes_max = 256 * 2 * 1024,
	43	};
	44
	45	struct mt8195_afe_rate {
	46	unsigned int rate;
	47	unsigned int reg_value;
	48	};
	49
	50	static const struct mt8195_afe_rate mt8195_afe_rates[] = {
	51	{ .rate = 8000, .reg_value = 0, },
	52	{ .rate = 12000, .reg_value = 1, },
	53	{ .rate = 16000, .reg_value = 2, },
	54	{ .rate = 24000, .reg_value = 3, },
	55	{ .rate = 32000, .reg_value = 4, },
	56	{ .rate = 48000, .reg_value = 5, },
	57	{ .rate = 96000, .reg_value = 6, },
	58	{ .rate = 192000, .reg_value = 7, },
	59	{ .rate = 384000, .reg_value = 8, },
	60	{ .rate = 7350, .reg_value = 16, },
	61	{ .rate = 11025, .reg_value = 17, },
	62	{ .rate = 14700, .reg_value = 18, },
	63	{ .rate = 22050, .reg_value = 19, },
	64	{ .rate = 29400, .reg_value = 20, },
	65	{ .rate = 44100, .reg_value = 21, },
	66	{ .rate = 88200, .reg_value = 22, },
	67	{ .rate = 176400, .reg_value = 23, },
	68	{ .rate = 352800, .reg_value = 24, },
	69	};
	70
	71	int mt8195_afe_fs_timing(unsigned int rate)
	72	{
	73	int i;
	74
	75	for (i = 0; i < ARRAY_SIZE(mt8195_afe_rates); i++)
	76	if (mt8195_afe_rates[i].rate == rate)
	77	return mt8195_afe_rates[i].reg_value;
	78
	79	return -EINVAL;
	80	}
	81
	82	static int mt8195_memif_fs(struct snd_pcm_substream *substream,
	83	unsigned int rate)
	84	{
	85	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	86	struct snd_soc_component *component =
	87	snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
	88	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
	89	int id = asoc_rtd_to_cpu(rtd, 0)->id;
	90	struct mtk_base_afe_memif *memif = &afe->memif[id];
	91	int fs = mt8195_afe_fs_timing(rate);
	92
	93	switch (memif->data->id) {
	94	case MT8195_AFE_MEMIF_DL10:
	95	fs = MT8195_ETDM_OUT3_1X_EN;
	96	break;
	97	case MT8195_AFE_MEMIF_UL8:
	98	fs = MT8195_ETDM_IN1_NX_EN;
	99	break;
	100	case MT8195_AFE_MEMIF_UL3:
	101	fs = MT8195_ETDM_IN2_NX_EN;
	102	break;
	103	default:
	104	break;
	105	}
	106
	107	return fs;
	108	}
	109
	110	static int mt8195_irq_fs(struct snd_pcm_substream *substream,
	111	unsigned int rate)
	112	{
	113	int fs = mt8195_memif_fs(substream, rate);
	114
	115	switch (fs) {
	116	case MT8195_ETDM_IN1_NX_EN:
	117	fs = MT8195_ETDM_IN1_1X_EN;
	118	break;
	119	case MT8195_ETDM_IN2_NX_EN:
	120	fs = MT8195_ETDM_IN2_1X_EN;
	121	break;
	122	default:
	123	break;
	124	}
	125
	126	return fs;
	127	}
	128
	129	enum {
	130	MT8195_AFE_CM0,
	131	MT8195_AFE_CM1,
	132	MT8195_AFE_CM2,
	133	MT8195_AFE_CM_NUM,
	134	};
	135
	136	struct mt8195_afe_channel_merge {
	137	int id;
	138	int reg;
	139	unsigned int sel_shift;
	140	unsigned int sel_maskbit;
	141	unsigned int sel_default;
	142	unsigned int ch_num_shift;
	143	unsigned int ch_num_maskbit;
	144	unsigned int en_shift;
	145	unsigned int en_maskbit;
	146	unsigned int update_cnt_shift;
	147	unsigned int update_cnt_maskbit;
	148	unsigned int update_cnt_default;
	149	};
	150
	151	static const struct mt8195_afe_channel_merge
	152	mt8195_afe_cm[MT8195_AFE_CM_NUM] = {
	153	[MT8195_AFE_CM0] = {
	154	.id = MT8195_AFE_CM0,
	155	.reg = AFE_CM0_CON,
	156	.sel_shift = 30,
	157	.sel_maskbit = 0x1,
	158	.sel_default = 1,
	159	.ch_num_shift = 2,
	160	.ch_num_maskbit = 0x3f,
	161	.en_shift = 0,
	162	.en_maskbit = 0x1,
	163	.update_cnt_shift = 16,
	164	.update_cnt_maskbit = 0x1fff,
	165	.update_cnt_default = 0x3,
	166	},
	167	[MT8195_AFE_CM1] = {
	168	.id = MT8195_AFE_CM1,
	169	.reg = AFE_CM1_CON,
	170	.sel_shift = 30,
	171	.sel_maskbit = 0x1,
	172	.sel_default = 1,
	173	.ch_num_shift = 2,
	174	.ch_num_maskbit = 0x1f,
	175	.en_shift = 0,
	176	.en_maskbit = 0x1,
	177	.update_cnt_shift = 16,
	178	.update_cnt_maskbit = 0x1fff,
	179	.update_cnt_default = 0x3,
	180	},
	181	[MT8195_AFE_CM2] = {
	182	.id = MT8195_AFE_CM2,
	183	.reg = AFE_CM2_CON,
	184	.sel_shift = 30,
	185	.sel_maskbit = 0x1,
	186	.sel_default = 1,
	187	.ch_num_shift = 2,
	188	.ch_num_maskbit = 0x1f,
	189	.en_shift = 0,
	190	.en_maskbit = 0x1,
	191	.update_cnt_shift = 16,
	192	.update_cnt_maskbit = 0x1fff,
	193	.update_cnt_default = 0x3,
	194	},
	195	};
	196
	197	static int mt8195_afe_memif_is_ul(int id)
	198	{
	199	if (id >= MT8195_AFE_MEMIF_UL_START && id < MT8195_AFE_MEMIF_END)
	200	return 1;
	201	else
	202	return 0;
	203	}
	204
	205	static const struct mt8195_afe_channel_merge*
	206	mt8195_afe_found_cm(struct snd_soc_dai *dai)
	207	{
	208	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	209	int id = -EINVAL;
	210
	211	if (mt8195_afe_memif_is_ul(dai->id) == 0)
	212	return NULL;
	213
	214	switch (dai->id) {
	215	case MT8195_AFE_MEMIF_UL9:
	216	id = MT8195_AFE_CM0;
	217	break;
	218	case MT8195_AFE_MEMIF_UL2:
	219	id = MT8195_AFE_CM1;
	220	break;
	221	case MT8195_AFE_MEMIF_UL10:
	222	id = MT8195_AFE_CM2;
	223	break;
	224	default:
	225	break;
	226	}
	227
	228	if (id < 0) {
	229	dev_dbg(afe->dev, "%s, memif %d cannot find CM!\n",
	230	__func__, dai->id);
	231	return NULL;
	232	}
	233
	234	return &mt8195_afe_cm[id];
	235	}
	236
	237	static int mt8195_afe_config_cm(struct mtk_base_afe *afe,
	238	const struct mt8195_afe_channel_merge *cm,
	239	unsigned int channels)
	240	{
	241	if (!cm)
	242	return -EINVAL;
	243
	244	regmap_update_bits(afe->regmap,
	245	cm->reg,
	246	cm->sel_maskbit << cm->sel_shift,
	247	cm->sel_default << cm->sel_shift);
	248
	249	regmap_update_bits(afe->regmap,
	250	cm->reg,
	251	cm->ch_num_maskbit << cm->ch_num_shift,
	252	(channels - 1) << cm->ch_num_shift);
	253
	254	regmap_update_bits(afe->regmap,
	255	cm->reg,
	256	cm->update_cnt_maskbit << cm->update_cnt_shift,
	257	cm->update_cnt_default << cm->update_cnt_shift);
	258
	259	return 0;
	260	}
	261
	262	static int mt8195_afe_enable_cm(struct mtk_base_afe *afe,
	263	const struct mt8195_afe_channel_merge *cm,
	264	bool enable)
	265	{
	266	if (!cm)
	267	return -EINVAL;
	268
	269	regmap_update_bits(afe->regmap,
	270	cm->reg,
	271	cm->en_maskbit << cm->en_shift,
	272	enable << cm->en_shift);
	273
	274	return 0;
	275	}
	276
	277	static int
	278	mt8195_afe_paired_memif_clk_prepare(struct snd_pcm_substream *substream,
	279	struct snd_soc_dai *dai,
	280	int enable)
	281	{
	282	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	283	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	284	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	285	int id = asoc_rtd_to_cpu(rtd, 0)->id;
	286	int clk_id;
	287
	288	if (id != MT8195_AFE_MEMIF_DL8 && id != MT8195_AFE_MEMIF_DL10)
	289	return 0;
	290
	291	if (enable) {
	292	clk_id = MT8195_CLK_AUD_MEMIF_DL10;
	293	mt8195_afe_prepare_clk(afe, afe_priv->clk[clk_id]);
	294	clk_id = MT8195_CLK_AUD_MEMIF_DL8;
	295	mt8195_afe_prepare_clk(afe, afe_priv->clk[clk_id]);
	296	} else {
	297	clk_id = MT8195_CLK_AUD_MEMIF_DL8;
	298	mt8195_afe_unprepare_clk(afe, afe_priv->clk[clk_id]);
	299	clk_id = MT8195_CLK_AUD_MEMIF_DL10;
	300	mt8195_afe_unprepare_clk(afe, afe_priv->clk[clk_id]);
	301	}
	302
	303	return 0;
	304	}
	305
	306	static int
	307	mt8195_afe_paired_memif_clk_enable(struct snd_pcm_substream *substream,
	308	struct snd_soc_dai *dai,
	309	int enable)
	310	{
	311	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	312	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	313	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	314	int id = asoc_rtd_to_cpu(rtd, 0)->id;
	315	int clk_id;
	316
	317	if (id != MT8195_AFE_MEMIF_DL8 && id != MT8195_AFE_MEMIF_DL10)
	318	return 0;
	319
	320	if (enable) {
	321	/* DL8_DL10_MEM */
	322	clk_id = MT8195_CLK_AUD_MEMIF_DL10;
	323	mt8195_afe_enable_clk_atomic(afe, afe_priv->clk[clk_id]);
	324	udelay(1);
	325	/* DL8_DL10_AGENT */
	326	clk_id = MT8195_CLK_AUD_MEMIF_DL8;
	327	mt8195_afe_enable_clk_atomic(afe, afe_priv->clk[clk_id]);
	328	} else {
	329	/* DL8_DL10_AGENT */
	330	clk_id = MT8195_CLK_AUD_MEMIF_DL8;
	331	mt8195_afe_disable_clk_atomic(afe, afe_priv->clk[clk_id]);
	332	/* DL8_DL10_MEM */
	333	clk_id = MT8195_CLK_AUD_MEMIF_DL10;
	334	mt8195_afe_disable_clk_atomic(afe, afe_priv->clk[clk_id]);
	335	}
	336
	337	return 0;
	338	}
	339
	340	static int mt8195_afe_fe_startup(struct snd_pcm_substream *substream,
	341	struct snd_soc_dai *dai)
	342	{
	343	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	344	struct snd_pcm_runtime *runtime = substream->runtime;
	345	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	346	int id = asoc_rtd_to_cpu(rtd, 0)->id;
	347	int ret = 0;
	348
	349	mt8195_afe_paired_memif_clk_prepare(substream, dai, 1);
	350
	351	ret = mtk_afe_fe_startup(substream, dai);
	352
	353	snd_pcm_hw_constraint_step(runtime, 0,
	354	SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
	355	MT8195_MEMIF_BUFFER_BYTES_ALIGN);
	356
	357	if (id != MT8195_AFE_MEMIF_DL7)
	358	goto out;
	359
	360	ret = snd_pcm_hw_constraint_minmax(runtime,
	361	SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
	362	1,
	363	MT8195_MEMIF_DL7_MAX_PERIOD_SIZE);
	364	if (ret < 0)
	365	dev_dbg(afe->dev, "hw_constraint_minmax failed\n");
	366	out:
	367	return ret;
	368	}
	369
	370	static void mt8195_afe_fe_shutdown(struct snd_pcm_substream *substream,
	371	struct snd_soc_dai *dai)
	372	{
	373	mtk_afe_fe_shutdown(substream, dai);
	374	mt8195_afe_paired_memif_clk_prepare(substream, dai, 0);
	375	}
	376
	377	static int mt8195_afe_fe_hw_params(struct snd_pcm_substream *substream,
	378	struct snd_pcm_hw_params *params,
	379	struct snd_soc_dai *dai)
	380	{
	381	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	382	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	383	int id = asoc_rtd_to_cpu(rtd, 0)->id;
	384	struct mtk_base_afe_memif *memif = &afe->memif[id];
	385	const struct mtk_base_memif_data *data = memif->data;
	386	const struct mt8195_afe_channel_merge *cm = mt8195_afe_found_cm(dai);
	387	unsigned int ch_num = params_channels(params);
	388
	389	mt8195_afe_config_cm(afe, cm, params_channels(params));
	390
	391	if (data->ch_num_reg >= 0) {
	392	regmap_update_bits(afe->regmap, data->ch_num_reg,
	393	data->ch_num_maskbit << data->ch_num_shift,
	394	ch_num << data->ch_num_shift);
	395	}
	396
	397	return mtk_afe_fe_hw_params(substream, params, dai);
	398	}
	399
	400	static int mt8195_afe_fe_hw_free(struct snd_pcm_substream *substream,
	401	struct snd_soc_dai *dai)
	402	{
	403	return mtk_afe_fe_hw_free(substream, dai);
	404	}
	405
	406	static int mt8195_afe_fe_prepare(struct snd_pcm_substream *substream,
	407	struct snd_soc_dai *dai)
	408	{
	409	return mtk_afe_fe_prepare(substream, dai);
	410	}
	411
	412	static int mt8195_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd,
	413	struct snd_soc_dai *dai)
	414	{
	415	int ret = 0;
	416	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	417	const struct mt8195_afe_channel_merge *cm = mt8195_afe_found_cm(dai);
	418
	419	switch (cmd) {
	420	case SNDRV_PCM_TRIGGER_START:
	421	case SNDRV_PCM_TRIGGER_RESUME:
	422	mt8195_afe_enable_cm(afe, cm, true);
	423	break;
	424	case SNDRV_PCM_TRIGGER_STOP:
	425	case SNDRV_PCM_TRIGGER_SUSPEND:
	426	mt8195_afe_enable_cm(afe, cm, false);
	427	break;
	428	default:
	429	break;
	430	}
	431
	432	ret = mtk_afe_fe_trigger(substream, cmd, dai);
	433
	434	switch (cmd) {
	435	case SNDRV_PCM_TRIGGER_START:
	436	case SNDRV_PCM_TRIGGER_RESUME:
	437	mt8195_afe_paired_memif_clk_enable(substream, dai, 1);
	438	break;
	439	case SNDRV_PCM_TRIGGER_STOP:
	440	case SNDRV_PCM_TRIGGER_SUSPEND:
	441	mt8195_afe_paired_memif_clk_enable(substream, dai, 0);
	442	break;
	443	default:
	444	break;
	445	}
	446
	447	return ret;
	448	}
	449
	450	static int mt8195_afe_fe_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
	451	{
	452	return 0;
	453	}
	454
	455	static const struct snd_soc_dai_ops mt8195_afe_fe_dai_ops = {
	456	.startup = mt8195_afe_fe_startup,
	457	.shutdown = mt8195_afe_fe_shutdown,
	458	.hw_params = mt8195_afe_fe_hw_params,
	459	.hw_free = mt8195_afe_fe_hw_free,
	460	.prepare = mt8195_afe_fe_prepare,
	461	.trigger = mt8195_afe_fe_trigger,
	462	.set_fmt = mt8195_afe_fe_set_fmt,
	463	};
	464
	465	#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 \|\
	466	SNDRV_PCM_RATE_88200 \|\
	467	SNDRV_PCM_RATE_96000 \|\
	468	SNDRV_PCM_RATE_176400 \|\
	469	SNDRV_PCM_RATE_192000 \|\
	470	SNDRV_PCM_RATE_352800 \|\
	471	SNDRV_PCM_RATE_384000)
	472
	473	#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE \|\
	474	SNDRV_PCM_FMTBIT_S24_LE \|\
	475	SNDRV_PCM_FMTBIT_S32_LE)
	476
	477	static struct snd_soc_dai_driver mt8195_memif_dai_driver[] = {
	478	/* FE DAIs: memory intefaces to CPU */
	479	{
	480	.name = "DL2",
	481	.id = MT8195_AFE_MEMIF_DL2,
	482	.playback = {
	483	.stream_name = "DL2",
	484	.channels_min = 1,
	485	.channels_max = 2,
	486	.rates = MTK_PCM_RATES,
	487	.formats = MTK_PCM_FORMATS,
	488	},
	489	.ops = &mt8195_afe_fe_dai_ops,
	490	},
	491	{
	492	.name = "DL3",
	493	.id = MT8195_AFE_MEMIF_DL3,
	494	.playback = {
	495	.stream_name = "DL3",
	496	.channels_min = 1,
	497	.channels_max = 2,
	498	.rates = MTK_PCM_RATES,
	499	.formats = MTK_PCM_FORMATS,
	500	},
	501	.ops = &mt8195_afe_fe_dai_ops,
	502	},
	503	{
	504	.name = "DL6",
	505	.id = MT8195_AFE_MEMIF_DL6,
	506	.playback = {
	507	.stream_name = "DL6",
	508	.channels_min = 1,
	509	.channels_max = 2,
	510	.rates = MTK_PCM_RATES,
	511	.formats = MTK_PCM_FORMATS,
	512	},
	513	.ops = &mt8195_afe_fe_dai_ops,
	514	},
	515	{
	516	.name = "DL7",
	517	.id = MT8195_AFE_MEMIF_DL7,
	518	.playback = {
	519	.stream_name = "DL7",
	520	.channels_min = 1,
	521	.channels_max = 2,
	522	.rates = MTK_PCM_RATES,
	523	.formats = MTK_PCM_FORMATS,
	524	},
	525	.ops = &mt8195_afe_fe_dai_ops,
	526	},
	527	{
	528	.name = "DL8",
	529	.id = MT8195_AFE_MEMIF_DL8,
	530	.playback = {
	531	.stream_name = "DL8",
	532	.channels_min = 1,
	533	.channels_max = 24,
	534	.rates = MTK_PCM_RATES,
	535	.formats = MTK_PCM_FORMATS,
	536	},
	537	.ops = &mt8195_afe_fe_dai_ops,
	538	},
	539	{
	540	.name = "DL10",
	541	.id = MT8195_AFE_MEMIF_DL10,
	542	.playback = {
	543	.stream_name = "DL10",
	544	.channels_min = 1,
	545	.channels_max = 8,
	546	.rates = MTK_PCM_RATES,
	547	.formats = MTK_PCM_FORMATS,
	548	},
	549	.ops = &mt8195_afe_fe_dai_ops,
	550	},
	551	{
	552	.name = "DL11",
	553	.id = MT8195_AFE_MEMIF_DL11,
	554	.playback = {
	555	.stream_name = "DL11",
	556	.channels_min = 1,
	557	.channels_max = 48,
	558	.rates = MTK_PCM_RATES,
	559	.formats = MTK_PCM_FORMATS,
	560	},
	561	.ops = &mt8195_afe_fe_dai_ops,
	562	},
	563	{
	564	.name = "UL1",
	565	.id = MT8195_AFE_MEMIF_UL1,
	566	.capture = {
	567	.stream_name = "UL1",
	568	.channels_min = 1,
	569	.channels_max = 8,
	570	.rates = MTK_PCM_RATES,
	571	.formats = MTK_PCM_FORMATS,
	572	},
	573	.ops = &mt8195_afe_fe_dai_ops,
	574	},
	575	{
	576	.name = "UL2",
	577	.id = MT8195_AFE_MEMIF_UL2,
	578	.capture = {
	579	.stream_name = "UL2",
	580	.channels_min = 1,
	581	.channels_max = 8,
	582	.rates = MTK_PCM_RATES,
	583	.formats = MTK_PCM_FORMATS,
	584	},
	585	.ops = &mt8195_afe_fe_dai_ops,
	586	},
	587	{
	588	.name = "UL3",
	589	.id = MT8195_AFE_MEMIF_UL3,
	590	.capture = {
	591	.stream_name = "UL3",
	592	.channels_min = 1,
	593	.channels_max = 16,
	594	.rates = MTK_PCM_RATES,
	595	.formats = MTK_PCM_FORMATS,
	596	},
	597	.ops = &mt8195_afe_fe_dai_ops,
	598	},
	599	{
	600	.name = "UL4",
	601	.id = MT8195_AFE_MEMIF_UL4,
	602	.capture = {
	603	.stream_name = "UL4",
	604	.channels_min = 1,
	605	.channels_max = 2,
	606	.rates = MTK_PCM_RATES,
	607	.formats = MTK_PCM_FORMATS,
	608	},
	609	.ops = &mt8195_afe_fe_dai_ops,
	610	},
	611	{
	612	.name = "UL5",
	613	.id = MT8195_AFE_MEMIF_UL5,
	614	.capture = {
	615	.stream_name = "UL5",
	616	.channels_min = 1,
	617	.channels_max = 2,
	618	.rates = MTK_PCM_RATES,
	619	.formats = MTK_PCM_FORMATS,
	620	},
	621	.ops = &mt8195_afe_fe_dai_ops,
	622	},
	623	{
	624	.name = "UL6",
	625	.id = MT8195_AFE_MEMIF_UL6,
	626	.capture = {
	627	.stream_name = "UL6",
	628	.channels_min = 1,
	629	.channels_max = 8,
	630	.rates = MTK_PCM_RATES,
	631	.formats = MTK_PCM_FORMATS,
	632	},
	633	.ops = &mt8195_afe_fe_dai_ops,
	634	},
	635	{
	636	.name = "UL8",
	637	.id = MT8195_AFE_MEMIF_UL8,
	638	.capture = {
	639	.stream_name = "UL8",
	640	.channels_min = 1,
	641	.channels_max = 24,
	642	.rates = MTK_PCM_RATES,
	643	.formats = MTK_PCM_FORMATS,
	644	},
	645	.ops = &mt8195_afe_fe_dai_ops,
	646	},
	647	{
	648	.name = "UL9",
	649	.id = MT8195_AFE_MEMIF_UL9,
	650	.capture = {
	651	.stream_name = "UL9",
	652	.channels_min = 1,
	653	.channels_max = 32,
	654	.rates = MTK_PCM_RATES,
	655	.formats = MTK_PCM_FORMATS,
	656	},
	657	.ops = &mt8195_afe_fe_dai_ops,
	658	},
	659	{
	660	.name = "UL10",
	661	.id = MT8195_AFE_MEMIF_UL10,
	662	.capture = {
	663	.stream_name = "UL10",
	664	.channels_min = 1,
	665	.channels_max = 4,
	666	.rates = MTK_PCM_RATES,
	667	.formats = MTK_PCM_FORMATS,
	668	},
	669	.ops = &mt8195_afe_fe_dai_ops,
	670	},
	671	};
	672
	673	static const struct snd_kcontrol_new o002_mix[] = {
	674	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN2, 0, 1, 0),
	675	SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN2, 12, 1, 0),
	676	SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN2, 20, 1, 0),
	677	SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN2, 22, 1, 0),
	678	SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN2_2, 6, 1, 0),
	679	SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN2_2, 8, 1, 0),
	680	SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN2_5, 8, 1, 0),
	681	};
	682
	683	static const struct snd_kcontrol_new o003_mix[] = {
	684	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN3, 1, 1, 0),
	685	SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN3, 13, 1, 0),
	686	SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN3, 21, 1, 0),
	687	SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN3, 23, 1, 0),
	688	SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN3_2, 7, 1, 0),
	689	SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN3_2, 9, 1, 0),
	690	SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN3_5, 9, 1, 0),
	691	};
	692
	693	static const struct snd_kcontrol_new o004_mix[] = {
	694	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN4, 0, 1, 0),
	695	SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN4, 14, 1, 0),
	696	SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN4, 24, 1, 0),
	697	SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN4_2, 10, 1, 0),
	698	SOC_DAPM_SINGLE_AUTODISABLE("I170 Switch", AFE_CONN4_5, 10, 1, 0),
	699	};
	700
	701	static const struct snd_kcontrol_new o005_mix[] = {
	702	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN5, 1, 1, 0),
	703	SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN5, 15, 1, 0),
	704	SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN5, 25, 1, 0),
	705	SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN5_2, 11, 1, 0),
	706	SOC_DAPM_SINGLE_AUTODISABLE("I171 Switch", AFE_CONN5_5, 11, 1, 0),
	707	};
	708
	709	static const struct snd_kcontrol_new o006_mix[] = {
	710	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN6, 0, 1, 0),
	711	SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN6, 16, 1, 0),
	712	SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN6, 26, 1, 0),
	713	SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN6_2, 12, 1, 0),
	714	};
	715
	716	static const struct snd_kcontrol_new o007_mix[] = {
	717	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN7, 1, 1, 0),
	718	SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN7, 17, 1, 0),
	719	SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN7, 27, 1, 0),
	720	SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN7_2, 13, 1, 0),
	721	};
	722
	723	static const struct snd_kcontrol_new o008_mix[] = {
	724	SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN8, 18, 1, 0),
	725	SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN8, 28, 1, 0),
	726	SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN8_2, 14, 1, 0),
	727	};
	728
	729	static const struct snd_kcontrol_new o009_mix[] = {
	730	SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN9, 19, 1, 0),
	731	SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN9, 29, 1, 0),
	732	SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN9_2, 15, 1, 0),
	733	};
	734
	735	static const struct snd_kcontrol_new o010_mix[] = {
	736	SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN10, 22, 1, 0),
	737	SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN10, 30, 1, 0),
	738	SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN10_1, 14, 1, 0),
	739	SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN10_2, 8, 1, 0),
	740	};
	741
	742	static const struct snd_kcontrol_new o011_mix[] = {
	743	SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN11, 23, 1, 0),
	744	SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN11, 31, 1, 0),
	745	SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN11_1, 15, 1, 0),
	746	SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN11_2, 9, 1, 0),
	747	};
	748
	749	static const struct snd_kcontrol_new o012_mix[] = {
	750	SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN12, 24, 1, 0),
	751	SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN12_1, 0, 1, 0),
	752	SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN12_1, 16, 1, 0),
	753	SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN12_2, 10, 1, 0),
	754	};
	755
	756	static const struct snd_kcontrol_new o013_mix[] = {
	757	SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN13, 25, 1, 0),
	758	SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN13_1, 1, 1, 0),
	759	SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN13_1, 17, 1, 0),
	760	SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN13_2, 11, 1, 0),
	761	};
	762
	763	static const struct snd_kcontrol_new o014_mix[] = {
	764	SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN14, 26, 1, 0),
	765	SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN14_1, 2, 1, 0),
	766	SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN14_1, 18, 1, 0),
	767	SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN14_2, 12, 1, 0),
	768	};
	769
	770	static const struct snd_kcontrol_new o015_mix[] = {
	771	SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN15, 27, 1, 0),
	772	SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN15_1, 3, 1, 0),
	773	SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN15_1, 19, 1, 0),
	774	SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN15_2, 13, 1, 0),
	775	};
	776
	777	static const struct snd_kcontrol_new o016_mix[] = {
	778	SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN16, 28, 1, 0),
	779	SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN16_1, 4, 1, 0),
	780	SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN16_1, 20, 1, 0),
	781	SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN16_2, 14, 1, 0),
	782	};
	783
	784	static const struct snd_kcontrol_new o017_mix[] = {
	785	SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN17, 29, 1, 0),
	786	SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN17_1, 5, 1, 0),
	787	SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN17_1, 21, 1, 0),
	788	SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN17_2, 15, 1, 0),
	789	};
	790
	791	static const struct snd_kcontrol_new o018_mix[] = {
	792	SOC_DAPM_SINGLE_AUTODISABLE("I038 Switch", AFE_CONN18_1, 6, 1, 0),
	793	SOC_DAPM_SINGLE_AUTODISABLE("I080 Switch", AFE_CONN18_2, 16, 1, 0),
	794	};
	795
	796	static const struct snd_kcontrol_new o019_mix[] = {
	797	SOC_DAPM_SINGLE_AUTODISABLE("I039 Switch", AFE_CONN19_1, 7, 1, 0),
	798	SOC_DAPM_SINGLE_AUTODISABLE("I081 Switch", AFE_CONN19_2, 17, 1, 0),
	799	};
	800
	801	static const struct snd_kcontrol_new o020_mix[] = {
	802	SOC_DAPM_SINGLE_AUTODISABLE("I040 Switch", AFE_CONN20_1, 8, 1, 0),
	803	SOC_DAPM_SINGLE_AUTODISABLE("I082 Switch", AFE_CONN20_2, 18, 1, 0),
	804	};
	805
	806	static const struct snd_kcontrol_new o021_mix[] = {
	807	SOC_DAPM_SINGLE_AUTODISABLE("I041 Switch", AFE_CONN21_1, 9, 1, 0),
	808	SOC_DAPM_SINGLE_AUTODISABLE("I083 Switch", AFE_CONN21_2, 19, 1, 0),
	809	};
	810
	811	static const struct snd_kcontrol_new o022_mix[] = {
	812	SOC_DAPM_SINGLE_AUTODISABLE("I042 Switch", AFE_CONN22_1, 10, 1, 0),
	813	SOC_DAPM_SINGLE_AUTODISABLE("I084 Switch", AFE_CONN22_2, 20, 1, 0),
	814	};
	815
	816	static const struct snd_kcontrol_new o023_mix[] = {
	817	SOC_DAPM_SINGLE_AUTODISABLE("I043 Switch", AFE_CONN23_1, 11, 1, 0),
	818	SOC_DAPM_SINGLE_AUTODISABLE("I085 Switch", AFE_CONN23_2, 21, 1, 0),
	819	};
	820
	821	static const struct snd_kcontrol_new o024_mix[] = {
	822	SOC_DAPM_SINGLE_AUTODISABLE("I044 Switch", AFE_CONN24_1, 12, 1, 0),
	823	SOC_DAPM_SINGLE_AUTODISABLE("I086 Switch", AFE_CONN24_2, 22, 1, 0),
	824	};
	825
	826	static const struct snd_kcontrol_new o025_mix[] = {
	827	SOC_DAPM_SINGLE_AUTODISABLE("I045 Switch", AFE_CONN25_1, 13, 1, 0),
	828	SOC_DAPM_SINGLE_AUTODISABLE("I087 Switch", AFE_CONN25_2, 23, 1, 0),
	829	};
	830
	831	static const struct snd_kcontrol_new o026_mix[] = {
	832	SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN26_1, 14, 1, 0),
	833	SOC_DAPM_SINGLE_AUTODISABLE("I088 Switch", AFE_CONN26_2, 24, 1, 0),
	834	};
	835
	836	static const struct snd_kcontrol_new o027_mix[] = {
	837	SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN27_1, 15, 1, 0),
	838	SOC_DAPM_SINGLE_AUTODISABLE("I089 Switch", AFE_CONN27_2, 25, 1, 0),
	839	};
	840
	841	static const struct snd_kcontrol_new o028_mix[] = {
	842	SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN28_1, 16, 1, 0),
	843	SOC_DAPM_SINGLE_AUTODISABLE("I090 Switch", AFE_CONN28_2, 26, 1, 0),
	844	};
	845
	846	static const struct snd_kcontrol_new o029_mix[] = {
	847	SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN29_1, 17, 1, 0),
	848	SOC_DAPM_SINGLE_AUTODISABLE("I091 Switch", AFE_CONN29_2, 27, 1, 0),
	849	};
	850
	851	static const struct snd_kcontrol_new o030_mix[] = {
	852	SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN30_1, 18, 1, 0),
	853	SOC_DAPM_SINGLE_AUTODISABLE("I092 Switch", AFE_CONN30_2, 28, 1, 0),
	854	};
	855
	856	static const struct snd_kcontrol_new o031_mix[] = {
	857	SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN31_1, 19, 1, 0),
	858	SOC_DAPM_SINGLE_AUTODISABLE("I093 Switch", AFE_CONN31_2, 29, 1, 0),
	859	};
	860
	861	static const struct snd_kcontrol_new o032_mix[] = {
	862	SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN32_1, 20, 1, 0),
	863	SOC_DAPM_SINGLE_AUTODISABLE("I094 Switch", AFE_CONN32_2, 30, 1, 0),
	864	};
	865
	866	static const struct snd_kcontrol_new o033_mix[] = {
	867	SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN33_1, 21, 1, 0),
	868	SOC_DAPM_SINGLE_AUTODISABLE("I095 Switch", AFE_CONN33_2, 31, 1, 0),
	869	};
	870
	871	static const struct snd_kcontrol_new o034_mix[] = {
	872	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN34, 0, 1, 0),
	873	SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN34, 2, 1, 0),
	874	SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN34, 12, 1, 0),
	875	SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN34, 20, 1, 0),
	876	SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN34_2, 6, 1, 0),
	877	SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN34_2, 8, 1, 0),
	878	SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN34_5, 8, 1, 0),
	879	SOC_DAPM_SINGLE_AUTODISABLE("I170 Switch", AFE_CONN34_5, 10, 1, 0),
	880	};
	881
	882	static const struct snd_kcontrol_new o035_mix[] = {
	883	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN35, 1, 1, 0),
	884	SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN35, 3, 1, 0),
	885	SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN35, 13, 1, 0),
	886	SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN35, 21, 1, 0),
	887	SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN35_2, 7, 1, 0),
	888	SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN35_2, 9, 1, 0),
	889	SOC_DAPM_SINGLE_AUTODISABLE("I137 Switch", AFE_CONN35_4, 9, 1, 0),
	890	SOC_DAPM_SINGLE_AUTODISABLE("I139 Switch", AFE_CONN35_4, 11, 1, 0),
	891	SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN35_5, 8, 1, 0),
	892	SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN35_5, 9, 1, 0),
	893	SOC_DAPM_SINGLE_AUTODISABLE("I170 Switch", AFE_CONN35_5, 10, 1, 0),
	894	SOC_DAPM_SINGLE_AUTODISABLE("I171 Switch", AFE_CONN35_5, 11, 1, 0),
	895	};
	896
	897	static const struct snd_kcontrol_new o036_mix[] = {
	898	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN36, 0, 1, 0),
	899	SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN36, 12, 1, 0),
	900	SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN36, 20, 1, 0),
	901	SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN36_2, 6, 1, 0),
	902	SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN36_5, 8, 1, 0),
	903	};
	904
	905	static const struct snd_kcontrol_new o037_mix[] = {
	906	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN37, 1, 1, 0),
	907	SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN37, 13, 1, 0),
	908	SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN37, 21, 1, 0),
	909	SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN37_2, 7, 1, 0),
	910	SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN37_5, 9, 1, 0),
	911	};
	912
	913	static const struct snd_kcontrol_new o038_mix[] = {
	914	SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN38, 22, 1, 0),
	915	};
	916
	917	static const struct snd_kcontrol_new o039_mix[] = {
	918	SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN39, 23, 1, 0),
	919	};
	920
	921	static const struct snd_kcontrol_new o040_mix[] = {
	922	SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN40, 2, 1, 0),
	923	SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN40, 12, 1, 0),
	924	SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN40, 22, 1, 0),
	925	SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN40_5, 8, 1, 0),
	926	};
	927
	928	static const struct snd_kcontrol_new o041_mix[] = {
	929	SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN41, 3, 1, 0),
	930	SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN41, 13, 1, 0),
	931	SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN41, 23, 1, 0),
	932	SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN41_5, 9, 1, 0),
	933	};
	934
	935	static const struct snd_kcontrol_new o042_mix[] = {
	936	SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN42, 14, 1, 0),
	937	SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN42, 24, 1, 0),
	938	SOC_DAPM_SINGLE_AUTODISABLE("I170 Switch", AFE_CONN42_5, 10, 1, 0),
	939	};
	940
	941	static const struct snd_kcontrol_new o043_mix[] = {
	942	SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN43, 15, 1, 0),
	943	SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN43, 25, 1, 0),
	944	SOC_DAPM_SINGLE_AUTODISABLE("I171 Switch", AFE_CONN43_5, 11, 1, 0),
	945	};
	946
	947	static const struct snd_kcontrol_new o044_mix[] = {
	948	SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN44, 16, 1, 0),
	949	SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN44, 26, 1, 0),
	950	};
	951
	952	static const struct snd_kcontrol_new o045_mix[] = {
	953	SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN45, 17, 1, 0),
	954	SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN45, 27, 1, 0),
	955	};
	956
	957	static const struct snd_kcontrol_new o046_mix[] = {
	958	SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN46, 18, 1, 0),
	959	SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN46, 28, 1, 0),
	960	};
	961
	962	static const struct snd_kcontrol_new o047_mix[] = {
	963	SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN47, 19, 1, 0),
	964	SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN47, 29, 1, 0),
	965	};
	966
	967	static const struct snd_kcontrol_new o182_mix[] = {
	968	SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN182, 24, 1, 0),
	969	};
	970
	971	static const struct snd_kcontrol_new o183_mix[] = {
	972	SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN183, 25, 1, 0),
	973	};
	974
	975	static const char * const dl8_dl11_data_sel_mux_text[] = {
	976	"dl8", "dl11",
	977	};
	978
	979	static SOC_ENUM_SINGLE_DECL(dl8_dl11_data_sel_mux_enum,
	980	AFE_DAC_CON2, 0, dl8_dl11_data_sel_mux_text);
	981
	982	static const struct snd_kcontrol_new dl8_dl11_data_sel_mux =
	983	SOC_DAPM_ENUM("DL8_DL11 Sink", dl8_dl11_data_sel_mux_enum);
	984
	985	static const struct snd_soc_dapm_widget mt8195_memif_widgets[] = {
	986	/* DL6 */
	987	SND_SOC_DAPM_MIXER("I000", SND_SOC_NOPM, 0, 0, NULL, 0),
	988	SND_SOC_DAPM_MIXER("I001", SND_SOC_NOPM, 0, 0, NULL, 0),
	989
	990	/* DL3 */
	991	SND_SOC_DAPM_MIXER("I020", SND_SOC_NOPM, 0, 0, NULL, 0),
	992	SND_SOC_DAPM_MIXER("I021", SND_SOC_NOPM, 0, 0, NULL, 0),
	993
	994	/* DL11 */
	995	SND_SOC_DAPM_MIXER("I022", SND_SOC_NOPM, 0, 0, NULL, 0),
	996	SND_SOC_DAPM_MIXER("I023", SND_SOC_NOPM, 0, 0, NULL, 0),
	997	SND_SOC_DAPM_MIXER("I024", SND_SOC_NOPM, 0, 0, NULL, 0),
	998	SND_SOC_DAPM_MIXER("I025", SND_SOC_NOPM, 0, 0, NULL, 0),
	999	SND_SOC_DAPM_MIXER("I026", SND_SOC_NOPM, 0, 0, NULL, 0),
	1000	SND_SOC_DAPM_MIXER("I027", SND_SOC_NOPM, 0, 0, NULL, 0),
	1001	SND_SOC_DAPM_MIXER("I028", SND_SOC_NOPM, 0, 0, NULL, 0),
	1002	SND_SOC_DAPM_MIXER("I029", SND_SOC_NOPM, 0, 0, NULL, 0),
	1003	SND_SOC_DAPM_MIXER("I030", SND_SOC_NOPM, 0, 0, NULL, 0),
	1004	SND_SOC_DAPM_MIXER("I031", SND_SOC_NOPM, 0, 0, NULL, 0),
	1005	SND_SOC_DAPM_MIXER("I032", SND_SOC_NOPM, 0, 0, NULL, 0),
	1006	SND_SOC_DAPM_MIXER("I033", SND_SOC_NOPM, 0, 0, NULL, 0),
	1007	SND_SOC_DAPM_MIXER("I034", SND_SOC_NOPM, 0, 0, NULL, 0),
	1008	SND_SOC_DAPM_MIXER("I035", SND_SOC_NOPM, 0, 0, NULL, 0),
	1009	SND_SOC_DAPM_MIXER("I036", SND_SOC_NOPM, 0, 0, NULL, 0),
	1010	SND_SOC_DAPM_MIXER("I037", SND_SOC_NOPM, 0, 0, NULL, 0),
	1011	SND_SOC_DAPM_MIXER("I038", SND_SOC_NOPM, 0, 0, NULL, 0),
	1012	SND_SOC_DAPM_MIXER("I039", SND_SOC_NOPM, 0, 0, NULL, 0),
	1013	SND_SOC_DAPM_MIXER("I040", SND_SOC_NOPM, 0, 0, NULL, 0),
	1014	SND_SOC_DAPM_MIXER("I041", SND_SOC_NOPM, 0, 0, NULL, 0),
	1015	SND_SOC_DAPM_MIXER("I042", SND_SOC_NOPM, 0, 0, NULL, 0),
	1016	SND_SOC_DAPM_MIXER("I043", SND_SOC_NOPM, 0, 0, NULL, 0),
	1017	SND_SOC_DAPM_MIXER("I044", SND_SOC_NOPM, 0, 0, NULL, 0),
	1018	SND_SOC_DAPM_MIXER("I045", SND_SOC_NOPM, 0, 0, NULL, 0),
	1019
	1020	/* DL11/DL8 */
	1021	SND_SOC_DAPM_MIXER("I046", SND_SOC_NOPM, 0, 0, NULL, 0),
	1022	SND_SOC_DAPM_MIXER("I047", SND_SOC_NOPM, 0, 0, NULL, 0),
	1023	SND_SOC_DAPM_MIXER("I048", SND_SOC_NOPM, 0, 0, NULL, 0),
	1024	SND_SOC_DAPM_MIXER("I049", SND_SOC_NOPM, 0, 0, NULL, 0),
	1025	SND_SOC_DAPM_MIXER("I050", SND_SOC_NOPM, 0, 0, NULL, 0),
	1026	SND_SOC_DAPM_MIXER("I051", SND_SOC_NOPM, 0, 0, NULL, 0),
	1027	SND_SOC_DAPM_MIXER("I052", SND_SOC_NOPM, 0, 0, NULL, 0),
	1028	SND_SOC_DAPM_MIXER("I053", SND_SOC_NOPM, 0, 0, NULL, 0),
	1029	SND_SOC_DAPM_MIXER("I054", SND_SOC_NOPM, 0, 0, NULL, 0),
	1030	SND_SOC_DAPM_MIXER("I055", SND_SOC_NOPM, 0, 0, NULL, 0),
	1031	SND_SOC_DAPM_MIXER("I056", SND_SOC_NOPM, 0, 0, NULL, 0),
	1032	SND_SOC_DAPM_MIXER("I057", SND_SOC_NOPM, 0, 0, NULL, 0),
	1033	SND_SOC_DAPM_MIXER("I058", SND_SOC_NOPM, 0, 0, NULL, 0),
	1034	SND_SOC_DAPM_MIXER("I059", SND_SOC_NOPM, 0, 0, NULL, 0),
	1035	SND_SOC_DAPM_MIXER("I060", SND_SOC_NOPM, 0, 0, NULL, 0),
	1036	SND_SOC_DAPM_MIXER("I061", SND_SOC_NOPM, 0, 0, NULL, 0),
	1037	SND_SOC_DAPM_MIXER("I062", SND_SOC_NOPM, 0, 0, NULL, 0),
	1038	SND_SOC_DAPM_MIXER("I063", SND_SOC_NOPM, 0, 0, NULL, 0),
	1039	SND_SOC_DAPM_MIXER("I064", SND_SOC_NOPM, 0, 0, NULL, 0),
	1040	SND_SOC_DAPM_MIXER("I065", SND_SOC_NOPM, 0, 0, NULL, 0),
	1041	SND_SOC_DAPM_MIXER("I066", SND_SOC_NOPM, 0, 0, NULL, 0),
	1042	SND_SOC_DAPM_MIXER("I067", SND_SOC_NOPM, 0, 0, NULL, 0),
	1043	SND_SOC_DAPM_MIXER("I068", SND_SOC_NOPM, 0, 0, NULL, 0),
	1044	SND_SOC_DAPM_MIXER("I069", SND_SOC_NOPM, 0, 0, NULL, 0),
	1045
	1046	/* DL2 */
	1047	SND_SOC_DAPM_MIXER("I070", SND_SOC_NOPM, 0, 0, NULL, 0),
	1048	SND_SOC_DAPM_MIXER("I071", SND_SOC_NOPM, 0, 0, NULL, 0),
	1049
	1050	SND_SOC_DAPM_MUX("DL8_DL11 Mux",
	1051	SND_SOC_NOPM, 0, 0, &dl8_dl11_data_sel_mux),
	1052
	1053	/* UL9 */
	1054	SND_SOC_DAPM_MIXER("O002", SND_SOC_NOPM, 0, 0,
	1055	o002_mix, ARRAY_SIZE(o002_mix)),
	1056	SND_SOC_DAPM_MIXER("O003", SND_SOC_NOPM, 0, 0,
	1057	o003_mix, ARRAY_SIZE(o003_mix)),
	1058	SND_SOC_DAPM_MIXER("O004", SND_SOC_NOPM, 0, 0,
	1059	o004_mix, ARRAY_SIZE(o004_mix)),
	1060	SND_SOC_DAPM_MIXER("O005", SND_SOC_NOPM, 0, 0,
	1061	o005_mix, ARRAY_SIZE(o005_mix)),
	1062	SND_SOC_DAPM_MIXER("O006", SND_SOC_NOPM, 0, 0,
	1063	o006_mix, ARRAY_SIZE(o006_mix)),
	1064	SND_SOC_DAPM_MIXER("O007", SND_SOC_NOPM, 0, 0,
	1065	o007_mix, ARRAY_SIZE(o007_mix)),
	1066	SND_SOC_DAPM_MIXER("O008", SND_SOC_NOPM, 0, 0,
	1067	o008_mix, ARRAY_SIZE(o008_mix)),
	1068	SND_SOC_DAPM_MIXER("O009", SND_SOC_NOPM, 0, 0,
	1069	o009_mix, ARRAY_SIZE(o009_mix)),
	1070	SND_SOC_DAPM_MIXER("O010", SND_SOC_NOPM, 0, 0,
	1071	o010_mix, ARRAY_SIZE(o010_mix)),
	1072	SND_SOC_DAPM_MIXER("O011", SND_SOC_NOPM, 0, 0,
	1073	o011_mix, ARRAY_SIZE(o011_mix)),
	1074	SND_SOC_DAPM_MIXER("O012", SND_SOC_NOPM, 0, 0,
	1075	o012_mix, ARRAY_SIZE(o012_mix)),
	1076	SND_SOC_DAPM_MIXER("O013", SND_SOC_NOPM, 0, 0,
	1077	o013_mix, ARRAY_SIZE(o013_mix)),
	1078	SND_SOC_DAPM_MIXER("O014", SND_SOC_NOPM, 0, 0,
	1079	o014_mix, ARRAY_SIZE(o014_mix)),
	1080	SND_SOC_DAPM_MIXER("O015", SND_SOC_NOPM, 0, 0,
	1081	o015_mix, ARRAY_SIZE(o015_mix)),
	1082	SND_SOC_DAPM_MIXER("O016", SND_SOC_NOPM, 0, 0,
	1083	o016_mix, ARRAY_SIZE(o016_mix)),
	1084	SND_SOC_DAPM_MIXER("O017", SND_SOC_NOPM, 0, 0,
	1085	o017_mix, ARRAY_SIZE(o017_mix)),
	1086	SND_SOC_DAPM_MIXER("O018", SND_SOC_NOPM, 0, 0,
	1087	o018_mix, ARRAY_SIZE(o018_mix)),
	1088	SND_SOC_DAPM_MIXER("O019", SND_SOC_NOPM, 0, 0,
	1089	o019_mix, ARRAY_SIZE(o019_mix)),
	1090	SND_SOC_DAPM_MIXER("O020", SND_SOC_NOPM, 0, 0,
	1091	o020_mix, ARRAY_SIZE(o020_mix)),
	1092	SND_SOC_DAPM_MIXER("O021", SND_SOC_NOPM, 0, 0,
	1093	o021_mix, ARRAY_SIZE(o021_mix)),
	1094	SND_SOC_DAPM_MIXER("O022", SND_SOC_NOPM, 0, 0,
	1095	o022_mix, ARRAY_SIZE(o022_mix)),
	1096	SND_SOC_DAPM_MIXER("O023", SND_SOC_NOPM, 0, 0,
	1097	o023_mix, ARRAY_SIZE(o023_mix)),
	1098	SND_SOC_DAPM_MIXER("O024", SND_SOC_NOPM, 0, 0,
	1099	o024_mix, ARRAY_SIZE(o024_mix)),
	1100	SND_SOC_DAPM_MIXER("O025", SND_SOC_NOPM, 0, 0,
	1101	o025_mix, ARRAY_SIZE(o025_mix)),
	1102	SND_SOC_DAPM_MIXER("O026", SND_SOC_NOPM, 0, 0,
	1103	o026_mix, ARRAY_SIZE(o026_mix)),
	1104	SND_SOC_DAPM_MIXER("O027", SND_SOC_NOPM, 0, 0,
	1105	o027_mix, ARRAY_SIZE(o027_mix)),
	1106	SND_SOC_DAPM_MIXER("O028", SND_SOC_NOPM, 0, 0,
	1107	o028_mix, ARRAY_SIZE(o028_mix)),
	1108	SND_SOC_DAPM_MIXER("O029", SND_SOC_NOPM, 0, 0,
	1109	o029_mix, ARRAY_SIZE(o029_mix)),
	1110	SND_SOC_DAPM_MIXER("O030", SND_SOC_NOPM, 0, 0,
	1111	o030_mix, ARRAY_SIZE(o030_mix)),
	1112	SND_SOC_DAPM_MIXER("O031", SND_SOC_NOPM, 0, 0,
	1113	o031_mix, ARRAY_SIZE(o031_mix)),
	1114	SND_SOC_DAPM_MIXER("O032", SND_SOC_NOPM, 0, 0,
	1115	o032_mix, ARRAY_SIZE(o032_mix)),
	1116	SND_SOC_DAPM_MIXER("O033", SND_SOC_NOPM, 0, 0,
	1117	o033_mix, ARRAY_SIZE(o033_mix)),
	1118
	1119	/* UL4 */
	1120	SND_SOC_DAPM_MIXER("O034", SND_SOC_NOPM, 0, 0,
	1121	o034_mix, ARRAY_SIZE(o034_mix)),
	1122	SND_SOC_DAPM_MIXER("O035", SND_SOC_NOPM, 0, 0,
	1123	o035_mix, ARRAY_SIZE(o035_mix)),
	1124
	1125	/* UL5 */
	1126	SND_SOC_DAPM_MIXER("O036", SND_SOC_NOPM, 0, 0,
	1127	o036_mix, ARRAY_SIZE(o036_mix)),
	1128	SND_SOC_DAPM_MIXER("O037", SND_SOC_NOPM, 0, 0,
	1129	o037_mix, ARRAY_SIZE(o037_mix)),
	1130
	1131	/* UL10 */
	1132	SND_SOC_DAPM_MIXER("O038", SND_SOC_NOPM, 0, 0,
	1133	o038_mix, ARRAY_SIZE(o038_mix)),
	1134	SND_SOC_DAPM_MIXER("O039", SND_SOC_NOPM, 0, 0,
	1135	o039_mix, ARRAY_SIZE(o039_mix)),
	1136	SND_SOC_DAPM_MIXER("O182", SND_SOC_NOPM, 0, 0,
	1137	o182_mix, ARRAY_SIZE(o182_mix)),
	1138	SND_SOC_DAPM_MIXER("O183", SND_SOC_NOPM, 0, 0,
	1139	o183_mix, ARRAY_SIZE(o183_mix)),
	1140
	1141	/* UL2 */
	1142	SND_SOC_DAPM_MIXER("O040", SND_SOC_NOPM, 0, 0,
	1143	o040_mix, ARRAY_SIZE(o040_mix)),
	1144	SND_SOC_DAPM_MIXER("O041", SND_SOC_NOPM, 0, 0,
	1145	o041_mix, ARRAY_SIZE(o041_mix)),
	1146	SND_SOC_DAPM_MIXER("O042", SND_SOC_NOPM, 0, 0,
	1147	o042_mix, ARRAY_SIZE(o042_mix)),
	1148	SND_SOC_DAPM_MIXER("O043", SND_SOC_NOPM, 0, 0,
	1149	o043_mix, ARRAY_SIZE(o043_mix)),
	1150	SND_SOC_DAPM_MIXER("O044", SND_SOC_NOPM, 0, 0,
	1151	o044_mix, ARRAY_SIZE(o044_mix)),
	1152	SND_SOC_DAPM_MIXER("O045", SND_SOC_NOPM, 0, 0,
	1153	o045_mix, ARRAY_SIZE(o045_mix)),
	1154	SND_SOC_DAPM_MIXER("O046", SND_SOC_NOPM, 0, 0,
	1155	o046_mix, ARRAY_SIZE(o046_mix)),
	1156	SND_SOC_DAPM_MIXER("O047", SND_SOC_NOPM, 0, 0,
	1157	o047_mix, ARRAY_SIZE(o047_mix)),
	1158	};
	1159
	1160	static const struct snd_soc_dapm_route mt8195_memif_routes[] = {
	1161	{"I000", NULL, "DL6"},
	1162	{"I001", NULL, "DL6"},
	1163
	1164	{"I020", NULL, "DL3"},
	1165	{"I021", NULL, "DL3"},
	1166
	1167	{"I022", NULL, "DL11"},
	1168	{"I023", NULL, "DL11"},
	1169	{"I024", NULL, "DL11"},
	1170	{"I025", NULL, "DL11"},
	1171	{"I026", NULL, "DL11"},
	1172	{"I027", NULL, "DL11"},
	1173	{"I028", NULL, "DL11"},
	1174	{"I029", NULL, "DL11"},
	1175	{"I030", NULL, "DL11"},
	1176	{"I031", NULL, "DL11"},
	1177	{"I032", NULL, "DL11"},
	1178	{"I033", NULL, "DL11"},
	1179	{"I034", NULL, "DL11"},
	1180	{"I035", NULL, "DL11"},
	1181	{"I036", NULL, "DL11"},
	1182	{"I037", NULL, "DL11"},
	1183	{"I038", NULL, "DL11"},
	1184	{"I039", NULL, "DL11"},
	1185	{"I040", NULL, "DL11"},
	1186	{"I041", NULL, "DL11"},
	1187	{"I042", NULL, "DL11"},
	1188	{"I043", NULL, "DL11"},
	1189	{"I044", NULL, "DL11"},
	1190	{"I045", NULL, "DL11"},
	1191
	1192	{"DL8_DL11 Mux", "dl8", "DL8"},
	1193	{"DL8_DL11 Mux", "dl11", "DL11"},
	1194
	1195	{"I046", NULL, "DL8_DL11 Mux"},
	1196	{"I047", NULL, "DL8_DL11 Mux"},
	1197	{"I048", NULL, "DL8_DL11 Mux"},
	1198	{"I049", NULL, "DL8_DL11 Mux"},
	1199	{"I050", NULL, "DL8_DL11 Mux"},
	1200	{"I051", NULL, "DL8_DL11 Mux"},
	1201	{"I052", NULL, "DL8_DL11 Mux"},
	1202	{"I053", NULL, "DL8_DL11 Mux"},
	1203	{"I054", NULL, "DL8_DL11 Mux"},
	1204	{"I055", NULL, "DL8_DL11 Mux"},
	1205	{"I056", NULL, "DL8_DL11 Mux"},
	1206	{"I057", NULL, "DL8_DL11 Mux"},
	1207	{"I058", NULL, "DL8_DL11 Mux"},
	1208	{"I059", NULL, "DL8_DL11 Mux"},
	1209	{"I060", NULL, "DL8_DL11 Mux"},
	1210	{"I061", NULL, "DL8_DL11 Mux"},
	1211	{"I062", NULL, "DL8_DL11 Mux"},
	1212	{"I063", NULL, "DL8_DL11 Mux"},
	1213	{"I064", NULL, "DL8_DL11 Mux"},
	1214	{"I065", NULL, "DL8_DL11 Mux"},
	1215	{"I066", NULL, "DL8_DL11 Mux"},
	1216	{"I067", NULL, "DL8_DL11 Mux"},
	1217	{"I068", NULL, "DL8_DL11 Mux"},
	1218	{"I069", NULL, "DL8_DL11 Mux"},
	1219
	1220	{"I070", NULL, "DL2"},
	1221	{"I071", NULL, "DL2"},
	1222
	1223	{"UL9", NULL, "O002"},
	1224	{"UL9", NULL, "O003"},
	1225	{"UL9", NULL, "O004"},
	1226	{"UL9", NULL, "O005"},
	1227	{"UL9", NULL, "O006"},
	1228	{"UL9", NULL, "O007"},
	1229	{"UL9", NULL, "O008"},
	1230	{"UL9", NULL, "O009"},
	1231	{"UL9", NULL, "O010"},
	1232	{"UL9", NULL, "O011"},
	1233	{"UL9", NULL, "O012"},
	1234	{"UL9", NULL, "O013"},
	1235	{"UL9", NULL, "O014"},
	1236	{"UL9", NULL, "O015"},
	1237	{"UL9", NULL, "O016"},
	1238	{"UL9", NULL, "O017"},
	1239	{"UL9", NULL, "O018"},
	1240	{"UL9", NULL, "O019"},
	1241	{"UL9", NULL, "O020"},
	1242	{"UL9", NULL, "O021"},
	1243	{"UL9", NULL, "O022"},
	1244	{"UL9", NULL, "O023"},
	1245	{"UL9", NULL, "O024"},
	1246	{"UL9", NULL, "O025"},
	1247	{"UL9", NULL, "O026"},
	1248	{"UL9", NULL, "O027"},
	1249	{"UL9", NULL, "O028"},
	1250	{"UL9", NULL, "O029"},
	1251	{"UL9", NULL, "O030"},
	1252	{"UL9", NULL, "O031"},
	1253	{"UL9", NULL, "O032"},
	1254	{"UL9", NULL, "O033"},
	1255
	1256	{"UL4", NULL, "O034"},
	1257	{"UL4", NULL, "O035"},
	1258
	1259	{"UL5", NULL, "O036"},
	1260	{"UL5", NULL, "O037"},
	1261
	1262	{"UL10", NULL, "O038"},
	1263	{"UL10", NULL, "O039"},
	1264	{"UL10", NULL, "O182"},
	1265	{"UL10", NULL, "O183"},
	1266
	1267	{"UL2", NULL, "O040"},
	1268	{"UL2", NULL, "O041"},
	1269	{"UL2", NULL, "O042"},
	1270	{"UL2", NULL, "O043"},
	1271	{"UL2", NULL, "O044"},
	1272	{"UL2", NULL, "O045"},
	1273	{"UL2", NULL, "O046"},
	1274	{"UL2", NULL, "O047"},
	1275
	1276	{"O004", "I000 Switch", "I000"},
	1277	{"O005", "I001 Switch", "I001"},
	1278
	1279	{"O006", "I000 Switch", "I000"},
	1280	{"O007", "I001 Switch", "I001"},
	1281
	1282	{"O010", "I022 Switch", "I022"},
	1283	{"O011", "I023 Switch", "I023"},
	1284	{"O012", "I024 Switch", "I024"},
	1285	{"O013", "I025 Switch", "I025"},
	1286	{"O014", "I026 Switch", "I026"},
	1287	{"O015", "I027 Switch", "I027"},
	1288	{"O016", "I028 Switch", "I028"},
	1289	{"O017", "I029 Switch", "I029"},
	1290
	1291	{"O010", "I046 Switch", "I046"},
	1292	{"O011", "I047 Switch", "I047"},
	1293	{"O012", "I048 Switch", "I048"},
	1294	{"O013", "I049 Switch", "I049"},
	1295	{"O014", "I050 Switch", "I050"},
	1296	{"O015", "I051 Switch", "I051"},
	1297	{"O016", "I052 Switch", "I052"},
	1298	{"O017", "I053 Switch", "I053"},
	1299	{"O002", "I022 Switch", "I022"},
	1300	{"O003", "I023 Switch", "I023"},
	1301	{"O004", "I024 Switch", "I024"},
	1302	{"O005", "I025 Switch", "I025"},
	1303	{"O006", "I026 Switch", "I026"},
	1304	{"O007", "I027 Switch", "I027"},
	1305	{"O008", "I028 Switch", "I028"},
	1306	{"O009", "I029 Switch", "I029"},
	1307	{"O010", "I030 Switch", "I030"},
	1308	{"O011", "I031 Switch", "I031"},
	1309	{"O012", "I032 Switch", "I032"},
	1310	{"O013", "I033 Switch", "I033"},
	1311	{"O014", "I034 Switch", "I034"},
	1312	{"O015", "I035 Switch", "I035"},
	1313	{"O016", "I036 Switch", "I036"},
	1314	{"O017", "I037 Switch", "I037"},
	1315	{"O018", "I038 Switch", "I038"},
	1316	{"O019", "I039 Switch", "I039"},
	1317	{"O020", "I040 Switch", "I040"},
	1318	{"O021", "I041 Switch", "I041"},
	1319	{"O022", "I042 Switch", "I042"},
	1320	{"O023", "I043 Switch", "I043"},
	1321	{"O024", "I044 Switch", "I044"},
	1322	{"O025", "I045 Switch", "I045"},
	1323	{"O026", "I046 Switch", "I046"},
	1324	{"O027", "I047 Switch", "I047"},
	1325	{"O028", "I048 Switch", "I048"},
	1326	{"O029", "I049 Switch", "I049"},
	1327	{"O030", "I050 Switch", "I050"},
	1328	{"O031", "I051 Switch", "I051"},
	1329	{"O032", "I052 Switch", "I052"},
	1330	{"O033", "I053 Switch", "I053"},
	1331
	1332	{"O002", "I000 Switch", "I000"},
	1333	{"O003", "I001 Switch", "I001"},
	1334	{"O002", "I020 Switch", "I020"},
	1335	{"O003", "I021 Switch", "I021"},
	1336	{"O002", "I070 Switch", "I070"},
	1337	{"O003", "I071 Switch", "I071"},
	1338
	1339	{"O034", "I000 Switch", "I000"},
	1340	{"O035", "I001 Switch", "I001"},
	1341	{"O034", "I002 Switch", "I002"},
	1342	{"O035", "I003 Switch", "I003"},
	1343	{"O034", "I012 Switch", "I012"},
	1344	{"O035", "I013 Switch", "I013"},
	1345	{"O034", "I020 Switch", "I020"},
	1346	{"O035", "I021 Switch", "I021"},
	1347	{"O034", "I070 Switch", "I070"},
	1348	{"O035", "I071 Switch", "I071"},
	1349	{"O034", "I072 Switch", "I072"},
	1350	{"O035", "I073 Switch", "I073"},
	1351
	1352	{"O036", "I000 Switch", "I000"},
	1353	{"O037", "I001 Switch", "I001"},
	1354	{"O036", "I012 Switch", "I012"},
	1355	{"O037", "I013 Switch", "I013"},
	1356	{"O036", "I020 Switch", "I020"},
	1357	{"O037", "I021 Switch", "I021"},
	1358	{"O036", "I070 Switch", "I070"},
	1359	{"O037", "I071 Switch", "I071"},
	1360	{"O036", "I168 Switch", "I168"},
	1361	{"O037", "I169 Switch", "I169"},
	1362
	1363	{"O038", "I022 Switch", "I022"},
	1364	{"O039", "I023 Switch", "I023"},
	1365	{"O182", "I024 Switch", "I024"},
	1366	{"O183", "I025 Switch", "I025"},
	1367
	1368	{"O040", "I022 Switch", "I022"},
	1369	{"O041", "I023 Switch", "I023"},
	1370	{"O042", "I024 Switch", "I024"},
	1371	{"O043", "I025 Switch", "I025"},
	1372	{"O044", "I026 Switch", "I026"},
	1373	{"O045", "I027 Switch", "I027"},
	1374	{"O046", "I028 Switch", "I028"},
	1375	{"O047", "I029 Switch", "I029"},
	1376
	1377	{"O040", "I002 Switch", "I002"},
	1378	{"O041", "I003 Switch", "I003"},
	1379	{"O002", "I012 Switch", "I012"},
	1380	{"O003", "I013 Switch", "I013"},
	1381	{"O004", "I014 Switch", "I014"},
	1382	{"O005", "I015 Switch", "I015"},
	1383	{"O006", "I016 Switch", "I016"},
	1384	{"O007", "I017 Switch", "I017"},
	1385	{"O008", "I018 Switch", "I018"},
	1386	{"O009", "I019 Switch", "I019"},
	1387
	1388	{"O040", "I012 Switch", "I012"},
	1389	{"O041", "I013 Switch", "I013"},
	1390	{"O042", "I014 Switch", "I014"},
	1391	{"O043", "I015 Switch", "I015"},
	1392	{"O044", "I016 Switch", "I016"},
	1393	{"O045", "I017 Switch", "I017"},
	1394	{"O046", "I018 Switch", "I018"},
	1395	{"O047", "I019 Switch", "I019"},
	1396
	1397	{"O002", "I072 Switch", "I072"},
	1398	{"O003", "I073 Switch", "I073"},
	1399	{"O004", "I074 Switch", "I074"},
	1400	{"O005", "I075 Switch", "I075"},
	1401	{"O006", "I076 Switch", "I076"},
	1402	{"O007", "I077 Switch", "I077"},
	1403	{"O008", "I078 Switch", "I078"},
	1404	{"O009", "I079 Switch", "I079"},
	1405
	1406	{"O010", "I072 Switch", "I072"},
	1407	{"O011", "I073 Switch", "I073"},
	1408	{"O012", "I074 Switch", "I074"},
	1409	{"O013", "I075 Switch", "I075"},
	1410	{"O014", "I076 Switch", "I076"},
	1411	{"O015", "I077 Switch", "I077"},
	1412	{"O016", "I078 Switch", "I078"},
	1413	{"O017", "I079 Switch", "I079"},
	1414	{"O018", "I080 Switch", "I080"},
	1415	{"O019", "I081 Switch", "I081"},
	1416	{"O020", "I082 Switch", "I082"},
	1417	{"O021", "I083 Switch", "I083"},
	1418	{"O022", "I084 Switch", "I084"},
	1419	{"O023", "I085 Switch", "I085"},
	1420	{"O024", "I086 Switch", "I086"},
	1421	{"O025", "I087 Switch", "I087"},
	1422	{"O026", "I088 Switch", "I088"},
	1423	{"O027", "I089 Switch", "I089"},
	1424	{"O028", "I090 Switch", "I090"},
	1425	{"O029", "I091 Switch", "I091"},
	1426	{"O030", "I092 Switch", "I092"},
	1427	{"O031", "I093 Switch", "I093"},
	1428	{"O032", "I094 Switch", "I094"},
	1429	{"O033", "I095 Switch", "I095"},
	1430
	1431	{"O002", "I168 Switch", "I168"},
	1432	{"O003", "I169 Switch", "I169"},
	1433	{"O004", "I170 Switch", "I170"},
	1434	{"O005", "I171 Switch", "I171"},
	1435
	1436	{"O034", "I168 Switch", "I168"},
	1437	{"O035", "I168 Switch", "I168"},
	1438	{"O035", "I169 Switch", "I169"},
	1439
	1440	{"O034", "I170 Switch", "I170"},
	1441	{"O035", "I170 Switch", "I170"},
	1442	{"O035", "I171 Switch", "I171"},
	1443
	1444	{"O040", "I168 Switch", "I168"},
	1445	{"O041", "I169 Switch", "I169"},
	1446	{"O042", "I170 Switch", "I170"},
	1447	{"O043", "I171 Switch", "I171"},
	1448	};
	1449
	1450	static const char * const mt8195_afe_1x_en_sel_text[] = {
	1451	"a1sys_a2sys", "a3sys", "a4sys",
	1452	};
	1453
	1454	static const unsigned int mt8195_afe_1x_en_sel_values[] = {
	1455	0, 1, 2,
	1456	};
	1457
	1458	static int mt8195_memif_1x_en_sel_put(struct snd_kcontrol *kcontrol,
	1459	struct snd_ctl_elem_value *ucontrol)
	1460	{
	1461	struct snd_soc_component *component =
	1462	snd_soc_kcontrol_component(kcontrol);
	1463	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
	1464	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	1465	struct mtk_dai_memif_priv *memif_priv;
	1466	unsigned int dai_id = kcontrol->id.device;
	1467	long val = ucontrol->value.integer.value[0];
	1468	int ret = 0;
	1469
	1470	memif_priv = afe_priv->dai_priv[dai_id];
	1471
	1472	if (val == memif_priv->asys_timing_sel)
	1473	return 0;
	1474
	1475	ret = snd_soc_put_enum_double(kcontrol, ucontrol);
	1476
	1477	memif_priv->asys_timing_sel = val;
	1478
	1479	return ret;
	1480	}
	1481
	1482	static int mt8195_asys_irq_1x_en_sel_put(struct snd_kcontrol *kcontrol,
	1483	struct snd_ctl_elem_value *ucontrol)
	1484	{
	1485	struct snd_soc_component *component =
	1486	snd_soc_kcontrol_component(kcontrol);
	1487	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
	1488	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	1489	unsigned int id = kcontrol->id.device;
	1490	long val = ucontrol->value.integer.value[0];
	1491	int ret = 0;
	1492
	1493	if (val == afe_priv->irq_priv[id].asys_timing_sel)
	1494	return 0;
	1495
	1496	ret = snd_soc_put_enum_double(kcontrol, ucontrol);
	1497
	1498	afe_priv->irq_priv[id].asys_timing_sel = val;
	1499
	1500	return ret;
	1501	}
	1502
	1503	static SOC_VALUE_ENUM_SINGLE_DECL(dl2_1x_en_sel_enum,
	1504	A3_A4_TIMING_SEL1, 18, 0x3,
	1505	mt8195_afe_1x_en_sel_text,
	1506	mt8195_afe_1x_en_sel_values);
	1507	static SOC_VALUE_ENUM_SINGLE_DECL(dl3_1x_en_sel_enum,
	1508	A3_A4_TIMING_SEL1, 20, 0x3,
	1509	mt8195_afe_1x_en_sel_text,
	1510	mt8195_afe_1x_en_sel_values);
	1511	static SOC_VALUE_ENUM_SINGLE_DECL(dl6_1x_en_sel_enum,
	1512	A3_A4_TIMING_SEL1, 22, 0x3,
	1513	mt8195_afe_1x_en_sel_text,
	1514	mt8195_afe_1x_en_sel_values);
	1515	static SOC_VALUE_ENUM_SINGLE_DECL(dl7_1x_en_sel_enum,
	1516	A3_A4_TIMING_SEL1, 24, 0x3,
	1517	mt8195_afe_1x_en_sel_text,
	1518	mt8195_afe_1x_en_sel_values);
	1519	static SOC_VALUE_ENUM_SINGLE_DECL(dl8_1x_en_sel_enum,
	1520	A3_A4_TIMING_SEL1, 26, 0x3,
	1521	mt8195_afe_1x_en_sel_text,
	1522	mt8195_afe_1x_en_sel_values);
	1523	static SOC_VALUE_ENUM_SINGLE_DECL(dl10_1x_en_sel_enum,
	1524	A3_A4_TIMING_SEL1, 28, 0x3,
	1525	mt8195_afe_1x_en_sel_text,
	1526	mt8195_afe_1x_en_sel_values);
	1527	static SOC_VALUE_ENUM_SINGLE_DECL(dl11_1x_en_sel_enum,
	1528	A3_A4_TIMING_SEL1, 30, 0x3,
	1529	mt8195_afe_1x_en_sel_text,
	1530	mt8195_afe_1x_en_sel_values);
	1531	static SOC_VALUE_ENUM_SINGLE_DECL(ul1_1x_en_sel_enum,
	1532	A3_A4_TIMING_SEL1, 0, 0x3,
	1533	mt8195_afe_1x_en_sel_text,
	1534	mt8195_afe_1x_en_sel_values);
	1535	static SOC_VALUE_ENUM_SINGLE_DECL(ul2_1x_en_sel_enum,
	1536	A3_A4_TIMING_SEL1, 2, 0x3,
	1537	mt8195_afe_1x_en_sel_text,
	1538	mt8195_afe_1x_en_sel_values);
	1539	static SOC_VALUE_ENUM_SINGLE_DECL(ul3_1x_en_sel_enum,
	1540	A3_A4_TIMING_SEL1, 4, 0x3,
	1541	mt8195_afe_1x_en_sel_text,
	1542	mt8195_afe_1x_en_sel_values);
	1543	static SOC_VALUE_ENUM_SINGLE_DECL(ul4_1x_en_sel_enum,
	1544	A3_A4_TIMING_SEL1, 6, 0x3,
	1545	mt8195_afe_1x_en_sel_text,
	1546	mt8195_afe_1x_en_sel_values);
	1547	static SOC_VALUE_ENUM_SINGLE_DECL(ul5_1x_en_sel_enum,
	1548	A3_A4_TIMING_SEL1, 8, 0x3,
	1549	mt8195_afe_1x_en_sel_text,
	1550	mt8195_afe_1x_en_sel_values);
	1551	static SOC_VALUE_ENUM_SINGLE_DECL(ul6_1x_en_sel_enum,
	1552	A3_A4_TIMING_SEL1, 10, 0x3,
	1553	mt8195_afe_1x_en_sel_text,
	1554	mt8195_afe_1x_en_sel_values);
	1555	static SOC_VALUE_ENUM_SINGLE_DECL(ul8_1x_en_sel_enum,
	1556	A3_A4_TIMING_SEL1, 12, 0x3,
	1557	mt8195_afe_1x_en_sel_text,
	1558	mt8195_afe_1x_en_sel_values);
	1559	static SOC_VALUE_ENUM_SINGLE_DECL(ul9_1x_en_sel_enum,
	1560	A3_A4_TIMING_SEL1, 14, 0x3,
	1561	mt8195_afe_1x_en_sel_text,
	1562	mt8195_afe_1x_en_sel_values);
	1563	static SOC_VALUE_ENUM_SINGLE_DECL(ul10_1x_en_sel_enum,
	1564	A3_A4_TIMING_SEL1, 16, 0x3,
	1565	mt8195_afe_1x_en_sel_text,
	1566	mt8195_afe_1x_en_sel_values);
	1567
	1568	static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq1_1x_en_sel_enum,
	1569	A3_A4_TIMING_SEL6, 0, 0x3,
	1570	mt8195_afe_1x_en_sel_text,
	1571	mt8195_afe_1x_en_sel_values);
	1572	static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq2_1x_en_sel_enum,
	1573	A3_A4_TIMING_SEL6, 2, 0x3,
	1574	mt8195_afe_1x_en_sel_text,
	1575	mt8195_afe_1x_en_sel_values);
	1576	static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq3_1x_en_sel_enum,
	1577	A3_A4_TIMING_SEL6, 4, 0x3,
	1578	mt8195_afe_1x_en_sel_text,
	1579	mt8195_afe_1x_en_sel_values);
	1580	static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq4_1x_en_sel_enum,
	1581	A3_A4_TIMING_SEL6, 6, 0x3,
	1582	mt8195_afe_1x_en_sel_text,
	1583	mt8195_afe_1x_en_sel_values);
	1584	static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq5_1x_en_sel_enum,
	1585	A3_A4_TIMING_SEL6, 8, 0x3,
	1586	mt8195_afe_1x_en_sel_text,
	1587	mt8195_afe_1x_en_sel_values);
	1588	static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq6_1x_en_sel_enum,
	1589	A3_A4_TIMING_SEL6, 10, 0x3,
	1590	mt8195_afe_1x_en_sel_text,
	1591	mt8195_afe_1x_en_sel_values);
	1592	static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq7_1x_en_sel_enum,
	1593	A3_A4_TIMING_SEL6, 12, 0x3,
	1594	mt8195_afe_1x_en_sel_text,
	1595	mt8195_afe_1x_en_sel_values);
	1596	static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq8_1x_en_sel_enum,
	1597	A3_A4_TIMING_SEL6, 14, 0x3,
	1598	mt8195_afe_1x_en_sel_text,
	1599	mt8195_afe_1x_en_sel_values);
	1600	static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq9_1x_en_sel_enum,
	1601	A3_A4_TIMING_SEL6, 16, 0x3,
	1602	mt8195_afe_1x_en_sel_text,
	1603	mt8195_afe_1x_en_sel_values);
	1604	static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq10_1x_en_sel_enum,
	1605	A3_A4_TIMING_SEL6, 18, 0x3,
	1606	mt8195_afe_1x_en_sel_text,
	1607	mt8195_afe_1x_en_sel_values);
	1608	static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq11_1x_en_sel_enum,
	1609	A3_A4_TIMING_SEL6, 20, 0x3,
	1610	mt8195_afe_1x_en_sel_text,
	1611	mt8195_afe_1x_en_sel_values);
	1612	static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq12_1x_en_sel_enum,
	1613	A3_A4_TIMING_SEL6, 22, 0x3,
	1614	mt8195_afe_1x_en_sel_text,
	1615	mt8195_afe_1x_en_sel_values);
	1616	static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq13_1x_en_sel_enum,
	1617	A3_A4_TIMING_SEL6, 24, 0x3,
	1618	mt8195_afe_1x_en_sel_text,
	1619	mt8195_afe_1x_en_sel_values);
	1620	static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq14_1x_en_sel_enum,
	1621	A3_A4_TIMING_SEL6, 26, 0x3,
	1622	mt8195_afe_1x_en_sel_text,
	1623	mt8195_afe_1x_en_sel_values);
	1624	static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq15_1x_en_sel_enum,
	1625	A3_A4_TIMING_SEL6, 28, 0x3,
	1626	mt8195_afe_1x_en_sel_text,
	1627	mt8195_afe_1x_en_sel_values);
	1628	static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq16_1x_en_sel_enum,
	1629	A3_A4_TIMING_SEL6, 30, 0x3,
	1630	mt8195_afe_1x_en_sel_text,
	1631	mt8195_afe_1x_en_sel_values);
	1632
	1633	static const struct snd_kcontrol_new mt8195_memif_controls[] = {
	1634	MT8195_SOC_ENUM_EXT("dl2_1x_en_sel",
	1635	dl2_1x_en_sel_enum,
	1636	snd_soc_get_enum_double,
	1637	mt8195_memif_1x_en_sel_put,
	1638	MT8195_AFE_MEMIF_DL2),
	1639	MT8195_SOC_ENUM_EXT("dl3_1x_en_sel",
	1640	dl3_1x_en_sel_enum,
	1641	snd_soc_get_enum_double,
	1642	mt8195_memif_1x_en_sel_put,
	1643	MT8195_AFE_MEMIF_DL3),
	1644	MT8195_SOC_ENUM_EXT("dl6_1x_en_sel",
	1645	dl6_1x_en_sel_enum,
	1646	snd_soc_get_enum_double,
	1647	mt8195_memif_1x_en_sel_put,
	1648	MT8195_AFE_MEMIF_DL6),
	1649	MT8195_SOC_ENUM_EXT("dl7_1x_en_sel",
	1650	dl7_1x_en_sel_enum,
	1651	snd_soc_get_enum_double,
	1652	mt8195_memif_1x_en_sel_put,
	1653	MT8195_AFE_MEMIF_DL7),
	1654	MT8195_SOC_ENUM_EXT("dl8_1x_en_sel",
	1655	dl8_1x_en_sel_enum,
	1656	snd_soc_get_enum_double,
	1657	mt8195_memif_1x_en_sel_put,
	1658	MT8195_AFE_MEMIF_DL8),
	1659	MT8195_SOC_ENUM_EXT("dl10_1x_en_sel",
	1660	dl10_1x_en_sel_enum,
	1661	snd_soc_get_enum_double,
	1662	mt8195_memif_1x_en_sel_put,
	1663	MT8195_AFE_MEMIF_DL10),
	1664	MT8195_SOC_ENUM_EXT("dl11_1x_en_sel",
	1665	dl11_1x_en_sel_enum,
	1666	snd_soc_get_enum_double,
	1667	mt8195_memif_1x_en_sel_put,
	1668	MT8195_AFE_MEMIF_DL11),
	1669	MT8195_SOC_ENUM_EXT("ul1_1x_en_sel",
	1670	ul1_1x_en_sel_enum,
	1671	snd_soc_get_enum_double,
	1672	mt8195_memif_1x_en_sel_put,
	1673	MT8195_AFE_MEMIF_UL1),
	1674	MT8195_SOC_ENUM_EXT("ul2_1x_en_sel",
	1675	ul2_1x_en_sel_enum,
	1676	snd_soc_get_enum_double,
	1677	mt8195_memif_1x_en_sel_put,
	1678	MT8195_AFE_MEMIF_UL2),
	1679	MT8195_SOC_ENUM_EXT("ul3_1x_en_sel",
	1680	ul3_1x_en_sel_enum,
	1681	snd_soc_get_enum_double,
	1682	mt8195_memif_1x_en_sel_put,
	1683	MT8195_AFE_MEMIF_UL3),
	1684	MT8195_SOC_ENUM_EXT("ul4_1x_en_sel",
	1685	ul4_1x_en_sel_enum,
	1686	snd_soc_get_enum_double,
	1687	mt8195_memif_1x_en_sel_put,
	1688	MT8195_AFE_MEMIF_UL4),
	1689	MT8195_SOC_ENUM_EXT("ul5_1x_en_sel",
	1690	ul5_1x_en_sel_enum,
	1691	snd_soc_get_enum_double,
	1692	mt8195_memif_1x_en_sel_put,
	1693	MT8195_AFE_MEMIF_UL5),
	1694	MT8195_SOC_ENUM_EXT("ul6_1x_en_sel",
	1695	ul6_1x_en_sel_enum,
	1696	snd_soc_get_enum_double,
	1697	mt8195_memif_1x_en_sel_put,
	1698	MT8195_AFE_MEMIF_UL6),
	1699	MT8195_SOC_ENUM_EXT("ul8_1x_en_sel",
	1700	ul8_1x_en_sel_enum,
	1701	snd_soc_get_enum_double,
	1702	mt8195_memif_1x_en_sel_put,
	1703	MT8195_AFE_MEMIF_UL8),
	1704	MT8195_SOC_ENUM_EXT("ul9_1x_en_sel",
	1705	ul9_1x_en_sel_enum,
	1706	snd_soc_get_enum_double,
	1707	mt8195_memif_1x_en_sel_put,
	1708	MT8195_AFE_MEMIF_UL9),
	1709	MT8195_SOC_ENUM_EXT("ul10_1x_en_sel",
	1710	ul10_1x_en_sel_enum,
	1711	snd_soc_get_enum_double,
	1712	mt8195_memif_1x_en_sel_put,
	1713	MT8195_AFE_MEMIF_UL10),
	1714	MT8195_SOC_ENUM_EXT("asys_irq1_1x_en_sel",
	1715	asys_irq1_1x_en_sel_enum,
	1716	snd_soc_get_enum_double,
	1717	mt8195_asys_irq_1x_en_sel_put,
	1718	MT8195_AFE_IRQ_13),
	1719	MT8195_SOC_ENUM_EXT("asys_irq2_1x_en_sel",
	1720	asys_irq2_1x_en_sel_enum,
	1721	snd_soc_get_enum_double,
	1722	mt8195_asys_irq_1x_en_sel_put,
	1723	MT8195_AFE_IRQ_14),
	1724	MT8195_SOC_ENUM_EXT("asys_irq3_1x_en_sel",
	1725	asys_irq3_1x_en_sel_enum,
	1726	snd_soc_get_enum_double,
	1727	mt8195_asys_irq_1x_en_sel_put,
	1728	MT8195_AFE_IRQ_15),
	1729	MT8195_SOC_ENUM_EXT("asys_irq4_1x_en_sel",
	1730	asys_irq4_1x_en_sel_enum,
	1731	snd_soc_get_enum_double,
	1732	mt8195_asys_irq_1x_en_sel_put,
	1733	MT8195_AFE_IRQ_16),
	1734	MT8195_SOC_ENUM_EXT("asys_irq5_1x_en_sel",
	1735	asys_irq5_1x_en_sel_enum,
	1736	snd_soc_get_enum_double,
	1737	mt8195_asys_irq_1x_en_sel_put,
	1738	MT8195_AFE_IRQ_17),
	1739	MT8195_SOC_ENUM_EXT("asys_irq6_1x_en_sel",
	1740	asys_irq6_1x_en_sel_enum,
	1741	snd_soc_get_enum_double,
	1742	mt8195_asys_irq_1x_en_sel_put,
	1743	MT8195_AFE_IRQ_18),
	1744	MT8195_SOC_ENUM_EXT("asys_irq7_1x_en_sel",
	1745	asys_irq7_1x_en_sel_enum,
	1746	snd_soc_get_enum_double,
	1747	mt8195_asys_irq_1x_en_sel_put,
	1748	MT8195_AFE_IRQ_19),
	1749	MT8195_SOC_ENUM_EXT("asys_irq8_1x_en_sel",
	1750	asys_irq8_1x_en_sel_enum,
	1751	snd_soc_get_enum_double,
	1752	mt8195_asys_irq_1x_en_sel_put,
	1753	MT8195_AFE_IRQ_20),
	1754	MT8195_SOC_ENUM_EXT("asys_irq9_1x_en_sel",
	1755	asys_irq9_1x_en_sel_enum,
	1756	snd_soc_get_enum_double,
	1757	mt8195_asys_irq_1x_en_sel_put,
	1758	MT8195_AFE_IRQ_21),
	1759	MT8195_SOC_ENUM_EXT("asys_irq10_1x_en_sel",
	1760	asys_irq10_1x_en_sel_enum,
	1761	snd_soc_get_enum_double,
	1762	mt8195_asys_irq_1x_en_sel_put,
	1763	MT8195_AFE_IRQ_22),
	1764	MT8195_SOC_ENUM_EXT("asys_irq11_1x_en_sel",
	1765	asys_irq11_1x_en_sel_enum,
	1766	snd_soc_get_enum_double,
	1767	mt8195_asys_irq_1x_en_sel_put,
	1768	MT8195_AFE_IRQ_23),
	1769	MT8195_SOC_ENUM_EXT("asys_irq12_1x_en_sel",
	1770	asys_irq12_1x_en_sel_enum,
	1771	snd_soc_get_enum_double,
	1772	mt8195_asys_irq_1x_en_sel_put,
	1773	MT8195_AFE_IRQ_24),
	1774	MT8195_SOC_ENUM_EXT("asys_irq13_1x_en_sel",
	1775	asys_irq13_1x_en_sel_enum,
	1776	snd_soc_get_enum_double,
	1777	mt8195_asys_irq_1x_en_sel_put,
	1778	MT8195_AFE_IRQ_25),
	1779	MT8195_SOC_ENUM_EXT("asys_irq14_1x_en_sel",
	1780	asys_irq14_1x_en_sel_enum,
	1781	snd_soc_get_enum_double,
	1782	mt8195_asys_irq_1x_en_sel_put,
	1783	MT8195_AFE_IRQ_26),
	1784	MT8195_SOC_ENUM_EXT("asys_irq15_1x_en_sel",
	1785	asys_irq15_1x_en_sel_enum,
	1786	snd_soc_get_enum_double,
	1787	mt8195_asys_irq_1x_en_sel_put,
	1788	MT8195_AFE_IRQ_27),
	1789	MT8195_SOC_ENUM_EXT("asys_irq16_1x_en_sel",
	1790	asys_irq16_1x_en_sel_enum,
	1791	snd_soc_get_enum_double,
	1792	mt8195_asys_irq_1x_en_sel_put,
	1793	MT8195_AFE_IRQ_28),
	1794	};
	1795
	1796	static const struct snd_soc_component_driver mt8195_afe_pcm_dai_component = {
	1797	.name = "mt8195-afe-pcm-dai",
	1798	};
	1799
	1800	static const struct mtk_base_memif_data memif_data[MT8195_AFE_MEMIF_NUM] = {
	1801	[MT8195_AFE_MEMIF_DL2] = {
	1802	.name = "DL2",
	1803	.id = MT8195_AFE_MEMIF_DL2,
	1804	.reg_ofs_base = AFE_DL2_BASE,
	1805	.reg_ofs_cur = AFE_DL2_CUR,
	1806	.reg_ofs_end = AFE_DL2_END,
	1807	.fs_reg = AFE_MEMIF_AGENT_FS_CON0,
	1808	.fs_shift = 10,
	1809	.fs_maskbit = 0x1f,
	1810	.mono_reg = -1,
	1811	.mono_shift = 0,
	1812	.int_odd_flag_reg = -1,
	1813	.int_odd_flag_shift = 0,
	1814	.enable_reg = AFE_DAC_CON0,
	1815	.enable_shift = 18,
	1816	.hd_reg = AFE_DL2_CON0,
	1817	.hd_shift = 5,
	1818	.agent_disable_reg = AUDIO_TOP_CON5,
	1819	.agent_disable_shift = 18,
	1820	.ch_num_reg = AFE_DL2_CON0,
	1821	.ch_num_shift = 0,
	1822	.ch_num_maskbit = 0x1f,
	1823	.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
	1824	.msb_shift = 18,
	1825	.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
	1826	.msb_end_shift = 18,
	1827	},
	1828	[MT8195_AFE_MEMIF_DL3] = {
	1829	.name = "DL3",
	1830	.id = MT8195_AFE_MEMIF_DL3,
	1831	.reg_ofs_base = AFE_DL3_BASE,
	1832	.reg_ofs_cur = AFE_DL3_CUR,
	1833	.reg_ofs_end = AFE_DL3_END,
	1834	.fs_reg = AFE_MEMIF_AGENT_FS_CON0,
	1835	.fs_shift = 15,
	1836	.fs_maskbit = 0x1f,
	1837	.mono_reg = -1,
	1838	.mono_shift = 0,
	1839	.int_odd_flag_reg = -1,
	1840	.int_odd_flag_shift = 0,
	1841	.enable_reg = AFE_DAC_CON0,
	1842	.enable_shift = 19,
	1843	.hd_reg = AFE_DL3_CON0,
	1844	.hd_shift = 5,
	1845	.agent_disable_reg = AUDIO_TOP_CON5,
	1846	.agent_disable_shift = 19,
	1847	.ch_num_reg = AFE_DL3_CON0,
	1848	.ch_num_shift = 0,
	1849	.ch_num_maskbit = 0x1f,
	1850	.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
	1851	.msb_shift = 19,
	1852	.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
	1853	.msb_end_shift = 19,
	1854	},
	1855	[MT8195_AFE_MEMIF_DL6] = {
	1856	.name = "DL6",
	1857	.id = MT8195_AFE_MEMIF_DL6,
	1858	.reg_ofs_base = AFE_DL6_BASE,
	1859	.reg_ofs_cur = AFE_DL6_CUR,
	1860	.reg_ofs_end = AFE_DL6_END,
	1861	.fs_reg = AFE_MEMIF_AGENT_FS_CON1,
	1862	.fs_shift = 0,
	1863	.fs_maskbit = 0x1f,
	1864	.mono_reg = -1,
	1865	.mono_shift = 0,
	1866	.int_odd_flag_reg = -1,
	1867	.int_odd_flag_shift = 0,
	1868	.enable_reg = AFE_DAC_CON0,
	1869	.enable_shift = 22,
	1870	.hd_reg = AFE_DL6_CON0,
	1871	.hd_shift = 5,
	1872	.agent_disable_reg = AUDIO_TOP_CON5,
	1873	.agent_disable_shift = 22,
	1874	.ch_num_reg = AFE_DL6_CON0,
	1875	.ch_num_shift = 0,
	1876	.ch_num_maskbit = 0x1f,
	1877	.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
	1878	.msb_shift = 22,
	1879	.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
	1880	.msb_end_shift = 22,
	1881	},
	1882	[MT8195_AFE_MEMIF_DL7] = {
	1883	.name = "DL7",
	1884	.id = MT8195_AFE_MEMIF_DL7,
	1885	.reg_ofs_base = AFE_DL7_BASE,
	1886	.reg_ofs_cur = AFE_DL7_CUR,
	1887	.reg_ofs_end = AFE_DL7_END,
	1888	.fs_reg = -1,
	1889	.fs_shift = 0,
	1890	.fs_maskbit = 0,
	1891	.mono_reg = -1,
	1892	.mono_shift = 0,
	1893	.int_odd_flag_reg = -1,
	1894	.int_odd_flag_shift = 0,
	1895	.enable_reg = AFE_DAC_CON0,
	1896	.enable_shift = 23,
	1897	.hd_reg = AFE_DL7_CON0,
	1898	.hd_shift = 5,
	1899	.agent_disable_reg = AUDIO_TOP_CON5,
	1900	.agent_disable_shift = 23,
	1901	.ch_num_reg = AFE_DL7_CON0,
	1902	.ch_num_shift = 0,
	1903	.ch_num_maskbit = 0x1f,
	1904	.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
	1905	.msb_shift = 23,
	1906	.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
	1907	.msb_end_shift = 23,
	1908	},
	1909	[MT8195_AFE_MEMIF_DL8] = {
	1910	.name = "DL8",
	1911	.id = MT8195_AFE_MEMIF_DL8,
	1912	.reg_ofs_base = AFE_DL8_BASE,
	1913	.reg_ofs_cur = AFE_DL8_CUR,
	1914	.reg_ofs_end = AFE_DL8_END,
	1915	.fs_reg = AFE_MEMIF_AGENT_FS_CON1,
	1916	.fs_shift = 10,
	1917	.fs_maskbit = 0x1f,
	1918	.mono_reg = -1,
	1919	.mono_shift = 0,
	1920	.int_odd_flag_reg = -1,
	1921	.int_odd_flag_shift = 0,
	1922	.enable_reg = AFE_DAC_CON0,
	1923	.enable_shift = 24,
	1924	.hd_reg = AFE_DL8_CON0,
	1925	.hd_shift = 6,
	1926	.agent_disable_reg = -1,
	1927	.agent_disable_shift = 0,
	1928	.ch_num_reg = AFE_DL8_CON0,
	1929	.ch_num_shift = 0,
	1930	.ch_num_maskbit = 0x3f,
	1931	.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
	1932	.msb_shift = 24,
	1933	.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
	1934	.msb_end_shift = 24,
	1935	},
	1936	[MT8195_AFE_MEMIF_DL10] = {
	1937	.name = "DL10",
	1938	.id = MT8195_AFE_MEMIF_DL10,
	1939	.reg_ofs_base = AFE_DL10_BASE,
	1940	.reg_ofs_cur = AFE_DL10_CUR,
	1941	.reg_ofs_end = AFE_DL10_END,
	1942	.fs_reg = AFE_MEMIF_AGENT_FS_CON1,
	1943	.fs_shift = 20,
	1944	.fs_maskbit = 0x1f,
	1945	.mono_reg = -1,
	1946	.mono_shift = 0,
	1947	.int_odd_flag_reg = -1,
	1948	.int_odd_flag_shift = 0,
	1949	.enable_reg = AFE_DAC_CON0,
	1950	.enable_shift = 26,
	1951	.hd_reg = AFE_DL10_CON0,
	1952	.hd_shift = 5,
	1953	.agent_disable_reg = -1,
	1954	.agent_disable_shift = 0,
	1955	.ch_num_reg = AFE_DL10_CON0,
	1956	.ch_num_shift = 0,
	1957	.ch_num_maskbit = 0x1f,
	1958	.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
	1959	.msb_shift = 26,
	1960	.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
	1961	.msb_end_shift = 26,
	1962	},
	1963	[MT8195_AFE_MEMIF_DL11] = {
	1964	.name = "DL11",
	1965	.id = MT8195_AFE_MEMIF_DL11,
	1966	.reg_ofs_base = AFE_DL11_BASE,
	1967	.reg_ofs_cur = AFE_DL11_CUR,
	1968	.reg_ofs_end = AFE_DL11_END,
	1969	.fs_reg = AFE_MEMIF_AGENT_FS_CON1,
	1970	.fs_shift = 25,
	1971	.fs_maskbit = 0x1f,
	1972	.mono_reg = -1,
	1973	.mono_shift = 0,
	1974	.int_odd_flag_reg = -1,
	1975	.int_odd_flag_shift = 0,
	1976	.enable_reg = AFE_DAC_CON0,
	1977	.enable_shift = 27,
	1978	.hd_reg = AFE_DL11_CON0,
	1979	.hd_shift = 7,
	1980	.agent_disable_reg = AUDIO_TOP_CON5,
	1981	.agent_disable_shift = 27,
	1982	.ch_num_reg = AFE_DL11_CON0,
	1983	.ch_num_shift = 0,
	1984	.ch_num_maskbit = 0x7f,
	1985	.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
	1986	.msb_shift = 27,
	1987	.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
	1988	.msb_end_shift = 27,
	1989	},
	1990	[MT8195_AFE_MEMIF_UL1] = {
	1991	.name = "UL1",
	1992	.id = MT8195_AFE_MEMIF_UL1,
	1993	.reg_ofs_base = AFE_UL1_BASE,
	1994	.reg_ofs_cur = AFE_UL1_CUR,
	1995	.reg_ofs_end = AFE_UL1_END,
	1996	.fs_reg = -1,
	1997	.fs_shift = 0,
	1998	.fs_maskbit = 0,
	1999	.mono_reg = AFE_UL1_CON0,
	2000	.mono_shift = 1,
	2001	.int_odd_flag_reg = AFE_UL1_CON0,
	2002	.int_odd_flag_shift = 0,
	2003	.enable_reg = AFE_DAC_CON0,
	2004	.enable_shift = 1,
	2005	.hd_reg = AFE_UL1_CON0,
	2006	.hd_shift = 5,
	2007	.agent_disable_reg = AUDIO_TOP_CON5,
	2008	.agent_disable_shift = 0,
	2009	.ch_num_reg = -1,
	2010	.ch_num_shift = 0,
	2011	.ch_num_maskbit = 0,
	2012	.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
	2013	.msb_shift = 0,
	2014	.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
	2015	.msb_end_shift = 0,
	2016	},
	2017	[MT8195_AFE_MEMIF_UL2] = {
	2018	.name = "UL2",
	2019	.id = MT8195_AFE_MEMIF_UL2,
	2020	.reg_ofs_base = AFE_UL2_BASE,
	2021	.reg_ofs_cur = AFE_UL2_CUR,
	2022	.reg_ofs_end = AFE_UL2_END,
	2023	.fs_reg = AFE_MEMIF_AGENT_FS_CON2,
	2024	.fs_shift = 5,
	2025	.fs_maskbit = 0x1f,
	2026	.mono_reg = AFE_UL2_CON0,
	2027	.mono_shift = 1,
	2028	.int_odd_flag_reg = AFE_UL2_CON0,
	2029	.int_odd_flag_shift = 0,
	2030	.enable_reg = AFE_DAC_CON0,
	2031	.enable_shift = 2,
	2032	.hd_reg = AFE_UL2_CON0,
	2033	.hd_shift = 5,
	2034	.agent_disable_reg = AUDIO_TOP_CON5,
	2035	.agent_disable_shift = 1,
	2036	.ch_num_reg = -1,
	2037	.ch_num_shift = 0,
	2038	.ch_num_maskbit = 0,
	2039	.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
	2040	.msb_shift = 1,
	2041	.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
	2042	.msb_end_shift = 1,
	2043	},
	2044	[MT8195_AFE_MEMIF_UL3] = {
	2045	.name = "UL3",
	2046	.id = MT8195_AFE_MEMIF_UL3,
	2047	.reg_ofs_base = AFE_UL3_BASE,
	2048	.reg_ofs_cur = AFE_UL3_CUR,
	2049	.reg_ofs_end = AFE_UL3_END,
	2050	.fs_reg = AFE_MEMIF_AGENT_FS_CON2,
	2051	.fs_shift = 10,
	2052	.fs_maskbit = 0x1f,
	2053	.mono_reg = AFE_UL3_CON0,
	2054	.mono_shift = 1,
	2055	.int_odd_flag_reg = AFE_UL3_CON0,
	2056	.int_odd_flag_shift = 0,
	2057	.enable_reg = AFE_DAC_CON0,
	2058	.enable_shift = 3,
	2059	.hd_reg = AFE_UL3_CON0,
	2060	.hd_shift = 5,
	2061	.agent_disable_reg = AUDIO_TOP_CON5,
	2062	.agent_disable_shift = 2,
	2063	.ch_num_reg = -1,
	2064	.ch_num_shift = 0,
	2065	.ch_num_maskbit = 0,
	2066	.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
	2067	.msb_shift = 2,
	2068	.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
	2069	.msb_end_shift = 2,
	2070	},
	2071	[MT8195_AFE_MEMIF_UL4] = {
	2072	.name = "UL4",
	2073	.id = MT8195_AFE_MEMIF_UL4,
	2074	.reg_ofs_base = AFE_UL4_BASE,
	2075	.reg_ofs_cur = AFE_UL4_CUR,
	2076	.reg_ofs_end = AFE_UL4_END,
	2077	.fs_reg = AFE_MEMIF_AGENT_FS_CON2,
	2078	.fs_shift = 15,
	2079	.fs_maskbit = 0x1f,
	2080	.mono_reg = AFE_UL4_CON0,
	2081	.mono_shift = 1,
	2082	.int_odd_flag_reg = AFE_UL4_CON0,
	2083	.int_odd_flag_shift = 0,
	2084	.enable_reg = AFE_DAC_CON0,
	2085	.enable_shift = 4,
	2086	.hd_reg = AFE_UL4_CON0,
	2087	.hd_shift = 5,
	2088	.agent_disable_reg = AUDIO_TOP_CON5,
	2089	.agent_disable_shift = 3,
	2090	.ch_num_reg = -1,
	2091	.ch_num_shift = 0,
	2092	.ch_num_maskbit = 0,
	2093	.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
	2094	.msb_shift = 3,
	2095	.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
	2096	.msb_end_shift = 3,
	2097	},
	2098	[MT8195_AFE_MEMIF_UL5] = {
	2099	.name = "UL5",
	2100	.id = MT8195_AFE_MEMIF_UL5,
	2101	.reg_ofs_base = AFE_UL5_BASE,
	2102	.reg_ofs_cur = AFE_UL5_CUR,
	2103	.reg_ofs_end = AFE_UL5_END,
	2104	.fs_reg = AFE_MEMIF_AGENT_FS_CON2,
	2105	.fs_shift = 20,
	2106	.fs_maskbit = 0x1f,
	2107	.mono_reg = AFE_UL5_CON0,
	2108	.mono_shift = 1,
	2109	.int_odd_flag_reg = AFE_UL5_CON0,
	2110	.int_odd_flag_shift = 0,
	2111	.enable_reg = AFE_DAC_CON0,
	2112	.enable_shift = 5,
	2113	.hd_reg = AFE_UL5_CON0,
	2114	.hd_shift = 5,
	2115	.agent_disable_reg = AUDIO_TOP_CON5,
	2116	.agent_disable_shift = 4,
	2117	.ch_num_reg = -1,
	2118	.ch_num_shift = 0,
	2119	.ch_num_maskbit = 0,
	2120	.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
	2121	.msb_shift = 4,
	2122	.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
	2123	.msb_end_shift = 4,
	2124	},
	2125	[MT8195_AFE_MEMIF_UL6] = {
	2126	.name = "UL6",
	2127	.id = MT8195_AFE_MEMIF_UL6,
	2128	.reg_ofs_base = AFE_UL6_BASE,
	2129	.reg_ofs_cur = AFE_UL6_CUR,
	2130	.reg_ofs_end = AFE_UL6_END,
	2131	.fs_reg = -1,
	2132	.fs_shift = 0,
	2133	.fs_maskbit = 0,
	2134	.mono_reg = AFE_UL6_CON0,
	2135	.mono_shift = 1,
	2136	.int_odd_flag_reg = AFE_UL6_CON0,
	2137	.int_odd_flag_shift = 0,
	2138	.enable_reg = AFE_DAC_CON0,
	2139	.enable_shift = 6,
	2140	.hd_reg = AFE_UL6_CON0,
	2141	.hd_shift = 5,
	2142	.agent_disable_reg = AUDIO_TOP_CON5,
	2143	.agent_disable_shift = 5,
	2144	.ch_num_reg = -1,
	2145	.ch_num_shift = 0,
	2146	.ch_num_maskbit = 0,
	2147	.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
	2148	.msb_shift = 5,
	2149	.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
	2150	.msb_end_shift = 5,
	2151	},
	2152	[MT8195_AFE_MEMIF_UL8] = {
	2153	.name = "UL8",
	2154	.id = MT8195_AFE_MEMIF_UL8,
	2155	.reg_ofs_base = AFE_UL8_BASE,
	2156	.reg_ofs_cur = AFE_UL8_CUR,
	2157	.reg_ofs_end = AFE_UL8_END,
	2158	.fs_reg = AFE_MEMIF_AGENT_FS_CON3,
	2159	.fs_shift = 5,
	2160	.fs_maskbit = 0x1f,
	2161	.mono_reg = AFE_UL8_CON0,
	2162	.mono_shift = 1,
	2163	.int_odd_flag_reg = AFE_UL8_CON0,
	2164	.int_odd_flag_shift = 0,
	2165	.enable_reg = AFE_DAC_CON0,
	2166	.enable_shift = 8,
	2167	.hd_reg = AFE_UL8_CON0,
	2168	.hd_shift = 5,
	2169	.agent_disable_reg = AUDIO_TOP_CON5,
	2170	.agent_disable_shift = 7,
	2171	.ch_num_reg = -1,
	2172	.ch_num_shift = 0,
	2173	.ch_num_maskbit = 0,
	2174	.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
	2175	.msb_shift = 7,
	2176	.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
	2177	.msb_end_shift = 7,
	2178	},
	2179	[MT8195_AFE_MEMIF_UL9] = {
	2180	.name = "UL9",
	2181	.id = MT8195_AFE_MEMIF_UL9,
	2182	.reg_ofs_base = AFE_UL9_BASE,
	2183	.reg_ofs_cur = AFE_UL9_CUR,
	2184	.reg_ofs_end = AFE_UL9_END,
	2185	.fs_reg = AFE_MEMIF_AGENT_FS_CON3,
	2186	.fs_shift = 10,
	2187	.fs_maskbit = 0x1f,
	2188	.mono_reg = AFE_UL9_CON0,
	2189	.mono_shift = 1,
	2190	.int_odd_flag_reg = AFE_UL9_CON0,
	2191	.int_odd_flag_shift = 0,
	2192	.enable_reg = AFE_DAC_CON0,
	2193	.enable_shift = 9,
	2194	.hd_reg = AFE_UL9_CON0,
	2195	.hd_shift = 5,
	2196	.agent_disable_reg = AUDIO_TOP_CON5,
	2197	.agent_disable_shift = 8,
	2198	.ch_num_reg = -1,
	2199	.ch_num_shift = 0,
	2200	.ch_num_maskbit = 0,
	2201	.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
	2202	.msb_shift = 8,
	2203	.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
	2204	.msb_end_shift = 8,
	2205	},
	2206	[MT8195_AFE_MEMIF_UL10] = {
	2207	.name = "UL10",
	2208	.id = MT8195_AFE_MEMIF_UL10,
	2209	.reg_ofs_base = AFE_UL10_BASE,
	2210	.reg_ofs_cur = AFE_UL10_CUR,
	2211	.reg_ofs_end = AFE_UL10_END,
	2212	.fs_reg = AFE_MEMIF_AGENT_FS_CON3,
	2213	.fs_shift = 15,
	2214	.fs_maskbit = 0x1f,
	2215	.mono_reg = AFE_UL10_CON0,
	2216	.mono_shift = 1,
	2217	.int_odd_flag_reg = AFE_UL10_CON0,
	2218	.int_odd_flag_shift = 0,
	2219	.enable_reg = AFE_DAC_CON0,
	2220	.enable_shift = 10,
	2221	.hd_reg = AFE_UL10_CON0,
	2222	.hd_shift = 5,
	2223	.agent_disable_reg = AUDIO_TOP_CON5,
	2224	.agent_disable_shift = 9,
	2225	.ch_num_reg = -1,
	2226	.ch_num_shift = 0,
	2227	.ch_num_maskbit = 0,
	2228	.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
	2229	.msb_shift = 9,
	2230	.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
	2231	.msb_end_shift = 9,
	2232	},
	2233	};
	2234
	2235	static const struct mtk_base_irq_data irq_data[MT8195_AFE_IRQ_NUM] = {
	2236	[MT8195_AFE_IRQ_1] = {
	2237	.id = MT8195_AFE_IRQ_1,
	2238	.irq_cnt_reg = -1,
	2239	.irq_cnt_shift = 0,
	2240	.irq_cnt_maskbit = 0,
	2241	.irq_fs_reg = -1,
	2242	.irq_fs_shift = 0,
	2243	.irq_fs_maskbit = 0,
	2244	.irq_en_reg = AFE_IRQ1_CON,
	2245	.irq_en_shift = 31,
	2246	.irq_clr_reg = AFE_IRQ_MCU_CLR,
	2247	.irq_clr_shift = 0,
	2248	.irq_status_shift = 16,
	2249	},
	2250	[MT8195_AFE_IRQ_2] = {
	2251	.id = MT8195_AFE_IRQ_2,
	2252	.irq_cnt_reg = -1,
	2253	.irq_cnt_shift = 0,
	2254	.irq_cnt_maskbit = 0,
	2255	.irq_fs_reg = -1,
	2256	.irq_fs_shift = 0,
	2257	.irq_fs_maskbit = 0,
	2258	.irq_en_reg = AFE_IRQ2_CON,
	2259	.irq_en_shift = 31,
	2260	.irq_clr_reg = AFE_IRQ_MCU_CLR,
	2261	.irq_clr_shift = 1,
	2262	.irq_status_shift = 17,
	2263	},
	2264	[MT8195_AFE_IRQ_3] = {
	2265	.id = MT8195_AFE_IRQ_3,
	2266	.irq_cnt_reg = AFE_IRQ3_CON,
	2267	.irq_cnt_shift = 0,
	2268	.irq_cnt_maskbit = 0xffffff,
	2269	.irq_fs_reg = -1,
	2270	.irq_fs_shift = 0,
	2271	.irq_fs_maskbit = 0,
	2272	.irq_en_reg = AFE_IRQ3_CON,
	2273	.irq_en_shift = 31,
	2274	.irq_clr_reg = AFE_IRQ_MCU_CLR,
	2275	.irq_clr_shift = 2,
	2276	.irq_status_shift = 18,
	2277	},
	2278	[MT8195_AFE_IRQ_8] = {
	2279	.id = MT8195_AFE_IRQ_8,
	2280	.irq_cnt_reg = -1,
	2281	.irq_cnt_shift = 0,
	2282	.irq_cnt_maskbit = 0,
	2283	.irq_fs_reg = -1,
	2284	.irq_fs_shift = 0,
	2285	.irq_fs_maskbit = 0,
	2286	.irq_en_reg = AFE_IRQ8_CON,
	2287	.irq_en_shift = 31,
	2288	.irq_clr_reg = AFE_IRQ_MCU_CLR,
	2289	.irq_clr_shift = 7,
	2290	.irq_status_shift = 23,
	2291	},
	2292	[MT8195_AFE_IRQ_9] = {
	2293	.id = MT8195_AFE_IRQ_9,
	2294	.irq_cnt_reg = AFE_IRQ9_CON,
	2295	.irq_cnt_shift = 0,
	2296	.irq_cnt_maskbit = 0xffffff,
	2297	.irq_fs_reg = -1,
	2298	.irq_fs_shift = 0,
	2299	.irq_fs_maskbit = 0,
	2300	.irq_en_reg = AFE_IRQ9_CON,
	2301	.irq_en_shift = 31,
	2302	.irq_clr_reg = AFE_IRQ_MCU_CLR,
	2303	.irq_clr_shift = 8,
	2304	.irq_status_shift = 24,
	2305	},
	2306	[MT8195_AFE_IRQ_10] = {
	2307	.id = MT8195_AFE_IRQ_10,
	2308	.irq_cnt_reg = -1,
	2309	.irq_cnt_shift = 0,
	2310	.irq_cnt_maskbit = 0,
	2311	.irq_fs_reg = -1,
	2312	.irq_fs_shift = 0,
	2313	.irq_fs_maskbit = 0,
	2314	.irq_en_reg = AFE_IRQ10_CON,
	2315	.irq_en_shift = 31,
	2316	.irq_clr_reg = AFE_IRQ_MCU_CLR,
	2317	.irq_clr_shift = 9,
	2318	.irq_status_shift = 25,
	2319	},
	2320	[MT8195_AFE_IRQ_13] = {
	2321	.id = MT8195_AFE_IRQ_13,
	2322	.irq_cnt_reg = ASYS_IRQ1_CON,
	2323	.irq_cnt_shift = 0,
	2324	.irq_cnt_maskbit = 0xffffff,
	2325	.irq_fs_reg = ASYS_IRQ1_CON,
	2326	.irq_fs_shift = 24,
	2327	.irq_fs_maskbit = 0x1ffff,
	2328	.irq_en_reg = ASYS_IRQ1_CON,
	2329	.irq_en_shift = 31,
	2330	.irq_clr_reg = ASYS_IRQ_CLR,
	2331	.irq_clr_shift = 0,
	2332	.irq_status_shift = 0,
	2333	},
	2334	[MT8195_AFE_IRQ_14] = {
	2335	.id = MT8195_AFE_IRQ_14,
	2336	.irq_cnt_reg = ASYS_IRQ2_CON,
	2337	.irq_cnt_shift = 0,
	2338	.irq_cnt_maskbit = 0xffffff,
	2339	.irq_fs_reg = ASYS_IRQ2_CON,
	2340	.irq_fs_shift = 24,
	2341	.irq_fs_maskbit = 0x1ffff,
	2342	.irq_en_reg = ASYS_IRQ2_CON,
	2343	.irq_en_shift = 31,
	2344	.irq_clr_reg = ASYS_IRQ_CLR,
	2345	.irq_clr_shift = 1,
	2346	.irq_status_shift = 1,
	2347	},
	2348	[MT8195_AFE_IRQ_15] = {
	2349	.id = MT8195_AFE_IRQ_15,
	2350	.irq_cnt_reg = ASYS_IRQ3_CON,
	2351	.irq_cnt_shift = 0,
	2352	.irq_cnt_maskbit = 0xffffff,
	2353	.irq_fs_reg = ASYS_IRQ3_CON,
	2354	.irq_fs_shift = 24,
	2355	.irq_fs_maskbit = 0x1ffff,
	2356	.irq_en_reg = ASYS_IRQ3_CON,
	2357	.irq_en_shift = 31,
	2358	.irq_clr_reg = ASYS_IRQ_CLR,
	2359	.irq_clr_shift = 2,
	2360	.irq_status_shift = 2,
	2361	},
	2362	[MT8195_AFE_IRQ_16] = {
	2363	.id = MT8195_AFE_IRQ_16,
	2364	.irq_cnt_reg = ASYS_IRQ4_CON,
	2365	.irq_cnt_shift = 0,
	2366	.irq_cnt_maskbit = 0xffffff,
	2367	.irq_fs_reg = ASYS_IRQ4_CON,
	2368	.irq_fs_shift = 24,
	2369	.irq_fs_maskbit = 0x1ffff,
	2370	.irq_en_reg = ASYS_IRQ4_CON,
	2371	.irq_en_shift = 31,
	2372	.irq_clr_reg = ASYS_IRQ_CLR,
	2373	.irq_clr_shift = 3,
	2374	.irq_status_shift = 3,
	2375	},
	2376	[MT8195_AFE_IRQ_17] = {
	2377	.id = MT8195_AFE_IRQ_17,
	2378	.irq_cnt_reg = ASYS_IRQ5_CON,
	2379	.irq_cnt_shift = 0,
	2380	.irq_cnt_maskbit = 0xffffff,
	2381	.irq_fs_reg = ASYS_IRQ5_CON,
	2382	.irq_fs_shift = 24,
	2383	.irq_fs_maskbit = 0x1ffff,
	2384	.irq_en_reg = ASYS_IRQ5_CON,
	2385	.irq_en_shift = 31,
	2386	.irq_clr_reg = ASYS_IRQ_CLR,
	2387	.irq_clr_shift = 4,
	2388	.irq_status_shift = 4,
	2389	},
	2390	[MT8195_AFE_IRQ_18] = {
	2391	.id = MT8195_AFE_IRQ_18,
	2392	.irq_cnt_reg = ASYS_IRQ6_CON,
	2393	.irq_cnt_shift = 0,
	2394	.irq_cnt_maskbit = 0xffffff,
	2395	.irq_fs_reg = ASYS_IRQ6_CON,
	2396	.irq_fs_shift = 24,
	2397	.irq_fs_maskbit = 0x1ffff,
	2398	.irq_en_reg = ASYS_IRQ6_CON,
	2399	.irq_en_shift = 31,
	2400	.irq_clr_reg = ASYS_IRQ_CLR,
	2401	.irq_clr_shift = 5,
	2402	.irq_status_shift = 5,
	2403	},
	2404	[MT8195_AFE_IRQ_19] = {
	2405	.id = MT8195_AFE_IRQ_19,
	2406	.irq_cnt_reg = ASYS_IRQ7_CON,
	2407	.irq_cnt_shift = 0,
	2408	.irq_cnt_maskbit = 0xffffff,
	2409	.irq_fs_reg = ASYS_IRQ7_CON,
	2410	.irq_fs_shift = 24,
	2411	.irq_fs_maskbit = 0x1ffff,
	2412	.irq_en_reg = ASYS_IRQ7_CON,
	2413	.irq_en_shift = 31,
	2414	.irq_clr_reg = ASYS_IRQ_CLR,
	2415	.irq_clr_shift = 6,
	2416	.irq_status_shift = 6,
	2417	},
	2418	[MT8195_AFE_IRQ_20] = {
	2419	.id = MT8195_AFE_IRQ_20,
	2420	.irq_cnt_reg = ASYS_IRQ8_CON,
	2421	.irq_cnt_shift = 0,
	2422	.irq_cnt_maskbit = 0xffffff,
	2423	.irq_fs_reg = ASYS_IRQ8_CON,
	2424	.irq_fs_shift = 24,
	2425	.irq_fs_maskbit = 0x1ffff,
	2426	.irq_en_reg = ASYS_IRQ8_CON,
	2427	.irq_en_shift = 31,
	2428	.irq_clr_reg = ASYS_IRQ_CLR,
	2429	.irq_clr_shift = 7,
	2430	.irq_status_shift = 7,
	2431	},
	2432	[MT8195_AFE_IRQ_21] = {
	2433	.id = MT8195_AFE_IRQ_21,
	2434	.irq_cnt_reg = ASYS_IRQ9_CON,
	2435	.irq_cnt_shift = 0,
	2436	.irq_cnt_maskbit = 0xffffff,
	2437	.irq_fs_reg = ASYS_IRQ9_CON,
	2438	.irq_fs_shift = 24,
	2439	.irq_fs_maskbit = 0x1ffff,
	2440	.irq_en_reg = ASYS_IRQ9_CON,
	2441	.irq_en_shift = 31,
	2442	.irq_clr_reg = ASYS_IRQ_CLR,
	2443	.irq_clr_shift = 8,
	2444	.irq_status_shift = 8,
	2445	},
	2446	[MT8195_AFE_IRQ_22] = {
	2447	.id = MT8195_AFE_IRQ_22,
	2448	.irq_cnt_reg = ASYS_IRQ10_CON,
	2449	.irq_cnt_shift = 0,
	2450	.irq_cnt_maskbit = 0xffffff,
	2451	.irq_fs_reg = ASYS_IRQ10_CON,
	2452	.irq_fs_shift = 24,
	2453	.irq_fs_maskbit = 0x1ffff,
	2454	.irq_en_reg = ASYS_IRQ10_CON,
	2455	.irq_en_shift = 31,
	2456	.irq_clr_reg = ASYS_IRQ_CLR,
	2457	.irq_clr_shift = 9,
	2458	.irq_status_shift = 9,
	2459	},
	2460	[MT8195_AFE_IRQ_23] = {
	2461	.id = MT8195_AFE_IRQ_23,
	2462	.irq_cnt_reg = ASYS_IRQ11_CON,
	2463	.irq_cnt_shift = 0,
	2464	.irq_cnt_maskbit = 0xffffff,
	2465	.irq_fs_reg = ASYS_IRQ11_CON,
	2466	.irq_fs_shift = 24,
	2467	.irq_fs_maskbit = 0x1ffff,
	2468	.irq_en_reg = ASYS_IRQ11_CON,
	2469	.irq_en_shift = 31,
	2470	.irq_clr_reg = ASYS_IRQ_CLR,
	2471	.irq_clr_shift = 10,
	2472	.irq_status_shift = 10,
	2473	},
	2474	[MT8195_AFE_IRQ_24] = {
	2475	.id = MT8195_AFE_IRQ_24,
	2476	.irq_cnt_reg = ASYS_IRQ12_CON,
	2477	.irq_cnt_shift = 0,
	2478	.irq_cnt_maskbit = 0xffffff,
	2479	.irq_fs_reg = ASYS_IRQ12_CON,
	2480	.irq_fs_shift = 24,
	2481	.irq_fs_maskbit = 0x1ffff,
	2482	.irq_en_reg = ASYS_IRQ12_CON,
	2483	.irq_en_shift = 31,
	2484	.irq_clr_reg = ASYS_IRQ_CLR,
	2485	.irq_clr_shift = 11,
	2486	.irq_status_shift = 11,
	2487	},
	2488	[MT8195_AFE_IRQ_25] = {
	2489	.id = MT8195_AFE_IRQ_25,
	2490	.irq_cnt_reg = ASYS_IRQ13_CON,
	2491	.irq_cnt_shift = 0,
	2492	.irq_cnt_maskbit = 0xffffff,
	2493	.irq_fs_reg = ASYS_IRQ13_CON,
	2494	.irq_fs_shift = 24,
	2495	.irq_fs_maskbit = 0x1ffff,
	2496	.irq_en_reg = ASYS_IRQ13_CON,
	2497	.irq_en_shift = 31,
	2498	.irq_clr_reg = ASYS_IRQ_CLR,
	2499	.irq_clr_shift = 12,
	2500	.irq_status_shift = 12,
	2501	},
	2502	[MT8195_AFE_IRQ_26] = {
	2503	.id = MT8195_AFE_IRQ_26,
	2504	.irq_cnt_reg = ASYS_IRQ14_CON,
	2505	.irq_cnt_shift = 0,
	2506	.irq_cnt_maskbit = 0xffffff,
	2507	.irq_fs_reg = ASYS_IRQ14_CON,
	2508	.irq_fs_shift = 24,
	2509	.irq_fs_maskbit = 0x1ffff,
	2510	.irq_en_reg = ASYS_IRQ14_CON,
	2511	.irq_en_shift = 31,
	2512	.irq_clr_reg = ASYS_IRQ_CLR,
	2513	.irq_clr_shift = 13,
	2514	.irq_status_shift = 13,
	2515	},
	2516	[MT8195_AFE_IRQ_27] = {
	2517	.id = MT8195_AFE_IRQ_27,
	2518	.irq_cnt_reg = ASYS_IRQ15_CON,
	2519	.irq_cnt_shift = 0,
	2520	.irq_cnt_maskbit = 0xffffff,
	2521	.irq_fs_reg = ASYS_IRQ15_CON,
	2522	.irq_fs_shift = 24,
	2523	.irq_fs_maskbit = 0x1ffff,
	2524	.irq_en_reg = ASYS_IRQ15_CON,
	2525	.irq_en_shift = 31,
	2526	.irq_clr_reg = ASYS_IRQ_CLR,
	2527	.irq_clr_shift = 14,
	2528	.irq_status_shift = 14,
	2529	},
	2530	[MT8195_AFE_IRQ_28] = {
	2531	.id = MT8195_AFE_IRQ_28,
	2532	.irq_cnt_reg = ASYS_IRQ16_CON,
	2533	.irq_cnt_shift = 0,
	2534	.irq_cnt_maskbit = 0xffffff,
	2535	.irq_fs_reg = ASYS_IRQ16_CON,
	2536	.irq_fs_shift = 24,
	2537	.irq_fs_maskbit = 0x1ffff,
	2538	.irq_en_reg = ASYS_IRQ16_CON,
	2539	.irq_en_shift = 31,
	2540	.irq_clr_reg = ASYS_IRQ_CLR,
	2541	.irq_clr_shift = 15,
	2542	.irq_status_shift = 15,
	2543	},
	2544	};
	2545
	2546	static const int mt8195_afe_memif_const_irqs[MT8195_AFE_MEMIF_NUM] = {
	2547	[MT8195_AFE_MEMIF_DL2] = MT8195_AFE_IRQ_13,
	2548	[MT8195_AFE_MEMIF_DL3] = MT8195_AFE_IRQ_14,
	2549	[MT8195_AFE_MEMIF_DL6] = MT8195_AFE_IRQ_15,
	2550	[MT8195_AFE_MEMIF_DL7] = MT8195_AFE_IRQ_1,
	2551	[MT8195_AFE_MEMIF_DL8] = MT8195_AFE_IRQ_16,
	2552	[MT8195_AFE_MEMIF_DL10] = MT8195_AFE_IRQ_17,
	2553	[MT8195_AFE_MEMIF_DL11] = MT8195_AFE_IRQ_18,
	2554	[MT8195_AFE_MEMIF_UL1] = MT8195_AFE_IRQ_3,
	2555	[MT8195_AFE_MEMIF_UL2] = MT8195_AFE_IRQ_19,
	2556	[MT8195_AFE_MEMIF_UL3] = MT8195_AFE_IRQ_20,
	2557	[MT8195_AFE_MEMIF_UL4] = MT8195_AFE_IRQ_21,
	2558	[MT8195_AFE_MEMIF_UL5] = MT8195_AFE_IRQ_22,
	2559	[MT8195_AFE_MEMIF_UL6] = MT8195_AFE_IRQ_9,
	2560	[MT8195_AFE_MEMIF_UL8] = MT8195_AFE_IRQ_23,
	2561	[MT8195_AFE_MEMIF_UL9] = MT8195_AFE_IRQ_24,
	2562	[MT8195_AFE_MEMIF_UL10] = MT8195_AFE_IRQ_25,
	2563	};
	2564
	2565	static bool mt8195_is_volatile_reg(struct device *dev, unsigned int reg)
	2566	{
	2567	/* these auto-gen reg has read-only bit, so put it as volatile */
	2568	/* volatile reg cannot be cached, so cannot be set when power off */
	2569	switch (reg) {
	2570	case AUDIO_TOP_CON0:
	2571	case AUDIO_TOP_CON1:
	2572	case AUDIO_TOP_CON3:
	2573	case AUDIO_TOP_CON4:
	2574	case AUDIO_TOP_CON5:
	2575	case AUDIO_TOP_CON6:
	2576	case ASYS_IRQ_CLR:
	2577	case ASYS_IRQ_STATUS:
	2578	case ASYS_IRQ_MON1:
	2579	case ASYS_IRQ_MON2:
	2580	case AFE_IRQ_MCU_CLR:
	2581	case AFE_IRQ_STATUS:
	2582	case AFE_IRQ3_CON_MON:
	2583	case AFE_IRQ_MCU_MON2:
	2584	case ADSP_IRQ_STATUS:
	2585	case AFE_APLL_TUNER_CFG:
	2586	case AFE_APLL_TUNER_CFG1:
	2587	case AUDIO_TOP_STA0:
	2588	case AUDIO_TOP_STA1:
	2589	case AFE_GAIN1_CUR:
	2590	case AFE_GAIN2_CUR:
	2591	case AFE_IEC_BURST_INFO:
	2592	case AFE_IEC_CHL_STAT0:
	2593	case AFE_IEC_CHL_STAT1:
	2594	case AFE_IEC_CHR_STAT0:
	2595	case AFE_IEC_CHR_STAT1:
	2596	case AFE_SPDIFIN_CHSTS1:
	2597	case AFE_SPDIFIN_CHSTS2:
	2598	case AFE_SPDIFIN_CHSTS3:
	2599	case AFE_SPDIFIN_CHSTS4:
	2600	case AFE_SPDIFIN_CHSTS5:
	2601	case AFE_SPDIFIN_CHSTS6:
	2602	case AFE_SPDIFIN_DEBUG1:
	2603	case AFE_SPDIFIN_DEBUG2:
	2604	case AFE_SPDIFIN_DEBUG3:
	2605	case AFE_SPDIFIN_DEBUG4:
	2606	case AFE_SPDIFIN_EC:
	2607	case AFE_SPDIFIN_CKLOCK_CFG:
	2608	case AFE_SPDIFIN_BR_DBG1:
	2609	case AFE_SPDIFIN_CKFBDIV:
	2610	case AFE_SPDIFIN_INT_EXT:
	2611	case AFE_SPDIFIN_INT_EXT2:
	2612	case SPDIFIN_FREQ_STATUS:
	2613	case SPDIFIN_USERCODE1:
	2614	case SPDIFIN_USERCODE2:
	2615	case SPDIFIN_USERCODE3:
	2616	case SPDIFIN_USERCODE4:
	2617	case SPDIFIN_USERCODE5:
	2618	case SPDIFIN_USERCODE6:
	2619	case SPDIFIN_USERCODE7:
	2620	case SPDIFIN_USERCODE8:
	2621	case SPDIFIN_USERCODE9:
	2622	case SPDIFIN_USERCODE10:
	2623	case SPDIFIN_USERCODE11:
	2624	case SPDIFIN_USERCODE12:
	2625	case AFE_SPDIFIN_APLL_TUNER_CFG:
	2626	case AFE_LINEIN_APLL_TUNER_MON:
	2627	case AFE_EARC_APLL_TUNER_MON:
	2628	case AFE_CM0_MON:
	2629	case AFE_CM1_MON:
	2630	case AFE_CM2_MON:
	2631	case AFE_MPHONE_MULTI_DET_MON0:
	2632	case AFE_MPHONE_MULTI_DET_MON1:
	2633	case AFE_MPHONE_MULTI_DET_MON2:
	2634	case AFE_MPHONE_MULTI2_DET_MON0:
	2635	case AFE_MPHONE_MULTI2_DET_MON1:
	2636	case AFE_MPHONE_MULTI2_DET_MON2:
	2637	case AFE_ADDA_MTKAIF_MON0:
	2638	case AFE_ADDA_MTKAIF_MON1:
	2639	case AFE_AUD_PAD_TOP:
	2640	case AFE_ADDA6_MTKAIF_MON0:
	2641	case AFE_ADDA6_MTKAIF_MON1:
	2642	case AFE_ADDA6_SRC_DEBUG_MON0:
	2643	case AFE_ADDA6_UL_SRC_MON0:
	2644	case AFE_ADDA6_UL_SRC_MON1:
	2645	case AFE_ASRC11_NEW_CON8:
	2646	case AFE_ASRC11_NEW_CON9:
	2647	case AFE_ASRC12_NEW_CON8:
	2648	case AFE_ASRC12_NEW_CON9:
	2649	case AFE_LRCK_CNT:
	2650	case AFE_DAC_MON0:
	2651	case AFE_DL2_CUR:
	2652	case AFE_DL3_CUR:
	2653	case AFE_DL6_CUR:
	2654	case AFE_DL7_CUR:
	2655	case AFE_DL8_CUR:
	2656	case AFE_DL10_CUR:
	2657	case AFE_DL11_CUR:
	2658	case AFE_UL1_CUR:
	2659	case AFE_UL2_CUR:
	2660	case AFE_UL3_CUR:
	2661	case AFE_UL4_CUR:
	2662	case AFE_UL5_CUR:
	2663	case AFE_UL6_CUR:
	2664	case AFE_UL8_CUR:
	2665	case AFE_UL9_CUR:
	2666	case AFE_UL10_CUR:
	2667	case AFE_DL8_CHK_SUM1:
	2668	case AFE_DL8_CHK_SUM2:
	2669	case AFE_DL8_CHK_SUM3:
	2670	case AFE_DL8_CHK_SUM4:
	2671	case AFE_DL8_CHK_SUM5:
	2672	case AFE_DL8_CHK_SUM6:
	2673	case AFE_DL10_CHK_SUM1:
	2674	case AFE_DL10_CHK_SUM2:
	2675	case AFE_DL10_CHK_SUM3:
	2676	case AFE_DL10_CHK_SUM4:
	2677	case AFE_DL10_CHK_SUM5:
	2678	case AFE_DL10_CHK_SUM6:
	2679	case AFE_DL11_CHK_SUM1:
	2680	case AFE_DL11_CHK_SUM2:
	2681	case AFE_DL11_CHK_SUM3:
	2682	case AFE_DL11_CHK_SUM4:
	2683	case AFE_DL11_CHK_SUM5:
	2684	case AFE_DL11_CHK_SUM6:
	2685	case AFE_UL1_CHK_SUM1:
	2686	case AFE_UL1_CHK_SUM2:
	2687	case AFE_UL2_CHK_SUM1:
	2688	case AFE_UL2_CHK_SUM2:
	2689	case AFE_UL3_CHK_SUM1:
	2690	case AFE_UL3_CHK_SUM2:
	2691	case AFE_UL4_CHK_SUM1:
	2692	case AFE_UL4_CHK_SUM2:
	2693	case AFE_UL5_CHK_SUM1:
	2694	case AFE_UL5_CHK_SUM2:
	2695	case AFE_UL6_CHK_SUM1:
	2696	case AFE_UL6_CHK_SUM2:
	2697	case AFE_UL8_CHK_SUM1:
	2698	case AFE_UL8_CHK_SUM2:
	2699	case AFE_DL2_CHK_SUM1:
	2700	case AFE_DL2_CHK_SUM2:
	2701	case AFE_DL3_CHK_SUM1:
	2702	case AFE_DL3_CHK_SUM2:
	2703	case AFE_DL6_CHK_SUM1:
	2704	case AFE_DL6_CHK_SUM2:
	2705	case AFE_DL7_CHK_SUM1:
	2706	case AFE_DL7_CHK_SUM2:
	2707	case AFE_UL9_CHK_SUM1:
	2708	case AFE_UL9_CHK_SUM2:
	2709	case AFE_BUS_MON1:
	2710	case UL1_MOD2AGT_CNT_LAT:
	2711	case UL2_MOD2AGT_CNT_LAT:
	2712	case UL3_MOD2AGT_CNT_LAT:
	2713	case UL4_MOD2AGT_CNT_LAT:
	2714	case UL5_MOD2AGT_CNT_LAT:
	2715	case UL6_MOD2AGT_CNT_LAT:
	2716	case UL8_MOD2AGT_CNT_LAT:
	2717	case UL9_MOD2AGT_CNT_LAT:
	2718	case UL10_MOD2AGT_CNT_LAT:
	2719	case AFE_MEMIF_BUF_FULL_MON:
	2720	case AFE_MEMIF_BUF_MON1:
	2721	case AFE_MEMIF_BUF_MON3:
	2722	case AFE_MEMIF_BUF_MON4:
	2723	case AFE_MEMIF_BUF_MON5:
	2724	case AFE_MEMIF_BUF_MON6:
	2725	case AFE_MEMIF_BUF_MON7:
	2726	case AFE_MEMIF_BUF_MON8:
	2727	case AFE_MEMIF_BUF_MON9:
	2728	case AFE_MEMIF_BUF_MON10:
	2729	case DL2_AGENT2MODULE_CNT:
	2730	case DL3_AGENT2MODULE_CNT:
	2731	case DL6_AGENT2MODULE_CNT:
	2732	case DL7_AGENT2MODULE_CNT:
	2733	case DL8_AGENT2MODULE_CNT:
	2734	case DL10_AGENT2MODULE_CNT:
	2735	case DL11_AGENT2MODULE_CNT:
	2736	case UL1_MODULE2AGENT_CNT:
	2737	case UL2_MODULE2AGENT_CNT:
	2738	case UL3_MODULE2AGENT_CNT:
	2739	case UL4_MODULE2AGENT_CNT:
	2740	case UL5_MODULE2AGENT_CNT:
	2741	case UL6_MODULE2AGENT_CNT:
	2742	case UL8_MODULE2AGENT_CNT:
	2743	case UL9_MODULE2AGENT_CNT:
	2744	case UL10_MODULE2AGENT_CNT:
	2745	case AFE_DMIC0_SRC_DEBUG_MON0:
	2746	case AFE_DMIC0_UL_SRC_MON0:
	2747	case AFE_DMIC0_UL_SRC_MON1:
	2748	case AFE_DMIC1_SRC_DEBUG_MON0:
	2749	case AFE_DMIC1_UL_SRC_MON0:
	2750	case AFE_DMIC1_UL_SRC_MON1:
	2751	case AFE_DMIC2_SRC_DEBUG_MON0:
	2752	case AFE_DMIC2_UL_SRC_MON0:
	2753	case AFE_DMIC2_UL_SRC_MON1:
	2754	case AFE_DMIC3_SRC_DEBUG_MON0:
	2755	case AFE_DMIC3_UL_SRC_MON0:
	2756	case AFE_DMIC3_UL_SRC_MON1:
	2757	case DMIC_GAIN1_CUR:
	2758	case DMIC_GAIN2_CUR:
	2759	case DMIC_GAIN3_CUR:
	2760	case DMIC_GAIN4_CUR:
	2761	case ETDM_IN1_MONITOR:
	2762	case ETDM_IN2_MONITOR:
	2763	case ETDM_OUT1_MONITOR:
	2764	case ETDM_OUT2_MONITOR:
	2765	case ETDM_OUT3_MONITOR:
	2766	case AFE_ADDA_SRC_DEBUG_MON0:
	2767	case AFE_ADDA_SRC_DEBUG_MON1:
	2768	case AFE_ADDA_DL_SDM_FIFO_MON:
	2769	case AFE_ADDA_DL_SRC_LCH_MON:
	2770	case AFE_ADDA_DL_SRC_RCH_MON:
	2771	case AFE_ADDA_DL_SDM_OUT_MON:
	2772	case AFE_GASRC0_NEW_CON8:
	2773	case AFE_GASRC0_NEW_CON9:
	2774	case AFE_GASRC0_NEW_CON12:
	2775	case AFE_GASRC1_NEW_CON8:
	2776	case AFE_GASRC1_NEW_CON9:
	2777	case AFE_GASRC1_NEW_CON12:
	2778	case AFE_GASRC2_NEW_CON8:
	2779	case AFE_GASRC2_NEW_CON9:
	2780	case AFE_GASRC2_NEW_CON12:
	2781	case AFE_GASRC3_NEW_CON8:
	2782	case AFE_GASRC3_NEW_CON9:
	2783	case AFE_GASRC3_NEW_CON12:
	2784	case AFE_GASRC4_NEW_CON8:
	2785	case AFE_GASRC4_NEW_CON9:
	2786	case AFE_GASRC4_NEW_CON12:
	2787	case AFE_GASRC5_NEW_CON8:
	2788	case AFE_GASRC5_NEW_CON9:
	2789	case AFE_GASRC5_NEW_CON12:
	2790	case AFE_GASRC6_NEW_CON8:
	2791	case AFE_GASRC6_NEW_CON9:
	2792	case AFE_GASRC6_NEW_CON12:
	2793	case AFE_GASRC7_NEW_CON8:
	2794	case AFE_GASRC7_NEW_CON9:
	2795	case AFE_GASRC7_NEW_CON12:
	2796	case AFE_GASRC8_NEW_CON8:
	2797	case AFE_GASRC8_NEW_CON9:
	2798	case AFE_GASRC8_NEW_CON12:
	2799	case AFE_GASRC9_NEW_CON8:
	2800	case AFE_GASRC9_NEW_CON9:
	2801	case AFE_GASRC9_NEW_CON12:
	2802	case AFE_GASRC10_NEW_CON8:
	2803	case AFE_GASRC10_NEW_CON9:
	2804	case AFE_GASRC10_NEW_CON12:
	2805	case AFE_GASRC11_NEW_CON8:
	2806	case AFE_GASRC11_NEW_CON9:
	2807	case AFE_GASRC11_NEW_CON12:
	2808	case AFE_GASRC12_NEW_CON8:
	2809	case AFE_GASRC12_NEW_CON9:
	2810	case AFE_GASRC12_NEW_CON12:
	2811	case AFE_GASRC13_NEW_CON8:
	2812	case AFE_GASRC13_NEW_CON9:
	2813	case AFE_GASRC13_NEW_CON12:
	2814	case AFE_GASRC14_NEW_CON8:
	2815	case AFE_GASRC14_NEW_CON9:
	2816	case AFE_GASRC14_NEW_CON12:
	2817	case AFE_GASRC15_NEW_CON8:
	2818	case AFE_GASRC15_NEW_CON9:
	2819	case AFE_GASRC15_NEW_CON12:
	2820	case AFE_GASRC16_NEW_CON8:
	2821	case AFE_GASRC16_NEW_CON9:
	2822	case AFE_GASRC16_NEW_CON12:
	2823	case AFE_GASRC17_NEW_CON8:
	2824	case AFE_GASRC17_NEW_CON9:
	2825	case AFE_GASRC17_NEW_CON12:
	2826	case AFE_GASRC18_NEW_CON8:
	2827	case AFE_GASRC18_NEW_CON9:
	2828	case AFE_GASRC18_NEW_CON12:
	2829	case AFE_GASRC19_NEW_CON8:
	2830	case AFE_GASRC19_NEW_CON9:
	2831	case AFE_GASRC19_NEW_CON12:
	2832	return true;
	2833	default:
	2834	return false;
	2835	};
	2836	}
	2837
	2838	static const struct regmap_config mt8195_afe_regmap_config = {
	2839	.reg_bits = 32,
	2840	.reg_stride = 4,
	2841	.val_bits = 32,
	2842	.volatile_reg = mt8195_is_volatile_reg,
	2843	.max_register = AFE_MAX_REGISTER,
	2844	.num_reg_defaults_raw = ((AFE_MAX_REGISTER / 4) + 1),
	2845	.cache_type = REGCACHE_FLAT,
	2846	};
	2847
	2848	#define AFE_IRQ_CLR_BITS (0x387)
	2849	#define ASYS_IRQ_CLR_BITS (0xffff)
	2850
	2851	static irqreturn_t mt8195_afe_irq_handler(int irq_id, void *dev_id)
	2852	{
	2853	struct mtk_base_afe *afe = dev_id;
	2854	unsigned int val = 0;
	2855	unsigned int asys_irq_clr_bits = 0;
	2856	unsigned int afe_irq_clr_bits = 0;
	2857	unsigned int irq_status_bits = 0;
	2858	unsigned int irq_clr_bits = 0;
	2859	unsigned int mcu_irq_mask = 0;
	2860	int i = 0;
	2861	int ret = 0;
	2862
	2863	ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, &val);
	2864	if (ret) {
	2865	dev_info(afe->dev, "%s irq status err\n", __func__);
	2866	afe_irq_clr_bits = AFE_IRQ_CLR_BITS;
	2867	asys_irq_clr_bits = ASYS_IRQ_CLR_BITS;
	2868	goto err_irq;
	2869	}
	2870
	2871	ret = regmap_read(afe->regmap, AFE_IRQ_MASK, &mcu_irq_mask);
	2872	if (ret) {
	2873	dev_info(afe->dev, "%s read irq mask err\n", __func__);
	2874	afe_irq_clr_bits = AFE_IRQ_CLR_BITS;
	2875	asys_irq_clr_bits = ASYS_IRQ_CLR_BITS;
	2876	goto err_irq;
	2877	}
	2878
	2879	/* only clr cpu irq */
	2880	val &= mcu_irq_mask;
	2881
	2882	for (i = 0; i < MT8195_AFE_MEMIF_NUM; i++) {
	2883	struct mtk_base_afe_memif *memif = &afe->memif[i];
	2884	struct mtk_base_irq_data const *irq_data;
	2885
	2886	if (memif->irq_usage < 0)
	2887	continue;
	2888
	2889	irq_data = afe->irqs[memif->irq_usage].irq_data;
	2890
	2891	irq_status_bits = BIT(irq_data->irq_status_shift);
	2892	irq_clr_bits = BIT(irq_data->irq_clr_shift);
	2893
	2894	if (!(val & irq_status_bits))
	2895	continue;
	2896
	2897	if (irq_data->irq_clr_reg == ASYS_IRQ_CLR)
	2898	asys_irq_clr_bits \|= irq_clr_bits;
	2899	else
	2900	afe_irq_clr_bits \|= irq_clr_bits;
	2901
	2902	snd_pcm_period_elapsed(memif->substream);
	2903	}
	2904
	2905	err_irq:
	2906	/* clear irq */
	2907	if (asys_irq_clr_bits)
	2908	regmap_write(afe->regmap, ASYS_IRQ_CLR, asys_irq_clr_bits);
	2909	if (afe_irq_clr_bits)
	2910	regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, afe_irq_clr_bits);
	2911
	2912	return IRQ_HANDLED;
	2913	}
	2914
	2915	static int mt8195_afe_runtime_suspend(struct device *dev)
	2916	{
	2917	struct mtk_base_afe *afe = dev_get_drvdata(dev);
	2918	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	2919
	2920	if (!afe->regmap \|\| afe_priv->pm_runtime_bypass_reg_ctl)
	2921	goto skip_regmap;
	2922
	2923	mt8195_afe_disable_main_clock(afe);
	2924
	2925	regcache_cache_only(afe->regmap, true);
	2926	regcache_mark_dirty(afe->regmap);
	2927
	2928	skip_regmap:
	2929	mt8195_afe_disable_reg_rw_clk(afe);
	2930
	2931	return 0;
	2932	}
	2933
	2934	static int mt8195_afe_runtime_resume(struct device *dev)
	2935	{
	2936	struct mtk_base_afe *afe = dev_get_drvdata(dev);
	2937	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	2938
	2939	mt8195_afe_enable_reg_rw_clk(afe);
	2940
	2941	if (!afe->regmap \|\| afe_priv->pm_runtime_bypass_reg_ctl)
	2942	goto skip_regmap;
	2943
	2944	regcache_cache_only(afe->regmap, false);
	2945	regcache_sync(afe->regmap);
	2946
	2947	mt8195_afe_enable_main_clock(afe);
	2948	skip_regmap:
	2949	return 0;
	2950	}
	2951
	2952	static int mt8195_afe_component_probe(struct snd_soc_component *component)
	2953	{
	2954	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
	2955	int ret = 0;
	2956
	2957	snd_soc_component_init_regmap(component, afe->regmap);
	2958
	2959	ret = mtk_afe_add_sub_dai_control(component);
	2960
	2961	return ret;
	2962	}
	2963
	2964	static const struct snd_soc_component_driver mt8195_afe_component = {
	2965	.name = AFE_PCM_NAME,
	2966	.pointer = mtk_afe_pcm_pointer,
	2967	.pcm_construct = mtk_afe_pcm_new,
	2968	.probe = mt8195_afe_component_probe,
	2969	};
	2970
	2971	static int init_memif_priv_data(struct mtk_base_afe *afe)
	2972	{
	2973	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	2974	struct mtk_dai_memif_priv *memif_priv;
	2975	int i;
	2976
	2977	for (i = MT8195_AFE_MEMIF_START; i < MT8195_AFE_MEMIF_END; i++) {
	2978	memif_priv = devm_kzalloc(afe->dev,
	2979	sizeof(struct mtk_dai_memif_priv),
	2980	GFP_KERNEL);
	2981	if (!memif_priv)
	2982	return -ENOMEM;
	2983
	2984	afe_priv->dai_priv[i] = memif_priv;
	2985	}
	2986
	2987	return 0;
	2988	}
	2989
	2990	static int mt8195_dai_memif_register(struct mtk_base_afe *afe)
	2991	{
	2992	struct mtk_base_afe_dai *dai;
	2993
	2994	dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
	2995	if (!dai)
	2996	return -ENOMEM;
	2997
	2998	list_add(&dai->list, &afe->sub_dais);
	2999
	3000	dai->dai_drivers = mt8195_memif_dai_driver;
	3001	dai->num_dai_drivers = ARRAY_SIZE(mt8195_memif_dai_driver);
	3002
	3003	dai->dapm_widgets = mt8195_memif_widgets;
	3004	dai->num_dapm_widgets = ARRAY_SIZE(mt8195_memif_widgets);
	3005	dai->dapm_routes = mt8195_memif_routes;
	3006	dai->num_dapm_routes = ARRAY_SIZE(mt8195_memif_routes);
	3007	dai->controls = mt8195_memif_controls;
	3008	dai->num_controls = ARRAY_SIZE(mt8195_memif_controls);
	3009
	3010	return init_memif_priv_data(afe);
	3011	}
	3012
	3013	typedef int (dai_register_cb)(struct mtk_base_afe );
	3014	static const dai_register_cb dai_register_cbs[] = {
	3015	mt8195_dai_adda_register,
	3016	mt8195_dai_etdm_register,
	3017	mt8195_dai_pcm_register,
	3018	mt8195_dai_memif_register,
	3019	};
	3020
	3021	static const struct reg_sequence mt8195_afe_reg_defaults[] = {
	3022	{ AFE_IRQ_MASK, 0x387ffff },
	3023	{ AFE_IRQ3_CON, BIT(30) },
	3024	{ AFE_IRQ9_CON, BIT(30) },
	3025	{ ETDM_IN1_CON4, 0x12000100 },
	3026	{ ETDM_IN2_CON4, 0x12000100 },
	3027	};
	3028
	3029	static const struct reg_sequence mt8195_cg_patch[] = {
	3030	{ AUDIO_TOP_CON0, 0xfffffffb },
	3031	{ AUDIO_TOP_CON1, 0xfffffffa },
	3032	};
	3033
	3034	static int mt8195_afe_init_registers(struct mtk_base_afe *afe)
	3035	{
	3036	return regmap_multi_reg_write(afe->regmap,
	3037	mt8195_afe_reg_defaults,
	3038	ARRAY_SIZE(mt8195_afe_reg_defaults));
	3039	}
	3040
	3041	static void mt8195_afe_parse_of(struct mtk_base_afe *afe,
	3042	struct device_node *np)
	3043	{
	3044	#if IS_ENABLED(CONFIG_SND_SOC_MT6359)
	3045	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	3046
	3047	afe_priv->topckgen = syscon_regmap_lookup_by_phandle(afe->dev->of_node,
	3048	"mediatek,topckgen");
	3049	if (IS_ERR(afe_priv->topckgen)) {
	3050	dev_info(afe->dev, "%s() Cannot find topckgen controller: %ld\n",
	3051	__func__, PTR_ERR(afe_priv->topckgen));
	3052	}
	3053	#endif
	3054	}
	3055
	3056	static int mt8195_afe_pcm_dev_probe(struct platform_device *pdev)
	3057	{
	3058	struct mtk_base_afe *afe;
	3059	struct mt8195_afe_private *afe_priv;
	3060	struct resource *res;
	3061	struct device *dev = &pdev->dev;
	3062	int i, irq_id, ret;
	3063	struct snd_soc_component *component;
	3064
	3065	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(33));
	3066	if (ret)
	3067	return ret;
	3068
	3069	afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL);
	3070	if (!afe)
	3071	return -ENOMEM;
	3072
	3073	afe->platform_priv = devm_kzalloc(dev, sizeof(*afe_priv),
	3074	GFP_KERNEL);
	3075	if (!afe->platform_priv)
	3076	return -ENOMEM;
	3077
	3078	afe_priv = afe->platform_priv;
	3079	afe->dev = &pdev->dev;
	3080
	3081	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	3082	afe->base_addr = devm_ioremap_resource(&pdev->dev, res);
	3083	if (IS_ERR(afe->base_addr))
	3084	return PTR_ERR(afe->base_addr);
	3085
	3086	/* initial audio related clock */
	3087	ret = mt8195_afe_init_clock(afe);
	3088	if (ret) {
	3089	dev_err(dev, "init clock error\n");
	3090	return ret;
	3091	}
	3092
	3093	spin_lock_init(&afe_priv->afe_ctrl_lock);
	3094
	3095	mutex_init(&afe->irq_alloc_lock);
	3096
	3097	/* irq initialize */
	3098	afe->irqs_size = MT8195_AFE_IRQ_NUM;
	3099	afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
	3100	GFP_KERNEL);
	3101	if (!afe->irqs)
	3102	return -ENOMEM;
	3103
	3104	for (i = 0; i < afe->irqs_size; i++)
	3105	afe->irqs[i].irq_data = &irq_data[i];
	3106
	3107	/* init memif */
	3108	afe->memif_size = MT8195_AFE_MEMIF_NUM;
	3109	afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
	3110	GFP_KERNEL);
	3111	if (!afe->memif)
	3112	return -ENOMEM;
	3113
	3114	for (i = 0; i < afe->memif_size; i++) {
	3115	afe->memif[i].data = &memif_data[i];
	3116	afe->memif[i].irq_usage = mt8195_afe_memif_const_irqs[i];
	3117	afe->memif[i].const_irq = 1;
	3118	afe->irqs[afe->memif[i].irq_usage].irq_occupyed = true;
	3119	}
	3120
	3121	/* request irq */
	3122	irq_id = platform_get_irq(pdev, 0);
	3123	if (irq_id < 0) {
	3124	dev_err(dev, "%s no irq found\n", dev->of_node->name);
	3125	return -ENXIO;
	3126	}
	3127
	3128	ret = devm_request_irq(dev, irq_id, mt8195_afe_irq_handler,
	3129	IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
	3130	if (ret) {
	3131	dev_err(dev, "could not request_irq for asys-isr\n");
	3132	return ret;
	3133	}
	3134
	3135	/* init sub_dais */
	3136	INIT_LIST_HEAD(&afe->sub_dais);
	3137
	3138	for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
	3139	ret = dai_register_cbs[i](afe);
	3140	if (ret) {
	3141	dev_warn(dev, "dai register i %d fail, ret %d\n",
	3142	i, ret);
	3143	return ret;
	3144	}
	3145	}
	3146
	3147	/* init dai_driver and component_driver */
	3148	ret = mtk_afe_combine_sub_dai(afe);
	3149	if (ret) {
	3150	dev_warn(dev, "mtk_afe_combine_sub_dai fail, ret %d\n",
	3151	ret);
	3152	return ret;
	3153	}
	3154
	3155	afe->mtk_afe_hardware = &mt8195_afe_hardware;
	3156	afe->memif_fs = mt8195_memif_fs;
	3157	afe->irq_fs = mt8195_irq_fs;
	3158
	3159	afe->runtime_resume = mt8195_afe_runtime_resume;
	3160	afe->runtime_suspend = mt8195_afe_runtime_suspend;
	3161
	3162	platform_set_drvdata(pdev, afe);
	3163
	3164	mt8195_afe_parse_of(afe, pdev->dev.of_node);
	3165
	3166	pm_runtime_enable(dev);
	3167	if (!pm_runtime_enabled(dev)) {
	3168	ret = mt8195_afe_runtime_resume(dev);
	3169	if (ret)
	3170	return ret;
	3171	}
	3172
	3173	/* enable clock for regcache get default value from hw */
	3174	afe_priv->pm_runtime_bypass_reg_ctl = true;
	3175	pm_runtime_get_sync(dev);
	3176
	3177	afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
	3178	&mt8195_afe_regmap_config);
	3179	if (IS_ERR(afe->regmap)) {
	3180	ret = PTR_ERR(afe->regmap);
	3181	goto err_pm_put;
	3182	}
	3183
	3184	ret = regmap_register_patch(afe->regmap, mt8195_cg_patch,
	3185	ARRAY_SIZE(mt8195_cg_patch));
	3186	if (ret < 0) {
	3187	dev_err(dev, "Failed to apply cg patch\n");
	3188	goto err_pm_put;
	3189	}
	3190
	3191	/* register component */
	3192	ret = devm_snd_soc_register_component(dev, &mt8195_afe_component,
	3193	NULL, 0);
	3194	if (ret) {
	3195	dev_warn(dev, "err_platform\n");
	3196	goto err_pm_put;
	3197	}
	3198
	3199	component = devm_kzalloc(dev, sizeof(*component), GFP_KERNEL);
	3200	if (!component) {
	3201	ret = -ENOMEM;
	3202	goto err_pm_put;
	3203	}
	3204
	3205	ret = snd_soc_component_initialize(component,
	3206	&mt8195_afe_pcm_dai_component,
	3207	dev);
	3208	if (ret)
	3209	goto err_pm_put;
	3210
	3211	#ifdef CONFIG_DEBUG_FS
	3212	component->debugfs_prefix = "pcm";
	3213	#endif
	3214
	3215	ret = snd_soc_add_component(component,
	3216	afe->dai_drivers,
	3217	afe->num_dai_drivers);
	3218	if (ret) {
	3219	dev_warn(dev, "err_dai_component\n");
	3220	goto err_pm_put;
	3221	}
	3222
	3223	mt8195_afe_init_registers(afe);
	3224
	3225	pm_runtime_put_sync(dev);
	3226	afe_priv->pm_runtime_bypass_reg_ctl = false;
	3227
	3228	regcache_cache_only(afe->regmap, true);
	3229	regcache_mark_dirty(afe->regmap);
	3230
	3231	return 0;
	3232
	3233	err_pm_put:
	3234	pm_runtime_put_sync(dev);
	3235	pm_runtime_disable(dev);
	3236
	3237	return ret;
	3238	}
	3239
	3240	static int mt8195_afe_pcm_dev_remove(struct platform_device *pdev)
	3241	{
	3242	struct mtk_base_afe *afe = platform_get_drvdata(pdev);
	3243
	3244	snd_soc_unregister_component(&pdev->dev);
	3245
	3246	pm_runtime_disable(&pdev->dev);
	3247	if (!pm_runtime_status_suspended(&pdev->dev))
	3248	mt8195_afe_runtime_suspend(&pdev->dev);
	3249
	3250	mt8195_afe_deinit_clock(afe);
	3251	return 0;
	3252	}
	3253
	3254	static const struct of_device_id mt8195_afe_pcm_dt_match[] = {
	3255	{.compatible = "mediatek,mt8195-audio", },
	3256	{},
	3257	};
	3258	MODULE_DEVICE_TABLE(of, mt8195_afe_pcm_dt_match);
	3259
	3260	static const struct dev_pm_ops mt8195_afe_pm_ops = {
	3261	SET_RUNTIME_PM_OPS(mt8195_afe_runtime_suspend,
	3262	mt8195_afe_runtime_resume, NULL)
	3263	};
	3264
	3265	static struct platform_driver mt8195_afe_pcm_driver = {
	3266	.driver = {
	3267	.name = "mt8195-audio",
	3268	.of_match_table = mt8195_afe_pcm_dt_match,
	3269	#ifdef CONFIG_PM
	3270	.pm = &mt8195_afe_pm_ops,
	3271	#endif
	3272	},
	3273	.probe = mt8195_afe_pcm_dev_probe,
	3274	.remove = mt8195_afe_pcm_dev_remove,
	3275	};
	3276
	3277	module_platform_driver(mt8195_afe_pcm_driver);
	3278
	3279	MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8195");
	3280	MODULE_AUTHOR("Bicycle Tsai <bicycle.tsai@mediatek.com>");
	3281	MODULE_LICENSE("GPL v2");

sound/soc/mediatek/mt8195/mt8195-audsys-clk.c+214−0

@@ -0,0 +1,214 @@
	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* mt8195-audsys-clk.h -- Mediatek 8195 audsys clock control
	4	*
	5	* Copyright (c) 2021 MediaTek Inc.
	6	* Author: Trevor Wu <trevor.wu@mediatek.com>
	7	*/
	8
	9	#include <linux/clk.h>
	10	#include <linux/clk-provider.h>
	11	#include <linux/clkdev.h>
	12	#include "mt8195-afe-common.h"
	13	#include "mt8195-audsys-clk.h"
	14	#include "mt8195-audsys-clkid.h"
	15	#include "mt8195-reg.h"
	16
	17	struct afe_gate {
	18	int id;
	19	const char *name;
	20	const char *parent_name;
	21	int reg;
	22	u8 bit;
	23	const struct clk_ops *ops;
	24	unsigned long flags;
	25	u8 cg_flags;
	26	};
	27
	28	#define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\
	29	.id = _id, \
	30	.name = _name, \
	31	.parent_name = _parent, \
	32	.reg = _reg, \
	33	.bit = _bit, \
	34	.flags = _flags, \
	35	.cg_flags = _cgflags, \
	36	}
	37
	38	#define GATE_AFE(_id, _name, _parent, _reg, _bit) \
	39	GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
	40	CLK_SET_RATE_PARENT, CLK_GATE_SET_TO_DISABLE)
	41
	42	#define GATE_AUD0(_id, _name, _parent, _bit) \
	43	GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
	44
	45	#define GATE_AUD1(_id, _name, _parent, _bit) \
	46	GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
	47
	48	#define GATE_AUD3(_id, _name, _parent, _bit) \
	49	GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON3, _bit)
	50
	51	#define GATE_AUD4(_id, _name, _parent, _bit) \
	52	GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON4, _bit)
	53
	54	#define GATE_AUD5(_id, _name, _parent, _bit) \
	55	GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON5, _bit)
	56
	57	#define GATE_AUD6(_id, _name, _parent, _bit) \
	58	GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON6, _bit)
	59
	60	static const struct afe_gate aud_clks[CLK_AUD_NR_CLK] = {
	61	/* AUD0 */
	62	GATE_AUD0(CLK_AUD_AFE, "aud_afe", "a1sys_hp_sel", 2),
	63	GATE_AUD0(CLK_AUD_LRCK_CNT, "aud_lrck_cnt", "a1sys_hp_sel", 4),
	64	GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_APLL, "aud_spdifin_tuner_apll", "apll4_sel", 10),
	65	GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_DBG, "aud_spdifin_tuner_dbg", "apll4_sel", 11),
	66	GATE_AUD0(CLK_AUD_UL_TML, "aud_ul_tml", "a1sys_hp_sel", 18),
	67	GATE_AUD0(CLK_AUD_APLL1_TUNER, "aud_apll1_tuner", "apll1_sel", 19),
	68	GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "apll2_sel", 20),
	69	GATE_AUD0(CLK_AUD_TOP0_SPDF, "aud_top0_spdf", "aud_iec_sel", 21),
	70	GATE_AUD0(CLK_AUD_APLL, "aud_apll", "apll1_sel", 23),
	71	GATE_AUD0(CLK_AUD_APLL2, "aud_apll2", "apll2_sel", 24),
	72	GATE_AUD0(CLK_AUD_DAC, "aud_dac", "a1sys_hp_sel", 25),
	73	GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "a1sys_hp_sel", 26),
	74	GATE_AUD0(CLK_AUD_TML, "aud_tml", "a1sys_hp_sel", 27),
	75	GATE_AUD0(CLK_AUD_ADC, "aud_adc", "a1sys_hp_sel", 28),
	76	GATE_AUD0(CLK_AUD_DAC_HIRES, "aud_dac_hires", "audio_h_sel", 31),
	77
	78	/* AUD1 */
	79	GATE_AUD1(CLK_AUD_A1SYS_HP, "aud_a1sys_hp", "a1sys_hp_sel", 2),
	80	GATE_AUD1(CLK_AUD_AFE_DMIC1, "aud_afe_dmic1", "a1sys_hp_sel", 10),
	81	GATE_AUD1(CLK_AUD_AFE_DMIC2, "aud_afe_dmic2", "a1sys_hp_sel", 11),
	82	GATE_AUD1(CLK_AUD_AFE_DMIC3, "aud_afe_dmic3", "a1sys_hp_sel", 12),
	83	GATE_AUD1(CLK_AUD_AFE_DMIC4, "aud_afe_dmic4", "a1sys_hp_sel", 13),
	84	GATE_AUD1(CLK_AUD_AFE_26M_DMIC_TM, "aud_afe_26m_dmic_tm", "a1sys_hp_sel", 14),
	85	GATE_AUD1(CLK_AUD_UL_TML_HIRES, "aud_ul_tml_hires", "audio_h_sel", 16),
	86	GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires", "audio_h_sel", 17),
	87	GATE_AUD1(CLK_AUD_ADDA6_ADC, "aud_adda6_adc", "a1sys_hp_sel", 18),
	88	GATE_AUD1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires", "audio_h_sel", 19),
	89
	90	/* AUD3 */
	91	GATE_AUD3(CLK_AUD_LINEIN_TUNER, "aud_linein_tuner", "apll5_sel", 5),
	92	GATE_AUD3(CLK_AUD_EARC_TUNER, "aud_earc_tuner", "apll3_sel", 7),
	93
	94	/* AUD4 */
	95	GATE_AUD4(CLK_AUD_I2SIN, "aud_i2sin", "a1sys_hp_sel", 0),
	96	GATE_AUD4(CLK_AUD_TDM_IN, "aud_tdm_in", "a1sys_hp_sel", 1),
	97	GATE_AUD4(CLK_AUD_I2S_OUT, "aud_i2s_out", "a1sys_hp_sel", 6),
	98	GATE_AUD4(CLK_AUD_TDM_OUT, "aud_tdm_out", "a1sys_hp_sel", 7),
	99	GATE_AUD4(CLK_AUD_HDMI_OUT, "aud_hdmi_out", "a1sys_hp_sel", 8),
	100	GATE_AUD4(CLK_AUD_ASRC11, "aud_asrc11", "a1sys_hp_sel", 16),
	101	GATE_AUD4(CLK_AUD_ASRC12, "aud_asrc12", "a1sys_hp_sel", 17),
	102	GATE_AUD4(CLK_AUD_MULTI_IN, "aud_multi_in", "mphone_slave_b", 19),
	103	GATE_AUD4(CLK_AUD_INTDIR, "aud_intdir", "intdir_sel", 20),
	104	GATE_AUD4(CLK_AUD_A1SYS, "aud_a1sys", "a1sys_hp_sel", 21),
	105	GATE_AUD4(CLK_AUD_A2SYS, "aud_a2sys", "a2sys_sel", 22),
	106	GATE_AUD4(CLK_AUD_PCMIF, "aud_pcmif", "a1sys_hp_sel", 24),
	107	GATE_AUD4(CLK_AUD_A3SYS, "aud_a3sys", "a3sys_sel", 30),
	108	GATE_AUD4(CLK_AUD_A4SYS, "aud_a4sys", "a4sys_sel", 31),
	109
	110	/* AUD5 */
	111	GATE_AUD5(CLK_AUD_MEMIF_UL1, "aud_memif_ul1", "a1sys_hp_sel", 0),
	112	GATE_AUD5(CLK_AUD_MEMIF_UL2, "aud_memif_ul2", "a1sys_hp_sel", 1),
	113	GATE_AUD5(CLK_AUD_MEMIF_UL3, "aud_memif_ul3", "a1sys_hp_sel", 2),
	114	GATE_AUD5(CLK_AUD_MEMIF_UL4, "aud_memif_ul4", "a1sys_hp_sel", 3),
	115	GATE_AUD5(CLK_AUD_MEMIF_UL5, "aud_memif_ul5", "a1sys_hp_sel", 4),
	116	GATE_AUD5(CLK_AUD_MEMIF_UL6, "aud_memif_ul6", "a1sys_hp_sel", 5),
	117	GATE_AUD5(CLK_AUD_MEMIF_UL8, "aud_memif_ul8", "a1sys_hp_sel", 7),
	118	GATE_AUD5(CLK_AUD_MEMIF_UL9, "aud_memif_ul9", "a1sys_hp_sel", 8),
	119	GATE_AUD5(CLK_AUD_MEMIF_UL10, "aud_memif_ul10", "a1sys_hp_sel", 9),
	120	GATE_AUD5(CLK_AUD_MEMIF_DL2, "aud_memif_dl2", "a1sys_hp_sel", 18),
	121	GATE_AUD5(CLK_AUD_MEMIF_DL3, "aud_memif_dl3", "a1sys_hp_sel", 19),
	122	GATE_AUD5(CLK_AUD_MEMIF_DL6, "aud_memif_dl6", "a1sys_hp_sel", 22),
	123	GATE_AUD5(CLK_AUD_MEMIF_DL7, "aud_memif_dl7", "a1sys_hp_sel", 23),
	124	GATE_AUD5(CLK_AUD_MEMIF_DL8, "aud_memif_dl8", "a1sys_hp_sel", 24),
	125	GATE_AUD5(CLK_AUD_MEMIF_DL10, "aud_memif_dl10", "a1sys_hp_sel", 26),
	126	GATE_AUD5(CLK_AUD_MEMIF_DL11, "aud_memif_dl11", "a1sys_hp_sel", 27),
	127
	128	/* AUD6 */
	129	GATE_AUD6(CLK_AUD_GASRC0, "aud_gasrc0", "asm_h_sel", 0),
	130	GATE_AUD6(CLK_AUD_GASRC1, "aud_gasrc1", "asm_h_sel", 1),
	131	GATE_AUD6(CLK_AUD_GASRC2, "aud_gasrc2", "asm_h_sel", 2),
	132	GATE_AUD6(CLK_AUD_GASRC3, "aud_gasrc3", "asm_h_sel", 3),
	133	GATE_AUD6(CLK_AUD_GASRC4, "aud_gasrc4", "asm_h_sel", 4),
	134	GATE_AUD6(CLK_AUD_GASRC5, "aud_gasrc5", "asm_h_sel", 5),
	135	GATE_AUD6(CLK_AUD_GASRC6, "aud_gasrc6", "asm_h_sel", 6),
	136	GATE_AUD6(CLK_AUD_GASRC7, "aud_gasrc7", "asm_h_sel", 7),
	137	GATE_AUD6(CLK_AUD_GASRC8, "aud_gasrc8", "asm_h_sel", 8),
	138	GATE_AUD6(CLK_AUD_GASRC9, "aud_gasrc9", "asm_h_sel", 9),
	139	GATE_AUD6(CLK_AUD_GASRC10, "aud_gasrc10", "asm_h_sel", 10),
	140	GATE_AUD6(CLK_AUD_GASRC11, "aud_gasrc11", "asm_h_sel", 11),
	141	GATE_AUD6(CLK_AUD_GASRC12, "aud_gasrc12", "asm_h_sel", 12),
	142	GATE_AUD6(CLK_AUD_GASRC13, "aud_gasrc13", "asm_h_sel", 13),
	143	GATE_AUD6(CLK_AUD_GASRC14, "aud_gasrc14", "asm_h_sel", 14),
	144	GATE_AUD6(CLK_AUD_GASRC15, "aud_gasrc15", "asm_h_sel", 15),
	145	GATE_AUD6(CLK_AUD_GASRC16, "aud_gasrc16", "asm_h_sel", 16),
	146	GATE_AUD6(CLK_AUD_GASRC17, "aud_gasrc17", "asm_h_sel", 17),
	147	GATE_AUD6(CLK_AUD_GASRC18, "aud_gasrc18", "asm_h_sel", 18),
	148	GATE_AUD6(CLK_AUD_GASRC19, "aud_gasrc19", "asm_h_sel", 19),
	149	};
	150
	151	int mt8195_audsys_clk_register(struct mtk_base_afe *afe)
	152	{
	153	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	154	struct clk *clk;
	155	struct clk_lookup *cl;
	156	int i;
	157
	158	afe_priv->lookup = devm_kcalloc(afe->dev, CLK_AUD_NR_CLK,
	159	sizeof(*afe_priv->lookup),
	160	GFP_KERNEL);
	161
	162	if (!afe_priv->lookup)
	163	return -ENOMEM;
	164
	165	for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
	166	const struct afe_gate *gate = &aud_clks[i];
	167
	168	clk = clk_register_gate(afe->dev, gate->name, gate->parent_name,
	169	gate->flags, afe->base_addr + gate->reg,
	170	gate->bit, gate->cg_flags, NULL);
	171
	172	if (IS_ERR(clk)) {
	173	dev_err(afe->dev, "Failed to register clk %s: %ld\n",
	174	gate->name, PTR_ERR(clk));
	175	continue;
	176	}
	177
	178	/* add clk_lookup for devm_clk_get(SND_SOC_DAPM_CLOCK_SUPPLY) */
	179	cl = kzalloc(sizeof(*cl), GFP_KERNEL);
	180	if (!cl)
	181	return -ENOMEM;
	182
	183	cl->clk = clk;
	184	cl->con_id = gate->name;
	185	cl->dev_id = dev_name(afe->dev);
	186	clkdev_add(cl);
	187
	188	afe_priv->lookup[i] = cl;
	189	}
	190
	191	return 0;
	192	}
	193
	194	void mt8195_audsys_clk_unregister(struct mtk_base_afe *afe)
	195	{
	196	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	197	struct clk *clk;
	198	struct clk_lookup *cl;
	199	int i;
	200
	201	if (!afe_priv)
	202	return;
	203
	204	for (i = 0; i < CLK_AUD_NR_CLK; i++) {
	205	cl = afe_priv->lookup[i];
	206	if (!cl)
	207	continue;
	208
	209	clk = cl->clk;
	210	clk_unregister_gate(clk);
	211
	212	clkdev_drop(cl);
	213	}
	214	}

sound/soc/mediatek/mt8195/mt8195-audsys-clk.h+15−0

@@ -0,0 +1,15 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* mt8195-audsys-clk.h -- Mediatek 8195 audsys clock definition
	4	*
	5	* Copyright (c) 2021 MediaTek Inc.
	6	* Author: Trevor Wu <trevor.wu@mediatek.com>
	7	*/
	8
	9	#ifndef _MT8195_AUDSYS_CLK_H_
	10	#define _MT8195_AUDSYS_CLK_H_
	11
	12	int mt8195_audsys_clk_register(struct mtk_base_afe *afe);
	13	void mt8195_audsys_clk_unregister(struct mtk_base_afe *afe);
	14
	15	#endif

sound/soc/mediatek/mt8195/mt8195-audsys-clkid.h+93−0

@@ -0,0 +1,93 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* mt8195-audsys-clkid.h -- Mediatek 8195 audsys clock id definition
	4	*
	5	* Copyright (c) 2021 MediaTek Inc.
	6	* Author: Trevor Wu <trevor.wu@mediatek.com>
	7	*/
	8
	9	#ifndef _MT8195_AUDSYS_CLKID_H_
	10	#define _MT8195_AUDSYS_CLKID_H_
	11
	12	enum{
	13	CLK_AUD_AFE,
	14	CLK_AUD_LRCK_CNT,
	15	CLK_AUD_SPDIFIN_TUNER_APLL,
	16	CLK_AUD_SPDIFIN_TUNER_DBG,
	17	CLK_AUD_UL_TML,
	18	CLK_AUD_APLL1_TUNER,
	19	CLK_AUD_APLL2_TUNER,
	20	CLK_AUD_TOP0_SPDF,
	21	CLK_AUD_APLL,
	22	CLK_AUD_APLL2,
	23	CLK_AUD_DAC,
	24	CLK_AUD_DAC_PREDIS,
	25	CLK_AUD_TML,
	26	CLK_AUD_ADC,
	27	CLK_AUD_DAC_HIRES,
	28	CLK_AUD_A1SYS_HP,
	29	CLK_AUD_AFE_DMIC1,
	30	CLK_AUD_AFE_DMIC2,
	31	CLK_AUD_AFE_DMIC3,
	32	CLK_AUD_AFE_DMIC4,
	33	CLK_AUD_AFE_26M_DMIC_TM,
	34	CLK_AUD_UL_TML_HIRES,
	35	CLK_AUD_ADC_HIRES,
	36	CLK_AUD_ADDA6_ADC,
	37	CLK_AUD_ADDA6_ADC_HIRES,
	38	CLK_AUD_LINEIN_TUNER,
	39	CLK_AUD_EARC_TUNER,
	40	CLK_AUD_I2SIN,
	41	CLK_AUD_TDM_IN,
	42	CLK_AUD_I2S_OUT,
	43	CLK_AUD_TDM_OUT,
	44	CLK_AUD_HDMI_OUT,
	45	CLK_AUD_ASRC11,
	46	CLK_AUD_ASRC12,
	47	CLK_AUD_MULTI_IN,
	48	CLK_AUD_INTDIR,
	49	CLK_AUD_A1SYS,
	50	CLK_AUD_A2SYS,
	51	CLK_AUD_PCMIF,
	52	CLK_AUD_A3SYS,
	53	CLK_AUD_A4SYS,
	54	CLK_AUD_MEMIF_UL1,
	55	CLK_AUD_MEMIF_UL2,
	56	CLK_AUD_MEMIF_UL3,
	57	CLK_AUD_MEMIF_UL4,
	58	CLK_AUD_MEMIF_UL5,
	59	CLK_AUD_MEMIF_UL6,
	60	CLK_AUD_MEMIF_UL8,
	61	CLK_AUD_MEMIF_UL9,
	62	CLK_AUD_MEMIF_UL10,
	63	CLK_AUD_MEMIF_DL2,
	64	CLK_AUD_MEMIF_DL3,
	65	CLK_AUD_MEMIF_DL6,
	66	CLK_AUD_MEMIF_DL7,
	67	CLK_AUD_MEMIF_DL8,
	68	CLK_AUD_MEMIF_DL10,
	69	CLK_AUD_MEMIF_DL11,
	70	CLK_AUD_GASRC0,
	71	CLK_AUD_GASRC1,
	72	CLK_AUD_GASRC2,
	73	CLK_AUD_GASRC3,
	74	CLK_AUD_GASRC4,
	75	CLK_AUD_GASRC5,
	76	CLK_AUD_GASRC6,
	77	CLK_AUD_GASRC7,
	78	CLK_AUD_GASRC8,
	79	CLK_AUD_GASRC9,
	80	CLK_AUD_GASRC10,
	81	CLK_AUD_GASRC11,
	82	CLK_AUD_GASRC12,
	83	CLK_AUD_GASRC13,
	84	CLK_AUD_GASRC14,
	85	CLK_AUD_GASRC15,
	86	CLK_AUD_GASRC16,
	87	CLK_AUD_GASRC17,
	88	CLK_AUD_GASRC18,
	89	CLK_AUD_GASRC19,
	90	CLK_AUD_NR_CLK,
	91	};
	92
	93	#endif

sound/soc/mediatek/mt8195/mt8195-dai-adda.c+830−0

@@ -0,0 +1,830 @@
	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* MediaTek ALSA SoC Audio DAI ADDA Control
	4	*
	5	* Copyright (c) 2021 MediaTek Inc.
	6	* Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
	7	* Trevor Wu <trevor.wu@mediatek.com>
	8	*/
	9
	10	#include <linux/delay.h>
	11	#include <linux/regmap.h>
	12	#include "mt8195-afe-clk.h"
	13	#include "mt8195-afe-common.h"
	14	#include "mt8195-reg.h"
	15
	16	#define ADDA_DL_GAIN_LOOPBACK 0x1800
	17	#define ADDA_HIRES_THRES 48000
	18
	19	enum {
	20	SUPPLY_SEQ_CLOCK_SEL,
	21	SUPPLY_SEQ_CLOCK_ON,
	22	SUPPLY_SEQ_ADDA_DL_ON,
	23	SUPPLY_SEQ_ADDA_MTKAIF_CFG,
	24	SUPPLY_SEQ_ADDA_UL_ON,
	25	SUPPLY_SEQ_ADDA_AFE_ON,
	26	};
	27
	28	enum {
	29	MTK_AFE_ADDA_DL_RATE_8K = 0,
	30	MTK_AFE_ADDA_DL_RATE_11K = 1,
	31	MTK_AFE_ADDA_DL_RATE_12K = 2,
	32	MTK_AFE_ADDA_DL_RATE_16K = 3,
	33	MTK_AFE_ADDA_DL_RATE_22K = 4,
	34	MTK_AFE_ADDA_DL_RATE_24K = 5,
	35	MTK_AFE_ADDA_DL_RATE_32K = 6,
	36	MTK_AFE_ADDA_DL_RATE_44K = 7,
	37	MTK_AFE_ADDA_DL_RATE_48K = 8,
	38	MTK_AFE_ADDA_DL_RATE_96K = 9,
	39	MTK_AFE_ADDA_DL_RATE_192K = 10,
	40	};
	41
	42	enum {
	43	MTK_AFE_ADDA_UL_RATE_8K = 0,
	44	MTK_AFE_ADDA_UL_RATE_16K = 1,
	45	MTK_AFE_ADDA_UL_RATE_32K = 2,
	46	MTK_AFE_ADDA_UL_RATE_48K = 3,
	47	MTK_AFE_ADDA_UL_RATE_96K = 4,
	48	MTK_AFE_ADDA_UL_RATE_192K = 5,
	49	};
	50
	51	enum {
	52	DELAY_DATA_MISO1 = 0,
	53	DELAY_DATA_MISO0 = 1,
	54	DELAY_DATA_MISO2 = 1,
	55	};
	56
	57	enum {
	58	MTK_AFE_ADDA,
	59	MTK_AFE_ADDA6,
	60	};
	61
	62	struct mtk_dai_adda_priv {
	63	bool hires_required;
	64	};
	65
	66	static unsigned int afe_adda_dl_rate_transform(struct mtk_base_afe *afe,
	67	unsigned int rate)
	68	{
	69	switch (rate) {
	70	case 8000:
	71	return MTK_AFE_ADDA_DL_RATE_8K;
	72	case 11025:
	73	return MTK_AFE_ADDA_DL_RATE_11K;
	74	case 12000:
	75	return MTK_AFE_ADDA_DL_RATE_12K;
	76	case 16000:
	77	return MTK_AFE_ADDA_DL_RATE_16K;
	78	case 22050:
	79	return MTK_AFE_ADDA_DL_RATE_22K;
	80	case 24000:
	81	return MTK_AFE_ADDA_DL_RATE_24K;
	82	case 32000:
	83	return MTK_AFE_ADDA_DL_RATE_32K;
	84	case 44100:
	85	return MTK_AFE_ADDA_DL_RATE_44K;
	86	case 48000:
	87	return MTK_AFE_ADDA_DL_RATE_48K;
	88	case 96000:
	89	return MTK_AFE_ADDA_DL_RATE_96K;
	90	case 192000:
	91	return MTK_AFE_ADDA_DL_RATE_192K;
	92	default:
	93	dev_info(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
	94	__func__, rate);
	95	return MTK_AFE_ADDA_DL_RATE_48K;
	96	}
	97	}
	98
	99	static unsigned int afe_adda_ul_rate_transform(struct mtk_base_afe *afe,
	100	unsigned int rate)
	101	{
	102	switch (rate) {
	103	case 8000:
	104	return MTK_AFE_ADDA_UL_RATE_8K;
	105	case 16000:
	106	return MTK_AFE_ADDA_UL_RATE_16K;
	107	case 32000:
	108	return MTK_AFE_ADDA_UL_RATE_32K;
	109	case 48000:
	110	return MTK_AFE_ADDA_UL_RATE_48K;
	111	case 96000:
	112	return MTK_AFE_ADDA_UL_RATE_96K;
	113	case 192000:
	114	return MTK_AFE_ADDA_UL_RATE_192K;
	115	default:
	116	dev_info(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
	117	__func__, rate);
	118	return MTK_AFE_ADDA_UL_RATE_48K;
	119	}
	120	}
	121
	122	static int mt8195_adda_mtkaif_init(struct mtk_base_afe *afe)
	123	{
	124	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	125	struct mtkaif_param *param = &afe_priv->mtkaif_params;
	126	int delay_data;
	127	int delay_cycle;
	128	unsigned int mask = 0;
	129	unsigned int val = 0;
	130
	131	/* set rx protocol 2 & mtkaif_rxif_clkinv_adc inverse */
	132	mask = (MTKAIF_RXIF_CLKINV_ADC \| MTKAIF_RXIF_PROTOCOL2);
	133	val = (MTKAIF_RXIF_CLKINV_ADC \| MTKAIF_RXIF_PROTOCOL2);
	134
	135	regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0, mask, val);
	136	regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIF_CFG0, mask, val);
	137
	138	mask = RG_RX_PROTOCOL2;
	139	val = RG_RX_PROTOCOL2;
	140	regmap_update_bits(afe->regmap, AFE_AUD_PAD_TOP, mask, val);
	141
	142	if (!param->mtkaif_calibration_ok) {
	143	dev_info(afe->dev, "%s(), calibration fail\n", __func__);
	144	return 0;
	145	}
	146
	147	/* set delay for ch1, ch2 */
	148	if (param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0] >=
	149	param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1]) {
	150	delay_data = DELAY_DATA_MISO1;
	151	delay_cycle =
	152	param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0] -
	153	param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1];
	154	} else {
	155	delay_data = DELAY_DATA_MISO0;
	156	delay_cycle =
	157	param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1] -
	158	param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0];
	159	}
	160
	161	val = 0;
	162	mask = (MTKAIF_RXIF_DELAY_DATA \| MTKAIF_RXIF_DELAY_CYCLE_MASK);
	163	val \|= MTKAIF_RXIF_DELAY_CYCLE(delay_cycle) &
	164	MTKAIF_RXIF_DELAY_CYCLE_MASK;
	165	val \|= delay_data << MTKAIF_RXIF_DELAY_DATA_SHIFT;
	166	regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG2, mask, val);
	167
	168	/* set delay between ch3 and ch2 */
	169	if (param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2] >=
	170	param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1]) {
	171	delay_data = DELAY_DATA_MISO1;
	172	delay_cycle =
	173	param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2] -
	174	param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1];
	175	} else {
	176	delay_data = DELAY_DATA_MISO2;
	177	delay_cycle =
	178	param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1] -
	179	param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2];
	180	}
	181
	182	val = 0;
	183	mask = (MTKAIF_RXIF_DELAY_DATA \| MTKAIF_RXIF_DELAY_CYCLE_MASK);
	184	val \|= MTKAIF_RXIF_DELAY_CYCLE(delay_cycle) &
	185	MTKAIF_RXIF_DELAY_CYCLE_MASK;
	186	val \|= delay_data << MTKAIF_RXIF_DELAY_DATA_SHIFT;
	187	regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIF_RX_CFG2, mask, val);
	188
	189	return 0;
	190	}
	191
	192	static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w,
	193	struct snd_kcontrol *kcontrol,
	194	int event)
	195	{
	196	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
	197	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
	198
	199	dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
	200	__func__, w->name, event);
	201
	202	switch (event) {
	203	case SND_SOC_DAPM_PRE_PMU:
	204	mt8195_adda_mtkaif_init(afe);
	205	break;
	206	default:
	207	break;
	208	}
	209
	210	return 0;
	211	}
	212
	213	static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w,
	214	struct snd_kcontrol *kcontrol,
	215	int event)
	216	{
	217	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
	218	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
	219
	220	dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
	221	__func__, w->name, event);
	222
	223	switch (event) {
	224	case SND_SOC_DAPM_POST_PMD:
	225	/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
	226	usleep_range(125, 135);
	227	break;
	228	default:
	229	break;
	230	}
	231
	232	return 0;
	233	}
	234
	235	static void mtk_adda_ul_mictype(struct mtk_base_afe *afe, int adda, bool dmic)
	236	{
	237	unsigned int reg = 0;
	238	unsigned int mask = 0;
	239	unsigned int val = 0;
	240
	241	switch (adda) {
	242	case MTK_AFE_ADDA:
	243	reg = AFE_ADDA_UL_SRC_CON0;
	244	break;
	245	case MTK_AFE_ADDA6:
	246	reg = AFE_ADDA6_UL_SRC_CON0;
	247	break;
	248	default:
	249	dev_info(afe->dev, "%s(), wrong parameter\n", __func__);
	250	return;
	251	}
	252
	253	mask = (UL_SDM3_LEVEL_CTL \| UL_MODE_3P25M_CH1_CTL \|
	254	UL_MODE_3P25M_CH2_CTL);
	255
	256	/* turn on dmic, ch1, ch2 */
	257	if (dmic)
	258	val = mask;
	259
	260	regmap_update_bits(afe->regmap, reg, mask, val);
	261	}
	262
	263	static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
	264	struct snd_kcontrol *kcontrol,
	265	int event)
	266	{
	267	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
	268	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
	269	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	270	struct mtkaif_param *param = &afe_priv->mtkaif_params;
	271
	272	dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
	273	__func__, w->name, event);
	274
	275	switch (event) {
	276	case SND_SOC_DAPM_PRE_PMU:
	277	mtk_adda_ul_mictype(afe, MTK_AFE_ADDA, param->mtkaif_dmic_on);
	278	break;
	279	case SND_SOC_DAPM_POST_PMD:
	280	/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
	281	usleep_range(125, 135);
	282	break;
	283	default:
	284	break;
	285	}
	286
	287	return 0;
	288	}
	289
	290	static int mtk_adda6_ul_event(struct snd_soc_dapm_widget *w,
	291	struct snd_kcontrol *kcontrol,
	292	int event)
	293	{
	294	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
	295	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
	296	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	297	struct mtkaif_param *param = &afe_priv->mtkaif_params;
	298	unsigned int val;
	299
	300	dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
	301	__func__, w->name, event);
	302
	303	switch (event) {
	304	case SND_SOC_DAPM_PRE_PMU:
	305	mtk_adda_ul_mictype(afe, MTK_AFE_ADDA6, param->mtkaif_dmic_on);
	306
	307	val = (param->mtkaif_adda6_only ?
	308	ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE : 0);
	309
	310	regmap_update_bits(afe->regmap,
	311	AFE_ADDA_MTKAIF_SYNCWORD_CFG,
	312	ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE,
	313	val);
	314	break;
	315	case SND_SOC_DAPM_POST_PMD:
	316	/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
	317	usleep_range(125, 135);
	318	break;
	319	default:
	320	break;
	321	}
	322
	323	return 0;
	324	}
	325
	326	static int mtk_audio_hires_event(struct snd_soc_dapm_widget *w,
	327	struct snd_kcontrol *kcontrol,
	328	int event)
	329	{
	330	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
	331	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
	332	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	333	struct clk *clk = afe_priv->clk[MT8195_CLK_TOP_AUDIO_H_SEL];
	334	struct clk *clk_parent;
	335
	336	dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
	337	__func__, w->name, event);
	338
	339	switch (event) {
	340	case SND_SOC_DAPM_PRE_PMU:
	341	clk_parent = afe_priv->clk[MT8195_CLK_TOP_APLL1];
	342	break;
	343	case SND_SOC_DAPM_POST_PMD:
	344	clk_parent = afe_priv->clk[MT8195_CLK_XTAL_26M];
	345	break;
	346	default:
	347	return 0;
	348	}
	349	mt8195_afe_set_clk_parent(afe, clk, clk_parent);
	350
	351	return 0;
	352	}
	353
	354	static struct mtk_dai_adda_priv get_adda_priv_by_name(struct mtk_base_afe afe,
	355	const char *name)
	356	{
	357	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	358	int dai_id;
	359
	360	if (strstr(name, "aud_adc_hires"))
	361	dai_id = MT8195_AFE_IO_UL_SRC1;
	362	else if (strstr(name, "aud_adda6_adc_hires"))
	363	dai_id = MT8195_AFE_IO_UL_SRC2;
	364	else if (strstr(name, "aud_dac_hires"))
	365	dai_id = MT8195_AFE_IO_DL_SRC;
	366	else
	367	return NULL;
	368
	369	return afe_priv->dai_priv[dai_id];
	370	}
	371
	372	static int mtk_afe_adda_hires_connect(struct snd_soc_dapm_widget *source,
	373	struct snd_soc_dapm_widget *sink)
	374	{
	375	struct snd_soc_dapm_widget *w = source;
	376	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
	377	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
	378	struct mtk_dai_adda_priv *adda_priv;
	379
	380	adda_priv = get_adda_priv_by_name(afe, w->name);
	381
	382	if (!adda_priv) {
	383	dev_info(afe->dev, "adda_priv == NULL");
	384	return 0;
	385	}
	386
	387	return (adda_priv->hires_required) ? 1 : 0;
	388	}
	389
	390	static const struct snd_kcontrol_new mtk_dai_adda_o176_mix[] = {
	391	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN176, 0, 1, 0),
	392	SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN176, 2, 1, 0),
	393	SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN176, 20, 1, 0),
	394	SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN176, 22, 1, 0),
	395	SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN176_2, 6, 1, 0),
	396	};
	397
	398	static const struct snd_kcontrol_new mtk_dai_adda_o177_mix[] = {
	399	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN177, 1, 1, 0),
	400	SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN177, 3, 1, 0),
	401	SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN177, 21, 1, 0),
	402	SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN177, 23, 1, 0),
	403	SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN177_2, 7, 1, 0),
	404	};
	405
	406	static const char * const adda_dlgain_mux_map[] = {
	407	"Bypass", "Connect",
	408	};
	409
	410	static SOC_ENUM_SINGLE_DECL(adda_dlgain_mux_map_enum,
	411	SND_SOC_NOPM, 0,
	412	adda_dlgain_mux_map);
	413
	414	static const struct snd_kcontrol_new adda_dlgain_mux_control =
	415	SOC_DAPM_ENUM("DL_GAIN_MUX", adda_dlgain_mux_map_enum);
	416
	417	static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
	418	SND_SOC_DAPM_MIXER("I168", SND_SOC_NOPM, 0, 0, NULL, 0),
	419	SND_SOC_DAPM_MIXER("I169", SND_SOC_NOPM, 0, 0, NULL, 0),
	420	SND_SOC_DAPM_MIXER("I170", SND_SOC_NOPM, 0, 0, NULL, 0),
	421	SND_SOC_DAPM_MIXER("I171", SND_SOC_NOPM, 0, 0, NULL, 0),
	422
	423	SND_SOC_DAPM_MIXER("O176", SND_SOC_NOPM, 0, 0,
	424	mtk_dai_adda_o176_mix,
	425	ARRAY_SIZE(mtk_dai_adda_o176_mix)),
	426	SND_SOC_DAPM_MIXER("O177", SND_SOC_NOPM, 0, 0,
	427	mtk_dai_adda_o177_mix,
	428	ARRAY_SIZE(mtk_dai_adda_o177_mix)),
	429
	430	SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
	431	AFE_ADDA_UL_DL_CON0,
	432	ADDA_AFE_ON_SHIFT, 0,
	433	NULL,
	434	0),
	435
	436	SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
	437	AFE_ADDA_DL_SRC2_CON0,
	438	DL_2_SRC_ON_TMP_CTRL_PRE_SHIFT, 0,
	439	mtk_adda_dl_event,
	440	SND_SOC_DAPM_POST_PMD),
	441
	442	SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
	443	AFE_ADDA_UL_SRC_CON0,
	444	UL_SRC_ON_TMP_CTL_SHIFT, 0,
	445	mtk_adda_ul_event,
	446	SND_SOC_DAPM_PRE_PMU \| SND_SOC_DAPM_POST_PMD),
	447
	448	SND_SOC_DAPM_SUPPLY_S("ADDA6 Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
	449	AFE_ADDA6_UL_SRC_CON0,
	450	UL_SRC_ON_TMP_CTL_SHIFT, 0,
	451	mtk_adda6_ul_event,
	452	SND_SOC_DAPM_PRE_PMU \| SND_SOC_DAPM_POST_PMD),
	453
	454	SND_SOC_DAPM_SUPPLY_S("AUDIO_HIRES", SUPPLY_SEQ_CLOCK_SEL,
	455	SND_SOC_NOPM,
	456	0, 0,
	457	mtk_audio_hires_event,
	458	SND_SOC_DAPM_PRE_PMU \| SND_SOC_DAPM_POST_PMD),
	459
	460	SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG,
	461	SND_SOC_NOPM,
	462	0, 0,
	463	mtk_adda_mtkaif_cfg_event,
	464	SND_SOC_DAPM_PRE_PMU),
	465
	466	SND_SOC_DAPM_MUX("DL_GAIN_MUX", SND_SOC_NOPM, 0, 0,
	467	&adda_dlgain_mux_control),
	468
	469	SND_SOC_DAPM_PGA("DL_GAIN", AFE_ADDA_DL_SRC2_CON0,
	470	DL_2_GAIN_ON_CTL_PRE_SHIFT, 0, NULL, 0),
	471
	472	SND_SOC_DAPM_INPUT("ADDA_INPUT"),
	473	SND_SOC_DAPM_OUTPUT("ADDA_OUTPUT"),
	474
	475	SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac"),
	476	SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc"),
	477	SND_SOC_DAPM_CLOCK_SUPPLY("aud_adda6_adc"),
	478	SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_hires"),
	479	SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_hires"),
	480	SND_SOC_DAPM_CLOCK_SUPPLY("aud_adda6_adc_hires"),
	481	};
	482
	483	static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
	484	{"ADDA Capture", NULL, "ADDA Enable"},
	485	{"ADDA Capture", NULL, "ADDA Capture Enable"},
	486	{"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"},
	487	{"ADDA Capture", NULL, "aud_adc"},
	488	{"ADDA Capture", NULL, "aud_adc_hires", mtk_afe_adda_hires_connect},
	489	{"aud_adc_hires", NULL, "AUDIO_HIRES"},
	490
	491	{"ADDA6 Capture", NULL, "ADDA Enable"},
	492	{"ADDA6 Capture", NULL, "ADDA6 Capture Enable"},
	493	{"ADDA6 Capture", NULL, "ADDA_MTKAIF_CFG"},
	494	{"ADDA6 Capture", NULL, "aud_adda6_adc"},
	495	{"ADDA6 Capture", NULL, "aud_adda6_adc_hires",
	496	mtk_afe_adda_hires_connect},
	497	{"aud_adda6_adc_hires", NULL, "AUDIO_HIRES"},
	498
	499	{"I168", NULL, "ADDA Capture"},
	500	{"I169", NULL, "ADDA Capture"},
	501	{"I170", NULL, "ADDA6 Capture"},
	502	{"I171", NULL, "ADDA6 Capture"},
	503
	504	{"ADDA Playback", NULL, "ADDA Enable"},
	505	{"ADDA Playback", NULL, "ADDA Playback Enable"},
	506	{"ADDA Playback", NULL, "aud_dac"},
	507	{"ADDA Playback", NULL, "aud_dac_hires", mtk_afe_adda_hires_connect},
	508	{"aud_dac_hires", NULL, "AUDIO_HIRES"},
	509
	510	{"DL_GAIN", NULL, "O176"},
	511	{"DL_GAIN", NULL, "O177"},
	512
	513	{"DL_GAIN_MUX", "Bypass", "O176"},
	514	{"DL_GAIN_MUX", "Bypass", "O177"},
	515	{"DL_GAIN_MUX", "Connect", "DL_GAIN"},
	516
	517	{"ADDA Playback", NULL, "DL_GAIN_MUX"},
	518
	519	{"O176", "I000 Switch", "I000"},
	520	{"O177", "I001 Switch", "I001"},
	521
	522	{"O176", "I002 Switch", "I002"},
	523	{"O177", "I003 Switch", "I003"},
	524
	525	{"O176", "I020 Switch", "I020"},
	526	{"O177", "I021 Switch", "I021"},
	527
	528	{"O176", "I022 Switch", "I022"},
	529	{"O177", "I023 Switch", "I023"},
	530
	531	{"O176", "I070 Switch", "I070"},
	532	{"O177", "I071 Switch", "I071"},
	533
	534	{"ADDA Capture", NULL, "ADDA_INPUT"},
	535	{"ADDA6 Capture", NULL, "ADDA_INPUT"},
	536	{"ADDA_OUTPUT", NULL, "ADDA Playback"},
	537	};
	538
	539	static int mt8195_adda_dl_gain_put(struct snd_kcontrol *kcontrol,
	540	struct snd_ctl_elem_value *ucontrol)
	541	{
	542	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
	543	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
	544	unsigned int reg = AFE_ADDA_DL_SRC2_CON1;
	545	unsigned int mask = DL_2_GAIN_CTL_PRE_MASK;
	546	unsigned int value = (unsigned int)(ucontrol->value.integer.value[0]);
	547
	548	regmap_update_bits(afe->regmap, reg, mask, DL_2_GAIN_CTL_PRE(value));
	549	return 0;
	550	}
	551
	552	static int mt8195_adda_dl_gain_get(struct snd_kcontrol *kcontrol,
	553	struct snd_ctl_elem_value *ucontrol)
	554	{
	555	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
	556	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
	557	unsigned int reg = AFE_ADDA_DL_SRC2_CON1;
	558	unsigned int mask = DL_2_GAIN_CTL_PRE_MASK;
	559	unsigned int value = 0;
	560
	561	regmap_read(afe->regmap, reg, &value);
	562
	563	ucontrol->value.integer.value[0] = ((value & mask) >>
	564	DL_2_GAIN_CTL_PRE_SHIFT);
	565	return 0;
	566	}
	567
	568	static int mt8195_adda6_only_get(struct snd_kcontrol *kcontrol,
	569	struct snd_ctl_elem_value *ucontrol)
	570	{
	571	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
	572	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
	573	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	574	struct mtkaif_param *param = &afe_priv->mtkaif_params;
	575
	576	ucontrol->value.integer.value[0] = param->mtkaif_adda6_only;
	577	return 0;
	578	}
	579
	580	static int mt8195_adda6_only_set(struct snd_kcontrol *kcontrol,
	581	struct snd_ctl_elem_value *ucontrol)
	582	{
	583	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
	584	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
	585	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	586	struct mtkaif_param *param = &afe_priv->mtkaif_params;
	587	int mtkaif_adda6_only;
	588
	589	mtkaif_adda6_only = ucontrol->value.integer.value[0];
	590
	591	dev_info(afe->dev, "%s(), kcontrol name %s, mtkaif_adda6_only %d\n",
	592	__func__, kcontrol->id.name, mtkaif_adda6_only);
	593
	594	param->mtkaif_adda6_only = mtkaif_adda6_only;
	595
	596	return 0;
	597	}
	598
	599	static int mt8195_adda_dmic_get(struct snd_kcontrol *kcontrol,
	600	struct snd_ctl_elem_value *ucontrol)
	601	{
	602	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
	603	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
	604	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	605	struct mtkaif_param *param = &afe_priv->mtkaif_params;
	606
	607	ucontrol->value.integer.value[0] = param->mtkaif_dmic_on;
	608	return 0;
	609	}
	610
	611	static int mt8195_adda_dmic_set(struct snd_kcontrol *kcontrol,
	612	struct snd_ctl_elem_value *ucontrol)
	613	{
	614	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
	615	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
	616	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	617	struct mtkaif_param *param = &afe_priv->mtkaif_params;
	618	int dmic_on;
	619
	620	dmic_on = ucontrol->value.integer.value[0];
	621
	622	dev_dbg(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n",
	623	__func__, kcontrol->id.name, dmic_on);
	624
	625	param->mtkaif_dmic_on = dmic_on;
	626	return 0;
	627	}
	628
	629	static const struct snd_kcontrol_new mtk_dai_adda_controls[] = {
	630	SOC_SINGLE_EXT("ADDA_DL_Gain", SND_SOC_NOPM, 0, 65535, 0,
	631	mt8195_adda_dl_gain_get, mt8195_adda_dl_gain_put),
	632	SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC", 0,
	633	mt8195_adda_dmic_get, mt8195_adda_dmic_set),
	634	SOC_SINGLE_BOOL_EXT("MTKAIF_ADDA6_ONLY", 0,
	635	mt8195_adda6_only_get,
	636	mt8195_adda6_only_set),
	637	};
	638
	639	static int mtk_dai_da_configure(struct mtk_base_afe *afe,
	640	unsigned int rate, int id)
	641	{
	642	unsigned int val = 0;
	643	unsigned int mask = 0;
	644
	645	/* set sampling rate */
	646	mask \|= DL_2_INPUT_MODE_CTL_MASK;
	647	val \|= DL_2_INPUT_MODE_CTL(afe_adda_dl_rate_transform(afe, rate));
	648
	649	/* turn off saturation */
	650	mask \|= DL_2_CH1_SATURATION_EN_CTL;
	651	mask \|= DL_2_CH2_SATURATION_EN_CTL;
	652
	653	/* turn off mute function */
	654	mask \|= DL_2_MUTE_CH1_OFF_CTL_PRE;
	655	mask \|= DL_2_MUTE_CH2_OFF_CTL_PRE;
	656	val \|= DL_2_MUTE_CH1_OFF_CTL_PRE;
	657	val \|= DL_2_MUTE_CH2_OFF_CTL_PRE;
	658
	659	/* set voice input data if input sample rate is 8k or 16k */
	660	mask \|= DL_2_VOICE_MODE_CTL_PRE;
	661	if (rate == 8000 \|\| rate == 16000)
	662	val \|= DL_2_VOICE_MODE_CTL_PRE;
	663
	664	regmap_update_bits(afe->regmap, AFE_ADDA_DL_SRC2_CON0, mask, val);
	665
	666	mask = 0;
	667	val = 0;
	668
	669	/* new 2nd sdm */
	670	mask \|= DL_USE_NEW_2ND_SDM;
	671	val \|= DL_USE_NEW_2ND_SDM;
	672	regmap_update_bits(afe->regmap, AFE_ADDA_DL_SDM_DCCOMP_CON, mask, val);
	673
	674	return 0;
	675	}
	676
	677	static int mtk_dai_ad_configure(struct mtk_base_afe *afe,
	678	unsigned int rate, int id)
	679	{
	680	unsigned int val = 0;
	681	unsigned int mask = 0;
	682
	683	mask \|= UL_VOICE_MODE_CTL_MASK;
	684	val \|= UL_VOICE_MODE_CTL(afe_adda_ul_rate_transform(afe, rate));
	685
	686	switch (id) {
	687	case MT8195_AFE_IO_UL_SRC1:
	688	regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
	689	mask, val);
	690	break;
	691	case MT8195_AFE_IO_UL_SRC2:
	692	regmap_update_bits(afe->regmap, AFE_ADDA6_UL_SRC_CON0,
	693	mask, val);
	694	break;
	695	default:
	696	break;
	697	}
	698	return 0;
	699	}
	700
	701	static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
	702	struct snd_pcm_hw_params *params,
	703	struct snd_soc_dai *dai)
	704	{
	705	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	706	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	707	struct mtk_dai_adda_priv *adda_priv = afe_priv->dai_priv[dai->id];
	708	unsigned int rate = params_rate(params);
	709	int id = dai->id;
	710	int ret = 0;
	711
	712	dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
	713	__func__, id, substream->stream, rate);
	714
	715	if (rate > ADDA_HIRES_THRES)
	716	adda_priv->hires_required = 1;
	717	else
	718	adda_priv->hires_required = 0;
	719
	720	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	721	ret = mtk_dai_da_configure(afe, rate, id);
	722	else
	723	ret = mtk_dai_ad_configure(afe, rate, id);
	724
	725	return ret;
	726	}
	727
	728	static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
	729	.hw_params = mtk_dai_adda_hw_params,
	730	};
	731
	732	/* dai driver */
	733	#define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 \|\
	734	SNDRV_PCM_RATE_96000 \|\
	735	SNDRV_PCM_RATE_192000)
	736
	737	#define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 \|\
	738	SNDRV_PCM_RATE_16000 \|\
	739	SNDRV_PCM_RATE_32000 \|\
	740	SNDRV_PCM_RATE_48000 \|\
	741	SNDRV_PCM_RATE_96000 \|\
	742	SNDRV_PCM_RATE_192000)
	743
	744	#define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE \|\
	745	SNDRV_PCM_FMTBIT_S24_LE \|\
	746	SNDRV_PCM_FMTBIT_S32_LE)
	747
	748	static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
	749	{
	750	.name = "DL_SRC",
	751	.id = MT8195_AFE_IO_DL_SRC,
	752	.playback = {
	753	.stream_name = "ADDA Playback",
	754	.channels_min = 1,
	755	.channels_max = 2,
	756	.rates = MTK_ADDA_PLAYBACK_RATES,
	757	.formats = MTK_ADDA_FORMATS,
	758	},
	759	.ops = &mtk_dai_adda_ops,
	760	},
	761	{
	762	.name = "UL_SRC1",
	763	.id = MT8195_AFE_IO_UL_SRC1,
	764	.capture = {
	765	.stream_name = "ADDA Capture",
	766	.channels_min = 1,
	767	.channels_max = 2,
	768	.rates = MTK_ADDA_CAPTURE_RATES,
	769	.formats = MTK_ADDA_FORMATS,
	770	},
	771	.ops = &mtk_dai_adda_ops,
	772	},
	773	{
	774	.name = "UL_SRC2",
	775	.id = MT8195_AFE_IO_UL_SRC2,
	776	.capture = {
	777	.stream_name = "ADDA6 Capture",
	778	.channels_min = 1,
	779	.channels_max = 2,
	780	.rates = MTK_ADDA_CAPTURE_RATES,
	781	.formats = MTK_ADDA_FORMATS,
	782	},
	783	.ops = &mtk_dai_adda_ops,
	784	},
	785	};
	786
	787	static int init_adda_priv_data(struct mtk_base_afe *afe)
	788	{
	789	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	790	struct mtk_dai_adda_priv *adda_priv;
	791	int adda_dai_list[] = { MT8195_AFE_IO_DL_SRC,
	792	MT8195_AFE_IO_UL_SRC1,
	793	MT8195_AFE_IO_UL_SRC2};
	794	int i;
	795
	796	for (i = 0; i < ARRAY_SIZE(adda_dai_list); i++) {
	797	adda_priv = devm_kzalloc(afe->dev,
	798	sizeof(struct mtk_dai_adda_priv),
	799	GFP_KERNEL);
	800	if (!adda_priv)
	801	return -ENOMEM;
	802
	803	afe_priv->dai_priv[adda_dai_list[i]] = adda_priv;
	804	}
	805
	806	return 0;
	807	}
	808
	809	int mt8195_dai_adda_register(struct mtk_base_afe *afe)
	810	{
	811	struct mtk_base_afe_dai *dai;
	812
	813	dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
	814	if (!dai)
	815	return -ENOMEM;
	816
	817	list_add(&dai->list, &afe->sub_dais);
	818
	819	dai->dai_drivers = mtk_dai_adda_driver;
	820	dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
	821
	822	dai->dapm_widgets = mtk_dai_adda_widgets;
	823	dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
	824	dai->dapm_routes = mtk_dai_adda_routes;
	825	dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
	826	dai->controls = mtk_dai_adda_controls;
	827	dai->num_controls = ARRAY_SIZE(mtk_dai_adda_controls);
	828
	829	return init_adda_priv_data(afe);
	830	}

sound/soc/mediatek/mt8195/mt8195-dai-etdm.c+2639−0

@@ -0,0 +1,2639 @@
	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* MediaTek ALSA SoC Audio DAI eTDM Control
	4	*
	5	* Copyright (c) 2021 MediaTek Inc.
	6	* Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
	7	* Trevor Wu <trevor.wu@mediatek.com>
	8	*/
	9
	10	#include <linux/delay.h>
	11	#include <linux/pm_runtime.h>
	12	#include <linux/regmap.h>
	13	#include <sound/pcm_params.h>
	14	#include "mt8195-afe-clk.h"
	15	#include "mt8195-afe-common.h"
	16	#include "mt8195-reg.h"
	17
	18	#define MT8195_ETDM_MAX_CHANNELS 24
	19	#define MT8195_ETDM_NORMAL_MAX_BCK_RATE 24576000
	20	#define ETDM_TO_DAI_ID(x) ((x) + MT8195_AFE_IO_ETDM_START)
	21	#define ENUM_TO_STR(x) #x
	22
	23	enum {
	24	MTK_DAI_ETDM_FORMAT_I2S = 0,
	25	MTK_DAI_ETDM_FORMAT_LJ,
	26	MTK_DAI_ETDM_FORMAT_RJ,
	27	MTK_DAI_ETDM_FORMAT_EIAJ,
	28	MTK_DAI_ETDM_FORMAT_DSPA,
	29	MTK_DAI_ETDM_FORMAT_DSPB,
	30	};
	31
	32	enum {
	33	MTK_DAI_ETDM_DATA_ONE_PIN = 0,
	34	MTK_DAI_ETDM_DATA_MULTI_PIN,
	35	};
	36
	37	enum {
	38	ETDM_IN,
	39	ETDM_OUT,
	40	};
	41
	42	enum {
	43	ETDM_IN_FROM_PAD,
	44	ETDM_IN_FROM_ETDM_OUT1,
	45	ETDM_IN_FROM_ETDM_OUT2,
	46	};
	47
	48	enum {
	49	ETDM_IN_SLAVE_FROM_PAD,
	50	ETDM_IN_SLAVE_FROM_ETDM_OUT1,
	51	ETDM_IN_SLAVE_FROM_ETDM_OUT2,
	52	};
	53
	54	enum {
	55	ETDM_OUT_SLAVE_FROM_PAD,
	56	ETDM_OUT_SLAVE_FROM_ETDM_IN1,
	57	ETDM_OUT_SLAVE_FROM_ETDM_IN2,
	58	};
	59
	60	enum {
	61	COWORK_ETDM_NONE = 0,
	62	COWORK_ETDM_IN1_M = 2,
	63	COWORK_ETDM_IN1_S = 3,
	64	COWORK_ETDM_IN2_M = 4,
	65	COWORK_ETDM_IN2_S = 5,
	66	COWORK_ETDM_OUT1_M = 10,
	67	COWORK_ETDM_OUT1_S = 11,
	68	COWORK_ETDM_OUT2_M = 12,
	69	COWORK_ETDM_OUT2_S = 13,
	70	COWORK_ETDM_OUT3_M = 14,
	71	COWORK_ETDM_OUT3_S = 15,
	72	};
	73
	74	enum {
	75	ETDM_RELATCH_TIMING_A1A2SYS,
	76	ETDM_RELATCH_TIMING_A3SYS,
	77	ETDM_RELATCH_TIMING_A4SYS,
	78	};
	79
	80	enum {
	81	ETDM_SYNC_NONE,
	82	ETDM_SYNC_FROM_IN1,
	83	ETDM_SYNC_FROM_IN2,
	84	ETDM_SYNC_FROM_OUT1,
	85	ETDM_SYNC_FROM_OUT2,
	86	ETDM_SYNC_FROM_OUT3,
	87	};
	88
	89	struct etdm_con_reg {
	90	unsigned int con0;
	91	unsigned int con1;
	92	unsigned int con2;
	93	unsigned int con3;
	94	unsigned int con4;
	95	unsigned int con5;
	96	};
	97
	98	struct mtk_dai_etdm_rate {
	99	unsigned int rate;
	100	unsigned int reg_value;
	101	};
	102
	103	struct mtk_dai_etdm_priv {
	104	unsigned int clock_mode;
	105	unsigned int data_mode;
	106	bool slave_mode;
	107	bool lrck_inv;
	108	bool bck_inv;
	109	unsigned int format;
	110	unsigned int slots;
	111	unsigned int lrck_width;
	112	unsigned int mclk_freq;
	113	unsigned int mclk_apll;
	114	unsigned int mclk_dir;
	115	int cowork_source_id; //dai id
	116	unsigned int cowork_slv_count;
	117	int cowork_slv_id[MT8195_AFE_IO_ETDM_NUM - 1]; //dai_id
	118	bool in_disable_ch[MT8195_ETDM_MAX_CHANNELS];
	119	unsigned int en_ref_cnt;
	120	};
	121
	122	static const struct mtk_dai_etdm_rate mt8195_etdm_rates[] = {
	123	{ .rate = 8000, .reg_value = 0, },
	124	{ .rate = 12000, .reg_value = 1, },
	125	{ .rate = 16000, .reg_value = 2, },
	126	{ .rate = 24000, .reg_value = 3, },
	127	{ .rate = 32000, .reg_value = 4, },
	128	{ .rate = 48000, .reg_value = 5, },
	129	{ .rate = 96000, .reg_value = 7, },
	130	{ .rate = 192000, .reg_value = 9, },
	131	{ .rate = 384000, .reg_value = 11, },
	132	{ .rate = 11025, .reg_value = 16, },
	133	{ .rate = 22050, .reg_value = 17, },
	134	{ .rate = 44100, .reg_value = 18, },
	135	{ .rate = 88200, .reg_value = 19, },
	136	{ .rate = 176400, .reg_value = 20, },
	137	{ .rate = 352800, .reg_value = 21, },
	138	};
	139
	140	static int get_etdm_fs_timing(unsigned int rate)
	141	{
	142	int i;
	143
	144	for (i = 0; i < ARRAY_SIZE(mt8195_etdm_rates); i++)
	145	if (mt8195_etdm_rates[i].rate == rate)
	146	return mt8195_etdm_rates[i].reg_value;
	147
	148	return -EINVAL;
	149	}
	150
	151	static unsigned int get_etdm_ch_fixup(unsigned int channels)
	152	{
	153	if (channels > 16)
	154	return 24;
	155	else if (channels > 8)
	156	return 16;
	157	else if (channels > 4)
	158	return 8;
	159	else if (channels > 2)
	160	return 4;
	161	else
	162	return 2;
	163	}
	164
	165	static int get_etdm_reg(unsigned int dai_id, struct etdm_con_reg *etdm_reg)
	166	{
	167	switch (dai_id) {
	168	case MT8195_AFE_IO_ETDM1_IN:
	169	etdm_reg->con0 = ETDM_IN1_CON0;
	170	etdm_reg->con1 = ETDM_IN1_CON1;
	171	etdm_reg->con2 = ETDM_IN1_CON2;
	172	etdm_reg->con3 = ETDM_IN1_CON3;
	173	etdm_reg->con4 = ETDM_IN1_CON4;
	174	etdm_reg->con5 = ETDM_IN1_CON5;
	175	break;
	176	case MT8195_AFE_IO_ETDM2_IN:
	177	etdm_reg->con0 = ETDM_IN2_CON0;
	178	etdm_reg->con1 = ETDM_IN2_CON1;
	179	etdm_reg->con2 = ETDM_IN2_CON2;
	180	etdm_reg->con3 = ETDM_IN2_CON3;
	181	etdm_reg->con4 = ETDM_IN2_CON4;
	182	etdm_reg->con5 = ETDM_IN2_CON5;
	183	break;
	184	case MT8195_AFE_IO_ETDM1_OUT:
	185	etdm_reg->con0 = ETDM_OUT1_CON0;
	186	etdm_reg->con1 = ETDM_OUT1_CON1;
	187	etdm_reg->con2 = ETDM_OUT1_CON2;
	188	etdm_reg->con3 = ETDM_OUT1_CON3;
	189	etdm_reg->con4 = ETDM_OUT1_CON4;
	190	etdm_reg->con5 = ETDM_OUT1_CON5;
	191	break;
	192	case MT8195_AFE_IO_ETDM2_OUT:
	193	etdm_reg->con0 = ETDM_OUT2_CON0;
	194	etdm_reg->con1 = ETDM_OUT2_CON1;
	195	etdm_reg->con2 = ETDM_OUT2_CON2;
	196	etdm_reg->con3 = ETDM_OUT2_CON3;
	197	etdm_reg->con4 = ETDM_OUT2_CON4;
	198	etdm_reg->con5 = ETDM_OUT2_CON5;
	199	break;
	200	case MT8195_AFE_IO_ETDM3_OUT:
	201	case MT8195_AFE_IO_DPTX:
	202	etdm_reg->con0 = ETDM_OUT3_CON0;
	203	etdm_reg->con1 = ETDM_OUT3_CON1;
	204	etdm_reg->con2 = ETDM_OUT3_CON2;
	205	etdm_reg->con3 = ETDM_OUT3_CON3;
	206	etdm_reg->con4 = ETDM_OUT3_CON4;
	207	etdm_reg->con5 = ETDM_OUT3_CON5;
	208	break;
	209	default:
	210	return -EINVAL;
	211	}
	212	return 0;
	213	}
	214
	215	static int get_etdm_dir(unsigned int dai_id)
	216	{
	217	switch (dai_id) {
	218	case MT8195_AFE_IO_ETDM1_IN:
	219	case MT8195_AFE_IO_ETDM2_IN:
	220	return ETDM_IN;
	221	case MT8195_AFE_IO_ETDM1_OUT:
	222	case MT8195_AFE_IO_ETDM2_OUT:
	223	case MT8195_AFE_IO_ETDM3_OUT:
	224	return ETDM_OUT;
	225	default:
	226	return -EINVAL;
	227	}
	228	}
	229
	230	static int get_etdm_wlen(unsigned int bitwidth)
	231	{
	232	return bitwidth <= 16 ? 16 : 32;
	233	}
	234
	235	static int is_cowork_mode(struct snd_soc_dai *dai)
	236	{
	237	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	238	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	239	struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id];
	240
	241	return (etdm_data->cowork_slv_count > 0 \|\|
	242	etdm_data->cowork_source_id != COWORK_ETDM_NONE);
	243	}
	244
	245	static int sync_to_dai_id(int source_sel)
	246	{
	247	switch (source_sel) {
	248	case ETDM_SYNC_FROM_IN1:
	249	return MT8195_AFE_IO_ETDM1_IN;
	250	case ETDM_SYNC_FROM_IN2:
	251	return MT8195_AFE_IO_ETDM2_IN;
	252	case ETDM_SYNC_FROM_OUT1:
	253	return MT8195_AFE_IO_ETDM1_OUT;
	254	case ETDM_SYNC_FROM_OUT2:
	255	return MT8195_AFE_IO_ETDM2_OUT;
	256	case ETDM_SYNC_FROM_OUT3:
	257	return MT8195_AFE_IO_ETDM3_OUT;
	258	default:
	259	return 0;
	260	}
	261	}
	262
	263	static int get_etdm_cowork_master_id(struct snd_soc_dai *dai)
	264	{
	265	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	266	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	267	struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id];
	268	int dai_id = etdm_data->cowork_source_id;
	269
	270	if (dai_id == COWORK_ETDM_NONE)
	271	dai_id = dai->id;
	272
	273	return dai_id;
	274	}
	275
	276	static const struct snd_kcontrol_new mtk_dai_etdm_o048_mix[] = {
	277	SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN48, 20, 1, 0),
	278	SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN48, 22, 1, 0),
	279	SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN48_1, 14, 1, 0),
	280	SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN48_2, 6, 1, 0),
	281	};
	282
	283	static const struct snd_kcontrol_new mtk_dai_etdm_o049_mix[] = {
	284	SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN49, 21, 1, 0),
	285	SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN49, 23, 1, 0),
	286	SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN49_1, 15, 1, 0),
	287	SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN49_2, 7, 1, 0),
	288	};
	289
	290	static const struct snd_kcontrol_new mtk_dai_etdm_o050_mix[] = {
	291	SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN50, 24, 1, 0),
	292	SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN50_1, 16, 1, 0),
	293	};
	294
	295	static const struct snd_kcontrol_new mtk_dai_etdm_o051_mix[] = {
	296	SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN51, 25, 1, 0),
	297	SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN51_1, 17, 1, 0),
	298	};
	299
	300	static const struct snd_kcontrol_new mtk_dai_etdm_o052_mix[] = {
	301	SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN52, 26, 1, 0),
	302	SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN52_1, 18, 1, 0),
	303	};
	304
	305	static const struct snd_kcontrol_new mtk_dai_etdm_o053_mix[] = {
	306	SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN53, 27, 1, 0),
	307	SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN53_1, 19, 1, 0),
	308	};
	309
	310	static const struct snd_kcontrol_new mtk_dai_etdm_o054_mix[] = {
	311	SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN54, 28, 1, 0),
	312	SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN54_1, 20, 1, 0),
	313	};
	314
	315	static const struct snd_kcontrol_new mtk_dai_etdm_o055_mix[] = {
	316	SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN55, 29, 1, 0),
	317	SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN55_1, 21, 1, 0),
	318	};
	319
	320	static const struct snd_kcontrol_new mtk_dai_etdm_o056_mix[] = {
	321	SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN56, 30, 1, 0),
	322	SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN56_1, 22, 1, 0),
	323	};
	324
	325	static const struct snd_kcontrol_new mtk_dai_etdm_o057_mix[] = {
	326	SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN57, 31, 1, 0),
	327	SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN57_1, 23, 1, 0),
	328	};
	329
	330	static const struct snd_kcontrol_new mtk_dai_etdm_o058_mix[] = {
	331	SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN58_1, 0, 1, 0),
	332	SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN58_1, 24, 1, 0),
	333	};
	334
	335	static const struct snd_kcontrol_new mtk_dai_etdm_o059_mix[] = {
	336	SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN59_1, 1, 1, 0),
	337	SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN59_1, 25, 1, 0),
	338	};
	339
	340	static const struct snd_kcontrol_new mtk_dai_etdm_o060_mix[] = {
	341	SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN60_1, 2, 1, 0),
	342	SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN60_1, 26, 1, 0),
	343	};
	344
	345	static const struct snd_kcontrol_new mtk_dai_etdm_o061_mix[] = {
	346	SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN61_1, 3, 1, 0),
	347	SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN61_1, 27, 1, 0),
	348	};
	349
	350	static const struct snd_kcontrol_new mtk_dai_etdm_o062_mix[] = {
	351	SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN62_1, 4, 1, 0),
	352	SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN62_1, 28, 1, 0),
	353	};
	354
	355	static const struct snd_kcontrol_new mtk_dai_etdm_o063_mix[] = {
	356	SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN63_1, 5, 1, 0),
	357	SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN63_1, 29, 1, 0),
	358	};
	359
	360	static const struct snd_kcontrol_new mtk_dai_etdm_o064_mix[] = {
	361	SOC_DAPM_SINGLE_AUTODISABLE("I038 Switch", AFE_CONN64_1, 6, 1, 0),
	362	SOC_DAPM_SINGLE_AUTODISABLE("I062 Switch", AFE_CONN64_1, 30, 1, 0),
	363	};
	364
	365	static const struct snd_kcontrol_new mtk_dai_etdm_o065_mix[] = {
	366	SOC_DAPM_SINGLE_AUTODISABLE("I039 Switch", AFE_CONN65_1, 7, 1, 0),
	367	SOC_DAPM_SINGLE_AUTODISABLE("I063 Switch", AFE_CONN65_1, 31, 1, 0),
	368	};
	369
	370	static const struct snd_kcontrol_new mtk_dai_etdm_o066_mix[] = {
	371	SOC_DAPM_SINGLE_AUTODISABLE("I040 Switch", AFE_CONN66_1, 8, 1, 0),
	372	SOC_DAPM_SINGLE_AUTODISABLE("I064 Switch", AFE_CONN66_2, 0, 1, 0),
	373	};
	374
	375	static const struct snd_kcontrol_new mtk_dai_etdm_o067_mix[] = {
	376	SOC_DAPM_SINGLE_AUTODISABLE("I041 Switch", AFE_CONN67_1, 9, 1, 0),
	377	SOC_DAPM_SINGLE_AUTODISABLE("I065 Switch", AFE_CONN67_2, 1, 1, 0),
	378	};
	379
	380	static const struct snd_kcontrol_new mtk_dai_etdm_o068_mix[] = {
	381	SOC_DAPM_SINGLE_AUTODISABLE("I042 Switch", AFE_CONN68_1, 10, 1, 0),
	382	SOC_DAPM_SINGLE_AUTODISABLE("I066 Switch", AFE_CONN68_2, 2, 1, 0),
	383	};
	384
	385	static const struct snd_kcontrol_new mtk_dai_etdm_o069_mix[] = {
	386	SOC_DAPM_SINGLE_AUTODISABLE("I043 Switch", AFE_CONN69_1, 11, 1, 0),
	387	SOC_DAPM_SINGLE_AUTODISABLE("I067 Switch", AFE_CONN69_2, 3, 1, 0),
	388	};
	389
	390	static const struct snd_kcontrol_new mtk_dai_etdm_o070_mix[] = {
	391	SOC_DAPM_SINGLE_AUTODISABLE("I044 Switch", AFE_CONN70_1, 12, 1, 0),
	392	SOC_DAPM_SINGLE_AUTODISABLE("I068 Switch", AFE_CONN70_2, 4, 1, 0),
	393	};
	394
	395	static const struct snd_kcontrol_new mtk_dai_etdm_o071_mix[] = {
	396	SOC_DAPM_SINGLE_AUTODISABLE("I045 Switch", AFE_CONN71_1, 13, 1, 0),
	397	SOC_DAPM_SINGLE_AUTODISABLE("I069 Switch", AFE_CONN71_2, 5, 1, 0),
	398	};
	399
	400	static const struct snd_kcontrol_new mtk_dai_etdm_o072_mix[] = {
	401	SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN72, 20, 1, 0),
	402	SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN72, 22, 1, 0),
	403	SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN72_1, 14, 1, 0),
	404	SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN72_2, 6, 1, 0),
	405	};
	406
	407	static const struct snd_kcontrol_new mtk_dai_etdm_o073_mix[] = {
	408	SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN73, 21, 1, 0),
	409	SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN73, 23, 1, 0),
	410	SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN73_1, 15, 1, 0),
	411	SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN73_2, 7, 1, 0),
	412	};
	413
	414	static const struct snd_kcontrol_new mtk_dai_etdm_o074_mix[] = {
	415	SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN74, 24, 1, 0),
	416	SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN74_1, 16, 1, 0),
	417	};
	418
	419	static const struct snd_kcontrol_new mtk_dai_etdm_o075_mix[] = {
	420	SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN75, 25, 1, 0),
	421	SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN75_1, 17, 1, 0),
	422	};
	423
	424	static const struct snd_kcontrol_new mtk_dai_etdm_o076_mix[] = {
	425	SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN76, 26, 1, 0),
	426	SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN76_1, 18, 1, 0),
	427	};
	428
	429	static const struct snd_kcontrol_new mtk_dai_etdm_o077_mix[] = {
	430	SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN77, 27, 1, 0),
	431	SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN77_1, 19, 1, 0),
	432	};
	433
	434	static const struct snd_kcontrol_new mtk_dai_etdm_o078_mix[] = {
	435	SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN78, 28, 1, 0),
	436	SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN78_1, 20, 1, 0),
	437	};
	438
	439	static const struct snd_kcontrol_new mtk_dai_etdm_o079_mix[] = {
	440	SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN79, 29, 1, 0),
	441	SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN79_1, 21, 1, 0),
	442	};
	443
	444	static const struct snd_kcontrol_new mtk_dai_etdm_o080_mix[] = {
	445	SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN80, 30, 1, 0),
	446	SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN80_1, 22, 1, 0),
	447	};
	448
	449	static const struct snd_kcontrol_new mtk_dai_etdm_o081_mix[] = {
	450	SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN81, 31, 1, 0),
	451	SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN81_1, 23, 1, 0),
	452	};
	453
	454	static const struct snd_kcontrol_new mtk_dai_etdm_o082_mix[] = {
	455	SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN82_1, 0, 1, 0),
	456	SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN82_1, 24, 1, 0),
	457	};
	458
	459	static const struct snd_kcontrol_new mtk_dai_etdm_o083_mix[] = {
	460	SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN83_1, 1, 1, 0),
	461	SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN83_1, 25, 1, 0),
	462	};
	463
	464	static const struct snd_kcontrol_new mtk_dai_etdm_o084_mix[] = {
	465	SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN84_1, 2, 1, 0),
	466	SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN84_1, 26, 1, 0),
	467	};
	468
	469	static const struct snd_kcontrol_new mtk_dai_etdm_o085_mix[] = {
	470	SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN85_1, 3, 1, 0),
	471	SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN85_1, 27, 1, 0),
	472	};
	473
	474	static const struct snd_kcontrol_new mtk_dai_etdm_o086_mix[] = {
	475	SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN86_1, 4, 1, 0),
	476	SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN86_1, 28, 1, 0),
	477	};
	478
	479	static const struct snd_kcontrol_new mtk_dai_etdm_o087_mix[] = {
	480	SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN87_1, 5, 1, 0),
	481	SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN87_1, 29, 1, 0),
	482	};
	483
	484	static const struct snd_kcontrol_new mtk_dai_etdm_o088_mix[] = {
	485	SOC_DAPM_SINGLE_AUTODISABLE("I038 Switch", AFE_CONN88_1, 6, 1, 0),
	486	SOC_DAPM_SINGLE_AUTODISABLE("I062 Switch", AFE_CONN88_1, 30, 1, 0),
	487	};
	488
	489	static const struct snd_kcontrol_new mtk_dai_etdm_o089_mix[] = {
	490	SOC_DAPM_SINGLE_AUTODISABLE("I039 Switch", AFE_CONN89_1, 7, 1, 0),
	491	SOC_DAPM_SINGLE_AUTODISABLE("I063 Switch", AFE_CONN89_1, 31, 1, 0),
	492	};
	493
	494	static const struct snd_kcontrol_new mtk_dai_etdm_o090_mix[] = {
	495	SOC_DAPM_SINGLE_AUTODISABLE("I040 Switch", AFE_CONN90_1, 8, 1, 0),
	496	SOC_DAPM_SINGLE_AUTODISABLE("I064 Switch", AFE_CONN90_2, 0, 1, 0),
	497	};
	498
	499	static const struct snd_kcontrol_new mtk_dai_etdm_o091_mix[] = {
	500	SOC_DAPM_SINGLE_AUTODISABLE("I041 Switch", AFE_CONN91_1, 9, 1, 0),
	501	SOC_DAPM_SINGLE_AUTODISABLE("I065 Switch", AFE_CONN91_2, 1, 1, 0),
	502	};
	503
	504	static const struct snd_kcontrol_new mtk_dai_etdm_o092_mix[] = {
	505	SOC_DAPM_SINGLE_AUTODISABLE("I042 Switch", AFE_CONN92_1, 10, 1, 0),
	506	SOC_DAPM_SINGLE_AUTODISABLE("I066 Switch", AFE_CONN92_2, 2, 1, 0),
	507	};
	508
	509	static const struct snd_kcontrol_new mtk_dai_etdm_o093_mix[] = {
	510	SOC_DAPM_SINGLE_AUTODISABLE("I043 Switch", AFE_CONN93_1, 11, 1, 0),
	511	SOC_DAPM_SINGLE_AUTODISABLE("I067 Switch", AFE_CONN93_2, 3, 1, 0),
	512	};
	513
	514	static const struct snd_kcontrol_new mtk_dai_etdm_o094_mix[] = {
	515	SOC_DAPM_SINGLE_AUTODISABLE("I044 Switch", AFE_CONN94_1, 12, 1, 0),
	516	SOC_DAPM_SINGLE_AUTODISABLE("I068 Switch", AFE_CONN94_2, 4, 1, 0),
	517	};
	518
	519	static const struct snd_kcontrol_new mtk_dai_etdm_o095_mix[] = {
	520	SOC_DAPM_SINGLE_AUTODISABLE("I045 Switch", AFE_CONN95_1, 13, 1, 0),
	521	SOC_DAPM_SINGLE_AUTODISABLE("I069 Switch", AFE_CONN95_2, 5, 1, 0),
	522	};
	523
	524	static const char * const mt8195_etdm_clk_src_sel_text[] = {
	525	"26m",
	526	"a1sys_a2sys",
	527	"a3sys",
	528	"a4sys",
	529	};
	530
	531	static SOC_ENUM_SINGLE_EXT_DECL(etdmout_clk_src_enum,
	532	mt8195_etdm_clk_src_sel_text);
	533
	534	static const char * const hdmitx_dptx_mux_map[] = {
	535	"Disconnect", "Connect",
	536	};
	537
	538	static int hdmitx_dptx_mux_map_value[] = {
	539	0, 1,
	540	};
	541
	542	/* HDMI_OUT_MUX */
	543	static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(hdmi_out_mux_map_enum,
	544	SND_SOC_NOPM,
	545	0,
	546	1,
	547	hdmitx_dptx_mux_map,
	548	hdmitx_dptx_mux_map_value);
	549
	550	static const struct snd_kcontrol_new hdmi_out_mux_control =
	551	SOC_DAPM_ENUM("HDMI_OUT_MUX", hdmi_out_mux_map_enum);
	552
	553	/* DPTX_OUT_MUX */
	554	static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(dptx_out_mux_map_enum,
	555	SND_SOC_NOPM,
	556	0,
	557	1,
	558	hdmitx_dptx_mux_map,
	559	hdmitx_dptx_mux_map_value);
	560
	561	static const struct snd_kcontrol_new dptx_out_mux_control =
	562	SOC_DAPM_ENUM("DPTX_OUT_MUX", dptx_out_mux_map_enum);
	563
	564	/* HDMI_CH0_MUX ~ HDMI_CH7_MUX */
	565	static const char *const afe_conn_hdmi_mux_map[] = {
	566	"CH0", "CH1", "CH2", "CH3", "CH4", "CH5", "CH6", "CH7",
	567	};
	568
	569	static int afe_conn_hdmi_mux_map_value[] = {
	570	0, 1, 2, 3, 4, 5, 6, 7,
	571	};
	572
	573	static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum,
	574	AFE_TDMOUT_CONN0,
	575	0,
	576	0xf,
	577	afe_conn_hdmi_mux_map,
	578	afe_conn_hdmi_mux_map_value);
	579
	580	static const struct snd_kcontrol_new hdmi_ch0_mux_control =
	581	SOC_DAPM_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum);
	582
	583	static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum,
	584	AFE_TDMOUT_CONN0,
	585	4,
	586	0xf,
	587	afe_conn_hdmi_mux_map,
	588	afe_conn_hdmi_mux_map_value);
	589
	590	static const struct snd_kcontrol_new hdmi_ch1_mux_control =
	591	SOC_DAPM_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum);
	592
	593	static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum,
	594	AFE_TDMOUT_CONN0,
	595	8,
	596	0xf,
	597	afe_conn_hdmi_mux_map,
	598	afe_conn_hdmi_mux_map_value);
	599
	600	static const struct snd_kcontrol_new hdmi_ch2_mux_control =
	601	SOC_DAPM_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum);
	602
	603	static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum,
	604	AFE_TDMOUT_CONN0,
	605	12,
	606	0xf,
	607	afe_conn_hdmi_mux_map,
	608	afe_conn_hdmi_mux_map_value);
	609
	610	static const struct snd_kcontrol_new hdmi_ch3_mux_control =
	611	SOC_DAPM_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum);
	612
	613	static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum,
	614	AFE_TDMOUT_CONN0,
	615	16,
	616	0xf,
	617	afe_conn_hdmi_mux_map,
	618	afe_conn_hdmi_mux_map_value);
	619
	620	static const struct snd_kcontrol_new hdmi_ch4_mux_control =
	621	SOC_DAPM_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum);
	622
	623	static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum,
	624	AFE_TDMOUT_CONN0,
	625	20,
	626	0xf,
	627	afe_conn_hdmi_mux_map,
	628	afe_conn_hdmi_mux_map_value);
	629
	630	static const struct snd_kcontrol_new hdmi_ch5_mux_control =
	631	SOC_DAPM_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum);
	632
	633	static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum,
	634	AFE_TDMOUT_CONN0,
	635	24,
	636	0xf,
	637	afe_conn_hdmi_mux_map,
	638	afe_conn_hdmi_mux_map_value);
	639
	640	static const struct snd_kcontrol_new hdmi_ch6_mux_control =
	641	SOC_DAPM_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum);
	642
	643	static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum,
	644	AFE_TDMOUT_CONN0,
	645	28,
	646	0xf,
	647	afe_conn_hdmi_mux_map,
	648	afe_conn_hdmi_mux_map_value);
	649
	650	static const struct snd_kcontrol_new hdmi_ch7_mux_control =
	651	SOC_DAPM_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum);
	652
	653	static int mt8195_etdm_clk_src_sel_put(struct snd_kcontrol *kcontrol,
	654	struct snd_ctl_elem_value *ucontrol)
	655	{
	656	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
	657	struct soc_enum e = (struct soc_enum )kcontrol->private_value;
	658	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
	659	unsigned int source = ucontrol->value.enumerated.item[0];
	660	unsigned int val;
	661	unsigned int mask;
	662	unsigned int reg;
	663
	664	if (source >= e->items)
	665	return -EINVAL;
	666
	667	reg = 0;
	668	if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) {
	669	reg = ETDM_OUT1_CON4;
	670	mask = ETDM_OUT_CON4_CLOCK_MASK;
	671	val = ETDM_OUT_CON4_CLOCK(source);
	672	} else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) {
	673	reg = ETDM_OUT2_CON4;
	674	mask = ETDM_OUT_CON4_CLOCK_MASK;
	675	val = ETDM_OUT_CON4_CLOCK(source);
	676	} else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) {
	677	reg = ETDM_OUT3_CON4;
	678	mask = ETDM_OUT_CON4_CLOCK_MASK;
	679	val = ETDM_OUT_CON4_CLOCK(source);
	680	} else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) {
	681	reg = ETDM_IN1_CON2;
	682	mask = ETDM_IN_CON2_CLOCK_MASK;
	683	val = ETDM_IN_CON2_CLOCK(source);
	684	} else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) {
	685	reg = ETDM_IN2_CON2;
	686	mask = ETDM_IN_CON2_CLOCK_MASK;
	687	val = ETDM_IN_CON2_CLOCK(source);
	688	}
	689
	690	if (reg)
	691	regmap_update_bits(afe->regmap, reg, mask, val);
	692
	693	return 0;
	694	}
	695
	696	static int mt8195_etdm_clk_src_sel_get(struct snd_kcontrol *kcontrol,
	697	struct snd_ctl_elem_value *ucontrol)
	698	{
	699	struct snd_soc_component *component =
	700	snd_soc_kcontrol_component(kcontrol);
	701	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
	702	unsigned int value = 0;
	703	unsigned int reg = 0;
	704	unsigned int mask = 0;
	705	unsigned int shift = 0;
	706
	707	if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) {
	708	reg = ETDM_OUT1_CON4;
	709	mask = ETDM_OUT_CON4_CLOCK_MASK;
	710	shift = ETDM_OUT_CON4_CLOCK_SHIFT;
	711	} else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) {
	712	reg = ETDM_OUT2_CON4;
	713	mask = ETDM_OUT_CON4_CLOCK_MASK;
	714	shift = ETDM_OUT_CON4_CLOCK_SHIFT;
	715	} else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) {
	716	reg = ETDM_OUT3_CON4;
	717	mask = ETDM_OUT_CON4_CLOCK_MASK;
	718	shift = ETDM_OUT_CON4_CLOCK_SHIFT;
	719	} else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) {
	720	reg = ETDM_IN1_CON2;
	721	mask = ETDM_IN_CON2_CLOCK_MASK;
	722	shift = ETDM_IN_CON2_CLOCK_SHIFT;
	723	} else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) {
	724	reg = ETDM_IN2_CON2;
	725	mask = ETDM_IN_CON2_CLOCK_MASK;
	726	shift = ETDM_IN_CON2_CLOCK_SHIFT;
	727	}
	728
	729	if (reg)
	730	regmap_read(afe->regmap, reg, &value);
	731
	732	value &= mask;
	733	value >>= shift;
	734	ucontrol->value.enumerated.item[0] = value;
	735	return 0;
	736	}
	737
	738	static const struct snd_kcontrol_new mtk_dai_etdm_controls[] = {
	739	SOC_ENUM_EXT("ETDM_OUT1_Clock_Source",
	740	etdmout_clk_src_enum,
	741	mt8195_etdm_clk_src_sel_get,
	742	mt8195_etdm_clk_src_sel_put),
	743	SOC_ENUM_EXT("ETDM_OUT2_Clock_Source",
	744	etdmout_clk_src_enum,
	745	mt8195_etdm_clk_src_sel_get,
	746	mt8195_etdm_clk_src_sel_put),
	747	SOC_ENUM_EXT("ETDM_OUT3_Clock_Source",
	748	etdmout_clk_src_enum,
	749	mt8195_etdm_clk_src_sel_get,
	750	mt8195_etdm_clk_src_sel_put),
	751	SOC_ENUM_EXT("ETDM_IN1_Clock_Source",
	752	etdmout_clk_src_enum,
	753	mt8195_etdm_clk_src_sel_get,
	754	mt8195_etdm_clk_src_sel_put),
	755	SOC_ENUM_EXT("ETDM_IN2_Clock_Source",
	756	etdmout_clk_src_enum,
	757	mt8195_etdm_clk_src_sel_get,
	758	mt8195_etdm_clk_src_sel_put),
	759	};
	760
	761	static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = {
	762	/* eTDM_IN2 */
	763	SND_SOC_DAPM_MIXER("I012", SND_SOC_NOPM, 0, 0, NULL, 0),
	764	SND_SOC_DAPM_MIXER("I013", SND_SOC_NOPM, 0, 0, NULL, 0),
	765	SND_SOC_DAPM_MIXER("I014", SND_SOC_NOPM, 0, 0, NULL, 0),
	766	SND_SOC_DAPM_MIXER("I015", SND_SOC_NOPM, 0, 0, NULL, 0),
	767	SND_SOC_DAPM_MIXER("I016", SND_SOC_NOPM, 0, 0, NULL, 0),
	768	SND_SOC_DAPM_MIXER("I017", SND_SOC_NOPM, 0, 0, NULL, 0),
	769	SND_SOC_DAPM_MIXER("I018", SND_SOC_NOPM, 0, 0, NULL, 0),
	770	SND_SOC_DAPM_MIXER("I019", SND_SOC_NOPM, 0, 0, NULL, 0),
	771
	772	/* eTDM_IN1 */
	773	SND_SOC_DAPM_MIXER("I072", SND_SOC_NOPM, 0, 0, NULL, 0),
	774	SND_SOC_DAPM_MIXER("I073", SND_SOC_NOPM, 0, 0, NULL, 0),
	775	SND_SOC_DAPM_MIXER("I074", SND_SOC_NOPM, 0, 0, NULL, 0),
	776	SND_SOC_DAPM_MIXER("I075", SND_SOC_NOPM, 0, 0, NULL, 0),
	777	SND_SOC_DAPM_MIXER("I076", SND_SOC_NOPM, 0, 0, NULL, 0),
	778	SND_SOC_DAPM_MIXER("I077", SND_SOC_NOPM, 0, 0, NULL, 0),
	779	SND_SOC_DAPM_MIXER("I078", SND_SOC_NOPM, 0, 0, NULL, 0),
	780	SND_SOC_DAPM_MIXER("I079", SND_SOC_NOPM, 0, 0, NULL, 0),
	781	SND_SOC_DAPM_MIXER("I080", SND_SOC_NOPM, 0, 0, NULL, 0),
	782	SND_SOC_DAPM_MIXER("I081", SND_SOC_NOPM, 0, 0, NULL, 0),
	783	SND_SOC_DAPM_MIXER("I082", SND_SOC_NOPM, 0, 0, NULL, 0),
	784	SND_SOC_DAPM_MIXER("I083", SND_SOC_NOPM, 0, 0, NULL, 0),
	785	SND_SOC_DAPM_MIXER("I084", SND_SOC_NOPM, 0, 0, NULL, 0),
	786	SND_SOC_DAPM_MIXER("I085", SND_SOC_NOPM, 0, 0, NULL, 0),
	787	SND_SOC_DAPM_MIXER("I086", SND_SOC_NOPM, 0, 0, NULL, 0),
	788	SND_SOC_DAPM_MIXER("I087", SND_SOC_NOPM, 0, 0, NULL, 0),
	789	SND_SOC_DAPM_MIXER("I088", SND_SOC_NOPM, 0, 0, NULL, 0),
	790	SND_SOC_DAPM_MIXER("I089", SND_SOC_NOPM, 0, 0, NULL, 0),
	791	SND_SOC_DAPM_MIXER("I090", SND_SOC_NOPM, 0, 0, NULL, 0),
	792	SND_SOC_DAPM_MIXER("I091", SND_SOC_NOPM, 0, 0, NULL, 0),
	793	SND_SOC_DAPM_MIXER("I092", SND_SOC_NOPM, 0, 0, NULL, 0),
	794	SND_SOC_DAPM_MIXER("I093", SND_SOC_NOPM, 0, 0, NULL, 0),
	795	SND_SOC_DAPM_MIXER("I094", SND_SOC_NOPM, 0, 0, NULL, 0),
	796	SND_SOC_DAPM_MIXER("I095", SND_SOC_NOPM, 0, 0, NULL, 0),
	797
	798	/* eTDM_OUT2 */
	799	SND_SOC_DAPM_MIXER("O048", SND_SOC_NOPM, 0, 0,
	800	mtk_dai_etdm_o048_mix,
	801	ARRAY_SIZE(mtk_dai_etdm_o048_mix)),
	802	SND_SOC_DAPM_MIXER("O049", SND_SOC_NOPM, 0, 0,
	803	mtk_dai_etdm_o049_mix,
	804	ARRAY_SIZE(mtk_dai_etdm_o049_mix)),
	805	SND_SOC_DAPM_MIXER("O050", SND_SOC_NOPM, 0, 0,
	806	mtk_dai_etdm_o050_mix,
	807	ARRAY_SIZE(mtk_dai_etdm_o050_mix)),
	808	SND_SOC_DAPM_MIXER("O051", SND_SOC_NOPM, 0, 0,
	809	mtk_dai_etdm_o051_mix,
	810	ARRAY_SIZE(mtk_dai_etdm_o051_mix)),
	811	SND_SOC_DAPM_MIXER("O052", SND_SOC_NOPM, 0, 0,
	812	mtk_dai_etdm_o052_mix,
	813	ARRAY_SIZE(mtk_dai_etdm_o052_mix)),
	814	SND_SOC_DAPM_MIXER("O053", SND_SOC_NOPM, 0, 0,
	815	mtk_dai_etdm_o053_mix,
	816	ARRAY_SIZE(mtk_dai_etdm_o053_mix)),
	817	SND_SOC_DAPM_MIXER("O054", SND_SOC_NOPM, 0, 0,
	818	mtk_dai_etdm_o054_mix,
	819	ARRAY_SIZE(mtk_dai_etdm_o054_mix)),
	820	SND_SOC_DAPM_MIXER("O055", SND_SOC_NOPM, 0, 0,
	821	mtk_dai_etdm_o055_mix,
	822	ARRAY_SIZE(mtk_dai_etdm_o055_mix)),
	823	SND_SOC_DAPM_MIXER("O056", SND_SOC_NOPM, 0, 0,
	824	mtk_dai_etdm_o056_mix,
	825	ARRAY_SIZE(mtk_dai_etdm_o056_mix)),
	826	SND_SOC_DAPM_MIXER("O057", SND_SOC_NOPM, 0, 0,
	827	mtk_dai_etdm_o057_mix,
	828	ARRAY_SIZE(mtk_dai_etdm_o057_mix)),
	829	SND_SOC_DAPM_MIXER("O058", SND_SOC_NOPM, 0, 0,
	830	mtk_dai_etdm_o058_mix,
	831	ARRAY_SIZE(mtk_dai_etdm_o058_mix)),
	832	SND_SOC_DAPM_MIXER("O059", SND_SOC_NOPM, 0, 0,
	833	mtk_dai_etdm_o059_mix,
	834	ARRAY_SIZE(mtk_dai_etdm_o059_mix)),
	835	SND_SOC_DAPM_MIXER("O060", SND_SOC_NOPM, 0, 0,
	836	mtk_dai_etdm_o060_mix,
	837	ARRAY_SIZE(mtk_dai_etdm_o060_mix)),
	838	SND_SOC_DAPM_MIXER("O061", SND_SOC_NOPM, 0, 0,
	839	mtk_dai_etdm_o061_mix,
	840	ARRAY_SIZE(mtk_dai_etdm_o061_mix)),
	841	SND_SOC_DAPM_MIXER("O062", SND_SOC_NOPM, 0, 0,
	842	mtk_dai_etdm_o062_mix,
	843	ARRAY_SIZE(mtk_dai_etdm_o062_mix)),
	844	SND_SOC_DAPM_MIXER("O063", SND_SOC_NOPM, 0, 0,
	845	mtk_dai_etdm_o063_mix,
	846	ARRAY_SIZE(mtk_dai_etdm_o063_mix)),
	847	SND_SOC_DAPM_MIXER("O064", SND_SOC_NOPM, 0, 0,
	848	mtk_dai_etdm_o064_mix,
	849	ARRAY_SIZE(mtk_dai_etdm_o064_mix)),
	850	SND_SOC_DAPM_MIXER("O065", SND_SOC_NOPM, 0, 0,
	851	mtk_dai_etdm_o065_mix,
	852	ARRAY_SIZE(mtk_dai_etdm_o065_mix)),
	853	SND_SOC_DAPM_MIXER("O066", SND_SOC_NOPM, 0, 0,
	854	mtk_dai_etdm_o066_mix,
	855	ARRAY_SIZE(mtk_dai_etdm_o066_mix)),
	856	SND_SOC_DAPM_MIXER("O067", SND_SOC_NOPM, 0, 0,
	857	mtk_dai_etdm_o067_mix,
	858	ARRAY_SIZE(mtk_dai_etdm_o067_mix)),
	859	SND_SOC_DAPM_MIXER("O068", SND_SOC_NOPM, 0, 0,
	860	mtk_dai_etdm_o068_mix,
	861	ARRAY_SIZE(mtk_dai_etdm_o068_mix)),
	862	SND_SOC_DAPM_MIXER("O069", SND_SOC_NOPM, 0, 0,
	863	mtk_dai_etdm_o069_mix,
	864	ARRAY_SIZE(mtk_dai_etdm_o069_mix)),
	865	SND_SOC_DAPM_MIXER("O070", SND_SOC_NOPM, 0, 0,
	866	mtk_dai_etdm_o070_mix,
	867	ARRAY_SIZE(mtk_dai_etdm_o070_mix)),
	868	SND_SOC_DAPM_MIXER("O071", SND_SOC_NOPM, 0, 0,
	869	mtk_dai_etdm_o071_mix,
	870	ARRAY_SIZE(mtk_dai_etdm_o071_mix)),
	871
	872	/* eTDM_OUT1 */
	873	SND_SOC_DAPM_MIXER("O072", SND_SOC_NOPM, 0, 0,
	874	mtk_dai_etdm_o072_mix,
	875	ARRAY_SIZE(mtk_dai_etdm_o072_mix)),
	876	SND_SOC_DAPM_MIXER("O073", SND_SOC_NOPM, 0, 0,
	877	mtk_dai_etdm_o073_mix,
	878	ARRAY_SIZE(mtk_dai_etdm_o073_mix)),
	879	SND_SOC_DAPM_MIXER("O074", SND_SOC_NOPM, 0, 0,
	880	mtk_dai_etdm_o074_mix,
	881	ARRAY_SIZE(mtk_dai_etdm_o074_mix)),
	882	SND_SOC_DAPM_MIXER("O075", SND_SOC_NOPM, 0, 0,
	883	mtk_dai_etdm_o075_mix,
	884	ARRAY_SIZE(mtk_dai_etdm_o075_mix)),
	885	SND_SOC_DAPM_MIXER("O076", SND_SOC_NOPM, 0, 0,
	886	mtk_dai_etdm_o076_mix,
	887	ARRAY_SIZE(mtk_dai_etdm_o076_mix)),
	888	SND_SOC_DAPM_MIXER("O077", SND_SOC_NOPM, 0, 0,
	889	mtk_dai_etdm_o077_mix,
	890	ARRAY_SIZE(mtk_dai_etdm_o077_mix)),
	891	SND_SOC_DAPM_MIXER("O078", SND_SOC_NOPM, 0, 0,
	892	mtk_dai_etdm_o078_mix,
	893	ARRAY_SIZE(mtk_dai_etdm_o078_mix)),
	894	SND_SOC_DAPM_MIXER("O079", SND_SOC_NOPM, 0, 0,
	895	mtk_dai_etdm_o079_mix,
	896	ARRAY_SIZE(mtk_dai_etdm_o079_mix)),
	897	SND_SOC_DAPM_MIXER("O080", SND_SOC_NOPM, 0, 0,
	898	mtk_dai_etdm_o080_mix,
	899	ARRAY_SIZE(mtk_dai_etdm_o080_mix)),
	900	SND_SOC_DAPM_MIXER("O081", SND_SOC_NOPM, 0, 0,
	901	mtk_dai_etdm_o081_mix,
	902	ARRAY_SIZE(mtk_dai_etdm_o081_mix)),
	903	SND_SOC_DAPM_MIXER("O082", SND_SOC_NOPM, 0, 0,
	904	mtk_dai_etdm_o082_mix,
	905	ARRAY_SIZE(mtk_dai_etdm_o082_mix)),
	906	SND_SOC_DAPM_MIXER("O083", SND_SOC_NOPM, 0, 0,
	907	mtk_dai_etdm_o083_mix,
	908	ARRAY_SIZE(mtk_dai_etdm_o083_mix)),
	909	SND_SOC_DAPM_MIXER("O084", SND_SOC_NOPM, 0, 0,
	910	mtk_dai_etdm_o084_mix,
	911	ARRAY_SIZE(mtk_dai_etdm_o084_mix)),
	912	SND_SOC_DAPM_MIXER("O085", SND_SOC_NOPM, 0, 0,
	913	mtk_dai_etdm_o085_mix,
	914	ARRAY_SIZE(mtk_dai_etdm_o085_mix)),
	915	SND_SOC_DAPM_MIXER("O086", SND_SOC_NOPM, 0, 0,
	916	mtk_dai_etdm_o086_mix,
	917	ARRAY_SIZE(mtk_dai_etdm_o086_mix)),
	918	SND_SOC_DAPM_MIXER("O087", SND_SOC_NOPM, 0, 0,
	919	mtk_dai_etdm_o087_mix,
	920	ARRAY_SIZE(mtk_dai_etdm_o087_mix)),
	921	SND_SOC_DAPM_MIXER("O088", SND_SOC_NOPM, 0, 0,
	922	mtk_dai_etdm_o088_mix,
	923	ARRAY_SIZE(mtk_dai_etdm_o088_mix)),
	924	SND_SOC_DAPM_MIXER("O089", SND_SOC_NOPM, 0, 0,
	925	mtk_dai_etdm_o089_mix,
	926	ARRAY_SIZE(mtk_dai_etdm_o089_mix)),
	927	SND_SOC_DAPM_MIXER("O090", SND_SOC_NOPM, 0, 0,
	928	mtk_dai_etdm_o090_mix,
	929	ARRAY_SIZE(mtk_dai_etdm_o090_mix)),
	930	SND_SOC_DAPM_MIXER("O091", SND_SOC_NOPM, 0, 0,
	931	mtk_dai_etdm_o091_mix,
	932	ARRAY_SIZE(mtk_dai_etdm_o091_mix)),
	933	SND_SOC_DAPM_MIXER("O092", SND_SOC_NOPM, 0, 0,
	934	mtk_dai_etdm_o092_mix,
	935	ARRAY_SIZE(mtk_dai_etdm_o092_mix)),
	936	SND_SOC_DAPM_MIXER("O093", SND_SOC_NOPM, 0, 0,
	937	mtk_dai_etdm_o093_mix,
	938	ARRAY_SIZE(mtk_dai_etdm_o093_mix)),
	939	SND_SOC_DAPM_MIXER("O094", SND_SOC_NOPM, 0, 0,
	940	mtk_dai_etdm_o094_mix,
	941	ARRAY_SIZE(mtk_dai_etdm_o094_mix)),
	942	SND_SOC_DAPM_MIXER("O095", SND_SOC_NOPM, 0, 0,
	943	mtk_dai_etdm_o095_mix,
	944	ARRAY_SIZE(mtk_dai_etdm_o095_mix)),
	945
	946	/* eTDM_OUT3 */
	947	SND_SOC_DAPM_MUX("HDMI_OUT_MUX", SND_SOC_NOPM, 0, 0,
	948	&hdmi_out_mux_control),
	949	SND_SOC_DAPM_MUX("DPTX_OUT_MUX", SND_SOC_NOPM, 0, 0,
	950	&dptx_out_mux_control),
	951
	952	SND_SOC_DAPM_MUX("HDMI_CH0_MUX", SND_SOC_NOPM, 0, 0,
	953	&hdmi_ch0_mux_control),
	954	SND_SOC_DAPM_MUX("HDMI_CH1_MUX", SND_SOC_NOPM, 0, 0,
	955	&hdmi_ch1_mux_control),
	956	SND_SOC_DAPM_MUX("HDMI_CH2_MUX", SND_SOC_NOPM, 0, 0,
	957	&hdmi_ch2_mux_control),
	958	SND_SOC_DAPM_MUX("HDMI_CH3_MUX", SND_SOC_NOPM, 0, 0,
	959	&hdmi_ch3_mux_control),
	960	SND_SOC_DAPM_MUX("HDMI_CH4_MUX", SND_SOC_NOPM, 0, 0,
	961	&hdmi_ch4_mux_control),
	962	SND_SOC_DAPM_MUX("HDMI_CH5_MUX", SND_SOC_NOPM, 0, 0,
	963	&hdmi_ch5_mux_control),
	964	SND_SOC_DAPM_MUX("HDMI_CH6_MUX", SND_SOC_NOPM, 0, 0,
	965	&hdmi_ch6_mux_control),
	966	SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0,
	967	&hdmi_ch7_mux_control),
	968
	969	SND_SOC_DAPM_INPUT("ETDM_INPUT"),
	970	SND_SOC_DAPM_OUTPUT("ETDM_OUTPUT"),
	971	};
	972
	973	static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = {
	974	{"I012", NULL, "ETDM2 Capture"},
	975	{"I013", NULL, "ETDM2 Capture"},
	976	{"I014", NULL, "ETDM2 Capture"},
	977	{"I015", NULL, "ETDM2 Capture"},
	978	{"I016", NULL, "ETDM2 Capture"},
	979	{"I017", NULL, "ETDM2 Capture"},
	980	{"I018", NULL, "ETDM2 Capture"},
	981	{"I019", NULL, "ETDM2 Capture"},
	982
	983	{"I072", NULL, "ETDM1 Capture"},
	984	{"I073", NULL, "ETDM1 Capture"},
	985	{"I074", NULL, "ETDM1 Capture"},
	986	{"I075", NULL, "ETDM1 Capture"},
	987	{"I076", NULL, "ETDM1 Capture"},
	988	{"I077", NULL, "ETDM1 Capture"},
	989	{"I078", NULL, "ETDM1 Capture"},
	990	{"I079", NULL, "ETDM1 Capture"},
	991	{"I080", NULL, "ETDM1 Capture"},
	992	{"I081", NULL, "ETDM1 Capture"},
	993	{"I082", NULL, "ETDM1 Capture"},
	994	{"I083", NULL, "ETDM1 Capture"},
	995	{"I084", NULL, "ETDM1 Capture"},
	996	{"I085", NULL, "ETDM1 Capture"},
	997	{"I086", NULL, "ETDM1 Capture"},
	998	{"I087", NULL, "ETDM1 Capture"},
	999	{"I088", NULL, "ETDM1 Capture"},
	1000	{"I089", NULL, "ETDM1 Capture"},
	1001	{"I090", NULL, "ETDM1 Capture"},
	1002	{"I091", NULL, "ETDM1 Capture"},
	1003	{"I092", NULL, "ETDM1 Capture"},
	1004	{"I093", NULL, "ETDM1 Capture"},
	1005	{"I094", NULL, "ETDM1 Capture"},
	1006	{"I095", NULL, "ETDM1 Capture"},
	1007
	1008	{"UL8", NULL, "ETDM1 Capture"},
	1009	{"UL3", NULL, "ETDM2 Capture"},
	1010
	1011	{"ETDM2 Playback", NULL, "O048"},
	1012	{"ETDM2 Playback", NULL, "O049"},
	1013	{"ETDM2 Playback", NULL, "O050"},
	1014	{"ETDM2 Playback", NULL, "O051"},
	1015	{"ETDM2 Playback", NULL, "O052"},
	1016	{"ETDM2 Playback", NULL, "O053"},
	1017	{"ETDM2 Playback", NULL, "O054"},
	1018	{"ETDM2 Playback", NULL, "O055"},
	1019	{"ETDM2 Playback", NULL, "O056"},
	1020	{"ETDM2 Playback", NULL, "O057"},
	1021	{"ETDM2 Playback", NULL, "O058"},
	1022	{"ETDM2 Playback", NULL, "O059"},
	1023	{"ETDM2 Playback", NULL, "O060"},
	1024	{"ETDM2 Playback", NULL, "O061"},
	1025	{"ETDM2 Playback", NULL, "O062"},
	1026	{"ETDM2 Playback", NULL, "O063"},
	1027	{"ETDM2 Playback", NULL, "O064"},
	1028	{"ETDM2 Playback", NULL, "O065"},
	1029	{"ETDM2 Playback", NULL, "O066"},
	1030	{"ETDM2 Playback", NULL, "O067"},
	1031	{"ETDM2 Playback", NULL, "O068"},
	1032	{"ETDM2 Playback", NULL, "O069"},
	1033	{"ETDM2 Playback", NULL, "O070"},
	1034	{"ETDM2 Playback", NULL, "O071"},
	1035
	1036	{"ETDM1 Playback", NULL, "O072"},
	1037	{"ETDM1 Playback", NULL, "O073"},
	1038	{"ETDM1 Playback", NULL, "O074"},
	1039	{"ETDM1 Playback", NULL, "O075"},
	1040	{"ETDM1 Playback", NULL, "O076"},
	1041	{"ETDM1 Playback", NULL, "O077"},
	1042	{"ETDM1 Playback", NULL, "O078"},
	1043	{"ETDM1 Playback", NULL, "O079"},
	1044	{"ETDM1 Playback", NULL, "O080"},
	1045	{"ETDM1 Playback", NULL, "O081"},
	1046	{"ETDM1 Playback", NULL, "O082"},
	1047	{"ETDM1 Playback", NULL, "O083"},
	1048	{"ETDM1 Playback", NULL, "O084"},
	1049	{"ETDM1 Playback", NULL, "O085"},
	1050	{"ETDM1 Playback", NULL, "O086"},
	1051	{"ETDM1 Playback", NULL, "O087"},
	1052	{"ETDM1 Playback", NULL, "O088"},
	1053	{"ETDM1 Playback", NULL, "O089"},
	1054	{"ETDM1 Playback", NULL, "O090"},
	1055	{"ETDM1 Playback", NULL, "O091"},
	1056	{"ETDM1 Playback", NULL, "O092"},
	1057	{"ETDM1 Playback", NULL, "O093"},
	1058	{"ETDM1 Playback", NULL, "O094"},
	1059	{"ETDM1 Playback", NULL, "O095"},
	1060
	1061	{"O048", "I020 Switch", "I020"},
	1062	{"O049", "I021 Switch", "I021"},
	1063
	1064	{"O048", "I022 Switch", "I022"},
	1065	{"O049", "I023 Switch", "I023"},
	1066	{"O050", "I024 Switch", "I024"},
	1067	{"O051", "I025 Switch", "I025"},
	1068	{"O052", "I026 Switch", "I026"},
	1069	{"O053", "I027 Switch", "I027"},
	1070	{"O054", "I028 Switch", "I028"},
	1071	{"O055", "I029 Switch", "I029"},
	1072	{"O056", "I030 Switch", "I030"},
	1073	{"O057", "I031 Switch", "I031"},
	1074	{"O058", "I032 Switch", "I032"},
	1075	{"O059", "I033 Switch", "I033"},
	1076	{"O060", "I034 Switch", "I034"},
	1077	{"O061", "I035 Switch", "I035"},
	1078	{"O062", "I036 Switch", "I036"},
	1079	{"O063", "I037 Switch", "I037"},
	1080	{"O064", "I038 Switch", "I038"},
	1081	{"O065", "I039 Switch", "I039"},
	1082	{"O066", "I040 Switch", "I040"},
	1083	{"O067", "I041 Switch", "I041"},
	1084	{"O068", "I042 Switch", "I042"},
	1085	{"O069", "I043 Switch", "I043"},
	1086	{"O070", "I044 Switch", "I044"},
	1087	{"O071", "I045 Switch", "I045"},
	1088
	1089	{"O048", "I046 Switch", "I046"},
	1090	{"O049", "I047 Switch", "I047"},
	1091	{"O050", "I048 Switch", "I048"},
	1092	{"O051", "I049 Switch", "I049"},
	1093	{"O052", "I050 Switch", "I050"},
	1094	{"O053", "I051 Switch", "I051"},
	1095	{"O054", "I052 Switch", "I052"},
	1096	{"O055", "I053 Switch", "I053"},
	1097	{"O056", "I054 Switch", "I054"},
	1098	{"O057", "I055 Switch", "I055"},
	1099	{"O058", "I056 Switch", "I056"},
	1100	{"O059", "I057 Switch", "I057"},
	1101	{"O060", "I058 Switch", "I058"},
	1102	{"O061", "I059 Switch", "I059"},
	1103	{"O062", "I060 Switch", "I060"},
	1104	{"O063", "I061 Switch", "I061"},
	1105	{"O064", "I062 Switch", "I062"},
	1106	{"O065", "I063 Switch", "I063"},
	1107	{"O066", "I064 Switch", "I064"},
	1108	{"O067", "I065 Switch", "I065"},
	1109	{"O068", "I066 Switch", "I066"},
	1110	{"O069", "I067 Switch", "I067"},
	1111	{"O070", "I068 Switch", "I068"},
	1112	{"O071", "I069 Switch", "I069"},
	1113
	1114	{"O048", "I070 Switch", "I070"},
	1115	{"O049", "I071 Switch", "I071"},
	1116
	1117	{"O072", "I020 Switch", "I020"},
	1118	{"O073", "I021 Switch", "I021"},
	1119
	1120	{"O072", "I022 Switch", "I022"},
	1121	{"O073", "I023 Switch", "I023"},
	1122	{"O074", "I024 Switch", "I024"},
	1123	{"O075", "I025 Switch", "I025"},
	1124	{"O076", "I026 Switch", "I026"},
	1125	{"O077", "I027 Switch", "I027"},
	1126	{"O078", "I028 Switch", "I028"},
	1127	{"O079", "I029 Switch", "I029"},
	1128	{"O080", "I030 Switch", "I030"},
	1129	{"O081", "I031 Switch", "I031"},
	1130	{"O082", "I032 Switch", "I032"},
	1131	{"O083", "I033 Switch", "I033"},
	1132	{"O084", "I034 Switch", "I034"},
	1133	{"O085", "I035 Switch", "I035"},
	1134	{"O086", "I036 Switch", "I036"},
	1135	{"O087", "I037 Switch", "I037"},
	1136	{"O088", "I038 Switch", "I038"},
	1137	{"O089", "I039 Switch", "I039"},
	1138	{"O090", "I040 Switch", "I040"},
	1139	{"O091", "I041 Switch", "I041"},
	1140	{"O092", "I042 Switch", "I042"},
	1141	{"O093", "I043 Switch", "I043"},
	1142	{"O094", "I044 Switch", "I044"},
	1143	{"O095", "I045 Switch", "I045"},
	1144
	1145	{"O072", "I046 Switch", "I046"},
	1146	{"O073", "I047 Switch", "I047"},
	1147	{"O074", "I048 Switch", "I048"},
	1148	{"O075", "I049 Switch", "I049"},
	1149	{"O076", "I050 Switch", "I050"},
	1150	{"O077", "I051 Switch", "I051"},
	1151	{"O078", "I052 Switch", "I052"},
	1152	{"O079", "I053 Switch", "I053"},
	1153	{"O080", "I054 Switch", "I054"},
	1154	{"O081", "I055 Switch", "I055"},
	1155	{"O082", "I056 Switch", "I056"},
	1156	{"O083", "I057 Switch", "I057"},
	1157	{"O084", "I058 Switch", "I058"},
	1158	{"O085", "I059 Switch", "I059"},
	1159	{"O086", "I060 Switch", "I060"},
	1160	{"O087", "I061 Switch", "I061"},
	1161	{"O088", "I062 Switch", "I062"},
	1162	{"O089", "I063 Switch", "I063"},
	1163	{"O090", "I064 Switch", "I064"},
	1164	{"O091", "I065 Switch", "I065"},
	1165	{"O092", "I066 Switch", "I066"},
	1166	{"O093", "I067 Switch", "I067"},
	1167	{"O094", "I068 Switch", "I068"},
	1168	{"O095", "I069 Switch", "I069"},
	1169
	1170	{"O072", "I070 Switch", "I070"},
	1171	{"O073", "I071 Switch", "I071"},
	1172
	1173	{"HDMI_CH0_MUX", "CH0", "DL10"},
	1174	{"HDMI_CH0_MUX", "CH1", "DL10"},
	1175	{"HDMI_CH0_MUX", "CH2", "DL10"},
	1176	{"HDMI_CH0_MUX", "CH3", "DL10"},
	1177	{"HDMI_CH0_MUX", "CH4", "DL10"},
	1178	{"HDMI_CH0_MUX", "CH5", "DL10"},
	1179	{"HDMI_CH0_MUX", "CH6", "DL10"},
	1180	{"HDMI_CH0_MUX", "CH7", "DL10"},
	1181
	1182	{"HDMI_CH1_MUX", "CH0", "DL10"},
	1183	{"HDMI_CH1_MUX", "CH1", "DL10"},
	1184	{"HDMI_CH1_MUX", "CH2", "DL10"},
	1185	{"HDMI_CH1_MUX", "CH3", "DL10"},
	1186	{"HDMI_CH1_MUX", "CH4", "DL10"},
	1187	{"HDMI_CH1_MUX", "CH5", "DL10"},
	1188	{"HDMI_CH1_MUX", "CH6", "DL10"},
	1189	{"HDMI_CH1_MUX", "CH7", "DL10"},
	1190
	1191	{"HDMI_CH2_MUX", "CH0", "DL10"},
	1192	{"HDMI_CH2_MUX", "CH1", "DL10"},
	1193	{"HDMI_CH2_MUX", "CH2", "DL10"},
	1194	{"HDMI_CH2_MUX", "CH3", "DL10"},
	1195	{"HDMI_CH2_MUX", "CH4", "DL10"},
	1196	{"HDMI_CH2_MUX", "CH5", "DL10"},
	1197	{"HDMI_CH2_MUX", "CH6", "DL10"},
	1198	{"HDMI_CH2_MUX", "CH7", "DL10"},
	1199
	1200	{"HDMI_CH3_MUX", "CH0", "DL10"},
	1201	{"HDMI_CH3_MUX", "CH1", "DL10"},
	1202	{"HDMI_CH3_MUX", "CH2", "DL10"},
	1203	{"HDMI_CH3_MUX", "CH3", "DL10"},
	1204	{"HDMI_CH3_MUX", "CH4", "DL10"},
	1205	{"HDMI_CH3_MUX", "CH5", "DL10"},
	1206	{"HDMI_CH3_MUX", "CH6", "DL10"},
	1207	{"HDMI_CH3_MUX", "CH7", "DL10"},
	1208
	1209	{"HDMI_CH4_MUX", "CH0", "DL10"},
	1210	{"HDMI_CH4_MUX", "CH1", "DL10"},
	1211	{"HDMI_CH4_MUX", "CH2", "DL10"},
	1212	{"HDMI_CH4_MUX", "CH3", "DL10"},
	1213	{"HDMI_CH4_MUX", "CH4", "DL10"},
	1214	{"HDMI_CH4_MUX", "CH5", "DL10"},
	1215	{"HDMI_CH4_MUX", "CH6", "DL10"},
	1216	{"HDMI_CH4_MUX", "CH7", "DL10"},
	1217
	1218	{"HDMI_CH5_MUX", "CH0", "DL10"},
	1219	{"HDMI_CH5_MUX", "CH1", "DL10"},
	1220	{"HDMI_CH5_MUX", "CH2", "DL10"},
	1221	{"HDMI_CH5_MUX", "CH3", "DL10"},
	1222	{"HDMI_CH5_MUX", "CH4", "DL10"},
	1223	{"HDMI_CH5_MUX", "CH5", "DL10"},
	1224	{"HDMI_CH5_MUX", "CH6", "DL10"},
	1225	{"HDMI_CH5_MUX", "CH7", "DL10"},
	1226
	1227	{"HDMI_CH6_MUX", "CH0", "DL10"},
	1228	{"HDMI_CH6_MUX", "CH1", "DL10"},
	1229	{"HDMI_CH6_MUX", "CH2", "DL10"},
	1230	{"HDMI_CH6_MUX", "CH3", "DL10"},
	1231	{"HDMI_CH6_MUX", "CH4", "DL10"},
	1232	{"HDMI_CH6_MUX", "CH5", "DL10"},
	1233	{"HDMI_CH6_MUX", "CH6", "DL10"},
	1234	{"HDMI_CH6_MUX", "CH7", "DL10"},
	1235
	1236	{"HDMI_CH7_MUX", "CH0", "DL10"},
	1237	{"HDMI_CH7_MUX", "CH1", "DL10"},
	1238	{"HDMI_CH7_MUX", "CH2", "DL10"},
	1239	{"HDMI_CH7_MUX", "CH3", "DL10"},
	1240	{"HDMI_CH7_MUX", "CH4", "DL10"},
	1241	{"HDMI_CH7_MUX", "CH5", "DL10"},
	1242	{"HDMI_CH7_MUX", "CH6", "DL10"},
	1243	{"HDMI_CH7_MUX", "CH7", "DL10"},
	1244
	1245	{"HDMI_OUT_MUX", "Connect", "HDMI_CH0_MUX"},
	1246	{"HDMI_OUT_MUX", "Connect", "HDMI_CH1_MUX"},
	1247	{"HDMI_OUT_MUX", "Connect", "HDMI_CH2_MUX"},
	1248	{"HDMI_OUT_MUX", "Connect", "HDMI_CH3_MUX"},
	1249	{"HDMI_OUT_MUX", "Connect", "HDMI_CH4_MUX"},
	1250	{"HDMI_OUT_MUX", "Connect", "HDMI_CH5_MUX"},
	1251	{"HDMI_OUT_MUX", "Connect", "HDMI_CH6_MUX"},
	1252	{"HDMI_OUT_MUX", "Connect", "HDMI_CH7_MUX"},
	1253
	1254	{"DPTX_OUT_MUX", "Connect", "HDMI_CH0_MUX"},
	1255	{"DPTX_OUT_MUX", "Connect", "HDMI_CH1_MUX"},
	1256	{"DPTX_OUT_MUX", "Connect", "HDMI_CH2_MUX"},
	1257	{"DPTX_OUT_MUX", "Connect", "HDMI_CH3_MUX"},
	1258	{"DPTX_OUT_MUX", "Connect", "HDMI_CH4_MUX"},
	1259	{"DPTX_OUT_MUX", "Connect", "HDMI_CH5_MUX"},
	1260	{"DPTX_OUT_MUX", "Connect", "HDMI_CH6_MUX"},
	1261	{"DPTX_OUT_MUX", "Connect", "HDMI_CH7_MUX"},
	1262
	1263	{"ETDM3 Playback", NULL, "HDMI_OUT_MUX"},
	1264	{"DPTX Playback", NULL, "DPTX_OUT_MUX"},
	1265
	1266	{"ETDM_OUTPUT", NULL, "DPTX Playback"},
	1267	{"ETDM_OUTPUT", NULL, "ETDM1 Playback"},
	1268	{"ETDM_OUTPUT", NULL, "ETDM2 Playback"},
	1269	{"ETDM_OUTPUT", NULL, "ETDM3 Playback"},
	1270	{"ETDM1 Capture", NULL, "ETDM_INPUT"},
	1271	{"ETDM2 Capture", NULL, "ETDM_INPUT"},
	1272	};
	1273
	1274	static int mt8195_afe_enable_etdm(struct mtk_base_afe *afe, int dai_id)
	1275	{
	1276	int ret = 0;
	1277	struct etdm_con_reg etdm_reg;
	1278	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	1279	struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id];
	1280	unsigned long flags;
	1281
	1282	spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
	1283	etdm_data->en_ref_cnt++;
	1284	if (etdm_data->en_ref_cnt == 1) {
	1285	ret = get_etdm_reg(dai_id, &etdm_reg);
	1286	if (ret < 0)
	1287	goto out;
	1288
	1289	regmap_update_bits(afe->regmap, etdm_reg.con0,
	1290	ETDM_CON0_EN, ETDM_CON0_EN);
	1291	}
	1292	out:
	1293	spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
	1294	return ret;
	1295	}
	1296
	1297	static int mt8195_afe_disable_etdm(struct mtk_base_afe *afe, int dai_id)
	1298	{
	1299	int ret = 0;
	1300	struct etdm_con_reg etdm_reg;
	1301	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	1302	struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id];
	1303	unsigned long flags;
	1304
	1305	spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
	1306	if (etdm_data->en_ref_cnt > 0) {
	1307	etdm_data->en_ref_cnt--;
	1308	if (etdm_data->en_ref_cnt == 0) {
	1309	ret = get_etdm_reg(dai_id, &etdm_reg);
	1310	if (ret < 0)
	1311	goto out;
	1312
	1313	regmap_update_bits(afe->regmap, etdm_reg.con0,
	1314	ETDM_CON0_EN, 0);
	1315	}
	1316	}
	1317	out:
	1318	spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
	1319	return 0;
	1320	}
	1321
	1322	static int etdm_cowork_slv_sel(int id, int slave_mode)
	1323	{
	1324	if (slave_mode) {
	1325	switch (id) {
	1326	case MT8195_AFE_IO_ETDM1_IN:
	1327	return COWORK_ETDM_IN1_S;
	1328	case MT8195_AFE_IO_ETDM2_IN:
	1329	return COWORK_ETDM_IN2_S;
	1330	case MT8195_AFE_IO_ETDM1_OUT:
	1331	return COWORK_ETDM_OUT1_S;
	1332	case MT8195_AFE_IO_ETDM2_OUT:
	1333	return COWORK_ETDM_OUT2_S;
	1334	case MT8195_AFE_IO_ETDM3_OUT:
	1335	return COWORK_ETDM_OUT3_S;
	1336	default:
	1337	return -EINVAL;
	1338	}
	1339	} else {
	1340	switch (id) {
	1341	case MT8195_AFE_IO_ETDM1_IN:
	1342	return COWORK_ETDM_IN1_M;
	1343	case MT8195_AFE_IO_ETDM2_IN:
	1344	return COWORK_ETDM_IN2_M;
	1345	case MT8195_AFE_IO_ETDM1_OUT:
	1346	return COWORK_ETDM_OUT1_M;
	1347	case MT8195_AFE_IO_ETDM2_OUT:
	1348	return COWORK_ETDM_OUT2_M;
	1349	case MT8195_AFE_IO_ETDM3_OUT:
	1350	return COWORK_ETDM_OUT3_M;
	1351	default:
	1352	return -EINVAL;
	1353	}
	1354	}
	1355	}
	1356
	1357	static int mt8195_etdm_sync_mode_configure(struct mtk_base_afe *afe, int dai_id)
	1358	{
	1359	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	1360	struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id];
	1361	unsigned int reg = 0;
	1362	unsigned int mask;
	1363	unsigned int val;
	1364	int cowork_source_sel;
	1365
	1366	if (etdm_data->cowork_source_id == COWORK_ETDM_NONE)
	1367	return 0;
	1368
	1369	cowork_source_sel = etdm_cowork_slv_sel(etdm_data->cowork_source_id,
	1370	etdm_data->slave_mode);
	1371	if (cowork_source_sel < 0)
	1372	return cowork_source_sel;
	1373
	1374	switch (dai_id) {
	1375	case MT8195_AFE_IO_ETDM1_IN:
	1376	reg = ETDM_COWORK_CON1;
	1377	mask = ETDM_IN1_SLAVE_SEL_MASK;
	1378	val = ETDM_IN1_SLAVE_SEL(cowork_source_sel);
	1379	break;
	1380	case MT8195_AFE_IO_ETDM2_IN:
	1381	reg = ETDM_COWORK_CON2;
	1382	mask = ETDM_IN2_SLAVE_SEL_MASK;
	1383	val = ETDM_IN2_SLAVE_SEL(cowork_source_sel);
	1384	break;
	1385	case MT8195_AFE_IO_ETDM1_OUT:
	1386	reg = ETDM_COWORK_CON0;
	1387	mask = ETDM_OUT1_SLAVE_SEL_MASK;
	1388	val = ETDM_OUT1_SLAVE_SEL(cowork_source_sel);
	1389	break;
	1390	case MT8195_AFE_IO_ETDM2_OUT:
	1391	reg = ETDM_COWORK_CON2;
	1392	mask = ETDM_OUT2_SLAVE_SEL_MASK;
	1393	val = ETDM_OUT2_SLAVE_SEL(cowork_source_sel);
	1394	break;
	1395	case MT8195_AFE_IO_ETDM3_OUT:
	1396	reg = ETDM_COWORK_CON2;
	1397	mask = ETDM_OUT3_SLAVE_SEL_MASK;
	1398	val = ETDM_OUT3_SLAVE_SEL(cowork_source_sel);
	1399	break;
	1400	default:
	1401	return 0;
	1402	}
	1403
	1404	regmap_update_bits(afe->regmap, reg, mask, val);
	1405
	1406	return 0;
	1407	}
	1408
	1409	static int mtk_dai_etdm_get_cg_id_by_dai_id(int dai_id)
	1410	{
	1411	int cg_id = -1;
	1412
	1413	switch (dai_id) {
	1414	case MT8195_AFE_IO_DPTX:
	1415	cg_id = MT8195_CLK_AUD_HDMI_OUT;
	1416	break;
	1417	case MT8195_AFE_IO_ETDM1_IN:
	1418	cg_id = MT8195_CLK_AUD_TDM_IN;
	1419	break;
	1420	case MT8195_AFE_IO_ETDM2_IN:
	1421	cg_id = MT8195_CLK_AUD_I2SIN;
	1422	break;
	1423	case MT8195_AFE_IO_ETDM1_OUT:
	1424	cg_id = MT8195_CLK_AUD_TDM_OUT;
	1425	break;
	1426	case MT8195_AFE_IO_ETDM2_OUT:
	1427	cg_id = MT8195_CLK_AUD_I2S_OUT;
	1428	break;
	1429	case MT8195_AFE_IO_ETDM3_OUT:
	1430	cg_id = MT8195_CLK_AUD_HDMI_OUT;
	1431	break;
	1432	default:
	1433	break;
	1434	}
	1435
	1436	return cg_id;
	1437	}
	1438
	1439	static int mtk_dai_etdm_get_clk_id_by_dai_id(int dai_id)
	1440	{
	1441	int clk_id = -1;
	1442
	1443	switch (dai_id) {
	1444	case MT8195_AFE_IO_DPTX:
	1445	clk_id = MT8195_CLK_TOP_DPTX_M_SEL;
	1446	break;
	1447	case MT8195_AFE_IO_ETDM1_IN:
	1448	clk_id = MT8195_CLK_TOP_I2SI1_M_SEL;
	1449	break;
	1450	case MT8195_AFE_IO_ETDM2_IN:
	1451	clk_id = MT8195_CLK_TOP_I2SI2_M_SEL;
	1452	break;
	1453	case MT8195_AFE_IO_ETDM1_OUT:
	1454	clk_id = MT8195_CLK_TOP_I2SO1_M_SEL;
	1455	break;
	1456	case MT8195_AFE_IO_ETDM2_OUT:
	1457	clk_id = MT8195_CLK_TOP_I2SO2_M_SEL;
	1458	break;
	1459	case MT8195_AFE_IO_ETDM3_OUT:
	1460	default:
	1461	break;
	1462	}
	1463
	1464	return clk_id;
	1465	}
	1466
	1467	static int mtk_dai_etdm_get_clkdiv_id_by_dai_id(int dai_id)
	1468	{
	1469	int clk_id = -1;
	1470
	1471	switch (dai_id) {
	1472	case MT8195_AFE_IO_DPTX:
	1473	clk_id = MT8195_CLK_TOP_APLL12_DIV9;
	1474	break;
	1475	case MT8195_AFE_IO_ETDM1_IN:
	1476	clk_id = MT8195_CLK_TOP_APLL12_DIV0;
	1477	break;
	1478	case MT8195_AFE_IO_ETDM2_IN:
	1479	clk_id = MT8195_CLK_TOP_APLL12_DIV1;
	1480	break;
	1481	case MT8195_AFE_IO_ETDM1_OUT:
	1482	clk_id = MT8195_CLK_TOP_APLL12_DIV2;
	1483	break;
	1484	case MT8195_AFE_IO_ETDM2_OUT:
	1485	clk_id = MT8195_CLK_TOP_APLL12_DIV3;
	1486	break;
	1487	case MT8195_AFE_IO_ETDM3_OUT:
	1488	default:
	1489	break;
	1490	}
	1491
	1492	return clk_id;
	1493	}
	1494
	1495	static int mtk_dai_etdm_enable_mclk(struct mtk_base_afe *afe, int dai_id)
	1496	{
	1497	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	1498	int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id);
	1499
	1500	if (clkdiv_id < 0)
	1501	return -EINVAL;
	1502
	1503	mt8195_afe_enable_clk(afe, afe_priv->clk[clkdiv_id]);
	1504
	1505	return 0;
	1506	}
	1507
	1508	static int mtk_dai_etdm_disable_mclk(struct mtk_base_afe *afe, int dai_id)
	1509	{
	1510	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	1511	int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id);
	1512
	1513	if (clkdiv_id < 0)
	1514	return -EINVAL;
	1515
	1516	mt8195_afe_disable_clk(afe, afe_priv->clk[clkdiv_id]);
	1517
	1518	return 0;
	1519	}
	1520
	1521	/* dai ops */
	1522	static int mtk_dai_etdm_startup(struct snd_pcm_substream *substream,
	1523	struct snd_soc_dai *dai)
	1524	{
	1525	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	1526	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	1527	struct mtk_dai_etdm_priv *mst_etdm_data;
	1528	int cg_id;
	1529	int mst_dai_id;
	1530	int slv_dai_id;
	1531	int i;
	1532
	1533	if (is_cowork_mode(dai)) {
	1534	mst_dai_id = get_etdm_cowork_master_id(dai);
	1535	mtk_dai_etdm_enable_mclk(afe, mst_dai_id);
	1536
	1537	cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id);
	1538	if (cg_id >= 0)
	1539	mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]);
	1540
	1541	mst_etdm_data = afe_priv->dai_priv[mst_dai_id];
	1542
	1543	for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) {
	1544	slv_dai_id = mst_etdm_data->cowork_slv_id[i];
	1545	cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id);
	1546	if (cg_id >= 0)
	1547	mt8195_afe_enable_clk(afe,
	1548	afe_priv->clk[cg_id]);
	1549	}
	1550	} else {
	1551	mtk_dai_etdm_enable_mclk(afe, dai->id);
	1552
	1553	cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id);
	1554	if (cg_id >= 0)
	1555	mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]);
	1556	}
	1557
	1558	return 0;
	1559	}
	1560
	1561	static void mtk_dai_etdm_shutdown(struct snd_pcm_substream *substream,
	1562	struct snd_soc_dai *dai)
	1563	{
	1564	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	1565	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	1566	struct mtk_dai_etdm_priv *mst_etdm_data;
	1567	int cg_id;
	1568	int mst_dai_id;
	1569	int slv_dai_id;
	1570	int i;
	1571
	1572	if (is_cowork_mode(dai)) {
	1573	mst_dai_id = get_etdm_cowork_master_id(dai);
	1574	cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id);
	1575	if (cg_id >= 0)
	1576	mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]);
	1577
	1578	mst_etdm_data = afe_priv->dai_priv[mst_dai_id];
	1579	for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) {
	1580	slv_dai_id = mst_etdm_data->cowork_slv_id[i];
	1581	cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id);
	1582	if (cg_id >= 0)
	1583	mt8195_afe_disable_clk(afe,
	1584	afe_priv->clk[cg_id]);
	1585	}
	1586	mtk_dai_etdm_disable_mclk(afe, mst_dai_id);
	1587	} else {
	1588	cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id);
	1589	if (cg_id >= 0)
	1590	mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]);
	1591
	1592	mtk_dai_etdm_disable_mclk(afe, dai->id);
	1593	}
	1594	}
	1595
	1596	static int mtk_dai_etdm_fifo_mode(struct mtk_base_afe *afe,
	1597	int dai_id, unsigned int rate)
	1598	{
	1599	unsigned int mode = 0;
	1600	unsigned int reg = 0;
	1601	unsigned int val = 0;
	1602	unsigned int mask = (ETDM_IN_AFIFO_MODE_MASK \| ETDM_IN_USE_AFIFO);
	1603
	1604	if (rate != 0)
	1605	mode = mt8195_afe_fs_timing(rate);
	1606
	1607	switch (dai_id) {
	1608	case MT8195_AFE_IO_ETDM1_IN:
	1609	reg = ETDM_IN1_AFIFO_CON;
	1610	if (rate == 0)
	1611	mode = MT8195_ETDM_IN1_1X_EN;
	1612	break;
	1613	case MT8195_AFE_IO_ETDM2_IN:
	1614	reg = ETDM_IN2_AFIFO_CON;
	1615	if (rate == 0)
	1616	mode = MT8195_ETDM_IN2_1X_EN;
	1617	break;
	1618	default:
	1619	return -EINVAL;
	1620	}
	1621
	1622	val = (mode \| ETDM_IN_USE_AFIFO);
	1623
	1624	regmap_update_bits(afe->regmap, reg, mask, val);
	1625	return 0;
	1626	}
	1627
	1628	static int mtk_dai_etdm_in_configure(struct mtk_base_afe *afe,
	1629	unsigned int rate,
	1630	unsigned int channels,
	1631	int dai_id)
	1632	{
	1633	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	1634	struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id];
	1635	struct etdm_con_reg etdm_reg;
	1636	bool slave_mode = etdm_data->slave_mode;
	1637	unsigned int data_mode = etdm_data->data_mode;
	1638	unsigned int lrck_width = etdm_data->lrck_width;
	1639	unsigned int val = 0;
	1640	unsigned int mask = 0;
	1641	int i;
	1642	int ret;
	1643
	1644	dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n",
	1645	__func__, rate, channels, dai_id);
	1646
	1647	ret = get_etdm_reg(dai_id, &etdm_reg);
	1648	if (ret < 0)
	1649	return ret;
	1650
	1651	if (etdm_data->cowork_source_id != COWORK_ETDM_NONE)
	1652	slave_mode = true;
	1653
	1654	/* afifo */
	1655	if (slave_mode)
	1656	mtk_dai_etdm_fifo_mode(afe, dai_id, 0);
	1657	else
	1658	mtk_dai_etdm_fifo_mode(afe, dai_id, rate);
	1659
	1660	/* con1 */
	1661	if (lrck_width > 0) {
	1662	mask \|= (ETDM_IN_CON1_LRCK_AUTO_MODE \|
	1663	ETDM_IN_CON1_LRCK_WIDTH_MASK);
	1664	val \|= ETDM_IN_CON1_LRCK_WIDTH(lrck_width);
	1665	}
	1666	regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val);
	1667
	1668	mask = 0;
	1669	val = 0;
	1670
	1671	/* con2 */
	1672	if (!slave_mode) {
	1673	mask \|= ETDM_IN_CON2_UPDATE_GAP_MASK;
	1674	if (rate == 352800 \|\| rate == 384000)
	1675	val \|= ETDM_IN_CON2_UPDATE_GAP(4);
	1676	else
	1677	val \|= ETDM_IN_CON2_UPDATE_GAP(3);
	1678	}
	1679	mask \|= (ETDM_IN_CON2_MULTI_IP_2CH_MODE \|
	1680	ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK);
	1681	if (data_mode == MTK_DAI_ETDM_DATA_MULTI_PIN) {
	1682	val \|= ETDM_IN_CON2_MULTI_IP_2CH_MODE \|
	1683	ETDM_IN_CON2_MULTI_IP_TOTAL_CH(channels);
	1684	}
	1685	regmap_update_bits(afe->regmap, etdm_reg.con2, mask, val);
	1686
	1687	mask = 0;
	1688	val = 0;
	1689
	1690	/* con3 */
	1691	mask \|= ETDM_IN_CON3_DISABLE_OUT_MASK;
	1692	for (i = 0; i < channels; i += 2) {
	1693	if (etdm_data->in_disable_ch[i] &&
	1694	etdm_data->in_disable_ch[i + 1])
	1695	val \|= ETDM_IN_CON3_DISABLE_OUT(i >> 1);
	1696	}
	1697	if (!slave_mode) {
	1698	mask \|= ETDM_IN_CON3_FS_MASK;
	1699	val \|= ETDM_IN_CON3_FS(get_etdm_fs_timing(rate));
	1700	}
	1701	regmap_update_bits(afe->regmap, etdm_reg.con3, mask, val);
	1702
	1703	mask = 0;
	1704	val = 0;
	1705
	1706	/* con4 */
	1707	mask \|= (ETDM_IN_CON4_MASTER_LRCK_INV \| ETDM_IN_CON4_MASTER_BCK_INV \|
	1708	ETDM_IN_CON4_SLAVE_LRCK_INV \| ETDM_IN_CON4_SLAVE_BCK_INV);
	1709	if (slave_mode) {
	1710	if (etdm_data->lrck_inv)
	1711	val \|= ETDM_IN_CON4_SLAVE_LRCK_INV;
	1712	if (etdm_data->bck_inv)
	1713	val \|= ETDM_IN_CON4_SLAVE_BCK_INV;
	1714	} else {
	1715	if (etdm_data->lrck_inv)
	1716	val \|= ETDM_IN_CON4_MASTER_LRCK_INV;
	1717	if (etdm_data->bck_inv)
	1718	val \|= ETDM_IN_CON4_MASTER_BCK_INV;
	1719	}
	1720	regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val);
	1721
	1722	mask = 0;
	1723	val = 0;
	1724
	1725	/* con5 */
	1726	mask \|= ETDM_IN_CON5_LR_SWAP_MASK;
	1727	mask \|= ETDM_IN_CON5_ENABLE_ODD_MASK;
	1728	for (i = 0; i < channels; i += 2) {
	1729	if (etdm_data->in_disable_ch[i] &&
	1730	!etdm_data->in_disable_ch[i + 1]) {
	1731	if (i == (channels - 2))
	1732	val \|= ETDM_IN_CON5_LR_SWAP(15);
	1733	else
	1734	val \|= ETDM_IN_CON5_LR_SWAP(i >> 1);
	1735	val \|= ETDM_IN_CON5_ENABLE_ODD(i >> 1);
	1736	} else if (!etdm_data->in_disable_ch[i] &&
	1737	etdm_data->in_disable_ch[i + 1]) {
	1738	val \|= ETDM_IN_CON5_ENABLE_ODD(i >> 1);
	1739	}
	1740	}
	1741	regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val);
	1742	return 0;
	1743	}
	1744
	1745	static int mtk_dai_etdm_out_configure(struct mtk_base_afe *afe,
	1746	unsigned int rate,
	1747	unsigned int channels,
	1748	int dai_id)
	1749	{
	1750	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	1751	struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id];
	1752	struct etdm_con_reg etdm_reg;
	1753	bool slave_mode = etdm_data->slave_mode;
	1754	unsigned int lrck_width = etdm_data->lrck_width;
	1755	unsigned int val = 0;
	1756	unsigned int mask = 0;
	1757	int ret;
	1758	int fs = 0;
	1759
	1760	dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n",
	1761	__func__, rate, channels, dai_id);
	1762
	1763	ret = get_etdm_reg(dai_id, &etdm_reg);
	1764	if (ret < 0)
	1765	return ret;
	1766
	1767	if (etdm_data->cowork_source_id != COWORK_ETDM_NONE)
	1768	slave_mode = true;
	1769
	1770	/* con0 */
	1771	mask = ETDM_OUT_CON0_RELATCH_DOMAIN_MASK;
	1772	val = ETDM_OUT_CON0_RELATCH_DOMAIN(ETDM_RELATCH_TIMING_A1A2SYS);
	1773	regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val);
	1774
	1775	mask = 0;
	1776	val = 0;
	1777
	1778	/* con1 */
	1779	if (lrck_width > 0) {
	1780	mask \|= (ETDM_OUT_CON1_LRCK_AUTO_MODE \|
	1781	ETDM_OUT_CON1_LRCK_WIDTH_MASK);
	1782	val \|= ETDM_OUT_CON1_LRCK_WIDTH(lrck_width);
	1783	}
	1784	regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val);
	1785
	1786	mask = 0;
	1787	val = 0;
	1788
	1789	if (slave_mode) {
	1790	/* con2 */
	1791	mask = (ETDM_OUT_CON2_LRCK_DELAY_BCK_INV \|
	1792	ETDM_OUT_CON2_LRCK_DELAY_0P5T_EN);
	1793	val = (ETDM_OUT_CON2_LRCK_DELAY_BCK_INV \|
	1794	ETDM_OUT_CON2_LRCK_DELAY_0P5T_EN);
	1795	regmap_update_bits(afe->regmap, etdm_reg.con2,
	1796	mask, val);
	1797	mask = 0;
	1798	val = 0;
	1799	} else {
	1800	/* con4 */
	1801	mask \|= ETDM_OUT_CON4_FS_MASK;
	1802	val \|= ETDM_OUT_CON4_FS(get_etdm_fs_timing(rate));
	1803	}
	1804
	1805	mask \|= ETDM_OUT_CON4_RELATCH_EN_MASK;
	1806	if (dai_id == MT8195_AFE_IO_ETDM1_OUT)
	1807	fs = MT8195_ETDM_OUT1_1X_EN;
	1808	else if (dai_id == MT8195_AFE_IO_ETDM2_OUT)
	1809	fs = MT8195_ETDM_OUT2_1X_EN;
	1810
	1811	val \|= ETDM_OUT_CON4_RELATCH_EN(fs);
	1812
	1813	regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val);
	1814
	1815	mask = 0;
	1816	val = 0;
	1817
	1818	/* con5 */
	1819	mask \|= (ETDM_OUT_CON5_MASTER_LRCK_INV \| ETDM_OUT_CON5_MASTER_BCK_INV \|
	1820	ETDM_OUT_CON5_SLAVE_LRCK_INV \| ETDM_OUT_CON5_SLAVE_BCK_INV);
	1821	if (slave_mode) {
	1822	if (etdm_data->lrck_inv)
	1823	val \|= ETDM_OUT_CON5_SLAVE_LRCK_INV;
	1824	if (etdm_data->bck_inv)
	1825	val \|= ETDM_OUT_CON5_SLAVE_BCK_INV;
	1826	} else {
	1827	if (etdm_data->lrck_inv)
	1828	val \|= ETDM_OUT_CON5_MASTER_LRCK_INV;
	1829	if (etdm_data->bck_inv)
	1830	val \|= ETDM_OUT_CON5_MASTER_BCK_INV;
	1831	}
	1832	regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val);
	1833
	1834	return 0;
	1835	}
	1836
	1837	static int mtk_dai_etdm_mclk_configure(struct mtk_base_afe *afe, int dai_id)
	1838	{
	1839	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	1840	struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id];
	1841	int clk_id = mtk_dai_etdm_get_clk_id_by_dai_id(dai_id);
	1842	int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id);
	1843	int apll;
	1844	int apll_clk_id;
	1845	struct etdm_con_reg etdm_reg;
	1846	unsigned int val = 0;
	1847	unsigned int mask = 0;
	1848	int ret = 0;
	1849
	1850	if (clk_id < 0 \|\| clkdiv_id < 0)
	1851	return 0;
	1852
	1853	ret = get_etdm_reg(dai_id, &etdm_reg);
	1854	if (ret < 0)
	1855	return ret;
	1856
	1857	mask \|= ETDM_CON1_MCLK_OUTPUT;
	1858	if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT)
	1859	val \|= ETDM_CON1_MCLK_OUTPUT;
	1860	regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val);
	1861
	1862	if (etdm_data->mclk_freq) {
	1863	apll = etdm_data->mclk_apll;
	1864	apll_clk_id = mt8195_afe_get_mclk_source_clk_id(apll);
	1865	if (apll_clk_id < 0)
	1866	return apll_clk_id;
	1867
	1868	/* select apll */
	1869	ret = mt8195_afe_set_clk_parent(afe, afe_priv->clk[clk_id],
	1870	afe_priv->clk[apll_clk_id]);
	1871	if (ret)
	1872	return ret;
	1873
	1874	/* set rate */
	1875	ret = mt8195_afe_set_clk_rate(afe, afe_priv->clk[clkdiv_id],
	1876	etdm_data->mclk_freq);
	1877	} else {
	1878	if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT)
	1879	dev_dbg(afe->dev, "%s mclk freq = 0\n", __func__);
	1880	}
	1881	return ret;
	1882	}
	1883
	1884	static int mtk_dai_etdm_configure(struct mtk_base_afe *afe,
	1885	unsigned int rate,
	1886	unsigned int channels,
	1887	unsigned int bit_width,
	1888	int dai_id)
	1889	{
	1890	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	1891	struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id];
	1892	struct etdm_con_reg etdm_reg;
	1893	bool slave_mode = etdm_data->slave_mode;
	1894	unsigned int etdm_channels;
	1895	unsigned int val = 0;
	1896	unsigned int mask = 0;
	1897	unsigned int bck;
	1898	unsigned int wlen = get_etdm_wlen(bit_width);
	1899	int ret;
	1900
	1901	ret = get_etdm_reg(dai_id, &etdm_reg);
	1902	if (ret < 0)
	1903	return ret;
	1904
	1905	if (etdm_data->cowork_source_id != COWORK_ETDM_NONE)
	1906	slave_mode = true;
	1907
	1908	dev_dbg(afe->dev, "%s fmt %u data %u lrck %d-%u bck %d, clock %u slv %u\n",
	1909	__func__, etdm_data->format, etdm_data->data_mode,
	1910	etdm_data->lrck_inv, etdm_data->lrck_width, etdm_data->bck_inv,
	1911	etdm_data->clock_mode, etdm_data->slave_mode);
	1912	dev_dbg(afe->dev, "%s rate %u channels %u bitwidth %u, id %d\n",
	1913	__func__, rate, channels, bit_width, dai_id);
	1914
	1915	etdm_channels = (etdm_data->data_mode == MTK_DAI_ETDM_DATA_ONE_PIN) ?
	1916	get_etdm_ch_fixup(channels) : 2;
	1917
	1918	bck = rate * etdm_channels * wlen;
	1919	if (bck > MT8195_ETDM_NORMAL_MAX_BCK_RATE) {
	1920	dev_info(afe->dev, "%s bck rate %u not support\n",
	1921	__func__, bck);
	1922	return -EINVAL;
	1923	}
	1924
	1925	/* con0 */
	1926	mask \|= ETDM_CON0_BIT_LEN_MASK;
	1927	val \|= ETDM_CON0_BIT_LEN(bit_width);
	1928	mask \|= ETDM_CON0_WORD_LEN_MASK;
	1929	val \|= ETDM_CON0_WORD_LEN(wlen);
	1930	mask \|= ETDM_CON0_FORMAT_MASK;
	1931	val \|= ETDM_CON0_FORMAT(etdm_data->format);
	1932	mask \|= ETDM_CON0_CH_NUM_MASK;
	1933	val \|= ETDM_CON0_CH_NUM(etdm_channels);
	1934
	1935	mask \|= ETDM_CON0_SLAVE_MODE;
	1936	if (slave_mode) {
	1937	if (dai_id == MT8195_AFE_IO_ETDM1_OUT &&
	1938	etdm_data->cowork_source_id == COWORK_ETDM_NONE) {
	1939	dev_info(afe->dev, "%s id %d only support master mode\n",
	1940	__func__, dai_id);
	1941	return -EINVAL;
	1942	}
	1943	val \|= ETDM_CON0_SLAVE_MODE;
	1944	}
	1945	regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val);
	1946
	1947	if (get_etdm_dir(dai_id) == ETDM_IN)
	1948	mtk_dai_etdm_in_configure(afe, rate, channels, dai_id);
	1949	else
	1950	mtk_dai_etdm_out_configure(afe, rate, channels, dai_id);
	1951
	1952	return 0;
	1953	}
	1954
	1955	static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream,
	1956	struct snd_pcm_hw_params *params,
	1957	struct snd_soc_dai *dai)
	1958	{
	1959	int ret = 0;
	1960	unsigned int rate = params_rate(params);
	1961	unsigned int bit_width = params_width(params);
	1962	unsigned int channels = params_channels(params);
	1963	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	1964	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	1965	struct mtk_dai_etdm_priv *mst_etdm_data;
	1966	int mst_dai_id;
	1967	int slv_dai_id;
	1968	int i;
	1969
	1970	dev_dbg(afe->dev, "%s '%s' period %u-%u\n",
	1971	__func__, snd_pcm_stream_str(substream),
	1972	params_period_size(params), params_periods(params));
	1973
	1974	if (is_cowork_mode(dai)) {
	1975	mst_dai_id = get_etdm_cowork_master_id(dai);
	1976
	1977	ret = mtk_dai_etdm_mclk_configure(afe, mst_dai_id);
	1978	if (ret)
	1979	return ret;
	1980
	1981	ret = mtk_dai_etdm_configure(afe, rate, channels,
	1982	bit_width, mst_dai_id);
	1983	if (ret)
	1984	return ret;
	1985
	1986	mst_etdm_data = afe_priv->dai_priv[mst_dai_id];
	1987	for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) {
	1988	slv_dai_id = mst_etdm_data->cowork_slv_id[i];
	1989	ret = mtk_dai_etdm_configure(afe, rate, channels,
	1990	bit_width, slv_dai_id);
	1991	if (ret)
	1992	return ret;
	1993
	1994	ret = mt8195_etdm_sync_mode_configure(afe, slv_dai_id);
	1995	if (ret)
	1996	return ret;
	1997	}
	1998	} else {
	1999	ret = mtk_dai_etdm_mclk_configure(afe, dai->id);
	2000	if (ret)
	2001	return ret;
	2002
	2003	ret = mtk_dai_etdm_configure(afe, rate, channels,
	2004	bit_width, dai->id);
	2005	}
	2006
	2007	return ret;
	2008	}
	2009
	2010	static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd,
	2011	struct snd_soc_dai *dai)
	2012	{
	2013	int ret = 0;
	2014	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	2015	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	2016	struct mtk_dai_etdm_priv *mst_etdm_data;
	2017	int mst_dai_id;
	2018	int slv_dai_id;
	2019	int i;
	2020
	2021	dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id);
	2022	switch (cmd) {
	2023	case SNDRV_PCM_TRIGGER_START:
	2024	case SNDRV_PCM_TRIGGER_RESUME:
	2025	if (is_cowork_mode(dai)) {
	2026	mst_dai_id = get_etdm_cowork_master_id(dai);
	2027	mst_etdm_data = afe_priv->dai_priv[mst_dai_id];
	2028
	2029	//open master first
	2030	ret \|= mt8195_afe_enable_etdm(afe, mst_dai_id);
	2031	for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) {
	2032	slv_dai_id = mst_etdm_data->cowork_slv_id[i];
	2033	ret \|= mt8195_afe_enable_etdm(afe, slv_dai_id);
	2034	}
	2035	} else {
	2036	ret = mt8195_afe_enable_etdm(afe, dai->id);
	2037	}
	2038	break;
	2039	case SNDRV_PCM_TRIGGER_STOP:
	2040	case SNDRV_PCM_TRIGGER_SUSPEND:
	2041	if (is_cowork_mode(dai)) {
	2042	mst_dai_id = get_etdm_cowork_master_id(dai);
	2043	mst_etdm_data = afe_priv->dai_priv[mst_dai_id];
	2044
	2045	for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) {
	2046	slv_dai_id = mst_etdm_data->cowork_slv_id[i];
	2047	ret \|= mt8195_afe_disable_etdm(afe, slv_dai_id);
	2048	}
	2049	// close master at last
	2050	ret \|= mt8195_afe_disable_etdm(afe, mst_dai_id);
	2051	} else {
	2052	ret = mt8195_afe_disable_etdm(afe, dai->id);
	2053	}
	2054	break;
	2055	default:
	2056	break;
	2057	}
	2058	return ret;
	2059	}
	2060
	2061	static int mtk_dai_etdm_cal_mclk(struct mtk_base_afe *afe, int freq, int dai_id)
	2062	{
	2063	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	2064	struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id];
	2065	int apll;
	2066	int apll_rate;
	2067
	2068	if (freq == 0) {
	2069	etdm_data->mclk_freq = freq;
	2070	return 0;
	2071	}
	2072
	2073	apll = mt8195_afe_get_default_mclk_source_by_rate(freq);
	2074	apll_rate = mt8195_afe_get_mclk_source_rate(afe, apll);
	2075
	2076	if (freq > apll_rate) {
	2077	dev_info(afe->dev, "freq %d > apll rate %d\n", freq, apll_rate);
	2078	return -EINVAL;
	2079	}
	2080
	2081	if (apll_rate % freq != 0) {
	2082	dev_info(afe->dev, "APLL%d cannot generate freq Hz\n", apll);
	2083	return -EINVAL;
	2084	}
	2085
	2086	etdm_data->mclk_apll = apll;
	2087	etdm_data->mclk_freq = freq;
	2088
	2089	return 0;
	2090	}
	2091
	2092	static int mtk_dai_etdm_set_sysclk(struct snd_soc_dai *dai,
	2093	int clk_id, unsigned int freq, int dir)
	2094	{
	2095	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	2096	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	2097	struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id];
	2098	int dai_id;
	2099
	2100	dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n",
	2101	__func__, dai->id, freq, dir);
	2102	if (is_cowork_mode(dai))
	2103	dai_id = get_etdm_cowork_master_id(dai);
	2104	else
	2105	dai_id = dai->id;
	2106
	2107	etdm_data = afe_priv->dai_priv[dai_id];
	2108	etdm_data->mclk_dir = dir;
	2109	return mtk_dai_etdm_cal_mclk(afe, freq, dai_id);
	2110	}
	2111
	2112	static int mtk_dai_etdm_set_tdm_slot(struct snd_soc_dai *dai,
	2113	unsigned int tx_mask, unsigned int rx_mask,
	2114	int slots, int slot_width)
	2115	{
	2116	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	2117	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	2118	struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id];
	2119
	2120	dev_dbg(dai->dev, "%s id %d slot_width %d\n",
	2121	__func__, dai->id, slot_width);
	2122
	2123	etdm_data->slots = slots;
	2124	etdm_data->lrck_width = slot_width;
	2125	return 0;
	2126	}
	2127
	2128	static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
	2129	{
	2130	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	2131	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	2132	struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id];
	2133
	2134	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	2135	case SND_SOC_DAIFMT_I2S:
	2136	etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S;
	2137	break;
	2138	case SND_SOC_DAIFMT_LEFT_J:
	2139	etdm_data->format = MTK_DAI_ETDM_FORMAT_LJ;
	2140	break;
	2141	case SND_SOC_DAIFMT_RIGHT_J:
	2142	etdm_data->format = MTK_DAI_ETDM_FORMAT_RJ;
	2143	break;
	2144	case SND_SOC_DAIFMT_DSP_A:
	2145	etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA;
	2146	break;
	2147	case SND_SOC_DAIFMT_DSP_B:
	2148	etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB;
	2149	break;
	2150	default:
	2151	return -EINVAL;
	2152	}
	2153
	2154	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	2155	case SND_SOC_DAIFMT_NB_NF:
	2156	etdm_data->bck_inv = false;
	2157	etdm_data->lrck_inv = false;
	2158	break;
	2159	case SND_SOC_DAIFMT_NB_IF:
	2160	etdm_data->bck_inv = false;
	2161	etdm_data->lrck_inv = true;
	2162	break;
	2163	case SND_SOC_DAIFMT_IB_NF:
	2164	etdm_data->bck_inv = true;
	2165	etdm_data->lrck_inv = false;
	2166	break;
	2167	case SND_SOC_DAIFMT_IB_IF:
	2168	etdm_data->bck_inv = true;
	2169	etdm_data->lrck_inv = true;
	2170	break;
	2171	default:
	2172	return -EINVAL;
	2173	}
	2174
	2175	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	2176	case SND_SOC_DAIFMT_CBM_CFM:
	2177	etdm_data->slave_mode = true;
	2178	break;
	2179	case SND_SOC_DAIFMT_CBS_CFS:
	2180	etdm_data->slave_mode = false;
	2181	break;
	2182	default:
	2183	return -EINVAL;
	2184	}
	2185
	2186	return 0;
	2187	}
	2188
	2189	static int mtk_dai_hdmitx_dptx_startup(struct snd_pcm_substream *substream,
	2190	struct snd_soc_dai *dai)
	2191	{
	2192	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	2193	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	2194	int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id);
	2195
	2196	if (cg_id >= 0)
	2197	mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]);
	2198
	2199	mtk_dai_etdm_enable_mclk(afe, dai->id);
	2200
	2201	return 0;
	2202	}
	2203
	2204	static void mtk_dai_hdmitx_dptx_shutdown(struct snd_pcm_substream *substream,
	2205	struct snd_soc_dai *dai)
	2206	{
	2207	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	2208	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	2209	int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id);
	2210
	2211	mtk_dai_etdm_disable_mclk(afe, dai->id);
	2212
	2213	if (cg_id >= 0)
	2214	mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]);
	2215	}
	2216
	2217	static unsigned int mtk_dai_get_dptx_ch_en(unsigned int channel)
	2218	{
	2219	switch (channel) {
	2220	case 1 ... 2:
	2221	return AFE_DPTX_CON_CH_EN_2CH;
	2222	case 3 ... 4:
	2223	return AFE_DPTX_CON_CH_EN_4CH;
	2224	case 5 ... 6:
	2225	return AFE_DPTX_CON_CH_EN_6CH;
	2226	case 7 ... 8:
	2227	return AFE_DPTX_CON_CH_EN_8CH;
	2228	default:
	2229	return AFE_DPTX_CON_CH_EN_2CH;
	2230	}
	2231	}
	2232
	2233	static unsigned int mtk_dai_get_dptx_ch(unsigned int ch)
	2234	{
	2235	return (ch > 2) ?
	2236	AFE_DPTX_CON_CH_NUM_8CH : AFE_DPTX_CON_CH_NUM_2CH;
	2237	}
	2238
	2239	static unsigned int mtk_dai_get_dptx_wlen(snd_pcm_format_t format)
	2240	{
	2241	return snd_pcm_format_physical_width(format) <= 16 ?
	2242	AFE_DPTX_CON_16BIT : AFE_DPTX_CON_24BIT;
	2243	}
	2244
	2245	static int mtk_dai_hdmitx_dptx_hw_params(struct snd_pcm_substream *substream,
	2246	struct snd_pcm_hw_params *params,
	2247	struct snd_soc_dai *dai)
	2248	{
	2249	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	2250	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	2251	struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id];
	2252	unsigned int rate = params_rate(params);
	2253	unsigned int channels = params_channels(params);
	2254	snd_pcm_format_t format = params_format(params);
	2255	int width = snd_pcm_format_physical_width(format);
	2256	int ret = 0;
	2257
	2258	/* dptx configure */
	2259	if (dai->id == MT8195_AFE_IO_DPTX) {
	2260	regmap_update_bits(afe->regmap, AFE_DPTX_CON,
	2261	AFE_DPTX_CON_CH_EN_MASK,
	2262	mtk_dai_get_dptx_ch_en(channels));
	2263	regmap_update_bits(afe->regmap, AFE_DPTX_CON,
	2264	AFE_DPTX_CON_CH_NUM_MASK,
	2265	mtk_dai_get_dptx_ch(channels));
	2266	regmap_update_bits(afe->regmap, AFE_DPTX_CON,
	2267	AFE_DPTX_CON_16BIT_MASK,
	2268	mtk_dai_get_dptx_wlen(format));
	2269
	2270	if (mtk_dai_get_dptx_ch(channels) == AFE_DPTX_CON_CH_NUM_8CH) {
	2271	etdm_data->data_mode = MTK_DAI_ETDM_DATA_ONE_PIN;
	2272	channels = 8;
	2273	} else {
	2274	channels = 2;
	2275	}
	2276	} else {
	2277	etdm_data->data_mode = MTK_DAI_ETDM_DATA_MULTI_PIN;
	2278	}
	2279
	2280	ret = mtk_dai_etdm_mclk_configure(afe, dai->id);
	2281	if (ret)
	2282	return ret;
	2283
	2284	ret = mtk_dai_etdm_configure(afe, rate, channels, width, dai->id);
	2285
	2286	return ret;
	2287	}
	2288
	2289	static int mtk_dai_hdmitx_dptx_trigger(struct snd_pcm_substream *substream,
	2290	int cmd,
	2291	struct snd_soc_dai *dai)
	2292	{
	2293	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	2294	int ret = 0;
	2295
	2296	dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id);
	2297
	2298	switch (cmd) {
	2299	case SNDRV_PCM_TRIGGER_START:
	2300	case SNDRV_PCM_TRIGGER_RESUME:
	2301	/* enable dptx interface */
	2302	if (dai->id == MT8195_AFE_IO_DPTX)
	2303	regmap_update_bits(afe->regmap, AFE_DPTX_CON,
	2304	AFE_DPTX_CON_ON_MASK,
	2305	AFE_DPTX_CON_ON);
	2306
	2307	/* enable etdm_out3 */
	2308	ret = mt8195_afe_enable_etdm(afe, dai->id);
	2309	break;
	2310	case SNDRV_PCM_TRIGGER_STOP:
	2311	case SNDRV_PCM_TRIGGER_SUSPEND:
	2312	/* disable etdm_out3 */
	2313	ret = mt8195_afe_disable_etdm(afe, dai->id);
	2314
	2315	/* disable dptx interface */
	2316	if (dai->id == MT8195_AFE_IO_DPTX)
	2317	regmap_update_bits(afe->regmap, AFE_DPTX_CON,
	2318	AFE_DPTX_CON_ON_MASK, 0);
	2319	break;
	2320	default:
	2321	return -EINVAL;
	2322	}
	2323
	2324	return ret;
	2325	}
	2326
	2327	static int mtk_dai_hdmitx_dptx_set_sysclk(struct snd_soc_dai *dai,
	2328	int clk_id,
	2329	unsigned int freq,
	2330	int dir)
	2331	{
	2332	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	2333	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	2334	struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id];
	2335
	2336	dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n",
	2337	__func__, dai->id, freq, dir);
	2338
	2339	etdm_data->mclk_dir = dir;
	2340	return mtk_dai_etdm_cal_mclk(afe, freq, dai->id);
	2341	}
	2342
	2343	static const struct snd_soc_dai_ops mtk_dai_etdm_ops = {
	2344	.startup = mtk_dai_etdm_startup,
	2345	.shutdown = mtk_dai_etdm_shutdown,
	2346	.hw_params = mtk_dai_etdm_hw_params,
	2347	.trigger = mtk_dai_etdm_trigger,
	2348	.set_sysclk = mtk_dai_etdm_set_sysclk,
	2349	.set_fmt = mtk_dai_etdm_set_fmt,
	2350	.set_tdm_slot = mtk_dai_etdm_set_tdm_slot,
	2351	};
	2352
	2353	static const struct snd_soc_dai_ops mtk_dai_hdmitx_dptx_ops = {
	2354	.startup = mtk_dai_hdmitx_dptx_startup,
	2355	.shutdown = mtk_dai_hdmitx_dptx_shutdown,
	2356	.hw_params = mtk_dai_hdmitx_dptx_hw_params,
	2357	.trigger = mtk_dai_hdmitx_dptx_trigger,
	2358	.set_sysclk = mtk_dai_hdmitx_dptx_set_sysclk,
	2359	.set_fmt = mtk_dai_etdm_set_fmt,
	2360	};
	2361
	2362	/* dai driver */
	2363	#define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_384000)
	2364
	2365	#define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE \|\
	2366	SNDRV_PCM_FMTBIT_S24_LE \|\
	2367	SNDRV_PCM_FMTBIT_S32_LE)
	2368
	2369	static int mtk_dai_etdm_probe(struct snd_soc_dai *dai)
	2370	{
	2371	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	2372	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	2373	struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id];
	2374
	2375	dev_dbg(dai->dev, "%s id %d\n", __func__, dai->id);
	2376
	2377	if (etdm_data->mclk_freq) {
	2378	dev_dbg(afe->dev, "MCLK always on, rate %d\n",
	2379	etdm_data->mclk_freq);
	2380	pm_runtime_get_sync(afe->dev);
	2381	mtk_dai_etdm_mclk_configure(afe, dai->id);
	2382	mtk_dai_etdm_enable_mclk(afe, dai->id);
	2383	pm_runtime_put_sync(afe->dev);
	2384	}
	2385	return 0;
	2386	}
	2387
	2388	static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = {
	2389	{
	2390	.name = "DPTX",
	2391	.id = MT8195_AFE_IO_DPTX,
	2392	.playback = {
	2393	.stream_name = "DPTX Playback",
	2394	.channels_min = 1,
	2395	.channels_max = 8,
	2396	.rates = MTK_ETDM_RATES,
	2397	.formats = MTK_ETDM_FORMATS,
	2398	},
	2399	.ops = &mtk_dai_hdmitx_dptx_ops,
	2400	},
	2401	{
	2402	.name = "ETDM1_IN",
	2403	.id = MT8195_AFE_IO_ETDM1_IN,
	2404	.capture = {
	2405	.stream_name = "ETDM1 Capture",
	2406	.channels_min = 1,
	2407	.channels_max = 24,
	2408	.rates = MTK_ETDM_RATES,
	2409	.formats = MTK_ETDM_FORMATS,
	2410	},
	2411	.ops = &mtk_dai_etdm_ops,
	2412	.probe = mtk_dai_etdm_probe,
	2413	},
	2414	{
	2415	.name = "ETDM2_IN",
	2416	.id = MT8195_AFE_IO_ETDM2_IN,
	2417	.capture = {
	2418	.stream_name = "ETDM2 Capture",
	2419	.channels_min = 1,
	2420	.channels_max = 16,
	2421	.rates = MTK_ETDM_RATES,
	2422	.formats = MTK_ETDM_FORMATS,
	2423	},
	2424	.ops = &mtk_dai_etdm_ops,
	2425	.probe = mtk_dai_etdm_probe,
	2426	},
	2427	{
	2428	.name = "ETDM1_OUT",
	2429	.id = MT8195_AFE_IO_ETDM1_OUT,
	2430	.playback = {
	2431	.stream_name = "ETDM1 Playback",
	2432	.channels_min = 1,
	2433	.channels_max = 24,
	2434	.rates = MTK_ETDM_RATES,
	2435	.formats = MTK_ETDM_FORMATS,
	2436	},
	2437	.ops = &mtk_dai_etdm_ops,
	2438	.probe = mtk_dai_etdm_probe,
	2439	},
	2440	{
	2441	.name = "ETDM2_OUT",
	2442	.id = MT8195_AFE_IO_ETDM2_OUT,
	2443	.playback = {
	2444	.stream_name = "ETDM2 Playback",
	2445	.channels_min = 1,
	2446	.channels_max = 24,
	2447	.rates = MTK_ETDM_RATES,
	2448	.formats = MTK_ETDM_FORMATS,
	2449	},
	2450	.ops = &mtk_dai_etdm_ops,
	2451	.probe = mtk_dai_etdm_probe,
	2452	},
	2453	{
	2454	.name = "ETDM3_OUT",
	2455	.id = MT8195_AFE_IO_ETDM3_OUT,
	2456	.playback = {
	2457	.stream_name = "ETDM3 Playback",
	2458	.channels_min = 1,
	2459	.channels_max = 8,
	2460	.rates = MTK_ETDM_RATES,
	2461	.formats = MTK_ETDM_FORMATS,
	2462	},
	2463	.ops = &mtk_dai_hdmitx_dptx_ops,
	2464	.probe = mtk_dai_etdm_probe,
	2465	},
	2466	};
	2467
	2468	static void mt8195_etdm_update_sync_info(struct mtk_base_afe *afe)
	2469	{
	2470	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	2471	struct mtk_dai_etdm_priv *etdm_data;
	2472	struct mtk_dai_etdm_priv *mst_data;
	2473	int i;
	2474	int mst_dai_id;
	2475
	2476	for (i = MT8195_AFE_IO_ETDM_START; i < MT8195_AFE_IO_ETDM_END; i++) {
	2477	etdm_data = afe_priv->dai_priv[i];
	2478	if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) {
	2479	mst_dai_id = etdm_data->cowork_source_id;
	2480	mst_data = afe_priv->dai_priv[mst_dai_id];
	2481	if (mst_data->cowork_source_id != COWORK_ETDM_NONE)
	2482	dev_info(afe->dev, "%s [%d] wrong sync source\n"
	2483	, __func__, i);
	2484	mst_data->cowork_slv_id[mst_data->cowork_slv_count] = i;
	2485	mst_data->cowork_slv_count++;
	2486	}
	2487	}
	2488	}
	2489
	2490	static void mt8195_dai_etdm_parse_of(struct mtk_base_afe *afe)
	2491	{
	2492	const struct device_node *of_node = afe->dev->of_node;
	2493	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	2494	struct mtk_dai_etdm_priv *etdm_data;
	2495	int i, j;
	2496	char prop[48];
	2497	u8 disable_chn[MT8195_ETDM_MAX_CHANNELS];
	2498	int max_chn = MT8195_ETDM_MAX_CHANNELS;
	2499	u32 sel;
	2500	int ret;
	2501	int dai_id;
	2502	unsigned int sync_id;
	2503	struct {
	2504	const char *name;
	2505	const unsigned int sync_id;
	2506	} of_afe_etdms[MT8195_AFE_IO_ETDM_NUM] = {
	2507	{"etdm-in1", ETDM_SYNC_FROM_IN1},
	2508	{"etdm-in2", ETDM_SYNC_FROM_IN2},
	2509	{"etdm-out1", ETDM_SYNC_FROM_OUT1},
	2510	{"etdm-out2", ETDM_SYNC_FROM_OUT2},
	2511	{"etdm-out3", ETDM_SYNC_FROM_OUT3},
	2512	};
	2513
	2514	for (i = 0; i < MT8195_AFE_IO_ETDM_NUM; i++) {
	2515	dai_id = ETDM_TO_DAI_ID(i);
	2516	etdm_data = afe_priv->dai_priv[dai_id];
	2517
	2518	ret = snprintf(prop, sizeof(prop),
	2519	"mediatek,%s-mclk-always-on-rate",
	2520	of_afe_etdms[i].name);
	2521	if (ret < 0) {
	2522	dev_info(afe->dev, "%s snprintf err=%d\n",
	2523	__func__, ret);
	2524	return;
	2525	}
	2526	ret = of_property_read_u32(of_node, prop, &sel);
	2527	if (ret == 0) {
	2528	etdm_data->mclk_dir = SND_SOC_CLOCK_OUT;
	2529	if (mtk_dai_etdm_cal_mclk(afe, sel, dai_id))
	2530	dev_info(afe->dev, "%s unsupported mclk %uHz\n",
	2531	__func__, sel);
	2532	}
	2533
	2534	ret = snprintf(prop, sizeof(prop),
	2535	"mediatek,%s-multi-pin-mode",
	2536	of_afe_etdms[i].name);
	2537	if (ret < 0) {
	2538	dev_info(afe->dev, "%s snprintf err=%d\n",
	2539	__func__, ret);
	2540	return;
	2541	}
	2542	etdm_data->data_mode = of_property_read_bool(of_node, prop);
	2543
	2544	ret = snprintf(prop, sizeof(prop),
	2545	"mediatek,%s-cowork-source",
	2546	of_afe_etdms[i].name);
	2547	if (ret < 0) {
	2548	dev_info(afe->dev, "%s snprintf err=%d\n",
	2549	__func__, ret);
	2550	return;
	2551	}
	2552	ret = of_property_read_u32(of_node, prop, &sel);
	2553	if (ret == 0) {
	2554	if (sel >= MT8195_AFE_IO_ETDM_NUM) {
	2555	dev_info(afe->dev, "%s invalid id=%d\n",
	2556	__func__, sel);
	2557	etdm_data->cowork_source_id = COWORK_ETDM_NONE;
	2558	} else {
	2559	sync_id = of_afe_etdms[sel].sync_id;
	2560	etdm_data->cowork_source_id =
	2561	sync_to_dai_id(sync_id);
	2562	}
	2563	} else {
	2564	etdm_data->cowork_source_id = COWORK_ETDM_NONE;
	2565	}
	2566	}
	2567
	2568	/* etdm in only */
	2569	for (i = 0; i < 2; i++) {
	2570	ret = snprintf(prop, sizeof(prop),
	2571	"mediatek,%s-chn-disabled",
	2572	of_afe_etdms[i].name);
	2573	if (ret < 0) {
	2574	dev_info(afe->dev, "%s snprintf err=%d\n",
	2575	__func__, ret);
	2576	return;
	2577	}
	2578	ret = of_property_read_variable_u8_array(of_node, prop,
	2579	disable_chn,
	2580	1, max_chn);
	2581	if (ret < 0)
	2582	continue;
	2583
	2584	for (j = 0; j < ret; j++) {
	2585	if (disable_chn[j] >= MT8195_ETDM_MAX_CHANNELS)
	2586	dev_info(afe->dev, "%s [%d] invalid chn %u\n",
	2587	__func__, j, disable_chn[j]);
	2588	else
	2589	etdm_data->in_disable_ch[disable_chn[j]] = true;
	2590	}
	2591	}
	2592	mt8195_etdm_update_sync_info(afe);
	2593	}
	2594
	2595	static int init_etdm_priv_data(struct mtk_base_afe *afe)
	2596	{
	2597	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	2598	struct mtk_dai_etdm_priv *etdm_priv;
	2599	int i;
	2600
	2601	for (i = MT8195_AFE_IO_ETDM_START; i < MT8195_AFE_IO_ETDM_END; i++) {
	2602	etdm_priv = devm_kzalloc(afe->dev,
	2603	sizeof(struct mtk_dai_etdm_priv),
	2604	GFP_KERNEL);
	2605	if (!etdm_priv)
	2606	return -ENOMEM;
	2607
	2608	afe_priv->dai_priv[i] = etdm_priv;
	2609	}
	2610
	2611	afe_priv->dai_priv[MT8195_AFE_IO_DPTX] =
	2612	afe_priv->dai_priv[MT8195_AFE_IO_ETDM3_OUT];
	2613
	2614	mt8195_dai_etdm_parse_of(afe);
	2615	return 0;
	2616	}
	2617
	2618	int mt8195_dai_etdm_register(struct mtk_base_afe *afe)
	2619	{
	2620	struct mtk_base_afe_dai *dai;
	2621
	2622	dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
	2623	if (!dai)
	2624	return -ENOMEM;
	2625
	2626	list_add(&dai->list, &afe->sub_dais);
	2627
	2628	dai->dai_drivers = mtk_dai_etdm_driver;
	2629	dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver);
	2630
	2631	dai->dapm_widgets = mtk_dai_etdm_widgets;
	2632	dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets);
	2633	dai->dapm_routes = mtk_dai_etdm_routes;
	2634	dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes);
	2635	dai->controls = mtk_dai_etdm_controls;
	2636	dai->num_controls = ARRAY_SIZE(mtk_dai_etdm_controls);
	2637
	2638	return init_etdm_priv_data(afe);
	2639	}

sound/soc/mediatek/mt8195/mt8195-dai-pcm.c+389−0

@@ -0,0 +1,389 @@
	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* MediaTek ALSA SoC Audio DAI PCM I/F Control
	4	*
	5	* Copyright (c) 2020 MediaTek Inc.
	6	* Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
	7	* Trevor Wu <trevor.wu@mediatek.com>
	8	*/
	9
	10	#include <linux/regmap.h>
	11	#include <sound/pcm_params.h>
	12	#include "mt8195-afe-clk.h"
	13	#include "mt8195-afe-common.h"
	14	#include "mt8195-reg.h"
	15
	16	enum {
	17	MTK_DAI_PCM_FMT_I2S,
	18	MTK_DAI_PCM_FMT_EIAJ,
	19	MTK_DAI_PCM_FMT_MODEA,
	20	MTK_DAI_PCM_FMT_MODEB,
	21	};
	22
	23	enum {
	24	MTK_DAI_PCM_CLK_A1SYS,
	25	MTK_DAI_PCM_CLK_A2SYS,
	26	MTK_DAI_PCM_CLK_26M_48K,
	27	MTK_DAI_PCM_CLK_26M_441K,
	28	};
	29
	30	struct mtk_dai_pcm_rate {
	31	unsigned int rate;
	32	unsigned int reg_value;
	33	};
	34
	35	struct mtk_dai_pcmif_priv {
	36	unsigned int slave_mode;
	37	unsigned int lrck_inv;
	38	unsigned int bck_inv;
	39	unsigned int format;
	40	};
	41
	42	static const struct mtk_dai_pcm_rate mtk_dai_pcm_rates[] = {
	43	{ .rate = 8000, .reg_value = 0, },
	44	{ .rate = 16000, .reg_value = 1, },
	45	{ .rate = 32000, .reg_value = 2, },
	46	{ .rate = 48000, .reg_value = 3, },
	47	{ .rate = 11025, .reg_value = 1, },
	48	{ .rate = 22050, .reg_value = 2, },
	49	{ .rate = 44100, .reg_value = 3, },
	50	};
	51
	52	static int mtk_dai_pcm_mode(unsigned int rate)
	53	{
	54	int i;
	55
	56	for (i = 0; i < ARRAY_SIZE(mtk_dai_pcm_rates); i++)
	57	if (mtk_dai_pcm_rates[i].rate == rate)
	58	return mtk_dai_pcm_rates[i].reg_value;
	59
	60	return -EINVAL;
	61	}
	62
	63	static const struct snd_kcontrol_new mtk_dai_pcm_o000_mix[] = {
	64	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN0, 0, 1, 0),
	65	SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN0_2, 6, 1, 0),
	66	};
	67
	68	static const struct snd_kcontrol_new mtk_dai_pcm_o001_mix[] = {
	69	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN1, 1, 1, 0),
	70	SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN1_2, 7, 1, 0),
	71	};
	72
	73	static const struct snd_soc_dapm_widget mtk_dai_pcm_widgets[] = {
	74	SND_SOC_DAPM_MIXER("I002", SND_SOC_NOPM, 0, 0, NULL, 0),
	75	SND_SOC_DAPM_MIXER("I003", SND_SOC_NOPM, 0, 0, NULL, 0),
	76	SND_SOC_DAPM_MIXER("O000", SND_SOC_NOPM, 0, 0,
	77	mtk_dai_pcm_o000_mix,
	78	ARRAY_SIZE(mtk_dai_pcm_o000_mix)),
	79	SND_SOC_DAPM_MIXER("O001", SND_SOC_NOPM, 0, 0,
	80	mtk_dai_pcm_o001_mix,
	81	ARRAY_SIZE(mtk_dai_pcm_o001_mix)),
	82
	83	SND_SOC_DAPM_INPUT("PCM1_INPUT"),
	84	SND_SOC_DAPM_OUTPUT("PCM1_OUTPUT"),
	85	};
	86
	87	static const struct snd_soc_dapm_route mtk_dai_pcm_routes[] = {
	88	{"I002", NULL, "PCM1 Capture"},
	89	{"I003", NULL, "PCM1 Capture"},
	90
	91	{"O000", "I000 Switch", "I000"},
	92	{"O001", "I001 Switch", "I001"},
	93
	94	{"O000", "I070 Switch", "I070"},
	95	{"O001", "I071 Switch", "I071"},
	96
	97	{"PCM1 Playback", NULL, "O000"},
	98	{"PCM1 Playback", NULL, "O001"},
	99
	100	{"PCM1_OUTPUT", NULL, "PCM1 Playback"},
	101	{"PCM1 Capture", NULL, "PCM1_INPUT"},
	102	};
	103
	104	static void mtk_dai_pcm_enable(struct mtk_base_afe *afe)
	105	{
	106	regmap_update_bits(afe->regmap, PCM_INTF_CON1,
	107	PCM_INTF_CON1_PCM_EN, PCM_INTF_CON1_PCM_EN);
	108	}
	109
	110	static void mtk_dai_pcm_disable(struct mtk_base_afe *afe)
	111	{
	112	regmap_update_bits(afe->regmap, PCM_INTF_CON1,
	113	PCM_INTF_CON1_PCM_EN, 0x0);
	114	}
	115
	116	static int mtk_dai_pcm_configure(struct snd_pcm_substream *substream,
	117	struct snd_soc_dai *dai)
	118	{
	119	struct snd_pcm_runtime * const runtime = substream->runtime;
	120	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	121	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	122	struct mtk_dai_pcmif_priv *pcmif_priv = afe_priv->dai_priv[dai->id];
	123	unsigned int slave_mode = pcmif_priv->slave_mode;
	124	unsigned int lrck_inv = pcmif_priv->lrck_inv;
	125	unsigned int bck_inv = pcmif_priv->bck_inv;
	126	unsigned int fmt = pcmif_priv->format;
	127	unsigned int bit_width = dai->sample_bits;
	128	unsigned int val = 0;
	129	unsigned int mask = 0;
	130	int fs = 0;
	131	int mode = 0;
	132
	133	/* sync freq mode */
	134	fs = mt8195_afe_fs_timing(runtime->rate);
	135	if (fs < 0)
	136	return -EINVAL;
	137	val \|= PCM_INTF_CON2_SYNC_FREQ_MODE(fs);
	138	mask \|= PCM_INTF_CON2_SYNC_FREQ_MODE_MASK;
	139
	140	/* clk domain sel */
	141	if (runtime->rate % 8000)
	142	val \|= PCM_INTF_CON2_CLK_DOMAIN_SEL(MTK_DAI_PCM_CLK_26M_441K);
	143	else
	144	val \|= PCM_INTF_CON2_CLK_DOMAIN_SEL(MTK_DAI_PCM_CLK_26M_48K);
	145	mask \|= PCM_INTF_CON2_CLK_DOMAIN_SEL_MASK;
	146
	147	regmap_update_bits(afe->regmap, PCM_INTF_CON2, mask, val);
	148
	149	val = 0;
	150	mask = 0;
	151
	152	/* pcm mode */
	153	mode = mtk_dai_pcm_mode(runtime->rate);
	154	if (mode < 0)
	155	return -EINVAL;
	156	val \|= PCM_INTF_CON1_PCM_MODE(mode);
	157	mask \|= PCM_INTF_CON1_PCM_MODE_MASK;
	158
	159	/* pcm format */
	160	val \|= PCM_INTF_CON1_PCM_FMT(fmt);
	161	mask \|= PCM_INTF_CON1_PCM_FMT_MASK;
	162
	163	/* pcm sync length */
	164	if (fmt == MTK_DAI_PCM_FMT_MODEA \|\|
	165	fmt == MTK_DAI_PCM_FMT_MODEB)
	166	val \|= PCM_INTF_CON1_SYNC_LENGTH(1);
	167	else
	168	val \|= PCM_INTF_CON1_SYNC_LENGTH(bit_width);
	169	mask \|= PCM_INTF_CON1_SYNC_LENGTH_MASK;
	170
	171	/* pcm bits, word length */
	172	if (bit_width > 16) {
	173	val \|= PCM_INTF_CON1_PCM_24BIT;
	174	val \|= PCM_INTF_CON1_PCM_WLEN_64BCK;
	175	} else {
	176	val \|= PCM_INTF_CON1_PCM_16BIT;
	177	val \|= PCM_INTF_CON1_PCM_WLEN_32BCK;
	178	}
	179	mask \|= PCM_INTF_CON1_PCM_BIT_MASK;
	180	mask \|= PCM_INTF_CON1_PCM_WLEN_MASK;
	181
	182	/* master/slave */
	183	if (!slave_mode) {
	184	val \|= PCM_INTF_CON1_PCM_MASTER;
	185
	186	if (lrck_inv)
	187	val \|= PCM_INTF_CON1_SYNC_OUT_INV;
	188	if (bck_inv)
	189	val \|= PCM_INTF_CON1_BCLK_OUT_INV;
	190	mask \|= PCM_INTF_CON1_CLK_OUT_INV_MASK;
	191	} else {
	192	val \|= PCM_INTF_CON1_PCM_SLAVE;
	193
	194	if (lrck_inv)
	195	val \|= PCM_INTF_CON1_SYNC_IN_INV;
	196	if (bck_inv)
	197	val \|= PCM_INTF_CON1_BCLK_IN_INV;
	198	mask \|= PCM_INTF_CON1_CLK_IN_INV_MASK;
	199
	200	/* TODO: add asrc setting for slave mode */
	201	}
	202	mask \|= PCM_INTF_CON1_PCM_M_S_MASK;
	203
	204	regmap_update_bits(afe->regmap, PCM_INTF_CON1, mask, val);
	205
	206	return 0;
	207	}
	208
	209	/* dai ops */
	210	static int mtk_dai_pcm_startup(struct snd_pcm_substream *substream,
	211	struct snd_soc_dai *dai)
	212	{
	213	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	214	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	215
	216	if (dai->component->active)
	217	return 0;
	218
	219	mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_ASRC11]);
	220	mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_ASRC12]);
	221	mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_PCMIF]);
	222
	223	return 0;
	224	}
	225
	226	static void mtk_dai_pcm_shutdown(struct snd_pcm_substream *substream,
	227	struct snd_soc_dai *dai)
	228	{
	229	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	230	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	231
	232	if (dai->component->active)
	233	return;
	234
	235	mtk_dai_pcm_disable(afe);
	236
	237	mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_PCMIF]);
	238	mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_ASRC12]);
	239	mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_ASRC11]);
	240	}
	241
	242	static int mtk_dai_pcm_prepare(struct snd_pcm_substream *substream,
	243	struct snd_soc_dai *dai)
	244	{
	245	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	246	int ret = 0;
	247
	248	if (snd_soc_dai_stream_active(dai, SNDRV_PCM_STREAM_PLAYBACK) &&
	249	snd_soc_dai_stream_active(dai, SNDRV_PCM_STREAM_CAPTURE))
	250	return 0;
	251
	252	ret = mtk_dai_pcm_configure(substream, dai);
	253	if (ret)
	254	return ret;
	255
	256	mtk_dai_pcm_enable(afe);
	257
	258	return 0;
	259	}
	260
	261	static int mtk_dai_pcm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
	262	{
	263	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
	264	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	265	struct mtk_dai_pcmif_priv *pcmif_priv = afe_priv->dai_priv[dai->id];
	266
	267	dev_dbg(dai->dev, "%s fmt 0x%x\n", __func__, fmt);
	268
	269	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	270	case SND_SOC_DAIFMT_I2S:
	271	pcmif_priv->format = MTK_DAI_PCM_FMT_I2S;
	272	break;
	273	case SND_SOC_DAIFMT_DSP_A:
	274	pcmif_priv->format = MTK_DAI_PCM_FMT_MODEA;
	275	break;
	276	case SND_SOC_DAIFMT_DSP_B:
	277	pcmif_priv->format = MTK_DAI_PCM_FMT_MODEB;
	278	break;
	279	default:
	280	return -EINVAL;
	281	}
	282
	283	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	284	case SND_SOC_DAIFMT_NB_NF:
	285	pcmif_priv->bck_inv = 0;
	286	pcmif_priv->lrck_inv = 0;
	287	break;
	288	case SND_SOC_DAIFMT_NB_IF:
	289	pcmif_priv->bck_inv = 0;
	290	pcmif_priv->lrck_inv = 1;
	291	break;
	292	case SND_SOC_DAIFMT_IB_NF:
	293	pcmif_priv->bck_inv = 1;
	294	pcmif_priv->lrck_inv = 0;
	295	break;
	296	case SND_SOC_DAIFMT_IB_IF:
	297	pcmif_priv->bck_inv = 1;
	298	pcmif_priv->lrck_inv = 1;
	299	break;
	300	default:
	301	return -EINVAL;
	302	}
	303
	304	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	305	case SND_SOC_DAIFMT_CBM_CFM:
	306	pcmif_priv->slave_mode = 1;
	307	break;
	308	case SND_SOC_DAIFMT_CBS_CFS:
	309	pcmif_priv->slave_mode = 0;
	310	break;
	311	default:
	312	return -EINVAL;
	313	}
	314
	315	return 0;
	316	}
	317
	318	static const struct snd_soc_dai_ops mtk_dai_pcm_ops = {
	319	.startup = mtk_dai_pcm_startup,
	320	.shutdown = mtk_dai_pcm_shutdown,
	321	.prepare = mtk_dai_pcm_prepare,
	322	.set_fmt = mtk_dai_pcm_set_fmt,
	323	};
	324
	325	/* dai driver */
	326	#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000)
	327
	328	#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE \|\
	329	SNDRV_PCM_FMTBIT_S24_LE \|\
	330	SNDRV_PCM_FMTBIT_S32_LE)
	331
	332	static struct snd_soc_dai_driver mtk_dai_pcm_driver[] = {
	333	{
	334	.name = "PCM1",
	335	.id = MT8195_AFE_IO_PCM,
	336	.playback = {
	337	.stream_name = "PCM1 Playback",
	338	.channels_min = 1,
	339	.channels_max = 2,
	340	.rates = MTK_PCM_RATES,
	341	.formats = MTK_PCM_FORMATS,
	342	},
	343	.capture = {
	344	.stream_name = "PCM1 Capture",
	345	.channels_min = 1,
	346	.channels_max = 2,
	347	.rates = MTK_PCM_RATES,
	348	.formats = MTK_PCM_FORMATS,
	349	},
	350	.ops = &mtk_dai_pcm_ops,
	351	.symmetric_rate = 1,
	352	.symmetric_sample_bits = 1,
	353	},
	354	};
	355
	356	static int init_pcmif_priv_data(struct mtk_base_afe *afe)
	357	{
	358	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	359	struct mtk_dai_pcmif_priv *pcmif_priv;
	360
	361	pcmif_priv = devm_kzalloc(afe->dev, sizeof(struct mtk_dai_pcmif_priv),
	362	GFP_KERNEL);
	363	if (!pcmif_priv)
	364	return -ENOMEM;
	365
	366	afe_priv->dai_priv[MT8195_AFE_IO_PCM] = pcmif_priv;
	367	return 0;
	368	}
	369
	370	int mt8195_dai_pcm_register(struct mtk_base_afe *afe)
	371	{
	372	struct mtk_base_afe_dai *dai;
	373
	374	dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
	375	if (!dai)
	376	return -ENOMEM;
	377
	378	list_add(&dai->list, &afe->sub_dais);
	379
	380	dai->dai_drivers = mtk_dai_pcm_driver;
	381	dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_pcm_driver);
	382
	383	dai->dapm_widgets = mtk_dai_pcm_widgets;
	384	dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_pcm_widgets);
	385	dai->dapm_routes = mtk_dai_pcm_routes;
	386	dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_pcm_routes);
	387
	388	return init_pcmif_priv_data(afe);
	389	}

sound/soc/mediatek/mt8195/mt8195-mt6359-rt1019-rt5682.c+1087−0

@@ -0,0 +1,1087 @@
	1	// SPDX-License-Identifier: GPL-2.0
	2	//
	3	// mt8195-mt6359-rt1019-rt5682.c --
	4	// MT8195-MT6359-RT1019-RT6358 ALSA SoC machine driver
	5	//
	6	// Copyright (c) 2021 MediaTek Inc.
	7	// Author: Trevor Wu <trevor.wu@mediatek.com>
	8	//
	9
	10	#include <linux/input.h>
	11	#include <linux/module.h>
	12	#include <linux/pm_runtime.h>
	13	#include <sound/jack.h>
	14	#include <sound/pcm_params.h>
	15	#include <sound/rt5682.h>
	16	#include <sound/soc.h>
	17	#include "../../codecs/mt6359.h"
	18	#include "../../codecs/rt5682.h"
	19	#include "../common/mtk-afe-platform-driver.h"
	20	#include "mt8195-afe-common.h"
	21
	22	#define RT1019_CODEC_DAI "HiFi"
	23	#define RT1019_DEV0_NAME "rt1019p"
	24
	25	#define RT5682_CODEC_DAI "rt5682-aif1"
	26	#define RT5682_DEV0_NAME "rt5682.2-001a"
	27
	28	struct mt8195_mt6359_rt1019_rt5682_priv {
	29	struct snd_soc_jack headset_jack;
	30	struct snd_soc_jack dp_jack;
	31	struct snd_soc_jack hdmi_jack;
	32	};
	33
	34	static const struct snd_soc_dapm_widget
	35	mt8195_mt6359_rt1019_rt5682_widgets[] = {
	36	SND_SOC_DAPM_SPK("Speakers", NULL),
	37	SND_SOC_DAPM_HP("Headphone Jack", NULL),
	38	SND_SOC_DAPM_MIC("Headset Mic", NULL),
	39	};
	40
	41	static const struct snd_soc_dapm_route mt8195_mt6359_rt1019_rt5682_routes[] = {
	42	/* speaker */
	43	{ "Speakers", NULL, "Speaker" },
	44	/* headset */
	45	{ "Headphone Jack", NULL, "HPOL" },
	46	{ "Headphone Jack", NULL, "HPOR" },
	47	{ "IN1P", NULL, "Headset Mic" },
	48	};
	49
	50	static const struct snd_kcontrol_new mt8195_mt6359_rt1019_rt5682_controls[] = {
	51	SOC_DAPM_PIN_SWITCH("Speakers"),
	52	SOC_DAPM_PIN_SWITCH("Headphone Jack"),
	53	SOC_DAPM_PIN_SWITCH("Headset Mic"),
	54	};
	55
	56	static int mt8195_rt5682_etdm_hw_params(struct snd_pcm_substream *substream,
	57	struct snd_pcm_hw_params *params)
	58	{
	59	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	60	struct snd_soc_card *card = rtd->card;
	61	struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
	62	struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
	63	unsigned int rate = params_rate(params);
	64	unsigned int mclk_fs_ratio = 128;
	65	unsigned int mclk_fs = rate * mclk_fs_ratio;
	66	int bitwidth;
	67	int ret;
	68
	69	bitwidth = snd_pcm_format_width(params_format(params));
	70	if (bitwidth < 0) {
	71	dev_err(card->dev, "invalid bit width: %d\n", bitwidth);
	72	return bitwidth;
	73	}
	74
	75	ret = snd_soc_dai_set_tdm_slot(codec_dai, 0x00, 0x0, 0x2, bitwidth);
	76	if (ret) {
	77	dev_err(card->dev, "failed to set tdm slot\n");
	78	return ret;
	79	}
	80
	81	ret = snd_soc_dai_set_pll(codec_dai, RT5682_PLL1,
	82	RT5682_PLL1_S_BCLK1,
	83	params_rate(params) * 64,
	84	params_rate(params) * 512);
	85	if (ret) {
	86	dev_err(card->dev, "failed to set pll\n");
	87	return ret;
	88	}
	89
	90	ret = snd_soc_dai_set_sysclk(codec_dai,
	91	RT5682_SCLK_S_PLL1,
	92	params_rate(params) * 512,
	93	SND_SOC_CLOCK_IN);
	94	if (ret) {
	95	dev_err(card->dev, "failed to set sysclk\n");
	96	return ret;
	97	}
	98
	99	return snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_fs, SND_SOC_CLOCK_OUT);
	100	}
	101
	102	static const struct snd_soc_ops mt8195_rt5682_etdm_ops = {
	103	.hw_params = mt8195_rt5682_etdm_hw_params,
	104	};
	105
	106	#define CKSYS_AUD_TOP_CFG 0x032c
	107	#define CKSYS_AUD_TOP_MON 0x0330
	108
	109	static int mt8195_mt6359_mtkaif_calibration(struct snd_soc_pcm_runtime *rtd)
	110	{
	111	struct snd_soc_component *cmpnt_afe =
	112	snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
	113	struct snd_soc_component *cmpnt_codec =
	114	asoc_rtd_to_codec(rtd, 0)->component;
	115	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt_afe);
	116	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	117	struct mtkaif_param *param = &afe_priv->mtkaif_params;
	118	int phase;
	119	unsigned int monitor;
	120	int mtkaif_calibration_num_phase;
	121	int test_done_1, test_done_2, test_done_3;
	122	int cycle_1, cycle_2, cycle_3;
	123	int prev_cycle_1, prev_cycle_2, prev_cycle_3;
	124	int chosen_phase_1, chosen_phase_2, chosen_phase_3;
	125	int counter;
	126	bool mtkaif_calibration_ok;
	127	int mtkaif_chosen_phase[MT8195_MTKAIF_MISO_NUM];
	128	int mtkaif_phase_cycle[MT8195_MTKAIF_MISO_NUM];
	129	int i;
	130
	131	dev_info(afe->dev, "%s(), start\n", __func__);
	132
	133	param->mtkaif_calibration_ok = false;
	134	for (i = 0; i < MT8195_MTKAIF_MISO_NUM; i++) {
	135	param->mtkaif_chosen_phase[i] = -1;
	136	param->mtkaif_phase_cycle[i] = 0;
	137	mtkaif_chosen_phase[i] = -1;
	138	mtkaif_phase_cycle[i] = 0;
	139	}
	140
	141	if (IS_ERR(afe_priv->topckgen)) {
	142	dev_info(afe->dev, "%s() Cannot find topckgen controller\n",
	143	__func__);
	144	return 0;
	145	}
	146
	147	pm_runtime_get_sync(afe->dev);
	148	mt6359_mtkaif_calibration_enable(cmpnt_codec);
	149
	150	/* set test type to synchronizer pulse */
	151	regmap_update_bits(afe_priv->topckgen,
	152	CKSYS_AUD_TOP_CFG, 0xffff, 0x4);
	153	mtkaif_calibration_num_phase = 42; /* mt6359: 0 ~ 42 */
	154	mtkaif_calibration_ok = true;
	155
	156	for (phase = 0;
	157	phase <= mtkaif_calibration_num_phase && mtkaif_calibration_ok;
	158	phase++) {
	159	mt6359_set_mtkaif_calibration_phase(cmpnt_codec,
	160	phase, phase, phase);
	161
	162	regmap_update_bits(afe_priv->topckgen,
	163	CKSYS_AUD_TOP_CFG, 0x1, 0x1);
	164
	165	test_done_1 = 0;
	166	test_done_2 = 0;
	167	test_done_3 = 0;
	168	cycle_1 = -1;
	169	cycle_2 = -1;
	170	cycle_3 = -1;
	171	counter = 0;
	172	while (!(test_done_1 & test_done_2 & test_done_3)) {
	173	regmap_read(afe_priv->topckgen,
	174	CKSYS_AUD_TOP_MON, &monitor);
	175	test_done_1 = (monitor >> 28) & 0x1;
	176	test_done_2 = (monitor >> 29) & 0x1;
	177	test_done_3 = (monitor >> 30) & 0x1;
	178	if (test_done_1 == 1)
	179	cycle_1 = monitor & 0xf;
	180
	181	if (test_done_2 == 1)
	182	cycle_2 = (monitor >> 4) & 0xf;
	183
	184	if (test_done_3 == 1)
	185	cycle_3 = (monitor >> 8) & 0xf;
	186
	187	/* handle if never test done */
	188	if (++counter > 10000) {
	189	dev_info(afe->dev, "%s(), test fail, cycle_1 %d, cycle_2 %d, cycle_3 %d, monitor 0x%x\n",
	190	__func__,
	191	cycle_1, cycle_2, cycle_3, monitor);
	192	mtkaif_calibration_ok = false;
	193	break;
	194	}
	195	}
	196
	197	if (phase == 0) {
	198	prev_cycle_1 = cycle_1;
	199	prev_cycle_2 = cycle_2;
	200	prev_cycle_3 = cycle_3;
	201	}
	202
	203	if (cycle_1 != prev_cycle_1 &&
	204	mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0] < 0) {
	205	mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0] = phase - 1;
	206	mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0] = prev_cycle_1;
	207	}
	208
	209	if (cycle_2 != prev_cycle_2 &&
	210	mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1] < 0) {
	211	mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1] = phase - 1;
	212	mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1] = prev_cycle_2;
	213	}
	214
	215	if (cycle_3 != prev_cycle_3 &&
	216	mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2] < 0) {
	217	mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2] = phase - 1;
	218	mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2] = prev_cycle_3;
	219	}
	220
	221	regmap_update_bits(afe_priv->topckgen,
	222	CKSYS_AUD_TOP_CFG, 0x1, 0x0);
	223
	224	if (mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0] >= 0 &&
	225	mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1] >= 0 &&
	226	mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2] >= 0)
	227	break;
	228	}
	229
	230	if (mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0] < 0) {
	231	mtkaif_calibration_ok = false;
	232	chosen_phase_1 = 0;
	233	} else {
	234	chosen_phase_1 = mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0];
	235	}
	236
	237	if (mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1] < 0) {
	238	mtkaif_calibration_ok = false;
	239	chosen_phase_2 = 0;
	240	} else {
	241	chosen_phase_2 = mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1];
	242	}
	243
	244	if (mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2] < 0) {
	245	mtkaif_calibration_ok = false;
	246	chosen_phase_3 = 0;
	247	} else {
	248	chosen_phase_3 = mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2];
	249	}
	250
	251	mt6359_set_mtkaif_calibration_phase(cmpnt_codec,
	252	chosen_phase_1,
	253	chosen_phase_2,
	254	chosen_phase_3);
	255
	256	mt6359_mtkaif_calibration_disable(cmpnt_codec);
	257	pm_runtime_put(afe->dev);
	258
	259	param->mtkaif_calibration_ok = mtkaif_calibration_ok;
	260	param->mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0] = chosen_phase_1;
	261	param->mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1] = chosen_phase_2;
	262	param->mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2] = chosen_phase_3;
	263	for (i = 0; i < MT8195_MTKAIF_MISO_NUM; i++)
	264	param->mtkaif_phase_cycle[i] = mtkaif_phase_cycle[i];
	265
	266	dev_info(afe->dev, "%s(), end, calibration ok %d\n",
	267	__func__, param->mtkaif_calibration_ok);
	268
	269	return 0;
	270	}
	271
	272	static int mt8195_mt6359_init(struct snd_soc_pcm_runtime *rtd)
	273	{
	274	struct snd_soc_component *cmpnt_codec =
	275	asoc_rtd_to_codec(rtd, 0)->component;
	276
	277	/* set mtkaif protocol */
	278	mt6359_set_mtkaif_protocol(cmpnt_codec,
	279	MT6359_MTKAIF_PROTOCOL_2_CLK_P2);
	280
	281	/* mtkaif calibration */
	282	mt8195_mt6359_mtkaif_calibration(rtd);
	283
	284	return 0;
	285	}
	286
	287	static int mt8195_rt5682_init(struct snd_soc_pcm_runtime *rtd)
	288	{
	289	struct snd_soc_component *cmpnt_codec =
	290	asoc_rtd_to_codec(rtd, 0)->component;
	291	struct mt8195_mt6359_rt1019_rt5682_priv *priv =
	292	snd_soc_card_get_drvdata(rtd->card);
	293	struct snd_soc_jack *jack = &priv->headset_jack;
	294	int ret;
	295
	296	ret = snd_soc_card_jack_new(rtd->card, "Headset Jack",
	297	SND_JACK_HEADSET \| SND_JACK_BTN_0 \|
	298	SND_JACK_BTN_1 \| SND_JACK_BTN_2 \|
	299	SND_JACK_BTN_3,
	300	jack, NULL, 0);
	301	if (ret) {
	302	dev_err(rtd->dev, "Headset Jack creation failed: %d\n", ret);
	303	return ret;
	304	}
	305
	306	snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
	307	snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
	308	snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
	309	snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
	310
	311	ret = snd_soc_component_set_jack(cmpnt_codec, jack, NULL);
	312	if (ret) {
	313	dev_err(rtd->dev, "Headset Jack set failed: %d\n", ret);
	314	return ret;
	315	}
	316
	317	return 0;
	318	};
	319
	320	static int mt8195_etdm_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
	321	struct snd_pcm_hw_params *params)
	322	{
	323	/* fix BE i2s format to 32bit, clean param mask first */
	324	snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT),
	325	0, (__force unsigned int)SNDRV_PCM_FORMAT_LAST);
	326
	327	params_set_format(params, SNDRV_PCM_FORMAT_S24_LE);
	328
	329	return 0;
	330	}
	331
	332	static int mt8195_hdmitx_dptx_startup(struct snd_pcm_substream *substream)
	333	{
	334	static const unsigned int rates[] = {
	335	48000
	336	};
	337	static const unsigned int channels[] = {
	338	2, 4, 6, 8
	339	};
	340	static const struct snd_pcm_hw_constraint_list constraints_rates = {
	341	.count = ARRAY_SIZE(rates),
	342	.list = rates,
	343	.mask = 0,
	344	};
	345	static const struct snd_pcm_hw_constraint_list constraints_channels = {
	346	.count = ARRAY_SIZE(channels),
	347	.list = channels,
	348	.mask = 0,
	349	};
	350
	351	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
	352	struct snd_pcm_runtime *runtime = substream->runtime;
	353	int ret;
	354
	355	ret = snd_pcm_hw_constraint_list(runtime, 0,
	356	SNDRV_PCM_HW_PARAM_RATE,
	357	&constraints_rates);
	358	if (ret < 0) {
	359	dev_err(rtd->dev, "hw_constraint_list rate failed\n");
	360	return ret;
	361	}
	362
	363	ret = snd_pcm_hw_constraint_list(runtime, 0,
	364	SNDRV_PCM_HW_PARAM_CHANNELS,
	365	&constraints_channels);
	366	if (ret < 0) {
	367	dev_err(rtd->dev, "hw_constraint_list channel failed\n");
	368	return ret;
	369	}
	370
	371	return 0;
	372	}
	373
	374	static const struct snd_soc_ops mt8195_hdmitx_dptx_playback_ops = {
	375	.startup = mt8195_hdmitx_dptx_startup,
	376	};
	377
	378	static int mt8195_dptx_hw_params(struct snd_pcm_substream *substream,
	379	struct snd_pcm_hw_params *params)
	380	{
	381	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	382	struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
	383	unsigned int rate = params_rate(params);
	384	unsigned int mclk_fs_ratio = 256;
	385	unsigned int mclk_fs = rate * mclk_fs_ratio;
	386
	387	return snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_fs,
	388	SND_SOC_CLOCK_OUT);
	389	}
	390
	391	static struct snd_soc_ops mt8195_dptx_ops = {
	392	.hw_params = mt8195_dptx_hw_params,
	393	};
	394
	395	static int mt8195_dptx_codec_init(struct snd_soc_pcm_runtime *rtd)
	396	{
	397	struct mt8195_mt6359_rt1019_rt5682_priv *priv =
	398	snd_soc_card_get_drvdata(rtd->card);
	399	struct snd_soc_component *cmpnt_codec =
	400	asoc_rtd_to_codec(rtd, 0)->component;
	401	int ret = 0;
	402
	403	ret = snd_soc_card_jack_new(rtd->card, "DP Jack", SND_JACK_LINEOUT,
	404	&priv->dp_jack, NULL, 0);
	405	if (ret)
	406	return ret;
	407
	408	return snd_soc_component_set_jack(cmpnt_codec, &priv->dp_jack, NULL);
	409	}
	410
	411	static int mt8195_hdmi_codec_init(struct snd_soc_pcm_runtime *rtd)
	412	{
	413	struct mt8195_mt6359_rt1019_rt5682_priv *priv =
	414	snd_soc_card_get_drvdata(rtd->card);
	415	struct snd_soc_component *cmpnt_codec =
	416	asoc_rtd_to_codec(rtd, 0)->component;
	417	int ret = 0;
	418
	419	ret = snd_soc_card_jack_new(rtd->card, "HDMI Jack", SND_JACK_LINEOUT,
	420	&priv->hdmi_jack, NULL, 0);
	421	if (ret)
	422	return ret;
	423
	424	return snd_soc_component_set_jack(cmpnt_codec, &priv->hdmi_jack, NULL);
	425	}
	426
	427	static int mt8195_hdmitx_dptx_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
	428	struct snd_pcm_hw_params *params)
	429
	430	{
	431	/* fix BE i2s format to 32bit, clean param mask first */
	432	snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT),
	433	0, (__force unsigned int)SNDRV_PCM_FORMAT_LAST);
	434
	435	params_set_format(params, SNDRV_PCM_FORMAT_S24_LE);
	436
	437	return 0;
	438	}
	439
	440	static int mt8195_playback_startup(struct snd_pcm_substream *substream)
	441	{
	442	static const unsigned int rates[] = {
	443	48000
	444	};
	445	static const unsigned int channels[] = {
	446	2
	447	};
	448	static const struct snd_pcm_hw_constraint_list constraints_rates = {
	449	.count = ARRAY_SIZE(rates),
	450	.list = rates,
	451	.mask = 0,
	452	};
	453	static const struct snd_pcm_hw_constraint_list constraints_channels = {
	454	.count = ARRAY_SIZE(channels),
	455	.list = channels,
	456	.mask = 0,
	457	};
	458
	459	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
	460	struct snd_pcm_runtime *runtime = substream->runtime;
	461	int ret;
	462
	463	ret = snd_pcm_hw_constraint_list(runtime, 0,
	464	SNDRV_PCM_HW_PARAM_RATE,
	465	&constraints_rates);
	466	if (ret < 0) {
	467	dev_err(rtd->dev, "hw_constraint_list rate failed\n");
	468	return ret;
	469	}
	470
	471	ret = snd_pcm_hw_constraint_list(runtime, 0,
	472	SNDRV_PCM_HW_PARAM_CHANNELS,
	473	&constraints_channels);
	474	if (ret < 0) {
	475	dev_err(rtd->dev, "hw_constraint_list channel failed\n");
	476	return ret;
	477	}
	478
	479	return 0;
	480	}
	481
	482	static const struct snd_soc_ops mt8195_playback_ops = {
	483	.startup = mt8195_playback_startup,
	484	};
	485
	486	static int mt8195_capture_startup(struct snd_pcm_substream *substream)
	487	{
	488	static const unsigned int rates[] = {
	489	48000
	490	};
	491	static const unsigned int channels[] = {
	492	1, 2
	493	};
	494	static const struct snd_pcm_hw_constraint_list constraints_rates = {
	495	.count = ARRAY_SIZE(rates),
	496	.list = rates,
	497	.mask = 0,
	498	};
	499	static const struct snd_pcm_hw_constraint_list constraints_channels = {
	500	.count = ARRAY_SIZE(channels),
	501	.list = channels,
	502	.mask = 0,
	503	};
	504
	505	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
	506	struct snd_pcm_runtime *runtime = substream->runtime;
	507	int ret;
	508
	509	ret = snd_pcm_hw_constraint_list(runtime, 0,
	510	SNDRV_PCM_HW_PARAM_RATE,
	511	&constraints_rates);
	512	if (ret < 0) {
	513	dev_err(rtd->dev, "hw_constraint_list rate failed\n");
	514	return ret;
	515	}
	516
	517	ret = snd_pcm_hw_constraint_list(runtime, 0,
	518	SNDRV_PCM_HW_PARAM_CHANNELS,
	519	&constraints_channels);
	520	if (ret < 0) {
	521	dev_err(rtd->dev, "hw_constraint_list channel failed\n");
	522	return ret;
	523	}
	524
	525	return 0;
	526	}
	527
	528	static const struct snd_soc_ops mt8195_capture_ops = {
	529	.startup = mt8195_capture_startup,
	530	};
	531
	532	enum {
	533	DAI_LINK_DL2_FE,
	534	DAI_LINK_DL3_FE,
	535	DAI_LINK_DL6_FE,
	536	DAI_LINK_DL7_FE,
	537	DAI_LINK_DL8_FE,
	538	DAI_LINK_DL10_FE,
	539	DAI_LINK_DL11_FE,
	540	DAI_LINK_UL1_FE,
	541	DAI_LINK_UL2_FE,
	542	DAI_LINK_UL3_FE,
	543	DAI_LINK_UL4_FE,
	544	DAI_LINK_UL5_FE,
	545	DAI_LINK_UL6_FE,
	546	DAI_LINK_UL8_FE,
	547	DAI_LINK_UL9_FE,
	548	DAI_LINK_UL10_FE,
	549	DAI_LINK_DL_SRC_BE,
	550	DAI_LINK_DPTX_BE,
	551	DAI_LINK_ETDM1_IN_BE,
	552	DAI_LINK_ETDM2_IN_BE,
	553	DAI_LINK_ETDM1_OUT_BE,
	554	DAI_LINK_ETDM2_OUT_BE,
	555	DAI_LINK_ETDM3_OUT_BE,
	556	DAI_LINK_PCM1_BE,
	557	DAI_LINK_UL_SRC1_BE,
	558	DAI_LINK_UL_SRC2_BE,
	559	};
	560
	561	/* FE */
	562	SND_SOC_DAILINK_DEFS(DL2_FE,
	563	DAILINK_COMP_ARRAY(COMP_CPU("DL2")),
	564	DAILINK_COMP_ARRAY(COMP_DUMMY()),
	565	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	566
	567	SND_SOC_DAILINK_DEFS(DL3_FE,
	568	DAILINK_COMP_ARRAY(COMP_CPU("DL3")),
	569	DAILINK_COMP_ARRAY(COMP_DUMMY()),
	570	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	571
	572	SND_SOC_DAILINK_DEFS(DL6_FE,
	573	DAILINK_COMP_ARRAY(COMP_CPU("DL6")),
	574	DAILINK_COMP_ARRAY(COMP_DUMMY()),
	575	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	576
	577	SND_SOC_DAILINK_DEFS(DL7_FE,
	578	DAILINK_COMP_ARRAY(COMP_CPU("DL7")),
	579	DAILINK_COMP_ARRAY(COMP_DUMMY()),
	580	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	581
	582	SND_SOC_DAILINK_DEFS(DL8_FE,
	583	DAILINK_COMP_ARRAY(COMP_CPU("DL8")),
	584	DAILINK_COMP_ARRAY(COMP_DUMMY()),
	585	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	586
	587	SND_SOC_DAILINK_DEFS(DL10_FE,
	588	DAILINK_COMP_ARRAY(COMP_CPU("DL10")),
	589	DAILINK_COMP_ARRAY(COMP_DUMMY()),
	590	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	591
	592	SND_SOC_DAILINK_DEFS(DL11_FE,
	593	DAILINK_COMP_ARRAY(COMP_CPU("DL11")),
	594	DAILINK_COMP_ARRAY(COMP_DUMMY()),
	595	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	596
	597	SND_SOC_DAILINK_DEFS(UL1_FE,
	598	DAILINK_COMP_ARRAY(COMP_CPU("UL1")),
	599	DAILINK_COMP_ARRAY(COMP_DUMMY()),
	600	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	601
	602	SND_SOC_DAILINK_DEFS(UL2_FE,
	603	DAILINK_COMP_ARRAY(COMP_CPU("UL2")),
	604	DAILINK_COMP_ARRAY(COMP_DUMMY()),
	605	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	606
	607	SND_SOC_DAILINK_DEFS(UL3_FE,
	608	DAILINK_COMP_ARRAY(COMP_CPU("UL3")),
	609	DAILINK_COMP_ARRAY(COMP_DUMMY()),
	610	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	611
	612	SND_SOC_DAILINK_DEFS(UL4_FE,
	613	DAILINK_COMP_ARRAY(COMP_CPU("UL4")),
	614	DAILINK_COMP_ARRAY(COMP_DUMMY()),
	615	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	616
	617	SND_SOC_DAILINK_DEFS(UL5_FE,
	618	DAILINK_COMP_ARRAY(COMP_CPU("UL5")),
	619	DAILINK_COMP_ARRAY(COMP_DUMMY()),
	620	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	621
	622	SND_SOC_DAILINK_DEFS(UL6_FE,
	623	DAILINK_COMP_ARRAY(COMP_CPU("UL6")),
	624	DAILINK_COMP_ARRAY(COMP_DUMMY()),
	625	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	626
	627	SND_SOC_DAILINK_DEFS(UL8_FE,
	628	DAILINK_COMP_ARRAY(COMP_CPU("UL8")),
	629	DAILINK_COMP_ARRAY(COMP_DUMMY()),
	630	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	631
	632	SND_SOC_DAILINK_DEFS(UL9_FE,
	633	DAILINK_COMP_ARRAY(COMP_CPU("UL9")),
	634	DAILINK_COMP_ARRAY(COMP_DUMMY()),
	635	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	636
	637	SND_SOC_DAILINK_DEFS(UL10_FE,
	638	DAILINK_COMP_ARRAY(COMP_CPU("UL10")),
	639	DAILINK_COMP_ARRAY(COMP_DUMMY()),
	640	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	641
	642	/* BE */
	643	SND_SOC_DAILINK_DEFS(DL_SRC_BE,
	644	DAILINK_COMP_ARRAY(COMP_CPU("DL_SRC")),
	645	DAILINK_COMP_ARRAY(COMP_CODEC("mt6359-sound",
	646	"mt6359-snd-codec-aif1")),
	647	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	648
	649	SND_SOC_DAILINK_DEFS(DPTX_BE,
	650	DAILINK_COMP_ARRAY(COMP_CPU("DPTX")),
	651	DAILINK_COMP_ARRAY(COMP_DUMMY()),
	652	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	653
	654	SND_SOC_DAILINK_DEFS(ETDM1_IN_BE,
	655	DAILINK_COMP_ARRAY(COMP_CPU("ETDM1_IN")),
	656	DAILINK_COMP_ARRAY(COMP_DUMMY()),
	657	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	658
	659	SND_SOC_DAILINK_DEFS(ETDM2_IN_BE,
	660	DAILINK_COMP_ARRAY(COMP_CPU("ETDM2_IN")),
	661	DAILINK_COMP_ARRAY(COMP_CODEC(RT5682_DEV0_NAME,
	662	RT5682_CODEC_DAI)),
	663	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	664
	665	SND_SOC_DAILINK_DEFS(ETDM1_OUT_BE,
	666	DAILINK_COMP_ARRAY(COMP_CPU("ETDM1_OUT")),
	667	DAILINK_COMP_ARRAY(COMP_CODEC(RT5682_DEV0_NAME,
	668	RT5682_CODEC_DAI)),
	669	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	670
	671	SND_SOC_DAILINK_DEFS(ETDM2_OUT_BE,
	672	DAILINK_COMP_ARRAY(COMP_CPU("ETDM2_OUT")),
	673	DAILINK_COMP_ARRAY(COMP_CODEC(RT1019_DEV0_NAME,
	674	RT1019_CODEC_DAI)),
	675	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	676
	677	SND_SOC_DAILINK_DEFS(ETDM3_OUT_BE,
	678	DAILINK_COMP_ARRAY(COMP_CPU("ETDM3_OUT")),
	679	DAILINK_COMP_ARRAY(COMP_DUMMY()),
	680	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	681
	682	SND_SOC_DAILINK_DEFS(PCM1_BE,
	683	DAILINK_COMP_ARRAY(COMP_CPU("PCM1")),
	684	DAILINK_COMP_ARRAY(COMP_DUMMY()),
	685	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	686
	687	SND_SOC_DAILINK_DEFS(UL_SRC1_BE,
	688	DAILINK_COMP_ARRAY(COMP_CPU("UL_SRC1")),
	689	DAILINK_COMP_ARRAY(COMP_CODEC("mt6359-sound",
	690	"mt6359-snd-codec-aif1"),
	691	COMP_CODEC("dmic-codec",
	692	"dmic-hifi")),
	693	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	694
	695	SND_SOC_DAILINK_DEFS(UL_SRC2_BE,
	696	DAILINK_COMP_ARRAY(COMP_CPU("UL_SRC2")),
	697	DAILINK_COMP_ARRAY(COMP_CODEC("mt6359-sound",
	698	"mt6359-snd-codec-aif2")),
	699	DAILINK_COMP_ARRAY(COMP_EMPTY()));
	700
	701	static struct snd_soc_dai_link mt8195_mt6359_rt1019_rt5682_dai_links[] = {
	702	/* FE */
	703	[DAI_LINK_DL2_FE] = {
	704	.name = "DL2_FE",
	705	.stream_name = "DL2 Playback",
	706	.trigger = {
	707	SND_SOC_DPCM_TRIGGER_POST,
	708	SND_SOC_DPCM_TRIGGER_POST,
	709	},
	710	.dynamic = 1,
	711	.dpcm_playback = 1,
	712	.ops = &mt8195_playback_ops,
	713	SND_SOC_DAILINK_REG(DL2_FE),
	714	},
	715	[DAI_LINK_DL3_FE] = {
	716	.name = "DL3_FE",
	717	.stream_name = "DL3 Playback",
	718	.trigger = {
	719	SND_SOC_DPCM_TRIGGER_POST,
	720	SND_SOC_DPCM_TRIGGER_POST,
	721	},
	722	.dynamic = 1,
	723	.dpcm_playback = 1,
	724	.ops = &mt8195_playback_ops,
	725	SND_SOC_DAILINK_REG(DL3_FE),
	726	},
	727	[DAI_LINK_DL6_FE] = {
	728	.name = "DL6_FE",
	729	.stream_name = "DL6 Playback",
	730	.trigger = {
	731	SND_SOC_DPCM_TRIGGER_POST,
	732	SND_SOC_DPCM_TRIGGER_POST,
	733	},
	734	.dynamic = 1,
	735	.dpcm_playback = 1,
	736	.ops = &mt8195_playback_ops,
	737	SND_SOC_DAILINK_REG(DL6_FE),
	738	},
	739	[DAI_LINK_DL7_FE] = {
	740	.name = "DL7_FE",
	741	.stream_name = "DL7 Playback",
	742	.trigger = {
	743	SND_SOC_DPCM_TRIGGER_PRE,
	744	SND_SOC_DPCM_TRIGGER_PRE,
	745	},
	746	.dynamic = 1,
	747	.dpcm_playback = 1,
	748	SND_SOC_DAILINK_REG(DL7_FE),
	749	},
	750	[DAI_LINK_DL8_FE] = {
	751	.name = "DL8_FE",
	752	.stream_name = "DL8 Playback",
	753	.trigger = {
	754	SND_SOC_DPCM_TRIGGER_POST,
	755	SND_SOC_DPCM_TRIGGER_POST,
	756	},
	757	.dynamic = 1,
	758	.dpcm_playback = 1,
	759	.ops = &mt8195_playback_ops,
	760	SND_SOC_DAILINK_REG(DL8_FE),
	761	},
	762	[DAI_LINK_DL10_FE] = {
	763	.name = "DL10_FE",
	764	.stream_name = "DL10 Playback",
	765	.trigger = {
	766	SND_SOC_DPCM_TRIGGER_POST,
	767	SND_SOC_DPCM_TRIGGER_POST,
	768	},
	769	.dynamic = 1,
	770	.dpcm_playback = 1,
	771	.ops = &mt8195_hdmitx_dptx_playback_ops,
	772	SND_SOC_DAILINK_REG(DL10_FE),
	773	},
	774	[DAI_LINK_DL11_FE] = {
	775	.name = "DL11_FE",
	776	.stream_name = "DL11 Playback",
	777	.trigger = {
	778	SND_SOC_DPCM_TRIGGER_POST,
	779	SND_SOC_DPCM_TRIGGER_POST,
	780	},
	781	.dynamic = 1,
	782	.dpcm_playback = 1,
	783	.ops = &mt8195_playback_ops,
	784	SND_SOC_DAILINK_REG(DL11_FE),
	785	},
	786	[DAI_LINK_UL1_FE] = {
	787	.name = "UL1_FE",
	788	.stream_name = "UL1 Capture",
	789	.trigger = {
	790	SND_SOC_DPCM_TRIGGER_PRE,
	791	SND_SOC_DPCM_TRIGGER_PRE,
	792	},
	793	.dynamic = 1,
	794	.dpcm_capture = 1,
	795	SND_SOC_DAILINK_REG(UL1_FE),
	796	},
	797	[DAI_LINK_UL2_FE] = {
	798	.name = "UL2_FE",
	799	.stream_name = "UL2 Capture",
	800	.trigger = {
	801	SND_SOC_DPCM_TRIGGER_POST,
	802	SND_SOC_DPCM_TRIGGER_POST,
	803	},
	804	.dynamic = 1,
	805	.dpcm_capture = 1,
	806	.ops = &mt8195_capture_ops,
	807	SND_SOC_DAILINK_REG(UL2_FE),
	808	},
	809	[DAI_LINK_UL3_FE] = {
	810	.name = "UL3_FE",
	811	.stream_name = "UL3 Capture",
	812	.trigger = {
	813	SND_SOC_DPCM_TRIGGER_POST,
	814	SND_SOC_DPCM_TRIGGER_POST,
	815	},
	816	.dynamic = 1,
	817	.dpcm_capture = 1,
	818	.ops = &mt8195_capture_ops,
	819	SND_SOC_DAILINK_REG(UL3_FE),
	820	},
	821	[DAI_LINK_UL4_FE] = {
	822	.name = "UL4_FE",
	823	.stream_name = "UL4 Capture",
	824	.trigger = {
	825	SND_SOC_DPCM_TRIGGER_POST,
	826	SND_SOC_DPCM_TRIGGER_POST,
	827	},
	828	.dynamic = 1,
	829	.dpcm_capture = 1,
	830	.ops = &mt8195_capture_ops,
	831	SND_SOC_DAILINK_REG(UL4_FE),
	832	},
	833	[DAI_LINK_UL5_FE] = {
	834	.name = "UL5_FE",
	835	.stream_name = "UL5 Capture",
	836	.trigger = {
	837	SND_SOC_DPCM_TRIGGER_POST,
	838	SND_SOC_DPCM_TRIGGER_POST,
	839	},
	840	.dynamic = 1,
	841	.dpcm_capture = 1,
	842	.ops = &mt8195_capture_ops,
	843	SND_SOC_DAILINK_REG(UL5_FE),
	844	},
	845	[DAI_LINK_UL6_FE] = {
	846	.name = "UL6_FE",
	847	.stream_name = "UL6 Capture",
	848	.trigger = {
	849	SND_SOC_DPCM_TRIGGER_PRE,
	850	SND_SOC_DPCM_TRIGGER_PRE,
	851	},
	852	.dynamic = 1,
	853	.dpcm_capture = 1,
	854	SND_SOC_DAILINK_REG(UL6_FE),
	855	},
	856	[DAI_LINK_UL8_FE] = {
	857	.name = "UL8_FE",
	858	.stream_name = "UL8 Capture",
	859	.trigger = {
	860	SND_SOC_DPCM_TRIGGER_POST,
	861	SND_SOC_DPCM_TRIGGER_POST,
	862	},
	863	.dynamic = 1,
	864	.dpcm_capture = 1,
	865	.ops = &mt8195_capture_ops,
	866	SND_SOC_DAILINK_REG(UL8_FE),
	867	},
	868	[DAI_LINK_UL9_FE] = {
	869	.name = "UL9_FE",
	870	.stream_name = "UL9 Capture",
	871	.trigger = {
	872	SND_SOC_DPCM_TRIGGER_POST,
	873	SND_SOC_DPCM_TRIGGER_POST,
	874	},
	875	.dynamic = 1,
	876	.dpcm_capture = 1,
	877	.ops = &mt8195_capture_ops,
	878	SND_SOC_DAILINK_REG(UL9_FE),
	879	},
	880	[DAI_LINK_UL10_FE] = {
	881	.name = "UL10_FE",
	882	.stream_name = "UL10 Capture",
	883	.trigger = {
	884	SND_SOC_DPCM_TRIGGER_POST,
	885	SND_SOC_DPCM_TRIGGER_POST,
	886	},
	887	.dynamic = 1,
	888	.dpcm_capture = 1,
	889	.ops = &mt8195_capture_ops,
	890	SND_SOC_DAILINK_REG(UL10_FE),
	891	},
	892	/* BE */
	893	[DAI_LINK_DL_SRC_BE] = {
	894	.name = "DL_SRC_BE",
	895	.init = mt8195_mt6359_init,
	896	.no_pcm = 1,
	897	.dpcm_playback = 1,
	898	SND_SOC_DAILINK_REG(DL_SRC_BE),
	899	},
	900	[DAI_LINK_DPTX_BE] = {
	901	.name = "DPTX_BE",
	902	.no_pcm = 1,
	903	.dpcm_playback = 1,
	904	.ops = &mt8195_dptx_ops,
	905	.be_hw_params_fixup = mt8195_hdmitx_dptx_hw_params_fixup,
	906	SND_SOC_DAILINK_REG(DPTX_BE),
	907	},
	908	[DAI_LINK_ETDM1_IN_BE] = {
	909	.name = "ETDM1_IN_BE",
	910	.no_pcm = 1,
	911	.dai_fmt = SND_SOC_DAIFMT_I2S \|
	912	SND_SOC_DAIFMT_NB_NF \|
	913	SND_SOC_DAIFMT_CBS_CFS,
	914	.dpcm_capture = 1,
	915	SND_SOC_DAILINK_REG(ETDM1_IN_BE),
	916	},
	917	[DAI_LINK_ETDM2_IN_BE] = {
	918	.name = "ETDM2_IN_BE",
	919	.no_pcm = 1,
	920	.dai_fmt = SND_SOC_DAIFMT_I2S \|
	921	SND_SOC_DAIFMT_NB_NF \|
	922	SND_SOC_DAIFMT_CBS_CFS,
	923	.dpcm_capture = 1,
	924	.init = mt8195_rt5682_init,
	925	.ops = &mt8195_rt5682_etdm_ops,
	926	.be_hw_params_fixup = mt8195_etdm_hw_params_fixup,
	927	SND_SOC_DAILINK_REG(ETDM2_IN_BE),
	928	},
	929	[DAI_LINK_ETDM1_OUT_BE] = {
	930	.name = "ETDM1_OUT_BE",
	931	.no_pcm = 1,
	932	.dai_fmt = SND_SOC_DAIFMT_I2S \|
	933	SND_SOC_DAIFMT_NB_NF \|
	934	SND_SOC_DAIFMT_CBS_CFS,
	935	.dpcm_playback = 1,
	936	.ops = &mt8195_rt5682_etdm_ops,
	937	.be_hw_params_fixup = mt8195_etdm_hw_params_fixup,
	938	SND_SOC_DAILINK_REG(ETDM1_OUT_BE),
	939	},
	940	[DAI_LINK_ETDM2_OUT_BE] = {
	941	.name = "ETDM2_OUT_BE",
	942	.no_pcm = 1,
	943	.dai_fmt = SND_SOC_DAIFMT_I2S \|
	944	SND_SOC_DAIFMT_NB_NF \|
	945	SND_SOC_DAIFMT_CBS_CFS,
	946	.dpcm_playback = 1,
	947	SND_SOC_DAILINK_REG(ETDM2_OUT_BE),
	948	},
	949	[DAI_LINK_ETDM3_OUT_BE] = {
	950	.name = "ETDM3_OUT_BE",
	951	.no_pcm = 1,
	952	.dai_fmt = SND_SOC_DAIFMT_I2S \|
	953	SND_SOC_DAIFMT_NB_NF \|
	954	SND_SOC_DAIFMT_CBS_CFS,
	955	.dpcm_playback = 1,
	956	.be_hw_params_fixup = mt8195_hdmitx_dptx_hw_params_fixup,
	957	SND_SOC_DAILINK_REG(ETDM3_OUT_BE),
	958	},
	959	[DAI_LINK_PCM1_BE] = {
	960	.name = "PCM1_BE",
	961	.no_pcm = 1,
	962	.dai_fmt = SND_SOC_DAIFMT_I2S \|
	963	SND_SOC_DAIFMT_NB_NF \|
	964	SND_SOC_DAIFMT_CBS_CFS,
	965	.dpcm_capture = 1,
	966	SND_SOC_DAILINK_REG(PCM1_BE),
	967	},
	968	[DAI_LINK_UL_SRC1_BE] = {
	969	.name = "UL_SRC1_BE",
	970	.no_pcm = 1,
	971	.dpcm_capture = 1,
	972	SND_SOC_DAILINK_REG(UL_SRC1_BE),
	973	},
	974	[DAI_LINK_UL_SRC2_BE] = {
	975	.name = "UL_SRC2_BE",
	976	.no_pcm = 1,
	977	.dpcm_capture = 1,
	978	SND_SOC_DAILINK_REG(UL_SRC2_BE),
	979	},
	980	};
	981
	982	static struct snd_soc_card mt8195_mt6359_rt1019_rt5682_soc_card = {
	983	.name = "mt8195_r1019_5682",
	984	.owner = THIS_MODULE,
	985	.dai_link = mt8195_mt6359_rt1019_rt5682_dai_links,
	986	.num_links = ARRAY_SIZE(mt8195_mt6359_rt1019_rt5682_dai_links),
	987	.controls = mt8195_mt6359_rt1019_rt5682_controls,
	988	.num_controls = ARRAY_SIZE(mt8195_mt6359_rt1019_rt5682_controls),
	989	.dapm_widgets = mt8195_mt6359_rt1019_rt5682_widgets,
	990	.num_dapm_widgets = ARRAY_SIZE(mt8195_mt6359_rt1019_rt5682_widgets),
	991	.dapm_routes = mt8195_mt6359_rt1019_rt5682_routes,
	992	.num_dapm_routes = ARRAY_SIZE(mt8195_mt6359_rt1019_rt5682_routes),
	993	};
	994
	995	static int mt8195_mt6359_rt1019_rt5682_dev_probe(struct platform_device *pdev)
	996	{
	997	struct snd_soc_card *card = &mt8195_mt6359_rt1019_rt5682_soc_card;
	998	struct device_node *platform_node;
	999	struct snd_soc_dai_link *dai_link;
	1000	struct mt8195_mt6359_rt1019_rt5682_priv *priv = NULL;
	1001	int ret, i;
	1002
	1003	card->dev = &pdev->dev;
	1004
	1005	platform_node = of_parse_phandle(pdev->dev.of_node,
	1006	"mediatek,platform", 0);
	1007	if (!platform_node) {
	1008	dev_dbg(&pdev->dev, "Property 'platform' missing or invalid\n");
	1009	return -EINVAL;
	1010	}
	1011
	1012	for_each_card_prelinks(card, i, dai_link) {
	1013	if (!dai_link->platforms->name)
	1014	dai_link->platforms->of_node = platform_node;
	1015
	1016	if (strcmp(dai_link->name, "DPTX_BE") == 0) {
	1017	dai_link->codecs->of_node =
	1018	of_parse_phandle(pdev->dev.of_node,
	1019	"mediatek,dptx-codec", 0);
	1020	if (!dai_link->codecs->of_node) {
	1021	dev_err(&pdev->dev, "Property 'dptx-codec' missing or invalid\n");
	1022	return -EINVAL;
	1023	}
	1024
	1025	dai_link->codecs->name = NULL;
	1026	dai_link->codecs->dai_name = "i2s-hifi";
	1027	dai_link->init = mt8195_dptx_codec_init;
	1028	}
	1029
	1030	if (strcmp(dai_link->name, "ETDM3_OUT_BE") == 0) {
	1031	dai_link->codecs->of_node =
	1032	of_parse_phandle(pdev->dev.of_node,
	1033	"mediatek,hdmi-codec", 0);
	1034	if (!dai_link->codecs->of_node) {
	1035	dev_err(&pdev->dev, "Property 'hdmi-codec' missing or invalid\n");
	1036	return -EINVAL;
	1037	}
	1038
	1039	dai_link->codecs->name = NULL;
	1040	dai_link->codecs->dai_name = "i2s-hifi";
	1041	dai_link->init = mt8195_hdmi_codec_init;
	1042	}
	1043	}
	1044
	1045	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	1046	if (!priv)
	1047	return -ENOMEM;
	1048
	1049	snd_soc_card_set_drvdata(card, priv);
	1050
	1051	ret = devm_snd_soc_register_card(&pdev->dev, card);
	1052	if (ret)
	1053	dev_err(&pdev->dev, "%s snd_soc_register_card fail %d\n",
	1054	__func__, ret);
	1055	return ret;
	1056	}
	1057
	1058	#ifdef CONFIG_OF
	1059	static const struct of_device_id mt8195_mt6359_rt1019_rt5682_dt_match[] = {
	1060	{.compatible = "mediatek,mt8195_mt6359_rt1019_rt5682",},
	1061	{}
	1062	};
	1063	#endif
	1064
	1065	static const struct dev_pm_ops mt8195_mt6359_rt1019_rt5682_pm_ops = {
	1066	.poweroff = snd_soc_poweroff,
	1067	.restore = snd_soc_resume,
	1068	};
	1069
	1070	static struct platform_driver mt8195_mt6359_rt1019_rt5682_driver = {
	1071	.driver = {
	1072	.name = "mt8195_mt6359_rt1019_rt5682",
	1073	#ifdef CONFIG_OF
	1074	.of_match_table = mt8195_mt6359_rt1019_rt5682_dt_match,
	1075	#endif
	1076	.pm = &mt8195_mt6359_rt1019_rt5682_pm_ops,
	1077	},
	1078	.probe = mt8195_mt6359_rt1019_rt5682_dev_probe,
	1079	};
	1080
	1081	module_platform_driver(mt8195_mt6359_rt1019_rt5682_driver);
	1082
	1083	/* Module information */
	1084	MODULE_DESCRIPTION("MT8195-MT6359-RT1019-RT5682 ALSA SoC machine driver");
	1085	MODULE_AUTHOR("Trevor Wu <trevor.wu@mediatek.com>");
	1086	MODULE_LICENSE("GPL v2");
	1087	MODULE_ALIAS("mt8195_mt6359_rt1019_rt5682 soc card");

sound/soc/mediatek/mt8195/mt8195-reg.h+2796−0

@@ -0,0 +1,2796 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* mt8195-reg.h -- Mediatek 8195 audio driver reg definition
	4	*
	5	* Copyright (c) 2021 MediaTek Inc.
	6	* Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
	7	* Trevor Wu <trevor.wu@mediatek.com>
	8	*/
	9
	10	#ifndef _MT8195_REG_H_
	11	#define _MT8195_REG_H_
	12
	13	#define AFE_SRAM_BASE (0x10880000)
	14	#define AFE_SRAM_SIZE (0x10000)
	15
	16	#define AUDIO_TOP_CON0 (0x0000)
	17	#define AUDIO_TOP_CON1 (0x0004)
	18	#define AUDIO_TOP_CON2 (0x0008)
	19	#define AUDIO_TOP_CON3 (0x000c)
	20	#define AUDIO_TOP_CON4 (0x0010)
	21	#define AUDIO_TOP_CON5 (0x0014)
	22	#define AUDIO_TOP_CON6 (0x0018)
	23	#define AFE_MAS_HADDR_MSB (0x0020)
	24	#define PWR1_ASM_CON1 (0x0108)
	25	#define ASYS_IRQ_CONFIG (0x0110)
	26	#define ASYS_IRQ1_CON (0x0114)
	27	#define ASYS_IRQ2_CON (0x0118)
	28	#define ASYS_IRQ3_CON (0x011c)
	29	#define ASYS_IRQ4_CON (0x0120)
	30	#define ASYS_IRQ5_CON (0x0124)
	31	#define ASYS_IRQ6_CON (0x0128)
	32	#define ASYS_IRQ7_CON (0x012c)
	33	#define ASYS_IRQ8_CON (0x0130)
	34	#define ASYS_IRQ9_CON (0x0134)
	35	#define ASYS_IRQ10_CON (0x0138)
	36	#define ASYS_IRQ11_CON (0x013c)
	37	#define ASYS_IRQ12_CON (0x0140)
	38	#define ASYS_IRQ13_CON (0x0144)
	39	#define ASYS_IRQ14_CON (0x0148)
	40	#define ASYS_IRQ15_CON (0x014c)
	41	#define ASYS_IRQ16_CON (0x0150)
	42	#define ASYS_IRQ_CLR (0x0154)
	43	#define ASYS_IRQ_STATUS (0x0158)
	44	#define ASYS_IRQ_MON1 (0x015c)
	45	#define ASYS_IRQ_MON2 (0x0160)
	46	#define AFE_IRQ1_CON (0x0164)
	47	#define AFE_IRQ2_CON (0x0168)
	48	#define AFE_IRQ3_CON (0x016c)
	49	#define AFE_IRQ_MCU_CLR (0x0170)
	50	#define AFE_IRQ_STATUS (0x0174)
	51	#define AFE_IRQ_MASK (0x0178)
	52	#define ASYS_IRQ_MASK (0x017c)
	53	#define AFE_IRQ3_CON_MON (0x01b0)
	54	#define AFE_IRQ_MCU_MON2 (0x01b4)
	55	#define AFE_IRQ8_CON (0x01b8)
	56	#define AFE_IRQ9_CON (0x01bc)
	57	#define AFE_IRQ10_CON (0x01c0)
	58	#define AFE_IRQ9_CON_MON (0x01c4)
	59	#define ADSP_IRQ_MASK (0x01c8)
	60	#define ADSP_IRQ_STATUS (0x01cc)
	61	#define AFE_SINEGEN_CON0 (0x01f0)
	62	#define AFE_SINEGEN_CON1 (0x01f4)
	63	#define AFE_SINEGEN_CON2 (0x01f8)
	64	#define AFE_SINEGEN_CON3 (0x01fc)
	65	#define AFE_SPDIF_OUT_CON0 (0x0380)
	66	#define AFE_TDMOUT_CONN0 (0x0390)
	67	#define PWR1_ASM_CON2 (0x03b0)
	68	#define PWR1_ASM_CON3 (0x03b4)
	69	#define PWR1_ASM_CON4 (0x03b8)
	70	#define AFE_APLL_TUNER_CFG (0x03f8)
	71	#define AFE_APLL_TUNER_CFG1 (0x03fc)
	72	#define AUDIO_TOP_STA0 (0x0400)
	73	#define AUDIO_TOP_STA1 (0x0404)
	74	#define AFE_GAIN1_CON0 (0x0410)
	75	#define AFE_GAIN1_CON1 (0x0414)
	76	#define AFE_GAIN1_CON2 (0x0418)
	77	#define AFE_GAIN1_CON3 (0x041c)
	78	#define AFE_GAIN1_CUR (0x0424)
	79	#define AFE_GAIN2_CON0 (0x0428)
	80	#define AFE_GAIN2_CON1 (0x042c)
	81	#define AFE_GAIN2_CON2 (0x0430)
	82	#define AFE_GAIN2_CON3 (0x0434)
	83	#define AFE_GAIN2_CUR (0x043c)
	84	#define AFE_IEC_CFG (0x0480)
	85	#define AFE_IEC_NSNUM (0x0484)
	86	#define AFE_IEC_BURST_INFO (0x0488)
	87	#define AFE_IEC_BURST_LEN (0x048c)
	88	#define AFE_IEC_NSADR (0x0490)
	89	#define AFE_IEC_CHL_STAT0 (0x04a0)
	90	#define AFE_IEC_CHL_STAT1 (0x04a4)
	91	#define AFE_IEC_CHR_STAT0 (0x04a8)
	92	#define AFE_IEC_CHR_STAT1 (0x04ac)
	93	#define AFE_SPDIFIN_CFG0 (0x0500)
	94	#define AFE_SPDIFIN_CFG1 (0x0504)
	95	#define AFE_SPDIFIN_CHSTS1 (0x0508)
	96	#define AFE_SPDIFIN_CHSTS2 (0x050c)
	97	#define AFE_SPDIFIN_CHSTS3 (0x0510)
	98	#define AFE_SPDIFIN_CHSTS4 (0x0514)
	99	#define AFE_SPDIFIN_CHSTS5 (0x0518)
	100	#define AFE_SPDIFIN_CHSTS6 (0x051c)
	101	#define AFE_SPDIFIN_DEBUG1 (0x0520)
	102	#define AFE_SPDIFIN_DEBUG2 (0x0524)
	103	#define AFE_SPDIFIN_DEBUG3 (0x0528)
	104	#define AFE_SPDIFIN_DEBUG4 (0x052c)
	105	#define AFE_SPDIFIN_EC (0x0530)
	106	#define AFE_SPDIFIN_CKLOCK_CFG (0x0534)
	107	#define AFE_SPDIFIN_BR (0x053c)
	108	#define AFE_SPDIFIN_BR_DBG1 (0x0540)
	109	#define AFE_SPDIFIN_CKFBDIV (0x0544)
	110	#define AFE_SPDIFIN_INT_EXT (0x0548)
	111	#define AFE_SPDIFIN_INT_EXT2 (0x054c)
	112	#define SPDIFIN_FREQ_INFO (0x0550)
	113	#define SPDIFIN_FREQ_INFO_2 (0x0554)
	114	#define SPDIFIN_FREQ_INFO_3 (0x0558)
	115	#define SPDIFIN_FREQ_STATUS (0x055c)
	116	#define SPDIFIN_USERCODE1 (0x0560)
	117	#define SPDIFIN_USERCODE2 (0x0564)
	118	#define SPDIFIN_USERCODE3 (0x0568)
	119	#define SPDIFIN_USERCODE4 (0x056c)
	120	#define SPDIFIN_USERCODE5 (0x0570)
	121	#define SPDIFIN_USERCODE6 (0x0574)
	122	#define SPDIFIN_USERCODE7 (0x0578)
	123	#define SPDIFIN_USERCODE8 (0x057c)
	124	#define SPDIFIN_USERCODE9 (0x0580)
	125	#define SPDIFIN_USERCODE10 (0x0584)
	126	#define SPDIFIN_USERCODE11 (0x0588)
	127	#define SPDIFIN_USERCODE12 (0x058c)
	128	#define AFE_SPDIFIN_APLL_TUNER_CFG (0x0594)
	129	#define AFE_SPDIFIN_APLL_TUNER_CFG1 (0x0598)
	130	#define ASYS_TOP_CON (0x0600)
	131	#define AFE_LINEIN_APLL_TUNER_CFG (0x0610)
	132	#define AFE_LINEIN_APLL_TUNER_MON (0x0614)
	133	#define AFE_EARC_APLL_TUNER_CFG (0x0618)
	134	#define AFE_EARC_APLL_TUNER_MON (0x061c)
	135	#define PWR2_TOP_CON0 (0x0634)
	136	#define PWR2_TOP_CON1 (0x0638)
	137	#define PCM_INTF_CON1 (0x063c)
	138	#define PCM_INTF_CON2 (0x0640)
	139	#define AFE_CM0_CON (0x0660)
	140	#define AFE_CM1_CON (0x0664)
	141	#define AFE_CM2_CON (0x0668)
	142	#define AFE_CM0_MON (0x0670)
	143	#define AFE_CM1_MON (0x0674)
	144	#define AFE_CM2_MON (0x0678)
	145	#define AFE_MPHONE_MULTI_CON0 (0x06a4)
	146	#define AFE_MPHONE_MULTI_CON1 (0x06a8)
	147	#define AFE_MPHONE_MULTI_CON2 (0x06ac)
	148	#define AFE_MPHONE_MULTI_MON (0x06b0)
	149	#define AFE_MPHONE_MULTI_DET_REG_CON0 (0x06b4)
	150	#define AFE_MPHONE_MULTI_DET_REG_CON1 (0x06b8)
	151	#define AFE_MPHONE_MULTI_DET_REG_CON2 (0x06bc)
	152	#define AFE_MPHONE_MULTI_DET_REG_CON3 (0x06c0)
	153	#define AFE_MPHONE_MULTI_DET_MON0 (0x06c4)
	154	#define AFE_MPHONE_MULTI_DET_MON1 (0x06c8)
	155	#define AFE_MPHONE_MULTI_DET_MON2 (0x06d0)
	156	#define AFE_MPHONE_MULTI2_CON0 (0x06d4)
	157	#define AFE_MPHONE_MULTI2_CON1 (0x06d8)
	158	#define AFE_MPHONE_MULTI2_CON2 (0x06dc)
	159	#define AFE_MPHONE_MULTI2_MON (0x06e0)
	160	#define AFE_MPHONE_MULTI2_DET_REG_CON0 (0x06e4)
	161	#define AFE_MPHONE_MULTI2_DET_REG_CON1 (0x06e8)
	162	#define AFE_MPHONE_MULTI2_DET_REG_CON2 (0x06ec)
	163	#define AFE_MPHONE_MULTI2_DET_REG_CON3 (0x06f0)
	164	#define AFE_MPHONE_MULTI2_DET_MON0 (0x06f4)
	165	#define AFE_MPHONE_MULTI2_DET_MON1 (0x06f8)
	166	#define AFE_MPHONE_MULTI2_DET_MON2 (0x06fc)
	167	#define AFE_ADDA_IIR_COEF_02_01 (0x0700)
	168	#define AFE_ADDA_IIR_COEF_04_03 (0x0704)
	169	#define AFE_ADDA_IIR_COEF_06_05 (0x0708)
	170	#define AFE_ADDA_IIR_COEF_08_07 (0x070c)
	171	#define AFE_ADDA_IIR_COEF_10_09 (0x0710)
	172	#define AFE_ADDA_ULCF_CFG_02_01 (0x0714)
	173	#define AFE_ADDA_ULCF_CFG_04_03 (0x0718)
	174	#define AFE_ADDA_ULCF_CFG_06_05 (0x071c)
	175	#define AFE_ADDA_ULCF_CFG_08_07 (0x0720)
	176	#define AFE_ADDA_ULCF_CFG_10_09 (0x0724)
	177	#define AFE_ADDA_ULCF_CFG_12_11 (0x0728)
	178	#define AFE_ADDA_ULCF_CFG_14_13 (0x072c)
	179	#define AFE_ADDA_ULCF_CFG_16_15 (0x0730)
	180	#define AFE_ADDA_ULCF_CFG_18_17 (0x0734)
	181	#define AFE_ADDA_ULCF_CFG_20_19 (0x0738)
	182	#define AFE_ADDA_ULCF_CFG_22_21 (0x073c)
	183	#define AFE_ADDA_ULCF_CFG_24_23 (0x0740)
	184	#define AFE_ADDA_ULCF_CFG_26_25 (0x0744)
	185	#define AFE_ADDA_ULCF_CFG_28_27 (0x0748)
	186	#define AFE_ADDA_ULCF_CFG_30_29 (0x074c)
	187	#define AFE_ADDA6_IIR_COEF_02_01 (0x0750)
	188	#define AFE_ADDA6_IIR_COEF_04_03 (0x0754)
	189	#define AFE_ADDA6_IIR_COEF_06_05 (0x0758)
	190	#define AFE_ADDA6_IIR_COEF_08_07 (0x075c)
	191	#define AFE_ADDA6_IIR_COEF_10_09 (0x0760)
	192	#define AFE_ADDA6_ULCF_CFG_02_01 (0x0764)
	193	#define AFE_ADDA6_ULCF_CFG_04_03 (0x0768)
	194	#define AFE_ADDA6_ULCF_CFG_06_05 (0x076c)
	195	#define AFE_ADDA6_ULCF_CFG_08_07 (0x0770)
	196	#define AFE_ADDA6_ULCF_CFG_10_09 (0x0774)
	197	#define AFE_ADDA6_ULCF_CFG_12_11 (0x0778)
	198	#define AFE_ADDA6_ULCF_CFG_14_13 (0x077c)
	199	#define AFE_ADDA6_ULCF_CFG_16_15 (0x0780)
	200	#define AFE_ADDA6_ULCF_CFG_18_17 (0x0784)
	201	#define AFE_ADDA6_ULCF_CFG_20_19 (0x0788)
	202	#define AFE_ADDA6_ULCF_CFG_22_21 (0x078c)
	203	#define AFE_ADDA6_ULCF_CFG_24_23 (0x0790)
	204	#define AFE_ADDA6_ULCF_CFG_26_25 (0x0794)
	205	#define AFE_ADDA6_ULCF_CFG_28_27 (0x0798)
	206	#define AFE_ADDA6_ULCF_CFG_30_29 (0x079c)
	207	#define AFE_ADDA_MTKAIF_CFG0 (0x07a0)
	208	#define AFE_ADDA_MTKAIF_SYNCWORD_CFG (0x07a8)
	209	#define AFE_ADDA_MTKAIF_RX_CFG0 (0x07b4)
	210	#define AFE_ADDA_MTKAIF_RX_CFG1 (0x07b8)
	211	#define AFE_ADDA_MTKAIF_RX_CFG2 (0x07bc)
	212	#define AFE_ADDA_MTKAIF_MON0 (0x07c8)
	213	#define AFE_ADDA_MTKAIF_MON1 (0x07cc)
	214	#define AFE_AUD_PAD_TOP (0x07d4)
	215	#define AFE_ADDA6_MTKAIF_MON0 (0x07d8)
	216	#define AFE_ADDA6_MTKAIF_MON1 (0x07dc)
	217	#define AFE_ADDA6_MTKAIF_CFG0 (0x07e0)
	218	#define AFE_ADDA6_MTKAIF_RX_CFG0 (0x07e4)
	219	#define AFE_ADDA6_MTKAIF_RX_CFG1 (0x07e8)
	220	#define AFE_ADDA6_MTKAIF_RX_CFG2 (0x07ec)
	221	#define AFE_ADDA6_TOP_CON0 (0x07f0)
	222	#define AFE_ADDA6_UL_SRC_CON0 (0x07f4)
	223	#define AFE_ADDA6_UL_SRC_CON1 (0x07f8)
	224	#define AFE_ADDA6_SRC_DEBUG (0x0800)
	225	#define AFE_ADDA6_SRC_DEBUG_MON0 (0x0804)
	226	#define AFE_ADDA6_UL_SRC_MON0 (0x0818)
	227	#define AFE_ADDA6_UL_SRC_MON1 (0x081c)
	228	#define AFE_CONN0_5 (0x0830)
	229	#define AFE_CONN1_5 (0x0834)
	230	#define AFE_CONN2_5 (0x0838)
	231	#define AFE_CONN3_5 (0x083c)
	232	#define AFE_CONN4_5 (0x0840)
	233	#define AFE_CONN5_5 (0x0844)
	234	#define AFE_CONN6_5 (0x0848)
	235	#define AFE_CONN7_5 (0x084c)
	236	#define AFE_CONN8_5 (0x0850)
	237	#define AFE_CONN9_5 (0x0854)
	238	#define AFE_CONN10_5 (0x0858)
	239	#define AFE_CONN11_5 (0x085c)
	240	#define AFE_CONN12_5 (0x0860)
	241	#define AFE_CONN13_5 (0x0864)
	242	#define AFE_CONN14_5 (0x0868)
	243	#define AFE_CONN15_5 (0x086c)
	244	#define AFE_CONN16_5 (0x0870)
	245	#define AFE_CONN17_5 (0x0874)
	246	#define AFE_CONN18_5 (0x0878)
	247	#define AFE_CONN19_5 (0x087c)
	248	#define AFE_CONN20_5 (0x0880)
	249	#define AFE_CONN21_5 (0x0884)
	250	#define AFE_CONN22_5 (0x0888)
	251	#define AFE_CONN23_5 (0x088c)
	252	#define AFE_CONN24_5 (0x0890)
	253	#define AFE_CONN25_5 (0x0894)
	254	#define AFE_CONN26_5 (0x0898)
	255	#define AFE_CONN27_5 (0x089c)
	256	#define AFE_CONN28_5 (0x08a0)
	257	#define AFE_CONN29_5 (0x08a4)
	258	#define AFE_CONN30_5 (0x08a8)
	259	#define AFE_CONN31_5 (0x08ac)
	260	#define AFE_CONN32_5 (0x08b0)
	261	#define AFE_CONN33_5 (0x08b4)
	262	#define AFE_CONN34_5 (0x08b8)
	263	#define AFE_CONN35_5 (0x08bc)
	264	#define AFE_CONN36_5 (0x08c0)
	265	#define AFE_CONN37_5 (0x08c4)
	266	#define AFE_CONN38_5 (0x08c8)
	267	#define AFE_CONN39_5 (0x08cc)
	268	#define AFE_CONN40_5 (0x08d0)
	269	#define AFE_CONN41_5 (0x08d4)
	270	#define AFE_CONN42_5 (0x08d8)
	271	#define AFE_CONN43_5 (0x08dc)
	272	#define AFE_CONN44_5 (0x08e0)
	273	#define AFE_CONN45_5 (0x08e4)
	274	#define AFE_CONN46_5 (0x08e8)
	275	#define AFE_CONN47_5 (0x08ec)
	276	#define AFE_CONN48_5 (0x08f0)
	277	#define AFE_CONN49_5 (0x08f4)
	278	#define AFE_CONN50_5 (0x08f8)
	279	#define AFE_CONN51_5 (0x08fc)
	280	#define AFE_CONN52_5 (0x0900)
	281	#define AFE_CONN53_5 (0x0904)
	282	#define AFE_CONN54_5 (0x0908)
	283	#define AFE_CONN55_5 (0x090c)
	284	#define AFE_CONN56_5 (0x0910)
	285	#define AFE_CONN57_5 (0x0914)
	286	#define AFE_CONN58_5 (0x0918)
	287	#define AFE_CONN59_5 (0x091c)
	288	#define AFE_CONN60_5 (0x0920)
	289	#define AFE_CONN61_5 (0x0924)
	290	#define AFE_CONN62_5 (0x0928)
	291	#define AFE_CONN63_5 (0x092c)
	292	#define AFE_CONN64_5 (0x0930)
	293	#define AFE_CONN65_5 (0x0934)
	294	#define AFE_CONN66_5 (0x0938)
	295	#define AFE_CONN67_5 (0x093c)
	296	#define AFE_CONN68_5 (0x0940)
	297	#define AFE_CONN69_5 (0x0944)
	298	#define AFE_CONN70_5 (0x0948)
	299	#define AFE_CONN71_5 (0x094c)
	300	#define AFE_CONN72_5 (0x0950)
	301	#define AFE_CONN73_5 (0x0954)
	302	#define AFE_CONN74_5 (0x0958)
	303	#define AFE_CONN75_5 (0x095c)
	304	#define AFE_CONN76_5 (0x0960)
	305	#define AFE_CONN77_5 (0x0964)
	306	#define AFE_CONN78_5 (0x0968)
	307	#define AFE_CONN79_5 (0x096c)
	308	#define AFE_CONN80_5 (0x0970)
	309	#define AFE_CONN81_5 (0x0974)
	310	#define AFE_CONN82_5 (0x0978)
	311	#define AFE_CONN83_5 (0x097c)
	312	#define AFE_CONN84_5 (0x0980)
	313	#define AFE_CONN85_5 (0x0984)
	314	#define AFE_CONN86_5 (0x0988)
	315	#define AFE_CONN87_5 (0x098c)
	316	#define AFE_CONN88_5 (0x0990)
	317	#define AFE_CONN89_5 (0x0994)
	318	#define AFE_CONN90_5 (0x0998)
	319	#define AFE_CONN91_5 (0x099c)
	320	#define AFE_CONN92_5 (0x09a0)
	321	#define AFE_CONN93_5 (0x09a4)
	322	#define AFE_CONN94_5 (0x09a8)
	323	#define AFE_CONN95_5 (0x09ac)
	324	#define AFE_CONN96_5 (0x09b0)
	325	#define AFE_CONN97_5 (0x09b4)
	326	#define AFE_CONN98_5 (0x09b8)
	327	#define AFE_CONN99_5 (0x09bc)
	328	#define AFE_CONN100_5 (0x09c0)
	329	#define AFE_CONN101_5 (0x09c4)
	330	#define AFE_CONN102_5 (0x09c8)
	331	#define AFE_CONN103_5 (0x09cc)
	332	#define AFE_CONN104_5 (0x09d0)
	333	#define AFE_CONN105_5 (0x09d4)
	334	#define AFE_CONN106_5 (0x09d8)
	335	#define AFE_CONN107_5 (0x09dc)
	336	#define AFE_CONN108_5 (0x09e0)
	337	#define AFE_CONN109_5 (0x09e4)
	338	#define AFE_CONN110_5 (0x09e8)
	339	#define AFE_CONN111_5 (0x09ec)
	340	#define AFE_CONN112_5 (0x09f0)
	341	#define AFE_CONN113_5 (0x09f4)
	342	#define AFE_CONN114_5 (0x09f8)
	343	#define AFE_CONN115_5 (0x09fc)
	344	#define AFE_CONN116_5 (0x0a00)
	345	#define AFE_CONN117_5 (0x0a04)
	346	#define AFE_CONN118_5 (0x0a08)
	347	#define AFE_CONN119_5 (0x0a0c)
	348	#define AFE_CONN120_5 (0x0a10)
	349	#define AFE_CONN121_5 (0x0a14)
	350	#define AFE_CONN122_5 (0x0a18)
	351	#define AFE_CONN123_5 (0x0a1c)
	352	#define AFE_CONN124_5 (0x0a20)
	353	#define AFE_CONN125_5 (0x0a24)
	354	#define AFE_CONN126_5 (0x0a28)
	355	#define AFE_CONN127_5 (0x0a2c)
	356	#define AFE_CONN128_5 (0x0a30)
	357	#define AFE_CONN129_5 (0x0a34)
	358	#define AFE_CONN130_5 (0x0a38)
	359	#define AFE_CONN131_5 (0x0a3c)
	360	#define AFE_CONN132_5 (0x0a40)
	361	#define AFE_CONN133_5 (0x0a44)
	362	#define AFE_CONN134_5 (0x0a48)
	363	#define AFE_CONN135_5 (0x0a4c)
	364	#define AFE_CONN136_5 (0x0a50)
	365	#define AFE_CONN137_5 (0x0a54)
	366	#define AFE_CONN138_5 (0x0a58)
	367	#define AFE_CONN139_5 (0x0a5c)
	368	#define AFE_CONN_RS_5 (0x0a60)
	369	#define AFE_CONN_DI_5 (0x0a64)
	370	#define AFE_CONN_16BIT_5 (0x0a68)
	371	#define AFE_CONN_24BIT_5 (0x0a6c)
	372	#define AFE_ASRC11_NEW_CON0 (0x0d80)
	373	#define AFE_ASRC11_NEW_CON1 (0x0d84)
	374	#define AFE_ASRC11_NEW_CON2 (0x0d88)
	375	#define AFE_ASRC11_NEW_CON3 (0x0d8c)
	376	#define AFE_ASRC11_NEW_CON4 (0x0d90)
	377	#define AFE_ASRC11_NEW_CON5 (0x0d94)
	378	#define AFE_ASRC11_NEW_CON6 (0x0d98)
	379	#define AFE_ASRC11_NEW_CON7 (0x0d9c)
	380	#define AFE_ASRC11_NEW_CON8 (0x0da0)
	381	#define AFE_ASRC11_NEW_CON9 (0x0da4)
	382	#define AFE_ASRC11_NEW_CON10 (0x0da8)
	383	#define AFE_ASRC11_NEW_CON11 (0x0dac)
	384	#define AFE_ASRC11_NEW_CON13 (0x0db4)
	385	#define AFE_ASRC11_NEW_CON14 (0x0db8)
	386	#define AFE_ASRC12_NEW_CON0 (0x0dc0)
	387	#define AFE_ASRC12_NEW_CON1 (0x0dc4)
	388	#define AFE_ASRC12_NEW_CON2 (0x0dc8)
	389	#define AFE_ASRC12_NEW_CON3 (0x0dcc)
	390	#define AFE_ASRC12_NEW_CON4 (0x0dd0)
	391	#define AFE_ASRC12_NEW_CON5 (0x0dd4)
	392	#define AFE_ASRC12_NEW_CON6 (0x0dd8)
	393	#define AFE_ASRC12_NEW_CON7 (0x0ddc)
	394	#define AFE_ASRC12_NEW_CON8 (0x0de0)
	395	#define AFE_ASRC12_NEW_CON9 (0x0de4)
	396	#define AFE_ASRC12_NEW_CON10 (0x0de8)
	397	#define AFE_ASRC12_NEW_CON11 (0x0dec)
	398	#define AFE_ASRC12_NEW_CON13 (0x0df4)
	399	#define AFE_ASRC12_NEW_CON14 (0x0df8)
	400	#define AFE_LRCK_CNT (0x1018)
	401	#define AFE_DAC_CON0 (0x1200)
	402	#define AFE_DAC_CON1 (0x1204)
	403	#define AFE_DAC_CON2 (0x1208)
	404	#define AFE_DAC_MON0 (0x1218)
	405	#define AFE_DL2_BASE (0x1250)
	406	#define AFE_DL2_CUR (0x1254)
	407	#define AFE_DL2_END (0x1258)
	408	#define AFE_DL2_CON0 (0x125c)
	409	#define AFE_DL3_BASE (0x1260)
	410	#define AFE_DL3_CUR (0x1264)
	411	#define AFE_DL3_END (0x1268)
	412	#define AFE_DL3_CON0 (0x126c)
	413	#define AFE_DL6_BASE (0x1290)
	414	#define AFE_DL6_CUR (0x1294)
	415	#define AFE_DL6_END (0x1298)
	416	#define AFE_DL6_CON0 (0x129c)
	417	#define AFE_DL7_BASE (0x12a0)
	418	#define AFE_DL7_CUR (0x12a4)
	419	#define AFE_DL7_END (0x12a8)
	420	#define AFE_DL7_CON0 (0x12ac)
	421	#define AFE_DL8_BASE (0x12b0)
	422	#define AFE_DL8_CUR (0x12b4)
	423	#define AFE_DL8_END (0x12b8)
	424	#define AFE_DL8_CON0 (0x12bc)
	425	#define AFE_DL10_BASE (0x12d0)
	426	#define AFE_DL10_CUR (0x12d4)
	427	#define AFE_DL10_END (0x12d8)
	428	#define AFE_DL10_CON0 (0x12dc)
	429	#define AFE_DL11_BASE (0x12e0)
	430	#define AFE_DL11_CUR (0x12e4)
	431	#define AFE_DL11_END (0x12e8)
	432	#define AFE_DL11_CON0 (0x12ec)
	433	#define AFE_UL1_BASE (0x1300)
	434	#define AFE_UL1_CUR (0x1304)
	435	#define AFE_UL1_END (0x1308)
	436	#define AFE_UL1_CON0 (0x130c)
	437	#define AFE_UL2_BASE (0x1310)
	438	#define AFE_UL2_CUR (0x1314)
	439	#define AFE_UL2_END (0x1318)
	440	#define AFE_UL2_CON0 (0x131c)
	441	#define AFE_UL3_BASE (0x1320)
	442	#define AFE_UL3_CUR (0x1324)
	443	#define AFE_UL3_END (0x1328)
	444	#define AFE_UL3_CON0 (0x132c)
	445	#define AFE_UL4_BASE (0x1330)
	446	#define AFE_UL4_CUR (0x1334)
	447	#define AFE_UL4_END (0x1338)
	448	#define AFE_UL4_CON0 (0x133c)
	449	#define AFE_UL5_BASE (0x1340)
	450	#define AFE_UL5_CUR (0x1344)
	451	#define AFE_UL5_END (0x1348)
	452	#define AFE_UL5_CON0 (0x134c)
	453	#define AFE_UL6_BASE (0x1350)
	454	#define AFE_UL6_CUR (0x1354)
	455	#define AFE_UL6_END (0x1358)
	456	#define AFE_UL6_CON0 (0x135c)
	457	#define AFE_UL8_BASE (0x1370)
	458	#define AFE_UL8_CUR (0x1374)
	459	#define AFE_UL8_END (0x1378)
	460	#define AFE_UL8_CON0 (0x137c)
	461	#define AFE_UL9_BASE (0x1380)
	462	#define AFE_UL9_CUR (0x1384)
	463	#define AFE_UL9_END (0x1388)
	464	#define AFE_UL9_CON0 (0x138c)
	465	#define AFE_UL10_BASE (0x13d0)
	466	#define AFE_UL10_CUR (0x13d4)
	467	#define AFE_UL10_END (0x13d8)
	468	#define AFE_UL10_CON0 (0x13dc)
	469	#define AFE_DL8_CHK_SUM1 (0x1400)
	470	#define AFE_DL8_CHK_SUM2 (0x1404)
	471	#define AFE_DL8_CHK_SUM3 (0x1408)
	472	#define AFE_DL8_CHK_SUM4 (0x140c)
	473	#define AFE_DL8_CHK_SUM5 (0x1410)
	474	#define AFE_DL8_CHK_SUM6 (0x1414)
	475	#define AFE_DL10_CHK_SUM1 (0x1418)
	476	#define AFE_DL10_CHK_SUM2 (0x141c)
	477	#define AFE_DL10_CHK_SUM3 (0x1420)
	478	#define AFE_DL10_CHK_SUM4 (0x1424)
	479	#define AFE_DL10_CHK_SUM5 (0x1428)
	480	#define AFE_DL10_CHK_SUM6 (0x142c)
	481	#define AFE_DL11_CHK_SUM1 (0x1430)
	482	#define AFE_DL11_CHK_SUM2 (0x1434)
	483	#define AFE_DL11_CHK_SUM3 (0x1438)
	484	#define AFE_DL11_CHK_SUM4 (0x143c)
	485	#define AFE_DL11_CHK_SUM5 (0x1440)
	486	#define AFE_DL11_CHK_SUM6 (0x1444)
	487	#define AFE_UL1_CHK_SUM1 (0x1450)
	488	#define AFE_UL1_CHK_SUM2 (0x1454)
	489	#define AFE_UL2_CHK_SUM1 (0x1458)
	490	#define AFE_UL2_CHK_SUM2 (0x145c)
	491	#define AFE_UL3_CHK_SUM1 (0x1460)
	492	#define AFE_UL3_CHK_SUM2 (0x1464)
	493	#define AFE_UL4_CHK_SUM1 (0x1468)
	494	#define AFE_UL4_CHK_SUM2 (0x146c)
	495	#define AFE_UL5_CHK_SUM1 (0x1470)
	496	#define AFE_UL5_CHK_SUM2 (0x1474)
	497	#define AFE_UL6_CHK_SUM1 (0x1478)
	498	#define AFE_UL6_CHK_SUM2 (0x147c)
	499	#define AFE_UL8_CHK_SUM1 (0x1488)
	500	#define AFE_UL8_CHK_SUM2 (0x148c)
	501	#define AFE_DL2_CHK_SUM1 (0x14a0)
	502	#define AFE_DL2_CHK_SUM2 (0x14a4)
	503	#define AFE_DL3_CHK_SUM1 (0x14b0)
	504	#define AFE_DL3_CHK_SUM2 (0x14b4)
	505	#define AFE_DL6_CHK_SUM1 (0x14e0)
	506	#define AFE_DL6_CHK_SUM2 (0x14e4)
	507	#define AFE_DL7_CHK_SUM1 (0x14f0)
	508	#define AFE_DL7_CHK_SUM2 (0x14f4)
	509	#define AFE_UL9_CHK_SUM1 (0x1528)
	510	#define AFE_UL9_CHK_SUM2 (0x152c)
	511	#define AFE_BUS_MON1 (0x1540)
	512	#define UL1_MOD2AGT_CNT_LAT (0x1568)
	513	#define UL2_MOD2AGT_CNT_LAT (0x156c)
	514	#define UL3_MOD2AGT_CNT_LAT (0x1570)
	515	#define UL4_MOD2AGT_CNT_LAT (0x1574)
	516	#define UL5_MOD2AGT_CNT_LAT (0x1578)
	517	#define UL6_MOD2AGT_CNT_LAT (0x157c)
	518	#define UL8_MOD2AGT_CNT_LAT (0x1588)
	519	#define UL9_MOD2AGT_CNT_LAT (0x158c)
	520	#define UL10_MOD2AGT_CNT_LAT (0x1590)
	521	#define AFE_MEMIF_AGENT_FS_CON0 (0x15a0)
	522	#define AFE_MEMIF_AGENT_FS_CON1 (0x15a4)
	523	#define AFE_MEMIF_AGENT_FS_CON2 (0x15a8)
	524	#define AFE_MEMIF_AGENT_FS_CON3 (0x15ac)
	525	#define AFE_MEMIF_BURST_CFG (0x1600)
	526	#define AFE_MEMIF_BUF_FULL_MON (0x1610)
	527	#define AFE_MEMIF_BUF_MON1 (0x161c)
	528	#define AFE_MEMIF_BUF_MON3 (0x1624)
	529	#define AFE_MEMIF_BUF_MON4 (0x1628)
	530	#define AFE_MEMIF_BUF_MON5 (0x162c)
	531	#define AFE_MEMIF_BUF_MON6 (0x1630)
	532	#define AFE_MEMIF_BUF_MON7 (0x1634)
	533	#define AFE_MEMIF_BUF_MON8 (0x1638)
	534	#define AFE_MEMIF_BUF_MON9 (0x163c)
	535	#define AFE_MEMIF_BUF_MON10 (0x1640)
	536	#define DL2_AGENT2MODULE_CNT (0x1678)
	537	#define DL3_AGENT2MODULE_CNT (0x167c)
	538	#define DL6_AGENT2MODULE_CNT (0x1688)
	539	#define DL7_AGENT2MODULE_CNT (0x168c)
	540	#define DL8_AGENT2MODULE_CNT (0x1690)
	541	#define DL10_AGENT2MODULE_CNT (0x1698)
	542	#define DL11_AGENT2MODULE_CNT (0x169c)
	543	#define UL1_MODULE2AGENT_CNT (0x16a0)
	544	#define UL2_MODULE2AGENT_CNT (0x16a4)
	545	#define UL3_MODULE2AGENT_CNT (0x16a8)
	546	#define UL4_MODULE2AGENT_CNT (0x16ac)
	547	#define UL5_MODULE2AGENT_CNT (0x16b0)
	548	#define UL6_MODULE2AGENT_CNT (0x16b4)
	549	#define UL8_MODULE2AGENT_CNT (0x16bc)
	550	#define UL9_MODULE2AGENT_CNT (0x16c0)
	551	#define UL10_MODULE2AGENT_CNT (0x16c4)
	552	#define AFE_SECURE_CON2 (0x1798)
	553	#define AFE_SECURE_CON1 (0x179c)
	554	#define AFE_SECURE_CON (0x17a0)
	555	#define AFE_SRAM_BOUND (0x17a4)
	556	#define AFE_SE_SECURE_CON (0x17a8)
	557	#define AFE_SECURE_MASK_LOOPBACK (0x17bc)
	558	#define AFE_SECURE_SIDEBAND0 (0x1908)
	559	#define AFE_SECURE_SIDEBAND1 (0x190c)
	560	#define AFE_SECURE_SIDEBAND2 (0x1910)
	561	#define AFE_SECURE_SIDEBAND3 (0x1914)
	562	#define AFE_SECURE_MASK_BASE_ADR_MSB (0x1920)
	563	#define AFE_SECURE_MASK_END_ADR_MSB (0x1924)
	564	#define AFE_NORMAL_BASE_ADR_MSB (0x192c)
	565	#define AFE_NORMAL_END_ADR_MSB (0x1930)
	566	#define AFE_SECURE_MASK_LOOPBACK0 (0x1940)
	567	#define AFE_SECURE_MASK_LOOPBACK1 (0x1944)
	568	#define AFE_SECURE_MASK_LOOPBACK2 (0x1948)
	569	#define AFE_LOOPBACK_CFG0 (0x1950)
	570	#define AFE_LOOPBACK_CFG1 (0x1954)
	571	#define AFE_LOOPBACK_CFG2 (0x1958)
	572	#define AFE_DMIC0_UL_SRC_CON0 (0x1a00)
	573	#define AFE_DMIC0_UL_SRC_CON1 (0x1a04)
	574	#define AFE_DMIC0_SRC_DEBUG (0x1a08)
	575	#define AFE_DMIC0_SRC_DEBUG_MON0 (0x1a0c)
	576	#define AFE_DMIC0_UL_SRC_MON0 (0x1a10)
	577	#define AFE_DMIC0_UL_SRC_MON1 (0x1a14)
	578	#define AFE_DMIC0_IIR_COEF_02_01 (0x1a18)
	579	#define AFE_DMIC0_IIR_COEF_04_03 (0x1a1c)
	580	#define AFE_DMIC0_IIR_COEF_06_05 (0x1a20)
	581	#define AFE_DMIC0_IIR_COEF_08_07 (0x1a24)
	582	#define AFE_DMIC0_IIR_COEF_10_09 (0x1a28)
	583	#define AFE_DMIC1_UL_SRC_CON0 (0x1a68)
	584	#define AFE_DMIC1_UL_SRC_CON1 (0x1a6c)
	585	#define AFE_DMIC1_SRC_DEBUG (0x1a70)
	586	#define AFE_DMIC1_SRC_DEBUG_MON0 (0x1a74)
	587	#define AFE_DMIC1_UL_SRC_MON0 (0x1a78)
	588	#define AFE_DMIC1_UL_SRC_MON1 (0x1a7c)
	589	#define AFE_DMIC1_IIR_COEF_02_01 (0x1a80)
	590	#define AFE_DMIC1_IIR_COEF_04_03 (0x1a84)
	591	#define AFE_DMIC1_IIR_COEF_06_05 (0x1a88)
	592	#define AFE_DMIC1_IIR_COEF_08_07 (0x1a8c)
	593	#define AFE_DMIC1_IIR_COEF_10_09 (0x1a90)
	594	#define AFE_DMIC2_UL_SRC_CON0 (0x1ad0)
	595	#define AFE_DMIC2_UL_SRC_CON1 (0x1ad4)
	596	#define AFE_DMIC2_SRC_DEBUG (0x1ad8)
	597	#define AFE_DMIC2_SRC_DEBUG_MON0 (0x1adc)
	598	#define AFE_DMIC2_UL_SRC_MON0 (0x1ae0)
	599	#define AFE_DMIC2_UL_SRC_MON1 (0x1ae4)
	600	#define AFE_DMIC2_IIR_COEF_02_01 (0x1ae8)
	601	#define AFE_DMIC2_IIR_COEF_04_03 (0x1aec)
	602	#define AFE_DMIC2_IIR_COEF_06_05 (0x1af0)
	603	#define AFE_DMIC2_IIR_COEF_08_07 (0x1af4)
	604	#define AFE_DMIC2_IIR_COEF_10_09 (0x1af8)
	605	#define AFE_DMIC3_UL_SRC_CON0 (0x1b38)
	606	#define AFE_DMIC3_UL_SRC_CON1 (0x1b3c)
	607	#define AFE_DMIC3_SRC_DEBUG (0x1b40)
	608	#define AFE_DMIC3_SRC_DEBUG_MON0 (0x1b44)
	609	#define AFE_DMIC3_UL_SRC_MON0 (0x1b48)
	610	#define AFE_DMIC3_UL_SRC_MON1 (0x1b4c)
	611	#define AFE_DMIC3_IIR_COEF_02_01 (0x1b50)
	612	#define AFE_DMIC3_IIR_COEF_04_03 (0x1b54)
	613	#define AFE_DMIC3_IIR_COEF_06_05 (0x1b58)
	614	#define AFE_DMIC3_IIR_COEF_08_07 (0x1b5c)
	615	#define AFE_DMIC3_IIR_COEF_10_09 (0x1b60)
	616	#define DMIC_BYPASS_HW_GAIN (0x1bf0)
	617	#define DMIC_GAIN1_CON0 (0x1c00)
	618	#define DMIC_GAIN1_CON1 (0x1c04)
	619	#define DMIC_GAIN1_CON2 (0x1c08)
	620	#define DMIC_GAIN1_CON3 (0x1c0c)
	621	#define DMIC_GAIN1_CUR (0x1c10)
	622	#define DMIC_GAIN2_CON0 (0x1c20)
	623	#define DMIC_GAIN2_CON1 (0x1c24)
	624	#define DMIC_GAIN2_CON2 (0x1c28)
	625	#define DMIC_GAIN2_CON3 (0x1c2c)
	626	#define DMIC_GAIN2_CUR (0x1c30)
	627	#define DMIC_GAIN3_CON0 (0x1c40)
	628	#define DMIC_GAIN3_CON1 (0x1c44)
	629	#define DMIC_GAIN3_CON2 (0x1c48)
	630	#define DMIC_GAIN3_CON3 (0x1c4c)
	631	#define DMIC_GAIN3_CUR (0x1c50)
	632	#define DMIC_GAIN4_CON0 (0x1c60)
	633	#define DMIC_GAIN4_CON1 (0x1c64)
	634	#define DMIC_GAIN4_CON2 (0x1c68)
	635	#define DMIC_GAIN4_CON3 (0x1c6c)
	636	#define DMIC_GAIN4_CUR (0x1c70)
	637	#define ETDM_OUT1_DSD_FADE_CON (0x2260)
	638	#define ETDM_OUT1_DSD_FADE_CON1 (0x2264)
	639	#define ETDM_OUT3_DSD_FADE_CON (0x2280)
	640	#define ETDM_OUT3_DSD_FADE_CON1 (0x2284)
	641	#define ETDM_IN1_AFIFO_CON (0x2294)
	642	#define ETDM_IN2_AFIFO_CON (0x2298)
	643	#define ETDM_IN1_MONITOR (0x22c0)
	644	#define ETDM_IN2_MONITOR (0x22c4)
	645	#define ETDM_OUT1_MONITOR (0x22d0)
	646	#define ETDM_OUT2_MONITOR (0x22d4)
	647	#define ETDM_OUT3_MONITOR (0x22d8)
	648	#define ETDM_COWORK_SEC_CON0 (0x22e0)
	649	#define ETDM_COWORK_SEC_CON1 (0x22e4)
	650	#define ETDM_COWORK_SEC_CON2 (0x22e8)
	651	#define ETDM_COWORK_SEC_CON3 (0x22ec)
	652	#define ETDM_COWORK_CON0 (0x22f0)
	653	#define ETDM_COWORK_CON1 (0x22f4)
	654	#define ETDM_COWORK_CON2 (0x22f8)
	655	#define ETDM_COWORK_CON3 (0x22fc)
	656	#define ETDM_IN1_CON0 (0x2300)
	657	#define ETDM_IN1_CON1 (0x2304)
	658	#define ETDM_IN1_CON2 (0x2308)
	659	#define ETDM_IN1_CON3 (0x230c)
	660	#define ETDM_IN1_CON4 (0x2310)
	661	#define ETDM_IN1_CON5 (0x2314)
	662	#define ETDM_IN1_CON6 (0x2318)
	663	#define ETDM_IN1_CON7 (0x231c)
	664	#define ETDM_IN2_CON0 (0x2320)
	665	#define ETDM_IN2_CON1 (0x2324)
	666	#define ETDM_IN2_CON2 (0x2328)
	667	#define ETDM_IN2_CON3 (0x232c)
	668	#define ETDM_IN2_CON4 (0x2330)
	669	#define ETDM_IN2_CON5 (0x2334)
	670	#define ETDM_IN2_CON6 (0x2338)
	671	#define ETDM_IN2_CON7 (0x233c)
	672	#define ETDM_OUT1_CON0 (0x2380)
	673	#define ETDM_OUT1_CON1 (0x2384)
	674	#define ETDM_OUT1_CON2 (0x2388)
	675	#define ETDM_OUT1_CON3 (0x238c)
	676	#define ETDM_OUT1_CON4 (0x2390)
	677	#define ETDM_OUT1_CON5 (0x2394)
	678	#define ETDM_OUT1_CON6 (0x2398)
	679	#define ETDM_OUT1_CON7 (0x239c)
	680	#define ETDM_OUT2_CON0 (0x23a0)
	681	#define ETDM_OUT2_CON1 (0x23a4)
	682	#define ETDM_OUT2_CON2 (0x23a8)
	683	#define ETDM_OUT2_CON3 (0x23ac)
	684	#define ETDM_OUT2_CON4 (0x23b0)
	685	#define ETDM_OUT2_CON5 (0x23b4)
	686	#define ETDM_OUT2_CON6 (0x23b8)
	687	#define ETDM_OUT2_CON7 (0x23bc)
	688	#define ETDM_OUT3_CON0 (0x23c0)
	689	#define ETDM_OUT3_CON1 (0x23c4)
	690	#define ETDM_OUT3_CON2 (0x23c8)
	691	#define ETDM_OUT3_CON3 (0x23cc)
	692	#define ETDM_OUT3_CON4 (0x23d0)
	693	#define ETDM_OUT3_CON5 (0x23d4)
	694	#define ETDM_OUT3_CON6 (0x23d8)
	695	#define ETDM_OUT3_CON7 (0x23dc)
	696	#define ETDM_OUT3_CON8 (0x23e0)
	697	#define ETDM_OUT1_CON8 (0x23e4)
	698	#define ETDM_OUT2_CON8 (0x23e8)
	699	#define GASRC_TIMING_CON0 (0x2414)
	700	#define GASRC_TIMING_CON1 (0x2418)
	701	#define GASRC_TIMING_CON2 (0x241c)
	702	#define GASRC_TIMING_CON3 (0x2420)
	703	#define GASRC_TIMING_CON4 (0x2424)
	704	#define GASRC_TIMING_CON5 (0x2428)
	705	#define GASRC_TIMING_CON6 (0x242c)
	706	#define GASRC_TIMING_CON7 (0x2430)
	707	#define A3_A4_TIMING_SEL0 (0x2440)
	708	#define A3_A4_TIMING_SEL1 (0x2444)
	709	#define A3_A4_TIMING_SEL2 (0x2448)
	710	#define A3_A4_TIMING_SEL3 (0x244c)
	711	#define A3_A4_TIMING_SEL4 (0x2450)
	712	#define A3_A4_TIMING_SEL5 (0x2454)
	713	#define A3_A4_TIMING_SEL6 (0x2458)
	714	#define ASYS_TOP_DEBUG (0x2500)
	715	#define AFE_DPTX_CON (0x2558)
	716	#define AFE_DPTX_MON (0x255c)
	717	#define AFE_ADDA_DL_SRC2_CON0 (0x2d00)
	718	#define AFE_ADDA_DL_SRC2_CON1 (0x2d04)
	719	#define AFE_ADDA_TOP_CON0 (0x2d0c)
	720	#define AFE_ADDA_UL_DL_CON0 (0x2d10)
	721	#define AFE_ADDA_SRC_DEBUG (0x2d14)
	722	#define AFE_ADDA_SRC_DEBUG_MON0 (0x2d18)
	723	#define AFE_ADDA_SRC_DEBUG_MON1 (0x2d20)
	724	#define AFE_ADDA_PREDIS_CON0 (0x2d24)
	725	#define AFE_ADDA_PREDIS_CON1 (0x2d28)
	726	#define AFE_ADDA_PREDIS_CON2 (0x2d2c)
	727	#define AFE_ADDA_PREDIS_CON3 (0x2d30)
	728	#define AFE_ADDA_DL_SDM_DCCOMP_CON (0x2d34)
	729	#define AFE_ADDA_DL_SDM_TEST (0x2d38)
	730	#define AFE_ADDA_DL_DC_COMP_CFG0 (0x2d3c)
	731	#define AFE_ADDA_DL_DC_COMP_CFG1 (0x2d40)
	732	#define AFE_ADDA_DL_SDM_FIFO_MON (0x2d44)
	733	#define AFE_ADDA_DL_SRC_LCH_MON (0x2d50)
	734	#define AFE_ADDA_DL_SRC_RCH_MON (0x2d54)
	735	#define AFE_ADDA_DL_SDM_OUT_MON (0x2d58)
	736	#define AFE_ADDA_DL_SDM_DITHER_CON (0x2d5c)
	737	#define AFE_ADDA_DL_SDM_AUTO_RESET_CON (0x2d60)
	738	#define AFE_ADDA_UL_SRC_CON0 (0x2e3c)
	739	#define AFE_ADDA_UL_SRC_CON1 (0x2e40)
	740	#define AFE_CONN0 (0x3000)
	741	#define AFE_CONN0_1 (0x3004)
	742	#define AFE_CONN0_2 (0x3008)
	743	#define AFE_CONN0_3 (0x300c)
	744	#define AFE_CONN0_4 (0x3010)
	745	#define AFE_CONN1 (0x3014)
	746	#define AFE_CONN1_1 (0x3018)
	747	#define AFE_CONN1_2 (0x301c)
	748	#define AFE_CONN1_3 (0x3020)
	749	#define AFE_CONN1_4 (0x3024)
	750	#define AFE_CONN2 (0x3028)
	751	#define AFE_CONN2_1 (0x302c)
	752	#define AFE_CONN2_2 (0x3030)
	753	#define AFE_CONN2_3 (0x3034)
	754	#define AFE_CONN2_4 (0x3038)
	755	#define AFE_CONN3 (0x303c)
	756	#define AFE_CONN3_1 (0x3040)
	757	#define AFE_CONN3_2 (0x3044)
	758	#define AFE_CONN3_3 (0x3048)
	759	#define AFE_CONN3_4 (0x304c)
	760	#define AFE_CONN4 (0x3050)
	761	#define AFE_CONN4_1 (0x3054)
	762	#define AFE_CONN4_2 (0x3058)
	763	#define AFE_CONN4_3 (0x305c)
	764	#define AFE_CONN4_4 (0x3060)
	765	#define AFE_CONN5 (0x3064)
	766	#define AFE_CONN5_1 (0x3068)
	767	#define AFE_CONN5_2 (0x306c)
	768	#define AFE_CONN5_3 (0x3070)
	769	#define AFE_CONN5_4 (0x3074)
	770	#define AFE_CONN6 (0x3078)
	771	#define AFE_CONN6_1 (0x307c)
	772	#define AFE_CONN6_2 (0x3080)
	773	#define AFE_CONN6_3 (0x3084)
	774	#define AFE_CONN6_4 (0x3088)
	775	#define AFE_CONN7 (0x308c)
	776	#define AFE_CONN7_1 (0x3090)
	777	#define AFE_CONN7_2 (0x3094)
	778	#define AFE_CONN7_3 (0x3098)
	779	#define AFE_CONN7_4 (0x309c)
	780	#define AFE_CONN8 (0x30a0)
	781	#define AFE_CONN8_1 (0x30a4)
	782	#define AFE_CONN8_2 (0x30a8)
	783	#define AFE_CONN8_3 (0x30ac)
	784	#define AFE_CONN8_4 (0x30b0)
	785	#define AFE_CONN9 (0x30b4)
	786	#define AFE_CONN9_1 (0x30b8)
	787	#define AFE_CONN9_2 (0x30bc)
	788	#define AFE_CONN9_3 (0x30c0)
	789	#define AFE_CONN9_4 (0x30c4)
	790	#define AFE_CONN10 (0x30c8)
	791	#define AFE_CONN10_1 (0x30cc)
	792	#define AFE_CONN10_2 (0x30d0)
	793	#define AFE_CONN10_3 (0x30d4)
	794	#define AFE_CONN10_4 (0x30d8)
	795	#define AFE_CONN11 (0x30dc)
	796	#define AFE_CONN11_1 (0x30e0)
	797	#define AFE_CONN11_2 (0x30e4)
	798	#define AFE_CONN11_3 (0x30e8)
	799	#define AFE_CONN11_4 (0x30ec)
	800	#define AFE_CONN12 (0x30f0)
	801	#define AFE_CONN12_1 (0x30f4)
	802	#define AFE_CONN12_2 (0x30f8)
	803	#define AFE_CONN12_3 (0x30fc)
	804	#define AFE_CONN12_4 (0x3100)
	805	#define AFE_CONN13 (0x3104)
	806	#define AFE_CONN13_1 (0x3108)
	807	#define AFE_CONN13_2 (0x310c)
	808	#define AFE_CONN13_3 (0x3110)
	809	#define AFE_CONN13_4 (0x3114)
	810	#define AFE_CONN14 (0x3118)
	811	#define AFE_CONN14_1 (0x311c)
	812	#define AFE_CONN14_2 (0x3120)
	813	#define AFE_CONN14_3 (0x3124)
	814	#define AFE_CONN14_4 (0x3128)
	815	#define AFE_CONN15 (0x312c)
	816	#define AFE_CONN15_1 (0x3130)
	817	#define AFE_CONN15_2 (0x3134)
	818	#define AFE_CONN15_3 (0x3138)
	819	#define AFE_CONN15_4 (0x313c)
	820	#define AFE_CONN16 (0x3140)
	821	#define AFE_CONN16_1 (0x3144)
	822	#define AFE_CONN16_2 (0x3148)
	823	#define AFE_CONN16_3 (0x314c)
	824	#define AFE_CONN16_4 (0x3150)
	825	#define AFE_CONN17 (0x3154)
	826	#define AFE_CONN17_1 (0x3158)
	827	#define AFE_CONN17_2 (0x315c)
	828	#define AFE_CONN17_3 (0x3160)
	829	#define AFE_CONN17_4 (0x3164)
	830	#define AFE_CONN18 (0x3168)
	831	#define AFE_CONN18_1 (0x316c)
	832	#define AFE_CONN18_2 (0x3170)
	833	#define AFE_CONN18_3 (0x3174)
	834	#define AFE_CONN18_4 (0x3178)
	835	#define AFE_CONN19 (0x317c)
	836	#define AFE_CONN19_1 (0x3180)
	837	#define AFE_CONN19_2 (0x3184)
	838	#define AFE_CONN19_3 (0x3188)
	839	#define AFE_CONN19_4 (0x318c)
	840	#define AFE_CONN20 (0x3190)
	841	#define AFE_CONN20_1 (0x3194)
	842	#define AFE_CONN20_2 (0x3198)
	843	#define AFE_CONN20_3 (0x319c)
	844	#define AFE_CONN20_4 (0x31a0)
	845	#define AFE_CONN21 (0x31a4)
	846	#define AFE_CONN21_1 (0x31a8)
	847	#define AFE_CONN21_2 (0x31ac)
	848	#define AFE_CONN21_3 (0x31b0)
	849	#define AFE_CONN21_4 (0x31b4)
	850	#define AFE_CONN22 (0x31b8)
	851	#define AFE_CONN22_1 (0x31bc)
	852	#define AFE_CONN22_2 (0x31c0)
	853	#define AFE_CONN22_3 (0x31c4)
	854	#define AFE_CONN22_4 (0x31c8)
	855	#define AFE_CONN23 (0x31cc)
	856	#define AFE_CONN23_1 (0x31d0)
	857	#define AFE_CONN23_2 (0x31d4)
	858	#define AFE_CONN23_3 (0x31d8)
	859	#define AFE_CONN23_4 (0x31dc)
	860	#define AFE_CONN24 (0x31e0)
	861	#define AFE_CONN24_1 (0x31e4)
	862	#define AFE_CONN24_2 (0x31e8)
	863	#define AFE_CONN24_3 (0x31ec)
	864	#define AFE_CONN24_4 (0x31f0)
	865	#define AFE_CONN25 (0x31f4)
	866	#define AFE_CONN25_1 (0x31f8)
	867	#define AFE_CONN25_2 (0x31fc)
	868	#define AFE_CONN25_3 (0x3200)
	869	#define AFE_CONN25_4 (0x3204)
	870	#define AFE_CONN26 (0x3208)
	871	#define AFE_CONN26_1 (0x320c)
	872	#define AFE_CONN26_2 (0x3210)
	873	#define AFE_CONN26_3 (0x3214)
	874	#define AFE_CONN26_4 (0x3218)
	875	#define AFE_CONN27 (0x321c)
	876	#define AFE_CONN27_1 (0x3220)
	877	#define AFE_CONN27_2 (0x3224)
	878	#define AFE_CONN27_3 (0x3228)
	879	#define AFE_CONN27_4 (0x322c)
	880	#define AFE_CONN28 (0x3230)
	881	#define AFE_CONN28_1 (0x3234)
	882	#define AFE_CONN28_2 (0x3238)
	883	#define AFE_CONN28_3 (0x323c)
	884	#define AFE_CONN28_4 (0x3240)
	885	#define AFE_CONN29 (0x3244)
	886	#define AFE_CONN29_1 (0x3248)
	887	#define AFE_CONN29_2 (0x324c)
	888	#define AFE_CONN29_3 (0x3250)
	889	#define AFE_CONN29_4 (0x3254)
	890	#define AFE_CONN30 (0x3258)
	891	#define AFE_CONN30_1 (0x325c)
	892	#define AFE_CONN30_2 (0x3260)
	893	#define AFE_CONN30_3 (0x3264)
	894	#define AFE_CONN30_4 (0x3268)
	895	#define AFE_CONN31 (0x326c)
	896	#define AFE_CONN31_1 (0x3270)
	897	#define AFE_CONN31_2 (0x3274)
	898	#define AFE_CONN31_3 (0x3278)
	899	#define AFE_CONN31_4 (0x327c)
	900	#define AFE_CONN32 (0x3280)
	901	#define AFE_CONN32_1 (0x3284)
	902	#define AFE_CONN32_2 (0x3288)
	903	#define AFE_CONN32_3 (0x328c)
	904	#define AFE_CONN32_4 (0x3290)
	905	#define AFE_CONN33 (0x3294)
	906	#define AFE_CONN33_1 (0x3298)
	907	#define AFE_CONN33_2 (0x329c)
	908	#define AFE_CONN33_3 (0x32a0)
	909	#define AFE_CONN33_4 (0x32a4)
	910	#define AFE_CONN34 (0x32a8)
	911	#define AFE_CONN34_1 (0x32ac)
	912	#define AFE_CONN34_2 (0x32b0)
	913	#define AFE_CONN34_3 (0x32b4)
	914	#define AFE_CONN34_4 (0x32b8)
	915	#define AFE_CONN35 (0x32bc)
	916	#define AFE_CONN35_1 (0x32c0)
	917	#define AFE_CONN35_2 (0x32c4)
	918	#define AFE_CONN35_3 (0x32c8)
	919	#define AFE_CONN35_4 (0x32cc)
	920	#define AFE_CONN36 (0x32d0)
	921	#define AFE_CONN36_1 (0x32d4)
	922	#define AFE_CONN36_2 (0x32d8)
	923	#define AFE_CONN36_3 (0x32dc)
	924	#define AFE_CONN36_4 (0x32e0)
	925	#define AFE_CONN37 (0x32e4)
	926	#define AFE_CONN37_1 (0x32e8)
	927	#define AFE_CONN37_2 (0x32ec)
	928	#define AFE_CONN37_3 (0x32f0)
	929	#define AFE_CONN37_4 (0x32f4)
	930	#define AFE_CONN38 (0x32f8)
	931	#define AFE_CONN38_1 (0x32fc)
	932	#define AFE_CONN38_2 (0x3300)
	933	#define AFE_CONN38_3 (0x3304)
	934	#define AFE_CONN38_4 (0x3308)
	935	#define AFE_CONN39 (0x330c)
	936	#define AFE_CONN39_1 (0x3310)
	937	#define AFE_CONN39_2 (0x3314)
	938	#define AFE_CONN39_3 (0x3318)
	939	#define AFE_CONN39_4 (0x331c)
	940	#define AFE_CONN40 (0x3320)
	941	#define AFE_CONN40_1 (0x3324)
	942	#define AFE_CONN40_2 (0x3328)
	943	#define AFE_CONN40_3 (0x332c)
	944	#define AFE_CONN40_4 (0x3330)
	945	#define AFE_CONN41 (0x3334)
	946	#define AFE_CONN41_1 (0x3338)
	947	#define AFE_CONN41_2 (0x333c)
	948	#define AFE_CONN41_3 (0x3340)
	949	#define AFE_CONN41_4 (0x3344)
	950	#define AFE_CONN42 (0x3348)
	951	#define AFE_CONN42_1 (0x334c)
	952	#define AFE_CONN42_2 (0x3350)
	953	#define AFE_CONN42_3 (0x3354)
	954	#define AFE_CONN42_4 (0x3358)
	955	#define AFE_CONN43 (0x335c)
	956	#define AFE_CONN43_1 (0x3360)
	957	#define AFE_CONN43_2 (0x3364)
	958	#define AFE_CONN43_3 (0x3368)
	959	#define AFE_CONN43_4 (0x336c)
	960	#define AFE_CONN44 (0x3370)
	961	#define AFE_CONN44_1 (0x3374)
	962	#define AFE_CONN44_2 (0x3378)
	963	#define AFE_CONN44_3 (0x337c)
	964	#define AFE_CONN44_4 (0x3380)
	965	#define AFE_CONN45 (0x3384)
	966	#define AFE_CONN45_1 (0x3388)
	967	#define AFE_CONN45_2 (0x338c)
	968	#define AFE_CONN45_3 (0x3390)
	969	#define AFE_CONN45_4 (0x3394)
	970	#define AFE_CONN46 (0x3398)
	971	#define AFE_CONN46_1 (0x339c)
	972	#define AFE_CONN46_2 (0x33a0)
	973	#define AFE_CONN46_3 (0x33a4)
	974	#define AFE_CONN46_4 (0x33a8)
	975	#define AFE_CONN47 (0x33ac)
	976	#define AFE_CONN47_1 (0x33b0)
	977	#define AFE_CONN47_2 (0x33b4)
	978	#define AFE_CONN47_3 (0x33b8)
	979	#define AFE_CONN47_4 (0x33bc)
	980	#define AFE_CONN48 (0x33c0)
	981	#define AFE_CONN48_1 (0x33c4)
	982	#define AFE_CONN48_2 (0x33c8)
	983	#define AFE_CONN48_3 (0x33cc)
	984	#define AFE_CONN48_4 (0x33d0)
	985	#define AFE_CONN49 (0x33d4)
	986	#define AFE_CONN49_1 (0x33d8)
	987	#define AFE_CONN49_2 (0x33dc)
	988	#define AFE_CONN49_3 (0x33e0)
	989	#define AFE_CONN49_4 (0x33e4)
	990	#define AFE_CONN50 (0x33e8)
	991	#define AFE_CONN50_1 (0x33ec)
	992	#define AFE_CONN50_2 (0x33f0)
	993	#define AFE_CONN50_3 (0x33f4)
	994	#define AFE_CONN50_4 (0x33f8)
	995	#define AFE_CONN51 (0x33fc)
	996	#define AFE_CONN51_1 (0x3400)
	997	#define AFE_CONN51_2 (0x3404)
	998	#define AFE_CONN51_3 (0x3408)
	999	#define AFE_CONN51_4 (0x340c)
	1000	#define AFE_CONN52 (0x3410)
	1001	#define AFE_CONN52_1 (0x3414)
	1002	#define AFE_CONN52_2 (0x3418)
	1003	#define AFE_CONN52_3 (0x341c)
	1004	#define AFE_CONN52_4 (0x3420)
	1005	#define AFE_CONN53 (0x3424)
	1006	#define AFE_CONN53_1 (0x3428)
	1007	#define AFE_CONN53_2 (0x342c)
	1008	#define AFE_CONN53_3 (0x3430)
	1009	#define AFE_CONN53_4 (0x3434)
	1010	#define AFE_CONN54 (0x3438)
	1011	#define AFE_CONN54_1 (0x343c)
	1012	#define AFE_CONN54_2 (0x3440)
	1013	#define AFE_CONN54_3 (0x3444)
	1014	#define AFE_CONN54_4 (0x3448)
	1015	#define AFE_CONN55 (0x344c)
	1016	#define AFE_CONN55_1 (0x3450)
	1017	#define AFE_CONN55_2 (0x3454)
	1018	#define AFE_CONN55_3 (0x3458)
	1019	#define AFE_CONN55_4 (0x345c)
	1020	#define AFE_CONN56 (0x3460)
	1021	#define AFE_CONN56_1 (0x3464)
	1022	#define AFE_CONN56_2 (0x3468)
	1023	#define AFE_CONN56_3 (0x346c)
	1024	#define AFE_CONN56_4 (0x3470)
	1025	#define AFE_CONN57 (0x3474)
	1026	#define AFE_CONN57_1 (0x3478)
	1027	#define AFE_CONN57_2 (0x347c)
	1028	#define AFE_CONN57_3 (0x3480)
	1029	#define AFE_CONN57_4 (0x3484)
	1030	#define AFE_CONN58 (0x3488)
	1031	#define AFE_CONN58_1 (0x348c)
	1032	#define AFE_CONN58_2 (0x3490)
	1033	#define AFE_CONN58_3 (0x3494)
	1034	#define AFE_CONN58_4 (0x3498)
	1035	#define AFE_CONN59 (0x349c)
	1036	#define AFE_CONN59_1 (0x34a0)
	1037	#define AFE_CONN59_2 (0x34a4)
	1038	#define AFE_CONN59_3 (0x34a8)
	1039	#define AFE_CONN59_4 (0x34ac)
	1040	#define AFE_CONN60 (0x34b0)
	1041	#define AFE_CONN60_1 (0x34b4)
	1042	#define AFE_CONN60_2 (0x34b8)
	1043	#define AFE_CONN60_3 (0x34bc)
	1044	#define AFE_CONN60_4 (0x34c0)
	1045	#define AFE_CONN61 (0x34c4)
	1046	#define AFE_CONN61_1 (0x34c8)
	1047	#define AFE_CONN61_2 (0x34cc)
	1048	#define AFE_CONN61_3 (0x34d0)
	1049	#define AFE_CONN61_4 (0x34d4)
	1050	#define AFE_CONN62 (0x34d8)
	1051	#define AFE_CONN62_1 (0x34dc)
	1052	#define AFE_CONN62_2 (0x34e0)
	1053	#define AFE_CONN62_3 (0x34e4)
	1054	#define AFE_CONN62_4 (0x34e8)
	1055	#define AFE_CONN63 (0x34ec)
	1056	#define AFE_CONN63_1 (0x34f0)
	1057	#define AFE_CONN63_2 (0x34f4)
	1058	#define AFE_CONN63_3 (0x34f8)
	1059	#define AFE_CONN63_4 (0x34fc)
	1060	#define AFE_CONN64 (0x3500)
	1061	#define AFE_CONN64_1 (0x3504)
	1062	#define AFE_CONN64_2 (0x3508)
	1063	#define AFE_CONN64_3 (0x350c)
	1064	#define AFE_CONN64_4 (0x3510)
	1065	#define AFE_CONN65 (0x3514)
	1066	#define AFE_CONN65_1 (0x3518)
	1067	#define AFE_CONN65_2 (0x351c)
	1068	#define AFE_CONN65_3 (0x3520)
	1069	#define AFE_CONN65_4 (0x3524)
	1070	#define AFE_CONN66 (0x3528)
	1071	#define AFE_CONN66_1 (0x352c)
	1072	#define AFE_CONN66_2 (0x3530)
	1073	#define AFE_CONN66_3 (0x3534)
	1074	#define AFE_CONN66_4 (0x3538)
	1075	#define AFE_CONN67 (0x353c)
	1076	#define AFE_CONN67_1 (0x3540)
	1077	#define AFE_CONN67_2 (0x3544)
	1078	#define AFE_CONN67_3 (0x3548)
	1079	#define AFE_CONN67_4 (0x354c)
	1080	#define AFE_CONN68 (0x3550)
	1081	#define AFE_CONN68_1 (0x3554)
	1082	#define AFE_CONN68_2 (0x3558)
	1083	#define AFE_CONN68_3 (0x355c)
	1084	#define AFE_CONN68_4 (0x3560)
	1085	#define AFE_CONN69 (0x3564)
	1086	#define AFE_CONN69_1 (0x3568)
	1087	#define AFE_CONN69_2 (0x356c)
	1088	#define AFE_CONN69_3 (0x3570)
	1089	#define AFE_CONN69_4 (0x3574)
	1090	#define AFE_CONN70 (0x3578)
	1091	#define AFE_CONN70_1 (0x357c)
	1092	#define AFE_CONN70_2 (0x3580)
	1093	#define AFE_CONN70_3 (0x3584)
	1094	#define AFE_CONN70_4 (0x3588)
	1095	#define AFE_CONN71 (0x358c)
	1096	#define AFE_CONN71_1 (0x3590)
	1097	#define AFE_CONN71_2 (0x3594)
	1098	#define AFE_CONN71_3 (0x3598)
	1099	#define AFE_CONN71_4 (0x359c)
	1100	#define AFE_CONN72 (0x35a0)
	1101	#define AFE_CONN72_1 (0x35a4)
	1102	#define AFE_CONN72_2 (0x35a8)
	1103	#define AFE_CONN72_3 (0x35ac)
	1104	#define AFE_CONN72_4 (0x35b0)
	1105	#define AFE_CONN73 (0x35b4)
	1106	#define AFE_CONN73_1 (0x35b8)
	1107	#define AFE_CONN73_2 (0x35bc)
	1108	#define AFE_CONN73_3 (0x35c0)
	1109	#define AFE_CONN73_4 (0x35c4)
	1110	#define AFE_CONN74 (0x35c8)
	1111	#define AFE_CONN74_1 (0x35cc)
	1112	#define AFE_CONN74_2 (0x35d0)
	1113	#define AFE_CONN74_3 (0x35d4)
	1114	#define AFE_CONN74_4 (0x35d8)
	1115	#define AFE_CONN75 (0x35dc)
	1116	#define AFE_CONN75_1 (0x35e0)
	1117	#define AFE_CONN75_2 (0x35e4)
	1118	#define AFE_CONN75_3 (0x35e8)
	1119	#define AFE_CONN75_4 (0x35ec)
	1120	#define AFE_CONN76 (0x35f0)
	1121	#define AFE_CONN76_1 (0x35f4)
	1122	#define AFE_CONN76_2 (0x35f8)
	1123	#define AFE_CONN76_3 (0x35fc)
	1124	#define AFE_CONN76_4 (0x3600)
	1125	#define AFE_CONN77 (0x3604)
	1126	#define AFE_CONN77_1 (0x3608)
	1127	#define AFE_CONN77_2 (0x360c)
	1128	#define AFE_CONN77_3 (0x3610)
	1129	#define AFE_CONN77_4 (0x3614)
	1130	#define AFE_CONN78 (0x3618)
	1131	#define AFE_CONN78_1 (0x361c)
	1132	#define AFE_CONN78_2 (0x3620)
	1133	#define AFE_CONN78_3 (0x3624)
	1134	#define AFE_CONN78_4 (0x3628)
	1135	#define AFE_CONN79 (0x362c)
	1136	#define AFE_CONN79_1 (0x3630)
	1137	#define AFE_CONN79_2 (0x3634)
	1138	#define AFE_CONN79_3 (0x3638)
	1139	#define AFE_CONN79_4 (0x363c)
	1140	#define AFE_CONN80 (0x3640)
	1141	#define AFE_CONN80_1 (0x3644)
	1142	#define AFE_CONN80_2 (0x3648)
	1143	#define AFE_CONN80_3 (0x364c)
	1144	#define AFE_CONN80_4 (0x3650)
	1145	#define AFE_CONN81 (0x3654)
	1146	#define AFE_CONN81_1 (0x3658)
	1147	#define AFE_CONN81_2 (0x365c)
	1148	#define AFE_CONN81_3 (0x3660)
	1149	#define AFE_CONN81_4 (0x3664)
	1150	#define AFE_CONN82 (0x3668)
	1151	#define AFE_CONN82_1 (0x366c)
	1152	#define AFE_CONN82_2 (0x3670)
	1153	#define AFE_CONN82_3 (0x3674)
	1154	#define AFE_CONN82_4 (0x3678)
	1155	#define AFE_CONN83 (0x367c)
	1156	#define AFE_CONN83_1 (0x3680)
	1157	#define AFE_CONN83_2 (0x3684)
	1158	#define AFE_CONN83_3 (0x3688)
	1159	#define AFE_CONN83_4 (0x368c)
	1160	#define AFE_CONN84 (0x3690)
	1161	#define AFE_CONN84_1 (0x3694)
	1162	#define AFE_CONN84_2 (0x3698)
	1163	#define AFE_CONN84_3 (0x369c)
	1164	#define AFE_CONN84_4 (0x36a0)
	1165	#define AFE_CONN85 (0x36a4)
	1166	#define AFE_CONN85_1 (0x36a8)
	1167	#define AFE_CONN85_2 (0x36ac)
	1168	#define AFE_CONN85_3 (0x36b0)
	1169	#define AFE_CONN85_4 (0x36b4)
	1170	#define AFE_CONN86 (0x36b8)
	1171	#define AFE_CONN86_1 (0x36bc)
	1172	#define AFE_CONN86_2 (0x36c0)
	1173	#define AFE_CONN86_3 (0x36c4)
	1174	#define AFE_CONN86_4 (0x36c8)
	1175	#define AFE_CONN87 (0x36cc)
	1176	#define AFE_CONN87_1 (0x36d0)
	1177	#define AFE_CONN87_2 (0x36d4)
	1178	#define AFE_CONN87_3 (0x36d8)
	1179	#define AFE_CONN87_4 (0x36dc)
	1180	#define AFE_CONN88 (0x36e0)
	1181	#define AFE_CONN88_1 (0x36e4)
	1182	#define AFE_CONN88_2 (0x36e8)
	1183	#define AFE_CONN88_3 (0x36ec)
	1184	#define AFE_CONN88_4 (0x36f0)
	1185	#define AFE_CONN89 (0x36f4)
	1186	#define AFE_CONN89_1 (0x36f8)
	1187	#define AFE_CONN89_2 (0x36fc)
	1188	#define AFE_CONN89_3 (0x3700)
	1189	#define AFE_CONN89_4 (0x3704)
	1190	#define AFE_CONN90 (0x3708)
	1191	#define AFE_CONN90_1 (0x370c)
	1192	#define AFE_CONN90_2 (0x3710)
	1193	#define AFE_CONN90_3 (0x3714)
	1194	#define AFE_CONN90_4 (0x3718)
	1195	#define AFE_CONN91 (0x371c)
	1196	#define AFE_CONN91_1 (0x3720)
	1197	#define AFE_CONN91_2 (0x3724)
	1198	#define AFE_CONN91_3 (0x3728)
	1199	#define AFE_CONN91_4 (0x372c)
	1200	#define AFE_CONN92 (0x3730)
	1201	#define AFE_CONN92_1 (0x3734)
	1202	#define AFE_CONN92_2 (0x3738)
	1203	#define AFE_CONN92_3 (0x373c)
	1204	#define AFE_CONN92_4 (0x3740)
	1205	#define AFE_CONN93 (0x3744)
	1206	#define AFE_CONN93_1 (0x3748)
	1207	#define AFE_CONN93_2 (0x374c)
	1208	#define AFE_CONN93_3 (0x3750)
	1209	#define AFE_CONN93_4 (0x3754)
	1210	#define AFE_CONN94 (0x3758)
	1211	#define AFE_CONN94_1 (0x375c)
	1212	#define AFE_CONN94_2 (0x3760)
	1213	#define AFE_CONN94_3 (0x3764)
	1214	#define AFE_CONN94_4 (0x3768)
	1215	#define AFE_CONN95 (0x376c)
	1216	#define AFE_CONN95_1 (0x3770)
	1217	#define AFE_CONN95_2 (0x3774)
	1218	#define AFE_CONN95_3 (0x3778)
	1219	#define AFE_CONN95_4 (0x377c)
	1220	#define AFE_CONN96 (0x3780)
	1221	#define AFE_CONN96_1 (0x3784)
	1222	#define AFE_CONN96_2 (0x3788)
	1223	#define AFE_CONN96_3 (0x378c)
	1224	#define AFE_CONN96_4 (0x3790)
	1225	#define AFE_CONN97 (0x3794)
	1226	#define AFE_CONN97_1 (0x3798)
	1227	#define AFE_CONN97_2 (0x379c)
	1228	#define AFE_CONN97_3 (0x37a0)
	1229	#define AFE_CONN97_4 (0x37a4)
	1230	#define AFE_CONN98 (0x37a8)
	1231	#define AFE_CONN98_1 (0x37ac)
	1232	#define AFE_CONN98_2 (0x37b0)
	1233	#define AFE_CONN98_3 (0x37b4)
	1234	#define AFE_CONN98_4 (0x37b8)
	1235	#define AFE_CONN99 (0x37bc)
	1236	#define AFE_CONN99_1 (0x37c0)
	1237	#define AFE_CONN99_2 (0x37c4)
	1238	#define AFE_CONN99_3 (0x37c8)
	1239	#define AFE_CONN99_4 (0x37cc)
	1240	#define AFE_CONN100 (0x37d0)
	1241	#define AFE_CONN100_1 (0x37d4)
	1242	#define AFE_CONN100_2 (0x37d8)
	1243	#define AFE_CONN100_3 (0x37dc)
	1244	#define AFE_CONN100_4 (0x37e0)
	1245	#define AFE_CONN101 (0x37e4)
	1246	#define AFE_CONN101_1 (0x37e8)
	1247	#define AFE_CONN101_2 (0x37ec)
	1248	#define AFE_CONN101_3 (0x37f0)
	1249	#define AFE_CONN101_4 (0x37f4)
	1250	#define AFE_CONN102 (0x37f8)
	1251	#define AFE_CONN102_1 (0x37fc)
	1252	#define AFE_CONN102_2 (0x3800)
	1253	#define AFE_CONN102_3 (0x3804)
	1254	#define AFE_CONN102_4 (0x3808)
	1255	#define AFE_CONN103 (0x380c)
	1256	#define AFE_CONN103_1 (0x3810)
	1257	#define AFE_CONN103_2 (0x3814)
	1258	#define AFE_CONN103_3 (0x3818)
	1259	#define AFE_CONN103_4 (0x381c)
	1260	#define AFE_CONN104 (0x3820)
	1261	#define AFE_CONN104_1 (0x3824)
	1262	#define AFE_CONN104_2 (0x3828)
	1263	#define AFE_CONN104_3 (0x382c)
	1264	#define AFE_CONN104_4 (0x3830)
	1265	#define AFE_CONN105 (0x3834)
	1266	#define AFE_CONN105_1 (0x3838)
	1267	#define AFE_CONN105_2 (0x383c)
	1268	#define AFE_CONN105_3 (0x3840)
	1269	#define AFE_CONN105_4 (0x3844)
	1270	#define AFE_CONN106 (0x3848)
	1271	#define AFE_CONN106_1 (0x384c)
	1272	#define AFE_CONN106_2 (0x3850)
	1273	#define AFE_CONN106_3 (0x3854)
	1274	#define AFE_CONN106_4 (0x3858)
	1275	#define AFE_CONN107 (0x385c)
	1276	#define AFE_CONN107_1 (0x3860)
	1277	#define AFE_CONN107_2 (0x3864)
	1278	#define AFE_CONN107_3 (0x3868)
	1279	#define AFE_CONN107_4 (0x386c)
	1280	#define AFE_CONN108 (0x3870)
	1281	#define AFE_CONN108_1 (0x3874)
	1282	#define AFE_CONN108_2 (0x3878)
	1283	#define AFE_CONN108_3 (0x387c)
	1284	#define AFE_CONN108_4 (0x3880)
	1285	#define AFE_CONN109 (0x3884)
	1286	#define AFE_CONN109_1 (0x3888)
	1287	#define AFE_CONN109_2 (0x388c)
	1288	#define AFE_CONN109_3 (0x3890)
	1289	#define AFE_CONN109_4 (0x3894)
	1290	#define AFE_CONN110 (0x3898)
	1291	#define AFE_CONN110_1 (0x389c)
	1292	#define AFE_CONN110_2 (0x38a0)
	1293	#define AFE_CONN110_3 (0x38a4)
	1294	#define AFE_CONN110_4 (0x38a8)
	1295	#define AFE_CONN111 (0x38ac)
	1296	#define AFE_CONN111_1 (0x38b0)
	1297	#define AFE_CONN111_2 (0x38b4)
	1298	#define AFE_CONN111_3 (0x38b8)
	1299	#define AFE_CONN111_4 (0x38bc)
	1300	#define AFE_CONN112 (0x38c0)
	1301	#define AFE_CONN112_1 (0x38c4)
	1302	#define AFE_CONN112_2 (0x38c8)
	1303	#define AFE_CONN112_3 (0x38cc)
	1304	#define AFE_CONN112_4 (0x38d0)
	1305	#define AFE_CONN113 (0x38d4)
	1306	#define AFE_CONN113_1 (0x38d8)
	1307	#define AFE_CONN113_2 (0x38dc)
	1308	#define AFE_CONN113_3 (0x38e0)
	1309	#define AFE_CONN113_4 (0x38e4)
	1310	#define AFE_CONN114 (0x38e8)
	1311	#define AFE_CONN114_1 (0x38ec)
	1312	#define AFE_CONN114_2 (0x38f0)
	1313	#define AFE_CONN114_3 (0x38f4)
	1314	#define AFE_CONN114_4 (0x38f8)
	1315	#define AFE_CONN115 (0x38fc)
	1316	#define AFE_CONN115_1 (0x3900)
	1317	#define AFE_CONN115_2 (0x3904)
	1318	#define AFE_CONN115_3 (0x3908)
	1319	#define AFE_CONN115_4 (0x390c)
	1320	#define AFE_CONN116 (0x3910)
	1321	#define AFE_CONN116_1 (0x3914)
	1322	#define AFE_CONN116_2 (0x3918)
	1323	#define AFE_CONN116_3 (0x391c)
	1324	#define AFE_CONN116_4 (0x3920)
	1325	#define AFE_CONN117 (0x3924)
	1326	#define AFE_CONN117_1 (0x3928)
	1327	#define AFE_CONN117_2 (0x392c)
	1328	#define AFE_CONN117_3 (0x3930)
	1329	#define AFE_CONN117_4 (0x3934)
	1330	#define AFE_CONN118 (0x3938)
	1331	#define AFE_CONN118_1 (0x393c)
	1332	#define AFE_CONN118_2 (0x3940)
	1333	#define AFE_CONN118_3 (0x3944)
	1334	#define AFE_CONN118_4 (0x3948)
	1335	#define AFE_CONN119 (0x394c)
	1336	#define AFE_CONN119_1 (0x3950)
	1337	#define AFE_CONN119_2 (0x3954)
	1338	#define AFE_CONN119_3 (0x3958)
	1339	#define AFE_CONN119_4 (0x395c)
	1340	#define AFE_CONN120 (0x3960)
	1341	#define AFE_CONN120_1 (0x3964)
	1342	#define AFE_CONN120_2 (0x3968)
	1343	#define AFE_CONN120_3 (0x396c)
	1344	#define AFE_CONN120_4 (0x3970)
	1345	#define AFE_CONN121 (0x3974)
	1346	#define AFE_CONN121_1 (0x3978)
	1347	#define AFE_CONN121_2 (0x397c)
	1348	#define AFE_CONN121_3 (0x3980)
	1349	#define AFE_CONN121_4 (0x3984)
	1350	#define AFE_CONN122 (0x3988)
	1351	#define AFE_CONN122_1 (0x398c)
	1352	#define AFE_CONN122_2 (0x3990)
	1353	#define AFE_CONN122_3 (0x3994)
	1354	#define AFE_CONN122_4 (0x3998)
	1355	#define AFE_CONN123 (0x399c)
	1356	#define AFE_CONN123_1 (0x39a0)
	1357	#define AFE_CONN123_2 (0x39a4)
	1358	#define AFE_CONN123_3 (0x39a8)
	1359	#define AFE_CONN123_4 (0x39ac)
	1360	#define AFE_CONN124 (0x39b0)
	1361	#define AFE_CONN124_1 (0x39b4)
	1362	#define AFE_CONN124_2 (0x39b8)
	1363	#define AFE_CONN124_3 (0x39bc)
	1364	#define AFE_CONN124_4 (0x39c0)
	1365	#define AFE_CONN125 (0x39c4)
	1366	#define AFE_CONN125_1 (0x39c8)
	1367	#define AFE_CONN125_2 (0x39cc)
	1368	#define AFE_CONN125_3 (0x39d0)
	1369	#define AFE_CONN125_4 (0x39d4)
	1370	#define AFE_CONN126 (0x39d8)
	1371	#define AFE_CONN126_1 (0x39dc)
	1372	#define AFE_CONN126_2 (0x39e0)
	1373	#define AFE_CONN126_3 (0x39e4)
	1374	#define AFE_CONN126_4 (0x39e8)
	1375	#define AFE_CONN127 (0x39ec)
	1376	#define AFE_CONN127_1 (0x39f0)
	1377	#define AFE_CONN127_2 (0x39f4)
	1378	#define AFE_CONN127_3 (0x39f8)
	1379	#define AFE_CONN127_4 (0x39fc)
	1380	#define AFE_CONN128 (0x3a00)
	1381	#define AFE_CONN128_1 (0x3a04)
	1382	#define AFE_CONN128_2 (0x3a08)
	1383	#define AFE_CONN128_3 (0x3a0c)
	1384	#define AFE_CONN128_4 (0x3a10)
	1385	#define AFE_CONN129 (0x3a14)
	1386	#define AFE_CONN129_1 (0x3a18)
	1387	#define AFE_CONN129_2 (0x3a1c)
	1388	#define AFE_CONN129_3 (0x3a20)
	1389	#define AFE_CONN129_4 (0x3a24)
	1390	#define AFE_CONN130 (0x3a28)
	1391	#define AFE_CONN130_1 (0x3a2c)
	1392	#define AFE_CONN130_2 (0x3a30)
	1393	#define AFE_CONN130_3 (0x3a34)
	1394	#define AFE_CONN130_4 (0x3a38)
	1395	#define AFE_CONN131 (0x3a3c)
	1396	#define AFE_CONN131_1 (0x3a40)
	1397	#define AFE_CONN131_2 (0x3a44)
	1398	#define AFE_CONN131_3 (0x3a48)
	1399	#define AFE_CONN131_4 (0x3a4c)
	1400	#define AFE_CONN132 (0x3a50)
	1401	#define AFE_CONN132_1 (0x3a54)
	1402	#define AFE_CONN132_2 (0x3a58)
	1403	#define AFE_CONN132_3 (0x3a5c)
	1404	#define AFE_CONN132_4 (0x3a60)
	1405	#define AFE_CONN133 (0x3a64)
	1406	#define AFE_CONN133_1 (0x3a68)
	1407	#define AFE_CONN133_2 (0x3a6c)
	1408	#define AFE_CONN133_3 (0x3a70)
	1409	#define AFE_CONN133_4 (0x3a74)
	1410	#define AFE_CONN134 (0x3a78)
	1411	#define AFE_CONN134_1 (0x3a7c)
	1412	#define AFE_CONN134_2 (0x3a80)
	1413	#define AFE_CONN134_3 (0x3a84)
	1414	#define AFE_CONN134_4 (0x3a88)
	1415	#define AFE_CONN135 (0x3a8c)
	1416	#define AFE_CONN135_1 (0x3a90)
	1417	#define AFE_CONN135_2 (0x3a94)
	1418	#define AFE_CONN135_3 (0x3a98)
	1419	#define AFE_CONN135_4 (0x3a9c)
	1420	#define AFE_CONN136 (0x3aa0)
	1421	#define AFE_CONN136_1 (0x3aa4)
	1422	#define AFE_CONN136_2 (0x3aa8)
	1423	#define AFE_CONN136_3 (0x3aac)
	1424	#define AFE_CONN136_4 (0x3ab0)
	1425	#define AFE_CONN137 (0x3ab4)
	1426	#define AFE_CONN137_1 (0x3ab8)
	1427	#define AFE_CONN137_2 (0x3abc)
	1428	#define AFE_CONN137_3 (0x3ac0)
	1429	#define AFE_CONN137_4 (0x3ac4)
	1430	#define AFE_CONN138 (0x3ac8)
	1431	#define AFE_CONN138_1 (0x3acc)
	1432	#define AFE_CONN138_2 (0x3ad0)
	1433	#define AFE_CONN138_3 (0x3ad4)
	1434	#define AFE_CONN138_4 (0x3ad8)
	1435	#define AFE_CONN139 (0x3adc)
	1436	#define AFE_CONN139_1 (0x3ae0)
	1437	#define AFE_CONN139_2 (0x3ae4)
	1438	#define AFE_CONN139_3 (0x3ae8)
	1439	#define AFE_CONN139_4 (0x3aec)
	1440	#define AFE_CONN_RS (0x3af0)
	1441	#define AFE_CONN_RS_1 (0x3af4)
	1442	#define AFE_CONN_RS_2 (0x3af8)
	1443	#define AFE_CONN_RS_3 (0x3afc)
	1444	#define AFE_CONN_RS_4 (0x3b00)
	1445	#define AFE_CONN_16BIT (0x3b04)
	1446	#define AFE_CONN_16BIT_1 (0x3b08)
	1447	#define AFE_CONN_16BIT_2 (0x3b0c)
	1448	#define AFE_CONN_16BIT_3 (0x3b10)
	1449	#define AFE_CONN_16BIT_4 (0x3b14)
	1450	#define AFE_CONN_24BIT (0x3b18)
	1451	#define AFE_CONN_24BIT_1 (0x3b1c)
	1452	#define AFE_CONN_24BIT_2 (0x3b20)
	1453	#define AFE_CONN_24BIT_3 (0x3b24)
	1454	#define AFE_CONN_24BIT_4 (0x3b28)
	1455	#define AFE_CONN_DI (0x3b2c)
	1456	#define AFE_CONN_DI_1 (0x3b30)
	1457	#define AFE_CONN_DI_2 (0x3b34)
	1458	#define AFE_CONN_DI_3 (0x3b38)
	1459	#define AFE_CONN_DI_4 (0x3b3c)
	1460	#define AFE_CONN176 (0x3ea0)
	1461	#define AFE_CONN176_1 (0x3ea4)
	1462	#define AFE_CONN176_2 (0x3ea8)
	1463	#define AFE_CONN176_3 (0x3eac)
	1464	#define AFE_CONN176_4 (0x3eb0)
	1465	#define AFE_CONN176_5 (0x3eb4)
	1466	#define AFE_CONN177 (0x3eb8)
	1467	#define AFE_CONN177_1 (0x3ebc)
	1468	#define AFE_CONN177_2 (0x3ec0)
	1469	#define AFE_CONN177_3 (0x3ec4)
	1470	#define AFE_CONN177_4 (0x3ec8)
	1471	#define AFE_CONN177_5 (0x3ecc)
	1472	#define AFE_CONN182 (0x3f30)
	1473	#define AFE_CONN182_1 (0x3f34)
	1474	#define AFE_CONN182_2 (0x3f38)
	1475	#define AFE_CONN182_3 (0x3f3c)
	1476	#define AFE_CONN182_4 (0x3f40)
	1477	#define AFE_CONN182_5 (0x3f44)
	1478	#define AFE_CONN183 (0x3f48)
	1479	#define AFE_CONN183_1 (0x3f4c)
	1480	#define AFE_CONN183_2 (0x3f50)
	1481	#define AFE_CONN183_3 (0x3f54)
	1482	#define AFE_CONN183_4 (0x3f58)
	1483	#define AFE_CONN183_5 (0x3f5c)
	1484	#define AFE_SECURE_MASK_CONN0 (0x4000)
	1485	#define AFE_SECURE_MASK_CONN0_1 (0x4004)
	1486	#define AFE_SECURE_MASK_CONN0_2 (0x4008)
	1487	#define AFE_SECURE_MASK_CONN0_3 (0x400c)
	1488	#define AFE_SECURE_MASK_CONN0_4 (0x4010)
	1489	#define AFE_SECURE_MASK_CONN1 (0x4014)
	1490	#define AFE_SECURE_MASK_CONN1_1 (0x4018)
	1491	#define AFE_SECURE_MASK_CONN1_2 (0x401c)
	1492	#define AFE_SECURE_MASK_CONN1_3 (0x4020)
	1493	#define AFE_SECURE_MASK_CONN1_4 (0x4024)
	1494	#define AFE_SECURE_MASK_CONN2 (0x4028)
	1495	#define AFE_SECURE_MASK_CONN2_1 (0x402c)
	1496	#define AFE_SECURE_MASK_CONN2_2 (0x4030)
	1497	#define AFE_SECURE_MASK_CONN2_3 (0x4034)
	1498	#define AFE_SECURE_MASK_CONN2_4 (0x4038)
	1499	#define AFE_SECURE_MASK_CONN3 (0x403c)
	1500	#define AFE_SECURE_MASK_CONN3_1 (0x4040)
	1501	#define AFE_SECURE_MASK_CONN3_2 (0x4044)
	1502	#define AFE_SECURE_MASK_CONN3_3 (0x4048)
	1503	#define AFE_SECURE_MASK_CONN3_4 (0x404c)
	1504	#define AFE_SECURE_MASK_CONN4 (0x4050)
	1505	#define AFE_SECURE_MASK_CONN4_1 (0x4054)
	1506	#define AFE_SECURE_MASK_CONN4_2 (0x4058)
	1507	#define AFE_SECURE_MASK_CONN4_3 (0x405c)
	1508	#define AFE_SECURE_MASK_CONN4_4 (0x4060)
	1509	#define AFE_SECURE_MASK_CONN5 (0x4064)
	1510	#define AFE_SECURE_MASK_CONN5_1 (0x4068)
	1511	#define AFE_SECURE_MASK_CONN5_2 (0x406c)
	1512	#define AFE_SECURE_MASK_CONN5_3 (0x4070)
	1513	#define AFE_SECURE_MASK_CONN5_4 (0x4074)
	1514	#define AFE_SECURE_MASK_CONN6 (0x4078)
	1515	#define AFE_SECURE_MASK_CONN6_1 (0x407c)
	1516	#define AFE_SECURE_MASK_CONN6_2 (0x4080)
	1517	#define AFE_SECURE_MASK_CONN6_3 (0x4084)
	1518	#define AFE_SECURE_MASK_CONN6_4 (0x4088)
	1519	#define AFE_SECURE_MASK_CONN7 (0x408c)
	1520	#define AFE_SECURE_MASK_CONN7_1 (0x4090)
	1521	#define AFE_SECURE_MASK_CONN7_2 (0x4094)
	1522	#define AFE_SECURE_MASK_CONN7_3 (0x4098)
	1523	#define AFE_SECURE_MASK_CONN7_4 (0x409c)
	1524	#define AFE_SECURE_MASK_CONN8 (0x40a0)
	1525	#define AFE_SECURE_MASK_CONN8_1 (0x40a4)
	1526	#define AFE_SECURE_MASK_CONN8_2 (0x40a8)
	1527	#define AFE_SECURE_MASK_CONN8_3 (0x40ac)
	1528	#define AFE_SECURE_MASK_CONN8_4 (0x40b0)
	1529	#define AFE_SECURE_MASK_CONN9 (0x40b4)
	1530	#define AFE_SECURE_MASK_CONN9_1 (0x40b8)
	1531	#define AFE_SECURE_MASK_CONN9_2 (0x40bc)
	1532	#define AFE_SECURE_MASK_CONN9_3 (0x40c0)
	1533	#define AFE_SECURE_MASK_CONN9_4 (0x40c4)
	1534	#define AFE_SECURE_MASK_CONN10 (0x40c8)
	1535	#define AFE_SECURE_MASK_CONN10_1 (0x40cc)
	1536	#define AFE_SECURE_MASK_CONN10_2 (0x40d0)
	1537	#define AFE_SECURE_MASK_CONN10_3 (0x40d4)
	1538	#define AFE_SECURE_MASK_CONN10_4 (0x40d8)
	1539	#define AFE_SECURE_MASK_CONN11 (0x40dc)
	1540	#define AFE_SECURE_MASK_CONN11_1 (0x40e0)
	1541	#define AFE_SECURE_MASK_CONN11_2 (0x40e4)
	1542	#define AFE_SECURE_MASK_CONN11_3 (0x40e8)
	1543	#define AFE_SECURE_MASK_CONN11_4 (0x40ec)
	1544	#define AFE_SECURE_MASK_CONN12 (0x40f0)
	1545	#define AFE_SECURE_MASK_CONN12_1 (0x40f4)
	1546	#define AFE_SECURE_MASK_CONN12_2 (0x40f8)
	1547	#define AFE_SECURE_MASK_CONN12_3 (0x40fc)
	1548	#define AFE_SECURE_MASK_CONN12_4 (0x4100)
	1549	#define AFE_SECURE_MASK_CONN13 (0x4104)
	1550	#define AFE_SECURE_MASK_CONN13_1 (0x4108)
	1551	#define AFE_SECURE_MASK_CONN13_2 (0x410c)
	1552	#define AFE_SECURE_MASK_CONN13_3 (0x4110)
	1553	#define AFE_SECURE_MASK_CONN13_4 (0x4114)
	1554	#define AFE_SECURE_MASK_CONN14 (0x4118)
	1555	#define AFE_SECURE_MASK_CONN14_1 (0x411c)
	1556	#define AFE_SECURE_MASK_CONN14_2 (0x4120)
	1557	#define AFE_SECURE_MASK_CONN14_3 (0x4124)
	1558	#define AFE_SECURE_MASK_CONN14_4 (0x4128)
	1559	#define AFE_SECURE_MASK_CONN15 (0x412c)
	1560	#define AFE_SECURE_MASK_CONN15_1 (0x4130)
	1561	#define AFE_SECURE_MASK_CONN15_2 (0x4134)
	1562	#define AFE_SECURE_MASK_CONN15_3 (0x4138)
	1563	#define AFE_SECURE_MASK_CONN15_4 (0x413c)
	1564	#define AFE_SECURE_MASK_CONN16 (0x4140)
	1565	#define AFE_SECURE_MASK_CONN16_1 (0x4144)
	1566	#define AFE_SECURE_MASK_CONN16_2 (0x4148)
	1567	#define AFE_SECURE_MASK_CONN16_3 (0x414c)
	1568	#define AFE_SECURE_MASK_CONN16_4 (0x4150)
	1569	#define AFE_SECURE_MASK_CONN17 (0x4154)
	1570	#define AFE_SECURE_MASK_CONN17_1 (0x4158)
	1571	#define AFE_SECURE_MASK_CONN17_2 (0x415c)
	1572	#define AFE_SECURE_MASK_CONN17_3 (0x4160)
	1573	#define AFE_SECURE_MASK_CONN17_4 (0x4164)
	1574	#define AFE_SECURE_MASK_CONN18 (0x4168)
	1575	#define AFE_SECURE_MASK_CONN18_1 (0x416c)
	1576	#define AFE_SECURE_MASK_CONN18_2 (0x4170)
	1577	#define AFE_SECURE_MASK_CONN18_3 (0x4174)
	1578	#define AFE_SECURE_MASK_CONN18_4 (0x4178)
	1579	#define AFE_SECURE_MASK_CONN19 (0x417c)
	1580	#define AFE_SECURE_MASK_CONN19_1 (0x4180)
	1581	#define AFE_SECURE_MASK_CONN19_2 (0x4184)
	1582	#define AFE_SECURE_MASK_CONN19_3 (0x4188)
	1583	#define AFE_SECURE_MASK_CONN19_4 (0x418c)
	1584	#define AFE_SECURE_MASK_CONN20 (0x4190)
	1585	#define AFE_SECURE_MASK_CONN20_1 (0x4194)
	1586	#define AFE_SECURE_MASK_CONN20_2 (0x4198)
	1587	#define AFE_SECURE_MASK_CONN20_3 (0x419c)
	1588	#define AFE_SECURE_MASK_CONN20_4 (0x41a0)
	1589	#define AFE_SECURE_MASK_CONN21 (0x41a4)
	1590	#define AFE_SECURE_MASK_CONN21_1 (0x41a8)
	1591	#define AFE_SECURE_MASK_CONN21_2 (0x41ac)
	1592	#define AFE_SECURE_MASK_CONN21_3 (0x41b0)
	1593	#define AFE_SECURE_MASK_CONN21_4 (0x41b4)
	1594	#define AFE_SECURE_MASK_CONN22 (0x41b8)
	1595	#define AFE_SECURE_MASK_CONN22_1 (0x41bc)
	1596	#define AFE_SECURE_MASK_CONN22_2 (0x41c0)
	1597	#define AFE_SECURE_MASK_CONN22_3 (0x41c4)
	1598	#define AFE_SECURE_MASK_CONN22_4 (0x41c8)
	1599	#define AFE_SECURE_MASK_CONN23 (0x41cc)
	1600	#define AFE_SECURE_MASK_CONN23_1 (0x41d0)
	1601	#define AFE_SECURE_MASK_CONN23_2 (0x41d4)
	1602	#define AFE_SECURE_MASK_CONN23_3 (0x41d8)
	1603	#define AFE_SECURE_MASK_CONN23_4 (0x41dc)
	1604	#define AFE_SECURE_MASK_CONN24 (0x41e0)
	1605	#define AFE_SECURE_MASK_CONN24_1 (0x41e4)
	1606	#define AFE_SECURE_MASK_CONN24_2 (0x41e8)
	1607	#define AFE_SECURE_MASK_CONN24_3 (0x41ec)
	1608	#define AFE_SECURE_MASK_CONN24_4 (0x41f0)
	1609	#define AFE_SECURE_MASK_CONN25 (0x41f4)
	1610	#define AFE_SECURE_MASK_CONN25_1 (0x41f8)
	1611	#define AFE_SECURE_MASK_CONN25_2 (0x41fc)
	1612	#define AFE_SECURE_MASK_CONN25_3 (0x4200)
	1613	#define AFE_SECURE_MASK_CONN25_4 (0x4204)
	1614	#define AFE_SECURE_MASK_CONN26 (0x4208)
	1615	#define AFE_SECURE_MASK_CONN26_1 (0x420c)
	1616	#define AFE_SECURE_MASK_CONN26_2 (0x4210)
	1617	#define AFE_SECURE_MASK_CONN26_3 (0x4214)
	1618	#define AFE_SECURE_MASK_CONN26_4 (0x4218)
	1619	#define AFE_SECURE_MASK_CONN27 (0x421c)
	1620	#define AFE_SECURE_MASK_CONN27_1 (0x4220)
	1621	#define AFE_SECURE_MASK_CONN27_2 (0x4224)
	1622	#define AFE_SECURE_MASK_CONN27_3 (0x4228)
	1623	#define AFE_SECURE_MASK_CONN27_4 (0x422c)
	1624	#define AFE_SECURE_MASK_CONN28 (0x4230)
	1625	#define AFE_SECURE_MASK_CONN28_1 (0x4234)
	1626	#define AFE_SECURE_MASK_CONN28_2 (0x4238)
	1627	#define AFE_SECURE_MASK_CONN28_3 (0x423c)
	1628	#define AFE_SECURE_MASK_CONN28_4 (0x4240)
	1629	#define AFE_SECURE_MASK_CONN29 (0x4244)
	1630	#define AFE_SECURE_MASK_CONN29_1 (0x4248)
	1631	#define AFE_SECURE_MASK_CONN29_2 (0x424c)
	1632	#define AFE_SECURE_MASK_CONN29_3 (0x4250)
	1633	#define AFE_SECURE_MASK_CONN29_4 (0x4254)
	1634	#define AFE_SECURE_MASK_CONN30 (0x4258)
	1635	#define AFE_SECURE_MASK_CONN30_1 (0x425c)
	1636	#define AFE_SECURE_MASK_CONN30_2 (0x4260)
	1637	#define AFE_SECURE_MASK_CONN30_3 (0x4264)
	1638	#define AFE_SECURE_MASK_CONN30_4 (0x4268)
	1639	#define AFE_SECURE_MASK_CONN31 (0x426c)
	1640	#define AFE_SECURE_MASK_CONN31_1 (0x4270)
	1641	#define AFE_SECURE_MASK_CONN31_2 (0x4274)
	1642	#define AFE_SECURE_MASK_CONN31_3 (0x4278)
	1643	#define AFE_SECURE_MASK_CONN31_4 (0x427c)
	1644	#define AFE_SECURE_MASK_CONN32 (0x4280)
	1645	#define AFE_SECURE_MASK_CONN32_1 (0x4284)
	1646	#define AFE_SECURE_MASK_CONN32_2 (0x4288)
	1647	#define AFE_SECURE_MASK_CONN32_3 (0x428c)
	1648	#define AFE_SECURE_MASK_CONN32_4 (0x4290)
	1649	#define AFE_SECURE_MASK_CONN33 (0x4294)
	1650	#define AFE_SECURE_MASK_CONN33_1 (0x4298)
	1651	#define AFE_SECURE_MASK_CONN33_2 (0x429c)
	1652	#define AFE_SECURE_MASK_CONN33_3 (0x42a0)
	1653	#define AFE_SECURE_MASK_CONN33_4 (0x42a4)
	1654	#define AFE_SECURE_MASK_CONN34 (0x42a8)
	1655	#define AFE_SECURE_MASK_CONN34_1 (0x42ac)
	1656	#define AFE_SECURE_MASK_CONN34_2 (0x42b0)
	1657	#define AFE_SECURE_MASK_CONN34_3 (0x42b4)
	1658	#define AFE_SECURE_MASK_CONN34_4 (0x42b8)
	1659	#define AFE_SECURE_MASK_CONN35 (0x42bc)
	1660	#define AFE_SECURE_MASK_CONN35_1 (0x42c0)
	1661	#define AFE_SECURE_MASK_CONN35_2 (0x42c4)
	1662	#define AFE_SECURE_MASK_CONN35_3 (0x42c8)
	1663	#define AFE_SECURE_MASK_CONN35_4 (0x42cc)
	1664	#define AFE_SECURE_MASK_CONN36 (0x42d0)
	1665	#define AFE_SECURE_MASK_CONN36_1 (0x42d4)
	1666	#define AFE_SECURE_MASK_CONN36_2 (0x42d8)
	1667	#define AFE_SECURE_MASK_CONN36_3 (0x42dc)
	1668	#define AFE_SECURE_MASK_CONN36_4 (0x42e0)
	1669	#define AFE_SECURE_MASK_CONN37 (0x42e4)
	1670	#define AFE_SECURE_MASK_CONN37_1 (0x42e8)
	1671	#define AFE_SECURE_MASK_CONN37_2 (0x42ec)
	1672	#define AFE_SECURE_MASK_CONN37_3 (0x42f0)
	1673	#define AFE_SECURE_MASK_CONN37_4 (0x42f4)
	1674	#define AFE_SECURE_MASK_CONN38 (0x42f8)
	1675	#define AFE_SECURE_MASK_CONN38_1 (0x42fc)
	1676	#define AFE_SECURE_MASK_CONN38_2 (0x4300)
	1677	#define AFE_SECURE_MASK_CONN38_3 (0x4304)
	1678	#define AFE_SECURE_MASK_CONN38_4 (0x4308)
	1679	#define AFE_SECURE_MASK_CONN39 (0x430c)
	1680	#define AFE_SECURE_MASK_CONN39_1 (0x4310)
	1681	#define AFE_SECURE_MASK_CONN39_2 (0x4314)
	1682	#define AFE_SECURE_MASK_CONN39_3 (0x4318)
	1683	#define AFE_SECURE_MASK_CONN39_4 (0x431c)
	1684	#define AFE_SECURE_MASK_CONN40 (0x4320)
	1685	#define AFE_SECURE_MASK_CONN40_1 (0x4324)
	1686	#define AFE_SECURE_MASK_CONN40_2 (0x4328)
	1687	#define AFE_SECURE_MASK_CONN40_3 (0x432c)
	1688	#define AFE_SECURE_MASK_CONN40_4 (0x4330)
	1689	#define AFE_SECURE_MASK_CONN41 (0x4334)
	1690	#define AFE_SECURE_MASK_CONN41_1 (0x4338)
	1691	#define AFE_SECURE_MASK_CONN41_2 (0x433c)
	1692	#define AFE_SECURE_MASK_CONN41_3 (0x4340)
	1693	#define AFE_SECURE_MASK_CONN41_4 (0x4344)
	1694	#define AFE_SECURE_MASK_CONN42 (0x4348)
	1695	#define AFE_SECURE_MASK_CONN42_1 (0x434c)
	1696	#define AFE_SECURE_MASK_CONN42_2 (0x4350)
	1697	#define AFE_SECURE_MASK_CONN42_3 (0x4354)
	1698	#define AFE_SECURE_MASK_CONN42_4 (0x4358)
	1699	#define AFE_SECURE_MASK_CONN43 (0x435c)
	1700	#define AFE_SECURE_MASK_CONN43_1 (0x4360)
	1701	#define AFE_SECURE_MASK_CONN43_2 (0x4364)
	1702	#define AFE_SECURE_MASK_CONN43_3 (0x4368)
	1703	#define AFE_SECURE_MASK_CONN43_4 (0x436c)
	1704	#define AFE_SECURE_MASK_CONN44 (0x4370)
	1705	#define AFE_SECURE_MASK_CONN44_1 (0x4374)
	1706	#define AFE_SECURE_MASK_CONN44_2 (0x4378)
	1707	#define AFE_SECURE_MASK_CONN44_3 (0x437c)
	1708	#define AFE_SECURE_MASK_CONN44_4 (0x4380)
	1709	#define AFE_SECURE_MASK_CONN45 (0x4384)
	1710	#define AFE_SECURE_MASK_CONN45_1 (0x4388)
	1711	#define AFE_SECURE_MASK_CONN45_2 (0x438c)
	1712	#define AFE_SECURE_MASK_CONN45_3 (0x4390)
	1713	#define AFE_SECURE_MASK_CONN45_4 (0x4394)
	1714	#define AFE_SECURE_MASK_CONN46 (0x4398)
	1715	#define AFE_SECURE_MASK_CONN46_1 (0x439c)
	1716	#define AFE_SECURE_MASK_CONN46_2 (0x43a0)
	1717	#define AFE_SECURE_MASK_CONN46_3 (0x43a4)
	1718	#define AFE_SECURE_MASK_CONN46_4 (0x43a8)
	1719	#define AFE_SECURE_MASK_CONN47 (0x43ac)
	1720	#define AFE_SECURE_MASK_CONN47_1 (0x43b0)
	1721	#define AFE_SECURE_MASK_CONN47_2 (0x43b4)
	1722	#define AFE_SECURE_MASK_CONN47_3 (0x43b8)
	1723	#define AFE_SECURE_MASK_CONN47_4 (0x43bc)
	1724	#define AFE_SECURE_MASK_CONN48 (0x43c0)
	1725	#define AFE_SECURE_MASK_CONN48_1 (0x43c4)
	1726	#define AFE_SECURE_MASK_CONN48_2 (0x43c8)
	1727	#define AFE_SECURE_MASK_CONN48_3 (0x43cc)
	1728	#define AFE_SECURE_MASK_CONN48_4 (0x43d0)
	1729	#define AFE_SECURE_MASK_CONN49 (0x43d4)
	1730	#define AFE_SECURE_MASK_CONN49_1 (0x43d8)
	1731	#define AFE_SECURE_MASK_CONN49_2 (0x43dc)
	1732	#define AFE_SECURE_MASK_CONN49_3 (0x43e0)
	1733	#define AFE_SECURE_MASK_CONN49_4 (0x43e4)
	1734	#define AFE_SECURE_MASK_CONN50 (0x43e8)
	1735	#define AFE_SECURE_MASK_CONN50_1 (0x43ec)
	1736	#define AFE_SECURE_MASK_CONN50_2 (0x43f0)
	1737	#define AFE_SECURE_MASK_CONN50_3 (0x43f4)
	1738	#define AFE_SECURE_MASK_CONN50_4 (0x43f8)
	1739	#define AFE_SECURE_MASK_CONN51 (0x43fc)
	1740	#define AFE_SECURE_MASK_CONN51_1 (0x4400)
	1741	#define AFE_SECURE_MASK_CONN51_2 (0x4404)
	1742	#define AFE_SECURE_MASK_CONN51_3 (0x4408)
	1743	#define AFE_SECURE_MASK_CONN51_4 (0x440c)
	1744	#define AFE_SECURE_MASK_CONN52 (0x4410)
	1745	#define AFE_SECURE_MASK_CONN52_1 (0x4414)
	1746	#define AFE_SECURE_MASK_CONN52_2 (0x4418)
	1747	#define AFE_SECURE_MASK_CONN52_3 (0x441c)
	1748	#define AFE_SECURE_MASK_CONN52_4 (0x4420)
	1749	#define AFE_SECURE_MASK_CONN53 (0x4424)
	1750	#define AFE_SECURE_MASK_CONN53_1 (0x4428)
	1751	#define AFE_SECURE_MASK_CONN53_2 (0x442c)
	1752	#define AFE_SECURE_MASK_CONN53_3 (0x4430)
	1753	#define AFE_SECURE_MASK_CONN53_4 (0x4434)
	1754	#define AFE_SECURE_MASK_CONN54 (0x4438)
	1755	#define AFE_SECURE_MASK_CONN54_1 (0x443c)
	1756	#define AFE_SECURE_MASK_CONN54_2 (0x4440)
	1757	#define AFE_SECURE_MASK_CONN54_3 (0x4444)
	1758	#define AFE_SECURE_MASK_CONN54_4 (0x4448)
	1759	#define AFE_SECURE_MASK_CONN55 (0x444c)
	1760	#define AFE_SECURE_MASK_CONN55_1 (0x4450)
	1761	#define AFE_SECURE_MASK_CONN55_2 (0x4454)
	1762	#define AFE_SECURE_MASK_CONN55_3 (0x4458)
	1763	#define AFE_SECURE_MASK_CONN55_4 (0x445c)
	1764	#define AFE_SECURE_MASK_CONN56 (0x4460)
	1765	#define AFE_SECURE_MASK_CONN56_1 (0x4464)
	1766	#define AFE_SECURE_MASK_CONN56_2 (0x4468)
	1767	#define AFE_SECURE_MASK_CONN56_3 (0x446c)
	1768	#define AFE_SECURE_MASK_CONN56_4 (0x4470)
	1769	#define AFE_SECURE_MASK_CONN57 (0x4474)
	1770	#define AFE_SECURE_MASK_CONN57_1 (0x4478)
	1771	#define AFE_SECURE_MASK_CONN57_2 (0x447c)
	1772	#define AFE_SECURE_MASK_CONN57_3 (0x4480)
	1773	#define AFE_SECURE_MASK_CONN57_4 (0x4484)
	1774	#define AFE_SECURE_MASK_CONN58 (0x4488)
	1775	#define AFE_SECURE_MASK_CONN58_1 (0x448c)
	1776	#define AFE_SECURE_MASK_CONN58_2 (0x4490)
	1777	#define AFE_SECURE_MASK_CONN58_3 (0x4494)
	1778	#define AFE_SECURE_MASK_CONN58_4 (0x4498)
	1779	#define AFE_SECURE_MASK_CONN59 (0x449c)
	1780	#define AFE_SECURE_MASK_CONN59_1 (0x44a0)
	1781	#define AFE_SECURE_MASK_CONN59_2 (0x44a4)
	1782	#define AFE_SECURE_MASK_CONN59_3 (0x44a8)
	1783	#define AFE_SECURE_MASK_CONN59_4 (0x44ac)
	1784	#define AFE_SECURE_MASK_CONN60 (0x44b0)
	1785	#define AFE_SECURE_MASK_CONN60_1 (0x44b4)
	1786	#define AFE_SECURE_MASK_CONN60_2 (0x44b8)
	1787	#define AFE_SECURE_MASK_CONN60_3 (0x44bc)
	1788	#define AFE_SECURE_MASK_CONN60_4 (0x44c0)
	1789	#define AFE_SECURE_MASK_CONN61 (0x44c4)
	1790	#define AFE_SECURE_MASK_CONN61_1 (0x44c8)
	1791	#define AFE_SECURE_MASK_CONN61_2 (0x44cc)
	1792	#define AFE_SECURE_MASK_CONN61_3 (0x44d0)
	1793	#define AFE_SECURE_MASK_CONN61_4 (0x44d4)
	1794	#define AFE_SECURE_MASK_CONN62 (0x44d8)
	1795	#define AFE_SECURE_MASK_CONN62_1 (0x44dc)
	1796	#define AFE_SECURE_MASK_CONN62_2 (0x44e0)
	1797	#define AFE_SECURE_MASK_CONN62_3 (0x44e4)
	1798	#define AFE_SECURE_MASK_CONN62_4 (0x44e8)
	1799	#define AFE_SECURE_MASK_CONN63 (0x44ec)
	1800	#define AFE_SECURE_MASK_CONN63_1 (0x44f0)
	1801	#define AFE_SECURE_MASK_CONN63_2 (0x44f4)
	1802	#define AFE_SECURE_MASK_CONN63_3 (0x44f8)
	1803	#define AFE_SECURE_MASK_CONN63_4 (0x44fc)
	1804	#define AFE_SECURE_MASK_CONN64 (0x4500)
	1805	#define AFE_SECURE_MASK_CONN64_1 (0x4504)
	1806	#define AFE_SECURE_MASK_CONN64_2 (0x4508)
	1807	#define AFE_SECURE_MASK_CONN64_3 (0x450c)
	1808	#define AFE_SECURE_MASK_CONN64_4 (0x4510)
	1809	#define AFE_SECURE_MASK_CONN65 (0x4514)
	1810	#define AFE_SECURE_MASK_CONN65_1 (0x4518)
	1811	#define AFE_SECURE_MASK_CONN65_2 (0x451c)
	1812	#define AFE_SECURE_MASK_CONN65_3 (0x4520)
	1813	#define AFE_SECURE_MASK_CONN65_4 (0x4524)
	1814	#define AFE_SECURE_MASK_CONN66 (0x4528)
	1815	#define AFE_SECURE_MASK_CONN66_1 (0x452c)
	1816	#define AFE_SECURE_MASK_CONN66_2 (0x4530)
	1817	#define AFE_SECURE_MASK_CONN66_3 (0x4534)
	1818	#define AFE_SECURE_MASK_CONN66_4 (0x4538)
	1819	#define AFE_SECURE_MASK_CONN67 (0x453c)
	1820	#define AFE_SECURE_MASK_CONN67_1 (0x4540)
	1821	#define AFE_SECURE_MASK_CONN67_2 (0x4544)
	1822	#define AFE_SECURE_MASK_CONN67_3 (0x4548)
	1823	#define AFE_SECURE_MASK_CONN67_4 (0x454c)
	1824	#define AFE_SECURE_MASK_CONN68 (0x4550)
	1825	#define AFE_SECURE_MASK_CONN68_1 (0x4554)
	1826	#define AFE_SECURE_MASK_CONN68_2 (0x4558)
	1827	#define AFE_SECURE_MASK_CONN68_3 (0x455c)
	1828	#define AFE_SECURE_MASK_CONN68_4 (0x4560)
	1829	#define AFE_SECURE_MASK_CONN69 (0x4564)
	1830	#define AFE_SECURE_MASK_CONN69_1 (0x4568)
	1831	#define AFE_SECURE_MASK_CONN69_2 (0x456c)
	1832	#define AFE_SECURE_MASK_CONN69_3 (0x4570)
	1833	#define AFE_SECURE_MASK_CONN69_4 (0x4574)
	1834	#define AFE_SECURE_MASK_CONN70 (0x4578)
	1835	#define AFE_SECURE_MASK_CONN70_1 (0x457c)
	1836	#define AFE_SECURE_MASK_CONN70_2 (0x4580)
	1837	#define AFE_SECURE_MASK_CONN70_3 (0x4584)
	1838	#define AFE_SECURE_MASK_CONN70_4 (0x4588)
	1839	#define AFE_SECURE_MASK_CONN71 (0x458c)

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