History

Merge tag 'pinctrl-v4.4-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij: - Driver fixes for Freescale i.MX7D, Intel, Broadcom 2835 - One MAINTAINERS entry * tag 'pinctrl-v4.4-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: MAINTAINERS: pinctrl: Add maintainers for pinctrl-single pinctrl: bcm2835: Fix initial value for direction_output pinctrl: intel: fix offset calculation issue of register PAD_OWN pinctrl: intel: fix bug of register offset calculation pinctrl: freescale: add ZERO_OFFSET_VALID flag for vf610 pinctrl

Linus Torvalds committed 10 years ago

Commit 38beb962 parents d7d3d84 13cbd907 files · +41 −28Browse files

Unified · Split

7 files
  1. MAINTAINERS +8 −0
  2. drivers/pinctrl/bcm/pinctrl-bcm2835.c +7 −6
  3. drivers/pinctrl/freescale/pinctrl-vf610.c +1 −1
  4. drivers/pinctrl/intel/pinctrl-broxton.c +1 −0
  5. drivers/pinctrl/intel/pinctrl-intel.c +20 −21
  6. drivers/pinctrl/intel/pinctrl-intel.h +3 −0
  7. drivers/pinctrl/intel/pinctrl-sunrisepoint.c +1 −0
MAINTAINERS+8−0
@@ -8380,6 +8380,14 @@ L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers) · 8379 unmodified lines
8380S: Maintained8380S: Maintained
8381F: drivers/pinctrl/samsung/8381F: drivers/pinctrl/samsung/
8382 8382
8383PIN CONTROLLER - SINGLE
8384M: Tony Lindgren <tony@atomide.com>
8385M: Haojian Zhuang <haojian.zhuang@linaro.org>
8386L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
8387L: linux-omap@vger.kernel.org
8388S: Maintained
8389F: drivers/pinctrl/pinctrl-single.c
8390
8383PIN CONTROLLER - ST SPEAR8391PIN CONTROLLER - ST SPEAR
8384M: Viresh Kumar <vireshk@kernel.org>8392M: Viresh Kumar <vireshk@kernel.org>
8385L: spear-devel@list.st.com8393L: spear-devel@list.st.com
drivers/pinctrl/bcm/pinctrl-bcm2835.c+7−6
@@ -342,12 +342,6 @@ static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset) · 341 unmodified lines
342 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);342 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
343}343}
344 344
345static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
346 unsigned offset, int value)
347{
348 return pinctrl_gpio_direction_output(chip->base + offset);
349}
350
351static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)345static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
352{346{
353 struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);347 struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
@@ -355,6 +349,13 @@ static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value) · 1 unmodified line
355 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);349 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
356}350}
357 351
352static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
353 unsigned offset, int value)
354{
355 bcm2835_gpio_set(chip, offset, value);
356 return pinctrl_gpio_direction_output(chip->base + offset);
357}
358
358static int bcm2835_gpio_to_irq(struct gpio_chip *chip, unsigned offset)359static int bcm2835_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
359{360{
360 struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);361 struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
drivers/pinctrl/freescale/pinctrl-vf610.c+1−1
@@ -299,7 +299,7 @@ static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = { · 298 unmodified lines
299static struct imx_pinctrl_soc_info vf610_pinctrl_info = {299static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
300 .pins = vf610_pinctrl_pads,300 .pins = vf610_pinctrl_pads,
301 .npins = ARRAY_SIZE(vf610_pinctrl_pads),301 .npins = ARRAY_SIZE(vf610_pinctrl_pads),
302 .flags = SHARE_MUX_CONF_REG,302 .flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
303};303};
304 304
305static const struct of_device_id vf610_pinctrl_of_match[] = {305static const struct of_device_id vf610_pinctrl_of_match[] = {
drivers/pinctrl/intel/pinctrl-broxton.c+1−0
@@ -28,6 +28,7 @@ · 27 unmodified lines
28 .padcfglock_offset = BXT_PADCFGLOCK, \28 .padcfglock_offset = BXT_PADCFGLOCK, \
29 .hostown_offset = BXT_HOSTSW_OWN, \29 .hostown_offset = BXT_HOSTSW_OWN, \
30 .ie_offset = BXT_GPI_IE, \30 .ie_offset = BXT_GPI_IE, \
31 .gpp_size = 32, \
31 .pin_base = (s), \32 .pin_base = (s), \
32 .npins = ((e) - (s) + 1), \33 .npins = ((e) - (s) + 1), \
33 }34 }
drivers/pinctrl/intel/pinctrl-intel.c+20−21
@@ -25,9 +25,6 @@ · 24 unmodified lines
25 25
26#include "pinctrl-intel.h"26#include "pinctrl-intel.h"
27 27
28/* Maximum number of pads in each group */
29#define NPADS_IN_GPP 24
30
31/* Offset from regs */28/* Offset from regs */
32#define PADBAR 0x00c29#define PADBAR 0x00c
33#define GPI_IS 0x10030#define GPI_IS 0x100
@@ -37,6 +34,7 @@ · 3 unmodified lines
37#define PADOWN_BITS 434#define PADOWN_BITS 4
38#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)35#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
39#define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))36#define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
37#define PADOWN_GPP(p) ((p) / 8)
40 38
41/* Offset from pad_regs */39/* Offset from pad_regs */
42#define PADCFG0 0x00040#define PADCFG0 0x000
@@ -142,7 +140,7 @@ static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin, · 99 unmodified lines
142static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)140static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
143{141{
144 const struct intel_community *community;142 const struct intel_community *community;
145 unsigned padno, gpp, gpp_offset, offset;143 unsigned padno, gpp, offset, group;
146 void __iomem *padown;144 void __iomem *padown;
147 145
148 community = intel_get_community(pctrl, pin);146 community = intel_get_community(pctrl, pin);
@@ -152,9 +150,9 @@ static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin) · 3 unmodified lines
152 return true;150 return true;
153 151
154 padno = pin_to_padno(community, pin);152 padno = pin_to_padno(community, pin);
155 gpp = padno / NPADS_IN_GPP;153 group = padno / community->gpp_size;
156 gpp_offset = padno % NPADS_IN_GPP;154 gpp = PADOWN_GPP(padno % community->gpp_size);
157 offset = community->padown_offset + gpp * 16 + (gpp_offset / 8) * 4;155 offset = community->padown_offset + 0x10 * group + gpp * 4;
158 padown = community->regs + offset;156 padown = community->regs + offset;
159 157
160 return !(readl(padown) & PADOWN_MASK(padno));158 return !(readl(padown) & PADOWN_MASK(padno));
@@ -173,11 +171,11 @@ static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin) · 12 unmodified lines
173 return false;171 return false;
174 172
175 padno = pin_to_padno(community, pin);173 padno = pin_to_padno(community, pin);
176 gpp = padno / NPADS_IN_GPP;174 gpp = padno / community->gpp_size;
177 offset = community->hostown_offset + gpp * 4;175 offset = community->hostown_offset + gpp * 4;
178 hostown = community->regs + offset;176 hostown = community->regs + offset;
179 177
180 return !(readl(hostown) & BIT(padno % NPADS_IN_GPP));178 return !(readl(hostown) & BIT(padno % community->gpp_size));
181}179}
182 180
183static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)181static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
@@ -193,7 +191,7 @@ static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) · 9 unmodified lines
193 return false;191 return false;
194 192
195 padno = pin_to_padno(community, pin);193 padno = pin_to_padno(community, pin);
196 gpp = padno / NPADS_IN_GPP;194 gpp = padno / community->gpp_size;
197 195
198 /*196 /*
199 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,197 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
@@ -202,12 +200,12 @@ static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) · 2 unmodified lines
202 */200 */
203 offset = community->padcfglock_offset + gpp * 8;201 offset = community->padcfglock_offset + gpp * 8;
204 value = readl(community->regs + offset);202 value = readl(community->regs + offset);
205 if (value & BIT(pin % NPADS_IN_GPP))203 if (value & BIT(pin % community->gpp_size))
206 return true;204 return true;
207 205
208 offset = community->padcfglock_offset + 4 + gpp * 8;206 offset = community->padcfglock_offset + 4 + gpp * 8;
209 value = readl(community->regs + offset);207 value = readl(community->regs + offset);
210 if (value & BIT(pin % NPADS_IN_GPP))208 if (value & BIT(pin % community->gpp_size))
211 return true;209 return true;
212 210
213 return false;211 return false;
@@ -663,8 +661,8 @@ static void intel_gpio_irq_ack(struct irq_data *d) · 449 unmodified lines
663 community = intel_get_community(pctrl, pin);661 community = intel_get_community(pctrl, pin);
664 if (community) {662 if (community) {
665 unsigned padno = pin_to_padno(community, pin);663 unsigned padno = pin_to_padno(community, pin);
666 unsigned gpp_offset = padno % NPADS_IN_GPP;664 unsigned gpp_offset = padno % community->gpp_size;
667 unsigned gpp = padno / NPADS_IN_GPP;665 unsigned gpp = padno / community->gpp_size;
668 666
669 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);667 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
670 }668 }
@@ -685,8 +683,8 @@ static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) · 14 unmodified lines
685 community = intel_get_community(pctrl, pin);683 community = intel_get_community(pctrl, pin);
686 if (community) {684 if (community) {
687 unsigned padno = pin_to_padno(community, pin);685 unsigned padno = pin_to_padno(community, pin);
688 unsigned gpp_offset = padno % NPADS_IN_GPP;686 unsigned gpp_offset = padno % community->gpp_size;
689 unsigned gpp = padno / NPADS_IN_GPP;687 unsigned gpp = padno / community->gpp_size;
690 void __iomem *reg;688 void __iomem *reg;
691 u32 value;689 u32 value;
692 690
@@ -780,8 +778,8 @@ static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) · 87 unmodified lines
780 return -EINVAL;778 return -EINVAL;
781 779
782 padno = pin_to_padno(community, pin);780 padno = pin_to_padno(community, pin);
783 gpp = padno / NPADS_IN_GPP;781 gpp = padno / community->gpp_size;
784 gpp_offset = padno % NPADS_IN_GPP;782 gpp_offset = padno % community->gpp_size;
785 783
786 /* Clear the existing wake status */784 /* Clear the existing wake status */
787 writel(BIT(gpp_offset), community->regs + GPI_GPE_STS + gpp * 4);785 writel(BIT(gpp_offset), community->regs + GPI_GPE_STS + gpp * 4);
@@ -819,14 +817,14 @@ static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, · 31 unmodified lines
819 /* Only interrupts that are enabled */817 /* Only interrupts that are enabled */
820 pending &= enabled;818 pending &= enabled;
821 819
822 for_each_set_bit(gpp_offset, &pending, NPADS_IN_GPP) {820 for_each_set_bit(gpp_offset, &pending, community->gpp_size) {
823 unsigned padno, irq;821 unsigned padno, irq;
824 822
825 /*823 /*
826 * The last group in community can have less pins824 * The last group in community can have less pins
827 * than NPADS_IN_GPP.825 * than NPADS_IN_GPP.
828 */826 */
829 padno = gpp_offset + gpp * NPADS_IN_GPP;827 padno = gpp_offset + gpp * community->gpp_size;
830 if (padno >= community->npins)828 if (padno >= community->npins)
831 break;829 break;
832 830
@@ -1002,7 +1000,8 @@ int intel_pinctrl_probe(struct platform_device *pdev, · 169 unmodified lines
1002 1000
1003 community->regs = regs;1001 community->regs = regs;
1004 community->pad_regs = regs + padbar;1002 community->pad_regs = regs + padbar;
1005 community->ngpps = DIV_ROUND_UP(community->npins, NPADS_IN_GPP);1003 community->ngpps = DIV_ROUND_UP(community->npins,
1004 community->gpp_size);
1006 }1005 }
1007 1006
1008 irq = platform_get_irq(pdev, 0);1007 irq = platform_get_irq(pdev, 0);
drivers/pinctrl/intel/pinctrl-intel.h+3−0
@@ -55,6 +55,8 @@ struct intel_function { · 54 unmodified lines
55 * ACPI).55 * ACPI).
56 * @ie_offset: Register offset of GPI_IE from @regs.56 * @ie_offset: Register offset of GPI_IE from @regs.
57 * @pin_base: Starting pin of pins in this community57 * @pin_base: Starting pin of pins in this community
58 * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
59 * HOSTSW_OWN, GPI_IS, GPI_IE, etc.
58 * @npins: Number of pins in this community60 * @npins: Number of pins in this community
59 * @regs: Community specific common registers (reserved for core driver)61 * @regs: Community specific common registers (reserved for core driver)
60 * @pad_regs: Community specific pad registers (reserved for core driver)62 * @pad_regs: Community specific pad registers (reserved for core driver)
@@ -68,6 +70,7 @@ struct intel_community { · 7 unmodified lines
68 unsigned hostown_offset;70 unsigned hostown_offset;
69 unsigned ie_offset;71 unsigned ie_offset;
70 unsigned pin_base;72 unsigned pin_base;
73 unsigned gpp_size;
71 size_t npins;74 size_t npins;
72 void __iomem *regs;75 void __iomem *regs;
73 void __iomem *pad_regs;76 void __iomem *pad_regs;
drivers/pinctrl/intel/pinctrl-sunrisepoint.c+1−0
@@ -30,6 +30,7 @@ · 29 unmodified lines
30 .padcfglock_offset = SPT_PADCFGLOCK, \30 .padcfglock_offset = SPT_PADCFGLOCK, \
31 .hostown_offset = SPT_HOSTSW_OWN, \31 .hostown_offset = SPT_HOSTSW_OWN, \
32 .ie_offset = SPT_GPI_IE, \32 .ie_offset = SPT_GPI_IE, \
33 .gpp_size = 24, \
33 .pin_base = (s), \34 .pin_base = (s), \
34 .npins = ((e) - (s) + 1), \35 .npins = ((e) - (s) + 1), \
35 }36 }