The patch adds API for configuring the NVM config attributes using Management FW (MFW) interfaces.
Unified · Split
| @@ -12580,6 +12580,8 @@ struct public_drv_mb { · 12579 unmodified lines | |||
| 12580 | #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000 | 12580 | #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000 |
| 12581 | #define DRV_MSG_CODE_NIG_DRAIN 0x30000000 | 12581 | #define DRV_MSG_CODE_NIG_DRAIN 0x30000000 |
| 12582 | #define DRV_MSG_CODE_S_TAG_UPDATE_ACK 0x3b000000 | 12582 | #define DRV_MSG_CODE_S_TAG_UPDATE_ACK 0x3b000000 |
| 12583 | #define DRV_MSG_CODE_GET_NVM_CFG_OPTION 0x003e0000 | ||
| 12584 | #define DRV_MSG_CODE_SET_NVM_CFG_OPTION 0x003f0000 | ||
| 12583 | #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000 | 12585 | #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000 |
| 12584 | #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 | 12586 | #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 |
| 12585 | #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000 | 12587 | #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000 |
| @@ -12748,6 +12750,21 @@ struct public_drv_mb { · 162 unmodified lines | |||
| 12748 | #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002 | 12750 | #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002 |
| 12749 | #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK 0x00010000 | 12751 | #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK 0x00010000 |
| 12750 | 12752 | ||
| 12753 | #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_SHIFT 0 | ||
| 12754 | #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK 0x0000FFFF | ||
| 12755 | #define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_SHIFT 16 | ||
| 12756 | #define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_MASK 0x00010000 | ||
| 12757 | #define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_SHIFT 17 | ||
| 12758 | #define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK 0x00020000 | ||
| 12759 | #define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_SHIFT 18 | ||
| 12760 | #define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK 0x00040000 | ||
| 12761 | #define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_SHIFT 19 | ||
| 12762 | #define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK 0x00080000 | ||
| 12763 | #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_SHIFT 20 | ||
| 12764 | #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_MASK 0x00100000 | ||
| 12765 | #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_SHIFT 24 | ||
| 12766 | #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_MASK 0x0f000000 | ||
| 12767 | |||
| 12751 | u32 fw_mb_header; | 12768 | u32 fw_mb_header; |
| 12752 | #define FW_MSG_CODE_MASK 0xffff0000 | 12769 | #define FW_MSG_CODE_MASK 0xffff0000 |
| 12753 | #define FW_MSG_CODE_UNSUPPORTED 0x00000000 | 12770 | #define FW_MSG_CODE_UNSUPPORTED 0x00000000 |
| @@ -3750,3 +3750,35 @@ int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) · 3749 unmodified lines | |||
| 3750 | 3750 | ||
| 3751 | return 0; | 3751 | return 0; |
| 3752 | } | 3752 | } |
| 3753 | |||
| 3754 | int qed_mcp_nvm_set_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, | ||
| 3755 | u16 option_id, u8 entity_id, u16 flags, u8 *p_buf, | ||
| 3756 | u32 len) | ||
| 3757 | { | ||
| 3758 | u32 mb_param = 0, resp, param; | ||
| 3759 | |||
| 3760 | QED_MFW_SET_FIELD(mb_param, DRV_MB_PARAM_NVM_CFG_OPTION_ID, option_id); | ||
| 3761 | if (flags & QED_NVM_CFG_OPTION_ALL) | ||
| 3762 | QED_MFW_SET_FIELD(mb_param, | ||
| 3763 | DRV_MB_PARAM_NVM_CFG_OPTION_ALL, 1); | ||
| 3764 | if (flags & QED_NVM_CFG_OPTION_INIT) | ||
| 3765 | QED_MFW_SET_FIELD(mb_param, | ||
| 3766 | DRV_MB_PARAM_NVM_CFG_OPTION_INIT, 1); | ||
| 3767 | if (flags & QED_NVM_CFG_OPTION_COMMIT) | ||
| 3768 | QED_MFW_SET_FIELD(mb_param, | ||
| 3769 | DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT, 1); | ||
| 3770 | if (flags & QED_NVM_CFG_OPTION_FREE) | ||
| 3771 | QED_MFW_SET_FIELD(mb_param, | ||
| 3772 | DRV_MB_PARAM_NVM_CFG_OPTION_FREE, 1); | ||
| 3773 | if (flags & QED_NVM_CFG_OPTION_ENTITY_SEL) { | ||
| 3774 | QED_MFW_SET_FIELD(mb_param, | ||
| 3775 | DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL, 1); | ||
| 3776 | QED_MFW_SET_FIELD(mb_param, | ||
| 3777 | DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID, | ||
| 3778 | entity_id); | ||
| 3779 | } | ||
| 3780 | |||
| 3781 | return qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, | ||
| 3782 | DRV_MSG_CODE_SET_NVM_CFG_OPTION, | ||
| 3783 | mb_param, &resp, ¶m, len, (u32 *)p_buf); | ||
| 3784 | } | ||
| @@ -251,6 +251,12 @@ union qed_mfw_tlv_data { · 250 unmodified lines | |||
| 251 | struct qed_mfw_tlv_iscsi iscsi; | 251 | struct qed_mfw_tlv_iscsi iscsi; |
| 252 | }; | 252 | }; |
| 253 | 253 | ||
| 254 | #define QED_NVM_CFG_OPTION_ALL BIT(0) | ||
| 255 | #define QED_NVM_CFG_OPTION_INIT BIT(1) | ||
| 256 | #define QED_NVM_CFG_OPTION_COMMIT BIT(2) | ||
| 257 | #define QED_NVM_CFG_OPTION_FREE BIT(3) | ||
| 258 | #define QED_NVM_CFG_OPTION_ENTITY_SEL BIT(4) | ||
| 259 | |||
| 254 | /** | 260 | /** |
| 255 | * @brief - returns the link params of the hw function | 261 | * @brief - returns the link params of the hw function |
| 256 | * | 262 | * |
| @@ -1202,4 +1208,18 @@ int qed_mcp_get_engine_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); · 945 unmodified lines | |||
| 1202 | */ | 1208 | */ |
| 1203 | int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); | 1209 | int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); |
| 1204 | 1210 | ||
| 1211 | /** | ||
| 1212 | * @brief Set NVM config attribute value. | ||
| 1213 | * | ||
| 1214 | * @param p_hwfn | ||
| 1215 | * @param p_ptt | ||
| 1216 | * @param option_id | ||
| 1217 | * @param entity_id | ||
| 1218 | * @param flags | ||
| 1219 | * @param p_buf | ||
| 1220 | * @param len | ||
| 1221 | */ | ||
| 1222 | int qed_mcp_nvm_set_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, | ||
| 1223 | u16 option_id, u8 entity_id, u16 flags, u8 *p_buf, | ||
| 1224 | u32 len); | ||
| 1205 | #endif | 1225 | #endif |