Some flash controllers don't have a software sequencer. Avoid configuring the register addresses for it, and double check everywhere that its not accidentally trying to be used. Every use of `sregs` is now guarded by a check of `sregs` or `swseq_reg`. The check might be done in the calling function.
Unified · Split
| @@ -187,12 +187,16 @@ static void intel_spi_dump_regs(struct intel_spi *ispi) · 186 unmodified lines | ||
| 187 | 187 | dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i, |
| 188 | 188 | readl(ispi->pregs + PR(i))); |
| 189 | 189 | |
| 190 | − value = readl(ispi->sregs + SSFSTS_CTL); | |
| 191 | − dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value); | |
| 192 | − dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n", | |
| 193 | − readl(ispi->sregs + PREOP_OPTYPE)); | |
| 194 | − dev_dbg(ispi->dev, "OPMENU0=0x%08x\n", readl(ispi->sregs + OPMENU0)); | |
| 195 | − dev_dbg(ispi->dev, "OPMENU1=0x%08x\n", readl(ispi->sregs + OPMENU1)); | |
| 190 | + if (ispi->sregs) { | |
| 191 | + value = readl(ispi->sregs + SSFSTS_CTL); | |
| 192 | + dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value); | |
| 193 | + dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n", | |
| 194 | + readl(ispi->sregs + PREOP_OPTYPE)); | |
| 195 | + dev_dbg(ispi->dev, "OPMENU0=0x%08x\n", | |
| 196 | + readl(ispi->sregs + OPMENU0)); | |
| 197 | + dev_dbg(ispi->dev, "OPMENU1=0x%08x\n", | |
| 198 | + readl(ispi->sregs + OPMENU1)); | |
| 199 | + } | |
| 196 | 200 | |
| 197 | 201 | if (ispi->info->type == INTEL_SPI_BYT) |
| 198 | 202 | dev_dbg(ispi->dev, "BCR=0x%08x\n", readl(ispi->base + BYT_BCR)); |
| @@ -367,6 +371,11 @@ static int intel_spi_init(struct intel_spi *ispi) · 168 unmodified lines | ||
| 367 | 371 | !(uvscc & ERASE_64K_OPCODE_MASK)) |
| 368 | 372 | ispi->erase_64k = false; |
| 369 | 373 | |
| 374 | + if (ispi->sregs == NULL && (ispi->swseq_reg || ispi->swseq_erase)) { | |
| 375 | + dev_err(ispi->dev, "software sequencer not supported, but required\n"); | |
| 376 | + return -EINVAL; | |
| 377 | + } | |
| 378 | + | |
| 370 | 379 | /* |
| 371 | 380 | * Some controllers can only do basic operations using hardware |
| 372 | 381 | * sequencer. All other operations are supposed to be carried out |
| @@ -383,7 +392,7 @@ static int intel_spi_init(struct intel_spi *ispi) · 10 unmodified lines | ||
| 383 | 392 | val = readl(ispi->base + HSFSTS_CTL); |
| 384 | 393 | ispi->locked = !!(val & HSFSTS_CTL_FLOCKDN); |
| 385 | 394 | |
| 386 | − if (ispi->locked) { | |
| 395 | + if (ispi->locked && ispi->sregs) { | |
| 387 | 396 | /* |
| 388 | 397 | * BIOS programs allowed opcodes and then locks down the |
| 389 | 398 | * register. So read back what opcodes it decided to support. |