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drm/amdgpu: update the core VI support for Stoney

Add core VI enablement for Stoney.

Samuel Li committed 11 years ago

Commit 39bb0c91 parent cfaba563 files · +34 −7Browse files

Unified · Split

3 files
  1. drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +2 −1
  2. drivers/gpu/drm/amd/amdgpu/vi.c +31 −5
  3. include/uapi/drm/amdgpu_drm.h +1 −1
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+2−1
@@ -1166,7 +1166,8 @@ static int amdgpu_early_init(struct amdgpu_device *adev) · 1165 unmodified lines
1166 case CHIP_TONGA:1166 case CHIP_TONGA:
1167 case CHIP_FIJI:1167 case CHIP_FIJI:
1168 case CHIP_CARRIZO:1168 case CHIP_CARRIZO:
1169 if (adev->asic_type == CHIP_CARRIZO)1169 case CHIP_STONEY:
1170 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1170 adev->family = AMDGPU_FAMILY_CZ;1171 adev->family = AMDGPU_FAMILY_CZ;
1171 else1172 else
1172 adev->family = AMDGPU_FAMILY_VI;1173 adev->family = AMDGPU_FAMILY_VI;
drivers/gpu/drm/amd/amdgpu/vi.c+31−5
@@ -232,6 +232,13 @@ static const u32 cz_mgcg_cgcg_init[] = · 231 unmodified lines
232 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,232 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
233};233};
234 234
235static const u32 stoney_mgcg_cgcg_init[] =
236{
237 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
238 mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
239 mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
240};
241
235static void vi_init_golden_registers(struct amdgpu_device *adev)242static void vi_init_golden_registers(struct amdgpu_device *adev)
236{243{
237 /* Some of the registers might be dependent on GRBM_GFX_INDEX */244 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
@@ -258,6 +265,11 @@ static void vi_init_golden_registers(struct amdgpu_device *adev) · 20 unmodified lines
258 cz_mgcg_cgcg_init,265 cz_mgcg_cgcg_init,
259 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));266 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
260 break;267 break;
268 case CHIP_STONEY:
269 amdgpu_program_register_sequence(adev,
270 stoney_mgcg_cgcg_init,
271 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
272 break;
261 default:273 default:
262 break;274 break;
263 }275 }
@@ -488,6 +500,7 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num, · 224 unmodified lines
488 case CHIP_FIJI:500 case CHIP_FIJI:
489 case CHIP_TONGA:501 case CHIP_TONGA:
490 case CHIP_CARRIZO:502 case CHIP_CARRIZO:
503 case CHIP_STONEY:
491 asic_register_table = cz_allowed_read_registers;504 asic_register_table = cz_allowed_read_registers;
492 size = ARRAY_SIZE(cz_allowed_read_registers);505 size = ARRAY_SIZE(cz_allowed_read_registers);
493 break;506 break;
@@ -543,8 +556,10 @@ static void vi_print_gpu_status_regs(struct amdgpu_device *adev) · 49 unmodified lines
543 RREG32(mmSRBM_STATUS2));556 RREG32(mmSRBM_STATUS2));
544 dev_info(adev->dev, " SDMA0_STATUS_REG = 0x%08X\n",557 dev_info(adev->dev, " SDMA0_STATUS_REG = 0x%08X\n",
545 RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));558 RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
546 dev_info(adev->dev, " SDMA1_STATUS_REG = 0x%08X\n",559 if (adev->sdma.num_instances > 1) {
547 RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));560 dev_info(adev->dev, " SDMA1_STATUS_REG = 0x%08X\n",
561 RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
562 }
548 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));563 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
549 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",564 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
550 RREG32(mmCP_STALLED_STAT1));565 RREG32(mmCP_STALLED_STAT1));
@@ -639,9 +654,11 @@ u32 vi_gpu_check_soft_reset(struct amdgpu_device *adev) · 88 unmodified lines
639 reset_mask |= AMDGPU_RESET_DMA;654 reset_mask |= AMDGPU_RESET_DMA;
640 655
641 /* SDMA1_STATUS_REG */656 /* SDMA1_STATUS_REG */
642 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);657 if (adev->sdma.num_instances > 1) {
643 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))658 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
644 reset_mask |= AMDGPU_RESET_DMA1;659 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
660 reset_mask |= AMDGPU_RESET_DMA1;
661 }
645#if 0662#if 0
646 /* VCE_STATUS */663 /* VCE_STATUS */
647 if (adev->asic_type != CHIP_TOPAZ) {664 if (adev->asic_type != CHIP_TOPAZ) {
@@ -1316,6 +1333,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) · 668 unmodified lines
1316 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);1333 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
1317 break;1334 break;
1318 case CHIP_CARRIZO:1335 case CHIP_CARRIZO:
1336 case CHIP_STONEY:
1319 adev->ip_blocks = cz_ip_blocks;1337 adev->ip_blocks = cz_ip_blocks;
1320 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);1338 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
1321 break;1339 break;
@@ -1327,11 +1345,18 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) · 5 unmodified lines
1327 return 0;1345 return 0;
1328}1346}
1329 1347
1348#define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044
1349#define ATI_REV_ID_FUSE_MACRO__SHIFT 9
1350#define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00
1351
1330static uint32_t vi_get_rev_id(struct amdgpu_device *adev)1352static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
1331{1353{
1332 if (adev->asic_type == CHIP_TOPAZ)1354 if (adev->asic_type == CHIP_TOPAZ)
1333 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)1355 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
1334 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;1356 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
1357 else if (adev->flags & AMD_IS_APU)
1358 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
1359 >> ATI_REV_ID_FUSE_MACRO__SHIFT;
1335 else1360 else
1336 return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)1361 return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
1337 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;1362 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
@@ -1398,6 +1423,7 @@ static int vi_common_early_init(void *handle) · 60 unmodified lines
1398 adev->firmware.smu_load = true;1423 adev->firmware.smu_load = true;
1399 break;1424 break;
1400 case CHIP_CARRIZO:1425 case CHIP_CARRIZO:
1426 case CHIP_STONEY:
1401 adev->has_uvd = true;1427 adev->has_uvd = true;
1402 adev->cg_flags = 0;1428 adev->cg_flags = 0;
1403 /* Disable UVD pg */1429 /* Disable UVD pg */
include/uapi/drm/amdgpu_drm.h+1−1
@@ -640,6 +640,6 @@ struct drm_amdgpu_info_hw_ip { · 639 unmodified lines
640#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */640#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */
641#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */641#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
642#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */642#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
643#define AMDGPU_FAMILY_CZ 135 /* Carrizo */643#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */
644 644
645#endif645#endif