Merge tag 'pinctrl-v5.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.12 kernel. This time a calm set with no core changes. New drivers/subdrivers: - Renesas R8A7790A0 pin controller. - Allwinner H616 and H616-R pin controllers. - Qualcomm SM8350 and SC8180x pin controllers. Improvements: - Redo the DT bindings for Ralink RT2880. - A common Qualcomm TLMM DT binding in YAML. - Delete the unused drivers for U300, COH901, Sirf Atlas, and ZTE ZX" * tag 'pinctrl-v5.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (71 commits) pinctrl: mediatek: Fix trigger type setting follow for unexpected interrupt dt-bindings: pinctrl: Group tuples in pin control properties pinctrl: nuvoton: npcm7xx: Fix alignment of table header comment pinctrl: at91-pio4: fix "Prefer 'unsigned int' to bare use of 'unsigned'" pinctrl: at91-pio4: add support for slew-rate dt-bindings: pinctrl: at91-pio4: add slew-rate pinctrl: actions: Add depends on || COMPILE_TEST pinctrl: single: set function name when adding function pinctrl: qcom: Add sc8180x TLMM driver dt-bindings: pinctrl: qcom: Add sc8180x binding dt-bindings: pinctrl: qcom: Define common TLMM binding pinctrl: qcom: Add SM8350 pinctrl driver dt-bindings: pinctrl: qcom: Add SM8350 pinctrl bindings pinctrl: samsung: use raw_spinlock for s3c64xx dt-bindings: mediatek: mt8192: Fix dt_binding_check warning pinctrl: qcom: spmi-mpp: Add PM8019 compatible pinctrl: pinmux: add function selector to pinmux-functions pinctrl: samsung: use raw_spinlock for locking pinctrl: clarify #pinctrl-cells for pinctrl-single,pins pinctrl: actions: Add the platform dependency to drivers ...

Linus Torvalds committed 5 years ago

Commit 3b9cdaf2 parents f81f213 b40b76088 files · +9220 −13458Browse files

Unified · Split

88 files

Documentation/devicetree/bindings/gpio/gpio-atlas7.txt +0 −50
Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt +0 −7
Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +15 −2
Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt +5 −3
Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.txt +1 −1
Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt +1 −1
Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt +1 −1
Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml +2 −2
Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt +0 −109
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +2 −2
Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt +1 −1
Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt +1 −1
Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +6 −6
Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt +0 −84
Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt +1 −0
Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-pinctrl.yaml +152 −0
Documentation/devicetree/bindings/pinctrl/qcom,sm8350-pinctrl.yaml +145 −0
Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml +85 −0
Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml +28 −34
Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml +2 −1
Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +1 −1
drivers/pinctrl/Kconfig +0 −25
drivers/pinctrl/Makefile +0 −4
drivers/pinctrl/actions/Kconfig +3 −0
drivers/pinctrl/actions/pinctrl-owl.c +0 −1
drivers/pinctrl/bcm/pinctrl-ns2-mux.c +1 −1
drivers/pinctrl/core.c +0 −1
drivers/pinctrl/freescale/pinctrl-imx1-core.c +0 −1
drivers/pinctrl/intel/pinctrl-intel.c +83 −34
drivers/pinctrl/intel/pinctrl-intel.h +4 −0
drivers/pinctrl/intel/pinctrl-tigerlake.c +1 −0
drivers/pinctrl/mediatek/mtk-eint.c +11 −2
drivers/pinctrl/mediatek/pinctrl-moore.c +2 −2
drivers/pinctrl/mediatek/pinctrl-paris.c +2 −2
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +0 −1
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +1 −1
drivers/pinctrl/pinctrl-at91-pio4.c +84 −53
drivers/pinctrl/pinctrl-at91.c +1 −2
drivers/pinctrl/pinctrl-coh901.c +0 −774
drivers/pinctrl/pinctrl-coh901.h +0 −6
drivers/pinctrl/pinctrl-ingenic.c +76 −22
drivers/pinctrl/pinctrl-single.c +1 −0
drivers/pinctrl/pinctrl-st.c +0 −1
drivers/pinctrl/pinctrl-sx150x.c +0 −1
drivers/pinctrl/pinctrl-u300.c +0 −1111
drivers/pinctrl/pinmux.c +1 −1
drivers/pinctrl/qcom/Kconfig +18 −0
drivers/pinctrl/qcom/Makefile +2 −0
drivers/pinctrl/qcom/pinctrl-sc8180x.c +1624 −0
drivers/pinctrl/qcom/pinctrl-sdm845.c +0 −1
drivers/pinctrl/qcom/pinctrl-sm8350.c +1649 −0
drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +1 −0
drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +0 −1
drivers/pinctrl/ralink/pinctrl-rt2880.c +23 −24
drivers/pinctrl/renesas/Kconfig +5 −0
drivers/pinctrl/renesas/Makefile +1 −0
drivers/pinctrl/renesas/core.c +28 −10
drivers/pinctrl/renesas/pfc-r8a77950.c +0 −1
drivers/pinctrl/renesas/pfc-r8a77951.c +0 −1
drivers/pinctrl/renesas/pfc-r8a7796.c +0 −1
drivers/pinctrl/renesas/pfc-r8a77965.c +0 −1
drivers/pinctrl/renesas/pfc-r8a779a0.c +4460 −0
drivers/pinctrl/renesas/pinctrl.c +14 −2
drivers/pinctrl/renesas/sh_pfc.h +23 −5
drivers/pinctrl/samsung/pinctrl-exynos.c +8 −8
drivers/pinctrl/samsung/pinctrl-s3c24xx.c +2 −2
drivers/pinctrl/samsung/pinctrl-s3c64xx.c +2 −2
drivers/pinctrl/samsung/pinctrl-samsung.c +11 −11
drivers/pinctrl/samsung/pinctrl-samsung.h +1 −1
drivers/pinctrl/sirf/Makefile +0 −7
drivers/pinctrl/sirf/pinctrl-atlas6.c +0 −1137
drivers/pinctrl/sirf/pinctrl-atlas7.c +0 −6157
drivers/pinctrl/sirf/pinctrl-prima2.c +0 −1131
drivers/pinctrl/sirf/pinctrl-sirf.c +0 −894
drivers/pinctrl/sirf/pinctrl-sirf.h +0 −116
drivers/pinctrl/sprd/pinctrl-sprd.c +1 −1
drivers/pinctrl/sunxi/Kconfig +10 −0
drivers/pinctrl/sunxi/Makefile +2 −0
drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c +2 −0
drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c +56 −0
drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c +548 −0
drivers/pinctrl/ti/pinctrl-ti-iodelay.c +3 −4
drivers/pinctrl/zte/Kconfig +0 −14
drivers/pinctrl/zte/Makefile +0 −3
drivers/pinctrl/zte/pinctrl-zx.c +0 −445
drivers/pinctrl/zte/pinctrl-zx.h +0 −102
drivers/pinctrl/zte/pinctrl-zx296718.c +0 −1024
include/linux/kconfig.h +6 −0

Documentation/devicetree/bindings/gpio/gpio-atlas7.txt+0−50

@@ -1,50 +0,0 @@
1		−CSR SiRFatlas7 GPIO controller bindings
2		−
3		−Required properties:
4		−- compatible : "sirf,atlas7-gpio"
5		−- reg : Address range of the pinctrl registers
6		−- interrupts : Interrupts used by every GPIO group
7		−- gpio-banks : How many gpio banks on this controller
8		−- gpio-controller : Indicates this device is a GPIO controller
9		−- interrupt-controller : Marks the device node as an interrupt controller
10		−
11		−The GPIO controller also acts as an interrupt controller. It uses the default
12		−two cells specifier as described in Documentation/devicetree/bindings/
13		−interrupt-controller/interrupts.txt.
14		−
15		−Example:
16		−
17		− gpio_0: gpio_mediam@17040000 {
18		− compatible = "sirf,atlas7-gpio";
19		− reg = <0x17040000 0x1000>;
20		− interrupts = <0 13 0>, <0 14 0>;
21		−
22		− #gpio-cells = <2>;
23		− #interrupt-cells = <2>;
24		−
25		− gpio-controller;
26		− interrupt-controller;
27		−
28		− gpio-banks = <2>;
29		− gpio-ranges = <&pinctrl 0 0 0>,
30		− <&pinctrl 32 0 0>;
31		− gpio-ranges-group-names = "lvds_gpio_grp",
32		− "uart_nand_gpio_grp";
33		− };
34		−
35		− leds {
36		− compatible = "gpio-leds";
37		−
38		− led1 {
39		− gpios = <&gpio_1 15 0>;
40		− ...
41		− };
42		−
43		− led2 {
44		− gpios = <&gpio_2 34 0>;
45		− ...
46		− };
47		− };
48		−
49		−Please refer to gpio.txt in this directory for details of the common
50		−gpio properties used by devices.

Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt+0−7

@@ -1,7 +0,0 @@
1		−ST-Ericsson COH 901 571/3 GPIO controller
2		−
3		−Required properties:
4		−- compatible: Compatible property value should be "stericsson,gpio-coh901"
5		−- reg: Physical base address of the controller and length of memory mapped
6		− region.
7		−- interrupts: the 0...n interrupts assigned to the different GPIO ports/banks.

Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml+15−2

@@ -53,6 +53,8 @@ properties: · 52 unmodified lines
53	53	- allwinner,sun50i-h5-pinctrl
54	54	- allwinner,sun50i-h6-pinctrl
55	55	- allwinner,sun50i-h6-r-pinctrl
	56	+ - allwinner,sun50i-h616-pinctrl
	57	+ - allwinner,sun50i-h616-r-pinctrl
56	58	- allwinner,suniv-f1c100s-pinctrl
57	59	- nextthing,gr8-pinctrl
58	60
@@ -61,7 +63,7 @@ properties: · 2 unmodified lines
61	63
62	64	interrupts:
63	65	minItems: 1
64		− maxItems: 7
	66	+ maxItems: 8
65	67	description:
66	68	One interrupt per external interrupt bank supported on the
67	69	controller, sorted by bank number ascending order.
@@ -91,7 +93,7 @@ properties: · 23 unmodified lines
91	93	bank found in the controller
92	94	$ref: /schemas/types.yaml#/definitions/uint32-array
93	95	minItems: 1
94		− maxItems: 5
	96	+ maxItems: 8
95	97
96	98	patternProperties:
97	99	# It's pretty scary, but the basic idea is that:
@@ -145,6 +147,17 @@ allOf: · 47 unmodified lines
145	147	# boards are defining it at the moment so it would generate a lot of
146	148	# warnings.
147	149
	150	+ - if:
	151	+ properties:
	152	+ compatible:
	153	+ enum:
	154	+ - allwinner,sun50i-h616-pinctrl
	155	+
	156	+ then:
	157	+ properties:
	158	+ interrupts:
	159	+ minItems: 8
	160	+
148	161	- if:
149	162	properties:
150	163	compatible:

Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt+5−3

@@ -35,9 +35,11 @@ ioset settings. Use the macros from boot/dts/<soc>-pinfunc.h file to get the · 34 unmodified lines
35	35	right representation of the pin.
36	36
37	37	Optional properties:
38		−- GENERIC_PINCONFIG: generic pinconfig options to use, bias-disable,
39		−bias-pull-down, bias-pull-up, drive-open-drain, input-schmitt-enable,
40		−input-debounce, output-low, output-high.
	38	+- GENERIC_PINCONFIG: generic pinconfig options to use:
	39	+ - bias-disable, bias-pull-down, bias-pull-up, drive-open-drain,
	40	+ input-schmitt-enable, input-debounce, output-low, output-high.
	41	+ - for microchip,sama7g5-pinctrl only:
	42	+ - slew-rate: 0 - disabled, 1 - enabled (default)
41	43	- atmel,drive-strength: 0 or 1 for low drive, 2 for medium drive and 3 for
42	44	high drive. The default value is low drive.
43	45

Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.txt+1−1

@@ -39,7 +39,7 @@ For example: · 38 unmodified lines
39	39	<0x660009b0 0x40>;
40	40
41	41	pinctrl-names = "default";
42		− pinctrl-0 = <&nand_sel &uart3_rx &sdio0_d4>;
	42	+ pinctrl-0 = <&nand_sel>, <&uart3_rx>, <&sdio0_d4>;
43	43
44	44	/* Select nand function */
45	45	nand_sel: nand_sel {

Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt+1−1

@@ -30,7 +30,7 @@ For example: · 29 unmodified lines
30	30	<0x1803f408 0x04>;
31	31
32	32	pinctrl-names = "default";
33		− pinctrl-0 = <&pwm &gpio_b &nand_sel>;
	33	+ pinctrl-0 = <&pwm>, <&gpio_b>, <&nand_sel>;
34	34
35	35	pwm: pwm {
36	36	function = "pwm";

Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt+1−1

@@ -60,7 +60,7 @@ iomuxc-lpsr controller and SDA pad from iomuxc controller as: · 59 unmodified lines
60	60
61	61	i2c1: i2c@30a20000 {
62	62	pinctrl-names = "default";
63		− pinctrl-0 = <&pinctrl_i2c1_1 &pinctrl_i2c1_2>;
	63	+ pinctrl-0 = <&pinctrl_i2c1_1>, <&pinctrl_i2c1_2>;
64	64	};
65	65
66	66	iomuxc-lpsr@302c0000 {

Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml+2−2

@@ -99,8 +99,8 @@ patternProperties: · 98 unmodified lines
99	99
100	100	'#interrupt-cells':
101	101	description:
102		− Specifies the pin (port and bit) and flags, as defined in
103		− defined in include/dt-bindings/interrupt-controller/irq.h
	102	+ Specifies the pin (port and bit) and flags, as defined in
	103	+ defined in include/dt-bindings/interrupt-controller/irq.h
104	104	const: 3
105	105
106	106	ngpios:

Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt+0−109

@@ -1,109 +0,0 @@
1		−CSR SiRFatlas7 pinmux controller
2		−
3		−Required properties:
4		−- compatible : "sirf,atlas7-ioc"
5		−- reg : Address range of the pinctrl registers
6		−
7		−For example, pinctrl might have properties like the following:
8		− pinctrl: ioc@18880000 {
9		− compatible = "sirf,atlas7-ioc";
10		− reg = <0x18880000 0x1000>;
11		−
12		− a_ac97_pmx: ac97@0 {
13		− ac97 {
14		− groups = "audio_ac97_grp";
15		− function = "audio_ac97";
16		− };
17		− };
18		−
19		− ...
20		−
21		− sd2_pmx: sd2@0 {
22		− sd2 {
23		− groups = "sd2_grp0";
24		− function = "sd2";
25		− };
26		− };
27		−
28		− ...
29		−
30		−
31		− sample0_cfg: sample0@0 {
32		− sample0 {
33		− pins = "ldd_0", "ldd_1";
34		− bias-pull-up;
35		− };
36		− };
37		−
38		− sample1_cfg: sample1@0 {
39		− sample1 {
40		− pins = "ldd_2", "ldd_3";
41		− input-schmitt-enable;
42		− };
43		− };
44		−
45		− sample2_cfg: sample2@0 {
46		− sample2 {
47		− groups = "uart4_nopause_grp";
48		− bias-pull-down;
49		− };
50		− };
51		−
52		− sample3_cfg: sample3@0 {
53		− sample3 {
54		− pins = "ldd_4", "ldd_5";
55		− drive-strength = <2>;
56		− };
57		− };
58		− };
59		−
60		−Please refer to pinctrl-bindings.txt in this directory for details of the common
61		−pinctrl bindings used by client devices.
62		−
63		−SiRFatlas7's pinmux nodes act as a container for an arbitrary number of subnodes.
64		−Each of these subnodes represents some desired configuration for a group of pins.
65		−
66		−Required subnode-properties:
67		−- groups : An array of strings. Each string contains the name of a group.
68		−- function: A string containing the name of the function to mux to the
69		− group.
70		−
71		− Valid values for group and function names can be found from looking at the
72		− group and function arrays in driver files:
73		− drivers/pinctrl/pinctrl-sirf.c
74		−
75		−For example, pinctrl might have subnodes like the following:
76		− sd0_pmx: sd0@0 {
77		− sd0 {
78		− groups = "sd0_grp";
79		− function = "sd0";
80		− };
81		− };
82		−
83		− sd1_pmx0: sd1@0 {
84		− sd1 {
85		− groups = "sd1_grp0";
86		− function = "sd1_m0";
87		− };
88		− };
89		−
90		− sd1_pmx1: sd1@1 {
91		− sd1 {
92		− groups = "sd1_grp1";
93		− function = "sd1_m1";
94		− };
95		− };
96		−
97		−For a specific board, if it wants to use sd1,
98		−it can add the following to its board-specific .dts file.
99		−sd1: sd@12340000 {
100		− pinctrl-names = "default";
101		− pinctrl-0 = <&sd1_pmx0>;
102		−}
103		−
104		−or
105		−
106		−sd1: sd@12340000 {
107		− pinctrl-names = "default";
108		− pinctrl-0 = <&sd1_pmx1>;
109		−}

Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt+2−2

@@ -77,13 +77,13 @@ For example: · 76 unmodified lines
77	77	device {
78	78	pinctrl-names = "active", "idle";
79	79	pinctrl-0 = <&state_0_node_a>;
80		− pinctrl-1 = <&state_1_node_a &state_1_node_b>;
	80	+ pinctrl-1 = <&state_1_node_a>, <&state_1_node_b>;
81	81	};
82	82
83	83	/* For the same device if using state IDs */
84	84	device {
85	85	pinctrl-0 = <&state_0_node_a>;
86		− pinctrl-1 = <&state_1_node_a &state_1_node_b>;
	86	+ pinctrl-1 = <&state_1_node_a>, <&state_1_node_b>;
87	87	};
88	88
89	89	/*

Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt+1−1

@@ -134,7 +134,7 @@ gpio21: gpio@21 { · 133 unmodified lines
134	134	#interrupt-cells = <0x2>;
135	135	microchip,irq-mirror;
136	136	pinctrl-names = "default";
137		− pinctrl-0 = <&i2cgpio0irq &gpio21pullups>;
	137	+ pinctrl-0 = <&i2cgpio0irq>, <&gpio21pullups>;
138	138
139	139	gpio21pullups: pinmux {
140	140	pins = "gpio0", "gpio1", "gpio2", "gpio3",

Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt+1−1

@@ -91,7 +91,7 @@ Examples: · 90 unmodified lines
91	91	pinctrl@1c20800 {
92	92	compatible = "mediatek,mt8135-pinctrl";
93	93	reg = <0 0x1000B000 0 0x1000>;
94		− mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
	94	+ mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
95	95	pins-are-numbered;
96	96	gpio-controller;
97	97	#gpio-cells = <2>;

Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt+6−6

@@ -8,7 +8,7 @@ Required properties: · 7 unmodified lines
8	8	- reg : offset and length of the register set for the mux registers
9	9
10	10	- #pinctrl-cells : number of cells in addition to the index, set to 1
11		− for pinctrl-single,pins and 2 for pinctrl-single,bits
	11	+ or 2 for pinctrl-single,pins and set to 2 for pinctrl-single,bits
12	12
13	13	- pinctrl-single,register-width : pinmux register access width in bits
14	14
@@ -80,7 +80,7 @@ Optional properties: · 65 unmodified lines
80	80	property.
81	81
82	82	/* pin base, nr pins & gpio function */
83		− pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;
	83	+ pinctrl-single,gpio-range = <&range 0 3 0>, <&range 3 9 1>;
84	84
85	85	- interrupt-controller : standard interrupt controller binding if using
86	86	interrupts for wake-up events for example. In this case pinctrl-single
@@ -185,10 +185,10 @@ pmx_gpio: pinmux@d401e000 { · 98 unmodified lines
185	185	pinctrl-single,function-mask = <7>;
186	186
187	187	/* sparse GPIO range could be supported */
188		− pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
189		− &range 12 1 0 &range 13 29 1
190		− &range 43 1 0 &range 44 49 1
191		− &range 94 1 1 &range 96 2 1>;
	188	+ pinctrl-single,gpio-range = <&range 0 3 0>, <&range 3 9 1>,
	189	+ <&range 12 1 0>, <&range 13 29 1>,
	190	+ <&range 43 1 0>, <&range 44 49 1>,
	191	+ <&range 94 1 1>, <&range 96 2 1>;
192	192
193	193	range: gpio-range {
194	194	#pinctrl-single,gpio-range-cells = <3>;

Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt+0−84

@@ -1,84 +0,0 @@
1		−* ZTE ZX Pin Controller
2		−
3		−The pin controller on ZTE ZX platforms is kinda of hybrid. It consists of
4		−a main controller and an auxiliary one. For example, on ZX296718 SoC, the
5		−main controller is TOP_PMM and the auxiliary one is AON_IOCFG. Both
6		−controllers work together to control pin multiplexing and configuration in
7		−the way illustrated as below.
8		−
9		−
10		− GMII_RXD3 ---+
11		− \|
12		− DVI1_HS ---+----------------------------- GMII_RXD3 (TOP pin)
13		− \|
14		− BGPIO16 ---+ ^
15		− \| pinconf
16		− ^ \|
17		− \| pinmux \|
18		− \| \|
19		−
20		− TOP_PMM (main) AON_IOCFG (aux)
21		−
22		− \| \| \|
23		− \| pinmux \| \|
24		− \| pinmux v \|
25		− v \| pinconf
26		− KEY_ROW2 ---+ v
27		− PORT1_LCD_TE ---+ \|
28		− \| AGPIO10 ---+------ KEY_ROW2 (AON pin)
29		− I2S0_DOUT3 ---+ \|
30		− \|-----------------------+
31		− PWM_OUT3 ---+
32		− \|
33		− VGA_VS1 ---+
34		−
35		−
36		−For most of pins like GMII_RXD3 in the figure, the pinmux function is
37		−controlled by TOP_PMM block only, and this type of pins are meant by term
38		−'TOP pins'. For pins like KEY_ROW2, the pinmux is controlled by both
39		−TOP_PMM and AON_IOCFG blocks, as the available multiplexing functions for
40		−the pin spread in both controllers. This type of pins are called 'AON pins'.
41		−Though pinmux implementation is quite different, pinconf is same for both
42		−types of pins. Both are controlled by auxiliary controller, i.e. AON_IOCFG
43		−on ZX296718.
44		−
45		−Required properties:
46		−- compatible: should be "zte,zx296718-pmm".
47		−- reg: the register physical address and length.
48		−- zte,auxiliary-controller: phandle to the auxiliary pin controller which
49		− implements pinmux for AON pins and pinconf for all pins.
50		−
51		−The following pin configuration are supported. Please refer to
52		−pinctrl-bindings.txt in this directory for more details of the common
53		−pinctrl bindings used by client devices.
54		−
55		−- bias-pull-up
56		−- bias-pull-down
57		−- drive-strength
58		−- input-enable
59		−- slew-rate
60		−
61		−Examples:
62		−
63		−iocfg: pin-controller@119000 {
64		− compatible = "zte,zx296718-iocfg";
65		− reg = <0x119000 0x1000>;
66		−};
67		−
68		−pmm: pin-controller@1462000 {
69		− compatible = "zte,zx296718-pmm";
70		− reg = <0x1462000 0x1000>;
71		− zte,auxiliary-controller = <&iocfg>;
72		−};
73		−
74		−&pmm {
75		− vga_pins: vga {
76		− pins = "KEY_COL1", "KEY_COL2", "KEY_ROW1", "KEY_ROW2";
77		− function = "VGA";
78		− };
79		−};
80		−
81		−&vga {
82		− pinctrl-names = "default";
83		− pinctrl-0 = <&vga_pins>;
84		−};

Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt+1−0

@@ -8,6 +8,7 @@ of PMIC's from Qualcomm. · 7 unmodified lines
8	8	Value type: <string>
9	9	Definition: Should contain one of:
10	10	"qcom,pm8018-mpp",
	11	+ "qcom,pm8019-mpp",
11	12	"qcom,pm8038-mpp",
12	13	"qcom,pm8058-mpp",
13	14	"qcom,pm8821-mpp",

Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-pinctrl.yaml+152−0

@@ -0,0 +1,152 @@
	1	+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	+%YAML 1.2
	3	+---
	4	+$id: http://devicetree.org/schemas/pinctrl/qcom,sc8180x-pinctrl.yaml#
	5	+$schema: http://devicetree.org/meta-schemas/core.yaml#
	6	+
	7	+title: Qualcomm Technologies, Inc. SC8180X TLMM block
	8	+
	9	+maintainers:
	10	+ - Bjorn Andersson <bjorn.andersson@linaro.org>
	11	+
	12	+description: \|
	13	+ This binding describes the Top Level Mode Multiplexer block found in the
	14	+ SC8180X platform.
	15	+
	16	+allOf:
	17	+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
	18	+
	19	+properties:
	20	+ compatible:
	21	+ const: qcom,sc8180x-tlmm
	22	+
	23	+ reg:
	24	+ maxItems: 3
	25	+
	26	+ reg-names:
	27	+ items:
	28	+ - const: "west"
	29	+ - const: "east"
	30	+ - const: "south"
	31	+
	32	+ interrupts: true
	33	+ interrupt-controller: true
	34	+ '#interrupt-cells': true
	35	+ gpio-controller: true
	36	+ gpio-reserved-ranges: true
	37	+ '#gpio-cells': true
	38	+ gpio-ranges: true
	39	+ wakeup-parent: true
	40	+
	41	+required:
	42	+ - compatible
	43	+ - reg
	44	+ - reg-names
	45	+
	46	+additionalProperties: false
	47	+
	48	+patternProperties:
	49	+ '-state$':
	50	+ oneOf:
	51	+ - $ref: "#/$defs/qcom-sc8180x-tlmm-state"
	52	+ - patternProperties:
	53	+ ".*":
	54	+ $ref: "#/$defs/qcom-sc8180x-tlmm-state"
	55	+
	56	+'$defs':
	57	+ qcom-sc8180x-tlmm-state:
	58	+ type: object
	59	+ description:
	60	+ Pinctrl node's client devices use subnodes for desired pin configuration.
	61	+ Client device subnodes use below standard properties.
	62	+ $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
	63	+
	64	+ properties:
	65	+ pins:
	66	+ description:
	67	+ List of gpio pins affected by the properties specified in this
	68	+ subnode.
	69	+ items:
	70	+ oneOf:
	71	+ - pattern: "^gpio([0-9]\|[1-9][0-9]\|1[0-8][0-9])$"
	72	+ - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
	73	+ minItems: 1
	74	+ maxItems: 16
	75	+
	76	+ function:
	77	+ description:
	78	+ Specify the alternative function to be configured for the specified
	79	+ pins.
	80	+
	81	+ enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_tsens,
	82	+ atest_tsens2, atest_usb0, atest_usb1, atest_usb2, atest_usb3,
	83	+ atest_usb4, audio_ref, btfm_slimbus, cam_mclk, cci_async,
	84	+ cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
	85	+ cci_timer4, cci_timer5, cci_timer6, cci_timer7, cci_timer8,
	86	+ cci_timer9, cri_trng, dbg_out, ddr_bist, ddr_pxi, debug_hot,
	87	+ dp_hot, edp_hot, edp_lcd, emac_phy, emac_pps, gcc_gp1, gcc_gp2,
	88	+ gcc_gp3, gcc_gp4, gcc_gp5, gpio, gps, grfc, hs1_mi2s, hs2_mi2s,
	89	+ hs3_mi2s, jitter_bist, lpass_slimbus, m_voc, mdp_vsync,
	90	+ mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4,
	91	+ mdp_vsync5, mss_lte, nav_pps, pa_indicator, pci_e0, pci_e1,
	92	+ pci_e2, pci_e3, phase_flag, pll_bist, pll_bypassnl, pll_reset,
	93	+ pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, qdss_gpio, qlink,
	94	+ qspi0, qspi0_clk, qspi0_cs, qspi1, qspi1_clk, qspi1_cs,
	95	+ qua_mi2s, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
	96	+ qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
	97	+ qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii, sd_write, sdc4,
	98	+ sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu,
	99	+ tsense_pwm1, tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt,
	100	+ usb0_phy, usb1_phy, usb2phy_ac, vfr_1, vsense_trigger,
	101	+ wlan1_adc, wlan2_adc, wmss_reset ]
	102	+
	103	+ bias-disable: true
	104	+ bias-pull-down: true
	105	+ bias-pull-up: true
	106	+ drive-strength: true
	107	+ input-enable: true
	108	+ output-high: true
	109	+ output-low: true
	110	+
	111	+ required:
	112	+ - pins
	113	+ - function
	114	+
	115	+ additionalProperties: false
	116	+
	117	+examples:
	118	+ - \|
	119	+ #include <dt-bindings/interrupt-controller/arm-gic.h>
	120	+ pinctrl@3100000 {
	121	+ compatible = "qcom,sc8180x-tlmm";
	122	+ reg = <0x03100000 0x300000>,
	123	+ <0x03500000 0x700000>,
	124	+ <0x03d00000 0x300000>;
	125	+ reg-names = "west", "east", "south";
	126	+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	127	+ gpio-controller;
	128	+ #gpio-cells = <2>;
	129	+ interrupt-controller;
	130	+ #interrupt-cells = <2>;
	131	+ gpio-ranges = <&tlmm 0 0 190>;
	132	+
	133	+ gpio-wo-subnode-state {
	134	+ pins = "gpio1";
	135	+ function = "gpio";
	136	+ };
	137	+
	138	+ uart-w-subnodes-state {
	139	+ rx {
	140	+ pins = "gpio4";
	141	+ function = "qup6";
	142	+ bias-pull-up;
	143	+ };
	144	+
	145	+ tx {
	146	+ pins = "gpio5";
	147	+ function = "qup6";
	148	+ bias-disable;
	149	+ };
	150	+ };
	151	+ };
	152	+...

Documentation/devicetree/bindings/pinctrl/qcom,sm8350-pinctrl.yaml+145−0

@@ -0,0 +1,145 @@
	1	+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	+%YAML 1.2
	3	+---
	4	+$id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-pinctrl.yaml#
	5	+$schema: http://devicetree.org/meta-schemas/core.yaml#
	6	+
	7	+title: Qualcomm Technologies, Inc. SM8350 TLMM block
	8	+
	9	+maintainers:
	10	+ - Vinod Koul <vkoul@kernel.org>
	11	+
	12	+description: \|
	13	+ This binding describes the Top Level Mode Multiplexer (TLMM) block found
	14	+ in the SM8350 platform.
	15	+
	16	+allOf:
	17	+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
	18	+
	19	+properties:
	20	+ compatible:
	21	+ const: qcom,sm8350-tlmm
	22	+
	23	+ reg:
	24	+ maxItems: 1
	25	+
	26	+ interrupts: true
	27	+ interrupt-controller: true
	28	+ '#interrupt-cells': true
	29	+ gpio-controller: true
	30	+ gpio-reserved-ranges: true
	31	+ '#gpio-cells': true
	32	+ gpio-ranges: true
	33	+ wakeup-parent: true
	34	+
	35	+required:
	36	+ - compatible
	37	+ - reg
	38	+
	39	+additionalProperties: false
	40	+
	41	+patternProperties:
	42	+ '-state$':
	43	+ oneOf:
	44	+ - $ref: "#/$defs/qcom-sm8350-tlmm-state"
	45	+ - patternProperties:
	46	+ ".*":
	47	+ $ref: "#/$defs/qcom-sm8350-tlmm-state"
	48	+
	49	+$defs:
	50	+ qcom-sm8350-tlmm-state:
	51	+ type: object
	52	+ description:
	53	+ Pinctrl node's client devices use subnodes for desired pin configuration.
	54	+ Client device subnodes use below standard properties.
	55	+ $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
	56	+
	57	+ properties:
	58	+ pins:
	59	+ description:
	60	+ List of gpio pins affected by the properties specified in this
	61	+ subnode.
	62	+ items:
	63	+ oneOf:
	64	+ - pattern: "^gpio([0-9]\|[1-9][0-9]\|1[0-9][0-9]\|20[0-3])$"
	65	+ - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
	66	+ minItems: 1
	67	+ maxItems: 36
	68	+
	69	+ function:
	70	+ description:
	71	+ Specify the alternative function to be configured for the specified
	72	+ pins.
	73	+
	74	+ enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async,
	75	+ cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng,
	76	+ cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
	77	+ ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
	78	+ gpio, ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
	79	+ mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
	80	+ mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck,
	81	+ mi2s1_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws,
	82	+ mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
	83	+ mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6,
	84	+ mss_grfc7, mss_grfc8, mss_grfc9, nav_gpio, pa_indicator,
	85	+ pcie0_clkreqn, pcie1_clkreqn, phase_flag, pll_bist, pll_clk,
	86	+ pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable,
	87	+ qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
	88	+ qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, qspi0,
	89	+ qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10,
	90	+ qup11, qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19,
	91	+ qup2, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5,
	92	+ qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk,
	93	+ sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2,
	94	+ tgu_ch3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data,
	95	+ uim0_present, uim0_reset, uim1_clk, uim1_data, uim1_present,
	96	+ uim1_reset, usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ]
	97	+
	98	+
	99	+ bias-disable: true
	100	+ bias-pull-down: true
	101	+ bias-pull-up: true
	102	+ drive-strength: true
	103	+ input-enable: true
	104	+ output-high: true
	105	+ output-low: true
	106	+
	107	+ required:
	108	+ - pins
	109	+ - function
	110	+
	111	+ additionalProperties: false
	112	+
	113	+examples:
	114	+ - \|
	115	+ #include <dt-bindings/interrupt-controller/arm-gic.h>
	116	+ pinctrl@f100000 {
	117	+ compatible = "qcom,sm8350-tlmm";
	118	+ reg = <0x0f100000 0x300000>;
	119	+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	120	+ gpio-controller;
	121	+ #gpio-cells = <2>;
	122	+ interrupt-controller;
	123	+ #interrupt-cells = <2>;
	124	+ gpio-ranges = <&tlmm 0 0 203>;
	125	+
	126	+ gpio-wo-subnode-state {
	127	+ pins = "gpio1";
	128	+ function = "gpio";
	129	+ };
	130	+
	131	+ uart-w-subnodes-state {
	132	+ rx {
	133	+ pins = "gpio18";
	134	+ function = "qup3";
	135	+ bias-pull-up;
	136	+ };
	137	+
	138	+ tx {
	139	+ pins = "gpio19";
	140	+ function = "qup3";
	141	+ bias-disable;
	142	+ };
	143	+ };
	144	+ };
	145	+...

Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml+85−0

@@ -0,0 +1,85 @@
	1	+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	+%YAML 1.2
	3	+---
	4	+$id: http://devicetree.org/schemas/pinctrl/qcom,tlmm-common.yaml#
	5	+$schema: http://devicetree.org/meta-schemas/core.yaml#
	6	+
	7	+title: Qualcomm Technologies, Inc. Top Level Mode Multiplexer (TLMM) definitions
	8	+
	9	+maintainers:
	10	+ - Bjorn Andersson <bjorn.andersson@linaro.org>
	11	+
	12	+description:
	13	+ This defines the common properties used to describe all Qualcomm Top Level
	14	+ Mode Multiplexer bindings and pinconf/pinmux states for these.
	15	+
	16	+properties:
	17	+ interrupts:
	18	+ description:
	19	+ Specifies the TLMM summary IRQ
	20	+ maxItems: 1
	21	+
	22	+ interrupt-controller: true
	23	+
	24	+ '#interrupt-cells':
	25	+ description:
	26	+ Specifies the PIN numbers and Flags, as defined in defined in
	27	+ include/dt-bindings/interrupt-controller/irq.h
	28	+ const: 2
	29	+
	30	+ gpio-controller: true
	31	+
	32	+ '#gpio-cells':
	33	+ description:
	34	+ Specifying the pin number and flags, as defined in
	35	+ include/dt-bindings/gpio/gpio.h
	36	+ const: 2
	37	+
	38	+ gpio-ranges:
	39	+ maxItems: 1
	40	+
	41	+ wakeup-parent:
	42	+ description:
	43	+ Specifying the interrupt-controller used to wake up the system when the
	44	+ TLMM block has been powered down.
	45	+ maxItems: 1
	46	+
	47	+ gpio-reserved-ranges:
	48	+ description:
	49	+ Pins can be reserved for trusted applications and thereby unaccessible
	50	+ from the OS. This property can be used to mark the pins which resources
	51	+ should not be accessed by the OS. Please see the ../gpio/gpio.txt for more
	52	+ information.
	53	+
	54	+required:
	55	+ - interrupts
	56	+ - interrupt-controller
	57	+ - '#interrupt-cells'
	58	+ - gpio-controller
	59	+ - '#gpio-cells'
	60	+ - gpio-ranges
	61	+
	62	+additionalProperties: true
	63	+
	64	+$defs:
	65	+ qcom-tlmm-state:
	66	+ allOf:
	67	+ - $ref: pincfg-node.yaml#
	68	+ - $ref: pinmux-node.yaml#
	69	+
	70	+ properties:
	71	+ drive-strength:
	72	+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
	73	+ default: 2
	74	+ description:
	75	+ Selects the drive strength for the specified pins, in mA.
	76	+
	77	+ bias-pull-down: true
	78	+ bias-pull-up: true
	79	+ bias-disable: true
	80	+ input-enable: true
	81	+ output-high: true
	82	+ output-low: true
	83	+
	84	+ additionalProperties: true
	85	+...

Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml+28−34

@@ -15,39 +15,38 @@ description: · 14 unmodified lines
15	15
16	16	properties:
17	17	compatible:
18		− enum:
19		− - ralink,rt2880-pinmux
	18	+ const: ralink,rt2880-pinmux
20	19
21		− pinctrl-0:
22		− description:
23		− A phandle to the node containing the subnodes containing default
24		− configurations. This is for pinctrl hogs.
	20	+patternProperties:
	21	+ '-pins$':
	22	+ type: object
	23	+ patternProperties:
	24	+ '^(.*-)?pinmux$':
	25	+ type: object
	26	+ description: node for pinctrl.
	27	+ $ref: pinmux-node.yaml#
	28	+
	29	+ properties:
	30	+ groups:
	31	+ description: Name of the pin group to use for the functions.
	32	+ enum: [i2c, spi, uart1, uart2, uart3, rgmii1, rgmii2, mdio,
	33	+ pcie, sdhci]
	34	+ function:
	35	+ description: The mux function to select
	36	+ enum: [gpio, i2c, spi, uart1, uart2, uart3, rgmii1, rgmii2,
	37	+ mdio, nand1, nand2, sdhci]
	38	+
	39	+ required:
	40	+ - groups
	41	+ - function
	42	+
	43	+ additionalProperties: false
25	44
26		− pinctrl-names:
27		− description:
28		− A pinctrl state named "default" can be defined.
29		− const: default
	45	+ additionalProperties: false
30	46
31	47	required:
32	48	- compatible
33	49
34		−patternProperties:
35		− '[a-z0-9_-]+':
36		− if:
37		− type: object
38		− description: node for pinctrl.
39		− $ref: "pinmux-node.yaml"
40		− then:
41		− properties:
42		− groups:
43		− description: Name of the pin group to use for the functions.
44		− enum: [i2c, spi, uart1, uart2, uart3, rgmii1, rgmii2, mdio,
45		− pcie, sdhci]
46		− function:
47		− description: The mux function to select
48		− enum: [gpio, i2c, spi, uart1, uart2, uart3, rgmii1, rgmii2,
49		− mdio, nand1, nand2, sdhci]
50		−
51	50	additionalProperties: false
52	51
53	52	examples:
@@ -55,14 +54,9 @@ examples: · 1 unmodified line
55	54	- \|
56	55	pinctrl {
57	56	compatible = "ralink,rt2880-pinmux";
58		− pinctrl-names = "default";
59		− pinctrl-0 = <&state_default>;
60		−
61		− state_default: pinctrl0 {
62		− };
63	57
64		− i2c_pins: i2c0 {
65		− i2c0 {
	58	+ i2c_pins: i2c0-pins {
	59	+ pinmux {
66	60	groups = "i2c";
67	61	function = "i2c";
68	62	};

Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml+2−1

@@ -43,11 +43,12 @@ properties: · 42 unmodified lines
43	43	- renesas,pfc-r8a77980 # R-Car V3H
44	44	- renesas,pfc-r8a77990 # R-Car E3
45	45	- renesas,pfc-r8a77995 # R-Car D3
	46	+ - renesas,pfc-r8a779a0 # R-Car V3U
46	47	- renesas,pfc-sh73a0 # SH-Mobile AG5
47	48
48	49	reg:
49	50	minItems: 1
50		− maxItems: 2
	51	+ maxItems: 10
51	52
52	53	gpio-controller: true
53	54

Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt+1−1

@@ -336,7 +336,7 @@ Example 3: A uart client node that supports 'default' and 'flow-control' states. · 335 unmodified lines
336	336	interrupts = <0 52 0>;
337	337	pinctrl-names = "default", "flow-control;
338	338	pinctrl-0 = <&uart0_data>;
339		− pinctrl-1 = <&uart0_data &uart0_fctl>;
	339	+ pinctrl-1 = <&uart0_data>, <&uart0_fctl>;
340	340	};
341	341
342	342	Example 4: Set up the default pin state for uart controller.

drivers/pinctrl/Kconfig+0−25

@@ -226,14 +226,6 @@ config PINCTRL_SINGLE · 225 unmodified lines
226	226	help
227	227	This selects the device tree based generic pinctrl driver.
228	228
229		−config PINCTRL_SIRF
230		− bool "CSR SiRFprimaII pin controller driver"
231		− depends on ARCH_SIRF
232		− select PINMUX
233		− select PINCONF
234		− select GENERIC_PINCONF
235		− select GPIOLIB_IRQCHIP
236		−
237	229	config PINCTRL_SX150X
238	230	bool "Semtech SX150x I2C GPIO expander pinctrl driver"
239	231	depends on I2C=y
@@ -279,22 +271,6 @@ config PINCTRL_STMFX · 39 unmodified lines
279	271	and configuring push-pull, open-drain, and can also be used as
280	272	interrupt-controller.
281	273
282		−config PINCTRL_U300
283		− bool "U300 pin controller driver"
284		− depends on ARCH_U300
285		− select PINMUX
286		− select GENERIC_PINCONF
287		−
288		−config PINCTRL_COH901
289		− bool "ST-Ericsson U300 COH 901 335/571 GPIO"
290		− depends on GPIOLIB && ARCH_U300 && PINCTRL_U300
291		− select GPIOLIB_IRQCHIP
292		− help
293		− Say yes here to support GPIO interface on ST-Ericsson U300.
294		− The names of the two IP block variants supported are
295		− COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
296		− ports of 8 GPIO pins each.
297		−
298	274	config PINCTRL_MAX77620
299	275	tristate "MAX77620/MAX20024 Pincontrol support"
300	276	depends on MFD_MAX77620 && OF
@@ -417,7 +393,6 @@ source "drivers/pinctrl/ti/Kconfig" · 116 unmodified lines
417	393	source "drivers/pinctrl/uniphier/Kconfig"
418	394	source "drivers/pinctrl/vt8500/Kconfig"
419	395	source "drivers/pinctrl/mediatek/Kconfig"
420		−source "drivers/pinctrl/zte/Kconfig"
421	396	source "drivers/pinctrl/meson/Kconfig"
422	397	source "drivers/pinctrl/cirrus/Kconfig"
423	398	source "drivers/pinctrl/visconti/Kconfig"

drivers/pinctrl/Makefile+0−4

@@ -31,11 +31,8 @@ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o · 30 unmodified lines
31	31	obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
32	32	obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
33	33	obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
34		−obj-$(CONFIG_PINCTRL_SIRF) += sirf/
35	34	obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
36	35	obj-$(CONFIG_ARCH_TEGRA) += tegra/
37		−obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
38		−obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
39	36	obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
40	37	obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
41	38	obj-$(CONFIG_PINCTRL_LPC18XX) += pinctrl-lpc18xx.o
@@ -71,6 +68,5 @@ obj-y += ti/ · 29 unmodified lines
71	68	obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
72	69	obj-$(CONFIG_ARCH_VT8500) += vt8500/
73	70	obj-y += mediatek/
74		−obj-$(CONFIG_PINCTRL_ZX) += zte/
75	71	obj-y += cirrus/
76	72	obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/

drivers/pinctrl/actions/Kconfig+3−0

@@ -12,18 +12,21 @@ config PINCTRL_OWL · 11 unmodified lines
12	12
13	13	config PINCTRL_S500
14	14	bool "Actions Semi S500 pinctrl driver"
	15	+ depends on ARM \|\| COMPILE_TEST
15	16	depends on PINCTRL_OWL
16	17	help
17	18	Say Y here to enable Actions Semi S500 pinctrl driver
18	19
19	20	config PINCTRL_S700
20	21	bool "Actions Semi S700 pinctrl driver"
	22	+ depends on ARM64 \|\| COMPILE_TEST
21	23	depends on PINCTRL_OWL
22	24	help
23	25	Say Y here to enable Actions Semi S700 pinctrl driver
24	26
25	27	config PINCTRL_S900
26	28	bool "Actions Semi S900 pinctrl driver"
	29	+ depends on ARM64 \|\| COMPILE_TEST
27	30	depends on PINCTRL_OWL
28	31	help
29	32	Say Y here to enable Actions Semi S900 pinctrl driver

drivers/pinctrl/actions/pinctrl-owl.c+0−1

@@ -444,7 +444,6 @@ static int owl_group_config_get(struct pinctrl_dev *pctrldev, · 443 unmodified lines
444	444	*config = pinconf_to_config_packed(param, arg);
445	445
446	446	return ret;
447		−
448	447	}
449	448
450	449	static int owl_group_config_set(struct pinctrl_dev *pctrldev,

drivers/pinctrl/bcm/pinctrl-ns2-mux.c+1−1

@@ -853,7 +853,7 @@ static int ns2_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, · 852 unmodified lines
853	853	switch (param) {
854	854	case PIN_CONFIG_BIAS_DISABLE:
855	855	ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);
856		− if ((pull_up == false) && (pull_down == false))
	856	+ if (!pull_up && !pull_down)
857	857	return 0;
858	858	else
859	859	return -EINVAL;

drivers/pinctrl/core.c+0−1

@@ -2117,7 +2117,6 @@ struct pinctrl_dev pinctrl_register(struct pinctrl_desc pctldesc, · 2116 unmodified lines
2117	2117	return ERR_PTR(error);
2118	2118
2119	2119	return pctldev;
2120		−
2121	2120	}
2122	2121	EXPORT_SYMBOL_GPL(pinctrl_register);
2123	2122

drivers/pinctrl/freescale/pinctrl-imx1-core.c+0−1

@@ -290,7 +290,6 @@ static const struct pinctrl_ops imx1_pctrl_ops = { · 289 unmodified lines
290	290	.pin_dbg_show = imx1_pin_dbg_show,
291	291	.dt_node_to_map = imx1_dt_node_to_map,
292	292	.dt_free_map = imx1_dt_free_map,
293		−
294	293	};
295	294
296	295	static int imx1_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,

drivers/pinctrl/intel/pinctrl-intel.c+83−34

@@ -29,6 +29,16 @@ · 28 unmodified lines
29	29	#define REVID_SHIFT 16
30	30	#define REVID_MASK GENMASK(31, 16)
31	31
	32	+#define CAPLIST 0x004
	33	+#define CAPLIST_ID_SHIFT 16
	34	+#define CAPLIST_ID_MASK GENMASK(23, 16)
	35	+#define CAPLIST_ID_GPIO_HW_INFO 1
	36	+#define CAPLIST_ID_PWM 2
	37	+#define CAPLIST_ID_BLINK 3
	38	+#define CAPLIST_ID_EXP 4
	39	+#define CAPLIST_NEXT_SHIFT 0
	40	+#define CAPLIST_NEXT_MASK GENMASK(15, 0)
	41	+
32	42	#define PADBAR 0x00c
33	43
34	44	#define PADOWN_BITS 4
@@ -1321,34 +1331,19 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) · 1286 unmodified lines
1321	1331	return 0;
1322	1332	}
1323	1333
1324		−static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
1325		− struct intel_community *community)
	1334	+static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl,
	1335	+ struct intel_community *community)
1326	1336	{
1327	1337	struct intel_padgroup *gpps;
1328		− unsigned int npins = community->npins;
1329	1338	unsigned int padown_num = 0;
1330		− size_t ngpps, i;
1331		−
1332		− if (community->gpps)
1333		− ngpps = community->ngpps;
1334		− else
1335		− ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
	1339	+ size_t i, ngpps = community->ngpps;
1336	1340
1337	1341	gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1338	1342	if (!gpps)
1339	1343	return -ENOMEM;
1340	1344
1341	1345	for (i = 0; i < ngpps; i++) {
1342		− if (community->gpps) {
1343		− gpps[i] = community->gpps[i];
1344		− } else {
1345		− unsigned int gpp_size = community->gpp_size;
1346		−
1347		− gpps[i].reg_num = i;
1348		− gpps[i].base = community->pin_base + i * gpp_size;
1349		− gpps[i].size = min(gpp_size, npins);
1350		− npins -= gpps[i].size;
1351		− }
	1346	+ gpps[i] = community->gpps[i];
1352	1347
1353	1348	if (gpps[i].size > 32)
1354	1349	return -EINVAL;
@@ -1366,6 +1361,38 @@ static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl, · 11 unmodified lines
1366	1361	break;
1367	1362	}
1368	1363
	1364	+ gpps[i].padown_num = padown_num;
	1365	+ padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
	1366	+ }
	1367	+
	1368	+ community->gpps = gpps;
	1369	+
	1370	+ return 0;
	1371	+}
	1372	+
	1373	+static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl,
	1374	+ struct intel_community *community)
	1375	+{
	1376	+ struct intel_padgroup *gpps;
	1377	+ unsigned int npins = community->npins;
	1378	+ unsigned int padown_num = 0;
	1379	+ size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size);
	1380	+
	1381	+ if (community->gpp_size > 32)
	1382	+ return -EINVAL;
	1383	+
	1384	+ gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
	1385	+ if (!gpps)
	1386	+ return -ENOMEM;
	1387	+
	1388	+ for (i = 0; i < ngpps; i++) {
	1389	+ unsigned int gpp_size = community->gpp_size;
	1390	+
	1391	+ gpps[i].reg_num = i;
	1392	+ gpps[i].base = community->pin_base + i * gpp_size;
	1393	+ gpps[i].size = min(gpp_size, npins);
	1394	+ npins -= gpps[i].size;
	1395	+
1369	1396	gpps[i].padown_num = padown_num;
1370	1397
1371	1398	/*
@@ -1455,7 +1482,8 @@ static int intel_pinctrl_probe(struct platform_device *pdev, · 83 unmodified lines
1455	1482	for (i = 0; i < pctrl->ncommunities; i++) {
1456	1483	struct intel_community *community = &pctrl->communities[i];
1457	1484	void __iomem *regs;
1458		− u32 padbar;
	1485	+ u32 offset;
	1486	+ u32 value;
1459	1487
1460	1488	*community = pctrl->soc->communities[i];
1461	1489
@@ -1463,27 +1491,48 @@ static int intel_pinctrl_probe(struct platform_device *pdev, · 1 unmodified line
1463	1491	if (IS_ERR(regs))
1464	1492	return PTR_ERR(regs);
1465	1493
1466		− /*
1467		− * Determine community features based on the revision if
1468		− * not specified already.
1469		− */
1470		− if (!community->features) {
1471		− u32 rev;
	1494	+ /* Determine community features based on the revision */
	1495	+ value = readl(regs + REVID);
	1496	+ if (((value & REVID_MASK) >> REVID_SHIFT) >= 0x94) {
	1497	+ community->features \|= PINCTRL_FEATURE_DEBOUNCE;
	1498	+ community->features \|= PINCTRL_FEATURE_1K_PD;
	1499	+ }
1472	1500
1473		− rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1474		− if (rev >= 0x94) {
1475		− community->features \|= PINCTRL_FEATURE_DEBOUNCE;
1476		− community->features \|= PINCTRL_FEATURE_1K_PD;
	1501	+ /* Determine community features based on the capabilities */
	1502	+ offset = CAPLIST;
	1503	+ do {
	1504	+ value = readl(regs + offset);
	1505	+ switch ((value & CAPLIST_ID_MASK) >> CAPLIST_ID_SHIFT) {
	1506	+ case CAPLIST_ID_GPIO_HW_INFO:
	1507	+ community->features \|= PINCTRL_FEATURE_GPIO_HW_INFO;
	1508	+ break;
	1509	+ case CAPLIST_ID_PWM:
	1510	+ community->features \|= PINCTRL_FEATURE_PWM;
	1511	+ break;
	1512	+ case CAPLIST_ID_BLINK:
	1513	+ community->features \|= PINCTRL_FEATURE_BLINK;
	1514	+ break;
	1515	+ case CAPLIST_ID_EXP:
	1516	+ community->features \|= PINCTRL_FEATURE_EXP;
	1517	+ break;
	1518	+ default:
	1519	+ break;
1477	1520	}
1478		− }
	1521	+ offset = (value & CAPLIST_NEXT_MASK) >> CAPLIST_NEXT_SHIFT;
	1522	+ } while (offset);
	1523	+
	1524	+ dev_dbg(&pdev->dev, "Community%d features: %#08x\n", i, community->features);
1479	1525
1480	1526	/* Read offset of the pad configuration registers */
1481		− padbar = readl(regs + PADBAR);
	1527	+ offset = readl(regs + PADBAR);
1482	1528
1483	1529	community->regs = regs;
1484		− community->pad_regs = regs + padbar;
	1530	+ community->pad_regs = regs + offset;
1485	1531
1486		− ret = intel_pinctrl_add_padgroups(pctrl, community);
	1532	+ if (community->gpps)
	1533	+ ret = intel_pinctrl_add_padgroups_by_gpps(pctrl, community);
	1534	+ else
	1535	+ ret = intel_pinctrl_add_padgroups_by_size(pctrl, community);
1487	1536	if (ret)
1488	1537	return ret;
1489	1538	}

drivers/pinctrl/intel/pinctrl-intel.h+4−0

@@ -143,6 +143,10 @@ struct intel_community { · 142 unmodified lines
143	143	/* Additional features supported by the hardware */
144	144	#define PINCTRL_FEATURE_DEBOUNCE BIT(0)
145	145	#define PINCTRL_FEATURE_1K_PD BIT(1)
	146	+#define PINCTRL_FEATURE_GPIO_HW_INFO BIT(2)
	147	+#define PINCTRL_FEATURE_PWM BIT(3)
	148	+#define PINCTRL_FEATURE_BLINK BIT(4)
	149	+#define PINCTRL_FEATURE_EXP BIT(5)
146	150
147	151	/**
148	152	* PIN_GROUP - Declare a pin group

drivers/pinctrl/intel/pinctrl-tigerlake.c+1−0

@@ -748,6 +748,7 @@ static const struct intel_pinctrl_soc_data tglh_soc_data = { · 747 unmodified lines
748	748	static const struct acpi_device_id tgl_pinctrl_acpi_match[] = {
749	749	{ "INT34C5", (kernel_ulong_t)&tgllp_soc_data },
750	750	{ "INT34C6", (kernel_ulong_t)&tglh_soc_data },
	751	+ { "INTC1055", (kernel_ulong_t)&tgllp_soc_data },
751	752	{ }
752	753	};
753	754	MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match);

drivers/pinctrl/mediatek/mtk-eint.c+11−2

@@ -157,6 +157,7 @@ static void mtk_eint_ack(struct irq_data *d) · 156 unmodified lines
157	157	static int mtk_eint_set_type(struct irq_data *d, unsigned int type)
158	158	{
159	159	struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
	160	+ bool masked;
160	161	u32 mask = BIT(d->hwirq & 0x1f);
161	162	void __iomem *reg;
162	163
@@ -173,6 +174,13 @@ static int mtk_eint_set_type(struct irq_data *d, unsigned int type) · 10 unmodified lines
173	174	else
174	175	eint->dual_edge[d->hwirq] = 0;
175	176
	177	+ if (!mtk_eint_get_mask(eint, d->hwirq)) {
	178	+ mtk_eint_mask(d);
	179	+ masked = false;
	180	+ } else {
	181	+ masked = true;
	182	+ }
	183	+
176	184	if (type & (IRQ_TYPE_LEVEL_LOW \| IRQ_TYPE_EDGE_FALLING)) {
177	185	reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_clr);
178	186	writel(mask, reg);
@@ -189,8 +197,9 @@ static int mtk_eint_set_type(struct irq_data *d, unsigned int type) · 10 unmodified lines
189	197	writel(mask, reg);
190	198	}
191	199
192		− if (eint->dual_edge[d->hwirq])
193		− mtk_eint_flip_edge(eint, d->hwirq);
	200	+ mtk_eint_ack(d);
	201	+ if (!masked)
	202	+ mtk_eint_unmask(d);
194	203
195	204	return 0;
196	205	}

drivers/pinctrl/mediatek/pinctrl-moore.c+2−2

@@ -514,8 +514,8 @@ static int mtk_build_gpiochip(struct mtk_pinctrl hw, struct device_node np) · 513 unmodified lines
514	514	chip->direction_output = mtk_gpio_direction_output;
515	515	chip->get = mtk_gpio_get;
516	516	chip->set = mtk_gpio_set;
517		− chip->to_irq = mtk_gpio_to_irq,
518		− chip->set_config = mtk_gpio_set_config,
	517	+ chip->to_irq = mtk_gpio_to_irq;
	518	+ chip->set_config = mtk_gpio_set_config;
519	519	chip->base = -1;
520	520	chip->ngpio = hw->soc->npins;
521	521	chip->of_node = np;

drivers/pinctrl/mediatek/pinctrl-paris.c+2−2

@@ -891,8 +891,8 @@ static int mtk_build_gpiochip(struct mtk_pinctrl hw, struct device_node np) · 890 unmodified lines
891	891	chip->direction_output = mtk_gpio_direction_output;
892	892	chip->get = mtk_gpio_get;
893	893	chip->set = mtk_gpio_set;
894		− chip->to_irq = mtk_gpio_to_irq,
895		− chip->set_config = mtk_gpio_set_config,
	894	+ chip->to_irq = mtk_gpio_to_irq;
	895	+ chip->set_config = mtk_gpio_set_config;
896	896	chip->base = -1;
897	897	chip->ngpio = hw->soc->npins;
898	898	chip->of_node = np;

drivers/pinctrl/mvebu/pinctrl-armada-37xx.c+0−1

@@ -188,7 +188,6 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = { · 187 unmodified lines
188	188	PIN_GRP_GPIO_2("led1_od", 12, 1, BIT(21), BIT(21), 0, "led"),
189	189	PIN_GRP_GPIO_2("led2_od", 13, 1, BIT(22), BIT(22), 0, "led"),
190	190	PIN_GRP_GPIO_2("led3_od", 14, 1, BIT(23), BIT(23), 0, "led"),
191		−
192	191	};
193	192
194	193	static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c+1−1

@@ -923,7 +923,7 @@ struct npcm7xx_pincfg { · 922 unmodified lines
923	923	};
924	924
925	925	static const struct npcm7xx_pincfg pincfg[] = {
926		− /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FLAGS */
	926	+ /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FLAGS */
927	927	NPCM7XX_PINCFG(0, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0),
928	928	NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DS(8, 12)),
929	929	NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DS(8, 12)),

drivers/pinctrl/pinctrl-at91-pio4.c+84−53

@@ -36,6 +36,7 @@ · 35 unmodified lines
36	36	#define ATMEL_PIO_DIR_MASK BIT(8)
37	37	#define ATMEL_PIO_PUEN_MASK BIT(9)
38	38	#define ATMEL_PIO_PDEN_MASK BIT(10)
	39	+#define ATMEL_PIO_SR_MASK BIT(11)
39	40	#define ATMEL_PIO_IFEN_MASK BIT(12)
40	41	#define ATMEL_PIO_IFSCEN_MASK BIT(13)
41	42	#define ATMEL_PIO_OPD_MASK BIT(14)
@@ -76,10 +77,12 @@ · 34 unmodified lines
76	77	* @nbanks: number of PIO banks
77	78	* @last_bank_count: number of lines in the last bank (can be less than
78	79	* the rest of the banks).
	80	+ * @slew_rate_support: slew rate support
79	81	*/
80	82	struct atmel_pioctrl_data {
81		− unsigned nbanks;
82		− unsigned last_bank_count;
	83	+ unsigned int nbanks;
	84	+ unsigned int last_bank_count;
	85	+ unsigned int slew_rate_support;
83	86	};
84	87
85	88	struct atmel_group {
@@ -88,11 +91,11 @@ struct atmel_group { · 2 unmodified lines
88	91	};
89	92
90	93	struct atmel_pin {
91		− unsigned pin_id;
92		− unsigned mux;
93		− unsigned ioset;
94		− unsigned bank;
95		− unsigned line;
	94	+ unsigned int pin_id;
	95	+ unsigned int mux;
	96	+ unsigned int ioset;
	97	+ unsigned int bank;
	98	+ unsigned int line;
96	99	const char *device;
97	100	};
98	101
@@ -117,20 +120,21 @@ struct atmel_pin { · 18 unmodified lines
117	120	* @pm_suspend_backup: backup/restore register values on suspend/resume
118	121	* @dev: device entry for the Atmel PIO controller.
119	122	* @node: node of the Atmel PIO controller.
	123	+ * @slew_rate_support: slew rate support
120	124	*/
121	125	struct atmel_pioctrl {
122	126	void __iomem *reg_base;
123	127	struct clk *clk;
124		− unsigned nbanks;
	128	+ unsigned int nbanks;
125	129	struct pinctrl_dev *pinctrl_dev;
126	130	struct atmel_group *groups;
127	131	const char * const *group_names;
128	132	struct atmel_pin **pins;
129		− unsigned npins;
	133	+ unsigned int npins;
130	134	struct gpio_chip *gpio_chip;
131	135	struct irq_domain *irq_domain;
132	136	int *irqs;
133		− unsigned *pm_wakeup_sources;
	137	+ unsigned int *pm_wakeup_sources;
134	138	struct {
135	139	u32 imr;
136	140	u32 odsr;
@@ -138,6 +142,7 @@ struct atmel_pioctrl { · 1 unmodified line
138	142	} *pm_suspend_backup;
139	143	struct device *dev;
140	144	struct device_node *node;
	145	+ unsigned int slew_rate_support;
141	146	};
142	147
143	148	static const char * const atmel_functions[] = {
@@ -172,11 +177,11 @@ static void atmel_gpio_irq_ack(struct irq_data *d) · 28 unmodified lines
172	177	*/
173	178	}
174	179
175		−static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type)
	180	+static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned int type)
176	181	{
177	182	struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
178	183	struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
179		− unsigned reg;
	184	+ unsigned int reg;
180	185
181	186	atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
182	187	BIT(pin->line));
@@ -263,7 +268,7 @@ static struct irq_chip atmel_gpio_irq_chip = { · 80 unmodified lines
263	268	.irq_set_wake = atmel_gpio_irq_set_wake,
264	269	};
265	270
266		−static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
	271	+static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
267	272	{
268	273	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
269	274
@@ -311,11 +316,12 @@ static void atmel_gpio_irq_handler(struct irq_desc *desc) · 41 unmodified lines
311	316	chained_irq_exit(chip, desc);
312	317	}
313	318
314		−static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	319	+static int atmel_gpio_direction_input(struct gpio_chip *chip,
	320	+ unsigned int offset)
315	321	{
316	322	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
317	323	struct atmel_pin *pin = atmel_pioctrl->pins[offset];
318		− unsigned reg;
	324	+ unsigned int reg;
319	325
320	326	atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
321	327	BIT(pin->line));
@@ -326,11 +332,11 @@ static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) · 4 unmodified lines
326	332	return 0;
327	333	}
328	334
329		−static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset)
	335	+static int atmel_gpio_get(struct gpio_chip *chip, unsigned int offset)
330	336	{
331	337	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
332	338	struct atmel_pin *pin = atmel_pioctrl->pins[offset];
333		− unsigned reg;
	339	+ unsigned int reg;
334	340
335	341	reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);
336	342
@@ -364,12 +370,13 @@ static int atmel_gpio_get_multiple(struct gpio_chip chip, unsigned long mask, · 27 unmodified lines
364	370	return 0;
365	371	}
366	372
367		−static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
	373	+static int atmel_gpio_direction_output(struct gpio_chip *chip,
	374	+ unsigned int offset,
368	375	int value)
369	376	{
370	377	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
371	378	struct atmel_pin *pin = atmel_pioctrl->pins[offset];
372		− unsigned reg;
	379	+ unsigned int reg;
373	380
374	381	atmel_gpio_write(atmel_pioctrl, pin->bank,
375	382	value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
@@ -384,7 +391,7 @@ static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, · 8 unmodified lines
384	391	return 0;
385	392	}
386	393
387		−static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
	394	+static void atmel_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
388	395	{
389	396	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
390	397	struct atmel_pin *pin = atmel_pioctrl->pins[offset];
@@ -440,11 +447,11 @@ static struct gpio_chip atmel_gpio_chip = { · 49 unmodified lines
440	447
441	448	/* --- PINCTRL --- */
442	449	static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,
443		− unsigned pin_id)
	450	+ unsigned int pin_id)
444	451	{
445	452	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
446		− unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
447		− unsigned line = atmel_pioctrl->pins[pin_id]->line;
	453	+ unsigned int bank = atmel_pioctrl->pins[pin_id]->bank;
	454	+ unsigned int line = atmel_pioctrl->pins[pin_id]->line;
448	455	void __iomem *addr = atmel_pioctrl->reg_base
449	456	+ bank * ATMEL_PIO_BANK_OFFSET;
450	457
@@ -456,11 +463,11 @@ static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev, · 5 unmodified lines
456	463	}
457	464
458	465	static void atmel_pin_config_write(struct pinctrl_dev *pctldev,
459		− unsigned pin_id, u32 conf)
	466	+ unsigned int pin_id, u32 conf)
460	467	{
461	468	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
462		− unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
463		− unsigned line = atmel_pioctrl->pins[pin_id]->line;
	469	+ unsigned int bank = atmel_pioctrl->pins[pin_id]->bank;
	470	+ unsigned int line = atmel_pioctrl->pins[pin_id]->line;
464	471	void __iomem *addr = atmel_pioctrl->reg_base
465	472	+ bank * ATMEL_PIO_BANK_OFFSET;
466	473
@@ -478,7 +485,7 @@ static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev) · 11 unmodified lines
478	485	}
479	486
480	487	static const char atmel_pctl_get_group_name(struct pinctrl_dev pctldev,
481		− unsigned selector)
	488	+ unsigned int selector)
482	489	{
483	490	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
484	491
@@ -486,19 +493,20 @@ static const char atmel_pctl_get_group_name(struct pinctrl_dev pctldev, · 1 unmodified line
486	493	}
487	494
488	495	static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,
489		− unsigned selector, const unsigned **pins,
490		− unsigned *num_pins)
	496	+ unsigned int selector,
	497	+ const unsigned int **pins,
	498	+ unsigned int *num_pins)
491	499	{
492	500	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
493	501
494		− pins = (unsigned )&atmel_pioctrl->groups[selector].pin;
	502	+ pins = (unsigned int )&atmel_pioctrl->groups[selector].pin;
495	503	*num_pins = 1;
496	504
497	505	return 0;
498	506	}
499	507
500	508	static struct atmel_group *
501		−atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin)
	509	+atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned int pin)
502	510	{
503	511	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
504	512	int i;
@@ -519,7 +527,7 @@ static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev, · 14 unmodified lines
519	527	const char **func_name)
520	528	{
521	529	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
522		− unsigned pin_id, func_id;
	530	+ unsigned int pin_id, func_id;
523	531	struct atmel_group *grp;
524	532
525	533	pin_id = ATMEL_GET_PIN_NO(pinfunc);
@@ -549,10 +557,10 @@ static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev, · 23 unmodified lines
549	557	static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
550	558	struct device_node *np,
551	559	struct pinctrl_map **map,
552		− unsigned *reserved_maps,
553		− unsigned *num_maps)
	560	+ unsigned int *reserved_maps,
	561	+ unsigned int *num_maps)
554	562	{
555		− unsigned num_pins, num_configs, reserve;
	563	+ unsigned int num_pins, num_configs, reserve;
556	564	unsigned long *configs;
557	565	struct property *pins;
558	566	u32 pinfunc;
@@ -623,10 +631,10 @@ exit: · 64 unmodified lines
623	631	static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
624	632	struct device_node *np_config,
625	633	struct pinctrl_map **map,
626		− unsigned *num_maps)
	634	+ unsigned int *num_maps)
627	635	{
628	636	struct device_node *np;
629		− unsigned reserved_maps;
	637	+ unsigned int reserved_maps;
630	638	int ret;
631	639
632	640	*map = NULL;
@@ -674,13 +682,13 @@ static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev) · 41 unmodified lines
674	682	}
675	683
676	684	static const char atmel_pmx_get_function_name(struct pinctrl_dev pctldev,
677		− unsigned selector)
	685	+ unsigned int selector)
678	686	{
679	687	return atmel_functions[selector];
680	688	}
681	689
682	690	static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,
683		− unsigned selector,
	691	+ unsigned int selector,
684	692	const char * const **groups,
685	693	unsigned * const num_groups)
686	694	{
@@ -693,11 +701,11 @@ static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev, · 6 unmodified lines
693	701	}
694	702
695	703	static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,
696		− unsigned function,
697		− unsigned group)
	704	+ unsigned int function,
	705	+ unsigned int group)
698	706	{
699	707	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
700		− unsigned pin;
	708	+ unsigned int pin;
701	709	u32 conf;
702	710
703	711	dev_dbg(pctldev->dev, "enable function %s group %s\n",
@@ -721,13 +729,13 @@ static const struct pinmux_ops atmel_pmxops = { · 17 unmodified lines
721	729	};
722	730
723	731	static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
724		− unsigned group,
	732	+ unsigned int group,
725	733	unsigned long *config)
726	734	{
727	735	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
728		− unsigned param = pinconf_to_config_param(*config), arg = 0;
	736	+ unsigned int param = pinconf_to_config_param(*config), arg = 0;
729	737	struct atmel_group *grp = atmel_pioctrl->groups + group;
730		− unsigned pin_id = grp->pin;
	738	+ unsigned int pin_id = grp->pin;
731	739	u32 res;
732	740
733	741	res = atmel_pin_config_read(pctldev, pin_id);
@@ -760,6 +768,13 @@ static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev, · 26 unmodified lines
760	768	return -EINVAL;
761	769	arg = 1;
762	770	break;
	771	+ case PIN_CONFIG_SLEW_RATE:
	772	+ if (!atmel_pioctrl->slew_rate_support)
	773	+ return -EOPNOTSUPP;
	774	+ if (!(res & ATMEL_PIO_SR_MASK))
	775	+ return -EINVAL;
	776	+ arg = 1;
	777	+ break;
763	778	case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
764	779	if (!(res & ATMEL_PIO_DRVSTR_MASK))
765	780	return -EINVAL;
@@ -774,25 +789,29 @@ static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev, · 8 unmodified lines
774	789	}
775	790
776	791	static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
777		− unsigned group,
	792	+ unsigned int group,
778	793	unsigned long *configs,
779		− unsigned num_configs)
	794	+ unsigned int num_configs)
780	795	{
781	796	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
782	797	struct atmel_group *grp = atmel_pioctrl->groups + group;
783		− unsigned bank, pin, pin_id = grp->pin;
	798	+ unsigned int bank, pin, pin_id = grp->pin;
784	799	u32 mask, conf = 0;
785	800	int i;
786	801
787	802	conf = atmel_pin_config_read(pctldev, pin_id);
788	803
789	804	for (i = 0; i < num_configs; i++) {
790		− unsigned param = pinconf_to_config_param(configs[i]);
791		− unsigned arg = pinconf_to_config_argument(configs[i]);
	805	+ unsigned int param = pinconf_to_config_param(configs[i]);
	806	+ unsigned int arg = pinconf_to_config_argument(configs[i]);
792	807
793	808	dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
794	809	__func__, pin_id, configs[i]);
795	810
	811	+ /* Keep slew rate enabled by default. */
	812	+ if (atmel_pioctrl->slew_rate_support)
	813	+ conf \|= ATMEL_PIO_SR_MASK;
	814	+
796	815	switch (param) {
797	816	case PIN_CONFIG_BIAS_DISABLE:
798	817	conf &= (~ATMEL_PIO_PUEN_MASK);
@@ -850,6 +869,13 @@ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, · 51 unmodified lines
850	869	ATMEL_PIO_SODR);
851	870	}
852	871	break;
	872	+ case PIN_CONFIG_SLEW_RATE:
	873	+ if (!atmel_pioctrl->slew_rate_support)
	874	+ break;
	875	+ /* And remove it if explicitly requested. */
	876	+ if (arg == 0)
	877	+ conf &= ~ATMEL_PIO_SR_MASK;
	878	+ break;
853	879	case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
854	880	switch (arg) {
855	881	case ATMEL_PIO_DRVSTR_LO:
@@ -877,7 +903,8 @@ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, · 21 unmodified lines
877	903	}
878	904
879	905	static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
880		− struct seq_file *s, unsigned pin_id)
	906	+ struct seq_file *s,
	907	+ unsigned int pin_id)
881	908	{
882	909	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
883	910	u32 conf;
@@ -901,6 +928,8 @@ static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev, · 17 unmodified lines
901	928	seq_printf(s, "%s ", "open-drain");
902	929	if (conf & ATMEL_PIO_SCHMITT_MASK)
903	930	seq_printf(s, "%s ", "schmitt");
	931	+ if (atmel_pioctrl->slew_rate_support && (conf & ATMEL_PIO_SR_MASK))
	932	+ seq_printf(s, "%s ", "slew-rate");
904	933	if (conf & ATMEL_PIO_DRVSTR_MASK) {
905	934	switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) {
906	935	case ATMEL_PIO_DRVSTR_ME:
@@ -994,6 +1023,7 @@ static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = { · 87 unmodified lines
994	1023	static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
995	1024	.nbanks = 5,
996	1025	.last_bank_count = 8, /* sama7g5 has only PE0 to PE7 */
	1026	+ .slew_rate_support = 1,
997	1027	};
998	1028
999	1029	static const struct of_device_id atmel_pctrl_of_match[] = {
@@ -1039,6 +1069,7 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) · 39 unmodified lines
1039	1069	atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK;
1040	1070	atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count;
1041	1071	}
	1072	+ atmel_pioctrl->slew_rate_support = atmel_pioctrl_data->slew_rate_support;
1042	1073
1043	1074	atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
1044	1075	if (IS_ERR(atmel_pioctrl->reg_base))
@@ -1081,8 +1112,8 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) · 36 unmodified lines
1081	1112	return -ENOMEM;
1082	1113	for (i = 0 ; i < atmel_pioctrl->npins; i++) {
1083	1114	struct atmel_group *group = atmel_pioctrl->groups + i;
1084		− unsigned bank = ATMEL_PIO_BANK(i);
1085		− unsigned line = ATMEL_PIO_LINE(i);
	1115	+ unsigned int bank = ATMEL_PIO_BANK(i);
	1116	+ unsigned int line = ATMEL_PIO_LINE(i);
1086	1117
1087	1118	atmel_pioctrl->pins[i] = devm_kzalloc(dev,
1088	1119	sizeof(**atmel_pioctrl->pins), GFP_KERNEL);

drivers/pinctrl/pinctrl-at91.c+1−2

@@ -733,7 +733,6 @@ static const struct at91_pinctrl_mux_ops sam9x60_ops = { · 732 unmodified lines
733	733	.get_slewrate = at91_mux_sam9x60_get_slewrate,
734	734	.set_slewrate = at91_mux_sam9x60_set_slewrate,
735	735	.irq_type = alt_gpio_irq_type,
736		−
737	736	};
738	737
739	738	static struct at91_pinctrl_mux_ops sama5d3_ops = {
@@ -1742,7 +1741,7 @@ static int at91_gpio_of_irq_setup(struct platform_device *pdev, · 1002 unmodified lines
1742	1741	gpio_irqchip->irq_disable = gpio_irq_mask;
1743	1742	gpio_irqchip->irq_mask = gpio_irq_mask;
1744	1743	gpio_irqchip->irq_unmask = gpio_irq_unmask;
1745		− gpio_irqchip->irq_set_wake = gpio_irq_set_wake,
	1744	+ gpio_irqchip->irq_set_wake = gpio_irq_set_wake;
1746	1745	gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type;
1747	1746
1748	1747	/* Disable irqs of this PIO controller */

drivers/pinctrl/pinctrl-coh901.c+0−774

@@ -1,774 +0,0 @@
1		−// SPDX-License-Identifier: GPL-2.0-only
2		−/*
3		− * U300 GPIO module.
4		− *
5		− * Copyright (C) 2007-2012 ST-Ericsson AB
6		− * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
7		− * Author: Linus Walleij <linus.walleij@linaro.org>
8		− * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
9		− */
10		−#include <linux/module.h>
11		−#include <linux/interrupt.h>
12		−#include <linux/delay.h>
13		−#include <linux/errno.h>
14		−#include <linux/io.h>
15		−#include <linux/clk.h>
16		−#include <linux/err.h>
17		−#include <linux/platform_device.h>
18		−#include <linux/gpio/driver.h>
19		−#include <linux/slab.h>
20		−#include <linux/pinctrl/consumer.h>
21		−#include <linux/pinctrl/pinconf-generic.h>
22		−#include "pinctrl-coh901.h"
23		−
24		−#define U300_GPIO_PORT_STRIDE (0x30)
25		−/*
26		− * Control Register 32bit (R/W)
27		− * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
28		− * gives the number of GPIO pins.
29		− * bit 8-2 (mask 0x000001FC) contains the core version ID.
30		− */
31		−#define U300_GPIO_CR (0x00)
32		−#define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL)
33		−#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
34		−#define U300_GPIO_PXPDIR (0x04)
35		−#define U300_GPIO_PXPDOR (0x08)
36		−#define U300_GPIO_PXPCR (0x0C)
37		−#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
38		−#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
39		−#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
40		−#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
41		−#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
42		−#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
43		−#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
44		−#define U300_GPIO_PXPER (0x10)
45		−#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
46		−#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
47		−#define U300_GPIO_PXIEV (0x14)
48		−#define U300_GPIO_PXIEN (0x18)
49		−#define U300_GPIO_PXIFR (0x1C)
50		−#define U300_GPIO_PXICR (0x20)
51		−#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
52		−#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
53		−#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
54		−#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
55		−
56		−/* 8 bits per port, no version has more than 7 ports */
57		−#define U300_GPIO_NUM_PORTS 7
58		−#define U300_GPIO_PINS_PER_PORT 8
59		−#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS)
60		−
61		−struct u300_gpio_port {
62		− struct u300_gpio *gpio;
63		− char name[8];
64		− int irq;
65		− int number;
66		− u8 toggle_edge_mode;
67		−};
68		−
69		−struct u300_gpio {
70		− struct gpio_chip chip;
71		− struct u300_gpio_port ports[U300_GPIO_NUM_PORTS];
72		− struct clk *clk;
73		− void __iomem *base;
74		− struct device *dev;
75		− u32 stride;
76		− /* Register offsets */
77		− u32 pcr;
78		− u32 dor;
79		− u32 dir;
80		− u32 per;
81		− u32 icr;
82		− u32 ien;
83		− u32 iev;
84		−};
85		−
86		−/*
87		− * Macro to expand to read a specific register found in the "gpio"
88		− * struct. It requires the struct u300_gpio *gpio variable to exist in
89		− * its context. It calculates the port offset from the given pin
90		− * offset, muliplies by the port stride and adds the register offset
91		− * so it provides a pointer to the desired register.
92		− */
93		−#define U300_PIN_REG(pin, reg) \
94		− (gpio->base + (pin >> 3) * gpio->stride + gpio->reg)
95		−
96		−/*
97		− * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO
98		− * register.
99		− */
100		−#define U300_PIN_BIT(pin) \
101		− (1 << (pin & 0x07))
102		−
103		−struct u300_gpio_confdata {
104		− u16 bias_mode;
105		− bool output;
106		− int outval;
107		−};
108		−
109		−#define U300_FLOATING_INPUT { \
110		− .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
111		− .output = false, \
112		−}
113		−
114		−#define U300_PULL_UP_INPUT { \
115		− .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \
116		− .output = false, \
117		−}
118		−
119		−#define U300_OUTPUT_LOW { \
120		− .output = true, \
121		− .outval = 0, \
122		−}
123		−
124		−#define U300_OUTPUT_HIGH { \
125		− .output = true, \
126		− .outval = 1, \
127		−}
128		−
129		−/* Initial configuration */
130		−static const struct u300_gpio_confdata __initconst
131		−bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
132		− /* Port 0, pins 0-7 */
133		− {
134		− U300_FLOATING_INPUT,
135		− U300_OUTPUT_HIGH,
136		− U300_FLOATING_INPUT,
137		− U300_OUTPUT_LOW,
138		− U300_OUTPUT_LOW,
139		− U300_OUTPUT_LOW,
140		− U300_OUTPUT_LOW,
141		− U300_OUTPUT_LOW,
142		− },
143		− /* Port 1, pins 0-7 */
144		− {
145		− U300_OUTPUT_LOW,
146		− U300_OUTPUT_LOW,
147		− U300_OUTPUT_LOW,
148		− U300_PULL_UP_INPUT,
149		− U300_FLOATING_INPUT,
150		− U300_OUTPUT_HIGH,
151		− U300_OUTPUT_LOW,
152		− U300_OUTPUT_LOW,
153		− },
154		− /* Port 2, pins 0-7 */
155		− {
156		− U300_FLOATING_INPUT,
157		− U300_FLOATING_INPUT,
158		− U300_FLOATING_INPUT,
159		− U300_FLOATING_INPUT,
160		− U300_OUTPUT_LOW,
161		− U300_PULL_UP_INPUT,
162		− U300_OUTPUT_LOW,
163		− U300_PULL_UP_INPUT,
164		− },
165		− /* Port 3, pins 0-7 */
166		− {
167		− U300_PULL_UP_INPUT,
168		− U300_OUTPUT_LOW,
169		− U300_FLOATING_INPUT,
170		− U300_FLOATING_INPUT,
171		− U300_FLOATING_INPUT,
172		− U300_FLOATING_INPUT,
173		− U300_FLOATING_INPUT,
174		− U300_FLOATING_INPUT,
175		− },
176		− /* Port 4, pins 0-7 */
177		− {
178		− U300_FLOATING_INPUT,
179		− U300_FLOATING_INPUT,
180		− U300_FLOATING_INPUT,
181		− U300_FLOATING_INPUT,
182		− U300_FLOATING_INPUT,
183		− U300_FLOATING_INPUT,
184		− U300_FLOATING_INPUT,
185		− U300_FLOATING_INPUT,
186		− },
187		− /* Port 5, pins 0-7 */
188		− {
189		− U300_FLOATING_INPUT,
190		− U300_FLOATING_INPUT,
191		− U300_FLOATING_INPUT,
192		− U300_FLOATING_INPUT,
193		− U300_FLOATING_INPUT,
194		− U300_FLOATING_INPUT,
195		− U300_FLOATING_INPUT,
196		− U300_FLOATING_INPUT,
197		− },
198		− /* Port 6, pind 0-7 */
199		− {
200		− U300_FLOATING_INPUT,
201		− U300_FLOATING_INPUT,
202		− U300_FLOATING_INPUT,
203		− U300_FLOATING_INPUT,
204		− U300_FLOATING_INPUT,
205		− U300_FLOATING_INPUT,
206		− U300_FLOATING_INPUT,
207		− U300_FLOATING_INPUT,
208		− }
209		−};
210		−
211		−static int u300_gpio_get(struct gpio_chip *chip, unsigned offset)
212		−{
213		− struct u300_gpio *gpio = gpiochip_get_data(chip);
214		−
215		− return !!(readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset));
216		−}
217		−
218		−static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
219		−{
220		− struct u300_gpio *gpio = gpiochip_get_data(chip);
221		− unsigned long flags;
222		− u32 val;
223		−
224		− local_irq_save(flags);
225		−
226		− val = readl(U300_PIN_REG(offset, dor));
227		− if (value)
228		− writel(val \| U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
229		− else
230		− writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
231		−
232		− local_irq_restore(flags);
233		−}
234		−
235		−static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
236		−{
237		− struct u300_gpio *gpio = gpiochip_get_data(chip);
238		− unsigned long flags;
239		− u32 val;
240		−
241		− local_irq_save(flags);
242		− val = readl(U300_PIN_REG(offset, pcr));
243		− /* Mask out this pin, note 2 bits per setting */
244		− val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
245		− writel(val, U300_PIN_REG(offset, pcr));
246		− local_irq_restore(flags);
247		− return 0;
248		−}
249		−
250		−static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
251		− int value)
252		−{
253		− struct u300_gpio *gpio = gpiochip_get_data(chip);
254		− unsigned long flags;
255		− u32 oldmode;
256		− u32 val;
257		−
258		− local_irq_save(flags);
259		− val = readl(U300_PIN_REG(offset, pcr));
260		− /*
261		− * Drive mode must be set by the special mode set function, set
262		− * push/pull mode by default if no mode has been selected.
263		− */
264		− oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK <<
265		− ((offset & 0x07) << 1));
266		− /* mode = 0 means input, else some mode is already set */
267		− if (oldmode == 0) {
268		− val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK <<
269		− ((offset & 0x07) << 1));
270		− val \|= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
271		− << ((offset & 0x07) << 1));
272		− writel(val, U300_PIN_REG(offset, pcr));
273		− }
274		− u300_gpio_set(chip, offset, value);
275		− local_irq_restore(flags);
276		− return 0;
277		−}
278		−
279		−/* Returning -EINVAL means "supported but not available" */
280		−int u300_gpio_config_get(struct gpio_chip *chip,
281		− unsigned offset,
282		− unsigned long *config)
283		−{
284		− struct u300_gpio *gpio = gpiochip_get_data(chip);
285		− enum pin_config_param param = (enum pin_config_param) *config;
286		− bool biasmode;
287		− u32 drmode;
288		−
289		− /* One bit per pin, clamp to bool range */
290		− biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset));
291		−
292		− /* Mask out the two bits for this pin and shift to bits 0,1 */
293		− drmode = readl(U300_PIN_REG(offset, pcr));
294		− drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
295		− drmode >>= ((offset & 0x07) << 1);
296		−
297		− switch (param) {
298		− case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
299		− *config = 0;
300		− if (biasmode)
301		− return 0;
302		− else
303		− return -EINVAL;
304		− break;
305		− case PIN_CONFIG_BIAS_PULL_UP:
306		− *config = 0;
307		− if (!biasmode)
308		− return 0;
309		− else
310		− return -EINVAL;
311		− break;
312		− case PIN_CONFIG_DRIVE_PUSH_PULL:
313		− *config = 0;
314		− if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL)
315		− return 0;
316		− else
317		− return -EINVAL;
318		− break;
319		− case PIN_CONFIG_DRIVE_OPEN_DRAIN:
320		− *config = 0;
321		− if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN)
322		− return 0;
323		− else
324		− return -EINVAL;
325		− break;
326		− case PIN_CONFIG_DRIVE_OPEN_SOURCE:
327		− *config = 0;
328		− if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE)
329		− return 0;
330		− else
331		− return -EINVAL;
332		− break;
333		− default:
334		− break;
335		− }
336		− return -ENOTSUPP;
337		−}
338		−
339		−int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
340		− enum pin_config_param param)
341		−{
342		− struct u300_gpio *gpio = gpiochip_get_data(chip);
343		− unsigned long flags;
344		− u32 val;
345		−
346		− local_irq_save(flags);
347		− switch (param) {
348		− case PIN_CONFIG_BIAS_DISABLE:
349		− case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
350		− val = readl(U300_PIN_REG(offset, per));
351		− writel(val \| U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
352		− break;
353		− case PIN_CONFIG_BIAS_PULL_UP:
354		− val = readl(U300_PIN_REG(offset, per));
355		− writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
356		− break;
357		− case PIN_CONFIG_DRIVE_PUSH_PULL:
358		− val = readl(U300_PIN_REG(offset, pcr));
359		− val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
360		− << ((offset & 0x07) << 1));
361		− val \|= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
362		− << ((offset & 0x07) << 1));
363		− writel(val, U300_PIN_REG(offset, pcr));
364		− break;
365		− case PIN_CONFIG_DRIVE_OPEN_DRAIN:
366		− val = readl(U300_PIN_REG(offset, pcr));
367		− val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
368		− << ((offset & 0x07) << 1));
369		− val \|= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
370		− << ((offset & 0x07) << 1));
371		− writel(val, U300_PIN_REG(offset, pcr));
372		− break;
373		− case PIN_CONFIG_DRIVE_OPEN_SOURCE:
374		− val = readl(U300_PIN_REG(offset, pcr));
375		− val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
376		− << ((offset & 0x07) << 1));
377		− val \|= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
378		− << ((offset & 0x07) << 1));
379		− writel(val, U300_PIN_REG(offset, pcr));
380		− break;
381		− default:
382		− local_irq_restore(flags);
383		− dev_err(gpio->dev, "illegal configuration requested\n");
384		− return -EINVAL;
385		− }
386		− local_irq_restore(flags);
387		− return 0;
388		−}
389		−
390		−static const struct gpio_chip u300_gpio_chip = {
391		− .label = "u300-gpio-chip",
392		− .owner = THIS_MODULE,
393		− .request = gpiochip_generic_request,
394		− .free = gpiochip_generic_free,
395		− .get = u300_gpio_get,
396		− .set = u300_gpio_set,
397		− .direction_input = u300_gpio_direction_input,
398		− .direction_output = u300_gpio_direction_output,
399		−};
400		−
401		−static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset)
402		−{
403		− u32 val;
404		−
405		− val = readl(U300_PIN_REG(offset, icr));
406		− /* Set mode depending on state */
407		− if (u300_gpio_get(&gpio->chip, offset)) {
408		− /* High now, let's trigger on falling edge next then */
409		− writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
410		− dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n",
411		− offset);
412		− } else {
413		− /* Low now, let's trigger on rising edge next then */
414		− writel(val \| U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
415		− dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n",
416		− offset);
417		− }
418		−}
419		−
420		−static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
421		−{
422		− struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
423		− struct u300_gpio *gpio = gpiochip_get_data(chip);
424		− struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3];
425		− int offset = d->hwirq;
426		− u32 val;
427		−
428		− if ((trigger & IRQF_TRIGGER_RISING) &&
429		− (trigger & IRQF_TRIGGER_FALLING)) {
430		− /*
431		− * The GPIO block can only trigger on falling OR rising edges,
432		− * not both. So we need to toggle the mode whenever the pin
433		− * goes from one state to the other with a special state flag
434		− */
435		− dev_dbg(gpio->dev,
436		− "trigger on both rising and falling edge on pin %d\n",
437		− offset);
438		− port->toggle_edge_mode \|= U300_PIN_BIT(offset);
439		− u300_toggle_trigger(gpio, offset);
440		− } else if (trigger & IRQF_TRIGGER_RISING) {
441		− dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n",
442		− offset);
443		− val = readl(U300_PIN_REG(offset, icr));
444		− writel(val \| U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
445		− port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
446		− } else if (trigger & IRQF_TRIGGER_FALLING) {
447		− dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n",
448		− offset);
449		− val = readl(U300_PIN_REG(offset, icr));
450		− writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
451		− port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
452		− }
453		−
454		− return 0;
455		−}
456		−
457		−static void u300_gpio_irq_enable(struct irq_data *d)
458		−{
459		− struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
460		− struct u300_gpio *gpio = gpiochip_get_data(chip);
461		− struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3];
462		− int offset = d->hwirq;
463		− u32 val;
464		− unsigned long flags;
465		−
466		− dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n",
467		− d->hwirq, port->name, offset);
468		− local_irq_save(flags);
469		− val = readl(U300_PIN_REG(offset, ien));
470		− writel(val \| U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
471		− local_irq_restore(flags);
472		−}
473		−
474		−static void u300_gpio_irq_disable(struct irq_data *d)
475		−{
476		− struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
477		− struct u300_gpio *gpio = gpiochip_get_data(chip);
478		− int offset = d->hwirq;
479		− u32 val;
480		− unsigned long flags;
481		−
482		− local_irq_save(flags);
483		− val = readl(U300_PIN_REG(offset, ien));
484		− writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
485		− local_irq_restore(flags);
486		−}
487		−
488		−static struct irq_chip u300_gpio_irqchip = {
489		− .name = "u300-gpio-irqchip",
490		− .irq_enable = u300_gpio_irq_enable,
491		− .irq_disable = u300_gpio_irq_disable,
492		− .irq_set_type = u300_gpio_irq_type,
493		−};
494		−
495		−static void u300_gpio_irq_handler(struct irq_desc *desc)
496		−{
497		− unsigned int irq = irq_desc_get_irq(desc);
498		− struct irq_chip *parent_chip = irq_desc_get_chip(desc);
499		− struct gpio_chip *chip = irq_desc_get_handler_data(desc);
500		− struct u300_gpio *gpio = gpiochip_get_data(chip);
501		− struct u300_gpio_port *port = &gpio->ports[irq - chip->base];
502		− int pinoffset = port->number << 3; /* get the right stride */
503		− unsigned long val;
504		−
505		− chained_irq_enter(parent_chip, desc);
506		−
507		− /* Read event register */
508		− val = readl(U300_PIN_REG(pinoffset, iev));
509		− /* Mask relevant bits */
510		− val &= 0xFFU; /* 8 bits per port */
511		− /* ACK IRQ (clear event) */
512		− writel(val, U300_PIN_REG(pinoffset, iev));
513		−
514		− /* Call IRQ handler */
515		− if (val != 0) {
516		− int irqoffset;
517		−
518		− for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
519		− int offset = pinoffset + irqoffset;
520		− int pin_irq = irq_find_mapping(chip->irq.domain, offset);
521		−
522		− dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
523		− pin_irq, offset);
524		− generic_handle_irq(pin_irq);
525		− /*
526		− * Triggering IRQ on both rising and falling edge
527		− * needs mockery
528		− */
529		− if (port->toggle_edge_mode & U300_PIN_BIT(offset))
530		− u300_toggle_trigger(gpio, offset);
531		− }
532		− }
533		−
534		− chained_irq_exit(parent_chip, desc);
535		−}
536		−
537		−static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
538		− int offset,
539		− const struct u300_gpio_confdata *conf)
540		−{
541		− /* Set mode: input or output */
542		− if (conf->output) {
543		− u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
544		−
545		− /* Deactivate bias mode for output */
546		− u300_gpio_config_set(&gpio->chip, offset,
547		− PIN_CONFIG_BIAS_HIGH_IMPEDANCE);
548		−
549		− /* Set drive mode for output */
550		− u300_gpio_config_set(&gpio->chip, offset,
551		− PIN_CONFIG_DRIVE_PUSH_PULL);
552		−
553		− dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
554		− offset, conf->outval);
555		− } else {
556		− u300_gpio_direction_input(&gpio->chip, offset);
557		−
558		− /* Always set output low on input pins */
559		− u300_gpio_set(&gpio->chip, offset, 0);
560		−
561		− /* Set bias mode for input */
562		− u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode);
563		−
564		− dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
565		− offset, conf->bias_mode);
566		− }
567		−}
568		−
569		−static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio)
570		−{
571		− int i, j;
572		−
573		− /* Write default config and values to all pins */
574		− for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
575		− for (j = 0; j < 8; j++) {
576		− const struct u300_gpio_confdata *conf;
577		− int offset = (i*8) + j;
578		−
579		− conf = &bs335_gpio_config[i][j];
580		− u300_gpio_init_pin(gpio, offset, conf);
581		− }
582		− }
583		−}
584		−
585		−/*
586		− * Here we map a GPIO in the local gpio_chip pin space to a pin in
587		− * the local pinctrl pin space. The pin controller used is
588		− * pinctrl-u300.
589		− */
590		−struct coh901_pinpair {
591		− unsigned int offset;
592		− unsigned int pin_base;
593		−};
594		−
595		−#define COH901_PINRANGE(a, b) { .offset = a, .pin_base = b }
596		−
597		−static struct coh901_pinpair coh901_pintable[] = {
598		− COH901_PINRANGE(10, 426),
599		− COH901_PINRANGE(11, 180),
600		− COH901_PINRANGE(12, 165), /* MS/MMC card insertion */
601		− COH901_PINRANGE(13, 179),
602		− COH901_PINRANGE(14, 178),
603		− COH901_PINRANGE(16, 194),
604		− COH901_PINRANGE(17, 193),
605		− COH901_PINRANGE(18, 192),
606		− COH901_PINRANGE(19, 191),
607		− COH901_PINRANGE(20, 186),
608		− COH901_PINRANGE(21, 185),
609		− COH901_PINRANGE(22, 184),
610		− COH901_PINRANGE(23, 183),
611		− COH901_PINRANGE(24, 182),
612		− COH901_PINRANGE(25, 181),
613		−};
614		−
615		−static int __init u300_gpio_probe(struct platform_device *pdev)
616		−{
617		− struct u300_gpio *gpio;
618		− struct gpio_irq_chip *girq;
619		− int err = 0;
620		− int portno;
621		− u32 val;
622		− u32 ifr;
623		− int i;
624		−
625		− gpio = devm_kzalloc(&pdev->dev, sizeof(struct u300_gpio), GFP_KERNEL);
626		− if (gpio == NULL)
627		− return -ENOMEM;
628		−
629		− gpio->chip = u300_gpio_chip;
630		− gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT;
631		− gpio->chip.parent = &pdev->dev;
632		− gpio->chip.base = 0;
633		− gpio->dev = &pdev->dev;
634		−
635		− gpio->base = devm_platform_ioremap_resource(pdev, 0);
636		− if (IS_ERR(gpio->base))
637		− return PTR_ERR(gpio->base);
638		−
639		− gpio->clk = devm_clk_get(gpio->dev, NULL);
640		− if (IS_ERR(gpio->clk)) {
641		− err = PTR_ERR(gpio->clk);
642		− dev_err(gpio->dev, "could not get GPIO clock\n");
643		− return err;
644		− }
645		−
646		− err = clk_prepare_enable(gpio->clk);
647		− if (err) {
648		− dev_err(gpio->dev, "could not enable GPIO clock\n");
649		− return err;
650		− }
651		−
652		− dev_info(gpio->dev,
653		− "initializing GPIO Controller COH 901 571/3\n");
654		− gpio->stride = U300_GPIO_PORT_STRIDE;
655		− gpio->pcr = U300_GPIO_PXPCR;
656		− gpio->dor = U300_GPIO_PXPDOR;
657		− gpio->dir = U300_GPIO_PXPDIR;
658		− gpio->per = U300_GPIO_PXPER;
659		− gpio->icr = U300_GPIO_PXICR;
660		− gpio->ien = U300_GPIO_PXIEN;
661		− gpio->iev = U300_GPIO_PXIEV;
662		− ifr = U300_GPIO_PXIFR;
663		−
664		− val = readl(gpio->base + U300_GPIO_CR);
665		− dev_info(gpio->dev, "COH901571/3 block version: %d, " \
666		− "number of cores: %d totalling %d pins\n",
667		− ((val & 0x000001FC) >> 2),
668		− ((val & 0x0000FE00) >> 9),
669		− ((val & 0x0000FE00) >> 9) * 8);
670		− writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
671		− gpio->base + U300_GPIO_CR);
672		− u300_gpio_init_coh901571(gpio);
673		−
674		− girq = &gpio->chip.irq;
675		− girq->chip = &u300_gpio_irqchip;
676		− girq->parent_handler = u300_gpio_irq_handler;
677		− girq->num_parents = U300_GPIO_NUM_PORTS;
678		− girq->parents = devm_kcalloc(gpio->dev, U300_GPIO_NUM_PORTS,
679		− sizeof(*girq->parents),
680		− GFP_KERNEL);
681		− if (!girq->parents) {
682		− err = -ENOMEM;
683		− goto err_dis_clk;
684		− }
685		− for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) {
686		− struct u300_gpio_port *port = &gpio->ports[portno];
687		−
688		− snprintf(port->name, 8, "gpio%d", portno);
689		− port->number = portno;
690		− port->gpio = gpio;
691		−
692		− port->irq = platform_get_irq(pdev, portno);
693		− girq->parents[portno] = port->irq;
694		−
695		− /* Turns off irq force (test register) for this port */
696		− writel(0x0, gpio->base + portno * gpio->stride + ifr);
697		− }
698		− girq->default_type = IRQ_TYPE_EDGE_FALLING;
699		− girq->handler = handle_simple_irq;
700		−#ifdef CONFIG_OF_GPIO
701		− gpio->chip.of_node = pdev->dev.of_node;
702		−#endif
703		− err = gpiochip_add_data(&gpio->chip, gpio);
704		− if (err) {
705		− dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
706		− goto err_dis_clk;
707		− }
708		−
709		− /*
710		− * Add pinctrl pin ranges, the pin controller must be registered
711		− * at this point
712		− */
713		− for (i = 0; i < ARRAY_SIZE(coh901_pintable); i++) {
714		− struct coh901_pinpair *p = &coh901_pintable[i];
715		−
716		− err = gpiochip_add_pin_range(&gpio->chip, "pinctrl-u300",
717		− p->offset, p->pin_base, 1);
718		− if (err)
719		− goto err_no_range;
720		− }
721		−
722		− platform_set_drvdata(pdev, gpio);
723		−
724		− return 0;
725		−
726		−err_no_range:
727		− gpiochip_remove(&gpio->chip);
728		−err_dis_clk:
729		− clk_disable_unprepare(gpio->clk);
730		− dev_err(&pdev->dev, "module ERROR:%d\n", err);
731		− return err;
732		−}
733		−
734		−static int __exit u300_gpio_remove(struct platform_device *pdev)
735		−{
736		− struct u300_gpio *gpio = platform_get_drvdata(pdev);
737		−
738		− /* Turn off the GPIO block */
739		− writel(0x00000000U, gpio->base + U300_GPIO_CR);
740		−
741		− gpiochip_remove(&gpio->chip);
742		− clk_disable_unprepare(gpio->clk);
743		− return 0;
744		−}
745		−
746		−static const struct of_device_id u300_gpio_match[] = {
747		− { .compatible = "stericsson,gpio-coh901" },
748		− {},
749		−};
750		−
751		−static struct platform_driver u300_gpio_driver = {
752		− .driver = {
753		− .name = "u300-gpio",
754		− .of_match_table = u300_gpio_match,
755		− },
756		− .remove = __exit_p(u300_gpio_remove),
757		−};
758		−
759		−static int __init u300_gpio_init(void)
760		−{
761		− return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe);
762		−}
763		−
764		−static void __exit u300_gpio_exit(void)
765		−{
766		− platform_driver_unregister(&u300_gpio_driver);
767		−}
768		−
769		−arch_initcall(u300_gpio_init);
770		−module_exit(u300_gpio_exit);
771		−
772		−MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
773		−MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver");
774		−MODULE_LICENSE("GPL");

drivers/pinctrl/pinctrl-coh901.h+0−6

@@ -1,6 +0,0 @@
1		−/* SPDX-License-Identifier: GPL-2.0 */
2		−int u300_gpio_config_get(struct gpio_chip *chip,
3		− unsigned offset,
4		− unsigned long *config);
5		−int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
6		− enum pin_config_param param);

drivers/pinctrl/pinctrl-ingenic.c+76−22

@@ -376,12 +376,21 @@ static int jz4760_cim_pins[] = { · 375 unmodified lines
376	376	0x26, 0x27, 0x28, 0x29,
377	377	0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
378	378	};
	379	+static int jz4760_lcd_8bit_pins[] = {
	380	+ 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x4c,
	381	+ 0x4d, 0x52, 0x53,
	382	+};
	383	+static int jz4760_lcd_16bit_pins[] = {
	384	+ 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,
	385	+};
	386	+static int jz4760_lcd_18bit_pins[] = {
	387	+ 0x5a, 0x5b,
	388	+};
379	389	static int jz4760_lcd_24bit_pins[] = {
380		− 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
381		− 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
382		− 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
383		− 0x58, 0x59, 0x5a, 0x5b,
	390	+ 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55,
384	391	};
	392	+static int jz4760_lcd_special_pins[] = { 0x40, 0x41, 0x4a, 0x54 };
	393	+static int jz4760_lcd_generic_pins[] = { 0x49, };
385	394	static int jz4760_pwm_pwm0_pins[] = { 0x80, };
386	395	static int jz4760_pwm_pwm1_pins[] = { 0x81, };
387	396	static int jz4760_pwm_pwm2_pins[] = { 0x82, };
@@ -390,6 +399,7 @@ static int jz4760_pwm_pwm4_pins[] = { 0x84, }; · 2 unmodified lines
390	399	static int jz4760_pwm_pwm5_pins[] = { 0x85, };
391	400	static int jz4760_pwm_pwm6_pins[] = { 0x6a, };
392	401	static int jz4760_pwm_pwm7_pins[] = { 0x6b, };
	402	+static int jz4760_otg_pins[] = { 0x8a, };
393	403
394	404	static u8 jz4760_uart3_data_funcs[] = { 0, 1, };
395	405	static u8 jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
@@ -436,8 +446,12 @@ static const struct group_desc jz4760_groups[] = { · 40 unmodified lines
436	446	INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0),
437	447	INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0),
438	448	INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0),
	449	+ INGENIC_PIN_GROUP("lcd-8bit", jz4760_lcd_8bit, 0),
	450	+ INGENIC_PIN_GROUP("lcd-16bit", jz4760_lcd_16bit, 0),
	451	+ INGENIC_PIN_GROUP("lcd-18bit", jz4760_lcd_18bit, 0),
439	452	INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0),
440		− { "lcd-no-pins", },
	453	+ INGENIC_PIN_GROUP("lcd-generic", jz4760_lcd_generic, 0),
	454	+ INGENIC_PIN_GROUP("lcd-special", jz4760_lcd_special, 1),
441	455	INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0, 0),
442	456	INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1, 0),
443	457	INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2, 0),
@@ -446,6 +460,7 @@ static const struct group_desc jz4760_groups[] = { · 2 unmodified lines
446	460	INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5, 0),
447	461	INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6, 0),
448	462	INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7, 0),
	463	+ INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
449	464	};
450	465
451	466	static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
@@ -477,7 +492,10 @@ static const char *jz4760_cs6_groups[] = { "nemc-cs6", }; · 25 unmodified lines
477	492	static const char *jz4760_i2c0_groups[] = { "i2c0-data", };
478	493	static const char *jz4760_i2c1_groups[] = { "i2c1-data", };
479	494	static const char *jz4760_cim_groups[] = { "cim-data", };
480		−static const char *jz4760_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
	495	+static const char *jz4760_lcd_groups[] = {
	496	+ "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
	497	+ "lcd-special", "lcd-generic",
	498	+};
481	499	static const char *jz4760_pwm0_groups[] = { "pwm0", };
482	500	static const char *jz4760_pwm1_groups[] = { "pwm1", };
483	501	static const char *jz4760_pwm2_groups[] = { "pwm2", };
@@ -486,6 +504,7 @@ static const char *jz4760_pwm4_groups[] = { "pwm4", }; · 2 unmodified lines
486	504	static const char *jz4760_pwm5_groups[] = { "pwm5", };
487	505	static const char *jz4760_pwm6_groups[] = { "pwm6", };
488	506	static const char *jz4760_pwm7_groups[] = { "pwm7", };
	507	+static const char *jz4760_otg_groups[] = { "otg-vbus", };
489	508
490	509	static const struct function_desc jz4760_functions[] = {
491	510	{ "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), },
@@ -514,6 +533,7 @@ static const struct function_desc jz4760_functions[] = { · 22 unmodified lines
514	533	{ "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), },
515	534	{ "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), },
516	535	{ "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), },
	536	+ { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), },
517	537	};
518	538
519	539	static const struct ingenic_chip_info jz4760_chip_info = {
@@ -648,7 +668,6 @@ static int jz4770_mac_rmii_pins[] = { · 128 unmodified lines
648	668	0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
649	669	};
650	670	static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, };
651		−static int jz4770_otg_pins[] = { 0x8a, };
652	671
653	672	static const struct group_desc jz4770_groups[] = {
654	673	INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
@@ -747,7 +766,7 @@ static const struct group_desc jz4770_groups[] = { · 92 unmodified lines
747	766	INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0),
748	767	INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0),
749	768	INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0),
750		− INGENIC_PIN_GROUP("otg-vbus", jz4770_otg, 0),
	769	+ INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
751	770	};
752	771
753	772	static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
@@ -808,7 +827,6 @@ static const char *jz4770_pwm5_groups[] = { "pwm5", }; · 54 unmodified lines
808	827	static const char *jz4770_pwm6_groups[] = { "pwm6", };
809	828	static const char *jz4770_pwm7_groups[] = { "pwm7", };
810	829	static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
811		−static const char *jz4770_otg_groups[] = { "otg-vbus", };
812	830
813	831	static const struct function_desc jz4770_functions[] = {
814	832	{ "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
@@ -841,7 +859,7 @@ static const struct function_desc jz4770_functions[] = { · 26 unmodified lines
841	859	{ "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
842	860	{ "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
843	861	{ "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), },
844		− { "otg", jz4770_otg_groups, ARRAY_SIZE(jz4770_otg_groups), },
	862	+ { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), },
845	863	};
846	864
847	865	static const struct ingenic_chip_info jz4770_chip_info = {
@@ -2384,6 +2402,12 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) · 1536 unmodified lines
2384	2402	unsigned int i;
2385	2403	int err;
2386	2404
	2405	+ chip_info = of_device_get_match_data(dev);
	2406	+ if (!chip_info) {
	2407	+ dev_err(dev, "Unsupported SoC\n");
	2408	+ return -EINVAL;
	2409	+ }
	2410	+
2387	2411	jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL);
2388	2412	if (!jzpc)
2389	2413	return -ENOMEM;
@@ -2400,7 +2424,7 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) · 10 unmodified lines
2400	2424	}
2401	2425
2402	2426	jzpc->dev = dev;
2403		− jzpc->info = chip_info = of_device_get_match_data(dev);
	2427	+ jzpc->info = chip_info;
2404	2428
2405	2429	pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
2406	2430	if (!pctl_desc)
@@ -2470,17 +2494,47 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) · 63 unmodified lines
2470	2494	}
2471	2495
2472	2496	static const struct of_device_id ingenic_pinctrl_of_match[] = {
2473		− { .compatible = "ingenic,jz4740-pinctrl", .data = &jz4740_chip_info },
2474		− { .compatible = "ingenic,jz4725b-pinctrl", .data = &jz4725b_chip_info },
2475		− { .compatible = "ingenic,jz4760-pinctrl", .data = &jz4760_chip_info },
2476		− { .compatible = "ingenic,jz4760b-pinctrl", .data = &jz4760_chip_info },
2477		− { .compatible = "ingenic,jz4770-pinctrl", .data = &jz4770_chip_info },
2478		− { .compatible = "ingenic,jz4780-pinctrl", .data = &jz4780_chip_info },
2479		− { .compatible = "ingenic,x1000-pinctrl", .data = &x1000_chip_info },
2480		− { .compatible = "ingenic,x1000e-pinctrl", .data = &x1000_chip_info },
2481		− { .compatible = "ingenic,x1500-pinctrl", .data = &x1500_chip_info },
2482		− { .compatible = "ingenic,x1830-pinctrl", .data = &x1830_chip_info },
2483		− {},
	2497	+ {
	2498	+ .compatible = "ingenic,jz4740-pinctrl",
	2499	+ .data = IF_ENABLED(CONFIG_MACH_JZ4740, &jz4740_chip_info)
	2500	+ },
	2501	+ {
	2502	+ .compatible = "ingenic,jz4725b-pinctrl",
	2503	+ .data = IF_ENABLED(CONFIG_MACH_JZ4725B, &jz4725b_chip_info)
	2504	+ },
	2505	+ {
	2506	+ .compatible = "ingenic,jz4760-pinctrl",
	2507	+ .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info)
	2508	+ },
	2509	+ {
	2510	+ .compatible = "ingenic,jz4760b-pinctrl",
	2511	+ .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info)
	2512	+ },
	2513	+ {
	2514	+ .compatible = "ingenic,jz4770-pinctrl",
	2515	+ .data = IF_ENABLED(CONFIG_MACH_JZ4770, &jz4770_chip_info)
	2516	+ },
	2517	+ {
	2518	+ .compatible = "ingenic,jz4780-pinctrl",
	2519	+ .data = IF_ENABLED(CONFIG_MACH_JZ4780, &jz4780_chip_info)
	2520	+ },
	2521	+ {
	2522	+ .compatible = "ingenic,x1000-pinctrl",
	2523	+ .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info)
	2524	+ },
	2525	+ {
	2526	+ .compatible = "ingenic,x1000e-pinctrl",
	2527	+ .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info)
	2528	+ },
	2529	+ {
	2530	+ .compatible = "ingenic,x1500-pinctrl",
	2531	+ .data = IF_ENABLED(CONFIG_MACH_X1500, &x1500_chip_info)
	2532	+ },
	2533	+ {
	2534	+ .compatible = "ingenic,x1830-pinctrl",
	2535	+ .data = IF_ENABLED(CONFIG_MACH_X1830, &x1830_chip_info)
	2536	+ },
	2537	+ { /* sentinel */ },
2484	2538	};
2485	2539
2486	2540	static struct platform_driver ingenic_pinctrl_driver = {

drivers/pinctrl/pinctrl-single.c+1−0

@@ -777,6 +777,7 @@ static int pcs_add_function(struct pcs_device *pcs, · 776 unmodified lines
777	777
778	778	function->vals = vals;
779	779	function->nvals = nvals;
	780	+ function->name = name;
780	781
781	782	selector = pinmux_generic_add_function(pcs->pctl, name,
782	783	pgnames, npgnames,

drivers/pinctrl/pinctrl-st.c+0−1

@@ -541,7 +541,6 @@ static void st_pinconf_set_retime_packed(struct st_pinctrl *info, · 540 unmodified lines
541	541	st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin);
542	542	/* 2 bit delay, msb */
543	543	st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin);
544		−
545	544	}
546	545
547	546	static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info,

drivers/pinctrl/pinctrl-sx150x.c+0−1

@@ -443,7 +443,6 @@ static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset, · 442 unmodified lines
443	443	sx150x_gpio_oscio_set(pctl, value);
444	444	else
445	445	__sx150x_gpio_set(pctl, offset, value);
446		−
447	446	}
448	447
449	448	static void sx150x_gpio_set_multiple(struct gpio_chip *chip,

drivers/pinctrl/pinctrl-u300.c+0−1111

@@ -1,1111 +0,0 @@
1		−// SPDX-License-Identifier: GPL-2.0-only
2		−/*
3		− * Driver for the U300 pin controller
4		− *
5		− * Based on the original U300 padmux functions
6		− * Copyright (C) 2009-2011 ST-Ericsson AB
7		− * Author: Martin Persson <martin.persson@stericsson.com>
8		− * Author: Linus Walleij <linus.walleij@linaro.org>
9		− *
10		− * The DB3350 design and control registers are oriented around pads rather than
11		− * pins, so we enumerate the pads we can mux rather than actual pins. The pads
12		− * are connected to different pins in different packaging types, so it would
13		− * be confusing.
14		− */
15		−#include <linux/init.h>
16		−#include <linux/module.h>
17		−#include <linux/mod_devicetable.h>
18		−#include <linux/platform_device.h>
19		−#include <linux/io.h>
20		−#include <linux/slab.h>
21		−#include <linux/err.h>
22		−#include <linux/pinctrl/pinctrl.h>
23		−#include <linux/pinctrl/pinmux.h>
24		−#include <linux/pinctrl/pinconf.h>
25		−#include <linux/pinctrl/pinconf-generic.h>
26		−#include "pinctrl-coh901.h"
27		−
28		−/*
29		− * Register definitions for the U300 Padmux control registers in the
30		− * system controller
31		− */
32		−
33		−/* PAD MUX Control register 1 (LOW) 16bit (R/W) */
34		−#define U300_SYSCON_PMC1LR 0x007C
35		−#define U300_SYSCON_PMC1LR_MASK 0xFFFF
36		−#define U300_SYSCON_PMC1LR_CDI_MASK 0xC000
37		−#define U300_SYSCON_PMC1LR_CDI_CDI 0x0000
38		−#define U300_SYSCON_PMC1LR_CDI_EMIF 0x4000
39		−/* For BS335 */
40		−#define U300_SYSCON_PMC1LR_CDI_CDI2 0x8000
41		−#define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO 0xC000
42		−/* For BS365 */
43		−#define U300_SYSCON_PMC1LR_CDI_GPIO 0x8000
44		−#define U300_SYSCON_PMC1LR_CDI_WCDMA 0xC000
45		−/* Common defs */
46		−#define U300_SYSCON_PMC1LR_PDI_MASK 0x3000
47		−#define U300_SYSCON_PMC1LR_PDI_PDI 0x0000
48		−#define U300_SYSCON_PMC1LR_PDI_EGG 0x1000
49		−#define U300_SYSCON_PMC1LR_PDI_WCDMA 0x3000
50		−#define U300_SYSCON_PMC1LR_MMCSD_MASK 0x0C00
51		−#define U300_SYSCON_PMC1LR_MMCSD_MMCSD 0x0000
52		−#define U300_SYSCON_PMC1LR_MMCSD_MSPRO 0x0400
53		−#define U300_SYSCON_PMC1LR_MMCSD_DSP 0x0800
54		−#define U300_SYSCON_PMC1LR_MMCSD_WCDMA 0x0C00
55		−#define U300_SYSCON_PMC1LR_ETM_MASK 0x0300
56		−#define U300_SYSCON_PMC1LR_ETM_ACC 0x0000
57		−#define U300_SYSCON_PMC1LR_ETM_APP 0x0100
58		−#define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK 0x00C0
59		−#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC 0x0000
60		−#define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF 0x0040
61		−#define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM 0x0080
62		−#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB 0x00C0
63		−#define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK 0x0030
64		−#define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC 0x0000
65		−#define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF 0x0010
66		−#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM 0x0020
67		−#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI 0x0030
68		−#define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK 0x000C
69		−#define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC 0x0000
70		−#define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF 0x0004
71		−#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM 0x0008
72		−#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI 0x000C
73		−#define U300_SYSCON_PMC1LR_EMIF_1_MASK 0x0003
74		−#define U300_SYSCON_PMC1LR_EMIF_1_STATIC 0x0000
75		−#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0 0x0001
76		−#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1 0x0002
77		−#define U300_SYSCON_PMC1LR_EMIF_1 0x0003
78		−/* PAD MUX Control register 2 (HIGH) 16bit (R/W) */
79		−#define U300_SYSCON_PMC1HR 0x007E
80		−#define U300_SYSCON_PMC1HR_MASK 0xFFFF
81		−#define U300_SYSCON_PMC1HR_MISC_2_MASK 0xC000
82		−#define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO 0x0000
83		−#define U300_SYSCON_PMC1HR_MISC_2_MSPRO 0x4000
84		−#define U300_SYSCON_PMC1HR_MISC_2_DSP 0x8000
85		−#define U300_SYSCON_PMC1HR_MISC_2_AAIF 0xC000
86		−#define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK 0x3000
87		−#define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO 0x0000
88		−#define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF 0x1000
89		−#define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP 0x2000
90		−#define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF 0x3000
91		−#define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK 0x0C00
92		−#define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO 0x0000
93		−#define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC 0x0400
94		−#define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP 0x0800
95		−#define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF 0x0C00
96		−#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK 0x0300
97		−#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO 0x0000
98		−#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI 0x0100
99		−#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF 0x0300
100		−#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK 0x00C0
101		−#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO 0x0000
102		−#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI 0x0040
103		−#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF 0x00C0
104		−#define U300_SYSCON_PMC1HR_APP_SPI_2_MASK 0x0030
105		−#define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO 0x0000
106		−#define U300_SYSCON_PMC1HR_APP_SPI_2_SPI 0x0010
107		−#define U300_SYSCON_PMC1HR_APP_SPI_2_DSP 0x0020
108		−#define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF 0x0030
109		−#define U300_SYSCON_PMC1HR_APP_UART0_2_MASK 0x000C
110		−#define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO 0x0000
111		−#define U300_SYSCON_PMC1HR_APP_UART0_2_UART0 0x0004
112		−#define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS 0x0008
113		−#define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF 0x000C
114		−#define U300_SYSCON_PMC1HR_APP_UART0_1_MASK 0x0003
115		−#define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO 0x0000
116		−#define U300_SYSCON_PMC1HR_APP_UART0_1_UART0 0x0001
117		−#define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF 0x0003
118		−/* Padmux 2 control */
119		−#define U300_SYSCON_PMC2R 0x100
120		−#define U300_SYSCON_PMC2R_APP_MISC_0_MASK 0x00C0
121		−#define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO 0x0000
122		−#define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM 0x0040
123		−#define U300_SYSCON_PMC2R_APP_MISC_0_MMC 0x0080
124		−#define U300_SYSCON_PMC2R_APP_MISC_0_CDI2 0x00C0
125		−#define U300_SYSCON_PMC2R_APP_MISC_1_MASK 0x0300
126		−#define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO 0x0000
127		−#define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM 0x0100
128		−#define U300_SYSCON_PMC2R_APP_MISC_1_MMC 0x0200
129		−#define U300_SYSCON_PMC2R_APP_MISC_1_CDI2 0x0300
130		−#define U300_SYSCON_PMC2R_APP_MISC_2_MASK 0x0C00
131		−#define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO 0x0000
132		−#define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM 0x0400
133		−#define U300_SYSCON_PMC2R_APP_MISC_2_MMC 0x0800
134		−#define U300_SYSCON_PMC2R_APP_MISC_2_CDI2 0x0C00
135		−#define U300_SYSCON_PMC2R_APP_MISC_3_MASK 0x3000
136		−#define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO 0x0000
137		−#define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM 0x1000
138		−#define U300_SYSCON_PMC2R_APP_MISC_3_MMC 0x2000
139		−#define U300_SYSCON_PMC2R_APP_MISC_3_CDI2 0x3000
140		−#define U300_SYSCON_PMC2R_APP_MISC_4_MASK 0xC000
141		−#define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO 0x0000
142		−#define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM 0x4000
143		−#define U300_SYSCON_PMC2R_APP_MISC_4_MMC 0x8000
144		−#define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO 0xC000
145		−/* TODO: More SYSCON registers missing */
146		−#define U300_SYSCON_PMC3R 0x10C
147		−#define U300_SYSCON_PMC3R_APP_MISC_11_MASK 0xC000
148		−#define U300_SYSCON_PMC3R_APP_MISC_11_SPI 0x4000
149		−#define U300_SYSCON_PMC3R_APP_MISC_10_MASK 0x3000
150		−#define U300_SYSCON_PMC3R_APP_MISC_10_SPI 0x1000
151		−/* TODO: Missing other configs */
152		−#define U300_SYSCON_PMC4R 0x168
153		−#define U300_SYSCON_PMC4R_APP_MISC_12_MASK 0x0003
154		−#define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO 0x0000
155		−#define U300_SYSCON_PMC4R_APP_MISC_13_MASK 0x000C
156		−#define U300_SYSCON_PMC4R_APP_MISC_13_CDI 0x0000
157		−#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA 0x0004
158		−#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2 0x0008
159		−#define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO 0x000C
160		−#define U300_SYSCON_PMC4R_APP_MISC_14_MASK 0x0030
161		−#define U300_SYSCON_PMC4R_APP_MISC_14_CDI 0x0000
162		−#define U300_SYSCON_PMC4R_APP_MISC_14_SMIA 0x0010
163		−#define U300_SYSCON_PMC4R_APP_MISC_14_CDI2 0x0020
164		−#define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO 0x0030
165		−#define U300_SYSCON_PMC4R_APP_MISC_16_MASK 0x0300
166		−#define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13 0x0000
167		−#define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS 0x0100
168		−#define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N 0x0200
169		−
170		−#define DRIVER_NAME "pinctrl-u300"
171		−
172		−/*
173		− * The DB3350 has 467 pads, I have enumerated the pads clockwise around the
174		− * edges of the silicon, finger by finger. LTCORNER upper left is pad 0.
175		− * Data taken from the PadRing chart, arranged like this:
176		− *
177		− * 0 ..... 104
178		− * 466 105
179		− * . .
180		− * . .
181		− * 358 224
182		− * 357 .... 225
183		− */
184		−#define U300_NUM_PADS 467
185		−
186		−/* Pad names for the pinmux subsystem */
187		−static const struct pinctrl_pin_desc u300_pads[] = {
188		− /* Pads along the top edge of the chip */
189		− PINCTRL_PIN(0, "P PAD VDD 28"),
190		− PINCTRL_PIN(1, "P PAD GND 28"),
191		− PINCTRL_PIN(2, "PO SIM RST N"),
192		− PINCTRL_PIN(3, "VSSIO 25"),
193		− PINCTRL_PIN(4, "VSSA ADDA ESDSUB"),
194		− PINCTRL_PIN(5, "PWR VSSCOMMON"),
195		− PINCTRL_PIN(6, "PI ADC I1 POS"),
196		− PINCTRL_PIN(7, "PI ADC I1 NEG"),
197		− PINCTRL_PIN(8, "PWR VSSAD0"),
198		− PINCTRL_PIN(9, "PWR VCCAD0"),
199		− PINCTRL_PIN(10, "PI ADC Q1 NEG"),
200		− PINCTRL_PIN(11, "PI ADC Q1 POS"),
201		− PINCTRL_PIN(12, "PWR VDDAD"),
202		− PINCTRL_PIN(13, "PWR GNDAD"),
203		− PINCTRL_PIN(14, "PI ADC I2 POS"),
204		− PINCTRL_PIN(15, "PI ADC I2 NEG"),
205		− PINCTRL_PIN(16, "PWR VSSAD1"),
206		− PINCTRL_PIN(17, "PWR VCCAD1"),
207		− PINCTRL_PIN(18, "PI ADC Q2 NEG"),
208		− PINCTRL_PIN(19, "PI ADC Q2 POS"),
209		− PINCTRL_PIN(20, "VSSA ADDA ESDSUB"),
210		− PINCTRL_PIN(21, "PWR VCCGPAD"),
211		− PINCTRL_PIN(22, "PI TX POW"),
212		− PINCTRL_PIN(23, "PWR VSSGPAD"),
213		− PINCTRL_PIN(24, "PO DAC I POS"),
214		− PINCTRL_PIN(25, "PO DAC I NEG"),
215		− PINCTRL_PIN(26, "PO DAC Q POS"),
216		− PINCTRL_PIN(27, "PO DAC Q NEG"),
217		− PINCTRL_PIN(28, "PWR VSSDA"),
218		− PINCTRL_PIN(29, "PWR VCCDA"),
219		− PINCTRL_PIN(30, "VSSA ADDA ESDSUB"),
220		− PINCTRL_PIN(31, "P PAD VDDIO 11"),
221		− PINCTRL_PIN(32, "PI PLL 26 FILTVDD"),
222		− PINCTRL_PIN(33, "PI PLL 26 VCONT"),
223		− PINCTRL_PIN(34, "PWR AGNDPLL2V5 32 13"),
224		− PINCTRL_PIN(35, "PWR AVDDPLL2V5 32 13"),
225		− PINCTRL_PIN(36, "VDDA PLL ESD"),
226		− PINCTRL_PIN(37, "VSSA PLL ESD"),
227		− PINCTRL_PIN(38, "VSS PLL"),
228		− PINCTRL_PIN(39, "VDDC PLL"),
229		− PINCTRL_PIN(40, "PWR AGNDPLL2V5 26 60"),
230		− PINCTRL_PIN(41, "PWR AVDDPLL2V5 26 60"),
231		− PINCTRL_PIN(42, "PWR AVDDPLL2V5 26 208"),
232		− PINCTRL_PIN(43, "PWR AGNDPLL2V5 26 208"),
233		− PINCTRL_PIN(44, "PWR AVDDPLL2V5 13 208"),
234		− PINCTRL_PIN(45, "PWR AGNDPLL2V5 13 208"),
235		− PINCTRL_PIN(46, "P PAD VSSIO 11"),
236		− PINCTRL_PIN(47, "P PAD VSSIO 12"),
237		− PINCTRL_PIN(48, "PI POW RST N"),
238		− PINCTRL_PIN(49, "VDDC IO"),
239		− PINCTRL_PIN(50, "P PAD VDDIO 16"),
240		− PINCTRL_PIN(51, "PO RF WCDMA EN 4"),
241		− PINCTRL_PIN(52, "PO RF WCDMA EN 3"),
242		− PINCTRL_PIN(53, "PO RF WCDMA EN 2"),
243		− PINCTRL_PIN(54, "PO RF WCDMA EN 1"),
244		− PINCTRL_PIN(55, "PO RF WCDMA EN 0"),
245		− PINCTRL_PIN(56, "PO GSM PA ENABLE"),
246		− PINCTRL_PIN(57, "PO RF DATA STRB"),
247		− PINCTRL_PIN(58, "PO RF DATA2"),
248		− PINCTRL_PIN(59, "PIO RF DATA1"),
249		− PINCTRL_PIN(60, "PIO RF DATA0"),
250		− PINCTRL_PIN(61, "P PAD VDD 11"),
251		− PINCTRL_PIN(62, "P PAD GND 11"),
252		− PINCTRL_PIN(63, "P PAD VSSIO 16"),
253		− PINCTRL_PIN(64, "P PAD VDDIO 18"),
254		− PINCTRL_PIN(65, "PO RF CTRL STRB2"),
255		− PINCTRL_PIN(66, "PO RF CTRL STRB1"),
256		− PINCTRL_PIN(67, "PO RF CTRL STRB0"),
257		− PINCTRL_PIN(68, "PIO RF CTRL DATA"),
258		− PINCTRL_PIN(69, "PO RF CTRL CLK"),
259		− PINCTRL_PIN(70, "PO TX ADC STRB"),
260		− PINCTRL_PIN(71, "PO ANT SW 2"),
261		− PINCTRL_PIN(72, "PO ANT SW 3"),
262		− PINCTRL_PIN(73, "PO ANT SW 0"),
263		− PINCTRL_PIN(74, "PO ANT SW 1"),
264		− PINCTRL_PIN(75, "PO M CLKRQ"),
265		− PINCTRL_PIN(76, "PI M CLK"),
266		− PINCTRL_PIN(77, "PI RTC CLK"),
267		− PINCTRL_PIN(78, "P PAD VDD 8"),
268		− PINCTRL_PIN(79, "P PAD GND 8"),
269		− PINCTRL_PIN(80, "P PAD VSSIO 13"),
270		− PINCTRL_PIN(81, "P PAD VDDIO 13"),
271		− PINCTRL_PIN(82, "PO SYS 1 CLK"),
272		− PINCTRL_PIN(83, "PO SYS 2 CLK"),
273		− PINCTRL_PIN(84, "PO SYS 0 CLK"),
274		− PINCTRL_PIN(85, "PI SYS 0 CLKRQ"),
275		− PINCTRL_PIN(86, "PO PWR MNGT CTRL 1"),
276		− PINCTRL_PIN(87, "PO PWR MNGT CTRL 0"),
277		− PINCTRL_PIN(88, "PO RESOUT2 RST N"),
278		− PINCTRL_PIN(89, "PO RESOUT1 RST N"),
279		− PINCTRL_PIN(90, "PO RESOUT0 RST N"),
280		− PINCTRL_PIN(91, "PI SERVICE N"),
281		− PINCTRL_PIN(92, "P PAD VDD 29"),
282		− PINCTRL_PIN(93, "P PAD GND 29"),
283		− PINCTRL_PIN(94, "P PAD VSSIO 8"),
284		− PINCTRL_PIN(95, "P PAD VDDIO 8"),
285		− PINCTRL_PIN(96, "PI EXT IRQ1 N"),
286		− PINCTRL_PIN(97, "PI EXT IRQ0 N"),
287		− PINCTRL_PIN(98, "PIO DC ON"),
288		− PINCTRL_PIN(99, "PIO ACC APP I2C DATA"),
289		− PINCTRL_PIN(100, "PIO ACC APP I2C CLK"),
290		− PINCTRL_PIN(101, "P PAD VDD 12"),
291		− PINCTRL_PIN(102, "P PAD GND 12"),
292		− PINCTRL_PIN(103, "P PAD VSSIO 14"),
293		− PINCTRL_PIN(104, "P PAD VDDIO 14"),
294		− /* Pads along the right edge of the chip */
295		− PINCTRL_PIN(105, "PIO APP I2C1 DATA"),
296		− PINCTRL_PIN(106, "PIO APP I2C1 CLK"),
297		− PINCTRL_PIN(107, "PO KEY OUT0"),
298		− PINCTRL_PIN(108, "PO KEY OUT1"),
299		− PINCTRL_PIN(109, "PO KEY OUT2"),
300		− PINCTRL_PIN(110, "PO KEY OUT3"),
301		− PINCTRL_PIN(111, "PO KEY OUT4"),
302		− PINCTRL_PIN(112, "PI KEY IN0"),
303		− PINCTRL_PIN(113, "PI KEY IN1"),
304		− PINCTRL_PIN(114, "PI KEY IN2"),
305		− PINCTRL_PIN(115, "P PAD VDDIO 15"),
306		− PINCTRL_PIN(116, "P PAD VSSIO 15"),
307		− PINCTRL_PIN(117, "P PAD GND 13"),
308		− PINCTRL_PIN(118, "P PAD VDD 13"),
309		− PINCTRL_PIN(119, "PI KEY IN3"),
310		− PINCTRL_PIN(120, "PI KEY IN4"),
311		− PINCTRL_PIN(121, "PI KEY IN5"),
312		− PINCTRL_PIN(122, "PIO APP PCM I2S1 DATA B"),
313		− PINCTRL_PIN(123, "PIO APP PCM I2S1 DATA A"),
314		− PINCTRL_PIN(124, "PIO APP PCM I2S1 WS"),
315		− PINCTRL_PIN(125, "PIO APP PCM I2S1 CLK"),
316		− PINCTRL_PIN(126, "PIO APP PCM I2S0 DATA B"),
317		− PINCTRL_PIN(127, "PIO APP PCM I2S0 DATA A"),
318		− PINCTRL_PIN(128, "PIO APP PCM I2S0 WS"),
319		− PINCTRL_PIN(129, "PIO APP PCM I2S0 CLK"),
320		− PINCTRL_PIN(130, "P PAD VDD 17"),
321		− PINCTRL_PIN(131, "P PAD GND 17"),
322		− PINCTRL_PIN(132, "P PAD VSSIO 19"),
323		− PINCTRL_PIN(133, "P PAD VDDIO 19"),
324		− PINCTRL_PIN(134, "UART0 RTS"),
325		− PINCTRL_PIN(135, "UART0 CTS"),
326		− PINCTRL_PIN(136, "UART0 TX"),
327		− PINCTRL_PIN(137, "UART0 RX"),
328		− PINCTRL_PIN(138, "PIO ACC SPI DO"),
329		− PINCTRL_PIN(139, "PIO ACC SPI DI"),
330		− PINCTRL_PIN(140, "PIO ACC SPI CS0 N"),
331		− PINCTRL_PIN(141, "PIO ACC SPI CS1 N"),
332		− PINCTRL_PIN(142, "PIO ACC SPI CS2 N"),
333		− PINCTRL_PIN(143, "PIO ACC SPI CLK"),
334		− PINCTRL_PIN(144, "PO PDI EXT RST N"),
335		− PINCTRL_PIN(145, "P PAD VDDIO 22"),
336		− PINCTRL_PIN(146, "P PAD VSSIO 22"),
337		− PINCTRL_PIN(147, "P PAD GND 18"),
338		− PINCTRL_PIN(148, "P PAD VDD 18"),
339		− PINCTRL_PIN(149, "PIO PDI C0"),
340		− PINCTRL_PIN(150, "PIO PDI C1"),
341		− PINCTRL_PIN(151, "PIO PDI C2"),
342		− PINCTRL_PIN(152, "PIO PDI C3"),
343		− PINCTRL_PIN(153, "PIO PDI C4"),
344		− PINCTRL_PIN(154, "PIO PDI C5"),
345		− PINCTRL_PIN(155, "PIO PDI D0"),
346		− PINCTRL_PIN(156, "PIO PDI D1"),
347		− PINCTRL_PIN(157, "PIO PDI D2"),
348		− PINCTRL_PIN(158, "PIO PDI D3"),
349		− PINCTRL_PIN(159, "P PAD VDDIO 21"),
350		− PINCTRL_PIN(160, "P PAD VSSIO 21"),
351		− PINCTRL_PIN(161, "PIO PDI D4"),
352		− PINCTRL_PIN(162, "PIO PDI D5"),
353		− PINCTRL_PIN(163, "PIO PDI D6"),
354		− PINCTRL_PIN(164, "PIO PDI D7"),
355		− PINCTRL_PIN(165, "PIO MS INS"),
356		− PINCTRL_PIN(166, "MMC DATA DIR LS"),
357		− PINCTRL_PIN(167, "MMC DATA 3"),
358		− PINCTRL_PIN(168, "MMC DATA 2"),
359		− PINCTRL_PIN(169, "MMC DATA 1"),
360		− PINCTRL_PIN(170, "MMC DATA 0"),
361		− PINCTRL_PIN(171, "MMC CMD DIR LS"),
362		− PINCTRL_PIN(172, "P PAD VDD 27"),
363		− PINCTRL_PIN(173, "P PAD GND 27"),
364		− PINCTRL_PIN(174, "P PAD VSSIO 20"),
365		− PINCTRL_PIN(175, "P PAD VDDIO 20"),
366		− PINCTRL_PIN(176, "MMC CMD"),
367		− PINCTRL_PIN(177, "MMC CLK"),
368		− PINCTRL_PIN(178, "PIO APP GPIO 14"),
369		− PINCTRL_PIN(179, "PIO APP GPIO 13"),
370		− PINCTRL_PIN(180, "PIO APP GPIO 11"),
371		− PINCTRL_PIN(181, "PIO APP GPIO 25"),
372		− PINCTRL_PIN(182, "PIO APP GPIO 24"),
373		− PINCTRL_PIN(183, "PIO APP GPIO 23"),
374		− PINCTRL_PIN(184, "PIO APP GPIO 22"),
375		− PINCTRL_PIN(185, "PIO APP GPIO 21"),
376		− PINCTRL_PIN(186, "PIO APP GPIO 20"),
377		− PINCTRL_PIN(187, "P PAD VDD 19"),
378		− PINCTRL_PIN(188, "P PAD GND 19"),
379		− PINCTRL_PIN(189, "P PAD VSSIO 23"),
380		− PINCTRL_PIN(190, "P PAD VDDIO 23"),
381		− PINCTRL_PIN(191, "PIO APP GPIO 19"),
382		− PINCTRL_PIN(192, "PIO APP GPIO 18"),
383		− PINCTRL_PIN(193, "PIO APP GPIO 17"),
384		− PINCTRL_PIN(194, "PIO APP GPIO 16"),
385		− PINCTRL_PIN(195, "PI CI D1"),
386		− PINCTRL_PIN(196, "PI CI D0"),
387		− PINCTRL_PIN(197, "PI CI HSYNC"),
388		− PINCTRL_PIN(198, "PI CI VSYNC"),
389		− PINCTRL_PIN(199, "PI CI EXT CLK"),
390		− PINCTRL_PIN(200, "PO CI EXT RST N"),
391		− PINCTRL_PIN(201, "P PAD VSSIO 43"),
392		− PINCTRL_PIN(202, "P PAD VDDIO 43"),
393		− PINCTRL_PIN(203, "PI CI D6"),
394		− PINCTRL_PIN(204, "PI CI D7"),
395		− PINCTRL_PIN(205, "PI CI D2"),
396		− PINCTRL_PIN(206, "PI CI D3"),
397		− PINCTRL_PIN(207, "PI CI D4"),
398		− PINCTRL_PIN(208, "PI CI D5"),
399		− PINCTRL_PIN(209, "PI CI D8"),
400		− PINCTRL_PIN(210, "PI CI D9"),
401		− PINCTRL_PIN(211, "P PAD VDD 20"),
402		− PINCTRL_PIN(212, "P PAD GND 20"),
403		− PINCTRL_PIN(213, "P PAD VSSIO 24"),
404		− PINCTRL_PIN(214, "P PAD VDDIO 24"),
405		− PINCTRL_PIN(215, "P PAD VDDIO 26"),
406		− PINCTRL_PIN(216, "PO EMIF 1 A26"),
407		− PINCTRL_PIN(217, "PO EMIF 1 A25"),
408		− PINCTRL_PIN(218, "P PAD VSSIO 26"),
409		− PINCTRL_PIN(219, "PO EMIF 1 A24"),
410		− PINCTRL_PIN(220, "PO EMIF 1 A23"),
411		− /* Pads along the bottom edge of the chip */
412		− PINCTRL_PIN(221, "PO EMIF 1 A22"),
413		− PINCTRL_PIN(222, "PO EMIF 1 A21"),
414		− PINCTRL_PIN(223, "P PAD VDD 21"),
415		− PINCTRL_PIN(224, "P PAD GND 21"),
416		− PINCTRL_PIN(225, "P PAD VSSIO 27"),
417		− PINCTRL_PIN(226, "P PAD VDDIO 27"),
418		− PINCTRL_PIN(227, "PO EMIF 1 A20"),
419		− PINCTRL_PIN(228, "PO EMIF 1 A19"),
420		− PINCTRL_PIN(229, "PO EMIF 1 A18"),
421		− PINCTRL_PIN(230, "PO EMIF 1 A17"),
422		− PINCTRL_PIN(231, "P PAD VDDIO 28"),
423		− PINCTRL_PIN(232, "P PAD VSSIO 28"),
424		− PINCTRL_PIN(233, "PO EMIF 1 A16"),
425		− PINCTRL_PIN(234, "PIO EMIF 1 D15"),
426		− PINCTRL_PIN(235, "PO EMIF 1 A15"),
427		− PINCTRL_PIN(236, "PIO EMIF 1 D14"),
428		− PINCTRL_PIN(237, "P PAD VDD 22"),
429		− PINCTRL_PIN(238, "P PAD GND 22"),
430		− PINCTRL_PIN(239, "P PAD VSSIO 29"),
431		− PINCTRL_PIN(240, "P PAD VDDIO 29"),
432		− PINCTRL_PIN(241, "PO EMIF 1 A14"),
433		− PINCTRL_PIN(242, "PIO EMIF 1 D13"),
434		− PINCTRL_PIN(243, "PO EMIF 1 A13"),
435		− PINCTRL_PIN(244, "PIO EMIF 1 D12"),
436		− PINCTRL_PIN(245, "P PAD VSSIO 30"),
437		− PINCTRL_PIN(246, "P PAD VDDIO 30"),
438		− PINCTRL_PIN(247, "PO EMIF 1 A12"),
439		− PINCTRL_PIN(248, "PIO EMIF 1 D11"),
440		− PINCTRL_PIN(249, "PO EMIF 1 A11"),
441		− PINCTRL_PIN(250, "PIO EMIF 1 D10"),
442		− PINCTRL_PIN(251, "P PAD VSSIO 31"),
443		− PINCTRL_PIN(252, "P PAD VDDIO 31"),
444		− PINCTRL_PIN(253, "PO EMIF 1 A10"),
445		− PINCTRL_PIN(254, "PIO EMIF 1 D09"),
446		− PINCTRL_PIN(255, "PO EMIF 1 A09"),
447		− PINCTRL_PIN(256, "P PAD VDDIO 32"),
448		− PINCTRL_PIN(257, "P PAD VSSIO 32"),
449		− PINCTRL_PIN(258, "P PAD GND 24"),
450		− PINCTRL_PIN(259, "P PAD VDD 24"),
451		− PINCTRL_PIN(260, "PIO EMIF 1 D08"),
452		− PINCTRL_PIN(261, "PO EMIF 1 A08"),
453		− PINCTRL_PIN(262, "PIO EMIF 1 D07"),
454		− PINCTRL_PIN(263, "PO EMIF 1 A07"),
455		− PINCTRL_PIN(264, "P PAD VDDIO 33"),
456		− PINCTRL_PIN(265, "P PAD VSSIO 33"),
457		− PINCTRL_PIN(266, "PIO EMIF 1 D06"),
458		− PINCTRL_PIN(267, "PO EMIF 1 A06"),
459		− PINCTRL_PIN(268, "PIO EMIF 1 D05"),
460		− PINCTRL_PIN(269, "PO EMIF 1 A05"),
461		− PINCTRL_PIN(270, "P PAD VDDIO 34"),
462		− PINCTRL_PIN(271, "P PAD VSSIO 34"),
463		− PINCTRL_PIN(272, "PIO EMIF 1 D04"),
464		− PINCTRL_PIN(273, "PO EMIF 1 A04"),
465		− PINCTRL_PIN(274, "PIO EMIF 1 D03"),
466		− PINCTRL_PIN(275, "PO EMIF 1 A03"),
467		− PINCTRL_PIN(276, "P PAD VDDIO 35"),
468		− PINCTRL_PIN(277, "P PAD VSSIO 35"),
469		− PINCTRL_PIN(278, "P PAD GND 23"),
470		− PINCTRL_PIN(279, "P PAD VDD 23"),
471		− PINCTRL_PIN(280, "PIO EMIF 1 D02"),
472		− PINCTRL_PIN(281, "PO EMIF 1 A02"),
473		− PINCTRL_PIN(282, "PIO EMIF 1 D01"),
474		− PINCTRL_PIN(283, "PO EMIF 1 A01"),
475		− PINCTRL_PIN(284, "P PAD VDDIO 36"),
476		− PINCTRL_PIN(285, "P PAD VSSIO 36"),
477		− PINCTRL_PIN(286, "PIO EMIF 1 D00"),
478		− PINCTRL_PIN(287, "PO EMIF 1 BE1 N"),
479		− PINCTRL_PIN(288, "PO EMIF 1 BE0 N"),
480		− PINCTRL_PIN(289, "PO EMIF 1 ADV N"),
481		− PINCTRL_PIN(290, "P PAD VDDIO 37"),
482		− PINCTRL_PIN(291, "P PAD VSSIO 37"),
483		− PINCTRL_PIN(292, "PO EMIF 1 SD CKE0"),
484		− PINCTRL_PIN(293, "PO EMIF 1 OE N"),
485		− PINCTRL_PIN(294, "PO EMIF 1 WE N"),
486		− PINCTRL_PIN(295, "P PAD VDDIO 38"),
487		− PINCTRL_PIN(296, "P PAD VSSIO 38"),
488		− PINCTRL_PIN(297, "PO EMIF 1 CLK"),
489		− PINCTRL_PIN(298, "PIO EMIF 1 SD CLK"),
490		− PINCTRL_PIN(299, "P PAD VSSIO 45 (not bonded)"),
491		− PINCTRL_PIN(300, "P PAD VDDIO 42"),
492		− PINCTRL_PIN(301, "P PAD VSSIO 42"),
493		− PINCTRL_PIN(302, "P PAD GND 31"),
494		− PINCTRL_PIN(303, "P PAD VDD 31"),
495		− PINCTRL_PIN(304, "PI EMIF 1 RET CLK"),
496		− PINCTRL_PIN(305, "PI EMIF 1 WAIT N"),
497		− PINCTRL_PIN(306, "PI EMIF 1 NFIF READY"),
498		− PINCTRL_PIN(307, "PO EMIF 1 SD CKE1"),
499		− PINCTRL_PIN(308, "PO EMIF 1 CS3 N"),
500		− PINCTRL_PIN(309, "P PAD VDD 25"),
501		− PINCTRL_PIN(310, "P PAD GND 25"),
502		− PINCTRL_PIN(311, "P PAD VSSIO 39"),
503		− PINCTRL_PIN(312, "P PAD VDDIO 39"),
504		− PINCTRL_PIN(313, "PO EMIF 1 CS2 N"),
505		− PINCTRL_PIN(314, "PO EMIF 1 CS1 N"),
506		− PINCTRL_PIN(315, "PO EMIF 1 CS0 N"),
507		− PINCTRL_PIN(316, "PO ETM TRACE PKT0"),
508		− PINCTRL_PIN(317, "PO ETM TRACE PKT1"),
509		− PINCTRL_PIN(318, "PO ETM TRACE PKT2"),
510		− PINCTRL_PIN(319, "P PAD VDD 30"),
511		− PINCTRL_PIN(320, "P PAD GND 30"),
512		− PINCTRL_PIN(321, "P PAD VSSIO 44"),
513		− PINCTRL_PIN(322, "P PAD VDDIO 44"),
514		− PINCTRL_PIN(323, "PO ETM TRACE PKT3"),
515		− PINCTRL_PIN(324, "PO ETM TRACE PKT4"),
516		− PINCTRL_PIN(325, "PO ETM TRACE PKT5"),
517		− PINCTRL_PIN(326, "PO ETM TRACE PKT6"),
518		− PINCTRL_PIN(327, "PO ETM TRACE PKT7"),
519		− PINCTRL_PIN(328, "PO ETM PIPE STAT0"),
520		− PINCTRL_PIN(329, "P PAD VDD 26"),
521		− PINCTRL_PIN(330, "P PAD GND 26"),
522		− PINCTRL_PIN(331, "P PAD VSSIO 40"),
523		− PINCTRL_PIN(332, "P PAD VDDIO 40"),
524		− PINCTRL_PIN(333, "PO ETM PIPE STAT1"),
525		− PINCTRL_PIN(334, "PO ETM PIPE STAT2"),
526		− PINCTRL_PIN(335, "PO ETM TRACE CLK"),
527		− PINCTRL_PIN(336, "PO ETM TRACE SYNC"),
528		− PINCTRL_PIN(337, "PIO ACC GPIO 33"),
529		− PINCTRL_PIN(338, "PIO ACC GPIO 32"),
530		− PINCTRL_PIN(339, "PIO ACC GPIO 30"),
531		− PINCTRL_PIN(340, "PIO ACC GPIO 29"),
532		− PINCTRL_PIN(341, "P PAD VDDIO 17"),
533		− PINCTRL_PIN(342, "P PAD VSSIO 17"),
534		− PINCTRL_PIN(343, "P PAD GND 15"),
535		− PINCTRL_PIN(344, "P PAD VDD 15"),
536		− PINCTRL_PIN(345, "PIO ACC GPIO 28"),
537		− PINCTRL_PIN(346, "PIO ACC GPIO 27"),
538		− PINCTRL_PIN(347, "PIO ACC GPIO 16"),
539		− PINCTRL_PIN(348, "PI TAP TMS"),
540		− PINCTRL_PIN(349, "PI TAP TDI"),
541		− PINCTRL_PIN(350, "PO TAP TDO"),
542		− PINCTRL_PIN(351, "PI TAP RST N"),
543		− /* Pads along the left edge of the chip */
544		− PINCTRL_PIN(352, "PI EMU MODE 0"),
545		− PINCTRL_PIN(353, "PO TAP RET CLK"),
546		− PINCTRL_PIN(354, "PI TAP CLK"),
547		− PINCTRL_PIN(355, "PO EMIF 0 SD CS N"),
548		− PINCTRL_PIN(356, "PO EMIF 0 SD CAS N"),
549		− PINCTRL_PIN(357, "PO EMIF 0 SD WE N"),
550		− PINCTRL_PIN(358, "P PAD VDDIO 1"),
551		− PINCTRL_PIN(359, "P PAD VSSIO 1"),
552		− PINCTRL_PIN(360, "P PAD GND 1"),
553		− PINCTRL_PIN(361, "P PAD VDD 1"),
554		− PINCTRL_PIN(362, "PO EMIF 0 SD CKE"),
555		− PINCTRL_PIN(363, "PO EMIF 0 SD DQML"),
556		− PINCTRL_PIN(364, "PO EMIF 0 SD DQMU"),
557		− PINCTRL_PIN(365, "PO EMIF 0 SD RAS N"),
558		− PINCTRL_PIN(366, "PIO EMIF 0 D15"),
559		− PINCTRL_PIN(367, "PO EMIF 0 A15"),
560		− PINCTRL_PIN(368, "PIO EMIF 0 D14"),
561		− PINCTRL_PIN(369, "PO EMIF 0 A14"),
562		− PINCTRL_PIN(370, "PIO EMIF 0 D13"),
563		− PINCTRL_PIN(371, "PO EMIF 0 A13"),
564		− PINCTRL_PIN(372, "P PAD VDDIO 2"),
565		− PINCTRL_PIN(373, "P PAD VSSIO 2"),
566		− PINCTRL_PIN(374, "P PAD GND 2"),
567		− PINCTRL_PIN(375, "P PAD VDD 2"),
568		− PINCTRL_PIN(376, "PIO EMIF 0 D12"),
569		− PINCTRL_PIN(377, "PO EMIF 0 A12"),
570		− PINCTRL_PIN(378, "PIO EMIF 0 D11"),
571		− PINCTRL_PIN(379, "PO EMIF 0 A11"),
572		− PINCTRL_PIN(380, "PIO EMIF 0 D10"),
573		− PINCTRL_PIN(381, "PO EMIF 0 A10"),
574		− PINCTRL_PIN(382, "PIO EMIF 0 D09"),
575		− PINCTRL_PIN(383, "PO EMIF 0 A09"),
576		− PINCTRL_PIN(384, "PIO EMIF 0 D08"),
577		− PINCTRL_PIN(385, "PO EMIF 0 A08"),
578		− PINCTRL_PIN(386, "PIO EMIF 0 D07"),
579		− PINCTRL_PIN(387, "PO EMIF 0 A07"),
580		− PINCTRL_PIN(388, "P PAD VDDIO 3"),
581		− PINCTRL_PIN(389, "P PAD VSSIO 3"),
582		− PINCTRL_PIN(390, "P PAD GND 3"),
583		− PINCTRL_PIN(391, "P PAD VDD 3"),
584		− PINCTRL_PIN(392, "PO EFUSE RDOUT1"),
585		− PINCTRL_PIN(393, "PIO EMIF 0 D06"),
586		− PINCTRL_PIN(394, "PO EMIF 0 A06"),
587		− PINCTRL_PIN(395, "PIO EMIF 0 D05"),
588		− PINCTRL_PIN(396, "PO EMIF 0 A05"),
589		− PINCTRL_PIN(397, "PIO EMIF 0 D04"),
590		− PINCTRL_PIN(398, "PO EMIF 0 A04"),
591		− PINCTRL_PIN(399, "A PADS/A VDDCO1v82v5 GND 80U SF LIN VDDCO AF"),
592		− PINCTRL_PIN(400, "PWR VDDCO AF"),
593		− PINCTRL_PIN(401, "PWR EFUSE HV1"),
594		− PINCTRL_PIN(402, "P PAD VSSIO 4"),
595		− PINCTRL_PIN(403, "P PAD VDDIO 4"),
596		− PINCTRL_PIN(404, "P PAD GND 4"),
597		− PINCTRL_PIN(405, "P PAD VDD 4"),
598		− PINCTRL_PIN(406, "PIO EMIF 0 D03"),
599		− PINCTRL_PIN(407, "PO EMIF 0 A03"),
600		− PINCTRL_PIN(408, "PWR EFUSE HV2"),
601		− PINCTRL_PIN(409, "PWR EFUSE HV3"),
602		− PINCTRL_PIN(410, "PIO EMIF 0 D02"),
603		− PINCTRL_PIN(411, "PO EMIF 0 A02"),
604		− PINCTRL_PIN(412, "PIO EMIF 0 D01"),
605		− PINCTRL_PIN(413, "P PAD VDDIO 5"),
606		− PINCTRL_PIN(414, "P PAD VSSIO 5"),
607		− PINCTRL_PIN(415, "P PAD GND 5"),
608		− PINCTRL_PIN(416, "P PAD VDD 5"),
609		− PINCTRL_PIN(417, "PO EMIF 0 A01"),
610		− PINCTRL_PIN(418, "PIO EMIF 0 D00"),
611		− PINCTRL_PIN(419, "IF 0 SD CLK"),
612		− PINCTRL_PIN(420, "APP SPI CLK"),
613		− PINCTRL_PIN(421, "APP SPI DO"),
614		− PINCTRL_PIN(422, "APP SPI DI"),
615		− PINCTRL_PIN(423, "APP SPI CS0"),
616		− PINCTRL_PIN(424, "APP SPI CS1"),
617		− PINCTRL_PIN(425, "APP SPI CS2"),
618		− PINCTRL_PIN(426, "PIO APP GPIO 10"),
619		− PINCTRL_PIN(427, "P PAD VDDIO 41"),
620		− PINCTRL_PIN(428, "P PAD VSSIO 41"),
621		− PINCTRL_PIN(429, "P PAD GND 6"),
622		− PINCTRL_PIN(430, "P PAD VDD 6"),
623		− PINCTRL_PIN(431, "PIO ACC SDIO0 CMD"),
624		− PINCTRL_PIN(432, "PIO ACC SDIO0 CK"),
625		− PINCTRL_PIN(433, "PIO ACC SDIO0 D3"),
626		− PINCTRL_PIN(434, "PIO ACC SDIO0 D2"),
627		− PINCTRL_PIN(435, "PIO ACC SDIO0 D1"),
628		− PINCTRL_PIN(436, "PIO ACC SDIO0 D0"),
629		− PINCTRL_PIN(437, "PIO USB PU"),
630		− PINCTRL_PIN(438, "PIO USB SP"),
631		− PINCTRL_PIN(439, "PIO USB DAT VP"),
632		− PINCTRL_PIN(440, "PIO USB SE0 VM"),
633		− PINCTRL_PIN(441, "PIO USB OE"),
634		− PINCTRL_PIN(442, "PIO USB SUSP"),
635		− PINCTRL_PIN(443, "P PAD VSSIO 6"),
636		− PINCTRL_PIN(444, "P PAD VDDIO 6"),
637		− PINCTRL_PIN(445, "PIO USB PUEN"),
638		− PINCTRL_PIN(446, "PIO ACC UART0 RX"),
639		− PINCTRL_PIN(447, "PIO ACC UART0 TX"),
640		− PINCTRL_PIN(448, "PIO ACC UART0 CTS"),
641		− PINCTRL_PIN(449, "PIO ACC UART0 RTS"),
642		− PINCTRL_PIN(450, "PIO ACC UART3 RX"),
643		− PINCTRL_PIN(451, "PIO ACC UART3 TX"),
644		− PINCTRL_PIN(452, "PIO ACC UART3 CTS"),
645		− PINCTRL_PIN(453, "PIO ACC UART3 RTS"),
646		− PINCTRL_PIN(454, "PIO ACC IRDA TX"),
647		− PINCTRL_PIN(455, "P PAD VDDIO 7"),
648		− PINCTRL_PIN(456, "P PAD VSSIO 7"),
649		− PINCTRL_PIN(457, "P PAD GND 7"),
650		− PINCTRL_PIN(458, "P PAD VDD 7"),
651		− PINCTRL_PIN(459, "PIO ACC IRDA RX"),
652		− PINCTRL_PIN(460, "PIO ACC PCM I2S CLK"),
653		− PINCTRL_PIN(461, "PIO ACC PCM I2S WS"),
654		− PINCTRL_PIN(462, "PIO ACC PCM I2S DATA A"),
655		− PINCTRL_PIN(463, "PIO ACC PCM I2S DATA B"),
656		− PINCTRL_PIN(464, "PO SIM CLK"),
657		− PINCTRL_PIN(465, "PIO ACC IRDA SD"),
658		− PINCTRL_PIN(466, "PIO SIM DATA"),
659		−};
660		−
661		−/**
662		− * @dev: a pointer back to containing device
663		− * @virtbase: the offset to the controller in virtual memory
664		− */
665		−struct u300_pmx {
666		− struct device *dev;
667		− struct pinctrl_dev *pctl;
668		− void __iomem *virtbase;
669		−};
670		−
671		−/**
672		− * u300_pmx_registers - the array of registers read/written for each pinmux
673		− * shunt setting
674		− */
675		−static const u32 u300_pmx_registers[] = {
676		− U300_SYSCON_PMC1LR,
677		− U300_SYSCON_PMC1HR,
678		− U300_SYSCON_PMC2R,
679		− U300_SYSCON_PMC3R,
680		− U300_SYSCON_PMC4R,
681		−};
682		−
683		−/**
684		− * struct u300_pin_group - describes a U300 pin group
685		− * @name: the name of this specific pin group
686		− * @pins: an array of discrete physical pins used in this group, taken
687		− * from the driver-local pin enumeration space
688		− * @num_pins: the number of pins in this group array, i.e. the number of
689		− * elements in .pins so we can iterate over that array
690		− */
691		−struct u300_pin_group {
692		− const char *name;
693		− const unsigned int *pins;
694		− const unsigned num_pins;
695		−};
696		−
697		−/**
698		− * struct pmx_onmask - mask bits to enable/disable padmux
699		− * @mask: mask bits to disable
700		− * @val: mask bits to enable
701		− *
702		− * onmask lazy dog:
703		− * onmask = {
704		− * {"PMC1LR" mask, "PMC1LR" value},
705		− * {"PMC1HR" mask, "PMC1HR" value},
706		− * {"PMC2R" mask, "PMC2R" value},
707		− * {"PMC3R" mask, "PMC3R" value},
708		− * {"PMC4R" mask, "PMC4R" value}
709		− * }
710		− */
711		−struct u300_pmx_mask {
712		− u16 mask;
713		− u16 bits;
714		−};
715		−
716		−/* The chip power pins are VDD, GND, VDDIO and VSSIO */
717		−static const unsigned power_pins[] = { 0, 1, 3, 31, 46, 47, 49, 50, 61, 62, 63,
718		− 64, 78, 79, 80, 81, 92, 93, 94, 95, 101, 102, 103, 104, 115, 116, 117,
719		− 118, 130, 131, 132, 133, 145, 146, 147, 148, 159, 160, 172, 173, 174,
720		− 175, 187, 188, 189, 190, 201, 202, 211, 212, 213, 214, 215, 218, 223,
721		− 224, 225, 226, 231, 232, 237, 238, 239, 240, 245, 246, 251, 252, 256,
722		− 257, 258, 259, 264, 265, 270, 271, 276, 277, 278, 279, 284, 285, 290,
723		− 291, 295, 296, 299, 300, 301, 302, 303, 309, 310, 311, 312, 319, 320,
724		− 321, 322, 329, 330, 331, 332, 341, 342, 343, 344, 358, 359, 360, 361,
725		− 372, 373, 374, 375, 388, 389, 390, 391, 402, 403, 404, 405, 413, 414,
726		− 415, 416, 427, 428, 429, 430, 443, 444, 455, 456, 457, 458 };
727		−static const unsigned emif0_pins[] = { 355, 356, 357, 362, 363, 364, 365, 366,
728		− 367, 368, 369, 370, 371, 376, 377, 378, 379, 380, 381, 382, 383, 384,
729		− 385, 386, 387, 393, 394, 395, 396, 397, 398, 406, 407, 410, 411, 412,
730		− 417, 418 };
731		−static const unsigned emif1_pins[] = { 216, 217, 219, 220, 221, 222, 227, 228,
732		− 229, 230, 233, 234, 235, 236, 241, 242, 243, 244, 247, 248, 249, 250,
733		− 253, 254, 255, 260, 261, 262, 263, 266, 267, 268, 269, 272, 273, 274,
734		− 275, 280, 281, 282, 283, 286, 287, 288, 289, 292, 293, 294, 297, 298,
735		− 304, 305, 306, 307, 308, 313, 314, 315 };
736		−static const unsigned uart0_pins[] = { 134, 135, 136, 137 };
737		−static const unsigned mmc0_pins[] = { 166, 167, 168, 169, 170, 171, 176, 177 };
738		−static const unsigned spi0_pins[] = { 420, 421, 422, 423, 424, 425 };
739		−
740		−static const struct u300_pmx_mask emif0_mask[] = {
741		− {0, 0},
742		− {0, 0},
743		− {0, 0},
744		− {0, 0},
745		− {0, 0},
746		−};
747		−
748		−static const struct u300_pmx_mask emif1_mask[] = {
749		− /*
750		− * This connects the SDRAM to CS2 and a NAND flash to
751		− * CS0 on the EMIF.
752		− */
753		− {
754		− U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK \|
755		− U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK \|
756		− U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK \|
757		− U300_SYSCON_PMC1LR_EMIF_1_MASK,
758		− U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM \|
759		− U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC \|
760		− U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF \|
761		− U300_SYSCON_PMC1LR_EMIF_1_SDRAM0
762		− },
763		− {0, 0},
764		− {0, 0},
765		− {0, 0},
766		− {0, 0},
767		−};
768		−
769		−static const struct u300_pmx_mask uart0_mask[] = {
770		− {0, 0},
771		− {
772		− U300_SYSCON_PMC1HR_APP_UART0_1_MASK \|
773		− U300_SYSCON_PMC1HR_APP_UART0_2_MASK,
774		− U300_SYSCON_PMC1HR_APP_UART0_1_UART0 \|
775		− U300_SYSCON_PMC1HR_APP_UART0_2_UART0
776		− },
777		− {0, 0},
778		− {0, 0},
779		− {0, 0},
780		−};
781		−
782		−static const struct u300_pmx_mask mmc0_mask[] = {
783		− { U300_SYSCON_PMC1LR_MMCSD_MASK, U300_SYSCON_PMC1LR_MMCSD_MMCSD},
784		− {0, 0},
785		− {0, 0},
786		− {0, 0},
787		− { U300_SYSCON_PMC4R_APP_MISC_12_MASK,
788		− U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO }
789		−};
790		−
791		−static const struct u300_pmx_mask spi0_mask[] = {
792		− {0, 0},
793		− {
794		− U300_SYSCON_PMC1HR_APP_SPI_2_MASK \|
795		− U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK \|
796		− U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK,
797		− U300_SYSCON_PMC1HR_APP_SPI_2_SPI \|
798		− U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI \|
799		− U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI
800		− },
801		− {0, 0},
802		− {0, 0},
803		− {0, 0}
804		−};
805		−
806		−static const struct u300_pin_group u300_pin_groups[] = {
807		− {
808		− .name = "powergrp",
809		− .pins = power_pins,
810		− .num_pins = ARRAY_SIZE(power_pins),
811		− },
812		− {
813		− .name = "emif0grp",
814		− .pins = emif0_pins,
815		− .num_pins = ARRAY_SIZE(emif0_pins),
816		− },
817		− {
818		− .name = "emif1grp",
819		− .pins = emif1_pins,
820		− .num_pins = ARRAY_SIZE(emif1_pins),
821		− },
822		− {
823		− .name = "uart0grp",
824		− .pins = uart0_pins,
825		− .num_pins = ARRAY_SIZE(uart0_pins),
826		− },
827		− {
828		− .name = "mmc0grp",
829		− .pins = mmc0_pins,
830		− .num_pins = ARRAY_SIZE(mmc0_pins),
831		− },
832		− {
833		− .name = "spi0grp",
834		− .pins = spi0_pins,
835		− .num_pins = ARRAY_SIZE(spi0_pins),
836		− },
837		−};
838		−
839		−static int u300_get_groups_count(struct pinctrl_dev *pctldev)
840		−{
841		− return ARRAY_SIZE(u300_pin_groups);
842		−}
843		−
844		−static const char u300_get_group_name(struct pinctrl_dev pctldev,
845		− unsigned selector)
846		−{
847		− return u300_pin_groups[selector].name;
848		−}
849		−
850		−static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
851		− const unsigned **pins,
852		− unsigned *num_pins)
853		−{
854		− *pins = u300_pin_groups[selector].pins;
855		− *num_pins = u300_pin_groups[selector].num_pins;
856		− return 0;
857		−}
858		−
859		−static void u300_pin_dbg_show(struct pinctrl_dev pctldev, struct seq_file s,
860		− unsigned offset)
861		−{
862		− seq_printf(s, " " DRIVER_NAME);
863		−}
864		−
865		−static const struct pinctrl_ops u300_pctrl_ops = {
866		− .get_groups_count = u300_get_groups_count,
867		− .get_group_name = u300_get_group_name,
868		− .get_group_pins = u300_get_group_pins,
869		− .pin_dbg_show = u300_pin_dbg_show,
870		−};
871		−
872		−/*
873		− * Here we define the available functions and their corresponding pin groups
874		− */
875		−
876		−/**
877		− * struct u300_pmx_func - describes U300 pinmux functions
878		− * @name: the name of this specific function
879		− * @groups: corresponding pin groups
880		− * @onmask: bits to set to enable this when doing pin muxing
881		− */
882		−struct u300_pmx_func {
883		− const char *name;
884		− const char * const *groups;
885		− const unsigned num_groups;
886		− const struct u300_pmx_mask *mask;
887		−};
888		−
889		−static const char * const powergrps[] = { "powergrp" };
890		−static const char * const emif0grps[] = { "emif0grp" };
891		−static const char * const emif1grps[] = { "emif1grp" };
892		−static const char * const uart0grps[] = { "uart0grp" };
893		−static const char * const mmc0grps[] = { "mmc0grp" };
894		−static const char * const spi0grps[] = { "spi0grp" };
895		−
896		−static const struct u300_pmx_func u300_pmx_functions[] = {
897		− {
898		− .name = "power",
899		− .groups = powergrps,
900		− .num_groups = ARRAY_SIZE(powergrps),
901		− /* Mask is N/A */
902		− },
903		− {
904		− .name = "emif0",
905		− .groups = emif0grps,
906		− .num_groups = ARRAY_SIZE(emif0grps),
907		− .mask = emif0_mask,
908		− },
909		− {
910		− .name = "emif1",
911		− .groups = emif1grps,
912		− .num_groups = ARRAY_SIZE(emif1grps),
913		− .mask = emif1_mask,
914		− },
915		− {
916		− .name = "uart0",
917		− .groups = uart0grps,
918		− .num_groups = ARRAY_SIZE(uart0grps),
919		− .mask = uart0_mask,
920		− },
921		− {
922		− .name = "mmc0",
923		− .groups = mmc0grps,
924		− .num_groups = ARRAY_SIZE(mmc0grps),
925		− .mask = mmc0_mask,
926		− },
927		− {
928		− .name = "spi0",
929		− .groups = spi0grps,
930		− .num_groups = ARRAY_SIZE(spi0grps),
931		− .mask = spi0_mask,
932		− },
933		−};
934		−
935		−static void u300_pmx_endisable(struct u300_pmx *upmx, unsigned selector,
936		− bool enable)
937		−{
938		− u16 regval, val, mask;
939		− int i;
940		− const struct u300_pmx_mask *upmx_mask;
941		−
942		− upmx_mask = u300_pmx_functions[selector].mask;
943		− for (i = 0; i < ARRAY_SIZE(u300_pmx_registers); i++) {
944		− if (enable)
945		− val = upmx_mask->bits;
946		− else
947		− val = 0;
948		−
949		− mask = upmx_mask->mask;
950		− if (mask != 0) {
951		− regval = readw(upmx->virtbase + u300_pmx_registers[i]);
952		− regval &= ~mask;
953		− regval \|= val;
954		− writew(regval, upmx->virtbase + u300_pmx_registers[i]);
955		− }
956		− upmx_mask++;
957		− }
958		−}
959		−
960		−static int u300_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
961		− unsigned group)
962		−{
963		− struct u300_pmx *upmx;
964		−
965		− /* There is nothing to do with the power pins */
966		− if (selector == 0)
967		− return 0;
968		−
969		− upmx = pinctrl_dev_get_drvdata(pctldev);
970		− u300_pmx_endisable(upmx, selector, true);
971		−
972		− return 0;
973		−}
974		−
975		−static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
976		−{
977		− return ARRAY_SIZE(u300_pmx_functions);
978		−}
979		−
980		−static const char u300_pmx_get_func_name(struct pinctrl_dev pctldev,
981		− unsigned selector)
982		−{
983		− return u300_pmx_functions[selector].name;
984		−}
985		−
986		−static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
987		− const char * const **groups,
988		− unsigned * const num_groups)
989		−{
990		− *groups = u300_pmx_functions[selector].groups;
991		− *num_groups = u300_pmx_functions[selector].num_groups;
992		− return 0;
993		−}
994		−
995		−static const struct pinmux_ops u300_pmx_ops = {
996		− .get_functions_count = u300_pmx_get_funcs_count,
997		− .get_function_name = u300_pmx_get_func_name,
998		− .get_function_groups = u300_pmx_get_groups,
999		− .set_mux = u300_pmx_set_mux,
1000		−};
1001		−
1002		−static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1003		− unsigned long *config)
1004		−{
1005		− struct pinctrl_gpio_range *range =
1006		− pinctrl_find_gpio_range_from_pin(pctldev, pin);
1007		−
1008		− /* We get config for those pins we CAN get it for and that's it */
1009		− if (!range)
1010		− return -ENOTSUPP;
1011		−
1012		− return u300_gpio_config_get(range->gc,
1013		− (pin - range->pin_base + range->base),
1014		− config);
1015		−}
1016		−
1017		−static int u300_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1018		− unsigned long *configs, unsigned num_configs)
1019		−{
1020		− struct pinctrl_gpio_range *range =
1021		− pinctrl_find_gpio_range_from_pin(pctldev, pin);
1022		− int ret, i;
1023		−
1024		− if (!range)
1025		− return -EINVAL;
1026		−
1027		− for (i = 0; i < num_configs; i++) {
1028		− /* Note: none of these configurations take any argument */
1029		− ret = u300_gpio_config_set(range->gc,
1030		− (pin - range->pin_base + range->base),
1031		− pinconf_to_config_param(configs[i]));
1032		− if (ret)
1033		− return ret;
1034		− } /* for each config */
1035		−
1036		− return 0;
1037		−}
1038		−
1039		−static const struct pinconf_ops u300_pconf_ops = {
1040		− .is_generic = true,
1041		− .pin_config_get = u300_pin_config_get,
1042		− .pin_config_set = u300_pin_config_set,
1043		−};
1044		−
1045		−static struct pinctrl_desc u300_pmx_desc = {
1046		− .name = DRIVER_NAME,
1047		− .pins = u300_pads,
1048		− .npins = ARRAY_SIZE(u300_pads),
1049		− .pctlops = &u300_pctrl_ops,
1050		− .pmxops = &u300_pmx_ops,
1051		− .confops = &u300_pconf_ops,
1052		− .owner = THIS_MODULE,
1053		−};
1054		−
1055		−static int u300_pmx_probe(struct platform_device *pdev)
1056		−{
1057		− struct u300_pmx *upmx;
1058		−
1059		− /* Create state holders etc for this driver */
1060		− upmx = devm_kzalloc(&pdev->dev, sizeof(*upmx), GFP_KERNEL);
1061		− if (!upmx)
1062		− return -ENOMEM;
1063		−
1064		− upmx->dev = &pdev->dev;
1065		−
1066		− upmx->virtbase = devm_platform_ioremap_resource(pdev, 0);
1067		− if (IS_ERR(upmx->virtbase))
1068		− return PTR_ERR(upmx->virtbase);
1069		−
1070		− upmx->pctl = devm_pinctrl_register(&pdev->dev, &u300_pmx_desc, upmx);
1071		− if (IS_ERR(upmx->pctl)) {
1072		− dev_err(&pdev->dev, "could not register U300 pinmux driver\n");
1073		− return PTR_ERR(upmx->pctl);
1074		− }
1075		−
1076		− platform_set_drvdata(pdev, upmx);
1077		−
1078		− dev_info(&pdev->dev, "initialized U300 pin control driver\n");
1079		−
1080		− return 0;
1081		−}
1082		−
1083		−static const struct of_device_id u300_pinctrl_match[] = {
1084		− { .compatible = "stericsson,pinctrl-u300" },
1085		− {},
1086		−};
1087		−
1088		−
1089		−static struct platform_driver u300_pmx_driver = {
1090		− .driver = {
1091		− .name = DRIVER_NAME,
1092		− .of_match_table = u300_pinctrl_match,
1093		− },
1094		− .probe = u300_pmx_probe,
1095		−};
1096		−
1097		−static int __init u300_pmx_init(void)
1098		−{
1099		− return platform_driver_register(&u300_pmx_driver);
1100		−}
1101		−arch_initcall(u300_pmx_init);
1102		−
1103		−static void __exit u300_pmx_exit(void)
1104		−{
1105		− platform_driver_unregister(&u300_pmx_driver);
1106		−}
1107		−module_exit(u300_pmx_exit);
1108		−
1109		−MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
1110		−MODULE_DESCRIPTION("U300 pin control driver");
1111		−MODULE_LICENSE("GPL v2");

drivers/pinctrl/pinmux.c+1−1

@@ -564,7 +564,7 @@ static int pinmux_functions_show(struct seq_file s, void what) · 563 unmodified lines
564	564	continue;
565	565	}
566	566
567		− seq_printf(s, "function: %s, groups = [ ", func);
	567	+ seq_printf(s, "function %d: %s, groups = [ ", func_selector, func);
568	568	for (i = 0; i < num_groups; i++)
569	569	seq_printf(s, "%s ", groups[i]);
570	570	seq_puts(s, "]\n");

drivers/pinctrl/qcom/Kconfig+18−0

@@ -220,6 +220,15 @@ config PINCTRL_SC7280 · 219 unmodified lines
220	220	Qualcomm Technologies Inc TLMM block found on the Qualcomm
221	221	Technologies Inc SC7280 platform.
222	222
	223	+config PINCTRL_SC8180X
	224	+ tristate "Qualcomm Technologies Inc SC8180x pin controller driver"
	225	+ depends on GPIOLIB && OF
	226	+ select PINCTRL_MSM
	227	+ help
	228	+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
	229	+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
	230	+ Technologies Inc SC8180x platform.
	231	+
223	232	config PINCTRL_SDM660
224	233	tristate "Qualcomm Technologies Inc SDM660 pin controller driver"
225	234	depends on GPIOLIB && OF
@@ -265,6 +274,15 @@ config PINCTRL_SM8250 · 39 unmodified lines
265	274	Qualcomm Technologies Inc TLMM block found on the Qualcomm
266	275	Technologies Inc SM8250 platform.
267	276
	277	+config PINCTRL_SM8350
	278	+ tristate "Qualcomm Technologies Inc SM8350 pin controller driver"
	279	+ depends on GPIOLIB && OF
	280	+ select PINCTRL_MSM
	281	+ help
	282	+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
	283	+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
	284	+ Technologies Inc SM8350 platform.
	285	+
268	286	config PINCTRL_LPASS_LPI
269	287	tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"
270	288	select PINMUX

drivers/pinctrl/qcom/Makefile+2−0

@@ -26,9 +26,11 @@ obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o · 25 unmodified lines
26	26	obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
27	27	obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o
28	28	obj-$(CONFIG_PINCTRL_SC7280) += pinctrl-sc7280.o
	29	+obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o
29	30	obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
30	31	obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
31	32	obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
32	33	obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
33	34	obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
	35	+obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o
34	36	obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o

drivers/pinctrl/qcom/pinctrl-sc8180x.c+1624−0

@@ -0,0 +1,1624 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+/*
	3	+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
	4	+ * Copyright (c) 2020-2021, Linaro Ltd.
	5	+ */
	6	+
	7	+#include <linux/module.h>
	8	+#include <linux/of.h>
	9	+#include <linux/platform_device.h>
	10	+#include <linux/pinctrl/pinctrl.h>
	11	+
	12	+#include "pinctrl-msm.h"
	13	+
	14	+static const char * const sc8180x_tiles[] = {
	15	+ "south",
	16	+ "east",
	17	+ "west"
	18	+};
	19	+
	20	+enum {
	21	+ SOUTH,
	22	+ EAST,
	23	+ WEST
	24	+};
	25	+
	26	+#define FUNCTION(fname) \
	27	+ [msm_mux_##fname] = { \
	28	+ .name = #fname, \
	29	+ .groups = fname##_groups, \
	30	+ .ngroups = ARRAY_SIZE(fname##_groups), \
	31	+ }
	32	+
	33	+#define REG_SIZE 0x1000
	34	+#define PINGROUP_OFFSET(id, _tile, offset, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
	35	+ { \
	36	+ .name = "gpio" #id, \
	37	+ .pins = gpio##id##_pins, \
	38	+ .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
	39	+ .funcs = (int[]){ \
	40	+ msm_mux_gpio, /* gpio mode */ \
	41	+ msm_mux_##f1, \
	42	+ msm_mux_##f2, \
	43	+ msm_mux_##f3, \
	44	+ msm_mux_##f4, \
	45	+ msm_mux_##f5, \
	46	+ msm_mux_##f6, \
	47	+ msm_mux_##f7, \
	48	+ msm_mux_##f8, \
	49	+ msm_mux_##f9 \
	50	+ }, \
	51	+ .nfuncs = 10, \
	52	+ .ctl_reg = REG_SIZE * id + offset, \
	53	+ .io_reg = REG_SIZE * id + 0x4 + offset, \
	54	+ .intr_cfg_reg = REG_SIZE * id + 0x8 + offset, \
	55	+ .intr_status_reg = REG_SIZE * id + 0xc + offset,\
	56	+ .intr_target_reg = REG_SIZE * id + 0x8 + offset,\
	57	+ .tile = _tile, \
	58	+ .mux_bit = 2, \
	59	+ .pull_bit = 0, \
	60	+ .drv_bit = 6, \
	61	+ .oe_bit = 9, \
	62	+ .in_bit = 0, \
	63	+ .out_bit = 1, \
	64	+ .intr_enable_bit = 0, \
	65	+ .intr_status_bit = 0, \
	66	+ .intr_target_bit = 5, \
	67	+ .intr_target_kpss_val = 3, \
	68	+ .intr_raw_status_bit = 4, \
	69	+ .intr_polarity_bit = 1, \
	70	+ .intr_detection_bit = 2, \
	71	+ .intr_detection_width = 2, \
	72	+ }
	73	+
	74	+#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
	75	+ PINGROUP_OFFSET(id, _tile, 0x0, f1, f2, f3, f4, f5, f6, f7, f8, f9)
	76	+
	77	+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
	78	+ { \
	79	+ .name = #pg_name, \
	80	+ .pins = pg_name##_pins, \
	81	+ .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
	82	+ .ctl_reg = ctl, \
	83	+ .io_reg = 0, \
	84	+ .intr_cfg_reg = 0, \
	85	+ .intr_status_reg = 0, \
	86	+ .intr_target_reg = 0, \
	87	+ .tile = EAST, \
	88	+ .mux_bit = -1, \
	89	+ .pull_bit = pull, \
	90	+ .drv_bit = drv, \
	91	+ .oe_bit = -1, \
	92	+ .in_bit = -1, \
	93	+ .out_bit = -1, \
	94	+ .intr_enable_bit = -1, \
	95	+ .intr_status_bit = -1, \
	96	+ .intr_target_bit = -1, \
	97	+ .intr_raw_status_bit = -1, \
	98	+ .intr_polarity_bit = -1, \
	99	+ .intr_detection_bit = -1, \
	100	+ .intr_detection_width = -1, \
	101	+ }
	102	+
	103	+#define UFS_RESET(pg_name) \
	104	+ { \
	105	+ .name = #pg_name, \
	106	+ .pins = pg_name##_pins, \
	107	+ .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
	108	+ .ctl_reg = 0xb6000, \
	109	+ .io_reg = 0xb6004, \
	110	+ .intr_cfg_reg = 0, \
	111	+ .intr_status_reg = 0, \
	112	+ .intr_target_reg = 0, \
	113	+ .tile = SOUTH, \
	114	+ .mux_bit = -1, \
	115	+ .pull_bit = 3, \
	116	+ .drv_bit = 0, \
	117	+ .oe_bit = -1, \
	118	+ .in_bit = -1, \
	119	+ .out_bit = 0, \
	120	+ .intr_enable_bit = -1, \
	121	+ .intr_status_bit = -1, \
	122	+ .intr_target_bit = -1, \
	123	+ .intr_raw_status_bit = -1, \
	124	+ .intr_polarity_bit = -1, \
	125	+ .intr_detection_bit = -1, \
	126	+ .intr_detection_width = -1, \
	127	+ }
	128	+static const struct pinctrl_pin_desc sc8180x_pins[] = {
	129	+ PINCTRL_PIN(0, "GPIO_0"),
	130	+ PINCTRL_PIN(1, "GPIO_1"),
	131	+ PINCTRL_PIN(2, "GPIO_2"),
	132	+ PINCTRL_PIN(3, "GPIO_3"),
	133	+ PINCTRL_PIN(4, "GPIO_4"),
	134	+ PINCTRL_PIN(5, "GPIO_5"),
	135	+ PINCTRL_PIN(6, "GPIO_6"),
	136	+ PINCTRL_PIN(7, "GPIO_7"),
	137	+ PINCTRL_PIN(8, "GPIO_8"),
	138	+ PINCTRL_PIN(9, "GPIO_9"),
	139	+ PINCTRL_PIN(10, "GPIO_10"),
	140	+ PINCTRL_PIN(11, "GPIO_11"),
	141	+ PINCTRL_PIN(12, "GPIO_12"),
	142	+ PINCTRL_PIN(13, "GPIO_13"),
	143	+ PINCTRL_PIN(14, "GPIO_14"),
	144	+ PINCTRL_PIN(15, "GPIO_15"),
	145	+ PINCTRL_PIN(16, "GPIO_16"),
	146	+ PINCTRL_PIN(17, "GPIO_17"),
	147	+ PINCTRL_PIN(18, "GPIO_18"),
	148	+ PINCTRL_PIN(19, "GPIO_19"),
	149	+ PINCTRL_PIN(20, "GPIO_20"),
	150	+ PINCTRL_PIN(21, "GPIO_21"),
	151	+ PINCTRL_PIN(22, "GPIO_22"),
	152	+ PINCTRL_PIN(23, "GPIO_23"),
	153	+ PINCTRL_PIN(24, "GPIO_24"),
	154	+ PINCTRL_PIN(25, "GPIO_25"),
	155	+ PINCTRL_PIN(26, "GPIO_26"),
	156	+ PINCTRL_PIN(27, "GPIO_27"),
	157	+ PINCTRL_PIN(28, "GPIO_28"),
	158	+ PINCTRL_PIN(29, "GPIO_29"),
	159	+ PINCTRL_PIN(30, "GPIO_30"),
	160	+ PINCTRL_PIN(31, "GPIO_31"),
	161	+ PINCTRL_PIN(32, "GPIO_32"),
	162	+ PINCTRL_PIN(33, "GPIO_33"),
	163	+ PINCTRL_PIN(34, "GPIO_34"),
	164	+ PINCTRL_PIN(35, "GPIO_35"),
	165	+ PINCTRL_PIN(36, "GPIO_36"),
	166	+ PINCTRL_PIN(37, "GPIO_37"),
	167	+ PINCTRL_PIN(38, "GPIO_38"),
	168	+ PINCTRL_PIN(39, "GPIO_39"),
	169	+ PINCTRL_PIN(40, "GPIO_40"),
	170	+ PINCTRL_PIN(41, "GPIO_41"),
	171	+ PINCTRL_PIN(42, "GPIO_42"),
	172	+ PINCTRL_PIN(43, "GPIO_43"),
	173	+ PINCTRL_PIN(44, "GPIO_44"),
	174	+ PINCTRL_PIN(45, "GPIO_45"),
	175	+ PINCTRL_PIN(46, "GPIO_46"),
	176	+ PINCTRL_PIN(47, "GPIO_47"),
	177	+ PINCTRL_PIN(48, "GPIO_48"),
	178	+ PINCTRL_PIN(49, "GPIO_49"),
	179	+ PINCTRL_PIN(50, "GPIO_50"),
	180	+ PINCTRL_PIN(51, "GPIO_51"),
	181	+ PINCTRL_PIN(52, "GPIO_52"),
	182	+ PINCTRL_PIN(53, "GPIO_53"),
	183	+ PINCTRL_PIN(54, "GPIO_54"),
	184	+ PINCTRL_PIN(55, "GPIO_55"),
	185	+ PINCTRL_PIN(56, "GPIO_56"),
	186	+ PINCTRL_PIN(57, "GPIO_57"),
	187	+ PINCTRL_PIN(58, "GPIO_58"),
	188	+ PINCTRL_PIN(59, "GPIO_59"),
	189	+ PINCTRL_PIN(60, "GPIO_60"),
	190	+ PINCTRL_PIN(61, "GPIO_61"),
	191	+ PINCTRL_PIN(62, "GPIO_62"),
	192	+ PINCTRL_PIN(63, "GPIO_63"),
	193	+ PINCTRL_PIN(64, "GPIO_64"),
	194	+ PINCTRL_PIN(65, "GPIO_65"),
	195	+ PINCTRL_PIN(66, "GPIO_66"),
	196	+ PINCTRL_PIN(67, "GPIO_67"),
	197	+ PINCTRL_PIN(68, "GPIO_68"),
	198	+ PINCTRL_PIN(69, "GPIO_69"),
	199	+ PINCTRL_PIN(70, "GPIO_70"),
	200	+ PINCTRL_PIN(71, "GPIO_71"),
	201	+ PINCTRL_PIN(72, "GPIO_72"),
	202	+ PINCTRL_PIN(73, "GPIO_73"),
	203	+ PINCTRL_PIN(74, "GPIO_74"),
	204	+ PINCTRL_PIN(75, "GPIO_75"),
	205	+ PINCTRL_PIN(76, "GPIO_76"),
	206	+ PINCTRL_PIN(77, "GPIO_77"),
	207	+ PINCTRL_PIN(78, "GPIO_78"),
	208	+ PINCTRL_PIN(79, "GPIO_79"),
	209	+ PINCTRL_PIN(80, "GPIO_80"),
	210	+ PINCTRL_PIN(81, "GPIO_81"),
	211	+ PINCTRL_PIN(82, "GPIO_82"),
	212	+ PINCTRL_PIN(83, "GPIO_83"),
	213	+ PINCTRL_PIN(84, "GPIO_84"),
	214	+ PINCTRL_PIN(85, "GPIO_85"),
	215	+ PINCTRL_PIN(86, "GPIO_86"),
	216	+ PINCTRL_PIN(87, "GPIO_87"),
	217	+ PINCTRL_PIN(88, "GPIO_88"),
	218	+ PINCTRL_PIN(89, "GPIO_89"),
	219	+ PINCTRL_PIN(90, "GPIO_90"),
	220	+ PINCTRL_PIN(91, "GPIO_91"),
	221	+ PINCTRL_PIN(92, "GPIO_92"),
	222	+ PINCTRL_PIN(93, "GPIO_93"),
	223	+ PINCTRL_PIN(94, "GPIO_94"),
	224	+ PINCTRL_PIN(95, "GPIO_95"),
	225	+ PINCTRL_PIN(96, "GPIO_96"),
	226	+ PINCTRL_PIN(97, "GPIO_97"),
	227	+ PINCTRL_PIN(98, "GPIO_98"),
	228	+ PINCTRL_PIN(99, "GPIO_99"),
	229	+ PINCTRL_PIN(100, "GPIO_100"),
	230	+ PINCTRL_PIN(101, "GPIO_101"),
	231	+ PINCTRL_PIN(102, "GPIO_102"),
	232	+ PINCTRL_PIN(103, "GPIO_103"),
	233	+ PINCTRL_PIN(104, "GPIO_104"),
	234	+ PINCTRL_PIN(105, "GPIO_105"),
	235	+ PINCTRL_PIN(106, "GPIO_106"),
	236	+ PINCTRL_PIN(107, "GPIO_107"),
	237	+ PINCTRL_PIN(108, "GPIO_108"),
	238	+ PINCTRL_PIN(109, "GPIO_109"),
	239	+ PINCTRL_PIN(110, "GPIO_110"),
	240	+ PINCTRL_PIN(111, "GPIO_111"),
	241	+ PINCTRL_PIN(112, "GPIO_112"),
	242	+ PINCTRL_PIN(113, "GPIO_113"),
	243	+ PINCTRL_PIN(114, "GPIO_114"),
	244	+ PINCTRL_PIN(115, "GPIO_115"),
	245	+ PINCTRL_PIN(116, "GPIO_116"),
	246	+ PINCTRL_PIN(117, "GPIO_117"),
	247	+ PINCTRL_PIN(118, "GPIO_118"),
	248	+ PINCTRL_PIN(119, "GPIO_119"),
	249	+ PINCTRL_PIN(120, "GPIO_120"),
	250	+ PINCTRL_PIN(121, "GPIO_121"),
	251	+ PINCTRL_PIN(122, "GPIO_122"),
	252	+ PINCTRL_PIN(123, "GPIO_123"),
	253	+ PINCTRL_PIN(124, "GPIO_124"),
	254	+ PINCTRL_PIN(125, "GPIO_125"),
	255	+ PINCTRL_PIN(126, "GPIO_126"),
	256	+ PINCTRL_PIN(127, "GPIO_127"),
	257	+ PINCTRL_PIN(128, "GPIO_128"),
	258	+ PINCTRL_PIN(129, "GPIO_129"),
	259	+ PINCTRL_PIN(130, "GPIO_130"),
	260	+ PINCTRL_PIN(131, "GPIO_131"),
	261	+ PINCTRL_PIN(132, "GPIO_132"),
	262	+ PINCTRL_PIN(133, "GPIO_133"),
	263	+ PINCTRL_PIN(134, "GPIO_134"),
	264	+ PINCTRL_PIN(135, "GPIO_135"),
	265	+ PINCTRL_PIN(136, "GPIO_136"),
	266	+ PINCTRL_PIN(137, "GPIO_137"),
	267	+ PINCTRL_PIN(138, "GPIO_138"),
	268	+ PINCTRL_PIN(139, "GPIO_139"),
	269	+ PINCTRL_PIN(140, "GPIO_140"),
	270	+ PINCTRL_PIN(141, "GPIO_141"),
	271	+ PINCTRL_PIN(142, "GPIO_142"),
	272	+ PINCTRL_PIN(143, "GPIO_143"),
	273	+ PINCTRL_PIN(144, "GPIO_144"),
	274	+ PINCTRL_PIN(145, "GPIO_145"),
	275	+ PINCTRL_PIN(146, "GPIO_146"),
	276	+ PINCTRL_PIN(147, "GPIO_147"),
	277	+ PINCTRL_PIN(148, "GPIO_148"),
	278	+ PINCTRL_PIN(149, "GPIO_149"),
	279	+ PINCTRL_PIN(150, "GPIO_150"),
	280	+ PINCTRL_PIN(151, "GPIO_151"),
	281	+ PINCTRL_PIN(152, "GPIO_152"),
	282	+ PINCTRL_PIN(153, "GPIO_153"),
	283	+ PINCTRL_PIN(154, "GPIO_154"),
	284	+ PINCTRL_PIN(155, "GPIO_155"),
	285	+ PINCTRL_PIN(156, "GPIO_156"),
	286	+ PINCTRL_PIN(157, "GPIO_157"),
	287	+ PINCTRL_PIN(158, "GPIO_158"),
	288	+ PINCTRL_PIN(159, "GPIO_159"),
	289	+ PINCTRL_PIN(160, "GPIO_160"),
	290	+ PINCTRL_PIN(161, "GPIO_161"),
	291	+ PINCTRL_PIN(162, "GPIO_162"),
	292	+ PINCTRL_PIN(163, "GPIO_163"),
	293	+ PINCTRL_PIN(164, "GPIO_164"),
	294	+ PINCTRL_PIN(165, "GPIO_165"),
	295	+ PINCTRL_PIN(166, "GPIO_166"),
	296	+ PINCTRL_PIN(167, "GPIO_167"),
	297	+ PINCTRL_PIN(168, "GPIO_168"),
	298	+ PINCTRL_PIN(169, "GPIO_169"),
	299	+ PINCTRL_PIN(170, "GPIO_170"),
	300	+ PINCTRL_PIN(171, "GPIO_171"),
	301	+ PINCTRL_PIN(172, "GPIO_172"),
	302	+ PINCTRL_PIN(173, "GPIO_173"),
	303	+ PINCTRL_PIN(174, "GPIO_174"),
	304	+ PINCTRL_PIN(175, "GPIO_175"),
	305	+ PINCTRL_PIN(176, "GPIO_176"),
	306	+ PINCTRL_PIN(177, "GPIO_177"),
	307	+ PINCTRL_PIN(178, "GPIO_178"),
	308	+ PINCTRL_PIN(179, "GPIO_179"),
	309	+ PINCTRL_PIN(180, "GPIO_180"),
	310	+ PINCTRL_PIN(181, "GPIO_181"),
	311	+ PINCTRL_PIN(182, "GPIO_182"),
	312	+ PINCTRL_PIN(183, "GPIO_183"),
	313	+ PINCTRL_PIN(184, "GPIO_184"),
	314	+ PINCTRL_PIN(185, "GPIO_185"),
	315	+ PINCTRL_PIN(186, "GPIO_186"),
	316	+ PINCTRL_PIN(187, "GPIO_187"),
	317	+ PINCTRL_PIN(188, "GPIO_188"),
	318	+ PINCTRL_PIN(189, "GPIO_189"),
	319	+ PINCTRL_PIN(190, "UFS_RESET"),
	320	+ PINCTRL_PIN(191, "SDC2_CLK"),
	321	+ PINCTRL_PIN(192, "SDC2_CMD"),
	322	+ PINCTRL_PIN(193, "SDC2_DATA"),
	323	+};
	324	+
	325	+#define DECLARE_MSM_GPIO_PINS(pin) \
	326	+ static const unsigned int gpio##pin##_pins[] = { pin }
	327	+DECLARE_MSM_GPIO_PINS(0);
	328	+DECLARE_MSM_GPIO_PINS(1);
	329	+DECLARE_MSM_GPIO_PINS(2);
	330	+DECLARE_MSM_GPIO_PINS(3);
	331	+DECLARE_MSM_GPIO_PINS(4);
	332	+DECLARE_MSM_GPIO_PINS(5);
	333	+DECLARE_MSM_GPIO_PINS(6);
	334	+DECLARE_MSM_GPIO_PINS(7);
	335	+DECLARE_MSM_GPIO_PINS(8);
	336	+DECLARE_MSM_GPIO_PINS(9);
	337	+DECLARE_MSM_GPIO_PINS(10);
	338	+DECLARE_MSM_GPIO_PINS(11);
	339	+DECLARE_MSM_GPIO_PINS(12);
	340	+DECLARE_MSM_GPIO_PINS(13);
	341	+DECLARE_MSM_GPIO_PINS(14);
	342	+DECLARE_MSM_GPIO_PINS(15);
	343	+DECLARE_MSM_GPIO_PINS(16);
	344	+DECLARE_MSM_GPIO_PINS(17);
	345	+DECLARE_MSM_GPIO_PINS(18);
	346	+DECLARE_MSM_GPIO_PINS(19);
	347	+DECLARE_MSM_GPIO_PINS(20);
	348	+DECLARE_MSM_GPIO_PINS(21);
	349	+DECLARE_MSM_GPIO_PINS(22);
	350	+DECLARE_MSM_GPIO_PINS(23);
	351	+DECLARE_MSM_GPIO_PINS(24);
	352	+DECLARE_MSM_GPIO_PINS(25);
	353	+DECLARE_MSM_GPIO_PINS(26);
	354	+DECLARE_MSM_GPIO_PINS(27);
	355	+DECLARE_MSM_GPIO_PINS(28);
	356	+DECLARE_MSM_GPIO_PINS(29);
	357	+DECLARE_MSM_GPIO_PINS(30);
	358	+DECLARE_MSM_GPIO_PINS(31);
	359	+DECLARE_MSM_GPIO_PINS(32);
	360	+DECLARE_MSM_GPIO_PINS(33);
	361	+DECLARE_MSM_GPIO_PINS(34);
	362	+DECLARE_MSM_GPIO_PINS(35);
	363	+DECLARE_MSM_GPIO_PINS(36);
	364	+DECLARE_MSM_GPIO_PINS(37);
	365	+DECLARE_MSM_GPIO_PINS(38);
	366	+DECLARE_MSM_GPIO_PINS(39);
	367	+DECLARE_MSM_GPIO_PINS(40);
	368	+DECLARE_MSM_GPIO_PINS(41);
	369	+DECLARE_MSM_GPIO_PINS(42);
	370	+DECLARE_MSM_GPIO_PINS(43);
	371	+DECLARE_MSM_GPIO_PINS(44);
	372	+DECLARE_MSM_GPIO_PINS(45);
	373	+DECLARE_MSM_GPIO_PINS(46);
	374	+DECLARE_MSM_GPIO_PINS(47);
	375	+DECLARE_MSM_GPIO_PINS(48);
	376	+DECLARE_MSM_GPIO_PINS(49);
	377	+DECLARE_MSM_GPIO_PINS(50);
	378	+DECLARE_MSM_GPIO_PINS(51);
	379	+DECLARE_MSM_GPIO_PINS(52);
	380	+DECLARE_MSM_GPIO_PINS(53);
	381	+DECLARE_MSM_GPIO_PINS(54);
	382	+DECLARE_MSM_GPIO_PINS(55);
	383	+DECLARE_MSM_GPIO_PINS(56);
	384	+DECLARE_MSM_GPIO_PINS(57);
	385	+DECLARE_MSM_GPIO_PINS(58);
	386	+DECLARE_MSM_GPIO_PINS(59);
	387	+DECLARE_MSM_GPIO_PINS(60);
	388	+DECLARE_MSM_GPIO_PINS(61);
	389	+DECLARE_MSM_GPIO_PINS(62);
	390	+DECLARE_MSM_GPIO_PINS(63);
	391	+DECLARE_MSM_GPIO_PINS(64);
	392	+DECLARE_MSM_GPIO_PINS(65);
	393	+DECLARE_MSM_GPIO_PINS(66);
	394	+DECLARE_MSM_GPIO_PINS(67);
	395	+DECLARE_MSM_GPIO_PINS(68);
	396	+DECLARE_MSM_GPIO_PINS(69);
	397	+DECLARE_MSM_GPIO_PINS(70);
	398	+DECLARE_MSM_GPIO_PINS(71);
	399	+DECLARE_MSM_GPIO_PINS(72);
	400	+DECLARE_MSM_GPIO_PINS(73);
	401	+DECLARE_MSM_GPIO_PINS(74);
	402	+DECLARE_MSM_GPIO_PINS(75);
	403	+DECLARE_MSM_GPIO_PINS(76);
	404	+DECLARE_MSM_GPIO_PINS(77);
	405	+DECLARE_MSM_GPIO_PINS(78);
	406	+DECLARE_MSM_GPIO_PINS(79);
	407	+DECLARE_MSM_GPIO_PINS(80);
	408	+DECLARE_MSM_GPIO_PINS(81);
	409	+DECLARE_MSM_GPIO_PINS(82);
	410	+DECLARE_MSM_GPIO_PINS(83);
	411	+DECLARE_MSM_GPIO_PINS(84);
	412	+DECLARE_MSM_GPIO_PINS(85);
	413	+DECLARE_MSM_GPIO_PINS(86);
	414	+DECLARE_MSM_GPIO_PINS(87);
	415	+DECLARE_MSM_GPIO_PINS(88);
	416	+DECLARE_MSM_GPIO_PINS(89);
	417	+DECLARE_MSM_GPIO_PINS(90);
	418	+DECLARE_MSM_GPIO_PINS(91);
	419	+DECLARE_MSM_GPIO_PINS(92);
	420	+DECLARE_MSM_GPIO_PINS(93);
	421	+DECLARE_MSM_GPIO_PINS(94);
	422	+DECLARE_MSM_GPIO_PINS(95);
	423	+DECLARE_MSM_GPIO_PINS(96);
	424	+DECLARE_MSM_GPIO_PINS(97);
	425	+DECLARE_MSM_GPIO_PINS(98);
	426	+DECLARE_MSM_GPIO_PINS(99);
	427	+DECLARE_MSM_GPIO_PINS(100);
	428	+DECLARE_MSM_GPIO_PINS(101);
	429	+DECLARE_MSM_GPIO_PINS(102);
	430	+DECLARE_MSM_GPIO_PINS(103);
	431	+DECLARE_MSM_GPIO_PINS(104);
	432	+DECLARE_MSM_GPIO_PINS(105);
	433	+DECLARE_MSM_GPIO_PINS(106);
	434	+DECLARE_MSM_GPIO_PINS(107);
	435	+DECLARE_MSM_GPIO_PINS(108);
	436	+DECLARE_MSM_GPIO_PINS(109);
	437	+DECLARE_MSM_GPIO_PINS(110);
	438	+DECLARE_MSM_GPIO_PINS(111);
	439	+DECLARE_MSM_GPIO_PINS(112);
	440	+DECLARE_MSM_GPIO_PINS(113);
	441	+DECLARE_MSM_GPIO_PINS(114);
	442	+DECLARE_MSM_GPIO_PINS(115);
	443	+DECLARE_MSM_GPIO_PINS(116);
	444	+DECLARE_MSM_GPIO_PINS(117);
	445	+DECLARE_MSM_GPIO_PINS(118);
	446	+DECLARE_MSM_GPIO_PINS(119);
	447	+DECLARE_MSM_GPIO_PINS(120);
	448	+DECLARE_MSM_GPIO_PINS(121);
	449	+DECLARE_MSM_GPIO_PINS(122);
	450	+DECLARE_MSM_GPIO_PINS(123);
	451	+DECLARE_MSM_GPIO_PINS(124);
	452	+DECLARE_MSM_GPIO_PINS(125);
	453	+DECLARE_MSM_GPIO_PINS(126);
	454	+DECLARE_MSM_GPIO_PINS(127);
	455	+DECLARE_MSM_GPIO_PINS(128);
	456	+DECLARE_MSM_GPIO_PINS(129);
	457	+DECLARE_MSM_GPIO_PINS(130);
	458	+DECLARE_MSM_GPIO_PINS(131);
	459	+DECLARE_MSM_GPIO_PINS(132);
	460	+DECLARE_MSM_GPIO_PINS(133);
	461	+DECLARE_MSM_GPIO_PINS(134);
	462	+DECLARE_MSM_GPIO_PINS(135);
	463	+DECLARE_MSM_GPIO_PINS(136);
	464	+DECLARE_MSM_GPIO_PINS(137);
	465	+DECLARE_MSM_GPIO_PINS(138);
	466	+DECLARE_MSM_GPIO_PINS(139);
	467	+DECLARE_MSM_GPIO_PINS(140);
	468	+DECLARE_MSM_GPIO_PINS(141);
	469	+DECLARE_MSM_GPIO_PINS(142);
	470	+DECLARE_MSM_GPIO_PINS(143);
	471	+DECLARE_MSM_GPIO_PINS(144);
	472	+DECLARE_MSM_GPIO_PINS(145);
	473	+DECLARE_MSM_GPIO_PINS(146);
	474	+DECLARE_MSM_GPIO_PINS(147);
	475	+DECLARE_MSM_GPIO_PINS(148);
	476	+DECLARE_MSM_GPIO_PINS(149);
	477	+DECLARE_MSM_GPIO_PINS(150);
	478	+DECLARE_MSM_GPIO_PINS(151);
	479	+DECLARE_MSM_GPIO_PINS(152);
	480	+DECLARE_MSM_GPIO_PINS(153);
	481	+DECLARE_MSM_GPIO_PINS(154);
	482	+DECLARE_MSM_GPIO_PINS(155);
	483	+DECLARE_MSM_GPIO_PINS(156);
	484	+DECLARE_MSM_GPIO_PINS(157);
	485	+DECLARE_MSM_GPIO_PINS(158);
	486	+DECLARE_MSM_GPIO_PINS(159);
	487	+DECLARE_MSM_GPIO_PINS(160);
	488	+DECLARE_MSM_GPIO_PINS(161);
	489	+DECLARE_MSM_GPIO_PINS(162);
	490	+DECLARE_MSM_GPIO_PINS(163);
	491	+DECLARE_MSM_GPIO_PINS(164);
	492	+DECLARE_MSM_GPIO_PINS(165);
	493	+DECLARE_MSM_GPIO_PINS(166);
	494	+DECLARE_MSM_GPIO_PINS(167);
	495	+DECLARE_MSM_GPIO_PINS(168);
	496	+DECLARE_MSM_GPIO_PINS(169);
	497	+DECLARE_MSM_GPIO_PINS(170);
	498	+DECLARE_MSM_GPIO_PINS(171);
	499	+DECLARE_MSM_GPIO_PINS(172);
	500	+DECLARE_MSM_GPIO_PINS(173);
	501	+DECLARE_MSM_GPIO_PINS(174);
	502	+DECLARE_MSM_GPIO_PINS(175);
	503	+DECLARE_MSM_GPIO_PINS(176);
	504	+DECLARE_MSM_GPIO_PINS(177);
	505	+DECLARE_MSM_GPIO_PINS(178);
	506	+DECLARE_MSM_GPIO_PINS(179);
	507	+DECLARE_MSM_GPIO_PINS(180);
	508	+DECLARE_MSM_GPIO_PINS(181);
	509	+DECLARE_MSM_GPIO_PINS(182);
	510	+DECLARE_MSM_GPIO_PINS(183);
	511	+DECLARE_MSM_GPIO_PINS(184);
	512	+DECLARE_MSM_GPIO_PINS(185);
	513	+DECLARE_MSM_GPIO_PINS(186);
	514	+DECLARE_MSM_GPIO_PINS(187);
	515	+DECLARE_MSM_GPIO_PINS(188);
	516	+DECLARE_MSM_GPIO_PINS(189);
	517	+
	518	+static const unsigned int sdc2_clk_pins[] = { 190 };
	519	+static const unsigned int sdc2_cmd_pins[] = { 191 };
	520	+static const unsigned int sdc2_data_pins[] = { 192 };
	521	+static const unsigned int ufs_reset_pins[] = { 193 };
	522	+
	523	+enum sc8180x_functions {
	524	+ msm_mux_adsp_ext,
	525	+ msm_mux_agera_pll,
	526	+ msm_mux_aoss_cti,
	527	+ msm_mux_atest_char,
	528	+ msm_mux_atest_tsens,
	529	+ msm_mux_atest_tsens2,
	530	+ msm_mux_atest_usb0,
	531	+ msm_mux_atest_usb1,
	532	+ msm_mux_atest_usb2,
	533	+ msm_mux_atest_usb3,
	534	+ msm_mux_atest_usb4,
	535	+ msm_mux_audio_ref,
	536	+ msm_mux_btfm_slimbus,
	537	+ msm_mux_cam_mclk,
	538	+ msm_mux_cci_async,
	539	+ msm_mux_cci_i2c,
	540	+ msm_mux_cci_timer0,
	541	+ msm_mux_cci_timer1,
	542	+ msm_mux_cci_timer2,
	543	+ msm_mux_cci_timer3,
	544	+ msm_mux_cci_timer4,
	545	+ msm_mux_cci_timer5,
	546	+ msm_mux_cci_timer6,
	547	+ msm_mux_cci_timer7,
	548	+ msm_mux_cci_timer8,
	549	+ msm_mux_cci_timer9,
	550	+ msm_mux_cri_trng,
	551	+ msm_mux_dbg_out,
	552	+ msm_mux_ddr_bist,
	553	+ msm_mux_ddr_pxi,
	554	+ msm_mux_debug_hot,
	555	+ msm_mux_dp_hot,
	556	+ msm_mux_edp_hot,
	557	+ msm_mux_edp_lcd,
	558	+ msm_mux_emac_phy,
	559	+ msm_mux_emac_pps,
	560	+ msm_mux_gcc_gp1,
	561	+ msm_mux_gcc_gp2,
	562	+ msm_mux_gcc_gp3,
	563	+ msm_mux_gcc_gp4,
	564	+ msm_mux_gcc_gp5,
	565	+ msm_mux_gpio,
	566	+ msm_mux_gps,
	567	+ msm_mux_grfc,
	568	+ msm_mux_hs1_mi2s,
	569	+ msm_mux_hs2_mi2s,
	570	+ msm_mux_hs3_mi2s,
	571	+ msm_mux_jitter_bist,
	572	+ msm_mux_lpass_slimbus,
	573	+ msm_mux_m_voc,
	574	+ msm_mux_mdp_vsync,
	575	+ msm_mux_mdp_vsync0,
	576	+ msm_mux_mdp_vsync1,
	577	+ msm_mux_mdp_vsync2,
	578	+ msm_mux_mdp_vsync3,
	579	+ msm_mux_mdp_vsync4,
	580	+ msm_mux_mdp_vsync5,
	581	+ msm_mux_mss_lte,
	582	+ msm_mux_nav_pps,
	583	+ msm_mux_pa_indicator,
	584	+ msm_mux_pci_e0,
	585	+ msm_mux_pci_e1,
	586	+ msm_mux_pci_e2,
	587	+ msm_mux_pci_e3,
	588	+ msm_mux_phase_flag,
	589	+ msm_mux_pll_bist,
	590	+ msm_mux_pll_bypassnl,
	591	+ msm_mux_pll_reset,
	592	+ msm_mux_pri_mi2s,
	593	+ msm_mux_pri_mi2s_ws,
	594	+ msm_mux_prng_rosc,
	595	+ msm_mux_qdss_cti,
	596	+ msm_mux_qdss_gpio,
	597	+ msm_mux_qlink,
	598	+ msm_mux_qspi0,
	599	+ msm_mux_qspi0_clk,
	600	+ msm_mux_qspi0_cs,
	601	+ msm_mux_qspi1,
	602	+ msm_mux_qspi1_clk,
	603	+ msm_mux_qspi1_cs,
	604	+ msm_mux_qua_mi2s,
	605	+ msm_mux_qup0,
	606	+ msm_mux_qup1,
	607	+ msm_mux_qup2,
	608	+ msm_mux_qup3,
	609	+ msm_mux_qup4,
	610	+ msm_mux_qup5,
	611	+ msm_mux_qup6,
	612	+ msm_mux_qup7,
	613	+ msm_mux_qup8,
	614	+ msm_mux_qup9,
	615	+ msm_mux_qup10,
	616	+ msm_mux_qup11,
	617	+ msm_mux_qup12,
	618	+ msm_mux_qup13,
	619	+ msm_mux_qup14,
	620	+ msm_mux_qup15,
	621	+ msm_mux_qup16,
	622	+ msm_mux_qup17,
	623	+ msm_mux_qup18,
	624	+ msm_mux_qup19,
	625	+ msm_mux_qup_l4,
	626	+ msm_mux_qup_l5,
	627	+ msm_mux_qup_l6,
	628	+ msm_mux_rgmii,
	629	+ msm_mux_sd_write,
	630	+ msm_mux_sdc4,
	631	+ msm_mux_sdc4_clk,
	632	+ msm_mux_sdc4_cmd,
	633	+ msm_mux_sec_mi2s,
	634	+ msm_mux_sp_cmu,
	635	+ msm_mux_spkr_i2s,
	636	+ msm_mux_ter_mi2s,
	637	+ msm_mux_tgu,
	638	+ msm_mux_tsense_pwm1,
	639	+ msm_mux_tsense_pwm2,
	640	+ msm_mux_tsif1,
	641	+ msm_mux_tsif2,
	642	+ msm_mux_uim1,
	643	+ msm_mux_uim2,
	644	+ msm_mux_uim_batt,
	645	+ msm_mux_usb0_phy,
	646	+ msm_mux_usb1_phy,
	647	+ msm_mux_usb2phy_ac,
	648	+ msm_mux_vfr_1,
	649	+ msm_mux_vsense_trigger,
	650	+ msm_mux_wlan1_adc,
	651	+ msm_mux_wlan2_adc,
	652	+ msm_mux_wmss_reset,
	653	+ msm_mux__,
	654	+};
	655	+
	656	+static const char * const adsp_ext_groups[] = {
	657	+ "gpio115",
	658	+};
	659	+
	660	+static const char * const agera_pll_groups[] = {
	661	+ "gpio37",
	662	+};
	663	+
	664	+static const char * const aoss_cti_groups[] = {
	665	+ "gpio113",
	666	+};
	667	+
	668	+static const char * const atest_char_groups[] = {
	669	+ "gpio133", "gpio134", "gpio135", "gpio140", "gpio142",
	670	+};
	671	+
	672	+static const char * const atest_tsens2_groups[] = {
	673	+ "gpio62",
	674	+};
	675	+
	676	+static const char * const atest_tsens_groups[] = {
	677	+ "gpio93",
	678	+};
	679	+
	680	+static const char * const atest_usb0_groups[] = {
	681	+ "gpio90", "gpio91", "gpio92", "gpio93", "gpio94",
	682	+};
	683	+
	684	+static const char * const atest_usb1_groups[] = {
	685	+ "gpio60", "gpio62", "gpio63", "gpio64", "gpio65",
	686	+};
	687	+
	688	+static const char * const atest_usb2_groups[] = {
	689	+ "gpio34", "gpio95", "gpio102", "gpio121", "gpio122",
	690	+};
	691	+
	692	+static const char * const atest_usb3_groups[] = {
	693	+ "gpio68", "gpio71", "gpio72", "gpio73", "gpio74",
	694	+};
	695	+
	696	+static const char * const atest_usb4_groups[] = {
	697	+ "gpio75", "gpio76", "gpio77", "gpio78", "gpio88",
	698	+};
	699	+
	700	+static const char * const audio_ref_groups[] = {
	701	+ "gpio148",
	702	+};
	703	+
	704	+static const char * const btfm_slimbus_groups[] = {
	705	+ "gpio153", "gpio154",
	706	+};
	707	+
	708	+static const char * const cam_mclk_groups[] = {
	709	+ "gpio13", "gpio14", "gpio15", "gpio16", "gpio25", "gpio179", "gpio180",
	710	+ "gpio181",
	711	+};
	712	+
	713	+static const char * const cci_async_groups[] = {
	714	+ "gpio24", "gpio25", "gpio26", "gpio176", "gpio185", "gpio186",
	715	+};
	716	+
	717	+static const char * const cci_i2c_groups[] = {
	718	+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio17", "gpio18", "gpio19",
	719	+ "gpio20", "gpio31", "gpio32", "gpio33", "gpio34", "gpio39", "gpio40",
	720	+ "gpio41", "gpio42",
	721	+};
	722	+
	723	+static const char * const cci_timer0_groups[] = {
	724	+ "gpio21",
	725	+};
	726	+
	727	+static const char * const cci_timer1_groups[] = {
	728	+ "gpio22",
	729	+};
	730	+
	731	+static const char * const cci_timer2_groups[] = {
	732	+ "gpio23",
	733	+};
	734	+
	735	+static const char * const cci_timer3_groups[] = {
	736	+ "gpio24",
	737	+};
	738	+
	739	+static const char * const cci_timer4_groups[] = {
	740	+ "gpio178",
	741	+};
	742	+
	743	+static const char * const cci_timer5_groups[] = {
	744	+ "gpio182",
	745	+};
	746	+
	747	+static const char * const cci_timer6_groups[] = {
	748	+ "gpio183",
	749	+};
	750	+
	751	+static const char * const cci_timer7_groups[] = {
	752	+ "gpio184",
	753	+};
	754	+
	755	+static const char * const cci_timer8_groups[] = {
	756	+ "gpio185",
	757	+};
	758	+
	759	+static const char * const cci_timer9_groups[] = {
	760	+ "gpio186",
	761	+};
	762	+
	763	+static const char * const cri_trng_groups[] = {
	764	+ "gpio159",
	765	+ "gpio160",
	766	+ "gpio161",
	767	+};
	768	+
	769	+static const char * const dbg_out_groups[] = {
	770	+ "gpio34",
	771	+};
	772	+
	773	+static const char * const ddr_bist_groups[] = {
	774	+ "gpio98", "gpio99", "gpio145", "gpio146",
	775	+};
	776	+
	777	+static const char * const ddr_pxi_groups[] = {
	778	+ "gpio60", "gpio62", "gpio63", "gpio64", "gpio65", "gpio68", "gpio71",
	779	+ "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", "gpio78",
	780	+ "gpio88", "gpio90",
	781	+};
	782	+
	783	+static const char * const debug_hot_groups[] = {
	784	+ "gpio7",
	785	+};
	786	+
	787	+static const char * const dp_hot_groups[] = {
	788	+ "gpio189",
	789	+};
	790	+
	791	+static const char * const edp_hot_groups[] = {
	792	+ "gpio10",
	793	+};
	794	+
	795	+static const char * const edp_lcd_groups[] = {
	796	+ "gpio11",
	797	+};
	798	+
	799	+static const char * const emac_phy_groups[] = {
	800	+ "gpio124",
	801	+};
	802	+
	803	+static const char * const emac_pps_groups[] = {
	804	+ "gpio81",
	805	+};
	806	+
	807	+static const char * const gcc_gp1_groups[] = {
	808	+ "gpio131", "gpio136",
	809	+};
	810	+
	811	+static const char * const gcc_gp2_groups[] = {
	812	+ "gpio21", "gpio137",
	813	+};
	814	+
	815	+static const char * const gcc_gp3_groups[] = {
	816	+ "gpio22", "gpio138",
	817	+};
	818	+
	819	+static const char * const gcc_gp4_groups[] = {
	820	+ "gpio139", "gpio182",
	821	+};
	822	+
	823	+static const char * const gcc_gp5_groups[] = {
	824	+ "gpio140", "gpio183",
	825	+};
	826	+
	827	+static const char * const gpio_groups[] = {
	828	+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
	829	+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio12", "gpio13",
	830	+ "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20",
	831	+ "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27",
	832	+ "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34",
	833	+ "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41",
	834	+ "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
	835	+ "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55",
	836	+ "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62",
	837	+ "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69",
	838	+ "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76",
	839	+ "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
	840	+ "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90",
	841	+ "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97",
	842	+ "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103",
	843	+ "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109",
	844	+ "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115",
	845	+ "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
	846	+ "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio127",
	847	+ "gpio128", "gpio129", "gpio130", "gpio131", "gpio132", "gpio133",
	848	+ "gpio134", "gpio135", "gpio136", "gpio137", "gpio138", "gpio139",
	849	+ "gpio140", "gpio141", "gpio142", "gpio143", "gpio144", "gpio145",
	850	+ "gpio146", "gpio147", "gpio148", "gpio149", "gpio150", "gpio151",
	851	+ "gpio152", "gpio153", "gpio154", "gpio155", "gpio156", "gpio157",
	852	+ "gpio158", "gpio159", "gpio160", "gpio161", "gpio162", "gpio163",
	853	+ "gpio164", "gpio165", "gpio166", "gpio167", "gpio168", "gpio169",
	854	+ "gpio170", "gpio171", "gpio172", "gpio173", "gpio174", "gpio175",
	855	+ "gpio176", "gpio177", "gpio177", "gpio178", "gpio179", "gpio180",
	856	+ "gpio181", "gpio182", "gpio183", "gpio184", "gpio185", "gpio186",
	857	+ "gpio186", "gpio187", "gpio187", "gpio188", "gpio188", "gpio189",
	858	+};
	859	+
	860	+static const char * const gps_groups[] = {
	861	+ "gpio60", "gpio76", "gpio77", "gpio81", "gpio82",
	862	+};
	863	+
	864	+static const char * const grfc_groups[] = {
	865	+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio71", "gpio72",
	866	+ "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", "gpio78", "gpio79",
	867	+ "gpio80", "gpio81", "gpio82",
	868	+};
	869	+
	870	+static const char * const hs1_mi2s_groups[] = {
	871	+ "gpio155", "gpio156", "gpio157", "gpio158", "gpio159",
	872	+};
	873	+
	874	+static const char * const hs2_mi2s_groups[] = {
	875	+ "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
	876	+};
	877	+
	878	+static const char * const hs3_mi2s_groups[] = {
	879	+ "gpio125", "gpio165", "gpio166", "gpio167", "gpio168",
	880	+};
	881	+
	882	+static const char * const jitter_bist_groups[] = {
	883	+ "gpio129",
	884	+};
	885	+
	886	+static const char * const lpass_slimbus_groups[] = {
	887	+ "gpio149", "gpio150", "gpio151", "gpio152",
	888	+};
	889	+
	890	+static const char * const m_voc_groups[] = {
	891	+ "gpio10",
	892	+};
	893	+
	894	+static const char * const mdp_vsync0_groups[] = {
	895	+ "gpio89",
	896	+};
	897	+
	898	+static const char * const mdp_vsync1_groups[] = {
	899	+ "gpio89",
	900	+};
	901	+
	902	+static const char * const mdp_vsync2_groups[] = {
	903	+ "gpio89",
	904	+};
	905	+
	906	+static const char * const mdp_vsync3_groups[] = {
	907	+ "gpio89",
	908	+};
	909	+
	910	+static const char * const mdp_vsync4_groups[] = {
	911	+ "gpio89",
	912	+};
	913	+
	914	+static const char * const mdp_vsync5_groups[] = {
	915	+ "gpio89",
	916	+};
	917	+
	918	+static const char * const mdp_vsync_groups[] = {
	919	+ "gpio8", "gpio9", "gpio10", "gpio60", "gpio82",
	920	+};
	921	+
	922	+static const char * const mss_lte_groups[] = {
	923	+ "gpio69", "gpio70",
	924	+};
	925	+
	926	+static const char * const nav_pps_groups[] = {
	927	+ "gpio60", "gpio60", "gpio76", "gpio76", "gpio77", "gpio77", "gpio81",
	928	+ "gpio81", "gpio82", "gpio82",
	929	+};
	930	+
	931	+static const char * const pa_indicator_groups[] = {
	932	+ "gpio68",
	933	+};
	934	+
	935	+static const char * const pci_e0_groups[] = {
	936	+ "gpio35", "gpio36",
	937	+};
	938	+
	939	+static const char * const pci_e1_groups[] = {
	940	+ "gpio102", "gpio103",
	941	+};
	942	+
	943	+static const char * const pci_e2_groups[] = {
	944	+ "gpio175", "gpio176",
	945	+};
	946	+
	947	+static const char * const pci_e3_groups[] = {
	948	+ "gpio178", "gpio179",
	949	+};
	950	+
	951	+static const char * const phase_flag_groups[] = {
	952	+ "gpio4", "gpio5", "gpio6", "gpio7", "gpio33", "gpio53", "gpio54",
	953	+ "gpio102", "gpio120", "gpio121", "gpio122", "gpio123", "gpio125",
	954	+ "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", "gpio155",
	955	+ "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161",
	956	+ "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167",
	957	+ "gpio168",
	958	+};
	959	+
	960	+static const char * const pll_bist_groups[] = {
	961	+ "gpio130",
	962	+};
	963	+
	964	+static const char * const pll_bypassnl_groups[] = {
	965	+ "gpio100",
	966	+};
	967	+
	968	+static const char * const pll_reset_groups[] = {
	969	+ "gpio101",
	970	+};
	971	+
	972	+static const char * const pri_mi2s_groups[] = {
	973	+ "gpio143", "gpio144", "gpio146", "gpio147",
	974	+};
	975	+
	976	+static const char * const pri_mi2s_ws_groups[] = {
	977	+ "gpio145",
	978	+};
	979	+
	980	+static const char * const prng_rosc_groups[] = {
	981	+ "gpio163",
	982	+};
	983	+
	984	+static const char * const qdss_cti_groups[] = {
	985	+ "gpio49", "gpio50", "gpio81", "gpio82", "gpio89", "gpio90", "gpio141",
	986	+ "gpio142",
	987	+};
	988	+
	989	+static const char * const qdss_gpio_groups[] = {
	990	+ "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
	991	+ "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
	992	+ "gpio27", "gpio28", "gpio29", "gpio30", "gpio39", "gpio40", "gpio41",
	993	+ "gpio42", "gpio92", "gpio114", "gpio115", "gpio116", "gpio117",
	994	+ "gpio118", "gpio119", "gpio120", "gpio121", "gpio130", "gpio132",
	995	+ "gpio133", "gpio134", "gpio135",
	996	+};
	997	+
	998	+static const char * const qlink_groups[] = {
	999	+ "gpio61", "gpio62",
	1000	+};
	1001	+
	1002	+static const char * const qspi0_groups[] = {
	1003	+ "gpio89", "gpio90", "gpio91", "gpio93",
	1004	+};
	1005	+
	1006	+static const char * const qspi0_clk_groups[] = {
	1007	+ "gpio92",
	1008	+};
	1009	+
	1010	+static const char * const qspi0_cs_groups[] = {
	1011	+ "gpio88", "gpio94",
	1012	+};
	1013	+
	1014	+static const char * const qspi1_groups[] = {
	1015	+ "gpio56", "gpio57", "gpio161", "gpio162",
	1016	+};
	1017	+
	1018	+static const char * const qspi1_clk_groups[] = {
	1019	+ "gpio163",
	1020	+};
	1021	+
	1022	+static const char * const qspi1_cs_groups[] = {
	1023	+ "gpio55", "gpio164",
	1024	+};
	1025	+
	1026	+static const char * const qua_mi2s_groups[] = {
	1027	+ "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", "gpio141",
	1028	+ "gpio142",
	1029	+};
	1030	+
	1031	+static const char * const qup0_groups[] = {
	1032	+ "gpio0", "gpio1", "gpio2", "gpio3",
	1033	+};
	1034	+
	1035	+static const char * const qup10_groups[] = {
	1036	+ "gpio9", "gpio10", "gpio11", "gpio12",
	1037	+};
	1038	+
	1039	+static const char * const qup11_groups[] = {
	1040	+ "gpio92", "gpio93", "gpio94", "gpio95",
	1041	+};
	1042	+
	1043	+static const char * const qup12_groups[] = {
	1044	+ "gpio83", "gpio84", "gpio85", "gpio86",
	1045	+};
	1046	+
	1047	+static const char * const qup13_groups[] = {
	1048	+ "gpio43", "gpio44", "gpio45", "gpio46",
	1049	+};
	1050	+
	1051	+static const char * const qup14_groups[] = {
	1052	+ "gpio47", "gpio48", "gpio49", "gpio50",
	1053	+};
	1054	+
	1055	+static const char * const qup15_groups[] = {
	1056	+ "gpio27", "gpio28", "gpio29", "gpio30",
	1057	+};
	1058	+
	1059	+static const char * const qup16_groups[] = {
	1060	+ "gpio83", "gpio84", "gpio85", "gpio86",
	1061	+};
	1062	+
	1063	+static const char * const qup17_groups[] = {
	1064	+ "gpio55", "gpio56", "gpio57", "gpio58",
	1065	+};
	1066	+
	1067	+static const char * const qup18_groups[] = {
	1068	+ "gpio23", "gpio24", "gpio25", "gpio26",
	1069	+};
	1070	+
	1071	+static const char * const qup19_groups[] = {
	1072	+ "gpio181", "gpio182", "gpio183", "gpio184",
	1073	+};
	1074	+
	1075	+static const char * const qup1_groups[] = {
	1076	+ "gpio114", "gpio115", "gpio116", "gpio117",
	1077	+};
	1078	+
	1079	+static const char * const qup2_groups[] = {
	1080	+ "gpio126", "gpio127", "gpio128", "gpio129",
	1081	+};
	1082	+
	1083	+static const char * const qup3_groups[] = {
	1084	+ "gpio144", "gpio145", "gpio146", "gpio147",
	1085	+};
	1086	+
	1087	+static const char * const qup4_groups[] = {
	1088	+ "gpio51", "gpio52", "gpio53", "gpio54",
	1089	+};
	1090	+
	1091	+static const char * const qup5_groups[] = {
	1092	+ "gpio119", "gpio120", "gpio121", "gpio122",
	1093	+};
	1094	+
	1095	+static const char * const qup6_groups[] = {
	1096	+ "gpio4", "gpio5", "gpio6", "gpio7",
	1097	+};
	1098	+
	1099	+static const char * const qup7_groups[] = {
	1100	+ "gpio98", "gpio99", "gpio100", "gpio101",
	1101	+};
	1102	+
	1103	+static const char * const qup8_groups[] = {
	1104	+ "gpio88", "gpio89", "gpio90", "gpio91",
	1105	+};
	1106	+
	1107	+static const char * const qup9_groups[] = {
	1108	+ "gpio39", "gpio40", "gpio41", "gpio42",
	1109	+};
	1110	+
	1111	+static const char * const qup_l4_groups[] = {
	1112	+ "gpio35", "gpio59", "gpio60", "gpio95",
	1113	+};
	1114	+
	1115	+static const char * const qup_l5_groups[] = {
	1116	+ "gpio7", "gpio33", "gpio36", "gpio96",
	1117	+};
	1118	+
	1119	+static const char * const qup_l6_groups[] = {
	1120	+ "gpio6", "gpio34", "gpio37", "gpio97",
	1121	+};
	1122	+
	1123	+static const char * const rgmii_groups[] = {
	1124	+ "gpio4", "gpio5", "gpio6", "gpio7", "gpio59", "gpio114", "gpio115",
	1125	+ "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
	1126	+ "gpio122",
	1127	+};
	1128	+
	1129	+static const char * const sd_write_groups[] = {
	1130	+ "gpio97",
	1131	+};
	1132	+
	1133	+static const char * const sdc4_groups[] = {
	1134	+ "gpio91", "gpio93", "gpio94", "gpio95",
	1135	+};
	1136	+
	1137	+static const char * const sdc4_clk_groups[] = {
	1138	+ "gpio92",
	1139	+};
	1140	+
	1141	+static const char * const sdc4_cmd_groups[] = {
	1142	+ "gpio90",
	1143	+};
	1144	+
	1145	+static const char * const sec_mi2s_groups[] = {
	1146	+ "gpio126", "gpio127", "gpio128", "gpio129", "gpio130",
	1147	+};
	1148	+
	1149	+static const char * const sp_cmu_groups[] = {
	1150	+ "gpio162",
	1151	+};
	1152	+
	1153	+static const char * const spkr_i2s_groups[] = {
	1154	+ "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
	1155	+};
	1156	+
	1157	+static const char * const ter_mi2s_groups[] = {
	1158	+ "gpio131", "gpio132", "gpio133", "gpio134", "gpio135",
	1159	+};
	1160	+
	1161	+static const char * const tgu_groups[] = {
	1162	+ "gpio89", "gpio90", "gpio91", "gpio88", "gpio74", "gpio77", "gpio76",
	1163	+ "gpio75",
	1164	+};
	1165	+
	1166	+static const char * const tsense_pwm1_groups[] = {
	1167	+ "gpio150",
	1168	+};
	1169	+
	1170	+static const char * const tsense_pwm2_groups[] = {
	1171	+ "gpio150",
	1172	+};
	1173	+
	1174	+static const char * const tsif1_groups[] = {
	1175	+ "gpio88", "gpio89", "gpio90", "gpio91", "gpio97",
	1176	+};
	1177	+
	1178	+static const char * const tsif2_groups[] = {
	1179	+ "gpio92", "gpio93", "gpio94", "gpio95", "gpio96",
	1180	+};
	1181	+
	1182	+static const char * const uim1_groups[] = {
	1183	+ "gpio109", "gpio110", "gpio111", "gpio112",
	1184	+};
	1185	+
	1186	+static const char * const uim2_groups[] = {
	1187	+ "gpio105", "gpio106", "gpio107", "gpio108",
	1188	+};
	1189	+
	1190	+static const char * const uim_batt_groups[] = {
	1191	+ "gpio113",
	1192	+};
	1193	+
	1194	+static const char * const usb0_phy_groups[] = {
	1195	+ "gpio38",
	1196	+};
	1197	+
	1198	+static const char * const usb1_phy_groups[] = {
	1199	+ "gpio58",
	1200	+};
	1201	+
	1202	+static const char * const usb2phy_ac_groups[] = {
	1203	+ "gpio47", "gpio48", "gpio113", "gpio123",
	1204	+};
	1205	+
	1206	+static const char * const vfr_1_groups[] = {
	1207	+ "gpio91",
	1208	+};
	1209	+
	1210	+static const char * const vsense_trigger_groups[] = {
	1211	+ "gpio62",
	1212	+};
	1213	+
	1214	+static const char * const wlan1_adc_groups[] = {
	1215	+ "gpio64", "gpio63",
	1216	+};
	1217	+
	1218	+static const char * const wlan2_adc_groups[] = {
	1219	+ "gpio68", "gpio65",
	1220	+};
	1221	+
	1222	+static const char * const wmss_reset_groups[] = {
	1223	+ "gpio63",
	1224	+};
	1225	+
	1226	+static const struct msm_function sc8180x_functions[] = {
	1227	+ FUNCTION(adsp_ext),
	1228	+ FUNCTION(agera_pll),
	1229	+ FUNCTION(aoss_cti),
	1230	+ FUNCTION(atest_char),
	1231	+ FUNCTION(atest_tsens),
	1232	+ FUNCTION(atest_tsens2),
	1233	+ FUNCTION(atest_usb0),
	1234	+ FUNCTION(atest_usb1),
	1235	+ FUNCTION(atest_usb2),
	1236	+ FUNCTION(atest_usb3),
	1237	+ FUNCTION(atest_usb4),
	1238	+ FUNCTION(audio_ref),
	1239	+ FUNCTION(btfm_slimbus),
	1240	+ FUNCTION(cam_mclk),
	1241	+ FUNCTION(cci_async),
	1242	+ FUNCTION(cci_i2c),
	1243	+ FUNCTION(cci_timer0),
	1244	+ FUNCTION(cci_timer1),
	1245	+ FUNCTION(cci_timer2),
	1246	+ FUNCTION(cci_timer3),
	1247	+ FUNCTION(cci_timer4),
	1248	+ FUNCTION(cci_timer5),
	1249	+ FUNCTION(cci_timer6),
	1250	+ FUNCTION(cci_timer7),
	1251	+ FUNCTION(cci_timer8),
	1252	+ FUNCTION(cci_timer9),
	1253	+ FUNCTION(cri_trng),
	1254	+ FUNCTION(dbg_out),
	1255	+ FUNCTION(ddr_bist),
	1256	+ FUNCTION(ddr_pxi),
	1257	+ FUNCTION(debug_hot),
	1258	+ FUNCTION(dp_hot),
	1259	+ FUNCTION(edp_hot),
	1260	+ FUNCTION(edp_lcd),
	1261	+ FUNCTION(emac_phy),
	1262	+ FUNCTION(emac_pps),
	1263	+ FUNCTION(gcc_gp1),
	1264	+ FUNCTION(gcc_gp2),
	1265	+ FUNCTION(gcc_gp3),
	1266	+ FUNCTION(gcc_gp4),
	1267	+ FUNCTION(gcc_gp5),
	1268	+ FUNCTION(gpio),
	1269	+ FUNCTION(gps),
	1270	+ FUNCTION(grfc),
	1271	+ FUNCTION(hs1_mi2s),
	1272	+ FUNCTION(hs2_mi2s),
	1273	+ FUNCTION(hs3_mi2s),
	1274	+ FUNCTION(jitter_bist),
	1275	+ FUNCTION(lpass_slimbus),
	1276	+ FUNCTION(m_voc),
	1277	+ FUNCTION(mdp_vsync),
	1278	+ FUNCTION(mdp_vsync0),
	1279	+ FUNCTION(mdp_vsync1),
	1280	+ FUNCTION(mdp_vsync2),
	1281	+ FUNCTION(mdp_vsync3),
	1282	+ FUNCTION(mdp_vsync4),
	1283	+ FUNCTION(mdp_vsync5),
	1284	+ FUNCTION(mss_lte),
	1285	+ FUNCTION(nav_pps),
	1286	+ FUNCTION(pa_indicator),
	1287	+ FUNCTION(pci_e0),
	1288	+ FUNCTION(pci_e1),
	1289	+ FUNCTION(pci_e2),
	1290	+ FUNCTION(pci_e3),
	1291	+ FUNCTION(phase_flag),
	1292	+ FUNCTION(pll_bist),
	1293	+ FUNCTION(pll_bypassnl),
	1294	+ FUNCTION(pll_reset),
	1295	+ FUNCTION(pri_mi2s),
	1296	+ FUNCTION(pri_mi2s_ws),
	1297	+ FUNCTION(prng_rosc),
	1298	+ FUNCTION(qdss_cti),
	1299	+ FUNCTION(qdss_gpio),
	1300	+ FUNCTION(qlink),
	1301	+ FUNCTION(qspi0),
	1302	+ FUNCTION(qspi0_clk),
	1303	+ FUNCTION(qspi0_cs),
	1304	+ FUNCTION(qspi1),
	1305	+ FUNCTION(qspi1_clk),
	1306	+ FUNCTION(qspi1_cs),
	1307	+ FUNCTION(qua_mi2s),
	1308	+ FUNCTION(qup0),
	1309	+ FUNCTION(qup1),
	1310	+ FUNCTION(qup2),
	1311	+ FUNCTION(qup3),
	1312	+ FUNCTION(qup4),
	1313	+ FUNCTION(qup5),
	1314	+ FUNCTION(qup6),
	1315	+ FUNCTION(qup7),
	1316	+ FUNCTION(qup8),
	1317	+ FUNCTION(qup9),
	1318	+ FUNCTION(qup10),
	1319	+ FUNCTION(qup11),
	1320	+ FUNCTION(qup12),
	1321	+ FUNCTION(qup13),
	1322	+ FUNCTION(qup14),
	1323	+ FUNCTION(qup15),
	1324	+ FUNCTION(qup16),
	1325	+ FUNCTION(qup17),
	1326	+ FUNCTION(qup18),
	1327	+ FUNCTION(qup19),
	1328	+ FUNCTION(qup_l4),
	1329	+ FUNCTION(qup_l5),
	1330	+ FUNCTION(qup_l6),
	1331	+ FUNCTION(rgmii),
	1332	+ FUNCTION(sd_write),
	1333	+ FUNCTION(sdc4),
	1334	+ FUNCTION(sdc4_clk),
	1335	+ FUNCTION(sdc4_cmd),
	1336	+ FUNCTION(sec_mi2s),
	1337	+ FUNCTION(sp_cmu),
	1338	+ FUNCTION(spkr_i2s),
	1339	+ FUNCTION(ter_mi2s),
	1340	+ FUNCTION(tgu),
	1341	+ FUNCTION(tsense_pwm1),
	1342	+ FUNCTION(tsense_pwm2),
	1343	+ FUNCTION(tsif1),
	1344	+ FUNCTION(tsif2),
	1345	+ FUNCTION(uim1),
	1346	+ FUNCTION(uim2),
	1347	+ FUNCTION(uim_batt),
	1348	+ FUNCTION(usb0_phy),
	1349	+ FUNCTION(usb1_phy),
	1350	+ FUNCTION(usb2phy_ac),
	1351	+ FUNCTION(vfr_1),
	1352	+ FUNCTION(vsense_trigger),
	1353	+ FUNCTION(wlan1_adc),
	1354	+ FUNCTION(wlan2_adc),
	1355	+ FUNCTION(wmss_reset),
	1356	+};
	1357	+
	1358	+/* Every pin is maintained as a single group, and missing or non-existing pin
	1359	+ * would be maintained as dummy group to synchronize pin group index with
	1360	+ * pin descriptor registered with pinctrl core.
	1361	+ * Clients would not be able to request these dummy pin groups.
	1362	+ */
	1363	+static const struct msm_pingroup sc8180x_groups[] = {
	1364	+ [0] = PINGROUP(0, WEST, qup0, cci_i2c, _, _, _, _, _, _, _),
	1365	+ [1] = PINGROUP(1, WEST, qup0, cci_i2c, _, _, _, _, _, _, _),
	1366	+ [2] = PINGROUP(2, WEST, qup0, cci_i2c, _, _, _, _, _, _, _),
	1367	+ [3] = PINGROUP(3, WEST, qup0, cci_i2c, _, _, _, _, _, _, _),
	1368	+ [4] = PINGROUP(4, WEST, qup6, rgmii, _, phase_flag, _, _, _, _, _),
	1369	+ [5] = PINGROUP(5, WEST, qup6, rgmii, _, phase_flag, _, _, _, _, _),
	1370	+ [6] = PINGROUP(6, WEST, qup6, rgmii, qup_l6, _, phase_flag, _, _, _, _),
	1371	+ [7] = PINGROUP(7, WEST, qup6, debug_hot, rgmii, qup_l5, _, phase_flag, _, _, _),
	1372	+ [8] = PINGROUP(8, EAST, mdp_vsync, _, _, _, _, _, _, _, _),
	1373	+ [9] = PINGROUP(9, EAST, mdp_vsync, qup10, _, _, _, _, _, _, _),
	1374	+ [10] = PINGROUP(10, EAST, edp_hot, m_voc, mdp_vsync, qup10, _, _, _, _, _),
	1375	+ [11] = PINGROUP(11, EAST, edp_lcd, qup10, _, _, _, _, _, _, _),
	1376	+ [12] = PINGROUP(12, EAST, qup10, _, _, _, _, _, _, _, _),
	1377	+ [13] = PINGROUP(13, EAST, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
	1378	+ [14] = PINGROUP(14, EAST, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
	1379	+ [15] = PINGROUP(15, EAST, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
	1380	+ [16] = PINGROUP(16, EAST, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
	1381	+ [17] = PINGROUP(17, EAST, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
	1382	+ [18] = PINGROUP(18, EAST, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
	1383	+ [19] = PINGROUP(19, EAST, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
	1384	+ [20] = PINGROUP(20, EAST, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
	1385	+ [21] = PINGROUP(21, EAST, cci_timer0, gcc_gp2, qdss_gpio, _, _, _, _, _, _),
	1386	+ [22] = PINGROUP(22, EAST, cci_timer1, gcc_gp3, qdss_gpio, _, _, _, _, _, _),
	1387	+ [23] = PINGROUP(23, EAST, cci_timer2, qup18, qdss_gpio, _, _, _, _, _, _),
	1388	+ [24] = PINGROUP(24, EAST, cci_timer3, cci_async, qup18, qdss_gpio, _, _, _, _, _),
	1389	+ [25] = PINGROUP(25, EAST, cam_mclk, cci_async, qup18, qdss_gpio, _, _, _, _, _),
	1390	+ [26] = PINGROUP(26, EAST, cci_async, qup18, qdss_gpio, _, _, _, _, _, _),
	1391	+ [27] = PINGROUP(27, EAST, qup15, _, qdss_gpio, _, _, _, _, _, _),
	1392	+ [28] = PINGROUP(28, EAST, qup15, qdss_gpio, _, _, _, _, _, _, _),
	1393	+ [29] = PINGROUP(29, EAST, qup15, qdss_gpio, _, _, _, _, _, _, _),
	1394	+ [30] = PINGROUP(30, EAST, qup15, qdss_gpio, _, _, _, _, _, _, _),
	1395	+ [31] = PINGROUP(31, EAST, cci_i2c, _, _, _, _, _, _, _, _),
	1396	+ [32] = PINGROUP(32, EAST, cci_i2c, _, _, _, _, _, _, _, _),
	1397	+ [33] = PINGROUP(33, EAST, cci_i2c, qup_l5, _, phase_flag, _, _, _, _, _),
	1398	+ [34] = PINGROUP(34, EAST, cci_i2c, qup_l6, dbg_out, atest_usb2, _, _, _, _, _),
	1399	+ [35] = PINGROUP(35, SOUTH, pci_e0, qup_l4, _, _, _, _, _, _, _),
	1400	+ [36] = PINGROUP(36, SOUTH, pci_e0, qup_l5, _, _, _, _, _, _, _),
	1401	+ [37] = PINGROUP(37, SOUTH, qup_l6, agera_pll, _, _, _, _, _, _, _),
	1402	+ [38] = PINGROUP(38, SOUTH, usb0_phy, _, _, _, _, _, _, _, _),
	1403	+ [39] = PINGROUP(39, EAST, qup9, cci_i2c, qdss_gpio, _, _, _, _, _, _),
	1404	+ [40] = PINGROUP(40, EAST, qup9, cci_i2c, qdss_gpio, _, _, _, _, _, _),
	1405	+ [41] = PINGROUP(41, EAST, qup9, cci_i2c, qdss_gpio, _, _, _, _, _, _),
	1406	+ [42] = PINGROUP(42, EAST, qup9, cci_i2c, qdss_gpio, _, _, _, _, _, _),
	1407	+ [43] = PINGROUP(43, EAST, qup13, _, _, _, _, _, _, _, _),
	1408	+ [44] = PINGROUP(44, EAST, qup13, _, _, _, _, _, _, _, _),
	1409	+ [45] = PINGROUP(45, EAST, qup13, _, _, _, _, _, _, _, _),
	1410	+ [46] = PINGROUP(46, EAST, qup13, _, _, _, _, _, _, _, _),
	1411	+ [47] = PINGROUP(47, EAST, qup14, usb2phy_ac, _, _, _, _, _, _, _),
	1412	+ [48] = PINGROUP(48, EAST, qup14, usb2phy_ac, _, _, _, _, _, _, _),
	1413	+ [49] = PINGROUP(49, EAST, qup14, qdss_cti, _, _, _, _, _, _, _),
	1414	+ [50] = PINGROUP(50, EAST, qup14, qdss_cti, _, _, _, _, _, _, _),
	1415	+ [51] = PINGROUP(51, WEST, qup4, _, _, _, _, _, _, _, _),
	1416	+ [52] = PINGROUP(52, WEST, qup4, _, _, _, _, _, _, _, _),
	1417	+ [53] = PINGROUP(53, WEST, qup4, _, phase_flag, _, _, _, _, _, _),
	1418	+ [54] = PINGROUP(54, WEST, qup4, _, _, phase_flag, _, _, _, _, _),
	1419	+ [55] = PINGROUP(55, WEST, qup17, qspi1_cs, _, _, _, _, _, _, _),
	1420	+ [56] = PINGROUP(56, WEST, qup17, qspi1, _, _, _, _, _, _, _),
	1421	+ [57] = PINGROUP(57, WEST, qup17, qspi1, _, _, _, _, _, _, _),
	1422	+ [58] = PINGROUP(58, WEST, usb1_phy, qup17, _, _, _, _, _, _, _),
	1423	+ [59] = PINGROUP(59, WEST, rgmii, qup_l4, _, _, _, _, _, _, _),
	1424	+ [60] = PINGROUP(60, EAST, gps, nav_pps, nav_pps, qup_l4, mdp_vsync, atest_usb1, ddr_pxi, _, _),
	1425	+ [61] = PINGROUP(61, EAST, qlink, _, _, _, _, _, _, _, _),
	1426	+ [62] = PINGROUP(62, EAST, qlink, atest_tsens2, atest_usb1, ddr_pxi, vsense_trigger, _, _, _, _),
	1427	+ [63] = PINGROUP(63, EAST, wmss_reset, _, atest_usb1, ddr_pxi, wlan1_adc, _, _, _, _),
	1428	+ [64] = PINGROUP(64, EAST, grfc, _, atest_usb1, ddr_pxi, wlan1_adc, _, _, _, _),
	1429	+ [65] = PINGROUP(65, EAST, grfc, atest_usb1, ddr_pxi, wlan2_adc, _, _, _, _, _),
	1430	+ [66] = PINGROUP(66, EAST, grfc, _, _, _, _, _, _, _, _),
	1431	+ [67] = PINGROUP(67, EAST, grfc, _, _, _, _, _, _, _, _),
	1432	+ [68] = PINGROUP(68, EAST, grfc, pa_indicator, atest_usb3, ddr_pxi, wlan2_adc, _, _, _, _),
	1433	+ [69] = PINGROUP(69, EAST, mss_lte, _, _, _, _, _, _, _, _),
	1434	+ [70] = PINGROUP(70, EAST, mss_lte, _, _, _, _, _, _, _, _),
	1435	+ [71] = PINGROUP(71, EAST, _, grfc, atest_usb3, ddr_pxi, _, _, _, _, _),
	1436	+ [72] = PINGROUP(72, EAST, _, grfc, atest_usb3, ddr_pxi, _, _, _, _, _),
	1437	+ [73] = PINGROUP(73, EAST, _, grfc, atest_usb3, ddr_pxi, _, _, _, _, _),
	1438	+ [74] = PINGROUP(74, EAST, _, grfc, tgu, atest_usb3, ddr_pxi, _, _, _, _),
	1439	+ [75] = PINGROUP(75, EAST, _, grfc, tgu, atest_usb4, ddr_pxi, _, _, _, _),
	1440	+ [76] = PINGROUP(76, EAST, _, grfc, gps, nav_pps, nav_pps, tgu, atest_usb4, ddr_pxi, _),
	1441	+ [77] = PINGROUP(77, EAST, _, grfc, gps, nav_pps, nav_pps, tgu, atest_usb4, ddr_pxi, _),
	1442	+ [78] = PINGROUP(78, EAST, _, grfc, _, atest_usb4, ddr_pxi, _, _, _, _),
	1443	+ [79] = PINGROUP(79, EAST, _, grfc, _, _, _, _, _, _, _),
	1444	+ [80] = PINGROUP(80, EAST, _, grfc, _, _, _, _, _, _, _),
	1445	+ [81] = PINGROUP(81, EAST, _, grfc, gps, nav_pps, nav_pps, qdss_cti, _, emac_pps, _),
	1446	+ [82] = PINGROUP(82, EAST, _, grfc, gps, nav_pps, nav_pps, mdp_vsync, qdss_cti, _, _),
	1447	+ [83] = PINGROUP(83, EAST, qup12, qup16, _, _, _, _, _, _, _),
	1448	+ [84] = PINGROUP(84, EAST, qup12, qup16, _, _, _, _, _, _, _),
	1449	+ [85] = PINGROUP(85, EAST, qup12, qup16, _, _, _, _, _, _, _),
	1450	+ [86] = PINGROUP(86, EAST, qup12, qup16, _, _, _, _, _, _, _),
	1451	+ [87] = PINGROUP(87, SOUTH, _, _, _, _, _, _, _, _, _),
	1452	+ [88] = PINGROUP(88, EAST, tsif1, qup8, qspi0_cs, tgu, atest_usb4, ddr_pxi, _, _, _),
	1453	+ [89] = PINGROUP(89, EAST, tsif1, qup8, qspi0, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5),
	1454	+ [90] = PINGROUP(90, EAST, tsif1, qup8, qspi0, sdc4_cmd, tgu, qdss_cti, atest_usb0, ddr_pxi, _),
	1455	+ [91] = PINGROUP(91, EAST, tsif1, qup8, qspi0, sdc4, vfr_1, tgu, atest_usb0, _, _),
	1456	+ [92] = PINGROUP(92, EAST, tsif2, qup11, qspi0_clk, sdc4_clk, qdss_gpio, atest_usb0, _, _, _),
	1457	+ [93] = PINGROUP(93, EAST, tsif2, qup11, qspi0, sdc4, atest_tsens, atest_usb0, _, _, _),
	1458	+ [94] = PINGROUP(94, EAST, tsif2, qup11, qspi0_cs, sdc4, _, atest_usb0, _, _, _),
	1459	+ [95] = PINGROUP(95, EAST, tsif2, qup11, sdc4, qup_l4, atest_usb2, _, _, _, _),
	1460	+ [96] = PINGROUP(96, WEST, tsif2, qup_l5, _, _, _, _, _, _, _),
	1461	+ [97] = PINGROUP(97, WEST, sd_write, tsif1, qup_l6, _, _, _, _, _, _),
	1462	+ [98] = PINGROUP(98, WEST, qup7, ddr_bist, _, _, _, _, _, _, _),
	1463	+ [99] = PINGROUP(99, WEST, qup7, ddr_bist, _, _, _, _, _, _, _),
	1464	+ [100] = PINGROUP(100, WEST, qup7, pll_bypassnl, _, _, _, _, _, _, _),
	1465	+ [101] = PINGROUP(101, WEST, qup7, pll_reset, _, _, _, _, _, _, _),
	1466	+ [102] = PINGROUP(102, SOUTH, pci_e1, _, phase_flag, atest_usb2, _, _, _, _, _),
	1467	+ [103] = PINGROUP(103, SOUTH, pci_e1, _, _, _, _, _, _, _, _),
	1468	+ [104] = PINGROUP(104, SOUTH, _, _, _, _, _, _, _, _, _),
	1469	+ [105] = PINGROUP(105, WEST, uim2, _, _, _, _, _, _, _, _),
	1470	+ [106] = PINGROUP(106, WEST, uim2, _, _, _, _, _, _, _, _),
	1471	+ [107] = PINGROUP(107, WEST, uim2, _, _, _, _, _, _, _, _),
	1472	+ [108] = PINGROUP(108, WEST, uim2, _, _, _, _, _, _, _, _),
	1473	+ [109] = PINGROUP(109, WEST, uim1, _, _, _, _, _, _, _, _),
	1474	+ [110] = PINGROUP(110, WEST, uim1, _, _, _, _, _, _, _, _),
	1475	+ [111] = PINGROUP(111, WEST, uim1, _, _, _, _, _, _, _, _),
	1476	+ [112] = PINGROUP(112, WEST, uim1, _, _, _, _, _, _, _, _),
	1477	+ [113] = PINGROUP(113, WEST, uim_batt, usb2phy_ac, aoss_cti, _, _, _, _, _, _),
	1478	+ [114] = PINGROUP(114, WEST, qup1, rgmii, _, qdss_gpio, _, _, _, _, _),
	1479	+ [115] = PINGROUP(115, WEST, qup1, rgmii, adsp_ext, _, qdss_gpio, _, _, _, _),
	1480	+ [116] = PINGROUP(116, WEST, qup1, rgmii, _, qdss_gpio, _, _, _, _, _),
	1481	+ [117] = PINGROUP(117, WEST, qup1, rgmii, _, qdss_gpio, _, _, _, _, _),
	1482	+ [118] = PINGROUP(118, WEST, rgmii, _, qdss_gpio, _, _, _, _, _, _),
	1483	+ [119] = PINGROUP(119, WEST, qup5, rgmii, _, qdss_gpio, _, _, _, _, _),
	1484	+ [120] = PINGROUP(120, WEST, qup5, rgmii, _, phase_flag, qdss_gpio, _, _, _, _),
	1485	+ [121] = PINGROUP(121, WEST, qup5, rgmii, _, phase_flag, qdss_gpio, atest_usb2, _, _, _),
	1486	+ [122] = PINGROUP(122, WEST, qup5, rgmii, _, phase_flag, atest_usb2, _, _, _, _),
	1487	+ [123] = PINGROUP(123, SOUTH, usb2phy_ac, _, phase_flag, _, _, _, _, _, _),
	1488	+ [124] = PINGROUP(124, SOUTH, emac_phy, _, _, _, _, _, _, _, _),
	1489	+ [125] = PINGROUP(125, WEST, hs3_mi2s, _, phase_flag, _, _, _, _, _, _),
	1490	+ [126] = PINGROUP(126, WEST, sec_mi2s, qup2, _, _, _, _, _, _, _),
	1491	+ [127] = PINGROUP(127, WEST, sec_mi2s, qup2, _, _, _, _, _, _, _),
	1492	+ [128] = PINGROUP(128, WEST, sec_mi2s, qup2, _, _, _, _, _, _, _),
	1493	+ [129] = PINGROUP(129, WEST, sec_mi2s, qup2, jitter_bist, _, _, _, _, _, _),
	1494	+ [130] = PINGROUP(130, WEST, sec_mi2s, pll_bist, _, qdss_gpio, _, _, _, _, _),
	1495	+ [131] = PINGROUP(131, WEST, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _),
	1496	+ [132] = PINGROUP(132, WEST, ter_mi2s, _, qdss_gpio, _, _, _, _, _, _),
	1497	+ [133] = PINGROUP(133, WEST, ter_mi2s, _, qdss_gpio, atest_char, _, _, _, _, _),
	1498	+ [134] = PINGROUP(134, WEST, ter_mi2s, _, qdss_gpio, atest_char, _, _, _, _, _),
	1499	+ [135] = PINGROUP(135, WEST, ter_mi2s, _, qdss_gpio, atest_char, _, _, _, _, _),
	1500	+ [136] = PINGROUP(136, WEST, qua_mi2s, gcc_gp1, _, _, _, _, _, _, _),
	1501	+ [137] = PINGROUP(137, WEST, qua_mi2s, gcc_gp2, _, _, _, _, _, _, _),
	1502	+ [138] = PINGROUP(138, WEST, qua_mi2s, gcc_gp3, _, _, _, _, _, _, _),
	1503	+ [139] = PINGROUP(139, WEST, qua_mi2s, gcc_gp4, _, _, _, _, _, _, _),
	1504	+ [140] = PINGROUP(140, WEST, qua_mi2s, gcc_gp5, _, atest_char, _, _, _, _, _),
	1505	+ [141] = PINGROUP(141, WEST, qua_mi2s, qdss_cti, _, _, _, _, _, _, _),
	1506	+ [142] = PINGROUP(142, WEST, qua_mi2s, _, _, qdss_cti, atest_char, _, _, _, _),
	1507	+ [143] = PINGROUP(143, WEST, pri_mi2s, _, _, _, _, _, _, _, _),
	1508	+ [144] = PINGROUP(144, WEST, pri_mi2s, qup3, _, _, _, _, _, _, _),
	1509	+ [145] = PINGROUP(145, WEST, pri_mi2s_ws, qup3, ddr_bist, _, _, _, _, _, _),
	1510	+ [146] = PINGROUP(146, WEST, pri_mi2s, qup3, ddr_bist, _, _, _, _, _, _),
	1511	+ [147] = PINGROUP(147, WEST, pri_mi2s, qup3, _, _, _, _, _, _, _),
	1512	+ [148] = PINGROUP(148, WEST, spkr_i2s, audio_ref, _, phase_flag, _, _, _, _, _),
	1513	+ [149] = PINGROUP(149, WEST, lpass_slimbus, spkr_i2s, _, phase_flag, _, _, _, _, _),
	1514	+ [150] = PINGROUP(150, WEST, lpass_slimbus, spkr_i2s, _, phase_flag, tsense_pwm1, tsense_pwm2, _, _, _),
	1515	+ [151] = PINGROUP(151, WEST, lpass_slimbus, spkr_i2s, _, phase_flag, _, _, _, _, _),
	1516	+ [152] = PINGROUP(152, WEST, lpass_slimbus, spkr_i2s, _, phase_flag, _, _, _, _, _),
	1517	+ [153] = PINGROUP(153, WEST, btfm_slimbus, _, _, _, _, _, _, _, _),
	1518	+ [154] = PINGROUP(154, WEST, btfm_slimbus, _, _, _, _, _, _, _, _),
	1519	+ [155] = PINGROUP(155, WEST, hs1_mi2s, _, phase_flag, _, _, _, _, _, _),
	1520	+ [156] = PINGROUP(156, WEST, hs1_mi2s, _, phase_flag, _, _, _, _, _, _),
	1521	+ [157] = PINGROUP(157, WEST, hs1_mi2s, _, phase_flag, _, _, _, _, _, _),
	1522	+ [158] = PINGROUP(158, WEST, hs1_mi2s, _, phase_flag, _, _, _, _, _, _),
	1523	+ [159] = PINGROUP(159, WEST, hs1_mi2s, cri_trng, _, phase_flag, _, _, _, _, _),
	1524	+ [160] = PINGROUP(160, WEST, hs2_mi2s, cri_trng, _, phase_flag, _, _, _, _, _),
	1525	+ [161] = PINGROUP(161, WEST, hs2_mi2s, qspi1, cri_trng, _, phase_flag, _, _, _, _),
	1526	+ [162] = PINGROUP(162, WEST, hs2_mi2s, qspi1, sp_cmu, _, phase_flag, _, _, _, _),
	1527	+ [163] = PINGROUP(163, WEST, hs2_mi2s, qspi1_clk, prng_rosc, _, phase_flag, _, _, _, _),
	1528	+ [164] = PINGROUP(164, WEST, hs2_mi2s, qspi1_cs, _, phase_flag, _, _, _, _, _),
	1529	+ [165] = PINGROUP(165, WEST, hs3_mi2s, _, phase_flag, _, _, _, _, _, _),
	1530	+ [166] = PINGROUP(166, WEST, hs3_mi2s, _, phase_flag, _, _, _, _, _, _),
	1531	+ [167] = PINGROUP(167, WEST, hs3_mi2s, _, phase_flag, _, _, _, _, _, _),
	1532	+ [168] = PINGROUP(168, WEST, hs3_mi2s, _, phase_flag, _, _, _, _, _, _),
	1533	+ [169] = PINGROUP(169, SOUTH, _, _, _, _, _, _, _, _, _),
	1534	+ [170] = PINGROUP(170, SOUTH, _, _, _, _, _, _, _, _, _),
	1535	+ [171] = PINGROUP(171, SOUTH, _, _, _, _, _, _, _, _, _),
	1536	+ [172] = PINGROUP(172, SOUTH, _, _, _, _, _, _, _, _, _),
	1537	+ [173] = PINGROUP(173, SOUTH, _, _, _, _, _, _, _, _, _),
	1538	+ [174] = PINGROUP(174, SOUTH, _, _, _, _, _, _, _, _, _),
	1539	+ [175] = PINGROUP(175, SOUTH, pci_e2, _, _, _, _, _, _, _, _),
	1540	+ [176] = PINGROUP(176, SOUTH, pci_e2, cci_async, _, _, _, _, _, _, _),
	1541	+ [177] = PINGROUP_OFFSET(177, SOUTH, 0x1e000, _, _, _, _, _, _, _, _, _),
	1542	+ [178] = PINGROUP_OFFSET(178, SOUTH, 0x1e000, pci_e3, cci_timer4, _, _, _, _, _, _, _),
	1543	+ [179] = PINGROUP_OFFSET(179, SOUTH, 0x1e000, pci_e3, cam_mclk, _, _, _, _, _, _, _),
	1544	+ [180] = PINGROUP_OFFSET(180, SOUTH, 0x1e000, cam_mclk, _, _, _, _, _, _, _, _),
	1545	+ [181] = PINGROUP_OFFSET(181, SOUTH, 0x1e000, qup19, cam_mclk, _, _, _, _, _, _, _),
	1546	+ [182] = PINGROUP_OFFSET(182, SOUTH, 0x1e000, qup19, cci_timer5, gcc_gp4, _, _, _, _, _, _),
	1547	+ [183] = PINGROUP_OFFSET(183, SOUTH, 0x1e000, qup19, cci_timer6, gcc_gp5, _, _, _, _, _, _),
	1548	+ [184] = PINGROUP_OFFSET(184, SOUTH, 0x1e000, qup19, cci_timer7, _, _, _, _, _, _, _),
	1549	+ [185] = PINGROUP_OFFSET(185, SOUTH, 0x1e000, cci_timer8, cci_async, _, _, _, _, _, _, _),
	1550	+ [186] = PINGROUP_OFFSET(186, SOUTH, 0x1e000, cci_timer9, cci_async, _, _, _, _, _, _, _),
	1551	+ [187] = PINGROUP_OFFSET(187, SOUTH, 0x1e000, _, _, _, _, _, _, _, _, _),
	1552	+ [188] = PINGROUP_OFFSET(188, SOUTH, 0x1e000, _, _, _, _, _, _, _, _, _),
	1553	+ [189] = PINGROUP_OFFSET(189, SOUTH, 0x1e000, dp_hot, _, _, _, _, _, _, _, _),
	1554	+ [190] = UFS_RESET(ufs_reset),
	1555	+ [191] = SDC_QDSD_PINGROUP(sdc2_clk, 0x4b2000, 14, 6),
	1556	+ [192] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x4b2000, 11, 3),
	1557	+ [193] = SDC_QDSD_PINGROUP(sdc2_data, 0x4b2000, 9, 0),
	1558	+};
	1559	+
	1560	+static const struct msm_gpio_wakeirq_map sc8180x_pdc_map[] = {
	1561	+ { 3, 31 }, { 5, 32 }, { 8, 33 }, { 9, 34 }, { 10, 100 }, { 12, 104 },
	1562	+ { 24, 37 }, { 26, 38 }, { 27, 41 }, { 28, 42 }, { 30, 39 }, { 36, 43 },
	1563	+ { 37, 43 }, { 38, 45 }, { 39, 118 }, { 39, 125 }, { 41, 47 },
	1564	+ { 42, 48 }, { 46, 50 }, { 47, 49 }, { 48, 51 }, { 49, 53 }, { 50, 52 },
	1565	+ { 51, 116 }, { 51, 123 }, { 53, 54 }, { 54, 55 }, { 55, 56 },
	1566	+ { 56, 57 }, { 58, 58 }, { 60, 60 }, { 68, 62 }, { 70, 63 }, { 76, 86 },
	1567	+ { 77, 36 }, { 81, 64 }, { 83, 65 }, { 86, 67 }, { 87, 84 }, { 88, 117 },
	1568	+ { 88, 124 }, { 90, 69 }, { 91, 70 }, { 93, 75 }, { 95, 72 }, { 97, 74 },
	1569	+ { 101, 76 }, { 103, 77 }, { 104, 78 }, { 114, 82 }, { 117, 85 },
	1570	+ { 118, 101 }, { 119, 87 }, { 120, 88 }, { 121, 89 }, { 122, 90 },
	1571	+ { 123, 91 }, { 124, 92 }, { 125, 93 }, { 129, 94 }, { 132, 105 },
	1572	+ { 133, 35 }, { 134, 36 }, { 136, 97 }, { 142, 103 }, { 144, 115 },
	1573	+ { 144, 122 }, { 147, 106 }, { 150, 107 }, { 152, 108 }, { 153, 109 },
	1574	+ { 177, 111 }, { 180, 112 }, { 184, 113 }, { 189, 114 }
	1575	+};
	1576	+
	1577	+static struct msm_pinctrl_soc_data sc8180x_pinctrl = {
	1578	+ .tiles = sc8180x_tiles,
	1579	+ .ntiles = ARRAY_SIZE(sc8180x_tiles),
	1580	+ .pins = sc8180x_pins,
	1581	+ .npins = ARRAY_SIZE(sc8180x_pins),
	1582	+ .functions = sc8180x_functions,
	1583	+ .nfunctions = ARRAY_SIZE(sc8180x_functions),
	1584	+ .groups = sc8180x_groups,
	1585	+ .ngroups = ARRAY_SIZE(sc8180x_groups),
	1586	+ .ngpios = 191,
	1587	+ .wakeirq_map = sc8180x_pdc_map,
	1588	+ .nwakeirq_map = ARRAY_SIZE(sc8180x_pdc_map),
	1589	+};
	1590	+
	1591	+static int sc8180x_pinctrl_probe(struct platform_device *pdev)
	1592	+{
	1593	+ return msm_pinctrl_probe(pdev, &sc8180x_pinctrl);
	1594	+}
	1595	+
	1596	+static const struct of_device_id sc8180x_pinctrl_of_match[] = {
	1597	+ { .compatible = "qcom,sc8180x-tlmm", },
	1598	+ { },
	1599	+};
	1600	+MODULE_DEVICE_TABLE(of, sc8180x_pinctrl_of_match);
	1601	+
	1602	+static struct platform_driver sc8180x_pinctrl_driver = {
	1603	+ .driver = {
	1604	+ .name = "sc8180x-pinctrl",
	1605	+ .of_match_table = sc8180x_pinctrl_of_match,
	1606	+ },
	1607	+ .probe = sc8180x_pinctrl_probe,
	1608	+ .remove = msm_pinctrl_remove,
	1609	+};
	1610	+
	1611	+static int __init sc8180x_pinctrl_init(void)
	1612	+{
	1613	+ return platform_driver_register(&sc8180x_pinctrl_driver);
	1614	+}
	1615	+arch_initcall(sc8180x_pinctrl_init);
	1616	+
	1617	+static void __exit sc8180x_pinctrl_exit(void)
	1618	+{
	1619	+ platform_driver_unregister(&sc8180x_pinctrl_driver);
	1620	+}
	1621	+module_exit(sc8180x_pinctrl_exit);
	1622	+
	1623	+MODULE_DESCRIPTION("QTI SC8180x pinctrl driver");
	1624	+MODULE_LICENSE("GPL v2");

drivers/pinctrl/qcom/pinctrl-sdm845.c+0−1

@@ -1310,7 +1310,6 @@ static const struct msm_pinctrl_soc_data sdm845_pinctrl = { · 1309 unmodified lines
1310	1310	.ngpios = 151,
1311	1311	.wakeirq_map = sdm845_pdc_map,
1312	1312	.nwakeirq_map = ARRAY_SIZE(sdm845_pdc_map),
1313		−
1314	1313	};
1315	1314
1316	1315	static const struct msm_pinctrl_soc_data sdm845_acpi_pinctrl = {

drivers/pinctrl/qcom/pinctrl-sm8350.c+1649−0

@@ -0,0 +1,1649 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
	2	+/*
	3	+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
	4	+ * Copyright (c) 2020-2021, Linaro Limited
	5	+ */
	6	+
	7	+#include <linux/module.h>
	8	+#include <linux/of.h>
	9	+#include <linux/platform_device.h>
	10	+#include <linux/pinctrl/pinctrl.h>
	11	+
	12	+#include "pinctrl-msm.h"
	13	+
	14	+#define FUNCTION(fname) \
	15	+ [msm_mux_##fname] = { \
	16	+ .name = #fname, \
	17	+ .groups = fname##_groups, \
	18	+ .ngroups = ARRAY_SIZE(fname##_groups), \
	19	+ }
	20	+
	21	+#define REG_SIZE 0x1000
	22	+
	23	+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
	24	+ { \
	25	+ .name = "gpio" #id, \
	26	+ .pins = gpio##id##_pins, \
	27	+ .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
	28	+ .funcs = (int[]){ \
	29	+ msm_mux_gpio, /* gpio mode */ \
	30	+ msm_mux_##f1, \
	31	+ msm_mux_##f2, \
	32	+ msm_mux_##f3, \
	33	+ msm_mux_##f4, \
	34	+ msm_mux_##f5, \
	35	+ msm_mux_##f6, \
	36	+ msm_mux_##f7, \
	37	+ msm_mux_##f8, \
	38	+ msm_mux_##f9 \
	39	+ }, \
	40	+ .nfuncs = 10, \
	41	+ .ctl_reg = REG_SIZE * id, \
	42	+ .io_reg = REG_SIZE * id + 0x4, \
	43	+ .intr_cfg_reg = REG_SIZE * id + 0x8, \
	44	+ .intr_status_reg = REG_SIZE * id + 0xc, \
	45	+ .intr_target_reg = REG_SIZE * id + 0x8, \
	46	+ .mux_bit = 2, \
	47	+ .pull_bit = 0, \
	48	+ .drv_bit = 6, \
	49	+ .oe_bit = 9, \
	50	+ .in_bit = 0, \
	51	+ .out_bit = 1, \
	52	+ .intr_enable_bit = 0, \
	53	+ .intr_status_bit = 0, \
	54	+ .intr_target_bit = 5, \
	55	+ .intr_target_kpss_val = 3, \
	56	+ .intr_raw_status_bit = 4, \
	57	+ .intr_polarity_bit = 1, \
	58	+ .intr_detection_bit = 2, \
	59	+ .intr_detection_width = 2, \
	60	+ }
	61	+
	62	+#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
	63	+ { \
	64	+ .name = #pg_name, \
	65	+ .pins = pg_name##_pins, \
	66	+ .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
	67	+ .ctl_reg = ctl, \
	68	+ .io_reg = 0, \
	69	+ .intr_cfg_reg = 0, \
	70	+ .intr_status_reg = 0, \
	71	+ .intr_target_reg = 0, \
	72	+ .mux_bit = -1, \
	73	+ .pull_bit = pull, \
	74	+ .drv_bit = drv, \
	75	+ .oe_bit = -1, \
	76	+ .in_bit = -1, \
	77	+ .out_bit = -1, \
	78	+ .intr_enable_bit = -1, \
	79	+ .intr_status_bit = -1, \
	80	+ .intr_target_bit = -1, \
	81	+ .intr_raw_status_bit = -1, \
	82	+ .intr_polarity_bit = -1, \
	83	+ .intr_detection_bit = -1, \
	84	+ .intr_detection_width = -1, \
	85	+ }
	86	+
	87	+#define UFS_RESET(pg_name, offset) \
	88	+ { \
	89	+ .name = #pg_name, \
	90	+ .pins = pg_name##_pins, \
	91	+ .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
	92	+ .ctl_reg = offset, \
	93	+ .io_reg = offset + 0x4, \
	94	+ .intr_cfg_reg = 0, \
	95	+ .intr_status_reg = 0, \
	96	+ .intr_target_reg = 0, \
	97	+ .mux_bit = -1, \
	98	+ .pull_bit = 3, \
	99	+ .drv_bit = 0, \
	100	+ .oe_bit = -1, \
	101	+ .in_bit = -1, \
	102	+ .out_bit = 0, \
	103	+ .intr_enable_bit = -1, \
	104	+ .intr_status_bit = -1, \
	105	+ .intr_target_bit = -1, \
	106	+ .intr_raw_status_bit = -1, \
	107	+ .intr_polarity_bit = -1, \
	108	+ .intr_detection_bit = -1, \
	109	+ .intr_detection_width = -1, \
	110	+ }
	111	+
	112	+static const struct pinctrl_pin_desc sm8350_pins[] = {
	113	+ PINCTRL_PIN(0, "GPIO_0"),
	114	+ PINCTRL_PIN(1, "GPIO_1"),
	115	+ PINCTRL_PIN(2, "GPIO_2"),
	116	+ PINCTRL_PIN(3, "GPIO_3"),
	117	+ PINCTRL_PIN(4, "GPIO_4"),
	118	+ PINCTRL_PIN(5, "GPIO_5"),
	119	+ PINCTRL_PIN(6, "GPIO_6"),
	120	+ PINCTRL_PIN(7, "GPIO_7"),
	121	+ PINCTRL_PIN(8, "GPIO_8"),
	122	+ PINCTRL_PIN(9, "GPIO_9"),
	123	+ PINCTRL_PIN(10, "GPIO_10"),
	124	+ PINCTRL_PIN(11, "GPIO_11"),
	125	+ PINCTRL_PIN(12, "GPIO_12"),
	126	+ PINCTRL_PIN(13, "GPIO_13"),
	127	+ PINCTRL_PIN(14, "GPIO_14"),
	128	+ PINCTRL_PIN(15, "GPIO_15"),
	129	+ PINCTRL_PIN(16, "GPIO_16"),
	130	+ PINCTRL_PIN(17, "GPIO_17"),
	131	+ PINCTRL_PIN(18, "GPIO_18"),
	132	+ PINCTRL_PIN(19, "GPIO_19"),
	133	+ PINCTRL_PIN(20, "GPIO_20"),
	134	+ PINCTRL_PIN(21, "GPIO_21"),
	135	+ PINCTRL_PIN(22, "GPIO_22"),
	136	+ PINCTRL_PIN(23, "GPIO_23"),
	137	+ PINCTRL_PIN(24, "GPIO_24"),
	138	+ PINCTRL_PIN(25, "GPIO_25"),
	139	+ PINCTRL_PIN(26, "GPIO_26"),
	140	+ PINCTRL_PIN(27, "GPIO_27"),
	141	+ PINCTRL_PIN(28, "GPIO_28"),
	142	+ PINCTRL_PIN(29, "GPIO_29"),
	143	+ PINCTRL_PIN(30, "GPIO_30"),
	144	+ PINCTRL_PIN(31, "GPIO_31"),
	145	+ PINCTRL_PIN(32, "GPIO_32"),
	146	+ PINCTRL_PIN(33, "GPIO_33"),
	147	+ PINCTRL_PIN(34, "GPIO_34"),
	148	+ PINCTRL_PIN(35, "GPIO_35"),
	149	+ PINCTRL_PIN(36, "GPIO_36"),
	150	+ PINCTRL_PIN(37, "GPIO_37"),
	151	+ PINCTRL_PIN(38, "GPIO_38"),
	152	+ PINCTRL_PIN(39, "GPIO_39"),
	153	+ PINCTRL_PIN(40, "GPIO_40"),
	154	+ PINCTRL_PIN(41, "GPIO_41"),
	155	+ PINCTRL_PIN(42, "GPIO_42"),
	156	+ PINCTRL_PIN(43, "GPIO_43"),
	157	+ PINCTRL_PIN(44, "GPIO_44"),
	158	+ PINCTRL_PIN(45, "GPIO_45"),
	159	+ PINCTRL_PIN(46, "GPIO_46"),
	160	+ PINCTRL_PIN(47, "GPIO_47"),
	161	+ PINCTRL_PIN(48, "GPIO_48"),
	162	+ PINCTRL_PIN(49, "GPIO_49"),
	163	+ PINCTRL_PIN(50, "GPIO_50"),
	164	+ PINCTRL_PIN(51, "GPIO_51"),
	165	+ PINCTRL_PIN(52, "GPIO_52"),
	166	+ PINCTRL_PIN(53, "GPIO_53"),
	167	+ PINCTRL_PIN(54, "GPIO_54"),
	168	+ PINCTRL_PIN(55, "GPIO_55"),
	169	+ PINCTRL_PIN(56, "GPIO_56"),
	170	+ PINCTRL_PIN(57, "GPIO_57"),
	171	+ PINCTRL_PIN(58, "GPIO_58"),
	172	+ PINCTRL_PIN(59, "GPIO_59"),
	173	+ PINCTRL_PIN(60, "GPIO_60"),
	174	+ PINCTRL_PIN(61, "GPIO_61"),
	175	+ PINCTRL_PIN(62, "GPIO_62"),
	176	+ PINCTRL_PIN(63, "GPIO_63"),
	177	+ PINCTRL_PIN(64, "GPIO_64"),
	178	+ PINCTRL_PIN(65, "GPIO_65"),
	179	+ PINCTRL_PIN(66, "GPIO_66"),
	180	+ PINCTRL_PIN(67, "GPIO_67"),
	181	+ PINCTRL_PIN(68, "GPIO_68"),
	182	+ PINCTRL_PIN(69, "GPIO_69"),
	183	+ PINCTRL_PIN(70, "GPIO_70"),
	184	+ PINCTRL_PIN(71, "GPIO_71"),
	185	+ PINCTRL_PIN(72, "GPIO_72"),
	186	+ PINCTRL_PIN(73, "GPIO_73"),
	187	+ PINCTRL_PIN(74, "GPIO_74"),
	188	+ PINCTRL_PIN(75, "GPIO_75"),
	189	+ PINCTRL_PIN(76, "GPIO_76"),
	190	+ PINCTRL_PIN(77, "GPIO_77"),
	191	+ PINCTRL_PIN(78, "GPIO_78"),
	192	+ PINCTRL_PIN(79, "GPIO_79"),
	193	+ PINCTRL_PIN(80, "GPIO_80"),
	194	+ PINCTRL_PIN(81, "GPIO_81"),
	195	+ PINCTRL_PIN(82, "GPIO_82"),
	196	+ PINCTRL_PIN(83, "GPIO_83"),
	197	+ PINCTRL_PIN(84, "GPIO_84"),
	198	+ PINCTRL_PIN(85, "GPIO_85"),
	199	+ PINCTRL_PIN(86, "GPIO_86"),
	200	+ PINCTRL_PIN(87, "GPIO_87"),
	201	+ PINCTRL_PIN(88, "GPIO_88"),
	202	+ PINCTRL_PIN(89, "GPIO_89"),
	203	+ PINCTRL_PIN(90, "GPIO_90"),
	204	+ PINCTRL_PIN(91, "GPIO_91"),
	205	+ PINCTRL_PIN(92, "GPIO_92"),
	206	+ PINCTRL_PIN(93, "GPIO_93"),
	207	+ PINCTRL_PIN(94, "GPIO_94"),
	208	+ PINCTRL_PIN(95, "GPIO_95"),
	209	+ PINCTRL_PIN(96, "GPIO_96"),
	210	+ PINCTRL_PIN(97, "GPIO_97"),
	211	+ PINCTRL_PIN(98, "GPIO_98"),
	212	+ PINCTRL_PIN(99, "GPIO_99"),
	213	+ PINCTRL_PIN(100, "GPIO_100"),
	214	+ PINCTRL_PIN(101, "GPIO_101"),
	215	+ PINCTRL_PIN(102, "GPIO_102"),
	216	+ PINCTRL_PIN(103, "GPIO_103"),
	217	+ PINCTRL_PIN(104, "GPIO_104"),
	218	+ PINCTRL_PIN(105, "GPIO_105"),
	219	+ PINCTRL_PIN(106, "GPIO_106"),
	220	+ PINCTRL_PIN(107, "GPIO_107"),
	221	+ PINCTRL_PIN(108, "GPIO_108"),
	222	+ PINCTRL_PIN(109, "GPIO_109"),
	223	+ PINCTRL_PIN(110, "GPIO_110"),
	224	+ PINCTRL_PIN(111, "GPIO_111"),
	225	+ PINCTRL_PIN(112, "GPIO_112"),
	226	+ PINCTRL_PIN(113, "GPIO_113"),
	227	+ PINCTRL_PIN(114, "GPIO_114"),
	228	+ PINCTRL_PIN(115, "GPIO_115"),
	229	+ PINCTRL_PIN(116, "GPIO_116"),
	230	+ PINCTRL_PIN(117, "GPIO_117"),
	231	+ PINCTRL_PIN(118, "GPIO_118"),
	232	+ PINCTRL_PIN(119, "GPIO_119"),
	233	+ PINCTRL_PIN(120, "GPIO_120"),
	234	+ PINCTRL_PIN(121, "GPIO_121"),
	235	+ PINCTRL_PIN(122, "GPIO_122"),
	236	+ PINCTRL_PIN(123, "GPIO_123"),
	237	+ PINCTRL_PIN(124, "GPIO_124"),
	238	+ PINCTRL_PIN(125, "GPIO_125"),
	239	+ PINCTRL_PIN(126, "GPIO_126"),
	240	+ PINCTRL_PIN(127, "GPIO_127"),
	241	+ PINCTRL_PIN(128, "GPIO_128"),
	242	+ PINCTRL_PIN(129, "GPIO_129"),
	243	+ PINCTRL_PIN(130, "GPIO_130"),
	244	+ PINCTRL_PIN(131, "GPIO_131"),
	245	+ PINCTRL_PIN(132, "GPIO_132"),
	246	+ PINCTRL_PIN(133, "GPIO_133"),
	247	+ PINCTRL_PIN(134, "GPIO_134"),
	248	+ PINCTRL_PIN(135, "GPIO_135"),
	249	+ PINCTRL_PIN(136, "GPIO_136"),
	250	+ PINCTRL_PIN(137, "GPIO_137"),
	251	+ PINCTRL_PIN(138, "GPIO_138"),
	252	+ PINCTRL_PIN(139, "GPIO_139"),
	253	+ PINCTRL_PIN(140, "GPIO_140"),
	254	+ PINCTRL_PIN(141, "GPIO_141"),
	255	+ PINCTRL_PIN(142, "GPIO_142"),
	256	+ PINCTRL_PIN(143, "GPIO_143"),
	257	+ PINCTRL_PIN(144, "GPIO_144"),
	258	+ PINCTRL_PIN(145, "GPIO_145"),
	259	+ PINCTRL_PIN(146, "GPIO_146"),
	260	+ PINCTRL_PIN(147, "GPIO_147"),
	261	+ PINCTRL_PIN(148, "GPIO_148"),
	262	+ PINCTRL_PIN(149, "GPIO_149"),
	263	+ PINCTRL_PIN(150, "GPIO_150"),
	264	+ PINCTRL_PIN(151, "GPIO_151"),
	265	+ PINCTRL_PIN(152, "GPIO_152"),
	266	+ PINCTRL_PIN(153, "GPIO_153"),
	267	+ PINCTRL_PIN(154, "GPIO_154"),
	268	+ PINCTRL_PIN(155, "GPIO_155"),
	269	+ PINCTRL_PIN(156, "GPIO_156"),
	270	+ PINCTRL_PIN(157, "GPIO_157"),
	271	+ PINCTRL_PIN(158, "GPIO_158"),
	272	+ PINCTRL_PIN(159, "GPIO_159"),
	273	+ PINCTRL_PIN(160, "GPIO_160"),
	274	+ PINCTRL_PIN(161, "GPIO_161"),
	275	+ PINCTRL_PIN(162, "GPIO_162"),
	276	+ PINCTRL_PIN(163, "GPIO_163"),
	277	+ PINCTRL_PIN(164, "GPIO_164"),
	278	+ PINCTRL_PIN(165, "GPIO_165"),
	279	+ PINCTRL_PIN(166, "GPIO_166"),
	280	+ PINCTRL_PIN(167, "GPIO_167"),
	281	+ PINCTRL_PIN(168, "GPIO_168"),
	282	+ PINCTRL_PIN(169, "GPIO_169"),
	283	+ PINCTRL_PIN(170, "GPIO_170"),
	284	+ PINCTRL_PIN(171, "GPIO_171"),
	285	+ PINCTRL_PIN(172, "GPIO_172"),
	286	+ PINCTRL_PIN(173, "GPIO_173"),
	287	+ PINCTRL_PIN(174, "GPIO_174"),
	288	+ PINCTRL_PIN(175, "GPIO_175"),
	289	+ PINCTRL_PIN(176, "GPIO_176"),
	290	+ PINCTRL_PIN(177, "GPIO_177"),
	291	+ PINCTRL_PIN(178, "GPIO_178"),
	292	+ PINCTRL_PIN(179, "GPIO_179"),
	293	+ PINCTRL_PIN(180, "GPIO_180"),
	294	+ PINCTRL_PIN(181, "GPIO_181"),
	295	+ PINCTRL_PIN(182, "GPIO_182"),
	296	+ PINCTRL_PIN(183, "GPIO_183"),
	297	+ PINCTRL_PIN(184, "GPIO_184"),
	298	+ PINCTRL_PIN(185, "GPIO_185"),
	299	+ PINCTRL_PIN(186, "GPIO_186"),
	300	+ PINCTRL_PIN(187, "GPIO_187"),
	301	+ PINCTRL_PIN(188, "GPIO_188"),
	302	+ PINCTRL_PIN(189, "GPIO_189"),
	303	+ PINCTRL_PIN(190, "GPIO_190"),
	304	+ PINCTRL_PIN(191, "GPIO_191"),
	305	+ PINCTRL_PIN(192, "GPIO_192"),
	306	+ PINCTRL_PIN(193, "GPIO_193"),
	307	+ PINCTRL_PIN(194, "GPIO_194"),
	308	+ PINCTRL_PIN(195, "GPIO_195"),
	309	+ PINCTRL_PIN(196, "GPIO_196"),
	310	+ PINCTRL_PIN(197, "GPIO_197"),
	311	+ PINCTRL_PIN(198, "GPIO_198"),
	312	+ PINCTRL_PIN(199, "GPIO_199"),
	313	+ PINCTRL_PIN(200, "GPIO_200"),
	314	+ PINCTRL_PIN(201, "GPIO_201"),
	315	+ PINCTRL_PIN(202, "GPIO_202"),
	316	+ PINCTRL_PIN(203, "UFS_RESET"),
	317	+ PINCTRL_PIN(204, "SDC2_CLK"),
	318	+ PINCTRL_PIN(205, "SDC2_CMD"),
	319	+ PINCTRL_PIN(206, "SDC2_DATA"),
	320	+};
	321	+
	322	+#define DECLARE_MSM_GPIO_PINS(pin) \
	323	+ static const unsigned int gpio##pin##_pins[] = { pin }
	324	+DECLARE_MSM_GPIO_PINS(0);
	325	+DECLARE_MSM_GPIO_PINS(1);
	326	+DECLARE_MSM_GPIO_PINS(2);
	327	+DECLARE_MSM_GPIO_PINS(3);
	328	+DECLARE_MSM_GPIO_PINS(4);
	329	+DECLARE_MSM_GPIO_PINS(5);
	330	+DECLARE_MSM_GPIO_PINS(6);
	331	+DECLARE_MSM_GPIO_PINS(7);
	332	+DECLARE_MSM_GPIO_PINS(8);
	333	+DECLARE_MSM_GPIO_PINS(9);
	334	+DECLARE_MSM_GPIO_PINS(10);
	335	+DECLARE_MSM_GPIO_PINS(11);
	336	+DECLARE_MSM_GPIO_PINS(12);
	337	+DECLARE_MSM_GPIO_PINS(13);
	338	+DECLARE_MSM_GPIO_PINS(14);
	339	+DECLARE_MSM_GPIO_PINS(15);
	340	+DECLARE_MSM_GPIO_PINS(16);
	341	+DECLARE_MSM_GPIO_PINS(17);
	342	+DECLARE_MSM_GPIO_PINS(18);
	343	+DECLARE_MSM_GPIO_PINS(19);
	344	+DECLARE_MSM_GPIO_PINS(20);
	345	+DECLARE_MSM_GPIO_PINS(21);
	346	+DECLARE_MSM_GPIO_PINS(22);
	347	+DECLARE_MSM_GPIO_PINS(23);
	348	+DECLARE_MSM_GPIO_PINS(24);
	349	+DECLARE_MSM_GPIO_PINS(25);
	350	+DECLARE_MSM_GPIO_PINS(26);
	351	+DECLARE_MSM_GPIO_PINS(27);
	352	+DECLARE_MSM_GPIO_PINS(28);
	353	+DECLARE_MSM_GPIO_PINS(29);
	354	+DECLARE_MSM_GPIO_PINS(30);
	355	+DECLARE_MSM_GPIO_PINS(31);
	356	+DECLARE_MSM_GPIO_PINS(32);
	357	+DECLARE_MSM_GPIO_PINS(33);
	358	+DECLARE_MSM_GPIO_PINS(34);
	359	+DECLARE_MSM_GPIO_PINS(35);
	360	+DECLARE_MSM_GPIO_PINS(36);
	361	+DECLARE_MSM_GPIO_PINS(37);
	362	+DECLARE_MSM_GPIO_PINS(38);
	363	+DECLARE_MSM_GPIO_PINS(39);
	364	+DECLARE_MSM_GPIO_PINS(40);
	365	+DECLARE_MSM_GPIO_PINS(41);
	366	+DECLARE_MSM_GPIO_PINS(42);
	367	+DECLARE_MSM_GPIO_PINS(43);
	368	+DECLARE_MSM_GPIO_PINS(44);
	369	+DECLARE_MSM_GPIO_PINS(45);
	370	+DECLARE_MSM_GPIO_PINS(46);
	371	+DECLARE_MSM_GPIO_PINS(47);
	372	+DECLARE_MSM_GPIO_PINS(48);
	373	+DECLARE_MSM_GPIO_PINS(49);
	374	+DECLARE_MSM_GPIO_PINS(50);
	375	+DECLARE_MSM_GPIO_PINS(51);
	376	+DECLARE_MSM_GPIO_PINS(52);
	377	+DECLARE_MSM_GPIO_PINS(53);
	378	+DECLARE_MSM_GPIO_PINS(54);
	379	+DECLARE_MSM_GPIO_PINS(55);
	380	+DECLARE_MSM_GPIO_PINS(56);
	381	+DECLARE_MSM_GPIO_PINS(57);
	382	+DECLARE_MSM_GPIO_PINS(58);
	383	+DECLARE_MSM_GPIO_PINS(59);
	384	+DECLARE_MSM_GPIO_PINS(60);
	385	+DECLARE_MSM_GPIO_PINS(61);
	386	+DECLARE_MSM_GPIO_PINS(62);
	387	+DECLARE_MSM_GPIO_PINS(63);
	388	+DECLARE_MSM_GPIO_PINS(64);
	389	+DECLARE_MSM_GPIO_PINS(65);
	390	+DECLARE_MSM_GPIO_PINS(66);
	391	+DECLARE_MSM_GPIO_PINS(67);
	392	+DECLARE_MSM_GPIO_PINS(68);
	393	+DECLARE_MSM_GPIO_PINS(69);
	394	+DECLARE_MSM_GPIO_PINS(70);
	395	+DECLARE_MSM_GPIO_PINS(71);
	396	+DECLARE_MSM_GPIO_PINS(72);
	397	+DECLARE_MSM_GPIO_PINS(73);
	398	+DECLARE_MSM_GPIO_PINS(74);
	399	+DECLARE_MSM_GPIO_PINS(75);
	400	+DECLARE_MSM_GPIO_PINS(76);
	401	+DECLARE_MSM_GPIO_PINS(77);
	402	+DECLARE_MSM_GPIO_PINS(78);
	403	+DECLARE_MSM_GPIO_PINS(79);
	404	+DECLARE_MSM_GPIO_PINS(80);
	405	+DECLARE_MSM_GPIO_PINS(81);
	406	+DECLARE_MSM_GPIO_PINS(82);
	407	+DECLARE_MSM_GPIO_PINS(83);
	408	+DECLARE_MSM_GPIO_PINS(84);
	409	+DECLARE_MSM_GPIO_PINS(85);
	410	+DECLARE_MSM_GPIO_PINS(86);
	411	+DECLARE_MSM_GPIO_PINS(87);
	412	+DECLARE_MSM_GPIO_PINS(88);
	413	+DECLARE_MSM_GPIO_PINS(89);
	414	+DECLARE_MSM_GPIO_PINS(90);
	415	+DECLARE_MSM_GPIO_PINS(91);
	416	+DECLARE_MSM_GPIO_PINS(92);
	417	+DECLARE_MSM_GPIO_PINS(93);
	418	+DECLARE_MSM_GPIO_PINS(94);
	419	+DECLARE_MSM_GPIO_PINS(95);
	420	+DECLARE_MSM_GPIO_PINS(96);
	421	+DECLARE_MSM_GPIO_PINS(97);
	422	+DECLARE_MSM_GPIO_PINS(98);
	423	+DECLARE_MSM_GPIO_PINS(99);
	424	+DECLARE_MSM_GPIO_PINS(100);
	425	+DECLARE_MSM_GPIO_PINS(101);
	426	+DECLARE_MSM_GPIO_PINS(102);
	427	+DECLARE_MSM_GPIO_PINS(103);
	428	+DECLARE_MSM_GPIO_PINS(104);
	429	+DECLARE_MSM_GPIO_PINS(105);
	430	+DECLARE_MSM_GPIO_PINS(106);
	431	+DECLARE_MSM_GPIO_PINS(107);
	432	+DECLARE_MSM_GPIO_PINS(108);
	433	+DECLARE_MSM_GPIO_PINS(109);
	434	+DECLARE_MSM_GPIO_PINS(110);
	435	+DECLARE_MSM_GPIO_PINS(111);
	436	+DECLARE_MSM_GPIO_PINS(112);
	437	+DECLARE_MSM_GPIO_PINS(113);
	438	+DECLARE_MSM_GPIO_PINS(114);
	439	+DECLARE_MSM_GPIO_PINS(115);
	440	+DECLARE_MSM_GPIO_PINS(116);
	441	+DECLARE_MSM_GPIO_PINS(117);
	442	+DECLARE_MSM_GPIO_PINS(118);
	443	+DECLARE_MSM_GPIO_PINS(119);
	444	+DECLARE_MSM_GPIO_PINS(120);
	445	+DECLARE_MSM_GPIO_PINS(121);
	446	+DECLARE_MSM_GPIO_PINS(122);
	447	+DECLARE_MSM_GPIO_PINS(123);
	448	+DECLARE_MSM_GPIO_PINS(124);
	449	+DECLARE_MSM_GPIO_PINS(125);
	450	+DECLARE_MSM_GPIO_PINS(126);
	451	+DECLARE_MSM_GPIO_PINS(127);
	452	+DECLARE_MSM_GPIO_PINS(128);
	453	+DECLARE_MSM_GPIO_PINS(129);
	454	+DECLARE_MSM_GPIO_PINS(130);
	455	+DECLARE_MSM_GPIO_PINS(131);
	456	+DECLARE_MSM_GPIO_PINS(132);
	457	+DECLARE_MSM_GPIO_PINS(133);
	458	+DECLARE_MSM_GPIO_PINS(134);
	459	+DECLARE_MSM_GPIO_PINS(135);
	460	+DECLARE_MSM_GPIO_PINS(136);
	461	+DECLARE_MSM_GPIO_PINS(137);
	462	+DECLARE_MSM_GPIO_PINS(138);
	463	+DECLARE_MSM_GPIO_PINS(139);
	464	+DECLARE_MSM_GPIO_PINS(140);
	465	+DECLARE_MSM_GPIO_PINS(141);
	466	+DECLARE_MSM_GPIO_PINS(142);
	467	+DECLARE_MSM_GPIO_PINS(143);
	468	+DECLARE_MSM_GPIO_PINS(144);
	469	+DECLARE_MSM_GPIO_PINS(145);
	470	+DECLARE_MSM_GPIO_PINS(146);
	471	+DECLARE_MSM_GPIO_PINS(147);
	472	+DECLARE_MSM_GPIO_PINS(148);
	473	+DECLARE_MSM_GPIO_PINS(149);
	474	+DECLARE_MSM_GPIO_PINS(150);
	475	+DECLARE_MSM_GPIO_PINS(151);
	476	+DECLARE_MSM_GPIO_PINS(152);
	477	+DECLARE_MSM_GPIO_PINS(153);
	478	+DECLARE_MSM_GPIO_PINS(154);
	479	+DECLARE_MSM_GPIO_PINS(155);
	480	+DECLARE_MSM_GPIO_PINS(156);
	481	+DECLARE_MSM_GPIO_PINS(157);
	482	+DECLARE_MSM_GPIO_PINS(158);
	483	+DECLARE_MSM_GPIO_PINS(159);
	484	+DECLARE_MSM_GPIO_PINS(160);
	485	+DECLARE_MSM_GPIO_PINS(161);
	486	+DECLARE_MSM_GPIO_PINS(162);
	487	+DECLARE_MSM_GPIO_PINS(163);
	488	+DECLARE_MSM_GPIO_PINS(164);
	489	+DECLARE_MSM_GPIO_PINS(165);
	490	+DECLARE_MSM_GPIO_PINS(166);
	491	+DECLARE_MSM_GPIO_PINS(167);
	492	+DECLARE_MSM_GPIO_PINS(168);
	493	+DECLARE_MSM_GPIO_PINS(169);
	494	+DECLARE_MSM_GPIO_PINS(170);
	495	+DECLARE_MSM_GPIO_PINS(171);
	496	+DECLARE_MSM_GPIO_PINS(172);
	497	+DECLARE_MSM_GPIO_PINS(173);
	498	+DECLARE_MSM_GPIO_PINS(174);
	499	+DECLARE_MSM_GPIO_PINS(175);
	500	+DECLARE_MSM_GPIO_PINS(176);
	501	+DECLARE_MSM_GPIO_PINS(177);
	502	+DECLARE_MSM_GPIO_PINS(178);
	503	+DECLARE_MSM_GPIO_PINS(179);
	504	+DECLARE_MSM_GPIO_PINS(180);
	505	+DECLARE_MSM_GPIO_PINS(181);
	506	+DECLARE_MSM_GPIO_PINS(182);
	507	+DECLARE_MSM_GPIO_PINS(183);
	508	+DECLARE_MSM_GPIO_PINS(184);
	509	+DECLARE_MSM_GPIO_PINS(185);
	510	+DECLARE_MSM_GPIO_PINS(186);
	511	+DECLARE_MSM_GPIO_PINS(187);
	512	+DECLARE_MSM_GPIO_PINS(188);
	513	+DECLARE_MSM_GPIO_PINS(189);
	514	+DECLARE_MSM_GPIO_PINS(190);
	515	+DECLARE_MSM_GPIO_PINS(191);
	516	+DECLARE_MSM_GPIO_PINS(192);
	517	+DECLARE_MSM_GPIO_PINS(193);
	518	+DECLARE_MSM_GPIO_PINS(194);
	519	+DECLARE_MSM_GPIO_PINS(195);
	520	+DECLARE_MSM_GPIO_PINS(196);
	521	+DECLARE_MSM_GPIO_PINS(197);
	522	+DECLARE_MSM_GPIO_PINS(198);
	523	+DECLARE_MSM_GPIO_PINS(199);
	524	+DECLARE_MSM_GPIO_PINS(200);
	525	+DECLARE_MSM_GPIO_PINS(201);
	526	+DECLARE_MSM_GPIO_PINS(202);
	527	+
	528	+static const unsigned int ufs_reset_pins[] = { 203 };
	529	+static const unsigned int sdc2_clk_pins[] = { 204 };
	530	+static const unsigned int sdc2_cmd_pins[] = { 205 };
	531	+static const unsigned int sdc2_data_pins[] = { 206 };
	532	+
	533	+enum sm8350_functions {
	534	+ msm_mux_atest_char,
	535	+ msm_mux_atest_usb,
	536	+ msm_mux_audio_ref,
	537	+ msm_mux_cam_mclk,
	538	+ msm_mux_cci_async,
	539	+ msm_mux_cci_i2c,
	540	+ msm_mux_cci_timer,
	541	+ msm_mux_cmu_rng,
	542	+ msm_mux_coex_uart1,
	543	+ msm_mux_coex_uart2,
	544	+ msm_mux_cri_trng,
	545	+ msm_mux_cri_trng0,
	546	+ msm_mux_cri_trng1,
	547	+ msm_mux_dbg_out,
	548	+ msm_mux_ddr_bist,
	549	+ msm_mux_ddr_pxi0,
	550	+ msm_mux_ddr_pxi1,
	551	+ msm_mux_ddr_pxi2,
	552	+ msm_mux_ddr_pxi3,
	553	+ msm_mux_dp_hot,
	554	+ msm_mux_dp_lcd,
	555	+ msm_mux_gcc_gp1,
	556	+ msm_mux_gcc_gp2,
	557	+ msm_mux_gcc_gp3,
	558	+ msm_mux_gpio,
	559	+ msm_mux_ibi_i3c,
	560	+ msm_mux_jitter_bist,
	561	+ msm_mux_lpass_slimbus,
	562	+ msm_mux_mdp_vsync,
	563	+ msm_mux_mdp_vsync0,
	564	+ msm_mux_mdp_vsync1,
	565	+ msm_mux_mdp_vsync2,
	566	+ msm_mux_mdp_vsync3,
	567	+ msm_mux_mi2s0_data0,
	568	+ msm_mux_mi2s0_data1,
	569	+ msm_mux_mi2s0_sck,
	570	+ msm_mux_mi2s0_ws,
	571	+ msm_mux_mi2s1_data0,
	572	+ msm_mux_mi2s1_data1,
	573	+ msm_mux_mi2s1_sck,
	574	+ msm_mux_mi2s1_ws,
	575	+ msm_mux_mi2s2_data0,
	576	+ msm_mux_mi2s2_data1,
	577	+ msm_mux_mi2s2_sck,
	578	+ msm_mux_mi2s2_ws,
	579	+ msm_mux_mss_grfc0,
	580	+ msm_mux_mss_grfc1,
	581	+ msm_mux_mss_grfc10,
	582	+ msm_mux_mss_grfc11,
	583	+ msm_mux_mss_grfc12,
	584	+ msm_mux_mss_grfc2,
	585	+ msm_mux_mss_grfc3,
	586	+ msm_mux_mss_grfc4,
	587	+ msm_mux_mss_grfc5,
	588	+ msm_mux_mss_grfc6,
	589	+ msm_mux_mss_grfc7,
	590	+ msm_mux_mss_grfc8,
	591	+ msm_mux_mss_grfc9,
	592	+ msm_mux_nav_gpio,
	593	+ msm_mux_pa_indicator,
	594	+ msm_mux_pcie0_clkreqn,
	595	+ msm_mux_pcie1_clkreqn,
	596	+ msm_mux_phase_flag,
	597	+ msm_mux_pll_bist,
	598	+ msm_mux_pll_clk,
	599	+ msm_mux_pri_mi2s,
	600	+ msm_mux_prng_rosc,
	601	+ msm_mux_qdss_cti,
	602	+ msm_mux_qdss_gpio,
	603	+ msm_mux_qlink0_enable,
	604	+ msm_mux_qlink0_request,
	605	+ msm_mux_qlink0_wmss,
	606	+ msm_mux_qlink1_enable,
	607	+ msm_mux_qlink1_request,
	608	+ msm_mux_qlink1_wmss,
	609	+ msm_mux_qlink2_enable,
	610	+ msm_mux_qlink2_request,
	611	+ msm_mux_qlink2_wmss,
	612	+ msm_mux_qspi0,
	613	+ msm_mux_qspi1,
	614	+ msm_mux_qspi2,
	615	+ msm_mux_qspi3,
	616	+ msm_mux_qspi_clk,
	617	+ msm_mux_qspi_cs,
	618	+ msm_mux_qup0,
	619	+ msm_mux_qup1,
	620	+ msm_mux_qup10,
	621	+ msm_mux_qup11,
	622	+ msm_mux_qup12,
	623	+ msm_mux_qup13,
	624	+ msm_mux_qup14,
	625	+ msm_mux_qup15,
	626	+ msm_mux_qup16,
	627	+ msm_mux_qup17,
	628	+ msm_mux_qup18,
	629	+ msm_mux_qup19,
	630	+ msm_mux_qup2,
	631	+ msm_mux_qup3,
	632	+ msm_mux_qup4,
	633	+ msm_mux_qup5,
	634	+ msm_mux_qup6,
	635	+ msm_mux_qup7,
	636	+ msm_mux_qup8,
	637	+ msm_mux_qup9,
	638	+ msm_mux_qup_l4,
	639	+ msm_mux_qup_l5,
	640	+ msm_mux_qup_l6,
	641	+ msm_mux_sd_write,
	642	+ msm_mux_sdc40,
	643	+ msm_mux_sdc41,
	644	+ msm_mux_sdc42,
	645	+ msm_mux_sdc43,
	646	+ msm_mux_sdc4_clk,
	647	+ msm_mux_sdc4_cmd,
	648	+ msm_mux_sec_mi2s,
	649	+ msm_mux_tb_trig,
	650	+ msm_mux_tgu_ch0,
	651	+ msm_mux_tgu_ch1,
	652	+ msm_mux_tgu_ch2,
	653	+ msm_mux_tgu_ch3,
	654	+ msm_mux_tsense_pwm1,
	655	+ msm_mux_tsense_pwm2,
	656	+ msm_mux_uim0_clk,
	657	+ msm_mux_uim0_data,
	658	+ msm_mux_uim0_present,
	659	+ msm_mux_uim0_reset,
	660	+ msm_mux_uim1_clk,
	661	+ msm_mux_uim1_data,
	662	+ msm_mux_uim1_present,
	663	+ msm_mux_uim1_reset,
	664	+ msm_mux_usb2phy_ac,
	665	+ msm_mux_usb_phy,
	666	+ msm_mux_vfr_0,
	667	+ msm_mux_vfr_1,
	668	+ msm_mux_vsense_trigger,
	669	+ msm_mux__,
	670	+};
	671	+
	672	+static const char * const gpio_groups[] = {
	673	+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
	674	+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
	675	+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
	676	+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
	677	+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
	678	+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
	679	+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
	680	+ "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
	681	+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
	682	+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
	683	+ "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
	684	+ "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
	685	+ "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
	686	+ "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
	687	+ "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
	688	+ "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
	689	+ "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
	690	+ "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
	691	+ "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
	692	+ "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
	693	+ "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
	694	+ "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
	695	+ "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
	696	+ "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158",
	697	+ "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
	698	+ "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
	699	+ "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176",
	700	+ "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182",
	701	+ "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188",
	702	+ "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194",
	703	+ "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200",
	704	+ "gpio201", "gpio202",
	705	+};
	706	+
	707	+static const char * const atest_char_groups[] = {
	708	+ "gpio85", "gpio86", "gpio87", "gpio115", "gpio117",
	709	+};
	710	+
	711	+static const char * const atest_usb_groups[] = {
	712	+ "gpio55", "gpio80", "gpio81", "gpio151", "gpio152",
	713	+ "gpio153", "gpio154", "gpio158", "gpio159", "gpio161",
	714	+};
	715	+
	716	+static const char * const audio_ref_groups[] = {
	717	+ "gpio124",
	718	+};
	719	+
	720	+static const char * const cam_mclk_groups[] = {
	721	+ "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105",
	722	+};
	723	+
	724	+static const char * const cci_async_groups[] = {
	725	+ "gpio106", "gpio118", "gpio119",
	726	+};
	727	+
	728	+static const char * const cci_i2c_groups[] = {
	729	+ "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", "gpio112",
	730	+ "gpio113", "gpio114",
	731	+};
	732	+
	733	+static const char * const cci_timer_groups[] = {
	734	+ "gpio115", "gpio116", "gpio117", "gpio118", "gpio119",
	735	+};
	736	+
	737	+static const char * const cmu_rng_groups[] = {
	738	+ "gpio174", "gpio175", "gpio176", "gpio177",
	739	+};
	740	+
	741	+static const char * const coex_uart1_groups[] = {
	742	+ "gpio151", "gpio152",
	743	+};
	744	+
	745	+static const char * const coex_uart2_groups[] = {
	746	+ "gpio153", "gpio154",
	747	+};
	748	+
	749	+static const char * const cri_trng_groups[] = {
	750	+ "gpio186",
	751	+};
	752	+
	753	+static const char * const cri_trng0_groups[] = {
	754	+ "gpio183",
	755	+};
	756	+
	757	+static const char * const cri_trng1_groups[] = {
	758	+ "gpio184",
	759	+};
	760	+
	761	+static const char * const dbg_out_groups[] = {
	762	+ "gpio14",
	763	+};
	764	+
	765	+static const char * const ddr_bist_groups[] = {
	766	+ "gpio36", "gpio37", "gpio40", "gpio41",
	767	+};
	768	+
	769	+static const char * const ddr_pxi0_groups[] = {
	770	+ "gpio51", "gpio52",
	771	+};
	772	+
	773	+static const char * const ddr_pxi1_groups[] = {
	774	+ "gpio48", "gpio49",
	775	+};
	776	+
	777	+static const char * const ddr_pxi2_groups[] = {
	778	+ "gpio45", "gpio47",
	779	+};
	780	+
	781	+static const char * const ddr_pxi3_groups[] = {
	782	+ "gpio43", "gpio44",
	783	+};
	784	+
	785	+static const char * const dp_hot_groups[] = {
	786	+ "gpio87",
	787	+};
	788	+
	789	+static const char * const dp_lcd_groups[] = {
	790	+ "gpio83",
	791	+};
	792	+
	793	+static const char * const gcc_gp1_groups[] = {
	794	+ "gpio115", "gpio129",
	795	+};
	796	+
	797	+static const char * const gcc_gp2_groups[] = {
	798	+ "gpio116", "gpio130",
	799	+};
	800	+
	801	+static const char * const gcc_gp3_groups[] = {
	802	+ "gpio117", "gpio131",
	803	+};
	804	+
	805	+static const char * const ibi_i3c_groups[] = {
	806	+ "gpio36", "gpio37", "gpio56", "gpio57", "gpio60", "gpio61",
	807	+};
	808	+
	809	+static const char * const jitter_bist_groups[] = {
	810	+ "gpio80",
	811	+};
	812	+
	813	+static const char * const lpass_slimbus_groups[] = {
	814	+ "gpio129", "gpio130",
	815	+};
	816	+
	817	+static const char * const mdp_vsync_groups[] = {
	818	+ "gpio15", "gpio26", "gpio82", "gpio83", "gpio84",
	819	+};
	820	+
	821	+static const char * const mdp_vsync0_groups[] = {
	822	+ "gpio86",
	823	+};
	824	+
	825	+static const char * const mdp_vsync1_groups[] = {
	826	+ "gpio86",
	827	+};
	828	+
	829	+static const char * const mdp_vsync2_groups[] = {
	830	+ "gpio87",
	831	+};
	832	+
	833	+static const char * const mdp_vsync3_groups[] = {
	834	+ "gpio87",
	835	+};
	836	+
	837	+static const char * const mi2s0_data0_groups[] = {
	838	+ "gpio126",
	839	+};
	840	+
	841	+static const char * const mi2s0_data1_groups[] = {
	842	+ "gpio127",
	843	+};
	844	+
	845	+static const char * const mi2s0_sck_groups[] = {
	846	+ "gpio125",
	847	+};
	848	+
	849	+static const char * const mi2s0_ws_groups[] = {
	850	+ "gpio128",
	851	+};
	852	+
	853	+static const char * const mi2s1_data0_groups[] = {
	854	+ "gpio130",
	855	+};
	856	+
	857	+static const char * const mi2s1_data1_groups[] = {
	858	+ "gpio131",
	859	+};
	860	+
	861	+static const char * const mi2s1_sck_groups[] = {
	862	+ "gpio129",
	863	+};
	864	+
	865	+static const char * const mi2s1_ws_groups[] = {
	866	+ "gpio132",
	867	+};
	868	+
	869	+static const char * const mi2s2_data0_groups[] = {
	870	+ "gpio121",
	871	+};
	872	+
	873	+static const char * const mi2s2_data1_groups[] = {
	874	+ "gpio124",
	875	+};
	876	+
	877	+static const char * const mi2s2_sck_groups[] = {
	878	+ "gpio120",
	879	+};
	880	+
	881	+static const char * const mi2s2_ws_groups[] = {
	882	+ "gpio122",
	883	+};
	884	+
	885	+static const char * const mss_grfc0_groups[] = {
	886	+ "gpio141", "gpio158",
	887	+};
	888	+
	889	+static const char * const mss_grfc1_groups[] = {
	890	+ "gpio142",
	891	+};
	892	+
	893	+static const char * const mss_grfc10_groups[] = {
	894	+ "gpio153",
	895	+};
	896	+
	897	+static const char * const mss_grfc11_groups[] = {
	898	+ "gpio154",
	899	+};
	900	+
	901	+static const char * const mss_grfc12_groups[] = {
	902	+ "gpio157",
	903	+};
	904	+
	905	+static const char * const mss_grfc2_groups[] = {
	906	+ "gpio143",
	907	+};
	908	+
	909	+static const char * const mss_grfc3_groups[] = {
	910	+ "gpio144",
	911	+};
	912	+
	913	+static const char * const mss_grfc4_groups[] = {
	914	+ "gpio145",
	915	+};
	916	+
	917	+static const char * const mss_grfc5_groups[] = {
	918	+ "gpio146",
	919	+};
	920	+
	921	+static const char * const mss_grfc6_groups[] = {
	922	+ "gpio147",
	923	+};
	924	+
	925	+static const char * const mss_grfc7_groups[] = {
	926	+ "gpio148",
	927	+};
	928	+
	929	+static const char * const mss_grfc8_groups[] = {
	930	+ "gpio149",
	931	+};
	932	+
	933	+static const char * const mss_grfc9_groups[] = {
	934	+ "gpio150",
	935	+};
	936	+
	937	+static const char * const nav_gpio_groups[] = {
	938	+ "gpio155", "gpio156", "gpio157",
	939	+};
	940	+
	941	+static const char * const pa_indicator_groups[] = {
	942	+ "gpio157",
	943	+};
	944	+
	945	+static const char * const pcie0_clkreqn_groups[] = {
	946	+ "gpio95",
	947	+};
	948	+
	949	+static const char * const pcie1_clkreqn_groups[] = {
	950	+ "gpio98",
	951	+};
	952	+
	953	+static const char * const phase_flag_groups[] = {
	954	+ "gpio12", "gpio13", "gpio16", "gpio17", "gpio28", "gpio29", "gpio30",
	955	+ "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio72", "gpio73",
	956	+ "gpio74", "gpio75", "gpio76", "gpio77", "gpio78", "gpio79", "gpio103",
	957	+ "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109",
	958	+ "gpio110", "gpio111", "gpio112", "gpio113", "gpio114",
	959	+};
	960	+
	961	+static const char * const pll_bist_groups[] = {
	962	+ "gpio81",
	963	+};
	964	+
	965	+static const char * const pll_clk_groups[] = {
	966	+ "gpio81",
	967	+};
	968	+
	969	+static const char * const pri_mi2s_groups[] = {
	970	+ "gpio123",
	971	+};
	972	+
	973	+static const char * const prng_rosc_groups[] = {
	974	+ "gpio185",
	975	+};
	976	+
	977	+static const char * const qdss_cti_groups[] = {
	978	+ "gpio14", "gpio27", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", "gpio92",
	979	+};
	980	+
	981	+static const char * const qdss_gpio_groups[] = {
	982	+ "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107",
	983	+ "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115",
	984	+ "gpio116", "gpio117", "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188",
	985	+ "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", "gpio195", "gpio196",
	986	+ "gpio197", "gpio198", "gpio199", "gpio200",
	987	+};
	988	+
	989	+static const char * const qlink0_enable_groups[] = {
	990	+ "gpio160",
	991	+};
	992	+
	993	+static const char * const qlink0_request_groups[] = {
	994	+ "gpio159",
	995	+};
	996	+
	997	+static const char * const qlink0_wmss_groups[] = {
	998	+ "gpio161",
	999	+};
	1000	+
	1001	+static const char * const qlink1_enable_groups[] = {
	1002	+ "gpio163",
	1003	+};
	1004	+
	1005	+static const char * const qlink1_request_groups[] = {
	1006	+ "gpio162",
	1007	+};
	1008	+
	1009	+static const char * const qlink1_wmss_groups[] = {
	1010	+ "gpio164",
	1011	+};
	1012	+
	1013	+static const char * const qlink2_enable_groups[] = {
	1014	+ "gpio166",
	1015	+};
	1016	+
	1017	+static const char * const qlink2_request_groups[] = {
	1018	+ "gpio165",
	1019	+};
	1020	+
	1021	+static const char * const qlink2_wmss_groups[] = {
	1022	+ "gpio167",
	1023	+};
	1024	+
	1025	+static const char * const qspi0_groups[] = {
	1026	+ "gpio44",
	1027	+};
	1028	+
	1029	+static const char * const qspi1_groups[] = {
	1030	+ "gpio45",
	1031	+};
	1032	+
	1033	+static const char * const qspi2_groups[] = {
	1034	+ "gpio48",
	1035	+};
	1036	+
	1037	+static const char * const qspi3_groups[] = {
	1038	+ "gpio49",
	1039	+};
	1040	+
	1041	+static const char * const qspi_clk_groups[] = {
	1042	+ "gpio50",
	1043	+};
	1044	+
	1045	+static const char * const qspi_cs_groups[] = {
	1046	+ "gpio47", "gpio51",
	1047	+};
	1048	+
	1049	+static const char * const qup0_groups[] = {
	1050	+ "gpio4", "gpio5", "gpio6", "gpio7",
	1051	+};
	1052	+
	1053	+static const char * const qup1_groups[] = {
	1054	+ "gpio8", "gpio9", "gpio10", "gpio11",
	1055	+};
	1056	+
	1057	+static const char * const qup10_groups[] = {
	1058	+ "gpio44", "gpio45", "gpio46", "gpio47",
	1059	+};
	1060	+
	1061	+static const char * const qup11_groups[] = {
	1062	+ "gpio48", "gpio49", "gpio50", "gpio51",
	1063	+};
	1064	+
	1065	+static const char * const qup12_groups[] = {
	1066	+ "gpio52", "gpio53", "gpio54", "gpio55",
	1067	+};
	1068	+
	1069	+static const char * const qup13_groups[] = {
	1070	+ "gpio0", "gpio1", "gpio2", "gpio3",
	1071	+};
	1072	+
	1073	+static const char * const qup14_groups[] = {
	1074	+ "gpio56", "gpio57", "gpio58", "gpio59",
	1075	+};
	1076	+
	1077	+static const char * const qup15_groups[] = {
	1078	+ "gpio60", "gpio61", "gpio62", "gpio63",
	1079	+};
	1080	+
	1081	+static const char * const qup16_groups[] = {
	1082	+ "gpio64", "gpio65", "gpio66", "gpio67",
	1083	+};
	1084	+
	1085	+static const char * const qup17_groups[] = {
	1086	+ "gpio72", "gpio73", "gpio74", "gpio75",
	1087	+};
	1088	+
	1089	+static const char * const qup18_groups[] = {
	1090	+ "gpio68", "gpio69", "gpio70", "gpio71",
	1091	+};
	1092	+
	1093	+static const char * const qup19_groups[] = {
	1094	+ "gpio76", "gpio77", "gpio78", "gpio79",
	1095	+};
	1096	+
	1097	+static const char * const qup2_groups[] = {
	1098	+ "gpio12", "gpio13", "gpio14", "gpio15",
	1099	+};
	1100	+
	1101	+static const char * const qup3_groups[] = {
	1102	+ "gpio16", "gpio17", "gpio18", "gpio19",
	1103	+};
	1104	+
	1105	+static const char * const qup4_groups[] = {
	1106	+ "gpio20", "gpio21", "gpio22", "gpio23",
	1107	+};
	1108	+
	1109	+static const char * const qup5_groups[] = {
	1110	+ "gpio24", "gpio25", "gpio26", "gpio27",
	1111	+};
	1112	+
	1113	+static const char * const qup6_groups[] = {
	1114	+ "gpio28", "gpio29", "gpio30", "gpio31",
	1115	+};
	1116	+
	1117	+static const char * const qup7_groups[] = {
	1118	+ "gpio32", "gpio33", "gpio34", "gpio35",
	1119	+};
	1120	+
	1121	+static const char * const qup8_groups[] = {
	1122	+ "gpio36", "gpio37", "gpio38", "gpio39",
	1123	+};
	1124	+
	1125	+static const char * const qup9_groups[] = {
	1126	+ "gpio40", "gpio41", "gpio42", "gpio43",
	1127	+};
	1128	+
	1129	+static const char * const qup_l4_groups[] = {
	1130	+ "gpio2", "gpio6", "gpio58", "gpio63",
	1131	+};
	1132	+
	1133	+static const char * const qup_l5_groups[] = {
	1134	+ "gpio3", "gpio7", "gpio59", "gpio66",
	1135	+};
	1136	+
	1137	+static const char * const qup_l6_groups[] = {
	1138	+ "gpio10", "gpio42", "gpio62", "gpio67",
	1139	+};
	1140	+
	1141	+static const char * const sd_write_groups[] = {
	1142	+ "gpio93",
	1143	+};
	1144	+
	1145	+static const char * const sdc40_groups[] = {
	1146	+ "gpio44",
	1147	+};
	1148	+
	1149	+static const char * const sdc41_groups[] = {
	1150	+ "gpio45",
	1151	+};
	1152	+
	1153	+static const char * const sdc42_groups[] = {
	1154	+ "gpio48",
	1155	+};
	1156	+
	1157	+static const char * const sdc43_groups[] = {
	1158	+ "gpio49",
	1159	+};
	1160	+
	1161	+static const char * const sdc4_clk_groups[] = {
	1162	+ "gpio50",
	1163	+};
	1164	+
	1165	+static const char * const sdc4_cmd_groups[] = {
	1166	+ "gpio51",
	1167	+};
	1168	+
	1169	+static const char * const sec_mi2s_groups[] = {
	1170	+ "gpio124",
	1171	+};
	1172	+
	1173	+static const char * const tb_trig_groups[] = {
	1174	+ "gpio64", "gpio136",
	1175	+};
	1176	+
	1177	+static const char * const tgu_ch0_groups[] = {
	1178	+ "gpio99",
	1179	+};
	1180	+
	1181	+static const char * const tgu_ch1_groups[] = {
	1182	+ "gpio100",
	1183	+};
	1184	+
	1185	+static const char * const tgu_ch2_groups[] = {
	1186	+ "gpio101",
	1187	+};
	1188	+
	1189	+static const char * const tgu_ch3_groups[] = {
	1190	+ "gpio102",
	1191	+};
	1192	+
	1193	+static const char * const tsense_pwm1_groups[] = {
	1194	+ "gpio88",
	1195	+};
	1196	+
	1197	+static const char * const tsense_pwm2_groups[] = {
	1198	+ "gpio88",
	1199	+};
	1200	+
	1201	+static const char * const uim0_clk_groups[] = {
	1202	+ "gpio138",
	1203	+};
	1204	+
	1205	+static const char * const uim0_data_groups[] = {
	1206	+ "gpio137",
	1207	+};
	1208	+
	1209	+static const char * const uim0_present_groups[] = {
	1210	+ "gpio140",
	1211	+};
	1212	+
	1213	+static const char * const uim0_reset_groups[] = {
	1214	+ "gpio139",
	1215	+};
	1216	+
	1217	+static const char * const uim1_clk_groups[] = {
	1218	+ "gpio134",
	1219	+};
	1220	+
	1221	+static const char * const uim1_data_groups[] = {
	1222	+ "gpio133",
	1223	+};
	1224	+
	1225	+static const char * const uim1_present_groups[] = {
	1226	+ "gpio136",
	1227	+};
	1228	+
	1229	+static const char * const uim1_reset_groups[] = {
	1230	+ "gpio135",
	1231	+};
	1232	+
	1233	+static const char * const usb2phy_ac_groups[] = {
	1234	+ "gpio39", "gpio80",
	1235	+};
	1236	+
	1237	+static const char * const usb_phy_groups[] = {
	1238	+ "gpio81",
	1239	+};
	1240	+
	1241	+static const char * const vfr_0_groups[] = {
	1242	+ "gpio84",
	1243	+};
	1244	+
	1245	+static const char * const vfr_1_groups[] = {
	1246	+ "gpio90",
	1247	+};
	1248	+
	1249	+static const char * const vsense_trigger_groups[] = {
	1250	+ "gpio78",
	1251	+};
	1252	+
	1253	+static const struct msm_function sm8350_functions[] = {
	1254	+ FUNCTION(atest_char),
	1255	+ FUNCTION(atest_usb),
	1256	+ FUNCTION(audio_ref),
	1257	+ FUNCTION(cam_mclk),
	1258	+ FUNCTION(cci_async),
	1259	+ FUNCTION(cci_i2c),
	1260	+ FUNCTION(cci_timer),
	1261	+ FUNCTION(cmu_rng),
	1262	+ FUNCTION(coex_uart1),
	1263	+ FUNCTION(coex_uart2),
	1264	+ FUNCTION(cri_trng),
	1265	+ FUNCTION(cri_trng0),
	1266	+ FUNCTION(cri_trng1),
	1267	+ FUNCTION(dbg_out),
	1268	+ FUNCTION(ddr_bist),
	1269	+ FUNCTION(ddr_pxi0),
	1270	+ FUNCTION(ddr_pxi1),
	1271	+ FUNCTION(ddr_pxi2),
	1272	+ FUNCTION(ddr_pxi3),
	1273	+ FUNCTION(dp_hot),
	1274	+ FUNCTION(dp_lcd),
	1275	+ FUNCTION(gcc_gp1),
	1276	+ FUNCTION(gcc_gp2),
	1277	+ FUNCTION(gcc_gp3),
	1278	+ FUNCTION(gpio),
	1279	+ FUNCTION(ibi_i3c),
	1280	+ FUNCTION(jitter_bist),
	1281	+ FUNCTION(lpass_slimbus),
	1282	+ FUNCTION(mdp_vsync),
	1283	+ FUNCTION(mdp_vsync0),
	1284	+ FUNCTION(mdp_vsync1),
	1285	+ FUNCTION(mdp_vsync2),
	1286	+ FUNCTION(mdp_vsync3),
	1287	+ FUNCTION(mi2s0_data0),
	1288	+ FUNCTION(mi2s0_data1),
	1289	+ FUNCTION(mi2s0_sck),
	1290	+ FUNCTION(mi2s0_ws),
	1291	+ FUNCTION(mi2s1_data0),
	1292	+ FUNCTION(mi2s1_data1),
	1293	+ FUNCTION(mi2s1_sck),
	1294	+ FUNCTION(mi2s1_ws),
	1295	+ FUNCTION(mi2s2_data0),
	1296	+ FUNCTION(mi2s2_data1),
	1297	+ FUNCTION(mi2s2_sck),
	1298	+ FUNCTION(mi2s2_ws),
	1299	+ FUNCTION(mss_grfc0),
	1300	+ FUNCTION(mss_grfc1),
	1301	+ FUNCTION(mss_grfc10),
	1302	+ FUNCTION(mss_grfc11),
	1303	+ FUNCTION(mss_grfc12),
	1304	+ FUNCTION(mss_grfc2),
	1305	+ FUNCTION(mss_grfc3),
	1306	+ FUNCTION(mss_grfc4),
	1307	+ FUNCTION(mss_grfc5),
	1308	+ FUNCTION(mss_grfc6),
	1309	+ FUNCTION(mss_grfc7),
	1310	+ FUNCTION(mss_grfc8),
	1311	+ FUNCTION(mss_grfc9),
	1312	+ FUNCTION(nav_gpio),
	1313	+ FUNCTION(pa_indicator),
	1314	+ FUNCTION(pcie0_clkreqn),
	1315	+ FUNCTION(pcie1_clkreqn),
	1316	+ FUNCTION(phase_flag),
	1317	+ FUNCTION(pll_bist),
	1318	+ FUNCTION(pll_clk),
	1319	+ FUNCTION(pri_mi2s),
	1320	+ FUNCTION(prng_rosc),
	1321	+ FUNCTION(qdss_cti),
	1322	+ FUNCTION(qdss_gpio),
	1323	+ FUNCTION(qlink0_enable),
	1324	+ FUNCTION(qlink0_request),
	1325	+ FUNCTION(qlink0_wmss),
	1326	+ FUNCTION(qlink1_enable),
	1327	+ FUNCTION(qlink1_request),
	1328	+ FUNCTION(qlink1_wmss),
	1329	+ FUNCTION(qlink2_enable),
	1330	+ FUNCTION(qlink2_request),
	1331	+ FUNCTION(qlink2_wmss),
	1332	+ FUNCTION(qspi0),
	1333	+ FUNCTION(qspi1),
	1334	+ FUNCTION(qspi2),
	1335	+ FUNCTION(qspi3),
	1336	+ FUNCTION(qspi_clk),
	1337	+ FUNCTION(qspi_cs),
	1338	+ FUNCTION(qup0),
	1339	+ FUNCTION(qup1),
	1340	+ FUNCTION(qup10),
	1341	+ FUNCTION(qup11),
	1342	+ FUNCTION(qup12),
	1343	+ FUNCTION(qup13),
	1344	+ FUNCTION(qup14),
	1345	+ FUNCTION(qup15),
	1346	+ FUNCTION(qup16),
	1347	+ FUNCTION(qup17),
	1348	+ FUNCTION(qup18),
	1349	+ FUNCTION(qup19),
	1350	+ FUNCTION(qup2),
	1351	+ FUNCTION(qup3),
	1352	+ FUNCTION(qup4),
	1353	+ FUNCTION(qup5),
	1354	+ FUNCTION(qup6),
	1355	+ FUNCTION(qup7),
	1356	+ FUNCTION(qup8),
	1357	+ FUNCTION(qup9),
	1358	+ FUNCTION(qup_l4),
	1359	+ FUNCTION(qup_l5),
	1360	+ FUNCTION(qup_l6),
	1361	+ FUNCTION(sd_write),
	1362	+ FUNCTION(sdc40),
	1363	+ FUNCTION(sdc41),
	1364	+ FUNCTION(sdc42),
	1365	+ FUNCTION(sdc43),
	1366	+ FUNCTION(sdc4_clk),
	1367	+ FUNCTION(sdc4_cmd),
	1368	+ FUNCTION(sec_mi2s),
	1369	+ FUNCTION(tb_trig),
	1370	+ FUNCTION(tgu_ch0),
	1371	+ FUNCTION(tgu_ch1),
	1372	+ FUNCTION(tgu_ch2),
	1373	+ FUNCTION(tgu_ch3),
	1374	+ FUNCTION(tsense_pwm1),
	1375	+ FUNCTION(tsense_pwm2),
	1376	+ FUNCTION(uim0_clk),
	1377	+ FUNCTION(uim0_data),
	1378	+ FUNCTION(uim0_present),
	1379	+ FUNCTION(uim0_reset),
	1380	+ FUNCTION(uim1_clk),
	1381	+ FUNCTION(uim1_data),
	1382	+ FUNCTION(uim1_present),
	1383	+ FUNCTION(uim1_reset),
	1384	+ FUNCTION(usb2phy_ac),
	1385	+ FUNCTION(usb_phy),
	1386	+ FUNCTION(vfr_0),
	1387	+ FUNCTION(vfr_1),
	1388	+ FUNCTION(vsense_trigger),
	1389	+};
	1390	+
	1391	+/* Every pin is maintained as a single group, and missing or non-existing pin
	1392	+ * would be maintained as dummy group to synchronize pin group index with
	1393	+ * pin descriptor registered with pinctrl core.
	1394	+ * Clients would not be able to request these dummy pin groups.
	1395	+ */
	1396	+static const struct msm_pingroup sm8350_groups[] = {
	1397	+ [0] = PINGROUP(0, qup13, _, _, _, _, _, _, _, _),
	1398	+ [1] = PINGROUP(1, qup13, _, _, _, _, _, _, _, _),
	1399	+ [2] = PINGROUP(2, qup13, qup_l4, _, _, _, _, _, _, _),
	1400	+ [3] = PINGROUP(3, qup13, qup_l5, _, _, _, _, _, _, _),
	1401	+ [4] = PINGROUP(4, qup0, _, _, _, _, _, _, _, _),
	1402	+ [5] = PINGROUP(5, qup0, _, _, _, _, _, _, _, _),
	1403	+ [6] = PINGROUP(6, qup0, qup_l4, _, _, _, _, _, _, _),
	1404	+ [7] = PINGROUP(7, qup0, qup_l5, _, _, _, _, _, _, _),
	1405	+ [8] = PINGROUP(8, qup1, _, _, _, _, _, _, _, _),
	1406	+ [9] = PINGROUP(9, qup1, _, _, _, _, _, _, _, _),
	1407	+ [10] = PINGROUP(10, qup1, qup_l6, _, _, _, _, _, _, _),
	1408	+ [11] = PINGROUP(11, qup1, _, _, _, _, _, _, _, _),
	1409	+ [12] = PINGROUP(12, qup2, phase_flag, _, _, _, _, _, _, _),
	1410	+ [13] = PINGROUP(13, qup2, phase_flag, _, _, _, _, _, _, _),
	1411	+ [14] = PINGROUP(14, qup2, qdss_cti, dbg_out, _, _, _, _, _, _),
	1412	+ [15] = PINGROUP(15, qup2, mdp_vsync, _, _, _, _, _, _, _),
	1413	+ [16] = PINGROUP(16, qup3, phase_flag, _, _, _, _, _, _, _),
	1414	+ [17] = PINGROUP(17, qup3, phase_flag, _, _, _, _, _, _, _),
	1415	+ [18] = PINGROUP(18, qup3, _, _, _, _, _, _, _, _),
	1416	+ [19] = PINGROUP(19, qup3, _, _, _, _, _, _, _, _),
	1417	+ [20] = PINGROUP(20, qup4, _, _, _, _, _, _, _, _),
	1418	+ [21] = PINGROUP(21, qup4, _, _, _, _, _, _, _, _),
	1419	+ [22] = PINGROUP(22, qup4, _, _, _, _, _, _, _, _),
	1420	+ [23] = PINGROUP(23, qup4, _, _, _, _, _, _, _, _),
	1421	+ [24] = PINGROUP(24, qup5, _, _, _, _, _, _, _, _),
	1422	+ [25] = PINGROUP(25, qup5, _, _, _, _, _, _, _, _),
	1423	+ [26] = PINGROUP(26, qup5, mdp_vsync, _, _, _, _, _, _, _),
	1424	+ [27] = PINGROUP(27, qup5, qdss_cti, _, _, _, _, _, _, _),
	1425	+ [28] = PINGROUP(28, qup6, phase_flag, _, _, _, _, _, _, _),
	1426	+ [29] = PINGROUP(29, qup6, phase_flag, _, _, _, _, _, _, _),
	1427	+ [30] = PINGROUP(30, qup6, phase_flag, _, _, _, _, _, _, _),
	1428	+ [31] = PINGROUP(31, qup6, phase_flag, _, _, _, _, _, _, _),
	1429	+ [32] = PINGROUP(32, qup7, phase_flag, _, _, _, _, _, _, _),
	1430	+ [33] = PINGROUP(33, qup7, phase_flag, _, _, _, _, _, _, _),
	1431	+ [34] = PINGROUP(34, qup7, phase_flag, _, _, _, _, _, _, _),
	1432	+ [35] = PINGROUP(35, qup7, phase_flag, _, _, _, _, _, _, _),
	1433	+ [36] = PINGROUP(36, qup8, ibi_i3c, ddr_bist, _, _, _, _, _, _),
	1434	+ [37] = PINGROUP(37, qup8, ibi_i3c, ddr_bist, _, _, _, _, _, _),
	1435	+ [38] = PINGROUP(38, qup8, _, _, _, _, _, _, _, _),
	1436	+ [39] = PINGROUP(39, qup8, usb2phy_ac, _, _, _, _, _, _, _),
	1437	+ [40] = PINGROUP(40, qup9, ddr_bist, _, _, _, _, _, _, _),
	1438	+ [41] = PINGROUP(41, qup9, ddr_bist, _, _, _, _, _, _, _),
	1439	+ [42] = PINGROUP(42, qup9, qup_l6, _, _, _, _, _, _, _),
	1440	+ [43] = PINGROUP(43, qup9, ddr_pxi3, _, _, _, _, _, _, _),
	1441	+ [44] = PINGROUP(44, qup10, qspi0, sdc40, ddr_pxi3, _, _, _, _, _),
	1442	+ [45] = PINGROUP(45, qup10, qspi1, sdc41, ddr_pxi2, _, _, _, _, _),
	1443	+ [46] = PINGROUP(46, qup10, _, _, _, _, _, _, _, _),
	1444	+ [47] = PINGROUP(47, qup10, qspi_cs, ddr_pxi2, _, _, _, _, _, _),
	1445	+ [48] = PINGROUP(48, qup11, qspi2, sdc42, ddr_pxi1, _, _, _, _, _),
	1446	+ [49] = PINGROUP(49, qup11, qspi3, sdc43, ddr_pxi1, _, _, _, _, _),
	1447	+ [50] = PINGROUP(50, qup11, qspi_clk, sdc4_clk, _, _, _, _, _, _),
	1448	+ [51] = PINGROUP(51, qup11, qspi_cs, sdc4_cmd, ddr_pxi0, _, _, _, _, _),
	1449	+ [52] = PINGROUP(52, qup12, ddr_pxi0, _, _, _, _, _, _, _),
	1450	+ [53] = PINGROUP(53, qup12, _, _, _, _, _, _, _, _),
	1451	+ [54] = PINGROUP(54, qup12, _, _, _, _, _, _, _, _),
	1452	+ [55] = PINGROUP(55, qup12, atest_usb, _, _, _, _, _, _, _),
	1453	+ [56] = PINGROUP(56, qup14, ibi_i3c, _, _, _, _, _, _, _),
	1454	+ [57] = PINGROUP(57, qup14, ibi_i3c, _, _, _, _, _, _, _),
	1455	+ [58] = PINGROUP(58, qup14, qup_l4, _, _, _, _, _, _, _),
	1456	+ [59] = PINGROUP(59, qup14, qup_l5, _, _, _, _, _, _, _),
	1457	+ [60] = PINGROUP(60, qup15, ibi_i3c, _, _, _, _, _, _, _),
	1458	+ [61] = PINGROUP(61, qup15, ibi_i3c, _, _, _, _, _, _, _),
	1459	+ [62] = PINGROUP(62, qup15, qup_l6, _, _, _, _, _, _, _),
	1460	+ [63] = PINGROUP(63, qup15, qup_l4, _, _, _, _, _, _, _),
	1461	+ [64] = PINGROUP(64, qup16, tb_trig, _, _, _, _, _, _, _),
	1462	+ [65] = PINGROUP(65, qup16, _, _, _, _, _, _, _, _),
	1463	+ [66] = PINGROUP(66, qup16, qup_l5, _, _, _, _, _, _, _),
	1464	+ [67] = PINGROUP(67, qup16, qup_l6, _, _, _, _, _, _, _),
	1465	+ [68] = PINGROUP(68, qup18, _, _, _, _, _, _, _, _),
	1466	+ [69] = PINGROUP(69, qup18, _, _, _, _, _, _, _, _),
	1467	+ [70] = PINGROUP(70, qup18, _, _, _, _, _, _, _, _),
	1468	+ [71] = PINGROUP(71, qup18, _, _, _, _, _, _, _, _),
	1469	+ [72] = PINGROUP(72, qup17, phase_flag, _, _, _, _, _, _, _),
	1470	+ [73] = PINGROUP(73, qup17, phase_flag, _, _, _, _, _, _, _),
	1471	+ [74] = PINGROUP(74, qup17, phase_flag, _, _, _, _, _, _, _),
	1472	+ [75] = PINGROUP(75, qup17, phase_flag, _, _, _, _, _, _, _),
	1473	+ [76] = PINGROUP(76, qup19, phase_flag, _, _, _, _, _, _, _),
	1474	+ [77] = PINGROUP(77, qup19, phase_flag, _, _, _, _, _, _, _),
	1475	+ [78] = PINGROUP(78, qup19, phase_flag, _, vsense_trigger, _, _, _, _, _),
	1476	+ [79] = PINGROUP(79, qup19, phase_flag, _, _, _, _, _, _, _),
	1477	+ [80] = PINGROUP(80, usb2phy_ac, jitter_bist, atest_usb, _, _, _, _, _, _),
	1478	+ [81] = PINGROUP(81, usb_phy, pll_bist, pll_clk, atest_usb, _, _, _, _, _),
	1479	+ [82] = PINGROUP(82, mdp_vsync, _, _, _, _, _, _, _, _),
	1480	+ [83] = PINGROUP(83, mdp_vsync, dp_lcd, _, _, _, _, _, _, _),
	1481	+ [84] = PINGROUP(84, mdp_vsync, vfr_0, _, _, _, _, _, _, _),
	1482	+ [85] = PINGROUP(85, atest_char, _, _, _, _, _, _, _, _),
	1483	+ [86] = PINGROUP(86, mdp_vsync0, mdp_vsync1, atest_char, _, _, _, _, _, _),
	1484	+ [87] = PINGROUP(87, dp_hot, mdp_vsync2, mdp_vsync3, qdss_cti, atest_char, _, _, _, _),
	1485	+ [88] = PINGROUP(88, qdss_cti, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _),
	1486	+ [89] = PINGROUP(89, qdss_cti, _, _, _, _, _, _, _, _),
	1487	+ [90] = PINGROUP(90, vfr_1, qdss_cti, _, _, _, _, _, _, _),
	1488	+ [91] = PINGROUP(91, qdss_cti, _, _, _, _, _, _, _, _),
	1489	+ [92] = PINGROUP(92, qdss_cti, _, _, _, _, _, _, _, _),
	1490	+ [93] = PINGROUP(93, sd_write, _, _, _, _, _, _, _, _),
	1491	+ [94] = PINGROUP(94, _, _, _, _, _, _, _, _, _),
	1492	+ [95] = PINGROUP(95, pcie0_clkreqn, _, _, _, _, _, _, _, _),
	1493	+ [96] = PINGROUP(96, _, _, _, _, _, _, _, _, _),
	1494	+ [97] = PINGROUP(97, _, _, _, _, _, _, _, _, _),
	1495	+ [98] = PINGROUP(98, pcie1_clkreqn, _, _, _, _, _, _, _, _),
	1496	+ [99] = PINGROUP(99, tgu_ch0, _, _, _, _, _, _, _, _),
	1497	+ [100] = PINGROUP(100, cam_mclk, tgu_ch1, qdss_gpio, _, _, _, _, _, _),
	1498	+ [101] = PINGROUP(101, cam_mclk, tgu_ch2, qdss_gpio, _, _, _, _, _, _),
	1499	+ [102] = PINGROUP(102, cam_mclk, tgu_ch3, qdss_gpio, _, _, _, _, _, _),
	1500	+ [103] = PINGROUP(103, cam_mclk, phase_flag, _, qdss_gpio, _, _, _, _, _),
	1501	+ [104] = PINGROUP(104, cam_mclk, phase_flag, _, qdss_gpio, _, _, _, _, _),
	1502	+ [105] = PINGROUP(105, cam_mclk, phase_flag, _, qdss_gpio, _, _, _, _, _),
	1503	+ [106] = PINGROUP(106, cci_async, phase_flag, _, qdss_gpio, _, _, _, _, _),
	1504	+ [107] = PINGROUP(107, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
	1505	+ [108] = PINGROUP(108, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
	1506	+ [109] = PINGROUP(109, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
	1507	+ [110] = PINGROUP(110, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
	1508	+ [111] = PINGROUP(111, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
	1509	+ [112] = PINGROUP(112, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
	1510	+ [113] = PINGROUP(113, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
	1511	+ [114] = PINGROUP(114, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
	1512	+ [115] = PINGROUP(115, cci_timer, gcc_gp1, qdss_gpio, atest_char, _, _, _, _, _),
	1513	+ [116] = PINGROUP(116, cci_timer, gcc_gp2, qdss_gpio, _, _, _, _, _, _),
	1514	+ [117] = PINGROUP(117, cci_timer, gcc_gp3, qdss_gpio, atest_char, _, _, _, _, _),
	1515	+ [118] = PINGROUP(118, cci_timer, cci_async, _, _, _, _, _, _, _),
	1516	+ [119] = PINGROUP(119, cci_timer, cci_async, _, _, _, _, _, _, _),
	1517	+ [120] = PINGROUP(120, mi2s2_sck, _, _, _, _, _, _, _, _),
	1518	+ [121] = PINGROUP(121, mi2s2_data0, _, _, _, _, _, _, _, _),
	1519	+ [122] = PINGROUP(122, mi2s2_ws, _, _, _, _, _, _, _, _),
	1520	+ [123] = PINGROUP(123, pri_mi2s, _, _, _, _, _, _, _, _),
	1521	+ [124] = PINGROUP(124, sec_mi2s, audio_ref, mi2s2_data1, _, _, _, _, _, _),
	1522	+ [125] = PINGROUP(125, mi2s0_sck, _, _, _, _, _, _, _, _),
	1523	+ [126] = PINGROUP(126, mi2s0_data0, _, _, _, _, _, _, _, _),
	1524	+ [127] = PINGROUP(127, mi2s0_data1, _, _, _, _, _, _, _, _),
	1525	+ [128] = PINGROUP(128, mi2s0_ws, _, _, _, _, _, _, _, _),
	1526	+ [129] = PINGROUP(129, lpass_slimbus, mi2s1_sck, gcc_gp1, _, _, _, _, _, _),
	1527	+ [130] = PINGROUP(130, lpass_slimbus, mi2s1_data0, gcc_gp2, _, _, _, _, _, _),
	1528	+ [131] = PINGROUP(131, mi2s1_data1, gcc_gp3, _, _, _, _, _, _, _),
	1529	+ [132] = PINGROUP(132, mi2s1_ws, _, _, _, _, _, _, _, _),
	1530	+ [133] = PINGROUP(133, uim1_data, _, _, _, _, _, _, _, _),
	1531	+ [134] = PINGROUP(134, uim1_clk, _, _, _, _, _, _, _, _),
	1532	+ [135] = PINGROUP(135, uim1_reset, _, _, _, _, _, _, _, _),
	1533	+ [136] = PINGROUP(136, uim1_present, tb_trig, _, _, _, _, _, _, _),
	1534	+ [137] = PINGROUP(137, uim0_data, _, _, _, _, _, _, _, _),
	1535	+ [138] = PINGROUP(138, uim0_clk, _, _, _, _, _, _, _, _),
	1536	+ [139] = PINGROUP(139, uim0_reset, _, _, _, _, _, _, _, _),
	1537	+ [140] = PINGROUP(140, uim0_present, _, _, _, _, _, _, _, _),
	1538	+ [141] = PINGROUP(141, _, mss_grfc0, _, _, _, _, _, _, _),
	1539	+ [142] = PINGROUP(142, _, mss_grfc1, _, _, _, _, _, _, _),
	1540	+ [143] = PINGROUP(143, _, mss_grfc2, _, _, _, _, _, _, _),
	1541	+ [144] = PINGROUP(144, _, mss_grfc3, _, _, _, _, _, _, _),
	1542	+ [145] = PINGROUP(145, _, mss_grfc4, _, _, _, _, _, _, _),
	1543	+ [146] = PINGROUP(146, _, mss_grfc5, _, _, _, _, _, _, _),
	1544	+ [147] = PINGROUP(147, _, mss_grfc6, _, _, _, _, _, _, _),
	1545	+ [148] = PINGROUP(148, _, mss_grfc7, _, _, _, _, _, _, _),
	1546	+ [149] = PINGROUP(149, _, mss_grfc8, _, _, _, _, _, _, _),
	1547	+ [150] = PINGROUP(150, _, mss_grfc9, _, _, _, _, _, _, _),
	1548	+ [151] = PINGROUP(151, coex_uart1, atest_usb, _, _, _, _, _, _, _),
	1549	+ [152] = PINGROUP(152, coex_uart1, atest_usb, _, _, _, _, _, _, _),
	1550	+ [153] = PINGROUP(153, coex_uart2, mss_grfc10, atest_usb, _, _, _, _, _, _),
	1551	+ [154] = PINGROUP(154, coex_uart2, mss_grfc11, atest_usb, _, _, _, _, _, _),
	1552	+ [155] = PINGROUP(155, nav_gpio, _, _, _, _, _, _, _, _),
	1553	+ [156] = PINGROUP(156, nav_gpio, _, _, _, _, _, _, _, _),
	1554	+ [157] = PINGROUP(157, mss_grfc12, pa_indicator, nav_gpio, _, _, _, _, _, _),
	1555	+ [158] = PINGROUP(158, mss_grfc0, atest_usb, _, _, _, _, _, _, _),
	1556	+ [159] = PINGROUP(159, qlink0_request, atest_usb, _, _, _, _, _, _, _),
	1557	+ [160] = PINGROUP(160, qlink0_enable, _, _, _, _, _, _, _, _),
	1558	+ [161] = PINGROUP(161, qlink0_wmss, atest_usb, _, _, _, _, _, _, _),
	1559	+ [162] = PINGROUP(162, qlink1_request, _, _, _, _, _, _, _, _),
	1560	+ [163] = PINGROUP(163, qlink1_enable, _, _, _, _, _, _, _, _),
	1561	+ [164] = PINGROUP(164, qlink1_wmss, _, _, _, _, _, _, _, _),
	1562	+ [165] = PINGROUP(165, qlink2_request, _, _, _, _, _, _, _, _),
	1563	+ [166] = PINGROUP(166, qlink2_enable, _, _, _, _, _, _, _, _),
	1564	+ [167] = PINGROUP(167, qlink2_wmss, _, _, _, _, _, _, _, _),
	1565	+ [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _),
	1566	+ [169] = PINGROUP(169, _, _, _, _, _, _, _, _, _),
	1567	+ [170] = PINGROUP(170, _, _, _, _, _, _, _, _, _),
	1568	+ [171] = PINGROUP(171, _, _, _, _, _, _, _, _, _),
	1569	+ [172] = PINGROUP(172, _, _, _, _, _, _, _, _, _),
	1570	+ [173] = PINGROUP(173, _, _, _, _, _, _, _, _, _),
	1571	+ [174] = PINGROUP(174, cmu_rng, _, _, _, _, _, _, _, _),
	1572	+ [175] = PINGROUP(175, cmu_rng, _, _, _, _, _, _, _, _),
	1573	+ [176] = PINGROUP(176, cmu_rng, _, _, _, _, _, _, _, _),
	1574	+ [177] = PINGROUP(177, cmu_rng, _, _, _, _, _, _, _, _),
	1575	+ [178] = PINGROUP(178, _, _, _, _, _, _, _, _, _),
	1576	+ [179] = PINGROUP(179, _, _, _, _, _, _, _, _, _),
	1577	+ [180] = PINGROUP(180, _, _, _, _, _, _, _, _, _),
	1578	+ [181] = PINGROUP(181, _, _, _, _, _, _, _, _, _),
	1579	+ [182] = PINGROUP(182, _, _, _, _, _, _, _, _, _),
	1580	+ [183] = PINGROUP(183, cri_trng0, qdss_gpio, _, _, _, _, _, _, _),
	1581	+ [184] = PINGROUP(184, cri_trng1, qdss_gpio, _, _, _, _, _, _, _),
	1582	+ [185] = PINGROUP(185, prng_rosc, qdss_gpio, _, _, _, _, _, _, _),
	1583	+ [186] = PINGROUP(186, cri_trng, qdss_gpio, _, _, _, _, _, _, _),
	1584	+ [187] = PINGROUP(187, qdss_gpio, _, _, _, _, _, _, _, _),
	1585	+ [188] = PINGROUP(188, qdss_gpio, _, _, _, _, _, _, _, _),
	1586	+ [189] = PINGROUP(189, qdss_gpio, _, _, _, _, _, _, _, _),
	1587	+ [190] = PINGROUP(190, qdss_gpio, _, _, _, _, _, _, _, _),
	1588	+ [191] = PINGROUP(191, qdss_gpio, _, _, _, _, _, _, _, _),
	1589	+ [192] = PINGROUP(192, qdss_gpio, _, _, _, _, _, _, _, _),
	1590	+ [193] = PINGROUP(193, qdss_gpio, _, _, _, _, _, _, _, _),
	1591	+ [194] = PINGROUP(194, qdss_gpio, _, _, _, _, _, _, _, _),
	1592	+ [195] = PINGROUP(195, qdss_gpio, _, _, _, _, _, _, _, _),
	1593	+ [196] = PINGROUP(196, qdss_gpio, _, _, _, _, _, _, _, _),
	1594	+ [197] = PINGROUP(197, qdss_gpio, _, _, _, _, _, _, _, _),
	1595	+ [198] = PINGROUP(198, qdss_gpio, _, _, _, _, _, _, _, _),
	1596	+ [199] = PINGROUP(199, qdss_gpio, _, _, _, _, _, _, _, _),
	1597	+ [200] = PINGROUP(200, qdss_gpio, _, _, _, _, _, _, _, _),
	1598	+ [201] = PINGROUP(201, _, _, _, _, _, _, _, _, _),
	1599	+ [202] = PINGROUP(202, _, _, _, _, _, _, _, _, _),
	1600	+ [203] = UFS_RESET(ufs_reset, 0x1d8000),
	1601	+ [204] = SDC_PINGROUP(sdc2_clk, 0x1cf000, 14, 6),
	1602	+ [205] = SDC_PINGROUP(sdc2_cmd, 0x1cf000, 11, 3),
	1603	+ [206] = SDC_PINGROUP(sdc2_data, 0x1cf000, 9, 0),
	1604	+};
	1605	+
	1606	+static const struct msm_pinctrl_soc_data sm8350_tlmm = {
	1607	+ .pins = sm8350_pins,
	1608	+ .npins = ARRAY_SIZE(sm8350_pins),
	1609	+ .functions = sm8350_functions,
	1610	+ .nfunctions = ARRAY_SIZE(sm8350_functions),
	1611	+ .groups = sm8350_groups,
	1612	+ .ngroups = ARRAY_SIZE(sm8350_groups),
	1613	+ .ngpios = 204,
	1614	+};
	1615	+
	1616	+static int sm8350_tlmm_probe(struct platform_device *pdev)
	1617	+{
	1618	+ return msm_pinctrl_probe(pdev, &sm8350_tlmm);
	1619	+}
	1620	+
	1621	+static const struct of_device_id sm8350_tlmm_of_match[] = {
	1622	+ { .compatible = "qcom,sm8350-tlmm", },
	1623	+ { },
	1624	+};
	1625	+
	1626	+static struct platform_driver sm8350_tlmm_driver = {
	1627	+ .driver = {
	1628	+ .name = "sm8350-tlmm",
	1629	+ .of_match_table = sm8350_tlmm_of_match,
	1630	+ },
	1631	+ .probe = sm8350_tlmm_probe,
	1632	+ .remove = msm_pinctrl_remove,
	1633	+};
	1634	+
	1635	+static int __init sm8350_tlmm_init(void)
	1636	+{
	1637	+ return platform_driver_register(&sm8350_tlmm_driver);
	1638	+}
	1639	+arch_initcall(sm8350_tlmm_init);
	1640	+
	1641	+static void __exit sm8350_tlmm_exit(void)
	1642	+{
	1643	+ platform_driver_unregister(&sm8350_tlmm_driver);
	1644	+}
	1645	+module_exit(sm8350_tlmm_exit);
	1646	+
	1647	+MODULE_DESCRIPTION("QTI SM8350 TLMM driver");
	1648	+MODULE_LICENSE("GPL v2");
	1649	+MODULE_DEVICE_TABLE(of, sm8350_tlmm_of_match);

drivers/pinctrl/qcom/pinctrl-spmi-mpp.c+1−0

@@ -912,6 +912,7 @@ static int pmic_mpp_remove(struct platform_device *pdev) · 911 unmodified lines
912	912	}
913	913
914	914	static const struct of_device_id pmic_mpp_of_match[] = {
	915	+ { .compatible = "qcom,pm8019-mpp" }, /* 6 MPP's */
915	916	{ .compatible = "qcom,pm8841-mpp" }, /* 4 MPP's */
916	917	{ .compatible = "qcom,pm8916-mpp" }, /* 4 MPP's */
917	918	{ .compatible = "qcom,pm8941-mpp" }, /* 8 MPP's */

drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c+0−1

@@ -617,7 +617,6 @@ static void pm8xxx_mpp_dbg_show_one(struct seq_file *s, · 616 unmodified lines
617	617	}
618	618	break;
619	619	}
620		−
621	620	}
622	621
623	622	static void pm8xxx_mpp_dbg_show(struct seq_file s, struct gpio_chip chip)

drivers/pinctrl/ralink/pinctrl-rt2880.c+23−24

@@ -193,7 +193,6 @@ static struct rt2880_pmx_func gpio_func = { · 192 unmodified lines
193	193
194	194	static int rt2880_pinmux_index(struct rt2880_priv *p)
195	195	{
196		− struct rt2880_pmx_func **f;
197	196	struct rt2880_pmx_group *mux = p->groups;
198	197	int i, j, c = 0;
199	198
@@ -207,7 +206,7 @@ static int rt2880_pinmux_index(struct rt2880_priv *p) · 7 unmodified lines
207	206	p->group_names = devm_kcalloc(p->dev, p->group_count,
208	207	sizeof(char *), GFP_KERNEL);
209	208	if (!p->group_names)
210		− return -1;
	209	+ return -ENOMEM;
211	210
212	211	for (i = 0; i < p->group_count; i++) {
213	212	p->group_names[i] = p->groups[i].name;
@@ -218,31 +217,31 @@ static int rt2880_pinmux_index(struct rt2880_priv *p) · 4 unmodified lines
218	217	p->func_count++;
219	218
220	219	/* allocate our function and group mapping index buffers */
221		− f = p->func = devm_kcalloc(p->dev,
222		− p->func_count,
223		− sizeof(*p->func),
224		− GFP_KERNEL);
	220	+ p->func = devm_kcalloc(p->dev, p->func_count,
	221	+ sizeof(*p->func), GFP_KERNEL);
225	222	gpio_func.groups = devm_kcalloc(p->dev, p->group_count, sizeof(int),
226	223	GFP_KERNEL);
227		− if (!f \|\| !gpio_func.groups)
228		− return -1;
	224	+ if (!p->func \|\| !gpio_func.groups)
	225	+ return -ENOMEM;
229	226
230	227	/* add a backpointer to the function so it knows its group */
231	228	gpio_func.group_count = p->group_count;
232	229	for (i = 0; i < gpio_func.group_count; i++)
233	230	gpio_func.groups[i] = i;
234	231
235		− f[c] = &gpio_func;
	232	+ p->func[c] = &gpio_func;
236	233	c++;
237	234
238	235	/* add remaining functions */
239	236	for (i = 0; i < p->group_count; i++) {
240	237	for (j = 0; j < p->groups[i].func_count; j++) {
241		− f[c] = &p->groups[i].func[j];
242		− f[c]->groups = devm_kzalloc(p->dev, sizeof(int),
	238	+ p->func[c] = &p->groups[i].func[j];
	239	+ p->func[c]->groups = devm_kzalloc(p->dev, sizeof(int),
243	240	GFP_KERNEL);
244		− f[c]->groups[0] = i;
245		− f[c]->group_count = 1;
	241	+ if (!p->func[c]->groups)
	242	+ return -ENOMEM;
	243	+ p->func[c]->groups[0] = i;
	244	+ p->func[c]->group_count = 1;
246	245	c++;
247	246	}
248	247	}
@@ -280,10 +279,8 @@ static int rt2880_pinmux_pins(struct rt2880_priv *p) · 31 unmodified lines
280	279	/* the pads needed to tell pinctrl about our pins */
281	280	p->pads = devm_kcalloc(p->dev, p->max_pins,
282	281	sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
283		− if (!p->pads \|\| !p->gpio) {
284		− dev_err(p->dev, "Failed to allocate gpio data\n");
	282	+ if (!p->pads \|\| !p->gpio)
285	283	return -ENOMEM;
286		− }
287	284
288	285	memset(p->gpio, 1, sizeof(u8) * p->max_pins);
289	286	for (i = 0; i < p->func_count; i++) {
@@ -318,6 +315,7 @@ static int rt2880_pinmux_probe(struct platform_device *pdev) · 28 unmodified lines
318	315	{
319	316	struct rt2880_priv *p;
320	317	struct pinctrl_dev *dev;
	318	+ int err;
321	319
322	320	if (!rt2880_pinmux_data)
323	321	return -ENOTSUPP;
@@ -333,19 +331,20 @@ static int rt2880_pinmux_probe(struct platform_device *pdev) · 9 unmodified lines
333	331	platform_set_drvdata(pdev, p);
334	332
335	333	/* init the device */
336		− if (rt2880_pinmux_index(p)) {
	334	+ err = rt2880_pinmux_index(p);
	335	+ if (err) {
337	336	dev_err(&pdev->dev, "failed to load index\n");
338		− return -EINVAL;
	337	+ return err;
339	338	}
340		− if (rt2880_pinmux_pins(p)) {
	339	+
	340	+ err = rt2880_pinmux_pins(p);
	341	+ if (err) {
341	342	dev_err(&pdev->dev, "failed to load pins\n");
342		− return -EINVAL;
	343	+ return err;
343	344	}
344	345	dev = pinctrl_register(p->desc, &pdev->dev, p);
345		− if (IS_ERR(dev))
346		− return PTR_ERR(dev);
347	346
348		− return 0;
	347	+ return PTR_ERR_OR_ZERO(dev);
349	348	}
350	349
351	350	static const struct of_device_id rt2880_pinmux_match[] = {
@@ -362,7 +361,7 @@ static struct platform_driver rt2880_pinmux_driver = { · 10 unmodified lines
362	361	},
363	362	};
364	363
365		−int __init rt2880_pinmux_init(void)
	364	+static int __init rt2880_pinmux_init(void)
366	365	{
367	366	return platform_driver_register(&rt2880_pinmux_driver);
368	367	}

drivers/pinctrl/renesas/Kconfig+5−0

@@ -36,6 +36,7 @@ config PINCTRL_RENESAS · 35 unmodified lines
36	36	select PINCTRL_PFC_R8A77980 if ARCH_R8A77980
37	37	select PINCTRL_PFC_R8A77990 if ARCH_R8A77990
38	38	select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
	39	+ select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0
39	40	select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
40	41	select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
41	42	select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
@@ -142,6 +143,10 @@ config PINCTRL_PFC_R8A77970 · 100 unmodified lines
142	143	bool "pin control support for R-Car V3M" if COMPILE_TEST
143	144	select PINCTRL_SH_PFC
144	145
	146	+config PINCTRL_PFC_R8A779A0
	147	+ bool "pin control support for R-Car V3U" if COMPILE_TEST
	148	+ select PINCTRL_SH_PFC
	149	+
145	150	config PINCTRL_PFC_R8A7740
146	151	bool "pin control support for R-Mobile A1" if COMPILE_TEST
147	152	select PINCTRL_SH_PFC_GPIO

drivers/pinctrl/renesas/Makefile+1−0

@@ -29,6 +29,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o · 28 unmodified lines
29	29	obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
30	30	obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
31	31	obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
	32	+obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
32	33	obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
33	34	obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
34	35	obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o

drivers/pinctrl/renesas/core.c+28−10

@@ -175,13 +175,25 @@ u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg) · 174 unmodified lines
175	175	return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
176	176	}
177	177
178		−void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
	178	+static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data)
179	179	{
180		− if (pfc->info->unlock_reg)
181		− sh_pfc_write_raw_reg(
182		− sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
183		− ~data);
	180	+ u32 unlock;
	181	+
	182	+ if (!pfc->info->unlock_reg)
	183	+ return;
	184	+
	185	+ if (pfc->info->unlock_reg >= 0x80000000UL)
	186	+ unlock = pfc->info->unlock_reg;
	187	+ else
	188	+ /* unlock_reg is a mask */
	189	+ unlock = reg & ~pfc->info->unlock_reg;
184	190
	191	+ sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, unlock), 32, ~data);
	192	+}
	193	+
	194	+void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
	195	+{
	196	+ sh_pfc_unlock_reg(pfc, reg, data);
185	197	sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
186	198	}
187	199
@@ -227,11 +239,7 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc, · 39 unmodified lines
227	239	data &= mask;
228	240	data \|= value;
229	241
230		− if (pfc->info->unlock_reg)
231		− sh_pfc_write_raw_reg(
232		− sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
233		− ~data);
234		−
	242	+ sh_pfc_unlock_reg(pfc, crp->reg, data);
235	243	sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
236	244	}
237	245
@@ -638,6 +646,12 @@ static const struct of_device_id sh_pfc_of_table[] = { · 400 unmodified lines
638	646	.data = &r8a77995_pinmux_info,
639	647	},
640	648	#endif
	649	+#ifdef CONFIG_PINCTRL_PFC_R8A779A0
	650	+ {
	651	+ .compatible = "renesas,pfc-r8a779a0",
	652	+ .data = &r8a779a0_pinmux_info,
	653	+ },
	654	+#endif
641	655	#ifdef CONFIG_PINCTRL_PFC_SH73A0
642	656	{
643	657	.compatible = "renesas,pfc-sh73a0",
@@ -1052,6 +1066,10 @@ static void __init sh_pfc_check_driver(const struct platform_driver *pdrv) · 408 unmodified lines
1052	1066	{
1053	1067	unsigned int i;
1054	1068
	1069	+ if (!IS_ENABLED(CONFIG_SUPERH) &&
	1070	+ !of_find_matching_node(NULL, pdrv->driver.of_match_table))
	1071	+ return;
	1072	+
1055	1073	sh_pfc_regs = kcalloc(SH_PFC_MAX_REGS, sizeof(*sh_pfc_regs),
1056	1074	GFP_KERNEL);
1057	1075	if (!sh_pfc_regs)

drivers/pinctrl/renesas/pfc-r8a77950.c+0−1

@@ -1668,7 +1668,6 @@ static const unsigned int avb_mii_pins[] = { · 1667 unmodified lines
1668	1668	PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1669	1669	PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1670	1670	PIN_AVB_TXCREFCLK,
1671		−
1672	1671	};
1673	1672	static const unsigned int avb_mii_mux[] = {
1674	1673	AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,

drivers/pinctrl/renesas/pfc-r8a77951.c+0−1

@@ -1727,7 +1727,6 @@ static const unsigned int avb_mii_pins[] = { · 1726 unmodified lines
1727	1727	PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1728	1728	PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1729	1729	PIN_AVB_TXCREFCLK,
1730		−
1731	1730	};
1732	1731	static const unsigned int avb_mii_mux[] = {
1733	1732	AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,

drivers/pinctrl/renesas/pfc-r8a7796.c+0−1

@@ -1731,7 +1731,6 @@ static const unsigned int avb_mii_pins[] = { · 1730 unmodified lines
1731	1731	PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1732	1732	PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1733	1733	PIN_AVB_TXCREFCLK,
1734		−
1735	1734	};
1736	1735	static const unsigned int avb_mii_mux[] = {
1737	1736	AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,

drivers/pinctrl/renesas/pfc-r8a77965.c+0−1

@@ -1736,7 +1736,6 @@ static const unsigned int avb_mii_pins[] = { · 1735 unmodified lines
1736	1736	PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1737	1737	PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1738	1738	PIN_AVB_TXCREFCLK,
1739		−
1740	1739	};
1741	1740	static const unsigned int avb_mii_mux[] = {
1742	1741	AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,

drivers/pinctrl/renesas/pfc-r8a779a0.c+4460−0

@@ -0,0 +1,4460 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+/*
	3	+ * R8A779A0 processor support - PFC hardware block.
	4	+ *
	5	+ * Copyright (C) 2020 Renesas Electronics Corp.
	6	+ *
	7	+ * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
	8	+ */
	9	+
	10	+#include <linux/errno.h>
	11	+#include <linux/io.h>
	12	+#include <linux/kernel.h>
	13	+
	14	+#include "core.h"
	15	+#include "sh_pfc.h"
	16	+
	17	+#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH \| SH_PFC_PIN_CFG_PULL_UP_DOWN)
	18	+
	19	+#define CPU_ALL_GP(fn, sfx) \
	20	+ PORT_GP_CFG_15(0, fn, sfx, CFG_FLAGS), \
	21	+ PORT_GP_CFG_1(0, 15, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	22	+ PORT_GP_CFG_1(0, 16, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	23	+ PORT_GP_CFG_1(0, 17, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	24	+ PORT_GP_CFG_1(0, 18, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	25	+ PORT_GP_CFG_1(0, 19, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	26	+ PORT_GP_CFG_1(0, 20, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	27	+ PORT_GP_CFG_1(0, 21, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	28	+ PORT_GP_CFG_1(0, 22, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	29	+ PORT_GP_CFG_1(0, 23, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	30	+ PORT_GP_CFG_1(0, 24, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	31	+ PORT_GP_CFG_1(0, 25, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	32	+ PORT_GP_CFG_1(0, 26, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	33	+ PORT_GP_CFG_1(0, 27, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	34	+ PORT_GP_CFG_31(1, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	35	+ PORT_GP_CFG_2(2, fn, sfx, CFG_FLAGS), \
	36	+ PORT_GP_CFG_1(2, 2, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	37	+ PORT_GP_CFG_1(2, 3, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	38	+ PORT_GP_CFG_1(2, 4, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	39	+ PORT_GP_CFG_1(2, 5, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	40	+ PORT_GP_CFG_1(2, 6, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	41	+ PORT_GP_CFG_1(2, 7, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	42	+ PORT_GP_CFG_1(2, 8, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	43	+ PORT_GP_CFG_1(2, 9, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	44	+ PORT_GP_CFG_1(2, 10, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	45	+ PORT_GP_CFG_1(2, 11, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	46	+ PORT_GP_CFG_1(2, 12, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	47	+ PORT_GP_CFG_1(2, 13, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	48	+ PORT_GP_CFG_1(2, 14, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	49	+ PORT_GP_CFG_1(2, 15, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
	50	+ PORT_GP_CFG_1(2, 16, fn, sfx, CFG_FLAGS), \
	51	+ PORT_GP_CFG_1(2, 17, fn, sfx, CFG_FLAGS), \
	52	+ PORT_GP_CFG_1(2, 18, fn, sfx, CFG_FLAGS), \
	53	+ PORT_GP_CFG_1(2, 19, fn, sfx, CFG_FLAGS), \
	54	+ PORT_GP_CFG_1(2, 20, fn, sfx, CFG_FLAGS), \
	55	+ PORT_GP_CFG_1(2, 21, fn, sfx, CFG_FLAGS), \
	56	+ PORT_GP_CFG_1(2, 22, fn, sfx, CFG_FLAGS), \
	57	+ PORT_GP_CFG_1(2, 23, fn, sfx, CFG_FLAGS), \
	58	+ PORT_GP_CFG_1(2, 24, fn, sfx, CFG_FLAGS), \
	59	+ PORT_GP_CFG_17(3, fn, sfx, CFG_FLAGS), \
	60	+ PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
	61	+ PORT_GP_CFG_1(4, 18, fn, sfx, CFG_FLAGS), \
	62	+ PORT_GP_CFG_1(4, 19, fn, sfx, CFG_FLAGS), \
	63	+ PORT_GP_CFG_1(4, 20, fn, sfx, CFG_FLAGS), \
	64	+ PORT_GP_CFG_1(4, 21, fn, sfx, CFG_FLAGS), \
	65	+ PORT_GP_CFG_1(4, 22, fn, sfx, CFG_FLAGS), \
	66	+ PORT_GP_CFG_1(4, 23, fn, sfx, CFG_FLAGS), \
	67	+ PORT_GP_CFG_1(4, 24, fn, sfx, CFG_FLAGS), \
	68	+ PORT_GP_CFG_1(4, 25, fn, sfx, CFG_FLAGS), \
	69	+ PORT_GP_CFG_1(4, 26, fn, sfx, CFG_FLAGS), \
	70	+ PORT_GP_CFG_18(5, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
	71	+ PORT_GP_CFG_1(5, 18, fn, sfx, CFG_FLAGS), \
	72	+ PORT_GP_CFG_1(5, 19, fn, sfx, CFG_FLAGS), \
	73	+ PORT_GP_CFG_1(5, 20, fn, sfx, CFG_FLAGS), \
	74	+ PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
	75	+ PORT_GP_CFG_1(6, 18, fn, sfx, CFG_FLAGS), \
	76	+ PORT_GP_CFG_1(6, 19, fn, sfx, CFG_FLAGS), \
	77	+ PORT_GP_CFG_1(6, 20, fn, sfx, CFG_FLAGS), \
	78	+ PORT_GP_CFG_18(7, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
	79	+ PORT_GP_CFG_1(7, 18, fn, sfx, CFG_FLAGS), \
	80	+ PORT_GP_CFG_1(7, 19, fn, sfx, CFG_FLAGS), \
	81	+ PORT_GP_CFG_1(7, 20, fn, sfx, CFG_FLAGS), \
	82	+ PORT_GP_CFG_18(8, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
	83	+ PORT_GP_CFG_1(8, 18, fn, sfx, CFG_FLAGS), \
	84	+ PORT_GP_CFG_1(8, 19, fn, sfx, CFG_FLAGS), \
	85	+ PORT_GP_CFG_1(8, 20, fn, sfx, CFG_FLAGS), \
	86	+ PORT_GP_CFG_18(9, fn, sfx, CFG_FLAGS \| SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
	87	+ PORT_GP_CFG_1(9, 18, fn, sfx, CFG_FLAGS), \
	88	+ PORT_GP_CFG_1(9, 19, fn, sfx, CFG_FLAGS), \
	89	+ PORT_GP_CFG_1(9, 20, fn, sfx, CFG_FLAGS)
	90	+
	91	+#define CPU_ALL_NOGP(fn) \
	92	+ PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
	93	+ PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
	94	+ PIN_NOGP_CFG(DCUTRST_N_LPDRST_N, "DCUTRST#_LPDRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
	95	+ PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
	96	+ PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
	97	+ PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
	98	+
	99	+/*
	100	+ * F_() : just information
	101	+ * FM() : macro for FN_xxx / xxx_MARK
	102	+ */
	103	+
	104	+/* GPSR0 */
	105	+#define GPSR0_27 FM(MMC_D7)
	106	+#define GPSR0_26 FM(MMC_D6)
	107	+#define GPSR0_25 FM(MMC_D5)
	108	+#define GPSR0_24 FM(MMC_D4)
	109	+#define GPSR0_23 FM(MMC_SD_CLK)
	110	+#define GPSR0_22 FM(MMC_SD_D3)
	111	+#define GPSR0_21 FM(MMC_SD_D2)
	112	+#define GPSR0_20 FM(MMC_SD_D1)
	113	+#define GPSR0_19 FM(MMC_SD_D0)
	114	+#define GPSR0_18 FM(MMC_SD_CMD)
	115	+#define GPSR0_17 FM(MMC_DS)
	116	+#define GPSR0_16 FM(SD_CD)
	117	+#define GPSR0_15 FM(SD_WP)
	118	+#define GPSR0_14 FM(RPC_INT_N)
	119	+#define GPSR0_13 FM(RPC_WP_N)
	120	+#define GPSR0_12 FM(RPC_RESET_N)
	121	+#define GPSR0_11 FM(QSPI1_SSL)
	122	+#define GPSR0_10 FM(QSPI1_IO3)
	123	+#define GPSR0_9 FM(QSPI1_IO2)
	124	+#define GPSR0_8 FM(QSPI1_MISO_IO1)
	125	+#define GPSR0_7 FM(QSPI1_MOSI_IO0)
	126	+#define GPSR0_6 FM(QSPI1_SPCLK)
	127	+#define GPSR0_5 FM(QSPI0_SSL)
	128	+#define GPSR0_4 FM(QSPI0_IO3)
	129	+#define GPSR0_3 FM(QSPI0_IO2)
	130	+#define GPSR0_2 FM(QSPI0_MISO_IO1)
	131	+#define GPSR0_1 FM(QSPI0_MOSI_IO0)
	132	+#define GPSR0_0 FM(QSPI0_SPCLK)
	133	+
	134	+/* GPSR1 */
	135	+#define GPSR1_30 F_(GP1_30, IP3SR1_27_24)
	136	+#define GPSR1_29 F_(GP1_29, IP3SR1_23_20)
	137	+#define GPSR1_28 F_(GP1_28, IP3SR1_19_16)
	138	+#define GPSR1_27 F_(IRQ3, IP3SR1_15_12)
	139	+#define GPSR1_26 F_(IRQ2, IP3SR1_11_8)
	140	+#define GPSR1_25 F_(IRQ1, IP3SR1_7_4)
	141	+#define GPSR1_24 F_(IRQ0, IP3SR1_3_0)
	142	+#define GPSR1_23 F_(MSIOF2_SS2, IP2SR1_31_28)
	143	+#define GPSR1_22 F_(MSIOF2_SS1, IP2SR1_27_24)
	144	+#define GPSR1_21 F_(MSIOF2_SYNC, IP2SR1_23_20)
	145	+#define GPSR1_20 F_(MSIOF2_SCK, IP2SR1_19_16)
	146	+#define GPSR1_19 F_(MSIOF2_TXD, IP2SR1_15_12)
	147	+#define GPSR1_18 F_(MSIOF2_RXD, IP2SR1_11_8)
	148	+#define GPSR1_17 F_(MSIOF1_SS2, IP2SR1_7_4)
	149	+#define GPSR1_16 F_(MSIOF1_SS1, IP2SR1_3_0)
	150	+#define GPSR1_15 F_(MSIOF1_SYNC, IP1SR1_31_28)
	151	+#define GPSR1_14 F_(MSIOF1_SCK, IP1SR1_27_24)
	152	+#define GPSR1_13 F_(MSIOF1_TXD, IP1SR1_23_20)
	153	+#define GPSR1_12 F_(MSIOF1_RXD, IP1SR1_19_16)
	154	+#define GPSR1_11 F_(MSIOF0_SS2, IP1SR1_15_12)
	155	+#define GPSR1_10 F_(MSIOF0_SS1, IP1SR1_11_8)
	156	+#define GPSR1_9 F_(MSIOF0_SYNC, IP1SR1_7_4)
	157	+#define GPSR1_8 F_(MSIOF0_SCK, IP1SR1_3_0)
	158	+#define GPSR1_7 F_(MSIOF0_TXD, IP0SR1_31_28)
	159	+#define GPSR1_6 F_(MSIOF0_RXD, IP0SR1_27_24)
	160	+#define GPSR1_5 F_(HTX0, IP0SR1_23_20)
	161	+#define GPSR1_4 F_(HCTS0_N, IP0SR1_19_16)
	162	+#define GPSR1_3 F_(HRTS0_N, IP0SR1_15_12)
	163	+#define GPSR1_2 F_(HSCK0, IP0SR1_11_8)
	164	+#define GPSR1_1 F_(HRX0, IP0SR1_7_4)
	165	+#define GPSR1_0 F_(SCIF_CLK, IP0SR1_3_0)
	166	+
	167	+/* GPSR2 */
	168	+#define GPSR2_24 FM(TCLK2_A)
	169	+#define GPSR2_23 F_(TCLK1_A, IP2SR2_31_28)
	170	+#define GPSR2_22 F_(TPU0TO1, IP2SR2_27_24)
	171	+#define GPSR2_21 F_(TPU0TO0, IP2SR2_23_20)
	172	+#define GPSR2_20 F_(CLK_EXTFXR, IP2SR2_19_16)
	173	+#define GPSR2_19 F_(RXDB_EXTFXR, IP2SR2_15_12)
	174	+#define GPSR2_18 F_(FXR_TXDB, IP2SR2_11_8)
	175	+#define GPSR2_17 F_(RXDA_EXTFXR_A, IP2SR2_7_4)
	176	+#define GPSR2_16 F_(FXR_TXDA_A, IP2SR2_3_0)
	177	+#define GPSR2_15 F_(GP2_15, IP1SR2_31_28)
	178	+#define GPSR2_14 F_(GP2_14, IP1SR2_27_24)
	179	+#define GPSR2_13 F_(GP2_13, IP1SR2_23_20)
	180	+#define GPSR2_12 F_(GP2_12, IP1SR2_19_16)
	181	+#define GPSR2_11 F_(GP2_11, IP1SR2_15_12)
	182	+#define GPSR2_10 F_(GP2_10, IP1SR2_11_8)
	183	+#define GPSR2_9 F_(GP2_09, IP1SR2_7_4)
	184	+#define GPSR2_8 F_(GP2_08, IP1SR2_3_0)
	185	+#define GPSR2_7 F_(GP2_07, IP0SR2_31_28)
	186	+#define GPSR2_6 F_(GP2_06, IP0SR2_27_24)
	187	+#define GPSR2_5 F_(GP2_05, IP0SR2_23_20)
	188	+#define GPSR2_4 F_(GP2_04, IP0SR2_19_16)
	189	+#define GPSR2_3 F_(GP2_03, IP0SR2_15_12)
	190	+#define GPSR2_2 F_(GP2_02, IP0SR2_11_8)
	191	+#define GPSR2_1 F_(IPC_CLKOUT, IP0SR2_7_4)
	192	+#define GPSR2_0 F_(IPC_CLKIN, IP0SR2_3_0)
	193	+
	194	+/* GPSR3 */
	195	+#define GPSR3_16 FM(CANFD7_RX)
	196	+#define GPSR3_15 FM(CANFD7_TX)
	197	+#define GPSR3_14 FM(CANFD6_RX)
	198	+#define GPSR3_13 F_(CANFD6_TX, IP1SR3_23_20)
	199	+#define GPSR3_12 F_(CANFD5_RX, IP1SR3_19_16)
	200	+#define GPSR3_11 F_(CANFD5_TX, IP1SR3_15_12)
	201	+#define GPSR3_10 F_(CANFD4_RX, IP1SR3_11_8)
	202	+#define GPSR3_9 F_(CANFD4_TX, IP1SR3_7_4)
	203	+#define GPSR3_8 F_(CANFD3_RX, IP1SR3_3_0)
	204	+#define GPSR3_7 F_(CANFD3_TX, IP0SR3_31_28)
	205	+#define GPSR3_6 F_(CANFD2_RX, IP0SR3_27_24)
	206	+#define GPSR3_5 F_(CANFD2_TX, IP0SR3_23_20)
	207	+#define GPSR3_4 FM(CANFD1_RX)
	208	+#define GPSR3_3 FM(CANFD1_TX)
	209	+#define GPSR3_2 F_(CANFD0_RX, IP0SR3_11_8)
	210	+#define GPSR3_1 F_(CANFD0_TX, IP0SR3_7_4)
	211	+#define GPSR3_0 FM(CAN_CLK)
	212	+
	213	+/* GPSR4 */
	214	+#define GPSR4_26 FM(AVS1)
	215	+#define GPSR4_25 FM(AVS0)
	216	+#define GPSR4_24 FM(PCIE3_CLKREQ_N)
	217	+#define GPSR4_23 FM(PCIE2_CLKREQ_N)
	218	+#define GPSR4_22 FM(PCIE1_CLKREQ_N)
	219	+#define GPSR4_21 FM(PCIE0_CLKREQ_N)
	220	+#define GPSR4_20 F_(AVB0_AVTP_PPS, IP2SR4_19_16)
	221	+#define GPSR4_19 F_(AVB0_AVTP_CAPTURE, IP2SR4_15_12)
	222	+#define GPSR4_18 F_(AVB0_AVTP_MATCH, IP2SR4_11_8)
	223	+#define GPSR4_17 F_(AVB0_LINK, IP2SR4_7_4)
	224	+#define GPSR4_16 FM(AVB0_PHY_INT)
	225	+#define GPSR4_15 F_(AVB0_MAGIC, IP1SR4_31_28)
	226	+#define GPSR4_14 F_(AVB0_MDC, IP1SR4_27_24)
	227	+#define GPSR4_13 F_(AVB0_MDIO, IP1SR4_23_20)
	228	+#define GPSR4_12 F_(AVB0_TXCREFCLK, IP1SR4_19_16)
	229	+#define GPSR4_11 F_(AVB0_TD3, IP1SR4_15_12)
	230	+#define GPSR4_10 F_(AVB0_TD2, IP1SR4_11_8)
	231	+#define GPSR4_9 F_(AVB0_TD1, IP1SR4_7_4)
	232	+#define GPSR4_8 F_(AVB0_TD0, IP1SR4_3_0)
	233	+#define GPSR4_7 F_(AVB0_TXC, IP0SR4_31_28)
	234	+#define GPSR4_6 F_(AVB0_TX_CTL, IP0SR4_27_24)
	235	+#define GPSR4_5 F_(AVB0_RD3, IP0SR4_23_20)
	236	+#define GPSR4_4 F_(AVB0_RD2, IP0SR4_19_16)
	237	+#define GPSR4_3 F_(AVB0_RD1, IP0SR4_15_12)
	238	+#define GPSR4_2 F_(AVB0_RD0, IP0SR4_11_8)
	239	+#define GPSR4_1 F_(AVB0_RXC, IP0SR4_7_4)
	240	+#define GPSR4_0 F_(AVB0_RX_CTL, IP0SR4_3_0)
	241	+
	242	+/* GPSR5 */
	243	+#define GPSR5_20 F_(AVB1_AVTP_PPS, IP2SR5_19_16)
	244	+#define GPSR5_19 F_(AVB1_AVTP_CAPTURE, IP2SR5_15_12)
	245	+#define GPSR5_18 F_(AVB1_AVTP_MATCH, IP2SR5_11_8)
	246	+#define GPSR5_17 F_(AVB1_LINK, IP2SR5_7_4)
	247	+#define GPSR5_16 FM(AVB1_PHY_INT)
	248	+#define GPSR5_15 F_(AVB1_MAGIC, IP1SR5_31_28)
	249	+#define GPSR5_14 F_(AVB1_MDC, IP1SR5_27_24)
	250	+#define GPSR5_13 F_(AVB1_MDIO, IP1SR5_23_20)
	251	+#define GPSR5_12 F_(AVB1_TXCREFCLK, IP1SR5_19_16)
	252	+#define GPSR5_11 F_(AVB1_TD3, IP1SR5_15_12)
	253	+#define GPSR5_10 F_(AVB1_TD2, IP1SR5_11_8)
	254	+#define GPSR5_9 F_(AVB1_TD1, IP1SR5_7_4)
	255	+#define GPSR5_8 F_(AVB1_TD0, IP1SR5_3_0)
	256	+#define GPSR5_7 F_(AVB1_TXC, IP0SR5_31_28)
	257	+#define GPSR5_6 F_(AVB1_TX_CTL, IP0SR5_27_24)
	258	+#define GPSR5_5 F_(AVB1_RD3, IP0SR5_23_20)
	259	+#define GPSR5_4 F_(AVB1_RD2, IP0SR5_19_16)
	260	+#define GPSR5_3 F_(AVB1_RD1, IP0SR5_15_12)
	261	+#define GPSR5_2 F_(AVB1_RD0, IP0SR5_11_8)
	262	+#define GPSR5_1 F_(AVB1_RXC, IP0SR5_7_4)
	263	+#define GPSR5_0 F_(AVB1_RX_CTL, IP0SR5_3_0)
	264	+
	265	+/* GPSR6 */
	266	+#define GPSR6_20 FM(AVB2_AVTP_PPS)
	267	+#define GPSR6_19 FM(AVB2_AVTP_CAPTURE)
	268	+#define GPSR6_18 FM(AVB2_AVTP_MATCH)
	269	+#define GPSR6_17 FM(AVB2_LINK)
	270	+#define GPSR6_16 FM(AVB2_PHY_INT)
	271	+#define GPSR6_15 FM(AVB2_MAGIC)
	272	+#define GPSR6_14 FM(AVB2_MDC)
	273	+#define GPSR6_13 FM(AVB2_MDIO)
	274	+#define GPSR6_12 FM(AVB2_TXCREFCLK)
	275	+#define GPSR6_11 FM(AVB2_TD3)
	276	+#define GPSR6_10 FM(AVB2_TD2)
	277	+#define GPSR6_9 FM(AVB2_TD1)
	278	+#define GPSR6_8 FM(AVB2_TD0)
	279	+#define GPSR6_7 FM(AVB2_TXC)
	280	+#define GPSR6_6 FM(AVB2_TX_CTL)
	281	+#define GPSR6_5 FM(AVB2_RD3)
	282	+#define GPSR6_4 FM(AVB2_RD2)
	283	+#define GPSR6_3 FM(AVB2_RD1)
	284	+#define GPSR6_2 FM(AVB2_RD0)
	285	+#define GPSR6_1 FM(AVB2_RXC)
	286	+#define GPSR6_0 FM(AVB2_RX_CTL)
	287	+
	288	+/* GPSR7 */
	289	+#define GPSR7_20 FM(AVB3_AVTP_PPS)
	290	+#define GPSR7_19 FM(AVB3_AVTP_CAPTURE)
	291	+#define GPSR7_18 FM(AVB3_AVTP_MATCH)
	292	+#define GPSR7_17 FM(AVB3_LINK)
	293	+#define GPSR7_16 FM(AVB3_PHY_INT)
	294	+#define GPSR7_15 FM(AVB3_MAGIC)
	295	+#define GPSR7_14 FM(AVB3_MDC)
	296	+#define GPSR7_13 FM(AVB3_MDIO)
	297	+#define GPSR7_12 FM(AVB3_TXCREFCLK)
	298	+#define GPSR7_11 FM(AVB3_TD3)
	299	+#define GPSR7_10 FM(AVB3_TD2)
	300	+#define GPSR7_9 FM(AVB3_TD1)
	301	+#define GPSR7_8 FM(AVB3_TD0)
	302	+#define GPSR7_7 FM(AVB3_TXC)
	303	+#define GPSR7_6 FM(AVB3_TX_CTL)
	304	+#define GPSR7_5 FM(AVB3_RD3)
	305	+#define GPSR7_4 FM(AVB3_RD2)
	306	+#define GPSR7_3 FM(AVB3_RD1)
	307	+#define GPSR7_2 FM(AVB3_RD0)
	308	+#define GPSR7_1 FM(AVB3_RXC)
	309	+#define GPSR7_0 FM(AVB3_RX_CTL)
	310	+
	311	+/* GPSR8 */
	312	+#define GPSR8_20 FM(AVB4_AVTP_PPS)
	313	+#define GPSR8_19 FM(AVB4_AVTP_CAPTURE)
	314	+#define GPSR8_18 FM(AVB4_AVTP_MATCH)
	315	+#define GPSR8_17 FM(AVB4_LINK)
	316	+#define GPSR8_16 FM(AVB4_PHY_INT)
	317	+#define GPSR8_15 FM(AVB4_MAGIC)
	318	+#define GPSR8_14 FM(AVB4_MDC)
	319	+#define GPSR8_13 FM(AVB4_MDIO)
	320	+#define GPSR8_12 FM(AVB4_TXCREFCLK)
	321	+#define GPSR8_11 FM(AVB4_TD3)
	322	+#define GPSR8_10 FM(AVB4_TD2)
	323	+#define GPSR8_9 FM(AVB4_TD1)
	324	+#define GPSR8_8 FM(AVB4_TD0)
	325	+#define GPSR8_7 FM(AVB4_TXC)
	326	+#define GPSR8_6 FM(AVB4_TX_CTL)
	327	+#define GPSR8_5 FM(AVB4_RD3)
	328	+#define GPSR8_4 FM(AVB4_RD2)
	329	+#define GPSR8_3 FM(AVB4_RD1)
	330	+#define GPSR8_2 FM(AVB4_RD0)
	331	+#define GPSR8_1 FM(AVB4_RXC)
	332	+#define GPSR8_0 FM(AVB4_RX_CTL)
	333	+
	334	+/* GPSR9 */
	335	+#define GPSR9_20 FM(AVB5_AVTP_PPS)
	336	+#define GPSR9_19 FM(AVB5_AVTP_CAPTURE)
	337	+#define GPSR9_18 FM(AVB5_AVTP_MATCH)
	338	+#define GPSR9_17 FM(AVB5_LINK)
	339	+#define GPSR9_16 FM(AVB5_PHY_INT)
	340	+#define GPSR9_15 FM(AVB5_MAGIC)
	341	+#define GPSR9_14 FM(AVB5_MDC)
	342	+#define GPSR9_13 FM(AVB5_MDIO)
	343	+#define GPSR9_12 FM(AVB5_TXCREFCLK)
	344	+#define GPSR9_11 FM(AVB5_TD3)
	345	+#define GPSR9_10 FM(AVB5_TD2)
	346	+#define GPSR9_9 FM(AVB5_TD1)
	347	+#define GPSR9_8 FM(AVB5_TD0)
	348	+#define GPSR9_7 FM(AVB5_TXC)
	349	+#define GPSR9_6 FM(AVB5_TX_CTL)
	350	+#define GPSR9_5 FM(AVB5_RD3)
	351	+#define GPSR9_4 FM(AVB5_RD2)
	352	+#define GPSR9_3 FM(AVB5_RD1)
	353	+#define GPSR9_2 FM(AVB5_RD0)
	354	+#define GPSR9_1 FM(AVB5_RXC)
	355	+#define GPSR9_0 FM(AVB5_RX_CTL)
	356	+
	357	+/* IP0SR1 / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 - F */
	358	+#define IP0SR1_3_0 FM(SCIF_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	359	+#define IP0SR1_7_4 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	360	+#define IP0SR1_11_8 FM(HSCK0) FM(SCK0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	361	+#define IP0SR1_15_12 FM(HRTS0_N) FM(RTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	362	+#define IP0SR1_19_16 FM(HCTS0_N) FM(CTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	363	+#define IP0SR1_23_20 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	364	+#define IP0SR1_27_24 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	365	+#define IP0SR1_31_28 FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR3) FM(A7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	366	+/* IP1SR1 / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 - F */
	367	+#define IP1SR1_3_0 FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR4) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	368	+#define IP1SR1_7_4 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	369	+#define IP1SR1_11_8 FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	370	+#define IP1SR1_15_12 FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR7) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	371	+#define IP1SR1_19_16 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DG2) FM(A12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	372	+#define IP1SR1_23_20 FM(MSIOF1_TXD) FM(HRX3) FM(SCK3) F_(0, 0) FM(DU_DG3) FM(A13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	373	+#define IP1SR1_27_24 FM(MSIOF1_SCK) FM(HSCK3) FM(CTS3_N) F_(0, 0) FM(DU_DG4) FM(A14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	374	+#define IP1SR1_31_28 FM(MSIOF1_SYNC) FM(HRTS3_N) FM(RTS3_N) F_(0, 0) FM(DU_DG5) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	375	+/* IP2SR1 / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 - F */
	376	+#define IP2SR1_3_0 FM(MSIOF1_SS1) FM(HCTS3_N) FM(RX3) F_(0, 0) FM(DU_DG6) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	377	+#define IP2SR1_7_4 FM(MSIOF1_SS2) FM(HTX3) FM(TX3) F_(0, 0) FM(DU_DG7) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	378	+#define IP2SR1_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) FM(DU_DB2) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	379	+#define IP2SR1_15_12 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) FM(DU_DB3) FM(A19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	380	+#define IP2SR1_19_16 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) FM(DU_DB4) FM(A20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	381	+#define IP2SR1_23_20 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1_A) F_(0, 0) FM(DU_DB5) FM(A21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	382	+#define IP2SR1_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1_A) F_(0, 0) FM(DU_DB6) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	383	+#define IP2SR1_31_28 FM(MSIOF2_SS2) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(DU_DB7) FM(A23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	384	+
	385	+/* IP3SR1 / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 - F */
	386	+#define IP3SR1_3_0 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKOUT) FM(A24) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	387	+#define IP3SR1_7_4 FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_HSYNC) FM(A25) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	388	+#define IP3SR1_11_8 FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_VSYNC) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	389	+#define IP3SR1_15_12 FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_ODDF_DISP_CDE) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	390	+#define IP3SR1_19_16 FM(GP1_28) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	391	+#define IP3SR1_23_20 FM(GP1_29) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	392	+#define IP3SR1_27_24 FM(GP1_30) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	393	+#define IP3SR1_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	394	+
	395	+/* IP0SR2 / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 - F */
	396	+#define IP0SR2_3_0 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	397	+#define IP0SR2_7_4 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	398	+#define IP0SR2_11_8 FM(GP2_02) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	399	+#define IP0SR2_15_12 FM(GP2_03) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	400	+#define IP0SR2_19_16 FM(GP2_04) F_(0, 0) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) FM(D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	401	+#define IP0SR2_23_20 FM(GP2_05) FM(HSCK2) FM(MSIOF4_TXD) FM(SCK4) F_(0, 0) FM(D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	402	+#define IP0SR2_27_24 FM(GP2_06) FM(HCTS2_N) FM(MSIOF4_SCK) FM(CTS4_N) F_(0, 0) FM(D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	403	+#define IP0SR2_31_28 FM(GP2_07) FM(HRTS2_N) FM(MSIOF4_SYNC) FM(RTS4_N) F_(0, 0) FM(D8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	404	+/* IP1SR2 / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 - F */
	405	+#define IP1SR2_3_0 FM(GP2_08) FM(HRX2) FM(MSIOF4_SS1) FM(RX4) F_(0, 0) FM(D9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	406	+#define IP1SR2_7_4 FM(GP2_09) FM(HTX2) FM(MSIOF4_SS2) FM(TX4) F_(0, 0) FM(D10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	407	+#define IP1SR2_11_8 FM(GP2_10) FM(TCLK2_B) FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) FM(D11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	408	+#define IP1SR2_15_12 FM(GP2_11) FM(TCLK3) FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) FM(D12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	409	+#define IP1SR2_19_16 FM(GP2_12) FM(TCLK4) FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) FM(D13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	410	+#define IP1SR2_23_20 FM(GP2_13) F_(0, 0) FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	411	+#define IP1SR2_27_24 FM(GP2_14) FM(IRQ4) FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	412	+#define IP1SR2_31_28 FM(GP2_15) FM(IRQ5) FM(MSIOF5_SS2) FM(CPG_CPCKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	413	+/* IP2SR2 / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 - F */
	414	+#define IP2SR2_3_0 FM(FXR_TXDA_A) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	415	+#define IP2SR2_7_4 FM(RXDA_EXTFXR_A) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) FM(BS_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	416	+#define IP2SR2_11_8 FM(FXR_TXDB) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(RD_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	417	+#define IP2SR2_15_12 FM(RXDB_EXTFXR) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(WE0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	418	+#define IP2SR2_19_16 FM(CLK_EXTFXR) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	419	+#define IP2SR2_23_20 FM(TPU0TO0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(RD_WR_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	420	+#define IP2SR2_27_24 FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	421	+#define IP2SR2_31_28 FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(EX_WAIT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	422	+
	423	+/* IP0SR3 / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 - F */
	424	+#define IP0SR3_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	425	+#define IP0SR3_7_4 FM(CANFD0_TX) FM(FXR_TXDA_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	426	+#define IP0SR3_11_8 FM(CANFD0_RX) FM(RXDA_EXTFXR_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	427	+#define IP0SR3_15_12 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	428	+#define IP0SR3_19_16 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	429	+#define IP0SR3_23_20 FM(CANFD2_TX) FM(TPU0TO2) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	430	+#define IP0SR3_27_24 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	431	+#define IP0SR3_31_28 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	432	+/* IP1SR3 / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 - F */
	433	+#define IP1SR3_3_0 FM(CANFD3_RX) F_(0, 0) FM(PWM3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	434	+#define IP1SR3_7_4 FM(CANFD4_TX) F_(0, 0) FM(PWM4) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	435	+#define IP1SR3_11_8 FM(CANFD4_RX) F_(0, 0) F_(0, 0) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	436	+#define IP1SR3_15_12 FM(CANFD5_TX) F_(0, 0) F_(0, 0) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	437	+#define IP1SR3_19_16 FM(CANFD5_RX) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	438	+#define IP1SR3_23_20 FM(CANFD6_TX) F_(0, 0) F_(0, 0) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	439	+#define IP1SR3_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	440	+#define IP1SR3_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	441	+
	442	+/* IP0SR4 / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 - F */
	443	+#define IP0SR4_3_0 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	444	+#define IP0SR4_7_4 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	445	+#define IP0SR4_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	446	+#define IP0SR4_15_12 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	447	+#define IP0SR4_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	448	+#define IP0SR4_23_20 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	449	+#define IP0SR4_27_24 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	450	+#define IP0SR4_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	451	+/* IP1SR4 / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 - F */
	452	+#define IP1SR4_3_0 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	453	+#define IP1SR4_7_4 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	454	+#define IP1SR4_11_8 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	455	+#define IP1SR4_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	456	+#define IP1SR4_19_16 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	457	+#define IP1SR4_23_20 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	458	+#define IP1SR4_27_24 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	459	+#define IP1SR4_31_28 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	460	+/* IP2SR4 / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 - F */
	461	+#define IP2SR4_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	462	+#define IP2SR4_7_4 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	463	+#define IP2SR4_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	464	+#define IP2SR4_15_12 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	465	+#define IP2SR4_19_16 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	466	+#define IP2SR4_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	467	+#define IP2SR4_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	468	+#define IP2SR4_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	469	+
	470	+/* IP0SR5 / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 - F */
	471	+#define IP0SR5_3_0 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	472	+#define IP0SR5_7_4 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	473	+#define IP0SR5_11_8 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	474	+#define IP0SR5_15_12 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	475	+#define IP0SR5_19_16 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	476	+#define IP0SR5_23_20 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	477	+#define IP0SR5_27_24 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	478	+#define IP0SR5_31_28 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	479	+/* IP1SR5 / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 - F */
	480	+#define IP1SR5_3_0 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	481	+#define IP1SR5_7_4 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	482	+#define IP1SR5_11_8 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	483	+#define IP1SR5_15_12 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	484	+#define IP1SR5_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	485	+#define IP1SR5_23_20 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	486	+#define IP1SR5_27_24 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	487	+#define IP1SR5_31_28 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	488	+/* IP2SR5 / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 - F */
	489	+#define IP2SR5_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	490	+#define IP2SR5_7_4 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	491	+#define IP2SR5_11_8 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	492	+#define IP2SR5_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	493	+#define IP2SR5_19_16 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	494	+#define IP2SR5_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	495	+#define IP2SR5_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	496	+#define IP2SR5_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	497	+
	498	+#define PINMUX_GPSR \
	499	+ \
	500	+ GPSR1_30 \
	501	+ GPSR1_29 \
	502	+ GPSR1_28 \
	503	+GPSR0_27 GPSR1_27 \
	504	+GPSR0_26 GPSR1_26 GPSR4_26 \
	505	+GPSR0_25 GPSR1_25 GPSR4_25 \
	506	+GPSR0_24 GPSR1_24 GPSR2_24 GPSR4_24 \
	507	+GPSR0_23 GPSR1_23 GPSR2_23 GPSR4_23 \
	508	+GPSR0_22 GPSR1_22 GPSR2_22 GPSR4_22 \
	509	+GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \
	510	+GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 GPSR6_20 GPSR7_20 GPSR8_20 GPSR9_20 \
	511	+GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 GPSR6_19 GPSR7_19 GPSR8_19 GPSR9_19 \
	512	+GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 GPSR6_18 GPSR7_18 GPSR8_18 GPSR9_18 \
	513	+GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 GPSR6_17 GPSR7_17 GPSR8_17 GPSR9_17 \
	514	+GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 GPSR5_16 GPSR6_16 GPSR7_16 GPSR8_16 GPSR9_16 \
	515	+GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 GPSR7_15 GPSR8_15 GPSR9_15 \
	516	+GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 GPSR7_14 GPSR8_14 GPSR9_14 \
	517	+GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 GPSR7_13 GPSR8_13 GPSR9_13 \
	518	+GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 GPSR7_12 GPSR8_12 GPSR9_12 \
	519	+GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 GPSR7_11 GPSR8_11 GPSR9_11 \
	520	+GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 GPSR7_10 GPSR8_10 GPSR9_10 \
	521	+GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 GPSR7_9 GPSR8_9 GPSR9_9 \
	522	+GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 GPSR7_8 GPSR8_8 GPSR9_8 \
	523	+GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 GPSR7_7 GPSR8_7 GPSR9_7 \
	524	+GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 GPSR7_6 GPSR8_6 GPSR9_6 \
	525	+GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 GPSR7_5 GPSR8_5 GPSR9_5 \
	526	+GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 GPSR7_4 GPSR8_4 GPSR9_4 \
	527	+GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 GPSR8_3 GPSR9_3 \
	528	+GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 GPSR8_2 GPSR9_2 \
	529	+GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 GPSR8_1 GPSR9_1 \
	530	+GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 GPSR8_0 GPSR9_0
	531	+
	532	+#define PINMUX_IPSR \
	533	+\
	534	+FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \
	535	+FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \
	536	+FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \
	537	+FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \
	538	+FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \
	539	+FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 FM(IP3SR1_23_20) IP3SR1_23_20 \
	540	+FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 FM(IP3SR1_27_24) IP3SR1_27_24 \
	541	+FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 FM(IP3SR1_31_28) IP3SR1_31_28 \
	542	+\
	543	+FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 FM(IP2SR2_3_0) IP2SR2_3_0 \
	544	+FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \
	545	+FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 FM(IP2SR2_11_8) IP2SR2_11_8 \
	546	+FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \
	547	+FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 FM(IP2SR2_19_16) IP2SR2_19_16 \
	548	+FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 FM(IP2SR2_23_20) IP2SR2_23_20 \
	549	+FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 FM(IP2SR2_27_24) IP2SR2_27_24 \
	550	+FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 FM(IP2SR2_31_28) IP2SR2_31_28 \
	551	+\
	552	+FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 \
	553	+FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 \
	554	+FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 \
	555	+FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 \
	556	+FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 \
	557	+FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 \
	558	+FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 \
	559	+FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 \
	560	+\
	561	+FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP2SR4_3_0) IP2SR4_3_0 \
	562	+FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 FM(IP2SR4_7_4) IP2SR4_7_4 \
	563	+FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 FM(IP2SR4_11_8) IP2SR4_11_8 \
	564	+FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 FM(IP2SR4_15_12) IP2SR4_15_12 \
	565	+FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 FM(IP2SR4_19_16) IP2SR4_19_16 \
	566	+FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \
	567	+FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 FM(IP2SR4_27_24) IP2SR4_27_24 \
	568	+FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \
	569	+\
	570	+FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \
	571	+FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \
	572	+FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \
	573	+FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \
	574	+FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \
	575	+FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 FM(IP2SR5_23_20) IP2SR5_23_20 \
	576	+FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 FM(IP2SR5_27_24) IP2SR5_27_24 \
	577	+FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 FM(IP2SR5_31_28) IP2SR5_31_28
	578	+
	579	+/* MOD_SEL2 / / 0 / / 1 / / 2 / / 3 */
	580	+#define MOD_SEL2_14_15 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3)
	581	+#define MOD_SEL2_12_13 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3)
	582	+#define MOD_SEL2_10_11 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3)
	583	+#define MOD_SEL2_8_9 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3)
	584	+#define MOD_SEL2_6_7 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3)
	585	+#define MOD_SEL2_4_5 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3)
	586	+#define MOD_SEL2_2_3 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3)
	587	+
	588	+#define PINMUX_MOD_SELS \
	589	+\
	590	+MOD_SEL2_14_15 \
	591	+MOD_SEL2_12_13 \
	592	+MOD_SEL2_10_11 \
	593	+MOD_SEL2_8_9 \
	594	+MOD_SEL2_6_7 \
	595	+MOD_SEL2_4_5 \
	596	+MOD_SEL2_2_3
	597	+
	598	+#define PINMUX_PHYS \
	599	+ FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \
	600	+ FM(SCL4) FM(SDA4) FM(SCL5) FM(SDA5) FM(SCL6) FM(SDA6)
	601	+
	602	+enum {
	603	+ PINMUX_RESERVED = 0,
	604	+
	605	+ PINMUX_DATA_BEGIN,
	606	+ GP_ALL(DATA),
	607	+ PINMUX_DATA_END,
	608	+
	609	+#define F_(x, y)
	610	+#define FM(x) FN_##x,
	611	+ PINMUX_FUNCTION_BEGIN,
	612	+ GP_ALL(FN),
	613	+ PINMUX_GPSR
	614	+ PINMUX_IPSR
	615	+ PINMUX_MOD_SELS
	616	+ PINMUX_FUNCTION_END,
	617	+#undef F_
	618	+#undef FM
	619	+
	620	+#define F_(x, y)
	621	+#define FM(x) x##_MARK,
	622	+ PINMUX_MARK_BEGIN,
	623	+ PINMUX_GPSR
	624	+ PINMUX_IPSR
	625	+ PINMUX_MOD_SELS
	626	+ PINMUX_PHYS
	627	+ PINMUX_MARK_END,
	628	+#undef F_
	629	+#undef FM
	630	+};
	631	+
	632	+static const u16 pinmux_data[] = {
	633	+ PINMUX_DATA_GP_ALL(),
	634	+
	635	+ PINMUX_SINGLE(MMC_D7),
	636	+ PINMUX_SINGLE(MMC_D6),
	637	+ PINMUX_SINGLE(MMC_D5),
	638	+ PINMUX_SINGLE(MMC_D4),
	639	+ PINMUX_SINGLE(MMC_SD_CLK),
	640	+ PINMUX_SINGLE(MMC_SD_D3),
	641	+ PINMUX_SINGLE(MMC_SD_D2),
	642	+ PINMUX_SINGLE(MMC_SD_D1),
	643	+ PINMUX_SINGLE(MMC_SD_D0),
	644	+ PINMUX_SINGLE(MMC_SD_CMD),
	645	+ PINMUX_SINGLE(MMC_DS),
	646	+
	647	+ PINMUX_SINGLE(SD_CD),
	648	+ PINMUX_SINGLE(SD_WP),
	649	+
	650	+ PINMUX_SINGLE(RPC_INT_N),
	651	+ PINMUX_SINGLE(RPC_WP_N),
	652	+ PINMUX_SINGLE(RPC_RESET_N),
	653	+
	654	+ PINMUX_SINGLE(QSPI1_SSL),
	655	+ PINMUX_SINGLE(QSPI1_IO3),
	656	+ PINMUX_SINGLE(QSPI1_IO2),
	657	+ PINMUX_SINGLE(QSPI1_MISO_IO1),
	658	+ PINMUX_SINGLE(QSPI1_MOSI_IO0),
	659	+ PINMUX_SINGLE(QSPI1_SPCLK),
	660	+ PINMUX_SINGLE(QSPI0_SSL),
	661	+ PINMUX_SINGLE(QSPI0_IO3),
	662	+ PINMUX_SINGLE(QSPI0_IO2),
	663	+ PINMUX_SINGLE(QSPI0_MISO_IO1),
	664	+ PINMUX_SINGLE(QSPI0_MOSI_IO0),
	665	+ PINMUX_SINGLE(QSPI0_SPCLK),
	666	+
	667	+ PINMUX_SINGLE(TCLK2_A),
	668	+
	669	+ PINMUX_SINGLE(CANFD7_RX),
	670	+ PINMUX_SINGLE(CANFD7_TX),
	671	+ PINMUX_SINGLE(CANFD6_RX),
	672	+ PINMUX_SINGLE(CANFD1_RX),
	673	+ PINMUX_SINGLE(CANFD1_TX),
	674	+ PINMUX_SINGLE(CAN_CLK),
	675	+
	676	+ PINMUX_SINGLE(AVS1),
	677	+ PINMUX_SINGLE(AVS0),
	678	+
	679	+ PINMUX_SINGLE(PCIE3_CLKREQ_N),
	680	+ PINMUX_SINGLE(PCIE2_CLKREQ_N),
	681	+ PINMUX_SINGLE(PCIE1_CLKREQ_N),
	682	+ PINMUX_SINGLE(PCIE0_CLKREQ_N),
	683	+
	684	+ PINMUX_SINGLE(AVB0_PHY_INT),
	685	+ PINMUX_SINGLE(AVB0_MAGIC),
	686	+ PINMUX_SINGLE(AVB0_MDC),
	687	+ PINMUX_SINGLE(AVB0_MDIO),
	688	+ PINMUX_SINGLE(AVB0_TXCREFCLK),
	689	+
	690	+ PINMUX_SINGLE(AVB1_PHY_INT),
	691	+ PINMUX_SINGLE(AVB1_MAGIC),
	692	+ PINMUX_SINGLE(AVB1_MDC),
	693	+ PINMUX_SINGLE(AVB1_MDIO),
	694	+ PINMUX_SINGLE(AVB1_TXCREFCLK),
	695	+
	696	+ PINMUX_SINGLE(AVB2_AVTP_PPS),
	697	+ PINMUX_SINGLE(AVB2_AVTP_CAPTURE),
	698	+ PINMUX_SINGLE(AVB2_AVTP_MATCH),
	699	+ PINMUX_SINGLE(AVB2_LINK),
	700	+ PINMUX_SINGLE(AVB2_PHY_INT),
	701	+ PINMUX_SINGLE(AVB2_MAGIC),
	702	+ PINMUX_SINGLE(AVB2_MDC),
	703	+ PINMUX_SINGLE(AVB2_MDIO),
	704	+ PINMUX_SINGLE(AVB2_TXCREFCLK),
	705	+ PINMUX_SINGLE(AVB2_TD3),
	706	+ PINMUX_SINGLE(AVB2_TD2),
	707	+ PINMUX_SINGLE(AVB2_TD1),
	708	+ PINMUX_SINGLE(AVB2_TD0),
	709	+ PINMUX_SINGLE(AVB2_TXC),
	710	+ PINMUX_SINGLE(AVB2_TX_CTL),
	711	+ PINMUX_SINGLE(AVB2_RD3),
	712	+ PINMUX_SINGLE(AVB2_RD2),
	713	+ PINMUX_SINGLE(AVB2_RD1),
	714	+ PINMUX_SINGLE(AVB2_RD0),
	715	+ PINMUX_SINGLE(AVB2_RXC),
	716	+ PINMUX_SINGLE(AVB2_RX_CTL),
	717	+
	718	+ PINMUX_SINGLE(AVB3_AVTP_PPS),
	719	+ PINMUX_SINGLE(AVB3_AVTP_CAPTURE),
	720	+ PINMUX_SINGLE(AVB3_AVTP_MATCH),
	721	+ PINMUX_SINGLE(AVB3_LINK),
	722	+ PINMUX_SINGLE(AVB3_PHY_INT),
	723	+ PINMUX_SINGLE(AVB3_MAGIC),
	724	+ PINMUX_SINGLE(AVB3_MDC),
	725	+ PINMUX_SINGLE(AVB3_MDIO),
	726	+ PINMUX_SINGLE(AVB3_TXCREFCLK),
	727	+ PINMUX_SINGLE(AVB3_TD3),
	728	+ PINMUX_SINGLE(AVB3_TD2),
	729	+ PINMUX_SINGLE(AVB3_TD1),
	730	+ PINMUX_SINGLE(AVB3_TD0),
	731	+ PINMUX_SINGLE(AVB3_TXC),
	732	+ PINMUX_SINGLE(AVB3_TX_CTL),
	733	+ PINMUX_SINGLE(AVB3_RD3),
	734	+ PINMUX_SINGLE(AVB3_RD2),
	735	+ PINMUX_SINGLE(AVB3_RD1),
	736	+ PINMUX_SINGLE(AVB3_RD0),
	737	+ PINMUX_SINGLE(AVB3_RXC),
	738	+ PINMUX_SINGLE(AVB3_RX_CTL),
	739	+
	740	+ PINMUX_SINGLE(AVB4_AVTP_PPS),
	741	+ PINMUX_SINGLE(AVB4_AVTP_CAPTURE),
	742	+ PINMUX_SINGLE(AVB4_AVTP_MATCH),
	743	+ PINMUX_SINGLE(AVB4_LINK),
	744	+ PINMUX_SINGLE(AVB4_PHY_INT),
	745	+ PINMUX_SINGLE(AVB4_MAGIC),
	746	+ PINMUX_SINGLE(AVB4_MDC),
	747	+ PINMUX_SINGLE(AVB4_MDIO),
	748	+ PINMUX_SINGLE(AVB4_TXCREFCLK),
	749	+ PINMUX_SINGLE(AVB4_TD3),
	750	+ PINMUX_SINGLE(AVB4_TD2),
	751	+ PINMUX_SINGLE(AVB4_TD1),
	752	+ PINMUX_SINGLE(AVB4_TD0),
	753	+ PINMUX_SINGLE(AVB4_TXC),
	754	+ PINMUX_SINGLE(AVB4_TX_CTL),
	755	+ PINMUX_SINGLE(AVB4_RD3),
	756	+ PINMUX_SINGLE(AVB4_RD2),
	757	+ PINMUX_SINGLE(AVB4_RD1),
	758	+ PINMUX_SINGLE(AVB4_RD0),
	759	+ PINMUX_SINGLE(AVB4_RXC),
	760	+ PINMUX_SINGLE(AVB4_RX_CTL),
	761	+
	762	+ PINMUX_SINGLE(AVB5_AVTP_PPS),
	763	+ PINMUX_SINGLE(AVB5_AVTP_CAPTURE),
	764	+ PINMUX_SINGLE(AVB5_AVTP_MATCH),
	765	+ PINMUX_SINGLE(AVB5_LINK),
	766	+ PINMUX_SINGLE(AVB5_PHY_INT),
	767	+ PINMUX_SINGLE(AVB5_MAGIC),
	768	+ PINMUX_SINGLE(AVB5_MDC),
	769	+ PINMUX_SINGLE(AVB5_MDIO),
	770	+ PINMUX_SINGLE(AVB5_TXCREFCLK),
	771	+ PINMUX_SINGLE(AVB5_TD3),
	772	+ PINMUX_SINGLE(AVB5_TD2),
	773	+ PINMUX_SINGLE(AVB5_TD1),
	774	+ PINMUX_SINGLE(AVB5_TD0),
	775	+ PINMUX_SINGLE(AVB5_TXC),
	776	+ PINMUX_SINGLE(AVB5_TX_CTL),
	777	+ PINMUX_SINGLE(AVB5_RD3),
	778	+ PINMUX_SINGLE(AVB5_RD2),
	779	+ PINMUX_SINGLE(AVB5_RD1),
	780	+ PINMUX_SINGLE(AVB5_RD0),
	781	+ PINMUX_SINGLE(AVB5_RXC),
	782	+ PINMUX_SINGLE(AVB5_RX_CTL),
	783	+
	784	+ /* IP0SR1 */
	785	+ PINMUX_IPSR_GPSR(IP0SR1_3_0, SCIF_CLK),
	786	+ PINMUX_IPSR_GPSR(IP0SR1_3_0, A0),
	787	+
	788	+ PINMUX_IPSR_GPSR(IP0SR1_7_4, HRX0),
	789	+ PINMUX_IPSR_GPSR(IP0SR1_7_4, RX0),
	790	+ PINMUX_IPSR_GPSR(IP0SR1_7_4, A1),
	791	+
	792	+ PINMUX_IPSR_GPSR(IP0SR1_11_8, HSCK0),
	793	+ PINMUX_IPSR_GPSR(IP0SR1_11_8, SCK0),
	794	+ PINMUX_IPSR_GPSR(IP0SR1_11_8, A2),
	795	+
	796	+ PINMUX_IPSR_GPSR(IP0SR1_15_12, HRTS0_N),
	797	+ PINMUX_IPSR_GPSR(IP0SR1_15_12, RTS0_N),
	798	+ PINMUX_IPSR_GPSR(IP0SR1_15_12, A3),
	799	+
	800	+ PINMUX_IPSR_GPSR(IP0SR1_19_16, HCTS0_N),
	801	+ PINMUX_IPSR_GPSR(IP0SR1_19_16, CTS0_N),
	802	+ PINMUX_IPSR_GPSR(IP0SR1_19_16, A4),
	803	+
	804	+ PINMUX_IPSR_GPSR(IP0SR1_23_20, HTX0),
	805	+ PINMUX_IPSR_GPSR(IP0SR1_23_20, TX0),
	806	+ PINMUX_IPSR_GPSR(IP0SR1_23_20, A5),
	807	+
	808	+ PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_RXD),
	809	+ PINMUX_IPSR_GPSR(IP0SR1_27_24, DU_DR2),
	810	+ PINMUX_IPSR_GPSR(IP0SR1_27_24, A6),
	811	+
	812	+ PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_TXD),
	813	+ PINMUX_IPSR_GPSR(IP0SR1_31_28, DU_DR3),
	814	+ PINMUX_IPSR_GPSR(IP0SR1_31_28, A7),
	815	+
	816	+ /* IP1SR1 */
	817	+ PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SCK),
	818	+ PINMUX_IPSR_GPSR(IP1SR1_3_0, DU_DR4),
	819	+ PINMUX_IPSR_GPSR(IP1SR1_3_0, A8),
	820	+
	821	+ PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_SYNC),
	822	+ PINMUX_IPSR_GPSR(IP1SR1_7_4, DU_DR5),
	823	+ PINMUX_IPSR_GPSR(IP1SR1_7_4, A9),
	824	+
	825	+ PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SS1),
	826	+ PINMUX_IPSR_GPSR(IP1SR1_11_8, DU_DR6),
	827	+ PINMUX_IPSR_GPSR(IP1SR1_11_8, A10),
	828	+
	829	+ PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_SS2),
	830	+ PINMUX_IPSR_GPSR(IP1SR1_15_12, DU_DR7),
	831	+ PINMUX_IPSR_GPSR(IP1SR1_15_12, A11),
	832	+
	833	+ PINMUX_IPSR_GPSR(IP1SR1_19_16, MSIOF1_RXD),
	834	+ PINMUX_IPSR_GPSR(IP1SR1_19_16, DU_DG2),
	835	+ PINMUX_IPSR_GPSR(IP1SR1_19_16, A12),
	836	+
	837	+ PINMUX_IPSR_GPSR(IP1SR1_23_20, MSIOF1_TXD),
	838	+ PINMUX_IPSR_GPSR(IP1SR1_23_20, HRX3),
	839	+ PINMUX_IPSR_GPSR(IP1SR1_23_20, SCK3),
	840	+ PINMUX_IPSR_GPSR(IP1SR1_23_20, DU_DG3),
	841	+ PINMUX_IPSR_GPSR(IP1SR1_23_20, A13),
	842	+
	843	+ PINMUX_IPSR_GPSR(IP1SR1_27_24, MSIOF1_SCK),
	844	+ PINMUX_IPSR_GPSR(IP1SR1_27_24, HSCK3),
	845	+ PINMUX_IPSR_GPSR(IP1SR1_27_24, CTS3_N),
	846	+ PINMUX_IPSR_GPSR(IP1SR1_27_24, DU_DG4),
	847	+ PINMUX_IPSR_GPSR(IP1SR1_27_24, A14),
	848	+
	849	+ PINMUX_IPSR_GPSR(IP1SR1_31_28, MSIOF1_SYNC),
	850	+ PINMUX_IPSR_GPSR(IP1SR1_31_28, HRTS3_N),
	851	+ PINMUX_IPSR_GPSR(IP1SR1_31_28, RTS3_N),
	852	+ PINMUX_IPSR_GPSR(IP1SR1_31_28, DU_DG5),
	853	+ PINMUX_IPSR_GPSR(IP1SR1_31_28, A15),
	854	+
	855	+ /* IP2SR1 */
	856	+ PINMUX_IPSR_GPSR(IP2SR1_3_0, MSIOF1_SS1),
	857	+ PINMUX_IPSR_GPSR(IP2SR1_3_0, HCTS3_N),
	858	+ PINMUX_IPSR_GPSR(IP2SR1_3_0, RX3),
	859	+ PINMUX_IPSR_GPSR(IP2SR1_3_0, DU_DG6),
	860	+ PINMUX_IPSR_GPSR(IP2SR1_3_0, A16),
	861	+
	862	+ PINMUX_IPSR_GPSR(IP2SR1_7_4, MSIOF1_SS2),
	863	+ PINMUX_IPSR_GPSR(IP2SR1_7_4, HTX3),
	864	+ PINMUX_IPSR_GPSR(IP2SR1_7_4, TX3),
	865	+ PINMUX_IPSR_GPSR(IP2SR1_7_4, DU_DG7),
	866	+ PINMUX_IPSR_GPSR(IP2SR1_7_4, A17),
	867	+
	868	+ PINMUX_IPSR_GPSR(IP2SR1_11_8, MSIOF2_RXD),
	869	+ PINMUX_IPSR_GPSR(IP2SR1_11_8, HSCK1),
	870	+ PINMUX_IPSR_GPSR(IP2SR1_11_8, SCK1),
	871	+ PINMUX_IPSR_GPSR(IP2SR1_11_8, DU_DB2),
	872	+ PINMUX_IPSR_GPSR(IP2SR1_11_8, A18),
	873	+
	874	+ PINMUX_IPSR_GPSR(IP2SR1_15_12, MSIOF2_TXD),
	875	+ PINMUX_IPSR_GPSR(IP2SR1_15_12, HCTS1_N),
	876	+ PINMUX_IPSR_GPSR(IP2SR1_15_12, CTS1_N),
	877	+ PINMUX_IPSR_GPSR(IP2SR1_15_12, DU_DB3),
	878	+ PINMUX_IPSR_GPSR(IP2SR1_15_12, A19),
	879	+
	880	+ PINMUX_IPSR_GPSR(IP2SR1_19_16, MSIOF2_SCK),
	881	+ PINMUX_IPSR_GPSR(IP2SR1_19_16, HRTS1_N),
	882	+ PINMUX_IPSR_GPSR(IP2SR1_19_16, RTS1_N),
	883	+ PINMUX_IPSR_GPSR(IP2SR1_19_16, DU_DB4),
	884	+ PINMUX_IPSR_GPSR(IP2SR1_19_16, A20),
	885	+
	886	+ PINMUX_IPSR_GPSR(IP2SR1_23_20, MSIOF2_SYNC),
	887	+ PINMUX_IPSR_GPSR(IP2SR1_23_20, HRX1),
	888	+ PINMUX_IPSR_GPSR(IP2SR1_23_20, RX1_A),
	889	+ PINMUX_IPSR_GPSR(IP2SR1_23_20, DU_DB5),
	890	+ PINMUX_IPSR_GPSR(IP2SR1_23_20, A21),
	891	+
	892	+ PINMUX_IPSR_GPSR(IP2SR1_27_24, MSIOF2_SS1),
	893	+ PINMUX_IPSR_GPSR(IP2SR1_27_24, HTX1),
	894	+ PINMUX_IPSR_GPSR(IP2SR1_27_24, TX1_A),
	895	+ PINMUX_IPSR_GPSR(IP2SR1_27_24, DU_DB6),
	896	+ PINMUX_IPSR_GPSR(IP2SR1_27_24, A22),
	897	+
	898	+ PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF2_SS2),
	899	+ PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK1_B),
	900	+ PINMUX_IPSR_GPSR(IP2SR1_31_28, DU_DB7),
	901	+ PINMUX_IPSR_GPSR(IP2SR1_31_28, A23),
	902	+
	903	+ /* IP3SR1 */
	904	+ PINMUX_IPSR_GPSR(IP3SR1_3_0, IRQ0),
	905	+ PINMUX_IPSR_GPSR(IP3SR1_3_0, DU_DOTCLKOUT),
	906	+ PINMUX_IPSR_GPSR(IP3SR1_3_0, A24),
	907	+
	908	+ PINMUX_IPSR_GPSR(IP3SR1_7_4, IRQ1),
	909	+ PINMUX_IPSR_GPSR(IP3SR1_7_4, DU_HSYNC),
	910	+ PINMUX_IPSR_GPSR(IP3SR1_7_4, A25),
	911	+
	912	+ PINMUX_IPSR_GPSR(IP3SR1_11_8, IRQ2),
	913	+ PINMUX_IPSR_GPSR(IP3SR1_11_8, DU_VSYNC),
	914	+ PINMUX_IPSR_GPSR(IP3SR1_11_8, CS1_N_A26),
	915	+
	916	+ PINMUX_IPSR_GPSR(IP3SR1_15_12, IRQ3),
	917	+ PINMUX_IPSR_GPSR(IP3SR1_15_12, DU_ODDF_DISP_CDE),
	918	+ PINMUX_IPSR_GPSR(IP3SR1_15_12, CS0_N),
	919	+
	920	+ PINMUX_IPSR_GPSR(IP3SR1_19_16, GP1_28),
	921	+ PINMUX_IPSR_GPSR(IP3SR1_19_16, D0),
	922	+
	923	+ PINMUX_IPSR_GPSR(IP3SR1_23_20, GP1_29),
	924	+ PINMUX_IPSR_GPSR(IP3SR1_23_20, D1),
	925	+
	926	+ PINMUX_IPSR_GPSR(IP3SR1_27_24, GP1_30),
	927	+ PINMUX_IPSR_GPSR(IP3SR1_27_24, D2),
	928	+
	929	+ /* IP0SR2 */
	930	+ PINMUX_IPSR_GPSR(IP0SR2_3_0, IPC_CLKIN),
	931	+ PINMUX_IPSR_GPSR(IP0SR2_3_0, IPC_CLKEN_IN),
	932	+ PINMUX_IPSR_GPSR(IP0SR2_3_0, DU_DOTCLKIN),
	933	+
	934	+ PINMUX_IPSR_GPSR(IP0SR2_7_4, IPC_CLKOUT),
	935	+ PINMUX_IPSR_GPSR(IP0SR2_7_4, IPC_CLKEN_OUT),
	936	+
	937	+ /* GP2_02 = SCL0 */
	938	+ PINMUX_IPSR_MSEL(IP0SR2_11_8, GP2_02, SEL_I2C0_0),
	939	+ PINMUX_IPSR_MSEL(IP0SR2_11_8, D3, SEL_I2C0_0),
	940	+ PINMUX_IPSR_PHYS(IP0SR2_11_8, SCL0, SEL_I2C0_3),
	941	+
	942	+ /* GP2_03 = SDA0 */
	943	+ PINMUX_IPSR_MSEL(IP0SR2_15_12, GP2_03, SEL_I2C0_0),
	944	+ PINMUX_IPSR_MSEL(IP0SR2_15_12, D4, SEL_I2C0_0),
	945	+ PINMUX_IPSR_PHYS(IP0SR2_15_12, SDA0, SEL_I2C0_3),
	946	+
	947	+ /* GP2_04 = SCL1 */
	948	+ PINMUX_IPSR_MSEL(IP0SR2_19_16, GP2_04, SEL_I2C1_0),
	949	+ PINMUX_IPSR_MSEL(IP0SR2_19_16, MSIOF4_RXD, SEL_I2C1_0),
	950	+ PINMUX_IPSR_MSEL(IP0SR2_19_16, D5, SEL_I2C1_0),
	951	+ PINMUX_IPSR_PHYS(IP0SR2_19_16, SCL1, SEL_I2C1_3),
	952	+
	953	+ /* GP2_05 = SDA1 */
	954	+ PINMUX_IPSR_MSEL(IP0SR2_23_20, GP2_05, SEL_I2C1_0),
	955	+ PINMUX_IPSR_MSEL(IP0SR2_23_20, HSCK2, SEL_I2C1_0),
	956	+ PINMUX_IPSR_MSEL(IP0SR2_23_20, MSIOF4_TXD, SEL_I2C1_0),
	957	+ PINMUX_IPSR_MSEL(IP0SR2_23_20, SCK4, SEL_I2C1_0),
	958	+ PINMUX_IPSR_MSEL(IP0SR2_23_20, D6, SEL_I2C1_0),
	959	+ PINMUX_IPSR_PHYS(IP0SR2_23_20, SDA1, SEL_I2C1_3),
	960	+
	961	+ /* GP2_06 = SCL2 */
	962	+ PINMUX_IPSR_MSEL(IP0SR2_27_24, GP2_06, SEL_I2C2_0),
	963	+ PINMUX_IPSR_MSEL(IP0SR2_27_24, HCTS2_N, SEL_I2C2_0),
	964	+ PINMUX_IPSR_MSEL(IP0SR2_27_24, MSIOF4_SCK, SEL_I2C2_0),
	965	+ PINMUX_IPSR_MSEL(IP0SR2_27_24, CTS4_N, SEL_I2C2_0),
	966	+ PINMUX_IPSR_MSEL(IP0SR2_27_24, D7, SEL_I2C2_0),
	967	+ PINMUX_IPSR_PHYS(IP0SR2_27_24, SCL2, SEL_I2C2_3),
	968	+
	969	+ /* GP2_07 = SDA2 */
	970	+ PINMUX_IPSR_MSEL(IP0SR2_31_28, GP2_07, SEL_I2C2_0),
	971	+ PINMUX_IPSR_MSEL(IP0SR2_31_28, HRTS2_N, SEL_I2C2_0),
	972	+ PINMUX_IPSR_MSEL(IP0SR2_31_28, MSIOF4_SYNC, SEL_I2C2_0),
	973	+ PINMUX_IPSR_MSEL(IP0SR2_31_28, RTS4_N, SEL_I2C2_0),
	974	+ PINMUX_IPSR_MSEL(IP0SR2_31_28, D8, SEL_I2C2_0),
	975	+ PINMUX_IPSR_PHYS(IP0SR2_31_28, SDA2, SEL_I2C2_3),
	976	+
	977	+ /* GP2_08 = SCL3 */
	978	+ PINMUX_IPSR_MSEL(IP1SR2_3_0, GP2_08, SEL_I2C3_0),
	979	+ PINMUX_IPSR_MSEL(IP1SR2_3_0, HRX2, SEL_I2C3_0),
	980	+ PINMUX_IPSR_MSEL(IP1SR2_3_0, MSIOF4_SS1, SEL_I2C3_0),
	981	+ PINMUX_IPSR_MSEL(IP1SR2_3_0, RX4, SEL_I2C3_0),
	982	+ PINMUX_IPSR_MSEL(IP1SR2_3_0, D9, SEL_I2C3_0),
	983	+ PINMUX_IPSR_PHYS(IP1SR2_3_0, SCL3, SEL_I2C3_3),
	984	+
	985	+ /* GP2_09 = SDA3 */
	986	+ PINMUX_IPSR_MSEL(IP1SR2_7_4, GP2_09, SEL_I2C3_0),
	987	+ PINMUX_IPSR_MSEL(IP1SR2_7_4, HTX2, SEL_I2C3_0),
	988	+ PINMUX_IPSR_MSEL(IP1SR2_7_4, MSIOF4_SS2, SEL_I2C3_0),
	989	+ PINMUX_IPSR_MSEL(IP1SR2_7_4, TX4, SEL_I2C3_0),
	990	+ PINMUX_IPSR_MSEL(IP1SR2_7_4, D10, SEL_I2C3_0),
	991	+ PINMUX_IPSR_PHYS(IP1SR2_7_4, SDA3, SEL_I2C3_3),
	992	+
	993	+ /* GP2_10 = SCL4 */
	994	+ PINMUX_IPSR_MSEL(IP1SR2_11_8, GP2_10, SEL_I2C4_0),
	995	+ PINMUX_IPSR_MSEL(IP1SR2_11_8, TCLK2_B, SEL_I2C4_0),
	996	+ PINMUX_IPSR_MSEL(IP1SR2_11_8, MSIOF5_RXD, SEL_I2C4_0),
	997	+ PINMUX_IPSR_MSEL(IP1SR2_11_8, D11, SEL_I2C4_0),
	998	+ PINMUX_IPSR_PHYS(IP1SR2_11_8, SCL4, SEL_I2C4_3),
	999	+
	1000	+ /* GP2_11 = SDA4 */
	1001	+ PINMUX_IPSR_MSEL(IP1SR2_15_12, GP2_11, SEL_I2C4_0),
	1002	+ PINMUX_IPSR_MSEL(IP1SR2_15_12, TCLK3, SEL_I2C4_0),
	1003	+ PINMUX_IPSR_MSEL(IP1SR2_15_12, MSIOF5_TXD, SEL_I2C4_0),
	1004	+ PINMUX_IPSR_MSEL(IP1SR2_15_12, D12, SEL_I2C4_0),
	1005	+ PINMUX_IPSR_PHYS(IP1SR2_15_12, SDA4, SEL_I2C4_3),
	1006	+
	1007	+ /* GP2_12 = SCL5 */
	1008	+ PINMUX_IPSR_MSEL(IP1SR2_19_16, GP2_12, SEL_I2C5_0),
	1009	+ PINMUX_IPSR_MSEL(IP1SR2_19_16, TCLK4, SEL_I2C5_0),
	1010	+ PINMUX_IPSR_MSEL(IP1SR2_19_16, MSIOF5_SCK, SEL_I2C5_0),
	1011	+ PINMUX_IPSR_MSEL(IP1SR2_19_16, D13, SEL_I2C5_0),
	1012	+ PINMUX_IPSR_PHYS(IP1SR2_19_16, SCL5, SEL_I2C5_3),
	1013	+
	1014	+ /* GP2_13 = SDA5 */
	1015	+ PINMUX_IPSR_MSEL(IP1SR2_23_20, GP2_13, SEL_I2C5_0),
	1016	+ PINMUX_IPSR_MSEL(IP1SR2_23_20, MSIOF5_SYNC, SEL_I2C5_0),
	1017	+ PINMUX_IPSR_MSEL(IP1SR2_23_20, D14, SEL_I2C5_0),
	1018	+ PINMUX_IPSR_PHYS(IP1SR2_23_20, SDA5, SEL_I2C5_3),
	1019	+
	1020	+ /* GP2_14 = SCL6 */
	1021	+ PINMUX_IPSR_MSEL(IP1SR2_27_24, GP2_14, SEL_I2C6_0),
	1022	+ PINMUX_IPSR_MSEL(IP1SR2_27_24, IRQ4, SEL_I2C6_0),
	1023	+ PINMUX_IPSR_MSEL(IP1SR2_27_24, MSIOF5_SS1, SEL_I2C6_0),
	1024	+ PINMUX_IPSR_MSEL(IP1SR2_27_24, D15, SEL_I2C6_0),
	1025	+ PINMUX_IPSR_PHYS(IP1SR2_27_24, SCL6, SEL_I2C6_3),
	1026	+
	1027	+ /* GP2_15 = SDA6 */
	1028	+ PINMUX_IPSR_MSEL(IP1SR2_31_28, GP2_15, SEL_I2C6_0),
	1029	+ PINMUX_IPSR_MSEL(IP1SR2_31_28, IRQ5, SEL_I2C6_0),
	1030	+ PINMUX_IPSR_MSEL(IP1SR2_31_28, MSIOF5_SS2, SEL_I2C6_0),
	1031	+ PINMUX_IPSR_MSEL(IP1SR2_31_28, CPG_CPCKOUT, SEL_I2C6_0),
	1032	+ PINMUX_IPSR_PHYS(IP1SR2_31_28, SDA6, SEL_I2C6_3),
	1033	+
	1034	+ /* IP2SR2 */
	1035	+ PINMUX_IPSR_GPSR(IP2SR2_3_0, FXR_TXDA_A),
	1036	+ PINMUX_IPSR_GPSR(IP2SR2_3_0, MSIOF3_SS1),
	1037	+
	1038	+ PINMUX_IPSR_GPSR(IP2SR2_7_4, RXDA_EXTFXR_A),
	1039	+ PINMUX_IPSR_GPSR(IP2SR2_7_4, MSIOF3_SS2),
	1040	+ PINMUX_IPSR_GPSR(IP2SR2_7_4, BS_N),
	1041	+
	1042	+ PINMUX_IPSR_GPSR(IP2SR2_11_8, FXR_TXDB),
	1043	+ PINMUX_IPSR_GPSR(IP2SR2_11_8, MSIOF3_RXD),
	1044	+ PINMUX_IPSR_GPSR(IP2SR2_11_8, RD_N),
	1045	+
	1046	+ PINMUX_IPSR_GPSR(IP2SR2_15_12, RXDB_EXTFXR),
	1047	+ PINMUX_IPSR_GPSR(IP2SR2_15_12, MSIOF3_TXD),
	1048	+ PINMUX_IPSR_GPSR(IP2SR2_15_12, WE0_N),
	1049	+
	1050	+ PINMUX_IPSR_GPSR(IP2SR2_19_16, CLK_EXTFXR),
	1051	+ PINMUX_IPSR_GPSR(IP2SR2_19_16, MSIOF3_SCK),
	1052	+ PINMUX_IPSR_GPSR(IP2SR2_19_16, WE1_N),
	1053	+
	1054	+ PINMUX_IPSR_GPSR(IP2SR2_23_20, TPU0TO0),
	1055	+ PINMUX_IPSR_GPSR(IP2SR2_23_20, MSIOF3_SYNC),
	1056	+ PINMUX_IPSR_GPSR(IP2SR2_23_20, RD_WR_N),
	1057	+
	1058	+ PINMUX_IPSR_GPSR(IP2SR2_27_24, TPU0TO1),
	1059	+ PINMUX_IPSR_GPSR(IP2SR2_27_24, CLKOUT),
	1060	+
	1061	+ PINMUX_IPSR_GPSR(IP2SR2_31_28, TCLK1_A),
	1062	+ PINMUX_IPSR_GPSR(IP2SR2_31_28, EX_WAIT0),
	1063	+
	1064	+ /* IP0SR3 */
	1065	+ PINMUX_IPSR_GPSR(IP0SR3_7_4, CANFD0_TX),
	1066	+ PINMUX_IPSR_GPSR(IP0SR3_7_4, FXR_TXDA_B),
	1067	+ PINMUX_IPSR_GPSR(IP0SR3_7_4, TX1_B),
	1068	+
	1069	+ PINMUX_IPSR_GPSR(IP0SR3_11_8, CANFD0_RX),
	1070	+ PINMUX_IPSR_GPSR(IP0SR3_11_8, RXDA_EXTFXR_B),
	1071	+ PINMUX_IPSR_GPSR(IP0SR3_11_8, RX1_B),
	1072	+
	1073	+ PINMUX_IPSR_GPSR(IP0SR3_23_20, CANFD2_TX),
	1074	+ PINMUX_IPSR_GPSR(IP0SR3_23_20, TPU0TO2),
	1075	+ PINMUX_IPSR_GPSR(IP0SR3_23_20, PWM0),
	1076	+
	1077	+ PINMUX_IPSR_GPSR(IP0SR3_27_24, CANFD2_RX),
	1078	+ PINMUX_IPSR_GPSR(IP0SR3_27_24, TPU0TO3),
	1079	+ PINMUX_IPSR_GPSR(IP0SR3_27_24, PWM1),
	1080	+
	1081	+ PINMUX_IPSR_GPSR(IP0SR3_31_28, CANFD3_TX),
	1082	+ PINMUX_IPSR_GPSR(IP0SR3_31_28, PWM2),
	1083	+
	1084	+ /* IP1SR3 */
	1085	+ PINMUX_IPSR_GPSR(IP1SR3_3_0, CANFD3_RX),
	1086	+ PINMUX_IPSR_GPSR(IP1SR3_3_0, PWM3),
	1087	+
	1088	+ PINMUX_IPSR_GPSR(IP1SR3_7_4, CANFD4_TX),
	1089	+ PINMUX_IPSR_GPSR(IP1SR3_7_4, PWM4),
	1090	+ PINMUX_IPSR_GPSR(IP1SR3_7_4, FXR_CLKOUT1),
	1091	+
	1092	+ PINMUX_IPSR_GPSR(IP1SR3_11_8, CANFD4_RX),
	1093	+ PINMUX_IPSR_GPSR(IP1SR3_11_8, FXR_CLKOUT2),
	1094	+
	1095	+ PINMUX_IPSR_GPSR(IP1SR3_15_12, CANFD5_TX),
	1096	+ PINMUX_IPSR_GPSR(IP1SR3_15_12, FXR_TXENA_N),
	1097	+
	1098	+ PINMUX_IPSR_GPSR(IP1SR3_19_16, CANFD5_RX),
	1099	+ PINMUX_IPSR_GPSR(IP1SR3_19_16, FXR_TXENB_N),
	1100	+
	1101	+ PINMUX_IPSR_GPSR(IP1SR3_23_20, CANFD6_TX),
	1102	+ PINMUX_IPSR_GPSR(IP1SR3_23_20, STPWT_EXTFXR),
	1103	+
	1104	+ /* IP0SR4 */
	1105	+ PINMUX_IPSR_GPSR(IP0SR4_3_0, AVB0_RX_CTL),
	1106	+ PINMUX_IPSR_GPSR(IP0SR4_3_0, AVB0_MII_RX_DV),
	1107	+
	1108	+ PINMUX_IPSR_GPSR(IP0SR4_7_4, AVB0_RXC),
	1109	+ PINMUX_IPSR_GPSR(IP0SR4_7_4, AVB0_MII_RXC),
	1110	+
	1111	+ PINMUX_IPSR_GPSR(IP0SR4_11_8, AVB0_RD0),
	1112	+ PINMUX_IPSR_GPSR(IP0SR4_11_8, AVB0_MII_RD0),
	1113	+
	1114	+ PINMUX_IPSR_GPSR(IP0SR4_15_12, AVB0_RD1),
	1115	+ PINMUX_IPSR_GPSR(IP0SR4_15_12, AVB0_MII_RD1),
	1116	+
	1117	+ PINMUX_IPSR_GPSR(IP0SR4_19_16, AVB0_RD2),
	1118	+ PINMUX_IPSR_GPSR(IP0SR4_19_16, AVB0_MII_RD2),
	1119	+
	1120	+ PINMUX_IPSR_GPSR(IP0SR4_23_20, AVB0_RD3),
	1121	+ PINMUX_IPSR_GPSR(IP0SR4_23_20, AVB0_MII_RD3),
	1122	+
	1123	+ PINMUX_IPSR_GPSR(IP0SR4_27_24, AVB0_TX_CTL),
	1124	+ PINMUX_IPSR_GPSR(IP0SR4_27_24, AVB0_MII_TX_EN),
	1125	+
	1126	+ PINMUX_IPSR_GPSR(IP0SR4_31_28, AVB0_TXC),
	1127	+ PINMUX_IPSR_GPSR(IP0SR4_31_28, AVB0_MII_TXC),
	1128	+
	1129	+ /* IP1SR4 */
	1130	+ PINMUX_IPSR_GPSR(IP1SR4_3_0, AVB0_TD0),
	1131	+ PINMUX_IPSR_GPSR(IP1SR4_3_0, AVB0_MII_TD0),
	1132	+
	1133	+ PINMUX_IPSR_GPSR(IP1SR4_7_4, AVB0_TD1),
	1134	+ PINMUX_IPSR_GPSR(IP1SR4_7_4, AVB0_MII_TD1),
	1135	+
	1136	+ PINMUX_IPSR_GPSR(IP1SR4_11_8, AVB0_TD2),
	1137	+ PINMUX_IPSR_GPSR(IP1SR4_11_8, AVB0_MII_TD2),
	1138	+
	1139	+ PINMUX_IPSR_GPSR(IP1SR4_15_12, AVB0_TD3),
	1140	+ PINMUX_IPSR_GPSR(IP1SR4_15_12, AVB0_MII_TD3),
	1141	+
	1142	+ PINMUX_IPSR_GPSR(IP1SR4_19_16, AVB0_TXCREFCLK),
	1143	+
	1144	+ PINMUX_IPSR_GPSR(IP1SR4_23_20, AVB0_MDIO),
	1145	+
	1146	+ PINMUX_IPSR_GPSR(IP1SR4_27_24, AVB0_MDC),
	1147	+
	1148	+ PINMUX_IPSR_GPSR(IP1SR4_31_28, AVB0_MAGIC),
	1149	+
	1150	+ /* IP2SR4 */
	1151	+ PINMUX_IPSR_GPSR(IP2SR4_7_4, AVB0_LINK),
	1152	+ PINMUX_IPSR_GPSR(IP2SR4_7_4, AVB0_MII_TX_ER),
	1153	+
	1154	+ PINMUX_IPSR_GPSR(IP2SR4_11_8, AVB0_AVTP_MATCH),
	1155	+ PINMUX_IPSR_GPSR(IP2SR4_11_8, AVB0_MII_RX_ER),
	1156	+ PINMUX_IPSR_GPSR(IP2SR4_11_8, CC5_OSCOUT),
	1157	+
	1158	+ PINMUX_IPSR_GPSR(IP2SR4_15_12, AVB0_AVTP_CAPTURE),
	1159	+ PINMUX_IPSR_GPSR(IP2SR4_15_12, AVB0_MII_CRS),
	1160	+
	1161	+ PINMUX_IPSR_GPSR(IP2SR4_19_16, AVB0_AVTP_PPS),
	1162	+ PINMUX_IPSR_GPSR(IP2SR4_19_16, AVB0_MII_COL),
	1163	+
	1164	+ /* IP0SR5 */
	1165	+ PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB1_RX_CTL),
	1166	+ PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB1_MII_RX_DV),
	1167	+
	1168	+ PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB1_RXC),
	1169	+ PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB1_MII_RXC),
	1170	+
	1171	+ PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB1_RD0),
	1172	+ PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB1_MII_RD0),
	1173	+
	1174	+ PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB1_RD1),
	1175	+ PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB1_MII_RD1),
	1176	+
	1177	+ PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB1_RD2),
	1178	+ PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB1_MII_RD2),
	1179	+
	1180	+ PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB1_RD3),
	1181	+ PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB1_MII_RD3),
	1182	+
	1183	+ PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB1_TX_CTL),
	1184	+ PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB1_MII_TX_EN),
	1185	+
	1186	+ PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB1_TXC),
	1187	+ PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB1_MII_TXC),
	1188	+
	1189	+ /* IP1SR5 */
	1190	+ PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB1_TD0),
	1191	+ PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB1_MII_TD0),
	1192	+
	1193	+ PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB1_TD1),
	1194	+ PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB1_MII_TD1),
	1195	+
	1196	+ PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB1_TD2),
	1197	+ PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB1_MII_TD2),
	1198	+
	1199	+ PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB1_TD3),
	1200	+ PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB1_MII_TD3),
	1201	+
	1202	+ PINMUX_IPSR_GPSR(IP1SR5_19_16, AVB1_TXCREFCLK),
	1203	+
	1204	+ PINMUX_IPSR_GPSR(IP1SR5_23_20, AVB1_MDIO),
	1205	+
	1206	+ PINMUX_IPSR_GPSR(IP1SR5_27_24, AVB1_MDC),
	1207	+
	1208	+ PINMUX_IPSR_GPSR(IP1SR5_31_28, AVB1_MAGIC),
	1209	+
	1210	+ /* IP2SR5 */
	1211	+ PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB1_LINK),
	1212	+ PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB1_MII_TX_ER),
	1213	+
	1214	+ PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB1_AVTP_MATCH),
	1215	+ PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB1_MII_RX_ER),
	1216	+
	1217	+ PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB1_AVTP_CAPTURE),
	1218	+ PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB1_MII_CRS),
	1219	+
	1220	+ PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB1_AVTP_PPS),
	1221	+ PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB1_MII_COL),
	1222	+};
	1223	+
	1224	+/*
	1225	+ * Pins not associated with a GPIO port.
	1226	+ */
	1227	+enum {
	1228	+ GP_ASSIGN_LAST(),
	1229	+ NOGP_ALL(),
	1230	+};
	1231	+
	1232	+static const struct sh_pfc_pin pinmux_pins[] = {
	1233	+ PINMUX_GPIO_GP_ALL(),
	1234	+};
	1235	+
	1236	+/* - AVB0 ------------------------------------------------ */
	1237	+static const unsigned int avb0_link_pins[] = {
	1238	+ /* AVB0_LINK */
	1239	+ RCAR_GP_PIN(4, 17),
	1240	+};
	1241	+static const unsigned int avb0_link_mux[] = {
	1242	+ AVB0_LINK_MARK,
	1243	+};
	1244	+static const unsigned int avb0_magic_pins[] = {
	1245	+ /* AVB0_MAGIC */
	1246	+ RCAR_GP_PIN(4, 15),
	1247	+};
	1248	+static const unsigned int avb0_magic_mux[] = {
	1249	+ AVB0_MAGIC_MARK,
	1250	+};
	1251	+static const unsigned int avb0_phy_int_pins[] = {
	1252	+ /* AVB0_PHY_INT */
	1253	+ RCAR_GP_PIN(4, 16),
	1254	+};
	1255	+static const unsigned int avb0_phy_int_mux[] = {
	1256	+ AVB0_PHY_INT_MARK,
	1257	+};
	1258	+static const unsigned int avb0_mdio_pins[] = {
	1259	+ /* AVB0_MDC, AVB0_MDIO */
	1260	+ RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
	1261	+};
	1262	+static const unsigned int avb0_mdio_mux[] = {
	1263	+ AVB0_MDC_MARK, AVB0_MDIO_MARK,
	1264	+};
	1265	+static const unsigned int avb0_rgmii_pins[] = {
	1266	+ /*
	1267	+ * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
	1268	+ * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3,
	1269	+ */
	1270	+ RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
	1271	+ RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
	1272	+ RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
	1273	+ RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
	1274	+ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
	1275	+ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
	1276	+};
	1277	+static const unsigned int avb0_rgmii_mux[] = {
	1278	+ AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
	1279	+ AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
	1280	+ AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
	1281	+ AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
	1282	+};
	1283	+static const unsigned int avb0_txcrefclk_pins[] = {
	1284	+ /* AVB0_TXCREFCLK */
	1285	+ RCAR_GP_PIN(4, 12),
	1286	+};
	1287	+static const unsigned int avb0_txcrefclk_mux[] = {
	1288	+ AVB0_TXCREFCLK_MARK,
	1289	+};
	1290	+static const unsigned int avb0_avtp_pps_pins[] = {
	1291	+ /* AVB0_AVTP_PPS */
	1292	+ RCAR_GP_PIN(4, 20),
	1293	+};
	1294	+static const unsigned int avb0_avtp_pps_mux[] = {
	1295	+ AVB0_AVTP_PPS_MARK,
	1296	+};
	1297	+static const unsigned int avb0_avtp_capture_pins[] = {
	1298	+ /* AVB0_AVTP_CAPTURE */
	1299	+ RCAR_GP_PIN(4, 19),
	1300	+};
	1301	+static const unsigned int avb0_avtp_capture_mux[] = {
	1302	+ AVB0_AVTP_CAPTURE_MARK,
	1303	+};
	1304	+static const unsigned int avb0_avtp_match_pins[] = {
	1305	+ /* AVB0_AVTP_MATCH */
	1306	+ RCAR_GP_PIN(4, 18),
	1307	+};
	1308	+static const unsigned int avb0_avtp_match_mux[] = {
	1309	+ AVB0_AVTP_MATCH_MARK,
	1310	+};
	1311	+
	1312	+/* - AVB1 ------------------------------------------------ */
	1313	+static const unsigned int avb1_link_pins[] = {
	1314	+ /* AVB1_LINK */
	1315	+ RCAR_GP_PIN(5, 17),
	1316	+};
	1317	+static const unsigned int avb1_link_mux[] = {
	1318	+ AVB1_LINK_MARK,
	1319	+};
	1320	+static const unsigned int avb1_magic_pins[] = {
	1321	+ /* AVB1_MAGIC */
	1322	+ RCAR_GP_PIN(5, 15),
	1323	+};
	1324	+static const unsigned int avb1_magic_mux[] = {
	1325	+ AVB1_MAGIC_MARK,
	1326	+};
	1327	+static const unsigned int avb1_phy_int_pins[] = {
	1328	+ /* AVB1_PHY_INT */
	1329	+ RCAR_GP_PIN(5, 16),
	1330	+};
	1331	+static const unsigned int avb1_phy_int_mux[] = {
	1332	+ AVB1_PHY_INT_MARK,
	1333	+};
	1334	+static const unsigned int avb1_mdio_pins[] = {
	1335	+ /* AVB1_MDC, AVB1_MDIO */
	1336	+ RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 13),
	1337	+};
	1338	+static const unsigned int avb1_mdio_mux[] = {
	1339	+ AVB1_MDC_MARK, AVB1_MDIO_MARK,
	1340	+};
	1341	+static const unsigned int avb1_rgmii_pins[] = {
	1342	+ /*
	1343	+ * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,
	1344	+ * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3,
	1345	+ */
	1346	+ RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
	1347	+ RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
	1348	+ RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
	1349	+ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
	1350	+ RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),
	1351	+ RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
	1352	+};
	1353	+static const unsigned int avb1_rgmii_mux[] = {
	1354	+ AVB1_TX_CTL_MARK, AVB1_TXC_MARK,
	1355	+ AVB1_TD0_MARK, AVB1_TD1_MARK, AVB1_TD2_MARK, AVB1_TD3_MARK,
	1356	+ AVB1_RX_CTL_MARK, AVB1_RXC_MARK,
	1357	+ AVB1_RD0_MARK, AVB1_RD1_MARK, AVB1_RD2_MARK, AVB1_RD3_MARK,
	1358	+};
	1359	+static const unsigned int avb1_txcrefclk_pins[] = {
	1360	+ /* AVB1_TXCREFCLK */
	1361	+ RCAR_GP_PIN(5, 12),
	1362	+};
	1363	+static const unsigned int avb1_txcrefclk_mux[] = {
	1364	+ AVB1_TXCREFCLK_MARK,
	1365	+};
	1366	+static const unsigned int avb1_avtp_pps_pins[] = {
	1367	+ /* AVB1_AVTP_PPS */
	1368	+ RCAR_GP_PIN(5, 20),
	1369	+};
	1370	+static const unsigned int avb1_avtp_pps_mux[] = {
	1371	+ AVB1_AVTP_PPS_MARK,
	1372	+};
	1373	+static const unsigned int avb1_avtp_capture_pins[] = {
	1374	+ /* AVB1_AVTP_CAPTURE */
	1375	+ RCAR_GP_PIN(5, 19),
	1376	+};
	1377	+static const unsigned int avb1_avtp_capture_mux[] = {
	1378	+ AVB1_AVTP_CAPTURE_MARK,
	1379	+};
	1380	+static const unsigned int avb1_avtp_match_pins[] = {
	1381	+ /* AVB1_AVTP_MATCH */
	1382	+ RCAR_GP_PIN(5, 18),
	1383	+};
	1384	+static const unsigned int avb1_avtp_match_mux[] = {
	1385	+ AVB1_AVTP_MATCH_MARK,
	1386	+};
	1387	+
	1388	+/* - AVB2 ------------------------------------------------ */
	1389	+static const unsigned int avb2_link_pins[] = {
	1390	+ /* AVB2_LINK */
	1391	+ RCAR_GP_PIN(6, 17),
	1392	+};
	1393	+static const unsigned int avb2_link_mux[] = {
	1394	+ AVB2_LINK_MARK,
	1395	+};
	1396	+static const unsigned int avb2_magic_pins[] = {
	1397	+ /* AVB2_MAGIC */
	1398	+ RCAR_GP_PIN(6, 15),
	1399	+};
	1400	+static const unsigned int avb2_magic_mux[] = {
	1401	+ AVB2_MAGIC_MARK,
	1402	+};
	1403	+static const unsigned int avb2_phy_int_pins[] = {
	1404	+ /* AVB2_PHY_INT */
	1405	+ RCAR_GP_PIN(6, 16),
	1406	+};
	1407	+static const unsigned int avb2_phy_int_mux[] = {
	1408	+ AVB2_PHY_INT_MARK,
	1409	+};
	1410	+static const unsigned int avb2_mdio_pins[] = {
	1411	+ /* AVB2_MDC, AVB2_MDIO */
	1412	+ RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 13),
	1413	+};
	1414	+static const unsigned int avb2_mdio_mux[] = {
	1415	+ AVB2_MDC_MARK, AVB2_MDIO_MARK,
	1416	+};
	1417	+static const unsigned int avb2_rgmii_pins[] = {
	1418	+ /*
	1419	+ * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3,
	1420	+ * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3,
	1421	+ */
	1422	+ RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
	1423	+ RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
	1424	+ RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
	1425	+ RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
	1426	+ RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
	1427	+ RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
	1428	+};
	1429	+static const unsigned int avb2_rgmii_mux[] = {
	1430	+ AVB2_TX_CTL_MARK, AVB2_TXC_MARK,
	1431	+ AVB2_TD0_MARK, AVB2_TD1_MARK, AVB2_TD2_MARK, AVB2_TD3_MARK,
	1432	+ AVB2_RX_CTL_MARK, AVB2_RXC_MARK,
	1433	+ AVB2_RD0_MARK, AVB2_RD1_MARK, AVB2_RD2_MARK, AVB2_RD3_MARK,
	1434	+};
	1435	+static const unsigned int avb2_txcrefclk_pins[] = {
	1436	+ /* AVB2_TXCREFCLK */
	1437	+ RCAR_GP_PIN(6, 12),
	1438	+};
	1439	+static const unsigned int avb2_txcrefclk_mux[] = {
	1440	+ AVB2_TXCREFCLK_MARK,
	1441	+};
	1442	+static const unsigned int avb2_avtp_pps_pins[] = {
	1443	+ /* AVB2_AVTP_PPS */
	1444	+ RCAR_GP_PIN(6, 20),
	1445	+};
	1446	+static const unsigned int avb2_avtp_pps_mux[] = {
	1447	+ AVB2_AVTP_PPS_MARK,
	1448	+};
	1449	+static const unsigned int avb2_avtp_capture_pins[] = {
	1450	+ /* AVB2_AVTP_CAPTURE */
	1451	+ RCAR_GP_PIN(6, 19),
	1452	+};
	1453	+static const unsigned int avb2_avtp_capture_mux[] = {
	1454	+ AVB2_AVTP_CAPTURE_MARK,
	1455	+};
	1456	+static const unsigned int avb2_avtp_match_pins[] = {
	1457	+ /* AVB2_AVTP_MATCH */
	1458	+ RCAR_GP_PIN(6, 18),
	1459	+};
	1460	+static const unsigned int avb2_avtp_match_mux[] = {
	1461	+ AVB2_AVTP_MATCH_MARK,
	1462	+};
	1463	+
	1464	+/* - AVB3 ------------------------------------------------ */
	1465	+static const unsigned int avb3_link_pins[] = {
	1466	+ /* AVB3_LINK */
	1467	+ RCAR_GP_PIN(7, 17),
	1468	+};
	1469	+static const unsigned int avb3_link_mux[] = {
	1470	+ AVB3_LINK_MARK,
	1471	+};
	1472	+static const unsigned int avb3_magic_pins[] = {
	1473	+ /* AVB3_MAGIC */
	1474	+ RCAR_GP_PIN(7, 15),
	1475	+};
	1476	+static const unsigned int avb3_magic_mux[] = {
	1477	+ AVB3_MAGIC_MARK,
	1478	+};
	1479	+static const unsigned int avb3_phy_int_pins[] = {
	1480	+ /* AVB3_PHY_INT */
	1481	+ RCAR_GP_PIN(7, 16),
	1482	+};
	1483	+static const unsigned int avb3_phy_int_mux[] = {
	1484	+ AVB3_PHY_INT_MARK,
	1485	+};
	1486	+static const unsigned int avb3_mdio_pins[] = {
	1487	+ /* AVB3_MDC, AVB3_MDIO */
	1488	+ RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 13),
	1489	+};
	1490	+static const unsigned int avb3_mdio_mux[] = {
	1491	+ AVB3_MDC_MARK, AVB3_MDIO_MARK,
	1492	+};
	1493	+static const unsigned int avb3_rgmii_pins[] = {
	1494	+ /*
	1495	+ * AVB3_TX_CTL, AVB3_TXC, AVB3_TD0, AVB3_TD1, AVB3_TD2, AVB3_TD3,
	1496	+ * AVB3_RX_CTL, AVB3_RXC, AVB3_RD0, AVB3_RD1, AVB3_RD2, AVB3_RD3,
	1497	+ */
	1498	+ RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
	1499	+ RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
	1500	+ RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
	1501	+ RCAR_GP_PIN(7, 0), RCAR_GP_PIN(7, 1),
	1502	+ RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
	1503	+ RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
	1504	+};
	1505	+static const unsigned int avb3_rgmii_mux[] = {
	1506	+ AVB3_TX_CTL_MARK, AVB3_TXC_MARK,
	1507	+ AVB3_TD0_MARK, AVB3_TD1_MARK, AVB3_TD2_MARK, AVB3_TD3_MARK,
	1508	+ AVB3_RX_CTL_MARK, AVB3_RXC_MARK,
	1509	+ AVB3_RD0_MARK, AVB3_RD1_MARK, AVB3_RD2_MARK, AVB3_RD3_MARK,
	1510	+};
	1511	+static const unsigned int avb3_txcrefclk_pins[] = {
	1512	+ /* AVB3_TXCREFCLK */
	1513	+ RCAR_GP_PIN(7, 12),
	1514	+};
	1515	+static const unsigned int avb3_txcrefclk_mux[] = {
	1516	+ AVB3_TXCREFCLK_MARK,
	1517	+};
	1518	+static const unsigned int avb3_avtp_pps_pins[] = {
	1519	+ /* AVB3_AVTP_PPS */
	1520	+ RCAR_GP_PIN(7, 20),
	1521	+};
	1522	+static const unsigned int avb3_avtp_pps_mux[] = {
	1523	+ AVB3_AVTP_PPS_MARK,
	1524	+};
	1525	+static const unsigned int avb3_avtp_capture_pins[] = {
	1526	+ /* AVB3_AVTP_CAPTURE */
	1527	+ RCAR_GP_PIN(7, 19),
	1528	+};
	1529	+static const unsigned int avb3_avtp_capture_mux[] = {
	1530	+ AVB3_AVTP_CAPTURE_MARK,
	1531	+};
	1532	+static const unsigned int avb3_avtp_match_pins[] = {
	1533	+ /* AVB3_AVTP_MATCH */
	1534	+ RCAR_GP_PIN(7, 18),
	1535	+};
	1536	+static const unsigned int avb3_avtp_match_mux[] = {
	1537	+ AVB3_AVTP_MATCH_MARK,
	1538	+};
	1539	+
	1540	+/* - AVB4 ------------------------------------------------ */
	1541	+static const unsigned int avb4_link_pins[] = {
	1542	+ /* AVB4_LINK */
	1543	+ RCAR_GP_PIN(8, 17),
	1544	+};
	1545	+static const unsigned int avb4_link_mux[] = {
	1546	+ AVB4_LINK_MARK,
	1547	+};
	1548	+static const unsigned int avb4_magic_pins[] = {
	1549	+ /* AVB4_MAGIC */
	1550	+ RCAR_GP_PIN(8, 15),
	1551	+};
	1552	+static const unsigned int avb4_magic_mux[] = {
	1553	+ AVB4_MAGIC_MARK,
	1554	+};
	1555	+static const unsigned int avb4_phy_int_pins[] = {
	1556	+ /* AVB4_PHY_INT */
	1557	+ RCAR_GP_PIN(8, 16),
	1558	+};
	1559	+static const unsigned int avb4_phy_int_mux[] = {
	1560	+ AVB4_PHY_INT_MARK,
	1561	+};
	1562	+static const unsigned int avb4_mdio_pins[] = {
	1563	+ /* AVB4_MDC, AVB4_MDIO */
	1564	+ RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 13),
	1565	+};
	1566	+static const unsigned int avb4_mdio_mux[] = {
	1567	+ AVB4_MDC_MARK, AVB4_MDIO_MARK,
	1568	+};
	1569	+static const unsigned int avb4_rgmii_pins[] = {
	1570	+ /*
	1571	+ * AVB4_TX_CTL, AVB4_TXC, AVB4_TD0, AVB4_TD1, AVB4_TD2, AVB4_TD3,
	1572	+ * AVB4_RX_CTL, AVB4_RXC, AVB4_RD0, AVB4_RD1, AVB4_RD2, AVB4_RD3,
	1573	+ */
	1574	+ RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
	1575	+ RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
	1576	+ RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
	1577	+ RCAR_GP_PIN(8, 0), RCAR_GP_PIN(8, 1),
	1578	+ RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),
	1579	+ RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
	1580	+};
	1581	+static const unsigned int avb4_rgmii_mux[] = {
	1582	+ AVB4_TX_CTL_MARK, AVB4_TXC_MARK,
	1583	+ AVB4_TD0_MARK, AVB4_TD1_MARK, AVB4_TD2_MARK, AVB4_TD3_MARK,
	1584	+ AVB4_RX_CTL_MARK, AVB4_RXC_MARK,
	1585	+ AVB4_RD0_MARK, AVB4_RD1_MARK, AVB4_RD2_MARK, AVB4_RD3_MARK,
	1586	+};
	1587	+static const unsigned int avb4_txcrefclk_pins[] = {
	1588	+ /* AVB4_TXCREFCLK */
	1589	+ RCAR_GP_PIN(8, 12),
	1590	+};
	1591	+static const unsigned int avb4_txcrefclk_mux[] = {
	1592	+ AVB4_TXCREFCLK_MARK,
	1593	+};
	1594	+static const unsigned int avb4_avtp_pps_pins[] = {
	1595	+ /* AVB4_AVTP_PPS */
	1596	+ RCAR_GP_PIN(8, 20),
	1597	+};
	1598	+static const unsigned int avb4_avtp_pps_mux[] = {
	1599	+ AVB4_AVTP_PPS_MARK,
	1600	+};
	1601	+static const unsigned int avb4_avtp_capture_pins[] = {
	1602	+ /* AVB4_AVTP_CAPTURE */
	1603	+ RCAR_GP_PIN(8, 19),
	1604	+};
	1605	+static const unsigned int avb4_avtp_capture_mux[] = {
	1606	+ AVB4_AVTP_CAPTURE_MARK,
	1607	+};
	1608	+static const unsigned int avb4_avtp_match_pins[] = {
	1609	+ /* AVB4_AVTP_MATCH */
	1610	+ RCAR_GP_PIN(8, 18),
	1611	+};
	1612	+static const unsigned int avb4_avtp_match_mux[] = {
	1613	+ AVB4_AVTP_MATCH_MARK,
	1614	+};
	1615	+
	1616	+/* - AVB5 ------------------------------------------------ */
	1617	+static const unsigned int avb5_link_pins[] = {
	1618	+ /* AVB5_LINK */
	1619	+ RCAR_GP_PIN(9, 17),
	1620	+};
	1621	+static const unsigned int avb5_link_mux[] = {
	1622	+ AVB5_LINK_MARK,
	1623	+};
	1624	+static const unsigned int avb5_magic_pins[] = {
	1625	+ /* AVB5_MAGIC */
	1626	+ RCAR_GP_PIN(9, 15),
	1627	+};
	1628	+static const unsigned int avb5_magic_mux[] = {
	1629	+ AVB5_MAGIC_MARK,
	1630	+};
	1631	+static const unsigned int avb5_phy_int_pins[] = {
	1632	+ /* AVB5_PHY_INT */
	1633	+ RCAR_GP_PIN(9, 16),
	1634	+};
	1635	+static const unsigned int avb5_phy_int_mux[] = {
	1636	+ AVB5_PHY_INT_MARK,
	1637	+};
	1638	+static const unsigned int avb5_mdio_pins[] = {
	1639	+ /* AVB5_MDC, AVB5_MDIO */
	1640	+ RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 13),
	1641	+};
	1642	+static const unsigned int avb5_mdio_mux[] = {
	1643	+ AVB5_MDC_MARK, AVB5_MDIO_MARK,
	1644	+};
	1645	+static const unsigned int avb5_rgmii_pins[] = {
	1646	+ /*
	1647	+ * AVB5_TX_CTL, AVB5_TXC, AVB5_TD0, AVB5_TD1, AVB5_TD2, AVB5_TD3,
	1648	+ * AVB5_RX_CTL, AVB5_RXC, AVB5_RD0, AVB5_RD1, AVB5_RD2, AVB5_RD3,
	1649	+ */
	1650	+ RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
	1651	+ RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
	1652	+ RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
	1653	+ RCAR_GP_PIN(9, 0), RCAR_GP_PIN(9, 1),
	1654	+ RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
	1655	+ RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
	1656	+};
	1657	+static const unsigned int avb5_rgmii_mux[] = {
	1658	+ AVB5_TX_CTL_MARK, AVB5_TXC_MARK,
	1659	+ AVB5_TD0_MARK, AVB5_TD1_MARK, AVB5_TD2_MARK, AVB5_TD3_MARK,
	1660	+ AVB5_RX_CTL_MARK, AVB5_RXC_MARK,
	1661	+ AVB5_RD0_MARK, AVB5_RD1_MARK, AVB5_RD2_MARK, AVB5_RD3_MARK,
	1662	+};
	1663	+static const unsigned int avb5_txcrefclk_pins[] = {
	1664	+ /* AVB5_TXCREFCLK */
	1665	+ RCAR_GP_PIN(9, 12),
	1666	+};
	1667	+static const unsigned int avb5_txcrefclk_mux[] = {
	1668	+ AVB5_TXCREFCLK_MARK,
	1669	+};
	1670	+static const unsigned int avb5_avtp_pps_pins[] = {
	1671	+ /* AVB5_AVTP_PPS */
	1672	+ RCAR_GP_PIN(9, 20),
	1673	+};
	1674	+static const unsigned int avb5_avtp_pps_mux[] = {
	1675	+ AVB5_AVTP_PPS_MARK,
	1676	+};
	1677	+static const unsigned int avb5_avtp_capture_pins[] = {
	1678	+ /* AVB5_AVTP_CAPTURE */
	1679	+ RCAR_GP_PIN(9, 19),
	1680	+};
	1681	+static const unsigned int avb5_avtp_capture_mux[] = {
	1682	+ AVB5_AVTP_CAPTURE_MARK,
	1683	+};
	1684	+static const unsigned int avb5_avtp_match_pins[] = {
	1685	+ /* AVB5_AVTP_MATCH */
	1686	+ RCAR_GP_PIN(9, 18),
	1687	+};
	1688	+static const unsigned int avb5_avtp_match_mux[] = {
	1689	+ AVB5_AVTP_MATCH_MARK,
	1690	+};
	1691	+
	1692	+/* - CANFD0 ----------------------------------------------------------------- */
	1693	+static const unsigned int canfd0_data_pins[] = {
	1694	+ /* CANFD0_TX, CANFD0_RX */
	1695	+ RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
	1696	+};
	1697	+static const unsigned int canfd0_data_mux[] = {
	1698	+ CANFD0_TX_MARK, CANFD0_RX_MARK,
	1699	+};
	1700	+
	1701	+/* - CANFD1 ----------------------------------------------------------------- */
	1702	+static const unsigned int canfd1_data_pins[] = {
	1703	+ /* CANFD1_TX, CANFD1_RX */
	1704	+ RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
	1705	+};
	1706	+static const unsigned int canfd1_data_mux[] = {
	1707	+ CANFD1_TX_MARK, CANFD1_RX_MARK,
	1708	+};
	1709	+
	1710	+/* - CANFD2 ----------------------------------------------------------------- */
	1711	+static const unsigned int canfd2_data_pins[] = {
	1712	+ /* CANFD2_TX, CANFD2_RX */
	1713	+ RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
	1714	+};
	1715	+static const unsigned int canfd2_data_mux[] = {
	1716	+ CANFD2_TX_MARK, CANFD2_RX_MARK,
	1717	+};
	1718	+
	1719	+/* - CANFD3 ----------------------------------------------------------------- */
	1720	+static const unsigned int canfd3_data_pins[] = {
	1721	+ /* CANFD3_TX, CANFD3_RX */
	1722	+ RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
	1723	+};
	1724	+static const unsigned int canfd3_data_mux[] = {
	1725	+ CANFD3_TX_MARK, CANFD3_RX_MARK,
	1726	+};
	1727	+
	1728	+/* - CANFD4 ----------------------------------------------------------------- */
	1729	+static const unsigned int canfd4_data_pins[] = {
	1730	+ /* CANFD4_TX, CANFD4_RX */
	1731	+ RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
	1732	+};
	1733	+static const unsigned int canfd4_data_mux[] = {
	1734	+ CANFD4_TX_MARK, CANFD4_RX_MARK,
	1735	+};
	1736	+
	1737	+/* - CANFD5 ----------------------------------------------------------------- */
	1738	+static const unsigned int canfd5_data_pins[] = {
	1739	+ /* CANFD5_TX, CANFD5_RX */
	1740	+ RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
	1741	+};
	1742	+static const unsigned int canfd5_data_mux[] = {
	1743	+ CANFD5_TX_MARK, CANFD5_RX_MARK,
	1744	+};
	1745	+
	1746	+/* - CANFD6 ----------------------------------------------------------------- */
	1747	+static const unsigned int canfd6_data_pins[] = {
	1748	+ /* CANFD6_TX, CANFD6_RX */
	1749	+ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
	1750	+};
	1751	+static const unsigned int canfd6_data_mux[] = {
	1752	+ CANFD6_TX_MARK, CANFD6_RX_MARK,
	1753	+};
	1754	+
	1755	+/* - CANFD7 ----------------------------------------------------------------- */
	1756	+static const unsigned int canfd7_data_pins[] = {
	1757	+ /* CANFD7_TX, CANFD7_RX */
	1758	+ RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
	1759	+};
	1760	+static const unsigned int canfd7_data_mux[] = {
	1761	+ CANFD7_TX_MARK, CANFD7_RX_MARK,
	1762	+};
	1763	+
	1764	+/* - CANFD Clock ------------------------------------------------------------ */
	1765	+static const unsigned int can_clk_pins[] = {
	1766	+ /* CAN_CLK */
	1767	+ RCAR_GP_PIN(3, 0),
	1768	+};
	1769	+static const unsigned int can_clk_mux[] = {
	1770	+ CAN_CLK_MARK,
	1771	+};
	1772	+
	1773	+/* - DU --------------------------------------------------------------------- */
	1774	+static const unsigned int du_rgb888_pins[] = {
	1775	+ /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
	1776	+ RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
	1777	+ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
	1778	+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
	1779	+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
	1780	+ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
	1781	+ RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
	1782	+};
	1783	+static const unsigned int du_rgb888_mux[] = {
	1784	+ DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
	1785	+ DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
	1786	+ DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
	1787	+ DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
	1788	+ DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
	1789	+ DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
	1790	+};
	1791	+static const unsigned int du_clk_out_pins[] = {
	1792	+ /* DU_DOTCLKOUT */
	1793	+ RCAR_GP_PIN(1, 24),
	1794	+};
	1795	+static const unsigned int du_clk_out_mux[] = {
	1796	+ DU_DOTCLKOUT_MARK,
	1797	+};
	1798	+static const unsigned int du_sync_pins[] = {
	1799	+ /* DU_HSYNC, DU_VSYNC */
	1800	+ RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 26),
	1801	+};
	1802	+static const unsigned int du_sync_mux[] = {
	1803	+ DU_HSYNC_MARK, DU_VSYNC_MARK,
	1804	+};
	1805	+static const unsigned int du_oddf_pins[] = {
	1806	+ /* DU_EXODDF/DU_ODDF/DISP/CDE */
	1807	+ RCAR_GP_PIN(1, 27),
	1808	+};
	1809	+static const unsigned int du_oddf_mux[] = {
	1810	+ DU_ODDF_DISP_CDE_MARK,
	1811	+};
	1812	+
	1813	+/* - HSCIF0 ----------------------------------------------------------------- */
	1814	+static const unsigned int hscif0_data_pins[] = {
	1815	+ /* HRX0, HTX0 */
	1816	+ RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5),
	1817	+};
	1818	+static const unsigned int hscif0_data_mux[] = {
	1819	+ HRX0_MARK, HTX0_MARK,
	1820	+};
	1821	+static const unsigned int hscif0_clk_pins[] = {
	1822	+ /* HSCK0 */
	1823	+ RCAR_GP_PIN(1, 2),
	1824	+};
	1825	+static const unsigned int hscif0_clk_mux[] = {
	1826	+ HSCK0_MARK,
	1827	+};
	1828	+static const unsigned int hscif0_ctrl_pins[] = {
	1829	+ /* HRTS0#, HCTS0# */
	1830	+ RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
	1831	+};
	1832	+static const unsigned int hscif0_ctrl_mux[] = {
	1833	+ HRTS0_N_MARK, HCTS0_N_MARK,
	1834	+};
	1835	+
	1836	+/* - HSCIF1 ----------------------------------------------------------------- */
	1837	+static const unsigned int hscif1_data_pins[] = {
	1838	+ /* HRX1, HTX1 */
	1839	+ RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
	1840	+};
	1841	+static const unsigned int hscif1_data_mux[] = {
	1842	+ HRX1_MARK, HTX1_MARK,
	1843	+};
	1844	+static const unsigned int hscif1_clk_pins[] = {
	1845	+ /* HSCK1 */
	1846	+ RCAR_GP_PIN(1, 18),
	1847	+};
	1848	+static const unsigned int hscif1_clk_mux[] = {
	1849	+ HSCK1_MARK,
	1850	+};
	1851	+static const unsigned int hscif1_ctrl_pins[] = {
	1852	+ /* HRTS1#, HCTS1# */
	1853	+ RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19),
	1854	+};
	1855	+static const unsigned int hscif1_ctrl_mux[] = {
	1856	+ HRTS1_N_MARK, HCTS1_N_MARK,
	1857	+};
	1858	+
	1859	+/* - HSCIF2 ----------------------------------------------------------------- */
	1860	+static const unsigned int hscif2_data_pins[] = {
	1861	+ /* HRX2, HTX2 */
	1862	+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
	1863	+};
	1864	+static const unsigned int hscif2_data_mux[] = {
	1865	+ HRX2_MARK, HTX2_MARK,
	1866	+};
	1867	+static const unsigned int hscif2_clk_pins[] = {
	1868	+ /* HSCK2 */
	1869	+ RCAR_GP_PIN(2, 5),
	1870	+};
	1871	+static const unsigned int hscif2_clk_mux[] = {
	1872	+ HSCK2_MARK,
	1873	+};
	1874	+static const unsigned int hscif2_ctrl_pins[] = {
	1875	+ /* HRTS2#, HCTS2# */
	1876	+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6),
	1877	+};
	1878	+static const unsigned int hscif2_ctrl_mux[] = {
	1879	+ HRTS2_N_MARK, HCTS2_N_MARK,
	1880	+};
	1881	+
	1882	+/* - HSCIF3 ----------------------------------------------------------------- */
	1883	+static const unsigned int hscif3_data_pins[] = {
	1884	+ /* HRX3, HTX3 */
	1885	+ RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 17),
	1886	+};
	1887	+static const unsigned int hscif3_data_mux[] = {
	1888	+ HRX3_MARK, HTX3_MARK,
	1889	+};
	1890	+static const unsigned int hscif3_clk_pins[] = {
	1891	+ /* HSCK3 */
	1892	+ RCAR_GP_PIN(1, 14),
	1893	+};
	1894	+static const unsigned int hscif3_clk_mux[] = {
	1895	+ HSCK3_MARK,
	1896	+};
	1897	+static const unsigned int hscif3_ctrl_pins[] = {
	1898	+ /* HRTS3#, HCTS3# */
	1899	+ RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
	1900	+};
	1901	+static const unsigned int hscif3_ctrl_mux[] = {
	1902	+ HRTS3_N_MARK, HCTS3_N_MARK,
	1903	+};
	1904	+
	1905	+/* - I2C0 ------------------------------------------------------------------- */
	1906	+static const unsigned int i2c0_pins[] = {
	1907	+ /* SDA0, SCL0 */
	1908	+ RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
	1909	+};
	1910	+static const unsigned int i2c0_mux[] = {
	1911	+ SDA0_MARK, SCL0_MARK,
	1912	+};
	1913	+
	1914	+/* - I2C1 ------------------------------------------------------------------- */
	1915	+static const unsigned int i2c1_pins[] = {
	1916	+ /* SDA1, SCL1 */
	1917	+ RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
	1918	+};
	1919	+static const unsigned int i2c1_mux[] = {
	1920	+ SDA1_MARK, SCL1_MARK,
	1921	+};
	1922	+
	1923	+/* - I2C2 ------------------------------------------------------------------- */
	1924	+static const unsigned int i2c2_pins[] = {
	1925	+ /* SDA2, SCL2 */
	1926	+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6),
	1927	+};
	1928	+static const unsigned int i2c2_mux[] = {
	1929	+ SDA2_MARK, SCL2_MARK,
	1930	+};
	1931	+
	1932	+/* - I2C3 ------------------------------------------------------------------- */
	1933	+static const unsigned int i2c3_pins[] = {
	1934	+ /* SDA3, SCL3 */
	1935	+ RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8),
	1936	+};
	1937	+static const unsigned int i2c3_mux[] = {
	1938	+ SDA3_MARK, SCL3_MARK,
	1939	+};
	1940	+
	1941	+/* - I2C4 ------------------------------------------------------------------- */
	1942	+static const unsigned int i2c4_pins[] = {
	1943	+ /* SDA4, SCL4 */
	1944	+ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
	1945	+};
	1946	+static const unsigned int i2c4_mux[] = {
	1947	+ SDA4_MARK, SCL4_MARK,
	1948	+};
	1949	+
	1950	+/* - I2C5 ------------------------------------------------------------------- */
	1951	+static const unsigned int i2c5_pins[] = {
	1952	+ /* SDA5, SCL5 */
	1953	+ RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12),
	1954	+};
	1955	+static const unsigned int i2c5_mux[] = {
	1956	+ SDA5_MARK, SCL5_MARK,
	1957	+};
	1958	+
	1959	+/* - I2C6 ------------------------------------------------------------------- */
	1960	+static const unsigned int i2c6_pins[] = {
	1961	+ /* SDA6, SCL6 */
	1962	+ RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14),
	1963	+};
	1964	+static const unsigned int i2c6_mux[] = {
	1965	+ SDA6_MARK, SCL6_MARK,
	1966	+};
	1967	+
	1968	+/* - INTC-EX ---------------------------------------------------------------- */
	1969	+static const unsigned int intc_ex_irq0_pins[] = {
	1970	+ /* IRQ0 */
	1971	+ RCAR_GP_PIN(1, 24),
	1972	+};
	1973	+static const unsigned int intc_ex_irq0_mux[] = {
	1974	+ IRQ0_MARK,
	1975	+};
	1976	+static const unsigned int intc_ex_irq1_pins[] = {
	1977	+ /* IRQ1 */
	1978	+ RCAR_GP_PIN(1, 25),
	1979	+};
	1980	+static const unsigned int intc_ex_irq1_mux[] = {
	1981	+ IRQ1_MARK,
	1982	+};
	1983	+static const unsigned int intc_ex_irq2_pins[] = {
	1984	+ /* IRQ2 */
	1985	+ RCAR_GP_PIN(1, 26),
	1986	+};
	1987	+static const unsigned int intc_ex_irq2_mux[] = {
	1988	+ IRQ2_MARK,
	1989	+};
	1990	+static const unsigned int intc_ex_irq3_pins[] = {
	1991	+ /* IRQ3 */
	1992	+ RCAR_GP_PIN(1, 27),
	1993	+};
	1994	+static const unsigned int intc_ex_irq3_mux[] = {
	1995	+ IRQ3_MARK,
	1996	+};
	1997	+static const unsigned int intc_ex_irq4_pins[] = {
	1998	+ /* IRQ4 */
	1999	+ RCAR_GP_PIN(2, 14),
	2000	+};
	2001	+static const unsigned int intc_ex_irq4_mux[] = {
	2002	+ IRQ4_MARK,
	2003	+};
	2004	+static const unsigned int intc_ex_irq5_pins[] = {
	2005	+ /* IRQ5 */
	2006	+ RCAR_GP_PIN(2, 15),
	2007	+};
	2008	+static const unsigned int intc_ex_irq5_mux[] = {
	2009	+ IRQ5_MARK,
	2010	+};
	2011	+
	2012	+/* - MMC -------------------------------------------------------------------- */
	2013	+static const unsigned int mmc_data1_pins[] = {
	2014	+ /* MMC_SD_D0 */
	2015	+ RCAR_GP_PIN(0, 19),
	2016	+};
	2017	+static const unsigned int mmc_data1_mux[] = {
	2018	+ MMC_SD_D0_MARK,
	2019	+};
	2020	+static const unsigned int mmc_data4_pins[] = {
	2021	+ /* MMC_SD_D[0:3] */
	2022	+ RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
	2023	+ RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
	2024	+};
	2025	+static const unsigned int mmc_data4_mux[] = {
	2026	+ MMC_SD_D0_MARK, MMC_SD_D1_MARK,
	2027	+ MMC_SD_D2_MARK, MMC_SD_D3_MARK,
	2028	+};
	2029	+static const unsigned int mmc_data8_pins[] = {
	2030	+ /* MMC_SD_D[0:3], MMC_D[4:7] */
	2031	+ RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
	2032	+ RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
	2033	+ RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
	2034	+ RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 27),
	2035	+};
	2036	+static const unsigned int mmc_data8_mux[] = {
	2037	+ MMC_SD_D0_MARK, MMC_SD_D1_MARK,
	2038	+ MMC_SD_D2_MARK, MMC_SD_D3_MARK,
	2039	+ MMC_D4_MARK, MMC_D5_MARK,
	2040	+ MMC_D6_MARK, MMC_D7_MARK,
	2041	+};
	2042	+static const unsigned int mmc_ctrl_pins[] = {
	2043	+ /* MMC_SD_CLK, MMC_SD_CMD */
	2044	+ RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 18),
	2045	+};
	2046	+static const unsigned int mmc_ctrl_mux[] = {
	2047	+ MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
	2048	+};
	2049	+static const unsigned int mmc_cd_pins[] = {
	2050	+ /* SD_CD */
	2051	+ RCAR_GP_PIN(0, 16),
	2052	+};
	2053	+static const unsigned int mmc_cd_mux[] = {
	2054	+ SD_CD_MARK,
	2055	+};
	2056	+static const unsigned int mmc_wp_pins[] = {
	2057	+ /* SD_WP */
	2058	+ RCAR_GP_PIN(0, 15),
	2059	+};
	2060	+static const unsigned int mmc_wp_mux[] = {
	2061	+ SD_WP_MARK,
	2062	+};
	2063	+static const unsigned int mmc_ds_pins[] = {
	2064	+ /* MMC_DS */
	2065	+ RCAR_GP_PIN(0, 17),
	2066	+};
	2067	+static const unsigned int mmc_ds_mux[] = {
	2068	+ MMC_DS_MARK,
	2069	+};
	2070	+
	2071	+/* - MSIOF0 ----------------------------------------------------------------- */
	2072	+static const unsigned int msiof0_clk_pins[] = {
	2073	+ /* MSIOF0_SCK */
	2074	+ RCAR_GP_PIN(1, 8),
	2075	+};
	2076	+static const unsigned int msiof0_clk_mux[] = {
	2077	+ MSIOF0_SCK_MARK,
	2078	+};
	2079	+static const unsigned int msiof0_sync_pins[] = {
	2080	+ /* MSIOF0_SYNC */
	2081	+ RCAR_GP_PIN(1, 9),
	2082	+};
	2083	+static const unsigned int msiof0_sync_mux[] = {
	2084	+ MSIOF0_SYNC_MARK,
	2085	+};
	2086	+static const unsigned int msiof0_ss1_pins[] = {
	2087	+ /* MSIOF0_SS1 */
	2088	+ RCAR_GP_PIN(1, 10),
	2089	+};
	2090	+static const unsigned int msiof0_ss1_mux[] = {
	2091	+ MSIOF0_SS1_MARK,
	2092	+};
	2093	+static const unsigned int msiof0_ss2_pins[] = {
	2094	+ /* MSIOF0_SS2 */
	2095	+ RCAR_GP_PIN(1, 11),
	2096	+};
	2097	+static const unsigned int msiof0_ss2_mux[] = {
	2098	+ MSIOF0_SS2_MARK,
	2099	+};
	2100	+static const unsigned int msiof0_txd_pins[] = {
	2101	+ /* MSIOF0_TXD */
	2102	+ RCAR_GP_PIN(1, 7),
	2103	+};
	2104	+static const unsigned int msiof0_txd_mux[] = {
	2105	+ MSIOF0_TXD_MARK,
	2106	+};
	2107	+static const unsigned int msiof0_rxd_pins[] = {
	2108	+ /* MSIOF0_RXD */
	2109	+ RCAR_GP_PIN(1, 6),
	2110	+};
	2111	+static const unsigned int msiof0_rxd_mux[] = {
	2112	+ MSIOF0_RXD_MARK,
	2113	+};
	2114	+
	2115	+/* - MSIOF1 ----------------------------------------------------------------- */
	2116	+static const unsigned int msiof1_clk_pins[] = {
	2117	+ /* MSIOF1_SCK */
	2118	+ RCAR_GP_PIN(1, 14),
	2119	+};
	2120	+static const unsigned int msiof1_clk_mux[] = {
	2121	+ MSIOF1_SCK_MARK,
	2122	+};
	2123	+static const unsigned int msiof1_sync_pins[] = {
	2124	+ /* MSIOF1_SYNC */
	2125	+ RCAR_GP_PIN(1, 15),
	2126	+};
	2127	+static const unsigned int msiof1_sync_mux[] = {
	2128	+ MSIOF1_SYNC_MARK,
	2129	+};
	2130	+static const unsigned int msiof1_ss1_pins[] = {
	2131	+ /* MSIOF1_SS1 */
	2132	+ RCAR_GP_PIN(1, 16),
	2133	+};
	2134	+static const unsigned int msiof1_ss1_mux[] = {
	2135	+ MSIOF1_SS1_MARK,
	2136	+};
	2137	+static const unsigned int msiof1_ss2_pins[] = {
	2138	+ /* MSIOF1_SS2 */
	2139	+ RCAR_GP_PIN(1, 17),
	2140	+};
	2141	+static const unsigned int msiof1_ss2_mux[] = {
	2142	+ MSIOF1_SS2_MARK,
	2143	+};
	2144	+static const unsigned int msiof1_txd_pins[] = {
	2145	+ /* MSIOF1_TXD */
	2146	+ RCAR_GP_PIN(1, 13),
	2147	+};
	2148	+static const unsigned int msiof1_txd_mux[] = {
	2149	+ MSIOF1_TXD_MARK,
	2150	+};
	2151	+static const unsigned int msiof1_rxd_pins[] = {
	2152	+ /* MSIOF1_RXD */
	2153	+ RCAR_GP_PIN(1, 12),
	2154	+};
	2155	+static const unsigned int msiof1_rxd_mux[] = {
	2156	+ MSIOF1_RXD_MARK,
	2157	+};
	2158	+
	2159	+/* - MSIOF2 ----------------------------------------------------------------- */
	2160	+static const unsigned int msiof2_clk_pins[] = {
	2161	+ /* MSIOF2_SCK */
	2162	+ RCAR_GP_PIN(1, 20),
	2163	+};
	2164	+static const unsigned int msiof2_clk_mux[] = {
	2165	+ MSIOF2_SCK_MARK,
	2166	+};
	2167	+static const unsigned int msiof2_sync_pins[] = {
	2168	+ /* MSIOF2_SYNC */
	2169	+ RCAR_GP_PIN(1, 21),
	2170	+};
	2171	+static const unsigned int msiof2_sync_mux[] = {
	2172	+ MSIOF2_SYNC_MARK,
	2173	+};
	2174	+static const unsigned int msiof2_ss1_pins[] = {
	2175	+ /* MSIOF2_SS1 */
	2176	+ RCAR_GP_PIN(1, 22),
	2177	+};
	2178	+static const unsigned int msiof2_ss1_mux[] = {
	2179	+ MSIOF2_SS1_MARK,
	2180	+};
	2181	+static const unsigned int msiof2_ss2_pins[] = {
	2182	+ /* MSIOF2_SS2 */
	2183	+ RCAR_GP_PIN(1, 23),
	2184	+};
	2185	+static const unsigned int msiof2_ss2_mux[] = {
	2186	+ MSIOF2_SS2_MARK,
	2187	+};
	2188	+static const unsigned int msiof2_txd_pins[] = {
	2189	+ /* MSIOF2_TXD */
	2190	+ RCAR_GP_PIN(1, 19),
	2191	+};
	2192	+static const unsigned int msiof2_txd_mux[] = {
	2193	+ MSIOF2_TXD_MARK,
	2194	+};
	2195	+static const unsigned int msiof2_rxd_pins[] = {
	2196	+ /* MSIOF2_RXD */
	2197	+ RCAR_GP_PIN(1, 18),
	2198	+};
	2199	+static const unsigned int msiof2_rxd_mux[] = {
	2200	+ MSIOF2_RXD_MARK,
	2201	+};
	2202	+
	2203	+/* - MSIOF3 ----------------------------------------------------------------- */
	2204	+static const unsigned int msiof3_clk_pins[] = {
	2205	+ /* MSIOF3_SCK */
	2206	+ RCAR_GP_PIN(2, 20),
	2207	+};
	2208	+static const unsigned int msiof3_clk_mux[] = {
	2209	+ MSIOF3_SCK_MARK,
	2210	+};
	2211	+static const unsigned int msiof3_sync_pins[] = {
	2212	+ /* MSIOF3_SYNC */
	2213	+ RCAR_GP_PIN(2, 21),
	2214	+};
	2215	+static const unsigned int msiof3_sync_mux[] = {
	2216	+ MSIOF3_SYNC_MARK,
	2217	+};
	2218	+static const unsigned int msiof3_ss1_pins[] = {
	2219	+ /* MSIOF3_SS1 */
	2220	+ RCAR_GP_PIN(2, 16),
	2221	+};
	2222	+static const unsigned int msiof3_ss1_mux[] = {
	2223	+ MSIOF3_SS1_MARK,
	2224	+};
	2225	+static const unsigned int msiof3_ss2_pins[] = {
	2226	+ /* MSIOF3_SS2 */
	2227	+ RCAR_GP_PIN(2, 17),
	2228	+};
	2229	+static const unsigned int msiof3_ss2_mux[] = {
	2230	+ MSIOF3_SS2_MARK,
	2231	+};
	2232	+static const unsigned int msiof3_txd_pins[] = {
	2233	+ /* MSIOF3_TXD */
	2234	+ RCAR_GP_PIN(2, 19),
	2235	+};
	2236	+static const unsigned int msiof3_txd_mux[] = {
	2237	+ MSIOF3_TXD_MARK,
	2238	+};
	2239	+static const unsigned int msiof3_rxd_pins[] = {
	2240	+ /* MSIOF3_RXD */
	2241	+ RCAR_GP_PIN(2, 18),
	2242	+};
	2243	+static const unsigned int msiof3_rxd_mux[] = {
	2244	+ MSIOF3_RXD_MARK,
	2245	+};
	2246	+
	2247	+/* - MSIOF4 ----------------------------------------------------------------- */
	2248	+static const unsigned int msiof4_clk_pins[] = {
	2249	+ /* MSIOF4_SCK */
	2250	+ RCAR_GP_PIN(2, 6),
	2251	+};
	2252	+static const unsigned int msiof4_clk_mux[] = {
	2253	+ MSIOF4_SCK_MARK,
	2254	+};
	2255	+static const unsigned int msiof4_sync_pins[] = {
	2256	+ /* MSIOF4_SYNC */
	2257	+ RCAR_GP_PIN(2, 7),
	2258	+};
	2259	+static const unsigned int msiof4_sync_mux[] = {
	2260	+ MSIOF4_SYNC_MARK,
	2261	+};
	2262	+static const unsigned int msiof4_ss1_pins[] = {
	2263	+ /* MSIOF4_SS1 */
	2264	+ RCAR_GP_PIN(2, 8),
	2265	+};
	2266	+static const unsigned int msiof4_ss1_mux[] = {
	2267	+ MSIOF4_SS1_MARK,
	2268	+};
	2269	+static const unsigned int msiof4_ss2_pins[] = {
	2270	+ /* MSIOF4_SS2 */
	2271	+ RCAR_GP_PIN(2, 9),
	2272	+};
	2273	+static const unsigned int msiof4_ss2_mux[] = {
	2274	+ MSIOF4_SS2_MARK,
	2275	+};
	2276	+static const unsigned int msiof4_txd_pins[] = {
	2277	+ /* MSIOF4_TXD */
	2278	+ RCAR_GP_PIN(2, 5),
	2279	+};
	2280	+static const unsigned int msiof4_txd_mux[] = {
	2281	+ MSIOF4_TXD_MARK,
	2282	+};
	2283	+static const unsigned int msiof4_rxd_pins[] = {
	2284	+ /* MSIOF4_RXD */
	2285	+ RCAR_GP_PIN(2, 4),
	2286	+};
	2287	+static const unsigned int msiof4_rxd_mux[] = {
	2288	+ MSIOF4_RXD_MARK,
	2289	+};
	2290	+
	2291	+/* - MSIOF5 ----------------------------------------------------------------- */
	2292	+static const unsigned int msiof5_clk_pins[] = {
	2293	+ /* MSIOF5_SCK */
	2294	+ RCAR_GP_PIN(2, 12),
	2295	+};
	2296	+static const unsigned int msiof5_clk_mux[] = {
	2297	+ MSIOF5_SCK_MARK,
	2298	+};
	2299	+static const unsigned int msiof5_sync_pins[] = {
	2300	+ /* MSIOF5_SYNC */
	2301	+ RCAR_GP_PIN(2, 13),
	2302	+};
	2303	+static const unsigned int msiof5_sync_mux[] = {
	2304	+ MSIOF5_SYNC_MARK,
	2305	+};
	2306	+static const unsigned int msiof5_ss1_pins[] = {
	2307	+ /* MSIOF5_SS1 */
	2308	+ RCAR_GP_PIN(2, 14),
	2309	+};
	2310	+static const unsigned int msiof5_ss1_mux[] = {
	2311	+ MSIOF5_SS1_MARK,
	2312	+};
	2313	+static const unsigned int msiof5_ss2_pins[] = {
	2314	+ /* MSIOF5_SS2 */
	2315	+ RCAR_GP_PIN(2, 15),
	2316	+};
	2317	+static const unsigned int msiof5_ss2_mux[] = {
	2318	+ MSIOF5_SS2_MARK,
	2319	+};
	2320	+static const unsigned int msiof5_txd_pins[] = {
	2321	+ /* MSIOF5_TXD */
	2322	+ RCAR_GP_PIN(2, 11),
	2323	+};
	2324	+static const unsigned int msiof5_txd_mux[] = {
	2325	+ MSIOF5_TXD_MARK,
	2326	+};
	2327	+static const unsigned int msiof5_rxd_pins[] = {
	2328	+ /* MSIOF5_RXD */
	2329	+ RCAR_GP_PIN(2, 10),
	2330	+};
	2331	+static const unsigned int msiof5_rxd_mux[] = {
	2332	+ MSIOF5_RXD_MARK,
	2333	+};
	2334	+
	2335	+/* - PWM0 ------------------------------------------------------------------- */
	2336	+static const unsigned int pwm0_pins[] = {
	2337	+ /* PWM0 */
	2338	+ RCAR_GP_PIN(3, 5),
	2339	+};
	2340	+static const unsigned int pwm0_mux[] = {
	2341	+ PWM0_MARK,
	2342	+};
	2343	+
	2344	+/* - PWM1 ------------------------------------------------------------------- */
	2345	+static const unsigned int pwm1_pins[] = {
	2346	+ /* PWM1 */
	2347	+ RCAR_GP_PIN(3, 6),
	2348	+};
	2349	+static const unsigned int pwm1_mux[] = {
	2350	+ PWM1_MARK,
	2351	+};
	2352	+
	2353	+/* - PWM2 ------------------------------------------------------------------- */
	2354	+static const unsigned int pwm2_pins[] = {
	2355	+ /* PWM2 */
	2356	+ RCAR_GP_PIN(3, 7),
	2357	+};
	2358	+static const unsigned int pwm2_mux[] = {
	2359	+ PWM2_MARK,
	2360	+};
	2361	+
	2362	+/* - PWM3 ------------------------------------------------------------------- */
	2363	+static const unsigned int pwm3_pins[] = {
	2364	+ /* PWM3 */
	2365	+ RCAR_GP_PIN(3, 8),
	2366	+};
	2367	+static const unsigned int pwm3_mux[] = {
	2368	+ PWM3_MARK,
	2369	+};
	2370	+
	2371	+/* - PWM4 ------------------------------------------------------------------- */
	2372	+static const unsigned int pwm4_pins[] = {
	2373	+ /* PWM4 */
	2374	+ RCAR_GP_PIN(3, 9),
	2375	+};
	2376	+static const unsigned int pwm4_mux[] = {
	2377	+ PWM4_MARK,
	2378	+};
	2379	+
	2380	+/* - QSPI0 ------------------------------------------------------------------ */
	2381	+static const unsigned int qspi0_ctrl_pins[] = {
	2382	+ /* SPCLK, SSL */
	2383	+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 5),
	2384	+};
	2385	+static const unsigned int qspi0_ctrl_mux[] = {
	2386	+ QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
	2387	+};
	2388	+static const unsigned int qspi0_data2_pins[] = {
	2389	+ /* MOSI_IO0, MISO_IO1 */
	2390	+ RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
	2391	+};
	2392	+static const unsigned int qspi0_data2_mux[] = {
	2393	+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
	2394	+};
	2395	+static const unsigned int qspi0_data4_pins[] = {
	2396	+ /* MOSI_IO0, MISO_IO1, IO2, IO3 */
	2397	+ RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
	2398	+ RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
	2399	+};
	2400	+static const unsigned int qspi0_data4_mux[] = {
	2401	+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
	2402	+ QSPI0_IO2_MARK, QSPI0_IO3_MARK
	2403	+};
	2404	+
	2405	+/* - QSPI1 ------------------------------------------------------------------ */
	2406	+static const unsigned int qspi1_ctrl_pins[] = {
	2407	+ /* SPCLK, SSL */
	2408	+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 11),
	2409	+};
	2410	+static const unsigned int qspi1_ctrl_mux[] = {
	2411	+ QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
	2412	+};
	2413	+static const unsigned int qspi1_data2_pins[] = {
	2414	+ /* MOSI_IO0, MISO_IO1 */
	2415	+ RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
	2416	+};
	2417	+static const unsigned int qspi1_data2_mux[] = {
	2418	+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
	2419	+};
	2420	+static const unsigned int qspi1_data4_pins[] = {
	2421	+ /* MOSI_IO0, MISO_IO1, IO2, IO3 */
	2422	+ RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
	2423	+ RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
	2424	+};
	2425	+static const unsigned int qspi1_data4_mux[] = {
	2426	+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
	2427	+ QSPI1_IO2_MARK, QSPI1_IO3_MARK
	2428	+};
	2429	+
	2430	+/* - SCIF0 ------------------------------------------------------------------ */
	2431	+static const unsigned int scif0_data_pins[] = {
	2432	+ /* RX0, TX0 */
	2433	+ RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5),
	2434	+};
	2435	+static const unsigned int scif0_data_mux[] = {
	2436	+ RX0_MARK, TX0_MARK,
	2437	+};
	2438	+static const unsigned int scif0_clk_pins[] = {
	2439	+ /* SCK0 */
	2440	+ RCAR_GP_PIN(1, 2),
	2441	+};
	2442	+static const unsigned int scif0_clk_mux[] = {
	2443	+ SCK0_MARK,
	2444	+};
	2445	+static const unsigned int scif0_ctrl_pins[] = {
	2446	+ /* RTS0#, CTS0# */
	2447	+ RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
	2448	+};
	2449	+static const unsigned int scif0_ctrl_mux[] = {
	2450	+ RTS0_N_MARK, CTS0_N_MARK,
	2451	+};
	2452	+
	2453	+/* - SCIF1 ------------------------------------------------------------------ */
	2454	+static const unsigned int scif1_data_a_pins[] = {
	2455	+ /* RX, TX */
	2456	+ RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
	2457	+};
	2458	+static const unsigned int scif1_data_a_mux[] = {
	2459	+ RX1_A_MARK, TX1_A_MARK,
	2460	+};
	2461	+static const unsigned int scif1_data_b_pins[] = {
	2462	+ /* RX, TX */
	2463	+ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 1),
	2464	+};
	2465	+static const unsigned int scif1_data_b_mux[] = {
	2466	+ RX1_B_MARK, TX1_B_MARK,
	2467	+};
	2468	+static const unsigned int scif1_clk_pins[] = {
	2469	+ /* SCK1 */
	2470	+ RCAR_GP_PIN(1, 18),
	2471	+};
	2472	+static const unsigned int scif1_clk_mux[] = {
	2473	+ SCK1_MARK,
	2474	+};
	2475	+static const unsigned int scif1_ctrl_pins[] = {
	2476	+ /* RTS1#, CTS1# */
	2477	+ RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19),
	2478	+};
	2479	+static const unsigned int scif1_ctrl_mux[] = {
	2480	+ RTS1_N_MARK, CTS1_N_MARK,
	2481	+};
	2482	+
	2483	+/* - SCIF3 ------------------------------------------------------------------ */
	2484	+static const unsigned int scif3_data_pins[] = {
	2485	+ /* RX3, TX3 */
	2486	+ RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
	2487	+};
	2488	+static const unsigned int scif3_data_mux[] = {
	2489	+ RX3_MARK, TX3_MARK,
	2490	+};
	2491	+static const unsigned int scif3_clk_pins[] = {
	2492	+ /* SCK3 */
	2493	+ RCAR_GP_PIN(1, 13),
	2494	+};
	2495	+static const unsigned int scif3_clk_mux[] = {
	2496	+ SCK3_MARK,
	2497	+};
	2498	+static const unsigned int scif3_ctrl_pins[] = {
	2499	+ /* RTS3#, CTS3# */
	2500	+ RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
	2501	+};
	2502	+static const unsigned int scif3_ctrl_mux[] = {
	2503	+ RTS3_N_MARK, CTS3_N_MARK,
	2504	+};
	2505	+
	2506	+/* - SCIF4 ------------------------------------------------------------------ */
	2507	+static const unsigned int scif4_data_pins[] = {
	2508	+ /* RX4, TX4 */
	2509	+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
	2510	+};
	2511	+static const unsigned int scif4_data_mux[] = {
	2512	+ RX4_MARK, TX4_MARK,
	2513	+};
	2514	+static const unsigned int scif4_clk_pins[] = {
	2515	+ /* SCK4 */
	2516	+ RCAR_GP_PIN(2, 5),
	2517	+};
	2518	+static const unsigned int scif4_clk_mux[] = {
	2519	+ SCK4_MARK,
	2520	+};
	2521	+static const unsigned int scif4_ctrl_pins[] = {
	2522	+ /* RTS4#, CTS4# */
	2523	+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6),
	2524	+};
	2525	+static const unsigned int scif4_ctrl_mux[] = {
	2526	+ RTS4_N_MARK, CTS4_N_MARK,
	2527	+};
	2528	+
	2529	+/* - SCIF Clock ------------------------------------------------------------- */
	2530	+static const unsigned int scif_clk_pins[] = {
	2531	+ /* SCIF_CLK */
	2532	+ RCAR_GP_PIN(1, 0),
	2533	+};
	2534	+static const unsigned int scif_clk_mux[] = {
	2535	+ SCIF_CLK_MARK,
	2536	+};
	2537	+
	2538	+/* - TMU -------------------------------------------------------------------- */
	2539	+static const unsigned int tmu_tclk1_a_pins[] = {
	2540	+ /* TCLK1 */
	2541	+ RCAR_GP_PIN(2, 23),
	2542	+};
	2543	+static const unsigned int tmu_tclk1_a_mux[] = {
	2544	+ TCLK1_A_MARK,
	2545	+};
	2546	+static const unsigned int tmu_tclk1_b_pins[] = {
	2547	+ /* TCLK1 */
	2548	+ RCAR_GP_PIN(1, 23),
	2549	+};
	2550	+static const unsigned int tmu_tclk1_b_mux[] = {
	2551	+ TCLK1_B_MARK,
	2552	+};
	2553	+
	2554	+static const unsigned int tmu_tclk2_a_pins[] = {
	2555	+ /* TCLK2 */
	2556	+ RCAR_GP_PIN(2, 24),
	2557	+};
	2558	+static const unsigned int tmu_tclk2_a_mux[] = {
	2559	+ TCLK2_A_MARK,
	2560	+};
	2561	+static const unsigned int tmu_tclk2_b_pins[] = {
	2562	+ /* TCLK2 */
	2563	+ RCAR_GP_PIN(2, 10),
	2564	+};
	2565	+static const unsigned int tmu_tclk2_b_mux[] = {
	2566	+ TCLK2_B_MARK,
	2567	+};
	2568	+
	2569	+static const unsigned int tmu_tclk3_pins[] = {
	2570	+ /* TCLK3 */
	2571	+ RCAR_GP_PIN(2, 11),
	2572	+};
	2573	+static const unsigned int tmu_tclk3_mux[] = {
	2574	+ TCLK3_MARK,
	2575	+};
	2576	+
	2577	+static const unsigned int tmu_tclk4_pins[] = {
	2578	+ /* TCLK4 */
	2579	+ RCAR_GP_PIN(2, 12),
	2580	+};
	2581	+static const unsigned int tmu_tclk4_mux[] = {
	2582	+ TCLK4_MARK,
	2583	+};
	2584	+
	2585	+/* - TPU ------------------------------------------------------------------- */
	2586	+static const unsigned int tpu_to0_pins[] = {
	2587	+ /* TPU0TO0 */
	2588	+ RCAR_GP_PIN(2, 21),
	2589	+};
	2590	+static const unsigned int tpu_to0_mux[] = {
	2591	+ TPU0TO0_MARK,
	2592	+};
	2593	+static const unsigned int tpu_to1_pins[] = {
	2594	+ /* TPU0TO1 */
	2595	+ RCAR_GP_PIN(2, 22),
	2596	+};
	2597	+static const unsigned int tpu_to1_mux[] = {
	2598	+ TPU0TO1_MARK,
	2599	+};
	2600	+static const unsigned int tpu_to2_pins[] = {
	2601	+ /* TPU0TO2 */
	2602	+ RCAR_GP_PIN(3, 5),
	2603	+};
	2604	+static const unsigned int tpu_to2_mux[] = {
	2605	+ TPU0TO2_MARK,
	2606	+};
	2607	+static const unsigned int tpu_to3_pins[] = {
	2608	+ /* TPU0TO3 */
	2609	+ RCAR_GP_PIN(3, 6),
	2610	+};
	2611	+static const unsigned int tpu_to3_mux[] = {
	2612	+ TPU0TO3_MARK,
	2613	+};
	2614	+
	2615	+static const struct sh_pfc_pin_group pinmux_groups[] = {
	2616	+ SH_PFC_PIN_GROUP(avb0_link),
	2617	+ SH_PFC_PIN_GROUP(avb0_magic),
	2618	+ SH_PFC_PIN_GROUP(avb0_phy_int),
	2619	+ SH_PFC_PIN_GROUP(avb0_mdio),
	2620	+ SH_PFC_PIN_GROUP(avb0_rgmii),
	2621	+ SH_PFC_PIN_GROUP(avb0_txcrefclk),
	2622	+ SH_PFC_PIN_GROUP(avb0_avtp_pps),
	2623	+ SH_PFC_PIN_GROUP(avb0_avtp_capture),
	2624	+ SH_PFC_PIN_GROUP(avb0_avtp_match),
	2625	+
	2626	+ SH_PFC_PIN_GROUP(avb1_link),
	2627	+ SH_PFC_PIN_GROUP(avb1_magic),
	2628	+ SH_PFC_PIN_GROUP(avb1_phy_int),
	2629	+ SH_PFC_PIN_GROUP(avb1_mdio),
	2630	+ SH_PFC_PIN_GROUP(avb1_rgmii),
	2631	+ SH_PFC_PIN_GROUP(avb1_txcrefclk),
	2632	+ SH_PFC_PIN_GROUP(avb1_avtp_pps),
	2633	+ SH_PFC_PIN_GROUP(avb1_avtp_capture),
	2634	+ SH_PFC_PIN_GROUP(avb1_avtp_match),
	2635	+
	2636	+ SH_PFC_PIN_GROUP(avb2_link),
	2637	+ SH_PFC_PIN_GROUP(avb2_magic),
	2638	+ SH_PFC_PIN_GROUP(avb2_phy_int),
	2639	+ SH_PFC_PIN_GROUP(avb2_mdio),
	2640	+ SH_PFC_PIN_GROUP(avb2_rgmii),
	2641	+ SH_PFC_PIN_GROUP(avb2_txcrefclk),
	2642	+ SH_PFC_PIN_GROUP(avb2_avtp_pps),
	2643	+ SH_PFC_PIN_GROUP(avb2_avtp_capture),
	2644	+ SH_PFC_PIN_GROUP(avb2_avtp_match),
	2645	+
	2646	+ SH_PFC_PIN_GROUP(avb3_link),
	2647	+ SH_PFC_PIN_GROUP(avb3_magic),
	2648	+ SH_PFC_PIN_GROUP(avb3_phy_int),
	2649	+ SH_PFC_PIN_GROUP(avb3_mdio),
	2650	+ SH_PFC_PIN_GROUP(avb3_rgmii),
	2651	+ SH_PFC_PIN_GROUP(avb3_txcrefclk),
	2652	+ SH_PFC_PIN_GROUP(avb3_avtp_pps),
	2653	+ SH_PFC_PIN_GROUP(avb3_avtp_capture),
	2654	+ SH_PFC_PIN_GROUP(avb3_avtp_match),
	2655	+
	2656	+ SH_PFC_PIN_GROUP(avb4_link),
	2657	+ SH_PFC_PIN_GROUP(avb4_magic),
	2658	+ SH_PFC_PIN_GROUP(avb4_phy_int),
	2659	+ SH_PFC_PIN_GROUP(avb4_mdio),
	2660	+ SH_PFC_PIN_GROUP(avb4_rgmii),
	2661	+ SH_PFC_PIN_GROUP(avb4_txcrefclk),
	2662	+ SH_PFC_PIN_GROUP(avb4_avtp_pps),
	2663	+ SH_PFC_PIN_GROUP(avb4_avtp_capture),
	2664	+ SH_PFC_PIN_GROUP(avb4_avtp_match),
	2665	+
	2666	+ SH_PFC_PIN_GROUP(avb5_link),
	2667	+ SH_PFC_PIN_GROUP(avb5_magic),
	2668	+ SH_PFC_PIN_GROUP(avb5_phy_int),
	2669	+ SH_PFC_PIN_GROUP(avb5_mdio),
	2670	+ SH_PFC_PIN_GROUP(avb5_rgmii),
	2671	+ SH_PFC_PIN_GROUP(avb5_txcrefclk),
	2672	+ SH_PFC_PIN_GROUP(avb5_avtp_pps),
	2673	+ SH_PFC_PIN_GROUP(avb5_avtp_capture),
	2674	+ SH_PFC_PIN_GROUP(avb5_avtp_match),
	2675	+
	2676	+ SH_PFC_PIN_GROUP(canfd0_data),
	2677	+ SH_PFC_PIN_GROUP(canfd1_data),
	2678	+ SH_PFC_PIN_GROUP(canfd2_data),
	2679	+ SH_PFC_PIN_GROUP(canfd3_data),
	2680	+ SH_PFC_PIN_GROUP(canfd4_data),
	2681	+ SH_PFC_PIN_GROUP(canfd5_data),
	2682	+ SH_PFC_PIN_GROUP(canfd6_data),
	2683	+ SH_PFC_PIN_GROUP(canfd7_data),
	2684	+ SH_PFC_PIN_GROUP(can_clk),
	2685	+
	2686	+ SH_PFC_PIN_GROUP(du_rgb888),
	2687	+ SH_PFC_PIN_GROUP(du_clk_out),
	2688	+ SH_PFC_PIN_GROUP(du_sync),
	2689	+ SH_PFC_PIN_GROUP(du_oddf),
	2690	+
	2691	+ SH_PFC_PIN_GROUP(hscif0_data),
	2692	+ SH_PFC_PIN_GROUP(hscif0_clk),
	2693	+ SH_PFC_PIN_GROUP(hscif0_ctrl),
	2694	+ SH_PFC_PIN_GROUP(hscif1_data),
	2695	+ SH_PFC_PIN_GROUP(hscif1_clk),
	2696	+ SH_PFC_PIN_GROUP(hscif1_ctrl),
	2697	+ SH_PFC_PIN_GROUP(hscif2_data),
	2698	+ SH_PFC_PIN_GROUP(hscif2_clk),
	2699	+ SH_PFC_PIN_GROUP(hscif2_ctrl),
	2700	+ SH_PFC_PIN_GROUP(hscif3_data),
	2701	+ SH_PFC_PIN_GROUP(hscif3_clk),
	2702	+ SH_PFC_PIN_GROUP(hscif3_ctrl),
	2703	+
	2704	+ SH_PFC_PIN_GROUP(i2c0),
	2705	+ SH_PFC_PIN_GROUP(i2c1),
	2706	+ SH_PFC_PIN_GROUP(i2c2),
	2707	+ SH_PFC_PIN_GROUP(i2c3),
	2708	+ SH_PFC_PIN_GROUP(i2c4),
	2709	+ SH_PFC_PIN_GROUP(i2c5),
	2710	+ SH_PFC_PIN_GROUP(i2c6),
	2711	+
	2712	+ SH_PFC_PIN_GROUP(intc_ex_irq0),
	2713	+ SH_PFC_PIN_GROUP(intc_ex_irq1),
	2714	+ SH_PFC_PIN_GROUP(intc_ex_irq2),
	2715	+ SH_PFC_PIN_GROUP(intc_ex_irq3),
	2716	+ SH_PFC_PIN_GROUP(intc_ex_irq4),
	2717	+ SH_PFC_PIN_GROUP(intc_ex_irq5),
	2718	+
	2719	+ SH_PFC_PIN_GROUP(mmc_data1),
	2720	+ SH_PFC_PIN_GROUP(mmc_data4),
	2721	+ SH_PFC_PIN_GROUP(mmc_data8),
	2722	+ SH_PFC_PIN_GROUP(mmc_ctrl),
	2723	+ SH_PFC_PIN_GROUP(mmc_cd),
	2724	+ SH_PFC_PIN_GROUP(mmc_wp),
	2725	+ SH_PFC_PIN_GROUP(mmc_ds),
	2726	+
	2727	+ SH_PFC_PIN_GROUP(msiof0_clk),
	2728	+ SH_PFC_PIN_GROUP(msiof0_sync),
	2729	+ SH_PFC_PIN_GROUP(msiof0_ss1),
	2730	+ SH_PFC_PIN_GROUP(msiof0_ss2),
	2731	+ SH_PFC_PIN_GROUP(msiof0_txd),
	2732	+ SH_PFC_PIN_GROUP(msiof0_rxd),
	2733	+ SH_PFC_PIN_GROUP(msiof1_clk),
	2734	+ SH_PFC_PIN_GROUP(msiof1_sync),
	2735	+ SH_PFC_PIN_GROUP(msiof1_ss1),
	2736	+ SH_PFC_PIN_GROUP(msiof1_ss2),
	2737	+ SH_PFC_PIN_GROUP(msiof1_txd),
	2738	+ SH_PFC_PIN_GROUP(msiof1_rxd),
	2739	+ SH_PFC_PIN_GROUP(msiof2_clk),
	2740	+ SH_PFC_PIN_GROUP(msiof2_sync),
	2741	+ SH_PFC_PIN_GROUP(msiof2_ss1),
	2742	+ SH_PFC_PIN_GROUP(msiof2_ss2),
	2743	+ SH_PFC_PIN_GROUP(msiof2_txd),
	2744	+ SH_PFC_PIN_GROUP(msiof2_rxd),
	2745	+ SH_PFC_PIN_GROUP(msiof3_clk),
	2746	+ SH_PFC_PIN_GROUP(msiof3_sync),
	2747	+ SH_PFC_PIN_GROUP(msiof3_ss1),
	2748	+ SH_PFC_PIN_GROUP(msiof3_ss2),
	2749	+ SH_PFC_PIN_GROUP(msiof3_txd),
	2750	+ SH_PFC_PIN_GROUP(msiof3_rxd),
	2751	+ SH_PFC_PIN_GROUP(msiof4_clk),
	2752	+ SH_PFC_PIN_GROUP(msiof4_sync),
	2753	+ SH_PFC_PIN_GROUP(msiof4_ss1),
	2754	+ SH_PFC_PIN_GROUP(msiof4_ss2),
	2755	+ SH_PFC_PIN_GROUP(msiof4_txd),
	2756	+ SH_PFC_PIN_GROUP(msiof4_rxd),
	2757	+ SH_PFC_PIN_GROUP(msiof5_clk),
	2758	+ SH_PFC_PIN_GROUP(msiof5_sync),
	2759	+ SH_PFC_PIN_GROUP(msiof5_ss1),
	2760	+ SH_PFC_PIN_GROUP(msiof5_ss2),
	2761	+ SH_PFC_PIN_GROUP(msiof5_txd),
	2762	+ SH_PFC_PIN_GROUP(msiof5_rxd),
	2763	+
	2764	+ SH_PFC_PIN_GROUP(pwm0),
	2765	+ SH_PFC_PIN_GROUP(pwm1),
	2766	+ SH_PFC_PIN_GROUP(pwm2),
	2767	+ SH_PFC_PIN_GROUP(pwm3),
	2768	+ SH_PFC_PIN_GROUP(pwm4),
	2769	+
	2770	+ SH_PFC_PIN_GROUP(qspi0_ctrl),
	2771	+ SH_PFC_PIN_GROUP(qspi0_data2),
	2772	+ SH_PFC_PIN_GROUP(qspi0_data4),
	2773	+ SH_PFC_PIN_GROUP(qspi1_ctrl),
	2774	+ SH_PFC_PIN_GROUP(qspi1_data2),
	2775	+ SH_PFC_PIN_GROUP(qspi1_data4),
	2776	+
	2777	+ SH_PFC_PIN_GROUP(scif0_data),
	2778	+ SH_PFC_PIN_GROUP(scif0_clk),
	2779	+ SH_PFC_PIN_GROUP(scif0_ctrl),
	2780	+ SH_PFC_PIN_GROUP(scif1_data_a),
	2781	+ SH_PFC_PIN_GROUP(scif1_data_b),
	2782	+ SH_PFC_PIN_GROUP(scif1_clk),
	2783	+ SH_PFC_PIN_GROUP(scif1_ctrl),
	2784	+ SH_PFC_PIN_GROUP(scif3_data),
	2785	+ SH_PFC_PIN_GROUP(scif3_clk),
	2786	+ SH_PFC_PIN_GROUP(scif3_ctrl),
	2787	+ SH_PFC_PIN_GROUP(scif4_data),
	2788	+ SH_PFC_PIN_GROUP(scif4_clk),
	2789	+ SH_PFC_PIN_GROUP(scif4_ctrl),
	2790	+ SH_PFC_PIN_GROUP(scif_clk),
	2791	+
	2792	+ SH_PFC_PIN_GROUP(tmu_tclk1_a),
	2793	+ SH_PFC_PIN_GROUP(tmu_tclk1_b),
	2794	+ SH_PFC_PIN_GROUP(tmu_tclk2_a),
	2795	+ SH_PFC_PIN_GROUP(tmu_tclk2_b),
	2796	+ SH_PFC_PIN_GROUP(tmu_tclk3),
	2797	+ SH_PFC_PIN_GROUP(tmu_tclk4),
	2798	+
	2799	+ SH_PFC_PIN_GROUP(tpu_to0),
	2800	+ SH_PFC_PIN_GROUP(tpu_to1),
	2801	+ SH_PFC_PIN_GROUP(tpu_to2),
	2802	+ SH_PFC_PIN_GROUP(tpu_to3),
	2803	+};
	2804	+
	2805	+static const char * const avb0_groups[] = {
	2806	+ "avb0_link",
	2807	+ "avb0_magic",
	2808	+ "avb0_phy_int",
	2809	+ "avb0_mdio",
	2810	+ "avb0_rgmii",
	2811	+ "avb0_txcrefclk",
	2812	+ "avb0_avtp_pps",
	2813	+ "avb0_avtp_capture",
	2814	+ "avb0_avtp_match",
	2815	+};
	2816	+
	2817	+static const char * const avb1_groups[] = {
	2818	+ "avb1_link",
	2819	+ "avb1_magic",
	2820	+ "avb1_phy_int",
	2821	+ "avb1_mdio",
	2822	+ "avb1_rgmii",
	2823	+ "avb1_txcrefclk",
	2824	+ "avb1_avtp_pps",
	2825	+ "avb1_avtp_capture",
	2826	+ "avb1_avtp_match",
	2827	+};
	2828	+
	2829	+static const char * const avb2_groups[] = {
	2830	+ "avb2_link",
	2831	+ "avb2_magic",
	2832	+ "avb2_phy_int",
	2833	+ "avb2_mdio",
	2834	+ "avb2_rgmii",
	2835	+ "avb2_txcrefclk",
	2836	+ "avb2_avtp_pps",
	2837	+ "avb2_avtp_capture",
	2838	+ "avb2_avtp_match",
	2839	+};
	2840	+
	2841	+static const char * const avb3_groups[] = {
	2842	+ "avb3_link",
	2843	+ "avb3_magic",
	2844	+ "avb3_phy_int",
	2845	+ "avb3_mdio",
	2846	+ "avb3_rgmii",
	2847	+ "avb3_txcrefclk",
	2848	+ "avb3_avtp_pps",
	2849	+ "avb3_avtp_capture",
	2850	+ "avb3_avtp_match",
	2851	+};
	2852	+
	2853	+static const char * const avb4_groups[] = {
	2854	+ "avb4_link",
	2855	+ "avb4_magic",
	2856	+ "avb4_phy_int",
	2857	+ "avb4_mdio",
	2858	+ "avb4_rgmii",
	2859	+ "avb4_txcrefclk",
	2860	+ "avb4_avtp_pps",
	2861	+ "avb4_avtp_capture",
	2862	+ "avb4_avtp_match",
	2863	+};
	2864	+
	2865	+static const char * const avb5_groups[] = {
	2866	+ "avb5_link",
	2867	+ "avb5_magic",
	2868	+ "avb5_phy_int",
	2869	+ "avb5_mdio",
	2870	+ "avb5_rgmii",
	2871	+ "avb5_txcrefclk",
	2872	+ "avb5_avtp_pps",
	2873	+ "avb5_avtp_capture",
	2874	+ "avb5_avtp_match",
	2875	+};
	2876	+
	2877	+static const char * const canfd0_groups[] = {
	2878	+ "canfd0_data",
	2879	+};
	2880	+
	2881	+static const char * const canfd1_groups[] = {
	2882	+ "canfd1_data",
	2883	+};
	2884	+
	2885	+static const char * const canfd2_groups[] = {
	2886	+ "canfd2_data",
	2887	+};
	2888	+
	2889	+static const char * const canfd3_groups[] = {
	2890	+ "canfd3_data",
	2891	+};
	2892	+
	2893	+static const char * const canfd4_groups[] = {
	2894	+ "canfd4_data",
	2895	+};
	2896	+
	2897	+static const char * const canfd5_groups[] = {
	2898	+ "canfd5_data",
	2899	+};
	2900	+
	2901	+static const char * const canfd6_groups[] = {
	2902	+ "canfd6_data",
	2903	+};
	2904	+
	2905	+static const char * const canfd7_groups[] = {
	2906	+ "canfd7_data",
	2907	+};
	2908	+
	2909	+static const char * const can_clk_groups[] = {
	2910	+ "can_clk",
	2911	+};
	2912	+
	2913	+static const char * const du_groups[] = {
	2914	+ "du_rgb888",
	2915	+ "du_clk_out",
	2916	+ "du_sync",
	2917	+ "du_oddf",
	2918	+};
	2919	+
	2920	+static const char * const hscif0_groups[] = {
	2921	+ "hscif0_data",
	2922	+ "hscif0_clk",
	2923	+ "hscif0_ctrl",
	2924	+};
	2925	+
	2926	+static const char * const hscif1_groups[] = {
	2927	+ "hscif1_data",
	2928	+ "hscif1_clk",
	2929	+ "hscif1_ctrl",
	2930	+};
	2931	+
	2932	+static const char * const hscif2_groups[] = {
	2933	+ "hscif2_data",
	2934	+ "hscif2_clk",
	2935	+ "hscif2_ctrl",
	2936	+};
	2937	+
	2938	+static const char * const hscif3_groups[] = {
	2939	+ "hscif3_data",
	2940	+ "hscif3_clk",
	2941	+ "hscif3_ctrl",
	2942	+};
	2943	+
	2944	+static const char * const i2c0_groups[] = {
	2945	+ "i2c0",
	2946	+};
	2947	+
	2948	+static const char * const i2c1_groups[] = {
	2949	+ "i2c1",
	2950	+};
	2951	+
	2952	+static const char * const i2c2_groups[] = {
	2953	+ "i2c2",
	2954	+};
	2955	+
	2956	+static const char * const i2c3_groups[] = {
	2957	+ "i2c3",
	2958	+};
	2959	+
	2960	+static const char * const i2c4_groups[] = {
	2961	+ "i2c4",
	2962	+};
	2963	+
	2964	+static const char * const i2c5_groups[] = {
	2965	+ "i2c5",
	2966	+};
	2967	+
	2968	+static const char * const i2c6_groups[] = {
	2969	+ "i2c6",
	2970	+};
	2971	+
	2972	+static const char * const intc_ex_groups[] = {
	2973	+ "intc_ex_irq0",
	2974	+ "intc_ex_irq1",
	2975	+ "intc_ex_irq2",
	2976	+ "intc_ex_irq3",
	2977	+ "intc_ex_irq4",
	2978	+ "intc_ex_irq5",
	2979	+};
	2980	+
	2981	+static const char * const mmc_groups[] = {
	2982	+ "mmc_data1",
	2983	+ "mmc_data4",
	2984	+ "mmc_data8",
	2985	+ "mmc_ctrl",
	2986	+ "mmc_cd",
	2987	+ "mmc_wp",
	2988	+ "mmc_ds",
	2989	+};
	2990	+
	2991	+static const char * const msiof0_groups[] = {
	2992	+ "msiof0_clk",
	2993	+ "msiof0_sync",
	2994	+ "msiof0_ss1",
	2995	+ "msiof0_ss2",
	2996	+ "msiof0_txd",
	2997	+ "msiof0_rxd",
	2998	+};
	2999	+
	3000	+static const char * const msiof1_groups[] = {
	3001	+ "msiof1_clk",
	3002	+ "msiof1_sync",
	3003	+ "msiof1_ss1",
	3004	+ "msiof1_ss2",
	3005	+ "msiof1_txd",
	3006	+ "msiof1_rxd",
	3007	+};
	3008	+
	3009	+static const char * const msiof2_groups[] = {
	3010	+ "msiof2_clk",
	3011	+ "msiof2_sync",
	3012	+ "msiof2_ss1",
	3013	+ "msiof2_ss2",
	3014	+ "msiof2_txd",
	3015	+ "msiof2_rxd",
	3016	+};
	3017	+
	3018	+static const char * const msiof3_groups[] = {
	3019	+ "msiof3_clk",
	3020	+ "msiof3_sync",
	3021	+ "msiof3_ss1",
	3022	+ "msiof3_ss2",
	3023	+ "msiof3_txd",
	3024	+ "msiof3_rxd",
	3025	+};
	3026	+
	3027	+static const char * const msiof4_groups[] = {
	3028	+ "msiof4_clk",
	3029	+ "msiof4_sync",
	3030	+ "msiof4_ss1",
	3031	+ "msiof4_ss2",
	3032	+ "msiof4_txd",
	3033	+ "msiof4_rxd",
	3034	+};
	3035	+
	3036	+static const char * const msiof5_groups[] = {
	3037	+ "msiof5_clk",
	3038	+ "msiof5_sync",
	3039	+ "msiof5_ss1",
	3040	+ "msiof5_ss2",
	3041	+ "msiof5_txd",
	3042	+ "msiof5_rxd",
	3043	+};
	3044	+
	3045	+static const char * const pwm0_groups[] = {
	3046	+ "pwm0",
	3047	+};
	3048	+
	3049	+static const char * const pwm1_groups[] = {
	3050	+ "pwm1",
	3051	+};
	3052	+
	3053	+static const char * const pwm2_groups[] = {
	3054	+ "pwm2",
	3055	+};
	3056	+
	3057	+static const char * const pwm3_groups[] = {
	3058	+ "pwm3",
	3059	+};
	3060	+
	3061	+static const char * const pwm4_groups[] = {
	3062	+ "pwm4",
	3063	+};
	3064	+
	3065	+static const char * const qspi0_groups[] = {
	3066	+ "qspi0_ctrl",
	3067	+ "qspi0_data2",
	3068	+ "qspi0_data4",
	3069	+};
	3070	+
	3071	+static const char * const qspi1_groups[] = {
	3072	+ "qspi1_ctrl",
	3073	+ "qspi1_data2",
	3074	+ "qspi1_data4",
	3075	+};
	3076	+
	3077	+static const char * const scif0_groups[] = {
	3078	+ "scif0_data",
	3079	+ "scif0_clk",
	3080	+ "scif0_ctrl",
	3081	+};
	3082	+
	3083	+static const char * const scif1_groups[] = {
	3084	+ "scif1_data_a",
	3085	+ "scif1_data_b",
	3086	+ "scif1_clk",
	3087	+ "scif1_ctrl",
	3088	+};
	3089	+
	3090	+static const char * const scif3_groups[] = {
	3091	+ "scif3_data",
	3092	+ "scif3_clk",
	3093	+ "scif3_ctrl",
	3094	+};
	3095	+
	3096	+static const char * const scif4_groups[] = {
	3097	+ "scif4_data",
	3098	+ "scif4_clk",
	3099	+ "scif4_ctrl",
	3100	+};
	3101	+
	3102	+static const char * const scif_clk_groups[] = {
	3103	+ "scif_clk",
	3104	+};
	3105	+
	3106	+static const char * const tmu_groups[] = {
	3107	+ "tmu_tclk1_a",
	3108	+ "tmu_tclk1_b",
	3109	+ "tmu_tclk2_a",
	3110	+ "tmu_tclk2_b",
	3111	+ "tmu_tclk3",
	3112	+ "tmu_tclk4",
	3113	+};
	3114	+
	3115	+static const char * const tpu_groups[] = {
	3116	+ "tpu_to0",
	3117	+ "tpu_to1",
	3118	+ "tpu_to2",
	3119	+ "tpu_to3",
	3120	+};
	3121	+
	3122	+static const struct sh_pfc_function pinmux_functions[] = {
	3123	+ SH_PFC_FUNCTION(avb0),
	3124	+ SH_PFC_FUNCTION(avb1),
	3125	+ SH_PFC_FUNCTION(avb2),
	3126	+ SH_PFC_FUNCTION(avb3),
	3127	+ SH_PFC_FUNCTION(avb4),
	3128	+ SH_PFC_FUNCTION(avb5),
	3129	+
	3130	+ SH_PFC_FUNCTION(canfd0),
	3131	+ SH_PFC_FUNCTION(canfd1),
	3132	+ SH_PFC_FUNCTION(canfd2),
	3133	+ SH_PFC_FUNCTION(canfd3),
	3134	+ SH_PFC_FUNCTION(canfd4),
	3135	+ SH_PFC_FUNCTION(canfd5),
	3136	+ SH_PFC_FUNCTION(canfd6),
	3137	+ SH_PFC_FUNCTION(canfd7),
	3138	+ SH_PFC_FUNCTION(can_clk),
	3139	+
	3140	+ SH_PFC_FUNCTION(du),
	3141	+
	3142	+ SH_PFC_FUNCTION(hscif0),
	3143	+ SH_PFC_FUNCTION(hscif1),
	3144	+ SH_PFC_FUNCTION(hscif2),
	3145	+ SH_PFC_FUNCTION(hscif3),
	3146	+
	3147	+ SH_PFC_FUNCTION(i2c0),
	3148	+ SH_PFC_FUNCTION(i2c1),
	3149	+ SH_PFC_FUNCTION(i2c2),
	3150	+ SH_PFC_FUNCTION(i2c3),
	3151	+ SH_PFC_FUNCTION(i2c4),
	3152	+ SH_PFC_FUNCTION(i2c5),
	3153	+ SH_PFC_FUNCTION(i2c6),
	3154	+
	3155	+ SH_PFC_FUNCTION(intc_ex),
	3156	+
	3157	+ SH_PFC_FUNCTION(mmc),
	3158	+
	3159	+ SH_PFC_FUNCTION(msiof0),
	3160	+ SH_PFC_FUNCTION(msiof1),
	3161	+ SH_PFC_FUNCTION(msiof2),
	3162	+ SH_PFC_FUNCTION(msiof3),
	3163	+ SH_PFC_FUNCTION(msiof4),
	3164	+ SH_PFC_FUNCTION(msiof5),
	3165	+
	3166	+ SH_PFC_FUNCTION(pwm0),
	3167	+ SH_PFC_FUNCTION(pwm1),
	3168	+ SH_PFC_FUNCTION(pwm2),
	3169	+ SH_PFC_FUNCTION(pwm3),
	3170	+ SH_PFC_FUNCTION(pwm4),
	3171	+
	3172	+ SH_PFC_FUNCTION(qspi0),
	3173	+ SH_PFC_FUNCTION(qspi1),
	3174	+
	3175	+ SH_PFC_FUNCTION(scif0),
	3176	+ SH_PFC_FUNCTION(scif1),
	3177	+ SH_PFC_FUNCTION(scif3),
	3178	+ SH_PFC_FUNCTION(scif4),
	3179	+ SH_PFC_FUNCTION(scif_clk),
	3180	+
	3181	+ SH_PFC_FUNCTION(tmu),
	3182	+
	3183	+ SH_PFC_FUNCTION(tpu),
	3184	+};
	3185	+
	3186	+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
	3187	+#define F_(x, y) FN_##y
	3188	+#define FM(x) FN_##x
	3189	+ { PINMUX_CFG_REG("GPSR0", 0xe6058040, 32, 1, GROUP(
	3190	+ 0, 0,
	3191	+ 0, 0,
	3192	+ 0, 0,
	3193	+ 0, 0,
	3194	+ GP_0_27_FN, GPSR0_27,
	3195	+ GP_0_26_FN, GPSR0_26,
	3196	+ GP_0_25_FN, GPSR0_25,
	3197	+ GP_0_24_FN, GPSR0_24,
	3198	+ GP_0_23_FN, GPSR0_23,
	3199	+ GP_0_22_FN, GPSR0_22,
	3200	+ GP_0_21_FN, GPSR0_21,
	3201	+ GP_0_20_FN, GPSR0_20,
	3202	+ GP_0_19_FN, GPSR0_19,
	3203	+ GP_0_18_FN, GPSR0_18,
	3204	+ GP_0_17_FN, GPSR0_17,
	3205	+ GP_0_16_FN, GPSR0_16,
	3206	+ GP_0_15_FN, GPSR0_15,
	3207	+ GP_0_14_FN, GPSR0_14,
	3208	+ GP_0_13_FN, GPSR0_13,
	3209	+ GP_0_12_FN, GPSR0_12,
	3210	+ GP_0_11_FN, GPSR0_11,
	3211	+ GP_0_10_FN, GPSR0_10,
	3212	+ GP_0_9_FN, GPSR0_9,
	3213	+ GP_0_8_FN, GPSR0_8,
	3214	+ GP_0_7_FN, GPSR0_7,
	3215	+ GP_0_6_FN, GPSR0_6,
	3216	+ GP_0_5_FN, GPSR0_5,
	3217	+ GP_0_4_FN, GPSR0_4,
	3218	+ GP_0_3_FN, GPSR0_3,
	3219	+ GP_0_2_FN, GPSR0_2,
	3220	+ GP_0_1_FN, GPSR0_1,
	3221	+ GP_0_0_FN, GPSR0_0, ))
	3222	+ },
	3223	+ { PINMUX_CFG_REG("GPSR1", 0xe6050040, 32, 1, GROUP(
	3224	+ 0, 0,
	3225	+ GP_1_30_FN, GPSR1_30,
	3226	+ GP_1_29_FN, GPSR1_29,
	3227	+ GP_1_28_FN, GPSR1_28,
	3228	+ GP_1_27_FN, GPSR1_27,
	3229	+ GP_1_26_FN, GPSR1_26,
	3230	+ GP_1_25_FN, GPSR1_25,
	3231	+ GP_1_24_FN, GPSR1_24,
	3232	+ GP_1_23_FN, GPSR1_23,
	3233	+ GP_1_22_FN, GPSR1_22,
	3234	+ GP_1_21_FN, GPSR1_21,
	3235	+ GP_1_20_FN, GPSR1_20,
	3236	+ GP_1_19_FN, GPSR1_19,
	3237	+ GP_1_18_FN, GPSR1_18,
	3238	+ GP_1_17_FN, GPSR1_17,
	3239	+ GP_1_16_FN, GPSR1_16,
	3240	+ GP_1_15_FN, GPSR1_15,
	3241	+ GP_1_14_FN, GPSR1_14,
	3242	+ GP_1_13_FN, GPSR1_13,
	3243	+ GP_1_12_FN, GPSR1_12,
	3244	+ GP_1_11_FN, GPSR1_11,
	3245	+ GP_1_10_FN, GPSR1_10,
	3246	+ GP_1_9_FN, GPSR1_9,
	3247	+ GP_1_8_FN, GPSR1_8,
	3248	+ GP_1_7_FN, GPSR1_7,
	3249	+ GP_1_6_FN, GPSR1_6,
	3250	+ GP_1_5_FN, GPSR1_5,
	3251	+ GP_1_4_FN, GPSR1_4,
	3252	+ GP_1_3_FN, GPSR1_3,
	3253	+ GP_1_2_FN, GPSR1_2,
	3254	+ GP_1_1_FN, GPSR1_1,
	3255	+ GP_1_0_FN, GPSR1_0, ))
	3256	+ },
	3257	+ { PINMUX_CFG_REG("GPSR2", 0xe6050840, 32, 1, GROUP(
	3258	+ 0, 0,
	3259	+ 0, 0,
	3260	+ 0, 0,
	3261	+ 0, 0,
	3262	+ 0, 0,
	3263	+ 0, 0,
	3264	+ 0, 0,
	3265	+ GP_2_24_FN, GPSR2_24,
	3266	+ GP_2_23_FN, GPSR2_23,
	3267	+ GP_2_22_FN, GPSR2_22,
	3268	+ GP_2_21_FN, GPSR2_21,
	3269	+ GP_2_20_FN, GPSR2_20,
	3270	+ GP_2_19_FN, GPSR2_19,
	3271	+ GP_2_18_FN, GPSR2_18,
	3272	+ GP_2_17_FN, GPSR2_17,
	3273	+ GP_2_16_FN, GPSR2_16,
	3274	+ GP_2_15_FN, GPSR2_15,
	3275	+ GP_2_14_FN, GPSR2_14,
	3276	+ GP_2_13_FN, GPSR2_13,
	3277	+ GP_2_12_FN, GPSR2_12,
	3278	+ GP_2_11_FN, GPSR2_11,
	3279	+ GP_2_10_FN, GPSR2_10,
	3280	+ GP_2_9_FN, GPSR2_9,
	3281	+ GP_2_8_FN, GPSR2_8,
	3282	+ GP_2_7_FN, GPSR2_7,
	3283	+ GP_2_6_FN, GPSR2_6,
	3284	+ GP_2_5_FN, GPSR2_5,
	3285	+ GP_2_4_FN, GPSR2_4,
	3286	+ GP_2_3_FN, GPSR2_3,
	3287	+ GP_2_2_FN, GPSR2_2,
	3288	+ GP_2_1_FN, GPSR2_1,
	3289	+ GP_2_0_FN, GPSR2_0, ))
	3290	+ },
	3291	+ { PINMUX_CFG_REG("GPSR3", 0xe6058840, 32, 1, GROUP(
	3292	+ 0, 0,
	3293	+ 0, 0,
	3294	+ 0, 0,
	3295	+ 0, 0,
	3296	+ 0, 0,
	3297	+ 0, 0,
	3298	+ 0, 0,
	3299	+ 0, 0,
	3300	+ 0, 0,
	3301	+ 0, 0,
	3302	+ 0, 0,
	3303	+ 0, 0,
	3304	+ 0, 0,
	3305	+ 0, 0,
	3306	+ 0, 0,
	3307	+ GP_3_16_FN, GPSR3_16,
	3308	+ GP_3_15_FN, GPSR3_15,
	3309	+ GP_3_14_FN, GPSR3_14,
	3310	+ GP_3_13_FN, GPSR3_13,
	3311	+ GP_3_12_FN, GPSR3_12,
	3312	+ GP_3_11_FN, GPSR3_11,
	3313	+ GP_3_10_FN, GPSR3_10,
	3314	+ GP_3_9_FN, GPSR3_9,
	3315	+ GP_3_8_FN, GPSR3_8,
	3316	+ GP_3_7_FN, GPSR3_7,
	3317	+ GP_3_6_FN, GPSR3_6,
	3318	+ GP_3_5_FN, GPSR3_5,
	3319	+ GP_3_4_FN, GPSR3_4,
	3320	+ GP_3_3_FN, GPSR3_3,
	3321	+ GP_3_2_FN, GPSR3_2,
	3322	+ GP_3_1_FN, GPSR3_1,
	3323	+ GP_3_0_FN, GPSR3_0, ))
	3324	+ },
	3325	+ { PINMUX_CFG_REG("GPSR4", 0xe6060040, 32, 1, GROUP(
	3326	+ 0, 0,
	3327	+ 0, 0,
	3328	+ 0, 0,
	3329	+ 0, 0,
	3330	+ 0, 0,
	3331	+ GP_4_26_FN, GPSR4_26,
	3332	+ GP_4_25_FN, GPSR4_25,
	3333	+ GP_4_24_FN, GPSR4_24,
	3334	+ GP_4_23_FN, GPSR4_23,
	3335	+ GP_4_22_FN, GPSR4_22,
	3336	+ GP_4_21_FN, GPSR4_21,
	3337	+ GP_4_20_FN, GPSR4_20,
	3338	+ GP_4_19_FN, GPSR4_19,
	3339	+ GP_4_18_FN, GPSR4_18,
	3340	+ GP_4_17_FN, GPSR4_17,
	3341	+ GP_4_16_FN, GPSR4_16,
	3342	+ GP_4_15_FN, GPSR4_15,
	3343	+ GP_4_14_FN, GPSR4_14,
	3344	+ GP_4_13_FN, GPSR4_13,
	3345	+ GP_4_12_FN, GPSR4_12,
	3346	+ GP_4_11_FN, GPSR4_11,
	3347	+ GP_4_10_FN, GPSR4_10,
	3348	+ GP_4_9_FN, GPSR4_9,
	3349	+ GP_4_8_FN, GPSR4_8,
	3350	+ GP_4_7_FN, GPSR4_7,
	3351	+ GP_4_6_FN, GPSR4_6,
	3352	+ GP_4_5_FN, GPSR4_5,
	3353	+ GP_4_4_FN, GPSR4_4,
	3354	+ GP_4_3_FN, GPSR4_3,
	3355	+ GP_4_2_FN, GPSR4_2,
	3356	+ GP_4_1_FN, GPSR4_1,
	3357	+ GP_4_0_FN, GPSR4_0, ))
	3358	+ },
	3359	+ { PINMUX_CFG_REG("GPSR5", 0xe6060840, 32, 1, GROUP(
	3360	+ 0, 0,
	3361	+ 0, 0,
	3362	+ 0, 0,
	3363	+ 0, 0,
	3364	+ 0, 0,
	3365	+ 0, 0,
	3366	+ 0, 0,
	3367	+ 0, 0,
	3368	+ 0, 0,
	3369	+ 0, 0,
	3370	+ 0, 0,
	3371	+ GP_5_20_FN, GPSR5_20,
	3372	+ GP_5_19_FN, GPSR5_19,
	3373	+ GP_5_18_FN, GPSR5_18,
	3374	+ GP_5_17_FN, GPSR5_17,
	3375	+ GP_5_16_FN, GPSR5_16,
	3376	+ GP_5_15_FN, GPSR5_15,
	3377	+ GP_5_14_FN, GPSR5_14,
	3378	+ GP_5_13_FN, GPSR5_13,
	3379	+ GP_5_12_FN, GPSR5_12,
	3380	+ GP_5_11_FN, GPSR5_11,
	3381	+ GP_5_10_FN, GPSR5_10,
	3382	+ GP_5_9_FN, GPSR5_9,
	3383	+ GP_5_8_FN, GPSR5_8,
	3384	+ GP_5_7_FN, GPSR5_7,
	3385	+ GP_5_6_FN, GPSR5_6,
	3386	+ GP_5_5_FN, GPSR5_5,
	3387	+ GP_5_4_FN, GPSR5_4,
	3388	+ GP_5_3_FN, GPSR5_3,
	3389	+ GP_5_2_FN, GPSR5_2,
	3390	+ GP_5_1_FN, GPSR5_1,
	3391	+ GP_5_0_FN, GPSR5_0, ))
	3392	+ },
	3393	+ { PINMUX_CFG_REG("GPSR6", 0xe6068040, 32, 1, GROUP(
	3394	+ 0, 0,
	3395	+ 0, 0,
	3396	+ 0, 0,
	3397	+ 0, 0,
	3398	+ 0, 0,
	3399	+ 0, 0,
	3400	+ 0, 0,
	3401	+ 0, 0,
	3402	+ 0, 0,
	3403	+ 0, 0,
	3404	+ 0, 0,
	3405	+ GP_6_20_FN, GPSR6_20,
	3406	+ GP_6_19_FN, GPSR6_19,
	3407	+ GP_6_18_FN, GPSR6_18,
	3408	+ GP_6_17_FN, GPSR6_17,
	3409	+ GP_6_16_FN, GPSR6_16,
	3410	+ GP_6_15_FN, GPSR6_15,
	3411	+ GP_6_14_FN, GPSR6_14,
	3412	+ GP_6_13_FN, GPSR6_13,
	3413	+ GP_6_12_FN, GPSR6_12,
	3414	+ GP_6_11_FN, GPSR6_11,
	3415	+ GP_6_10_FN, GPSR6_10,
	3416	+ GP_6_9_FN, GPSR6_9,
	3417	+ GP_6_8_FN, GPSR6_8,
	3418	+ GP_6_7_FN, GPSR6_7,
	3419	+ GP_6_6_FN, GPSR6_6,
	3420	+ GP_6_5_FN, GPSR6_5,
	3421	+ GP_6_4_FN, GPSR6_4,
	3422	+ GP_6_3_FN, GPSR6_3,
	3423	+ GP_6_2_FN, GPSR6_2,
	3424	+ GP_6_1_FN, GPSR6_1,
	3425	+ GP_6_0_FN, GPSR6_0, ))
	3426	+ },
	3427	+ { PINMUX_CFG_REG("GPSR7", 0xe6068840, 32, 1, GROUP(
	3428	+ 0, 0,
	3429	+ 0, 0,
	3430	+ 0, 0,
	3431	+ 0, 0,
	3432	+ 0, 0,
	3433	+ 0, 0,
	3434	+ 0, 0,
	3435	+ 0, 0,
	3436	+ 0, 0,
	3437	+ 0, 0,
	3438	+ 0, 0,
	3439	+ GP_7_20_FN, GPSR7_20,
	3440	+ GP_7_19_FN, GPSR7_19,
	3441	+ GP_7_18_FN, GPSR7_18,
	3442	+ GP_7_17_FN, GPSR7_17,
	3443	+ GP_7_16_FN, GPSR7_16,
	3444	+ GP_7_15_FN, GPSR7_15,
	3445	+ GP_7_14_FN, GPSR7_14,
	3446	+ GP_7_13_FN, GPSR7_13,
	3447	+ GP_7_12_FN, GPSR7_12,
	3448	+ GP_7_11_FN, GPSR7_11,
	3449	+ GP_7_10_FN, GPSR7_10,
	3450	+ GP_7_9_FN, GPSR7_9,
	3451	+ GP_7_8_FN, GPSR7_8,
	3452	+ GP_7_7_FN, GPSR7_7,
	3453	+ GP_7_6_FN, GPSR7_6,
	3454	+ GP_7_5_FN, GPSR7_5,
	3455	+ GP_7_4_FN, GPSR7_4,
	3456	+ GP_7_3_FN, GPSR7_3,
	3457	+ GP_7_2_FN, GPSR7_2,
	3458	+ GP_7_1_FN, GPSR7_1,
	3459	+ GP_7_0_FN, GPSR7_0, ))
	3460	+ },
	3461	+ { PINMUX_CFG_REG("GPSR8", 0xe6069040, 32, 1, GROUP(
	3462	+ 0, 0,
	3463	+ 0, 0,
	3464	+ 0, 0,
	3465	+ 0, 0,
	3466	+ 0, 0,
	3467	+ 0, 0,
	3468	+ 0, 0,
	3469	+ 0, 0,
	3470	+ 0, 0,
	3471	+ 0, 0,
	3472	+ 0, 0,
	3473	+ GP_8_20_FN, GPSR8_20,
	3474	+ GP_8_19_FN, GPSR8_19,
	3475	+ GP_8_18_FN, GPSR8_18,
	3476	+ GP_8_17_FN, GPSR8_17,
	3477	+ GP_8_16_FN, GPSR8_16,
	3478	+ GP_8_15_FN, GPSR8_15,
	3479	+ GP_8_14_FN, GPSR8_14,
	3480	+ GP_8_13_FN, GPSR8_13,
	3481	+ GP_8_12_FN, GPSR8_12,
	3482	+ GP_8_11_FN, GPSR8_11,
	3483	+ GP_8_10_FN, GPSR8_10,
	3484	+ GP_8_9_FN, GPSR8_9,
	3485	+ GP_8_8_FN, GPSR8_8,
	3486	+ GP_8_7_FN, GPSR8_7,
	3487	+ GP_8_6_FN, GPSR8_6,
	3488	+ GP_8_5_FN, GPSR8_5,
	3489	+ GP_8_4_FN, GPSR8_4,
	3490	+ GP_8_3_FN, GPSR8_3,
	3491	+ GP_8_2_FN, GPSR8_2,
	3492	+ GP_8_1_FN, GPSR8_1,
	3493	+ GP_8_0_FN, GPSR8_0, ))
	3494	+ },
	3495	+ { PINMUX_CFG_REG("GPSR9", 0xe6069840, 32, 1, GROUP(
	3496	+ 0, 0,
	3497	+ 0, 0,
	3498	+ 0, 0,
	3499	+ 0, 0,
	3500	+ 0, 0,
	3501	+ 0, 0,
	3502	+ 0, 0,
	3503	+ 0, 0,
	3504	+ 0, 0,
	3505	+ 0, 0,
	3506	+ 0, 0,
	3507	+ GP_9_20_FN, GPSR9_20,
	3508	+ GP_9_19_FN, GPSR9_19,
	3509	+ GP_9_18_FN, GPSR9_18,
	3510	+ GP_9_17_FN, GPSR9_17,
	3511	+ GP_9_16_FN, GPSR9_16,
	3512	+ GP_9_15_FN, GPSR9_15,
	3513	+ GP_9_14_FN, GPSR9_14,
	3514	+ GP_9_13_FN, GPSR9_13,
	3515	+ GP_9_12_FN, GPSR9_12,
	3516	+ GP_9_11_FN, GPSR9_11,
	3517	+ GP_9_10_FN, GPSR9_10,
	3518	+ GP_9_9_FN, GPSR9_9,
	3519	+ GP_9_8_FN, GPSR9_8,
	3520	+ GP_9_7_FN, GPSR9_7,
	3521	+ GP_9_6_FN, GPSR9_6,
	3522	+ GP_9_5_FN, GPSR9_5,
	3523	+ GP_9_4_FN, GPSR9_4,
	3524	+ GP_9_3_FN, GPSR9_3,
	3525	+ GP_9_2_FN, GPSR9_2,
	3526	+ GP_9_1_FN, GPSR9_1,
	3527	+ GP_9_0_FN, GPSR9_0, ))
	3528	+ },
	3529	+#undef F_
	3530	+#undef FM
	3531	+
	3532	+#define F_(x, y) x,
	3533	+#define FM(x) FN_##x,
	3534	+ { PINMUX_CFG_REG("IP0SR1", 0xe6050060, 32, 4, GROUP(
	3535	+ IP0SR1_31_28
	3536	+ IP0SR1_27_24
	3537	+ IP0SR1_23_20
	3538	+ IP0SR1_19_16
	3539	+ IP0SR1_15_12
	3540	+ IP0SR1_11_8
	3541	+ IP0SR1_7_4
	3542	+ IP0SR1_3_0))
	3543	+ },
	3544	+ { PINMUX_CFG_REG("IP1SR1", 0xe6050064, 32, 4, GROUP(
	3545	+ IP1SR1_31_28
	3546	+ IP1SR1_27_24
	3547	+ IP1SR1_23_20
	3548	+ IP1SR1_19_16
	3549	+ IP1SR1_15_12
	3550	+ IP1SR1_11_8
	3551	+ IP1SR1_7_4
	3552	+ IP1SR1_3_0))
	3553	+ },
	3554	+ { PINMUX_CFG_REG("IP2SR1", 0xe6050068, 32, 4, GROUP(
	3555	+ IP2SR1_31_28
	3556	+ IP2SR1_27_24
	3557	+ IP2SR1_23_20
	3558	+ IP2SR1_19_16
	3559	+ IP2SR1_15_12
	3560	+ IP2SR1_11_8
	3561	+ IP2SR1_7_4
	3562	+ IP2SR1_3_0))
	3563	+ },
	3564	+ { PINMUX_CFG_REG("IP3SR1", 0xe605006c, 32, 4, GROUP(
	3565	+ IP3SR1_31_28
	3566	+ IP3SR1_27_24
	3567	+ IP3SR1_23_20
	3568	+ IP3SR1_19_16
	3569	+ IP3SR1_15_12
	3570	+ IP3SR1_11_8
	3571	+ IP3SR1_7_4
	3572	+ IP3SR1_3_0))
	3573	+ },
	3574	+ { PINMUX_CFG_REG("IP0SR2", 0xe6050860, 32, 4, GROUP(
	3575	+ IP0SR2_31_28
	3576	+ IP0SR2_27_24
	3577	+ IP0SR2_23_20
	3578	+ IP0SR2_19_16
	3579	+ IP0SR2_15_12
	3580	+ IP0SR2_11_8
	3581	+ IP0SR2_7_4
	3582	+ IP0SR2_3_0))
	3583	+ },
	3584	+ { PINMUX_CFG_REG("IP1SR2", 0xe6050864, 32, 4, GROUP(
	3585	+ IP1SR2_31_28
	3586	+ IP1SR2_27_24
	3587	+ IP1SR2_23_20
	3588	+ IP1SR2_19_16
	3589	+ IP1SR2_15_12
	3590	+ IP1SR2_11_8
	3591	+ IP1SR2_7_4
	3592	+ IP1SR2_3_0))
	3593	+ },
	3594	+ { PINMUX_CFG_REG("IP2SR2", 0xe6050868, 32, 4, GROUP(
	3595	+ IP2SR2_31_28
	3596	+ IP2SR2_27_24
	3597	+ IP2SR2_23_20
	3598	+ IP2SR2_19_16
	3599	+ IP2SR2_15_12
	3600	+ IP2SR2_11_8
	3601	+ IP2SR2_7_4
	3602	+ IP2SR2_3_0))
	3603	+ },
	3604	+ { PINMUX_CFG_REG("IP0SR3", 0xe6058860, 32, 4, GROUP(
	3605	+ IP0SR3_31_28
	3606	+ IP0SR3_27_24
	3607	+ IP0SR3_23_20
	3608	+ IP0SR3_19_16
	3609	+ IP0SR3_15_12
	3610	+ IP0SR3_11_8
	3611	+ IP0SR3_7_4
	3612	+ IP0SR3_3_0))
	3613	+ },
	3614	+ { PINMUX_CFG_REG("IP1SR3", 0xe6058864, 32, 4, GROUP(
	3615	+ IP1SR3_31_28
	3616	+ IP1SR3_27_24
	3617	+ IP1SR3_23_20
	3618	+ IP1SR3_19_16
	3619	+ IP1SR3_15_12
	3620	+ IP1SR3_11_8
	3621	+ IP1SR3_7_4
	3622	+ IP1SR3_3_0))
	3623	+ },
	3624	+ { PINMUX_CFG_REG("IP0SR4", 0xe6060060, 32, 4, GROUP(
	3625	+ IP0SR4_31_28
	3626	+ IP0SR4_27_24
	3627	+ IP0SR4_23_20
	3628	+ IP0SR4_19_16
	3629	+ IP0SR4_15_12
	3630	+ IP0SR4_11_8
	3631	+ IP0SR4_7_4
	3632	+ IP0SR4_3_0))
	3633	+ },
	3634	+ { PINMUX_CFG_REG("IP1SR4", 0xe6060064, 32, 4, GROUP(
	3635	+ IP1SR4_31_28
	3636	+ IP1SR4_27_24
	3637	+ IP1SR4_23_20
	3638	+ IP1SR4_19_16
	3639	+ IP1SR4_15_12
	3640	+ IP1SR4_11_8
	3641	+ IP1SR4_7_4
	3642	+ IP1SR4_3_0))
	3643	+ },
	3644	+ { PINMUX_CFG_REG("IP2SR4", 0xe6060068, 32, 4, GROUP(
	3645	+ IP2SR4_31_28
	3646	+ IP2SR4_27_24
	3647	+ IP2SR4_23_20
	3648	+ IP2SR4_19_16
	3649	+ IP2SR4_15_12
	3650	+ IP2SR4_11_8
	3651	+ IP2SR4_7_4
	3652	+ IP2SR4_3_0))
	3653	+ },
	3654	+ { PINMUX_CFG_REG("IP0SR5", 0xe6060860, 32, 4, GROUP(
	3655	+ IP0SR5_31_28
	3656	+ IP0SR5_27_24
	3657	+ IP0SR5_23_20
	3658	+ IP0SR5_19_16
	3659	+ IP0SR5_15_12
	3660	+ IP0SR5_11_8
	3661	+ IP0SR5_7_4
	3662	+ IP0SR5_3_0))
	3663	+ },
	3664	+ { PINMUX_CFG_REG("IP1SR5", 0xe6060864, 32, 4, GROUP(
	3665	+ IP1SR5_31_28
	3666	+ IP1SR5_27_24
	3667	+ IP1SR5_23_20
	3668	+ IP1SR5_19_16
	3669	+ IP1SR5_15_12
	3670	+ IP1SR5_11_8
	3671	+ IP1SR5_7_4
	3672	+ IP1SR5_3_0))
	3673	+ },
	3674	+ { PINMUX_CFG_REG("IP2SR5", 0xe6060868, 32, 4, GROUP(
	3675	+ IP2SR5_31_28
	3676	+ IP2SR5_27_24
	3677	+ IP2SR5_23_20
	3678	+ IP2SR5_19_16
	3679	+ IP2SR5_15_12
	3680	+ IP2SR5_11_8
	3681	+ IP2SR5_7_4
	3682	+ IP2SR5_3_0))
	3683	+ },
	3684	+#undef F_
	3685	+#undef FM
	3686	+
	3687	+#define F_(x, y) x,
	3688	+#define FM(x) FN_##x,
	3689	+ { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6050900, 32,
	3690	+ GROUP(4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 1, 1),
	3691	+ GROUP(
	3692	+ /* RESERVED 31, 30, 29, 28 */
	3693	+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
	3694	+ /* RESERVED 27, 26, 25, 24 */
	3695	+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
	3696	+ /* RESERVED 23, 22, 21, 20 */
	3697	+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
	3698	+ /* RESERVED 19, 18, 17, 16 */
	3699	+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
	3700	+ MOD_SEL2_14_15
	3701	+ MOD_SEL2_12_13
	3702	+ MOD_SEL2_10_11
	3703	+ MOD_SEL2_8_9
	3704	+ MOD_SEL2_6_7
	3705	+ MOD_SEL2_4_5
	3706	+ MOD_SEL2_2_3
	3707	+ 0, 0,
	3708	+ 0, 0, ))
	3709	+ },
	3710	+ { },
	3711	+};
	3712	+
	3713	+static const struct pinmux_drive_reg pinmux_drive_regs[] = {
	3714	+ { PINMUX_DRIVE_REG("DRV0CTRL0", 0xe6058080) {
	3715	+ { RCAR_GP_PIN(0, 7), 28, 2 }, /* QSPI1_MOSI_IO0 */
	3716	+ { RCAR_GP_PIN(0, 6), 24, 2 }, /* QSPI1_SPCLK */
	3717	+ { RCAR_GP_PIN(0, 5), 20, 2 }, /* QSPI0_SSL */
	3718	+ { RCAR_GP_PIN(0, 4), 16, 2 }, /* QSPI0_IO3 */
	3719	+ { RCAR_GP_PIN(0, 3), 12, 2 }, /* QSPI0_IO2 */
	3720	+ { RCAR_GP_PIN(0, 2), 8, 2 }, /* QSPI0_MISO_IO1 */
	3721	+ { RCAR_GP_PIN(0, 1), 4, 2 }, /* QSPI0_MOSI_IO0 */
	3722	+ { RCAR_GP_PIN(0, 0), 0, 2 }, /* QSPI0_SPCLK */
	3723	+ } },
	3724	+ { PINMUX_DRIVE_REG("DRV1CTRL0", 0xe6058084) {
	3725	+ { RCAR_GP_PIN(0, 15), 28, 3 }, /* SD_WP */
	3726	+ { RCAR_GP_PIN(0, 14), 24, 2 }, /* RPC_INT_N */
	3727	+ { RCAR_GP_PIN(0, 13), 20, 2 }, /* RPC_WP_N */
	3728	+ { RCAR_GP_PIN(0, 12), 16, 2 }, /* RPC_RESET_N */
	3729	+ { RCAR_GP_PIN(0, 11), 12, 2 }, /* QSPI1_SSL */
	3730	+ { RCAR_GP_PIN(0, 10), 8, 2 }, /* QSPI1_IO3 */
	3731	+ { RCAR_GP_PIN(0, 9), 4, 2 }, /* QSPI1_IO2 */
	3732	+ { RCAR_GP_PIN(0, 8), 0, 2 }, /* QSPI1_MISO_IO1 */
	3733	+ } },
	3734	+ { PINMUX_DRIVE_REG("DRV2CTRL0", 0xe6058088) {
	3735	+ { RCAR_GP_PIN(0, 23), 28, 3 }, /* MMC_SD_CLK */
	3736	+ { RCAR_GP_PIN(0, 22), 24, 3 }, /* MMC_SD_D3 */
	3737	+ { RCAR_GP_PIN(0, 21), 20, 3 }, /* MMC_SD_D2 */
	3738	+ { RCAR_GP_PIN(0, 20), 16, 3 }, /* MMC_SD_D1 */
	3739	+ { RCAR_GP_PIN(0, 19), 12, 3 }, /* MMC_SD_D0 */
	3740	+ { RCAR_GP_PIN(0, 18), 8, 3 }, /* MMC_SD_CMD */
	3741	+ { RCAR_GP_PIN(0, 17), 4, 3 }, /* MMC_DS */
	3742	+ { RCAR_GP_PIN(0, 16), 0, 3 }, /* SD_CD */
	3743	+ } },
	3744	+ { PINMUX_DRIVE_REG("DRV3CTRL0", 0xe605808c) {
	3745	+ { RCAR_GP_PIN(0, 27), 12, 3 }, /* MMC_D7 */
	3746	+ { RCAR_GP_PIN(0, 26), 8, 3 }, /* MMC_D6 */
	3747	+ { RCAR_GP_PIN(0, 25), 4, 3 }, /* MMC_D5 */
	3748	+ { RCAR_GP_PIN(0, 24), 0, 3 }, /* MMC_D4 */
	3749	+ } },
	3750	+ { PINMUX_DRIVE_REG("DRV0CTRL1", 0xe6050080) {
	3751	+ { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_TXD */
	3752	+ { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_RXD */
	3753	+ { RCAR_GP_PIN(1, 5), 20, 3 }, /* HTX0 */
	3754	+ { RCAR_GP_PIN(1, 4), 16, 3 }, /* HCTS0_N */
	3755	+ { RCAR_GP_PIN(1, 3), 12, 3 }, /* HRTS0_N */
	3756	+ { RCAR_GP_PIN(1, 2), 8, 3 }, /* HSCK0 */
	3757	+ { RCAR_GP_PIN(1, 1), 4, 3 }, /* HRX0 */
	3758	+ { RCAR_GP_PIN(1, 0), 0, 3 }, /* SCIF_CLK */
	3759	+ } },
	3760	+ { PINMUX_DRIVE_REG("DRV1CTRL1", 0xe6050084) {
	3761	+ { RCAR_GP_PIN(1, 15), 28, 3 }, /* MSIOF1_SYNC */
	3762	+ { RCAR_GP_PIN(1, 14), 24, 3 }, /* MSIOF1_SCK */
	3763	+ { RCAR_GP_PIN(1, 13), 20, 3 }, /* MSIOF1_TXD */
	3764	+ { RCAR_GP_PIN(1, 12), 16, 3 }, /* MSIOF1_RXD */
	3765	+ { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_SS2 */
	3766	+ { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SS1 */
	3767	+ { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_SYNC */
	3768	+ { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SCK */
	3769	+ } },
	3770	+ { PINMUX_DRIVE_REG("DRV2CTRL1", 0xe6050088) {
	3771	+ { RCAR_GP_PIN(1, 23), 28, 3 }, /* MSIOF2_SS2 */
	3772	+ { RCAR_GP_PIN(1, 22), 24, 3 }, /* MSIOF2_SS1 */
	3773	+ { RCAR_GP_PIN(1, 21), 20, 3 }, /* MSIOF2_SYNC */
	3774	+ { RCAR_GP_PIN(1, 20), 16, 3 }, /* MSIOF2_SCK */
	3775	+ { RCAR_GP_PIN(1, 19), 12, 3 }, /* MSIOF2_TXD */
	3776	+ { RCAR_GP_PIN(1, 18), 8, 3 }, /* MSIOF2_RXD */
	3777	+ { RCAR_GP_PIN(1, 17), 4, 3 }, /* MSIOF1_SS2 */
	3778	+ { RCAR_GP_PIN(1, 16), 0, 3 }, /* MSIOF1_SS1 */
	3779	+ } },
	3780	+ { PINMUX_DRIVE_REG("DRV3CTRL1", 0xe605008c) {
	3781	+ { RCAR_GP_PIN(1, 30), 24, 3 }, /* GP1_30 */
	3782	+ { RCAR_GP_PIN(1, 29), 20, 3 }, /* GP1_29 */
	3783	+ { RCAR_GP_PIN(1, 28), 16, 3 }, /* GP1_28 */
	3784	+ { RCAR_GP_PIN(1, 27), 12, 3 }, /* IRQ3 */
	3785	+ { RCAR_GP_PIN(1, 26), 8, 3 }, /* IRQ2 */
	3786	+ { RCAR_GP_PIN(1, 25), 4, 3 }, /* IRQ1 */
	3787	+ { RCAR_GP_PIN(1, 24), 0, 3 }, /* IRQ0 */
	3788	+ } },
	3789	+ { PINMUX_DRIVE_REG("DRV0CTRL2", 0xe6050880) {
	3790	+ { RCAR_GP_PIN(2, 7), 28, 3 }, /* GP2_07 */
	3791	+ { RCAR_GP_PIN(2, 6), 24, 3 }, /* GP2_06 */
	3792	+ { RCAR_GP_PIN(2, 5), 20, 3 }, /* GP2_05 */
	3793	+ { RCAR_GP_PIN(2, 4), 16, 3 }, /* GP2_04 */
	3794	+ { RCAR_GP_PIN(2, 3), 12, 3 }, /* GP2_03 */
	3795	+ { RCAR_GP_PIN(2, 2), 8, 3 }, /* GP2_02 */
	3796	+ { RCAR_GP_PIN(2, 1), 4, 2 }, /* IPC_CLKOUT */
	3797	+ { RCAR_GP_PIN(2, 0), 0, 2 }, /* IPC_CLKIN */
	3798	+ } },
	3799	+ { PINMUX_DRIVE_REG("DRV1CTRL2", 0xe6050884) {
	3800	+ { RCAR_GP_PIN(2, 15), 28, 3 }, /* GP2_15 */
	3801	+ { RCAR_GP_PIN(2, 14), 24, 3 }, /* GP2_14 */
	3802	+ { RCAR_GP_PIN(2, 13), 20, 3 }, /* GP2_13 */
	3803	+ { RCAR_GP_PIN(2, 12), 16, 3 }, /* GP2_12 */
	3804	+ { RCAR_GP_PIN(2, 11), 12, 3 }, /* GP2_11 */
	3805	+ { RCAR_GP_PIN(2, 10), 8, 3 }, /* GP2_10 */
	3806	+ { RCAR_GP_PIN(2, 9), 4, 3 }, /* GP2_9 */
	3807	+ { RCAR_GP_PIN(2, 8), 0, 3 }, /* GP2_8 */
	3808	+ } },
	3809	+ { PINMUX_DRIVE_REG("DRV2CTRL2", 0xe6050888) {
	3810	+ { RCAR_GP_PIN(2, 23), 28, 3 }, /* TCLK1_A */
	3811	+ { RCAR_GP_PIN(2, 22), 24, 3 }, /* TPU0TO1 */
	3812	+ { RCAR_GP_PIN(2, 21), 20, 3 }, /* TPU0TO0 */
	3813	+ { RCAR_GP_PIN(2, 20), 16, 3 }, /* CLK_EXTFXR */
	3814	+ { RCAR_GP_PIN(2, 19), 12, 3 }, /* RXDB_EXTFXR */
	3815	+ { RCAR_GP_PIN(2, 18), 8, 3 }, /* FXR_TXDB */
	3816	+ { RCAR_GP_PIN(2, 17), 4, 3 }, /* RXDA_EXTFXR_A */
	3817	+ { RCAR_GP_PIN(2, 16), 0, 3 }, /* FXR_TXDA_A */
	3818	+ } },
	3819	+ { PINMUX_DRIVE_REG("DRV3CTRL2", 0xe605088c) {
	3820	+ { RCAR_GP_PIN(2, 24), 0, 3 }, /* TCLK2_A */
	3821	+ } },
	3822	+ { PINMUX_DRIVE_REG("DRV0CTRL3", 0xe6058880) {
	3823	+ { RCAR_GP_PIN(3, 7), 28, 3 }, /* CANFD3_TX */
	3824	+ { RCAR_GP_PIN(3, 6), 24, 3 }, /* CANFD2_RX */
	3825	+ { RCAR_GP_PIN(3, 5), 20, 3 }, /* CANFD2_TX */
	3826	+ { RCAR_GP_PIN(3, 4), 16, 3 }, /* CANFD1_RX */
	3827	+ { RCAR_GP_PIN(3, 3), 12, 3 }, /* CANFD1_TX */
	3828	+ { RCAR_GP_PIN(3, 2), 8, 3 }, /* CANFD0_RX */
	3829	+ { RCAR_GP_PIN(3, 1), 4, 2 }, /* CANFD0_TX */
	3830	+ { RCAR_GP_PIN(3, 0), 0, 2 }, /* CAN_CLK */
	3831	+ } },
	3832	+ { PINMUX_DRIVE_REG("DRV1CTRL3", 0xe6058884) {
	3833	+ { RCAR_GP_PIN(3, 15), 28, 3 }, /* CANFD7_TX */
	3834	+ { RCAR_GP_PIN(3, 14), 24, 3 }, /* CANFD6_RX */
	3835	+ { RCAR_GP_PIN(3, 13), 20, 3 }, /* CANFD6_TX */
	3836	+ { RCAR_GP_PIN(3, 12), 16, 3 }, /* CANFD5_RX */
	3837	+ { RCAR_GP_PIN(3, 11), 12, 3 }, /* CANFD5_TX */
	3838	+ { RCAR_GP_PIN(3, 10), 8, 3 }, /* CANFD4_RX */
	3839	+ { RCAR_GP_PIN(3, 9), 4, 3 }, /* CANFD4_TX*/
	3840	+ { RCAR_GP_PIN(3, 8), 0, 3 }, /* CANFD3_RX */
	3841	+ } },
	3842	+ { PINMUX_DRIVE_REG("DRV2CTRL3", 0xe6058888) {
	3843	+ { RCAR_GP_PIN(3, 16), 0, 3 }, /* CANFD7_RX */
	3844	+ } },
	3845	+ { PINMUX_DRIVE_REG("DRV0CTRL4", 0xe6060080) {
	3846	+ { RCAR_GP_PIN(4, 7), 28, 3 }, /* AVB0_TXC */
	3847	+ { RCAR_GP_PIN(4, 6), 24, 3 }, /* AVB0_TX_CTL */
	3848	+ { RCAR_GP_PIN(4, 5), 20, 3 }, /* AVB0_RD3 */
	3849	+ { RCAR_GP_PIN(4, 4), 16, 3 }, /* AVB0_RD2 */
	3850	+ { RCAR_GP_PIN(4, 3), 12, 3 }, /* AVB0_RD1 */
	3851	+ { RCAR_GP_PIN(4, 2), 8, 3 }, /* AVB0_RD0 */
	3852	+ { RCAR_GP_PIN(4, 1), 4, 3 }, /* AVB0_RXC */
	3853	+ { RCAR_GP_PIN(4, 0), 0, 3 }, /* AVB0_RX_CTL */
	3854	+ } },
	3855	+ { PINMUX_DRIVE_REG("DRV1CTRL4", 0xe6060084) {
	3856	+ { RCAR_GP_PIN(4, 15), 28, 3 }, /* AVB0_MAGIC */
	3857	+ { RCAR_GP_PIN(4, 14), 24, 3 }, /* AVB0_MDC */
	3858	+ { RCAR_GP_PIN(4, 13), 20, 3 }, /* AVB0_MDIO */
	3859	+ { RCAR_GP_PIN(4, 12), 16, 3 }, /* AVB0_TXCREFCLK */
	3860	+ { RCAR_GP_PIN(4, 11), 12, 3 }, /* AVB0_TD3 */
	3861	+ { RCAR_GP_PIN(4, 10), 8, 3 }, /* AVB0_TD2 */
	3862	+ { RCAR_GP_PIN(4, 9), 4, 3 }, /* AVB0_TD1*/
	3863	+ { RCAR_GP_PIN(4, 8), 0, 3 }, /* AVB0_TD0 */
	3864	+ } },
	3865	+ { PINMUX_DRIVE_REG("DRV2CTRL4", 0xe6060088) {
	3866	+ { RCAR_GP_PIN(4, 23), 28, 3 }, /* PCIE2_CLKREQ_N */
	3867	+ { RCAR_GP_PIN(4, 22), 24, 3 }, /* PCIE1_CLKREQ_N */
	3868	+ { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */
	3869	+ { RCAR_GP_PIN(4, 20), 16, 3 }, /* AVB0_AVTP_PPS */
	3870	+ { RCAR_GP_PIN(4, 19), 12, 3 }, /* AVB0_AVTP_CAPTURE */
	3871	+ { RCAR_GP_PIN(4, 18), 8, 3 }, /* AVB0_AVTP_MATCH */
	3872	+ { RCAR_GP_PIN(4, 17), 4, 3 }, /* AVB0_LINK */
	3873	+ { RCAR_GP_PIN(4, 16), 0, 3 }, /* AVB0_PHY_INT */
	3874	+ } },
	3875	+ { PINMUX_DRIVE_REG("DRV3CTRL4", 0xe606008c) {
	3876	+ { RCAR_GP_PIN(4, 26), 8, 3 }, /* AVS1 */
	3877	+ { RCAR_GP_PIN(4, 25), 4, 3 }, /* AVS0 */
	3878	+ { RCAR_GP_PIN(4, 24), 0, 3 }, /* PCIE3_CLKREQ_N */
	3879	+ } },
	3880	+ { PINMUX_DRIVE_REG("DRV0CTRL5", 0xe6060880) {
	3881	+ { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB1_TXC */
	3882	+ { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB1_TX_CTL */
	3883	+ { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB1_RD3 */
	3884	+ { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB1_RD2 */
	3885	+ { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB1_RD1 */
	3886	+ { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB1_RD0 */
	3887	+ { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB1_RXC */
	3888	+ { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB1_RX_CTL */
	3889	+ } },
	3890	+ { PINMUX_DRIVE_REG("DRV1CTRL5", 0xe6060884) {
	3891	+ { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB1_MAGIC */
	3892	+ { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB1_MDC */
	3893	+ { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB1_MDIO */
	3894	+ { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB1_TXCREFCLK */
	3895	+ { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB1_TD3 */
	3896	+ { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB1_TD2 */
	3897	+ { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB1_TD1*/
	3898	+ { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB1_TD0 */
	3899	+ } },
	3900	+ { PINMUX_DRIVE_REG("DRV2CTRL5", 0xe6060888) {
	3901	+ { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB1_AVTP_PPS */
	3902	+ { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB1_AVTP_CAPTURE */
	3903	+ { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB1_AVTP_MATCH */
	3904	+ { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB1_LINK */
	3905	+ { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB1_PHY_INT */
	3906	+ } },
	3907	+ { PINMUX_DRIVE_REG("DRV0CTRL6", 0xe6068080) {
	3908	+ { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB2_TXC */
	3909	+ { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB2_TX_CTL */
	3910	+ { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB2_RD3 */
	3911	+ { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB2_RD2 */
	3912	+ { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB2_RD1 */
	3913	+ { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB2_RD0 */
	3914	+ { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB2_RXC */
	3915	+ { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB2_RX_CTL */
	3916	+ } },
	3917	+ { PINMUX_DRIVE_REG("DRV1CTRL6", 0xe6068084) {
	3918	+ { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB2_MAGIC */
	3919	+ { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB2_MDC */
	3920	+ { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB2_MDIO */
	3921	+ { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB2_TXCREFCLK */
	3922	+ { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB2_TD3 */
	3923	+ { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB2_TD2 */
	3924	+ { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB2_TD1*/
	3925	+ { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB2_TD0 */
	3926	+ } },
	3927	+ { PINMUX_DRIVE_REG("DRV2CTRL6", 0xe6068088) {
	3928	+ { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB2_AVTP_PPS */
	3929	+ { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB2_AVTP_CAPTURE */
	3930	+ { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB2_AVTP_MATCH */
	3931	+ { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB2_LINK */
	3932	+ { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB2_PHY_INT */
	3933	+ } },
	3934	+ { PINMUX_DRIVE_REG("DRV0CTRL7", 0xe6068880) {
	3935	+ { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB3_TXC */
	3936	+ { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB3_TX_CTL */
	3937	+ { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB3_RD3 */
	3938	+ { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB3_RD2 */
	3939	+ { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB3_RD1 */
	3940	+ { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB3_RD0 */
	3941	+ { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB3_RXC */
	3942	+ { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB3_RX_CTL */
	3943	+ } },
	3944	+ { PINMUX_DRIVE_REG("DRV1CTRL7", 0xe6068884) {
	3945	+ { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB3_MAGIC */
	3946	+ { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB3_MDC */
	3947	+ { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB3_MDIO */
	3948	+ { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB3_TXCREFCLK */
	3949	+ { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB3_TD3 */
	3950	+ { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB3_TD2 */
	3951	+ { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB3_TD1*/
	3952	+ { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB3_TD0 */
	3953	+ } },
	3954	+ { PINMUX_DRIVE_REG("DRV2CTRL7", 0xe6068888) {
	3955	+ { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB3_AVTP_PPS */
	3956	+ { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB3_AVTP_CAPTURE */
	3957	+ { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB3_AVTP_MATCH */
	3958	+ { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB3_LINK */
	3959	+ { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB3_PHY_INT */
	3960	+ } },
	3961	+ { PINMUX_DRIVE_REG("DRV0CTRL8", 0xe6069080) {
	3962	+ { RCAR_GP_PIN(8, 7), 28, 3 }, /* AVB4_TXC */
	3963	+ { RCAR_GP_PIN(8, 6), 24, 3 }, /* AVB4_TX_CTL */
	3964	+ { RCAR_GP_PIN(8, 5), 20, 3 }, /* AVB4_RD3 */
	3965	+ { RCAR_GP_PIN(8, 4), 16, 3 }, /* AVB4_RD2 */
	3966	+ { RCAR_GP_PIN(8, 3), 12, 3 }, /* AVB4_RD1 */
	3967	+ { RCAR_GP_PIN(8, 2), 8, 3 }, /* AVB4_RD0 */
	3968	+ { RCAR_GP_PIN(8, 1), 4, 3 }, /* AVB4_RXC */
	3969	+ { RCAR_GP_PIN(8, 0), 0, 3 }, /* AVB4_RX_CTL */
	3970	+ } },
	3971	+ { PINMUX_DRIVE_REG("DRV1CTRL8", 0xe6069084) {
	3972	+ { RCAR_GP_PIN(8, 15), 28, 3 }, /* AVB4_MAGIC */
	3973	+ { RCAR_GP_PIN(8, 14), 24, 3 }, /* AVB4_MDC */
	3974	+ { RCAR_GP_PIN(8, 13), 20, 3 }, /* AVB4_MDIO */
	3975	+ { RCAR_GP_PIN(8, 12), 16, 3 }, /* AVB4_TXCREFCLK */
	3976	+ { RCAR_GP_PIN(8, 11), 12, 3 }, /* AVB4_TD3 */
	3977	+ { RCAR_GP_PIN(8, 10), 8, 3 }, /* AVB4_TD2 */
	3978	+ { RCAR_GP_PIN(8, 9), 4, 3 }, /* AVB4_TD1*/
	3979	+ { RCAR_GP_PIN(8, 8), 0, 3 }, /* AVB4_TD0 */
	3980	+ } },
	3981	+ { PINMUX_DRIVE_REG("DRV2CTRL8", 0xe6069088) {
	3982	+ { RCAR_GP_PIN(8, 20), 16, 3 }, /* AVB4_AVTP_PPS */
	3983	+ { RCAR_GP_PIN(8, 19), 12, 3 }, /* AVB4_AVTP_CAPTURE */
	3984	+ { RCAR_GP_PIN(8, 18), 8, 3 }, /* AVB4_AVTP_MATCH */
	3985	+ { RCAR_GP_PIN(8, 17), 4, 3 }, /* AVB4_LINK */
	3986	+ { RCAR_GP_PIN(8, 16), 0, 3 }, /* AVB4_PHY_INT */
	3987	+ } },
	3988	+ { PINMUX_DRIVE_REG("DRV0CTRL9", 0xe6069880) {
	3989	+ { RCAR_GP_PIN(9, 7), 28, 3 }, /* AVB5_TXC */
	3990	+ { RCAR_GP_PIN(9, 6), 24, 3 }, /* AVB5_TX_CTL */
	3991	+ { RCAR_GP_PIN(9, 5), 20, 3 }, /* AVB5_RD3 */
	3992	+ { RCAR_GP_PIN(9, 4), 16, 3 }, /* AVB5_RD2 */
	3993	+ { RCAR_GP_PIN(9, 3), 12, 3 }, /* AVB5_RD1 */
	3994	+ { RCAR_GP_PIN(9, 2), 8, 3 }, /* AVB5_RD0 */
	3995	+ { RCAR_GP_PIN(9, 1), 4, 3 }, /* AVB5_RXC */
	3996	+ { RCAR_GP_PIN(9, 0), 0, 3 }, /* AVB5_RX_CTL */
	3997	+ } },
	3998	+ { PINMUX_DRIVE_REG("DRV1CTRL9", 0xe6069884) {
	3999	+ { RCAR_GP_PIN(9, 15), 28, 3 }, /* AVB5_MAGIC */
	4000	+ { RCAR_GP_PIN(9, 14), 24, 3 }, /* AVB5_MDC */
	4001	+ { RCAR_GP_PIN(9, 13), 20, 3 }, /* AVB5_MDIO */
	4002	+ { RCAR_GP_PIN(9, 12), 16, 3 }, /* AVB5_TXCREFCLK */
	4003	+ { RCAR_GP_PIN(9, 11), 12, 3 }, /* AVB5_TD3 */
	4004	+ { RCAR_GP_PIN(9, 10), 8, 3 }, /* AVB5_TD2 */
	4005	+ { RCAR_GP_PIN(9, 9), 4, 3 }, /* AVB5_TD1*/
	4006	+ { RCAR_GP_PIN(9, 8), 0, 3 }, /* AVB5_TD0 */
	4007	+ } },
	4008	+ { PINMUX_DRIVE_REG("DRV2CTRL9", 0xe6069888) {
	4009	+ { RCAR_GP_PIN(9, 20), 16, 3 }, /* AVB5_AVTP_PPS */
	4010	+ { RCAR_GP_PIN(9, 19), 12, 3 }, /* AVB5_AVTP_CAPTURE */
	4011	+ { RCAR_GP_PIN(9, 18), 8, 3 }, /* AVB5_AVTP_MATCH */
	4012	+ { RCAR_GP_PIN(9, 17), 4, 3 }, /* AVB5_LINK */
	4013	+ { RCAR_GP_PIN(9, 16), 0, 3 }, /* AVB5_PHY_INT */
	4014	+ } },
	4015	+ { },
	4016	+};
	4017	+
	4018	+enum ioctrl_regs {
	4019	+ POC0,
	4020	+ POC1,
	4021	+ POC2,
	4022	+ POC4,
	4023	+ POC5,
	4024	+ POC6,
	4025	+ POC7,
	4026	+ POC8,
	4027	+ POC9,
	4028	+ TD1SEL0,
	4029	+};
	4030	+
	4031	+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
	4032	+ [POC0] = { 0xe60580a0, },
	4033	+ [POC1] = { 0xe60500a0, },
	4034	+ [POC2] = { 0xe60508a0, },
	4035	+ [POC4] = { 0xe60600a0, },
	4036	+ [POC5] = { 0xe60608a0, },
	4037	+ [POC6] = { 0xe60680a0, },
	4038	+ [POC7] = { 0xe60688a0, },
	4039	+ [POC8] = { 0xe60690a0, },
	4040	+ [POC9] = { 0xe60698a0, },
	4041	+ [TD1SEL0] = { 0xe6058124, },
	4042	+ { /* sentinel */ },
	4043	+};
	4044	+
	4045	+static int r8a779a0_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
	4046	+ u32 *pocctrl)
	4047	+{
	4048	+ int bit = pin & 0x1f;
	4049	+
	4050	+ *pocctrl = pinmux_ioctrl_regs[POC0].reg;
	4051	+ if (pin >= RCAR_GP_PIN(0, 15) && pin <= RCAR_GP_PIN(0, 27))
	4052	+ return bit;
	4053	+
	4054	+ *pocctrl = pinmux_ioctrl_regs[POC1].reg;
	4055	+ if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 30))
	4056	+ return bit;
	4057	+
	4058	+ *pocctrl = pinmux_ioctrl_regs[POC2].reg;
	4059	+ if (pin >= RCAR_GP_PIN(2, 2) && pin <= RCAR_GP_PIN(2, 15))
	4060	+ return bit;
	4061	+
	4062	+ *pocctrl = pinmux_ioctrl_regs[POC4].reg;
	4063	+ if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
	4064	+ return bit;
	4065	+
	4066	+ *pocctrl = pinmux_ioctrl_regs[POC5].reg;
	4067	+ if (pin >= RCAR_GP_PIN(5, 0) && pin <= RCAR_GP_PIN(5, 17))
	4068	+ return bit;
	4069	+
	4070	+ *pocctrl = pinmux_ioctrl_regs[POC6].reg;
	4071	+ if (pin >= RCAR_GP_PIN(6, 0) && pin <= RCAR_GP_PIN(6, 17))
	4072	+ return bit;
	4073	+
	4074	+ *pocctrl = pinmux_ioctrl_regs[POC7].reg;
	4075	+ if (pin >= RCAR_GP_PIN(7, 0) && pin <= RCAR_GP_PIN(7, 17))
	4076	+ return bit;
	4077	+
	4078	+ *pocctrl = pinmux_ioctrl_regs[POC8].reg;
	4079	+ if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 17))
	4080	+ return bit;
	4081	+
	4082	+ *pocctrl = pinmux_ioctrl_regs[POC9].reg;
	4083	+ if (pin >= RCAR_GP_PIN(9, 0) && pin <= RCAR_GP_PIN(9, 17))
	4084	+ return bit;
	4085	+
	4086	+ return -EINVAL;
	4087	+}
	4088	+
	4089	+static const struct pinmux_bias_reg pinmux_bias_regs[] = {
	4090	+ { PINMUX_BIAS_REG("PUEN0", 0xe60580c0, "PUD0", 0xe60580e0) {
	4091	+ [ 0] = RCAR_GP_PIN(0, 0), /* QSPI0_SPCLK */
	4092	+ [ 1] = RCAR_GP_PIN(0, 1), /* QSPI0_MOSI_IO0 */
	4093	+ [ 2] = RCAR_GP_PIN(0, 2), /* QSPI0_MISO_IO1 */
	4094	+ [ 3] = RCAR_GP_PIN(0, 3), /* QSPI0_IO2 */
	4095	+ [ 4] = RCAR_GP_PIN(0, 4), /* QSPI0_IO3 */
	4096	+ [ 5] = RCAR_GP_PIN(0, 5), /* QSPI0_SSL */
	4097	+ [ 6] = RCAR_GP_PIN(0, 6), /* QSPI1_SPCLK */
	4098	+ [ 7] = RCAR_GP_PIN(0, 7), /* QSPI1_MOSI_IO0 */
	4099	+ [ 8] = RCAR_GP_PIN(0, 8), /* QSPI1_MISO_IO1 */
	4100	+ [ 9] = RCAR_GP_PIN(0, 9), /* QSPI1_IO2 */
	4101	+ [10] = RCAR_GP_PIN(0, 10), /* QSPI1_IO3 */
	4102	+ [11] = RCAR_GP_PIN(0, 11), /* QSPI1_SSL */
	4103	+ [12] = RCAR_GP_PIN(0, 12), /* RPC_RESET_N */
	4104	+ [13] = RCAR_GP_PIN(0, 13), /* RPC_WP_N */
	4105	+ [14] = RCAR_GP_PIN(0, 14), /* RPC_INT_N */
	4106	+ [15] = RCAR_GP_PIN(0, 15), /* SD_WP */
	4107	+ [16] = RCAR_GP_PIN(0, 16), /* SD_CD */
	4108	+ [17] = RCAR_GP_PIN(0, 17), /* MMC_DS */
	4109	+ [18] = RCAR_GP_PIN(0, 18), /* MMC_SD_CMD */
	4110	+ [19] = RCAR_GP_PIN(0, 19), /* MMC_SD_D0 */
	4111	+ [20] = RCAR_GP_PIN(0, 20), /* MMC_SD_D1 */
	4112	+ [21] = RCAR_GP_PIN(0, 21), /* MMC_SD_D2 */
	4113	+ [22] = RCAR_GP_PIN(0, 22), /* MMC_SD_D3 */
	4114	+ [23] = RCAR_GP_PIN(0, 23), /* MMC_SD_CLK */
	4115	+ [24] = RCAR_GP_PIN(0, 24), /* MMC_D4 */
	4116	+ [25] = RCAR_GP_PIN(0, 25), /* MMC_D5 */
	4117	+ [26] = RCAR_GP_PIN(0, 26), /* MMC_D6 */
	4118	+ [27] = RCAR_GP_PIN(0, 27), /* MMC_D7 */
	4119	+ [28] = SH_PFC_PIN_NONE,
	4120	+ [29] = SH_PFC_PIN_NONE,
	4121	+ [30] = SH_PFC_PIN_NONE,
	4122	+ [31] = SH_PFC_PIN_NONE,
	4123	+ } },
	4124	+ { PINMUX_BIAS_REG("PUEN1", 0xe60500c0, "PUD1", 0xe60500e0) {
	4125	+ [ 0] = RCAR_GP_PIN(1, 0), /* SCIF_CLK */
	4126	+ [ 1] = RCAR_GP_PIN(1, 1), /* HRX0 */
	4127	+ [ 2] = RCAR_GP_PIN(1, 2), /* HSCK0 */
	4128	+ [ 3] = RCAR_GP_PIN(1, 3), /* HRTS0_N */
	4129	+ [ 4] = RCAR_GP_PIN(1, 4), /* HCTS0_N */
	4130	+ [ 5] = RCAR_GP_PIN(1, 5), /* HTX0 */
	4131	+ [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_RXD */
	4132	+ [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_TXD */
	4133	+ [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SCK */
	4134	+ [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_SYNC */
	4135	+ [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SS1 */
	4136	+ [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_SS2 */
	4137	+ [12] = RCAR_GP_PIN(1, 12), /* MSIOF1_RXD */
	4138	+ [13] = RCAR_GP_PIN(1, 13), /* MSIOF1_TXD */
	4139	+ [14] = RCAR_GP_PIN(1, 14), /* MSIOF1_SCK */
	4140	+ [15] = RCAR_GP_PIN(1, 15), /* MSIOF1_SYNC */
	4141	+ [16] = RCAR_GP_PIN(1, 16), /* MSIOF1_SS1 */
	4142	+ [17] = RCAR_GP_PIN(1, 17), /* MSIOF1_SS2 */
	4143	+ [18] = RCAR_GP_PIN(1, 18), /* MSIOF2_RXD */
	4144	+ [19] = RCAR_GP_PIN(1, 19), /* MSIOF2_TXD */
	4145	+ [20] = RCAR_GP_PIN(1, 20), /* MSIOF2_SCK */
	4146	+ [21] = RCAR_GP_PIN(1, 21), /* MSIOF2_SYNC */
	4147	+ [22] = RCAR_GP_PIN(1, 22), /* MSIOF2_SS1 */
	4148	+ [23] = RCAR_GP_PIN(1, 23), /* MSIOF2_SS2 */
	4149	+ [24] = RCAR_GP_PIN(1, 24), /* IRQ0 */
	4150	+ [25] = RCAR_GP_PIN(1, 25), /* IRQ1 */
	4151	+ [26] = RCAR_GP_PIN(1, 26), /* IRQ2 */
	4152	+ [27] = RCAR_GP_PIN(1, 27), /* IRQ3 */
	4153	+ [28] = RCAR_GP_PIN(1, 28), /* GP1_28 */
	4154	+ [29] = RCAR_GP_PIN(1, 29), /* GP1_29 */
	4155	+ [30] = RCAR_GP_PIN(1, 30), /* GP1_30 */
	4156	+ [31] = SH_PFC_PIN_NONE,
	4157	+ } },
	4158	+ { PINMUX_BIAS_REG("PUEN2", 0xe60508c0, "PUD2", 0xe60508e0) {
	4159	+ [ 0] = RCAR_GP_PIN(2, 0), /* IPC_CLKIN */
	4160	+ [ 1] = RCAR_GP_PIN(2, 1), /* IPC_CLKOUT */
	4161	+ [ 2] = RCAR_GP_PIN(2, 2), /* GP2_02 */
	4162	+ [ 3] = RCAR_GP_PIN(2, 3), /* GP2_03 */
	4163	+ [ 4] = RCAR_GP_PIN(2, 4), /* GP2_04 */
	4164	+ [ 5] = RCAR_GP_PIN(2, 5), /* GP2_05 */
	4165	+ [ 6] = RCAR_GP_PIN(2, 6), /* GP2_06 */
	4166	+ [ 7] = RCAR_GP_PIN(2, 7), /* GP2_07 */
	4167	+ [ 8] = RCAR_GP_PIN(2, 8), /* GP2_08 */
	4168	+ [ 9] = RCAR_GP_PIN(2, 9), /* GP2_09 */
	4169	+ [10] = RCAR_GP_PIN(2, 10), /* GP2_10 */
	4170	+ [11] = RCAR_GP_PIN(2, 11), /* GP2_11 */
	4171	+ [12] = RCAR_GP_PIN(2, 12), /* GP2_12 */
	4172	+ [13] = RCAR_GP_PIN(2, 13), /* GP2_13 */
	4173	+ [14] = RCAR_GP_PIN(2, 14), /* GP2_14 */
	4174	+ [15] = RCAR_GP_PIN(2, 15), /* GP2_15 */
	4175	+ [16] = RCAR_GP_PIN(2, 16), /* FXR_TXDA_A */
	4176	+ [17] = RCAR_GP_PIN(2, 17), /* RXDA_EXTFXR_A */
	4177	+ [18] = RCAR_GP_PIN(2, 18), /* FXR_TXDB */
	4178	+ [19] = RCAR_GP_PIN(2, 19), /* RXDB_EXTFXR */
	4179	+ [20] = RCAR_GP_PIN(2, 20), /* CLK_EXTFXR */
	4180	+ [21] = RCAR_GP_PIN(2, 21), /* TPU0TO0 */
	4181	+ [22] = RCAR_GP_PIN(2, 22), /* TPU0TO1 */
	4182	+ [23] = RCAR_GP_PIN(2, 23), /* TCLK1_A */
	4183	+ [24] = RCAR_GP_PIN(2, 24), /* TCLK2_A */
	4184	+ [25] = SH_PFC_PIN_NONE,
	4185	+ [26] = SH_PFC_PIN_NONE,
	4186	+ [27] = SH_PFC_PIN_NONE,
	4187	+ [28] = SH_PFC_PIN_NONE,
	4188	+ [29] = SH_PFC_PIN_NONE,
	4189	+ [30] = SH_PFC_PIN_NONE,
	4190	+ [31] = SH_PFC_PIN_NONE,
	4191	+ } },
	4192	+ { PINMUX_BIAS_REG("PUEN3", 0xe60588c0, "PUD3", 0xe60588e0) {
	4193	+ [ 0] = RCAR_GP_PIN(3, 0), /* CAN_CLK */
	4194	+ [ 1] = RCAR_GP_PIN(3, 1), /* CANFD0_TX */
	4195	+ [ 2] = RCAR_GP_PIN(3, 2), /* CANFD0_RX */
	4196	+ [ 3] = RCAR_GP_PIN(3, 3), /* CANFD1_TX */
	4197	+ [ 4] = RCAR_GP_PIN(3, 4), /* CANFD1_RX */
	4198	+ [ 5] = RCAR_GP_PIN(3, 5), /* CANFD2_TX */
	4199	+ [ 6] = RCAR_GP_PIN(3, 6), /* CANFD2_RX */
	4200	+ [ 7] = RCAR_GP_PIN(3, 7), /* CANFD3_TX */
	4201	+ [ 8] = RCAR_GP_PIN(3, 8), /* CANFD3_RX */
	4202	+ [ 9] = RCAR_GP_PIN(3, 9), /* CANFD4_TX */
	4203	+ [10] = RCAR_GP_PIN(3, 10), /* CANFD4_RX */
	4204	+ [11] = RCAR_GP_PIN(3, 11), /* CANFD5_TX */
	4205	+ [12] = RCAR_GP_PIN(3, 12), /* CANFD5_RX */
	4206	+ [13] = RCAR_GP_PIN(3, 13), /* CANFD6_TX */
	4207	+ [14] = RCAR_GP_PIN(3, 14), /* CANFD6_RX */
	4208	+ [15] = RCAR_GP_PIN(3, 15), /* CANFD7_TX */
	4209	+ [16] = RCAR_GP_PIN(3, 16), /* CANFD7_RX */
	4210	+ [17] = SH_PFC_PIN_NONE,
	4211	+ [18] = SH_PFC_PIN_NONE,
	4212	+ [19] = SH_PFC_PIN_NONE,
	4213	+ [20] = SH_PFC_PIN_NONE,
	4214	+ [21] = SH_PFC_PIN_NONE,
	4215	+ [22] = SH_PFC_PIN_NONE,
	4216	+ [23] = SH_PFC_PIN_NONE,
	4217	+ [24] = SH_PFC_PIN_NONE,
	4218	+ [25] = SH_PFC_PIN_NONE,
	4219	+ [26] = SH_PFC_PIN_NONE,
	4220	+ [27] = SH_PFC_PIN_NONE,
	4221	+ [28] = SH_PFC_PIN_NONE,
	4222	+ [29] = SH_PFC_PIN_NONE,
	4223	+ [30] = SH_PFC_PIN_NONE,
	4224	+ [31] = SH_PFC_PIN_NONE,
	4225	+ } },
	4226	+ { PINMUX_BIAS_REG("PUEN4", 0xe60600c0, "PUD4", 0xe60600e0) {
	4227	+ [ 0] = RCAR_GP_PIN(4, 0), /* AVB0_RX_CTL */
	4228	+ [ 1] = RCAR_GP_PIN(4, 1), /* AVB0_RXC */
	4229	+ [ 2] = RCAR_GP_PIN(4, 2), /* AVB0_RD0 */
	4230	+ [ 3] = RCAR_GP_PIN(4, 3), /* AVB0_RD1 */
	4231	+ [ 4] = RCAR_GP_PIN(4, 4), /* AVB0_RD2 */
	4232	+ [ 5] = RCAR_GP_PIN(4, 5), /* AVB0_RD3 */
	4233	+ [ 6] = RCAR_GP_PIN(4, 6), /* AVB0_TX_CTL */
	4234	+ [ 7] = RCAR_GP_PIN(4, 7), /* AVB0_TXC */
	4235	+ [ 8] = RCAR_GP_PIN(4, 8), /* AVB0_TD0 */
	4236	+ [ 9] = RCAR_GP_PIN(4, 9), /* AVB0_TD1 */
	4237	+ [10] = RCAR_GP_PIN(4, 10), /* AVB0_TD2 */
	4238	+ [11] = RCAR_GP_PIN(4, 11), /* AVB0_TD3 */
	4239	+ [12] = RCAR_GP_PIN(4, 12), /* AVB0_TXREFCLK */
	4240	+ [13] = RCAR_GP_PIN(4, 13), /* AVB0_MDIO */
	4241	+ [14] = RCAR_GP_PIN(4, 14), /* AVB0_MDC */
	4242	+ [15] = RCAR_GP_PIN(4, 15), /* AVB0_MAGIC */
	4243	+ [16] = RCAR_GP_PIN(4, 16), /* AVB0_PHY_INT */
	4244	+ [17] = RCAR_GP_PIN(4, 17), /* AVB0_LINK */
	4245	+ [18] = RCAR_GP_PIN(4, 18), /* AVB0_AVTP_MATCH */
	4246	+ [19] = RCAR_GP_PIN(4, 19), /* AVB0_AVTP_CAPTURE */
	4247	+ [20] = RCAR_GP_PIN(4, 20), /* AVB0_AVTP_PPS */
	4248	+ [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */
	4249	+ [22] = RCAR_GP_PIN(4, 22), /* PCIE1_CLKREQ_N */
	4250	+ [23] = RCAR_GP_PIN(4, 23), /* PCIE2_CLKREQ_N */
	4251	+ [24] = RCAR_GP_PIN(4, 24), /* PCIE3_CLKREQ_N */
	4252	+ [25] = RCAR_GP_PIN(4, 25), /* AVS0 */
	4253	+ [26] = RCAR_GP_PIN(4, 26), /* AVS1 */
	4254	+ [27] = SH_PFC_PIN_NONE,
	4255	+ [28] = SH_PFC_PIN_NONE,
	4256	+ [29] = SH_PFC_PIN_NONE,
	4257	+ [30] = SH_PFC_PIN_NONE,
	4258	+ [31] = SH_PFC_PIN_NONE,
	4259	+ } },
	4260	+ { PINMUX_BIAS_REG("PUEN5", 0xe60608c0, "PUD5", 0xe60608e0) {
	4261	+ [ 0] = RCAR_GP_PIN(5, 0), /* AVB1_RX_CTL */
	4262	+ [ 1] = RCAR_GP_PIN(5, 1), /* AVB1_RXC */
	4263	+ [ 2] = RCAR_GP_PIN(5, 2), /* AVB1_RD0 */
	4264	+ [ 3] = RCAR_GP_PIN(5, 3), /* AVB1_RD1 */
	4265	+ [ 4] = RCAR_GP_PIN(5, 4), /* AVB1_RD2 */
	4266	+ [ 5] = RCAR_GP_PIN(5, 5), /* AVB1_RD3 */
	4267	+ [ 6] = RCAR_GP_PIN(5, 6), /* AVB1_TX_CTL */
	4268	+ [ 7] = RCAR_GP_PIN(5, 7), /* AVB1_TXC */
	4269	+ [ 8] = RCAR_GP_PIN(5, 8), /* AVB1_TD0 */
	4270	+ [ 9] = RCAR_GP_PIN(5, 9), /* AVB1_TD1 */
	4271	+ [10] = RCAR_GP_PIN(5, 10), /* AVB1_TD2 */
	4272	+ [11] = RCAR_GP_PIN(5, 11), /* AVB1_TD3 */
	4273	+ [12] = RCAR_GP_PIN(5, 12), /* AVB1_TXCREFCLK */
	4274	+ [13] = RCAR_GP_PIN(5, 13), /* AVB1_MDIO */
	4275	+ [14] = RCAR_GP_PIN(5, 14), /* AVB1_MDC */
	4276	+ [15] = RCAR_GP_PIN(5, 15), /* AVB1_MAGIC */
	4277	+ [16] = RCAR_GP_PIN(5, 16), /* AVB1_PHY_INT */
	4278	+ [17] = RCAR_GP_PIN(5, 17), /* AVB1_LINK */
	4279	+ [18] = RCAR_GP_PIN(5, 18), /* AVB1_AVTP_MATCH */
	4280	+ [19] = RCAR_GP_PIN(5, 19), /* AVB1_AVTP_CAPTURE */
	4281	+ [20] = RCAR_GP_PIN(5, 20), /* AVB1_AVTP_PPS */
	4282	+ [21] = SH_PFC_PIN_NONE,
	4283	+ [22] = SH_PFC_PIN_NONE,
	4284	+ [23] = SH_PFC_PIN_NONE,
	4285	+ [24] = SH_PFC_PIN_NONE,
	4286	+ [25] = SH_PFC_PIN_NONE,
	4287	+ [26] = SH_PFC_PIN_NONE,
	4288	+ [27] = SH_PFC_PIN_NONE,
	4289	+ [28] = SH_PFC_PIN_NONE,
	4290	+ [29] = SH_PFC_PIN_NONE,
	4291	+ [30] = SH_PFC_PIN_NONE,
	4292	+ [31] = SH_PFC_PIN_NONE,
	4293	+ } },
	4294	+ { PINMUX_BIAS_REG("PUEN6", 0xe60680c0, "PUD6", 0xe60680e0) {
	4295	+ [ 0] = RCAR_GP_PIN(6, 0), /* AVB2_RX_CTL */
	4296	+ [ 1] = RCAR_GP_PIN(6, 1), /* AVB2_RXC */
	4297	+ [ 2] = RCAR_GP_PIN(6, 2), /* AVB2_RD0 */
	4298	+ [ 3] = RCAR_GP_PIN(6, 3), /* AVB2_RD1 */
	4299	+ [ 4] = RCAR_GP_PIN(6, 4), /* AVB2_RD2 */
	4300	+ [ 5] = RCAR_GP_PIN(6, 5), /* AVB2_RD3 */
	4301	+ [ 6] = RCAR_GP_PIN(6, 6), /* AVB2_TX_CTL */
	4302	+ [ 7] = RCAR_GP_PIN(6, 7), /* AVB2_TXC */
	4303	+ [ 8] = RCAR_GP_PIN(6, 8), /* AVB2_TD0 */
	4304	+ [ 9] = RCAR_GP_PIN(6, 9), /* AVB2_TD1 */
	4305	+ [10] = RCAR_GP_PIN(6, 10), /* AVB2_TD2 */
	4306	+ [11] = RCAR_GP_PIN(6, 11), /* AVB2_TD3 */
	4307	+ [12] = RCAR_GP_PIN(6, 12), /* AVB2_TXCREFCLK */
	4308	+ [13] = RCAR_GP_PIN(6, 13), /* AVB2_MDIO */
	4309	+ [14] = RCAR_GP_PIN(6, 14), /* AVB2_MDC*/
	4310	+ [15] = RCAR_GP_PIN(6, 15), /* AVB2_MAGIC */
	4311	+ [16] = RCAR_GP_PIN(6, 16), /* AVB2_PHY_INT */
	4312	+ [17] = RCAR_GP_PIN(6, 17), /* AVB2_LINK */
	4313	+ [18] = RCAR_GP_PIN(6, 18), /* AVB2_AVTP_MATCH */
	4314	+ [19] = RCAR_GP_PIN(6, 19), /* AVB2_AVTP_CAPTURE */
	4315	+ [20] = RCAR_GP_PIN(6, 20), /* AVB2_AVTP_PPS */
	4316	+ [21] = SH_PFC_PIN_NONE,
	4317	+ [22] = SH_PFC_PIN_NONE,
	4318	+ [23] = SH_PFC_PIN_NONE,
	4319	+ [24] = SH_PFC_PIN_NONE,
	4320	+ [25] = SH_PFC_PIN_NONE,
	4321	+ [26] = SH_PFC_PIN_NONE,
	4322	+ [27] = SH_PFC_PIN_NONE,
	4323	+ [28] = SH_PFC_PIN_NONE,
	4324	+ [29] = SH_PFC_PIN_NONE,
	4325	+ [30] = SH_PFC_PIN_NONE,
	4326	+ [31] = SH_PFC_PIN_NONE,
	4327	+ } },
	4328	+ { PINMUX_BIAS_REG("PUEN7", 0xe60688c0, "PUD7", 0xe60688e0) {
	4329	+ [ 0] = RCAR_GP_PIN(7, 0), /* AVB3_RX_CTL */
	4330	+ [ 1] = RCAR_GP_PIN(7, 1), /* AVB3_RXC */
	4331	+ [ 2] = RCAR_GP_PIN(7, 2), /* AVB3_RD0 */
	4332	+ [ 3] = RCAR_GP_PIN(7, 3), /* AVB3_RD1 */
	4333	+ [ 4] = RCAR_GP_PIN(7, 4), /* AVB3_RD2 */
	4334	+ [ 5] = RCAR_GP_PIN(7, 5), /* AVB3_RD3 */
	4335	+ [ 6] = RCAR_GP_PIN(7, 6), /* AVB3_TX_CTL */
	4336	+ [ 7] = RCAR_GP_PIN(7, 7), /* AVB3_TXC */
	4337	+ [ 8] = RCAR_GP_PIN(7, 8), /* AVB3_TD0 */
	4338	+ [ 9] = RCAR_GP_PIN(7, 9), /* AVB3_TD1 */
	4339	+ [10] = RCAR_GP_PIN(7, 10), /* AVB3_TD2 */
	4340	+ [11] = RCAR_GP_PIN(7, 11), /* AVB3_TD3 */
	4341	+ [12] = RCAR_GP_PIN(7, 12), /* AVB3_TXCREFCLK */
	4342	+ [13] = RCAR_GP_PIN(7, 13), /* AVB3_MDIO */
	4343	+ [14] = RCAR_GP_PIN(7, 14), /* AVB3_MDC */
	4344	+ [15] = RCAR_GP_PIN(7, 15), /* AVB3_MAGIC */
	4345	+ [16] = RCAR_GP_PIN(7, 16), /* AVB3_PHY_INT */
	4346	+ [17] = RCAR_GP_PIN(7, 17), /* AVB3_LINK */
	4347	+ [18] = RCAR_GP_PIN(7, 18), /* AVB3_AVTP_MATCH */
	4348	+ [19] = RCAR_GP_PIN(7, 19), /* AVB3_AVTP_CAPTURE */
	4349	+ [20] = RCAR_GP_PIN(7, 20), /* AVB3_AVTP_PPS */
	4350	+ [21] = SH_PFC_PIN_NONE,
	4351	+ [22] = SH_PFC_PIN_NONE,
	4352	+ [23] = SH_PFC_PIN_NONE,
	4353	+ [24] = SH_PFC_PIN_NONE,
	4354	+ [25] = SH_PFC_PIN_NONE,
	4355	+ [26] = SH_PFC_PIN_NONE,
	4356	+ [27] = SH_PFC_PIN_NONE,
	4357	+ [28] = SH_PFC_PIN_NONE,
	4358	+ [29] = SH_PFC_PIN_NONE,
	4359	+ [30] = SH_PFC_PIN_NONE,
	4360	+ [31] = SH_PFC_PIN_NONE,
	4361	+ } },
	4362	+ { PINMUX_BIAS_REG("PUEN8", 0xe60690c0, "PUD8", 0xe60690e0) {
	4363	+ [ 0] = RCAR_GP_PIN(8, 0), /* AVB4_RX_CTL */
	4364	+ [ 1] = RCAR_GP_PIN(8, 1), /* AVB4_RXC */
	4365	+ [ 2] = RCAR_GP_PIN(8, 2), /* AVB4_RD0 */
	4366	+ [ 3] = RCAR_GP_PIN(8, 3), /* AVB4_RD1 */
	4367	+ [ 4] = RCAR_GP_PIN(8, 4), /* AVB4_RD2 */
	4368	+ [ 5] = RCAR_GP_PIN(8, 5), /* AVB4_RD3 */
	4369	+ [ 6] = RCAR_GP_PIN(8, 6), /* AVB4_TX_CTL */
	4370	+ [ 7] = RCAR_GP_PIN(8, 7), /* AVB4_TXC */
	4371	+ [ 8] = RCAR_GP_PIN(8, 8), /* AVB4_TD0 */
	4372	+ [ 9] = RCAR_GP_PIN(8, 9), /* AVB4_TD1 */
	4373	+ [10] = RCAR_GP_PIN(8, 10), /* AVB4_TD2 */
	4374	+ [11] = RCAR_GP_PIN(8, 11), /* AVB4_TD3 */
	4375	+ [12] = RCAR_GP_PIN(8, 12), /* AVB4_TXCREFCLK */
	4376	+ [13] = RCAR_GP_PIN(8, 13), /* AVB4_MDIO */
	4377	+ [14] = RCAR_GP_PIN(8, 14), /* AVB4_MDC */
	4378	+ [15] = RCAR_GP_PIN(8, 15), /* AVB4_MAGIC */
	4379	+ [16] = RCAR_GP_PIN(8, 16), /* AVB4_PHY_INT */
	4380	+ [17] = RCAR_GP_PIN(8, 17), /* AVB4_LINK */
	4381	+ [18] = RCAR_GP_PIN(8, 18), /* AVB4_AVTP_MATCH */
	4382	+ [19] = RCAR_GP_PIN(8, 19), /* AVB4_AVTP_CAPTURE */
	4383	+ [20] = RCAR_GP_PIN(8, 20), /* AVB4_AVTP_PPS */
	4384	+ [21] = SH_PFC_PIN_NONE,
	4385	+ [22] = SH_PFC_PIN_NONE,
	4386	+ [23] = SH_PFC_PIN_NONE,
	4387	+ [24] = SH_PFC_PIN_NONE,
	4388	+ [25] = SH_PFC_PIN_NONE,
	4389	+ [26] = SH_PFC_PIN_NONE,
	4390	+ [27] = SH_PFC_PIN_NONE,
	4391	+ [28] = SH_PFC_PIN_NONE,
	4392	+ [29] = SH_PFC_PIN_NONE,
	4393	+ [30] = SH_PFC_PIN_NONE,
	4394	+ [31] = SH_PFC_PIN_NONE,
	4395	+ } },
	4396	+ { PINMUX_BIAS_REG("PUEN9", 0xe60698c0, "PUD9", 0xe60698e0) {
	4397	+ [ 0] = RCAR_GP_PIN(9, 0), /* AVB5_RX_CTL */
	4398	+ [ 1] = RCAR_GP_PIN(9, 1), /* AVB5_RXC */
	4399	+ [ 2] = RCAR_GP_PIN(9, 2), /* AVB5_RD0 */
	4400	+ [ 3] = RCAR_GP_PIN(9, 3), /* AVB5_RD1 */
	4401	+ [ 4] = RCAR_GP_PIN(9, 4), /* AVB5_RD2 */
	4402	+ [ 5] = RCAR_GP_PIN(9, 5), /* AVB5_RD3 */
	4403	+ [ 6] = RCAR_GP_PIN(9, 6), /* AVB5_TX_CTL */
	4404	+ [ 7] = RCAR_GP_PIN(9, 7), /* AVB5_TXC */
	4405	+ [ 8] = RCAR_GP_PIN(9, 8), /* AVB5_TD0 */
	4406	+ [ 9] = RCAR_GP_PIN(9, 9), /* AVB5_TD1 */
	4407	+ [10] = RCAR_GP_PIN(9, 10), /* AVB5_TD2 */
	4408	+ [11] = RCAR_GP_PIN(9, 11), /* AVB5_TD3 */
	4409	+ [12] = RCAR_GP_PIN(9, 12), /* AVB5_TXCREFCLK */
	4410	+ [13] = RCAR_GP_PIN(9, 13), /* AVB5_MDIO */
	4411	+ [14] = RCAR_GP_PIN(9, 14), /* AVB5_MDC */
	4412	+ [15] = RCAR_GP_PIN(9, 15), /* AVB5_MAGIC */
	4413	+ [16] = RCAR_GP_PIN(9, 16), /* AVB5_PHY_INT */
	4414	+ [17] = RCAR_GP_PIN(9, 17), /* AVB5_LINK */
	4415	+ [18] = RCAR_GP_PIN(9, 18), /* AVB5_AVTP_MATCH */
	4416	+ [19] = RCAR_GP_PIN(9, 19), /* AVB5_AVTP_CAPTURE */
	4417	+ [20] = RCAR_GP_PIN(9, 20), /* AVB5_AVTP_PPS */
	4418	+ [21] = SH_PFC_PIN_NONE,
	4419	+ [22] = SH_PFC_PIN_NONE,
	4420	+ [23] = SH_PFC_PIN_NONE,
	4421	+ [24] = SH_PFC_PIN_NONE,
	4422	+ [25] = SH_PFC_PIN_NONE,
	4423	+ [26] = SH_PFC_PIN_NONE,
	4424	+ [27] = SH_PFC_PIN_NONE,
	4425	+ [28] = SH_PFC_PIN_NONE,
	4426	+ [29] = SH_PFC_PIN_NONE,
	4427	+ [30] = SH_PFC_PIN_NONE,
	4428	+ [31] = SH_PFC_PIN_NONE,
	4429	+ } },
	4430	+ { /* sentinel */ },
	4431	+};
	4432	+
	4433	+static const struct sh_pfc_soc_operations pinmux_ops = {
	4434	+ .pin_to_pocctrl = r8a779a0_pin_to_pocctrl,
	4435	+ .get_bias = rcar_pinmux_get_bias,
	4436	+ .set_bias = rcar_pinmux_set_bias,
	4437	+};
	4438	+
	4439	+const struct sh_pfc_soc_info r8a779a0_pinmux_info = {
	4440	+ .name = "r8a779a0_pfc",
	4441	+ .ops = &pinmux_ops,
	4442	+ .unlock_reg = 0x1ff, /* PMMRn mask */
	4443	+
	4444	+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
	4445	+
	4446	+ .pins = pinmux_pins,
	4447	+ .nr_pins = ARRAY_SIZE(pinmux_pins),
	4448	+ .groups = pinmux_groups,
	4449	+ .nr_groups = ARRAY_SIZE(pinmux_groups),
	4450	+ .functions = pinmux_functions,
	4451	+ .nr_functions = ARRAY_SIZE(pinmux_functions),
	4452	+
	4453	+ .cfg_regs = pinmux_config_regs,
	4454	+ .drive_regs = pinmux_drive_regs,
	4455	+ .bias_regs = pinmux_bias_regs,
	4456	+ .ioctrl_regs = pinmux_ioctrl_regs,
	4457	+
	4458	+ .pinmux_data = pinmux_data,
	4459	+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
	4460	+};

drivers/pinctrl/renesas/pinctrl.c+14−2

@@ -634,6 +634,9 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, · 633 unmodified lines
634	634	}
635	635
636	636	case PIN_CONFIG_POWER_SOURCE: {
	637	+ int idx = sh_pfc_get_pin_index(pfc, _pin);
	638	+ const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
	639	+ unsigned int lower_voltage;
637	640	u32 pocctrl, val;
638	641	int bit;
639	642
@@ -648,7 +651,10 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, · 8 unmodified lines
648	651	val = sh_pfc_read(pfc, pocctrl);
649	652	spin_unlock_irqrestore(&pfc->lock, flags);
650	653
651		− arg = (val & BIT(bit)) ? 3300 : 1800;
	654	+ lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
	655	+ 2500 : 1800;
	656	+
	657	+ arg = (val & BIT(bit)) ? 3300 : lower_voltage;
652	658	break;
653	659	}
654	660
@@ -702,6 +708,9 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, · 47 unmodified lines
702	708
703	709	case PIN_CONFIG_POWER_SOURCE: {
704	710	unsigned int mV = pinconf_to_config_argument(configs[i]);
	711	+ int idx = sh_pfc_get_pin_index(pfc, _pin);
	712	+ const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
	713	+ unsigned int lower_voltage;
705	714	u32 pocctrl, val;
706	715	int bit;
707	716
@@ -712,7 +721,10 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, · 4 unmodified lines
712	721	if (WARN(bit < 0, "invalid pin %#x", _pin))
713	722	return bit;
714	723
715		− if (mV != 1800 && mV != 3300)
	724	+ lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
	725	+ 2500 : 1800;
	726	+
	727	+ if (mV != lower_voltage && mV != 3300)
716	728	return -EINVAL;
717	729
718	730	spin_lock_irqsave(&pfc->lock, flags);

drivers/pinctrl/renesas/sh_pfc.h+23−5

@@ -31,6 +31,15 @@ enum { · 30 unmodified lines
31	31	SH_PFC_PIN_CFG_PULL_DOWN)
32	32	#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
33	33	#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
	34	+
	35	+#define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6)
	36	+#define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6)
	37	+
	38	+#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE \| \
	39	+ SH_PFC_PIN_VOLTAGE_18_33)
	40	+#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE \| \
	41	+ SH_PFC_PIN_VOLTAGE_25_33)
	42	+
34	43	#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
35	44
36	45	struct sh_pfc_pin {
@@ -300,7 +309,7 @@ struct sh_pfc_soc_info { · 263 unmodified lines
300	309	const u16 *pinmux_data;
301	310	unsigned int pinmux_data_size;
302	311
303		− u32 unlock_reg;
	312	+ u32 unlock_reg; /* can be literal address or mask */
304	313	};
305	314
306	315	extern const struct sh_pfc_soc_info emev2_pinmux_info;
@@ -331,6 +340,7 @@ extern const struct sh_pfc_soc_info r8a77970_pinmux_info; · 24 unmodified lines
331	340	extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
332	341	extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
333	342	extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
	343	+extern const struct sh_pfc_soc_info r8a779a0_pinmux_info;
334	344	extern const struct sh_pfc_soc_info sh7203_pinmux_info;
335	345	extern const struct sh_pfc_soc_info sh7264_pinmux_info;
336	346	extern const struct sh_pfc_soc_info sh7269_pinmux_info;
@@ -451,9 +461,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; · 114 unmodified lines
451	461	fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
452	462	#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
453	463
454		−#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
	464	+#define PORT_GP_CFG_2(bank, fn, sfx, cfg) \
455	465	PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
456		− PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
	466	+ PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
	467	+#define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0)
	468	+
	469	+#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
	470	+ PORT_GP_CFG_2(bank, fn, sfx, cfg), \
457	471	PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
458	472	PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
459	473	#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
@@ -572,9 +586,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; · 112 unmodified lines
572	586	PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
573	587	#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
574	588
575		−#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
	589	+#define PORT_GP_CFG_31(bank, fn, sfx, cfg) \
576	590	PORT_GP_CFG_30(bank, fn, sfx, cfg), \
577		− PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \
	591	+ PORT_GP_CFG_1(bank, 30, fn, sfx, cfg)
	592	+#define PORT_GP_31(bank, fn, sfx) PORT_GP_CFG_31(bank, fn, sfx, 0)
	593	+
	594	+#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
	595	+ PORT_GP_CFG_31(bank, fn, sfx, cfg), \
578	596	PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
579	597	#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
580	598

drivers/pinctrl/samsung/pinctrl-exynos.c+8−8

@@ -58,13 +58,13 @@ static void exynos_irq_mask(struct irq_data *irqd) · 57 unmodified lines
58	58	unsigned long mask;
59	59	unsigned long flags;
60	60
61		− spin_lock_irqsave(&bank->slock, flags);
	61	+ raw_spin_lock_irqsave(&bank->slock, flags);
62	62
63	63	mask = readl(bank->eint_base + reg_mask);
64	64	mask \|= 1 << irqd->hwirq;
65	65	writel(mask, bank->eint_base + reg_mask);
66	66
67		− spin_unlock_irqrestore(&bank->slock, flags);
	67	+ raw_spin_unlock_irqrestore(&bank->slock, flags);
68	68	}
69	69
70	70	static void exynos_irq_ack(struct irq_data *irqd)
@@ -97,13 +97,13 @@ static void exynos_irq_unmask(struct irq_data *irqd) · 26 unmodified lines
97	97	if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
98	98	exynos_irq_ack(irqd);
99	99
100		− spin_lock_irqsave(&bank->slock, flags);
	100	+ raw_spin_lock_irqsave(&bank->slock, flags);
101	101
102	102	mask = readl(bank->eint_base + reg_mask);
103	103	mask &= ~(1 << irqd->hwirq);
104	104	writel(mask, bank->eint_base + reg_mask);
105	105
106		− spin_unlock_irqrestore(&bank->slock, flags);
	106	+ raw_spin_unlock_irqrestore(&bank->slock, flags);
107	107	}
108	108
109	109	static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
@@ -169,14 +169,14 @@ static int exynos_irq_request_resources(struct irq_data *irqd) · 59 unmodified lines
169	169	shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
170	170	mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
171	171
172		− spin_lock_irqsave(&bank->slock, flags);
	172	+ raw_spin_lock_irqsave(&bank->slock, flags);
173	173
174	174	con = readl(bank->pctl_base + reg_con);
175	175	con &= ~(mask << shift);
176	176	con \|= EXYNOS_PIN_FUNC_EINT << shift;
177	177	writel(con, bank->pctl_base + reg_con);
178	178
179		− spin_unlock_irqrestore(&bank->slock, flags);
	179	+ raw_spin_unlock_irqrestore(&bank->slock, flags);
180	180
181	181	return 0;
182	182	}
@@ -192,14 +192,14 @@ static void exynos_irq_release_resources(struct irq_data *irqd) · 9 unmodified lines
192	192	shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
193	193	mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
194	194
195		− spin_lock_irqsave(&bank->slock, flags);
	195	+ raw_spin_lock_irqsave(&bank->slock, flags);
196	196
197	197	con = readl(bank->pctl_base + reg_con);
198	198	con &= ~(mask << shift);
199	199	con \|= EXYNOS_PIN_FUNC_INPUT << shift;
200	200	writel(con, bank->pctl_base + reg_con);
201	201
202		− spin_unlock_irqrestore(&bank->slock, flags);
	202	+ raw_spin_unlock_irqrestore(&bank->slock, flags);
203	203
204	204	gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
205	205	}

drivers/pinctrl/samsung/pinctrl-s3c24xx.c+2−2

@@ -145,14 +145,14 @@ static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d, · 144 unmodified lines
145	145	shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
146	146	mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
147	147
148		− spin_lock_irqsave(&bank->slock, flags);
	148	+ raw_spin_lock_irqsave(&bank->slock, flags);
149	149
150	150	val = readl(reg);
151	151	val &= ~(mask << shift);
152	152	val \|= bank->eint_func << shift;
153	153	writel(val, reg);
154	154
155		− spin_unlock_irqrestore(&bank->slock, flags);
	155	+ raw_spin_unlock_irqrestore(&bank->slock, flags);
156	156	}
157	157
158	158	static int s3c24xx_eint_type(struct irq_data *data, unsigned int type)

drivers/pinctrl/samsung/pinctrl-s3c64xx.c+2−2

@@ -286,14 +286,14 @@ static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d, · 285 unmodified lines
286	286	shift = shift * bank_type->fld_width[PINCFG_TYPE_FUNC];
287	287	mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
288	288
289		− spin_lock_irqsave(&bank->slock, flags);
	289	+ raw_spin_lock_irqsave(&bank->slock, flags);
290	290
291	291	val = readl(reg);
292	292	val &= ~(mask << shift);
293	293	val \|= bank->eint_func << shift;
294	294	writel(val, reg);
295	295
296		− spin_unlock_irqrestore(&bank->slock, flags);
	296	+ raw_spin_unlock_irqrestore(&bank->slock, flags);
297	297	}
298	298
299	299	/*

drivers/pinctrl/samsung/pinctrl-samsung.c+11−11

@@ -400,14 +400,14 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector, · 399 unmodified lines
400	400	reg += 4;
401	401	}
402	402
403		− spin_lock_irqsave(&bank->slock, flags);
	403	+ raw_spin_lock_irqsave(&bank->slock, flags);
404	404
405	405	data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]);
406	406	data &= ~(mask << shift);
407	407	data \|= func->val << shift;
408	408	writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]);
409	409
410		− spin_unlock_irqrestore(&bank->slock, flags);
	410	+ raw_spin_unlock_irqrestore(&bank->slock, flags);
411	411	}
412	412
413	413	/* enable a specified pinmux by writing to registers */
@@ -451,7 +451,7 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin, · 37 unmodified lines
451	451	width = type->fld_width[cfg_type];
452	452	cfg_reg = type->reg_offset[cfg_type];
453	453
454		− spin_lock_irqsave(&bank->slock, flags);
	454	+ raw_spin_lock_irqsave(&bank->slock, flags);
455	455
456	456	mask = (1 << width) - 1;
457	457	shift = pin_offset * width;
@@ -468,7 +468,7 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin, · 10 unmodified lines
468	468	*config = PINCFG_PACK(cfg_type, data);
469	469	}
470	470
471		− spin_unlock_irqrestore(&bank->slock, flags);
	471	+ raw_spin_unlock_irqrestore(&bank->slock, flags);
472	472
473	473	return 0;
474	474	}
@@ -561,9 +561,9 @@ static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value) · 86 unmodified lines
561	561	struct samsung_pin_bank *bank = gpiochip_get_data(gc);
562	562	unsigned long flags;
563	563
564		− spin_lock_irqsave(&bank->slock, flags);
	564	+ raw_spin_lock_irqsave(&bank->slock, flags);
565	565	samsung_gpio_set_value(gc, offset, value);
566		− spin_unlock_irqrestore(&bank->slock, flags);
	566	+ raw_spin_unlock_irqrestore(&bank->slock, flags);
567	567	}
568	568
569	569	/* gpiolib gpio_get callback function */
@@ -626,9 +626,9 @@ static int samsung_gpio_direction_input(struct gpio_chip *gc, unsigned offset) · 56 unmodified lines
626	626	unsigned long flags;
627	627	int ret;
628	628
629		− spin_lock_irqsave(&bank->slock, flags);
	629	+ raw_spin_lock_irqsave(&bank->slock, flags);
630	630	ret = samsung_gpio_set_direction(gc, offset, true);
631		− spin_unlock_irqrestore(&bank->slock, flags);
	631	+ raw_spin_unlock_irqrestore(&bank->slock, flags);
632	632	return ret;
633	633	}
634	634
@@ -640,10 +640,10 @@ static int samsung_gpio_direction_output(struct gpio_chip *gc, unsigned offset, · 5 unmodified lines
640	640	unsigned long flags;
641	641	int ret;
642	642
643		− spin_lock_irqsave(&bank->slock, flags);
	643	+ raw_spin_lock_irqsave(&bank->slock, flags);
644	644	samsung_gpio_set_value(gc, offset, value);
645	645	ret = samsung_gpio_set_direction(gc, offset, false);
646		− spin_unlock_irqrestore(&bank->slock, flags);
	646	+ raw_spin_unlock_irqrestore(&bank->slock, flags);
647	647
648	648	return ret;
649	649	}
@@ -1057,7 +1057,7 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, · 407 unmodified lines
1057	1057	bank->eint_offset = bdata->eint_offset;
1058	1058	bank->name = bdata->name;
1059	1059
1060		− spin_lock_init(&bank->slock);
	1060	+ raw_spin_lock_init(&bank->slock);
1061	1061	bank->drvdata = d;
1062	1062	bank->pin_base = d->nr_pins;
1063	1063	d->nr_pins += bank->nr_pins;

drivers/pinctrl/samsung/pinctrl-samsung.h+1−1

@@ -171,7 +171,7 @@ struct samsung_pin_bank { · 170 unmodified lines
171	171	struct gpio_chip gpio_chip;
172	172	struct pinctrl_gpio_range grange;
173	173	struct exynos_irq_chip *irq_chip;
174		− spinlock_t slock;
	174	+ raw_spinlock_t slock;
175	175
176	176	u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/
177	177	};

drivers/pinctrl/sirf/Makefile+0−7

@@ -1,7 +0,0 @@
1		−# SPDX-License-Identifier: GPL-2.0-only
2		−# CSR SiRFsoc pinmux support
3		−
4		−obj-y += pinctrl-sirf.o
5		−obj-y += pinctrl-prima2.o
6		−obj-y += pinctrl-atlas6.o
7		−obj-y += pinctrl-atlas7.o

drivers/pinctrl/sirf/pinctrl-atlas6.c+0−1137

@@ -1,1137 +0,0 @@
1		−// SPDX-License-Identifier: GPL-2.0-or-later
2		−/*
3		− * pinctrl pads, groups, functions for CSR SiRFatlasVI
4		− *
5		− * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
6		− * company.
7		− */
8		−
9		−#include <linux/pinctrl/pinctrl.h>
10		−#include <linux/bitops.h>
11		−
12		−#include "pinctrl-sirf.h"
13		−
14		−/*
15		− * pad list for the pinmux subsystem
16		− * refer to atlasVI_io_table_v0.93.xls
17		− */
18		−static const struct pinctrl_pin_desc sirfsoc_pads[] = {
19		− PINCTRL_PIN(0, "gpio0-0"),
20		− PINCTRL_PIN(1, "gpio0-1"),
21		− PINCTRL_PIN(2, "gpio0-2"),
22		− PINCTRL_PIN(3, "gpio0-3"),
23		− PINCTRL_PIN(4, "pwm0"),
24		− PINCTRL_PIN(5, "pwm1"),
25		− PINCTRL_PIN(6, "pwm2"),
26		− PINCTRL_PIN(7, "pwm3"),
27		− PINCTRL_PIN(8, "warm_rst_b"),
28		− PINCTRL_PIN(9, "odo_0"),
29		− PINCTRL_PIN(10, "odo_1"),
30		− PINCTRL_PIN(11, "dr_dir"),
31		− PINCTRL_PIN(12, "rts_0"),
32		− PINCTRL_PIN(13, "scl_1"),
33		− PINCTRL_PIN(14, "ntrst"),
34		− PINCTRL_PIN(15, "sda_1"),
35		− PINCTRL_PIN(16, "x_ldd[16]"),
36		− PINCTRL_PIN(17, "x_ldd[17]"),
37		− PINCTRL_PIN(18, "x_ldd[18]"),
38		− PINCTRL_PIN(19, "x_ldd[19]"),
39		− PINCTRL_PIN(20, "x_ldd[20]"),
40		− PINCTRL_PIN(21, "x_ldd[21]"),
41		− PINCTRL_PIN(22, "x_ldd[22]"),
42		− PINCTRL_PIN(23, "x_ldd[23]"),
43		− PINCTRL_PIN(24, "gps_sgn"),
44		− PINCTRL_PIN(25, "gps_mag"),
45		− PINCTRL_PIN(26, "gps_clk"),
46		− PINCTRL_PIN(27, "sd_cd_b_2"),
47		− PINCTRL_PIN(28, "sd_vcc_on_2"),
48		− PINCTRL_PIN(29, "sd_wp_b_2"),
49		− PINCTRL_PIN(30, "sd_clk_3"),
50		− PINCTRL_PIN(31, "sd_cmd_3"),
51		−
52		− PINCTRL_PIN(32, "x_sd_dat_3[0]"),
53		− PINCTRL_PIN(33, "x_sd_dat_3[1]"),
54		− PINCTRL_PIN(34, "x_sd_dat_3[2]"),
55		− PINCTRL_PIN(35, "x_sd_dat_3[3]"),
56		− PINCTRL_PIN(36, "usb_clk"),
57		− PINCTRL_PIN(37, "usb_dir"),
58		− PINCTRL_PIN(38, "usb_nxt"),
59		− PINCTRL_PIN(39, "usb_stp"),
60		− PINCTRL_PIN(40, "usb_dat[7]"),
61		− PINCTRL_PIN(41, "usb_dat[6]"),
62		− PINCTRL_PIN(42, "x_cko_1"),
63		− PINCTRL_PIN(43, "spi_clk_1"),
64		− PINCTRL_PIN(44, "spi_dout_1"),
65		− PINCTRL_PIN(45, "spi_din_1"),
66		− PINCTRL_PIN(46, "spi_en_1"),
67		− PINCTRL_PIN(47, "x_txd_1"),
68		− PINCTRL_PIN(48, "x_txd_2"),
69		− PINCTRL_PIN(49, "x_rxd_1"),
70		− PINCTRL_PIN(50, "x_rxd_2"),
71		− PINCTRL_PIN(51, "x_usclk_0"),
72		− PINCTRL_PIN(52, "x_utxd_0"),
73		− PINCTRL_PIN(53, "x_urxd_0"),
74		− PINCTRL_PIN(54, "x_utfs_0"),
75		− PINCTRL_PIN(55, "x_urfs_0"),
76		− PINCTRL_PIN(56, "usb_dat5"),
77		− PINCTRL_PIN(57, "usb_dat4"),
78		− PINCTRL_PIN(58, "usb_dat3"),
79		− PINCTRL_PIN(59, "usb_dat2"),
80		− PINCTRL_PIN(60, "usb_dat1"),
81		− PINCTRL_PIN(61, "usb_dat0"),
82		− PINCTRL_PIN(62, "x_ldd[14]"),
83		− PINCTRL_PIN(63, "x_ldd[15]"),
84		−
85		− PINCTRL_PIN(64, "x_gps_gpio"),
86		− PINCTRL_PIN(65, "x_ldd[13]"),
87		− PINCTRL_PIN(66, "x_df_we_b"),
88		− PINCTRL_PIN(67, "x_df_re_b"),
89		− PINCTRL_PIN(68, "x_txd_0"),
90		− PINCTRL_PIN(69, "x_rxd_0"),
91		− PINCTRL_PIN(70, "x_l_lck"),
92		− PINCTRL_PIN(71, "x_l_fck"),
93		− PINCTRL_PIN(72, "x_l_de"),
94		− PINCTRL_PIN(73, "x_ldd[0]"),
95		− PINCTRL_PIN(74, "x_ldd[1]"),
96		− PINCTRL_PIN(75, "x_ldd[2]"),
97		− PINCTRL_PIN(76, "x_ldd[3]"),
98		− PINCTRL_PIN(77, "x_ldd[4]"),
99		− PINCTRL_PIN(78, "x_cko_0"),
100		− PINCTRL_PIN(79, "x_ldd[5]"),
101		− PINCTRL_PIN(80, "x_ldd[6]"),
102		− PINCTRL_PIN(81, "x_ldd[7]"),
103		− PINCTRL_PIN(82, "x_ldd[8]"),
104		− PINCTRL_PIN(83, "x_ldd[9]"),
105		− PINCTRL_PIN(84, "x_ldd[10]"),
106		− PINCTRL_PIN(85, "x_ldd[11]"),
107		− PINCTRL_PIN(86, "x_ldd[12]"),
108		− PINCTRL_PIN(87, "x_vip_vsync"),
109		− PINCTRL_PIN(88, "x_vip_hsync"),
110		− PINCTRL_PIN(89, "x_vip_pxclk"),
111		− PINCTRL_PIN(90, "x_sda_0"),
112		− PINCTRL_PIN(91, "x_scl_0"),
113		− PINCTRL_PIN(92, "x_df_ry_by"),
114		− PINCTRL_PIN(93, "x_df_cs_b[1]"),
115		− PINCTRL_PIN(94, "x_df_cs_b[0]"),
116		− PINCTRL_PIN(95, "x_l_pclk"),
117		−
118		− PINCTRL_PIN(96, "x_df_dqs"),
119		− PINCTRL_PIN(97, "x_df_wp_b"),
120		− PINCTRL_PIN(98, "ac97_sync"),
121		− PINCTRL_PIN(99, "ac97_bit_clk "),
122		− PINCTRL_PIN(100, "ac97_dout"),
123		− PINCTRL_PIN(101, "ac97_din"),
124		− PINCTRL_PIN(102, "x_rtc_io"),
125		−
126		− PINCTRL_PIN(103, "x_usb1_dp"),
127		− PINCTRL_PIN(104, "x_usb1_dn"),
128		−};
129		−
130		−static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
131		− {
132		− .group = 1,
133		− .mask = BIT(30) \| BIT(31),
134		− }, {
135		− .group = 2,
136		− .mask = BIT(1) \| BIT(6) \| BIT(7) \| BIT(8) \| BIT(9) \|
137		− BIT(10) \| BIT(11) \| BIT(12) \| BIT(13) \| BIT(15) \|
138		− BIT(16) \| BIT(17) \| BIT(18) \| BIT(19) \|
139		− BIT(20) \| BIT(21) \| BIT(22) \| BIT(31),
140		− },
141		−};
142		−
143		−static const struct sirfsoc_padmux lcd_16bits_padmux = {
144		− .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
145		− .muxmask = lcd_16bits_sirfsoc_muxmask,
146		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
147		− .funcmask = BIT(4),
148		− .funcval = 0,
149		−};
150		−
151		−static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75,
152		− 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 };
153		−
154		−static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
155		− {
156		− .group = 2,
157		− .mask = BIT(1) \| BIT(6) \| BIT(7) \| BIT(8) \| BIT(9) \|
158		− BIT(10) \| BIT(11) \| BIT(12) \| BIT(13) \| BIT(15) \|
159		− BIT(16) \| BIT(17) \| BIT(18) \| BIT(19) \|
160		− BIT(20) \| BIT(21) \| BIT(22) \| BIT(31),
161		− }, {
162		− .group = 1,
163		− .mask = BIT(30) \| BIT(31),
164		− }, {
165		− .group = 0,
166		− .mask = BIT(16) \| BIT(17),
167		− },
168		−};
169		−
170		−static const struct sirfsoc_padmux lcd_18bits_padmux = {
171		− .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
172		− .muxmask = lcd_18bits_muxmask,
173		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
174		− .funcmask = BIT(4) \| BIT(15),
175		− .funcval = 0,
176		−};
177		−
178		−static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73,
179		− 74, 75, 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 };
180		−
181		−static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
182		− {
183		− .group = 2,
184		− .mask = BIT(1) \| BIT(6) \| BIT(7) \| BIT(8) \| BIT(9) \|
185		− BIT(10) \| BIT(11) \| BIT(12) \| BIT(13) \| BIT(15) \|
186		− BIT(16) \| BIT(17) \| BIT(18) \| BIT(19) \|
187		− BIT(20) \| BIT(21) \| BIT(22) \| BIT(31),
188		− }, {
189		− .group = 1,
190		− .mask = BIT(30) \| BIT(31),
191		− }, {
192		− .group = 0,
193		− .mask = BIT(16) \| BIT(17) \| BIT(18) \| BIT(19) \| BIT(20) \|
194		− BIT(21) \| BIT(22) \| BIT(23),
195		− },
196		−};
197		−
198		−static const struct sirfsoc_padmux lcd_24bits_padmux = {
199		− .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
200		− .muxmask = lcd_24bits_muxmask,
201		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
202		− .funcmask = BIT(4) \| BIT(15),
203		− .funcval = 0,
204		−};
205		−
206		−static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62,
207		− 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 84,
208		− 85, 86, 95};
209		−
210		−static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
211		− {
212		− .group = 2,
213		− .mask = BIT(1) \| BIT(6) \| BIT(7) \| BIT(8) \| BIT(9) \| BIT(10) \|
214		− BIT(11) \| BIT(12) \| BIT(13) \| BIT(15) \| BIT(16) \|
215		− BIT(17) \| BIT(18) \| BIT(19) \|
216		− BIT(20) \| BIT(21) \| BIT(22) \| BIT(31),
217		− }, {
218		− .group = 1,
219		− .mask = BIT(30) \| BIT(31),
220		− }, {
221		− .group = 0,
222		− .mask = BIT(8),
223		− },
224		−};
225		−
226		−static const struct sirfsoc_padmux lcdrom_padmux = {
227		− .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
228		− .muxmask = lcdrom_muxmask,
229		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
230		− .funcmask = BIT(4),
231		− .funcval = BIT(4),
232		−};
233		−
234		−static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75,
235		− 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95};
236		−
237		−static const struct sirfsoc_muxmask uart0_muxmask[] = {
238		− {
239		− .group = 0,
240		− .mask = BIT(12),
241		− }, {
242		− .group = 1,
243		− .mask = BIT(23),
244		− }, {
245		− .group = 2,
246		− .mask = BIT(4) \| BIT(5),
247		− },
248		−};
249		−
250		−static const struct sirfsoc_padmux uart0_padmux = {
251		− .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
252		− .muxmask = uart0_muxmask,
253		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
254		− .funcmask = BIT(9),
255		− .funcval = BIT(9),
256		−};
257		−
258		−static const unsigned uart0_pins[] = { 12, 55, 68, 69 };
259		−
260		−static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
261		− {
262		− .group = 2,
263		− .mask = BIT(4) \| BIT(5),
264		− },
265		−};
266		−
267		−static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
268		− .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
269		− .muxmask = uart0_nostreamctrl_muxmask,
270		−};
271		−
272		−static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
273		−
274		−static const struct sirfsoc_muxmask uart1_muxmask[] = {
275		− {
276		− .group = 1,
277		− .mask = BIT(15) \| BIT(17),
278		− },
279		−};
280		−
281		−static const struct sirfsoc_padmux uart1_padmux = {
282		− .muxmask_counts = ARRAY_SIZE(uart1_muxmask),
283		− .muxmask = uart1_muxmask,
284		−};
285		−
286		−static const unsigned uart1_pins[] = { 47, 49 };
287		−
288		−static const struct sirfsoc_muxmask uart2_muxmask[] = {
289		− {
290		− .group = 0,
291		− .mask = BIT(10) \| BIT(14),
292		− }, {
293		− .group = 1,
294		− .mask = BIT(16) \| BIT(18),
295		− },
296		−};
297		−
298		−static const struct sirfsoc_padmux uart2_padmux = {
299		− .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
300		− .muxmask = uart2_muxmask,
301		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
302		− .funcmask = BIT(10),
303		− .funcval = BIT(10),
304		−};
305		−
306		−static const unsigned uart2_pins[] = { 10, 14, 48, 50 };
307		−
308		−static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
309		− {
310		− .group = 1,
311		− .mask = BIT(16) \| BIT(18),
312		− },
313		−};
314		−
315		−static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
316		− .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
317		− .muxmask = uart2_nostreamctrl_muxmask,
318		−};
319		−
320		−static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
321		−
322		−static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
323		− {
324		− .group = 0,
325		− .mask = BIT(30) \| BIT(31),
326		− }, {
327		− .group = 1,
328		− .mask = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3),
329		− },
330		−};
331		−
332		−static const struct sirfsoc_padmux sdmmc3_padmux = {
333		− .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
334		− .muxmask = sdmmc3_muxmask,
335		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
336		− .funcmask = BIT(7),
337		− .funcval = 0,
338		−};
339		−
340		−static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
341		−
342		−static const struct sirfsoc_muxmask spi0_muxmask[] = {
343		− {
344		− .group = 0,
345		− .mask = BIT(30),
346		− }, {
347		− .group = 1,
348		− .mask = BIT(0) \| BIT(2) \| BIT(3),
349		− },
350		−};
351		−
352		−static const struct sirfsoc_padmux spi0_padmux = {
353		− .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
354		− .muxmask = spi0_muxmask,
355		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
356		− .funcmask = BIT(7),
357		− .funcval = BIT(7),
358		−};
359		−
360		−static const unsigned spi0_pins[] = { 30, 32, 34, 35 };
361		−
362		−static const struct sirfsoc_muxmask cko1_muxmask[] = {
363		− {
364		− .group = 1,
365		− .mask = BIT(10),
366		− },
367		−};
368		−
369		−static const struct sirfsoc_padmux cko1_padmux = {
370		− .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
371		− .muxmask = cko1_muxmask,
372		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
373		− .funcmask = BIT(3),
374		− .funcval = 0,
375		−};
376		−
377		−static const unsigned cko1_pins[] = { 42 };
378		−
379		−static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
380		− {
381		− .group = 1,
382		− .mask = BIT(10),
383		− },
384		−};
385		−
386		−static const struct sirfsoc_padmux i2s_mclk_padmux = {
387		− .muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
388		− .muxmask = i2s_mclk_muxmask,
389		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
390		− .funcmask = BIT(3),
391		− .funcval = BIT(3),
392		−};
393		−
394		−static const unsigned i2s_mclk_pins[] = { 42 };
395		−
396		−static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = {
397		− {
398		− .group = 1,
399		− .mask = BIT(19),
400		− },
401		−};
402		−
403		−static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = {
404		− .muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask),
405		− .muxmask = i2s_ext_clk_input_muxmask,
406		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
407		− .funcmask = BIT(2),
408		− .funcval = BIT(2),
409		−};
410		−
411		−static const unsigned i2s_ext_clk_input_pins[] = { 51 };
412		−
413		−static const struct sirfsoc_muxmask i2s_muxmask[] = {
414		− {
415		− .group = 3,
416		− .mask = BIT(2) \| BIT(3) \| BIT(4) \| BIT(5),
417		− },
418		−};
419		−
420		−static const struct sirfsoc_padmux i2s_padmux = {
421		− .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
422		− .muxmask = i2s_muxmask,
423		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
424		−};
425		−
426		−static const unsigned i2s_pins[] = { 98, 99, 100, 101 };
427		−
428		−static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
429		− {
430		− .group = 3,
431		− .mask = BIT(2) \| BIT(3) \| BIT(4),
432		− },
433		−};
434		−
435		−static const struct sirfsoc_padmux i2s_no_din_padmux = {
436		− .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
437		− .muxmask = i2s_no_din_muxmask,
438		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
439		−};
440		−
441		−static const unsigned i2s_no_din_pins[] = { 98, 99, 100 };
442		−
443		−static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
444		− {
445		− .group = 3,
446		− .mask = BIT(2) \| BIT(3) \| BIT(4) \| BIT(5),
447		− },
448		−};
449		−
450		−static const struct sirfsoc_padmux i2s_6chn_padmux = {
451		− .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
452		− .muxmask = i2s_6chn_muxmask,
453		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
454		− .funcmask = BIT(1) \| BIT(9),
455		− .funcval = BIT(1) \| BIT(9),
456		−};
457		−
458		−static const unsigned i2s_6chn_pins[] = { 52, 55, 98, 99, 100, 101 };
459		−
460		−static const struct sirfsoc_muxmask ac97_muxmask[] = {
461		− {
462		− .group = 3,
463		− .mask = BIT(2) \| BIT(3) \| BIT(4) \| BIT(5),
464		− },
465		−};
466		−
467		−static const struct sirfsoc_padmux ac97_padmux = {
468		− .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
469		− .muxmask = ac97_muxmask,
470		−};
471		−
472		−static const unsigned ac97_pins[] = { 98, 99, 100, 101 };
473		−
474		−static const struct sirfsoc_muxmask spi1_muxmask[] = {
475		− {
476		− .group = 1,
477		− .mask = BIT(11) \| BIT(12) \| BIT(13) \| BIT(14),
478		− },
479		−};
480		−
481		−static const struct sirfsoc_padmux spi1_padmux = {
482		− .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
483		− .muxmask = spi1_muxmask,
484		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
485		− .funcmask = BIT(16),
486		− .funcval = 0,
487		−};
488		−
489		−static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
490		−
491		−static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
492		− {
493		− .group = 2,
494		− .mask = BIT(2) \| BIT(3),
495		− },
496		−};
497		−
498		−static const struct sirfsoc_padmux sdmmc1_padmux = {
499		− .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
500		− .muxmask = sdmmc1_muxmask,
501		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
502		− .funcmask = BIT(5),
503		− .funcval = BIT(5),
504		−};
505		−
506		−static const unsigned sdmmc1_pins[] = { 66, 67 };
507		−
508		−static const struct sirfsoc_muxmask gps_muxmask[] = {
509		− {
510		− .group = 0,
511		− .mask = BIT(24) \| BIT(25) \| BIT(26),
512		− },
513		−};
514		−
515		−static const struct sirfsoc_padmux gps_padmux = {
516		− .muxmask_counts = ARRAY_SIZE(gps_muxmask),
517		− .muxmask = gps_muxmask,
518		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
519		− .funcmask = BIT(13),
520		− .funcval = 0,
521		−};
522		−
523		−static const unsigned gps_pins[] = { 24, 25, 26 };
524		−
525		−static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
526		− {
527		− .group = 0,
528		− .mask = BIT(24) \| BIT(25) \| BIT(26),
529		− },
530		−};
531		−
532		−static const struct sirfsoc_padmux sdmmc5_padmux = {
533		− .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
534		− .muxmask = sdmmc5_muxmask,
535		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
536		− .funcmask = BIT(13),
537		− .funcval = BIT(13),
538		−};
539		−
540		−static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
541		−
542		−static const struct sirfsoc_muxmask usp0_muxmask[] = {
543		− {
544		− .group = 1,
545		− .mask = BIT(19) \| BIT(20) \| BIT(21) \| BIT(22) \| BIT(23),
546		− },
547		−};
548		−
549		−static const struct sirfsoc_padmux usp0_padmux = {
550		− .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
551		− .muxmask = usp0_muxmask,
552		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
553		− .funcmask = BIT(1) \| BIT(2) \| BIT(9),
554		− .funcval = 0,
555		−};
556		−
557		−static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
558		−
559		−static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = {
560		− {
561		− .group = 1,
562		− .mask = BIT(19) \| BIT(20) \| BIT(21) \| BIT(22),
563		− },
564		−};
565		−
566		−static const struct sirfsoc_padmux usp0_only_utfs_padmux = {
567		− .muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask),
568		− .muxmask = usp0_only_utfs_muxmask,
569		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
570		− .funcmask = BIT(1) \| BIT(2) \| BIT(6),
571		− .funcval = 0,
572		−};
573		−
574		−static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 };
575		−
576		−static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = {
577		− {
578		− .group = 1,
579		− .mask = BIT(19) \| BIT(20) \| BIT(21) \| BIT(23),
580		− },
581		−};
582		−
583		−static const struct sirfsoc_padmux usp0_only_urfs_padmux = {
584		− .muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask),
585		− .muxmask = usp0_only_urfs_muxmask,
586		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
587		− .funcmask = BIT(1) \| BIT(2) \| BIT(9),
588		− .funcval = 0,
589		−};
590		−
591		−static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 };
592		−
593		−static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
594		− {
595		− .group = 1,
596		− .mask = BIT(20) \| BIT(21),
597		− },
598		−};
599		−
600		−static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
601		− .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
602		− .muxmask = usp0_uart_nostreamctrl_muxmask,
603		−};
604		−
605		−static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
606		−static const struct sirfsoc_muxmask usp1_muxmask[] = {
607		− {
608		− .group = 0,
609		− .mask = BIT(15),
610		− }, {
611		− .group = 1,
612		− .mask = BIT(11) \| BIT(12) \| BIT(13) \| BIT(14),
613		− },
614		−};
615		−
616		−static const struct sirfsoc_padmux usp1_padmux = {
617		− .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
618		− .muxmask = usp1_muxmask,
619		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
620		− .funcmask = BIT(16),
621		− .funcval = BIT(16),
622		−};
623		−
624		−static const unsigned usp1_pins[] = { 15, 43, 44, 45, 46 };
625		−
626		−static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
627		− {
628		− .group = 1,
629		− .mask = BIT(12) \| BIT(13),
630		− },
631		−};
632		−
633		−static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
634		− .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
635		− .muxmask = usp1_uart_nostreamctrl_muxmask,
636		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
637		− .funcmask = BIT(16),
638		− .funcval = BIT(16),
639		−};
640		−
641		−static const unsigned usp1_uart_nostreamctrl_pins[] = { 44, 45 };
642		−
643		−static const struct sirfsoc_muxmask nand_muxmask[] = {
644		− {
645		− .group = 2,
646		− .mask = BIT(2) \| BIT(3) \| BIT(28) \| BIT(29) \| BIT(30),
647		− }, {
648		− .group = 3,
649		− .mask = BIT(0) \| BIT(1),
650		− },
651		−};
652		−
653		−static const struct sirfsoc_padmux nand_padmux = {
654		− .muxmask_counts = ARRAY_SIZE(nand_muxmask),
655		− .muxmask = nand_muxmask,
656		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
657		− .funcmask = BIT(5) \| BIT(19),
658		− .funcval = 0,
659		−};
660		−
661		−static const unsigned nand_pins[] = { 66, 67, 92, 93, 94, 96, 97 };
662		−
663		−static const struct sirfsoc_muxmask sdmmc0_muxmask[] = {
664		− {
665		− .group = 3,
666		− .mask = BIT(1),
667		− },
668		−};
669		−
670		−static const struct sirfsoc_padmux sdmmc0_padmux = {
671		− .muxmask_counts = ARRAY_SIZE(sdmmc0_muxmask),
672		− .muxmask = sdmmc0_muxmask,
673		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
674		− .funcmask = BIT(5) \| BIT(19),
675		− .funcval = BIT(19),
676		−};
677		−
678		−static const unsigned sdmmc0_pins[] = { 97 };
679		−
680		−static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
681		− {
682		− .group = 0,
683		− .mask = BIT(27) \| BIT(28) \| BIT(29),
684		− },
685		−};
686		−
687		−static const struct sirfsoc_padmux sdmmc2_padmux = {
688		− .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
689		− .muxmask = sdmmc2_muxmask,
690		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
691		− .funcmask = BIT(11),
692		− .funcval = 0,
693		−};
694		−
695		−static const unsigned sdmmc2_pins[] = { 27, 28, 29 };
696		−
697		−static const struct sirfsoc_muxmask sdmmc2_nowp_muxmask[] = {
698		− {
699		− .group = 0,
700		− .mask = BIT(27) \| BIT(28),
701		− },
702		−};
703		−
704		−static const struct sirfsoc_padmux sdmmc2_nowp_padmux = {
705		− .muxmask_counts = ARRAY_SIZE(sdmmc2_nowp_muxmask),
706		− .muxmask = sdmmc2_nowp_muxmask,
707		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
708		− .funcmask = BIT(11),
709		− .funcval = 0,
710		−};
711		−
712		−static const unsigned sdmmc2_nowp_pins[] = { 27, 28 };
713		−
714		−static const struct sirfsoc_muxmask cko0_muxmask[] = {
715		− {
716		− .group = 2,
717		− .mask = BIT(14),
718		− },
719		−};
720		−
721		−static const struct sirfsoc_padmux cko0_padmux = {
722		− .muxmask_counts = ARRAY_SIZE(cko0_muxmask),
723		− .muxmask = cko0_muxmask,
724		−};
725		−
726		−static const unsigned cko0_pins[] = { 78 };
727		−
728		−static const struct sirfsoc_muxmask vip_muxmask[] = {
729		− {
730		− .group = 1,
731		− .mask = BIT(4) \| BIT(5) \| BIT(6) \| BIT(8) \| BIT(9)
732		− \| BIT(24) \| BIT(25) \| BIT(26) \| BIT(27) \| BIT(28) \|
733		− BIT(29),
734		− },
735		−};
736		−
737		−static const struct sirfsoc_padmux vip_padmux = {
738		− .muxmask_counts = ARRAY_SIZE(vip_muxmask),
739		− .muxmask = vip_muxmask,
740		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
741		− .funcmask = BIT(18),
742		− .funcval = BIT(18),
743		−};
744		−
745		−static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59,
746		− 60, 61 };
747		−
748		−static const struct sirfsoc_muxmask vip_noupli_muxmask[] = {
749		− {
750		− .group = 0,
751		− .mask = BIT(16) \| BIT(17) \| BIT(18) \| BIT(19) \| BIT(20)
752		− \| BIT(21) \| BIT(22) \| BIT(23),
753		− }, {
754		− .group = 2,
755		− .mask = BIT(23) \| BIT(24) \| BIT(25),
756		− },
757		−};
758		−
759		−static const struct sirfsoc_padmux vip_noupli_padmux = {
760		− .muxmask_counts = ARRAY_SIZE(vip_noupli_muxmask),
761		− .muxmask = vip_noupli_muxmask,
762		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
763		− .funcmask = BIT(15),
764		− .funcval = BIT(15),
765		−};
766		−
767		−static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23,
768		− 87, 88, 89 };
769		−
770		−static const struct sirfsoc_muxmask i2c0_muxmask[] = {
771		− {
772		− .group = 2,
773		− .mask = BIT(26) \| BIT(27),
774		− },
775		−};
776		−
777		−static const struct sirfsoc_padmux i2c0_padmux = {
778		− .muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
779		− .muxmask = i2c0_muxmask,
780		−};
781		−
782		−static const unsigned i2c0_pins[] = { 90, 91 };
783		−
784		−static const struct sirfsoc_muxmask i2c1_muxmask[] = {
785		− {
786		− .group = 0,
787		− .mask = BIT(13) \| BIT(15),
788		− },
789		−};
790		−
791		−static const struct sirfsoc_padmux i2c1_padmux = {
792		− .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
793		− .muxmask = i2c1_muxmask,
794		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
795		− .funcmask = BIT(16),
796		− .funcval = 0,
797		−};
798		−
799		−static const unsigned i2c1_pins[] = { 13, 15 };
800		−
801		−static const struct sirfsoc_muxmask pwm0_muxmask[] = {
802		− {
803		− .group = 0,
804		− .mask = BIT(4),
805		− },
806		−};
807		−
808		−static const struct sirfsoc_padmux pwm0_padmux = {
809		− .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
810		− .muxmask = pwm0_muxmask,
811		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
812		− .funcmask = BIT(12),
813		− .funcval = 0,
814		−};
815		−
816		−static const unsigned pwm0_pins[] = { 4 };
817		−
818		−static const struct sirfsoc_muxmask pwm1_muxmask[] = {
819		− {
820		− .group = 0,
821		− .mask = BIT(5),
822		− },
823		−};
824		−
825		−static const struct sirfsoc_padmux pwm1_padmux = {
826		− .muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
827		− .muxmask = pwm1_muxmask,
828		−};
829		−
830		−static const unsigned pwm1_pins[] = { 5 };
831		−
832		−static const struct sirfsoc_muxmask pwm2_muxmask[] = {
833		− {
834		− .group = 0,
835		− .mask = BIT(6),
836		− },
837		−};
838		−
839		−static const struct sirfsoc_padmux pwm2_padmux = {
840		− .muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
841		− .muxmask = pwm2_muxmask,
842		−};
843		−
844		−static const unsigned pwm2_pins[] = { 6 };
845		−
846		−static const struct sirfsoc_muxmask pwm3_muxmask[] = {
847		− {
848		− .group = 0,
849		− .mask = BIT(7),
850		− },
851		−};
852		−
853		−static const struct sirfsoc_padmux pwm3_padmux = {
854		− .muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
855		− .muxmask = pwm3_muxmask,
856		−};
857		−
858		−static const unsigned pwm3_pins[] = { 7 };
859		−
860		−static const struct sirfsoc_muxmask pwm4_muxmask[] = {
861		− {
862		− .group = 2,
863		− .mask = BIT(14),
864		− },
865		−};
866		−
867		−static const struct sirfsoc_padmux pwm4_padmux = {
868		− .muxmask_counts = ARRAY_SIZE(pwm4_muxmask),
869		− .muxmask = pwm4_muxmask,
870		−};
871		−
872		−static const unsigned pwm4_pins[] = { 78 };
873		−
874		−static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
875		− {
876		− .group = 0,
877		− .mask = BIT(8),
878		− },
879		−};
880		−
881		−static const struct sirfsoc_padmux warm_rst_padmux = {
882		− .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
883		− .muxmask = warm_rst_muxmask,
884		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
885		− .funcmask = BIT(4),
886		− .funcval = 0,
887		−};
888		−
889		−static const unsigned warm_rst_pins[] = { 8 };
890		−
891		−static const struct sirfsoc_muxmask usb0_upli_drvbus_muxmask[] = {
892		− {
893		− .group = 1,
894		− .mask = BIT(4) \| BIT(5) \| BIT(6) \| BIT(7) \| BIT(8)
895		− \| BIT(9) \| BIT(24) \| BIT(25) \| BIT(26) \|
896		− BIT(27) \| BIT(28) \| BIT(29),
897		− },
898		−};
899		−static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = {
900		− .muxmask_counts = ARRAY_SIZE(usb0_upli_drvbus_muxmask),
901		− .muxmask = usb0_upli_drvbus_muxmask,
902		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
903		− .funcmask = BIT(18),
904		− .funcval = 0,
905		−};
906		−
907		−static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40,
908		− 41, 56, 57, 58, 59, 60, 61 };
909		−
910		−static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
911		− {
912		− .group = 0,
913		− .mask = BIT(28),
914		− },
915		−};
916		−
917		−static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
918		− .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
919		− .muxmask = usb1_utmi_drvbus_muxmask,
920		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
921		− .funcmask = BIT(11),
922		− .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
923		−};
924		−
925		−static const unsigned usb1_utmi_drvbus_pins[] = { 28 };
926		−
927		−static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
928		− .muxmask_counts = 0,
929		− .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
930		− .funcmask = BIT(2),
931		− .funcval = BIT(2),
932		−};
933		−
934		−static const unsigned usb1_dp_dn_pins[] = { 103, 104 };
935		−
936		−static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
937		− .muxmask_counts = 0,
938		− .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
939		− .funcmask = BIT(2),
940		− .funcval = 0,
941		−};
942		−
943		−static const unsigned uart1_route_io_usb1_pins[] = { 103, 104 };
944		−
945		−static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
946		− {
947		− .group = 0,
948		− .mask = BIT(9) \| BIT(10) \| BIT(11),
949		− },
950		−};
951		−
952		−static const struct sirfsoc_padmux pulse_count_padmux = {
953		− .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
954		− .muxmask = pulse_count_muxmask,
955		−};
956		−
957		−static const unsigned pulse_count_pins[] = { 9, 10, 11 };
958		−
959		−static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
960		− SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
961		− SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
962		− SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
963		− SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
964		− SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
965		− SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
966		− SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
967		− SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
968		− SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
969		− SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
970		− SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
971		− usp0_uart_nostreamctrl_pins),
972		− SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins),
973		− SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins),
974		− SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
975		− SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
976		− usp1_uart_nostreamctrl_pins),
977		− SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
978		− SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
979		− SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
980		− SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
981		− SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
982		− SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
983		− SIRFSOC_PIN_GROUP("pwm4grp", pwm4_pins),
984		− SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
985		− SIRFSOC_PIN_GROUP("vip_noupligrp", vip_noupli_pins),
986		− SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
987		− SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
988		− SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
989		− SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
990		− SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
991		− SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
992		− SIRFSOC_PIN_GROUP("sdmmc2_nowpgrp", sdmmc2_nowp_pins),
993		− SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
994		− SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
995		− SIRFSOC_PIN_GROUP("usb0_upli_drvbusgrp", usb0_upli_drvbus_pins),
996		− SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
997		− SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
998		− SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
999		− SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
1000		− SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
1001		− SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins),
1002		− SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
1003		− SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
1004		− SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
1005		− SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
1006		− SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
1007		− SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
1008		− SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
1009		− SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
1010		−};
1011		−
1012		−static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
1013		−static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
1014		−static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
1015		−static const char * const lcdromgrp[] = { "lcdromgrp" };
1016		−static const char * const uart0grp[] = { "uart0grp" };
1017		−static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
1018		−static const char * const uart1grp[] = { "uart1grp" };
1019		−static const char * const uart2grp[] = { "uart2grp" };
1020		−static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
1021		−static const char * const usp0_uart_nostreamctrl_grp[] = {
1022		− "usp0_uart_nostreamctrl_grp" };
1023		−static const char * const usp0grp[] = { "usp0grp" };
1024		−static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
1025		−static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
1026		−
1027		−static const char * const usp1grp[] = { "usp1grp" };
1028		−static const char * const usp1_uart_nostreamctrl_grp[] = {
1029		− "usp1_uart_nostreamctrl_grp" };
1030		−static const char * const i2c0grp[] = { "i2c0grp" };
1031		−static const char * const i2c1grp[] = { "i2c1grp" };
1032		−static const char * const pwm0grp[] = { "pwm0grp" };
1033		−static const char * const pwm1grp[] = { "pwm1grp" };
1034		−static const char * const pwm2grp[] = { "pwm2grp" };
1035		−static const char * const pwm3grp[] = { "pwm3grp" };
1036		−static const char * const pwm4grp[] = { "pwm4grp" };
1037		−static const char * const vipgrp[] = { "vipgrp" };
1038		−static const char * const vip_noupligrp[] = { "vip_noupligrp" };
1039		−static const char * const warm_rstgrp[] = { "warm_rstgrp" };
1040		−static const char * const cko0grp[] = { "cko0grp" };
1041		−static const char * const cko1grp[] = { "cko1grp" };
1042		−static const char * const sdmmc0grp[] = { "sdmmc0grp" };
1043		−static const char * const sdmmc1grp[] = { "sdmmc1grp" };
1044		−static const char * const sdmmc2grp[] = { "sdmmc2grp" };
1045		−static const char * const sdmmc3grp[] = { "sdmmc3grp" };
1046		−static const char * const sdmmc5grp[] = { "sdmmc5grp" };
1047		−static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" };
1048		−static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" };
1049		−static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
1050		−static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
1051		−static const char * const
1052		− uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
1053		−static const char * const pulse_countgrp[] = { "pulse_countgrp" };
1054		−static const char * const i2smclkgrp[] = { "i2smclkgrp" };
1055		−static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" };
1056		−static const char * const i2sgrp[] = { "i2sgrp" };
1057		−static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
1058		−static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
1059		−static const char * const ac97grp[] = { "ac97grp" };
1060		−static const char * const nandgrp[] = { "nandgrp" };
1061		−static const char * const spi0grp[] = { "spi0grp" };
1062		−static const char * const spi1grp[] = { "spi1grp" };
1063		−static const char * const gpsgrp[] = { "gpsgrp" };
1064		−
1065		−static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
1066		− SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
1067		− SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
1068		− SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
1069		− SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
1070		− SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
1071		− SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp,
1072		− uart0_nostreamctrl_padmux),
1073		− SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
1074		− SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
1075		− SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl",
1076		− uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
1077		− SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
1078		− SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
1079		− usp0_uart_nostreamctrl_grp,
1080		− usp0_uart_nostreamctrl_padmux),
1081		− SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp,
1082		− usp0_only_utfs_padmux),
1083		− SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp,
1084		− usp0_only_urfs_padmux),
1085		− SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
1086		− SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
1087		− usp1_uart_nostreamctrl_grp,
1088		− usp1_uart_nostreamctrl_padmux),
1089		− SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
1090		− SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
1091		− SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
1092		− SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
1093		− SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
1094		− SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
1095		− SIRFSOC_PMX_FUNCTION("pwm4", pwm4grp, pwm4_padmux),
1096		− SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
1097		− SIRFSOC_PMX_FUNCTION("vip_noupli", vip_noupligrp, vip_noupli_padmux),
1098		− SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
1099		− SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
1100		− SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
1101		− SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
1102		− SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
1103		− SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
1104		− SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
1105		− SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
1106		− SIRFSOC_PMX_FUNCTION("sdmmc2_nowp",
1107		− sdmmc2_nowpgrp, sdmmc2_nowp_padmux),
1108		− SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus",
1109		− usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux),
1110		− SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus",
1111		− usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
1112		− SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
1113		− SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
1114		− uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
1115		− SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
1116		− SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
1117		− SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp,
1118		− i2s_ext_clk_input_padmux),
1119		− SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
1120		− SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
1121		− SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
1122		− SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
1123		− SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
1124		− SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
1125		− SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
1126		− SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
1127		−};
1128		−
1129		−struct sirfsoc_pinctrl_data atlas6_pinctrl_data = {
1130		− (struct pinctrl_pin_desc *)sirfsoc_pads,
1131		− ARRAY_SIZE(sirfsoc_pads),
1132		− (struct sirfsoc_pin_group *)sirfsoc_pin_groups,
1133		− ARRAY_SIZE(sirfsoc_pin_groups),
1134		− (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
1135		− ARRAY_SIZE(sirfsoc_pmx_functions),
1136		−};
1137		−

drivers/pinctrl/sirf/pinctrl-atlas7.c+0−6157

@@ -1,6157 +0,0 @@
1		−// SPDX-License-Identifier: GPL-2.0-or-later
2		−/*
3		− * pinctrl pads, groups, functions for CSR SiRFatlasVII
4		− *
5		− * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
6		− * company.
7		− */
8		−
9		−#include <linux/init.h>
10		−#include <linux/platform_device.h>
11		−#include <linux/io.h>
12		−#include <linux/bitops.h>
13		−#include <linux/irq.h>
14		−#include <linux/slab.h>
15		−#include <linux/clk.h>
16		−#include <linux/of.h>
17		−#include <linux/of_address.h>
18		−#include <linux/of_device.h>
19		−#include <linux/of_platform.h>
20		−#include <linux/of_irq.h>
21		−#include <linux/pinctrl/machine.h>
22		−#include <linux/pinctrl/pinconf.h>
23		−#include <linux/pinctrl/pinctrl.h>
24		−#include <linux/pinctrl/pinmux.h>
25		−#include <linux/pinctrl/consumer.h>
26		−#include <linux/pinctrl/pinconf-generic.h>
27		−#include <linux/gpio/driver.h>
28		−
29		−/* Definition of Pad&Mux Properties */
30		−#define N 0
31		−
32		−/* The Bank contains input-disable regisgers */
33		−#define BANK_DS 0
34		−
35		−/* Clear Register offset */
36		−#define CLR_REG(r) ((r) + 0x04)
37		−
38		−/* Definition of multiple function select register */
39		−#define FUNC_CLEAR_MASK 0x7
40		−#define FUNC_GPIO 0
41		−#define FUNC_ANALOGUE 0x8
42		−#define ANA_CLEAR_MASK 0x1
43		−
44		−/* The Atlas7's Pad Type List */
45		−enum altas7_pad_type {
46		− PAD_T_4WE_PD = 0, /* ZIO_PAD3V_4WE_PD */
47		− PAD_T_4WE_PU, /* ZIO_PAD3V_4WE_PD */
48		− PAD_T_16ST, /* ZIO_PAD3V_SDCLK_PD */
49		− PAD_T_M31_0204_PD, /* PRDW0204SDGZ_M311311_PD */
50		− PAD_T_M31_0204_PU, /* PRDW0204SDGZ_M311311_PU */
51		− PAD_T_M31_0610_PD, /* PRUW0610SDGZ_M311311_PD */
52		− PAD_T_M31_0610_PU, /* PRUW0610SDGZ_M311311_PU */
53		− PAD_T_AD, /* PRDWUWHW08SCDG_HZ */
54		−};
55		−
56		−/* Raw value of Driver-Strength Bits */
57		−#define DS3 BIT(3)
58		−#define DS2 BIT(2)
59		−#define DS1 BIT(1)
60		−#define DS0 BIT(0)
61		−#define DSZ 0
62		−
63		−/* Drive-Strength Intermediate Values */
64		−#define DS_NULL -1
65		−#define DS_1BIT_IM_VAL DS0
66		−#define DS_1BIT_MASK 0x1
67		−#define DS_2BIT_IM_VAL (DS1 \| DS0)
68		−#define DS_2BIT_MASK 0x3
69		−#define DS_4BIT_IM_VAL (DS3 \| DS2 \| DS1 \| DS0)
70		−#define DS_4BIT_MASK 0xf
71		−
72		−/* The Drive-Strength of 4WE Pad DS1 0 CO */
73		−#define DS_4WE_3 (DS1 \| DS0) /* 1 1 3 */
74		−#define DS_4WE_2 (DS1) /* 1 0 2 */
75		−#define DS_4WE_1 (DS0) /* 0 1 1 */
76		−#define DS_4WE_0 (DSZ) /* 0 0 0 */
77		−
78		−/* The Drive-Strength of 16st Pad DS3 2 1 0 CO */
79		−#define DS_16ST_15 (DS3 \| DS2 \| DS1 \| DS0) /* 1 1 1 1 15 */
80		−#define DS_16ST_14 (DS3 \| DS2 \| DS0) /* 1 1 0 1 13 */
81		−#define DS_16ST_13 (DS3 \| DS2 \| DS1) /* 1 1 1 0 14 */
82		−#define DS_16ST_12 (DS2 \| DS1 \| DS0) /* 0 1 1 1 7 */
83		−#define DS_16ST_11 (DS2 \| DS0) /* 0 1 0 1 5 */
84		−#define DS_16ST_10 (DS3 \| DS1 \| DS0) /* 1 0 1 1 11 */
85		−#define DS_16ST_9 (DS3 \| DS0) /* 1 0 0 1 9 */
86		−#define DS_16ST_8 (DS1 \| DS0) /* 0 0 1 1 3 */
87		−#define DS_16ST_7 (DS2 \| DS1) /* 0 1 1 0 6 */
88		−#define DS_16ST_6 (DS3 \| DS2) /* 1 1 0 0 12 */
89		−#define DS_16ST_5 (DS2) /* 0 1 0 0 4 */
90		−#define DS_16ST_4 (DS3 \| DS1) /* 1 0 1 0 10 */
91		−#define DS_16ST_3 (DS1) /* 0 0 1 0 2 */
92		−#define DS_16ST_2 (DS0) /* 0 0 0 1 1 */
93		−#define DS_16ST_1 (DSZ) /* 0 0 0 0 0 */
94		−#define DS_16ST_0 (DS3) /* 1 0 0 0 8 */
95		−
96		−/* The Drive-Strength of M31 Pad DS0 CO */
97		−#define DS_M31_0 (DSZ) /* 0 0 */
98		−#define DS_M31_1 (DS0) /* 1 1 */
99		−
100		−/* Raw values of Pull Option Bits */
101		−#define PUN BIT(1)
102		−#define PD BIT(0)
103		−#define PE BIT(0)
104		−#define PZ 0
105		−
106		−/* Definition of Pull Types */
107		−#define PULL_UP 0
108		−#define HIGH_HYSTERESIS 1
109		−#define HIGH_Z 2
110		−#define PULL_DOWN 3
111		−#define PULL_DISABLE 4
112		−#define PULL_ENABLE 5
113		−#define PULL_UNKNOWN -1
114		−
115		−/* Pull Options for 4WE Pad PUN PD CO */
116		−#define P4WE_PULL_MASK 0x3
117		−#define P4WE_PULL_DOWN (PUN \| PD) /* 1 1 3 */
118		−#define P4WE_HIGH_Z (PUN) /* 1 0 2 */
119		−#define P4WE_HIGH_HYSTERESIS (PD) /* 0 1 1 */
120		−#define P4WE_PULL_UP (PZ) /* 0 0 0 */
121		−
122		−/* Pull Options for 16ST Pad PUN PD CO */
123		−#define P16ST_PULL_MASK 0x3
124		−#define P16ST_PULL_DOWN (PUN \| PD) /* 1 1 3 */
125		−#define P16ST_HIGH_Z (PUN) /* 1 0 2 */
126		−#define P16ST_PULL_UP (PZ) /* 0 0 0 */
127		−
128		−/* Pull Options for M31 Pad PE */
129		−#define PM31_PULL_MASK 0x1
130		−#define PM31_PULL_ENABLED (PE) /* 1 */
131		−#define PM31_PULL_DISABLED (PZ) /* 0 */
132		−
133		−/* Pull Options for A/D Pad PUN PD CO */
134		−#define PANGD_PULL_MASK 0x3
135		−#define PANGD_PULL_DOWN (PUN \| PD) /* 1 1 3 */
136		−#define PANGD_HIGH_Z (PUN) /* 1 0 2 */
137		−#define PANGD_PULL_UP (PZ) /* 0 0 0 */
138		−
139		−/* Definition of Input Disable */
140		−#define DI_MASK 0x1
141		−#define DI_DISABLE 0x1
142		−#define DI_ENABLE 0x0
143		−
144		−/* Definition of Input Disable Value */
145		−#define DIV_MASK 0x1
146		−#define DIV_DISABLE 0x1
147		−#define DIV_ENABLE 0x0
148		−
149		−/* Number of Function input disable registers */
150		−#define NUM_OF_IN_DISABLE_REG 0x2
151		−
152		−/* Offset of Function input disable registers */
153		−#define IN_DISABLE_0_REG_SET 0x0A00
154		−#define IN_DISABLE_0_REG_CLR 0x0A04
155		−#define IN_DISABLE_1_REG_SET 0x0A08
156		−#define IN_DISABLE_1_REG_CLR 0x0A0C
157		−#define IN_DISABLE_VAL_0_REG_SET 0x0A80
158		−#define IN_DISABLE_VAL_0_REG_CLR 0x0A84
159		−#define IN_DISABLE_VAL_1_REG_SET 0x0A88
160		−#define IN_DISABLE_VAL_1_REG_CLR 0x0A8C
161		−
162		−/* Offset of the SDIO9SEL*/
163		−#define SYS2PCI_SDIO9SEL 0x14
164		−
165		−struct dt_params {
166		− const char *property;
167		− int value;
168		−};
169		−
170		−/**
171		− * struct atlas7_pad_conf - Atlas7 Pad Configuration
172		− * @id: The ID of this Pad.
173		− * @type: The type of this Pad.
174		− * @mux_reg: The mux register offset.
175		− * This register contains the mux.
176		− * @pupd_reg: The pull-up/down register offset.
177		− * @drvstr_reg: The drive-strength register offset.
178		− * @ad_ctrl_reg: The Analogue/Digital Control register.
179		− *
180		− * @mux_bit: The start bit of mux register.
181		− * @pupd_bit: The start bit of pull-up/down register.
182		− * @drvstr_bit: The start bit of drive-strength register.
183		− * @ad_ctrl_bit: The start bit of analogue/digital register.
184		− */
185		−struct atlas7_pad_config {
186		− const u32 id;
187		− u32 type;
188		− u32 mux_reg;
189		− u32 pupd_reg;
190		− u32 drvstr_reg;
191		− u32 ad_ctrl_reg;
192		− /* bits in register */
193		− u8 mux_bit;
194		− u8 pupd_bit;
195		− u8 drvstr_bit;
196		− u8 ad_ctrl_bit;
197		−};
198		−
199		−#define PADCONF(pad, t, mr, pr, dsr, adr, mb, pb, dsb, adb) \
200		− { \
201		− .id = pad, \
202		− .type = t, \
203		− .mux_reg = mr, \
204		− .pupd_reg = pr, \
205		− .drvstr_reg = dsr, \
206		− .ad_ctrl_reg = adr, \
207		− .mux_bit = mb, \
208		− .pupd_bit = pb, \
209		− .drvstr_bit = dsb, \
210		− .ad_ctrl_bit = adb, \
211		− }
212		−
213		−/*
214		− * struct atlas7_pad_status - Atlas7 Pad status
215		− */
216		−struct atlas7_pad_status {
217		− u8 func;
218		− u8 pull;
219		− u8 dstr;
220		− u8 reserved;
221		−};
222		−
223		−/**
224		− * struct atlas7_pad_mux - Atlas7 mux
225		− * @bank: The bank of this pad's registers on.
226		− * @pin : The ID of this Pad.
227		− * @func: The mux func on this Pad.
228		− * @dinput_reg: The Input-Disable register offset.
229		− * @dinput_bit: The start bit of Input-Disable register.
230		− * @dinput_val_reg: The Input-Disable-value register offset.
231		− * This register is used to set the value of this pad
232		− * if this pad was disabled.
233		− * @dinput_val_bit: The start bit of Input-Disable Value register.
234		− */
235		−struct atlas7_pad_mux {
236		− u32 bank;
237		− u32 pin;
238		− u32 func;
239		− u32 dinput_reg;
240		− u32 dinput_bit;
241		− u32 dinput_val_reg;
242		− u32 dinput_val_bit;
243		−};
244		−
245		−#define MUX(b, pad, f, dr, db, dvr, dvb) \
246		− { \
247		− .bank = b, \
248		− .pin = pad, \
249		− .func = f, \
250		− .dinput_reg = dr, \
251		− .dinput_bit = db, \
252		− .dinput_val_reg = dvr, \
253		− .dinput_val_bit = dvb, \
254		− }
255		−
256		−struct atlas7_grp_mux {
257		− unsigned int group;
258		− unsigned int pad_mux_count;
259		− const struct atlas7_pad_mux *pad_mux_list;
260		−};
261		−
262		− /**
263		− * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
264		− * @name: the name of this specific pin group
265		− * @pins: an array of discrete physical pins used in this group, taken
266		− * from the driver-local pin enumeration space
267		− * @num_pins: the number of pins in this group array, i.e. the number of
268		− * elements in .pins so we can iterate over that array
269		− */
270		−struct atlas7_pin_group {
271		− const char *name;
272		− const unsigned int *pins;
273		− const unsigned num_pins;
274		−};
275		−
276		−#define GROUP(n, p) \
277		− { \
278		− .name = n, \
279		− .pins = p, \
280		− .num_pins = ARRAY_SIZE(p), \
281		− }
282		−
283		−struct atlas7_pmx_func {
284		− const char *name;
285		− const char * const *groups;
286		− const unsigned num_groups;
287		− const struct atlas7_grp_mux *grpmux;
288		−};
289		−
290		−#define FUNCTION(n, g, m) \
291		− { \
292		− .name = n, \
293		− .groups = g, \
294		− .num_groups = ARRAY_SIZE(g), \
295		− .grpmux = m, \
296		− }
297		−
298		−struct atlas7_pinctrl_data {
299		− struct pinctrl_pin_desc *pads;
300		− int pads_cnt;
301		− struct atlas7_pin_group *grps;
302		− int grps_cnt;
303		− struct atlas7_pmx_func *funcs;
304		− int funcs_cnt;
305		− struct atlas7_pad_config *confs;
306		− int confs_cnt;
307		−};
308		−
309		−/* Platform info of atlas7 pinctrl */
310		−#define ATLAS7_PINCTRL_REG_BANKS 2
311		−#define ATLAS7_PINCTRL_BANK_0_PINS 18
312		−#define ATLAS7_PINCTRL_BANK_1_PINS 141
313		−#define ATLAS7_PINCTRL_TOTAL_PINS \
314		− (ATLAS7_PINCTRL_BANK_0_PINS + ATLAS7_PINCTRL_BANK_1_PINS)
315		−
316		−/**
317		− * Atlas7 GPIO Chip
318		− */
319		−
320		−#define NGPIO_OF_BANK 32
321		−#define GPIO_TO_BANK(gpio) ((gpio) / NGPIO_OF_BANK)
322		−
323		−/* Registers of GPIO Controllers */
324		−#define ATLAS7_GPIO_BASE(g, b) ((g)->reg + 0x100 * (b))
325		−#define ATLAS7_GPIO_CTRL(b, i) ((b)->base + 4 * (i))
326		−#define ATLAS7_GPIO_INT_STATUS(b) ((b)->base + 0x8C)
327		−
328		−/* Definition bits of GPIO Control Registers */
329		−#define ATLAS7_GPIO_CTL_INTR_LOW_MASK BIT(0)
330		−#define ATLAS7_GPIO_CTL_INTR_HIGH_MASK BIT(1)
331		−#define ATLAS7_GPIO_CTL_INTR_TYPE_MASK BIT(2)
332		−#define ATLAS7_GPIO_CTL_INTR_EN_MASK BIT(3)
333		−#define ATLAS7_GPIO_CTL_INTR_STATUS_MASK BIT(4)
334		−#define ATLAS7_GPIO_CTL_OUT_EN_MASK BIT(5)
335		−#define ATLAS7_GPIO_CTL_DATAOUT_MASK BIT(6)
336		−#define ATLAS7_GPIO_CTL_DATAIN_MASK BIT(7)
337		−
338		−struct atlas7_gpio_bank {
339		− int id;
340		− int irq;
341		− void __iomem *base;
342		− unsigned int gpio_offset;
343		− unsigned int ngpio;
344		− const unsigned int *gpio_pins;
345		− u32 sleep_data[NGPIO_OF_BANK];
346		−};
347		−
348		−struct atlas7_gpio_chip {
349		− const char *name;
350		− void __iomem *reg;
351		− struct clk *clk;
352		− int nbank;
353		− raw_spinlock_t lock;
354		− struct gpio_chip chip;
355		− struct atlas7_gpio_bank banks[];
356		−};
357		−
358		−struct atlas7_pmx {
359		− struct device *dev;
360		− struct pinctrl_dev *pctl;
361		− struct pinctrl_desc pctl_desc;
362		− struct atlas7_pinctrl_data *pctl_data;
363		− void __iomem *regs[ATLAS7_PINCTRL_REG_BANKS];
364		− void __iomem *sys2pci_base;
365		− u32 status_ds[NUM_OF_IN_DISABLE_REG];
366		− u32 status_dsv[NUM_OF_IN_DISABLE_REG];
367		− struct atlas7_pad_status sleep_data[ATLAS7_PINCTRL_TOTAL_PINS];
368		−};
369		−
370		−/*
371		− * Pad list for the pinmux subsystem
372		− * refer to A7DA IO Summary - CS-314158-DD-4E.xls
373		− */
374		−
375		−/* Pads in IOC RTC & TOP */
376		−static const struct pinctrl_pin_desc atlas7_ioc_pads[] = {
377		− /* RTC PADs */
378		− PINCTRL_PIN(0, "rtc_gpio_0"),
379		− PINCTRL_PIN(1, "rtc_gpio_1"),
380		− PINCTRL_PIN(2, "rtc_gpio_2"),
381		− PINCTRL_PIN(3, "rtc_gpio_3"),
382		− PINCTRL_PIN(4, "low_bat_ind_b"),
383		− PINCTRL_PIN(5, "on_key_b"),
384		− PINCTRL_PIN(6, "ext_on"),
385		− PINCTRL_PIN(7, "mem_on"),
386		− PINCTRL_PIN(8, "core_on"),
387		− PINCTRL_PIN(9, "io_on"),
388		− PINCTRL_PIN(10, "can0_tx"),
389		− PINCTRL_PIN(11, "can0_rx"),
390		− PINCTRL_PIN(12, "spi0_clk"),
391		− PINCTRL_PIN(13, "spi0_cs_b"),
392		− PINCTRL_PIN(14, "spi0_io_0"),
393		− PINCTRL_PIN(15, "spi0_io_1"),
394		− PINCTRL_PIN(16, "spi0_io_2"),
395		− PINCTRL_PIN(17, "spi0_io_3"),
396		−
397		− /* TOP PADs */
398		− PINCTRL_PIN(18, "spi1_en"),
399		− PINCTRL_PIN(19, "spi1_clk"),
400		− PINCTRL_PIN(20, "spi1_din"),
401		− PINCTRL_PIN(21, "spi1_dout"),
402		− PINCTRL_PIN(22, "trg_spi_clk"),
403		− PINCTRL_PIN(23, "trg_spi_di"),
404		− PINCTRL_PIN(24, "trg_spi_do"),
405		− PINCTRL_PIN(25, "trg_spi_cs_b"),
406		− PINCTRL_PIN(26, "trg_acq_d1"),
407		− PINCTRL_PIN(27, "trg_irq_b"),
408		− PINCTRL_PIN(28, "trg_acq_d0"),
409		− PINCTRL_PIN(29, "trg_acq_clk"),
410		− PINCTRL_PIN(30, "trg_shutdown_b_out"),
411		− PINCTRL_PIN(31, "sdio2_clk"),
412		− PINCTRL_PIN(32, "sdio2_cmd"),
413		− PINCTRL_PIN(33, "sdio2_dat_0"),
414		− PINCTRL_PIN(34, "sdio2_dat_1"),
415		− PINCTRL_PIN(35, "sdio2_dat_2"),
416		− PINCTRL_PIN(36, "sdio2_dat_3"),
417		− PINCTRL_PIN(37, "df_ad_7"),
418		− PINCTRL_PIN(38, "df_ad_6"),
419		− PINCTRL_PIN(39, "df_ad_5"),
420		− PINCTRL_PIN(40, "df_ad_4"),
421		− PINCTRL_PIN(41, "df_ad_3"),
422		− PINCTRL_PIN(42, "df_ad_2"),
423		− PINCTRL_PIN(43, "df_ad_1"),
424		− PINCTRL_PIN(44, "df_ad_0"),
425		− PINCTRL_PIN(45, "df_dqs"),
426		− PINCTRL_PIN(46, "df_cle"),
427		− PINCTRL_PIN(47, "df_ale"),
428		− PINCTRL_PIN(48, "df_we_b"),
429		− PINCTRL_PIN(49, "df_re_b"),
430		− PINCTRL_PIN(50, "df_ry_by"),
431		− PINCTRL_PIN(51, "df_cs_b_1"),
432		− PINCTRL_PIN(52, "df_cs_b_0"),
433		− PINCTRL_PIN(53, "l_pclk"),
434		− PINCTRL_PIN(54, "l_lck"),
435		− PINCTRL_PIN(55, "l_fck"),
436		− PINCTRL_PIN(56, "l_de"),
437		− PINCTRL_PIN(57, "ldd_0"),
438		− PINCTRL_PIN(58, "ldd_1"),
439		− PINCTRL_PIN(59, "ldd_2"),
440		− PINCTRL_PIN(60, "ldd_3"),
441		− PINCTRL_PIN(61, "ldd_4"),
442		− PINCTRL_PIN(62, "ldd_5"),
443		− PINCTRL_PIN(63, "ldd_6"),
444		− PINCTRL_PIN(64, "ldd_7"),
445		− PINCTRL_PIN(65, "ldd_8"),
446		− PINCTRL_PIN(66, "ldd_9"),
447		− PINCTRL_PIN(67, "ldd_10"),
448		− PINCTRL_PIN(68, "ldd_11"),
449		− PINCTRL_PIN(69, "ldd_12"),
450		− PINCTRL_PIN(70, "ldd_13"),
451		− PINCTRL_PIN(71, "ldd_14"),
452		− PINCTRL_PIN(72, "ldd_15"),
453		− PINCTRL_PIN(73, "lcd_gpio_20"),
454		− PINCTRL_PIN(74, "vip_0"),
455		− PINCTRL_PIN(75, "vip_1"),
456		− PINCTRL_PIN(76, "vip_2"),
457		− PINCTRL_PIN(77, "vip_3"),
458		− PINCTRL_PIN(78, "vip_4"),
459		− PINCTRL_PIN(79, "vip_5"),
460		− PINCTRL_PIN(80, "vip_6"),
461		− PINCTRL_PIN(81, "vip_7"),
462		− PINCTRL_PIN(82, "vip_pxclk"),
463		− PINCTRL_PIN(83, "vip_hsync"),
464		− PINCTRL_PIN(84, "vip_vsync"),
465		− PINCTRL_PIN(85, "sdio3_clk"),
466		− PINCTRL_PIN(86, "sdio3_cmd"),
467		− PINCTRL_PIN(87, "sdio3_dat_0"),
468		− PINCTRL_PIN(88, "sdio3_dat_1"),
469		− PINCTRL_PIN(89, "sdio3_dat_2"),
470		− PINCTRL_PIN(90, "sdio3_dat_3"),
471		− PINCTRL_PIN(91, "sdio5_clk"),
472		− PINCTRL_PIN(92, "sdio5_cmd"),
473		− PINCTRL_PIN(93, "sdio5_dat_0"),
474		− PINCTRL_PIN(94, "sdio5_dat_1"),
475		− PINCTRL_PIN(95, "sdio5_dat_2"),
476		− PINCTRL_PIN(96, "sdio5_dat_3"),
477		− PINCTRL_PIN(97, "rgmii_txd_0"),
478		− PINCTRL_PIN(98, "rgmii_txd_1"),
479		− PINCTRL_PIN(99, "rgmii_txd_2"),
480		− PINCTRL_PIN(100, "rgmii_txd_3"),
481		− PINCTRL_PIN(101, "rgmii_txclk"),
482		− PINCTRL_PIN(102, "rgmii_tx_ctl"),
483		− PINCTRL_PIN(103, "rgmii_rxd_0"),
484		− PINCTRL_PIN(104, "rgmii_rxd_1"),
485		− PINCTRL_PIN(105, "rgmii_rxd_2"),
486		− PINCTRL_PIN(106, "rgmii_rxd_3"),
487		− PINCTRL_PIN(107, "rgmii_rx_clk"),
488		− PINCTRL_PIN(108, "rgmii_rxc_ctl"),
489		− PINCTRL_PIN(109, "rgmii_mdio"),
490		− PINCTRL_PIN(110, "rgmii_mdc"),
491		− PINCTRL_PIN(111, "rgmii_intr_n"),
492		− PINCTRL_PIN(112, "i2s_mclk"),
493		− PINCTRL_PIN(113, "i2s_bclk"),
494		− PINCTRL_PIN(114, "i2s_ws"),
495		− PINCTRL_PIN(115, "i2s_dout0"),
496		− PINCTRL_PIN(116, "i2s_dout1"),
497		− PINCTRL_PIN(117, "i2s_dout2"),
498		− PINCTRL_PIN(118, "i2s_din"),
499		− PINCTRL_PIN(119, "gpio_0"),
500		− PINCTRL_PIN(120, "gpio_1"),
501		− PINCTRL_PIN(121, "gpio_2"),
502		− PINCTRL_PIN(122, "gpio_3"),
503		− PINCTRL_PIN(123, "gpio_4"),
504		− PINCTRL_PIN(124, "gpio_5"),
505		− PINCTRL_PIN(125, "gpio_6"),
506		− PINCTRL_PIN(126, "gpio_7"),
507		− PINCTRL_PIN(127, "sda_0"),
508		− PINCTRL_PIN(128, "scl_0"),
509		− PINCTRL_PIN(129, "coex_pio_0"),
510		− PINCTRL_PIN(130, "coex_pio_1"),
511		− PINCTRL_PIN(131, "coex_pio_2"),
512		− PINCTRL_PIN(132, "coex_pio_3"),
513		− PINCTRL_PIN(133, "uart0_tx"),
514		− PINCTRL_PIN(134, "uart0_rx"),
515		− PINCTRL_PIN(135, "uart1_tx"),
516		− PINCTRL_PIN(136, "uart1_rx"),
517		− PINCTRL_PIN(137, "uart3_tx"),
518		− PINCTRL_PIN(138, "uart3_rx"),
519		− PINCTRL_PIN(139, "uart4_tx"),
520		− PINCTRL_PIN(140, "uart4_rx"),
521		− PINCTRL_PIN(141, "usp0_clk"),
522		− PINCTRL_PIN(142, "usp0_tx"),
523		− PINCTRL_PIN(143, "usp0_rx"),
524		− PINCTRL_PIN(144, "usp0_fs"),
525		− PINCTRL_PIN(145, "usp1_clk"),
526		− PINCTRL_PIN(146, "usp1_tx"),
527		− PINCTRL_PIN(147, "usp1_rx"),
528		− PINCTRL_PIN(148, "usp1_fs"),
529		− PINCTRL_PIN(149, "lvds_tx0d4p"),
530		− PINCTRL_PIN(150, "lvds_tx0d4n"),
531		− PINCTRL_PIN(151, "lvds_tx0d3p"),
532		− PINCTRL_PIN(152, "lvds_tx0d3n"),
533		− PINCTRL_PIN(153, "lvds_tx0d2p"),
534		− PINCTRL_PIN(154, "lvds_tx0d2n"),
535		− PINCTRL_PIN(155, "lvds_tx0d1p"),
536		− PINCTRL_PIN(156, "lvds_tx0d1n"),
537		− PINCTRL_PIN(157, "lvds_tx0d0p"),
538		− PINCTRL_PIN(158, "lvds_tx0d0n"),
539		− PINCTRL_PIN(159, "jtag_tdo"),
540		− PINCTRL_PIN(160, "jtag_tms"),
541		− PINCTRL_PIN(161, "jtag_tck"),
542		− PINCTRL_PIN(162, "jtag_tdi"),
543		− PINCTRL_PIN(163, "jtag_trstn"),
544		−};
545		−
546		−static struct atlas7_pad_config atlas7_ioc_pad_confs[] = {
547		− /* The Configuration of IOC_RTC Pads */
548		− PADCONF(0, 3, 0x0, 0x100, 0x200, -1, 0, 0, 0, 0),
549		− PADCONF(1, 3, 0x0, 0x100, 0x200, -1, 4, 2, 2, 0),
550		− PADCONF(2, 3, 0x0, 0x100, 0x200, -1, 8, 4, 4, 0),
551		− PADCONF(3, 5, 0x0, 0x100, 0x200, -1, 12, 6, 6, 0),
552		− PADCONF(4, 4, 0x0, 0x100, 0x200, -1, 16, 8, 8, 0),
553		− PADCONF(5, 4, 0x0, 0x100, 0x200, -1, 20, 10, 10, 0),
554		− PADCONF(6, 3, 0x0, 0x100, 0x200, -1, 24, 12, 12, 0),
555		− PADCONF(7, 3, 0x0, 0x100, 0x200, -1, 28, 14, 14, 0),
556		− PADCONF(8, 3, 0x8, 0x100, 0x200, -1, 0, 16, 16, 0),
557		− PADCONF(9, 3, 0x8, 0x100, 0x200, -1, 4, 18, 18, 0),
558		− PADCONF(10, 4, 0x8, 0x100, 0x200, -1, 8, 20, 20, 0),
559		− PADCONF(11, 4, 0x8, 0x100, 0x200, -1, 12, 22, 22, 0),
560		− PADCONF(12, 5, 0x8, 0x100, 0x200, -1, 16, 24, 24, 0),
561		− PADCONF(13, 6, 0x8, 0x100, 0x200, -1, 20, 26, 26, 0),
562		− PADCONF(14, 5, 0x8, 0x100, 0x200, -1, 24, 28, 28, 0),
563		− PADCONF(15, 5, 0x8, 0x100, 0x200, -1, 28, 30, 30, 0),
564		− PADCONF(16, 5, 0x10, 0x108, 0x208, -1, 0, 0, 0, 0),
565		− PADCONF(17, 5, 0x10, 0x108, 0x208, -1, 4, 2, 2, 0),
566		− /* The Configuration of IOC_TOP Pads */
567		− PADCONF(18, 5, 0x80, 0x180, 0x300, -1, 0, 0, 0, 0),
568		− PADCONF(19, 5, 0x80, 0x180, 0x300, -1, 4, 2, 2, 0),
569		− PADCONF(20, 5, 0x80, 0x180, 0x300, -1, 8, 4, 4, 0),
570		− PADCONF(21, 5, 0x80, 0x180, 0x300, -1, 12, 6, 6, 0),
571		− PADCONF(22, 5, 0x88, 0x188, 0x308, -1, 0, 0, 0, 0),
572		− PADCONF(23, 5, 0x88, 0x188, 0x308, -1, 4, 2, 2, 0),
573		− PADCONF(24, 5, 0x88, 0x188, 0x308, -1, 8, 4, 4, 0),
574		− PADCONF(25, 6, 0x88, 0x188, 0x308, -1, 12, 6, 6, 0),
575		− PADCONF(26, 5, 0x88, 0x188, 0x308, -1, 16, 8, 8, 0),
576		− PADCONF(27, 6, 0x88, 0x188, 0x308, -1, 20, 10, 10, 0),
577		− PADCONF(28, 5, 0x88, 0x188, 0x308, -1, 24, 12, 12, 0),
578		− PADCONF(29, 5, 0x88, 0x188, 0x308, -1, 28, 14, 14, 0),
579		− PADCONF(30, 5, 0x90, 0x188, 0x308, -1, 0, 16, 16, 0),
580		− PADCONF(31, 2, 0x98, 0x190, 0x310, -1, 0, 0, 0, 0),
581		− PADCONF(32, 1, 0x98, 0x190, 0x310, -1, 4, 2, 4, 0),
582		− PADCONF(33, 1, 0x98, 0x190, 0x310, -1, 8, 4, 6, 0),
583		− PADCONF(34, 1, 0x98, 0x190, 0x310, -1, 12, 6, 8, 0),
584		− PADCONF(35, 1, 0x98, 0x190, 0x310, -1, 16, 8, 10, 0),
585		− PADCONF(36, 1, 0x98, 0x190, 0x310, -1, 20, 10, 12, 0),
586		− PADCONF(37, 1, 0xa0, 0x198, 0x318, -1, 0, 0, 0, 0),
587		− PADCONF(38, 1, 0xa0, 0x198, 0x318, -1, 4, 2, 2, 0),
588		− PADCONF(39, 1, 0xa0, 0x198, 0x318, -1, 8, 4, 4, 0),
589		− PADCONF(40, 1, 0xa0, 0x198, 0x318, -1, 12, 6, 6, 0),
590		− PADCONF(41, 1, 0xa0, 0x198, 0x318, -1, 16, 8, 8, 0),
591		− PADCONF(42, 1, 0xa0, 0x198, 0x318, -1, 20, 10, 10, 0),
592		− PADCONF(43, 1, 0xa0, 0x198, 0x318, -1, 24, 12, 12, 0),
593		− PADCONF(44, 1, 0xa0, 0x198, 0x318, -1, 28, 14, 14, 0),
594		− PADCONF(45, 0, 0xa8, 0x198, 0x318, -1, 0, 16, 16, 0),
595		− PADCONF(46, 0, 0xa8, 0x198, 0x318, -1, 4, 18, 18, 0),
596		− PADCONF(47, 1, 0xa8, 0x198, 0x318, -1, 8, 20, 20, 0),
597		− PADCONF(48, 1, 0xa8, 0x198, 0x318, -1, 12, 22, 22, 0),
598		− PADCONF(49, 1, 0xa8, 0x198, 0x318, -1, 16, 24, 24, 0),
599		− PADCONF(50, 1, 0xa8, 0x198, 0x318, -1, 20, 26, 26, 0),
600		− PADCONF(51, 1, 0xa8, 0x198, 0x318, -1, 24, 28, 28, 0),
601		− PADCONF(52, 1, 0xa8, 0x198, 0x318, -1, 28, 30, 30, 0),
602		− PADCONF(53, 0, 0xb0, 0x1a0, 0x320, -1, 0, 0, 0, 0),
603		− PADCONF(54, 0, 0xb0, 0x1a0, 0x320, -1, 4, 2, 2, 0),
604		− PADCONF(55, 0, 0xb0, 0x1a0, 0x320, -1, 8, 4, 4, 0),
605		− PADCONF(56, 0, 0xb0, 0x1a0, 0x320, -1, 12, 6, 6, 0),
606		− PADCONF(57, 0, 0xb0, 0x1a0, 0x320, -1, 16, 8, 8, 0),
607		− PADCONF(58, 0, 0xb0, 0x1a0, 0x320, -1, 20, 10, 10, 0),
608		− PADCONF(59, 0, 0xb0, 0x1a0, 0x320, -1, 24, 12, 12, 0),
609		− PADCONF(60, 0, 0xb0, 0x1a0, 0x320, -1, 28, 14, 14, 0),
610		− PADCONF(61, 0, 0xb8, 0x1a0, 0x320, -1, 0, 16, 16, 0),
611		− PADCONF(62, 0, 0xb8, 0x1a0, 0x320, -1, 4, 18, 18, 0),
612		− PADCONF(63, 0, 0xb8, 0x1a0, 0x320, -1, 8, 20, 20, 0),
613		− PADCONF(64, 0, 0xb8, 0x1a0, 0x320, -1, 12, 22, 22, 0),
614		− PADCONF(65, 0, 0xb8, 0x1a0, 0x320, -1, 16, 24, 24, 0),
615		− PADCONF(66, 0, 0xb8, 0x1a0, 0x320, -1, 20, 26, 26, 0),
616		− PADCONF(67, 0, 0xb8, 0x1a0, 0x320, -1, 24, 28, 28, 0),
617		− PADCONF(68, 0, 0xb8, 0x1a0, 0x320, -1, 28, 30, 30, 0),
618		− PADCONF(69, 0, 0xc0, 0x1a8, 0x328, -1, 0, 0, 0, 0),
619		− PADCONF(70, 0, 0xc0, 0x1a8, 0x328, -1, 4, 2, 2, 0),
620		− PADCONF(71, 0, 0xc0, 0x1a8, 0x328, -1, 8, 4, 4, 0),
621		− PADCONF(72, 0, 0xc0, 0x1a8, 0x328, -1, 12, 6, 6, 0),
622		− PADCONF(73, 0, 0xc0, 0x1a8, 0x328, -1, 16, 8, 8, 0),
623		− PADCONF(74, 0, 0xc8, 0x1b0, 0x330, -1, 0, 0, 0, 0),
624		− PADCONF(75, 0, 0xc8, 0x1b0, 0x330, -1, 4, 2, 2, 0),
625		− PADCONF(76, 0, 0xc8, 0x1b0, 0x330, -1, 8, 4, 4, 0),
626		− PADCONF(77, 0, 0xc8, 0x1b0, 0x330, -1, 12, 6, 6, 0),
627		− PADCONF(78, 0, 0xc8, 0x1b0, 0x330, -1, 16, 8, 8, 0),
628		− PADCONF(79, 0, 0xc8, 0x1b0, 0x330, -1, 20, 10, 10, 0),
629		− PADCONF(80, 0, 0xc8, 0x1b0, 0x330, -1, 24, 12, 12, 0),
630		− PADCONF(81, 0, 0xc8, 0x1b0, 0x330, -1, 28, 14, 14, 0),
631		− PADCONF(82, 0, 0xd0, 0x1b0, 0x330, -1, 0, 16, 16, 0),
632		− PADCONF(83, 0, 0xd0, 0x1b0, 0x330, -1, 4, 18, 18, 0),
633		− PADCONF(84, 0, 0xd0, 0x1b0, 0x330, -1, 8, 20, 20, 0),
634		− PADCONF(85, 2, 0xd8, 0x1b8, 0x338, -1, 0, 0, 0, 0),
635		− PADCONF(86, 1, 0xd8, 0x1b8, 0x338, -1, 4, 4, 4, 0),
636		− PADCONF(87, 1, 0xd8, 0x1b8, 0x338, -1, 8, 6, 6, 0),
637		− PADCONF(88, 1, 0xd8, 0x1b8, 0x338, -1, 12, 8, 8, 0),
638		− PADCONF(89, 1, 0xd8, 0x1b8, 0x338, -1, 16, 10, 10, 0),
639		− PADCONF(90, 1, 0xd8, 0x1b8, 0x338, -1, 20, 12, 12, 0),
640		− PADCONF(91, 2, 0xe0, 0x1c0, 0x340, -1, 0, 0, 0, 0),
641		− PADCONF(92, 1, 0xe0, 0x1c0, 0x340, -1, 4, 4, 4, 0),
642		− PADCONF(93, 1, 0xe0, 0x1c0, 0x340, -1, 8, 6, 6, 0),
643		− PADCONF(94, 1, 0xe0, 0x1c0, 0x340, -1, 12, 8, 8, 0),
644		− PADCONF(95, 1, 0xe0, 0x1c0, 0x340, -1, 16, 10, 10, 0),
645		− PADCONF(96, 1, 0xe0, 0x1c0, 0x340, -1, 20, 12, 12, 0),
646		− PADCONF(97, 0, 0xe8, 0x1c8, 0x348, -1, 0, 0, 0, 0),
647		− PADCONF(98, 0, 0xe8, 0x1c8, 0x348, -1, 4, 2, 2, 0),
648		− PADCONF(99, 0, 0xe8, 0x1c8, 0x348, -1, 8, 4, 4, 0),
649		− PADCONF(100, 0, 0xe8, 0x1c8, 0x348, -1, 12, 6, 6, 0),
650		− PADCONF(101, 2, 0xe8, 0x1c8, 0x348, -1, 16, 8, 8, 0),
651		− PADCONF(102, 0, 0xe8, 0x1c8, 0x348, -1, 20, 12, 12, 0),
652		− PADCONF(103, 0, 0xe8, 0x1c8, 0x348, -1, 24, 14, 14, 0),
653		− PADCONF(104, 0, 0xe8, 0x1c8, 0x348, -1, 28, 16, 16, 0),
654		− PADCONF(105, 0, 0xf0, 0x1c8, 0x348, -1, 0, 18, 18, 0),
655		− PADCONF(106, 0, 0xf0, 0x1c8, 0x348, -1, 4, 20, 20, 0),
656		− PADCONF(107, 0, 0xf0, 0x1c8, 0x348, -1, 8, 22, 22, 0),
657		− PADCONF(108, 0, 0xf0, 0x1c8, 0x348, -1, 12, 24, 24, 0),
658		− PADCONF(109, 1, 0xf0, 0x1c8, 0x348, -1, 16, 26, 26, 0),
659		− PADCONF(110, 0, 0xf0, 0x1c8, 0x348, -1, 20, 28, 28, 0),
660		− PADCONF(111, 1, 0xf0, 0x1c8, 0x348, -1, 24, 30, 30, 0),
661		− PADCONF(112, 5, 0xf8, 0x200, 0x350, -1, 0, 0, 0, 0),
662		− PADCONF(113, 5, 0xf8, 0x200, 0x350, -1, 4, 2, 2, 0),
663		− PADCONF(114, 5, 0xf8, 0x200, 0x350, -1, 8, 4, 4, 0),
664		− PADCONF(115, 5, 0xf8, 0x200, 0x350, -1, 12, 6, 6, 0),
665		− PADCONF(116, 5, 0xf8, 0x200, 0x350, -1, 16, 8, 8, 0),
666		− PADCONF(117, 5, 0xf8, 0x200, 0x350, -1, 20, 10, 10, 0),
667		− PADCONF(118, 5, 0xf8, 0x200, 0x350, -1, 24, 12, 12, 0),
668		− PADCONF(119, 5, 0x100, 0x250, 0x358, -1, 0, 0, 0, 0),
669		− PADCONF(120, 5, 0x100, 0x250, 0x358, -1, 4, 2, 2, 0),
670		− PADCONF(121, 5, 0x100, 0x250, 0x358, -1, 8, 4, 4, 0),
671		− PADCONF(122, 5, 0x100, 0x250, 0x358, -1, 12, 6, 6, 0),
672		− PADCONF(123, 6, 0x100, 0x250, 0x358, -1, 16, 8, 8, 0),
673		− PADCONF(124, 6, 0x100, 0x250, 0x358, -1, 20, 10, 10, 0),
674		− PADCONF(125, 6, 0x100, 0x250, 0x358, -1, 24, 12, 12, 0),
675		− PADCONF(126, 6, 0x100, 0x250, 0x358, -1, 28, 14, 14, 0),
676		− PADCONF(127, 6, 0x108, 0x250, 0x358, -1, 16, 24, 24, 0),
677		− PADCONF(128, 6, 0x108, 0x250, 0x358, -1, 20, 26, 26, 0),
678		− PADCONF(129, 0, 0x110, 0x258, 0x360, -1, 0, 0, 0, 0),
679		− PADCONF(130, 0, 0x110, 0x258, 0x360, -1, 4, 2, 2, 0),
680		− PADCONF(131, 0, 0x110, 0x258, 0x360, -1, 8, 4, 4, 0),
681		− PADCONF(132, 0, 0x110, 0x258, 0x360, -1, 12, 6, 6, 0),
682		− PADCONF(133, 6, 0x118, 0x260, 0x368, -1, 0, 0, 0, 0),
683		− PADCONF(134, 6, 0x118, 0x260, 0x368, -1, 4, 2, 2, 0),
684		− PADCONF(135, 6, 0x118, 0x260, 0x368, -1, 16, 8, 8, 0),
685		− PADCONF(136, 6, 0x118, 0x260, 0x368, -1, 20, 10, 10, 0),
686		− PADCONF(137, 6, 0x118, 0x260, 0x368, -1, 24, 12, 12, 0),
687		− PADCONF(138, 6, 0x118, 0x260, 0x368, -1, 28, 14, 14, 0),
688		− PADCONF(139, 6, 0x120, 0x260, 0x368, -1, 0, 16, 16, 0),
689		− PADCONF(140, 6, 0x120, 0x260, 0x368, -1, 4, 18, 18, 0),
690		− PADCONF(141, 5, 0x128, 0x268, 0x378, -1, 0, 0, 0, 0),
691		− PADCONF(142, 5, 0x128, 0x268, 0x378, -1, 4, 2, 2, 0),
692		− PADCONF(143, 5, 0x128, 0x268, 0x378, -1, 8, 4, 4, 0),
693		− PADCONF(144, 5, 0x128, 0x268, 0x378, -1, 12, 6, 6, 0),
694		− PADCONF(145, 5, 0x128, 0x268, 0x378, -1, 16, 8, 8, 0),
695		− PADCONF(146, 5, 0x128, 0x268, 0x378, -1, 20, 10, 10, 0),
696		− PADCONF(147, 5, 0x128, 0x268, 0x378, -1, 24, 12, 12, 0),
697		− PADCONF(148, 5, 0x128, 0x268, 0x378, -1, 28, 14, 14, 0),
698		− PADCONF(149, 7, 0x130, 0x270, -1, 0x480, 0, 0, 0, 0),
699		− PADCONF(150, 7, 0x130, 0x270, -1, 0x480, 4, 2, 0, 1),
700		− PADCONF(151, 7, 0x130, 0x270, -1, 0x480, 8, 4, 0, 2),
701		− PADCONF(152, 7, 0x130, 0x270, -1, 0x480, 12, 6, 0, 3),
702		− PADCONF(153, 7, 0x130, 0x270, -1, 0x480, 16, 8, 0, 4),
703		− PADCONF(154, 7, 0x130, 0x270, -1, 0x480, 20, 10, 0, 5),
704		− PADCONF(155, 7, 0x130, 0x270, -1, 0x480, 24, 12, 0, 6),
705		− PADCONF(156, 7, 0x130, 0x270, -1, 0x480, 28, 14, 0, 7),
706		− PADCONF(157, 7, 0x138, 0x278, -1, 0x480, 0, 0, 0, 8),
707		− PADCONF(158, 7, 0x138, 0x278, -1, 0x480, 4, 2, 0, 9),
708		− PADCONF(159, 5, 0x140, 0x280, 0x380, -1, 0, 0, 0, 0),
709		− PADCONF(160, 6, 0x140, 0x280, 0x380, -1, 4, 2, 2, 0),
710		− PADCONF(161, 5, 0x140, 0x280, 0x380, -1, 8, 4, 4, 0),
711		− PADCONF(162, 6, 0x140, 0x280, 0x380, -1, 12, 6, 6, 0),
712		− PADCONF(163, 6, 0x140, 0x280, 0x380, -1, 16, 8, 8, 0),
713		−};
714		−
715		−/* pin list of each pin group */
716		−static const unsigned int gnss_gpio_pins[] = { 119, 120, 121, 122, 123, 124,
717		− 125, 126, 127, 128, 22, 23, 24, 25, 26, 27, 28, 29, 30, };
718		−static const unsigned int lcd_vip_gpio_pins[] = { 74, 75, 76, 77, 78, 79, 80,
719		− 81, 82, 83, 84, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
720		− 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, };
721		−static const unsigned int sdio_i2s_gpio_pins[] = { 31, 32, 33, 34, 35, 36,
722		− 85, 86, 87, 88, 89, 90, 129, 130, 131, 132, 91, 92, 93, 94,
723		− 95, 96, 112, 113, 114, 115, 116, 117, 118, };
724		−static const unsigned int sp_rgmii_gpio_pins[] = { 97, 98, 99, 100, 101, 102,
725		− 103, 104, 105, 106, 107, 108, 109, 110, 111, 18, 19, 20, 21,
726		− 141, 142, 143, 144, 145, 146, 147, 148, };
727		−static const unsigned int lvds_gpio_pins[] = { 157, 158, 155, 156, 153, 154,
728		− 151, 152, 149, 150, };
729		−static const unsigned int jtag_uart_nand_gpio_pins[] = { 44, 43, 42, 41, 40,
730		− 39, 38, 37, 46, 47, 48, 49, 50, 52, 51, 45, 133, 134, 135,
731		− 136, 137, 138, 139, 140, 159, 160, 161, 162, 163, };
732		−static const unsigned int rtc_gpio_pins[] = { 0, 1, 2, 3, 4, 10, 11, 12, 13,
733		− 14, 15, 16, 17, 9, };
734		−static const unsigned int audio_ac97_pins[] = { 113, 118, 115, 114, };
735		−static const unsigned int audio_digmic_pins0[] = { 51, };
736		−static const unsigned int audio_digmic_pins1[] = { 122, };
737		−static const unsigned int audio_digmic_pins2[] = { 161, };
738		−static const unsigned int audio_func_dbg_pins[] = { 141, 144, 44, 43, 42, 41,
739		− 40, 39, 38, 37, 74, 75, 76, 77, 78, 79, 81, 113, 114, 118,
740		− 115, 49, 50, 142, 143, 80, };
741		−static const unsigned int audio_i2s_pins[] = { 118, 115, 116, 117, 112, 113,
742		− 114, };
743		−static const unsigned int audio_i2s_2ch_pins[] = { 118, 115, 112, 113, 114, };
744		−static const unsigned int audio_i2s_extclk_pins[] = { 112, };
745		−static const unsigned int audio_spdif_out_pins0[] = { 112, };
746		−static const unsigned int audio_spdif_out_pins1[] = { 116, };
747		−static const unsigned int audio_spdif_out_pins2[] = { 142, };
748		−static const unsigned int audio_uart0_basic_pins[] = { 143, 142, 141, 144, };
749		−static const unsigned int audio_uart0_urfs_pins0[] = { 117, };
750		−static const unsigned int audio_uart0_urfs_pins1[] = { 139, };
751		−static const unsigned int audio_uart0_urfs_pins2[] = { 163, };
752		−static const unsigned int audio_uart0_urfs_pins3[] = { 162, };
753		−static const unsigned int audio_uart1_basic_pins[] = { 147, 146, 145, 148, };
754		−static const unsigned int audio_uart1_urfs_pins0[] = { 117, };
755		−static const unsigned int audio_uart1_urfs_pins1[] = { 140, };
756		−static const unsigned int audio_uart1_urfs_pins2[] = { 163, };
757		−static const unsigned int audio_uart2_urfs_pins0[] = { 139, };
758		−static const unsigned int audio_uart2_urfs_pins1[] = { 163, };
759		−static const unsigned int audio_uart2_urfs_pins2[] = { 96, };
760		−static const unsigned int audio_uart2_urxd_pins0[] = { 20, };
761		−static const unsigned int audio_uart2_urxd_pins1[] = { 109, };
762		−static const unsigned int audio_uart2_urxd_pins2[] = { 93, };
763		−static const unsigned int audio_uart2_usclk_pins0[] = { 19, };
764		−static const unsigned int audio_uart2_usclk_pins1[] = { 101, };
765		−static const unsigned int audio_uart2_usclk_pins2[] = { 91, };
766		−static const unsigned int audio_uart2_utfs_pins0[] = { 18, };
767		−static const unsigned int audio_uart2_utfs_pins1[] = { 111, };
768		−static const unsigned int audio_uart2_utfs_pins2[] = { 94, };
769		−static const unsigned int audio_uart2_utxd_pins0[] = { 21, };
770		−static const unsigned int audio_uart2_utxd_pins1[] = { 110, };
771		−static const unsigned int audio_uart2_utxd_pins2[] = { 92, };
772		−static const unsigned int c_can_trnsvr_en_pins0[] = { 2, };
773		−static const unsigned int c_can_trnsvr_en_pins1[] = { 0, };
774		−static const unsigned int c_can_trnsvr_intr_pins[] = { 1, };
775		−static const unsigned int c_can_trnsvr_stb_n_pins[] = { 3, };
776		−static const unsigned int c0_can_rxd_trnsv0_pins[] = { 11, };
777		−static const unsigned int c0_can_rxd_trnsv1_pins[] = { 2, };
778		−static const unsigned int c0_can_txd_trnsv0_pins[] = { 10, };
779		−static const unsigned int c0_can_txd_trnsv1_pins[] = { 3, };
780		−static const unsigned int c1_can_rxd_pins0[] = { 138, };
781		−static const unsigned int c1_can_rxd_pins1[] = { 147, };
782		−static const unsigned int c1_can_rxd_pins2[] = { 2, };
783		−static const unsigned int c1_can_rxd_pins3[] = { 162, };
784		−static const unsigned int c1_can_txd_pins0[] = { 137, };
785		−static const unsigned int c1_can_txd_pins1[] = { 146, };
786		−static const unsigned int c1_can_txd_pins2[] = { 3, };
787		−static const unsigned int c1_can_txd_pins3[] = { 161, };
788		−static const unsigned int ca_audio_lpc_pins[] = { 62, 63, 64, 65, 66, 67, 68,
789		− 69, 70, 71, };
790		−static const unsigned int ca_bt_lpc_pins[] = { 85, 86, 87, 88, 89, 90, };
791		−static const unsigned int ca_coex_pins[] = { 129, 130, 131, 132, };
792		−static const unsigned int ca_curator_lpc_pins[] = { 57, 58, 59, 60, };
793		−static const unsigned int ca_pcm_debug_pins[] = { 91, 93, 94, 92, };
794		−static const unsigned int ca_pio_pins[] = { 121, 122, 125, 126, 38, 37, 47,
795		− 49, 50, 54, 55, 56, };
796		−static const unsigned int ca_sdio_debug_pins[] = { 40, 39, 44, 43, 42, 41, };
797		−static const unsigned int ca_spi_pins[] = { 82, 79, 80, 81, };
798		−static const unsigned int ca_trb_pins[] = { 91, 93, 94, 95, 96, 78, 74, 75,
799		− 76, 77, };
800		−static const unsigned int ca_uart_debug_pins[] = { 136, 135, 134, 133, };
801		−static const unsigned int clkc_pins0[] = { 30, 47, };
802		−static const unsigned int clkc_pins1[] = { 78, 54, };
803		−static const unsigned int gn_gnss_i2c_pins[] = { 128, 127, };
804		−static const unsigned int gn_gnss_uart_nopause_pins[] = { 134, 133, };
805		−static const unsigned int gn_gnss_uart_pins[] = { 134, 133, 136, 135, };
806		−static const unsigned int gn_trg_spi_pins0[] = { 22, 25, 23, 24, };
807		−static const unsigned int gn_trg_spi_pins1[] = { 82, 79, 80, 81, };
808		−static const unsigned int cvbs_dbg_pins[] = { 54, 53, 82, 74, 75, 76, 77, 78,
809		− 79, 80, 81, 83, 84, 73, 55, 56, };
810		−static const unsigned int cvbs_dbg_test_pins0[] = { 57, };
811		−static const unsigned int cvbs_dbg_test_pins1[] = { 58, };
812		−static const unsigned int cvbs_dbg_test_pins2[] = { 59, };
813		−static const unsigned int cvbs_dbg_test_pins3[] = { 60, };
814		−static const unsigned int cvbs_dbg_test_pins4[] = { 61, };
815		−static const unsigned int cvbs_dbg_test_pins5[] = { 62, };
816		−static const unsigned int cvbs_dbg_test_pins6[] = { 63, };
817		−static const unsigned int cvbs_dbg_test_pins7[] = { 64, };
818		−static const unsigned int cvbs_dbg_test_pins8[] = { 65, };
819		−static const unsigned int cvbs_dbg_test_pins9[] = { 66, };
820		−static const unsigned int cvbs_dbg_test_pins10[] = { 67, };
821		−static const unsigned int cvbs_dbg_test_pins11[] = { 68, };
822		−static const unsigned int cvbs_dbg_test_pins12[] = { 69, };
823		−static const unsigned int cvbs_dbg_test_pins13[] = { 70, };
824		−static const unsigned int cvbs_dbg_test_pins14[] = { 71, };
825		−static const unsigned int cvbs_dbg_test_pins15[] = { 72, };
826		−static const unsigned int gn_gnss_power_pins[] = { 123, 124, 121, 122, 125,
827		− 120, };
828		−static const unsigned int gn_gnss_sw_status_pins[] = { 57, 58, 59, 60, 61,
829		− 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 55, 56, 54, };
830		−static const unsigned int gn_gnss_eclk_pins[] = { 113, };
831		−static const unsigned int gn_gnss_irq1_pins0[] = { 112, };
832		−static const unsigned int gn_gnss_irq2_pins0[] = { 118, };
833		−static const unsigned int gn_gnss_tm_pins[] = { 115, };
834		−static const unsigned int gn_gnss_tsync_pins[] = { 114, };
835		−static const unsigned int gn_io_gnsssys_sw_cfg_pins[] = { 44, 43, 42, 41, 40,
836		− 39, 38, 37, 49, 50, 91, 92, 93, 94, 95, 96, };
837		−static const unsigned int gn_trg_pins0[] = { 29, 28, 26, 27, };
838		−static const unsigned int gn_trg_pins1[] = { 77, 76, 74, 75, };
839		−static const unsigned int gn_trg_shutdown_pins0[] = { 30, };
840		−static const unsigned int gn_trg_shutdown_pins1[] = { 83, };
841		−static const unsigned int gn_trg_shutdown_pins2[] = { 117, };
842		−static const unsigned int gn_trg_shutdown_pins3[] = { 123, };
843		−static const unsigned int i2c0_pins[] = { 128, 127, };
844		−static const unsigned int i2c1_pins[] = { 126, 125, };
845		−static const unsigned int i2s0_pins[] = { 91, 93, 94, 92, };
846		−static const unsigned int i2s1_basic_pins[] = { 95, 96, };
847		−static const unsigned int i2s1_rxd0_pins0[] = { 61, };
848		−static const unsigned int i2s1_rxd0_pins1[] = { 131, };
849		−static const unsigned int i2s1_rxd0_pins2[] = { 129, };
850		−static const unsigned int i2s1_rxd0_pins3[] = { 117, };
851		−static const unsigned int i2s1_rxd0_pins4[] = { 83, };
852		−static const unsigned int i2s1_rxd1_pins0[] = { 72, };
853		−static const unsigned int i2s1_rxd1_pins1[] = { 132, };
854		−static const unsigned int i2s1_rxd1_pins2[] = { 130, };
855		−static const unsigned int i2s1_rxd1_pins3[] = { 118, };
856		−static const unsigned int i2s1_rxd1_pins4[] = { 84, };
857		−static const unsigned int jtag_jt_dbg_nsrst_pins[] = { 125, };
858		−static const unsigned int jtag_ntrst_pins0[] = { 4, };
859		−static const unsigned int jtag_ntrst_pins1[] = { 163, };
860		−static const unsigned int jtag_swdiotms_pins0[] = { 2, };
861		−static const unsigned int jtag_swdiotms_pins1[] = { 160, };
862		−static const unsigned int jtag_tck_pins0[] = { 0, };
863		−static const unsigned int jtag_tck_pins1[] = { 161, };
864		−static const unsigned int jtag_tdi_pins0[] = { 1, };
865		−static const unsigned int jtag_tdi_pins1[] = { 162, };
866		−static const unsigned int jtag_tdo_pins0[] = { 3, };
867		−static const unsigned int jtag_tdo_pins1[] = { 159, };
868		−static const unsigned int ks_kas_spi_pins0[] = { 141, 144, 143, 142, };
869		−static const unsigned int ld_ldd_pins[] = { 57, 58, 59, 60, 61, 62, 63, 64,
870		− 65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79, 80,
871		− 81, 56, 53, };
872		−static const unsigned int ld_ldd_16bit_pins[] = { 57, 58, 59, 60, 61, 62, 63,
873		− 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, };
874		−static const unsigned int ld_ldd_fck_pins[] = { 55, };
875		−static const unsigned int ld_ldd_lck_pins[] = { 54, };
876		−static const unsigned int lr_lcdrom_pins[] = { 73, 54, 57, 58, 59, 60, 61,
877		− 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, 55, };
878		−static const unsigned int lvds_analog_pins[] = { 149, 150, 151, 152, 153, 154,
879		− 155, 156, 157, 158, };
880		−static const unsigned int nd_df_basic_pins[] = { 44, 43, 42, 41, 40, 39, 38,
881		− 37, 47, 46, 52, 45, 49, 50, 48, };
882		−static const unsigned int nd_df_wp_pins[] = { 124, };
883		−static const unsigned int nd_df_cs_pins[] = { 51, };
884		−static const unsigned int ps_pins[] = { 120, 119, 121, };
885		−static const unsigned int ps_no_dir_pins[] = { 119, };
886		−static const unsigned int pwc_core_on_pins[] = { 8, };
887		−static const unsigned int pwc_ext_on_pins[] = { 6, };
888		−static const unsigned int pwc_gpio3_clk_pins[] = { 3, };
889		−static const unsigned int pwc_io_on_pins[] = { 9, };
890		−static const unsigned int pwc_lowbatt_b_pins0[] = { 4, };
891		−static const unsigned int pwc_mem_on_pins[] = { 7, };
892		−static const unsigned int pwc_on_key_b_pins0[] = { 5, };
893		−static const unsigned int pwc_wakeup_src0_pins[] = { 0, };
894		−static const unsigned int pwc_wakeup_src1_pins[] = { 1, };
895		−static const unsigned int pwc_wakeup_src2_pins[] = { 2, };
896		−static const unsigned int pwc_wakeup_src3_pins[] = { 3, };
897		−static const unsigned int pw_cko0_pins0[] = { 123, };
898		−static const unsigned int pw_cko0_pins1[] = { 101, };
899		−static const unsigned int pw_cko0_pins2[] = { 82, };
900		−static const unsigned int pw_cko0_pins3[] = { 162, };
901		−static const unsigned int pw_cko1_pins0[] = { 124, };
902		−static const unsigned int pw_cko1_pins1[] = { 110, };
903		−static const unsigned int pw_cko1_pins2[] = { 163, };
904		−static const unsigned int pw_i2s01_clk_pins0[] = { 125, };
905		−static const unsigned int pw_i2s01_clk_pins1[] = { 117, };
906		−static const unsigned int pw_i2s01_clk_pins2[] = { 132, };
907		−static const unsigned int pw_pwm0_pins0[] = { 119, };
908		−static const unsigned int pw_pwm0_pins1[] = { 159, };
909		−static const unsigned int pw_pwm1_pins0[] = { 120, };
910		−static const unsigned int pw_pwm1_pins1[] = { 160, };
911		−static const unsigned int pw_pwm1_pins2[] = { 131, };
912		−static const unsigned int pw_pwm2_pins0[] = { 121, };
913		−static const unsigned int pw_pwm2_pins1[] = { 98, };
914		−static const unsigned int pw_pwm2_pins2[] = { 161, };
915		−static const unsigned int pw_pwm3_pins0[] = { 122, };
916		−static const unsigned int pw_pwm3_pins1[] = { 73, };
917		−static const unsigned int pw_pwm_cpu_vol_pins0[] = { 121, };
918		−static const unsigned int pw_pwm_cpu_vol_pins1[] = { 98, };
919		−static const unsigned int pw_pwm_cpu_vol_pins2[] = { 161, };
920		−static const unsigned int pw_backlight_pins0[] = { 122, };
921		−static const unsigned int pw_backlight_pins1[] = { 73, };
922		−static const unsigned int rg_eth_mac_pins[] = { 108, 103, 104, 105, 106, 107,
923		− 102, 97, 98, 99, 100, 101, };
924		−static const unsigned int rg_gmac_phy_intr_n_pins[] = { 111, };
925		−static const unsigned int rg_rgmii_mac_pins[] = { 109, 110, };
926		−static const unsigned int rg_rgmii_phy_ref_clk_pins0[] = { 111, };
927		−static const unsigned int rg_rgmii_phy_ref_clk_pins1[] = { 53, };
928		−static const unsigned int sd0_pins[] = { 46, 47, 44, 43, 42, 41, 40, 39, 38,
929		− 37, };
930		−static const unsigned int sd0_4bit_pins[] = { 46, 47, 44, 43, 42, 41, };
931		−static const unsigned int sd1_pins[] = { 48, 49, 44, 43, 42, 41, 40, 39, 38,
932		− 37, };
933		−static const unsigned int sd1_4bit_pins0[] = { 48, 49, 44, 43, 42, 41, };
934		−static const unsigned int sd1_4bit_pins1[] = { 48, 49, 40, 39, 38, 37, };
935		−static const unsigned int sd2_basic_pins[] = { 31, 32, 33, 34, 35, 36, };
936		−static const unsigned int sd2_cdb_pins0[] = { 124, };
937		−static const unsigned int sd2_cdb_pins1[] = { 161, };
938		−static const unsigned int sd2_wpb_pins0[] = { 123, };
939		−static const unsigned int sd2_wpb_pins1[] = { 163, };
940		−static const unsigned int sd3_9_pins[] = { 85, 86, 87, 88, 89, 90, };
941		−static const unsigned int sd5_pins[] = { 91, 92, 93, 94, 95, 96, };
942		−static const unsigned int sd6_pins0[] = { 79, 78, 74, 75, 76, 77, };
943		−static const unsigned int sd6_pins1[] = { 101, 99, 100, 110, 109, 111, };
944		−static const unsigned int sp0_ext_ldo_on_pins[] = { 4, };
945		−static const unsigned int sp0_qspi_pins[] = { 12, 13, 14, 15, 16, 17, };
946		−static const unsigned int sp1_spi_pins[] = { 19, 20, 21, 18, };
947		−static const unsigned int tpiu_trace_pins[] = { 53, 56, 57, 58, 59, 60, 61,
948		− 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, };
949		−static const unsigned int uart0_pins[] = { 121, 120, 134, 133, };
950		−static const unsigned int uart0_nopause_pins[] = { 134, 133, };
951		−static const unsigned int uart1_pins[] = { 136, 135, };
952		−static const unsigned int uart2_cts_pins0[] = { 132, };
953		−static const unsigned int uart2_cts_pins1[] = { 162, };
954		−static const unsigned int uart2_rts_pins0[] = { 131, };
955		−static const unsigned int uart2_rts_pins1[] = { 161, };
956		−static const unsigned int uart2_rxd_pins0[] = { 11, };
957		−static const unsigned int uart2_rxd_pins1[] = { 160, };
958		−static const unsigned int uart2_rxd_pins2[] = { 130, };
959		−static const unsigned int uart2_txd_pins0[] = { 10, };
960		−static const unsigned int uart2_txd_pins1[] = { 159, };
961		−static const unsigned int uart2_txd_pins2[] = { 129, };
962		−static const unsigned int uart3_cts_pins0[] = { 125, };
963		−static const unsigned int uart3_cts_pins1[] = { 111, };
964		−static const unsigned int uart3_cts_pins2[] = { 140, };
965		−static const unsigned int uart3_rts_pins0[] = { 126, };
966		−static const unsigned int uart3_rts_pins1[] = { 109, };
967		−static const unsigned int uart3_rts_pins2[] = { 139, };
968		−static const unsigned int uart3_rxd_pins0[] = { 138, };
969		−static const unsigned int uart3_rxd_pins1[] = { 84, };
970		−static const unsigned int uart3_rxd_pins2[] = { 162, };
971		−static const unsigned int uart3_txd_pins0[] = { 137, };
972		−static const unsigned int uart3_txd_pins1[] = { 83, };
973		−static const unsigned int uart3_txd_pins2[] = { 161, };
974		−static const unsigned int uart4_basic_pins[] = { 140, 139, };
975		−static const unsigned int uart4_cts_pins0[] = { 122, };
976		−static const unsigned int uart4_cts_pins1[] = { 100, };
977		−static const unsigned int uart4_cts_pins2[] = { 117, };
978		−static const unsigned int uart4_rts_pins0[] = { 123, };
979		−static const unsigned int uart4_rts_pins1[] = { 99, };
980		−static const unsigned int uart4_rts_pins2[] = { 116, };
981		−static const unsigned int usb0_drvvbus_pins0[] = { 51, };
982		−static const unsigned int usb0_drvvbus_pins1[] = { 162, };
983		−static const unsigned int usb1_drvvbus_pins0[] = { 134, };
984		−static const unsigned int usb1_drvvbus_pins1[] = { 163, };
985		−static const unsigned int visbus_dout_pins[] = { 57, 58, 59, 60, 61, 62, 63,
986		− 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 54, 55, 56, 85, 86,
987		− 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, };
988		−static const unsigned int vi_vip1_pins[] = { 74, 75, 76, 77, 78, 79, 80, 81,
989		− 82, 83, 84, 103, 104, 105, 106, 107, 102, 97, 98, };
990		−static const unsigned int vi_vip1_ext_pins[] = { 74, 75, 76, 77, 78, 79, 80,
991		− 81, 82, 83, 84, 108, 103, 104, 105, 106, 107, 102, 97, 98,
992		− 99, 100, };
993		−static const unsigned int vi_vip1_low8bit_pins[] = { 74, 75, 76, 77, 78, 79,
994		− 80, 81, 82, 83, 84, };
995		−static const unsigned int vi_vip1_high8bit_pins[] = { 82, 83, 84, 103, 104,
996		− 105, 106, 107, 102, 97, 98, };
997		−
998		−/* definition of pin group table */
999		−static struct atlas7_pin_group altas7_pin_groups[] = {
1000		− GROUP("gnss_gpio_grp", gnss_gpio_pins),
1001		− GROUP("lcd_vip_gpio_grp", lcd_vip_gpio_pins),
1002		− GROUP("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins),
1003		− GROUP("sp_rgmii_gpio_grp", sp_rgmii_gpio_pins),
1004		− GROUP("lvds_gpio_grp", lvds_gpio_pins),
1005		− GROUP("jtag_uart_nand_gpio_grp", jtag_uart_nand_gpio_pins),
1006		− GROUP("rtc_gpio_grp", rtc_gpio_pins),
1007		− GROUP("audio_ac97_grp", audio_ac97_pins),
1008		− GROUP("audio_digmic_grp0", audio_digmic_pins0),
1009		− GROUP("audio_digmic_grp1", audio_digmic_pins1),
1010		− GROUP("audio_digmic_grp2", audio_digmic_pins2),
1011		− GROUP("audio_func_dbg_grp", audio_func_dbg_pins),
1012		− GROUP("audio_i2s_grp", audio_i2s_pins),
1013		− GROUP("audio_i2s_2ch_grp", audio_i2s_2ch_pins),
1014		− GROUP("audio_i2s_extclk_grp", audio_i2s_extclk_pins),
1015		− GROUP("audio_spdif_out_grp0", audio_spdif_out_pins0),
1016		− GROUP("audio_spdif_out_grp1", audio_spdif_out_pins1),
1017		− GROUP("audio_spdif_out_grp2", audio_spdif_out_pins2),
1018		− GROUP("audio_uart0_basic_grp", audio_uart0_basic_pins),
1019		− GROUP("audio_uart0_urfs_grp0", audio_uart0_urfs_pins0),
1020		− GROUP("audio_uart0_urfs_grp1", audio_uart0_urfs_pins1),
1021		− GROUP("audio_uart0_urfs_grp2", audio_uart0_urfs_pins2),
1022		− GROUP("audio_uart0_urfs_grp3", audio_uart0_urfs_pins3),
1023		− GROUP("audio_uart1_basic_grp", audio_uart1_basic_pins),
1024		− GROUP("audio_uart1_urfs_grp0", audio_uart1_urfs_pins0),
1025		− GROUP("audio_uart1_urfs_grp1", audio_uart1_urfs_pins1),
1026		− GROUP("audio_uart1_urfs_grp2", audio_uart1_urfs_pins2),
1027		− GROUP("audio_uart2_urfs_grp0", audio_uart2_urfs_pins0),
1028		− GROUP("audio_uart2_urfs_grp1", audio_uart2_urfs_pins1),
1029		− GROUP("audio_uart2_urfs_grp2", audio_uart2_urfs_pins2),
1030		− GROUP("audio_uart2_urxd_grp0", audio_uart2_urxd_pins0),
1031		− GROUP("audio_uart2_urxd_grp1", audio_uart2_urxd_pins1),
1032		− GROUP("audio_uart2_urxd_grp2", audio_uart2_urxd_pins2),
1033		− GROUP("audio_uart2_usclk_grp0", audio_uart2_usclk_pins0),
1034		− GROUP("audio_uart2_usclk_grp1", audio_uart2_usclk_pins1),
1035		− GROUP("audio_uart2_usclk_grp2", audio_uart2_usclk_pins2),
1036		− GROUP("audio_uart2_utfs_grp0", audio_uart2_utfs_pins0),
1037		− GROUP("audio_uart2_utfs_grp1", audio_uart2_utfs_pins1),
1038		− GROUP("audio_uart2_utfs_grp2", audio_uart2_utfs_pins2),
1039		− GROUP("audio_uart2_utxd_grp0", audio_uart2_utxd_pins0),
1040		− GROUP("audio_uart2_utxd_grp1", audio_uart2_utxd_pins1),
1041		− GROUP("audio_uart2_utxd_grp2", audio_uart2_utxd_pins2),
1042		− GROUP("c_can_trnsvr_en_grp0", c_can_trnsvr_en_pins0),
1043		− GROUP("c_can_trnsvr_en_grp1", c_can_trnsvr_en_pins1),
1044		− GROUP("c_can_trnsvr_intr_grp", c_can_trnsvr_intr_pins),
1045		− GROUP("c_can_trnsvr_stb_n_grp", c_can_trnsvr_stb_n_pins),
1046		− GROUP("c0_can_rxd_trnsv0_grp", c0_can_rxd_trnsv0_pins),
1047		− GROUP("c0_can_rxd_trnsv1_grp", c0_can_rxd_trnsv1_pins),
1048		− GROUP("c0_can_txd_trnsv0_grp", c0_can_txd_trnsv0_pins),
1049		− GROUP("c0_can_txd_trnsv1_grp", c0_can_txd_trnsv1_pins),
1050		− GROUP("c1_can_rxd_grp0", c1_can_rxd_pins0),
1051		− GROUP("c1_can_rxd_grp1", c1_can_rxd_pins1),
1052		− GROUP("c1_can_rxd_grp2", c1_can_rxd_pins2),
1053		− GROUP("c1_can_rxd_grp3", c1_can_rxd_pins3),
1054		− GROUP("c1_can_txd_grp0", c1_can_txd_pins0),
1055		− GROUP("c1_can_txd_grp1", c1_can_txd_pins1),
1056		− GROUP("c1_can_txd_grp2", c1_can_txd_pins2),
1057		− GROUP("c1_can_txd_grp3", c1_can_txd_pins3),
1058		− GROUP("ca_audio_lpc_grp", ca_audio_lpc_pins),
1059		− GROUP("ca_bt_lpc_grp", ca_bt_lpc_pins),
1060		− GROUP("ca_coex_grp", ca_coex_pins),
1061		− GROUP("ca_curator_lpc_grp", ca_curator_lpc_pins),
1062		− GROUP("ca_pcm_debug_grp", ca_pcm_debug_pins),
1063		− GROUP("ca_pio_grp", ca_pio_pins),
1064		− GROUP("ca_sdio_debug_grp", ca_sdio_debug_pins),
1065		− GROUP("ca_spi_grp", ca_spi_pins),
1066		− GROUP("ca_trb_grp", ca_trb_pins),
1067		− GROUP("ca_uart_debug_grp", ca_uart_debug_pins),
1068		− GROUP("clkc_grp0", clkc_pins0),
1069		− GROUP("clkc_grp1", clkc_pins1),
1070		− GROUP("gn_gnss_i2c_grp", gn_gnss_i2c_pins),
1071		− GROUP("gn_gnss_uart_nopause_grp", gn_gnss_uart_nopause_pins),
1072		− GROUP("gn_gnss_uart_grp", gn_gnss_uart_pins),
1073		− GROUP("gn_trg_spi_grp0", gn_trg_spi_pins0),
1074		− GROUP("gn_trg_spi_grp1", gn_trg_spi_pins1),
1075		− GROUP("cvbs_dbg_grp", cvbs_dbg_pins),
1076		− GROUP("cvbs_dbg_test_grp0", cvbs_dbg_test_pins0),
1077		− GROUP("cvbs_dbg_test_grp1", cvbs_dbg_test_pins1),
1078		− GROUP("cvbs_dbg_test_grp2", cvbs_dbg_test_pins2),
1079		− GROUP("cvbs_dbg_test_grp3", cvbs_dbg_test_pins3),
1080		− GROUP("cvbs_dbg_test_grp4", cvbs_dbg_test_pins4),
1081		− GROUP("cvbs_dbg_test_grp5", cvbs_dbg_test_pins5),
1082		− GROUP("cvbs_dbg_test_grp6", cvbs_dbg_test_pins6),
1083		− GROUP("cvbs_dbg_test_grp7", cvbs_dbg_test_pins7),
1084		− GROUP("cvbs_dbg_test_grp8", cvbs_dbg_test_pins8),
1085		− GROUP("cvbs_dbg_test_grp9", cvbs_dbg_test_pins9),
1086		− GROUP("cvbs_dbg_test_grp10", cvbs_dbg_test_pins10),
1087		− GROUP("cvbs_dbg_test_grp11", cvbs_dbg_test_pins11),
1088		− GROUP("cvbs_dbg_test_grp12", cvbs_dbg_test_pins12),
1089		− GROUP("cvbs_dbg_test_grp13", cvbs_dbg_test_pins13),
1090		− GROUP("cvbs_dbg_test_grp14", cvbs_dbg_test_pins14),
1091		− GROUP("cvbs_dbg_test_grp15", cvbs_dbg_test_pins15),
1092		− GROUP("gn_gnss_power_grp", gn_gnss_power_pins),
1093		− GROUP("gn_gnss_sw_status_grp", gn_gnss_sw_status_pins),
1094		− GROUP("gn_gnss_eclk_grp", gn_gnss_eclk_pins),
1095		− GROUP("gn_gnss_irq1_grp0", gn_gnss_irq1_pins0),
1096		− GROUP("gn_gnss_irq2_grp0", gn_gnss_irq2_pins0),
1097		− GROUP("gn_gnss_tm_grp", gn_gnss_tm_pins),
1098		− GROUP("gn_gnss_tsync_grp", gn_gnss_tsync_pins),
1099		− GROUP("gn_io_gnsssys_sw_cfg_grp", gn_io_gnsssys_sw_cfg_pins),
1100		− GROUP("gn_trg_grp0", gn_trg_pins0),
1101		− GROUP("gn_trg_grp1", gn_trg_pins1),
1102		− GROUP("gn_trg_shutdown_grp0", gn_trg_shutdown_pins0),
1103		− GROUP("gn_trg_shutdown_grp1", gn_trg_shutdown_pins1),
1104		− GROUP("gn_trg_shutdown_grp2", gn_trg_shutdown_pins2),
1105		− GROUP("gn_trg_shutdown_grp3", gn_trg_shutdown_pins3),
1106		− GROUP("i2c0_grp", i2c0_pins),
1107		− GROUP("i2c1_grp", i2c1_pins),
1108		− GROUP("i2s0_grp", i2s0_pins),
1109		− GROUP("i2s1_basic_grp", i2s1_basic_pins),
1110		− GROUP("i2s1_rxd0_grp0", i2s1_rxd0_pins0),
1111		− GROUP("i2s1_rxd0_grp1", i2s1_rxd0_pins1),
1112		− GROUP("i2s1_rxd0_grp2", i2s1_rxd0_pins2),
1113		− GROUP("i2s1_rxd0_grp3", i2s1_rxd0_pins3),
1114		− GROUP("i2s1_rxd0_grp4", i2s1_rxd0_pins4),
1115		− GROUP("i2s1_rxd1_grp0", i2s1_rxd1_pins0),
1116		− GROUP("i2s1_rxd1_grp1", i2s1_rxd1_pins1),
1117		− GROUP("i2s1_rxd1_grp2", i2s1_rxd1_pins2),
1118		− GROUP("i2s1_rxd1_grp3", i2s1_rxd1_pins3),
1119		− GROUP("i2s1_rxd1_grp4", i2s1_rxd1_pins4),
1120		− GROUP("jtag_jt_dbg_nsrst_grp", jtag_jt_dbg_nsrst_pins),
1121		− GROUP("jtag_ntrst_grp0", jtag_ntrst_pins0),
1122		− GROUP("jtag_ntrst_grp1", jtag_ntrst_pins1),
1123		− GROUP("jtag_swdiotms_grp0", jtag_swdiotms_pins0),
1124		− GROUP("jtag_swdiotms_grp1", jtag_swdiotms_pins1),
1125		− GROUP("jtag_tck_grp0", jtag_tck_pins0),
1126		− GROUP("jtag_tck_grp1", jtag_tck_pins1),
1127		− GROUP("jtag_tdi_grp0", jtag_tdi_pins0),
1128		− GROUP("jtag_tdi_grp1", jtag_tdi_pins1),
1129		− GROUP("jtag_tdo_grp0", jtag_tdo_pins0),
1130		− GROUP("jtag_tdo_grp1", jtag_tdo_pins1),
1131		− GROUP("ks_kas_spi_grp0", ks_kas_spi_pins0),
1132		− GROUP("ld_ldd_grp", ld_ldd_pins),
1133		− GROUP("ld_ldd_16bit_grp", ld_ldd_16bit_pins),
1134		− GROUP("ld_ldd_fck_grp", ld_ldd_fck_pins),
1135		− GROUP("ld_ldd_lck_grp", ld_ldd_lck_pins),
1136		− GROUP("lr_lcdrom_grp", lr_lcdrom_pins),
1137		− GROUP("lvds_analog_grp", lvds_analog_pins),
1138		− GROUP("nd_df_basic_grp", nd_df_basic_pins),
1139		− GROUP("nd_df_wp_grp", nd_df_wp_pins),
1140		− GROUP("nd_df_cs_grp", nd_df_cs_pins),
1141		− GROUP("ps_grp", ps_pins),
1142		− GROUP("ps_no_dir_grp", ps_no_dir_pins),
1143		− GROUP("pwc_core_on_grp", pwc_core_on_pins),
1144		− GROUP("pwc_ext_on_grp", pwc_ext_on_pins),
1145		− GROUP("pwc_gpio3_clk_grp", pwc_gpio3_clk_pins),
1146		− GROUP("pwc_io_on_grp", pwc_io_on_pins),
1147		− GROUP("pwc_lowbatt_b_grp0", pwc_lowbatt_b_pins0),
1148		− GROUP("pwc_mem_on_grp", pwc_mem_on_pins),
1149		− GROUP("pwc_on_key_b_grp0", pwc_on_key_b_pins0),
1150		− GROUP("pwc_wakeup_src0_grp", pwc_wakeup_src0_pins),
1151		− GROUP("pwc_wakeup_src1_grp", pwc_wakeup_src1_pins),
1152		− GROUP("pwc_wakeup_src2_grp", pwc_wakeup_src2_pins),
1153		− GROUP("pwc_wakeup_src3_grp", pwc_wakeup_src3_pins),
1154		− GROUP("pw_cko0_grp0", pw_cko0_pins0),
1155		− GROUP("pw_cko0_grp1", pw_cko0_pins1),
1156		− GROUP("pw_cko0_grp2", pw_cko0_pins2),
1157		− GROUP("pw_cko0_grp3", pw_cko0_pins3),
1158		− GROUP("pw_cko1_grp0", pw_cko1_pins0),
1159		− GROUP("pw_cko1_grp1", pw_cko1_pins1),
1160		− GROUP("pw_cko1_grp2", pw_cko1_pins2),
1161		− GROUP("pw_i2s01_clk_grp0", pw_i2s01_clk_pins0),
1162		− GROUP("pw_i2s01_clk_grp1", pw_i2s01_clk_pins1),
1163		− GROUP("pw_i2s01_clk_grp2", pw_i2s01_clk_pins2),
1164		− GROUP("pw_pwm0_grp0", pw_pwm0_pins0),
1165		− GROUP("pw_pwm0_grp1", pw_pwm0_pins1),
1166		− GROUP("pw_pwm1_grp0", pw_pwm1_pins0),
1167		− GROUP("pw_pwm1_grp1", pw_pwm1_pins1),
1168		− GROUP("pw_pwm1_grp2", pw_pwm1_pins2),
1169		− GROUP("pw_pwm2_grp0", pw_pwm2_pins0),
1170		− GROUP("pw_pwm2_grp1", pw_pwm2_pins1),
1171		− GROUP("pw_pwm2_grp2", pw_pwm2_pins2),
1172		− GROUP("pw_pwm3_grp0", pw_pwm3_pins0),
1173		− GROUP("pw_pwm3_grp1", pw_pwm3_pins1),
1174		− GROUP("pw_pwm_cpu_vol_grp0", pw_pwm_cpu_vol_pins0),
1175		− GROUP("pw_pwm_cpu_vol_grp1", pw_pwm_cpu_vol_pins1),
1176		− GROUP("pw_pwm_cpu_vol_grp2", pw_pwm_cpu_vol_pins2),
1177		− GROUP("pw_backlight_grp0", pw_backlight_pins0),
1178		− GROUP("pw_backlight_grp1", pw_backlight_pins1),
1179		− GROUP("rg_eth_mac_grp", rg_eth_mac_pins),
1180		− GROUP("rg_gmac_phy_intr_n_grp", rg_gmac_phy_intr_n_pins),
1181		− GROUP("rg_rgmii_mac_grp", rg_rgmii_mac_pins),
1182		− GROUP("rg_rgmii_phy_ref_clk_grp0", rg_rgmii_phy_ref_clk_pins0),
1183		− GROUP("rg_rgmii_phy_ref_clk_grp1", rg_rgmii_phy_ref_clk_pins1),
1184		− GROUP("sd0_grp", sd0_pins),
1185		− GROUP("sd0_4bit_grp", sd0_4bit_pins),
1186		− GROUP("sd1_grp", sd1_pins),
1187		− GROUP("sd1_4bit_grp0", sd1_4bit_pins0),
1188		− GROUP("sd1_4bit_grp1", sd1_4bit_pins1),
1189		− GROUP("sd2_basic_grp", sd2_basic_pins),
1190		− GROUP("sd2_cdb_grp0", sd2_cdb_pins0),
1191		− GROUP("sd2_cdb_grp1", sd2_cdb_pins1),
1192		− GROUP("sd2_wpb_grp0", sd2_wpb_pins0),
1193		− GROUP("sd2_wpb_grp1", sd2_wpb_pins1),
1194		− GROUP("sd3_9_grp", sd3_9_pins),
1195		− GROUP("sd5_grp", sd5_pins),
1196		− GROUP("sd6_grp0", sd6_pins0),
1197		− GROUP("sd6_grp1", sd6_pins1),
1198		− GROUP("sp0_ext_ldo_on_grp", sp0_ext_ldo_on_pins),
1199		− GROUP("sp0_qspi_grp", sp0_qspi_pins),
1200		− GROUP("sp1_spi_grp", sp1_spi_pins),
1201		− GROUP("tpiu_trace_grp", tpiu_trace_pins),
1202		− GROUP("uart0_grp", uart0_pins),
1203		− GROUP("uart0_nopause_grp", uart0_nopause_pins),
1204		− GROUP("uart1_grp", uart1_pins),
1205		− GROUP("uart2_cts_grp0", uart2_cts_pins0),
1206		− GROUP("uart2_cts_grp1", uart2_cts_pins1),
1207		− GROUP("uart2_rts_grp0", uart2_rts_pins0),
1208		− GROUP("uart2_rts_grp1", uart2_rts_pins1),
1209		− GROUP("uart2_rxd_grp0", uart2_rxd_pins0),
1210		− GROUP("uart2_rxd_grp1", uart2_rxd_pins1),
1211		− GROUP("uart2_rxd_grp2", uart2_rxd_pins2),
1212		− GROUP("uart2_txd_grp0", uart2_txd_pins0),
1213		− GROUP("uart2_txd_grp1", uart2_txd_pins1),
1214		− GROUP("uart2_txd_grp2", uart2_txd_pins2),
1215		− GROUP("uart3_cts_grp0", uart3_cts_pins0),
1216		− GROUP("uart3_cts_grp1", uart3_cts_pins1),
1217		− GROUP("uart3_cts_grp2", uart3_cts_pins2),
1218		− GROUP("uart3_rts_grp0", uart3_rts_pins0),
1219		− GROUP("uart3_rts_grp1", uart3_rts_pins1),
1220		− GROUP("uart3_rts_grp2", uart3_rts_pins2),
1221		− GROUP("uart3_rxd_grp0", uart3_rxd_pins0),
1222		− GROUP("uart3_rxd_grp1", uart3_rxd_pins1),
1223		− GROUP("uart3_rxd_grp2", uart3_rxd_pins2),
1224		− GROUP("uart3_txd_grp0", uart3_txd_pins0),
1225		− GROUP("uart3_txd_grp1", uart3_txd_pins1),
1226		− GROUP("uart3_txd_grp2", uart3_txd_pins2),
1227		− GROUP("uart4_basic_grp", uart4_basic_pins),
1228		− GROUP("uart4_cts_grp0", uart4_cts_pins0),
1229		− GROUP("uart4_cts_grp1", uart4_cts_pins1),
1230		− GROUP("uart4_cts_grp2", uart4_cts_pins2),
1231		− GROUP("uart4_rts_grp0", uart4_rts_pins0),
1232		− GROUP("uart4_rts_grp1", uart4_rts_pins1),
1233		− GROUP("uart4_rts_grp2", uart4_rts_pins2),
1234		− GROUP("usb0_drvvbus_grp0", usb0_drvvbus_pins0),
1235		− GROUP("usb0_drvvbus_grp1", usb0_drvvbus_pins1),
1236		− GROUP("usb1_drvvbus_grp0", usb1_drvvbus_pins0),
1237		− GROUP("usb1_drvvbus_grp1", usb1_drvvbus_pins1),
1238		− GROUP("visbus_dout_grp", visbus_dout_pins),
1239		− GROUP("vi_vip1_grp", vi_vip1_pins),
1240		− GROUP("vi_vip1_ext_grp", vi_vip1_ext_pins),
1241		− GROUP("vi_vip1_low8bit_grp", vi_vip1_low8bit_pins),
1242		− GROUP("vi_vip1_high8bit_grp", vi_vip1_high8bit_pins),
1243		−};
1244		−
1245		−/* How many groups that a function can use */
1246		−static const char * const gnss_gpio_grp[] = { "gnss_gpio_grp", };
1247		−static const char * const lcd_vip_gpio_grp[] = { "lcd_vip_gpio_grp", };
1248		−static const char * const sdio_i2s_gpio_grp[] = { "sdio_i2s_gpio_grp", };
1249		−static const char * const sp_rgmii_gpio_grp[] = { "sp_rgmii_gpio_grp", };
1250		−static const char * const lvds_gpio_grp[] = { "lvds_gpio_grp", };
1251		−static const char * const jtag_uart_nand_gpio_grp[] = {
1252		− "jtag_uart_nand_gpio_grp", };
1253		−static const char * const rtc_gpio_grp[] = { "rtc_gpio_grp", };
1254		−static const char * const audio_ac97_grp[] = { "audio_ac97_grp", };
1255		−static const char * const audio_digmic_grp0[] = { "audio_digmic_grp0", };
1256		−static const char * const audio_digmic_grp1[] = { "audio_digmic_grp1", };
1257		−static const char * const audio_digmic_grp2[] = { "audio_digmic_grp2", };
1258		−static const char * const audio_func_dbg_grp[] = { "audio_func_dbg_grp", };
1259		−static const char * const audio_i2s_grp[] = { "audio_i2s_grp", };
1260		−static const char * const audio_i2s_2ch_grp[] = { "audio_i2s_2ch_grp", };
1261		−static const char * const audio_i2s_extclk_grp[] = { "audio_i2s_extclk_grp", };
1262		−static const char * const audio_spdif_out_grp0[] = { "audio_spdif_out_grp0", };
1263		−static const char * const audio_spdif_out_grp1[] = { "audio_spdif_out_grp1", };
1264		−static const char * const audio_spdif_out_grp2[] = { "audio_spdif_out_grp2", };
1265		−static const char * const audio_uart0_basic_grp[] = {
1266		− "audio_uart0_basic_grp", };
1267		−static const char * const audio_uart0_urfs_grp0[] = {
1268		− "audio_uart0_urfs_grp0", };
1269		−static const char * const audio_uart0_urfs_grp1[] = {
1270		− "audio_uart0_urfs_grp1", };
1271		−static const char * const audio_uart0_urfs_grp2[] = {
1272		− "audio_uart0_urfs_grp2", };
1273		−static const char * const audio_uart0_urfs_grp3[] = {
1274		− "audio_uart0_urfs_grp3", };
1275		−static const char * const audio_uart1_basic_grp[] = {
1276		− "audio_uart1_basic_grp", };
1277		−static const char * const audio_uart1_urfs_grp0[] = {
1278		− "audio_uart1_urfs_grp0", };
1279		−static const char * const audio_uart1_urfs_grp1[] = {
1280		− "audio_uart1_urfs_grp1", };
1281		−static const char * const audio_uart1_urfs_grp2[] = {
1282		− "audio_uart1_urfs_grp2", };
1283		−static const char * const audio_uart2_urfs_grp0[] = {
1284		− "audio_uart2_urfs_grp0", };
1285		−static const char * const audio_uart2_urfs_grp1[] = {
1286		− "audio_uart2_urfs_grp1", };
1287		−static const char * const audio_uart2_urfs_grp2[] = {
1288		− "audio_uart2_urfs_grp2", };
1289		−static const char * const audio_uart2_urxd_grp0[] = {
1290		− "audio_uart2_urxd_grp0", };
1291		−static const char * const audio_uart2_urxd_grp1[] = {
1292		− "audio_uart2_urxd_grp1", };
1293		−static const char * const audio_uart2_urxd_grp2[] = {
1294		− "audio_uart2_urxd_grp2", };
1295		−static const char * const audio_uart2_usclk_grp0[] = {
1296		− "audio_uart2_usclk_grp0", };
1297		−static const char * const audio_uart2_usclk_grp1[] = {
1298		− "audio_uart2_usclk_grp1", };
1299		−static const char * const audio_uart2_usclk_grp2[] = {
1300		− "audio_uart2_usclk_grp2", };
1301		−static const char * const audio_uart2_utfs_grp0[] = {
1302		− "audio_uart2_utfs_grp0", };
1303		−static const char * const audio_uart2_utfs_grp1[] = {
1304		− "audio_uart2_utfs_grp1", };
1305		−static const char * const audio_uart2_utfs_grp2[] = {
1306		− "audio_uart2_utfs_grp2", };
1307		−static const char * const audio_uart2_utxd_grp0[] = {
1308		− "audio_uart2_utxd_grp0", };
1309		−static const char * const audio_uart2_utxd_grp1[] = {
1310		− "audio_uart2_utxd_grp1", };
1311		−static const char * const audio_uart2_utxd_grp2[] = {
1312		− "audio_uart2_utxd_grp2", };
1313		−static const char * const c_can_trnsvr_en_grp0[] = { "c_can_trnsvr_en_grp0", };
1314		−static const char * const c_can_trnsvr_en_grp1[] = { "c_can_trnsvr_en_grp1", };
1315		−static const char * const c_can_trnsvr_intr_grp[] = {
1316		− "c_can_trnsvr_intr_grp", };
1317		−static const char * const c_can_trnsvr_stb_n_grp[] = {
1318		− "c_can_trnsvr_stb_n_grp", };
1319		−static const char * const c0_can_rxd_trnsv0_grp[] = {
1320		− "c0_can_rxd_trnsv0_grp", };
1321		−static const char * const c0_can_rxd_trnsv1_grp[] = {
1322		− "c0_can_rxd_trnsv1_grp", };
1323		−static const char * const c0_can_txd_trnsv0_grp[] = {
1324		− "c0_can_txd_trnsv0_grp", };
1325		−static const char * const c0_can_txd_trnsv1_grp[] = {
1326		− "c0_can_txd_trnsv1_grp", };
1327		−static const char * const c1_can_rxd_grp0[] = { "c1_can_rxd_grp0", };
1328		−static const char * const c1_can_rxd_grp1[] = { "c1_can_rxd_grp1", };
1329		−static const char * const c1_can_rxd_grp2[] = { "c1_can_rxd_grp2", };
1330		−static const char * const c1_can_rxd_grp3[] = { "c1_can_rxd_grp3", };
1331		−static const char * const c1_can_txd_grp0[] = { "c1_can_txd_grp0", };
1332		−static const char * const c1_can_txd_grp1[] = { "c1_can_txd_grp1", };
1333		−static const char * const c1_can_txd_grp2[] = { "c1_can_txd_grp2", };
1334		−static const char * const c1_can_txd_grp3[] = { "c1_can_txd_grp3", };
1335		−static const char * const ca_audio_lpc_grp[] = { "ca_audio_lpc_grp", };
1336		−static const char * const ca_bt_lpc_grp[] = { "ca_bt_lpc_grp", };
1337		−static const char * const ca_coex_grp[] = { "ca_coex_grp", };
1338		−static const char * const ca_curator_lpc_grp[] = { "ca_curator_lpc_grp", };
1339		−static const char * const ca_pcm_debug_grp[] = { "ca_pcm_debug_grp", };
1340		−static const char * const ca_pio_grp[] = { "ca_pio_grp", };
1341		−static const char * const ca_sdio_debug_grp[] = { "ca_sdio_debug_grp", };
1342		−static const char * const ca_spi_grp[] = { "ca_spi_grp", };
1343		−static const char * const ca_trb_grp[] = { "ca_trb_grp", };
1344		−static const char * const ca_uart_debug_grp[] = { "ca_uart_debug_grp", };
1345		−static const char * const clkc_grp0[] = { "clkc_grp0", };
1346		−static const char * const clkc_grp1[] = { "clkc_grp1", };
1347		−static const char * const gn_gnss_i2c_grp[] = { "gn_gnss_i2c_grp", };
1348		−static const char * const gn_gnss_uart_nopause_grp[] = {
1349		− "gn_gnss_uart_nopause_grp", };
1350		−static const char * const gn_gnss_uart_grp[] = { "gn_gnss_uart_grp", };
1351		−static const char * const gn_trg_spi_grp0[] = { "gn_trg_spi_grp0", };
1352		−static const char * const gn_trg_spi_grp1[] = { "gn_trg_spi_grp1", };
1353		−static const char * const cvbs_dbg_grp[] = { "cvbs_dbg_grp", };
1354		−static const char * const cvbs_dbg_test_grp0[] = { "cvbs_dbg_test_grp0", };
1355		−static const char * const cvbs_dbg_test_grp1[] = { "cvbs_dbg_test_grp1", };
1356		−static const char * const cvbs_dbg_test_grp2[] = { "cvbs_dbg_test_grp2", };
1357		−static const char * const cvbs_dbg_test_grp3[] = { "cvbs_dbg_test_grp3", };
1358		−static const char * const cvbs_dbg_test_grp4[] = { "cvbs_dbg_test_grp4", };
1359		−static const char * const cvbs_dbg_test_grp5[] = { "cvbs_dbg_test_grp5", };
1360		−static const char * const cvbs_dbg_test_grp6[] = { "cvbs_dbg_test_grp6", };
1361		−static const char * const cvbs_dbg_test_grp7[] = { "cvbs_dbg_test_grp7", };
1362		−static const char * const cvbs_dbg_test_grp8[] = { "cvbs_dbg_test_grp8", };
1363		−static const char * const cvbs_dbg_test_grp9[] = { "cvbs_dbg_test_grp9", };
1364		−static const char * const cvbs_dbg_test_grp10[] = { "cvbs_dbg_test_grp10", };
1365		−static const char * const cvbs_dbg_test_grp11[] = { "cvbs_dbg_test_grp11", };
1366		−static const char * const cvbs_dbg_test_grp12[] = { "cvbs_dbg_test_grp12", };
1367		−static const char * const cvbs_dbg_test_grp13[] = { "cvbs_dbg_test_grp13", };
1368		−static const char * const cvbs_dbg_test_grp14[] = { "cvbs_dbg_test_grp14", };
1369		−static const char * const cvbs_dbg_test_grp15[] = { "cvbs_dbg_test_grp15", };
1370		−static const char * const gn_gnss_power_grp[] = { "gn_gnss_power_grp", };
1371		−static const char * const gn_gnss_sw_status_grp[] = {
1372		− "gn_gnss_sw_status_grp", };
1373		−static const char * const gn_gnss_eclk_grp[] = { "gn_gnss_eclk_grp", };
1374		−static const char * const gn_gnss_irq1_grp0[] = { "gn_gnss_irq1_grp0", };
1375		−static const char * const gn_gnss_irq2_grp0[] = { "gn_gnss_irq2_grp0", };
1376		−static const char * const gn_gnss_tm_grp[] = { "gn_gnss_tm_grp", };
1377		−static const char * const gn_gnss_tsync_grp[] = { "gn_gnss_tsync_grp", };
1378		−static const char * const gn_io_gnsssys_sw_cfg_grp[] = {
1379		− "gn_io_gnsssys_sw_cfg_grp", };
1380		−static const char * const gn_trg_grp0[] = { "gn_trg_grp0", };
1381		−static const char * const gn_trg_grp1[] = { "gn_trg_grp1", };
1382		−static const char * const gn_trg_shutdown_grp0[] = { "gn_trg_shutdown_grp0", };
1383		−static const char * const gn_trg_shutdown_grp1[] = { "gn_trg_shutdown_grp1", };
1384		−static const char * const gn_trg_shutdown_grp2[] = { "gn_trg_shutdown_grp2", };
1385		−static const char * const gn_trg_shutdown_grp3[] = { "gn_trg_shutdown_grp3", };
1386		−static const char * const i2c0_grp[] = { "i2c0_grp", };
1387		−static const char * const i2c1_grp[] = { "i2c1_grp", };
1388		−static const char * const i2s0_grp[] = { "i2s0_grp", };
1389		−static const char * const i2s1_basic_grp[] = { "i2s1_basic_grp", };
1390		−static const char * const i2s1_rxd0_grp0[] = { "i2s1_rxd0_grp0", };
1391		−static const char * const i2s1_rxd0_grp1[] = { "i2s1_rxd0_grp1", };
1392		−static const char * const i2s1_rxd0_grp2[] = { "i2s1_rxd0_grp2", };
1393		−static const char * const i2s1_rxd0_grp3[] = { "i2s1_rxd0_grp3", };
1394		−static const char * const i2s1_rxd0_grp4[] = { "i2s1_rxd0_grp4", };
1395		−static const char * const i2s1_rxd1_grp0[] = { "i2s1_rxd1_grp0", };
1396		−static const char * const i2s1_rxd1_grp1[] = { "i2s1_rxd1_grp1", };
1397		−static const char * const i2s1_rxd1_grp2[] = { "i2s1_rxd1_grp2", };
1398		−static const char * const i2s1_rxd1_grp3[] = { "i2s1_rxd1_grp3", };
1399		−static const char * const i2s1_rxd1_grp4[] = { "i2s1_rxd1_grp4", };
1400		−static const char * const jtag_jt_dbg_nsrst_grp[] = {
1401		− "jtag_jt_dbg_nsrst_grp", };
1402		−static const char * const jtag_ntrst_grp0[] = { "jtag_ntrst_grp0", };
1403		−static const char * const jtag_ntrst_grp1[] = { "jtag_ntrst_grp1", };
1404		−static const char * const jtag_swdiotms_grp0[] = { "jtag_swdiotms_grp0", };
1405		−static const char * const jtag_swdiotms_grp1[] = { "jtag_swdiotms_grp1", };
1406		−static const char * const jtag_tck_grp0[] = { "jtag_tck_grp0", };
1407		−static const char * const jtag_tck_grp1[] = { "jtag_tck_grp1", };
1408		−static const char * const jtag_tdi_grp0[] = { "jtag_tdi_grp0", };
1409		−static const char * const jtag_tdi_grp1[] = { "jtag_tdi_grp1", };
1410		−static const char * const jtag_tdo_grp0[] = { "jtag_tdo_grp0", };
1411		−static const char * const jtag_tdo_grp1[] = { "jtag_tdo_grp1", };
1412		−static const char * const ks_kas_spi_grp0[] = { "ks_kas_spi_grp0", };
1413		−static const char * const ld_ldd_grp[] = { "ld_ldd_grp", };
1414		−static const char * const ld_ldd_16bit_grp[] = { "ld_ldd_16bit_grp", };
1415		−static const char * const ld_ldd_fck_grp[] = { "ld_ldd_fck_grp", };
1416		−static const char * const ld_ldd_lck_grp[] = { "ld_ldd_lck_grp", };
1417		−static const char * const lr_lcdrom_grp[] = { "lr_lcdrom_grp", };
1418		−static const char * const lvds_analog_grp[] = { "lvds_analog_grp", };
1419		−static const char * const nd_df_basic_grp[] = { "nd_df_basic_grp", };
1420		−static const char * const nd_df_wp_grp[] = { "nd_df_wp_grp", };
1421		−static const char * const nd_df_cs_grp[] = { "nd_df_cs_grp", };
1422		−static const char * const ps_grp[] = { "ps_grp", };
1423		−static const char * const ps_no_dir_grp[] = { "ps_no_dir_grp", };
1424		−static const char * const pwc_core_on_grp[] = { "pwc_core_on_grp", };
1425		−static const char * const pwc_ext_on_grp[] = { "pwc_ext_on_grp", };
1426		−static const char * const pwc_gpio3_clk_grp[] = { "pwc_gpio3_clk_grp", };
1427		−static const char * const pwc_io_on_grp[] = { "pwc_io_on_grp", };
1428		−static const char * const pwc_lowbatt_b_grp0[] = { "pwc_lowbatt_b_grp0", };
1429		−static const char * const pwc_mem_on_grp[] = { "pwc_mem_on_grp", };
1430		−static const char * const pwc_on_key_b_grp0[] = { "pwc_on_key_b_grp0", };
1431		−static const char * const pwc_wakeup_src0_grp[] = { "pwc_wakeup_src0_grp", };
1432		−static const char * const pwc_wakeup_src1_grp[] = { "pwc_wakeup_src1_grp", };
1433		−static const char * const pwc_wakeup_src2_grp[] = { "pwc_wakeup_src2_grp", };
1434		−static const char * const pwc_wakeup_src3_grp[] = { "pwc_wakeup_src3_grp", };
1435		−static const char * const pw_cko0_grp0[] = { "pw_cko0_grp0", };
1436		−static const char * const pw_cko0_grp1[] = { "pw_cko0_grp1", };
1437		−static const char * const pw_cko0_grp2[] = { "pw_cko0_grp2", };
1438		−static const char * const pw_cko0_grp3[] = { "pw_cko0_grp3", };
1439		−static const char * const pw_cko1_grp0[] = { "pw_cko1_grp0", };
1440		−static const char * const pw_cko1_grp1[] = { "pw_cko1_grp1", };
1441		−static const char * const pw_cko1_grp2[] = { "pw_cko1_grp2", };
1442		−static const char * const pw_i2s01_clk_grp0[] = { "pw_i2s01_clk_grp0", };
1443		−static const char * const pw_i2s01_clk_grp1[] = { "pw_i2s01_clk_grp1", };
1444		−static const char * const pw_i2s01_clk_grp2[] = { "pw_i2s01_clk_grp2", };
1445		−static const char * const pw_pwm0_grp0[] = { "pw_pwm0_grp0", };
1446		−static const char * const pw_pwm0_grp1[] = { "pw_pwm0_grp1", };
1447		−static const char * const pw_pwm1_grp0[] = { "pw_pwm1_grp0", };
1448		−static const char * const pw_pwm1_grp1[] = { "pw_pwm1_grp1", };
1449		−static const char * const pw_pwm1_grp2[] = { "pw_pwm1_grp2", };
1450		−static const char * const pw_pwm2_grp0[] = { "pw_pwm2_grp0", };
1451		−static const char * const pw_pwm2_grp1[] = { "pw_pwm2_grp1", };
1452		−static const char * const pw_pwm2_grp2[] = { "pw_pwm2_grp2", };
1453		−static const char * const pw_pwm3_grp0[] = { "pw_pwm3_grp0", };
1454		−static const char * const pw_pwm3_grp1[] = { "pw_pwm3_grp1", };
1455		−static const char * const pw_pwm_cpu_vol_grp0[] = { "pw_pwm_cpu_vol_grp0", };
1456		−static const char * const pw_pwm_cpu_vol_grp1[] = { "pw_pwm_cpu_vol_grp1", };
1457		−static const char * const pw_pwm_cpu_vol_grp2[] = { "pw_pwm_cpu_vol_grp2", };
1458		−static const char * const pw_backlight_grp0[] = { "pw_backlight_grp0", };
1459		−static const char * const pw_backlight_grp1[] = { "pw_backlight_grp1", };
1460		−static const char * const rg_eth_mac_grp[] = { "rg_eth_mac_grp", };
1461		−static const char * const rg_gmac_phy_intr_n_grp[] = {
1462		− "rg_gmac_phy_intr_n_grp", };
1463		−static const char * const rg_rgmii_mac_grp[] = { "rg_rgmii_mac_grp", };
1464		−static const char * const rg_rgmii_phy_ref_clk_grp0[] = {
1465		− "rg_rgmii_phy_ref_clk_grp0", };
1466		−static const char * const rg_rgmii_phy_ref_clk_grp1[] = {
1467		− "rg_rgmii_phy_ref_clk_grp1", };
1468		−static const char * const sd0_grp[] = { "sd0_grp", };
1469		−static const char * const sd0_4bit_grp[] = { "sd0_4bit_grp", };
1470		−static const char * const sd1_grp[] = { "sd1_grp", };
1471		−static const char * const sd1_4bit_grp0[] = { "sd1_4bit_grp0", };
1472		−static const char * const sd1_4bit_grp1[] = { "sd1_4bit_grp1", };
1473		−static const char * const sd2_basic_grp[] = { "sd2_basic_grp", };
1474		−static const char * const sd2_cdb_grp0[] = { "sd2_cdb_grp0", };
1475		−static const char * const sd2_cdb_grp1[] = { "sd2_cdb_grp1", };
1476		−static const char * const sd2_wpb_grp0[] = { "sd2_wpb_grp0", };
1477		−static const char * const sd2_wpb_grp1[] = { "sd2_wpb_grp1", };
1478		−static const char * const sd3_9_grp[] = { "sd3_9_grp", };
1479		−static const char * const sd5_grp[] = { "sd5_grp", };
1480		−static const char * const sd6_grp0[] = { "sd6_grp0", };
1481		−static const char * const sd6_grp1[] = { "sd6_grp1", };
1482		−static const char * const sp0_ext_ldo_on_grp[] = { "sp0_ext_ldo_on_grp", };
1483		−static const char * const sp0_qspi_grp[] = { "sp0_qspi_grp", };
1484		−static const char * const sp1_spi_grp[] = { "sp1_spi_grp", };
1485		−static const char * const tpiu_trace_grp[] = { "tpiu_trace_grp", };
1486		−static const char * const uart0_grp[] = { "uart0_grp", };
1487		−static const char * const uart0_nopause_grp[] = { "uart0_nopause_grp", };
1488		−static const char * const uart1_grp[] = { "uart1_grp", };
1489		−static const char * const uart2_cts_grp0[] = { "uart2_cts_grp0", };
1490		−static const char * const uart2_cts_grp1[] = { "uart2_cts_grp1", };
1491		−static const char * const uart2_rts_grp0[] = { "uart2_rts_grp0", };
1492		−static const char * const uart2_rts_grp1[] = { "uart2_rts_grp1", };
1493		−static const char * const uart2_rxd_grp0[] = { "uart2_rxd_grp0", };
1494		−static const char * const uart2_rxd_grp1[] = { "uart2_rxd_grp1", };
1495		−static const char * const uart2_rxd_grp2[] = { "uart2_rxd_grp2", };
1496		−static const char * const uart2_txd_grp0[] = { "uart2_txd_grp0", };
1497		−static const char * const uart2_txd_grp1[] = { "uart2_txd_grp1", };
1498		−static const char * const uart2_txd_grp2[] = { "uart2_txd_grp2", };
1499		−static const char * const uart3_cts_grp0[] = { "uart3_cts_grp0", };
1500		−static const char * const uart3_cts_grp1[] = { "uart3_cts_grp1", };
1501		−static const char * const uart3_cts_grp2[] = { "uart3_cts_grp2", };
1502		−static const char * const uart3_rts_grp0[] = { "uart3_rts_grp0", };
1503		−static const char * const uart3_rts_grp1[] = { "uart3_rts_grp1", };
1504		−static const char * const uart3_rts_grp2[] = { "uart3_rts_grp2", };
1505		−static const char * const uart3_rxd_grp0[] = { "uart3_rxd_grp0", };
1506		−static const char * const uart3_rxd_grp1[] = { "uart3_rxd_grp1", };
1507		−static const char * const uart3_rxd_grp2[] = { "uart3_rxd_grp2", };
1508		−static const char * const uart3_txd_grp0[] = { "uart3_txd_grp0", };
1509		−static const char * const uart3_txd_grp1[] = { "uart3_txd_grp1", };
1510		−static const char * const uart3_txd_grp2[] = { "uart3_txd_grp2", };
1511		−static const char * const uart4_basic_grp[] = { "uart4_basic_grp", };
1512		−static const char * const uart4_cts_grp0[] = { "uart4_cts_grp0", };
1513		−static const char * const uart4_cts_grp1[] = { "uart4_cts_grp1", };
1514		−static const char * const uart4_cts_grp2[] = { "uart4_cts_grp2", };
1515		−static const char * const uart4_rts_grp0[] = { "uart4_rts_grp0", };
1516		−static const char * const uart4_rts_grp1[] = { "uart4_rts_grp1", };
1517		−static const char * const uart4_rts_grp2[] = { "uart4_rts_grp2", };
1518		−static const char * const usb0_drvvbus_grp0[] = { "usb0_drvvbus_grp0", };
1519		−static const char * const usb0_drvvbus_grp1[] = { "usb0_drvvbus_grp1", };
1520		−static const char * const usb1_drvvbus_grp0[] = { "usb1_drvvbus_grp0", };
1521		−static const char * const usb1_drvvbus_grp1[] = { "usb1_drvvbus_grp1", };
1522		−static const char * const visbus_dout_grp[] = { "visbus_dout_grp", };
1523		−static const char * const vi_vip1_grp[] = { "vi_vip1_grp", };
1524		−static const char * const vi_vip1_ext_grp[] = { "vi_vip1_ext_grp", };
1525		−static const char * const vi_vip1_low8bit_grp[] = { "vi_vip1_low8bit_grp", };
1526		−static const char * const vi_vip1_high8bit_grp[] = { "vi_vip1_high8bit_grp", };
1527		−
1528		−static struct atlas7_pad_mux gnss_gpio_grp_pad_mux[] = {
1529		− MUX(1, 119, 0, N, N, N, N),
1530		− MUX(1, 120, 0, N, N, N, N),
1531		− MUX(1, 121, 0, N, N, N, N),
1532		− MUX(1, 122, 0, N, N, N, N),
1533		− MUX(1, 123, 0, N, N, N, N),
1534		− MUX(1, 124, 0, N, N, N, N),
1535		− MUX(1, 125, 0, N, N, N, N),
1536		− MUX(1, 126, 0, N, N, N, N),
1537		− MUX(1, 127, 0, N, N, N, N),
1538		− MUX(1, 128, 0, N, N, N, N),
1539		− MUX(1, 22, 0, N, N, N, N),
1540		− MUX(1, 23, 0, N, N, N, N),
1541		− MUX(1, 24, 0, N, N, N, N),
1542		− MUX(1, 25, 0, N, N, N, N),
1543		− MUX(1, 26, 0, N, N, N, N),
1544		− MUX(1, 27, 0, N, N, N, N),
1545		− MUX(1, 28, 0, N, N, N, N),
1546		− MUX(1, 29, 0, N, N, N, N),
1547		− MUX(1, 30, 0, N, N, N, N),
1548		−};
1549		−
1550		−static struct atlas7_grp_mux gnss_gpio_grp_mux = {
1551		− .pad_mux_count = ARRAY_SIZE(gnss_gpio_grp_pad_mux),
1552		− .pad_mux_list = gnss_gpio_grp_pad_mux,
1553		−};
1554		−
1555		−static struct atlas7_pad_mux lcd_vip_gpio_grp_pad_mux[] = {
1556		− MUX(1, 74, 0, N, N, N, N),
1557		− MUX(1, 75, 0, N, N, N, N),
1558		− MUX(1, 76, 0, N, N, N, N),
1559		− MUX(1, 77, 0, N, N, N, N),
1560		− MUX(1, 78, 0, N, N, N, N),
1561		− MUX(1, 79, 0, N, N, N, N),
1562		− MUX(1, 80, 0, N, N, N, N),
1563		− MUX(1, 81, 0, N, N, N, N),
1564		− MUX(1, 82, 0, N, N, N, N),
1565		− MUX(1, 83, 0, N, N, N, N),
1566		− MUX(1, 84, 0, N, N, N, N),
1567		− MUX(1, 53, 0, N, N, N, N),
1568		− MUX(1, 54, 0, N, N, N, N),
1569		− MUX(1, 55, 0, N, N, N, N),
1570		− MUX(1, 56, 0, N, N, N, N),
1571		− MUX(1, 57, 0, N, N, N, N),
1572		− MUX(1, 58, 0, N, N, N, N),
1573		− MUX(1, 59, 0, N, N, N, N),
1574		− MUX(1, 60, 0, N, N, N, N),
1575		− MUX(1, 61, 0, N, N, N, N),
1576		− MUX(1, 62, 0, N, N, N, N),
1577		− MUX(1, 63, 0, N, N, N, N),
1578		− MUX(1, 64, 0, N, N, N, N),
1579		− MUX(1, 65, 0, N, N, N, N),
1580		− MUX(1, 66, 0, N, N, N, N),
1581		− MUX(1, 67, 0, N, N, N, N),
1582		− MUX(1, 68, 0, N, N, N, N),
1583		− MUX(1, 69, 0, N, N, N, N),
1584		− MUX(1, 70, 0, N, N, N, N),
1585		− MUX(1, 71, 0, N, N, N, N),
1586		− MUX(1, 72, 0, N, N, N, N),
1587		− MUX(1, 73, 0, N, N, N, N),
1588		−};
1589		−
1590		−static struct atlas7_grp_mux lcd_vip_gpio_grp_mux = {
1591		− .pad_mux_count = ARRAY_SIZE(lcd_vip_gpio_grp_pad_mux),
1592		− .pad_mux_list = lcd_vip_gpio_grp_pad_mux,
1593		−};
1594		−
1595		−static struct atlas7_pad_mux sdio_i2s_gpio_grp_pad_mux[] = {
1596		− MUX(1, 31, 0, N, N, N, N),
1597		− MUX(1, 32, 0, N, N, N, N),
1598		− MUX(1, 33, 0, N, N, N, N),
1599		− MUX(1, 34, 0, N, N, N, N),
1600		− MUX(1, 35, 0, N, N, N, N),
1601		− MUX(1, 36, 0, N, N, N, N),
1602		− MUX(1, 85, 0, N, N, N, N),
1603		− MUX(1, 86, 0, N, N, N, N),
1604		− MUX(1, 87, 0, N, N, N, N),
1605		− MUX(1, 88, 0, N, N, N, N),
1606		− MUX(1, 89, 0, N, N, N, N),
1607		− MUX(1, 90, 0, N, N, N, N),
1608		− MUX(1, 129, 0, N, N, N, N),
1609		− MUX(1, 130, 0, N, N, N, N),
1610		− MUX(1, 131, 0, N, N, N, N),
1611		− MUX(1, 132, 0, N, N, N, N),
1612		− MUX(1, 91, 0, N, N, N, N),
1613		− MUX(1, 92, 0, N, N, N, N),
1614		− MUX(1, 93, 0, N, N, N, N),
1615		− MUX(1, 94, 0, N, N, N, N),
1616		− MUX(1, 95, 0, N, N, N, N),
1617		− MUX(1, 96, 0, N, N, N, N),
1618		− MUX(1, 112, 0, N, N, N, N),
1619		− MUX(1, 113, 0, N, N, N, N),
1620		− MUX(1, 114, 0, N, N, N, N),
1621		− MUX(1, 115, 0, N, N, N, N),
1622		− MUX(1, 116, 0, N, N, N, N),
1623		− MUX(1, 117, 0, N, N, N, N),
1624		− MUX(1, 118, 0, N, N, N, N),
1625		−};
1626		−
1627		−static struct atlas7_grp_mux sdio_i2s_gpio_grp_mux = {
1628		− .pad_mux_count = ARRAY_SIZE(sdio_i2s_gpio_grp_pad_mux),
1629		− .pad_mux_list = sdio_i2s_gpio_grp_pad_mux,
1630		−};
1631		−
1632		−static struct atlas7_pad_mux sp_rgmii_gpio_grp_pad_mux[] = {
1633		− MUX(1, 97, 0, N, N, N, N),
1634		− MUX(1, 98, 0, N, N, N, N),
1635		− MUX(1, 99, 0, N, N, N, N),
1636		− MUX(1, 100, 0, N, N, N, N),
1637		− MUX(1, 101, 0, N, N, N, N),
1638		− MUX(1, 102, 0, N, N, N, N),
1639		− MUX(1, 103, 0, N, N, N, N),
1640		− MUX(1, 104, 0, N, N, N, N),
1641		− MUX(1, 105, 0, N, N, N, N),
1642		− MUX(1, 106, 0, N, N, N, N),
1643		− MUX(1, 107, 0, N, N, N, N),
1644		− MUX(1, 108, 0, N, N, N, N),
1645		− MUX(1, 109, 0, N, N, N, N),
1646		− MUX(1, 110, 0, N, N, N, N),
1647		− MUX(1, 111, 0, N, N, N, N),
1648		− MUX(1, 18, 0, N, N, N, N),
1649		− MUX(1, 19, 0, N, N, N, N),
1650		− MUX(1, 20, 0, N, N, N, N),
1651		− MUX(1, 21, 0, N, N, N, N),
1652		− MUX(1, 141, 0, N, N, N, N),
1653		− MUX(1, 142, 0, N, N, N, N),
1654		− MUX(1, 143, 0, N, N, N, N),
1655		− MUX(1, 144, 0, N, N, N, N),
1656		− MUX(1, 145, 0, N, N, N, N),
1657		− MUX(1, 146, 0, N, N, N, N),
1658		− MUX(1, 147, 0, N, N, N, N),
1659		− MUX(1, 148, 0, N, N, N, N),
1660		−};
1661		−
1662		−static struct atlas7_grp_mux sp_rgmii_gpio_grp_mux = {
1663		− .pad_mux_count = ARRAY_SIZE(sp_rgmii_gpio_grp_pad_mux),
1664		− .pad_mux_list = sp_rgmii_gpio_grp_pad_mux,
1665		−};
1666		−
1667		−static struct atlas7_pad_mux lvds_gpio_grp_pad_mux[] = {
1668		− MUX(1, 157, 0, N, N, N, N),
1669		− MUX(1, 158, 0, N, N, N, N),
1670		− MUX(1, 155, 0, N, N, N, N),
1671		− MUX(1, 156, 0, N, N, N, N),
1672		− MUX(1, 153, 0, N, N, N, N),
1673		− MUX(1, 154, 0, N, N, N, N),
1674		− MUX(1, 151, 0, N, N, N, N),
1675		− MUX(1, 152, 0, N, N, N, N),
1676		− MUX(1, 149, 0, N, N, N, N),
1677		− MUX(1, 150, 0, N, N, N, N),
1678		−};
1679		−
1680		−static struct atlas7_grp_mux lvds_gpio_grp_mux = {
1681		− .pad_mux_count = ARRAY_SIZE(lvds_gpio_grp_pad_mux),
1682		− .pad_mux_list = lvds_gpio_grp_pad_mux,
1683		−};
1684		−
1685		−static struct atlas7_pad_mux jtag_uart_nand_gpio_grp_pad_mux[] = {
1686		− MUX(1, 44, 0, N, N, N, N),
1687		− MUX(1, 43, 0, N, N, N, N),
1688		− MUX(1, 42, 0, N, N, N, N),
1689		− MUX(1, 41, 0, N, N, N, N),
1690		− MUX(1, 40, 0, N, N, N, N),
1691		− MUX(1, 39, 0, N, N, N, N),
1692		− MUX(1, 38, 0, N, N, N, N),
1693		− MUX(1, 37, 0, N, N, N, N),
1694		− MUX(1, 46, 0, N, N, N, N),
1695		− MUX(1, 47, 0, N, N, N, N),
1696		− MUX(1, 48, 0, N, N, N, N),
1697		− MUX(1, 49, 0, N, N, N, N),
1698		− MUX(1, 50, 0, N, N, N, N),
1699		− MUX(1, 52, 0, N, N, N, N),
1700		− MUX(1, 51, 0, N, N, N, N),
1701		− MUX(1, 45, 0, N, N, N, N),
1702		− MUX(1, 133, 0, N, N, N, N),
1703		− MUX(1, 134, 0, N, N, N, N),
1704		− MUX(1, 135, 0, N, N, N, N),
1705		− MUX(1, 136, 0, N, N, N, N),
1706		− MUX(1, 137, 0, N, N, N, N),
1707		− MUX(1, 138, 0, N, N, N, N),
1708		− MUX(1, 139, 0, N, N, N, N),
1709		− MUX(1, 140, 0, N, N, N, N),
1710		− MUX(1, 159, 0, N, N, N, N),
1711		− MUX(1, 160, 0, N, N, N, N),
1712		− MUX(1, 161, 0, N, N, N, N),
1713		− MUX(1, 162, 0, N, N, N, N),
1714		− MUX(1, 163, 0, N, N, N, N),
1715		−};
1716		−
1717		−static struct atlas7_grp_mux jtag_uart_nand_gpio_grp_mux = {
1718		− .pad_mux_count = ARRAY_SIZE(jtag_uart_nand_gpio_grp_pad_mux),
1719		− .pad_mux_list = jtag_uart_nand_gpio_grp_pad_mux,
1720		−};
1721		−
1722		−static struct atlas7_pad_mux rtc_gpio_grp_pad_mux[] = {
1723		− MUX(0, 0, 0, N, N, N, N),
1724		− MUX(0, 1, 0, N, N, N, N),
1725		− MUX(0, 2, 0, N, N, N, N),
1726		− MUX(0, 3, 0, N, N, N, N),
1727		− MUX(0, 4, 0, N, N, N, N),
1728		− MUX(0, 10, 0, N, N, N, N),
1729		− MUX(0, 11, 0, N, N, N, N),
1730		− MUX(0, 12, 0, N, N, N, N),
1731		− MUX(0, 13, 0, N, N, N, N),
1732		− MUX(0, 14, 0, N, N, N, N),
1733		− MUX(0, 15, 0, N, N, N, N),
1734		− MUX(0, 16, 0, N, N, N, N),
1735		− MUX(0, 17, 0, N, N, N, N),
1736		− MUX(0, 9, 0, N, N, N, N),
1737		−};
1738		−
1739		−static struct atlas7_grp_mux rtc_gpio_grp_mux = {
1740		− .pad_mux_count = ARRAY_SIZE(rtc_gpio_grp_pad_mux),
1741		− .pad_mux_list = rtc_gpio_grp_pad_mux,
1742		−};
1743		−
1744		−static struct atlas7_pad_mux audio_ac97_grp_pad_mux[] = {
1745		− MUX(1, 113, 2, N, N, N, N),
1746		− MUX(1, 118, 2, N, N, N, N),
1747		− MUX(1, 115, 2, N, N, N, N),
1748		− MUX(1, 114, 2, N, N, N, N),
1749		−};
1750		−
1751		−static struct atlas7_grp_mux audio_ac97_grp_mux = {
1752		− .pad_mux_count = ARRAY_SIZE(audio_ac97_grp_pad_mux),
1753		− .pad_mux_list = audio_ac97_grp_pad_mux,
1754		−};
1755		−
1756		−static struct atlas7_pad_mux audio_digmic_grp0_pad_mux[] = {
1757		− MUX(1, 51, 3, 0xa10, 20, 0xa90, 20),
1758		−};
1759		−
1760		−static struct atlas7_grp_mux audio_digmic_grp0_mux = {
1761		− .pad_mux_count = ARRAY_SIZE(audio_digmic_grp0_pad_mux),
1762		− .pad_mux_list = audio_digmic_grp0_pad_mux,
1763		−};
1764		−
1765		−static struct atlas7_pad_mux audio_digmic_grp1_pad_mux[] = {
1766		− MUX(1, 122, 5, 0xa10, 20, 0xa90, 20),
1767		−};
1768		−
1769		−static struct atlas7_grp_mux audio_digmic_grp1_mux = {
1770		− .pad_mux_count = ARRAY_SIZE(audio_digmic_grp1_pad_mux),
1771		− .pad_mux_list = audio_digmic_grp1_pad_mux,
1772		−};
1773		−
1774		−static struct atlas7_pad_mux audio_digmic_grp2_pad_mux[] = {
1775		− MUX(1, 161, 7, 0xa10, 20, 0xa90, 20),
1776		−};
1777		−
1778		−static struct atlas7_grp_mux audio_digmic_grp2_mux = {
1779		− .pad_mux_count = ARRAY_SIZE(audio_digmic_grp2_pad_mux),
1780		− .pad_mux_list = audio_digmic_grp2_pad_mux,
1781		−};
1782		−
1783		−static struct atlas7_pad_mux audio_func_dbg_grp_pad_mux[] = {
1784		− MUX(1, 141, 4, N, N, N, N),
1785		− MUX(1, 144, 4, N, N, N, N),
1786		− MUX(1, 44, 6, N, N, N, N),
1787		− MUX(1, 43, 6, N, N, N, N),
1788		− MUX(1, 42, 6, N, N, N, N),
1789		− MUX(1, 41, 6, N, N, N, N),
1790		− MUX(1, 40, 6, N, N, N, N),
1791		− MUX(1, 39, 6, N, N, N, N),
1792		− MUX(1, 38, 6, N, N, N, N),
1793		− MUX(1, 37, 6, N, N, N, N),
1794		− MUX(1, 74, 6, N, N, N, N),
1795		− MUX(1, 75, 6, N, N, N, N),
1796		− MUX(1, 76, 6, N, N, N, N),
1797		− MUX(1, 77, 6, N, N, N, N),
1798		− MUX(1, 78, 6, N, N, N, N),
1799		− MUX(1, 79, 6, N, N, N, N),
1800		− MUX(1, 81, 6, N, N, N, N),
1801		− MUX(1, 113, 6, N, N, N, N),
1802		− MUX(1, 114, 6, N, N, N, N),
1803		− MUX(1, 118, 6, N, N, N, N),
1804		− MUX(1, 115, 6, N, N, N, N),
1805		− MUX(1, 49, 6, N, N, N, N),
1806		− MUX(1, 50, 6, N, N, N, N),
1807		− MUX(1, 142, 4, N, N, N, N),
1808		− MUX(1, 143, 4, N, N, N, N),
1809		− MUX(1, 80, 6, N, N, N, N),
1810		−};
1811		−
1812		−static struct atlas7_grp_mux audio_func_dbg_grp_mux = {
1813		− .pad_mux_count = ARRAY_SIZE(audio_func_dbg_grp_pad_mux),
1814		− .pad_mux_list = audio_func_dbg_grp_pad_mux,
1815		−};
1816		−
1817		−static struct atlas7_pad_mux audio_i2s_grp_pad_mux[] = {
1818		− MUX(1, 118, 1, N, N, N, N),
1819		− MUX(1, 115, 1, N, N, N, N),
1820		− MUX(1, 116, 1, N, N, N, N),
1821		− MUX(1, 117, 1, N, N, N, N),
1822		− MUX(1, 112, 1, N, N, N, N),
1823		− MUX(1, 113, 1, N, N, N, N),
1824		− MUX(1, 114, 1, N, N, N, N),
1825		−};
1826		−
1827		−static struct atlas7_grp_mux audio_i2s_grp_mux = {
1828		− .pad_mux_count = ARRAY_SIZE(audio_i2s_grp_pad_mux),
1829		− .pad_mux_list = audio_i2s_grp_pad_mux,
1830		−};
1831		−
1832		−static struct atlas7_pad_mux audio_i2s_2ch_grp_pad_mux[] = {
1833		− MUX(1, 118, 1, N, N, N, N),
1834		− MUX(1, 115, 1, N, N, N, N),
1835		− MUX(1, 112, 1, N, N, N, N),
1836		− MUX(1, 113, 1, N, N, N, N),
1837		− MUX(1, 114, 1, N, N, N, N),
1838		−};
1839		−
1840		−static struct atlas7_grp_mux audio_i2s_2ch_grp_mux = {
1841		− .pad_mux_count = ARRAY_SIZE(audio_i2s_2ch_grp_pad_mux),
1842		− .pad_mux_list = audio_i2s_2ch_grp_pad_mux,
1843		−};
1844		−
1845		−static struct atlas7_pad_mux audio_i2s_extclk_grp_pad_mux[] = {
1846		− MUX(1, 112, 2, N, N, N, N),
1847		−};
1848		−
1849		−static struct atlas7_grp_mux audio_i2s_extclk_grp_mux = {
1850		− .pad_mux_count = ARRAY_SIZE(audio_i2s_extclk_grp_pad_mux),
1851		− .pad_mux_list = audio_i2s_extclk_grp_pad_mux,
1852		−};
1853		−
1854		−static struct atlas7_pad_mux audio_spdif_out_grp0_pad_mux[] = {
1855		− MUX(1, 112, 3, N, N, N, N),
1856		−};
1857		−
1858		−static struct atlas7_grp_mux audio_spdif_out_grp0_mux = {
1859		− .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp0_pad_mux),
1860		− .pad_mux_list = audio_spdif_out_grp0_pad_mux,
1861		−};
1862		−
1863		−static struct atlas7_pad_mux audio_spdif_out_grp1_pad_mux[] = {
1864		− MUX(1, 116, 3, N, N, N, N),
1865		−};
1866		−
1867		−static struct atlas7_grp_mux audio_spdif_out_grp1_mux = {
1868		− .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp1_pad_mux),
1869		− .pad_mux_list = audio_spdif_out_grp1_pad_mux,
1870		−};
1871		−
1872		−static struct atlas7_pad_mux audio_spdif_out_grp2_pad_mux[] = {
1873		− MUX(1, 142, 3, N, N, N, N),
1874		−};
1875		−
1876		−static struct atlas7_grp_mux audio_spdif_out_grp2_mux = {
1877		− .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp2_pad_mux),
1878		− .pad_mux_list = audio_spdif_out_grp2_pad_mux,
1879		−};
1880		−
1881		−static struct atlas7_pad_mux audio_uart0_basic_grp_pad_mux[] = {
1882		− MUX(1, 143, 1, N, N, N, N),
1883		− MUX(1, 142, 1, N, N, N, N),
1884		− MUX(1, 141, 1, N, N, N, N),
1885		− MUX(1, 144, 1, N, N, N, N),
1886		−};
1887		−
1888		−static struct atlas7_grp_mux audio_uart0_basic_grp_mux = {
1889		− .pad_mux_count = ARRAY_SIZE(audio_uart0_basic_grp_pad_mux),
1890		− .pad_mux_list = audio_uart0_basic_grp_pad_mux,
1891		−};
1892		−
1893		−static struct atlas7_pad_mux audio_uart0_urfs_grp0_pad_mux[] = {
1894		− MUX(1, 117, 5, 0xa10, 28, 0xa90, 28),
1895		−};
1896		−
1897		−static struct atlas7_grp_mux audio_uart0_urfs_grp0_mux = {
1898		− .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp0_pad_mux),
1899		− .pad_mux_list = audio_uart0_urfs_grp0_pad_mux,
1900		−};
1901		−
1902		−static struct atlas7_pad_mux audio_uart0_urfs_grp1_pad_mux[] = {
1903		− MUX(1, 139, 3, 0xa10, 28, 0xa90, 28),
1904		−};
1905		−
1906		−static struct atlas7_grp_mux audio_uart0_urfs_grp1_mux = {
1907		− .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp1_pad_mux),
1908		− .pad_mux_list = audio_uart0_urfs_grp1_pad_mux,
1909		−};
1910		−
1911		−static struct atlas7_pad_mux audio_uart0_urfs_grp2_pad_mux[] = {
1912		− MUX(1, 163, 3, 0xa10, 28, 0xa90, 28),
1913		−};
1914		−
1915		−static struct atlas7_grp_mux audio_uart0_urfs_grp2_mux = {
1916		− .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp2_pad_mux),
1917		− .pad_mux_list = audio_uart0_urfs_grp2_pad_mux,
1918		−};
1919		−
1920		−static struct atlas7_pad_mux audio_uart0_urfs_grp3_pad_mux[] = {
1921		− MUX(1, 162, 6, 0xa10, 28, 0xa90, 28),
1922		−};
1923		−
1924		−static struct atlas7_grp_mux audio_uart0_urfs_grp3_mux = {
1925		− .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp3_pad_mux),
1926		− .pad_mux_list = audio_uart0_urfs_grp3_pad_mux,
1927		−};
1928		−
1929		−static struct atlas7_pad_mux audio_uart1_basic_grp_pad_mux[] = {
1930		− MUX(1, 147, 1, 0xa10, 24, 0xa90, 24),
1931		− MUX(1, 146, 1, 0xa10, 25, 0xa90, 25),
1932		− MUX(1, 145, 1, 0xa10, 23, 0xa90, 23),
1933		− MUX(1, 148, 1, 0xa10, 22, 0xa90, 22),
1934		−};
1935		−
1936		−static struct atlas7_grp_mux audio_uart1_basic_grp_mux = {
1937		− .pad_mux_count = ARRAY_SIZE(audio_uart1_basic_grp_pad_mux),
1938		− .pad_mux_list = audio_uart1_basic_grp_pad_mux,
1939		−};
1940		−
1941		−static struct atlas7_pad_mux audio_uart1_urfs_grp0_pad_mux[] = {
1942		− MUX(1, 117, 6, 0xa10, 29, 0xa90, 29),
1943		−};
1944		−
1945		−static struct atlas7_grp_mux audio_uart1_urfs_grp0_mux = {
1946		− .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp0_pad_mux),
1947		− .pad_mux_list = audio_uart1_urfs_grp0_pad_mux,
1948		−};
1949		−
1950		−static struct atlas7_pad_mux audio_uart1_urfs_grp1_pad_mux[] = {
1951		− MUX(1, 140, 3, 0xa10, 29, 0xa90, 29),
1952		−};
1953		−
1954		−static struct atlas7_grp_mux audio_uart1_urfs_grp1_mux = {
1955		− .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp1_pad_mux),
1956		− .pad_mux_list = audio_uart1_urfs_grp1_pad_mux,
1957		−};
1958		−
1959		−static struct atlas7_pad_mux audio_uart1_urfs_grp2_pad_mux[] = {
1960		− MUX(1, 163, 4, 0xa10, 29, 0xa90, 29),
1961		−};
1962		−
1963		−static struct atlas7_grp_mux audio_uart1_urfs_grp2_mux = {
1964		− .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp2_pad_mux),
1965		− .pad_mux_list = audio_uart1_urfs_grp2_pad_mux,
1966		−};
1967		−
1968		−static struct atlas7_pad_mux audio_uart2_urfs_grp0_pad_mux[] = {
1969		− MUX(1, 139, 4, 0xa10, 30, 0xa90, 30),
1970		−};
1971		−
1972		−static struct atlas7_grp_mux audio_uart2_urfs_grp0_mux = {
1973		− .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp0_pad_mux),
1974		− .pad_mux_list = audio_uart2_urfs_grp0_pad_mux,
1975		−};
1976		−
1977		−static struct atlas7_pad_mux audio_uart2_urfs_grp1_pad_mux[] = {
1978		− MUX(1, 163, 6, 0xa10, 30, 0xa90, 30),
1979		−};
1980		−
1981		−static struct atlas7_grp_mux audio_uart2_urfs_grp1_mux = {
1982		− .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp1_pad_mux),
1983		− .pad_mux_list = audio_uart2_urfs_grp1_pad_mux,
1984		−};
1985		−
1986		−static struct atlas7_pad_mux audio_uart2_urfs_grp2_pad_mux[] = {
1987		− MUX(1, 96, 3, 0xa10, 30, 0xa90, 30),
1988		−};
1989		−
1990		−static struct atlas7_grp_mux audio_uart2_urfs_grp2_mux = {
1991		− .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp2_pad_mux),
1992		− .pad_mux_list = audio_uart2_urfs_grp2_pad_mux,
1993		−};
1994		−
1995		−static struct atlas7_pad_mux audio_uart2_urxd_grp0_pad_mux[] = {
1996		− MUX(1, 20, 2, 0xa00, 24, 0xa80, 24),
1997		−};
1998		−
1999		−static struct atlas7_grp_mux audio_uart2_urxd_grp0_mux = {
2000		− .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp0_pad_mux),
2001		− .pad_mux_list = audio_uart2_urxd_grp0_pad_mux,
2002		−};
2003		−
2004		−static struct atlas7_pad_mux audio_uart2_urxd_grp1_pad_mux[] = {
2005		− MUX(1, 109, 2, 0xa00, 24, 0xa80, 24),
2006		−};
2007		−
2008		−static struct atlas7_grp_mux audio_uart2_urxd_grp1_mux = {
2009		− .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp1_pad_mux),
2010		− .pad_mux_list = audio_uart2_urxd_grp1_pad_mux,
2011		−};
2012		−
2013		−static struct atlas7_pad_mux audio_uart2_urxd_grp2_pad_mux[] = {
2014		− MUX(1, 93, 3, 0xa00, 24, 0xa80, 24),
2015		−};
2016		−
2017		−static struct atlas7_grp_mux audio_uart2_urxd_grp2_mux = {
2018		− .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp2_pad_mux),
2019		− .pad_mux_list = audio_uart2_urxd_grp2_pad_mux,
2020		−};
2021		−
2022		−static struct atlas7_pad_mux audio_uart2_usclk_grp0_pad_mux[] = {
2023		− MUX(1, 19, 2, 0xa00, 23, 0xa80, 23),
2024		−};
2025		−
2026		−static struct atlas7_grp_mux audio_uart2_usclk_grp0_mux = {
2027		− .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp0_pad_mux),
2028		− .pad_mux_list = audio_uart2_usclk_grp0_pad_mux,
2029		−};
2030		−
2031		−static struct atlas7_pad_mux audio_uart2_usclk_grp1_pad_mux[] = {
2032		− MUX(1, 101, 2, 0xa00, 23, 0xa80, 23),
2033		−};
2034		−
2035		−static struct atlas7_grp_mux audio_uart2_usclk_grp1_mux = {
2036		− .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp1_pad_mux),
2037		− .pad_mux_list = audio_uart2_usclk_grp1_pad_mux,
2038		−};
2039		−
2040		−static struct atlas7_pad_mux audio_uart2_usclk_grp2_pad_mux[] = {
2041		− MUX(1, 91, 3, 0xa00, 23, 0xa80, 23),
2042		−};
2043		−
2044		−static struct atlas7_grp_mux audio_uart2_usclk_grp2_mux = {
2045		− .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp2_pad_mux),
2046		− .pad_mux_list = audio_uart2_usclk_grp2_pad_mux,
2047		−};
2048		−
2049		−static struct atlas7_pad_mux audio_uart2_utfs_grp0_pad_mux[] = {
2050		− MUX(1, 18, 2, 0xa00, 22, 0xa80, 22),
2051		−};
2052		−
2053		−static struct atlas7_grp_mux audio_uart2_utfs_grp0_mux = {
2054		− .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp0_pad_mux),
2055		− .pad_mux_list = audio_uart2_utfs_grp0_pad_mux,
2056		−};
2057		−
2058		−static struct atlas7_pad_mux audio_uart2_utfs_grp1_pad_mux[] = {
2059		− MUX(1, 111, 2, 0xa00, 22, 0xa80, 22),
2060		−};
2061		−
2062		−static struct atlas7_grp_mux audio_uart2_utfs_grp1_mux = {
2063		− .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp1_pad_mux),
2064		− .pad_mux_list = audio_uart2_utfs_grp1_pad_mux,
2065		−};
2066		−
2067		−static struct atlas7_pad_mux audio_uart2_utfs_grp2_pad_mux[] = {
2068		− MUX(1, 94, 3, 0xa00, 22, 0xa80, 22),
2069		−};
2070		−
2071		−static struct atlas7_grp_mux audio_uart2_utfs_grp2_mux = {
2072		− .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp2_pad_mux),
2073		− .pad_mux_list = audio_uart2_utfs_grp2_pad_mux,
2074		−};
2075		−
2076		−static struct atlas7_pad_mux audio_uart2_utxd_grp0_pad_mux[] = {
2077		− MUX(1, 21, 2, 0xa00, 25, 0xa80, 25),
2078		−};
2079		−
2080		−static struct atlas7_grp_mux audio_uart2_utxd_grp0_mux = {
2081		− .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp0_pad_mux),
2082		− .pad_mux_list = audio_uart2_utxd_grp0_pad_mux,
2083		−};
2084		−
2085		−static struct atlas7_pad_mux audio_uart2_utxd_grp1_pad_mux[] = {
2086		− MUX(1, 110, 2, 0xa00, 25, 0xa80, 25),
2087		−};
2088		−
2089		−static struct atlas7_grp_mux audio_uart2_utxd_grp1_mux = {
2090		− .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp1_pad_mux),
2091		− .pad_mux_list = audio_uart2_utxd_grp1_pad_mux,
2092		−};
2093		−
2094		−static struct atlas7_pad_mux audio_uart2_utxd_grp2_pad_mux[] = {
2095		− MUX(1, 92, 3, 0xa00, 25, 0xa80, 25),
2096		−};
2097		−
2098		−static struct atlas7_grp_mux audio_uart2_utxd_grp2_mux = {
2099		− .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp2_pad_mux),
2100		− .pad_mux_list = audio_uart2_utxd_grp2_pad_mux,
2101		−};
2102		−
2103		−static struct atlas7_pad_mux c_can_trnsvr_en_grp0_pad_mux[] = {
2104		− MUX(0, 2, 6, N, N, N, N),
2105		−};
2106		−
2107		−static struct atlas7_grp_mux c_can_trnsvr_en_grp0_mux = {
2108		− .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp0_pad_mux),
2109		− .pad_mux_list = c_can_trnsvr_en_grp0_pad_mux,
2110		−};
2111		−
2112		−static struct atlas7_pad_mux c_can_trnsvr_en_grp1_pad_mux[] = {
2113		− MUX(0, 0, 2, N, N, N, N),
2114		−};
2115		−
2116		−static struct atlas7_grp_mux c_can_trnsvr_en_grp1_mux = {
2117		− .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp1_pad_mux),
2118		− .pad_mux_list = c_can_trnsvr_en_grp1_pad_mux,
2119		−};
2120		−
2121		−static struct atlas7_pad_mux c_can_trnsvr_intr_grp_pad_mux[] = {
2122		− MUX(0, 1, 2, N, N, N, N),
2123		−};
2124		−
2125		−static struct atlas7_grp_mux c_can_trnsvr_intr_grp_mux = {
2126		− .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_intr_grp_pad_mux),
2127		− .pad_mux_list = c_can_trnsvr_intr_grp_pad_mux,
2128		−};
2129		−
2130		−static struct atlas7_pad_mux c_can_trnsvr_stb_n_grp_pad_mux[] = {
2131		− MUX(0, 3, 6, N, N, N, N),
2132		−};
2133		−
2134		−static struct atlas7_grp_mux c_can_trnsvr_stb_n_grp_mux = {
2135		− .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_stb_n_grp_pad_mux),
2136		− .pad_mux_list = c_can_trnsvr_stb_n_grp_pad_mux,
2137		−};
2138		−
2139		−static struct atlas7_pad_mux c0_can_rxd_trnsv0_grp_pad_mux[] = {
2140		− MUX(0, 11, 1, 0xa08, 9, 0xa88, 9),
2141		−};
2142		−
2143		−static struct atlas7_grp_mux c0_can_rxd_trnsv0_grp_mux = {
2144		− .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv0_grp_pad_mux),
2145		− .pad_mux_list = c0_can_rxd_trnsv0_grp_pad_mux,
2146		−};
2147		−
2148		−static struct atlas7_pad_mux c0_can_rxd_trnsv1_grp_pad_mux[] = {
2149		− MUX(0, 2, 5, 0xa10, 9, 0xa90, 9),
2150		−};
2151		−
2152		−static struct atlas7_grp_mux c0_can_rxd_trnsv1_grp_mux = {
2153		− .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv1_grp_pad_mux),
2154		− .pad_mux_list = c0_can_rxd_trnsv1_grp_pad_mux,
2155		−};
2156		−
2157		−static struct atlas7_pad_mux c0_can_txd_trnsv0_grp_pad_mux[] = {
2158		− MUX(0, 10, 1, N, N, N, N),
2159		−};
2160		−
2161		−static struct atlas7_grp_mux c0_can_txd_trnsv0_grp_mux = {
2162		− .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv0_grp_pad_mux),
2163		− .pad_mux_list = c0_can_txd_trnsv0_grp_pad_mux,
2164		−};
2165		−
2166		−static struct atlas7_pad_mux c0_can_txd_trnsv1_grp_pad_mux[] = {
2167		− MUX(0, 3, 5, N, N, N, N),
2168		−};
2169		−
2170		−static struct atlas7_grp_mux c0_can_txd_trnsv1_grp_mux = {
2171		− .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv1_grp_pad_mux),
2172		− .pad_mux_list = c0_can_txd_trnsv1_grp_pad_mux,
2173		−};
2174		−
2175		−static struct atlas7_pad_mux c1_can_rxd_grp0_pad_mux[] = {
2176		− MUX(1, 138, 2, 0xa00, 4, 0xa80, 4),
2177		−};
2178		−
2179		−static struct atlas7_grp_mux c1_can_rxd_grp0_mux = {
2180		− .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp0_pad_mux),
2181		− .pad_mux_list = c1_can_rxd_grp0_pad_mux,
2182		−};
2183		−
2184		−static struct atlas7_pad_mux c1_can_rxd_grp1_pad_mux[] = {
2185		− MUX(1, 147, 2, 0xa00, 4, 0xa80, 4),
2186		−};
2187		−
2188		−static struct atlas7_grp_mux c1_can_rxd_grp1_mux = {
2189		− .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp1_pad_mux),
2190		− .pad_mux_list = c1_can_rxd_grp1_pad_mux,
2191		−};
2192		−
2193		−static struct atlas7_pad_mux c1_can_rxd_grp2_pad_mux[] = {
2194		− MUX(0, 2, 2, 0xa00, 4, 0xa80, 4),
2195		−};
2196		−
2197		−static struct atlas7_grp_mux c1_can_rxd_grp2_mux = {
2198		− .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp2_pad_mux),
2199		− .pad_mux_list = c1_can_rxd_grp2_pad_mux,
2200		−};
2201		−
2202		−static struct atlas7_pad_mux c1_can_rxd_grp3_pad_mux[] = {
2203		− MUX(1, 162, 4, 0xa00, 4, 0xa80, 4),
2204		−};
2205		−
2206		−static struct atlas7_grp_mux c1_can_rxd_grp3_mux = {
2207		− .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp3_pad_mux),
2208		− .pad_mux_list = c1_can_rxd_grp3_pad_mux,
2209		−};
2210		−
2211		−static struct atlas7_pad_mux c1_can_txd_grp0_pad_mux[] = {
2212		− MUX(1, 137, 2, N, N, N, N),
2213		−};
2214		−
2215		−static struct atlas7_grp_mux c1_can_txd_grp0_mux = {
2216		− .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp0_pad_mux),
2217		− .pad_mux_list = c1_can_txd_grp0_pad_mux,
2218		−};
2219		−
2220		−static struct atlas7_pad_mux c1_can_txd_grp1_pad_mux[] = {
2221		− MUX(1, 146, 2, N, N, N, N),
2222		−};
2223		−
2224		−static struct atlas7_grp_mux c1_can_txd_grp1_mux = {
2225		− .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp1_pad_mux),
2226		− .pad_mux_list = c1_can_txd_grp1_pad_mux,
2227		−};
2228		−
2229		−static struct atlas7_pad_mux c1_can_txd_grp2_pad_mux[] = {
2230		− MUX(0, 3, 2, N, N, N, N),
2231		−};
2232		−
2233		−static struct atlas7_grp_mux c1_can_txd_grp2_mux = {
2234		− .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp2_pad_mux),
2235		− .pad_mux_list = c1_can_txd_grp2_pad_mux,
2236		−};
2237		−
2238		−static struct atlas7_pad_mux c1_can_txd_grp3_pad_mux[] = {
2239		− MUX(1, 161, 4, N, N, N, N),
2240		−};
2241		−
2242		−static struct atlas7_grp_mux c1_can_txd_grp3_mux = {
2243		− .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp3_pad_mux),
2244		− .pad_mux_list = c1_can_txd_grp3_pad_mux,
2245		−};
2246		−
2247		−static struct atlas7_pad_mux ca_audio_lpc_grp_pad_mux[] = {
2248		− MUX(1, 62, 4, N, N, N, N),
2249		− MUX(1, 63, 4, N, N, N, N),
2250		− MUX(1, 64, 4, N, N, N, N),
2251		− MUX(1, 65, 4, N, N, N, N),
2252		− MUX(1, 66, 4, N, N, N, N),
2253		− MUX(1, 67, 4, N, N, N, N),
2254		− MUX(1, 68, 4, N, N, N, N),
2255		− MUX(1, 69, 4, N, N, N, N),
2256		− MUX(1, 70, 4, N, N, N, N),
2257		− MUX(1, 71, 4, N, N, N, N),
2258		−};
2259		−
2260		−static struct atlas7_grp_mux ca_audio_lpc_grp_mux = {
2261		− .pad_mux_count = ARRAY_SIZE(ca_audio_lpc_grp_pad_mux),
2262		− .pad_mux_list = ca_audio_lpc_grp_pad_mux,
2263		−};
2264		−
2265		−static struct atlas7_pad_mux ca_bt_lpc_grp_pad_mux[] = {
2266		− MUX(1, 85, 5, N, N, N, N),
2267		− MUX(1, 86, 5, N, N, N, N),
2268		− MUX(1, 87, 5, N, N, N, N),
2269		− MUX(1, 88, 5, N, N, N, N),
2270		− MUX(1, 89, 5, N, N, N, N),
2271		− MUX(1, 90, 5, N, N, N, N),
2272		−};
2273		−
2274		−static struct atlas7_grp_mux ca_bt_lpc_grp_mux = {
2275		− .pad_mux_count = ARRAY_SIZE(ca_bt_lpc_grp_pad_mux),
2276		− .pad_mux_list = ca_bt_lpc_grp_pad_mux,
2277		−};
2278		−
2279		−static struct atlas7_pad_mux ca_coex_grp_pad_mux[] = {
2280		− MUX(1, 129, 1, N, N, N, N),
2281		− MUX(1, 130, 1, N, N, N, N),
2282		− MUX(1, 131, 1, N, N, N, N),
2283		− MUX(1, 132, 1, N, N, N, N),
2284		−};
2285		−
2286		−static struct atlas7_grp_mux ca_coex_grp_mux = {
2287		− .pad_mux_count = ARRAY_SIZE(ca_coex_grp_pad_mux),
2288		− .pad_mux_list = ca_coex_grp_pad_mux,
2289		−};
2290		−
2291		−static struct atlas7_pad_mux ca_curator_lpc_grp_pad_mux[] = {
2292		− MUX(1, 57, 4, N, N, N, N),
2293		− MUX(1, 58, 4, N, N, N, N),
2294		− MUX(1, 59, 4, N, N, N, N),
2295		− MUX(1, 60, 4, N, N, N, N),
2296		−};
2297		−
2298		−static struct atlas7_grp_mux ca_curator_lpc_grp_mux = {
2299		− .pad_mux_count = ARRAY_SIZE(ca_curator_lpc_grp_pad_mux),
2300		− .pad_mux_list = ca_curator_lpc_grp_pad_mux,
2301		−};
2302		−
2303		−static struct atlas7_pad_mux ca_pcm_debug_grp_pad_mux[] = {
2304		− MUX(1, 91, 5, N, N, N, N),
2305		− MUX(1, 93, 5, N, N, N, N),
2306		− MUX(1, 94, 5, N, N, N, N),
2307		− MUX(1, 92, 5, N, N, N, N),
2308		−};
2309		−
2310		−static struct atlas7_grp_mux ca_pcm_debug_grp_mux = {
2311		− .pad_mux_count = ARRAY_SIZE(ca_pcm_debug_grp_pad_mux),
2312		− .pad_mux_list = ca_pcm_debug_grp_pad_mux,
2313		−};
2314		−
2315		−static struct atlas7_pad_mux ca_pio_grp_pad_mux[] = {
2316		− MUX(1, 121, 2, N, N, N, N),
2317		− MUX(1, 122, 2, N, N, N, N),
2318		− MUX(1, 125, 6, N, N, N, N),
2319		− MUX(1, 126, 6, N, N, N, N),
2320		− MUX(1, 38, 5, N, N, N, N),
2321		− MUX(1, 37, 5, N, N, N, N),
2322		− MUX(1, 47, 5, N, N, N, N),
2323		− MUX(1, 49, 5, N, N, N, N),
2324		− MUX(1, 50, 5, N, N, N, N),
2325		− MUX(1, 54, 4, N, N, N, N),
2326		− MUX(1, 55, 4, N, N, N, N),
2327		− MUX(1, 56, 4, N, N, N, N),
2328		−};
2329		−
2330		−static struct atlas7_grp_mux ca_pio_grp_mux = {
2331		− .pad_mux_count = ARRAY_SIZE(ca_pio_grp_pad_mux),
2332		− .pad_mux_list = ca_pio_grp_pad_mux,
2333		−};
2334		−
2335		−static struct atlas7_pad_mux ca_sdio_debug_grp_pad_mux[] = {
2336		− MUX(1, 40, 5, N, N, N, N),
2337		− MUX(1, 39, 5, N, N, N, N),
2338		− MUX(1, 44, 5, N, N, N, N),
2339		− MUX(1, 43, 5, N, N, N, N),
2340		− MUX(1, 42, 5, N, N, N, N),
2341		− MUX(1, 41, 5, N, N, N, N),
2342		−};
2343		−
2344		−static struct atlas7_grp_mux ca_sdio_debug_grp_mux = {
2345		− .pad_mux_count = ARRAY_SIZE(ca_sdio_debug_grp_pad_mux),
2346		− .pad_mux_list = ca_sdio_debug_grp_pad_mux,
2347		−};
2348		−
2349		−static struct atlas7_pad_mux ca_spi_grp_pad_mux[] = {
2350		− MUX(1, 82, 5, N, N, N, N),
2351		− MUX(1, 79, 5, 0xa08, 6, 0xa88, 6),
2352		− MUX(1, 80, 5, N, N, N, N),
2353		− MUX(1, 81, 5, N, N, N, N),
2354		−};
2355		−
2356		−static struct atlas7_grp_mux ca_spi_grp_mux = {
2357		− .pad_mux_count = ARRAY_SIZE(ca_spi_grp_pad_mux),
2358		− .pad_mux_list = ca_spi_grp_pad_mux,
2359		−};
2360		−
2361		−static struct atlas7_pad_mux ca_trb_grp_pad_mux[] = {
2362		− MUX(1, 91, 4, N, N, N, N),
2363		− MUX(1, 93, 4, N, N, N, N),
2364		− MUX(1, 94, 4, N, N, N, N),
2365		− MUX(1, 95, 4, N, N, N, N),
2366		− MUX(1, 96, 4, N, N, N, N),
2367		− MUX(1, 78, 5, N, N, N, N),
2368		− MUX(1, 74, 5, N, N, N, N),
2369		− MUX(1, 75, 5, N, N, N, N),
2370		− MUX(1, 76, 5, N, N, N, N),
2371		− MUX(1, 77, 5, N, N, N, N),
2372		−};
2373		−
2374		−static struct atlas7_grp_mux ca_trb_grp_mux = {
2375		− .pad_mux_count = ARRAY_SIZE(ca_trb_grp_pad_mux),
2376		− .pad_mux_list = ca_trb_grp_pad_mux,
2377		−};
2378		−
2379		−static struct atlas7_pad_mux ca_uart_debug_grp_pad_mux[] = {
2380		− MUX(1, 136, 3, N, N, N, N),
2381		− MUX(1, 135, 3, N, N, N, N),
2382		− MUX(1, 134, 3, N, N, N, N),
2383		− MUX(1, 133, 3, N, N, N, N),
2384		−};
2385		−
2386		−static struct atlas7_grp_mux ca_uart_debug_grp_mux = {
2387		− .pad_mux_count = ARRAY_SIZE(ca_uart_debug_grp_pad_mux),
2388		− .pad_mux_list = ca_uart_debug_grp_pad_mux,
2389		−};
2390		−
2391		−static struct atlas7_pad_mux clkc_grp0_pad_mux[] = {
2392		− MUX(1, 30, 2, 0xa08, 14, 0xa88, 14),
2393		− MUX(1, 47, 6, N, N, N, N),
2394		−};
2395		−
2396		−static struct atlas7_grp_mux clkc_grp0_mux = {
2397		− .pad_mux_count = ARRAY_SIZE(clkc_grp0_pad_mux),
2398		− .pad_mux_list = clkc_grp0_pad_mux,
2399		−};
2400		−
2401		−static struct atlas7_pad_mux clkc_grp1_pad_mux[] = {
2402		− MUX(1, 78, 3, 0xa08, 14, 0xa88, 14),
2403		− MUX(1, 54, 5, N, N, N, N),
2404		−};
2405		−
2406		−static struct atlas7_grp_mux clkc_grp1_mux = {
2407		− .pad_mux_count = ARRAY_SIZE(clkc_grp1_pad_mux),
2408		− .pad_mux_list = clkc_grp1_pad_mux,
2409		−};
2410		−
2411		−static struct atlas7_pad_mux gn_gnss_i2c_grp_pad_mux[] = {
2412		− MUX(1, 128, 2, N, N, N, N),
2413		− MUX(1, 127, 2, N, N, N, N),
2414		−};
2415		−
2416		−static struct atlas7_grp_mux gn_gnss_i2c_grp_mux = {
2417		− .pad_mux_count = ARRAY_SIZE(gn_gnss_i2c_grp_pad_mux),
2418		− .pad_mux_list = gn_gnss_i2c_grp_pad_mux,
2419		−};
2420		−
2421		−static struct atlas7_pad_mux gn_gnss_uart_nopause_grp_pad_mux[] = {
2422		− MUX(1, 134, 4, N, N, N, N),
2423		− MUX(1, 133, 4, N, N, N, N),
2424		−};
2425		−
2426		−static struct atlas7_grp_mux gn_gnss_uart_nopause_grp_mux = {
2427		− .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_nopause_grp_pad_mux),
2428		− .pad_mux_list = gn_gnss_uart_nopause_grp_pad_mux,
2429		−};
2430		−
2431		−static struct atlas7_pad_mux gn_gnss_uart_grp_pad_mux[] = {
2432		− MUX(1, 134, 4, N, N, N, N),
2433		− MUX(1, 133, 4, N, N, N, N),
2434		− MUX(1, 136, 4, N, N, N, N),
2435		− MUX(1, 135, 4, N, N, N, N),
2436		−};
2437		−
2438		−static struct atlas7_grp_mux gn_gnss_uart_grp_mux = {
2439		− .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_grp_pad_mux),
2440		− .pad_mux_list = gn_gnss_uart_grp_pad_mux,
2441		−};
2442		−
2443		−static struct atlas7_pad_mux gn_trg_spi_grp0_pad_mux[] = {
2444		− MUX(1, 22, 1, N, N, N, N),
2445		− MUX(1, 25, 1, N, N, N, N),
2446		− MUX(1, 23, 1, 0xa00, 10, 0xa80, 10),
2447		− MUX(1, 24, 1, N, N, N, N),
2448		−};
2449		−
2450		−static struct atlas7_grp_mux gn_trg_spi_grp0_mux = {
2451		− .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp0_pad_mux),
2452		− .pad_mux_list = gn_trg_spi_grp0_pad_mux,
2453		−};
2454		−
2455		−static struct atlas7_pad_mux gn_trg_spi_grp1_pad_mux[] = {
2456		− MUX(1, 82, 3, N, N, N, N),
2457		− MUX(1, 79, 3, N, N, N, N),
2458		− MUX(1, 80, 3, 0xa00, 10, 0xa80, 10),
2459		− MUX(1, 81, 3, N, N, N, N),
2460		−};
2461		−
2462		−static struct atlas7_grp_mux gn_trg_spi_grp1_mux = {
2463		− .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp1_pad_mux),
2464		− .pad_mux_list = gn_trg_spi_grp1_pad_mux,
2465		−};
2466		−
2467		−static struct atlas7_pad_mux cvbs_dbg_grp_pad_mux[] = {
2468		− MUX(1, 54, 3, N, N, N, N),
2469		− MUX(1, 53, 3, N, N, N, N),
2470		− MUX(1, 82, 7, N, N, N, N),
2471		− MUX(1, 74, 7, N, N, N, N),
2472		− MUX(1, 75, 7, N, N, N, N),
2473		− MUX(1, 76, 7, N, N, N, N),
2474		− MUX(1, 77, 7, N, N, N, N),
2475		− MUX(1, 78, 7, N, N, N, N),
2476		− MUX(1, 79, 7, N, N, N, N),
2477		− MUX(1, 80, 7, N, N, N, N),
2478		− MUX(1, 81, 7, N, N, N, N),
2479		− MUX(1, 83, 7, N, N, N, N),
2480		− MUX(1, 84, 7, N, N, N, N),
2481		− MUX(1, 73, 3, N, N, N, N),
2482		− MUX(1, 55, 3, N, N, N, N),
2483		− MUX(1, 56, 3, N, N, N, N),
2484		−};
2485		−
2486		−static struct atlas7_grp_mux cvbs_dbg_grp_mux = {
2487		− .pad_mux_count = ARRAY_SIZE(cvbs_dbg_grp_pad_mux),
2488		− .pad_mux_list = cvbs_dbg_grp_pad_mux,
2489		−};
2490		−
2491		−static struct atlas7_pad_mux cvbs_dbg_test_grp0_pad_mux[] = {
2492		− MUX(1, 57, 3, N, N, N, N),
2493		−};
2494		−
2495		−static struct atlas7_grp_mux cvbs_dbg_test_grp0_mux = {
2496		− .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp0_pad_mux),
2497		− .pad_mux_list = cvbs_dbg_test_grp0_pad_mux,
2498		−};
2499		−
2500		−static struct atlas7_pad_mux cvbs_dbg_test_grp1_pad_mux[] = {
2501		− MUX(1, 58, 3, N, N, N, N),
2502		−};
2503		−
2504		−static struct atlas7_grp_mux cvbs_dbg_test_grp1_mux = {
2505		− .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp1_pad_mux),
2506		− .pad_mux_list = cvbs_dbg_test_grp1_pad_mux,
2507		−};
2508		−
2509		−static struct atlas7_pad_mux cvbs_dbg_test_grp2_pad_mux[] = {
2510		− MUX(1, 59, 3, N, N, N, N),
2511		−};
2512		−
2513		−static struct atlas7_grp_mux cvbs_dbg_test_grp2_mux = {
2514		− .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp2_pad_mux),
2515		− .pad_mux_list = cvbs_dbg_test_grp2_pad_mux,
2516		−};
2517		−
2518		−static struct atlas7_pad_mux cvbs_dbg_test_grp3_pad_mux[] = {
2519		− MUX(1, 60, 3, N, N, N, N),
2520		−};
2521		−
2522		−static struct atlas7_grp_mux cvbs_dbg_test_grp3_mux = {
2523		− .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp3_pad_mux),
2524		− .pad_mux_list = cvbs_dbg_test_grp3_pad_mux,
2525		−};
2526		−
2527		−static struct atlas7_pad_mux cvbs_dbg_test_grp4_pad_mux[] = {
2528		− MUX(1, 61, 3, N, N, N, N),
2529		−};
2530		−
2531		−static struct atlas7_grp_mux cvbs_dbg_test_grp4_mux = {
2532		− .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp4_pad_mux),
2533		− .pad_mux_list = cvbs_dbg_test_grp4_pad_mux,
2534		−};
2535		−
2536		−static struct atlas7_pad_mux cvbs_dbg_test_grp5_pad_mux[] = {
2537		− MUX(1, 62, 3, N, N, N, N),
2538		−};
2539		−
2540		−static struct atlas7_grp_mux cvbs_dbg_test_grp5_mux = {
2541		− .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp5_pad_mux),
2542		− .pad_mux_list = cvbs_dbg_test_grp5_pad_mux,
2543		−};
2544		−
2545		−static struct atlas7_pad_mux cvbs_dbg_test_grp6_pad_mux[] = {
2546		− MUX(1, 63, 3, N, N, N, N),
2547		−};
2548		−
2549		−static struct atlas7_grp_mux cvbs_dbg_test_grp6_mux = {
2550		− .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp6_pad_mux),
2551		− .pad_mux_list = cvbs_dbg_test_grp6_pad_mux,
2552		−};
2553		−
2554		−static struct atlas7_pad_mux cvbs_dbg_test_grp7_pad_mux[] = {
2555		− MUX(1, 64, 3, N, N, N, N),
2556		−};
2557		−
2558		−static struct atlas7_grp_mux cvbs_dbg_test_grp7_mux = {
2559		− .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp7_pad_mux),
2560		− .pad_mux_list = cvbs_dbg_test_grp7_pad_mux,
2561		−};
2562		−
2563		−static struct atlas7_pad_mux cvbs_dbg_test_grp8_pad_mux[] = {
2564		− MUX(1, 65, 3, N, N, N, N),
2565		−};
2566		−
2567		−static struct atlas7_grp_mux cvbs_dbg_test_grp8_mux = {
2568		− .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp8_pad_mux),
2569		− .pad_mux_list = cvbs_dbg_test_grp8_pad_mux,
2570		−};
2571		−
2572		−static struct atlas7_pad_mux cvbs_dbg_test_grp9_pad_mux[] = {
2573		− MUX(1, 66, 3, N, N, N, N),
2574		−};
2575		−
2576		−static struct atlas7_grp_mux cvbs_dbg_test_grp9_mux = {
2577		− .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp9_pad_mux),
2578		− .pad_mux_list = cvbs_dbg_test_grp9_pad_mux,
2579		−};
2580		−
2581		−static struct atlas7_pad_mux cvbs_dbg_test_grp10_pad_mux[] = {
2582		− MUX(1, 67, 3, N, N, N, N),
2583		−};
2584		−
2585		−static struct atlas7_grp_mux cvbs_dbg_test_grp10_mux = {
2586		− .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp10_pad_mux),
2587		− .pad_mux_list = cvbs_dbg_test_grp10_pad_mux,
2588		−};
2589		−
2590		−static struct atlas7_pad_mux cvbs_dbg_test_grp11_pad_mux[] = {
2591		− MUX(1, 68, 3, N, N, N, N),
2592		−};
2593		−
2594		−static struct atlas7_grp_mux cvbs_dbg_test_grp11_mux = {
2595		− .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp11_pad_mux),
2596		− .pad_mux_list = cvbs_dbg_test_grp11_pad_mux,
2597		−};
2598		−
2599		−static struct atlas7_pad_mux cvbs_dbg_test_grp12_pad_mux[] = {
2600		− MUX(1, 69, 3, N, N, N, N),
2601		−};
2602		−
2603		−static struct atlas7_grp_mux cvbs_dbg_test_grp12_mux = {
2604		− .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp12_pad_mux),
2605		− .pad_mux_list = cvbs_dbg_test_grp12_pad_mux,
2606		−};
2607		−
2608		−static struct atlas7_pad_mux cvbs_dbg_test_grp13_pad_mux[] = {
2609		− MUX(1, 70, 3, N, N, N, N),
2610		−};
2611		−
2612		−static struct atlas7_grp_mux cvbs_dbg_test_grp13_mux = {
2613		− .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp13_pad_mux),
2614		− .pad_mux_list = cvbs_dbg_test_grp13_pad_mux,
2615		−};
2616		−
2617		−static struct atlas7_pad_mux cvbs_dbg_test_grp14_pad_mux[] = {
2618		− MUX(1, 71, 3, N, N, N, N),
2619		−};
2620		−
2621		−static struct atlas7_grp_mux cvbs_dbg_test_grp14_mux = {
2622		− .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp14_pad_mux),
2623		− .pad_mux_list = cvbs_dbg_test_grp14_pad_mux,
2624		−};
2625		−
2626		−static struct atlas7_pad_mux cvbs_dbg_test_grp15_pad_mux[] = {
2627		− MUX(1, 72, 3, N, N, N, N),
2628		−};
2629		−
2630		−static struct atlas7_grp_mux cvbs_dbg_test_grp15_mux = {
2631		− .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp15_pad_mux),
2632		− .pad_mux_list = cvbs_dbg_test_grp15_pad_mux,
2633		−};
2634		−
2635		−static struct atlas7_pad_mux gn_gnss_power_grp_pad_mux[] = {
2636		− MUX(1, 123, 7, N, N, N, N),
2637		− MUX(1, 124, 7, N, N, N, N),
2638		− MUX(1, 121, 7, N, N, N, N),
2639		− MUX(1, 122, 7, N, N, N, N),
2640		− MUX(1, 125, 7, N, N, N, N),
2641		− MUX(1, 120, 7, N, N, N, N),
2642		−};
2643		−
2644		−static struct atlas7_grp_mux gn_gnss_power_grp_mux = {
2645		− .pad_mux_count = ARRAY_SIZE(gn_gnss_power_grp_pad_mux),
2646		− .pad_mux_list = gn_gnss_power_grp_pad_mux,
2647		−};
2648		−
2649		−static struct atlas7_pad_mux gn_gnss_sw_status_grp_pad_mux[] = {
2650		− MUX(1, 57, 7, N, N, N, N),
2651		− MUX(1, 58, 7, N, N, N, N),
2652		− MUX(1, 59, 7, N, N, N, N),
2653		− MUX(1, 60, 7, N, N, N, N),
2654		− MUX(1, 61, 7, N, N, N, N),
2655		− MUX(1, 62, 7, N, N, N, N),
2656		− MUX(1, 63, 7, N, N, N, N),
2657		− MUX(1, 64, 7, N, N, N, N),
2658		− MUX(1, 65, 7, N, N, N, N),
2659		− MUX(1, 66, 7, N, N, N, N),
2660		− MUX(1, 67, 7, N, N, N, N),
2661		− MUX(1, 68, 7, N, N, N, N),
2662		− MUX(1, 69, 7, N, N, N, N),
2663		− MUX(1, 70, 7, N, N, N, N),
2664		− MUX(1, 71, 7, N, N, N, N),
2665		− MUX(1, 72, 7, N, N, N, N),
2666		− MUX(1, 53, 7, N, N, N, N),
2667		− MUX(1, 55, 7, N, N, N, N),
2668		− MUX(1, 56, 7, 0xa08, 12, 0xa88, 12),
2669		− MUX(1, 54, 7, N, N, N, N),
2670		−};
2671		−
2672		−static struct atlas7_grp_mux gn_gnss_sw_status_grp_mux = {
2673		− .pad_mux_count = ARRAY_SIZE(gn_gnss_sw_status_grp_pad_mux),
2674		− .pad_mux_list = gn_gnss_sw_status_grp_pad_mux,
2675		−};
2676		−
2677		−static struct atlas7_pad_mux gn_gnss_eclk_grp_pad_mux[] = {
2678		− MUX(1, 113, 4, N, N, N, N),
2679		−};
2680		−
2681		−static struct atlas7_grp_mux gn_gnss_eclk_grp_mux = {
2682		− .pad_mux_count = ARRAY_SIZE(gn_gnss_eclk_grp_pad_mux),
2683		− .pad_mux_list = gn_gnss_eclk_grp_pad_mux,
2684		−};
2685		−
2686		−static struct atlas7_pad_mux gn_gnss_irq1_grp0_pad_mux[] = {
2687		− MUX(1, 112, 4, 0xa08, 10, 0xa88, 10),
2688		−};
2689		−
2690		−static struct atlas7_grp_mux gn_gnss_irq1_grp0_mux = {
2691		− .pad_mux_count = ARRAY_SIZE(gn_gnss_irq1_grp0_pad_mux),
2692		− .pad_mux_list = gn_gnss_irq1_grp0_pad_mux,
2693		−};
2694		−
2695		−static struct atlas7_pad_mux gn_gnss_irq2_grp0_pad_mux[] = {
2696		− MUX(1, 118, 4, 0xa08, 11, 0xa88, 11),
2697		−};
2698		−
2699		−static struct atlas7_grp_mux gn_gnss_irq2_grp0_mux = {
2700		− .pad_mux_count = ARRAY_SIZE(gn_gnss_irq2_grp0_pad_mux),
2701		− .pad_mux_list = gn_gnss_irq2_grp0_pad_mux,
2702		−};
2703		−
2704		−static struct atlas7_pad_mux gn_gnss_tm_grp_pad_mux[] = {
2705		− MUX(1, 115, 4, N, N, N, N),
2706		−};
2707		−
2708		−static struct atlas7_grp_mux gn_gnss_tm_grp_mux = {
2709		− .pad_mux_count = ARRAY_SIZE(gn_gnss_tm_grp_pad_mux),
2710		− .pad_mux_list = gn_gnss_tm_grp_pad_mux,
2711		−};
2712		−
2713		−static struct atlas7_pad_mux gn_gnss_tsync_grp_pad_mux[] = {
2714		− MUX(1, 114, 4, N, N, N, N),
2715		−};
2716		−
2717		−static struct atlas7_grp_mux gn_gnss_tsync_grp_mux = {
2718		− .pad_mux_count = ARRAY_SIZE(gn_gnss_tsync_grp_pad_mux),
2719		− .pad_mux_list = gn_gnss_tsync_grp_pad_mux,
2720		−};
2721		−
2722		−static struct atlas7_pad_mux gn_io_gnsssys_sw_cfg_grp_pad_mux[] = {
2723		− MUX(1, 44, 7, N, N, N, N),
2724		− MUX(1, 43, 7, N, N, N, N),
2725		− MUX(1, 42, 7, N, N, N, N),
2726		− MUX(1, 41, 7, N, N, N, N),
2727		− MUX(1, 40, 7, N, N, N, N),
2728		− MUX(1, 39, 7, N, N, N, N),
2729		− MUX(1, 38, 7, N, N, N, N),
2730		− MUX(1, 37, 7, N, N, N, N),
2731		− MUX(1, 49, 7, N, N, N, N),
2732		− MUX(1, 50, 7, N, N, N, N),
2733		− MUX(1, 91, 7, N, N, N, N),
2734		− MUX(1, 92, 7, N, N, N, N),
2735		− MUX(1, 93, 7, N, N, N, N),
2736		− MUX(1, 94, 7, N, N, N, N),
2737		− MUX(1, 95, 7, N, N, N, N),
2738		− MUX(1, 96, 7, N, N, N, N),
2739		−};
2740		−
2741		−static struct atlas7_grp_mux gn_io_gnsssys_sw_cfg_grp_mux = {
2742		− .pad_mux_count = ARRAY_SIZE(gn_io_gnsssys_sw_cfg_grp_pad_mux),
2743		− .pad_mux_list = gn_io_gnsssys_sw_cfg_grp_pad_mux,
2744		−};
2745		−
2746		−static struct atlas7_pad_mux gn_trg_grp0_pad_mux[] = {
2747		− MUX(1, 29, 1, 0xa00, 6, 0xa80, 6),
2748		− MUX(1, 28, 1, 0xa00, 7, 0xa80, 7),
2749		− MUX(1, 26, 1, 0xa00, 8, 0xa80, 8),
2750		− MUX(1, 27, 1, 0xa00, 9, 0xa80, 9),
2751		−};
2752		−
2753		−static struct atlas7_grp_mux gn_trg_grp0_mux = {
2754		− .pad_mux_count = ARRAY_SIZE(gn_trg_grp0_pad_mux),
2755		− .pad_mux_list = gn_trg_grp0_pad_mux,
2756		−};
2757		−
2758		−static struct atlas7_pad_mux gn_trg_grp1_pad_mux[] = {
2759		− MUX(1, 77, 3, 0xa00, 6, 0xa80, 6),
2760		− MUX(1, 76, 3, 0xa00, 7, 0xa80, 7),
2761		− MUX(1, 74, 3, 0xa00, 8, 0xa80, 8),
2762		− MUX(1, 75, 3, 0xa00, 9, 0xa80, 9),
2763		−};
2764		−
2765		−static struct atlas7_grp_mux gn_trg_grp1_mux = {
2766		− .pad_mux_count = ARRAY_SIZE(gn_trg_grp1_pad_mux),
2767		− .pad_mux_list = gn_trg_grp1_pad_mux,
2768		−};
2769		−
2770		−static struct atlas7_pad_mux gn_trg_shutdown_grp0_pad_mux[] = {
2771		− MUX(1, 30, 1, N, N, N, N),
2772		−};
2773		−
2774		−static struct atlas7_grp_mux gn_trg_shutdown_grp0_mux = {
2775		− .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp0_pad_mux),
2776		− .pad_mux_list = gn_trg_shutdown_grp0_pad_mux,
2777		−};
2778		−
2779		−static struct atlas7_pad_mux gn_trg_shutdown_grp1_pad_mux[] = {
2780		− MUX(1, 83, 3, N, N, N, N),
2781		−};
2782		−
2783		−static struct atlas7_grp_mux gn_trg_shutdown_grp1_mux = {
2784		− .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp1_pad_mux),
2785		− .pad_mux_list = gn_trg_shutdown_grp1_pad_mux,
2786		−};
2787		−
2788		−static struct atlas7_pad_mux gn_trg_shutdown_grp2_pad_mux[] = {
2789		− MUX(1, 117, 4, N, N, N, N),
2790		−};
2791		−
2792		−static struct atlas7_grp_mux gn_trg_shutdown_grp2_mux = {
2793		− .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp2_pad_mux),
2794		− .pad_mux_list = gn_trg_shutdown_grp2_pad_mux,
2795		−};
2796		−
2797		−static struct atlas7_pad_mux gn_trg_shutdown_grp3_pad_mux[] = {
2798		− MUX(1, 123, 5, N, N, N, N),
2799		−};
2800		−
2801		−static struct atlas7_grp_mux gn_trg_shutdown_grp3_mux = {
2802		− .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp3_pad_mux),
2803		− .pad_mux_list = gn_trg_shutdown_grp3_pad_mux,
2804		−};
2805		−
2806		−static struct atlas7_pad_mux i2c0_grp_pad_mux[] = {
2807		− MUX(1, 128, 1, N, N, N, N),
2808		− MUX(1, 127, 1, N, N, N, N),
2809		−};
2810		−
2811		−static struct atlas7_grp_mux i2c0_grp_mux = {
2812		− .pad_mux_count = ARRAY_SIZE(i2c0_grp_pad_mux),
2813		− .pad_mux_list = i2c0_grp_pad_mux,
2814		−};
2815		−
2816		−static struct atlas7_pad_mux i2c1_grp_pad_mux[] = {
2817		− MUX(1, 126, 4, N, N, N, N),
2818		− MUX(1, 125, 4, N, N, N, N),
2819		−};
2820		−
2821		−static struct atlas7_grp_mux i2c1_grp_mux = {
2822		− .pad_mux_count = ARRAY_SIZE(i2c1_grp_pad_mux),
2823		− .pad_mux_list = i2c1_grp_pad_mux,
2824		−};
2825		−
2826		−static struct atlas7_pad_mux i2s0_grp_pad_mux[] = {
2827		− MUX(1, 91, 2, 0xa10, 12, 0xa90, 12),
2828		− MUX(1, 93, 2, 0xa10, 13, 0xa90, 13),
2829		− MUX(1, 94, 2, 0xa10, 14, 0xa90, 14),
2830		− MUX(1, 92, 2, 0xa10, 15, 0xa90, 15),
2831		−};
2832		−
2833		−static struct atlas7_grp_mux i2s0_grp_mux = {
2834		− .pad_mux_count = ARRAY_SIZE(i2s0_grp_pad_mux),
2835		− .pad_mux_list = i2s0_grp_pad_mux,
2836		−};
2837		−
2838		−static struct atlas7_pad_mux i2s1_basic_grp_pad_mux[] = {
2839		− MUX(1, 95, 2, 0xa10, 16, 0xa90, 16),
2840		− MUX(1, 96, 2, 0xa10, 19, 0xa90, 19),
2841		−};
2842		−
2843		−static struct atlas7_grp_mux i2s1_basic_grp_mux = {
2844		− .pad_mux_count = ARRAY_SIZE(i2s1_basic_grp_pad_mux),
2845		− .pad_mux_list = i2s1_basic_grp_pad_mux,
2846		−};
2847		−
2848		−static struct atlas7_pad_mux i2s1_rxd0_grp0_pad_mux[] = {
2849		− MUX(1, 61, 4, 0xa10, 17, 0xa90, 17),
2850		−};
2851		−
2852		−static struct atlas7_grp_mux i2s1_rxd0_grp0_mux = {
2853		− .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp0_pad_mux),
2854		− .pad_mux_list = i2s1_rxd0_grp0_pad_mux,
2855		−};
2856		−
2857		−static struct atlas7_pad_mux i2s1_rxd0_grp1_pad_mux[] = {
2858		− MUX(1, 131, 4, 0xa10, 17, 0xa90, 17),
2859		−};
2860		−
2861		−static struct atlas7_grp_mux i2s1_rxd0_grp1_mux = {
2862		− .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp1_pad_mux),
2863		− .pad_mux_list = i2s1_rxd0_grp1_pad_mux,
2864		−};
2865		−
2866		−static struct atlas7_pad_mux i2s1_rxd0_grp2_pad_mux[] = {
2867		− MUX(1, 129, 2, 0xa10, 17, 0xa90, 17),
2868		−};
2869		−
2870		−static struct atlas7_grp_mux i2s1_rxd0_grp2_mux = {
2871		− .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp2_pad_mux),
2872		− .pad_mux_list = i2s1_rxd0_grp2_pad_mux,
2873		−};
2874		−
2875		−static struct atlas7_pad_mux i2s1_rxd0_grp3_pad_mux[] = {
2876		− MUX(1, 117, 7, 0xa10, 17, 0xa90, 17),
2877		−};
2878		−
2879		−static struct atlas7_grp_mux i2s1_rxd0_grp3_mux = {
2880		− .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp3_pad_mux),
2881		− .pad_mux_list = i2s1_rxd0_grp3_pad_mux,
2882		−};
2883		−
2884		−static struct atlas7_pad_mux i2s1_rxd0_grp4_pad_mux[] = {
2885		− MUX(1, 83, 4, 0xa10, 17, 0xa90, 17),
2886		−};
2887		−
2888		−static struct atlas7_grp_mux i2s1_rxd0_grp4_mux = {
2889		− .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp4_pad_mux),
2890		− .pad_mux_list = i2s1_rxd0_grp4_pad_mux,
2891		−};
2892		−
2893		−static struct atlas7_pad_mux i2s1_rxd1_grp0_pad_mux[] = {
2894		− MUX(1, 72, 4, 0xa10, 18, 0xa90, 18),
2895		−};
2896		−
2897		−static struct atlas7_grp_mux i2s1_rxd1_grp0_mux = {
2898		− .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp0_pad_mux),
2899		− .pad_mux_list = i2s1_rxd1_grp0_pad_mux,
2900		−};
2901		−
2902		−static struct atlas7_pad_mux i2s1_rxd1_grp1_pad_mux[] = {
2903		− MUX(1, 132, 4, 0xa10, 18, 0xa90, 18),
2904		−};
2905		−
2906		−static struct atlas7_grp_mux i2s1_rxd1_grp1_mux = {
2907		− .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp1_pad_mux),
2908		− .pad_mux_list = i2s1_rxd1_grp1_pad_mux,
2909		−};
2910		−
2911		−static struct atlas7_pad_mux i2s1_rxd1_grp2_pad_mux[] = {
2912		− MUX(1, 130, 2, 0xa10, 18, 0xa90, 18),
2913		−};
2914		−
2915		−static struct atlas7_grp_mux i2s1_rxd1_grp2_mux = {
2916		− .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp2_pad_mux),
2917		− .pad_mux_list = i2s1_rxd1_grp2_pad_mux,
2918		−};
2919		−
2920		−static struct atlas7_pad_mux i2s1_rxd1_grp3_pad_mux[] = {
2921		− MUX(1, 118, 7, 0xa10, 18, 0xa90, 18),
2922		−};
2923		−
2924		−static struct atlas7_grp_mux i2s1_rxd1_grp3_mux = {
2925		− .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp3_pad_mux),
2926		− .pad_mux_list = i2s1_rxd1_grp3_pad_mux,
2927		−};
2928		−
2929		−static struct atlas7_pad_mux i2s1_rxd1_grp4_pad_mux[] = {
2930		− MUX(1, 84, 4, 0xa10, 18, 0xa90, 18),
2931		−};
2932		−
2933		−static struct atlas7_grp_mux i2s1_rxd1_grp4_mux = {
2934		− .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp4_pad_mux),
2935		− .pad_mux_list = i2s1_rxd1_grp4_pad_mux,
2936		−};
2937		−
2938		−static struct atlas7_pad_mux jtag_jt_dbg_nsrst_grp_pad_mux[] = {
2939		− MUX(1, 125, 5, 0xa08, 2, 0xa88, 2),
2940		−};
2941		−
2942		−static struct atlas7_grp_mux jtag_jt_dbg_nsrst_grp_mux = {
2943		− .pad_mux_count = ARRAY_SIZE(jtag_jt_dbg_nsrst_grp_pad_mux),
2944		− .pad_mux_list = jtag_jt_dbg_nsrst_grp_pad_mux,
2945		−};
2946		−
2947		−static struct atlas7_pad_mux jtag_ntrst_grp0_pad_mux[] = {
2948		− MUX(0, 4, 3, 0xa08, 3, 0xa88, 3),
2949		−};
2950		−
2951		−static struct atlas7_grp_mux jtag_ntrst_grp0_mux = {
2952		− .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp0_pad_mux),
2953		− .pad_mux_list = jtag_ntrst_grp0_pad_mux,
2954		−};
2955		−
2956		−static struct atlas7_pad_mux jtag_ntrst_grp1_pad_mux[] = {
2957		− MUX(1, 163, 1, 0xa08, 3, 0xa88, 3),
2958		−};
2959		−
2960		−static struct atlas7_grp_mux jtag_ntrst_grp1_mux = {
2961		− .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp1_pad_mux),
2962		− .pad_mux_list = jtag_ntrst_grp1_pad_mux,
2963		−};
2964		−
2965		−static struct atlas7_pad_mux jtag_swdiotms_grp0_pad_mux[] = {
2966		− MUX(0, 2, 3, 0xa10, 10, 0xa90, 10),
2967		−};
2968		−
2969		−static struct atlas7_grp_mux jtag_swdiotms_grp0_mux = {
2970		− .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp0_pad_mux),
2971		− .pad_mux_list = jtag_swdiotms_grp0_pad_mux,
2972		−};
2973		−
2974		−static struct atlas7_pad_mux jtag_swdiotms_grp1_pad_mux[] = {
2975		− MUX(1, 160, 1, 0xa10, 10, 0xa90, 10),
2976		−};
2977		−
2978		−static struct atlas7_grp_mux jtag_swdiotms_grp1_mux = {
2979		− .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp1_pad_mux),
2980		− .pad_mux_list = jtag_swdiotms_grp1_pad_mux,
2981		−};
2982		−
2983		−static struct atlas7_pad_mux jtag_tck_grp0_pad_mux[] = {
2984		− MUX(0, 0, 3, 0xa10, 11, 0xa90, 11),
2985		−};
2986		−
2987		−static struct atlas7_grp_mux jtag_tck_grp0_mux = {
2988		− .pad_mux_count = ARRAY_SIZE(jtag_tck_grp0_pad_mux),
2989		− .pad_mux_list = jtag_tck_grp0_pad_mux,
2990		−};
2991		−
2992		−static struct atlas7_pad_mux jtag_tck_grp1_pad_mux[] = {
2993		− MUX(1, 161, 1, 0xa10, 11, 0xa90, 11),
2994		−};
2995		−
2996		−static struct atlas7_grp_mux jtag_tck_grp1_mux = {
2997		− .pad_mux_count = ARRAY_SIZE(jtag_tck_grp1_pad_mux),
2998		− .pad_mux_list = jtag_tck_grp1_pad_mux,
2999		−};
3000		−
3001		−static struct atlas7_pad_mux jtag_tdi_grp0_pad_mux[] = {
3002		− MUX(0, 1, 3, 0xa10, 31, 0xa90, 31),
3003		−};
3004		−
3005		−static struct atlas7_grp_mux jtag_tdi_grp0_mux = {
3006		− .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp0_pad_mux),
3007		− .pad_mux_list = jtag_tdi_grp0_pad_mux,
3008		−};
3009		−
3010		−static struct atlas7_pad_mux jtag_tdi_grp1_pad_mux[] = {
3011		− MUX(1, 162, 1, 0xa10, 31, 0xa90, 31),
3012		−};
3013		−
3014		−static struct atlas7_grp_mux jtag_tdi_grp1_mux = {
3015		− .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp1_pad_mux),
3016		− .pad_mux_list = jtag_tdi_grp1_pad_mux,
3017		−};
3018		−
3019		−static struct atlas7_pad_mux jtag_tdo_grp0_pad_mux[] = {
3020		− MUX(0, 3, 3, N, N, N, N),
3021		−};
3022		−
3023		−static struct atlas7_grp_mux jtag_tdo_grp0_mux = {
3024		− .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp0_pad_mux),
3025		− .pad_mux_list = jtag_tdo_grp0_pad_mux,
3026		−};
3027		−
3028		−static struct atlas7_pad_mux jtag_tdo_grp1_pad_mux[] = {
3029		− MUX(1, 159, 1, N, N, N, N),
3030		−};
3031		−
3032		−static struct atlas7_grp_mux jtag_tdo_grp1_mux = {
3033		− .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp1_pad_mux),
3034		− .pad_mux_list = jtag_tdo_grp1_pad_mux,
3035		−};
3036		−
3037		−static struct atlas7_pad_mux ks_kas_spi_grp0_pad_mux[] = {
3038		− MUX(1, 141, 2, N, N, N, N),
3039		− MUX(1, 144, 2, 0xa08, 8, 0xa88, 8),
3040		− MUX(1, 143, 2, N, N, N, N),
3041		− MUX(1, 142, 2, N, N, N, N),
3042		−};
3043		−
3044		−static struct atlas7_grp_mux ks_kas_spi_grp0_mux = {
3045		− .pad_mux_count = ARRAY_SIZE(ks_kas_spi_grp0_pad_mux),
3046		− .pad_mux_list = ks_kas_spi_grp0_pad_mux,
3047		−};
3048		−
3049		−static struct atlas7_pad_mux ld_ldd_grp_pad_mux[] = {
3050		− MUX(1, 57, 1, N, N, N, N),
3051		− MUX(1, 58, 1, N, N, N, N),
3052		− MUX(1, 59, 1, N, N, N, N),
3053		− MUX(1, 60, 1, N, N, N, N),
3054		− MUX(1, 61, 1, N, N, N, N),
3055		− MUX(1, 62, 1, N, N, N, N),
3056		− MUX(1, 63, 1, N, N, N, N),
3057		− MUX(1, 64, 1, N, N, N, N),
3058		− MUX(1, 65, 1, N, N, N, N),
3059		− MUX(1, 66, 1, N, N, N, N),
3060		− MUX(1, 67, 1, N, N, N, N),
3061		− MUX(1, 68, 1, N, N, N, N),
3062		− MUX(1, 69, 1, N, N, N, N),
3063		− MUX(1, 70, 1, N, N, N, N),
3064		− MUX(1, 71, 1, N, N, N, N),
3065		− MUX(1, 72, 1, N, N, N, N),
3066		− MUX(1, 74, 2, N, N, N, N),
3067		− MUX(1, 75, 2, N, N, N, N),
3068		− MUX(1, 76, 2, N, N, N, N),
3069		− MUX(1, 77, 2, N, N, N, N),
3070		− MUX(1, 78, 2, N, N, N, N),
3071		− MUX(1, 79, 2, N, N, N, N),
3072		− MUX(1, 80, 2, N, N, N, N),
3073		− MUX(1, 81, 2, N, N, N, N),
3074		− MUX(1, 56, 1, N, N, N, N),
3075		− MUX(1, 53, 1, N, N, N, N),
3076		−};
3077		−
3078		−static struct atlas7_grp_mux ld_ldd_grp_mux = {
3079		− .pad_mux_count = ARRAY_SIZE(ld_ldd_grp_pad_mux),
3080		− .pad_mux_list = ld_ldd_grp_pad_mux,
3081		−};
3082		−
3083		−static struct atlas7_pad_mux ld_ldd_16bit_grp_pad_mux[] = {
3084		− MUX(1, 57, 1, N, N, N, N),
3085		− MUX(1, 58, 1, N, N, N, N),
3086		− MUX(1, 59, 1, N, N, N, N),
3087		− MUX(1, 60, 1, N, N, N, N),
3088		− MUX(1, 61, 1, N, N, N, N),
3089		− MUX(1, 62, 1, N, N, N, N),
3090		− MUX(1, 63, 1, N, N, N, N),
3091		− MUX(1, 64, 1, N, N, N, N),
3092		− MUX(1, 65, 1, N, N, N, N),
3093		− MUX(1, 66, 1, N, N, N, N),
3094		− MUX(1, 67, 1, N, N, N, N),
3095		− MUX(1, 68, 1, N, N, N, N),
3096		− MUX(1, 69, 1, N, N, N, N),
3097		− MUX(1, 70, 1, N, N, N, N),
3098		− MUX(1, 71, 1, N, N, N, N),
3099		− MUX(1, 72, 1, N, N, N, N),
3100		− MUX(1, 56, 1, N, N, N, N),
3101		− MUX(1, 53, 1, N, N, N, N),
3102		−};
3103		−
3104		−static struct atlas7_grp_mux ld_ldd_16bit_grp_mux = {
3105		− .pad_mux_count = ARRAY_SIZE(ld_ldd_16bit_grp_pad_mux),
3106		− .pad_mux_list = ld_ldd_16bit_grp_pad_mux,
3107		−};
3108		−
3109		−static struct atlas7_pad_mux ld_ldd_fck_grp_pad_mux[] = {
3110		− MUX(1, 55, 1, N, N, N, N),
3111		−};
3112		−
3113		−static struct atlas7_grp_mux ld_ldd_fck_grp_mux = {
3114		− .pad_mux_count = ARRAY_SIZE(ld_ldd_fck_grp_pad_mux),
3115		− .pad_mux_list = ld_ldd_fck_grp_pad_mux,
3116		−};
3117		−
3118		−static struct atlas7_pad_mux ld_ldd_lck_grp_pad_mux[] = {
3119		− MUX(1, 54, 1, N, N, N, N),
3120		−};
3121		−
3122		−static struct atlas7_grp_mux ld_ldd_lck_grp_mux = {
3123		− .pad_mux_count = ARRAY_SIZE(ld_ldd_lck_grp_pad_mux),
3124		− .pad_mux_list = ld_ldd_lck_grp_pad_mux,
3125		−};
3126		−
3127		−static struct atlas7_pad_mux lr_lcdrom_grp_pad_mux[] = {
3128		− MUX(1, 73, 2, N, N, N, N),
3129		− MUX(1, 54, 2, N, N, N, N),
3130		− MUX(1, 57, 2, N, N, N, N),
3131		− MUX(1, 58, 2, N, N, N, N),
3132		− MUX(1, 59, 2, N, N, N, N),
3133		− MUX(1, 60, 2, N, N, N, N),
3134		− MUX(1, 61, 2, N, N, N, N),
3135		− MUX(1, 62, 2, N, N, N, N),
3136		− MUX(1, 63, 2, N, N, N, N),
3137		− MUX(1, 64, 2, N, N, N, N),
3138		− MUX(1, 65, 2, N, N, N, N),
3139		− MUX(1, 66, 2, N, N, N, N),
3140		− MUX(1, 67, 2, N, N, N, N),
3141		− MUX(1, 68, 2, N, N, N, N),
3142		− MUX(1, 69, 2, N, N, N, N),
3143		− MUX(1, 70, 2, N, N, N, N),
3144		− MUX(1, 71, 2, N, N, N, N),
3145		− MUX(1, 72, 2, N, N, N, N),
3146		− MUX(1, 56, 2, N, N, N, N),
3147		− MUX(1, 53, 2, N, N, N, N),
3148		− MUX(1, 55, 2, N, N, N, N),
3149		−};
3150		−
3151		−static struct atlas7_grp_mux lr_lcdrom_grp_mux = {
3152		− .pad_mux_count = ARRAY_SIZE(lr_lcdrom_grp_pad_mux),
3153		− .pad_mux_list = lr_lcdrom_grp_pad_mux,
3154		−};
3155		−
3156		−static struct atlas7_pad_mux lvds_analog_grp_pad_mux[] = {
3157		− MUX(1, 149, 8, N, N, N, N),
3158		− MUX(1, 150, 8, N, N, N, N),
3159		− MUX(1, 151, 8, N, N, N, N),
3160		− MUX(1, 152, 8, N, N, N, N),
3161		− MUX(1, 153, 8, N, N, N, N),
3162		− MUX(1, 154, 8, N, N, N, N),
3163		− MUX(1, 155, 8, N, N, N, N),
3164		− MUX(1, 156, 8, N, N, N, N),
3165		− MUX(1, 157, 8, N, N, N, N),
3166		− MUX(1, 158, 8, N, N, N, N),
3167		−};
3168		−
3169		−static struct atlas7_grp_mux lvds_analog_grp_mux = {
3170		− .pad_mux_count = ARRAY_SIZE(lvds_analog_grp_pad_mux),
3171		− .pad_mux_list = lvds_analog_grp_pad_mux,
3172		−};
3173		−
3174		−static struct atlas7_pad_mux nd_df_basic_grp_pad_mux[] = {
3175		− MUX(1, 44, 1, N, N, N, N),
3176		− MUX(1, 43, 1, N, N, N, N),
3177		− MUX(1, 42, 1, N, N, N, N),
3178		− MUX(1, 41, 1, N, N, N, N),
3179		− MUX(1, 40, 1, N, N, N, N),
3180		− MUX(1, 39, 1, N, N, N, N),
3181		− MUX(1, 38, 1, N, N, N, N),
3182		− MUX(1, 37, 1, N, N, N, N),
3183		− MUX(1, 47, 1, N, N, N, N),
3184		− MUX(1, 46, 1, N, N, N, N),
3185		− MUX(1, 52, 1, N, N, N, N),
3186		− MUX(1, 45, 1, N, N, N, N),
3187		− MUX(1, 49, 1, N, N, N, N),
3188		− MUX(1, 50, 1, N, N, N, N),
3189		− MUX(1, 48, 1, N, N, N, N),
3190		−};
3191		−
3192		−static struct atlas7_grp_mux nd_df_basic_grp_mux = {
3193		− .pad_mux_count = ARRAY_SIZE(nd_df_basic_grp_pad_mux),
3194		− .pad_mux_list = nd_df_basic_grp_pad_mux,
3195		−};
3196		−
3197		−static struct atlas7_pad_mux nd_df_wp_grp_pad_mux[] = {
3198		− MUX(1, 124, 4, N, N, N, N),
3199		−};
3200		−
3201		−static struct atlas7_grp_mux nd_df_wp_grp_mux = {
3202		− .pad_mux_count = ARRAY_SIZE(nd_df_wp_grp_pad_mux),
3203		− .pad_mux_list = nd_df_wp_grp_pad_mux,
3204		−};
3205		−
3206		−static struct atlas7_pad_mux nd_df_cs_grp_pad_mux[] = {
3207		− MUX(1, 51, 1, N, N, N, N),
3208		−};
3209		−
3210		−static struct atlas7_grp_mux nd_df_cs_grp_mux = {
3211		− .pad_mux_count = ARRAY_SIZE(nd_df_cs_grp_pad_mux),
3212		− .pad_mux_list = nd_df_cs_grp_pad_mux,
3213		−};
3214		−
3215		−static struct atlas7_pad_mux ps_grp_pad_mux[] = {
3216		− MUX(1, 120, 2, N, N, N, N),
3217		− MUX(1, 119, 2, N, N, N, N),
3218		− MUX(1, 121, 5, N, N, N, N),
3219		−};
3220		−
3221		−static struct atlas7_grp_mux ps_grp_mux = {
3222		− .pad_mux_count = ARRAY_SIZE(ps_grp_pad_mux),
3223		− .pad_mux_list = ps_grp_pad_mux,
3224		−};
3225		−
3226		−static struct atlas7_pad_mux ps_no_dir_grp_pad_mux[] = {
3227		− MUX(1, 119, 2, N, N, N, N),
3228		−};
3229		−
3230		−static struct atlas7_grp_mux ps_no_dir_grp_mux = {
3231		− .pad_mux_count = ARRAY_SIZE(ps_no_dir_grp_pad_mux),
3232		− .pad_mux_list = ps_no_dir_grp_pad_mux,
3233		−};
3234		−
3235		−static struct atlas7_pad_mux pwc_core_on_grp_pad_mux[] = {
3236		− MUX(0, 8, 1, N, N, N, N),
3237		−};
3238		−
3239		−static struct atlas7_grp_mux pwc_core_on_grp_mux = {
3240		− .pad_mux_count = ARRAY_SIZE(pwc_core_on_grp_pad_mux),
3241		− .pad_mux_list = pwc_core_on_grp_pad_mux,
3242		−};
3243		−
3244		−static struct atlas7_pad_mux pwc_ext_on_grp_pad_mux[] = {
3245		− MUX(0, 6, 1, N, N, N, N),
3246		−};
3247		−
3248		−static struct atlas7_grp_mux pwc_ext_on_grp_mux = {
3249		− .pad_mux_count = ARRAY_SIZE(pwc_ext_on_grp_pad_mux),
3250		− .pad_mux_list = pwc_ext_on_grp_pad_mux,
3251		−};
3252		−
3253		−static struct atlas7_pad_mux pwc_gpio3_clk_grp_pad_mux[] = {
3254		− MUX(0, 3, 4, N, N, N, N),
3255		−};
3256		−
3257		−static struct atlas7_grp_mux pwc_gpio3_clk_grp_mux = {
3258		− .pad_mux_count = ARRAY_SIZE(pwc_gpio3_clk_grp_pad_mux),
3259		− .pad_mux_list = pwc_gpio3_clk_grp_pad_mux,
3260		−};
3261		−
3262		−static struct atlas7_pad_mux pwc_io_on_grp_pad_mux[] = {
3263		− MUX(0, 9, 1, N, N, N, N),
3264		−};
3265		−
3266		−static struct atlas7_grp_mux pwc_io_on_grp_mux = {
3267		− .pad_mux_count = ARRAY_SIZE(pwc_io_on_grp_pad_mux),
3268		− .pad_mux_list = pwc_io_on_grp_pad_mux,
3269		−};
3270		−
3271		−static struct atlas7_pad_mux pwc_lowbatt_b_grp0_pad_mux[] = {
3272		− MUX(0, 4, 1, 0xa08, 4, 0xa88, 4),
3273		−};
3274		−
3275		−static struct atlas7_grp_mux pwc_lowbatt_b_grp0_mux = {
3276		− .pad_mux_count = ARRAY_SIZE(pwc_lowbatt_b_grp0_pad_mux),
3277		− .pad_mux_list = pwc_lowbatt_b_grp0_pad_mux,
3278		−};
3279		−
3280		−static struct atlas7_pad_mux pwc_mem_on_grp_pad_mux[] = {
3281		− MUX(0, 7, 1, N, N, N, N),
3282		−};
3283		−
3284		−static struct atlas7_grp_mux pwc_mem_on_grp_mux = {
3285		− .pad_mux_count = ARRAY_SIZE(pwc_mem_on_grp_pad_mux),
3286		− .pad_mux_list = pwc_mem_on_grp_pad_mux,
3287		−};
3288		−
3289		−static struct atlas7_pad_mux pwc_on_key_b_grp0_pad_mux[] = {
3290		− MUX(0, 5, 1, 0xa08, 5, 0xa88, 5),
3291		−};
3292		−
3293		−static struct atlas7_grp_mux pwc_on_key_b_grp0_mux = {
3294		− .pad_mux_count = ARRAY_SIZE(pwc_on_key_b_grp0_pad_mux),
3295		− .pad_mux_list = pwc_on_key_b_grp0_pad_mux,
3296		−};
3297		−
3298		−static struct atlas7_pad_mux pwc_wakeup_src0_grp_pad_mux[] = {
3299		− MUX(0, 0, 1, N, N, N, N),
3300		−};
3301		−
3302		−static struct atlas7_grp_mux pwc_wakeup_src0_grp_mux = {
3303		− .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src0_grp_pad_mux),
3304		− .pad_mux_list = pwc_wakeup_src0_grp_pad_mux,
3305		−};
3306		−
3307		−static struct atlas7_pad_mux pwc_wakeup_src1_grp_pad_mux[] = {
3308		− MUX(0, 1, 1, N, N, N, N),
3309		−};
3310		−
3311		−static struct atlas7_grp_mux pwc_wakeup_src1_grp_mux = {
3312		− .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src1_grp_pad_mux),
3313		− .pad_mux_list = pwc_wakeup_src1_grp_pad_mux,
3314		−};
3315		−
3316		−static struct atlas7_pad_mux pwc_wakeup_src2_grp_pad_mux[] = {
3317		− MUX(0, 2, 1, N, N, N, N),
3318		−};
3319		−
3320		−static struct atlas7_grp_mux pwc_wakeup_src2_grp_mux = {
3321		− .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src2_grp_pad_mux),
3322		− .pad_mux_list = pwc_wakeup_src2_grp_pad_mux,
3323		−};
3324		−
3325		−static struct atlas7_pad_mux pwc_wakeup_src3_grp_pad_mux[] = {
3326		− MUX(0, 3, 1, N, N, N, N),
3327		−};
3328		−
3329		−static struct atlas7_grp_mux pwc_wakeup_src3_grp_mux = {
3330		− .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src3_grp_pad_mux),
3331		− .pad_mux_list = pwc_wakeup_src3_grp_pad_mux,
3332		−};
3333		−
3334		−static struct atlas7_pad_mux pw_cko0_grp0_pad_mux[] = {
3335		− MUX(1, 123, 3, N, N, N, N),
3336		−};
3337		−
3338		−static struct atlas7_grp_mux pw_cko0_grp0_mux = {
3339		− .pad_mux_count = ARRAY_SIZE(pw_cko0_grp0_pad_mux),
3340		− .pad_mux_list = pw_cko0_grp0_pad_mux,
3341		−};
3342		−
3343		−static struct atlas7_pad_mux pw_cko0_grp1_pad_mux[] = {
3344		− MUX(1, 101, 4, N, N, N, N),
3345		−};
3346		−
3347		−static struct atlas7_grp_mux pw_cko0_grp1_mux = {
3348		− .pad_mux_count = ARRAY_SIZE(pw_cko0_grp1_pad_mux),
3349		− .pad_mux_list = pw_cko0_grp1_pad_mux,
3350		−};
3351		−
3352		−static struct atlas7_pad_mux pw_cko0_grp2_pad_mux[] = {
3353		− MUX(1, 82, 2, N, N, N, N),
3354		−};
3355		−
3356		−static struct atlas7_grp_mux pw_cko0_grp2_mux = {
3357		− .pad_mux_count = ARRAY_SIZE(pw_cko0_grp2_pad_mux),
3358		− .pad_mux_list = pw_cko0_grp2_pad_mux,
3359		−};
3360		−
3361		−static struct atlas7_pad_mux pw_cko0_grp3_pad_mux[] = {
3362		− MUX(1, 162, 5, N, N, N, N),
3363		−};
3364		−
3365		−static struct atlas7_grp_mux pw_cko0_grp3_mux = {
3366		− .pad_mux_count = ARRAY_SIZE(pw_cko0_grp3_pad_mux),
3367		− .pad_mux_list = pw_cko0_grp3_pad_mux,
3368		−};
3369		−
3370		−static struct atlas7_pad_mux pw_cko1_grp0_pad_mux[] = {
3371		− MUX(1, 124, 3, N, N, N, N),
3372		−};
3373		−
3374		−static struct atlas7_grp_mux pw_cko1_grp0_mux = {
3375		− .pad_mux_count = ARRAY_SIZE(pw_cko1_grp0_pad_mux),
3376		− .pad_mux_list = pw_cko1_grp0_pad_mux,
3377		−};
3378		−
3379		−static struct atlas7_pad_mux pw_cko1_grp1_pad_mux[] = {
3380		− MUX(1, 110, 4, N, N, N, N),
3381		−};
3382		−
3383		−static struct atlas7_grp_mux pw_cko1_grp1_mux = {
3384		− .pad_mux_count = ARRAY_SIZE(pw_cko1_grp1_pad_mux),
3385		− .pad_mux_list = pw_cko1_grp1_pad_mux,
3386		−};
3387		−
3388		−static struct atlas7_pad_mux pw_cko1_grp2_pad_mux[] = {
3389		− MUX(1, 163, 5, N, N, N, N),
3390		−};
3391		−
3392		−static struct atlas7_grp_mux pw_cko1_grp2_mux = {
3393		− .pad_mux_count = ARRAY_SIZE(pw_cko1_grp2_pad_mux),
3394		− .pad_mux_list = pw_cko1_grp2_pad_mux,
3395		−};
3396		−
3397		−static struct atlas7_pad_mux pw_i2s01_clk_grp0_pad_mux[] = {
3398		− MUX(1, 125, 3, N, N, N, N),
3399		−};
3400		−
3401		−static struct atlas7_grp_mux pw_i2s01_clk_grp0_mux = {
3402		− .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp0_pad_mux),
3403		− .pad_mux_list = pw_i2s01_clk_grp0_pad_mux,
3404		−};
3405		−
3406		−static struct atlas7_pad_mux pw_i2s01_clk_grp1_pad_mux[] = {
3407		− MUX(1, 117, 3, N, N, N, N),
3408		−};
3409		−
3410		−static struct atlas7_grp_mux pw_i2s01_clk_grp1_mux = {
3411		− .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp1_pad_mux),
3412		− .pad_mux_list = pw_i2s01_clk_grp1_pad_mux,
3413		−};
3414		−
3415		−static struct atlas7_pad_mux pw_i2s01_clk_grp2_pad_mux[] = {
3416		− MUX(1, 132, 2, N, N, N, N),
3417		−};
3418		−
3419		−static struct atlas7_grp_mux pw_i2s01_clk_grp2_mux = {
3420		− .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp2_pad_mux),
3421		− .pad_mux_list = pw_i2s01_clk_grp2_pad_mux,
3422		−};
3423		−
3424		−static struct atlas7_pad_mux pw_pwm0_grp0_pad_mux[] = {
3425		− MUX(1, 119, 3, N, N, N, N),
3426		−};
3427		−
3428		−static struct atlas7_grp_mux pw_pwm0_grp0_mux = {
3429		− .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp0_pad_mux),
3430		− .pad_mux_list = pw_pwm0_grp0_pad_mux,
3431		−};
3432		−
3433		−static struct atlas7_pad_mux pw_pwm0_grp1_pad_mux[] = {
3434		− MUX(1, 159, 5, N, N, N, N),
3435		−};
3436		−
3437		−static struct atlas7_grp_mux pw_pwm0_grp1_mux = {
3438		− .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp1_pad_mux),
3439		− .pad_mux_list = pw_pwm0_grp1_pad_mux,
3440		−};
3441		−
3442		−static struct atlas7_pad_mux pw_pwm1_grp0_pad_mux[] = {
3443		− MUX(1, 120, 3, N, N, N, N),
3444		−};
3445		−
3446		−static struct atlas7_grp_mux pw_pwm1_grp0_mux = {
3447		− .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp0_pad_mux),
3448		− .pad_mux_list = pw_pwm1_grp0_pad_mux,
3449		−};
3450		−
3451		−static struct atlas7_pad_mux pw_pwm1_grp1_pad_mux[] = {
3452		− MUX(1, 160, 5, N, N, N, N),
3453		−};
3454		−
3455		−static struct atlas7_grp_mux pw_pwm1_grp1_mux = {
3456		− .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp1_pad_mux),
3457		− .pad_mux_list = pw_pwm1_grp1_pad_mux,
3458		−};
3459		−
3460		−static struct atlas7_pad_mux pw_pwm1_grp2_pad_mux[] = {
3461		− MUX(1, 131, 2, N, N, N, N),
3462		−};
3463		−
3464		−static struct atlas7_grp_mux pw_pwm1_grp2_mux = {
3465		− .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp2_pad_mux),
3466		− .pad_mux_list = pw_pwm1_grp2_pad_mux,
3467		−};
3468		−
3469		−static struct atlas7_pad_mux pw_pwm2_grp0_pad_mux[] = {
3470		− MUX(1, 121, 3, N, N, N, N),
3471		−};
3472		−
3473		−static struct atlas7_grp_mux pw_pwm2_grp0_mux = {
3474		− .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp0_pad_mux),
3475		− .pad_mux_list = pw_pwm2_grp0_pad_mux,
3476		−};
3477		−
3478		−static struct atlas7_pad_mux pw_pwm2_grp1_pad_mux[] = {
3479		− MUX(1, 98, 3, N, N, N, N),
3480		−};
3481		−
3482		−static struct atlas7_grp_mux pw_pwm2_grp1_mux = {
3483		− .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp1_pad_mux),
3484		− .pad_mux_list = pw_pwm2_grp1_pad_mux,
3485		−};
3486		−
3487		−static struct atlas7_pad_mux pw_pwm2_grp2_pad_mux[] = {
3488		− MUX(1, 161, 5, N, N, N, N),
3489		−};
3490		−
3491		−static struct atlas7_grp_mux pw_pwm2_grp2_mux = {
3492		− .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp2_pad_mux),
3493		− .pad_mux_list = pw_pwm2_grp2_pad_mux,
3494		−};
3495		−
3496		−static struct atlas7_pad_mux pw_pwm3_grp0_pad_mux[] = {
3497		− MUX(1, 122, 3, N, N, N, N),
3498		−};
3499		−
3500		−static struct atlas7_grp_mux pw_pwm3_grp0_mux = {
3501		− .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp0_pad_mux),
3502		− .pad_mux_list = pw_pwm3_grp0_pad_mux,
3503		−};
3504		−
3505		−static struct atlas7_pad_mux pw_pwm3_grp1_pad_mux[] = {
3506		− MUX(1, 73, 4, N, N, N, N),
3507		−};
3508		−
3509		−static struct atlas7_grp_mux pw_pwm3_grp1_mux = {
3510		− .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp1_pad_mux),
3511		− .pad_mux_list = pw_pwm3_grp1_pad_mux,
3512		−};
3513		−
3514		−static struct atlas7_pad_mux pw_pwm_cpu_vol_grp0_pad_mux[] = {
3515		− MUX(1, 121, 3, N, N, N, N),
3516		−};
3517		−
3518		−static struct atlas7_grp_mux pw_pwm_cpu_vol_grp0_mux = {
3519		− .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp0_pad_mux),
3520		− .pad_mux_list = pw_pwm_cpu_vol_grp0_pad_mux,
3521		−};
3522		−
3523		−static struct atlas7_pad_mux pw_pwm_cpu_vol_grp1_pad_mux[] = {
3524		− MUX(1, 98, 3, N, N, N, N),
3525		−};
3526		−
3527		−static struct atlas7_grp_mux pw_pwm_cpu_vol_grp1_mux = {
3528		− .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp1_pad_mux),
3529		− .pad_mux_list = pw_pwm_cpu_vol_grp1_pad_mux,
3530		−};
3531		−
3532		−static struct atlas7_pad_mux pw_pwm_cpu_vol_grp2_pad_mux[] = {
3533		− MUX(1, 161, 5, N, N, N, N),
3534		−};
3535		−
3536		−static struct atlas7_grp_mux pw_pwm_cpu_vol_grp2_mux = {
3537		− .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp2_pad_mux),
3538		− .pad_mux_list = pw_pwm_cpu_vol_grp2_pad_mux,
3539		−};
3540		−
3541		−static struct atlas7_pad_mux pw_backlight_grp0_pad_mux[] = {
3542		− MUX(1, 122, 3, N, N, N, N),
3543		−};
3544		−
3545		−static struct atlas7_grp_mux pw_backlight_grp0_mux = {
3546		− .pad_mux_count = ARRAY_SIZE(pw_backlight_grp0_pad_mux),
3547		− .pad_mux_list = pw_backlight_grp0_pad_mux,
3548		−};
3549		−
3550		−static struct atlas7_pad_mux pw_backlight_grp1_pad_mux[] = {
3551		− MUX(1, 73, 4, N, N, N, N),
3552		−};
3553		−
3554		−static struct atlas7_grp_mux pw_backlight_grp1_mux = {
3555		− .pad_mux_count = ARRAY_SIZE(pw_backlight_grp1_pad_mux),
3556		− .pad_mux_list = pw_backlight_grp1_pad_mux,
3557		−};
3558		−
3559		−static struct atlas7_pad_mux rg_eth_mac_grp_pad_mux[] = {
3560		− MUX(1, 108, 1, N, N, N, N),
3561		− MUX(1, 103, 1, N, N, N, N),
3562		− MUX(1, 104, 1, N, N, N, N),
3563		− MUX(1, 105, 1, N, N, N, N),
3564		− MUX(1, 106, 1, N, N, N, N),
3565		− MUX(1, 107, 1, N, N, N, N),
3566		− MUX(1, 102, 1, N, N, N, N),
3567		− MUX(1, 97, 1, N, N, N, N),
3568		− MUX(1, 98, 1, N, N, N, N),
3569		− MUX(1, 99, 1, N, N, N, N),
3570		− MUX(1, 100, 1, N, N, N, N),
3571		− MUX(1, 101, 1, N, N, N, N),
3572		−};
3573		−
3574		−static struct atlas7_grp_mux rg_eth_mac_grp_mux = {
3575		− .pad_mux_count = ARRAY_SIZE(rg_eth_mac_grp_pad_mux),
3576		− .pad_mux_list = rg_eth_mac_grp_pad_mux,
3577		−};
3578		−
3579		−static struct atlas7_pad_mux rg_gmac_phy_intr_n_grp_pad_mux[] = {
3580		− MUX(1, 111, 1, 0xa08, 13, 0xa88, 13),
3581		−};
3582		−
3583		−static struct atlas7_grp_mux rg_gmac_phy_intr_n_grp_mux = {
3584		− .pad_mux_count = ARRAY_SIZE(rg_gmac_phy_intr_n_grp_pad_mux),
3585		− .pad_mux_list = rg_gmac_phy_intr_n_grp_pad_mux,
3586		−};
3587		−
3588		−static struct atlas7_pad_mux rg_rgmii_mac_grp_pad_mux[] = {
3589		− MUX(1, 109, 1, N, N, N, N),
3590		− MUX(1, 110, 1, N, N, N, N),
3591		−};
3592		−
3593		−static struct atlas7_grp_mux rg_rgmii_mac_grp_mux = {
3594		− .pad_mux_count = ARRAY_SIZE(rg_rgmii_mac_grp_pad_mux),
3595		− .pad_mux_list = rg_rgmii_mac_grp_pad_mux,
3596		−};
3597		−
3598		−static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp0_pad_mux[] = {
3599		− MUX(1, 111, 5, N, N, N, N),
3600		−};
3601		−
3602		−static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp0_mux = {
3603		− .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp0_pad_mux),
3604		− .pad_mux_list = rg_rgmii_phy_ref_clk_grp0_pad_mux,
3605		−};
3606		−
3607		−static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp1_pad_mux[] = {
3608		− MUX(1, 53, 4, N, N, N, N),
3609		−};
3610		−
3611		−static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp1_mux = {
3612		− .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp1_pad_mux),
3613		− .pad_mux_list = rg_rgmii_phy_ref_clk_grp1_pad_mux,
3614		−};
3615		−
3616		−static struct atlas7_pad_mux sd0_grp_pad_mux[] = {
3617		− MUX(1, 46, 2, N, N, N, N),
3618		− MUX(1, 47, 2, N, N, N, N),
3619		− MUX(1, 44, 2, N, N, N, N),
3620		− MUX(1, 43, 2, N, N, N, N),
3621		− MUX(1, 42, 2, N, N, N, N),
3622		− MUX(1, 41, 2, N, N, N, N),
3623		− MUX(1, 40, 2, N, N, N, N),
3624		− MUX(1, 39, 2, N, N, N, N),
3625		− MUX(1, 38, 2, N, N, N, N),
3626		− MUX(1, 37, 2, N, N, N, N),
3627		−};
3628		−
3629		−static struct atlas7_grp_mux sd0_grp_mux = {
3630		− .pad_mux_count = ARRAY_SIZE(sd0_grp_pad_mux),
3631		− .pad_mux_list = sd0_grp_pad_mux,
3632		−};
3633		−
3634		−static struct atlas7_pad_mux sd0_4bit_grp_pad_mux[] = {
3635		− MUX(1, 46, 2, N, N, N, N),
3636		− MUX(1, 47, 2, N, N, N, N),
3637		− MUX(1, 44, 2, N, N, N, N),
3638		− MUX(1, 43, 2, N, N, N, N),
3639		− MUX(1, 42, 2, N, N, N, N),
3640		− MUX(1, 41, 2, N, N, N, N),
3641		−};
3642		−
3643		−static struct atlas7_grp_mux sd0_4bit_grp_mux = {
3644		− .pad_mux_count = ARRAY_SIZE(sd0_4bit_grp_pad_mux),
3645		− .pad_mux_list = sd0_4bit_grp_pad_mux,
3646		−};
3647		−
3648		−static struct atlas7_pad_mux sd1_grp_pad_mux[] = {
3649		− MUX(1, 48, 3, N, N, N, N),
3650		− MUX(1, 49, 3, N, N, N, N),
3651		− MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
3652		− MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
3653		− MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
3654		− MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
3655		− MUX(1, 40, 3, N, N, N, N),
3656		− MUX(1, 39, 3, N, N, N, N),
3657		− MUX(1, 38, 3, N, N, N, N),
3658		− MUX(1, 37, 3, N, N, N, N),
3659		−};
3660		−
3661		−static struct atlas7_grp_mux sd1_grp_mux = {
3662		− .pad_mux_count = ARRAY_SIZE(sd1_grp_pad_mux),
3663		− .pad_mux_list = sd1_grp_pad_mux,
3664		−};
3665		−
3666		−static struct atlas7_pad_mux sd1_4bit_grp0_pad_mux[] = {
3667		− MUX(1, 48, 3, N, N, N, N),
3668		− MUX(1, 49, 3, N, N, N, N),
3669		− MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
3670		− MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
3671		− MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
3672		− MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
3673		−};
3674		−
3675		−static struct atlas7_grp_mux sd1_4bit_grp0_mux = {
3676		− .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp0_pad_mux),
3677		− .pad_mux_list = sd1_4bit_grp0_pad_mux,
3678		−};
3679		−
3680		−static struct atlas7_pad_mux sd1_4bit_grp1_pad_mux[] = {
3681		− MUX(1, 48, 3, N, N, N, N),
3682		− MUX(1, 49, 3, N, N, N, N),
3683		− MUX(1, 40, 4, 0xa00, 0, 0xa80, 0),
3684		− MUX(1, 39, 4, 0xa00, 1, 0xa80, 1),
3685		− MUX(1, 38, 4, 0xa00, 2, 0xa80, 2),
3686		− MUX(1, 37, 4, 0xa00, 3, 0xa80, 3),
3687		−};
3688		−
3689		−static struct atlas7_grp_mux sd1_4bit_grp1_mux = {
3690		− .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp1_pad_mux),
3691		− .pad_mux_list = sd1_4bit_grp1_pad_mux,
3692		−};
3693		−
3694		−static struct atlas7_pad_mux sd2_basic_grp_pad_mux[] = {
3695		− MUX(1, 31, 1, N, N, N, N),
3696		− MUX(1, 32, 1, N, N, N, N),
3697		− MUX(1, 33, 1, N, N, N, N),
3698		− MUX(1, 34, 1, N, N, N, N),
3699		− MUX(1, 35, 1, N, N, N, N),
3700		− MUX(1, 36, 1, N, N, N, N),
3701		−};
3702		−
3703		−static struct atlas7_grp_mux sd2_basic_grp_mux = {
3704		− .pad_mux_count = ARRAY_SIZE(sd2_basic_grp_pad_mux),
3705		− .pad_mux_list = sd2_basic_grp_pad_mux,
3706		−};
3707		−
3708		−static struct atlas7_pad_mux sd2_cdb_grp0_pad_mux[] = {
3709		− MUX(1, 124, 2, 0xa08, 7, 0xa88, 7),
3710		−};
3711		−
3712		−static struct atlas7_grp_mux sd2_cdb_grp0_mux = {
3713		− .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp0_pad_mux),
3714		− .pad_mux_list = sd2_cdb_grp0_pad_mux,
3715		−};
3716		−
3717		−static struct atlas7_pad_mux sd2_cdb_grp1_pad_mux[] = {
3718		− MUX(1, 161, 6, 0xa08, 7, 0xa88, 7),
3719		−};
3720		−
3721		−static struct atlas7_grp_mux sd2_cdb_grp1_mux = {
3722		− .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp1_pad_mux),
3723		− .pad_mux_list = sd2_cdb_grp1_pad_mux,
3724		−};
3725		−
3726		−static struct atlas7_pad_mux sd2_wpb_grp0_pad_mux[] = {
3727		− MUX(1, 123, 2, 0xa10, 6, 0xa90, 6),
3728		−};
3729		−
3730		−static struct atlas7_grp_mux sd2_wpb_grp0_mux = {
3731		− .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp0_pad_mux),
3732		− .pad_mux_list = sd2_wpb_grp0_pad_mux,
3733		−};
3734		−
3735		−static struct atlas7_pad_mux sd2_wpb_grp1_pad_mux[] = {
3736		− MUX(1, 163, 7, 0xa10, 6, 0xa90, 6),
3737		−};
3738		−
3739		−static struct atlas7_grp_mux sd2_wpb_grp1_mux = {
3740		− .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp1_pad_mux),
3741		− .pad_mux_list = sd2_wpb_grp1_pad_mux,
3742		−};
3743		−
3744		−static struct atlas7_pad_mux sd3_9_grp_pad_mux[] = {
3745		− MUX(1, 85, 1, N, N, N, N),
3746		− MUX(1, 86, 1, N, N, N, N),
3747		− MUX(1, 87, 1, N, N, N, N),
3748		− MUX(1, 88, 1, N, N, N, N),
3749		− MUX(1, 89, 1, N, N, N, N),
3750		− MUX(1, 90, 1, N, N, N, N),
3751		−};
3752		−
3753		−static struct atlas7_grp_mux sd3_9_grp_mux = {
3754		− .pad_mux_count = ARRAY_SIZE(sd3_9_grp_pad_mux),
3755		− .pad_mux_list = sd3_9_grp_pad_mux,
3756		−};
3757		−
3758		−static struct atlas7_pad_mux sd5_grp_pad_mux[] = {
3759		− MUX(1, 91, 1, N, N, N, N),
3760		− MUX(1, 92, 1, N, N, N, N),
3761		− MUX(1, 93, 1, N, N, N, N),
3762		− MUX(1, 94, 1, N, N, N, N),
3763		− MUX(1, 95, 1, N, N, N, N),
3764		− MUX(1, 96, 1, N, N, N, N),
3765		−};
3766		−
3767		−static struct atlas7_grp_mux sd5_grp_mux = {
3768		− .pad_mux_count = ARRAY_SIZE(sd5_grp_pad_mux),
3769		− .pad_mux_list = sd5_grp_pad_mux,
3770		−};
3771		−
3772		−static struct atlas7_pad_mux sd6_grp0_pad_mux[] = {
3773		− MUX(1, 79, 4, 0xa00, 27, 0xa80, 27),
3774		− MUX(1, 78, 4, 0xa00, 26, 0xa80, 26),
3775		− MUX(1, 74, 4, 0xa00, 28, 0xa80, 28),
3776		− MUX(1, 75, 4, 0xa00, 29, 0xa80, 29),
3777		− MUX(1, 76, 4, 0xa00, 30, 0xa80, 30),
3778		− MUX(1, 77, 4, 0xa00, 31, 0xa80, 31),
3779		−};
3780		−
3781		−static struct atlas7_grp_mux sd6_grp0_mux = {
3782		− .pad_mux_count = ARRAY_SIZE(sd6_grp0_pad_mux),
3783		− .pad_mux_list = sd6_grp0_pad_mux,
3784		−};
3785		−
3786		−static struct atlas7_pad_mux sd6_grp1_pad_mux[] = {
3787		− MUX(1, 101, 3, 0xa00, 27, 0xa80, 27),
3788		− MUX(1, 99, 3, 0xa00, 26, 0xa80, 26),
3789		− MUX(1, 100, 3, 0xa00, 28, 0xa80, 28),
3790		− MUX(1, 110, 3, 0xa00, 29, 0xa80, 29),
3791		− MUX(1, 109, 3, 0xa00, 30, 0xa80, 30),
3792		− MUX(1, 111, 3, 0xa00, 31, 0xa80, 31),
3793		−};
3794		−
3795		−static struct atlas7_grp_mux sd6_grp1_mux = {
3796		− .pad_mux_count = ARRAY_SIZE(sd6_grp1_pad_mux),
3797		− .pad_mux_list = sd6_grp1_pad_mux,
3798		−};
3799		−
3800		−static struct atlas7_pad_mux sp0_ext_ldo_on_grp_pad_mux[] = {
3801		− MUX(0, 4, 2, N, N, N, N),
3802		−};
3803		−
3804		−static struct atlas7_grp_mux sp0_ext_ldo_on_grp_mux = {
3805		− .pad_mux_count = ARRAY_SIZE(sp0_ext_ldo_on_grp_pad_mux),
3806		− .pad_mux_list = sp0_ext_ldo_on_grp_pad_mux,
3807		−};
3808		−
3809		−static struct atlas7_pad_mux sp0_qspi_grp_pad_mux[] = {
3810		− MUX(0, 12, 1, N, N, N, N),
3811		− MUX(0, 13, 1, N, N, N, N),
3812		− MUX(0, 14, 1, N, N, N, N),
3813		− MUX(0, 15, 1, N, N, N, N),
3814		− MUX(0, 16, 1, N, N, N, N),
3815		− MUX(0, 17, 1, N, N, N, N),
3816		−};
3817		−
3818		−static struct atlas7_grp_mux sp0_qspi_grp_mux = {
3819		− .pad_mux_count = ARRAY_SIZE(sp0_qspi_grp_pad_mux),
3820		− .pad_mux_list = sp0_qspi_grp_pad_mux,
3821		−};
3822		−
3823		−static struct atlas7_pad_mux sp1_spi_grp_pad_mux[] = {
3824		− MUX(1, 19, 1, N, N, N, N),
3825		− MUX(1, 20, 1, N, N, N, N),
3826		− MUX(1, 21, 1, N, N, N, N),
3827		− MUX(1, 18, 1, N, N, N, N),
3828		−};
3829		−
3830		−static struct atlas7_grp_mux sp1_spi_grp_mux = {
3831		− .pad_mux_count = ARRAY_SIZE(sp1_spi_grp_pad_mux),
3832		− .pad_mux_list = sp1_spi_grp_pad_mux,
3833		−};
3834		−
3835		−static struct atlas7_pad_mux tpiu_trace_grp_pad_mux[] = {
3836		− MUX(1, 53, 5, N, N, N, N),
3837		− MUX(1, 56, 5, N, N, N, N),
3838		− MUX(1, 57, 5, N, N, N, N),
3839		− MUX(1, 58, 5, N, N, N, N),
3840		− MUX(1, 59, 5, N, N, N, N),
3841		− MUX(1, 60, 5, N, N, N, N),
3842		− MUX(1, 61, 5, N, N, N, N),
3843		− MUX(1, 62, 5, N, N, N, N),
3844		− MUX(1, 63, 5, N, N, N, N),
3845		− MUX(1, 64, 5, N, N, N, N),
3846		− MUX(1, 65, 5, N, N, N, N),
3847		− MUX(1, 66, 5, N, N, N, N),
3848		− MUX(1, 67, 5, N, N, N, N),
3849		− MUX(1, 68, 5, N, N, N, N),
3850		− MUX(1, 69, 5, N, N, N, N),
3851		− MUX(1, 70, 5, N, N, N, N),
3852		− MUX(1, 71, 5, N, N, N, N),
3853		− MUX(1, 72, 5, N, N, N, N),
3854		−};
3855		−
3856		−static struct atlas7_grp_mux tpiu_trace_grp_mux = {
3857		− .pad_mux_count = ARRAY_SIZE(tpiu_trace_grp_pad_mux),
3858		− .pad_mux_list = tpiu_trace_grp_pad_mux,
3859		−};
3860		−
3861		−static struct atlas7_pad_mux uart0_grp_pad_mux[] = {
3862		− MUX(1, 121, 4, N, N, N, N),
3863		− MUX(1, 120, 4, N, N, N, N),
3864		− MUX(1, 134, 1, N, N, N, N),
3865		− MUX(1, 133, 1, N, N, N, N),
3866		−};
3867		−
3868		−static struct atlas7_grp_mux uart0_grp_mux = {
3869		− .pad_mux_count = ARRAY_SIZE(uart0_grp_pad_mux),
3870		− .pad_mux_list = uart0_grp_pad_mux,
3871		−};
3872		−
3873		−static struct atlas7_pad_mux uart0_nopause_grp_pad_mux[] = {
3874		− MUX(1, 134, 1, N, N, N, N),
3875		− MUX(1, 133, 1, N, N, N, N),
3876		−};
3877		−
3878		−static struct atlas7_grp_mux uart0_nopause_grp_mux = {
3879		− .pad_mux_count = ARRAY_SIZE(uart0_nopause_grp_pad_mux),
3880		− .pad_mux_list = uart0_nopause_grp_pad_mux,
3881		−};
3882		−
3883		−static struct atlas7_pad_mux uart1_grp_pad_mux[] = {
3884		− MUX(1, 136, 1, N, N, N, N),
3885		− MUX(1, 135, 1, N, N, N, N),
3886		−};
3887		−
3888		−static struct atlas7_grp_mux uart1_grp_mux = {
3889		− .pad_mux_count = ARRAY_SIZE(uart1_grp_pad_mux),
3890		− .pad_mux_list = uart1_grp_pad_mux,
3891		−};
3892		−
3893		−static struct atlas7_pad_mux uart2_cts_grp0_pad_mux[] = {
3894		− MUX(1, 132, 3, 0xa10, 2, 0xa90, 2),
3895		−};
3896		−
3897		−static struct atlas7_grp_mux uart2_cts_grp0_mux = {
3898		− .pad_mux_count = ARRAY_SIZE(uart2_cts_grp0_pad_mux),
3899		− .pad_mux_list = uart2_cts_grp0_pad_mux,
3900		−};
3901		−
3902		−static struct atlas7_pad_mux uart2_cts_grp1_pad_mux[] = {
3903		− MUX(1, 162, 2, 0xa10, 2, 0xa90, 2),
3904		−};
3905		−
3906		−static struct atlas7_grp_mux uart2_cts_grp1_mux = {
3907		− .pad_mux_count = ARRAY_SIZE(uart2_cts_grp1_pad_mux),
3908		− .pad_mux_list = uart2_cts_grp1_pad_mux,
3909		−};
3910		−
3911		−static struct atlas7_pad_mux uart2_rts_grp0_pad_mux[] = {
3912		− MUX(1, 131, 3, N, N, N, N),
3913		−};
3914		−
3915		−static struct atlas7_grp_mux uart2_rts_grp0_mux = {
3916		− .pad_mux_count = ARRAY_SIZE(uart2_rts_grp0_pad_mux),
3917		− .pad_mux_list = uart2_rts_grp0_pad_mux,
3918		−};
3919		−
3920		−static struct atlas7_pad_mux uart2_rts_grp1_pad_mux[] = {
3921		− MUX(1, 161, 2, N, N, N, N),
3922		−};
3923		−
3924		−static struct atlas7_grp_mux uart2_rts_grp1_mux = {
3925		− .pad_mux_count = ARRAY_SIZE(uart2_rts_grp1_pad_mux),
3926		− .pad_mux_list = uart2_rts_grp1_pad_mux,
3927		−};
3928		−
3929		−static struct atlas7_pad_mux uart2_rxd_grp0_pad_mux[] = {
3930		− MUX(0, 11, 2, 0xa10, 5, 0xa90, 5),
3931		−};
3932		−
3933		−static struct atlas7_grp_mux uart2_rxd_grp0_mux = {
3934		− .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp0_pad_mux),
3935		− .pad_mux_list = uart2_rxd_grp0_pad_mux,
3936		−};
3937		−
3938		−static struct atlas7_pad_mux uart2_rxd_grp1_pad_mux[] = {
3939		− MUX(1, 160, 2, 0xa10, 5, 0xa90, 5),
3940		−};
3941		−
3942		−static struct atlas7_grp_mux uart2_rxd_grp1_mux = {
3943		− .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp1_pad_mux),
3944		− .pad_mux_list = uart2_rxd_grp1_pad_mux,
3945		−};
3946		−
3947		−static struct atlas7_pad_mux uart2_rxd_grp2_pad_mux[] = {
3948		− MUX(1, 130, 3, 0xa10, 5, 0xa90, 5),
3949		−};
3950		−
3951		−static struct atlas7_grp_mux uart2_rxd_grp2_mux = {
3952		− .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp2_pad_mux),
3953		− .pad_mux_list = uart2_rxd_grp2_pad_mux,
3954		−};
3955		−
3956		−static struct atlas7_pad_mux uart2_txd_grp0_pad_mux[] = {
3957		− MUX(0, 10, 2, N, N, N, N),
3958		−};
3959		−
3960		−static struct atlas7_grp_mux uart2_txd_grp0_mux = {
3961		− .pad_mux_count = ARRAY_SIZE(uart2_txd_grp0_pad_mux),
3962		− .pad_mux_list = uart2_txd_grp0_pad_mux,
3963		−};
3964		−
3965		−static struct atlas7_pad_mux uart2_txd_grp1_pad_mux[] = {
3966		− MUX(1, 159, 2, N, N, N, N),
3967		−};
3968		−
3969		−static struct atlas7_grp_mux uart2_txd_grp1_mux = {
3970		− .pad_mux_count = ARRAY_SIZE(uart2_txd_grp1_pad_mux),
3971		− .pad_mux_list = uart2_txd_grp1_pad_mux,
3972		−};
3973		−
3974		−static struct atlas7_pad_mux uart2_txd_grp2_pad_mux[] = {
3975		− MUX(1, 129, 3, N, N, N, N),
3976		−};
3977		−
3978		−static struct atlas7_grp_mux uart2_txd_grp2_mux = {
3979		− .pad_mux_count = ARRAY_SIZE(uart2_txd_grp2_pad_mux),
3980		− .pad_mux_list = uart2_txd_grp2_pad_mux,
3981		−};
3982		−
3983		−static struct atlas7_pad_mux uart3_cts_grp0_pad_mux[] = {
3984		− MUX(1, 125, 2, 0xa08, 0, 0xa88, 0),
3985		−};
3986		−
3987		−static struct atlas7_grp_mux uart3_cts_grp0_mux = {
3988		− .pad_mux_count = ARRAY_SIZE(uart3_cts_grp0_pad_mux),
3989		− .pad_mux_list = uart3_cts_grp0_pad_mux,
3990		−};
3991		−
3992		−static struct atlas7_pad_mux uart3_cts_grp1_pad_mux[] = {
3993		− MUX(1, 111, 4, 0xa08, 0, 0xa88, 0),
3994		−};
3995		−
3996		−static struct atlas7_grp_mux uart3_cts_grp1_mux = {
3997		− .pad_mux_count = ARRAY_SIZE(uart3_cts_grp1_pad_mux),
3998		− .pad_mux_list = uart3_cts_grp1_pad_mux,
3999		−};
4000		−
4001		−static struct atlas7_pad_mux uart3_cts_grp2_pad_mux[] = {
4002		− MUX(1, 140, 2, 0xa08, 0, 0xa88, 0),
4003		−};
4004		−
4005		−static struct atlas7_grp_mux uart3_cts_grp2_mux = {
4006		− .pad_mux_count = ARRAY_SIZE(uart3_cts_grp2_pad_mux),
4007		− .pad_mux_list = uart3_cts_grp2_pad_mux,
4008		−};
4009		−
4010		−static struct atlas7_pad_mux uart3_rts_grp0_pad_mux[] = {
4011		− MUX(1, 126, 2, N, N, N, N),
4012		−};
4013		−
4014		−static struct atlas7_grp_mux uart3_rts_grp0_mux = {
4015		− .pad_mux_count = ARRAY_SIZE(uart3_rts_grp0_pad_mux),
4016		− .pad_mux_list = uart3_rts_grp0_pad_mux,
4017		−};
4018		−
4019		−static struct atlas7_pad_mux uart3_rts_grp1_pad_mux[] = {
4020		− MUX(1, 109, 4, N, N, N, N),
4021		−};
4022		−
4023		−static struct atlas7_grp_mux uart3_rts_grp1_mux = {
4024		− .pad_mux_count = ARRAY_SIZE(uart3_rts_grp1_pad_mux),
4025		− .pad_mux_list = uart3_rts_grp1_pad_mux,
4026		−};
4027		−
4028		−static struct atlas7_pad_mux uart3_rts_grp2_pad_mux[] = {
4029		− MUX(1, 139, 2, N, N, N, N),
4030		−};
4031		−
4032		−static struct atlas7_grp_mux uart3_rts_grp2_mux = {
4033		− .pad_mux_count = ARRAY_SIZE(uart3_rts_grp2_pad_mux),
4034		− .pad_mux_list = uart3_rts_grp2_pad_mux,
4035		−};
4036		−
4037		−static struct atlas7_pad_mux uart3_rxd_grp0_pad_mux[] = {
4038		− MUX(1, 138, 1, 0xa00, 5, 0xa80, 5),
4039		−};
4040		−
4041		−static struct atlas7_grp_mux uart3_rxd_grp0_mux = {
4042		− .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp0_pad_mux),
4043		− .pad_mux_list = uart3_rxd_grp0_pad_mux,
4044		−};
4045		−
4046		−static struct atlas7_pad_mux uart3_rxd_grp1_pad_mux[] = {
4047		− MUX(1, 84, 2, 0xa00, 5, 0xa80, 5),
4048		−};
4049		−
4050		−static struct atlas7_grp_mux uart3_rxd_grp1_mux = {
4051		− .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp1_pad_mux),
4052		− .pad_mux_list = uart3_rxd_grp1_pad_mux,
4053		−};
4054		−
4055		−static struct atlas7_pad_mux uart3_rxd_grp2_pad_mux[] = {
4056		− MUX(1, 162, 3, 0xa00, 5, 0xa80, 5),
4057		−};
4058		−
4059		−static struct atlas7_grp_mux uart3_rxd_grp2_mux = {
4060		− .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp2_pad_mux),
4061		− .pad_mux_list = uart3_rxd_grp2_pad_mux,
4062		−};
4063		−
4064		−static struct atlas7_pad_mux uart3_txd_grp0_pad_mux[] = {
4065		− MUX(1, 137, 1, N, N, N, N),
4066		−};
4067		−
4068		−static struct atlas7_grp_mux uart3_txd_grp0_mux = {
4069		− .pad_mux_count = ARRAY_SIZE(uart3_txd_grp0_pad_mux),
4070		− .pad_mux_list = uart3_txd_grp0_pad_mux,
4071		−};
4072		−
4073		−static struct atlas7_pad_mux uart3_txd_grp1_pad_mux[] = {
4074		− MUX(1, 83, 2, N, N, N, N),
4075		−};
4076		−
4077		−static struct atlas7_grp_mux uart3_txd_grp1_mux = {
4078		− .pad_mux_count = ARRAY_SIZE(uart3_txd_grp1_pad_mux),
4079		− .pad_mux_list = uart3_txd_grp1_pad_mux,
4080		−};
4081		−
4082		−static struct atlas7_pad_mux uart3_txd_grp2_pad_mux[] = {
4083		− MUX(1, 161, 3, N, N, N, N),
4084		−};
4085		−
4086		−static struct atlas7_grp_mux uart3_txd_grp2_mux = {
4087		− .pad_mux_count = ARRAY_SIZE(uart3_txd_grp2_pad_mux),
4088		− .pad_mux_list = uart3_txd_grp2_pad_mux,
4089		−};
4090		−
4091		−static struct atlas7_pad_mux uart4_basic_grp_pad_mux[] = {
4092		− MUX(1, 140, 1, N, N, N, N),
4093		− MUX(1, 139, 1, N, N, N, N),
4094		−};
4095		−
4096		−static struct atlas7_grp_mux uart4_basic_grp_mux = {
4097		− .pad_mux_count = ARRAY_SIZE(uart4_basic_grp_pad_mux),
4098		− .pad_mux_list = uart4_basic_grp_pad_mux,
4099		−};
4100		−
4101		−static struct atlas7_pad_mux uart4_cts_grp0_pad_mux[] = {
4102		− MUX(1, 122, 4, 0xa08, 1, 0xa88, 1),
4103		−};
4104		−
4105		−static struct atlas7_grp_mux uart4_cts_grp0_mux = {
4106		− .pad_mux_count = ARRAY_SIZE(uart4_cts_grp0_pad_mux),
4107		− .pad_mux_list = uart4_cts_grp0_pad_mux,
4108		−};
4109		−
4110		−static struct atlas7_pad_mux uart4_cts_grp1_pad_mux[] = {
4111		− MUX(1, 100, 4, 0xa08, 1, 0xa88, 1),
4112		−};
4113		−
4114		−static struct atlas7_grp_mux uart4_cts_grp1_mux = {
4115		− .pad_mux_count = ARRAY_SIZE(uart4_cts_grp1_pad_mux),
4116		− .pad_mux_list = uart4_cts_grp1_pad_mux,
4117		−};
4118		−
4119		−static struct atlas7_pad_mux uart4_cts_grp2_pad_mux[] = {
4120		− MUX(1, 117, 2, 0xa08, 1, 0xa88, 1),
4121		−};
4122		−
4123		−static struct atlas7_grp_mux uart4_cts_grp2_mux = {
4124		− .pad_mux_count = ARRAY_SIZE(uart4_cts_grp2_pad_mux),
4125		− .pad_mux_list = uart4_cts_grp2_pad_mux,
4126		−};
4127		−
4128		−static struct atlas7_pad_mux uart4_rts_grp0_pad_mux[] = {
4129		− MUX(1, 123, 4, N, N, N, N),
4130		−};
4131		−
4132		−static struct atlas7_grp_mux uart4_rts_grp0_mux = {
4133		− .pad_mux_count = ARRAY_SIZE(uart4_rts_grp0_pad_mux),
4134		− .pad_mux_list = uart4_rts_grp0_pad_mux,
4135		−};
4136		−
4137		−static struct atlas7_pad_mux uart4_rts_grp1_pad_mux[] = {
4138		− MUX(1, 99, 4, N, N, N, N),
4139		−};
4140		−
4141		−static struct atlas7_grp_mux uart4_rts_grp1_mux = {
4142		− .pad_mux_count = ARRAY_SIZE(uart4_rts_grp1_pad_mux),
4143		− .pad_mux_list = uart4_rts_grp1_pad_mux,
4144		−};
4145		−
4146		−static struct atlas7_pad_mux uart4_rts_grp2_pad_mux[] = {
4147		− MUX(1, 116, 2, N, N, N, N),
4148		−};
4149		−
4150		−static struct atlas7_grp_mux uart4_rts_grp2_mux = {
4151		− .pad_mux_count = ARRAY_SIZE(uart4_rts_grp2_pad_mux),
4152		− .pad_mux_list = uart4_rts_grp2_pad_mux,
4153		−};
4154		−
4155		−static struct atlas7_pad_mux usb0_drvvbus_grp0_pad_mux[] = {
4156		− MUX(1, 51, 2, N, N, N, N),
4157		−};
4158		−
4159		−static struct atlas7_grp_mux usb0_drvvbus_grp0_mux = {
4160		− .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp0_pad_mux),
4161		− .pad_mux_list = usb0_drvvbus_grp0_pad_mux,
4162		−};
4163		−
4164		−static struct atlas7_pad_mux usb0_drvvbus_grp1_pad_mux[] = {
4165		− MUX(1, 162, 7, N, N, N, N),
4166		−};
4167		−
4168		−static struct atlas7_grp_mux usb0_drvvbus_grp1_mux = {
4169		− .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp1_pad_mux),
4170		− .pad_mux_list = usb0_drvvbus_grp1_pad_mux,
4171		−};
4172		−
4173		−static struct atlas7_pad_mux usb1_drvvbus_grp0_pad_mux[] = {
4174		− MUX(1, 134, 2, N, N, N, N),
4175		−};
4176		−
4177		−static struct atlas7_grp_mux usb1_drvvbus_grp0_mux = {
4178		− .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp0_pad_mux),
4179		− .pad_mux_list = usb1_drvvbus_grp0_pad_mux,
4180		−};
4181		−
4182		−static struct atlas7_pad_mux usb1_drvvbus_grp1_pad_mux[] = {
4183		− MUX(1, 163, 2, N, N, N, N),
4184		−};
4185		−
4186		−static struct atlas7_grp_mux usb1_drvvbus_grp1_mux = {
4187		− .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp1_pad_mux),
4188		− .pad_mux_list = usb1_drvvbus_grp1_pad_mux,
4189		−};
4190		−
4191		−static struct atlas7_pad_mux visbus_dout_grp_pad_mux[] = {
4192		− MUX(1, 57, 6, N, N, N, N),
4193		− MUX(1, 58, 6, N, N, N, N),
4194		− MUX(1, 59, 6, N, N, N, N),
4195		− MUX(1, 60, 6, N, N, N, N),
4196		− MUX(1, 61, 6, N, N, N, N),
4197		− MUX(1, 62, 6, N, N, N, N),
4198		− MUX(1, 63, 6, N, N, N, N),
4199		− MUX(1, 64, 6, N, N, N, N),
4200		− MUX(1, 65, 6, N, N, N, N),
4201		− MUX(1, 66, 6, N, N, N, N),
4202		− MUX(1, 67, 6, N, N, N, N),
4203		− MUX(1, 68, 6, N, N, N, N),
4204		− MUX(1, 69, 6, N, N, N, N),
4205		− MUX(1, 70, 6, N, N, N, N),
4206		− MUX(1, 71, 6, N, N, N, N),
4207		− MUX(1, 72, 6, N, N, N, N),
4208		− MUX(1, 53, 6, N, N, N, N),
4209		− MUX(1, 54, 6, N, N, N, N),
4210		− MUX(1, 55, 6, N, N, N, N),
4211		− MUX(1, 56, 6, N, N, N, N),
4212		− MUX(1, 85, 6, N, N, N, N),
4213		− MUX(1, 86, 6, N, N, N, N),
4214		− MUX(1, 87, 6, N, N, N, N),
4215		− MUX(1, 88, 6, N, N, N, N),
4216		− MUX(1, 89, 6, N, N, N, N),
4217		− MUX(1, 90, 6, N, N, N, N),
4218		− MUX(1, 91, 6, N, N, N, N),
4219		− MUX(1, 92, 6, N, N, N, N),
4220		− MUX(1, 93, 6, N, N, N, N),
4221		− MUX(1, 94, 6, N, N, N, N),
4222		− MUX(1, 95, 6, N, N, N, N),
4223		− MUX(1, 96, 6, N, N, N, N),
4224		−};
4225		−
4226		−static struct atlas7_grp_mux visbus_dout_grp_mux = {
4227		− .pad_mux_count = ARRAY_SIZE(visbus_dout_grp_pad_mux),
4228		− .pad_mux_list = visbus_dout_grp_pad_mux,
4229		−};
4230		−
4231		−static struct atlas7_pad_mux vi_vip1_grp_pad_mux[] = {
4232		− MUX(1, 74, 1, N, N, N, N),
4233		− MUX(1, 75, 1, N, N, N, N),
4234		− MUX(1, 76, 1, N, N, N, N),
4235		− MUX(1, 77, 1, N, N, N, N),
4236		− MUX(1, 78, 1, N, N, N, N),
4237		− MUX(1, 79, 1, N, N, N, N),
4238		− MUX(1, 80, 1, N, N, N, N),
4239		− MUX(1, 81, 1, N, N, N, N),
4240		− MUX(1, 82, 1, N, N, N, N),
4241		− MUX(1, 83, 1, N, N, N, N),
4242		− MUX(1, 84, 1, N, N, N, N),
4243		− MUX(1, 103, 2, N, N, N, N),
4244		− MUX(1, 104, 2, N, N, N, N),
4245		− MUX(1, 105, 2, N, N, N, N),
4246		− MUX(1, 106, 2, N, N, N, N),
4247		− MUX(1, 107, 2, N, N, N, N),
4248		− MUX(1, 102, 2, N, N, N, N),
4249		− MUX(1, 97, 2, N, N, N, N),
4250		− MUX(1, 98, 2, N, N, N, N),
4251		−};
4252		−
4253		−static struct atlas7_grp_mux vi_vip1_grp_mux = {
4254		− .pad_mux_count = ARRAY_SIZE(vi_vip1_grp_pad_mux),
4255		− .pad_mux_list = vi_vip1_grp_pad_mux,
4256		−};
4257		−
4258		−static struct atlas7_pad_mux vi_vip1_ext_grp_pad_mux[] = {
4259		− MUX(1, 74, 1, N, N, N, N),
4260		− MUX(1, 75, 1, N, N, N, N),
4261		− MUX(1, 76, 1, N, N, N, N),
4262		− MUX(1, 77, 1, N, N, N, N),
4263		− MUX(1, 78, 1, N, N, N, N),
4264		− MUX(1, 79, 1, N, N, N, N),
4265		− MUX(1, 80, 1, N, N, N, N),
4266		− MUX(1, 81, 1, N, N, N, N),
4267		− MUX(1, 82, 1, N, N, N, N),
4268		− MUX(1, 83, 1, N, N, N, N),
4269		− MUX(1, 84, 1, N, N, N, N),
4270		− MUX(1, 108, 2, N, N, N, N),
4271		− MUX(1, 103, 2, N, N, N, N),
4272		− MUX(1, 104, 2, N, N, N, N),
4273		− MUX(1, 105, 2, N, N, N, N),
4274		− MUX(1, 106, 2, N, N, N, N),
4275		− MUX(1, 107, 2, N, N, N, N),
4276		− MUX(1, 102, 2, N, N, N, N),
4277		− MUX(1, 97, 2, N, N, N, N),
4278		− MUX(1, 98, 2, N, N, N, N),
4279		− MUX(1, 99, 2, N, N, N, N),
4280		− MUX(1, 100, 2, N, N, N, N),
4281		−};
4282		−
4283		−static struct atlas7_grp_mux vi_vip1_ext_grp_mux = {
4284		− .pad_mux_count = ARRAY_SIZE(vi_vip1_ext_grp_pad_mux),
4285		− .pad_mux_list = vi_vip1_ext_grp_pad_mux,
4286		−};
4287		−
4288		−static struct atlas7_pad_mux vi_vip1_low8bit_grp_pad_mux[] = {
4289		− MUX(1, 74, 1, N, N, N, N),
4290		− MUX(1, 75, 1, N, N, N, N),
4291		− MUX(1, 76, 1, N, N, N, N),
4292		− MUX(1, 77, 1, N, N, N, N),
4293		− MUX(1, 78, 1, N, N, N, N),
4294		− MUX(1, 79, 1, N, N, N, N),
4295		− MUX(1, 80, 1, N, N, N, N),
4296		− MUX(1, 81, 1, N, N, N, N),
4297		− MUX(1, 82, 1, N, N, N, N),
4298		− MUX(1, 83, 1, N, N, N, N),
4299		− MUX(1, 84, 1, N, N, N, N),
4300		−};
4301		−
4302		−static struct atlas7_grp_mux vi_vip1_low8bit_grp_mux = {
4303		− .pad_mux_count = ARRAY_SIZE(vi_vip1_low8bit_grp_pad_mux),
4304		− .pad_mux_list = vi_vip1_low8bit_grp_pad_mux,
4305		−};
4306		−
4307		−static struct atlas7_pad_mux vi_vip1_high8bit_grp_pad_mux[] = {
4308		− MUX(1, 82, 1, N, N, N, N),
4309		− MUX(1, 83, 1, N, N, N, N),
4310		− MUX(1, 84, 1, N, N, N, N),
4311		− MUX(1, 103, 2, N, N, N, N),
4312		− MUX(1, 104, 2, N, N, N, N),
4313		− MUX(1, 105, 2, N, N, N, N),
4314		− MUX(1, 106, 2, N, N, N, N),
4315		− MUX(1, 107, 2, N, N, N, N),
4316		− MUX(1, 102, 2, N, N, N, N),
4317		− MUX(1, 97, 2, N, N, N, N),
4318		− MUX(1, 98, 2, N, N, N, N),
4319		−};
4320		−
4321		−static struct atlas7_grp_mux vi_vip1_high8bit_grp_mux = {
4322		− .pad_mux_count = ARRAY_SIZE(vi_vip1_high8bit_grp_pad_mux),
4323		− .pad_mux_list = vi_vip1_high8bit_grp_pad_mux,
4324		−};
4325		−
4326		−static struct atlas7_pmx_func atlas7_pmx_functions[] = {
4327		− FUNCTION("gnss_gpio", gnss_gpio_grp, &gnss_gpio_grp_mux),
4328		− FUNCTION("lcd_vip_gpio", lcd_vip_gpio_grp, &lcd_vip_gpio_grp_mux),
4329		− FUNCTION("sdio_i2s_gpio", sdio_i2s_gpio_grp, &sdio_i2s_gpio_grp_mux),
4330		− FUNCTION("sp_rgmii_gpio", sp_rgmii_gpio_grp, &sp_rgmii_gpio_grp_mux),
4331		− FUNCTION("lvds_gpio", lvds_gpio_grp, &lvds_gpio_grp_mux),
4332		− FUNCTION("jtag_uart_nand_gpio",
4333		− jtag_uart_nand_gpio_grp,
4334		− &jtag_uart_nand_gpio_grp_mux),
4335		− FUNCTION("rtc_gpio", rtc_gpio_grp, &rtc_gpio_grp_mux),
4336		− FUNCTION("audio_ac97", audio_ac97_grp, &audio_ac97_grp_mux),
4337		− FUNCTION("audio_digmic_m0",
4338		− audio_digmic_grp0,
4339		− &audio_digmic_grp0_mux),
4340		− FUNCTION("audio_digmic_m1",
4341		− audio_digmic_grp1,
4342		− &audio_digmic_grp1_mux),
4343		− FUNCTION("audio_digmic_m2",
4344		− audio_digmic_grp2,
4345		− &audio_digmic_grp2_mux),
4346		− FUNCTION("audio_func_dbg",
4347		− audio_func_dbg_grp,
4348		− &audio_func_dbg_grp_mux),
4349		− FUNCTION("audio_i2s", audio_i2s_grp, &audio_i2s_grp_mux),
4350		− FUNCTION("audio_i2s_2ch", audio_i2s_2ch_grp, &audio_i2s_2ch_grp_mux),
4351		− FUNCTION("audio_i2s_extclk",
4352		− audio_i2s_extclk_grp,
4353		− &audio_i2s_extclk_grp_mux),
4354		− FUNCTION("audio_spdif_out_m0",
4355		− audio_spdif_out_grp0,
4356		− &audio_spdif_out_grp0_mux),
4357		− FUNCTION("audio_spdif_out_m1",
4358		− audio_spdif_out_grp1,
4359		− &audio_spdif_out_grp1_mux),
4360		− FUNCTION("audio_spdif_out_m2",
4361		− audio_spdif_out_grp2,
4362		− &audio_spdif_out_grp2_mux),
4363		− FUNCTION("audio_uart0_basic",
4364		− audio_uart0_basic_grp,
4365		− &audio_uart0_basic_grp_mux),
4366		− FUNCTION("audio_uart0_urfs_m0",
4367		− audio_uart0_urfs_grp0,
4368		− &audio_uart0_urfs_grp0_mux),
4369		− FUNCTION("audio_uart0_urfs_m1",
4370		− audio_uart0_urfs_grp1,
4371		− &audio_uart0_urfs_grp1_mux),
4372		− FUNCTION("audio_uart0_urfs_m2",
4373		− audio_uart0_urfs_grp2,
4374		− &audio_uart0_urfs_grp2_mux),
4375		− FUNCTION("audio_uart0_urfs_m3",
4376		− audio_uart0_urfs_grp3,
4377		− &audio_uart0_urfs_grp3_mux),
4378		− FUNCTION("audio_uart1_basic",
4379		− audio_uart1_basic_grp,
4380		− &audio_uart1_basic_grp_mux),
4381		− FUNCTION("audio_uart1_urfs_m0",
4382		− audio_uart1_urfs_grp0,
4383		− &audio_uart1_urfs_grp0_mux),
4384		− FUNCTION("audio_uart1_urfs_m1",
4385		− audio_uart1_urfs_grp1,
4386		− &audio_uart1_urfs_grp1_mux),
4387		− FUNCTION("audio_uart1_urfs_m2",
4388		− audio_uart1_urfs_grp2,
4389		− &audio_uart1_urfs_grp2_mux),
4390		− FUNCTION("audio_uart2_urfs_m0",
4391		− audio_uart2_urfs_grp0,
4392		− &audio_uart2_urfs_grp0_mux),
4393		− FUNCTION("audio_uart2_urfs_m1",
4394		− audio_uart2_urfs_grp1,
4395		− &audio_uart2_urfs_grp1_mux),
4396		− FUNCTION("audio_uart2_urfs_m2",
4397		− audio_uart2_urfs_grp2,
4398		− &audio_uart2_urfs_grp2_mux),
4399		− FUNCTION("audio_uart2_urxd_m0",
4400		− audio_uart2_urxd_grp0,
4401		− &audio_uart2_urxd_grp0_mux),
4402		− FUNCTION("audio_uart2_urxd_m1",
4403		− audio_uart2_urxd_grp1,
4404		− &audio_uart2_urxd_grp1_mux),
4405		− FUNCTION("audio_uart2_urxd_m2",
4406		− audio_uart2_urxd_grp2,
4407		− &audio_uart2_urxd_grp2_mux),
4408		− FUNCTION("audio_uart2_usclk_m0",
4409		− audio_uart2_usclk_grp0,
4410		− &audio_uart2_usclk_grp0_mux),
4411		− FUNCTION("audio_uart2_usclk_m1",
4412		− audio_uart2_usclk_grp1,
4413		− &audio_uart2_usclk_grp1_mux),
4414		− FUNCTION("audio_uart2_usclk_m2",
4415		− audio_uart2_usclk_grp2,
4416		− &audio_uart2_usclk_grp2_mux),
4417		− FUNCTION("audio_uart2_utfs_m0",
4418		− audio_uart2_utfs_grp0,
4419		− &audio_uart2_utfs_grp0_mux),
4420		− FUNCTION("audio_uart2_utfs_m1",
4421		− audio_uart2_utfs_grp1,
4422		− &audio_uart2_utfs_grp1_mux),
4423		− FUNCTION("audio_uart2_utfs_m2",
4424		− audio_uart2_utfs_grp2,
4425		− &audio_uart2_utfs_grp2_mux),
4426		− FUNCTION("audio_uart2_utxd_m0",
4427		− audio_uart2_utxd_grp0,
4428		− &audio_uart2_utxd_grp0_mux),
4429		− FUNCTION("audio_uart2_utxd_m1",
4430		− audio_uart2_utxd_grp1,
4431		− &audio_uart2_utxd_grp1_mux),
4432		− FUNCTION("audio_uart2_utxd_m2",
4433		− audio_uart2_utxd_grp2,
4434		− &audio_uart2_utxd_grp2_mux),
4435		− FUNCTION("c_can_trnsvr_en_m0",
4436		− c_can_trnsvr_en_grp0,
4437		− &c_can_trnsvr_en_grp0_mux),
4438		− FUNCTION("c_can_trnsvr_en_m1",
4439		− c_can_trnsvr_en_grp1,
4440		− &c_can_trnsvr_en_grp1_mux),
4441		− FUNCTION("c_can_trnsvr_intr",
4442		− c_can_trnsvr_intr_grp,
4443		− &c_can_trnsvr_intr_grp_mux),
4444		− FUNCTION("c_can_trnsvr_stb_n",
4445		− c_can_trnsvr_stb_n_grp,
4446		− &c_can_trnsvr_stb_n_grp_mux),
4447		− FUNCTION("c0_can_rxd_trnsv0",
4448		− c0_can_rxd_trnsv0_grp,
4449		− &c0_can_rxd_trnsv0_grp_mux),
4450		− FUNCTION("c0_can_rxd_trnsv1",
4451		− c0_can_rxd_trnsv1_grp,
4452		− &c0_can_rxd_trnsv1_grp_mux),
4453		− FUNCTION("c0_can_txd_trnsv0",
4454		− c0_can_txd_trnsv0_grp,
4455		− &c0_can_txd_trnsv0_grp_mux),
4456		− FUNCTION("c0_can_txd_trnsv1",
4457		− c0_can_txd_trnsv1_grp,
4458		− &c0_can_txd_trnsv1_grp_mux),
4459		− FUNCTION("c1_can_rxd_m0", c1_can_rxd_grp0, &c1_can_rxd_grp0_mux),
4460		− FUNCTION("c1_can_rxd_m1", c1_can_rxd_grp1, &c1_can_rxd_grp1_mux),
4461		− FUNCTION("c1_can_rxd_m2", c1_can_rxd_grp2, &c1_can_rxd_grp2_mux),
4462		− FUNCTION("c1_can_rxd_m3", c1_can_rxd_grp3, &c1_can_rxd_grp3_mux),
4463		− FUNCTION("c1_can_txd_m0", c1_can_txd_grp0, &c1_can_txd_grp0_mux),
4464		− FUNCTION("c1_can_txd_m1", c1_can_txd_grp1, &c1_can_txd_grp1_mux),
4465		− FUNCTION("c1_can_txd_m2", c1_can_txd_grp2, &c1_can_txd_grp2_mux),
4466		− FUNCTION("c1_can_txd_m3", c1_can_txd_grp3, &c1_can_txd_grp3_mux),
4467		− FUNCTION("ca_audio_lpc", ca_audio_lpc_grp, &ca_audio_lpc_grp_mux),
4468		− FUNCTION("ca_bt_lpc", ca_bt_lpc_grp, &ca_bt_lpc_grp_mux),
4469		− FUNCTION("ca_coex", ca_coex_grp, &ca_coex_grp_mux),
4470		− FUNCTION("ca_curator_lpc",
4471		− ca_curator_lpc_grp,
4472		− &ca_curator_lpc_grp_mux),
4473		− FUNCTION("ca_pcm_debug", ca_pcm_debug_grp, &ca_pcm_debug_grp_mux),
4474		− FUNCTION("ca_pio", ca_pio_grp, &ca_pio_grp_mux),
4475		− FUNCTION("ca_sdio_debug", ca_sdio_debug_grp, &ca_sdio_debug_grp_mux),
4476		− FUNCTION("ca_spi", ca_spi_grp, &ca_spi_grp_mux),
4477		− FUNCTION("ca_trb", ca_trb_grp, &ca_trb_grp_mux),
4478		− FUNCTION("ca_uart_debug", ca_uart_debug_grp, &ca_uart_debug_grp_mux),
4479		− FUNCTION("clkc_m0", clkc_grp0, &clkc_grp0_mux),
4480		− FUNCTION("clkc_m1", clkc_grp1, &clkc_grp1_mux),
4481		− FUNCTION("gn_gnss_i2c", gn_gnss_i2c_grp, &gn_gnss_i2c_grp_mux),
4482		− FUNCTION("gn_gnss_uart_nopause",
4483		− gn_gnss_uart_nopause_grp,
4484		− &gn_gnss_uart_nopause_grp_mux),
4485		− FUNCTION("gn_gnss_uart", gn_gnss_uart_grp, &gn_gnss_uart_grp_mux),
4486		− FUNCTION("gn_trg_spi_m0", gn_trg_spi_grp0, &gn_trg_spi_grp0_mux),
4487		− FUNCTION("gn_trg_spi_m1", gn_trg_spi_grp1, &gn_trg_spi_grp1_mux),
4488		− FUNCTION("cvbs_dbg", cvbs_dbg_grp, &cvbs_dbg_grp_mux),
4489		− FUNCTION("cvbs_dbg_test_m0",
4490		− cvbs_dbg_test_grp0,
4491		− &cvbs_dbg_test_grp0_mux),
4492		− FUNCTION("cvbs_dbg_test_m1",
4493		− cvbs_dbg_test_grp1,
4494		− &cvbs_dbg_test_grp1_mux),
4495		− FUNCTION("cvbs_dbg_test_m2",
4496		− cvbs_dbg_test_grp2,
4497		− &cvbs_dbg_test_grp2_mux),
4498		− FUNCTION("cvbs_dbg_test_m3",
4499		− cvbs_dbg_test_grp3,
4500		− &cvbs_dbg_test_grp3_mux),
4501		− FUNCTION("cvbs_dbg_test_m4",
4502		− cvbs_dbg_test_grp4,
4503		− &cvbs_dbg_test_grp4_mux),
4504		− FUNCTION("cvbs_dbg_test_m5",
4505		− cvbs_dbg_test_grp5,
4506		− &cvbs_dbg_test_grp5_mux),
4507		− FUNCTION("cvbs_dbg_test_m6",
4508		− cvbs_dbg_test_grp6,
4509		− &cvbs_dbg_test_grp6_mux),
4510		− FUNCTION("cvbs_dbg_test_m7",
4511		− cvbs_dbg_test_grp7,
4512		− &cvbs_dbg_test_grp7_mux),
4513		− FUNCTION("cvbs_dbg_test_m8",
4514		− cvbs_dbg_test_grp8,
4515		− &cvbs_dbg_test_grp8_mux),
4516		− FUNCTION("cvbs_dbg_test_m9",
4517		− cvbs_dbg_test_grp9,
4518		− &cvbs_dbg_test_grp9_mux),
4519		− FUNCTION("cvbs_dbg_test_m10",
4520		− cvbs_dbg_test_grp10,
4521		− &cvbs_dbg_test_grp10_mux),
4522		− FUNCTION("cvbs_dbg_test_m11",
4523		− cvbs_dbg_test_grp11,
4524		− &cvbs_dbg_test_grp11_mux),
4525		− FUNCTION("cvbs_dbg_test_m12",
4526		− cvbs_dbg_test_grp12,
4527		− &cvbs_dbg_test_grp12_mux),
4528		− FUNCTION("cvbs_dbg_test_m13",
4529		− cvbs_dbg_test_grp13,
4530		− &cvbs_dbg_test_grp13_mux),
4531		− FUNCTION("cvbs_dbg_test_m14",
4532		− cvbs_dbg_test_grp14,
4533		− &cvbs_dbg_test_grp14_mux),
4534		− FUNCTION("cvbs_dbg_test_m15",
4535		− cvbs_dbg_test_grp15,
4536		− &cvbs_dbg_test_grp15_mux),
4537		− FUNCTION("gn_gnss_power", gn_gnss_power_grp, &gn_gnss_power_grp_mux),
4538		− FUNCTION("gn_gnss_sw_status",
4539		− gn_gnss_sw_status_grp,
4540		− &gn_gnss_sw_status_grp_mux),
4541		− FUNCTION("gn_gnss_eclk", gn_gnss_eclk_grp, &gn_gnss_eclk_grp_mux),
4542		− FUNCTION("gn_gnss_irq1_m0",
4543		− gn_gnss_irq1_grp0,
4544		− &gn_gnss_irq1_grp0_mux),
4545		− FUNCTION("gn_gnss_irq2_m0",
4546		− gn_gnss_irq2_grp0,
4547		− &gn_gnss_irq2_grp0_mux),
4548		− FUNCTION("gn_gnss_tm", gn_gnss_tm_grp, &gn_gnss_tm_grp_mux),
4549		− FUNCTION("gn_gnss_tsync", gn_gnss_tsync_grp, &gn_gnss_tsync_grp_mux),
4550		− FUNCTION("gn_io_gnsssys_sw_cfg",
4551		− gn_io_gnsssys_sw_cfg_grp,
4552		− &gn_io_gnsssys_sw_cfg_grp_mux),
4553		− FUNCTION("gn_trg_m0", gn_trg_grp0, &gn_trg_grp0_mux),
4554		− FUNCTION("gn_trg_m1", gn_trg_grp1, &gn_trg_grp1_mux),
4555		− FUNCTION("gn_trg_shutdown_m0",
4556		− gn_trg_shutdown_grp0,
4557		− &gn_trg_shutdown_grp0_mux),
4558		− FUNCTION("gn_trg_shutdown_m1",
4559		− gn_trg_shutdown_grp1,
4560		− &gn_trg_shutdown_grp1_mux),
4561		− FUNCTION("gn_trg_shutdown_m2",
4562		− gn_trg_shutdown_grp2,
4563		− &gn_trg_shutdown_grp2_mux),
4564		− FUNCTION("gn_trg_shutdown_m3",
4565		− gn_trg_shutdown_grp3,
4566		− &gn_trg_shutdown_grp3_mux),
4567		− FUNCTION("i2c0", i2c0_grp, &i2c0_grp_mux),
4568		− FUNCTION("i2c1", i2c1_grp, &i2c1_grp_mux),
4569		− FUNCTION("i2s0", i2s0_grp, &i2s0_grp_mux),
4570		− FUNCTION("i2s1_basic", i2s1_basic_grp, &i2s1_basic_grp_mux),
4571		− FUNCTION("i2s1_rxd0_m0", i2s1_rxd0_grp0, &i2s1_rxd0_grp0_mux),
4572		− FUNCTION("i2s1_rxd0_m1", i2s1_rxd0_grp1, &i2s1_rxd0_grp1_mux),
4573		− FUNCTION("i2s1_rxd0_m2", i2s1_rxd0_grp2, &i2s1_rxd0_grp2_mux),
4574		− FUNCTION("i2s1_rxd0_m3", i2s1_rxd0_grp3, &i2s1_rxd0_grp3_mux),
4575		− FUNCTION("i2s1_rxd0_m4", i2s1_rxd0_grp4, &i2s1_rxd0_grp4_mux),
4576		− FUNCTION("i2s1_rxd1_m0", i2s1_rxd1_grp0, &i2s1_rxd1_grp0_mux),
4577		− FUNCTION("i2s1_rxd1_m1", i2s1_rxd1_grp1, &i2s1_rxd1_grp1_mux),
4578		− FUNCTION("i2s1_rxd1_m2", i2s1_rxd1_grp2, &i2s1_rxd1_grp2_mux),
4579		− FUNCTION("i2s1_rxd1_m3", i2s1_rxd1_grp3, &i2s1_rxd1_grp3_mux),
4580		− FUNCTION("i2s1_rxd1_m4", i2s1_rxd1_grp4, &i2s1_rxd1_grp4_mux),
4581		− FUNCTION("jtag_jt_dbg_nsrst",
4582		− jtag_jt_dbg_nsrst_grp,
4583		− &jtag_jt_dbg_nsrst_grp_mux),
4584		− FUNCTION("jtag_ntrst_m0", jtag_ntrst_grp0, &jtag_ntrst_grp0_mux),
4585		− FUNCTION("jtag_ntrst_m1", jtag_ntrst_grp1, &jtag_ntrst_grp1_mux),
4586		− FUNCTION("jtag_swdiotms_m0",
4587		− jtag_swdiotms_grp0,
4588		− &jtag_swdiotms_grp0_mux),
4589		− FUNCTION("jtag_swdiotms_m1",
4590		− jtag_swdiotms_grp1,
4591		− &jtag_swdiotms_grp1_mux),
4592		− FUNCTION("jtag_tck_m0", jtag_tck_grp0, &jtag_tck_grp0_mux),
4593		− FUNCTION("jtag_tck_m1", jtag_tck_grp1, &jtag_tck_grp1_mux),
4594		− FUNCTION("jtag_tdi_m0", jtag_tdi_grp0, &jtag_tdi_grp0_mux),
4595		− FUNCTION("jtag_tdi_m1", jtag_tdi_grp1, &jtag_tdi_grp1_mux),
4596		− FUNCTION("jtag_tdo_m0", jtag_tdo_grp0, &jtag_tdo_grp0_mux),
4597		− FUNCTION("jtag_tdo_m1", jtag_tdo_grp1, &jtag_tdo_grp1_mux),
4598		− FUNCTION("ks_kas_spi_m0", ks_kas_spi_grp0, &ks_kas_spi_grp0_mux),
4599		− FUNCTION("ld_ldd", ld_ldd_grp, &ld_ldd_grp_mux),
4600		− FUNCTION("ld_ldd_16bit", ld_ldd_16bit_grp, &ld_ldd_16bit_grp_mux),
4601		− FUNCTION("ld_ldd_fck", ld_ldd_fck_grp, &ld_ldd_fck_grp_mux),
4602		− FUNCTION("ld_ldd_lck", ld_ldd_lck_grp, &ld_ldd_lck_grp_mux),
4603		− FUNCTION("lr_lcdrom", lr_lcdrom_grp, &lr_lcdrom_grp_mux),
4604		− FUNCTION("lvds_analog", lvds_analog_grp, &lvds_analog_grp_mux),
4605		− FUNCTION("nd_df_basic", nd_df_basic_grp, &nd_df_basic_grp_mux),
4606		− FUNCTION("nd_df_wp", nd_df_wp_grp, &nd_df_wp_grp_mux),
4607		− FUNCTION("nd_df_cs", nd_df_cs_grp, &nd_df_cs_grp_mux),
4608		− FUNCTION("ps", ps_grp, &ps_grp_mux),
4609		− FUNCTION("ps_no_dir", ps_no_dir_grp, &ps_no_dir_grp_mux),
4610		− FUNCTION("pwc_core_on", pwc_core_on_grp, &pwc_core_on_grp_mux),
4611		− FUNCTION("pwc_ext_on", pwc_ext_on_grp, &pwc_ext_on_grp_mux),
4612		− FUNCTION("pwc_gpio3_clk", pwc_gpio3_clk_grp, &pwc_gpio3_clk_grp_mux),
4613		− FUNCTION("pwc_io_on", pwc_io_on_grp, &pwc_io_on_grp_mux),
4614		− FUNCTION("pwc_lowbatt_b_m0",
4615		− pwc_lowbatt_b_grp0,
4616		− &pwc_lowbatt_b_grp0_mux),
4617		− FUNCTION("pwc_mem_on", pwc_mem_on_grp, &pwc_mem_on_grp_mux),
4618		− FUNCTION("pwc_on_key_b_m0",
4619		− pwc_on_key_b_grp0,
4620		− &pwc_on_key_b_grp0_mux),
4621		− FUNCTION("pwc_wakeup_src0",
4622		− pwc_wakeup_src0_grp,
4623		− &pwc_wakeup_src0_grp_mux),
4624		− FUNCTION("pwc_wakeup_src1",
4625		− pwc_wakeup_src1_grp,
4626		− &pwc_wakeup_src1_grp_mux),
4627		− FUNCTION("pwc_wakeup_src2",
4628		− pwc_wakeup_src2_grp,
4629		− &pwc_wakeup_src2_grp_mux),
4630		− FUNCTION("pwc_wakeup_src3",
4631		− pwc_wakeup_src3_grp,
4632		− &pwc_wakeup_src3_grp_mux),
4633		− FUNCTION("pw_cko0_m0", pw_cko0_grp0, &pw_cko0_grp0_mux),
4634		− FUNCTION("pw_cko0_m1", pw_cko0_grp1, &pw_cko0_grp1_mux),
4635		− FUNCTION("pw_cko0_m2", pw_cko0_grp2, &pw_cko0_grp2_mux),
4636		− FUNCTION("pw_cko0_m3", pw_cko0_grp3, &pw_cko0_grp3_mux),
4637		− FUNCTION("pw_cko1_m0", pw_cko1_grp0, &pw_cko1_grp0_mux),
4638		− FUNCTION("pw_cko1_m1", pw_cko1_grp1, &pw_cko1_grp1_mux),
4639		− FUNCTION("pw_cko1_m2", pw_cko1_grp2, &pw_cko1_grp2_mux),
4640		− FUNCTION("pw_i2s01_clk_m0",
4641		− pw_i2s01_clk_grp0,
4642		− &pw_i2s01_clk_grp0_mux),
4643		− FUNCTION("pw_i2s01_clk_m1",
4644		− pw_i2s01_clk_grp1,
4645		− &pw_i2s01_clk_grp1_mux),
4646		− FUNCTION("pw_i2s01_clk_m2",
4647		− pw_i2s01_clk_grp2,
4648		− &pw_i2s01_clk_grp2_mux),
4649		− FUNCTION("pw_pwm0_m0", pw_pwm0_grp0, &pw_pwm0_grp0_mux),
4650		− FUNCTION("pw_pwm0_m1", pw_pwm0_grp1, &pw_pwm0_grp1_mux),
4651		− FUNCTION("pw_pwm1_m0", pw_pwm1_grp0, &pw_pwm1_grp0_mux),
4652		− FUNCTION("pw_pwm1_m1", pw_pwm1_grp1, &pw_pwm1_grp1_mux),
4653		− FUNCTION("pw_pwm1_m2", pw_pwm1_grp2, &pw_pwm1_grp2_mux),
4654		− FUNCTION("pw_pwm2_m0", pw_pwm2_grp0, &pw_pwm2_grp0_mux),
4655		− FUNCTION("pw_pwm2_m1", pw_pwm2_grp1, &pw_pwm2_grp1_mux),
4656		− FUNCTION("pw_pwm2_m2", pw_pwm2_grp2, &pw_pwm2_grp2_mux),
4657		− FUNCTION("pw_pwm3_m0", pw_pwm3_grp0, &pw_pwm3_grp0_mux),
4658		− FUNCTION("pw_pwm3_m1", pw_pwm3_grp1, &pw_pwm3_grp1_mux),
4659		− FUNCTION("pw_pwm_cpu_vol_m0",
4660		− pw_pwm_cpu_vol_grp0,
4661		− &pw_pwm_cpu_vol_grp0_mux),
4662		− FUNCTION("pw_pwm_cpu_vol_m1",
4663		− pw_pwm_cpu_vol_grp1,
4664		− &pw_pwm_cpu_vol_grp1_mux),
4665		− FUNCTION("pw_pwm_cpu_vol_m2",
4666		− pw_pwm_cpu_vol_grp2,
4667		− &pw_pwm_cpu_vol_grp2_mux),
4668		− FUNCTION("pw_backlight_m0",
4669		− pw_backlight_grp0,
4670		− &pw_backlight_grp0_mux),
4671		− FUNCTION("pw_backlight_m1",
4672		− pw_backlight_grp1,
4673		− &pw_backlight_grp1_mux),
4674		− FUNCTION("rg_eth_mac", rg_eth_mac_grp, &rg_eth_mac_grp_mux),
4675		− FUNCTION("rg_gmac_phy_intr_n",
4676		− rg_gmac_phy_intr_n_grp,
4677		− &rg_gmac_phy_intr_n_grp_mux),
4678		− FUNCTION("rg_rgmii_mac", rg_rgmii_mac_grp, &rg_rgmii_mac_grp_mux),
4679		− FUNCTION("rg_rgmii_phy_ref_clk_m0",
4680		− rg_rgmii_phy_ref_clk_grp0,
4681		− &rg_rgmii_phy_ref_clk_grp0_mux),
4682		− FUNCTION("rg_rgmii_phy_ref_clk_m1",
4683		− rg_rgmii_phy_ref_clk_grp1,
4684		− &rg_rgmii_phy_ref_clk_grp1_mux),
4685		− FUNCTION("sd0", sd0_grp, &sd0_grp_mux),
4686		− FUNCTION("sd0_4bit", sd0_4bit_grp, &sd0_4bit_grp_mux),
4687		− FUNCTION("sd1", sd1_grp, &sd1_grp_mux),
4688		− FUNCTION("sd1_4bit_m0", sd1_4bit_grp0, &sd1_4bit_grp0_mux),
4689		− FUNCTION("sd1_4bit_m1", sd1_4bit_grp1, &sd1_4bit_grp1_mux),
4690		− FUNCTION("sd2_basic", sd2_basic_grp, &sd2_basic_grp_mux),
4691		− FUNCTION("sd2_cdb_m0", sd2_cdb_grp0, &sd2_cdb_grp0_mux),
4692		− FUNCTION("sd2_cdb_m1", sd2_cdb_grp1, &sd2_cdb_grp1_mux),
4693		− FUNCTION("sd2_wpb_m0", sd2_wpb_grp0, &sd2_wpb_grp0_mux),
4694		− FUNCTION("sd2_wpb_m1", sd2_wpb_grp1, &sd2_wpb_grp1_mux),
4695		− FUNCTION("sd3", sd3_9_grp, &sd3_9_grp_mux),
4696		− FUNCTION("sd5", sd5_grp, &sd5_grp_mux),
4697		− FUNCTION("sd6_m0", sd6_grp0, &sd6_grp0_mux),
4698		− FUNCTION("sd6_m1", sd6_grp1, &sd6_grp1_mux),
4699		− FUNCTION("sd9", sd3_9_grp, &sd3_9_grp_mux),
4700		− FUNCTION("sp0_ext_ldo_on",
4701		− sp0_ext_ldo_on_grp,
4702		− &sp0_ext_ldo_on_grp_mux),
4703		− FUNCTION("sp0_qspi", sp0_qspi_grp, &sp0_qspi_grp_mux),
4704		− FUNCTION("sp1_spi", sp1_spi_grp, &sp1_spi_grp_mux),
4705		− FUNCTION("tpiu_trace", tpiu_trace_grp, &tpiu_trace_grp_mux),
4706		− FUNCTION("uart0", uart0_grp, &uart0_grp_mux),
4707		− FUNCTION("uart0_nopause", uart0_nopause_grp, &uart0_nopause_grp_mux),
4708		− FUNCTION("uart1", uart1_grp, &uart1_grp_mux),
4709		− FUNCTION("uart2_cts_m0", uart2_cts_grp0, &uart2_cts_grp0_mux),
4710		− FUNCTION("uart2_cts_m1", uart2_cts_grp1, &uart2_cts_grp1_mux),
4711		− FUNCTION("uart2_rts_m0", uart2_rts_grp0, &uart2_rts_grp0_mux),
4712		− FUNCTION("uart2_rts_m1", uart2_rts_grp1, &uart2_rts_grp1_mux),
4713		− FUNCTION("uart2_rxd_m0", uart2_rxd_grp0, &uart2_rxd_grp0_mux),
4714		− FUNCTION("uart2_rxd_m1", uart2_rxd_grp1, &uart2_rxd_grp1_mux),
4715		− FUNCTION("uart2_rxd_m2", uart2_rxd_grp2, &uart2_rxd_grp2_mux),
4716		− FUNCTION("uart2_txd_m0", uart2_txd_grp0, &uart2_txd_grp0_mux),
4717		− FUNCTION("uart2_txd_m1", uart2_txd_grp1, &uart2_txd_grp1_mux),
4718		− FUNCTION("uart2_txd_m2", uart2_txd_grp2, &uart2_txd_grp2_mux),
4719		− FUNCTION("uart3_cts_m0", uart3_cts_grp0, &uart3_cts_grp0_mux),
4720		− FUNCTION("uart3_cts_m1", uart3_cts_grp1, &uart3_cts_grp1_mux),
4721		− FUNCTION("uart3_cts_m2", uart3_cts_grp2, &uart3_cts_grp2_mux),
4722		− FUNCTION("uart3_rts_m0", uart3_rts_grp0, &uart3_rts_grp0_mux),
4723		− FUNCTION("uart3_rts_m1", uart3_rts_grp1, &uart3_rts_grp1_mux),
4724		− FUNCTION("uart3_rts_m2", uart3_rts_grp2, &uart3_rts_grp2_mux),
4725		− FUNCTION("uart3_rxd_m0", uart3_rxd_grp0, &uart3_rxd_grp0_mux),
4726		− FUNCTION("uart3_rxd_m1", uart3_rxd_grp1, &uart3_rxd_grp1_mux),
4727		− FUNCTION("uart3_rxd_m2", uart3_rxd_grp2, &uart3_rxd_grp2_mux),
4728		− FUNCTION("uart3_txd_m0", uart3_txd_grp0, &uart3_txd_grp0_mux),
4729		− FUNCTION("uart3_txd_m1", uart3_txd_grp1, &uart3_txd_grp1_mux),
4730		− FUNCTION("uart3_txd_m2", uart3_txd_grp2, &uart3_txd_grp2_mux),
4731		− FUNCTION("uart4_basic", uart4_basic_grp, &uart4_basic_grp_mux),
4732		− FUNCTION("uart4_cts_m0", uart4_cts_grp0, &uart4_cts_grp0_mux),
4733		− FUNCTION("uart4_cts_m1", uart4_cts_grp1, &uart4_cts_grp1_mux),
4734		− FUNCTION("uart4_cts_m2", uart4_cts_grp2, &uart4_cts_grp2_mux),
4735		− FUNCTION("uart4_rts_m0", uart4_rts_grp0, &uart4_rts_grp0_mux),
4736		− FUNCTION("uart4_rts_m1", uart4_rts_grp1, &uart4_rts_grp1_mux),
4737		− FUNCTION("uart4_rts_m2", uart4_rts_grp2, &uart4_rts_grp2_mux),
4738		− FUNCTION("usb0_drvvbus_m0",
4739		− usb0_drvvbus_grp0,
4740		− &usb0_drvvbus_grp0_mux),
4741		− FUNCTION("usb0_drvvbus_m1",
4742		− usb0_drvvbus_grp1,
4743		− &usb0_drvvbus_grp1_mux),
4744		− FUNCTION("usb1_drvvbus_m0",
4745		− usb1_drvvbus_grp0,
4746		− &usb1_drvvbus_grp0_mux),
4747		− FUNCTION("usb1_drvvbus_m1",
4748		− usb1_drvvbus_grp1,
4749		− &usb1_drvvbus_grp1_mux),
4750		− FUNCTION("visbus_dout", visbus_dout_grp, &visbus_dout_grp_mux),
4751		− FUNCTION("vi_vip1", vi_vip1_grp, &vi_vip1_grp_mux),
4752		− FUNCTION("vi_vip1_ext", vi_vip1_ext_grp, &vi_vip1_ext_grp_mux),
4753		− FUNCTION("vi_vip1_low8bit",
4754		− vi_vip1_low8bit_grp,
4755		− &vi_vip1_low8bit_grp_mux),
4756		− FUNCTION("vi_vip1_high8bit",
4757		− vi_vip1_high8bit_grp,
4758		− &vi_vip1_high8bit_grp_mux),
4759		−};
4760		−
4761		−static struct atlas7_pinctrl_data atlas7_ioc_data = {
4762		− .pads = (struct pinctrl_pin_desc *)atlas7_ioc_pads,
4763		− .pads_cnt = ARRAY_SIZE(atlas7_ioc_pads),
4764		− .grps = (struct atlas7_pin_group *)altas7_pin_groups,
4765		− .grps_cnt = ARRAY_SIZE(altas7_pin_groups),
4766		− .funcs = (struct atlas7_pmx_func *)atlas7_pmx_functions,
4767		− .funcs_cnt = ARRAY_SIZE(atlas7_pmx_functions),
4768		− .confs = (struct atlas7_pad_config *)atlas7_ioc_pad_confs,
4769		− .confs_cnt = ARRAY_SIZE(atlas7_ioc_pad_confs),
4770		−};
4771		−
4772		−/* Simple map data structure */
4773		−struct map_data {
4774		− u8 idx;
4775		− u8 data;
4776		−};
4777		−
4778		−/**
4779		− * struct atlas7_pull_info - Atlas7 Pad pull info
4780		− * @pad_type: The type of this Pad.
4781		− * @mask: The mas value of this pin's pull bits.
4782		− * @v2s: The map of pull register value to pull status.
4783		− * @s2v: The map of pull status to pull register value.
4784		− */
4785		−struct atlas7_pull_info {
4786		− u8 pad_type;
4787		− u8 mask;
4788		− const struct map_data *v2s;
4789		− const struct map_data *s2v;
4790		−};
4791		−
4792		−/* Pull Register value map to status */
4793		−static const struct map_data p4we_pull_v2s[] = {
4794		− { P4WE_PULL_UP, PULL_UP },
4795		− { P4WE_HIGH_HYSTERESIS, HIGH_HYSTERESIS },
4796		− { P4WE_HIGH_Z, HIGH_Z },
4797		− { P4WE_PULL_DOWN, PULL_DOWN },
4798		−};
4799		−
4800		−static const struct map_data p16st_pull_v2s[] = {
4801		− { P16ST_PULL_UP, PULL_UP },
4802		− { PD, PULL_UNKNOWN },
4803		− { P16ST_HIGH_Z, HIGH_Z },
4804		− { P16ST_PULL_DOWN, PULL_DOWN },
4805		−};
4806		−
4807		−static const struct map_data pm31_pull_v2s[] = {
4808		− { PM31_PULL_DISABLED, PULL_DOWN },
4809		− { PM31_PULL_ENABLED, PULL_UP },
4810		−};
4811		−
4812		−static const struct map_data pangd_pull_v2s[] = {
4813		− { PANGD_PULL_UP, PULL_UP },
4814		− { PD, PULL_UNKNOWN },
4815		− { PANGD_HIGH_Z, HIGH_Z },
4816		− { PANGD_PULL_DOWN, PULL_DOWN },
4817		−};
4818		−
4819		−/* Pull status map to register value */
4820		−static const struct map_data p4we_pull_s2v[] = {
4821		− { PULL_UP, P4WE_PULL_UP },
4822		− { HIGH_HYSTERESIS, P4WE_HIGH_HYSTERESIS },
4823		− { HIGH_Z, P4WE_HIGH_Z },
4824		− { PULL_DOWN, P4WE_PULL_DOWN },
4825		− { PULL_DISABLE, -1 },
4826		− { PULL_ENABLE, -1 },
4827		−};
4828		−
4829		−static const struct map_data p16st_pull_s2v[] = {
4830		− { PULL_UP, P16ST_PULL_UP },
4831		− { HIGH_HYSTERESIS, -1 },
4832		− { HIGH_Z, P16ST_HIGH_Z },
4833		− { PULL_DOWN, P16ST_PULL_DOWN },
4834		− { PULL_DISABLE, -1 },
4835		− { PULL_ENABLE, -1 },
4836		−};
4837		−
4838		−static const struct map_data pm31_pull_s2v[] = {
4839		− { PULL_UP, PM31_PULL_ENABLED },
4840		− { HIGH_HYSTERESIS, -1 },
4841		− { HIGH_Z, -1 },
4842		− { PULL_DOWN, PM31_PULL_DISABLED },
4843		− { PULL_DISABLE, -1 },
4844		− { PULL_ENABLE, -1 },
4845		−};
4846		−
4847		−static const struct map_data pangd_pull_s2v[] = {
4848		− { PULL_UP, PANGD_PULL_UP },
4849		− { HIGH_HYSTERESIS, -1 },
4850		− { HIGH_Z, PANGD_HIGH_Z },
4851		− { PULL_DOWN, PANGD_PULL_DOWN },
4852		− { PULL_DISABLE, -1 },
4853		− { PULL_ENABLE, -1 },
4854		−};
4855		−
4856		−static const struct atlas7_pull_info atlas7_pull_map[] = {
4857		− { PAD_T_4WE_PD, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
4858		− { PAD_T_4WE_PU, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
4859		− { PAD_T_16ST, P16ST_PULL_MASK, p16st_pull_v2s, p16st_pull_s2v },
4860		− { PAD_T_M31_0204_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4861		− { PAD_T_M31_0204_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4862		− { PAD_T_M31_0610_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4863		− { PAD_T_M31_0610_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4864		− { PAD_T_AD, PANGD_PULL_MASK, pangd_pull_v2s, pangd_pull_s2v },
4865		−};
4866		−
4867		−/**
4868		− * struct atlas7_ds_ma_info - Atlas7 Pad DriveStrength & currents info
4869		− * @ma: The Drive Strength in current value .
4870		− * @ds_16st: The correspond raw value of 16st pad.
4871		− * @ds_4we: The correspond raw value of 4we pad.
4872		− * @ds_0204m31: The correspond raw value of 0204m31 pad.
4873		− * @ds_0610m31: The correspond raw value of 0610m31 pad.
4874		− */
4875		−struct atlas7_ds_ma_info {
4876		− u32 ma;
4877		− u32 ds_16st;
4878		− u32 ds_4we;
4879		− u32 ds_0204m31;
4880		− u32 ds_0610m31;
4881		−};
4882		−
4883		−static const struct atlas7_ds_ma_info atlas7_ma2ds_map[] = {
4884		− { 2, DS_16ST_0, DS_4WE_0, DS_M31_0, DS_NULL },
4885		− { 4, DS_16ST_1, DS_NULL, DS_M31_1, DS_NULL },
4886		− { 6, DS_16ST_2, DS_NULL, DS_NULL, DS_M31_0 },
4887		− { 8, DS_16ST_3, DS_4WE_1, DS_NULL, DS_NULL },
4888		− { 10, DS_16ST_4, DS_NULL, DS_NULL, DS_M31_1 },
4889		− { 12, DS_16ST_5, DS_NULL, DS_NULL, DS_NULL },
4890		− { 14, DS_16ST_6, DS_NULL, DS_NULL, DS_NULL },
4891		− { 16, DS_16ST_7, DS_4WE_2, DS_NULL, DS_NULL },
4892		− { 18, DS_16ST_8, DS_NULL, DS_NULL, DS_NULL },
4893		− { 20, DS_16ST_9, DS_NULL, DS_NULL, DS_NULL },
4894		− { 22, DS_16ST_10, DS_NULL, DS_NULL, DS_NULL },
4895		− { 24, DS_16ST_11, DS_NULL, DS_NULL, DS_NULL },
4896		− { 26, DS_16ST_12, DS_NULL, DS_NULL, DS_NULL },
4897		− { 28, DS_16ST_13, DS_4WE_3, DS_NULL, DS_NULL },
4898		− { 30, DS_16ST_14, DS_NULL, DS_NULL, DS_NULL },
4899		− { 32, DS_16ST_15, DS_NULL, DS_NULL, DS_NULL },
4900		−};
4901		−
4902		−/**
4903		− * struct atlas7_ds_info - Atlas7 Pad DriveStrength info
4904		− * @type: The type of this Pad.
4905		− * @mask: The mask value of this pin's pull bits.
4906		− * @imval: The immediate value of drives trength register.
4907		− * @reserved: Reserved space
4908		− */
4909		−struct atlas7_ds_info {
4910		− u8 type;
4911		− u8 mask;
4912		− u8 imval;
4913		− u8 reserved;
4914		−};
4915		−
4916		−static const struct atlas7_ds_info atlas7_ds_map[] = {
4917		− { PAD_T_4WE_PD, DS_2BIT_MASK, DS_2BIT_IM_VAL },
4918		− { PAD_T_4WE_PU, DS_2BIT_MASK, DS_2BIT_IM_VAL },
4919		− { PAD_T_16ST, DS_4BIT_MASK, DS_4BIT_IM_VAL },
4920		− { PAD_T_M31_0204_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4921		− { PAD_T_M31_0204_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4922		− { PAD_T_M31_0610_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4923		− { PAD_T_M31_0610_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4924		− { PAD_T_AD, DS_NULL, DS_NULL },
4925		−};
4926		−
4927		−static inline u32 atlas7_pin_to_bank(u32 pin)
4928		−{
4929		− return (pin >= ATLAS7_PINCTRL_BANK_0_PINS) ? 1 : 0;
4930		−}
4931		−
4932		−static int atlas7_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
4933		−{
4934		− struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
4935		−
4936		− return pmx->pctl_data->funcs_cnt;
4937		−}
4938		−
4939		−static const char atlas7_pmx_get_func_name(struct pinctrl_dev pctldev,
4940		− u32 selector)
4941		−{
4942		− struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
4943		−
4944		− return pmx->pctl_data->funcs[selector].name;
4945		−}
4946		−
4947		−static int atlas7_pmx_get_func_groups(struct pinctrl_dev *pctldev,
4948		− u32 selector, const char * const **groups,
4949		− u32 * const num_groups)
4950		−{
4951		− struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
4952		−
4953		− *groups = pmx->pctl_data->funcs[selector].groups;
4954		− *num_groups = pmx->pctl_data->funcs[selector].num_groups;
4955		−
4956		− return 0;
4957		−}
4958		−
4959		−static void __atlas7_pmx_pin_input_disable_set(struct atlas7_pmx *pmx,
4960		− const struct atlas7_pad_mux *mux)
4961		−{
4962		− /* Set Input Disable to avoid input glitches
4963		− *
4964		− * All Input-Disable Control registers are located on IOCRTC.
4965		− * So the regs bank is always 0.
4966		− *
4967		− */
4968		− if (mux->dinput_reg && mux->dinput_val_reg) {
4969		− writel(DI_MASK << mux->dinput_bit,
4970		− pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
4971		− writel(DI_DISABLE << mux->dinput_bit,
4972		− pmx->regs[BANK_DS] + mux->dinput_reg);
4973		−
4974		−
4975		− writel(DIV_MASK << mux->dinput_val_bit,
4976		− pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
4977		− writel(DIV_DISABLE << mux->dinput_val_bit,
4978		− pmx->regs[BANK_DS] + mux->dinput_val_reg);
4979		− }
4980		−}
4981		−
4982		−static void __atlas7_pmx_pin_input_disable_clr(struct atlas7_pmx *pmx,
4983		− const struct atlas7_pad_mux *mux)
4984		−{
4985		− /* Clear Input Disable to avoid input glitches */
4986		− if (mux->dinput_reg && mux->dinput_val_reg) {
4987		− writel(DI_MASK << mux->dinput_bit,
4988		− pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
4989		− writel(DI_ENABLE << mux->dinput_bit,
4990		− pmx->regs[BANK_DS] + mux->dinput_reg);
4991		−
4992		− writel(DIV_MASK << mux->dinput_val_bit,
4993		− pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
4994		− writel(DIV_ENABLE << mux->dinput_val_bit,
4995		− pmx->regs[BANK_DS] + mux->dinput_val_reg);
4996		− }
4997		−}
4998		−
4999		−static int __atlas7_pmx_pin_ad_sel(struct atlas7_pmx *pmx,

1158 more lines aren’t shown here.

drivers/pinctrl/sirf/pinctrl-prima2.c+0−1131

@@ -1,1131 +0,0 @@
1		−// SPDX-License-Identifier: GPL-2.0-or-later
2		−/*
3		− * pinctrl pads, groups, functions for CSR SiRFprimaII
4		− *
5		− * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
6		− * company.
7		− */
8		−
9		−#include <linux/pinctrl/pinctrl.h>
10		−#include <linux/bitops.h>
11		−
12		−#include "pinctrl-sirf.h"
13		−
14		−/*
15		− * pad list for the pinmux subsystem
16		− * refer to CS-131858-DC-6A.xls
17		− */
18		−static const struct pinctrl_pin_desc sirfsoc_pads[] = {
19		− PINCTRL_PIN(0, "gpio0-0"),
20		− PINCTRL_PIN(1, "gpio0-1"),
21		− PINCTRL_PIN(2, "gpio0-2"),
22		− PINCTRL_PIN(3, "gpio0-3"),
23		− PINCTRL_PIN(4, "pwm0"),
24		− PINCTRL_PIN(5, "pwm1"),
25		− PINCTRL_PIN(6, "pwm2"),
26		− PINCTRL_PIN(7, "pwm3"),
27		− PINCTRL_PIN(8, "warm_rst_b"),
28		− PINCTRL_PIN(9, "odo_0"),
29		− PINCTRL_PIN(10, "odo_1"),
30		− PINCTRL_PIN(11, "dr_dir"),
31		− PINCTRL_PIN(12, "viprom_fa"),
32		− PINCTRL_PIN(13, "scl_1"),
33		− PINCTRL_PIN(14, "ntrst"),
34		− PINCTRL_PIN(15, "sda_1"),
35		− PINCTRL_PIN(16, "x_ldd[16]"),
36		− PINCTRL_PIN(17, "x_ldd[17]"),
37		− PINCTRL_PIN(18, "x_ldd[18]"),
38		− PINCTRL_PIN(19, "x_ldd[19]"),
39		− PINCTRL_PIN(20, "x_ldd[20]"),
40		− PINCTRL_PIN(21, "x_ldd[21]"),
41		− PINCTRL_PIN(22, "x_ldd[22]"),
42		− PINCTRL_PIN(23, "x_ldd[23], lcdrom_frdy"),
43		− PINCTRL_PIN(24, "gps_sgn"),
44		− PINCTRL_PIN(25, "gps_mag"),
45		− PINCTRL_PIN(26, "gps_clk"),
46		− PINCTRL_PIN(27, "sd_cd_b_1"),
47		− PINCTRL_PIN(28, "sd_vcc_on_1"),
48		− PINCTRL_PIN(29, "sd_wp_b_1"),
49		− PINCTRL_PIN(30, "sd_clk_3"),
50		− PINCTRL_PIN(31, "sd_cmd_3"),
51		−
52		− PINCTRL_PIN(32, "x_sd_dat_3[0]"),
53		− PINCTRL_PIN(33, "x_sd_dat_3[1]"),
54		− PINCTRL_PIN(34, "x_sd_dat_3[2]"),
55		− PINCTRL_PIN(35, "x_sd_dat_3[3]"),
56		− PINCTRL_PIN(36, "x_sd_clk_4"),
57		− PINCTRL_PIN(37, "x_sd_cmd_4"),
58		− PINCTRL_PIN(38, "x_sd_dat_4[0]"),
59		− PINCTRL_PIN(39, "x_sd_dat_4[1]"),
60		− PINCTRL_PIN(40, "x_sd_dat_4[2]"),
61		− PINCTRL_PIN(41, "x_sd_dat_4[3]"),
62		− PINCTRL_PIN(42, "x_cko_1"),
63		− PINCTRL_PIN(43, "x_ac97_bit_clk"),
64		− PINCTRL_PIN(44, "x_ac97_dout"),
65		− PINCTRL_PIN(45, "x_ac97_din"),
66		− PINCTRL_PIN(46, "x_ac97_sync"),
67		− PINCTRL_PIN(47, "x_txd_1"),
68		− PINCTRL_PIN(48, "x_txd_2"),
69		− PINCTRL_PIN(49, "x_rxd_1"),
70		− PINCTRL_PIN(50, "x_rxd_2"),
71		− PINCTRL_PIN(51, "x_usclk_0"),
72		− PINCTRL_PIN(52, "x_utxd_0"),
73		− PINCTRL_PIN(53, "x_urxd_0"),
74		− PINCTRL_PIN(54, "x_utfs_0"),
75		− PINCTRL_PIN(55, "x_urfs_0"),
76		− PINCTRL_PIN(56, "x_usclk_1"),
77		− PINCTRL_PIN(57, "x_utxd_1"),
78		− PINCTRL_PIN(58, "x_urxd_1"),
79		− PINCTRL_PIN(59, "x_utfs_1"),
80		− PINCTRL_PIN(60, "x_urfs_1"),
81		− PINCTRL_PIN(61, "x_usclk_2"),
82		− PINCTRL_PIN(62, "x_utxd_2"),
83		− PINCTRL_PIN(63, "x_urxd_2"),
84		−
85		− PINCTRL_PIN(64, "x_utfs_2"),
86		− PINCTRL_PIN(65, "x_urfs_2"),
87		− PINCTRL_PIN(66, "x_df_we_b"),
88		− PINCTRL_PIN(67, "x_df_re_b"),
89		− PINCTRL_PIN(68, "x_txd_0"),
90		− PINCTRL_PIN(69, "x_rxd_0"),
91		− PINCTRL_PIN(78, "x_cko_0"),
92		− PINCTRL_PIN(79, "x_vip_pxd[7]"),
93		− PINCTRL_PIN(80, "x_vip_pxd[6]"),
94		− PINCTRL_PIN(81, "x_vip_pxd[5]"),
95		− PINCTRL_PIN(82, "x_vip_pxd[4]"),
96		− PINCTRL_PIN(83, "x_vip_pxd[3]"),
97		− PINCTRL_PIN(84, "x_vip_pxd[2]"),
98		− PINCTRL_PIN(85, "x_vip_pxd[1]"),
99		− PINCTRL_PIN(86, "x_vip_pxd[0]"),
100		− PINCTRL_PIN(87, "x_vip_vsync"),
101		− PINCTRL_PIN(88, "x_vip_hsync"),
102		− PINCTRL_PIN(89, "x_vip_pxclk"),
103		− PINCTRL_PIN(90, "x_sda_0"),
104		− PINCTRL_PIN(91, "x_scl_0"),
105		− PINCTRL_PIN(92, "x_df_ry_by"),
106		− PINCTRL_PIN(93, "x_df_cs_b[1]"),
107		− PINCTRL_PIN(94, "x_df_cs_b[0]"),
108		− PINCTRL_PIN(95, "x_l_pclk"),
109		−
110		− PINCTRL_PIN(96, "x_l_lck"),
111		− PINCTRL_PIN(97, "x_l_fck"),
112		− PINCTRL_PIN(98, "x_l_de"),
113		− PINCTRL_PIN(99, "x_ldd[0]"),
114		− PINCTRL_PIN(100, "x_ldd[1]"),
115		− PINCTRL_PIN(101, "x_ldd[2]"),
116		− PINCTRL_PIN(102, "x_ldd[3]"),
117		− PINCTRL_PIN(103, "x_ldd[4]"),
118		− PINCTRL_PIN(104, "x_ldd[5]"),
119		− PINCTRL_PIN(105, "x_ldd[6]"),
120		− PINCTRL_PIN(106, "x_ldd[7]"),
121		− PINCTRL_PIN(107, "x_ldd[8]"),
122		− PINCTRL_PIN(108, "x_ldd[9]"),
123		− PINCTRL_PIN(109, "x_ldd[10]"),
124		− PINCTRL_PIN(110, "x_ldd[11]"),
125		− PINCTRL_PIN(111, "x_ldd[12]"),
126		− PINCTRL_PIN(112, "x_ldd[13]"),
127		− PINCTRL_PIN(113, "x_ldd[14]"),
128		− PINCTRL_PIN(114, "x_ldd[15]"),
129		−
130		− PINCTRL_PIN(115, "x_usb1_dp"),
131		− PINCTRL_PIN(116, "x_usb1_dn"),
132		−};
133		−
134		−static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
135		− {
136		− .group = 3,
137		− .mask = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \|
138		− BIT(6) \| BIT(7) \| BIT(8) \| BIT(9) \| BIT(10) \| BIT(11) \|
139		− BIT(12) \| BIT(13) \| BIT(14) \| BIT(15) \| BIT(16) \|
140		− BIT(17) \| BIT(18),
141		− }, {
142		− .group = 2,
143		− .mask = BIT(31),
144		− },
145		−};
146		−
147		−static const struct sirfsoc_padmux lcd_16bits_padmux = {
148		− .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
149		− .muxmask = lcd_16bits_sirfsoc_muxmask,
150		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
151		− .funcmask = BIT(4),
152		− .funcval = 0,
153		−};
154		−
155		−static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102,
156		− 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
157		−
158		−static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
159		− {
160		− .group = 3,
161		− .mask = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \|
162		− BIT(6) \| BIT(7) \| BIT(8) \| BIT(9) \| BIT(10) \| BIT(11) \|
163		− BIT(12) \| BIT(13) \| BIT(14) \| BIT(15) \| BIT(16) \|
164		− BIT(17) \| BIT(18),
165		− }, {
166		− .group = 2,
167		− .mask = BIT(31),
168		− }, {
169		− .group = 0,
170		− .mask = BIT(16) \| BIT(17),
171		− },
172		−};
173		−
174		−static const struct sirfsoc_padmux lcd_18bits_padmux = {
175		− .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
176		− .muxmask = lcd_18bits_muxmask,
177		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
178		− .funcmask = BIT(4),
179		− .funcval = 0,
180		−};
181		−
182		−static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100,
183		− 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114};
184		−
185		−static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
186		− {
187		− .group = 3,
188		− .mask = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \|
189		− BIT(6) \| BIT(7) \| BIT(8) \| BIT(9) \| BIT(10) \| BIT(11) \|
190		− BIT(12) \| BIT(13) \| BIT(14) \| BIT(15) \| BIT(16) \|
191		− BIT(17) \| BIT(18),
192		− }, {
193		− .group = 2,
194		− .mask = BIT(31),
195		− }, {
196		− .group = 0,
197		− .mask = BIT(16) \| BIT(17) \| BIT(18) \| BIT(19) \| BIT(20) \|
198		− BIT(21) \| BIT(22) \| BIT(23),
199		− },
200		−};
201		−
202		−static const struct sirfsoc_padmux lcd_24bits_padmux = {
203		− .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
204		− .muxmask = lcd_24bits_muxmask,
205		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
206		− .funcmask = BIT(4),
207		− .funcval = 0,
208		−};
209		−
210		−static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23,
211		− 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
212		− 110, 111, 112, 113, 114 };
213		−
214		−static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
215		− {
216		− .group = 3,
217		− .mask = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \|
218		− BIT(6) \| BIT(7) \| BIT(8) \| BIT(9) \| BIT(10) \| BIT(11) \|
219		− BIT(12) \| BIT(13) \| BIT(14) \| BIT(15) \| BIT(16) \|
220		− BIT(17) \| BIT(18),
221		− }, {
222		− .group = 2,
223		− .mask = BIT(31),
224		− }, {
225		− .group = 0,
226		− .mask = BIT(23),
227		− },
228		−};
229		−
230		−static const struct sirfsoc_padmux lcdrom_padmux = {
231		− .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
232		− .muxmask = lcdrom_muxmask,
233		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
234		− .funcmask = BIT(4),
235		− .funcval = BIT(4),
236		−};
237		−
238		−static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102,
239		− 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
240		−
241		−static const struct sirfsoc_muxmask uart0_muxmask[] = {
242		− {
243		− .group = 2,
244		− .mask = BIT(4) \| BIT(5),
245		− }, {
246		− .group = 1,
247		− .mask = BIT(23) \| BIT(28),
248		− },
249		−};
250		−
251		−static const struct sirfsoc_padmux uart0_padmux = {
252		− .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
253		− .muxmask = uart0_muxmask,
254		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
255		− .funcmask = BIT(9),
256		− .funcval = BIT(9),
257		−};
258		−
259		−static const unsigned uart0_pins[] = { 55, 60, 68, 69 };
260		−
261		−static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
262		− {
263		− .group = 2,
264		− .mask = BIT(4) \| BIT(5),
265		− },
266		−};
267		−
268		−static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
269		− .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
270		− .muxmask = uart0_nostreamctrl_muxmask,
271		−};
272		−
273		−static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
274		−
275		−static const struct sirfsoc_muxmask uart1_muxmask[] = {
276		− {
277		− .group = 1,
278		− .mask = BIT(15) \| BIT(17),
279		− },
280		−};
281		−
282		−static const struct sirfsoc_padmux uart1_padmux = {
283		− .muxmask_counts = ARRAY_SIZE(uart1_muxmask),
284		− .muxmask = uart1_muxmask,
285		−};
286		−
287		−static const unsigned uart1_pins[] = { 47, 49 };
288		−
289		−static const struct sirfsoc_muxmask uart2_muxmask[] = {
290		− {
291		− .group = 1,
292		− .mask = BIT(16) \| BIT(18) \| BIT(24) \| BIT(27),
293		− },
294		−};
295		−
296		−static const struct sirfsoc_padmux uart2_padmux = {
297		− .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
298		− .muxmask = uart2_muxmask,
299		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
300		− .funcmask = BIT(10),
301		− .funcval = BIT(10),
302		−};
303		−
304		−static const unsigned uart2_pins[] = { 48, 50, 56, 59 };
305		−
306		−static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
307		− {
308		− .group = 1,
309		− .mask = BIT(16) \| BIT(18),
310		− },
311		−};
312		−
313		−static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
314		− .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
315		− .muxmask = uart2_nostreamctrl_muxmask,
316		−};
317		−
318		−static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
319		−
320		−static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
321		− {
322		− .group = 0,
323		− .mask = BIT(30) \| BIT(31),
324		− }, {
325		− .group = 1,
326		− .mask = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3),
327		− },
328		−};
329		−
330		−static const struct sirfsoc_padmux sdmmc3_padmux = {
331		− .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
332		− .muxmask = sdmmc3_muxmask,
333		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
334		− .funcmask = BIT(7),
335		− .funcval = 0,
336		−};
337		−
338		−static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
339		−
340		−static const struct sirfsoc_muxmask spi0_muxmask[] = {
341		− {
342		− .group = 1,
343		− .mask = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3),
344		− },
345		−};
346		−
347		−static const struct sirfsoc_padmux spi0_padmux = {
348		− .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
349		− .muxmask = spi0_muxmask,
350		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
351		− .funcmask = BIT(7),
352		− .funcval = BIT(7),
353		−};
354		−
355		−static const unsigned spi0_pins[] = { 32, 33, 34, 35 };
356		−
357		−static const struct sirfsoc_muxmask sdmmc4_muxmask[] = {
358		− {
359		− .group = 1,
360		− .mask = BIT(4) \| BIT(5) \| BIT(6) \| BIT(7) \| BIT(8) \| BIT(9),
361		− },
362		−};
363		−
364		−static const struct sirfsoc_padmux sdmmc4_padmux = {
365		− .muxmask_counts = ARRAY_SIZE(sdmmc4_muxmask),
366		− .muxmask = sdmmc4_muxmask,
367		−};
368		−
369		−static const unsigned sdmmc4_pins[] = { 36, 37, 38, 39, 40, 41 };
370		−
371		−static const struct sirfsoc_muxmask cko1_muxmask[] = {
372		− {
373		− .group = 1,
374		− .mask = BIT(10),
375		− },
376		−};
377		−
378		−static const struct sirfsoc_padmux cko1_padmux = {
379		− .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
380		− .muxmask = cko1_muxmask,
381		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
382		− .funcmask = BIT(3),
383		− .funcval = 0,
384		−};
385		−
386		−static const unsigned cko1_pins[] = { 42 };
387		−
388		−static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
389		− {
390		− .group = 1,
391		− .mask = BIT(10),
392		− },
393		−};
394		−
395		−static const struct sirfsoc_padmux i2s_mclk_padmux = {
396		− .muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
397		− .muxmask = i2s_mclk_muxmask,
398		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
399		− .funcmask = BIT(3),
400		− .funcval = BIT(3),
401		−};
402		−
403		−static const unsigned i2s_mclk_pins[] = { 42 };
404		−
405		−static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = {
406		− {
407		− .group = 1,
408		− .mask = BIT(19),
409		− },
410		−};
411		−
412		−static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = {
413		− .muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask),
414		− .muxmask = i2s_ext_clk_input_muxmask,
415		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
416		− .funcmask = BIT(2),
417		− .funcval = BIT(2),
418		−};
419		−
420		−static const unsigned i2s_ext_clk_input_pins[] = { 51 };
421		−
422		−static const struct sirfsoc_muxmask i2s_muxmask[] = {
423		− {
424		− .group = 1,
425		− .mask = BIT(11) \| BIT(12) \| BIT(13) \| BIT(14),
426		− },
427		−};
428		−
429		−static const struct sirfsoc_padmux i2s_padmux = {
430		− .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
431		− .muxmask = i2s_muxmask,
432		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
433		−};
434		−
435		−static const unsigned i2s_pins[] = { 43, 44, 45, 46 };
436		−
437		−static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
438		− {
439		− .group = 1,
440		− .mask = BIT(11) \| BIT(12) \| BIT(14),
441		− },
442		−};
443		−
444		−static const struct sirfsoc_padmux i2s_no_din_padmux = {
445		− .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
446		− .muxmask = i2s_no_din_muxmask,
447		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
448		−};
449		−
450		−static const unsigned i2s_no_din_pins[] = { 43, 44, 46 };
451		−
452		−static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
453		− {
454		− .group = 1,
455		− .mask = BIT(11) \| BIT(12) \| BIT(13) \| BIT(14)
456		− \| BIT(23) \| BIT(28),
457		− },
458		−};
459		−
460		−static const struct sirfsoc_padmux i2s_6chn_padmux = {
461		− .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
462		− .muxmask = i2s_6chn_muxmask,
463		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
464		− .funcmask = BIT(1) \| BIT(9),
465		− .funcval = BIT(1) \| BIT(9),
466		−};
467		−
468		−static const unsigned i2s_6chn_pins[] = { 43, 44, 45, 46, 55, 60 };
469		−
470		−static const struct sirfsoc_muxmask ac97_muxmask[] = {
471		− {
472		− .group = 1,
473		− .mask = BIT(11) \| BIT(12) \| BIT(13) \| BIT(14),
474		− },
475		−};
476		−
477		−static const struct sirfsoc_padmux ac97_padmux = {
478		− .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
479		− .muxmask = ac97_muxmask,
480		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
481		− .funcmask = BIT(8),
482		− .funcval = 0,
483		−};
484		−
485		−static const unsigned ac97_pins[] = { 43, 44, 45, 46 };
486		−
487		−static const struct sirfsoc_muxmask spi1_muxmask[] = {
488		− {
489		− .group = 1,
490		− .mask = BIT(11) \| BIT(12) \| BIT(13) \| BIT(14),
491		− },
492		−};
493		−
494		−static const struct sirfsoc_padmux spi1_padmux = {
495		− .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
496		− .muxmask = spi1_muxmask,
497		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
498		− .funcmask = BIT(8),
499		− .funcval = BIT(8),
500		−};
501		−
502		−static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
503		−
504		−static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
505		− {
506		− .group = 0,
507		− .mask = BIT(27) \| BIT(28) \| BIT(29),
508		− },
509		−};
510		−
511		−static const struct sirfsoc_padmux sdmmc1_padmux = {
512		− .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
513		− .muxmask = sdmmc1_muxmask,
514		−};
515		−
516		−static const unsigned sdmmc1_pins[] = { 27, 28, 29 };
517		−
518		−static const struct sirfsoc_muxmask gps_muxmask[] = {
519		− {
520		− .group = 0,
521		− .mask = BIT(24) \| BIT(25) \| BIT(26),
522		− },
523		−};
524		−
525		−static const struct sirfsoc_padmux gps_padmux = {
526		− .muxmask_counts = ARRAY_SIZE(gps_muxmask),
527		− .muxmask = gps_muxmask,
528		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
529		− .funcmask = BIT(12) \| BIT(13) \| BIT(14),
530		− .funcval = BIT(12),
531		−};
532		−
533		−static const unsigned gps_pins[] = { 24, 25, 26 };
534		−
535		−static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
536		− {
537		− .group = 0,
538		− .mask = BIT(24) \| BIT(25) \| BIT(26),
539		− },
540		−};
541		−
542		−static const struct sirfsoc_padmux sdmmc5_padmux = {
543		− .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
544		− .muxmask = sdmmc5_muxmask,
545		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
546		− .funcmask = BIT(13) \| BIT(14),
547		− .funcval = BIT(13) \| BIT(14),
548		−};
549		−
550		−static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
551		−
552		−static const struct sirfsoc_muxmask usp0_muxmask[] = {
553		− {
554		− .group = 1,
555		− .mask = BIT(19) \| BIT(20) \| BIT(21) \| BIT(22) \| BIT(23),
556		− },
557		−};
558		−
559		−static const struct sirfsoc_padmux usp0_padmux = {
560		− .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
561		− .muxmask = usp0_muxmask,
562		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
563		− .funcmask = BIT(1) \| BIT(2) \| BIT(6) \| BIT(9),
564		− .funcval = 0,
565		−};
566		−
567		−static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
568		−
569		−static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = {
570		− {
571		− .group = 1,
572		− .mask = BIT(19) \| BIT(20) \| BIT(21) \| BIT(22),
573		− },
574		−};
575		−
576		−static const struct sirfsoc_padmux usp0_only_utfs_padmux = {
577		− .muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask),
578		− .muxmask = usp0_only_utfs_muxmask,
579		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
580		− .funcmask = BIT(1) \| BIT(2) \| BIT(6),
581		− .funcval = 0,
582		−};
583		−
584		−static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 };
585		−
586		−static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = {
587		− {
588		− .group = 1,
589		− .mask = BIT(19) \| BIT(20) \| BIT(21) \| BIT(23),
590		− },
591		−};
592		−
593		−static const struct sirfsoc_padmux usp0_only_urfs_padmux = {
594		− .muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask),
595		− .muxmask = usp0_only_urfs_muxmask,
596		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
597		− .funcmask = BIT(1) \| BIT(2) \| BIT(9),
598		− .funcval = 0,
599		−};
600		−
601		−static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 };
602		−
603		−static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
604		− {
605		− .group = 1,
606		− .mask = BIT(20) \| BIT(21),
607		− },
608		−};
609		−
610		−static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
611		− .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
612		− .muxmask = usp0_uart_nostreamctrl_muxmask,
613		−};
614		−
615		−static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
616		−
617		−static const struct sirfsoc_muxmask usp1_muxmask[] = {
618		− {
619		− .group = 1,
620		− .mask = BIT(24) \| BIT(25) \| BIT(26) \| BIT(27) \| BIT(28),
621		− },
622		−};
623		−
624		−static const struct sirfsoc_padmux usp1_padmux = {
625		− .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
626		− .muxmask = usp1_muxmask,
627		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
628		− .funcmask = BIT(1) \| BIT(9) \| BIT(10) \| BIT(11),
629		− .funcval = 0,
630		−};
631		−
632		−static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 };
633		−
634		−static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
635		− {
636		− .group = 1,
637		− .mask = BIT(25) \| BIT(26),
638		− },
639		−};
640		−
641		−static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
642		− .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
643		− .muxmask = usp1_uart_nostreamctrl_muxmask,
644		−};
645		−
646		−static const unsigned usp1_uart_nostreamctrl_pins[] = { 57, 58 };
647		−
648		−static const struct sirfsoc_muxmask usp2_muxmask[] = {
649		− {
650		− .group = 1,
651		− .mask = BIT(29) \| BIT(30) \| BIT(31),
652		− }, {
653		− .group = 2,
654		− .mask = BIT(0) \| BIT(1),
655		− },
656		−};
657		−
658		−static const struct sirfsoc_padmux usp2_padmux = {
659		− .muxmask_counts = ARRAY_SIZE(usp2_muxmask),
660		− .muxmask = usp2_muxmask,
661		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
662		− .funcmask = BIT(13) \| BIT(14),
663		− .funcval = 0,
664		−};
665		−
666		−static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 };
667		−
668		−static const struct sirfsoc_muxmask usp2_uart_nostreamctrl_muxmask[] = {
669		− {
670		− .group = 1,
671		− .mask = BIT(30) \| BIT(31),
672		− },
673		−};
674		−
675		−static const struct sirfsoc_padmux usp2_uart_nostreamctrl_padmux = {
676		− .muxmask_counts = ARRAY_SIZE(usp2_uart_nostreamctrl_muxmask),
677		− .muxmask = usp2_uart_nostreamctrl_muxmask,
678		−};
679		−
680		−static const unsigned usp2_uart_nostreamctrl_pins[] = { 62, 63 };
681		−
682		−static const struct sirfsoc_muxmask nand_muxmask[] = {
683		− {
684		− .group = 2,
685		− .mask = BIT(2) \| BIT(3) \| BIT(28) \| BIT(29) \| BIT(30),
686		− },
687		−};
688		−
689		−static const struct sirfsoc_padmux nand_padmux = {
690		− .muxmask_counts = ARRAY_SIZE(nand_muxmask),
691		− .muxmask = nand_muxmask,
692		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
693		− .funcmask = BIT(5),
694		− .funcval = 0,
695		−};
696		−
697		−static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 };
698		−
699		−static const struct sirfsoc_padmux sdmmc0_padmux = {
700		− .muxmask_counts = 0,
701		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
702		− .funcmask = BIT(5),
703		− .funcval = 0,
704		−};
705		−
706		−static const unsigned sdmmc0_pins[] = { };
707		−
708		−static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
709		− {
710		− .group = 2,
711		− .mask = BIT(2) \| BIT(3),
712		− },
713		−};
714		−
715		−static const struct sirfsoc_padmux sdmmc2_padmux = {
716		− .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
717		− .muxmask = sdmmc2_muxmask,
718		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
719		− .funcmask = BIT(5),
720		− .funcval = BIT(5),
721		−};
722		−
723		−static const unsigned sdmmc2_pins[] = { 66, 67 };
724		−
725		−static const struct sirfsoc_muxmask cko0_muxmask[] = {
726		− {
727		− .group = 2,
728		− .mask = BIT(14),
729		− },
730		−};
731		−
732		−static const struct sirfsoc_padmux cko0_padmux = {
733		− .muxmask_counts = ARRAY_SIZE(cko0_muxmask),
734		− .muxmask = cko0_muxmask,
735		−};
736		−
737		−static const unsigned cko0_pins[] = { 78 };
738		−
739		−static const struct sirfsoc_muxmask vip_muxmask[] = {
740		− {
741		− .group = 2,
742		− .mask = BIT(15) \| BIT(16) \| BIT(17) \| BIT(18) \| BIT(19)
743		− \| BIT(20) \| BIT(21) \| BIT(22) \| BIT(23) \| BIT(24) \|
744		− BIT(25),
745		− },
746		−};
747		−
748		−static const struct sirfsoc_padmux vip_padmux = {
749		− .muxmask_counts = ARRAY_SIZE(vip_muxmask),
750		− .muxmask = vip_muxmask,
751		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
752		− .funcmask = BIT(0),
753		− .funcval = 0,
754		−};
755		−
756		−static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87,
757		− 88, 89 };
758		−
759		−static const struct sirfsoc_muxmask i2c0_muxmask[] = {
760		− {
761		− .group = 2,
762		− .mask = BIT(26) \| BIT(27),
763		− },
764		−};
765		−
766		−static const struct sirfsoc_padmux i2c0_padmux = {
767		− .muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
768		− .muxmask = i2c0_muxmask,
769		−};
770		−
771		−static const unsigned i2c0_pins[] = { 90, 91 };
772		−
773		−static const struct sirfsoc_muxmask i2c1_muxmask[] = {
774		− {
775		− .group = 0,
776		− .mask = BIT(13) \| BIT(15),
777		− },
778		−};
779		−
780		−static const struct sirfsoc_padmux i2c1_padmux = {
781		− .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
782		− .muxmask = i2c1_muxmask,
783		−};
784		−
785		−static const unsigned i2c1_pins[] = { 13, 15 };
786		−
787		−static const struct sirfsoc_muxmask viprom_muxmask[] = {
788		− {
789		− .group = 2,
790		− .mask = BIT(15) \| BIT(16) \| BIT(17) \| BIT(18) \| BIT(19)
791		− \| BIT(20) \| BIT(21) \| BIT(22) \| BIT(23) \| BIT(24) \|
792		− BIT(25),
793		− }, {
794		− .group = 0,
795		− .mask = BIT(12),
796		− },
797		−};
798		−
799		−static const struct sirfsoc_padmux viprom_padmux = {
800		− .muxmask_counts = ARRAY_SIZE(viprom_muxmask),
801		− .muxmask = viprom_muxmask,
802		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
803		− .funcmask = BIT(0),
804		− .funcval = BIT(0),
805		−};
806		−
807		−static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86,
808		− 87, 88, 89 };
809		−
810		−static const struct sirfsoc_muxmask pwm0_muxmask[] = {
811		− {
812		− .group = 0,
813		− .mask = BIT(4),
814		− },
815		−};
816		−
817		−static const struct sirfsoc_padmux pwm0_padmux = {
818		− .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
819		− .muxmask = pwm0_muxmask,
820		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
821		− .funcmask = BIT(12),
822		− .funcval = 0,
823		−};
824		−
825		−static const unsigned pwm0_pins[] = { 4 };
826		−
827		−static const struct sirfsoc_muxmask pwm1_muxmask[] = {
828		− {
829		− .group = 0,
830		− .mask = BIT(5),
831		− },
832		−};
833		−
834		−static const struct sirfsoc_padmux pwm1_padmux = {
835		− .muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
836		− .muxmask = pwm1_muxmask,
837		−};
838		−
839		−static const unsigned pwm1_pins[] = { 5 };
840		−
841		−static const struct sirfsoc_muxmask pwm2_muxmask[] = {
842		− {
843		− .group = 0,
844		− .mask = BIT(6),
845		− },
846		−};
847		−
848		−static const struct sirfsoc_padmux pwm2_padmux = {
849		− .muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
850		− .muxmask = pwm2_muxmask,
851		−};
852		−
853		−static const unsigned pwm2_pins[] = { 6 };
854		−
855		−static const struct sirfsoc_muxmask pwm3_muxmask[] = {
856		− {
857		− .group = 0,
858		− .mask = BIT(7),
859		− },
860		−};
861		−
862		−static const struct sirfsoc_padmux pwm3_padmux = {
863		− .muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
864		− .muxmask = pwm3_muxmask,
865		−};
866		−
867		−static const unsigned pwm3_pins[] = { 7 };
868		−
869		−static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
870		− {
871		− .group = 0,
872		− .mask = BIT(8),
873		− },
874		−};
875		−
876		−static const struct sirfsoc_padmux warm_rst_padmux = {
877		− .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
878		− .muxmask = warm_rst_muxmask,
879		−};
880		−
881		−static const unsigned warm_rst_pins[] = { 8 };
882		−
883		−static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = {
884		− {
885		− .group = 1,
886		− .mask = BIT(22),
887		− },
888		−};
889		−static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = {
890		− .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask),
891		− .muxmask = usb0_utmi_drvbus_muxmask,
892		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
893		− .funcmask = BIT(6),
894		− .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */
895		−};
896		−
897		−static const unsigned usb0_utmi_drvbus_pins[] = { 54 };
898		−
899		−static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
900		− {
901		− .group = 1,
902		− .mask = BIT(27),
903		− },
904		−};
905		−
906		−static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
907		− .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
908		− .muxmask = usb1_utmi_drvbus_muxmask,
909		− .ctrlreg = SIRFSOC_RSC_PIN_MUX,
910		− .funcmask = BIT(11),
911		− .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
912		−};
913		−
914		−static const unsigned usb1_utmi_drvbus_pins[] = { 59 };
915		−
916		−static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
917		− .muxmask_counts = 0,
918		− .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
919		− .funcmask = BIT(2),
920		− .funcval = BIT(2),
921		−};
922		−
923		−static const unsigned usb1_dp_dn_pins[] = { 115, 116 };
924		−
925		−static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
926		− .muxmask_counts = 0,
927		− .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
928		− .funcmask = BIT(2),
929		− .funcval = 0,
930		−};
931		−
932		−static const unsigned uart1_route_io_usb1_pins[] = { 115, 116 };
933		−
934		−static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
935		− {
936		− .group = 0,
937		− .mask = BIT(9) \| BIT(10) \| BIT(11),
938		− },
939		−};
940		−
941		−static const struct sirfsoc_padmux pulse_count_padmux = {
942		− .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
943		− .muxmask = pulse_count_muxmask,
944		−};
945		−
946		−static const unsigned pulse_count_pins[] = { 9, 10, 11 };
947		−
948		−static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
949		− SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
950		− SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
951		− SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
952		− SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
953		− SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
954		− SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
955		− SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
956		− SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
957		− SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
958		− SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
959		− SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
960		− usp0_uart_nostreamctrl_pins),
961		− SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins),
962		− SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins),
963		− SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
964		− SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
965		− usp1_uart_nostreamctrl_pins),
966		− SIRFSOC_PIN_GROUP("usp2grp", usp2_pins),
967		− SIRFSOC_PIN_GROUP("usp2_uart_nostreamctrl_grp",
968		− usp2_uart_nostreamctrl_pins),
969		− SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
970		− SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
971		− SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
972		− SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
973		− SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
974		− SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
975		− SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
976		− SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins),
977		− SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
978		− SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
979		− SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
980		− SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
981		− SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
982		− SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
983		− SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
984		− SIRFSOC_PIN_GROUP("sdmmc4grp", sdmmc4_pins),
985		− SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
986		− SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins),
987		− SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
988		− SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
989		− SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
990		− SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
991		− SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
992		− SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins),
993		− SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
994		− SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
995		− SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
996		− SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
997		− SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
998		− SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
999		− SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
1000		− SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
1001		−};
1002		−
1003		−static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
1004		−static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
1005		−static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
1006		−static const char * const lcdromgrp[] = { "lcdromgrp" };
1007		−static const char * const uart0grp[] = { "uart0grp" };
1008		−static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
1009		−static const char * const uart1grp[] = { "uart1grp" };
1010		−static const char * const uart2grp[] = { "uart2grp" };
1011		−static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
1012		−static const char * const usp0grp[] = { "usp0grp" };
1013		−static const char * const usp0_uart_nostreamctrl_grp[] = {
1014		− "usp0_uart_nostreamctrl_grp"
1015		−};
1016		−static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
1017		−static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
1018		−static const char * const usp1grp[] = { "usp1grp" };
1019		−static const char * const usp1_uart_nostreamctrl_grp[] = {
1020		− "usp1_uart_nostreamctrl_grp"
1021		−};
1022		−static const char * const usp2grp[] = { "usp2grp" };
1023		−static const char * const usp2_uart_nostreamctrl_grp[] = {
1024		− "usp2_uart_nostreamctrl_grp"
1025		−};
1026		−static const char * const i2c0grp[] = { "i2c0grp" };
1027		−static const char * const i2c1grp[] = { "i2c1grp" };
1028		−static const char * const pwm0grp[] = { "pwm0grp" };
1029		−static const char * const pwm1grp[] = { "pwm1grp" };
1030		−static const char * const pwm2grp[] = { "pwm2grp" };
1031		−static const char * const pwm3grp[] = { "pwm3grp" };
1032		−static const char * const vipgrp[] = { "vipgrp" };
1033		−static const char * const vipromgrp[] = { "vipromgrp" };
1034		−static const char * const warm_rstgrp[] = { "warm_rstgrp" };
1035		−static const char * const cko0grp[] = { "cko0grp" };
1036		−static const char * const cko1grp[] = { "cko1grp" };
1037		−static const char * const sdmmc0grp[] = { "sdmmc0grp" };
1038		−static const char * const sdmmc1grp[] = { "sdmmc1grp" };
1039		−static const char * const sdmmc2grp[] = { "sdmmc2grp" };
1040		−static const char * const sdmmc3grp[] = { "sdmmc3grp" };
1041		−static const char * const sdmmc4grp[] = { "sdmmc4grp" };
1042		−static const char * const sdmmc5grp[] = { "sdmmc5grp" };
1043		−static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
1044		−static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
1045		−static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
1046		−static const char * const
1047		− uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
1048		−static const char * const pulse_countgrp[] = { "pulse_countgrp" };
1049		−static const char * const i2smclkgrp[] = { "i2smclkgrp" };
1050		−static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" };
1051		−static const char * const i2sgrp[] = { "i2sgrp" };
1052		−static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
1053		−static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
1054		−static const char * const ac97grp[] = { "ac97grp" };
1055		−static const char * const nandgrp[] = { "nandgrp" };
1056		−static const char * const spi0grp[] = { "spi0grp" };
1057		−static const char * const spi1grp[] = { "spi1grp" };
1058		−static const char * const gpsgrp[] = { "gpsgrp" };
1059		−
1060		−static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
1061		− SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
1062		− SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
1063		− SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
1064		− SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
1065		− SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
1066		− SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl",
1067		− uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux),
1068		− SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
1069		− SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
1070		− SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl",
1071		− uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
1072		− SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
1073		− SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
1074		− usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux),
1075		− SIRFSOC_PMX_FUNCTION("usp0_only_utfs",
1076		− usp0_only_utfs_grp, usp0_only_utfs_padmux),
1077		− SIRFSOC_PMX_FUNCTION("usp0_only_urfs",
1078		− usp0_only_urfs_grp, usp0_only_urfs_padmux),
1079		− SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
1080		− SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
1081		− usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux),
1082		− SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux),
1083		− SIRFSOC_PMX_FUNCTION("usp2_uart_nostreamctrl",
1084		− usp2_uart_nostreamctrl_grp, usp2_uart_nostreamctrl_padmux),
1085		− SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
1086		− SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
1087		− SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
1088		− SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
1089		− SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
1090		− SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
1091		− SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
1092		− SIRFSOC_PMX_FUNCTION("viprom", vipromgrp, viprom_padmux),
1093		− SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
1094		− SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
1095		− SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
1096		− SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
1097		− SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
1098		− SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
1099		− SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
1100		− SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux),
1101		− SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
1102		− SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus",
1103		− usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
1104		− SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus",
1105		− usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
1106		− SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
1107		− SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
1108		− uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
1109		− SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
1110		− SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
1111		− SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp,
1112		− i2s_ext_clk_input_padmux),
1113		− SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
1114		− SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
1115		− SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
1116		− SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
1117		− SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
1118		− SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
1119		− SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
1120		− SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
1121		−};
1122		−
1123		−struct sirfsoc_pinctrl_data prima2_pinctrl_data = {
1124		− (struct pinctrl_pin_desc *)sirfsoc_pads,
1125		− ARRAY_SIZE(sirfsoc_pads),
1126		− (struct sirfsoc_pin_group *)sirfsoc_pin_groups,
1127		− ARRAY_SIZE(sirfsoc_pin_groups),
1128		− (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
1129		− ARRAY_SIZE(sirfsoc_pmx_functions),
1130		−};
1131		−

drivers/pinctrl/sirf/pinctrl-sirf.c+0−894

@@ -1,894 +0,0 @@
1		−// SPDX-License-Identifier: GPL-2.0-or-later
2		−/*
3		− * pinmux driver for CSR SiRFprimaII
4		− *
5		− * Authors:
6		− * Rongjun Ying <rongjun.ying@csr.com>
7		− * Yuping Luo <yuping.luo@csr.com>
8		− * Barry Song <baohua.song@csr.com>
9		− *
10		− * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
11		− * company.
12		− */
13		−
14		−#include <linux/init.h>
15		−#include <linux/irq.h>
16		−#include <linux/platform_device.h>
17		−#include <linux/io.h>
18		−#include <linux/slab.h>
19		−#include <linux/err.h>
20		−#include <linux/pinctrl/pinctrl.h>
21		−#include <linux/pinctrl/pinmux.h>
22		−#include <linux/pinctrl/consumer.h>
23		−#include <linux/pinctrl/machine.h>
24		−#include <linux/of.h>
25		−#include <linux/of_address.h>
26		−#include <linux/of_device.h>
27		−#include <linux/of_platform.h>
28		−#include <linux/bitops.h>
29		−#include <linux/gpio/driver.h>
30		−#include <linux/of_gpio.h>
31		−
32		−#include "pinctrl-sirf.h"
33		−
34		−#define DRIVER_NAME "pinmux-sirf"
35		−
36		−struct sirfsoc_gpio_bank {
37		− int id;
38		− int parent_irq;
39		− spinlock_t lock;
40		−};
41		−
42		−struct sirfsoc_gpio_chip {
43		− struct of_mm_gpio_chip chip;
44		− struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
45		− spinlock_t lock;
46		−};
47		−
48		−static struct sirfsoc_pin_group *sirfsoc_pin_groups;
49		−static int sirfsoc_pingrp_cnt;
50		−
51		−static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
52		−{
53		− return sirfsoc_pingrp_cnt;
54		−}
55		−
56		−static const char sirfsoc_get_group_name(struct pinctrl_dev pctldev,
57		− unsigned selector)
58		−{
59		− return sirfsoc_pin_groups[selector].name;
60		−}
61		−
62		−static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev,
63		− unsigned selector,
64		− const unsigned **pins,
65		− unsigned *num_pins)
66		−{
67		− *pins = sirfsoc_pin_groups[selector].pins;
68		− *num_pins = sirfsoc_pin_groups[selector].num_pins;
69		− return 0;
70		−}
71		−
72		−static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev,
73		− struct seq_file *s, unsigned offset)
74		−{
75		− seq_printf(s, " " DRIVER_NAME);
76		−}
77		−
78		−static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
79		− struct device_node *np_config,
80		− struct pinctrl_map *map, unsigned num_maps)
81		−{
82		− struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
83		− struct device_node *np;
84		− struct property *prop;
85		− const char function, group;
86		− int ret, index = 0, count = 0;
87		−
88		− /* calculate number of maps required */
89		− for_each_child_of_node(np_config, np) {
90		− ret = of_property_read_string(np, "sirf,function", &function);
91		− if (ret < 0) {
92		− of_node_put(np);
93		− return ret;
94		− }
95		−
96		− ret = of_property_count_strings(np, "sirf,pins");
97		− if (ret < 0) {
98		− of_node_put(np);
99		− return ret;
100		− }
101		−
102		− count += ret;
103		− }
104		−
105		− if (!count) {
106		− dev_err(spmx->dev, "No child nodes passed via DT\n");
107		− return -ENODEV;
108		− }
109		−
110		− map = kcalloc(count, sizeof(*map), GFP_KERNEL);
111		− if (!*map)
112		− return -ENOMEM;
113		−
114		− for_each_child_of_node(np_config, np) {
115		− of_property_read_string(np, "sirf,function", &function);
116		− of_property_for_each_string(np, "sirf,pins", prop, group) {
117		− (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
118		− (*map)[index].data.mux.group = group;
119		− (*map)[index].data.mux.function = function;
120		− index++;
121		− }
122		− }
123		−
124		− *num_maps = count;
125		−
126		− return 0;
127		−}
128		−
129		−static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
130		− struct pinctrl_map *map, unsigned num_maps)
131		−{
132		− kfree(map);
133		−}
134		−
135		−static const struct pinctrl_ops sirfsoc_pctrl_ops = {
136		− .get_groups_count = sirfsoc_get_groups_count,
137		− .get_group_name = sirfsoc_get_group_name,
138		− .get_group_pins = sirfsoc_get_group_pins,
139		− .pin_dbg_show = sirfsoc_pin_dbg_show,
140		− .dt_node_to_map = sirfsoc_dt_node_to_map,
141		− .dt_free_map = sirfsoc_dt_free_map,
142		−};
143		−
144		−static struct sirfsoc_pmx_func *sirfsoc_pmx_functions;
145		−static int sirfsoc_pmxfunc_cnt;
146		−
147		−static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx,
148		− unsigned selector, bool enable)
149		−{
150		− int i;
151		− const struct sirfsoc_padmux *mux =
152		− sirfsoc_pmx_functions[selector].padmux;
153		− const struct sirfsoc_muxmask *mask = mux->muxmask;
154		−
155		− for (i = 0; i < mux->muxmask_counts; i++) {
156		− u32 muxval;
157		− muxval = readl(spmx->gpio_virtbase +
158		− SIRFSOC_GPIO_PAD_EN(mask[i].group));
159		− if (enable)
160		− muxval = muxval & ~mask[i].mask;
161		− else
162		− muxval = muxval \| mask[i].mask;
163		− writel(muxval, spmx->gpio_virtbase +
164		− SIRFSOC_GPIO_PAD_EN(mask[i].group));
165		− }
166		−
167		− if (mux->funcmask && enable) {
168		− u32 func_en_val;
169		−
170		− func_en_val =
171		− readl(spmx->rsc_virtbase + mux->ctrlreg);
172		− func_en_val =
173		− (func_en_val & ~mux->funcmask) \| (mux->funcval);
174		− writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg);
175		− }
176		−}
177		−
178		−static int sirfsoc_pinmux_set_mux(struct pinctrl_dev *pmxdev,
179		− unsigned selector,
180		− unsigned group)
181		−{
182		− struct sirfsoc_pmx *spmx;
183		−
184		− spmx = pinctrl_dev_get_drvdata(pmxdev);
185		− sirfsoc_pinmux_endisable(spmx, selector, true);
186		−
187		− return 0;
188		−}
189		−
190		−static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
191		−{
192		− return sirfsoc_pmxfunc_cnt;
193		−}
194		−
195		−static const char sirfsoc_pinmux_get_func_name(struct pinctrl_dev pctldev,
196		− unsigned selector)
197		−{
198		− return sirfsoc_pmx_functions[selector].name;
199		−}
200		−
201		−static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev,
202		− unsigned selector,
203		− const char * const **groups,
204		− unsigned * const num_groups)
205		−{
206		− *groups = sirfsoc_pmx_functions[selector].groups;
207		− *num_groups = sirfsoc_pmx_functions[selector].num_groups;
208		− return 0;
209		−}
210		−
211		−static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
212		− struct pinctrl_gpio_range *range, unsigned offset)
213		−{
214		− struct sirfsoc_pmx *spmx;
215		−
216		− int group = range->id;
217		−
218		− u32 muxval;
219		−
220		− spmx = pinctrl_dev_get_drvdata(pmxdev);
221		−
222		− muxval = readl(spmx->gpio_virtbase +
223		− SIRFSOC_GPIO_PAD_EN(group));
224		− muxval = muxval \| (1 << (offset - range->pin_base));
225		− writel(muxval, spmx->gpio_virtbase +
226		− SIRFSOC_GPIO_PAD_EN(group));
227		−
228		− return 0;
229		−}
230		−
231		−static const struct pinmux_ops sirfsoc_pinmux_ops = {
232		− .set_mux = sirfsoc_pinmux_set_mux,
233		− .get_functions_count = sirfsoc_pinmux_get_funcs_count,
234		− .get_function_name = sirfsoc_pinmux_get_func_name,
235		− .get_function_groups = sirfsoc_pinmux_get_groups,
236		− .gpio_request_enable = sirfsoc_pinmux_request_gpio,
237		−};
238		−
239		−static struct pinctrl_desc sirfsoc_pinmux_desc = {
240		− .name = DRIVER_NAME,
241		− .pctlops = &sirfsoc_pctrl_ops,
242		− .pmxops = &sirfsoc_pinmux_ops,
243		− .owner = THIS_MODULE,
244		−};
245		−
246		−static void __iomem *sirfsoc_rsc_of_iomap(void)
247		−{
248		− const struct of_device_id rsc_ids[] = {
249		− { .compatible = "sirf,prima2-rsc" },
250		− {}
251		− };
252		− struct device_node *np;
253		−
254		− np = of_find_matching_node(NULL, rsc_ids);
255		− if (!np)
256		− panic("unable to find compatible rsc node in dtb\n");
257		−
258		− return of_iomap(np, 0);
259		−}
260		−
261		−static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
262		− const struct of_phandle_args *gpiospec,
263		− u32 *flags)
264		−{
265		− if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
266		− return -EINVAL;
267		−
268		− if (flags)
269		− *flags = gpiospec->args[1];
270		−
271		− return gpiospec->args[0];
272		−}
273		−
274		−static const struct of_device_id pinmux_ids[] = {
275		− { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, },
276		− { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, },
277		− {}
278		−};
279		−
280		−static int sirfsoc_pinmux_probe(struct platform_device *pdev)
281		−{
282		− int ret;
283		− struct sirfsoc_pmx *spmx;
284		− struct device_node *np = pdev->dev.of_node;
285		− const struct sirfsoc_pinctrl_data *pdata;
286		−
287		− /* Create state holders etc for this driver */
288		− spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
289		− if (!spmx)
290		− return -ENOMEM;
291		−
292		− spmx->dev = &pdev->dev;
293		−
294		− platform_set_drvdata(pdev, spmx);
295		−
296		− spmx->gpio_virtbase = of_iomap(np, 0);
297		− if (!spmx->gpio_virtbase) {
298		− dev_err(&pdev->dev, "can't map gpio registers\n");
299		− return -ENOMEM;
300		− }
301		−
302		− spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();
303		− if (!spmx->rsc_virtbase) {
304		− ret = -ENOMEM;
305		− dev_err(&pdev->dev, "can't map rsc registers\n");
306		− goto out_no_rsc_remap;
307		− }
308		−
309		− pdata = of_match_node(pinmux_ids, np)->data;
310		− sirfsoc_pin_groups = pdata->grps;
311		− sirfsoc_pingrp_cnt = pdata->grps_cnt;
312		− sirfsoc_pmx_functions = pdata->funcs;
313		− sirfsoc_pmxfunc_cnt = pdata->funcs_cnt;
314		− sirfsoc_pinmux_desc.pins = pdata->pads;
315		− sirfsoc_pinmux_desc.npins = pdata->pads_cnt;
316		−
317		−
318		− /* Now register the pin controller and all pins it handles */
319		− spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);
320		− if (IS_ERR(spmx->pmx)) {
321		− dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");
322		− ret = PTR_ERR(spmx->pmx);
323		− goto out_no_pmx;
324		− }
325		−
326		− dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
327		−
328		− return 0;
329		−
330		−out_no_pmx:
331		− iounmap(spmx->rsc_virtbase);
332		−out_no_rsc_remap:
333		− iounmap(spmx->gpio_virtbase);
334		− return ret;
335		−}
336		−
337		−#ifdef CONFIG_PM_SLEEP
338		−static int sirfsoc_pinmux_suspend_noirq(struct device *dev)
339		−{
340		− int i, j;
341		− struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
342		−
343		− for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
344		− for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
345		− spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase +
346		− SIRFSOC_GPIO_CTRL(i, j));
347		− }
348		− spmx->ints_regs[i] = readl(spmx->gpio_virtbase +
349		− SIRFSOC_GPIO_INT_STATUS(i));
350		− spmx->paden_regs[i] = readl(spmx->gpio_virtbase +
351		− SIRFSOC_GPIO_PAD_EN(i));
352		− }
353		− spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
354		−
355		− for (i = 0; i < 3; i++)
356		− spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i);
357		−
358		− return 0;
359		−}
360		−
361		−static int sirfsoc_pinmux_resume_noirq(struct device *dev)
362		−{
363		− int i, j;
364		− struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
365		−
366		− for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
367		− for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
368		− writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase +
369		− SIRFSOC_GPIO_CTRL(i, j));
370		− }
371		− writel(spmx->ints_regs[i], spmx->gpio_virtbase +
372		− SIRFSOC_GPIO_INT_STATUS(i));
373		− writel(spmx->paden_regs[i], spmx->gpio_virtbase +
374		− SIRFSOC_GPIO_PAD_EN(i));
375		− }
376		− writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
377		−
378		− for (i = 0; i < 3; i++)
379		− writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i);
380		−
381		− return 0;
382		−}
383		−
384		−static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = {
385		− .suspend_noirq = sirfsoc_pinmux_suspend_noirq,
386		− .resume_noirq = sirfsoc_pinmux_resume_noirq,
387		− .freeze_noirq = sirfsoc_pinmux_suspend_noirq,
388		− .restore_noirq = sirfsoc_pinmux_resume_noirq,
389		−};
390		−#endif
391		−
392		−static struct platform_driver sirfsoc_pinmux_driver = {
393		− .driver = {
394		− .name = DRIVER_NAME,
395		− .of_match_table = pinmux_ids,
396		−#ifdef CONFIG_PM_SLEEP
397		− .pm = &sirfsoc_pinmux_pm_ops,
398		−#endif
399		− },
400		− .probe = sirfsoc_pinmux_probe,
401		−};
402		−
403		−static int __init sirfsoc_pinmux_init(void)
404		−{
405		− return platform_driver_register(&sirfsoc_pinmux_driver);
406		−}
407		−arch_initcall(sirfsoc_pinmux_init);
408		−
409		−static inline struct sirfsoc_gpio_bank *
410		−sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset)
411		−{
412		− return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE];
413		−}
414		−
415		−static inline int sirfsoc_gpio_to_bankoff(unsigned int offset)
416		−{
417		− return offset % SIRFSOC_GPIO_BANK_SIZE;
418		−}
419		−
420		−static void sirfsoc_gpio_irq_ack(struct irq_data *d)
421		−{
422		− struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
423		− struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
424		− struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
425		− int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
426		− u32 val, offset;
427		− unsigned long flags;
428		−
429		− offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
430		−
431		− spin_lock_irqsave(&sgpio->lock, flags);
432		−
433		− val = readl(sgpio->chip.regs + offset);
434		−
435		− writel(val, sgpio->chip.regs + offset);
436		−
437		− spin_unlock_irqrestore(&sgpio->lock, flags);
438		−}
439		−
440		−static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio,
441		− struct sirfsoc_gpio_bank *bank,
442		− int idx)
443		−{
444		− u32 val, offset;
445		− unsigned long flags;
446		−
447		− offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
448		−
449		− spin_lock_irqsave(&sgpio->lock, flags);
450		−
451		− val = readl(sgpio->chip.regs + offset);
452		− val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
453		− val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
454		− writel(val, sgpio->chip.regs + offset);
455		−
456		− spin_unlock_irqrestore(&sgpio->lock, flags);
457		−}
458		−
459		−static void sirfsoc_gpio_irq_mask(struct irq_data *d)
460		−{
461		− struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
462		− struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
463		− struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
464		−
465		− __sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
466		−}
467		−
468		−static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
469		−{
470		− struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
471		− struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
472		− struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
473		− int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
474		− u32 val, offset;
475		− unsigned long flags;
476		−
477		− offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
478		−
479		− spin_lock_irqsave(&sgpio->lock, flags);
480		−
481		− val = readl(sgpio->chip.regs + offset);
482		− val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
483		− val \|= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
484		− writel(val, sgpio->chip.regs + offset);
485		−
486		− spin_unlock_irqrestore(&sgpio->lock, flags);
487		−}
488		−
489		−static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
490		−{
491		− struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
492		− struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
493		− struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
494		− int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
495		− u32 val, offset;
496		− unsigned long flags;
497		−
498		− offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
499		−
500		− spin_lock_irqsave(&sgpio->lock, flags);
501		−
502		− val = readl(sgpio->chip.regs + offset);
503		− val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK \| SIRFSOC_GPIO_CTL_OUT_EN_MASK);
504		−
505		− switch (type) {
506		− case IRQ_TYPE_NONE:
507		− break;
508		− case IRQ_TYPE_EDGE_RISING:
509		− val \|= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK \|
510		− SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
511		− val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
512		− break;
513		− case IRQ_TYPE_EDGE_FALLING:
514		− val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
515		− val \|= SIRFSOC_GPIO_CTL_INTR_LOW_MASK \|
516		− SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
517		− break;
518		− case IRQ_TYPE_EDGE_BOTH:
519		− val \|= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK \|
520		− SIRFSOC_GPIO_CTL_INTR_LOW_MASK \|
521		− SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
522		− break;
523		− case IRQ_TYPE_LEVEL_LOW:
524		− val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK \|
525		− SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
526		− val \|= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;