It was noticed that on sdm845 after an MDSS suspend/resume cycle the driver can not read HW_REV registers properly (they will return 0 instead). Chaning the "iface" clock from <&gcc GCC_DISP_AHB_CLK> to <&dispcc DISP_CC_MDSS_AHB_CLK> fixes the issue.
Unified · Split
| @@ -4244,7 +4244,7 @@ · 4243 unmodified lines | ||
| 4244 | 4244 | |
| 4245 | 4245 | power-domains = <&dispcc MDSS_GDSC>; |
| 4246 | 4246 | |
| 4247 | − clocks = <&gcc GCC_DISP_AHB_CLK>, | |
| 4247 | + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, | |
| 4248 | 4248 | <&dispcc DISP_CC_MDSS_MDP_CLK>; |
| 4249 | 4249 | clock-names = "iface", "core"; |
| 4250 | 4250 | |