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Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux

Pull DRM updates from Dave Airlie: "This is the one and only next pull for 3.8, we had a regression we found last week, so I was waiting for that to resolve itself, and I ended up with some Intel fixes on top as well. Highlights: - new driver: nvidia tegra 20/30/hdmi support - radeon: add support for previously unused DMA engines, more HDMI regs, eviction speeds ups and fixes - i915: HSW support enable, agp removal on GEN6, seqno wrapping - exynos: IPP subsystem support (image post proc), HDMI - nouveau: display class reworking, nv20->40 z compression - ttm: start of locking fixes, rcu usage for lookups, - core: documentation updates, docbook integration, monotonic clock usage, move from connector to object properties" * 'drm-next' of git://people.freedesktop.org/~airlied/linux: (590 commits) drm/exynos: add gsc ipp driver drm/exynos: add rotator ipp driver drm/exynos: add fimc ipp driver drm/exynos: add iommu support for ipp drm/exynos: add ipp subsystem drm/exynos: support device tree for fimd radeon: fix regression with eviction since evict caching changes drm/radeon: add more pedantic checks in the CP DMA checker drm/radeon: bump version for CS ioctl support for async DMA drm/radeon: enable the async DMA rings in the CS ioctl drm/radeon: add VM CS parser support for async DMA on cayman/TN/SI drm/radeon/kms: add evergreen/cayman CS parser for async DMA (v2) drm/radeon/kms: add 6xx/7xx CS parser for async DMA (v2) drm/radeon: fix htile buffer size computation for command stream checker drm/radeon: fix fence locking in the pageflip callback drm/radeon: make indirect register access concurrency-safe drm/radeon: add W|RREG32_IDX for MM_INDEX|DATA based mmio accesss drm/exynos: support extended screen coordinate of fimd drm/exynos: fix x, y coordinates for right bottom pixel drm/exynos: fix fb offset calculation for plane ...

Linus Torvalds committed 13 years ago

Commit 3c2e81e2 parents 221392c 55bde6b364 files · +39036 −14981Browse files

Showing the changes to include/uapi (4 of 364 files). Show all

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4 files
  1. include/uapi/drm/drm.h +1 −0
  2. include/uapi/drm/exynos_drm.h +201 −2
  3. include/uapi/drm/i915_drm.h +6 −0
  4. include/uapi/drm/radeon_drm.h +6 −0
include/uapi/drm/drm.h+1−0
@@ -778,6 +778,7 @@ struct drm_event_vblank { · 777 unmodified lines
778#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3778#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
779#define DRM_CAP_DUMB_PREFER_SHADOW 0x4779#define DRM_CAP_DUMB_PREFER_SHADOW 0x4
780#define DRM_CAP_PRIME 0x5780#define DRM_CAP_PRIME 0x5
781#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
781 782
782#define DRM_PRIME_CAP_IMPORT 0x1783#define DRM_PRIME_CAP_IMPORT 0x1
783#define DRM_PRIME_CAP_EXPORT 0x2784#define DRM_PRIME_CAP_EXPORT 0x2
include/uapi/drm/exynos_drm.h+201−2
@@ -133,17 +133,26 @@ struct drm_exynos_g2d_cmd { · 132 unmodified lines
133 __u32 data;133 __u32 data;
134};134};
135 135
136enum drm_exynos_g2d_buf_type {
137 G2D_BUF_USERPTR = 1 << 31,
138};
139
136enum drm_exynos_g2d_event_type {140enum drm_exynos_g2d_event_type {
137 G2D_EVENT_NOT,141 G2D_EVENT_NOT,
138 G2D_EVENT_NONSTOP,142 G2D_EVENT_NONSTOP,
139 G2D_EVENT_STOP, /* not yet */143 G2D_EVENT_STOP, /* not yet */
140};144};
141 145
146struct drm_exynos_g2d_userptr {
147 unsigned long userptr;
148 unsigned long size;
149};
150
142struct drm_exynos_g2d_set_cmdlist {151struct drm_exynos_g2d_set_cmdlist {
143 __u64 cmd;152 __u64 cmd;
144 __u64 cmd_gem;153 __u64 cmd_buf;
145 __u32 cmd_nr;154 __u32 cmd_nr;
146 __u32 cmd_gem_nr;155 __u32 cmd_buf_nr;
147 156
148 /* for g2d event */157 /* for g2d event */
149 __u64 event_type;158 __u64 event_type;
@@ -154,6 +163,170 @@ struct drm_exynos_g2d_exec { · 4 unmodified lines
154 __u64 async;163 __u64 async;
155};164};
156 165
166enum drm_exynos_ops_id {
167 EXYNOS_DRM_OPS_SRC,
168 EXYNOS_DRM_OPS_DST,
169 EXYNOS_DRM_OPS_MAX,
170};
171
172struct drm_exynos_sz {
173 __u32 hsize;
174 __u32 vsize;
175};
176
177struct drm_exynos_pos {
178 __u32 x;
179 __u32 y;
180 __u32 w;
181 __u32 h;
182};
183
184enum drm_exynos_flip {
185 EXYNOS_DRM_FLIP_NONE = (0 << 0),
186 EXYNOS_DRM_FLIP_VERTICAL = (1 << 0),
187 EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1),
188};
189
190enum drm_exynos_degree {
191 EXYNOS_DRM_DEGREE_0,
192 EXYNOS_DRM_DEGREE_90,
193 EXYNOS_DRM_DEGREE_180,
194 EXYNOS_DRM_DEGREE_270,
195};
196
197enum drm_exynos_planer {
198 EXYNOS_DRM_PLANAR_Y,
199 EXYNOS_DRM_PLANAR_CB,
200 EXYNOS_DRM_PLANAR_CR,
201 EXYNOS_DRM_PLANAR_MAX,
202};
203
204/**
205 * A structure for ipp supported property list.
206 *
207 * @version: version of this structure.
208 * @ipp_id: id of ipp driver.
209 * @count: count of ipp driver.
210 * @writeback: flag of writeback supporting.
211 * @flip: flag of flip supporting.
212 * @degree: flag of degree information.
213 * @csc: flag of csc supporting.
214 * @crop: flag of crop supporting.
215 * @scale: flag of scale supporting.
216 * @refresh_min: min hz of refresh.
217 * @refresh_max: max hz of refresh.
218 * @crop_min: crop min resolution.
219 * @crop_max: crop max resolution.
220 * @scale_min: scale min resolution.
221 * @scale_max: scale max resolution.
222 */
223struct drm_exynos_ipp_prop_list {
224 __u32 version;
225 __u32 ipp_id;
226 __u32 count;
227 __u32 writeback;
228 __u32 flip;
229 __u32 degree;
230 __u32 csc;
231 __u32 crop;
232 __u32 scale;
233 __u32 refresh_min;
234 __u32 refresh_max;
235 __u32 reserved;
236 struct drm_exynos_sz crop_min;
237 struct drm_exynos_sz crop_max;
238 struct drm_exynos_sz scale_min;
239 struct drm_exynos_sz scale_max;
240};
241
242/**
243 * A structure for ipp config.
244 *
245 * @ops_id: property of operation directions.
246 * @flip: property of mirror, flip.
247 * @degree: property of rotation degree.
248 * @fmt: property of image format.
249 * @sz: property of image size.
250 * @pos: property of image position(src-cropped,dst-scaler).
251 */
252struct drm_exynos_ipp_config {
253 enum drm_exynos_ops_id ops_id;
254 enum drm_exynos_flip flip;
255 enum drm_exynos_degree degree;
256 __u32 fmt;
257 struct drm_exynos_sz sz;
258 struct drm_exynos_pos pos;
259};
260
261enum drm_exynos_ipp_cmd {
262 IPP_CMD_NONE,
263 IPP_CMD_M2M,
264 IPP_CMD_WB,
265 IPP_CMD_OUTPUT,
266 IPP_CMD_MAX,
267};
268
269/**
270 * A structure for ipp property.
271 *
272 * @config: source, destination config.
273 * @cmd: definition of command.
274 * @ipp_id: id of ipp driver.
275 * @prop_id: id of property.
276 * @refresh_rate: refresh rate.
277 */
278struct drm_exynos_ipp_property {
279 struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX];
280 enum drm_exynos_ipp_cmd cmd;
281 __u32 ipp_id;
282 __u32 prop_id;
283 __u32 refresh_rate;
284};
285
286enum drm_exynos_ipp_buf_type {
287 IPP_BUF_ENQUEUE,
288 IPP_BUF_DEQUEUE,
289};
290
291/**
292 * A structure for ipp buffer operations.
293 *
294 * @ops_id: operation directions.
295 * @buf_type: definition of buffer.
296 * @prop_id: id of property.
297 * @buf_id: id of buffer.
298 * @handle: Y, Cb, Cr each planar handle.
299 * @user_data: user data.
300 */
301struct drm_exynos_ipp_queue_buf {
302 enum drm_exynos_ops_id ops_id;
303 enum drm_exynos_ipp_buf_type buf_type;
304 __u32 prop_id;
305 __u32 buf_id;
306 __u32 handle[EXYNOS_DRM_PLANAR_MAX];
307 __u32 reserved;
308 __u64 user_data;
309};
310
311enum drm_exynos_ipp_ctrl {
312 IPP_CTRL_PLAY,
313 IPP_CTRL_STOP,
314 IPP_CTRL_PAUSE,
315 IPP_CTRL_RESUME,
316 IPP_CTRL_MAX,
317};
318
319/**
320 * A structure for ipp start/stop operations.
321 *
322 * @prop_id: id of property.
323 * @ctrl: definition of control.
324 */
325struct drm_exynos_ipp_cmd_ctrl {
326 __u32 prop_id;
327 enum drm_exynos_ipp_ctrl ctrl;
328};
329
157#define DRM_EXYNOS_GEM_CREATE 0x00330#define DRM_EXYNOS_GEM_CREATE 0x00
158#define DRM_EXYNOS_GEM_MAP_OFFSET 0x01331#define DRM_EXYNOS_GEM_MAP_OFFSET 0x01
159#define DRM_EXYNOS_GEM_MMAP 0x02332#define DRM_EXYNOS_GEM_MMAP 0x02
@@ -166,6 +339,12 @@ struct drm_exynos_g2d_exec { · 6 unmodified lines
166#define DRM_EXYNOS_G2D_SET_CMDLIST 0x21339#define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
167#define DRM_EXYNOS_G2D_EXEC 0x22340#define DRM_EXYNOS_G2D_EXEC 0x22
168 341
342/* IPP - Image Post Processing */
343#define DRM_EXYNOS_IPP_GET_PROPERTY 0x30
344#define DRM_EXYNOS_IPP_SET_PROPERTY 0x31
345#define DRM_EXYNOS_IPP_QUEUE_BUF 0x32
346#define DRM_EXYNOS_IPP_CMD_CTRL 0x33
347
169#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \348#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
170 DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)349 DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
171 350
@@ -188,8 +367,18 @@ struct drm_exynos_g2d_exec { · 16 unmodified lines
188#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \367#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
189 DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)368 DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
190 369
370#define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
371 DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list)
372#define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
373 DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property)
374#define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + \
375 DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf)
376#define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + \
377 DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl)
378
191/* EXYNOS specific events */379/* EXYNOS specific events */
192#define DRM_EXYNOS_G2D_EVENT 0x80000000380#define DRM_EXYNOS_G2D_EVENT 0x80000000
381#define DRM_EXYNOS_IPP_EVENT 0x80000001
193 382
194struct drm_exynos_g2d_event {383struct drm_exynos_g2d_event {
195 struct drm_event base;384 struct drm_event base;
@@ -200,4 +389,14 @@ struct drm_exynos_g2d_event { · 4 unmodified lines
200 __u32 reserved;389 __u32 reserved;
201};390};
202 391
392struct drm_exynos_ipp_event {
393 struct drm_event base;
394 __u64 user_data;
395 __u32 tv_sec;
396 __u32 tv_usec;
397 __u32 prop_id;
398 __u32 reserved;
399 __u32 buf_id[EXYNOS_DRM_OPS_MAX];
400};
401
203#endif /* _UAPI_EXYNOS_DRM_H_ */402#endif /* _UAPI_EXYNOS_DRM_H_ */
include/uapi/drm/i915_drm.h+6−0
@@ -306,6 +306,7 @@ typedef struct drm_i915_irq_wait { · 305 unmodified lines
306#define I915_PARAM_HAS_SEMAPHORES 20306#define I915_PARAM_HAS_SEMAPHORES 20
307#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21307#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
308#define I915_PARAM_RSVD_FOR_FUTURE_USE 22308#define I915_PARAM_RSVD_FOR_FUTURE_USE 22
309#define I915_PARAM_HAS_SECURE_BATCHES 23
309 310
310typedef struct drm_i915_getparam {311typedef struct drm_i915_getparam {
311 int param;312 int param;
@@ -671,6 +672,11 @@ struct drm_i915_gem_execbuffer2 { · 359 unmodified lines
671/** Resets the SO write offset registers for transform feedback on gen7. */672/** Resets the SO write offset registers for transform feedback on gen7. */
672#define I915_EXEC_GEN7_SOL_RESET (1<<8)673#define I915_EXEC_GEN7_SOL_RESET (1<<8)
673 674
675/** Request a privileged ("secure") batch buffer. Note only available for
676 * DRM_ROOT_ONLY | DRM_MASTER processes.
677 */
678#define I915_EXEC_SECURE (1<<9)
679
674#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)680#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
675#define i915_execbuffer2_set_context_id(eb2, context) \681#define i915_execbuffer2_set_context_id(eb2, context) \
676 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK682 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
include/uapi/drm/radeon_drm.h+6−0
@@ -913,9 +913,11 @@ struct drm_radeon_gem_va { · 912 unmodified lines
913/* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */913/* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */
914#define RADEON_CS_KEEP_TILING_FLAGS 0x01914#define RADEON_CS_KEEP_TILING_FLAGS 0x01
915#define RADEON_CS_USE_VM 0x02915#define RADEON_CS_USE_VM 0x02
916#define RADEON_CS_END_OF_FRAME 0x04 /* a hint from userspace which CS is the last one */
916/* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */917/* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */
917#define RADEON_CS_RING_GFX 0918#define RADEON_CS_RING_GFX 0
918#define RADEON_CS_RING_COMPUTE 1919#define RADEON_CS_RING_COMPUTE 1
920#define RADEON_CS_RING_DMA 2
919/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */921/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */
920/* 0 = normal, + = higher priority, - = lower priority */922/* 0 = normal, + = higher priority, - = lower priority */
921 923
@@ -966,6 +968,10 @@ struct drm_radeon_cs { · 44 unmodified lines
966#define RADEON_INFO_MAX_PIPES 0x10968#define RADEON_INFO_MAX_PIPES 0x10
967/* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock */969/* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock */
968#define RADEON_INFO_TIMESTAMP 0x11970#define RADEON_INFO_TIMESTAMP 0x11
971/* max shader engines (SE) - needed for geometry shaders, etc. */
972#define RADEON_INFO_MAX_SE 0x12
973/* max SH per SE */
974#define RADEON_INFO_MAX_SH_PER_SE 0x13
969 975
970struct drm_radeon_info {976struct drm_radeon_info {
971 uint32_t request;977 uint32_t request;