This patch is needed because the BASE-T1 uses different registers for status, control and advertisement to those already employed in the existing phy-c45 functions. Where required, genphy_c45 functions will now check whether the device supports BASE-T1 and use the specific registers instead: 45.2.7.19 BASE-T1 AN control register, 45.2.7.20 BASE-T1 AN status, 45.2.7.21 BASE-T1 AN advertisement register, 45.2.7.22 BASE-T1 AN LP Base Page ability register, 45.2.1.185 BASE-T1 PMA/PMD control register.
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| @@ -70,6 +70,7 @@ · 69 unmodified lines | |||
| 70 | #define MDIO_B10L_PMA_CTRL 2294 /* 10BASE-T1L PMA control */ | 70 | #define MDIO_B10L_PMA_CTRL 2294 /* 10BASE-T1L PMA control */ |
| 71 | #define MDIO_PMA_10T1L_STAT 2295 /* 10BASE-T1L PMA status */ | 71 | #define MDIO_PMA_10T1L_STAT 2295 /* 10BASE-T1L PMA status */ |
| 72 | #define MDIO_PCS_10T1L_CTRL 2278 /* 10BASE-T1L PCS control */ | 72 | #define MDIO_PCS_10T1L_CTRL 2278 /* 10BASE-T1L PCS control */ |
| 73 | #define MDIO_PMA_PMD_BT1 18 /* BASE-T1 PMA/PMD extended ability */ | ||
| 73 | #define MDIO_AN_T1_CTRL 512 /* BASE-T1 AN control */ | 74 | #define MDIO_AN_T1_CTRL 512 /* BASE-T1 AN control */ |
| 74 | #define MDIO_AN_T1_STAT 513 /* BASE-T1 AN status */ | 75 | #define MDIO_AN_T1_STAT 513 /* BASE-T1 AN status */ |
| 75 | #define MDIO_AN_T1_ADV_L 514 /* BASE-T1 AN advertisement register [15:0] */ | 76 | #define MDIO_AN_T1_ADV_L 514 /* BASE-T1 AN advertisement register [15:0] */ |
| @@ -78,6 +79,7 @@ · 2 unmodified lines | |||
| 78 | #define MDIO_AN_T1_LP_L 517 /* BASE-T1 AN LP Base Page ability register [15:0] */ | 79 | #define MDIO_AN_T1_LP_L 517 /* BASE-T1 AN LP Base Page ability register [15:0] */ |
| 79 | #define MDIO_AN_T1_LP_M 518 /* BASE-T1 AN LP Base Page ability register [31:16] */ | 80 | #define MDIO_AN_T1_LP_M 518 /* BASE-T1 AN LP Base Page ability register [31:16] */ |
| 80 | #define MDIO_AN_T1_LP_H 519 /* BASE-T1 AN LP Base Page ability register [47:32] */ | 81 | #define MDIO_AN_T1_LP_H 519 /* BASE-T1 AN LP Base Page ability register [47:32] */ |
| 82 | #define MDIO_PMA_PMD_BT1_CTRL 2100 /* BASE-T1 PMA/PMD control register */ | ||
| 81 | 83 | ||
| 82 | /* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */ | 84 | /* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */ |
| 83 | #define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */ | 85 | #define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */ |
| @@ -170,6 +172,7 @@ · 86 unmodified lines | |||
| 170 | #define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */ | 172 | #define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */ |
| 171 | #define MDIO_PMA_CTRL2_2_5GBT 0x0030 /* 2.5GBaseT type */ | 173 | #define MDIO_PMA_CTRL2_2_5GBT 0x0030 /* 2.5GBaseT type */ |
| 172 | #define MDIO_PMA_CTRL2_5GBT 0x0031 /* 5GBaseT type */ | 174 | #define MDIO_PMA_CTRL2_5GBT 0x0031 /* 5GBaseT type */ |
| 175 | #define MDIO_PMA_CTRL2_BASET1 0x003D /* BASE-T1 type */ | ||
| 173 | #define MDIO_PCS_CTRL2_TYPE 0x0003 /* PCS type selection */ | 176 | #define MDIO_PCS_CTRL2_TYPE 0x0003 /* PCS type selection */ |
| 174 | #define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */ | 177 | #define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */ |
| 175 | #define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */ | 178 | #define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */ |
| @@ -223,6 +226,7 @@ · 47 unmodified lines | |||
| 223 | #define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */ | 226 | #define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */ |
| 224 | #define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */ | 227 | #define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */ |
| 225 | #define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */ | 228 | #define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */ |
| 229 | #define MDIO_PMA_EXTABLE_BT1 0x0800 /* BASE-T1 ability */ | ||
| 226 | #define MDIO_PMA_EXTABLE_NBT 0x4000 /* 2.5/5GBASE-T ability */ | 230 | #define MDIO_PMA_EXTABLE_NBT 0x4000 /* 2.5/5GBASE-T ability */ |
| 227 | 231 | ||
| 228 | /* PHY XGXS lane state register. */ | 232 | /* PHY XGXS lane state register. */ |
| @@ -301,6 +305,9 @@ · 72 unmodified lines | |||
| 301 | #define MDIO_PCS_10T1L_CTRL_LB 0x4000 /* Enable PCS level loopback mode */ | 305 | #define MDIO_PCS_10T1L_CTRL_LB 0x4000 /* Enable PCS level loopback mode */ |
| 302 | #define MDIO_PCS_10T1L_CTRL_RESET 0x8000 /* PCS reset */ | 306 | #define MDIO_PCS_10T1L_CTRL_RESET 0x8000 /* PCS reset */ |
| 303 | 307 | ||
| 308 | /* BASE-T1 PMA/PMD extended ability register. */ | ||
| 309 | #define MDIO_PMA_PMD_BT1_B10L_ABLE 0x0004 /* 10BASE-T1L Ability */ | ||
| 310 | |||
| 304 | /* BASE-T1 auto-negotiation advertisement register [15:0] */ | 311 | /* BASE-T1 auto-negotiation advertisement register [15:0] */ |
| 305 | #define MDIO_AN_T1_ADV_L_PAUSE_CAP ADVERTISE_PAUSE_CAP | 312 | #define MDIO_AN_T1_ADV_L_PAUSE_CAP ADVERTISE_PAUSE_CAP |
| 306 | #define MDIO_AN_T1_ADV_L_PAUSE_ASYM ADVERTISE_PAUSE_ASYM | 313 | #define MDIO_AN_T1_ADV_L_PAUSE_ASYM ADVERTISE_PAUSE_ASYM |
| @@ -333,6 +340,9 @@ · 26 unmodified lines | |||
| 333 | #define MDIO_AN_T1_LP_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level LP Transmit Request */ | 340 | #define MDIO_AN_T1_LP_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level LP Transmit Request */ |
| 334 | #define MDIO_AN_T1_LP_H_10L_TX_HI 0x2000 /* 10BASE-T1L High Level LP Transmit Ability */ | 341 | #define MDIO_AN_T1_LP_H_10L_TX_HI 0x2000 /* 10BASE-T1L High Level LP Transmit Ability */ |
| 335 | 342 | ||
| 343 | /* BASE-T1 PMA/PMD control register */ | ||
| 344 | #define MDIO_PMA_PMD_BT1_CTRL_CFG_MST 0x4000 /* MASTER-SLAVE config value */ | ||
| 345 | |||
| 336 | /* EEE Supported/Advertisement/LP Advertisement registers. | 346 | /* EEE Supported/Advertisement/LP Advertisement registers. |
| 337 | * | 347 | * |
| 338 | * EEE capability Register (3.20), Advertisement (7.60) and | 348 | * EEE capability Register (3.20), Advertisement (7.60) and |