When we have mixed DMA32 and non DMA32 device in one system it could otherwise happen that the DMA32 device gets pages it can't work with.
Unified · Split
| @@ -63,6 +63,9 @@ static atomic_long_t allocated_pages; · 62 unmodified lines | |||
| 63 | static struct ttm_pool_type global_write_combined[MAX_ORDER]; | 63 | static struct ttm_pool_type global_write_combined[MAX_ORDER]; |
| 64 | static struct ttm_pool_type global_uncached[MAX_ORDER]; | 64 | static struct ttm_pool_type global_uncached[MAX_ORDER]; |
| 65 | 65 | ||
| 66 | static struct ttm_pool_type global_dma32_write_combined[MAX_ORDER]; | ||
| 67 | static struct ttm_pool_type global_dma32_uncached[MAX_ORDER]; | ||
| 68 | |||
| 66 | static spinlock_t shrinker_lock; | 69 | static spinlock_t shrinker_lock; |
| 67 | static struct list_head shrinker_list; | 70 | static struct list_head shrinker_list; |
| 68 | static struct shrinker mm_shrinker; | 71 | static struct shrinker mm_shrinker; |
| @@ -290,8 +293,14 @@ static struct ttm_pool_type *ttm_pool_select_type(struct ttm_pool *pool, · 221 unmodified lines | |||
| 290 | #ifdef CONFIG_X86 | 293 | #ifdef CONFIG_X86 |
| 291 | switch (caching) { | 294 | switch (caching) { |
| 292 | case ttm_write_combined: | 295 | case ttm_write_combined: |
| 296 | if (pool->use_dma32) | ||
| 297 | return &global_dma32_write_combined[order]; | ||
| 298 | |||
| 293 | return &global_write_combined[order]; | 299 | return &global_write_combined[order]; |
| 294 | case ttm_uncached: | 300 | case ttm_uncached: |
| 301 | if (pool->use_dma32) | ||
| 302 | return &global_dma32_uncached[order]; | ||
| 303 | |||
| 295 | return &global_uncached[order]; | 304 | return &global_uncached[order]; |
| 296 | default: | 305 | default: |
| 297 | break; | 306 | break; |
| @@ -570,6 +579,11 @@ int ttm_pool_debugfs(struct ttm_pool *pool, struct seq_file *m) · 272 unmodified lines | |||
| 570 | seq_puts(m, "uc\t:"); | 579 | seq_puts(m, "uc\t:"); |
| 571 | ttm_pool_debugfs_orders(global_uncached, m); | 580 | ttm_pool_debugfs_orders(global_uncached, m); |
| 572 | 581 | ||
| 582 | seq_puts(m, "wc 32\t:"); | ||
| 583 | ttm_pool_debugfs_orders(global_dma32_write_combined, m); | ||
| 584 | seq_puts(m, "uc 32\t:"); | ||
| 585 | ttm_pool_debugfs_orders(global_dma32_uncached, m); | ||
| 586 | |||
| 573 | for (i = 0; i < TTM_NUM_CACHING_TYPES; ++i) { | 587 | for (i = 0; i < TTM_NUM_CACHING_TYPES; ++i) { |
| 574 | seq_puts(m, "DMA "); | 588 | seq_puts(m, "DMA "); |
| 575 | switch (i) { | 589 | switch (i) { |
| @@ -640,6 +654,11 @@ int ttm_pool_mgr_init(unsigned long num_pages) · 64 unmodified lines | |||
| 640 | ttm_pool_type_init(&global_write_combined[i], NULL, | 654 | ttm_pool_type_init(&global_write_combined[i], NULL, |
| 641 | ttm_write_combined, i); | 655 | ttm_write_combined, i); |
| 642 | ttm_pool_type_init(&global_uncached[i], NULL, ttm_uncached, i); | 656 | ttm_pool_type_init(&global_uncached[i], NULL, ttm_uncached, i); |
| 657 | |||
| 658 | ttm_pool_type_init(&global_dma32_write_combined[i], NULL, | ||
| 659 | ttm_write_combined, i); | ||
| 660 | ttm_pool_type_init(&global_dma32_uncached[i], NULL, | ||
| 661 | ttm_uncached, i); | ||
| 643 | } | 662 | } |
| 644 | 663 | ||
| 645 | mm_shrinker.count_objects = ttm_pool_shrinker_count; | 664 | mm_shrinker.count_objects = ttm_pool_shrinker_count; |
| @@ -660,6 +679,9 @@ void ttm_pool_mgr_fini(void) · 14 unmodified lines | |||
| 660 | for (i = 0; i < MAX_ORDER; ++i) { | 679 | for (i = 0; i < MAX_ORDER; ++i) { |
| 661 | ttm_pool_type_fini(&global_write_combined[i]); | 680 | ttm_pool_type_fini(&global_write_combined[i]); |
| 662 | ttm_pool_type_fini(&global_uncached[i]); | 681 | ttm_pool_type_fini(&global_uncached[i]); |
| 682 | |||
| 683 | ttm_pool_type_fini(&global_dma32_write_combined[i]); | ||
| 684 | ttm_pool_type_fini(&global_dma32_uncached[i]); | ||
| 663 | } | 685 | } |
| 664 | 686 | ||
| 665 | unregister_shrinker(&mm_shrinker); | 687 | unregister_shrinker(&mm_shrinker); |