Pull i2c fix from Wolfram Sang: "Here is the revert for the regression of the i2c-octeon driver I mentioned last time. I wished for a bit more feedback, but all people working actively on it are in need of this patch, so here it goes" * 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: Revert "i2c: octeon: thunderx: Limit register access retries"
Unified · Split
| @@ -381,9 +381,7 @@ static int octeon_i2c_read(struct octeon_i2c *i2c, int target, · 380 unmodified lines | ||
| 381 | 381 | if (result) |
| 382 | 382 | return result; |
| 383 | 383 | |
| 384 | − data[i] = octeon_i2c_data_read(i2c, &result); | |
| 385 | − if (result) | |
| 386 | − return result; | |
| 384 | + data[i] = octeon_i2c_data_read(i2c); | |
| 387 | 385 | if (recv_len && i == 0) { |
| 388 | 386 | if (data[i] > I2C_SMBUS_BLOCK_MAX + 1) |
| 389 | 387 | return -EPROTO; |
| @@ -5,7 +5,6 @@ · 4 unmodified lines | ||
| 5 | 5 | #include <linux/i2c.h> |
| 6 | 6 | #include <linux/i2c-smbus.h> |
| 7 | 7 | #include <linux/io.h> |
| 8 | −#include <linux/iopoll.h> | |
| 9 | 8 | #include <linux/kernel.h> |
| 10 | 9 | #include <linux/pci.h> |
| 11 | 10 | |
| @@ -145,9 +144,9 @@ static inline void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 · 133 unmodified lines | ||
| 145 | 144 | u64 tmp; |
| 146 | 145 | |
| 147 | 146 | __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI(i2c)); |
| 148 | − | |
| 149 | − readq_poll_timeout(i2c->twsi_base + SW_TWSI(i2c), tmp, tmp & SW_TWSI_V, | |
| 150 | − I2C_OCTEON_EVENT_WAIT, i2c->adap.timeout); | |
| 147 | + do { | |
| 148 | + tmp = __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); | |
| 149 | + } while ((tmp & SW_TWSI_V) != 0); | |
| 151 | 150 | } |
| 152 | 151 | |
| 153 | 152 | #define octeon_i2c_ctl_write(i2c, val) \ |
| @@ -164,28 +163,24 @@ static inline void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 · 10 unmodified lines | ||
| 164 | 163 | * |
| 165 | 164 | * The I2C core registers are accessed indirectly via the SW_TWSI CSR. |
| 166 | 165 | */ |
| 167 | −static inline int octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg, | |
| 168 | − int *error) | |
| 166 | +static inline u8 octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg) | |
| 169 | 167 | { |
| 170 | 168 | u64 tmp; |
| 171 | − int ret; | |
| 172 | 169 | |
| 173 | 170 | __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI(i2c)); |
| 171 | + do { | |
| 172 | + tmp = __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); | |
| 173 | + } while ((tmp & SW_TWSI_V) != 0); | |
| 174 | 174 | |
| 175 | − ret = readq_poll_timeout(i2c->twsi_base + SW_TWSI(i2c), tmp, | |
| 176 | − tmp & SW_TWSI_V, I2C_OCTEON_EVENT_WAIT, | |
| 177 | − i2c->adap.timeout); | |
| 178 | − if (error) | |
| 179 | − *error = ret; | |
| 180 | 175 | return tmp & 0xFF; |
| 181 | 176 | } |
| 182 | 177 | |
| 183 | 178 | #define octeon_i2c_ctl_read(i2c) \ |
| 184 | − octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL, NULL) | |
| 185 | −#define octeon_i2c_data_read(i2c, error) \ | |
| 186 | − octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA, error) | |
| 179 | + octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL) | |
| 180 | +#define octeon_i2c_data_read(i2c) \ | |
| 181 | + octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA) | |
| 187 | 182 | #define octeon_i2c_stat_read(i2c) \ |
| 188 | − octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT, NULL) | |
| 183 | + octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT) | |
| 189 | 184 | |
| 190 | 185 | /** |
| 191 | 186 | * octeon_i2c_read_int - read the TWSI_INT register |