Now that 3.15 is released, this merges the 'next' branch into 'master', bringing us to the normal situation where my 'master' branch is the merge window. * accumulated work in next: (6809 commits) ufs: sb mutex merge + mutex_destroy powerpc: update comments for generic idle conversion cris: update comments for generic idle conversion idle: remove cpu_idle() forward declarations nbd: zero from and len fields in NBD_CMD_DISCONNECT. mm: convert some level-less printks to pr_* MAINTAINERS: adi-buildroot-devel is moderated MAINTAINERS: add linux-api for review of API/ABI changes mm/kmemleak-test.c: use pr_fmt for logging fs/dlm/debug_fs.c: replace seq_printf by seq_puts fs/dlm/lockspace.c: convert simple_str to kstr fs/dlm/config.c: convert simple_str to kstr mm: mark remap_file_pages() syscall as deprecated mm: memcontrol: remove unnecessary memcg argument from soft limit functions mm: memcontrol: clean up memcg zoneinfo lookup mm/memblock.c: call kmemleak directly from memblock_(alloc|free) mm/mempool.c: update the kmemleak stack trace for mempool allocations lib/radix-tree.c: update the kmemleak stack trace for radix tree allocations mm: introduce kmemleak_update_trace() mm/kmemleak.c: use %u to print ->checksum ...
Showing the changes to include/uapi/linux (14 of 5560 files). Show all
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| @@ -317,6 +317,7 @@ header-y += ppp-ioctl.h · 316 unmodified lines | ||
| 317 | 317 | header-y += ppp_defs.h |
| 318 | 318 | header-y += pps.h |
| 319 | 319 | header-y += prctl.h |
| 320 | +header-y += psci.h | |
| 320 | 321 | header-y += ptp_clock.h |
| 321 | 322 | header-y += ptrace.h |
| 322 | 323 | header-y += qnx4_fs.h |
| @@ -20,7 +20,7 @@ · 19 unmodified lines | ||
| 20 | 20 | |
| 21 | 21 | #define GFS2_MOUNT_LOCK 0 |
| 22 | 22 | #define GFS2_LIVE_LOCK 1 |
| 23 | −#define GFS2_TRANS_LOCK 2 | |
| 23 | +#define GFS2_FREEZE_LOCK 2 | |
| 24 | 24 | #define GFS2_RENAME_LOCK 3 |
| 25 | 25 | #define GFS2_CONTROL_LOCK 4 |
| 26 | 26 | #define GFS2_MOUNTED_LOCK 5 |
| @@ -462,7 +462,10 @@ struct input_keymap_entry { · 461 unmodified lines | ||
| 462 | 462 | #define KEY_VIDEO_NEXT 241 /* drive next video source */ |
| 463 | 463 | #define KEY_VIDEO_PREV 242 /* drive previous video source */ |
| 464 | 464 | #define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ |
| 465 | −#define KEY_BRIGHTNESS_ZERO 244 /* brightness off, use ambient */ | |
| 465 | +#define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual | |
| 466 | + brightness control is off, | |
| 467 | + rely on ambient */ | |
| 468 | +#define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO | |
| 466 | 469 | #define KEY_DISPLAY_OFF 245 /* display device to off state */ |
| 467 | 470 | |
| 468 | 471 | #define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */ |
| @@ -632,6 +635,7 @@ struct input_keymap_entry { · 163 unmodified lines | ||
| 632 | 635 | #define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ |
| 633 | 636 | #define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ |
| 634 | 637 | #define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ |
| 638 | +#define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE | |
| 635 | 639 | #define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ |
| 636 | 640 | #define KEY_LOGOFF 0x1b1 /* AL Logoff */ |
| 637 | 641 | |
| @@ -723,6 +727,17 @@ struct input_keymap_entry { · 85 unmodified lines | ||
| 723 | 727 | |
| 724 | 728 | #define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ |
| 725 | 729 | |
| 730 | +#define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ | |
| 731 | +#define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ | |
| 732 | +#define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */ | |
| 733 | +#define KEY_CONTROLPANEL 0x243 /* AL Control Panel */ | |
| 734 | +#define KEY_APPSELECT 0x244 /* AL Select Task/Application */ | |
| 735 | +#define KEY_SCREENSAVER 0x245 /* AL Screen Saver */ | |
| 736 | +#define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ | |
| 737 | + | |
| 738 | +#define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ | |
| 739 | +#define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ | |
| 740 | + | |
| 726 | 741 | #define BTN_TRIGGER_HAPPY 0x2c0 |
| 727 | 742 | #define BTN_TRIGGER_HAPPY1 0x2c0 |
| 728 | 743 | #define BTN_TRIGGER_HAPPY2 0x2c1 |
| @@ -171,6 +171,7 @@ struct kvm_pit_config { · 170 unmodified lines | ||
| 171 | 171 | #define KVM_EXIT_WATCHDOG 21 |
| 172 | 172 | #define KVM_EXIT_S390_TSCH 22 |
| 173 | 173 | #define KVM_EXIT_EPR 23 |
| 174 | +#define KVM_EXIT_SYSTEM_EVENT 24 | |
| 174 | 175 | |
| 175 | 176 | /* For KVM_EXIT_INTERNAL_ERROR */ |
| 176 | 177 | /* Emulate instruction failed. */ |
| @@ -301,6 +302,13 @@ struct kvm_run { · 124 unmodified lines | ||
| 301 | 302 | struct { |
| 302 | 303 | __u32 epr; |
| 303 | 304 | } epr; |
| 305 | + /* KVM_EXIT_SYSTEM_EVENT */ | |
| 306 | + struct { | |
| 307 | +#define KVM_SYSTEM_EVENT_SHUTDOWN 1 | |
| 308 | +#define KVM_SYSTEM_EVENT_RESET 2 | |
| 309 | + __u32 type; | |
| 310 | + __u64 flags; | |
| 311 | + } system_event; | |
| 304 | 312 | /* Fix the size of the union. */ |
| 305 | 313 | char padding[256]; |
| 306 | 314 | }; |
| @@ -416,6 +424,8 @@ struct kvm_s390_psw { · 109 unmodified lines | ||
| 416 | 424 | #define KVM_S390_INT_PFAULT_INIT 0xfffe0004u |
| 417 | 425 | #define KVM_S390_INT_PFAULT_DONE 0xfffe0005u |
| 418 | 426 | #define KVM_S390_MCHK 0xfffe1000u |
| 427 | +#define KVM_S390_INT_CLOCK_COMP 0xffff1004u | |
| 428 | +#define KVM_S390_INT_CPU_TIMER 0xffff1005u | |
| 419 | 429 | #define KVM_S390_INT_VIRTIO 0xffff2603u |
| 420 | 430 | #define KVM_S390_INT_SERVICE 0xffff2401u |
| 421 | 431 | #define KVM_S390_INT_EMERGENCY 0xffff1201u |
| @@ -515,6 +525,7 @@ enum { · 93 unmodified lines | ||
| 515 | 525 | kvm_ioeventfd_flag_nr_pio, |
| 516 | 526 | kvm_ioeventfd_flag_nr_deassign, |
| 517 | 527 | kvm_ioeventfd_flag_nr_virtio_ccw_notify, |
| 528 | + kvm_ioeventfd_flag_nr_fast_mmio, | |
| 518 | 529 | kvm_ioeventfd_flag_nr_max, |
| 519 | 530 | }; |
| 520 | 531 | |
| @@ -529,7 +540,7 @@ enum { · 8 unmodified lines | ||
| 529 | 540 | struct kvm_ioeventfd { |
| 530 | 541 | __u64 datamatch; |
| 531 | 542 | __u64 addr; /* legal pio/mmio address */ |
| 532 | − __u32 len; /* 1, 2, 4, or 8 bytes */ | |
| 543 | + __u32 len; /* 1, 2, 4, or 8 bytes; or 0 to ignore length */ | |
| 533 | 544 | __s32 fd; |
| 534 | 545 | __u32 flags; |
| 535 | 546 | __u8 pad[36]; |
| @@ -743,6 +754,10 @@ struct kvm_ppc_smmu_info { · 207 unmodified lines | ||
| 743 | 754 | #define KVM_CAP_IOAPIC_POLARITY_IGNORED 97 |
| 744 | 755 | #define KVM_CAP_ENABLE_CAP_VM 98 |
| 745 | 756 | #define KVM_CAP_S390_IRQCHIP 99 |
| 757 | +#define KVM_CAP_IOEVENTFD_NO_LENGTH 100 | |
| 758 | +#define KVM_CAP_VM_ATTRIBUTES 101 | |
| 759 | +#define KVM_CAP_ARM_PSCI_0_2 102 | |
| 760 | +#define KVM_CAP_PPC_FIXUP_HCALL 103 | |
| 746 | 761 | |
| 747 | 762 | #ifdef KVM_CAP_IRQ_ROUTING |
| 748 | 763 | |
| @@ -722,10 +722,10 @@ enum perf_callchain_context { · 721 unmodified lines | ||
| 722 | 722 | PERF_CONTEXT_MAX = (__u64)-4095, |
| 723 | 723 | }; |
| 724 | 724 | |
| 725 | −#define PERF_FLAG_FD_NO_GROUP (1U << 0) | |
| 726 | −#define PERF_FLAG_FD_OUTPUT (1U << 1) | |
| 727 | −#define PERF_FLAG_PID_CGROUP (1U << 2) /* pid=cgroup id, per-cpu mode only */ | |
| 728 | −#define PERF_FLAG_FD_CLOEXEC (1U << 3) /* O_CLOEXEC */ | |
| 725 | +#define PERF_FLAG_FD_NO_GROUP (1UL << 0) | |
| 726 | +#define PERF_FLAG_FD_OUTPUT (1UL << 1) | |
| 727 | +#define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */ | |
| 728 | +#define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */ | |
| 729 | 729 | |
| 730 | 730 | union perf_mem_data_src { |
| 731 | 731 | __u64 val; |
| @@ -0,0 +1,90 @@ | ||
| 1 | +/* | |
| 2 | + * ARM Power State and Coordination Interface (PSCI) header | |
| 3 | + * | |
| 4 | + * This header holds common PSCI defines and macros shared | |
| 5 | + * by: ARM kernel, ARM64 kernel, KVM ARM/ARM64 and user space. | |
| 6 | + * | |
| 7 | + * Copyright (C) 2014 Linaro Ltd. | |
| 8 | + * Author: Anup Patel <anup.patel@linaro.org> | |
| 9 | + */ | |
| 10 | + | |
| 11 | +#ifndef _UAPI_LINUX_PSCI_H | |
| 12 | +#define _UAPI_LINUX_PSCI_H | |
| 13 | + | |
| 14 | +/* | |
| 15 | + * PSCI v0.1 interface | |
| 16 | + * | |
| 17 | + * The PSCI v0.1 function numbers are implementation defined. | |
| 18 | + * | |
| 19 | + * Only PSCI return values such as: SUCCESS, NOT_SUPPORTED, | |
| 20 | + * INVALID_PARAMS, and DENIED defined below are applicable | |
| 21 | + * to PSCI v0.1. | |
| 22 | + */ | |
| 23 | + | |
| 24 | +/* PSCI v0.2 interface */ | |
| 25 | +#define PSCI_0_2_FN_BASE 0x84000000 | |
| 26 | +#define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n)) | |
| 27 | +#define PSCI_0_2_64BIT 0x40000000 | |
| 28 | +#define PSCI_0_2_FN64_BASE \ | |
| 29 | + (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT) | |
| 30 | +#define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n)) | |
| 31 | + | |
| 32 | +#define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0) | |
| 33 | +#define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1) | |
| 34 | +#define PSCI_0_2_FN_CPU_OFF PSCI_0_2_FN(2) | |
| 35 | +#define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3) | |
| 36 | +#define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4) | |
| 37 | +#define PSCI_0_2_FN_MIGRATE PSCI_0_2_FN(5) | |
| 38 | +#define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6) | |
| 39 | +#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU PSCI_0_2_FN(7) | |
| 40 | +#define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8) | |
| 41 | +#define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9) | |
| 42 | + | |
| 43 | +#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1) | |
| 44 | +#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3) | |
| 45 | +#define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4) | |
| 46 | +#define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5) | |
| 47 | +#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7) | |
| 48 | + | |
| 49 | +/* PSCI v0.2 power state encoding for CPU_SUSPEND function */ | |
| 50 | +#define PSCI_0_2_POWER_STATE_ID_MASK 0xffff | |
| 51 | +#define PSCI_0_2_POWER_STATE_ID_SHIFT 0 | |
| 52 | +#define PSCI_0_2_POWER_STATE_TYPE_SHIFT 16 | |
| 53 | +#define PSCI_0_2_POWER_STATE_TYPE_MASK \ | |
| 54 | + (0x1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT) | |
| 55 | +#define PSCI_0_2_POWER_STATE_AFFL_SHIFT 24 | |
| 56 | +#define PSCI_0_2_POWER_STATE_AFFL_MASK \ | |
| 57 | + (0x3 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | |
| 58 | + | |
| 59 | +/* PSCI v0.2 affinity level state returned by AFFINITY_INFO */ | |
| 60 | +#define PSCI_0_2_AFFINITY_LEVEL_ON 0 | |
| 61 | +#define PSCI_0_2_AFFINITY_LEVEL_OFF 1 | |
| 62 | +#define PSCI_0_2_AFFINITY_LEVEL_ON_PENDING 2 | |
| 63 | + | |
| 64 | +/* PSCI v0.2 multicore support in Trusted OS returned by MIGRATE_INFO_TYPE */ | |
| 65 | +#define PSCI_0_2_TOS_UP_MIGRATE 0 | |
| 66 | +#define PSCI_0_2_TOS_UP_NO_MIGRATE 1 | |
| 67 | +#define PSCI_0_2_TOS_MP 2 | |
| 68 | + | |
| 69 | +/* PSCI version decoding (independent of PSCI version) */ | |
| 70 | +#define PSCI_VERSION_MAJOR_SHIFT 16 | |
| 71 | +#define PSCI_VERSION_MINOR_MASK \ | |
| 72 | + ((1U << PSCI_VERSION_MAJOR_SHIFT) - 1) | |
| 73 | +#define PSCI_VERSION_MAJOR_MASK ~PSCI_VERSION_MINOR_MASK | |
| 74 | +#define PSCI_VERSION_MAJOR(ver) \ | |
| 75 | + (((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT) | |
| 76 | +#define PSCI_VERSION_MINOR(ver) \ | |
| 77 | + ((ver) & PSCI_VERSION_MINOR_MASK) | |
| 78 | + | |
| 79 | +/* PSCI return values (inclusive of all PSCI versions) */ | |
| 80 | +#define PSCI_RET_SUCCESS 0 | |
| 81 | +#define PSCI_RET_NOT_SUPPORTED -1 | |
| 82 | +#define PSCI_RET_INVALID_PARAMS -2 | |
| 83 | +#define PSCI_RET_DENIED -3 | |
| 84 | +#define PSCI_RET_ALREADY_ON -4 | |
| 85 | +#define PSCI_RET_ON_PENDING -5 | |
| 86 | +#define PSCI_RET_INTERNAL_FAILURE -6 | |
| 87 | +#define PSCI_RET_NOT_PRESENT -7 | |
| 88 | +#define PSCI_RET_DISABLED -8 | |
| 89 | + | |
| 90 | +#endif /* _UAPI_LINUX_PSCI_H */ | |
| @@ -211,7 +211,7 @@ · 210 unmodified lines | ||
| 211 | 211 | /* VIA VT8500 SoC */ |
| 212 | 212 | #define PORT_VT8500 97 |
| 213 | 213 | |
| 214 | −/* Xilinx PSS UART */ | |
| 214 | +/* Cadence (Xilinx Zynq) UART */ | |
| 215 | 215 | #define PORT_XUARTPS 98 |
| 216 | 216 | |
| 217 | 217 | /* Atheros AR933X SoC */ |
| @@ -238,4 +238,10 @@ · 20 unmodified lines | ||
| 238 | 238 | /* Tilera TILE-Gx UART */ |
| 239 | 239 | #define PORT_TILEGX 106 |
| 240 | 240 | |
| 241 | +/* MEN 16z135 UART */ | |
| 242 | +#define PORT_MEN_Z135 107 | |
| 243 | + | |
| 244 | +/* SC16IS74xx */ | |
| 245 | +#define PORT_SC16IS7XX 108 | |
| 246 | + | |
| 241 | 247 | #endif /* _UAPILINUX_SERIAL_CORE_H */ |
| @@ -32,7 +32,7 @@ · 31 unmodified lines | ||
| 32 | 32 | |
| 33 | 33 | #define UART_IIR 2 /* In: Interrupt ID Register */ |
| 34 | 34 | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
| 35 | −#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ | |
| 35 | +#define UART_IIR_ID 0x0e /* Mask for the interrupt ID */ | |
| 36 | 36 | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
| 37 | 37 | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
| 38 | 38 | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
| @@ -8,19 +8,20 @@ · 7 unmodified lines | ||
| 8 | 8 | #endif |
| 9 | 9 | |
| 10 | 10 | /* |
| 11 | − * SHMMAX, SHMMNI and SHMALL are upper limits are defaults which can | |
| 12 | − * be increased by sysctl | |
| 11 | + * SHMMNI, SHMMAX and SHMALL are default upper limits which can be | |
| 12 | + * modified by sysctl. The SHMMAX and SHMALL values have been chosen to | |
| 13 | + * be as large possible without facilitating scenarios where userspace | |
| 14 | + * causes overflows when adjusting the limits via operations of the form | |
| 15 | + * "retrieve current limit; add X; update limit". It is therefore not | |
| 16 | + * advised to make SHMMAX and SHMALL any larger. These limits are | |
| 17 | + * suitable for both 32 and 64-bit systems. | |
| 13 | 18 | */ |
| 14 | − | |
| 15 | −#define SHMMAX 0x2000000 /* max shared seg size (bytes) */ | |
| 16 | 19 | #define SHMMIN 1 /* min shared seg size (bytes) */ |
| 17 | 20 | #define SHMMNI 4096 /* max num of segs system wide */ |
| 18 | −#ifndef __KERNEL__ | |
| 19 | −#define SHMALL (SHMMAX/getpagesize()*(SHMMNI/16)) | |
| 20 | −#endif | |
| 21 | +#define SHMMAX (ULONG_MAX - (1UL << 24)) /* max shared seg size (bytes) */ | |
| 22 | +#define SHMALL (ULONG_MAX - (1UL << 24)) /* max shm system wide (pages) */ | |
| 21 | 23 | #define SHMSEG SHMMNI /* max shared segs per process */ |
| 22 | 24 | |
| 23 | − | |
| 24 | 25 | /* Obsolete, used only for backwards compatibility and libc5 compiles */ |
| 25 | 26 | struct shmid_ds { |
| 26 | 27 | struct ipc_perm shm_perm; /* operation perms */ |
| @@ -75,7 +75,7 @@ struct v4l2_edid { · 74 unmodified lines | ||
| 75 | 75 | __u32 start_block; |
| 76 | 76 | __u32 blocks; |
| 77 | 77 | __u32 reserved[5]; |
| 78 | − __u8 __user *edid; | |
| 78 | + __u8 *edid; | |
| 79 | 79 | }; |
| 80 | 80 | |
| 81 | 81 | #endif /* __V4L2_COMMON__ */ |
| @@ -173,6 +173,76 @@ · 172 unmodified lines | ||
| 173 | 173 | V4L2_DV_FL_CAN_REDUCE_FPS) \ |
| 174 | 174 | } |
| 175 | 175 | |
| 176 | +#define V4L2_DV_BT_CEA_3840X2160P24 { \ | |
| 177 | + .type = V4L2_DV_BT_656_1120, \ | |
| 178 | + V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ | |
| 179 | + 297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \ | |
| 180 | + V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ | |
| 181 | +} | |
| 182 | + | |
| 183 | +#define V4L2_DV_BT_CEA_3840X2160P25 { \ | |
| 184 | + .type = V4L2_DV_BT_656_1120, \ | |
| 185 | + V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ | |
| 186 | + 297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \ | |
| 187 | + V4L2_DV_BT_STD_CEA861, 0) \ | |
| 188 | +} | |
| 189 | + | |
| 190 | +#define V4L2_DV_BT_CEA_3840X2160P30 { \ | |
| 191 | + .type = V4L2_DV_BT_656_1120, \ | |
| 192 | + V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ | |
| 193 | + 297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \ | |
| 194 | + V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ | |
| 195 | +} | |
| 196 | + | |
| 197 | +#define V4L2_DV_BT_CEA_3840X2160P50 { \ | |
| 198 | + .type = V4L2_DV_BT_656_1120, \ | |
| 199 | + V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ | |
| 200 | + 594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \ | |
| 201 | + V4L2_DV_BT_STD_CEA861, 0) \ | |
| 202 | +} | |
| 203 | + | |
| 204 | +#define V4L2_DV_BT_CEA_3840X2160P60 { \ | |
| 205 | + .type = V4L2_DV_BT_656_1120, \ | |
| 206 | + V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ | |
| 207 | + 594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \ | |
| 208 | + V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ | |
| 209 | +} | |
| 210 | + | |
| 211 | +#define V4L2_DV_BT_CEA_4096X2160P24 { \ | |
| 212 | + .type = V4L2_DV_BT_656_1120, \ | |
| 213 | + V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ | |
| 214 | + 297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \ | |
| 215 | + V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ | |
| 216 | +} | |
| 217 | + | |
| 218 | +#define V4L2_DV_BT_CEA_4096X2160P25 { \ | |
| 219 | + .type = V4L2_DV_BT_656_1120, \ | |
| 220 | + V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ | |
| 221 | + 297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \ | |
| 222 | + V4L2_DV_BT_STD_CEA861, 0) \ | |
| 223 | +} | |
| 224 | + | |
| 225 | +#define V4L2_DV_BT_CEA_4096X2160P30 { \ | |
| 226 | + .type = V4L2_DV_BT_656_1120, \ | |
| 227 | + V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ | |
| 228 | + 297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \ | |
| 229 | + V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ | |
| 230 | +} | |
| 231 | + | |
| 232 | +#define V4L2_DV_BT_CEA_4096X2160P50 { \ | |
| 233 | + .type = V4L2_DV_BT_656_1120, \ | |
| 234 | + V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ | |
| 235 | + 594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \ | |
| 236 | + V4L2_DV_BT_STD_CEA861, 0) \ | |
| 237 | +} | |
| 238 | + | |
| 239 | +#define V4L2_DV_BT_CEA_4096X2160P60 { \ | |
| 240 | + .type = V4L2_DV_BT_656_1120, \ | |
| 241 | + V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ | |
| 242 | + 594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \ | |
| 243 | + V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ | |
| 244 | +} | |
| 245 | + | |
| 176 | 246 | |
| 177 | 247 | /* VESA Discrete Monitor Timings as per version 1.0, revision 12 */ |
| 178 | 248 | |
| @@ -52,7 +52,7 @@ enum v4l2_mbus_pixelcode { · 51 unmodified lines | ||
| 52 | 52 | V4L2_MBUS_FMT_RGB888_2X12_LE = 0x100c, |
| 53 | 53 | V4L2_MBUS_FMT_ARGB8888_1X32 = 0x100d, |
| 54 | 54 | |
| 55 | − /* YUV (including grey) - next is 0x2018 */ | |
| 55 | + /* YUV (including grey) - next is 0x2024 */ | |
| 56 | 56 | V4L2_MBUS_FMT_Y8_1X8 = 0x2001, |
| 57 | 57 | V4L2_MBUS_FMT_UV8_1X8 = 0x2015, |
| 58 | 58 | V4L2_MBUS_FMT_UYVY8_1_5X8 = 0x2002, |
| @@ -64,6 +64,8 @@ enum v4l2_mbus_pixelcode { · 5 unmodified lines | ||
| 64 | 64 | V4L2_MBUS_FMT_YUYV8_2X8 = 0x2008, |
| 65 | 65 | V4L2_MBUS_FMT_YVYU8_2X8 = 0x2009, |
| 66 | 66 | V4L2_MBUS_FMT_Y10_1X10 = 0x200a, |
| 67 | + V4L2_MBUS_FMT_UYVY10_2X10 = 0x2018, | |
| 68 | + V4L2_MBUS_FMT_VYUY10_2X10 = 0x2019, | |
| 67 | 69 | V4L2_MBUS_FMT_YUYV10_2X10 = 0x200b, |
| 68 | 70 | V4L2_MBUS_FMT_YVYU10_2X10 = 0x200c, |
| 69 | 71 | V4L2_MBUS_FMT_Y12_1X12 = 0x2013, |
| @@ -72,10 +74,20 @@ enum v4l2_mbus_pixelcode { · 2 unmodified lines | ||
| 72 | 74 | V4L2_MBUS_FMT_YUYV8_1X16 = 0x2011, |
| 73 | 75 | V4L2_MBUS_FMT_YVYU8_1X16 = 0x2012, |
| 74 | 76 | V4L2_MBUS_FMT_YDYUYDYV8_1X16 = 0x2014, |
| 77 | + V4L2_MBUS_FMT_UYVY10_1X20 = 0x201a, | |
| 78 | + V4L2_MBUS_FMT_VYUY10_1X20 = 0x201b, | |
| 75 | 79 | V4L2_MBUS_FMT_YUYV10_1X20 = 0x200d, |
| 76 | 80 | V4L2_MBUS_FMT_YVYU10_1X20 = 0x200e, |
| 77 | 81 | V4L2_MBUS_FMT_YUV10_1X30 = 0x2016, |
| 78 | 82 | V4L2_MBUS_FMT_AYUV8_1X32 = 0x2017, |
| 83 | + V4L2_MBUS_FMT_UYVY12_2X12 = 0x201c, | |
| 84 | + V4L2_MBUS_FMT_VYUY12_2X12 = 0x201d, | |
| 85 | + V4L2_MBUS_FMT_YUYV12_2X12 = 0x201e, | |
| 86 | + V4L2_MBUS_FMT_YVYU12_2X12 = 0x201f, | |
| 87 | + V4L2_MBUS_FMT_UYVY12_1X24 = 0x2020, | |
| 88 | + V4L2_MBUS_FMT_VYUY12_1X24 = 0x2021, | |
| 89 | + V4L2_MBUS_FMT_YUYV12_1X24 = 0x2022, | |
| 90 | + V4L2_MBUS_FMT_YVYU12_1X24 = 0x2023, | |
| 79 | 91 | |
| 80 | 92 | /* Bayer - next is 0x3019 */ |
| 81 | 93 | V4L2_MBUS_FMT_SBGGR8_1X8 = 0x3001, |
| @@ -151,26 +151,24 @@ struct v4l2_subdev_selection { · 150 unmodified lines | ||
| 151 | 151 | /* Backwards compatibility define --- to be removed */ |
| 152 | 152 | #define v4l2_subdev_edid v4l2_edid |
| 153 | 153 | |
| 154 | −#define VIDIOC_SUBDEV_G_FMT _IOWR('V', 4, struct v4l2_subdev_format) | |
| 155 | −#define VIDIOC_SUBDEV_S_FMT _IOWR('V', 5, struct v4l2_subdev_format) | |
| 156 | −#define VIDIOC_SUBDEV_G_FRAME_INTERVAL \ | |
| 157 | − _IOWR('V', 21, struct v4l2_subdev_frame_interval) | |
| 158 | −#define VIDIOC_SUBDEV_S_FRAME_INTERVAL \ | |
| 159 | − _IOWR('V', 22, struct v4l2_subdev_frame_interval) | |
| 160 | −#define VIDIOC_SUBDEV_ENUM_MBUS_CODE \ | |
| 161 | − _IOWR('V', 2, struct v4l2_subdev_mbus_code_enum) | |
| 162 | −#define VIDIOC_SUBDEV_ENUM_FRAME_SIZE \ | |
| 163 | − _IOWR('V', 74, struct v4l2_subdev_frame_size_enum) | |
| 164 | −#define VIDIOC_SUBDEV_ENUM_FRAME_INTERVAL \ | |
| 165 | − _IOWR('V', 75, struct v4l2_subdev_frame_interval_enum) | |
| 166 | −#define VIDIOC_SUBDEV_G_CROP _IOWR('V', 59, struct v4l2_subdev_crop) | |
| 167 | −#define VIDIOC_SUBDEV_S_CROP _IOWR('V', 60, struct v4l2_subdev_crop) | |
| 168 | −#define VIDIOC_SUBDEV_G_SELECTION \ | |
| 169 | − _IOWR('V', 61, struct v4l2_subdev_selection) | |
| 170 | −#define VIDIOC_SUBDEV_S_SELECTION \ | |
| 171 | − _IOWR('V', 62, struct v4l2_subdev_selection) | |
| 172 | −/* These two G/S_EDID ioctls are identical to the ioctls in videodev2.h */ | |
| 173 | −#define VIDIOC_SUBDEV_G_EDID _IOWR('V', 40, struct v4l2_edid) | |
| 174 | −#define VIDIOC_SUBDEV_S_EDID _IOWR('V', 41, struct v4l2_edid) | |
| 154 | +#define VIDIOC_SUBDEV_G_FMT _IOWR('V', 4, struct v4l2_subdev_format) | |
| 155 | +#define VIDIOC_SUBDEV_S_FMT _IOWR('V', 5, struct v4l2_subdev_format) | |
| 156 | +#define VIDIOC_SUBDEV_G_FRAME_INTERVAL _IOWR('V', 21, struct v4l2_subdev_frame_interval) | |
| 157 | +#define VIDIOC_SUBDEV_S_FRAME_INTERVAL _IOWR('V', 22, struct v4l2_subdev_frame_interval) | |
| 158 | +#define VIDIOC_SUBDEV_ENUM_MBUS_CODE _IOWR('V', 2, struct v4l2_subdev_mbus_code_enum) | |
| 159 | +#define VIDIOC_SUBDEV_ENUM_FRAME_SIZE _IOWR('V', 74, struct v4l2_subdev_frame_size_enum) | |
| 160 | +#define VIDIOC_SUBDEV_ENUM_FRAME_INTERVAL _IOWR('V', 75, struct v4l2_subdev_frame_interval_enum) | |
| 161 | +#define VIDIOC_SUBDEV_G_CROP _IOWR('V', 59, struct v4l2_subdev_crop) | |
| 162 | +#define VIDIOC_SUBDEV_S_CROP _IOWR('V', 60, struct v4l2_subdev_crop) | |
| 163 | +#define VIDIOC_SUBDEV_G_SELECTION _IOWR('V', 61, struct v4l2_subdev_selection) | |
| 164 | +#define VIDIOC_SUBDEV_S_SELECTION _IOWR('V', 62, struct v4l2_subdev_selection) | |
| 165 | +/* The following ioctls are identical to the ioctls in videodev2.h */ | |
| 166 | +#define VIDIOC_SUBDEV_G_EDID _IOWR('V', 40, struct v4l2_edid) | |
| 167 | +#define VIDIOC_SUBDEV_S_EDID _IOWR('V', 41, struct v4l2_edid) | |
| 168 | +#define VIDIOC_SUBDEV_S_DV_TIMINGS _IOWR('V', 87, struct v4l2_dv_timings) | |
| 169 | +#define VIDIOC_SUBDEV_G_DV_TIMINGS _IOWR('V', 88, struct v4l2_dv_timings) | |
| 170 | +#define VIDIOC_SUBDEV_ENUM_DV_TIMINGS _IOWR('V', 98, struct v4l2_enum_dv_timings) | |
| 171 | +#define VIDIOC_SUBDEV_QUERY_DV_TIMINGS _IOR('V', 99, struct v4l2_dv_timings) | |
| 172 | +#define VIDIOC_SUBDEV_DV_TIMINGS_CAP _IOWR('V', 100, struct v4l2_dv_timings_cap) | |
| 175 | 173 | |
| 176 | 174 | #endif |
| @@ -649,7 +649,6 @@ struct v4l2_plane { · 648 unmodified lines | ||
| 649 | 649 | * @length: size in bytes of the buffer (NOT its payload) for single-plane |
| 650 | 650 | * buffers (when type != *_MPLANE); number of elements in the |
| 651 | 651 | * planes array for multi-plane buffers |
| 652 | − * @input: input number from which the video data has has been captured | |
| 653 | 652 | * |
| 654 | 653 | * Contains data exchanged by application and driver using one of the Streaming |
| 655 | 654 | * I/O methods. |
| @@ -1107,12 +1106,15 @@ struct v4l2_dv_timings { · 451 unmodified lines | ||
| 1107 | 1106 | |
| 1108 | 1107 | /** struct v4l2_enum_dv_timings - DV timings enumeration |
| 1109 | 1108 | * @index: enumeration index |
| 1109 | + * @pad: the pad number for which to enumerate timings (used with | |
| 1110 | + * v4l-subdev nodes only) | |
| 1110 | 1111 | * @reserved: must be zeroed |
| 1111 | 1112 | * @timings: the timings for the given index |
| 1112 | 1113 | */ |
| 1113 | 1114 | struct v4l2_enum_dv_timings { |
| 1114 | 1115 | __u32 index; |
| 1115 | − __u32 reserved[3]; | |
| 1116 | + __u32 pad; | |
| 1117 | + __u32 reserved[2]; | |
| 1116 | 1118 | struct v4l2_dv_timings timings; |
| 1117 | 1119 | }; |
| 1118 | 1120 | |
| @@ -1150,11 +1152,14 @@ struct v4l2_bt_timings_cap { · 31 unmodified lines | ||
| 1150 | 1152 | |
| 1151 | 1153 | /** struct v4l2_dv_timings_cap - DV timings capabilities |
| 1152 | 1154 | * @type: the type of the timings (same as in struct v4l2_dv_timings) |
| 1155 | + * @pad: the pad number for which to query capabilities (used with | |
| 1156 | + * v4l-subdev nodes only) | |
| 1153 | 1157 | * @bt: the BT656/1120 timings capabilities |
| 1154 | 1158 | */ |
| 1155 | 1159 | struct v4l2_dv_timings_cap { |
| 1156 | 1160 | __u32 type; |
| 1157 | − __u32 reserved[3]; | |
| 1161 | + __u32 pad; | |
| 1162 | + __u32 reserved[2]; | |
| 1158 | 1163 | union { |
| 1159 | 1164 | struct v4l2_bt_timings_cap bt; |
| 1160 | 1165 | __u32 raw_data[32]; |
| @@ -1765,6 +1770,7 @@ struct v4l2_streamparm { · 604 unmodified lines | ||
| 1765 | 1770 | #define V4L2_EVENT_EOS 2 |
| 1766 | 1771 | #define V4L2_EVENT_CTRL 3 |
| 1767 | 1772 | #define V4L2_EVENT_FRAME_SYNC 4 |
| 1773 | +#define V4L2_EVENT_SOURCE_CHANGE 5 | |
| 1768 | 1774 | #define V4L2_EVENT_PRIVATE_START 0x08000000 |
| 1769 | 1775 | |
| 1770 | 1776 | /* Payload for V4L2_EVENT_VSYNC */ |
| @@ -1796,12 +1802,19 @@ struct v4l2_event_frame_sync { · 25 unmodified lines | ||
| 1796 | 1802 | __u32 frame_sequence; |
| 1797 | 1803 | }; |
| 1798 | 1804 | |
| 1805 | +#define V4L2_EVENT_SRC_CH_RESOLUTION (1 << 0) | |
| 1806 | + | |
| 1807 | +struct v4l2_event_src_change { | |
| 1808 | + __u32 changes; | |
| 1809 | +}; | |
| 1810 | + | |
| 1799 | 1811 | struct v4l2_event { |
| 1800 | 1812 | __u32 type; |
| 1801 | 1813 | union { |
| 1802 | 1814 | struct v4l2_event_vsync vsync; |
| 1803 | 1815 | struct v4l2_event_ctrl ctrl; |
| 1804 | 1816 | struct v4l2_event_frame_sync frame_sync; |
| 1817 | + struct v4l2_event_src_change src_change; | |
| 1805 | 1818 | __u8 data[64]; |
| 1806 | 1819 | } u; |
| 1807 | 1820 | __u32 pending; |