Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Will Deacon: "It's a little busier than normal, but it's still not a lot of code and things seem fairly quiet in general: - Fix allocation failure during SVE coredumps - Fix handling of SVE context on signal delivery - Enable Neoverse N2 CPU errata workarounds for Microsoft's "Azure Cobalt 100" clone - Work around CMN PMU erratum in AmpereOneX implementation - Fix typo in CXL PMU event definition - Fix jump label asm constraints" * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64/sve: Lower the maximum allocation for the SVE ptrace regset arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata perf/arm-cmn: Workaround AmpereOneX errata AC04_MESH_1 (incorrect child count) arm64: jump_label: use constraints "Si" instead of "i" arm64: fix typo in comments perf: CXL: fix mismatched cpmu event opcode arm64/signal: Don't assume that TIF_SVE means we saved SVE state

Linus Torvalds committed 2 years ago

Commit 3f3f64c2 parents efb0b63 281392611 files · +46 −16Browse files

Unified · Split

11 files

Documentation/arch/arm64/silicon-errata.rst +7 −0
arch/arm64/include/asm/cpufeature.h +1 −1
arch/arm64/include/asm/cputype.h +4 −0
arch/arm64/include/asm/fpsimd.h +6 −6
arch/arm64/include/asm/jump_label.h +8 −4
arch/arm64/kernel/cpu_errata.c +3 −0
arch/arm64/kernel/fpsimd.c +1 −1
arch/arm64/kernel/ptrace.c +2 −1
arch/arm64/kernel/signal.c +2 −2
drivers/perf/arm-cmn.c +11 −0
drivers/perf/cxl_pmu.c +1 −1

Documentation/arch/arm64/silicon-errata.rst+7−0

@@ -243,3 +243,10 @@ stable kernels. · 242 unmodified lines
243	243	+----------------+-----------------+-----------------+-----------------------------+
244	244	\| ASR \| ASR8601 \| #8601001 \| N/A \|
245	245	+----------------+-----------------+-----------------+-----------------------------+
	246	++----------------+-----------------+-----------------+-----------------------------+
	247	+\| Microsoft \| Azure Cobalt 100\| #2139208 \| ARM64_ERRATUM_2139208 \|
	248	++----------------+-----------------+-----------------+-----------------------------+
	249	+\| Microsoft \| Azure Cobalt 100\| #2067961 \| ARM64_ERRATUM_2067961 \|
	250	++----------------+-----------------+-----------------+-----------------------------+
	251	+\| Microsoft \| Azure Cobalt 100\| #2253138 \| ARM64_ERRATUM_2253138 \|
	252	++----------------+-----------------+-----------------+-----------------------------+

arch/arm64/include/asm/cpufeature.h+1−1

@@ -83,7 +83,7 @@ struct arm64_ftr_bits { · 82 unmodified lines
83	83	* to full-0 denotes that this field has no override
84	84	*
85	85	* A @mask field set to full-0 with the corresponding @val field set
86		− * to full-1 denotes thath this field has an invalid override.
	86	+ * to full-1 denotes that this field has an invalid override.
87	87	*/
88	88	struct arm64_ftr_override {
89	89	u64 val;

arch/arm64/include/asm/cputype.h+4−0

@@ -61,6 +61,7 @@ · 60 unmodified lines
61	61	#define ARM_CPU_IMP_HISI 0x48
62	62	#define ARM_CPU_IMP_APPLE 0x61
63	63	#define ARM_CPU_IMP_AMPERE 0xC0
	64	+#define ARM_CPU_IMP_MICROSOFT 0x6D
64	65
65	66	#define ARM_CPU_PART_AEM_V8 0xD0F
66	67	#define ARM_CPU_PART_FOUNDATION 0xD00
@@ -135,6 +136,8 @@ · 68 unmodified lines
135	136
136	137	#define AMPERE_CPU_PART_AMPERE1 0xAC3
137	138
	139	+#define MICROSOFT_CPU_PART_AZURE_COBALT_100 0xD49 /* Based on r0p0 of ARM Neoverse N2 */
	140	+
138	141	#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
139	142	#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
140	143	#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
@@ -193,6 +196,7 @@ · 52 unmodified lines
193	196	#define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
194	197	#define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
195	198	#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
	199	+#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100)
196	200
197	201	/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
198	202	#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX

arch/arm64/include/asm/fpsimd.h+6−6

@@ -62,13 +62,13 @@ static inline void cpacr_restore(unsigned long cpacr) · 61 unmodified lines
62	62	* When we defined the maximum SVE vector length we defined the ABI so
63	63	* that the maximum vector length included all the reserved for future
64	64	* expansion bits in ZCR rather than those just currently defined by
65		− * the architecture. While SME follows a similar pattern the fact that
66		− * it includes a square matrix means that any allocations that attempt
67		− * to cover the maximum potential vector length (such as happen with
68		− * the regset used for ptrace) end up being extremely large. Define
69		− * the much lower actual limit for use in such situations.
	65	+ * the architecture. Using this length to allocate worst size buffers
	66	+ * results in excessively large allocations, and this effect is even
	67	+ * more pronounced for SME due to ZA. Define more suitable VLs for
	68	+ * these situations.
70	69	*/
71		−#define SME_VQ_MAX 16
	70	+#define ARCH_SVE_VQ_MAX ((ZCR_ELx_LEN_MASK >> ZCR_ELx_LEN_SHIFT) + 1)
	71	+#define SME_VQ_MAX ((SMCR_ELx_LEN_MASK >> SMCR_ELx_LEN_SHIFT) + 1)
72	72
73	73	struct task_struct;
74	74

arch/arm64/include/asm/jump_label.h+8−4

@@ -15,6 +15,10 @@ · 14 unmodified lines
15	15
16	16	#define JUMP_LABEL_NOP_SIZE AARCH64_INSN_SIZE
17	17
	18	+/*
	19	+ * Prefer the constraint "S" to support PIC with GCC. Clang before 19 does not
	20	+ * support "S" on a symbol with a constant offset, so we use "i" as a fallback.
	21	+ */
18	22	static __always_inline bool arch_static_branch(struct static_key * const key,
19	23	const bool branch)
20	24	{
@@ -23,9 +27,9 @@ static __always_inline bool arch_static_branch(struct static_key * const key, · 2 unmodified lines
23	27	" .pushsection __jump_table, \"aw\" \n\t"
24	28	" .align 3 \n\t"
25	29	" .long 1b - ., %l[l_yes] - . \n\t"
26		− " .quad %c0 - . \n\t"
	30	+ " .quad (%[key] - .) + %[bit0] \n\t"
27	31	" .popsection \n\t"
28		− : : "i"(&((char *)key)[branch]) : : l_yes);
	32	+ : : [key]"Si"(key), [bit0]"i"(branch) : : l_yes);
29	33
30	34	return false;
31	35	l_yes:
@@ -40,9 +44,9 @@ static __always_inline bool arch_static_branch_jump(struct static_key * const ke · 8 unmodified lines
40	44	" .pushsection __jump_table, \"aw\" \n\t"
41	45	" .align 3 \n\t"
42	46	" .long 1b - ., %l[l_yes] - . \n\t"
43		− " .quad %c0 - . \n\t"
	47	+ " .quad (%[key] - .) + %[bit0] \n\t"
44	48	" .popsection \n\t"
45		− : : "i"(&((char *)key)[branch]) : : l_yes);
	49	+ : : [key]"Si"(key), [bit0]"i"(branch) : : l_yes);
46	50
47	51	return false;
48	52	l_yes:

arch/arm64/kernel/cpu_errata.c+3−0

@@ -374,6 +374,7 @@ static const struct midr_range erratum_1463225[] = { · 373 unmodified lines
374	374	static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
375	375	#ifdef CONFIG_ARM64_ERRATUM_2139208
376	376	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
	377	+ MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
377	378	#endif
378	379	#ifdef CONFIG_ARM64_ERRATUM_2119858
379	380	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
@@ -387,6 +388,7 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { · 7 unmodified lines
387	388	static const struct midr_range tsb_flush_fail_cpus[] = {
388	389	#ifdef CONFIG_ARM64_ERRATUM_2067961
389	390	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
	391	+ MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
390	392	#endif
391	393	#ifdef CONFIG_ARM64_ERRATUM_2054223
392	394	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
@@ -399,6 +401,7 @@ static const struct midr_range tsb_flush_fail_cpus[] = { · 6 unmodified lines
399	401	static struct midr_range trbe_write_out_of_range_cpus[] = {
400	402	#ifdef CONFIG_ARM64_ERRATUM_2253138
401	403	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
	404	+ MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
402	405	#endif
403	406	#ifdef CONFIG_ARM64_ERRATUM_2224489
404	407	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),

arch/arm64/kernel/fpsimd.c+1−1

@@ -1635,7 +1635,7 @@ void fpsimd_preserve_current_state(void) · 1634 unmodified lines
1635	1635	void fpsimd_signal_preserve_current_state(void)
1636	1636	{
1637	1637	fpsimd_preserve_current_state();
1638		− if (test_thread_flag(TIF_SVE))
	1638	+ if (current->thread.fp_type == FP_STATE_SVE)
1639	1639	sve_to_fpsimd(current);
1640	1640	}
1641	1641

arch/arm64/kernel/ptrace.c+2−1

@@ -1500,7 +1500,8 @@ static const struct user_regset aarch64_regsets[] = { · 1499 unmodified lines
1500	1500	#ifdef CONFIG_ARM64_SVE
1501	1501	[REGSET_SVE] = { /* Scalable Vector Extension */
1502	1502	.core_note_type = NT_ARM_SVE,
1503		− .n = DIV_ROUND_UP(SVE_PT_SIZE(SVE_VQ_MAX, SVE_PT_REGS_SVE),
	1503	+ .n = DIV_ROUND_UP(SVE_PT_SIZE(ARCH_SVE_VQ_MAX,
	1504	+ SVE_PT_REGS_SVE),
1504	1505	SVE_VQ_BYTES),
1505	1506	.size = SVE_VQ_BYTES,
1506	1507	.align = SVE_VQ_BYTES,

arch/arm64/kernel/signal.c+2−2

@@ -242,7 +242,7 @@ static int preserve_sve_context(struct sve_context __user *ctx) · 241 unmodified lines
242	242	vl = task_get_sme_vl(current);
243	243	vq = sve_vq_from_vl(vl);
244	244	flags \|= SVE_SIG_FLAG_SM;
245		− } else if (test_thread_flag(TIF_SVE)) {
	245	+ } else if (current->thread.fp_type == FP_STATE_SVE) {
246	246	vq = sve_vq_from_vl(vl);
247	247	}
248	248
@@ -878,7 +878,7 @@ static int setup_sigframe_layout(struct rt_sigframe_user_layout *user, · 629 unmodified lines
878	878	if (system_supports_sve() \|\| system_supports_sme()) {
879	879	unsigned int vq = 0;
880	880
881		− if (add_all \|\| test_thread_flag(TIF_SVE) \|\|
	881	+ if (add_all \|\| current->thread.fp_type == FP_STATE_SVE \|\|
882	882	thread_sm_enabled(&current->thread)) {
883	883	int vl = max(sve_max_vl(), sme_max_vl());
884	884

drivers/perf/arm-cmn.c+11−0

@@ -2305,6 +2305,17 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset) · 2304 unmodified lines
2305	2305	dev_dbg(cmn->dev, "ignoring external node %llx\n", reg);
2306	2306	continue;
2307	2307	}
	2308	+ /*
	2309	+ * AmpereOneX erratum AC04_MESH_1 makes some XPs report a bogus
	2310	+ * child count larger than the number of valid child pointers.
	2311	+ * A child offset of 0 can only occur on CMN-600; otherwise it
	2312	+ * would imply the root node being its own grandchild, which
	2313	+ * we can safely dismiss in general.
	2314	+ */
	2315	+ if (reg == 0 && cmn->part != PART_CMN600) {
	2316	+ dev_dbg(cmn->dev, "bogus child pointer?\n");
	2317	+ continue;
	2318	+ }
2308	2319
2309	2320	arm_cmn_init_node_info(cmn, reg & CMN_CHILD_NODE_ADDR, dn);
2310	2321

drivers/perf/cxl_pmu.c+1−1

@@ -419,7 +419,7 @@ static struct attribute *cxl_pmu_event_attrs[] = { · 418 unmodified lines
419	419	CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmp, CXL_PMU_GID_S2M_NDR, BIT(0)),
420	420	CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmps, CXL_PMU_GID_S2M_NDR, BIT(1)),
421	421	CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmpe, CXL_PMU_GID_S2M_NDR, BIT(2)),
422		− CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_biconflictack, CXL_PMU_GID_S2M_NDR, BIT(3)),
	422	+ CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_biconflictack, CXL_PMU_GID_S2M_NDR, BIT(4)),
423	423	/* CXL rev 3.0 Table 3-46 S2M DRS opcodes */
424	424	CXL_PMU_EVENT_CXL_ATTR(s2m_drs_memdata, CXL_PMU_GID_S2M_DRS, BIT(0)),
425	425	CXL_PMU_EVENT_CXL_ATTR(s2m_drs_memdatanxm, CXL_PMU_GID_S2M_DRS, BIT(1)),

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

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