After reset assertion, we only have to wait for the reset signals to propagate through the GPU before deasserting the reset again. A few hundred clock cycles should be more than enough. Replace the msleep(1), which can actually take about 30 ms on i.MX6Q in some configurations, with an usleep_range of a few microseconds. If the delay was too short, the FE would not be idle afterwards, and the reset would be retried.
Unified · Split
| @@ -456,7 +456,7 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) · 455 unmodified lines | |||
| 456 | gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); | 456 | gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); |
| 457 | 457 | ||
| 458 | /* wait for reset. */ | 458 | /* wait for reset. */ |
| 459 | msleep(1); | 459 | usleep_range(10, 20); |
| 460 | 460 | ||
| 461 | /* reset soft reset bit. */ | 461 | /* reset soft reset bit. */ |
| 462 | control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET; | 462 | control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET; |