Showing the changes to drivers/staging/lirc (1 of 1 file). Show all
Unified · Split
| @@ -0,0 +1,1282 @@ | |||
| 1 | /* | ||
| 2 | * LIRC SIR driver, (C) 2000 Milan Pikula <www@fornax.sk> | ||
| 3 | * | ||
| 4 | * lirc_sir - Device driver for use with SIR (serial infra red) | ||
| 5 | * mode of IrDA on many notebooks. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | * | ||
| 21 | * | ||
| 22 | * 2000/09/16 Frank Przybylski <mail@frankprzybylski.de> : | ||
| 23 | * added timeout and relaxed pulse detection, removed gap bug | ||
| 24 | * | ||
| 25 | * 2000/12/15 Christoph Bartelmus <lirc@bartelmus.de> : | ||
| 26 | * added support for Tekram Irmate 210 (sending does not work yet, | ||
| 27 | * kind of disappointing that nobody was able to implement that | ||
| 28 | * before), | ||
| 29 | * major clean-up | ||
| 30 | * | ||
| 31 | * 2001/02/27 Christoph Bartelmus <lirc@bartelmus.de> : | ||
| 32 | * added support for StrongARM SA1100 embedded microprocessor | ||
| 33 | * parts cut'n'pasted from sa1100_ir.c (C) 2000 Russell King | ||
| 34 | */ | ||
| 35 | |||
| 36 | #include <linux/module.h> | ||
| 37 | #include <linux/sched.h> | ||
| 38 | #include <linux/errno.h> | ||
| 39 | #include <linux/signal.h> | ||
| 40 | #include <linux/fs.h> | ||
| 41 | #include <linux/interrupt.h> | ||
| 42 | #include <linux/ioport.h> | ||
| 43 | #include <linux/kernel.h> | ||
| 44 | #include <linux/serial_reg.h> | ||
| 45 | #include <linux/time.h> | ||
| 46 | #include <linux/string.h> | ||
| 47 | #include <linux/types.h> | ||
| 48 | #include <linux/wait.h> | ||
| 49 | #include <linux/mm.h> | ||
| 50 | #include <linux/delay.h> | ||
| 51 | #include <linux/poll.h> | ||
| 52 | #include <asm/system.h> | ||
| 53 | #include <linux/io.h> | ||
| 54 | #include <asm/irq.h> | ||
| 55 | #include <linux/fcntl.h> | ||
| 56 | #ifdef LIRC_ON_SA1100 | ||
| 57 | #include <asm/hardware.h> | ||
| 58 | #ifdef CONFIG_SA1100_COLLIE | ||
| 59 | #include <asm/arch/tc35143.h> | ||
| 60 | #include <asm/ucb1200.h> | ||
| 61 | #endif | ||
| 62 | #endif | ||
| 63 | |||
| 64 | #include <linux/timer.h> | ||
| 65 | |||
| 66 | #include <media/lirc.h> | ||
| 67 | #include <media/lirc_dev.h> | ||
| 68 | |||
| 69 | /* SECTION: Definitions */ | ||
| 70 | |||
| 71 | /*** Tekram dongle ***/ | ||
| 72 | #ifdef LIRC_SIR_TEKRAM | ||
| 73 | /* stolen from kernel source */ | ||
| 74 | /* definitions for Tekram dongle */ | ||
| 75 | #define TEKRAM_115200 0x00 | ||
| 76 | #define TEKRAM_57600 0x01 | ||
| 77 | #define TEKRAM_38400 0x02 | ||
| 78 | #define TEKRAM_19200 0x03 | ||
| 79 | #define TEKRAM_9600 0x04 | ||
| 80 | #define TEKRAM_2400 0x08 | ||
| 81 | |||
| 82 | #define TEKRAM_PW 0x10 /* Pulse select bit */ | ||
| 83 | |||
| 84 | /* 10bit * 1s/115200bit in milliseconds = 87ms*/ | ||
| 85 | #define TIME_CONST (10000000ul/115200ul) | ||
| 86 | |||
| 87 | #endif | ||
| 88 | |||
| 89 | #ifdef LIRC_SIR_ACTISYS_ACT200L | ||
| 90 | static void init_act200(void); | ||
| 91 | #elif defined(LIRC_SIR_ACTISYS_ACT220L) | ||
| 92 | static void init_act220(void); | ||
| 93 | #endif | ||
| 94 | |||
| 95 | /*** SA1100 ***/ | ||
| 96 | #ifdef LIRC_ON_SA1100 | ||
| 97 | struct sa1100_ser2_registers { | ||
| 98 | /* HSSP control register */ | ||
| 99 | unsigned char hscr0; | ||
| 100 | /* UART registers */ | ||
| 101 | unsigned char utcr0; | ||
| 102 | unsigned char utcr1; | ||
| 103 | unsigned char utcr2; | ||
| 104 | unsigned char utcr3; | ||
| 105 | unsigned char utcr4; | ||
| 106 | unsigned char utdr; | ||
| 107 | unsigned char utsr0; | ||
| 108 | unsigned char utsr1; | ||
| 109 | } sr; | ||
| 110 | |||
| 111 | static int irq = IRQ_Ser2ICP; | ||
| 112 | |||
| 113 | #define LIRC_ON_SA1100_TRANSMITTER_LATENCY 0 | ||
| 114 | |||
| 115 | /* pulse/space ratio of 50/50 */ | ||
| 116 | static unsigned long pulse_width = (13-LIRC_ON_SA1100_TRANSMITTER_LATENCY); | ||
| 117 | /* 1000000/freq-pulse_width */ | ||
| 118 | static unsigned long space_width = (13-LIRC_ON_SA1100_TRANSMITTER_LATENCY); | ||
| 119 | static unsigned int freq = 38000; /* modulation frequency */ | ||
| 120 | static unsigned int duty_cycle = 50; /* duty cycle of 50% */ | ||
| 121 | |||
| 122 | #endif | ||
| 123 | |||
| 124 | #define RBUF_LEN 1024 | ||
| 125 | #define WBUF_LEN 1024 | ||
| 126 | |||
| 127 | #define LIRC_DRIVER_NAME "lirc_sir" | ||
| 128 | |||
| 129 | #define PULSE '[' | ||
| 130 | |||
| 131 | #ifndef LIRC_SIR_TEKRAM | ||
| 132 | /* 9bit * 1s/115200bit in milli seconds = 78.125ms*/ | ||
| 133 | #define TIME_CONST (9000000ul/115200ul) | ||
| 134 | #endif | ||
| 135 | |||
| 136 | |||
| 137 | /* timeout for sequences in jiffies (=5/100s), must be longer than TIME_CONST */ | ||
| 138 | #define SIR_TIMEOUT (HZ*5/100) | ||
| 139 | |||
| 140 | #ifndef LIRC_ON_SA1100 | ||
| 141 | #ifndef LIRC_IRQ | ||
| 142 | #define LIRC_IRQ 4 | ||
| 143 | #endif | ||
| 144 | #ifndef LIRC_PORT | ||
| 145 | /* for external dongles, default to com1 */ | ||
| 146 | #if defined(LIRC_SIR_ACTISYS_ACT200L) || \ | ||
| 147 | defined(LIRC_SIR_ACTISYS_ACT220L) || \ | ||
| 148 | defined(LIRC_SIR_TEKRAM) | ||
| 149 | #define LIRC_PORT 0x3f8 | ||
| 150 | #else | ||
| 151 | /* onboard sir ports are typically com3 */ | ||
| 152 | #define LIRC_PORT 0x3e8 | ||
| 153 | #endif | ||
| 154 | #endif | ||
| 155 | |||
| 156 | static int io = LIRC_PORT; | ||
| 157 | static int irq = LIRC_IRQ; | ||
| 158 | static int threshold = 3; | ||
| 159 | #endif | ||
| 160 | |||
| 161 | static DEFINE_SPINLOCK(timer_lock); | ||
| 162 | static struct timer_list timerlist; | ||
| 163 | /* time of last signal change detected */ | ||
| 164 | static struct timeval last_tv = {0, 0}; | ||
| 165 | /* time of last UART data ready interrupt */ | ||
| 166 | static struct timeval last_intr_tv = {0, 0}; | ||
| 167 | static int last_value; | ||
| 168 | |||
| 169 | static DECLARE_WAIT_QUEUE_HEAD(lirc_read_queue); | ||
| 170 | |||
| 171 | static DEFINE_SPINLOCK(hardware_lock); | ||
| 172 | |||
| 173 | static int rx_buf[RBUF_LEN]; | ||
| 174 | static unsigned int rx_tail, rx_head; | ||
| 175 | |||
| 176 | static int debug; | ||
| 177 | #define dprintk(fmt, args...) \ | ||
| 178 | do { \ | ||
| 179 | if (debug) \ | ||
| 180 | printk(KERN_DEBUG LIRC_DRIVER_NAME ": " \ | ||
| 181 | fmt, ## args); \ | ||
| 182 | } while (0) | ||
| 183 | |||
| 184 | /* SECTION: Prototypes */ | ||
| 185 | |||
| 186 | /* Communication with user-space */ | ||
| 187 | static unsigned int lirc_poll(struct file *file, poll_table *wait); | ||
| 188 | static ssize_t lirc_read(struct file *file, char *buf, size_t count, | ||
| 189 | loff_t *ppos); | ||
| 190 | static ssize_t lirc_write(struct file *file, const char *buf, size_t n, | ||
| 191 | loff_t *pos); | ||
| 192 | static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg); | ||
| 193 | static void add_read_queue(int flag, unsigned long val); | ||
| 194 | static int init_chrdev(void); | ||
| 195 | static void drop_chrdev(void); | ||
| 196 | /* Hardware */ | ||
| 197 | static irqreturn_t sir_interrupt(int irq, void *dev_id); | ||
| 198 | static void send_space(unsigned long len); | ||
| 199 | static void send_pulse(unsigned long len); | ||
| 200 | static int init_hardware(void); | ||
| 201 | static void drop_hardware(void); | ||
| 202 | /* Initialisation */ | ||
| 203 | static int init_port(void); | ||
| 204 | static void drop_port(void); | ||
| 205 | |||
| 206 | #ifdef LIRC_ON_SA1100 | ||
| 207 | static void on(void) | ||
| 208 | { | ||
| 209 | PPSR |= PPC_TXD2; | ||
| 210 | } | ||
| 211 | |||
| 212 | static void off(void) | ||
| 213 | { | ||
| 214 | PPSR &= ~PPC_TXD2; | ||
| 215 | } | ||
| 216 | #else | ||
| 217 | static inline unsigned int sinp(int offset) | ||
| 218 | { | ||
| 219 | return inb(io + offset); | ||
| 220 | } | ||
| 221 | |||
| 222 | static inline void soutp(int offset, int value) | ||
| 223 | { | ||
| 224 | outb(value, io + offset); | ||
| 225 | } | ||
| 226 | #endif | ||
| 227 | |||
| 228 | #ifndef MAX_UDELAY_MS | ||
| 229 | #define MAX_UDELAY_US 5000 | ||
| 230 | #else | ||
| 231 | #define MAX_UDELAY_US (MAX_UDELAY_MS*1000) | ||
| 232 | #endif | ||
| 233 | |||
| 234 | static void safe_udelay(unsigned long usecs) | ||
| 235 | { | ||
| 236 | while (usecs > MAX_UDELAY_US) { | ||
| 237 | udelay(MAX_UDELAY_US); | ||
| 238 | usecs -= MAX_UDELAY_US; | ||
| 239 | } | ||
| 240 | udelay(usecs); | ||
| 241 | } | ||
| 242 | |||
| 243 | /* SECTION: Communication with user-space */ | ||
| 244 | |||
| 245 | static unsigned int lirc_poll(struct file *file, poll_table *wait) | ||
| 246 | { | ||
| 247 | poll_wait(file, &lirc_read_queue, wait); | ||
| 248 | if (rx_head != rx_tail) | ||
| 249 | return POLLIN | POLLRDNORM; | ||
| 250 | return 0; | ||
| 251 | } | ||
| 252 | |||
| 253 | static ssize_t lirc_read(struct file *file, char *buf, size_t count, | ||
| 254 | loff_t *ppos) | ||
| 255 | { | ||
| 256 | int n = 0; | ||
| 257 | int retval = 0; | ||
| 258 | DECLARE_WAITQUEUE(wait, current); | ||
| 259 | |||
| 260 | if (count % sizeof(int)) | ||
| 261 | return -EINVAL; | ||
| 262 | |||
| 263 | add_wait_queue(&lirc_read_queue, &wait); | ||
| 264 | set_current_state(TASK_INTERRUPTIBLE); | ||
| 265 | while (n < count) { | ||
| 266 | if (rx_head != rx_tail) { | ||
| 267 | if (copy_to_user((void *) buf + n, | ||
| 268 | (void *) (rx_buf + rx_head), | ||
| 269 | sizeof(int))) { | ||
| 270 | retval = -EFAULT; | ||
| 271 | break; | ||
| 272 | } | ||
| 273 | rx_head = (rx_head + 1) & (RBUF_LEN - 1); | ||
| 274 | n += sizeof(int); | ||
| 275 | } else { | ||
| 276 | if (file->f_flags & O_NONBLOCK) { | ||
| 277 | retval = -EAGAIN; | ||
| 278 | break; | ||
| 279 | } | ||
| 280 | if (signal_pending(current)) { | ||
| 281 | retval = -ERESTARTSYS; | ||
| 282 | break; | ||
| 283 | } | ||
| 284 | schedule(); | ||
| 285 | set_current_state(TASK_INTERRUPTIBLE); | ||
| 286 | } | ||
| 287 | } | ||
| 288 | remove_wait_queue(&lirc_read_queue, &wait); | ||
| 289 | set_current_state(TASK_RUNNING); | ||
| 290 | return n ? n : retval; | ||
| 291 | } | ||
| 292 | static ssize_t lirc_write(struct file *file, const char *buf, size_t n, | ||
| 293 | loff_t *pos) | ||
| 294 | { | ||
| 295 | unsigned long flags; | ||
| 296 | int i, count; | ||
| 297 | int *tx_buf; | ||
| 298 | |||
| 299 | count = n / sizeof(int); | ||
| 300 | if (n % sizeof(int) || count % 2 == 0) | ||
| 301 | return -EINVAL; | ||
| 302 | tx_buf = memdup_user(buf, n); | ||
| 303 | if (IS_ERR(tx_buf)) | ||
| 304 | return PTR_ERR(tx_buf); | ||
| 305 | i = 0; | ||
| 306 | #ifdef LIRC_ON_SA1100 | ||
| 307 | /* disable receiver */ | ||
| 308 | Ser2UTCR3 = 0; | ||
| 309 | #endif | ||
| 310 | local_irq_save(flags); | ||
| 311 | while (1) { | ||
| 312 | if (i >= count) | ||
| 313 | break; | ||
| 314 | if (tx_buf[i]) | ||
| 315 | send_pulse(tx_buf[i]); | ||
| 316 | i++; | ||
| 317 | if (i >= count) | ||
| 318 | break; | ||
| 319 | if (tx_buf[i]) | ||
| 320 | send_space(tx_buf[i]); | ||
| 321 | i++; | ||
| 322 | } | ||
| 323 | local_irq_restore(flags); | ||
| 324 | #ifdef LIRC_ON_SA1100 | ||
| 325 | off(); | ||
| 326 | udelay(1000); /* wait 1ms for IR diode to recover */ | ||
| 327 | Ser2UTCR3 = 0; | ||
| 328 | /* clear status register to prevent unwanted interrupts */ | ||
| 329 | Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB); | ||
| 330 | /* enable receiver */ | ||
| 331 | Ser2UTCR3 = UTCR3_RXE|UTCR3_RIE; | ||
| 332 | #endif | ||
| 333 | return count; | ||
| 334 | } | ||
| 335 | |||
| 336 | static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) | ||
| 337 | { | ||
| 338 | int retval = 0; | ||
| 339 | unsigned long value = 0; | ||
| 340 | #ifdef LIRC_ON_SA1100 | ||
| 341 | unsigned int ivalue; | ||
| 342 | |||
| 343 | if (cmd == LIRC_GET_FEATURES) | ||
| 344 | value = LIRC_CAN_SEND_PULSE | | ||
| 345 | LIRC_CAN_SET_SEND_DUTY_CYCLE | | ||
| 346 | LIRC_CAN_SET_SEND_CARRIER | | ||
| 347 | LIRC_CAN_REC_MODE2; | ||
| 348 | else if (cmd == LIRC_GET_SEND_MODE) | ||
| 349 | value = LIRC_MODE_PULSE; | ||
| 350 | else if (cmd == LIRC_GET_REC_MODE) | ||
| 351 | value = LIRC_MODE_MODE2; | ||
| 352 | #else | ||
| 353 | if (cmd == LIRC_GET_FEATURES) | ||
| 354 | value = LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2; | ||
| 355 | else if (cmd == LIRC_GET_SEND_MODE) | ||
| 356 | value = LIRC_MODE_PULSE; | ||
| 357 | else if (cmd == LIRC_GET_REC_MODE) | ||
| 358 | value = LIRC_MODE_MODE2; | ||
| 359 | #endif | ||
| 360 | |||
| 361 | switch (cmd) { | ||
| 362 | case LIRC_GET_FEATURES: | ||
| 363 | case LIRC_GET_SEND_MODE: | ||
| 364 | case LIRC_GET_REC_MODE: | ||
| 365 | retval = put_user(value, (unsigned long *) arg); | ||
| 366 | break; | ||
| 367 | |||
| 368 | case LIRC_SET_SEND_MODE: | ||
| 369 | case LIRC_SET_REC_MODE: | ||
| 370 | retval = get_user(value, (unsigned long *) arg); | ||
| 371 | break; | ||
| 372 | #ifdef LIRC_ON_SA1100 | ||
| 373 | case LIRC_SET_SEND_DUTY_CYCLE: | ||
| 374 | retval = get_user(ivalue, (unsigned int *) arg); | ||
| 375 | if (retval) | ||
| 376 | return retval; | ||
| 377 | if (ivalue <= 0 || ivalue > 100) | ||
| 378 | return -EINVAL; | ||
| 379 | /* (ivalue/100)*(1000000/freq) */ | ||
| 380 | duty_cycle = ivalue; | ||
| 381 | pulse_width = (unsigned long) duty_cycle*10000/freq; | ||
| 382 | space_width = (unsigned long) 1000000L/freq-pulse_width; | ||
| 383 | if (pulse_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY) | ||
| 384 | pulse_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY; | ||
| 385 | if (space_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY) | ||
| 386 | space_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY; | ||
| 387 | break; | ||
| 388 | case LIRC_SET_SEND_CARRIER: | ||
| 389 | retval = get_user(ivalue, (unsigned int *) arg); | ||
| 390 | if (retval) | ||
| 391 | return retval; | ||
| 392 | if (ivalue > 500000 || ivalue < 20000) | ||
| 393 | return -EINVAL; | ||
| 394 | freq = ivalue; | ||
| 395 | pulse_width = (unsigned long) duty_cycle*10000/freq; | ||
| 396 | space_width = (unsigned long) 1000000L/freq-pulse_width; | ||
| 397 | if (pulse_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY) | ||
| 398 | pulse_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY; | ||
| 399 | if (space_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY) | ||
| 400 | space_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY; | ||
| 401 | break; | ||
| 402 | #endif | ||
| 403 | default: | ||
| 404 | retval = -ENOIOCTLCMD; | ||
| 405 | |||
| 406 | } | ||
| 407 | |||
| 408 | if (retval) | ||
| 409 | return retval; | ||
| 410 | if (cmd == LIRC_SET_REC_MODE) { | ||
| 411 | if (value != LIRC_MODE_MODE2) | ||
| 412 | retval = -ENOSYS; | ||
| 413 | } else if (cmd == LIRC_SET_SEND_MODE) { | ||
| 414 | if (value != LIRC_MODE_PULSE) | ||
| 415 | retval = -ENOSYS; | ||
| 416 | } | ||
| 417 | |||
| 418 | return retval; | ||
| 419 | } | ||
| 420 | |||
| 421 | static void add_read_queue(int flag, unsigned long val) | ||
| 422 | { | ||
| 423 | unsigned int new_rx_tail; | ||
| 424 | int newval; | ||
| 425 | |||
| 426 | dprintk("add flag %d with val %lu\n", flag, val); | ||
| 427 | |||
| 428 | newval = val & PULSE_MASK; | ||
| 429 | |||
| 430 | /* | ||
| 431 | * statistically, pulses are ~TIME_CONST/2 too long. we could | ||
| 432 | * maybe make this more exact, but this is good enough | ||
| 433 | */ | ||
| 434 | if (flag) { | ||
| 435 | /* pulse */ | ||
| 436 | if (newval > TIME_CONST/2) | ||
| 437 | newval -= TIME_CONST/2; | ||
| 438 | else /* should not ever happen */ | ||
| 439 | newval = 1; | ||
| 440 | newval |= PULSE_BIT; | ||
| 441 | } else { | ||
| 442 | newval += TIME_CONST/2; | ||
| 443 | } | ||
| 444 | new_rx_tail = (rx_tail + 1) & (RBUF_LEN - 1); | ||
| 445 | if (new_rx_tail == rx_head) { | ||
| 446 | dprintk("Buffer overrun.\n"); | ||
| 447 | return; | ||
| 448 | } | ||
| 449 | rx_buf[rx_tail] = newval; | ||
| 450 | rx_tail = new_rx_tail; | ||
| 451 | wake_up_interruptible(&lirc_read_queue); | ||
| 452 | } | ||
| 453 | |||
| 454 | static struct file_operations lirc_fops = { | ||
| 455 | .owner = THIS_MODULE, | ||
| 456 | .read = lirc_read, | ||
| 457 | .write = lirc_write, | ||
| 458 | .poll = lirc_poll, | ||
| 459 | .unlocked_ioctl = lirc_ioctl, | ||
| 460 | .open = lirc_dev_fop_open, | ||
| 461 | .release = lirc_dev_fop_close, | ||
| 462 | }; | ||
| 463 | |||
| 464 | static int set_use_inc(void *data) | ||
| 465 | { | ||
| 466 | return 0; | ||
| 467 | } | ||
| 468 | |||
| 469 | static void set_use_dec(void *data) | ||
| 470 | { | ||
| 471 | } | ||
| 472 | |||
| 473 | static struct lirc_driver driver = { | ||
| 474 | .name = LIRC_DRIVER_NAME, | ||
| 475 | .minor = -1, | ||
| 476 | .code_length = 1, | ||
| 477 | .sample_rate = 0, | ||
| 478 | .data = NULL, | ||
| 479 | .add_to_buf = NULL, | ||
| 480 | .set_use_inc = set_use_inc, | ||
| 481 | .set_use_dec = set_use_dec, | ||
| 482 | .fops = &lirc_fops, | ||
| 483 | .dev = NULL, | ||
| 484 | .owner = THIS_MODULE, | ||
| 485 | }; | ||
| 486 | |||
| 487 | |||
| 488 | static int init_chrdev(void) | ||
| 489 | { | ||
| 490 | driver.minor = lirc_register_driver(&driver); | ||
| 491 | if (driver.minor < 0) { | ||
| 492 | printk(KERN_ERR LIRC_DRIVER_NAME ": init_chrdev() failed.\n"); | ||
| 493 | return -EIO; | ||
| 494 | } | ||
| 495 | return 0; | ||
| 496 | } | ||
| 497 | |||
| 498 | static void drop_chrdev(void) | ||
| 499 | { | ||
| 500 | lirc_unregister_driver(driver.minor); | ||
| 501 | } | ||
| 502 | |||
| 503 | /* SECTION: Hardware */ | ||
| 504 | static long delta(struct timeval *tv1, struct timeval *tv2) | ||
| 505 | { | ||
| 506 | unsigned long deltv; | ||
| 507 | |||
| 508 | deltv = tv2->tv_sec - tv1->tv_sec; | ||
| 509 | if (deltv > 15) | ||
| 510 | deltv = 0xFFFFFF; | ||
| 511 | else | ||
| 512 | deltv = deltv*1000000 + | ||
| 513 | tv2->tv_usec - | ||
| 514 | tv1->tv_usec; | ||
| 515 | return deltv; | ||
| 516 | } | ||
| 517 | |||
| 518 | static void sir_timeout(unsigned long data) | ||
| 519 | { | ||
| 520 | /* | ||
| 521 | * if last received signal was a pulse, but receiving stopped | ||
| 522 | * within the 9 bit frame, we need to finish this pulse and | ||
| 523 | * simulate a signal change to from pulse to space. Otherwise | ||
| 524 | * upper layers will receive two sequences next time. | ||
| 525 | */ | ||
| 526 | |||
| 527 | unsigned long flags; | ||
| 528 | unsigned long pulse_end; | ||
| 529 | |||
| 530 | /* avoid interference with interrupt */ | ||
| 531 | spin_lock_irqsave(&timer_lock, flags); | ||
| 532 | if (last_value) { | ||
| 533 | #ifndef LIRC_ON_SA1100 | ||
| 534 | /* clear unread bits in UART and restart */ | ||
| 535 | outb(UART_FCR_CLEAR_RCVR, io + UART_FCR); | ||
| 536 | #endif | ||
| 537 | /* determine 'virtual' pulse end: */ | ||
| 538 | pulse_end = delta(&last_tv, &last_intr_tv); | ||
| 539 | dprintk("timeout add %d for %lu usec\n", last_value, pulse_end); | ||
| 540 | add_read_queue(last_value, pulse_end); | ||
| 541 | last_value = 0; | ||
| 542 | last_tv = last_intr_tv; | ||
| 543 | } | ||
| 544 | spin_unlock_irqrestore(&timer_lock, flags); | ||
| 545 | } | ||
| 546 | |||
| 547 | static irqreturn_t sir_interrupt(int irq, void *dev_id) | ||
| 548 | { | ||
| 549 | unsigned char data; | ||
| 550 | struct timeval curr_tv; | ||
| 551 | static unsigned long deltv; | ||
| 552 | #ifdef LIRC_ON_SA1100 | ||
| 553 | int status; | ||
| 554 | static int n; | ||
| 555 | |||
| 556 | status = Ser2UTSR0; | ||
| 557 | /* | ||
| 558 | * Deal with any receive errors first. The bytes in error may be | ||
| 559 | * the only bytes in the receive FIFO, so we do this first. | ||
| 560 | */ | ||
| 561 | while (status & UTSR0_EIF) { | ||
| 562 | int bstat; | ||
| 563 | |||
| 564 | if (debug) { | ||
| 565 | dprintk("EIF\n"); | ||
| 566 | bstat = Ser2UTSR1; | ||
| 567 | |||
| 568 | if (bstat & UTSR1_FRE) | ||
| 569 | dprintk("frame error\n"); | ||
| 570 | if (bstat & UTSR1_ROR) | ||
| 571 | dprintk("receive fifo overrun\n"); | ||
| 572 | if (bstat & UTSR1_PRE) | ||
| 573 | dprintk("parity error\n"); | ||
| 574 | } | ||
| 575 | |||
| 576 | bstat = Ser2UTDR; | ||
| 577 | n++; | ||
| 578 | status = Ser2UTSR0; | ||
| 579 | } | ||
| 580 | |||
| 581 | if (status & (UTSR0_RFS | UTSR0_RID)) { | ||
| 582 | do_gettimeofday(&curr_tv); | ||
| 583 | deltv = delta(&last_tv, &curr_tv); | ||
| 584 | do { | ||
| 585 | data = Ser2UTDR; | ||
| 586 | dprintk("%d data: %u\n", n, (unsigned int) data); | ||
| 587 | n++; | ||
| 588 | } while (status & UTSR0_RID && /* do not empty fifo in order to | ||
| 589 | * get UTSR0_RID in any case */ | ||
| 590 | Ser2UTSR1 & UTSR1_RNE); /* data ready */ | ||
| 591 | |||
| 592 | if (status&UTSR0_RID) { | ||
| 593 | add_read_queue(0 , deltv - n * TIME_CONST); /*space*/ | ||
| 594 | add_read_queue(1, n * TIME_CONST); /*pulse*/ | ||
| 595 | n = 0; | ||
| 596 | last_tv = curr_tv; | ||
| 597 | } | ||
| 598 | } | ||
| 599 | |||
| 600 | if (status & UTSR0_TFS) | ||
| 601 | printk(KERN_ERR "transmit fifo not full, shouldn't happen\n"); | ||
| 602 | |||
| 603 | /* We must clear certain bits. */ | ||
| 604 | status &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB); | ||
| 605 | if (status) | ||
| 606 | Ser2UTSR0 = status; | ||
| 607 | #else | ||
| 608 | unsigned long deltintrtv; | ||
| 609 | unsigned long flags; | ||
| 610 | int iir, lsr; | ||
| 611 | |||
| 612 | while ((iir = inb(io + UART_IIR) & UART_IIR_ID)) { | ||
| 613 | switch (iir&UART_IIR_ID) { /* FIXME toto treba preriedit */ | ||
| 614 | case UART_IIR_MSI: | ||
| 615 | (void) inb(io + UART_MSR); | ||
| 616 | break; | ||
| 617 | case UART_IIR_RLSI: | ||
| 618 | (void) inb(io + UART_LSR); | ||
| 619 | break; | ||
| 620 | case UART_IIR_THRI: | ||
| 621 | #if 0 | ||
| 622 | if (lsr & UART_LSR_THRE) /* FIFO is empty */ | ||
| 623 | outb(data, io + UART_TX) | ||
| 624 | #endif | ||
| 625 | break; | ||
| 626 | case UART_IIR_RDI: | ||
| 627 | /* avoid interference with timer */ | ||
| 628 | spin_lock_irqsave(&timer_lock, flags); | ||
| 629 | do { | ||
| 630 | del_timer(&timerlist); | ||
| 631 | data = inb(io + UART_RX); | ||
| 632 | do_gettimeofday(&curr_tv); | ||
| 633 | deltv = delta(&last_tv, &curr_tv); | ||
| 634 | deltintrtv = delta(&last_intr_tv, &curr_tv); | ||
| 635 | dprintk("t %lu, d %d\n", deltintrtv, (int)data); | ||
| 636 | /* | ||
| 637 | * if nothing came in last X cycles, | ||
| 638 | * it was gap | ||
| 639 | */ | ||
| 640 | if (deltintrtv > TIME_CONST * threshold) { | ||
| 641 | if (last_value) { | ||
| 642 | dprintk("GAP\n"); | ||
| 643 | /* simulate signal change */ | ||
| 644 | add_read_queue(last_value, | ||
| 645 | deltv - | ||
| 646 | deltintrtv); | ||
| 647 | last_value = 0; | ||
| 648 | last_tv.tv_sec = | ||
| 649 | last_intr_tv.tv_sec; | ||
| 650 | last_tv.tv_usec = | ||
| 651 | last_intr_tv.tv_usec; | ||
| 652 | deltv = deltintrtv; | ||
| 653 | } | ||
| 654 | } | ||
| 655 | data = 1; | ||
| 656 | if (data ^ last_value) { | ||
| 657 | /* | ||
| 658 | * deltintrtv > 2*TIME_CONST, remember? | ||
| 659 | * the other case is timeout | ||
| 660 | */ | ||
| 661 | add_read_queue(last_value, | ||
| 662 | deltv-TIME_CONST); | ||
| 663 | last_value = data; | ||
| 664 | last_tv = curr_tv; | ||
| 665 | if (last_tv.tv_usec >= TIME_CONST) { | ||
| 666 | last_tv.tv_usec -= TIME_CONST; | ||
| 667 | } else { | ||
| 668 | last_tv.tv_sec--; | ||
| 669 | last_tv.tv_usec += 1000000 - | ||
| 670 | TIME_CONST; | ||
| 671 | } | ||
| 672 | } | ||
| 673 | last_intr_tv = curr_tv; | ||
| 674 | if (data) { | ||
| 675 | /* | ||
| 676 | * start timer for end of | ||
| 677 | * sequence detection | ||
| 678 | */ | ||
| 679 | timerlist.expires = jiffies + | ||
| 680 | SIR_TIMEOUT; | ||
| 681 | add_timer(&timerlist); | ||
| 682 | } | ||
| 683 | |||
| 684 | lsr = inb(io + UART_LSR); | ||
| 685 | } while (lsr & UART_LSR_DR); /* data ready */ | ||
| 686 | spin_unlock_irqrestore(&timer_lock, flags); | ||
| 687 | break; | ||
| 688 | default: | ||
| 689 | break; | ||
| 690 | } | ||
| 691 | } | ||
| 692 | #endif | ||
| 693 | return IRQ_RETVAL(IRQ_HANDLED); | ||
| 694 | } | ||
| 695 | |||
| 696 | #ifdef LIRC_ON_SA1100 | ||
| 697 | static void send_pulse(unsigned long length) | ||
| 698 | { | ||
| 699 | unsigned long k, delay; | ||
| 700 | int flag; | ||
| 701 | |||
| 702 | if (length == 0) | ||
| 703 | return; | ||
| 704 | /* | ||
| 705 | * this won't give us the carrier frequency we really want | ||
| 706 | * due to integer arithmetic, but we can accept this inaccuracy | ||
| 707 | */ | ||
| 708 | |||
| 709 | for (k = flag = 0; k < length; k += delay, flag = !flag) { | ||
| 710 | if (flag) { | ||
| 711 | off(); | ||
| 712 | delay = space_width; | ||
| 713 | } else { | ||
| 714 | on(); | ||
| 715 | delay = pulse_width; | ||
| 716 | } | ||
| 717 | safe_udelay(delay); | ||
| 718 | } | ||
| 719 | off(); | ||
| 720 | } | ||
| 721 | |||
| 722 | static void send_space(unsigned long length) | ||
| 723 | { | ||
| 724 | if (length == 0) | ||
| 725 | return; | ||
| 726 | off(); | ||
| 727 | safe_udelay(length); | ||
| 728 | } | ||
| 729 | #else | ||
| 730 | static void send_space(unsigned long len) | ||
| 731 | { | ||
| 732 | safe_udelay(len); | ||
| 733 | } | ||
| 734 | |||
| 735 | static void send_pulse(unsigned long len) | ||
| 736 | { | ||
| 737 | long bytes_out = len / TIME_CONST; | ||
| 738 | long time_left; | ||
| 739 | |||
| 740 | time_left = (long)len - (long)bytes_out * (long)TIME_CONST; | ||
| 741 | if (bytes_out == 0) { | ||
| 742 | bytes_out++; | ||
| 743 | time_left = 0; | ||
| 744 | } | ||
| 745 | while (bytes_out--) { | ||
| 746 | outb(PULSE, io + UART_TX); | ||
| 747 | /* FIXME treba seriozne cakanie z char/serial.c */ | ||
| 748 | while (!(inb(io + UART_LSR) & UART_LSR_THRE)) | ||
| 749 | ; | ||
| 750 | } | ||
| 751 | #if 0 | ||
| 752 | if (time_left > 0) | ||
| 753 | safe_udelay(time_left); | ||
| 754 | #endif | ||
| 755 | } | ||
| 756 | #endif | ||
| 757 | |||
| 758 | #ifdef CONFIG_SA1100_COLLIE | ||
| 759 | static int sa1100_irda_set_power_collie(int state) | ||
| 760 | { | ||
| 761 | if (state) { | ||
| 762 | /* | ||
| 763 | * 0 - off | ||
| 764 | * 1 - short range, lowest power | ||
| 765 | * 2 - medium range, medium power | ||
| 766 | * 3 - maximum range, high power | ||
| 767 | */ | ||
| 768 | ucb1200_set_io_direction(TC35143_GPIO_IR_ON, | ||
| 769 | TC35143_IODIR_OUTPUT); | ||
| 770 | ucb1200_set_io(TC35143_GPIO_IR_ON, TC35143_IODAT_LOW); | ||
| 771 | udelay(100); | ||
| 772 | } else { | ||
| 773 | /* OFF */ | ||
| 774 | ucb1200_set_io_direction(TC35143_GPIO_IR_ON, | ||
| 775 | TC35143_IODIR_OUTPUT); | ||
| 776 | ucb1200_set_io(TC35143_GPIO_IR_ON, TC35143_IODAT_HIGH); | ||
| 777 | } | ||
| 778 | return 0; | ||
| 779 | } | ||
| 780 | #endif | ||
| 781 | |||
| 782 | static int init_hardware(void) | ||
| 783 | { | ||
| 784 | unsigned long flags; | ||
| 785 | |||
| 786 | spin_lock_irqsave(&hardware_lock, flags); | ||
| 787 | /* reset UART */ | ||
| 788 | #ifdef LIRC_ON_SA1100 | ||
| 789 | #ifdef CONFIG_SA1100_BITSY | ||
| 790 | if (machine_is_bitsy()) { | ||
| 791 | printk(KERN_INFO "Power on IR module\n"); | ||
| 792 | set_bitsy_egpio(EGPIO_BITSY_IR_ON); | ||
| 793 | } | ||
| 794 | #endif | ||
| 795 | #ifdef CONFIG_SA1100_COLLIE | ||
| 796 | sa1100_irda_set_power_collie(3); /* power on */ | ||
| 797 | #endif | ||
| 798 | sr.hscr0 = Ser2HSCR0; | ||
| 799 | |||
| 800 | sr.utcr0 = Ser2UTCR0; | ||
| 801 | sr.utcr1 = Ser2UTCR1; | ||
| 802 | sr.utcr2 = Ser2UTCR2; | ||
| 803 | sr.utcr3 = Ser2UTCR3; | ||
| 804 | sr.utcr4 = Ser2UTCR4; | ||
| 805 | |||
| 806 | sr.utdr = Ser2UTDR; | ||
| 807 | sr.utsr0 = Ser2UTSR0; | ||
| 808 | sr.utsr1 = Ser2UTSR1; | ||
| 809 | |||
| 810 | /* configure GPIO */ | ||
| 811 | /* output */ | ||
| 812 | PPDR |= PPC_TXD2; | ||
| 813 | PSDR |= PPC_TXD2; | ||
| 814 | /* set output to 0 */ | ||
| 815 | off(); | ||
| 816 | |||
| 817 | /* Enable HP-SIR modulation, and ensure that the port is disabled. */ | ||
| 818 | Ser2UTCR3 = 0; | ||
| 819 | Ser2HSCR0 = sr.hscr0 & (~HSCR0_HSSP); | ||
| 820 | |||
| 821 | /* clear status register to prevent unwanted interrupts */ | ||
| 822 | Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB); | ||
| 823 | |||
| 824 | /* 7N1 */ | ||
| 825 | Ser2UTCR0 = UTCR0_1StpBit|UTCR0_7BitData; | ||
| 826 | /* 115200 */ | ||
| 827 | Ser2UTCR1 = 0; | ||
| 828 | Ser2UTCR2 = 1; | ||
| 829 | /* use HPSIR, 1.6 usec pulses */ | ||
| 830 | Ser2UTCR4 = UTCR4_HPSIR|UTCR4_Z1_6us; | ||
| 831 | |||
| 832 | /* enable receiver, receive fifo interrupt */ | ||
| 833 | Ser2UTCR3 = UTCR3_RXE|UTCR3_RIE; | ||
| 834 | |||
| 835 | /* clear status register to prevent unwanted interrupts */ | ||
| 836 | Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB); | ||
| 837 | |||
| 838 | #elif defined(LIRC_SIR_TEKRAM) | ||
| 839 | /* disable FIFO */ | ||
| 840 | soutp(UART_FCR, | ||
| 841 | UART_FCR_CLEAR_RCVR| | ||
| 842 | UART_FCR_CLEAR_XMIT| | ||
| 843 | UART_FCR_TRIGGER_1); | ||
| 844 | |||
| 845 | /* Set DLAB 0. */ | ||
| 846 | soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); | ||
| 847 | |||
| 848 | /* First of all, disable all interrupts */ | ||
| 849 | soutp(UART_IER, sinp(UART_IER) & | ||
| 850 | (~(UART_IER_MSI|UART_IER_RLSI|UART_IER_THRI|UART_IER_RDI))); | ||
| 851 | |||
| 852 | /* Set DLAB 1. */ | ||
| 853 | soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB); | ||
| 854 | |||
| 855 | /* Set divisor to 12 => 9600 Baud */ | ||
| 856 | soutp(UART_DLM, 0); | ||
| 857 | soutp(UART_DLL, 12); | ||
| 858 | |||
| 859 | /* Set DLAB 0. */ | ||
| 860 | soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); | ||
| 861 | |||
| 862 | /* power supply */ | ||
| 863 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); | ||
| 864 | safe_udelay(50*1000); | ||
| 865 | |||
| 866 | /* -DTR low -> reset PIC */ | ||
| 867 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2); | ||
| 868 | udelay(1*1000); | ||
| 869 | |||
| 870 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); | ||
| 871 | udelay(100); | ||
| 872 | |||
| 873 | |||
| 874 | /* -RTS low -> send control byte */ | ||
| 875 | soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2); | ||
| 876 | udelay(7); | ||
| 877 | soutp(UART_TX, TEKRAM_115200|TEKRAM_PW); | ||
| 878 | |||
| 879 | /* one byte takes ~1042 usec to transmit at 9600,8N1 */ | ||
| 880 | udelay(1500); | ||
| 881 | |||
| 882 | /* back to normal operation */ | ||
| 883 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); | ||
| 884 | udelay(50); | ||
| 885 | |||
| 886 | udelay(1500); | ||
| 887 | |||
| 888 | /* read previous control byte */ | ||
| 889 | printk(KERN_INFO LIRC_DRIVER_NAME | ||
| 890 | ": 0x%02x\n", sinp(UART_RX)); | ||
| 891 | |||
| 892 | /* Set DLAB 1. */ | ||
| 893 | soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB); | ||
| 894 | |||
| 895 | /* Set divisor to 1 => 115200 Baud */ | ||
| 896 | soutp(UART_DLM, 0); | ||
| 897 | soutp(UART_DLL, 1); | ||
| 898 | |||
| 899 | /* Set DLAB 0, 8 Bit */ | ||
| 900 | soutp(UART_LCR, UART_LCR_WLEN8); | ||
| 901 | /* enable interrupts */ | ||
| 902 | soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI); | ||
| 903 | #else | ||
| 904 | outb(0, io + UART_MCR); | ||
| 905 | outb(0, io + UART_IER); | ||
| 906 | /* init UART */ | ||
| 907 | /* set DLAB, speed = 115200 */ | ||
| 908 | outb(UART_LCR_DLAB | UART_LCR_WLEN7, io + UART_LCR); | ||
| 909 | outb(1, io + UART_DLL); outb(0, io + UART_DLM); | ||
| 910 | /* 7N1+start = 9 bits at 115200 ~ 3 bits at 44000 */ | ||
| 911 | outb(UART_LCR_WLEN7, io + UART_LCR); | ||
| 912 | /* FIFO operation */ | ||
| 913 | outb(UART_FCR_ENABLE_FIFO, io + UART_FCR); | ||
| 914 | /* interrupts */ | ||
| 915 | /* outb(UART_IER_RLSI|UART_IER_RDI|UART_IER_THRI, io + UART_IER); */ | ||
| 916 | outb(UART_IER_RDI, io + UART_IER); | ||
| 917 | /* turn on UART */ | ||
| 918 | outb(UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2, io + UART_MCR); | ||
| 919 | #ifdef LIRC_SIR_ACTISYS_ACT200L | ||
| 920 | init_act200(); | ||
| 921 | #elif defined(LIRC_SIR_ACTISYS_ACT220L) | ||
| 922 | init_act220(); | ||
| 923 | #endif | ||
| 924 | #endif | ||
| 925 | spin_unlock_irqrestore(&hardware_lock, flags); | ||
| 926 | return 0; | ||
| 927 | } | ||
| 928 | |||
| 929 | static void drop_hardware(void) | ||
| 930 | { | ||
| 931 | unsigned long flags; | ||
| 932 | |||
| 933 | spin_lock_irqsave(&hardware_lock, flags); | ||
| 934 | |||
| 935 | #ifdef LIRC_ON_SA1100 | ||
| 936 | Ser2UTCR3 = 0; | ||
| 937 | |||
| 938 | Ser2UTCR0 = sr.utcr0; | ||
| 939 | Ser2UTCR1 = sr.utcr1; | ||
| 940 | Ser2UTCR2 = sr.utcr2; | ||
| 941 | Ser2UTCR4 = sr.utcr4; | ||
| 942 | Ser2UTCR3 = sr.utcr3; | ||
| 943 | |||
| 944 | Ser2HSCR0 = sr.hscr0; | ||
| 945 | #ifdef CONFIG_SA1100_BITSY | ||
| 946 | if (machine_is_bitsy()) | ||
| 947 | clr_bitsy_egpio(EGPIO_BITSY_IR_ON); | ||
| 948 | #endif | ||
| 949 | #ifdef CONFIG_SA1100_COLLIE | ||
| 950 | sa1100_irda_set_power_collie(0); /* power off */ | ||
| 951 | #endif | ||
| 952 | #else | ||
| 953 | /* turn off interrupts */ | ||
| 954 | outb(0, io + UART_IER); | ||
| 955 | #endif | ||
| 956 | spin_unlock_irqrestore(&hardware_lock, flags); | ||
| 957 | } | ||
| 958 | |||
| 959 | /* SECTION: Initialisation */ | ||
| 960 | |||
| 961 | static int init_port(void) | ||
| 962 | { | ||
| 963 | int retval; | ||
| 964 | |||
| 965 | /* get I/O port access and IRQ line */ | ||
| 966 | #ifndef LIRC_ON_SA1100 | ||
| 967 | if (request_region(io, 8, LIRC_DRIVER_NAME) == NULL) { | ||
| 968 | printk(KERN_ERR LIRC_DRIVER_NAME | ||
| 969 | ": i/o port 0x%.4x already in use.\n", io); | ||
| 970 | return -EBUSY; | ||
| 971 | } | ||
| 972 | #endif | ||
| 973 | retval = request_irq(irq, sir_interrupt, IRQF_DISABLED, | ||
| 974 | LIRC_DRIVER_NAME, NULL); | ||
| 975 | if (retval < 0) { | ||
| 976 | # ifndef LIRC_ON_SA1100 | ||
| 977 | release_region(io, 8); | ||
| 978 | # endif | ||
| 979 | printk(KERN_ERR LIRC_DRIVER_NAME | ||
| 980 | ": IRQ %d already in use.\n", | ||
| 981 | irq); | ||
| 982 | return retval; | ||
| 983 | } | ||
| 984 | #ifndef LIRC_ON_SA1100 | ||
| 985 | printk(KERN_INFO LIRC_DRIVER_NAME | ||
| 986 | ": I/O port 0x%.4x, IRQ %d.\n", | ||
| 987 | io, irq); | ||
| 988 | #endif | ||
| 989 | |||
| 990 | init_timer(&timerlist); | ||
| 991 | timerlist.function = sir_timeout; | ||
| 992 | timerlist.data = 0xabadcafe; | ||
| 993 | |||
| 994 | return 0; | ||
| 995 | } | ||
| 996 | |||
| 997 | static void drop_port(void) | ||
| 998 | { | ||
| 999 | free_irq(irq, NULL); | ||
| 1000 | del_timer_sync(&timerlist); | ||
| 1001 | #ifndef LIRC_ON_SA1100 | ||
| 1002 | release_region(io, 8); | ||
| 1003 | #endif | ||
| 1004 | } | ||
| 1005 | |||
| 1006 | #ifdef LIRC_SIR_ACTISYS_ACT200L | ||
| 1007 | /* Crystal/Cirrus CS8130 IR transceiver, used in Actisys Act200L dongle */ | ||
| 1008 | /* some code borrowed from Linux IRDA driver */ | ||
| 1009 | |||
| 1010 | /* Register 0: Control register #1 */ | ||
| 1011 | #define ACT200L_REG0 0x00 | ||
| 1012 | #define ACT200L_TXEN 0x01 /* Enable transmitter */ | ||
| 1013 | #define ACT200L_RXEN 0x02 /* Enable receiver */ | ||
| 1014 | #define ACT200L_ECHO 0x08 /* Echo control chars */ | ||
| 1015 | |||
| 1016 | /* Register 1: Control register #2 */ | ||
| 1017 | #define ACT200L_REG1 0x10 | ||
| 1018 | #define ACT200L_LODB 0x01 /* Load new baud rate count value */ | ||
| 1019 | #define ACT200L_WIDE 0x04 /* Expand the maximum allowable pulse */ | ||
| 1020 | |||
| 1021 | /* Register 3: Transmit mode register #2 */ | ||
| 1022 | #define ACT200L_REG3 0x30 | ||
| 1023 | #define ACT200L_B0 0x01 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */ | ||
| 1024 | #define ACT200L_B1 0x02 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */ | ||
| 1025 | #define ACT200L_CHSY 0x04 /* StartBit Synced 0=bittime, 1=startbit */ | ||
| 1026 | |||
| 1027 | /* Register 4: Output Power register */ | ||
| 1028 | #define ACT200L_REG4 0x40 | ||
| 1029 | #define ACT200L_OP0 0x01 /* Enable LED1C output */ | ||
| 1030 | #define ACT200L_OP1 0x02 /* Enable LED2C output */ | ||
| 1031 | #define ACT200L_BLKR 0x04 | ||
| 1032 | |||
| 1033 | /* Register 5: Receive Mode register */ | ||
| 1034 | #define ACT200L_REG5 0x50 | ||
| 1035 | #define ACT200L_RWIDL 0x01 /* fixed 1.6us pulse mode */ | ||
| 1036 | /*.. other various IRDA bit modes, and TV remote modes..*/ | ||
| 1037 | |||
| 1038 | /* Register 6: Receive Sensitivity register #1 */ | ||
| 1039 | #define ACT200L_REG6 0x60 | ||
| 1040 | #define ACT200L_RS0 0x01 /* receive threshold bit 0 */ | ||
| 1041 | #define ACT200L_RS1 0x02 /* receive threshold bit 1 */ | ||
| 1042 | |||
| 1043 | /* Register 7: Receive Sensitivity register #2 */ | ||
| 1044 | #define ACT200L_REG7 0x70 | ||
| 1045 | #define ACT200L_ENPOS 0x04 /* Ignore the falling edge */ | ||
| 1046 | |||
| 1047 | /* Register 8,9: Baud Rate Divider register #1,#2 */ | ||
| 1048 | #define ACT200L_REG8 0x80 | ||
| 1049 | #define ACT200L_REG9 0x90 | ||
| 1050 | |||
| 1051 | #define ACT200L_2400 0x5f | ||
| 1052 | #define ACT200L_9600 0x17 | ||
| 1053 | #define ACT200L_19200 0x0b | ||
| 1054 | #define ACT200L_38400 0x05 | ||
| 1055 | #define ACT200L_57600 0x03 | ||
| 1056 | #define ACT200L_115200 0x01 | ||
| 1057 | |||
| 1058 | /* Register 13: Control register #3 */ | ||
| 1059 | #define ACT200L_REG13 0xd0 | ||
| 1060 | #define ACT200L_SHDW 0x01 /* Enable access to shadow registers */ | ||
| 1061 | |||
| 1062 | /* Register 15: Status register */ | ||
| 1063 | #define ACT200L_REG15 0xf0 | ||
| 1064 | |||
| 1065 | /* Register 21: Control register #4 */ | ||
| 1066 | #define ACT200L_REG21 0x50 | ||
| 1067 | #define ACT200L_EXCK 0x02 /* Disable clock output driver */ | ||
| 1068 | #define ACT200L_OSCL 0x04 /* oscillator in low power, medium accuracy mode */ | ||
| 1069 | |||
| 1070 | static void init_act200(void) | ||
| 1071 | { | ||
| 1072 | int i; | ||
| 1073 | __u8 control[] = { | ||
| 1074 | ACT200L_REG15, | ||
| 1075 | ACT200L_REG13 | ACT200L_SHDW, | ||
| 1076 | ACT200L_REG21 | ACT200L_EXCK | ACT200L_OSCL, | ||
| 1077 | ACT200L_REG13, | ||
| 1078 | ACT200L_REG7 | ACT200L_ENPOS, | ||
| 1079 | ACT200L_REG6 | ACT200L_RS0 | ACT200L_RS1, | ||
| 1080 | ACT200L_REG5 | ACT200L_RWIDL, | ||
| 1081 | ACT200L_REG4 | ACT200L_OP0 | ACT200L_OP1 | ACT200L_BLKR, | ||
| 1082 | ACT200L_REG3 | ACT200L_B0, | ||
| 1083 | ACT200L_REG0 | ACT200L_TXEN | ACT200L_RXEN, | ||
| 1084 | ACT200L_REG8 | (ACT200L_115200 & 0x0f), | ||
| 1085 | ACT200L_REG9 | ((ACT200L_115200 >> 4) & 0x0f), | ||
| 1086 | ACT200L_REG1 | ACT200L_LODB | ACT200L_WIDE | ||
| 1087 | }; | ||
| 1088 | |||
| 1089 | /* Set DLAB 1. */ | ||
| 1090 | soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8); | ||
| 1091 | |||
| 1092 | /* Set divisor to 12 => 9600 Baud */ | ||
| 1093 | soutp(UART_DLM, 0); | ||
| 1094 | soutp(UART_DLL, 12); | ||
| 1095 | |||
| 1096 | /* Set DLAB 0. */ | ||
| 1097 | soutp(UART_LCR, UART_LCR_WLEN8); | ||
| 1098 | /* Set divisor to 12 => 9600 Baud */ | ||
| 1099 | |||
| 1100 | /* power supply */ | ||
| 1101 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); | ||
| 1102 | for (i = 0; i < 50; i++) | ||
| 1103 | safe_udelay(1000); | ||
| 1104 | |||
| 1105 | /* Reset the dongle : set RTS low for 25 ms */ | ||
| 1106 | soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2); | ||
| 1107 | for (i = 0; i < 25; i++) | ||
| 1108 | udelay(1000); | ||
| 1109 | |||
| 1110 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); | ||
| 1111 | udelay(100); | ||
| 1112 | |||
| 1113 | /* Clear DTR and set RTS to enter command mode */ | ||
| 1114 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2); | ||
| 1115 | udelay(7); | ||
| 1116 | |||
| 1117 | /* send out the control register settings for 115K 7N1 SIR operation */ | ||
| 1118 | for (i = 0; i < sizeof(control); i++) { | ||
| 1119 | soutp(UART_TX, control[i]); | ||
| 1120 | /* one byte takes ~1042 usec to transmit at 9600,8N1 */ | ||
| 1121 | udelay(1500); | ||
| 1122 | } | ||
| 1123 | |||
| 1124 | /* back to normal operation */ | ||
| 1125 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); | ||
| 1126 | udelay(50); | ||
| 1127 | |||
| 1128 | udelay(1500); | ||
| 1129 | soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB); | ||
| 1130 | |||
| 1131 | /* Set DLAB 1. */ | ||
| 1132 | soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7); | ||
| 1133 | |||
| 1134 | /* Set divisor to 1 => 115200 Baud */ | ||
| 1135 | soutp(UART_DLM, 0); | ||
| 1136 | soutp(UART_DLL, 1); | ||
| 1137 | |||
| 1138 | /* Set DLAB 0. */ | ||
| 1139 | soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); | ||
| 1140 | |||
| 1141 | /* Set DLAB 0, 7 Bit */ | ||
| 1142 | soutp(UART_LCR, UART_LCR_WLEN7); | ||
| 1143 | |||
| 1144 | /* enable interrupts */ | ||
| 1145 | soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI); | ||
| 1146 | } | ||
| 1147 | #endif | ||
| 1148 | |||
| 1149 | #ifdef LIRC_SIR_ACTISYS_ACT220L | ||
| 1150 | /* | ||
| 1151 | * Derived from linux IrDA driver (net/irda/actisys.c) | ||
| 1152 | * Drop me a mail for any kind of comment: maxx@spaceboyz.net | ||
| 1153 | */ | ||
| 1154 | |||
| 1155 | void init_act220(void) | ||
| 1156 | { | ||
| 1157 | int i; | ||
| 1158 | |||
| 1159 | /* DLAB 1 */ | ||
| 1160 | soutp(UART_LCR, UART_LCR_DLAB|UART_LCR_WLEN7); | ||
| 1161 | |||
| 1162 | /* 9600 baud */ | ||
| 1163 | soutp(UART_DLM, 0); | ||
| 1164 | soutp(UART_DLL, 12); | ||
| 1165 | |||
| 1166 | /* DLAB 0 */ | ||
| 1167 | soutp(UART_LCR, UART_LCR_WLEN7); | ||
| 1168 | |||
| 1169 | /* reset the dongle, set DTR low for 10us */ | ||
| 1170 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2); | ||
| 1171 | udelay(10); | ||
| 1172 | |||
| 1173 | /* back to normal (still 9600) */ | ||
| 1174 | soutp(UART_MCR, UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2); | ||
| 1175 | |||
| 1176 | /* | ||
| 1177 | * send RTS pulses until we reach 115200 | ||
| 1178 | * i hope this is really the same for act220l/act220l+ | ||
| 1179 | */ | ||
| 1180 | for (i = 0; i < 3; i++) { | ||
| 1181 | udelay(10); | ||
| 1182 | /* set RTS low for 10 us */ | ||
| 1183 | soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2); | ||
| 1184 | udelay(10); | ||
| 1185 | /* set RTS high for 10 us */ | ||
| 1186 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); | ||
| 1187 | } | ||
| 1188 | |||
| 1189 | /* back to normal operation */ | ||
| 1190 | udelay(1500); /* better safe than sorry ;) */ | ||
| 1191 | |||
| 1192 | /* Set DLAB 1. */ | ||
| 1193 | soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7); | ||
| 1194 | |||
| 1195 | /* Set divisor to 1 => 115200 Baud */ | ||
| 1196 | soutp(UART_DLM, 0); | ||
| 1197 | soutp(UART_DLL, 1); | ||
| 1198 | |||
| 1199 | /* Set DLAB 0, 7 Bit */ | ||
| 1200 | /* The dongle doesn't seem to have any problems with operation at 7N1 */ | ||
| 1201 | soutp(UART_LCR, UART_LCR_WLEN7); | ||
| 1202 | |||
| 1203 | /* enable interrupts */ | ||
| 1204 | soutp(UART_IER, UART_IER_RDI); | ||
| 1205 | } | ||
| 1206 | #endif | ||
| 1207 | |||
| 1208 | static int init_lirc_sir(void) | ||
| 1209 | { | ||
| 1210 | int retval; | ||
| 1211 | |||
| 1212 | init_waitqueue_head(&lirc_read_queue); | ||
| 1213 | retval = init_port(); | ||
| 1214 | if (retval < 0) | ||
| 1215 | return retval; | ||
| 1216 | init_hardware(); | ||
| 1217 | printk(KERN_INFO LIRC_DRIVER_NAME | ||
| 1218 | ": Installed.\n"); | ||
| 1219 | return 0; | ||
| 1220 | } | ||
| 1221 | |||
| 1222 | |||
| 1223 | static int __init lirc_sir_init(void) | ||
| 1224 | { | ||
| 1225 | int retval; | ||
| 1226 | |||
| 1227 | retval = init_chrdev(); | ||
| 1228 | if (retval < 0) | ||
| 1229 | return retval; | ||
| 1230 | retval = init_lirc_sir(); | ||
| 1231 | if (retval) { | ||
| 1232 | drop_chrdev(); | ||
| 1233 | return retval; | ||
| 1234 | } | ||
| 1235 | return 0; | ||
| 1236 | } | ||
| 1237 | |||
| 1238 | static void __exit lirc_sir_exit(void) | ||
| 1239 | { | ||
| 1240 | drop_hardware(); | ||
| 1241 | drop_chrdev(); | ||
| 1242 | drop_port(); | ||
| 1243 | printk(KERN_INFO LIRC_DRIVER_NAME ": Uninstalled.\n"); | ||
| 1244 | } | ||
| 1245 | |||
| 1246 | module_init(lirc_sir_init); | ||
| 1247 | module_exit(lirc_sir_exit); | ||
| 1248 | |||
| 1249 | #ifdef LIRC_SIR_TEKRAM | ||
| 1250 | MODULE_DESCRIPTION("Infrared receiver driver for Tekram Irmate 210"); | ||
| 1251 | MODULE_AUTHOR("Christoph Bartelmus"); | ||
| 1252 | #elif defined(LIRC_ON_SA1100) | ||
| 1253 | MODULE_DESCRIPTION("LIRC driver for StrongARM SA1100 embedded microprocessor"); | ||
| 1254 | MODULE_AUTHOR("Christoph Bartelmus"); | ||
| 1255 | #elif defined(LIRC_SIR_ACTISYS_ACT200L) | ||
| 1256 | MODULE_DESCRIPTION("LIRC driver for Actisys Act200L"); | ||
| 1257 | MODULE_AUTHOR("Karl Bongers"); | ||
| 1258 | #elif defined(LIRC_SIR_ACTISYS_ACT220L) | ||
| 1259 | MODULE_DESCRIPTION("LIRC driver for Actisys Act220L(+)"); | ||
| 1260 | MODULE_AUTHOR("Jan Roemisch"); | ||
| 1261 | #else | ||
| 1262 | MODULE_DESCRIPTION("Infrared receiver driver for SIR type serial ports"); | ||
| 1263 | MODULE_AUTHOR("Milan Pikula"); | ||
| 1264 | #endif | ||
| 1265 | MODULE_LICENSE("GPL"); | ||
| 1266 | |||
| 1267 | #ifdef LIRC_ON_SA1100 | ||
| 1268 | module_param(irq, int, S_IRUGO); | ||
| 1269 | MODULE_PARM_DESC(irq, "Interrupt (16)"); | ||
| 1270 | #else | ||
| 1271 | module_param(io, int, S_IRUGO); | ||
| 1272 | MODULE_PARM_DESC(io, "I/O address base (0x3f8 or 0x2f8)"); | ||
| 1273 | |||
| 1274 | module_param(irq, int, S_IRUGO); | ||
| 1275 | MODULE_PARM_DESC(irq, "Interrupt (4 or 3)"); | ||
| 1276 | |||
| 1277 | module_param(threshold, int, S_IRUGO); | ||
| 1278 | MODULE_PARM_DESC(threshold, "space detection threshold (3)"); | ||
| 1279 | #endif | ||
| 1280 | |||
| 1281 | module_param(debug, bool, S_IRUGO | S_IWUSR); | ||
| 1282 | MODULE_PARM_DESC(debug, "Enable debugging messages"); | ||