Merge tag 'pm+acpi-4.6-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm

Pull power management and ACPI fixes from Rafael Wysocki: "Fixes for some issues discovered after recent changes and for some that have just been found lately regardless of those changes (intel_pstate, intel_idle, PM core, mailbox/pcc, turbostat) plus support for some new CPU models (intel_idle, Intel RAPL driver, turbostat) and documentation updates (intel_pstate, PM core). Specifics: - intel_pstate fixes for two issues exposed by the recent switch over from using timers and for one issue introduced during the 4.4 cycle plus new comments describing data structures used by the driver (Rafael Wysocki, Srinivas Pandruvada). - intel_idle fixes related to CPU offline/online (Richard Cochran). - intel_idle support (new CPU IDs and state definitions mostly) for Skylake-X and Kabylake processors (Len Brown). - PCC mailbox driver fix for an out-of-bounds memory access that may cause the kernel to panic() (Shanker Donthineni). - New (missing) CPU ID for one apparently overlooked Haswell model in the Intel RAPL power capping driver (Srinivas Pandruvada). - Fix for the PM core's wakeup IRQs framework to make it work after wakeup settings reconfiguration from sysfs (Grygorii Strashko). - Runtime PM documentation update to make it describe what needs to be done during device removal more precisely (Krzysztof Kozlowski). - Stale comment removal cleanup in the cpufreq-dt driver (Viresh Kumar). - turbostat utility fixes and support for Broxton, Skylake-X and Kabylake processors (Len Brown)" * tag 'pm+acpi-4.6-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (28 commits) PM / wakeirq: fix wakeirq setting after wakup re-configuration from sysfs tools/power turbostat: work around RC6 counter wrap tools/power turbostat: initial KBL support tools/power turbostat: initial SKX support tools/power turbostat: decode BXT TSC frequency via CPUID tools/power turbostat: initial BXT support tools/power turbostat: print IRTL MSRs tools/power turbostat: SGX state should print only if --debug intel_idle: Add KBL support intel_idle: Add SKX support intel_idle: Clean up all registered devices on exit. intel_idle: Propagate hot plug errors. intel_idle: Don't overreact to a cpuidle registration failure. intel_idle: Setup the timer broadcast only on successful driver load. intel_idle: Avoid a double free of the per-CPU data. intel_idle: Fix dangling registration on error path. intel_idle: Fix deallocation order on the driver exit path. intel_idle: Remove redundant initialization calls. intel_idle: Fix a helper function's return value. intel_idle: remove useless return from void function. ...

Linus Torvalds committed 10 years ago

Commit 40bca9d2 parents 9ef11ce 73659be9 files · +380 −62Browse files

Unified · Split

9 files

Documentation/power/runtime_pm.txt +4 −0
arch/x86/include/asm/msr-index.h +8 −0
drivers/base/power/wakeup.c +2 −0
drivers/cpufreq/cpufreq-dt.c +0 −3
drivers/cpufreq/intel_pstate.c +189 −17
drivers/idle/intel_idle.c +67 −30
drivers/mailbox/pcc.c +2 −2
drivers/powercap/intel_rapl.c +1 −0
tools/power/x86/turbostat/turbostat.c +107 −10

Documentation/power/runtime_pm.txt+4−0

@@ -586,6 +586,10 @@ drivers to make their ->remove() callbacks avoid races with runtime PM directly, · 585 unmodified lines
586	586	but also it allows of more flexibility in the handling of devices during the
587	587	removal of their drivers.
588	588
	589	+Drivers in ->remove() callback should undo the runtime PM changes done
	590	+in ->probe(). Usually this means calling pm_runtime_disable(),
	591	+pm_runtime_dont_use_autosuspend() etc.
	592	+
589	593	The user space can effectively disallow the driver of the device to power manage
590	594	it at run time by changing the value of its /sys/devices/.../power/control
591	595	attribute to "on", which causes pm_runtime_forbid() to be called. In principle,

arch/x86/include/asm/msr-index.h+8−0

@@ -167,6 +167,14 @@ · 166 unmodified lines
167	167	#define MSR_PKG_C9_RESIDENCY 0x00000631
168	168	#define MSR_PKG_C10_RESIDENCY 0x00000632
169	169
	170	+/* Interrupt Response Limit */
	171	+#define MSR_PKGC3_IRTL 0x0000060a
	172	+#define MSR_PKGC6_IRTL 0x0000060b
	173	+#define MSR_PKGC7_IRTL 0x0000060c
	174	+#define MSR_PKGC8_IRTL 0x00000633
	175	+#define MSR_PKGC9_IRTL 0x00000634
	176	+#define MSR_PKGC10_IRTL 0x00000635
	177	+
170	178	/* Run Time Average Power Limiting (RAPL) Interface */
171	179
172	180	#define MSR_RAPL_POWER_UNIT 0x00000606

drivers/base/power/wakeup.c+2−0

@@ -246,6 +246,8 @@ static int device_wakeup_attach(struct device dev, struct wakeup_source ws) · 245 unmodified lines
246	246	return -EEXIST;
247	247	}
248	248	dev->power.wakeup = ws;
	249	+ if (dev->power.wakeirq)
	250	+ device_wakeup_attach_irq(dev, dev->power.wakeirq);
249	251	spin_unlock_irq(&dev->power.lock);
250	252	return 0;
251	253	}

drivers/cpufreq/cpufreq-dt.c+0−3

@@ -4,9 +4,6 @@ · 3 unmodified lines
4	4	* Copyright (C) 2014 Linaro.
5	5	* Viresh Kumar <viresh.kumar@linaro.org>
6	6	*
7		− * The OPP code in function set_target() is reused from
8		− * drivers/cpufreq/omap-cpufreq.c
9		− *
10	7	* This program is free software; you can redistribute it and/or modify
11	8	* it under the terms of the GNU General Public License version 2 as
12	9	* published by the Free Software Foundation.

drivers/cpufreq/intel_pstate.c+189−17

@@ -64,6 +64,25 @@ static inline int ceiling_fp(int32_t x) · 63 unmodified lines
64	64	return ret;
65	65	}
66	66
	67	+/**
	68	+ * struct sample - Store performance sample
	69	+ * @core_pct_busy: Ratio of APERF/MPERF in percent, which is actual
	70	+ * performance during last sample period
	71	+ * @busy_scaled: Scaled busy value which is used to calculate next
	72	+ * P state. This can be different than core_pct_busy
	73	+ * to account for cpu idle period
	74	+ * @aperf: Difference of actual performance frequency clock count
	75	+ * read from APERF MSR between last and current sample
	76	+ * @mperf: Difference of maximum performance frequency clock count
	77	+ * read from MPERF MSR between last and current sample
	78	+ * @tsc: Difference of time stamp counter between last and
	79	+ * current sample
	80	+ * @freq: Effective frequency calculated from APERF/MPERF
	81	+ * @time: Current time from scheduler
	82	+ *
	83	+ * This structure is used in the cpudata structure to store performance sample
	84	+ * data for choosing next P State.
	85	+ */
67	86	struct sample {
68	87	int32_t core_pct_busy;
69	88	int32_t busy_scaled;
@@ -74,6 +93,20 @@ struct sample { · 4 unmodified lines
74	93	u64 time;
75	94	};
76	95
	96	+/**
	97	+ * struct pstate_data - Store P state data
	98	+ * @current_pstate: Current requested P state
	99	+ * @min_pstate: Min P state possible for this platform
	100	+ * @max_pstate: Max P state possible for this platform
	101	+ * @max_pstate_physical:This is physical Max P state for a processor
	102	+ * This can be higher than the max_pstate which can
	103	+ * be limited by platform thermal design power limits
	104	+ * @scaling: Scaling factor to convert frequency to cpufreq
	105	+ * frequency units
	106	+ * @turbo_pstate: Max Turbo P state possible for this platform
	107	+ *
	108	+ * Stores the per cpu model P state limits and current P state.
	109	+ */
77	110	struct pstate_data {
78	111	int current_pstate;
79	112	int min_pstate;
@@ -83,6 +116,19 @@ struct pstate_data { · 3 unmodified lines
83	116	int turbo_pstate;
84	117	};
85	118
	119	+/**
	120	+ * struct vid_data - Stores voltage information data
	121	+ * @min: VID data for this platform corresponding to
	122	+ * the lowest P state
	123	+ * @max: VID data corresponding to the highest P State.
	124	+ * @turbo: VID data for turbo P state
	125	+ * @ratio: Ratio of (vid max - vid min) /
	126	+ * (max P state - Min P State)
	127	+ *
	128	+ * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
	129	+ * This data is used in Atom platforms, where in addition to target P state,
	130	+ * the voltage data needs to be specified to select next P State.
	131	+ */
86	132	struct vid_data {
87	133	int min;
88	134	int max;
@@ -90,6 +136,18 @@ struct vid_data { · 1 unmodified line
90	136	int32_t ratio;
91	137	};
92	138
	139	+/**
	140	+ * struct _pid - Stores PID data
	141	+ * @setpoint: Target set point for busyness or performance
	142	+ * @integral: Storage for accumulated error values
	143	+ * @p_gain: PID proportional gain
	144	+ * @i_gain: PID integral gain
	145	+ * @d_gain: PID derivative gain
	146	+ * @deadband: PID deadband
	147	+ * @last_err: Last error storage for integral part of PID calculation
	148	+ *
	149	+ * Stores PID coefficients and last error for PID controller.
	150	+ */
93	151	struct _pid {
94	152	int setpoint;
95	153	int32_t integral;
@@ -100,6 +158,23 @@ struct _pid { · 4 unmodified lines
100	158	int32_t last_err;
101	159	};
102	160
	161	+/**
	162	+ * struct cpudata - Per CPU instance data storage
	163	+ * @cpu: CPU number for this instance data
	164	+ * @update_util: CPUFreq utility callback information
	165	+ * @pstate: Stores P state limits for this CPU
	166	+ * @vid: Stores VID limits for this CPU
	167	+ * @pid: Stores PID parameters for this CPU
	168	+ * @last_sample_time: Last Sample time
	169	+ * @prev_aperf: Last APERF value read from APERF MSR
	170	+ * @prev_mperf: Last MPERF value read from MPERF MSR
	171	+ * @prev_tsc: Last timestamp counter (TSC) value
	172	+ * @prev_cummulative_iowait: IO Wait time difference from last and
	173	+ * current sample
	174	+ * @sample: Storage for storing last Sample data
	175	+ *
	176	+ * This structure stores per CPU instance data for all CPUs.
	177	+ */
103	178	struct cpudata {
104	179	int cpu;
105	180
@@ -118,6 +193,19 @@ struct cpudata { · 12 unmodified lines
118	193	};
119	194
120	195	static struct cpudata **all_cpu_data;
	196	+
	197	+/**
	198	+ * struct pid_adjust_policy - Stores static PID configuration data
	199	+ * @sample_rate_ms: PID calculation sample rate in ms
	200	+ * @sample_rate_ns: Sample rate calculation in ns
	201	+ * @deadband: PID deadband
	202	+ * @setpoint: PID Setpoint
	203	+ * @p_gain_pct: PID proportional gain
	204	+ * @i_gain_pct: PID integral gain
	205	+ * @d_gain_pct: PID derivative gain
	206	+ *
	207	+ * Stores per CPU model static PID configuration data.
	208	+ */
121	209	struct pstate_adjust_policy {
122	210	int sample_rate_ms;
123	211	s64 sample_rate_ns;
@@ -128,6 +216,20 @@ struct pstate_adjust_policy { · 4 unmodified lines
128	216	int i_gain_pct;
129	217	};
130	218
	219	+/**
	220	+ * struct pstate_funcs - Per CPU model specific callbacks
	221	+ * @get_max: Callback to get maximum non turbo effective P state
	222	+ * @get_max_physical: Callback to get maximum non turbo physical P state
	223	+ * @get_min: Callback to get minimum P state
	224	+ * @get_turbo: Callback to get turbo P state
	225	+ * @get_scaling: Callback to get frequency scaling factor
	226	+ * @get_val: Callback to convert P state to actual MSR write value
	227	+ * @get_vid: Callback to get VID data for Atom platforms
	228	+ * @get_target_pstate: Callback to a function to calculate next P state to use
	229	+ *
	230	+ * Core and Atom CPU models have different way to get P State limits. This
	231	+ * structure is used to store those callbacks.
	232	+ */
131	233	struct pstate_funcs {
132	234	int (*get_max)(void);
133	235	int (*get_max_physical)(void);
@@ -139,6 +241,11 @@ struct pstate_funcs { · 5 unmodified lines
139	241	int32_t (get_target_pstate)(struct cpudata );
140	242	};
141	243
	244	+/**
	245	+ * struct cpu_defaults- Per CPU model default config data
	246	+ * @pid_policy: PID config data
	247	+ * @funcs: Callback function data
	248	+ */
142	249	struct cpu_defaults {
143	250	struct pstate_adjust_policy pid_policy;
144	251	struct pstate_funcs funcs;
@@ -151,6 +258,34 @@ static struct pstate_adjust_policy pid_params; · 6 unmodified lines
151	258	static struct pstate_funcs pstate_funcs;
152	259	static int hwp_active;
153	260
	261	+
	262	+/**
	263	+ * struct perf_limits - Store user and policy limits
	264	+ * @no_turbo: User requested turbo state from intel_pstate sysfs
	265	+ * @turbo_disabled: Platform turbo status either from msr
	266	+ * MSR_IA32_MISC_ENABLE or when maximum available pstate
	267	+ * matches the maximum turbo pstate
	268	+ * @max_perf_pct: Effective maximum performance limit in percentage, this
	269	+ * is minimum of either limits enforced by cpufreq policy
	270	+ * or limits from user set limits via intel_pstate sysfs
	271	+ * @min_perf_pct: Effective minimum performance limit in percentage, this
	272	+ * is maximum of either limits enforced by cpufreq policy
	273	+ * or limits from user set limits via intel_pstate sysfs
	274	+ * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct
	275	+ * This value is used to limit max pstate
	276	+ * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct
	277	+ * This value is used to limit min pstate
	278	+ * @max_policy_pct: The maximum performance in percentage enforced by
	279	+ * cpufreq setpolicy interface
	280	+ * @max_sysfs_pct: The maximum performance in percentage enforced by
	281	+ * intel pstate sysfs interface
	282	+ * @min_policy_pct: The minimum performance in percentage enforced by
	283	+ * cpufreq setpolicy interface
	284	+ * @min_sysfs_pct: The minimum performance in percentage enforced by
	285	+ * intel pstate sysfs interface
	286	+ *
	287	+ * Storage for user and policy defined limits.
	288	+ */
154	289	struct perf_limits {
155	290	int no_turbo;
156	291	int turbo_disabled;
@@ -910,7 +1045,14 @@ static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) · 753 unmodified lines
910	1045	cpu->prev_aperf = aperf;
911	1046	cpu->prev_mperf = mperf;
912	1047	cpu->prev_tsc = tsc;
913		− return true;
	1048	+ /*
	1049	+ * First time this function is invoked in a given cycle, all of the
	1050	+ * previous sample data fields are equal to zero or stale and they must
	1051	+ * be populated with meaningful numbers for things to work, so assume
	1052	+ * that sample.time will always be reset before setting the utilization
	1053	+ * update hook and make the caller skip the sample then.
	1054	+ */
	1055	+ return !!cpu->last_sample_time;
914	1056	}
915	1057
916	1058	static inline int32_t get_avg_frequency(struct cpudata *cpu)
@@ -984,8 +1126,7 @@ static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu) · 67 unmodified lines
984	1126	* enough period of time to adjust our busyness.
985	1127	*/
986	1128	duration_ns = cpu->sample.time - cpu->last_sample_time;
987		− if ((s64)duration_ns > pid_params.sample_rate_ns * 3
988		− && cpu->last_sample_time > 0) {
	1129	+ if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
989	1130	sample_ratio = div_fp(int_tofp(pid_params.sample_rate_ns),
990	1131	int_tofp(duration_ns));
991	1132	core_busy = mul_fp(core_busy, sample_ratio);
@@ -1100,10 +1241,8 @@ static int intel_pstate_init_cpu(unsigned int cpunum) · 108 unmodified lines
1100	1241	intel_pstate_get_cpu_pstates(cpu);
1101	1242
1102	1243	intel_pstate_busy_pid_reset(cpu);
1103		− intel_pstate_sample(cpu, 0);
1104	1244
1105	1245	cpu->update_util.func = intel_pstate_update_util;
1106		− cpufreq_set_update_util_data(cpunum, &cpu->update_util);
1107	1246
1108	1247	pr_debug("intel_pstate: controlling: cpu %d\n", cpunum);
1109	1248
@@ -1122,22 +1261,54 @@ static unsigned int intel_pstate_get(unsigned int cpu_num) · 12 unmodified lines
1122	1261	return get_avg_frequency(cpu);
1123	1262	}
1124	1263
	1264	+static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
	1265	+{
	1266	+ struct cpudata *cpu = all_cpu_data[cpu_num];
	1267	+
	1268	+ /* Prevent intel_pstate_update_util() from using stale data. */
	1269	+ cpu->sample.time = 0;
	1270	+ cpufreq_set_update_util_data(cpu_num, &cpu->update_util);
	1271	+}
	1272	+
	1273	+static void intel_pstate_clear_update_util_hook(unsigned int cpu)
	1274	+{
	1275	+ cpufreq_set_update_util_data(cpu, NULL);
	1276	+ synchronize_sched();
	1277	+}
	1278	+
	1279	+static void intel_pstate_set_performance_limits(struct perf_limits *limits)
	1280	+{
	1281	+ limits->no_turbo = 0;
	1282	+ limits->turbo_disabled = 0;
	1283	+ limits->max_perf_pct = 100;
	1284	+ limits->max_perf = int_tofp(1);
	1285	+ limits->min_perf_pct = 100;
	1286	+ limits->min_perf = int_tofp(1);
	1287	+ limits->max_policy_pct = 100;
	1288	+ limits->max_sysfs_pct = 100;
	1289	+ limits->min_policy_pct = 0;
	1290	+ limits->min_sysfs_pct = 0;
	1291	+}
	1292	+
1125	1293	static int intel_pstate_set_policy(struct cpufreq_policy *policy)
1126	1294	{
1127	1295	if (!policy->cpuinfo.max_freq)
1128	1296	return -ENODEV;
1129	1297
1130		− if (policy->policy == CPUFREQ_POLICY_PERFORMANCE &&
1131		− policy->max >= policy->cpuinfo.max_freq) {
1132		− pr_debug("intel_pstate: set performance\n");
	1298	+ intel_pstate_clear_update_util_hook(policy->cpu);
	1299	+
	1300	+ if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
1133	1301	limits = &performance_limits;
1134		− if (hwp_active)
1135		− intel_pstate_hwp_set(policy->cpus);
1136		− return 0;
	1302	+ if (policy->max >= policy->cpuinfo.max_freq) {
	1303	+ pr_debug("intel_pstate: set performance\n");
	1304	+ intel_pstate_set_performance_limits(limits);
	1305	+ goto out;
	1306	+ }
	1307	+ } else {
	1308	+ pr_debug("intel_pstate: set powersave\n");
	1309	+ limits = &powersave_limits;
1137	1310	}
1138	1311
1139		− pr_debug("intel_pstate: set powersave\n");
1140		− limits = &powersave_limits;
1141	1312	limits->min_policy_pct = (policy->min * 100) / policy->cpuinfo.max_freq;
1142	1313	limits->min_policy_pct = clamp_t(int, limits->min_policy_pct, 0 , 100);
1143	1314	limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100,
@@ -1163,6 +1334,9 @@ static int intel_pstate_set_policy(struct cpufreq_policy *policy) · 19 unmodified lines
1163	1334	limits->max_perf = div_fp(int_tofp(limits->max_perf_pct),
1164	1335	int_tofp(100));
1165	1336
	1337	+ out:
	1338	+ intel_pstate_set_update_util_hook(policy->cpu);
	1339	+
1166	1340	if (hwp_active)
1167	1341	intel_pstate_hwp_set(policy->cpus);
1168	1342
@@ -1187,8 +1361,7 @@ static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) · 18 unmodified lines
1187	1361
1188	1362	pr_debug("intel_pstate: CPU %d exiting\n", cpu_num);
1189	1363
1190		− cpufreq_set_update_util_data(cpu_num, NULL);
1191		− synchronize_sched();
	1364	+ intel_pstate_clear_update_util_hook(cpu_num);
1192	1365
1193	1366	if (hwp_active)
1194	1367	return;
@@ -1455,8 +1628,7 @@ out: · 260 unmodified lines
1455	1628	get_online_cpus();
1456	1629	for_each_online_cpu(cpu) {
1457	1630	if (all_cpu_data[cpu]) {
1458		− cpufreq_set_update_util_data(cpu, NULL);
1459		− synchronize_sched();
	1631	+ intel_pstate_clear_update_util_hook(cpu);
1460	1632	kfree(all_cpu_data[cpu]);
1461	1633	}
1462	1634	}

drivers/idle/intel_idle.c+67−30

@@ -660,6 +660,35 @@ static struct cpuidle_state skl_cstates[] = { · 659 unmodified lines
660	660	.enter = NULL }
661	661	};
662	662
	663	+static struct cpuidle_state skx_cstates[] = {
	664	+ {
	665	+ .name = "C1-SKX",
	666	+ .desc = "MWAIT 0x00",
	667	+ .flags = MWAIT2flg(0x00),
	668	+ .exit_latency = 2,
	669	+ .target_residency = 2,
	670	+ .enter = &intel_idle,
	671	+ .enter_freeze = intel_idle_freeze, },
	672	+ {
	673	+ .name = "C1E-SKX",
	674	+ .desc = "MWAIT 0x01",
	675	+ .flags = MWAIT2flg(0x01),
	676	+ .exit_latency = 10,
	677	+ .target_residency = 20,
	678	+ .enter = &intel_idle,
	679	+ .enter_freeze = intel_idle_freeze, },
	680	+ {
	681	+ .name = "C6-SKX",
	682	+ .desc = "MWAIT 0x20",
	683	+ .flags = MWAIT2flg(0x20) \| CPUIDLE_FLAG_TLB_FLUSHED,
	684	+ .exit_latency = 133,
	685	+ .target_residency = 600,
	686	+ .enter = &intel_idle,
	687	+ .enter_freeze = intel_idle_freeze, },
	688	+ {
	689	+ .enter = NULL }
	690	+};
	691	+
663	692	static struct cpuidle_state atom_cstates[] = {
664	693	{
665	694	.name = "C1E-ATM",
@@ -818,8 +847,11 @@ static int cpu_hotplug_notify(struct notifier_block *n, · 152 unmodified lines
818	847	* driver in this case
819	848	*/
820	849	dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
821		− if (!dev->registered)
822		− intel_idle_cpu_init(hotcpu);
	850	+ if (dev->registered)
	851	+ break;
	852	+
	853	+ if (intel_idle_cpu_init(hotcpu))
	854	+ return NOTIFY_BAD;
823	855
824	856	break;
825	857	}
@@ -904,6 +936,10 @@ static const struct idle_cpu idle_cpu_skl = { · 78 unmodified lines
904	936	.disable_promotion_to_c1e = true,
905	937	};
906	938
	939	+static const struct idle_cpu idle_cpu_skx = {
	940	+ .state_table = skx_cstates,
	941	+ .disable_promotion_to_c1e = true,
	942	+};
907	943
908	944	static const struct idle_cpu idle_cpu_avn = {
909	945	.state_table = avn_cstates,
@@ -945,6 +981,9 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = { · 35 unmodified lines
945	981	ICPU(0x56, idle_cpu_bdw),
946	982	ICPU(0x4e, idle_cpu_skl),
947	983	ICPU(0x5e, idle_cpu_skl),
	984	+ ICPU(0x8e, idle_cpu_skl),
	985	+ ICPU(0x9e, idle_cpu_skl),
	986	+ ICPU(0x55, idle_cpu_skx),
948	987	ICPU(0x57, idle_cpu_knl),
949	988	{}
950	989	};
@@ -987,22 +1026,15 @@ static int __init intel_idle_probe(void) · 36 unmodified lines
987	1026	icpu = (const struct idle_cpu *)id->driver_data;
988	1027	cpuidle_state_table = icpu->state_table;
989	1028
990		− if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
991		− lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
992		− else
993		− on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
994		−
995	1029	pr_debug(PREFIX "v" INTEL_IDLE_VERSION
996	1030	" model 0x%X\n", boot_cpu_data.x86_model);
997	1031
998		− pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
999		− lapic_timer_reliable_states);
1000	1032	return 0;
1001	1033	}
1002	1034
1003	1035	/*
1004	1036	* intel_idle_cpuidle_devices_uninit()
1005		− * unregister, free cpuidle_devices
	1037	+ * Unregisters the cpuidle devices.
1006	1038	*/
1007	1039	static void intel_idle_cpuidle_devices_uninit(void)
1008	1040	{
@@ -1013,9 +1045,6 @@ static void intel_idle_cpuidle_devices_uninit(void) · 4 unmodified lines
1013	1045	dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
1014	1046	cpuidle_unregister_device(dev);
1015	1047	}
1016		−
1017		− free_percpu(intel_idle_cpuidle_devices);
1018		− return;
1019	1048	}
1020	1049
1021	1050	/*
@@ -1111,7 +1140,7 @@ static void intel_idle_state_table_update(void) · 89 unmodified lines
1111	1140	* intel_idle_cpuidle_driver_init()
1112	1141	* allocate, initialize cpuidle_states
1113	1142	*/
1114		−static int __init intel_idle_cpuidle_driver_init(void)
	1143	+static void __init intel_idle_cpuidle_driver_init(void)
1115	1144	{
1116	1145	int cstate;
1117	1146	struct cpuidle_driver *drv = &intel_idle_driver;
@@ -1163,18 +1192,10 @@ static int __init intel_idle_cpuidle_driver_init(void) · 45 unmodified lines
1163	1192	drv->state_count += 1;
1164	1193	}
1165	1194
1166		− if (icpu->auto_demotion_disable_flags)
1167		− on_each_cpu(auto_demotion_disable, NULL, 1);
1168		−
1169	1195	if (icpu->byt_auto_demotion_disable_flag) {
1170	1196	wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);
1171	1197	wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);
1172	1198	}
1173		−
1174		− if (icpu->disable_promotion_to_c1e) /* each-cpu is redundant */
1175		− on_each_cpu(c1e_promotion_disable, NULL, 1);
1176		−
1177		− return 0;
1178	1199	}
1179	1200
1180	1201
@@ -1193,7 +1214,6 @@ static int intel_idle_cpu_init(int cpu) · 12 unmodified lines
1193	1214
1194	1215	if (cpuidle_register_device(dev)) {
1195	1216	pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu);
1196		− intel_idle_cpuidle_devices_uninit();
1197	1217	return -EIO;
1198	1218	}
1199	1219
@@ -1218,40 +1238,51 @@ static int __init intel_idle_init(void) · 18 unmodified lines
1218	1238	if (retval)
1219	1239	return retval;
1220	1240
	1241	+ intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
	1242	+ if (intel_idle_cpuidle_devices == NULL)
	1243	+ return -ENOMEM;
	1244	+
1221	1245	intel_idle_cpuidle_driver_init();
1222	1246	retval = cpuidle_register_driver(&intel_idle_driver);
1223	1247	if (retval) {
1224	1248	struct cpuidle_driver *drv = cpuidle_get_driver();
1225	1249	printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
1226	1250	drv ? drv->name : "none");
	1251	+ free_percpu(intel_idle_cpuidle_devices);
1227	1252	return retval;
1228	1253	}
1229	1254
1230		− intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
1231		− if (intel_idle_cpuidle_devices == NULL)
1232		− return -ENOMEM;
1233		−
1234	1255	cpu_notifier_register_begin();
1235	1256
1236	1257	for_each_online_cpu(i) {
1237	1258	retval = intel_idle_cpu_init(i);
1238	1259	if (retval) {
	1260	+ intel_idle_cpuidle_devices_uninit();
1239	1261	cpu_notifier_register_done();
1240	1262	cpuidle_unregister_driver(&intel_idle_driver);
	1263	+ free_percpu(intel_idle_cpuidle_devices);
1241	1264	return retval;
1242	1265	}
1243	1266	}
1244	1267	__register_cpu_notifier(&cpu_hotplug_notifier);
1245	1268
	1269	+ if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
	1270	+ lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
	1271	+ else
	1272	+ on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
	1273	+
1246	1274	cpu_notifier_register_done();
1247	1275
	1276	+ pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
	1277	+ lapic_timer_reliable_states);
	1278	+
1248	1279	return 0;
1249	1280	}
1250	1281
1251	1282	static void __exit intel_idle_exit(void)
1252	1283	{
1253		− intel_idle_cpuidle_devices_uninit();
1254		− cpuidle_unregister_driver(&intel_idle_driver);
	1284	+ struct cpuidle_device *dev;
	1285	+ int i;
1255	1286
1256	1287	cpu_notifier_register_begin();
1257	1288
@@ -1259,9 +1290,15 @@ static void __exit intel_idle_exit(void) · 1 unmodified line
1259	1290	on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
1260	1291	__unregister_cpu_notifier(&cpu_hotplug_notifier);
1261	1292
	1293	+ for_each_possible_cpu(i) {
	1294	+ dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
	1295	+ cpuidle_unregister_device(dev);
	1296	+ }
	1297	+
1262	1298	cpu_notifier_register_done();
1263	1299
1264		− return;
	1300	+ cpuidle_unregister_driver(&intel_idle_driver);
	1301	+ free_percpu(intel_idle_cpuidle_devices);
1265	1302	}
1266	1303
1267	1304	module_init(intel_idle_init);

drivers/mailbox/pcc.c+2−2

@@ -361,8 +361,6 @@ static int __init acpi_pcc_probe(void) · 360 unmodified lines
361	361	struct acpi_generic_address *db_reg;
362	362	struct acpi_pcct_hw_reduced *pcct_ss;
363	363	pcc_mbox_channels[i].con_priv = pcct_entry;
364		− pcct_entry = (struct acpi_subtable_header *)
365		− ((unsigned long) pcct_entry + pcct_entry->length);
366	364
367	365	/* If doorbell is in system memory cache the virt address */
368	366	pcct_ss = (struct acpi_pcct_hw_reduced *)pcct_entry;
@@ -370,6 +368,8 @@ static int __init acpi_pcc_probe(void) · 1 unmodified line
370	368	if (db_reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
371	369	pcc_doorbell_vaddr[i] = acpi_os_ioremap(db_reg->address,
372	370	db_reg->bit_width/8);
	371	+ pcct_entry = (struct acpi_subtable_header *)
	372	+ ((unsigned long) pcct_entry + pcct_entry->length);
373	373	}
374	374
375	375	pcc_mbox_ctrl.num_chans = count;

drivers/powercap/intel_rapl.c+1−0

@@ -1091,6 +1091,7 @@ static const struct x86_cpu_id rapl_ids[] __initconst = { · 1090 unmodified lines
1091	1091	RAPL_CPU(0x3f, rapl_defaults_hsw_server),/* Haswell servers */
1092	1092	RAPL_CPU(0x4f, rapl_defaults_hsw_server),/* Broadwell servers */
1093	1093	RAPL_CPU(0x45, rapl_defaults_core),/* Haswell ULT */
	1094	+ RAPL_CPU(0x46, rapl_defaults_core),/* Haswell */
1094	1095	RAPL_CPU(0x47, rapl_defaults_core),/* Broadwell-H */
1095	1096	RAPL_CPU(0x4E, rapl_defaults_core),/* Skylake */
1096	1097	RAPL_CPU(0x4C, rapl_defaults_cht),/* Braswell/Cherryview */

tools/power/x86/turbostat/turbostat.c+107−10

@@ -66,6 +66,8 @@ unsigned int do_slm_cstates; · 65 unmodified lines
66	66	unsigned int use_c1_residency_msr;
67	67	unsigned int has_aperf;
68	68	unsigned int has_epb;
	69	+unsigned int do_irtl_snb;
	70	+unsigned int do_irtl_hsw;
69	71	unsigned int units = 1000000; /* MHz etc */
70	72	unsigned int genuine_intel;
71	73	unsigned int has_invariant_tsc;
@@ -187,7 +189,7 @@ struct pkg_data { · 115 unmodified lines
187	189	unsigned long long pkg_any_core_c0;
188	190	unsigned long long pkg_any_gfxe_c0;
189	191	unsigned long long pkg_both_core_gfxe_c0;
190		− unsigned long long gfx_rc6_ms;
	192	+ long long gfx_rc6_ms;
191	193	unsigned int gfx_mhz;
192	194	unsigned int package_id;
193	195	unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */
@@ -621,8 +623,14 @@ int format_counters(struct thread_data t, struct core_data c, · 427 unmodified lines
621	623	outp += sprintf(outp, "%8d", p->pkg_temp_c);
622	624
623	625	/* GFXrc6 */
624		− if (do_gfx_rc6_ms)
625		− outp += sprintf(outp, "%8.2f", 100.0 * p->gfx_rc6_ms / 1000.0 / interval_float);
	626	+ if (do_gfx_rc6_ms) {
	627	+ if (p->gfx_rc6_ms == -1) { /* detect counter reset */
	628	+ outp += sprintf(outp, " *.");
	629	+ } else {
	630	+ outp += sprintf(outp, "%8.2f",
	631	+ p->gfx_rc6_ms / 10.0 / interval_float);
	632	+ }
	633	+ }
626	634
627	635	/* GFXMHz */
628	636	if (do_gfx_mhz)
@@ -766,7 +774,12 @@ delta_package(struct pkg_data new, struct pkg_data old) · 137 unmodified lines
766	774	old->pc10 = new->pc10 - old->pc10;
767	775	old->pkg_temp_c = new->pkg_temp_c;
768	776
769		− old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms;
	777	+ /* flag an error when rc6 counter resets/wraps */
	778	+ if (old->gfx_rc6_ms > new->gfx_rc6_ms)
	779	+ old->gfx_rc6_ms = -1;
	780	+ else
	781	+ old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms;
	782	+
770	783	old->gfx_mhz = new->gfx_mhz;
771	784
772	785	DELTA_WRAP32(new->energy_pkg, old->energy_pkg);
@@ -1296,6 +1309,7 @@ int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, · 523 unmodified lines
1296	1309	int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1297	1310	int amt_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1298	1311	int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
	1312	+int bxt_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1299	1313
1300	1314
1301	1315	static void
@@ -1579,6 +1593,47 @@ dump_config_tdp(void) · 277 unmodified lines
1579	1593	fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
1580	1594	fprintf(outf, ")\n");
1581	1595	}
	1596	+
	1597	+unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
	1598	+
	1599	+void print_irtl(void)
	1600	+{
	1601	+ unsigned long long msr;
	1602	+
	1603	+ get_msr(base_cpu, MSR_PKGC3_IRTL, &msr);
	1604	+ fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr);
	1605	+ fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
	1606	+ (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
	1607	+
	1608	+ get_msr(base_cpu, MSR_PKGC6_IRTL, &msr);
	1609	+ fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr);
	1610	+ fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
	1611	+ (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
	1612	+
	1613	+ get_msr(base_cpu, MSR_PKGC7_IRTL, &msr);
	1614	+ fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr);
	1615	+ fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
	1616	+ (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
	1617	+
	1618	+ if (!do_irtl_hsw)
	1619	+ return;
	1620	+
	1621	+ get_msr(base_cpu, MSR_PKGC8_IRTL, &msr);
	1622	+ fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr);
	1623	+ fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
	1624	+ (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
	1625	+
	1626	+ get_msr(base_cpu, MSR_PKGC9_IRTL, &msr);
	1627	+ fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr);
	1628	+ fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
	1629	+ (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
	1630	+
	1631	+ get_msr(base_cpu, MSR_PKGC10_IRTL, &msr);
	1632	+ fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr);
	1633	+ fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
	1634	+ (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
	1635	+
	1636	+}
1582	1637	void free_fd_percpu(void)
1583	1638	{
1584	1639	int i;
@@ -2144,6 +2199,9 @@ int probe_nhm_msrs(unsigned int family, unsigned int model) · 559 unmodified lines
2144	2199	case 0x56: /* BDX-DE */
2145	2200	case 0x4E: /* SKL */
2146	2201	case 0x5E: /* SKL */
	2202	+ case 0x8E: /* KBL */
	2203	+ case 0x9E: /* KBL */
	2204	+ case 0x55: /* SKX */
2147	2205	pkg_cstate_limits = hsw_pkg_cstate_limits;
2148	2206	break;
2149	2207	case 0x37: /* BYT */
@@ -2156,6 +2214,9 @@ int probe_nhm_msrs(unsigned int family, unsigned int model) · 6 unmodified lines
2156	2214	case 0x57: /* PHI */
2157	2215	pkg_cstate_limits = phi_pkg_cstate_limits;
2158	2216	break;
	2217	+ case 0x5C: /* BXT */
	2218	+ pkg_cstate_limits = bxt_pkg_cstate_limits;
	2219	+ break;
2159	2220	default:
2160	2221	return 0;
2161	2222	}
@@ -2248,6 +2309,9 @@ int has_config_tdp(unsigned int family, unsigned int model) · 86 unmodified lines
2248	2309	case 0x56: /* BDX-DE */
2249	2310	case 0x4E: /* SKL */
2250	2311	case 0x5E: /* SKL */
	2312	+ case 0x8E: /* KBL */
	2313	+ case 0x9E: /* KBL */
	2314	+ case 0x55: /* SKX */
2251	2315
2252	2316	case 0x57: /* Knights Landing */
2253	2317	return 1;
@@ -2585,13 +2649,19 @@ void rapl_probe(unsigned int family, unsigned int model) · 331 unmodified lines
2585	2649	case 0x47: /* BDW */
2586	2650	do_rapl = RAPL_PKG \| RAPL_CORES \| RAPL_CORE_POLICY \| RAPL_GFX \| RAPL_PKG_POWER_INFO;
2587	2651	break;
	2652	+ case 0x5C: /* BXT */
	2653	+ do_rapl = RAPL_PKG \| RAPL_PKG_POWER_INFO;
	2654	+ break;
2588	2655	case 0x4E: /* SKL */
2589	2656	case 0x5E: /* SKL */
	2657	+ case 0x8E: /* KBL */
	2658	+ case 0x9E: /* KBL */
2590	2659	do_rapl = RAPL_PKG \| RAPL_DRAM \| RAPL_DRAM_PERF_STATUS \| RAPL_PKG_PERF_STATUS \| RAPL_PKG_POWER_INFO;
2591	2660	break;
2592	2661	case 0x3F: /* HSX */
2593	2662	case 0x4F: /* BDX */
2594	2663	case 0x56: /* BDX-DE */
	2664	+ case 0x55: /* SKX */
2595	2665	case 0x57: /* KNL */
2596	2666	do_rapl = RAPL_PKG \| RAPL_DRAM \| RAPL_DRAM_POWER_INFO \| RAPL_DRAM_PERF_STATUS \| RAPL_PKG_PERF_STATUS \| RAPL_PKG_POWER_INFO;
2597	2667	break;
@@ -2871,6 +2941,10 @@ int has_snb_msrs(unsigned int family, unsigned int model) · 273 unmodified lines
2871	2941	case 0x56: /* BDX-DE */
2872	2942	case 0x4E: /* SKL */
2873	2943	case 0x5E: /* SKL */
	2944	+ case 0x8E: /* KBL */
	2945	+ case 0x9E: /* KBL */
	2946	+ case 0x55: /* SKX */
	2947	+ case 0x5C: /* BXT */
2874	2948	return 1;
2875	2949	}
2876	2950	return 0;
@@ -2879,9 +2953,14 @@ int has_snb_msrs(unsigned int family, unsigned int model) · 2 unmodified lines
2879	2953	/*
2880	2954	* HSW adds support for additional MSRs:
2881	2955	*
2882		− * MSR_PKG_C8_RESIDENCY 0x00000630
2883		− * MSR_PKG_C9_RESIDENCY 0x00000631
2884		− * MSR_PKG_C10_RESIDENCY 0x00000632
	2956	+ * MSR_PKG_C8_RESIDENCY 0x00000630
	2957	+ * MSR_PKG_C9_RESIDENCY 0x00000631
	2958	+ * MSR_PKG_C10_RESIDENCY 0x00000632
	2959	+ *
	2960	+ * MSR_PKGC8_IRTL 0x00000633
	2961	+ * MSR_PKGC9_IRTL 0x00000634
	2962	+ * MSR_PKGC10_IRTL 0x00000635
	2963	+ *
2885	2964	*/
2886	2965	int has_hsw_msrs(unsigned int family, unsigned int model)
2887	2966	{
@@ -2893,6 +2972,9 @@ int has_hsw_msrs(unsigned int family, unsigned int model) · 5 unmodified lines
2893	2972	case 0x3D: /* BDW */
2894	2973	case 0x4E: /* SKL */
2895	2974	case 0x5E: /* SKL */
	2975	+ case 0x8E: /* KBL */
	2976	+ case 0x9E: /* KBL */
	2977	+ case 0x5C: /* BXT */
2896	2978	return 1;
2897	2979	}
2898	2980	return 0;
@@ -2914,6 +2996,8 @@ int has_skl_msrs(unsigned int family, unsigned int model) · 15 unmodified lines
2914	2996	switch (model) {
2915	2997	case 0x4E: /* SKL */
2916	2998	case 0x5E: /* SKL */
	2999	+ case 0x8E: /* KBL */
	3000	+ case 0x9E: /* KBL */
2917	3001	return 1;
2918	3002	}
2919	3003	return 0;
@@ -3187,7 +3271,7 @@ void process_cpuid() · 267 unmodified lines
3187	3271	if (debug)
3188	3272	decode_misc_enable_msr();
3189	3273
3190		− if (max_level >= 0x7) {
	3274	+ if (max_level >= 0x7 && debug) {
3191	3275	int has_sgx;
3192	3276
3193	3277	ecx = 0;
@@ -3221,7 +3305,15 @@ void process_cpuid() · 27 unmodified lines
3221	3305	switch(model) {
3222	3306	case 0x4E: /* SKL */
3223	3307	case 0x5E: /* SKL */
3224		− crystal_hz = 24000000; /* 24 MHz */
	3308	+ case 0x8E: /* KBL */
	3309	+ case 0x9E: /* KBL */
	3310	+ crystal_hz = 24000000; /* 24.0 MHz */
	3311	+ break;
	3312	+ case 0x55: /* SKX */
	3313	+ crystal_hz = 25000000; /* 25.0 MHz */
	3314	+ break;
	3315	+ case 0x5C: /* BXT */
	3316	+ crystal_hz = 19200000; /* 19.2 MHz */
3225	3317	break;
3226	3318	default:
3227	3319	crystal_hz = 0;
@@ -3254,11 +3346,13 @@ void process_cpuid() · 26 unmodified lines
3254	3346
3255	3347	do_nhm_platform_info = do_nhm_cstates = do_smi = probe_nhm_msrs(family, model);
3256	3348	do_snb_cstates = has_snb_msrs(family, model);
	3349	+ do_irtl_snb = has_snb_msrs(family, model);
3257	3350	do_pc2 = do_snb_cstates && (pkg_cstate_limit >= PCL__2);
3258	3351	do_pc3 = (pkg_cstate_limit >= PCL__3);
3259	3352	do_pc6 = (pkg_cstate_limit >= PCL__6);
3260	3353	do_pc7 = do_snb_cstates && (pkg_cstate_limit >= PCL__7);
3261	3354	do_c8_c9_c10 = has_hsw_msrs(family, model);
	3355	+ do_irtl_hsw = has_hsw_msrs(family, model);
3262	3356	do_skl_residency = has_skl_msrs(family, model);
3263	3357	do_slm_cstates = is_slm(family, model);
3264	3358	do_knl_cstates = is_knl(family, model);
@@ -3564,6 +3658,9 @@ void turbostat_init() · 299 unmodified lines
3564	3658
3565	3659	if (debug)
3566	3660	for_all_cpus(print_thermal, ODD_COUNTERS);
	3661	+
	3662	+ if (debug && do_irtl_snb)
	3663	+ print_irtl();
3567	3664	}
3568	3665
3569	3666	int fork_it(char **argv)
@@ -3629,7 +3726,7 @@ int get_and_dump_counters(void) · 59 unmodified lines
3629	3726	}
3630	3727
3631	3728	void print_version() {
3632		− fprintf(outf, "turbostat version 4.11 27 Feb 2016"
	3729	+ fprintf(outf, "turbostat version 4.12 5 Apr 2016"
3633	3730	" - Len Brown <lenb@kernel.org>\n");
3634	3731	}
3635	3732