invalid/prime icahce operation takes effect both pipes cuconrrently, therefore CP_MES_IC_BASE_LO/HI and CP_MES_MDBASE_LO/HI both have to be set before prime icache. Otherwise MES hardware gets garbage data in above regsters and causes page fault [ 470.873200] amdgpu 0000:33:00.0: amdgpu: [gfxhub] page fault (src_id:0 ring:217 vmid:0 pasid:0, for process pid 0 thread pid 0) [ 470.873222] amdgpu 0000:33:00.0: amdgpu: in page starting at address 0x000092cb89b00000 from client 10 [ 470.873234] amdgpu 0000:33:00.0: amdgpu: GCVM_L2_PROTECTION_FAULT_STATUS:0x00000BB3 [ 470.873242] amdgpu 0000:33:00.0: amdgpu: Faulty UTCL2 client ID: CPC (0x5) [ 470.873247] amdgpu 0000:33:00.0: amdgpu: MORE_FAULTS: 0x1 [ 470.873251] amdgpu 0000:33:00.0: amdgpu: WALKER_ERROR: 0x1 [ 470.873256] amdgpu 0000:33:00.0: amdgpu: PERMISSION_FAULTS: 0xb [ 470.873260] amdgpu 0000:33:00.0: amdgpu: MAPPING_ERROR: 0x1 [ 470.873264] amdgpu 0000:33:00.0: amdgpu: RW: 0x0
Unified · Split
| @@ -541,7 +541,7 @@ static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) · 540 unmodified lines | |||
| 541 | 541 | ||
| 542 | /* This function is for backdoor MES firmware */ | 542 | /* This function is for backdoor MES firmware */ |
| 543 | static int mes_v11_0_load_microcode(struct amdgpu_device *adev, | 543 | static int mes_v11_0_load_microcode(struct amdgpu_device *adev, |
| 544 | enum admgpu_mes_pipe pipe) | 544 | enum admgpu_mes_pipe pipe, bool prime_icache) |
| 545 | { | 545 | { |
| 546 | int r; | 546 | int r; |
| 547 | uint32_t data; | 547 | uint32_t data; |
| @@ -593,16 +593,18 @@ static int mes_v11_0_load_microcode(struct amdgpu_device *adev, · 45 unmodified lines | |||
| 593 | /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ | 593 | /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ |
| 594 | WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF); | 594 | WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF); |
| 595 | 595 | ||
| 596 | /* invalidate ICACHE */ | 596 | if (prime_icache) { |
| 597 | data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); | 597 | /* invalidate ICACHE */ |
| 598 | data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); | 598 | data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); |
| 599 | data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); | 599 | data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); |
| 600 | WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); | 600 | data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); |
| 601 | 601 | WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); | |
| 602 | /* prime the ICACHE. */ | 602 | |
| 603 | data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); | 603 | /* prime the ICACHE. */ |
| 604 | data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); | 604 | data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); |
| 605 | WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); | 605 | data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); |
| 606 | WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); | ||
| 607 | } | ||
| 606 | 608 | ||
| 607 | soc21_grbm_select(adev, 0, 0, 0, 0); | 609 | soc21_grbm_select(adev, 0, 0, 0, 0); |
| 608 | mutex_unlock(&adev->srbm_mutex); | 610 | mutex_unlock(&adev->srbm_mutex); |
| @@ -1044,17 +1046,19 @@ static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) · 435 unmodified lines | |||
| 1044 | int r = 0; | 1046 | int r = 0; |
| 1045 | 1047 | ||
| 1046 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { | 1048 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { |
| 1047 | r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE); | 1049 | |
| 1050 | r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); | ||
| 1048 | if (r) { | 1051 | if (r) { |
| 1049 | DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); | 1052 | DRM_ERROR("failed to load MES fw, r=%d\n", r); |
| 1050 | return r; | 1053 | return r; |
| 1051 | } | 1054 | } |
| 1052 | 1055 | ||
| 1053 | r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE); | 1056 | r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); |
| 1054 | if (r) { | 1057 | if (r) { |
| 1055 | DRM_ERROR("failed to load MES fw, r=%d\n", r); | 1058 | DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); |
| 1056 | return r; | 1059 | return r; |
| 1057 | } | 1060 | } |
| 1061 | |||
| 1058 | } | 1062 | } |
| 1059 | 1063 | ||
| 1060 | mes_v11_0_enable(adev, true); | 1064 | mes_v11_0_enable(adev, true); |
| @@ -1086,7 +1090,7 @@ static int mes_v11_0_hw_init(void *handle) · 25 unmodified lines | |||
| 1086 | if (!adev->enable_mes_kiq) { | 1090 | if (!adev->enable_mes_kiq) { |
| 1087 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { | 1091 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { |
| 1088 | r = mes_v11_0_load_microcode(adev, | 1092 | r = mes_v11_0_load_microcode(adev, |
| 1089 | AMDGPU_MES_SCHED_PIPE); | 1093 | AMDGPU_MES_SCHED_PIPE, true); |
| 1090 | if (r) { | 1094 | if (r) { |
| 1091 | DRM_ERROR("failed to MES fw, r=%d\n", r); | 1095 | DRM_ERROR("failed to MES fw, r=%d\n", r); |
| 1092 | return r; | 1096 | return r; |