History

Merge tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.3 kernel cycle: Core changes: - Device links can optionally be added between a pin control producer and its consumers. This will affect how the system power management is handled: a pin controller will not suspend before all of its consumers have been suspended. This was necessary for the ST Microelectronics STMFX expander and need to be tested on other systems as well: it makes sense to make this default in the long run. Right now it is opt-in per driver. - Drive strength can be specified in microamps. With decreases in silicon technology, milliamps isn't granular enough, let's make it possible to select drive strengths in microamps. Right now the Meson (AMlogic) driver needs this. New drivers: - New subdriver for the Tegra 194 SoC. - New subdriver for the Qualcomm SDM845. - New subdriver for the Qualcomm SM8150. - New subdriver for the Freescale i.MX8MN (Freescale is now a product line of NXP). - New subdriver for Marvell MV98DX1135. Driver improvements: - The Bitmain BM1880 driver now supports pin config in addition to muxing. - The Qualcomm drivers can now reserve some GPIOs as taken aside and not usable for users. This is used in ACPI systems to take out some GPIO lines used by the BIOS so that noone else (neither kernel nor userspace) will play with them by mistake and crash the machine. - A slew of refurbishing around the Aspeed drivers (board management controllers for servers) in preparation for the new Aspeed AST2600 SoC. - A slew of improvements over the SH PFC drivers as usual. - Misc cleanups and fixes" * tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (106 commits) pinctrl: aspeed: Strip moved macros and structs from private header pinctrl: aspeed: Fix missed include pinctrl: baytrail: Use GENMASK() consistently pinctrl: baytrail: Re-use data structures from pinctrl-intel.h pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux() pinctrl: qcom: Add SM8150 pinctrl driver dt-bindings: pinctrl: qcom: Add SM8150 pinctrl binding dt-bindings: pinctrl: qcom: Document missing gpio nodes pinctrl: aspeed: Add implementation-related documentation pinctrl: aspeed: Split out pinmux from general pinctrl pinctrl: aspeed: Clarify comment about strapping W1C pinctrl: aspeed: Correct comment that is no longer true MAINTAINERS: Add entry for ASPEED pinctrl drivers dt-bindings: pinctrl: aspeed: Convert AST2500 bindings to json-schema dt-bindings: pinctrl: aspeed: Convert AST2400 bindings to json-schema dt-bindings: pinctrl: aspeed: Split bindings document in two pinctrl: qcom: Add irq_enable callback for msm gpio pinctrl: madera: Fixup SPDX headers pinctrl: qcom: sdm845: Fix CONFIG preprocessor guard pinctrl: tegra: Add bitmask support for parked bits ...

Linus Torvalds committed 7 years ago

Commit 43c95d32 parents 073c916 4c10576109 files · +7689 −3198Browse files

Unified · Split

109 files
  1. Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +2 −0
  2. Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml +81 −0
  3. Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml +134 −0
  4. Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt +31 −3
  5. Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt +3 −0
  6. Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt +1 −1
  7. Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.txt +39 −0
  8. Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt +42 −2
  9. Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt +13 −3
  10. Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt +1 −1
  11. Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt +107 −0
  12. Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt +0 −172
  13. Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +3 −0
  14. Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt +3 −3
  15. Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt +3 −3
  16. Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.txt +3 −3
  17. Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.txt +3 −3
  18. Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.txt +3 −3
  19. Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.txt +3 −3
  20. Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.txt +3 −3
  21. Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt +13 −3
  22. Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.txt +3 −3
  23. Documentation/devicetree/bindings/pinctrl/qcom,sdm660-pinctrl.txt +3 −3
  24. Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt +4 −4
  25. Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.txt +190 −0
  26. Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +0 −208
  27. Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml +264 −0
  28. MAINTAINERS +9 −0
  29. arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h +646 −0
  30. drivers/pinctrl/aspeed/Makefile +1 −1
  31. drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c +90 −4
  32. drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +121 −6
  33. drivers/pinctrl/aspeed/pinctrl-aspeed.c +37 −209
  34. drivers/pinctrl/aspeed/pinctrl-aspeed.h +9 −533
  35. drivers/pinctrl/aspeed/pinmux-aspeed.c +96 −0
  36. drivers/pinctrl/aspeed/pinmux-aspeed.h +735 −0
  37. drivers/pinctrl/bcm/Kconfig +5 −1
  38. drivers/pinctrl/bcm/pinctrl-ns2-mux.c +2 −0
  39. drivers/pinctrl/cirrus/pinctrl-cs47l35.c +1 −5
  40. drivers/pinctrl/cirrus/pinctrl-cs47l85.c +1 −5
  41. drivers/pinctrl/cirrus/pinctrl-cs47l90.c +1 −5
  42. drivers/pinctrl/cirrus/pinctrl-madera-core.c +1 −5
  43. drivers/pinctrl/cirrus/pinctrl-madera.h +1 −5
  44. drivers/pinctrl/core.c +17 −27
  45. drivers/pinctrl/freescale/Kconfig +7 −0
  46. drivers/pinctrl/freescale/Makefile +1 −0
  47. drivers/pinctrl/freescale/pinctrl-imx8mn.c +348 −0
  48. drivers/pinctrl/intel/pinctrl-baytrail.c +71 −251
  49. drivers/pinctrl/mediatek/pinctrl-mt8183.c +1 −0
  50. drivers/pinctrl/mediatek/pinctrl-paris.c +19 −0
  51. drivers/pinctrl/mediatek/pinctrl-paris.h +2 −0
  52. drivers/pinctrl/meson/pinctrl-meson-g12a.c +18 −18
  53. drivers/pinctrl/meson/pinctrl-meson.c +267 −83
  54. drivers/pinctrl/meson/pinctrl-meson.h +17 −1
  55. drivers/pinctrl/mvebu/pinctrl-kirkwood.c +297 −279
  56. drivers/pinctrl/pinconf-generic.c +2 −0
  57. drivers/pinctrl/pinctrl-bm1880.c +563 −170
  58. drivers/pinctrl/pinctrl-rockchip.c +1 −0
  59. drivers/pinctrl/pinctrl-stmfx.c +1 −0
  60. drivers/pinctrl/pinctrl-tb10x.c +5 −7
  61. drivers/pinctrl/qcom/Kconfig +10 −1
  62. drivers/pinctrl/qcom/Makefile +1 −0
  63. drivers/pinctrl/qcom/pinctrl-msm.c +42 −1
  64. drivers/pinctrl/qcom/pinctrl-msm.h +1 −0
  65. drivers/pinctrl/qcom/pinctrl-sdm845.c +40 −6
  66. drivers/pinctrl/qcom/pinctrl-sm8150.c +1548 −0
  67. drivers/pinctrl/sh-pfc/core.c +50 −10
  68. drivers/pinctrl/sh-pfc/pfc-emev2.c +34 −36
  69. drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +1 −1
  70. drivers/pinctrl/sh-pfc/pfc-r8a7740.c +1 −1
  71. drivers/pinctrl/sh-pfc/pfc-r8a77470.c +1 −1
  72. drivers/pinctrl/sh-pfc/pfc-r8a7778.c +55 −70
  73. drivers/pinctrl/sh-pfc/pfc-r8a7779.c +1 −1
  74. drivers/pinctrl/sh-pfc/pfc-r8a7790.c +20 −16
  75. drivers/pinctrl/sh-pfc/pfc-r8a7791.c +1 −1
  76. drivers/pinctrl/sh-pfc/pfc-r8a7792.c +1 −1
  77. drivers/pinctrl/sh-pfc/pfc-r8a7794.c +1 −1
  78. drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c +233 −201
  79. drivers/pinctrl/sh-pfc/pfc-r8a7795.c +224 −190
  80. drivers/pinctrl/sh-pfc/pfc-r8a7796.c +224 −190
  81. drivers/pinctrl/sh-pfc/pfc-r8a77965.c +222 −188
  82. drivers/pinctrl/sh-pfc/pfc-r8a77970.c +3 −23
  83. drivers/pinctrl/sh-pfc/pfc-r8a77980.c +1 −1
  84. drivers/pinctrl/sh-pfc/pfc-r8a77990.c +87 −94
  85. drivers/pinctrl/sh-pfc/pfc-r8a77995.c +1 −1
  86. drivers/pinctrl/sh-pfc/pfc-sh73a0.c +13 −8
  87. drivers/pinctrl/sh-pfc/pfc-sh7734.c +1 −1
  88. drivers/pinctrl/sh-pfc/pinctrl.c +1 −2
  89. drivers/pinctrl/sh-pfc/sh_pfc.h +69 −21
  90. drivers/pinctrl/stm32/pinctrl-stm32.c +183 −1
  91. drivers/pinctrl/stm32/pinctrl-stm32.h +2 −0
  92. drivers/pinctrl/stm32/pinctrl-stm32mp157.c +5 −0
  93. drivers/pinctrl/tegra/Kconfig +4 −0
  94. drivers/pinctrl/tegra/Makefile +1 −0
  95. drivers/pinctrl/tegra/pinctrl-tegra.c +18 −8
  96. drivers/pinctrl/tegra/pinctrl-tegra.h +6 −6
  97. drivers/pinctrl/tegra/pinctrl-tegra114.c +3 −3
  98. drivers/pinctrl/tegra/pinctrl-tegra124.c +3 −3
  99. drivers/pinctrl/tegra/pinctrl-tegra194.c +170 −0
  100. drivers/pinctrl/tegra/pinctrl-tegra20.c +3 −3
  101. drivers/pinctrl/tegra/pinctrl-tegra210.c +31 −31
  102. drivers/pinctrl/tegra/pinctrl-tegra30.c +2 −2
  103. include/linux/gpio.h +1 −0
  104. include/linux/gpio/driver.h +2 −0
  105. include/linux/pinctrl/pinconf-generic.h +9 −14
  106. include/linux/pinctrl/pinconf.h +1 −3
  107. include/linux/pinctrl/pinctrl-state.h +5 −0
  108. include/linux/pinctrl/pinctrl.h +5 −14
  109. include/linux/pinctrl/pinmux.h +0 −4
Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt+2−0
@@ -24,6 +24,8 @@ Required properties: · 23 unmodified lines
2424 "allwinner,sun8i-h3-pinctrl"
2525 "allwinner,sun8i-h3-r-pinctrl"
2626 "allwinner,sun8i-r40-pinctrl"
27+ "allwinner,sun8i-v3-pinctrl"
28+ "allwinner,sun8i-v3s-pinctrl"
2729 "allwinner,sun50i-a64-pinctrl"
2830 "allwinner,sun50i-a64-r-pinctrl"
2931 "allwinner,sun50i-h5-pinctrl"
Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml+81−0
@@ -0,0 +1,81 @@
1+# SPDX-License-Identifier: GPL-2.0-or-later
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2400-pinctrl.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: ASPEED AST2400 Pin Controller
8+
9+maintainers:
10+ - Andrew Jeffery <andrew@aj.id.au>
11+
12+description: |+
13+ The pin controller node should be the child of a syscon node with the
14+ required property:
15+
16+ - compatible: Should be one of the following:
17+ "aspeed,ast2400-scu", "syscon", "simple-mfd"
18+ "aspeed,g4-scu", "syscon", "simple-mfd"
19+
20+ Refer to the the bindings described in
21+ Documentation/devicetree/bindings/mfd/syscon.txt
22+
23+properties:
24+ compatible:
25+ enum: [ aspeed,ast2400-pinctrl, aspeed,g4-pinctrl ]
26+
27+patternProperties:
28+ '^.*$':
29+ if:
30+ type: object
31+ then:
32+ patternProperties:
33+ "^function|groups$":
34+ allOf:
35+ - $ref: "/schemas/types.yaml#/definitions/string"
36+ - enum: [ "ACPI", "ADC0", "ADC1", "ADC10", "ADC11", "ADC12", "ADC13",
37+ "ADC14", "ADC15", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6", "ADC7",
38+ "ADC8", "ADC9", "BMCINT", "DDCCLK", "DDCDAT", "EXTRST", "FLACK",
39+ "FLBUSY", "FLWP", "GPID", "GPID0", "GPID2", "GPID4", "GPID6",
40+ "GPIE0", "GPIE2", "GPIE4", "GPIE6", "I2C10", "I2C11", "I2C12",
41+ "I2C13", "I2C14", "I2C3", "I2C4", "I2C5", "I2C6", "I2C7", "I2C8",
42+ "I2C9", "LPCPD", "LPCPME", "LPCRST", "LPCSMI", "MAC1LINK",
43+ "MAC2LINK", "MDIO1", "MDIO2", "NCTS1", "NCTS2", "NCTS3", "NCTS4",
44+ "NDCD1", "NDCD2", "NDCD3", "NDCD4", "NDSR1", "NDSR2", "NDSR3",
45+ "NDSR4", "NDTR1", "NDTR2", "NDTR3", "NDTR4", "NDTS4", "NRI1",
46+ "NRI2", "NRI3", "NRI4", "NRTS1", "NRTS2", "NRTS3", "OSCCLK",
47+ "PWM0", "PWM1", "PWM2", "PWM3", "PWM4", "PWM5", "PWM6", "PWM7",
48+ "RGMII1", "RGMII2", "RMII1", "RMII2", "ROM16", "ROM8", "ROMCS1",
49+ "ROMCS2", "ROMCS3", "ROMCS4", "RXD1", "RXD2", "RXD3", "RXD4",
50+ "SALT1", "SALT2", "SALT3", "SALT4", "SD1", "SD2", "SGPMCK",
51+ "SGPMI", "SGPMLD", "SGPMO", "SGPSCK", "SGPSI0", "SGPSI1", "SGPSLD",
52+ "SIOONCTRL", "SIOPBI", "SIOPBO", "SIOPWREQ", "SIOPWRGD", "SIOS3",
53+ "SIOS5", "SIOSCI", "SPI1", "SPI1DEBUG", "SPI1PASSTHRU", "SPICS1",
54+ "TIMER3", "TIMER4", "TIMER5", "TIMER6", "TIMER7", "TIMER8", "TXD1",
55+ "TXD2", "TXD3", "TXD4", "UART6", "USB11D1", "USB11H2", "USB2D1",
56+ "USB2H1", "USBCKI", "VGABIOS_ROM", "VGAHS", "VGAVS", "VPI18",
57+ "VPI24", "VPI30", "VPO12", "VPO24", "WDTRST1", "WDTRST2" ]
58+
59+required:
60+ - compatible
61+
62+examples:
63+ - |
64+ syscon: scu@1e6e2000 {
65+ compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
66+ reg = <0x1e6e2000 0x1a8>;
67+
68+ pinctrl: pinctrl {
69+ compatible = "aspeed,g4-pinctrl";
70+
71+ pinctrl_i2c3_default: i2c3_default {
72+ function = "I2C3";
73+ groups = "I2C3";
74+ };
75+
76+ pinctrl_gpioh0_unbiased_default: gpioh0 {
77+ pins = "A8";
78+ bias-disable;
79+ };
80+ };
81+ };
Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml+134−0
@@ -0,0 +1,134 @@
1+# SPDX-License-Identifier: GPL-2.0-or-later
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2500-pinctrl.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: ASPEED AST2500 Pin Controller
8+
9+maintainers:
10+ - Andrew Jeffery <andrew@aj.id.au>
11+
12+description: |+
13+ The pin controller node should be the child of a syscon node with the
14+ required property:
15+
16+ - compatible: Should be one of the following:
17+ "aspeed,ast2500-scu", "syscon", "simple-mfd"
18+ "aspeed,g5-scu", "syscon", "simple-mfd"
19+
20+ Refer to the the bindings described in
21+ Documentation/devicetree/bindings/mfd/syscon.txt
22+
23+properties:
24+ compatible:
25+ enum: [ aspeed,ast2500-pinctrl, aspeed,g5-pinctrl ]
26+ aspeed,external-nodes:
27+ minItems: 2
28+ maxItems: 2
29+ allOf:
30+ - $ref: /schemas/types.yaml#/definitions/phandle-array
31+ description: |
32+ A cell of phandles to external controller nodes:
33+ 0: compatible with "aspeed,ast2500-gfx", "syscon"
34+ 1: compatible with "aspeed,ast2500-lhc", "syscon"
35+
36+patternProperties:
37+ '^.*$':
38+ if:
39+ type: object
40+ then:
41+ patternProperties:
42+ "^function|groups$":
43+ allOf:
44+ - $ref: "/schemas/types.yaml#/definitions/string"
45+ - enum: [ "ACPI", "ADC0", "ADC1", "ADC10", "ADC11", "ADC12", "ADC13",
46+ "ADC14", "ADC15", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6", "ADC7",
47+ "ADC8", "ADC9", "BMCINT", "DDCCLK", "DDCDAT", "ESPI", "FWSPICS1",
48+ "FWSPICS2", "GPID0", "GPID2", "GPID4", "GPID6", "GPIE0", "GPIE2",
49+ "GPIE4", "GPIE6", "I2C10", "I2C11", "I2C12", "I2C13", "I2C14",
50+ "I2C3", "I2C4", "I2C5", "I2C6", "I2C7", "I2C8", "I2C9", "LAD0",
51+ "LAD1", "LAD2", "LAD3", "LCLK", "LFRAME", "LPCHC", "LPCPD",
52+ "LPCPLUS", "LPCPME", "LPCRST", "LPCSMI", "LSIRQ", "MAC1LINK",
53+ "MAC2LINK", "MDIO1", "MDIO2", "NCTS1", "NCTS2", "NCTS3", "NCTS4",
54+ "NDCD1", "NDCD2", "NDCD3", "NDCD4", "NDSR1", "NDSR2", "NDSR3",
55+ "NDSR4", "NDTR1", "NDTR2", "NDTR3", "NDTR4", "NRI1", "NRI2",
56+ "NRI3", "NRI4", "NRTS1", "NRTS2", "NRTS3", "NRTS4", "OSCCLK",
57+ "PEWAKE", "PNOR", "PWM0", "PWM1", "PWM2", "PWM3", "PWM4", "PWM5",
58+ "PWM6", "PWM7", "RGMII1", "RGMII2", "RMII1", "RMII2", "RXD1",
59+ "RXD2", "RXD3", "RXD4", "SALT1", "SALT10", "SALT11", "SALT12",
60+ "SALT13", "SALT14", "SALT2", "SALT3", "SALT4", "SALT5", "SALT6",
61+ "SALT7", "SALT8", "SALT9", "SCL1", "SCL2", "SD1", "SD2", "SDA1",
62+ "SDA2", "SGPS1", "SGPS2", "SIOONCTRL", "SIOPBI", "SIOPBO",
63+ "SIOPWREQ", "SIOPWRGD", "SIOS3", "SIOS5", "SIOSCI", "SPI1",
64+ "SPI1CS1", "SPI1DEBUG", "SPI1PASSTHRU", "SPI2CK", "SPI2CS0",
65+ "SPI2CS1", "SPI2MISO", "SPI2MOSI", "TIMER3", "TIMER4", "TIMER5",
66+ "TIMER6", "TIMER7", "TIMER8", "TXD1", "TXD2", "TXD3", "TXD4",
67+ "UART6", "USB11BHID", "USB2AD", "USB2AH", "USB2BD", "USB2BH",
68+ "USBCKI", "VGABIOSROM", "VGAHS", "VGAVS", "VPI24", "VPO",
69+ "WDTRST1", "WDTRST2", ]
70+
71+required:
72+ - compatible
73+ - aspeed,external-nodes
74+
75+examples:
76+ - |
77+ compatible = "simple-bus";
78+ ranges;
79+
80+ apb {
81+ compatible = "simple-bus";
82+ #address-cells = <1>;
83+ #size-cells = <1>;
84+ ranges;
85+
86+ syscon: scu@1e6e2000 {
87+ compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
88+ reg = <0x1e6e2000 0x1a8>;
89+
90+ pinctrl: pinctrl {
91+ compatible = "aspeed,g5-pinctrl";
92+ aspeed,external-nodes = <&gfx &lhc>;
93+
94+ pinctrl_i2c3_default: i2c3_default {
95+ function = "I2C3";
96+ groups = "I2C3";
97+ };
98+
99+ pinctrl_gpioh0_unbiased_default: gpioh0 {
100+ pins = "A18";
101+ bias-disable;
102+ };
103+ };
104+ };
105+
106+ gfx: display@1e6e6000 {
107+ compatible = "aspeed,ast2500-gfx", "syscon";
108+ reg = <0x1e6e6000 0x1000>;
109+ };
110+ };
111+
112+ lpc: lpc@1e789000 {
113+ compatible = "aspeed,ast2500-lpc", "simple-mfd";
114+ reg = <0x1e789000 0x1000>;
115+
116+ #address-cells = <1>;
117+ #size-cells = <1>;
118+ ranges = <0x0 0x1e789000 0x1000>;
119+
120+ lpc_host: lpc-host@80 {
121+ compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
122+ reg = <0x80 0x1e0>;
123+ reg-io-width = <4>;
124+
125+ #address-cells = <1>;
126+ #size-cells = <1>;
127+ ranges = <0x0 0x80 0x1e0>;
128+
129+ lhc: lhc@20 {
130+ compatible = "aspeed,ast2500-lhc";
131+ reg = <0x20 0x24 0x48 0x8>;
132+ };
133+ };
134+ };
Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt+31−3
@@ -14,7 +14,8 @@ phrase "pin configuration node". · 13 unmodified lines
1414 The pin configuration nodes act as a container for an arbitrary number of
1515 subnodes. Each of these subnodes represents some desired configuration for a
1616 pin, a group, or a list of pins or groups. This configuration for BM1880 SoC
17−includes only pinmux as there is no pinconf support available in SoC.
17+includes pinmux and various pin configuration parameters, such as pull-up,
18+slew rate etc...
1819
1920 Each configuration node can consist of multiple nodes describing the pinmux
2021 options. The name of each subnode is not important; all subnodes should be
@@ -84,10 +85,37 @@ Required Properties: · 63 unmodified lines
8485 gpio66, gpio67, eth1, i2s0, i2s0_mclkin, i2s1, i2s1_mclkin,
8586 spi0
8687
88+Optional Properties:
89+
90+- bias-disable: No arguments. Disable pin bias.
91+- bias-pull-down: No arguments. The specified pins should be configured as
92+ pull down.
93+- bias-pull-up: No arguments. The specified pins should be configured as
94+ pull up.
95+- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified
96+ pins
97+- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified
98+ pins
99+- slew-rate: Integer. Sets slew rate for the specified pins.
100+ Valid values are:
101+ <0> - Slow
102+ <1> - Fast
103+- drive-strength: Integer. Selects the drive strength for the specified
104+ pins in mA.
105+ Valid values are:
106+ <4>
107+ <8>
108+ <12>
109+ <16>
110+ <20>
111+ <24>
112+ <28>
113+ <32>
114+
87115 Example:
88− pinctrl: pinctrl@50 {
116+ pinctrl: pinctrl@400 {
89117 compatible = "bitmain,bm1880-pinctrl";
90− reg = <0x50 0x4B0>;
118+ reg = <0x400 0x120>;
91119
92120 pinctrl_uart0_default: uart0-default {
93121 pinmux {
Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt+3−0
@@ -5,6 +5,9 @@ controller, and pinmux/control device. · 4 unmodified lines
55
66 Required properties:
77 - compatible: "brcm,bcm2835-gpio"
8+- compatible: should be one of:
9+ "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10+ "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
811 - reg: Should contain the physical address of the GPIO module's registers.
912 - gpio-controller: Marks the device node as a GPIO controller.
1013 - #gpio-cells : Should be two. The first cell is the pin number and the
Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt+1−1
@@ -12,7 +12,7 @@ Required properties in sub-nodes: · 11 unmodified lines
1212 - fsl,pins: each entry consists of 6 integers and represents the mux and config
1313 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
1414 input_val> are specified using a PIN_FUNC_ID macro, which can be found in
15− <dt-bindings/pinctrl/imx8mm-pinfunc.h>. The last integer CONFIG is
15+ <arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h>. The last integer CONFIG is
1616 the pad setting value like pull-up on this pin. Please refer to i.MX8M Mini
1717 Reference Manual for detailed CONFIG settings.
1818
Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.txt+39−0
@@ -0,0 +1,39 @@
1+* Freescale IMX8MN IOMUX Controller
2+
3+Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
4+for common binding part and usage.
5+
6+Required properties:
7+- compatible: "fsl,imx8mn-iomuxc"
8+- reg: should contain the base physical address and size of the iomuxc
9+ registers.
10+
11+Required properties in sub-nodes:
12+- fsl,pins: each entry consists of 6 integers and represents the mux and config
13+ setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
14+ input_val> are specified using a PIN_FUNC_ID macro, which can be found in
15+ <arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h>. The last integer CONFIG is
16+ the pad setting value like pull-up on this pin. Please refer to i.MX8M Nano
17+ Reference Manual for detailed CONFIG settings.
18+
19+Examples:
20+
21+&uart1 {
22+ pinctrl-names = "default";
23+ pinctrl-0 = <&pinctrl_uart1>;
24+};
25+
26+iomuxc: pinctrl@30330000 {
27+ compatible = "fsl,imx8mn-iomuxc";
28+ reg = <0x0 0x30330000 0x0 0x10000>;
29+
30+ pinctrl_uart1: uart1grp {
31+ fsl,pins = <
32+ MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
33+ MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
34+ MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
35+ MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
36+ MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19
37+ >;
38+ };
39+};
Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt+42−2
@@ -6,8 +6,8 @@ part and usage. · 5 unmodified lines
66 Required properties:
77 - compatible: "marvell,88f6180-pinctrl",
88 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9− "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
10− "marvell,98dx4122-pinctrl"
9+ "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10+ "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
1111 - reg: register specifier of MPP registers
1212
1313 This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
@@ -317,3 +317,43 @@ mpp44 44 gpio · 303 unmodified lines
317317 mpp45 45 gpio
318318 mpp49 49 gpio
319319
320+* Marvell Poncat2 98dx1135
321+
322+name pins functions
323+================================================================================
324+
325+mpp0 0 gpio, nand(io2), spi(cs)
326+mpp1 1 gpo, nand(io3), spi(mosi)
327+mpp2 2 gpo, nand(io4), spi(sck)
328+mpp3 3 gpo, nand(io5), spi(miso)
329+mpp4 4 gpio, nand(io6), uart0(rxd)
330+mpp5 5 gpo, nand(io7), uart0(txd)
331+mpp6 6 sysrst(out)
332+mpp7 7 gpo, spi(cs)
333+mpp8 8 gpio, twsi0(sda), uart1(rts)
334+mpp9 9 gpio, twsi(sck), uart1(cts)
335+mpp10 10 gpo, uart0(txd)
336+mpp11 11 gpio, uart0(rxd)
337+mpp13 13 gpio, uart1(txd)
338+mpp14 14 gpio, uart1(rxd)
339+mpp15 15 gpio, uart0(rts)
340+mpp16 16 gpio, uart0(cts)
341+mpp17 17 gpio, nand(cle)
342+mpp18 18 gpo, nand(io0)
343+mpp19 19 gpo, nand(io1)
344+mpp20 20 gpio
345+mpp21 21 gpio
346+mpp22 22 gpio
347+mpp23 23 gpio
348+mpp24 24 gpio
349+mpp25 25 gpio
350+mpp26 26 gpio
351+mpp27 27 gpio
352+mpp28 28 gpio, nand(ren)
353+mpp29 29 gpio, nand(wen)
354+mpp30 30 gpio
355+mpp31 31 gpio
356+mpp32 32 gpio
357+mpp33 33 gpio
358+mpp34 34 gpio, nand(ale)
359+mpp35 35 gpio, nand(cen)
Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt+13−3
@@ -47,9 +47,19 @@ Required properties for pinmux nodes are: · 46 unmodified lines
4747 Required properties for configuration nodes:
4848 - pins: a list of pin names
4949
50−Configuration nodes support the generic properties "bias-disable",
51−"bias-pull-up" and "bias-pull-down", described in file
52−pinctrl-bindings.txt
50+Configuration nodes support the following generic properties, as
51+described in file pinctrl-bindings.txt:
52+ - "bias-disable"
53+ - "bias-pull-up"
54+ - "bias-pull-down"
55+ - "output-enable"
56+ - "output-disable"
57+ - "output-low"
58+ - "output-high"
59+
60+Optional properties :
61+ - drive-strength-microamp: Drive strength for the specified pins in uA.
62+ This property is only valid for G12A and newer.
5363
5464 === Example ===
5565
Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt+1−1
@@ -5,7 +5,7 @@ Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and · 4 unmodified lines
55 pin controller, GPIO, and interrupt bindings.
66
77 PIC32 'pin configuration node' is a node of a group of pins which can be
8−used for a specific device or function. This node represents configuraions of
8+used for a specific device or function. This node represents configurations of
99 pins, optional function, and optional mux related configuration.
1010
1111 Required properties for pin controller node:
Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt+107−0
@@ -0,0 +1,107 @@
1+NVIDIA Tegra194 pinmux controller
2+
3+Required properties:
4+- compatible: "nvidia,tegra194-pinmux"
5+- reg: Should contain a list of base address and size pairs for:
6+ - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control)
7+ - second entry: The PINMUX_AUX_* registers (pinmux)
8+
9+Please refer to pinctrl-bindings.txt in this directory for details of the
10+common pinctrl bindings used by client devices, including the meaning of the
11+phrase "pin configuration node".
12+
13+Tegra's pin configuration nodes act as a container for an arbitrary number of
14+subnodes. Each of these subnodes represents some desired configuration for a
15+pin, a group, or a list of pins or groups. This configuration can include the
16+mux function to select on those pin(s)/group(s), and various pin configuration
17+parameters, such as pull-up, tristate, drive strength, etc.
18+
19+See the TRM to determine which properties and values apply to each pin/group.
20+Macro values for property values are defined in
21+include/dt-binding/pinctrl/pinctrl-tegra.h.
22+
23+Required subnode-properties:
24+- nvidia,pins : An array of strings. Each string contains the name of a pin or
25+ group. Valid values for these names are listed below.
26+
27+Optional subnode-properties:
28+- nvidia,function: A string containing the name of the function to mux to the
29+ pin or group.
30+- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
31+ 0: none, 1: down, 2: up.
32+- nvidia,tristate: Integer.
33+ 0: drive, 1: tristate.
34+- nvidia,enable-input: Integer. Enable the pin's input path.
35+ enable :TEGRA_PIN_ENABLE and
36+ disable or output only: TEGRA_PIN_DISABLE.
37+- nvidia,open-drain: Integer.
38+ enable: TEGRA_PIN_ENABLE.
39+ disable: TEGRA_PIN_DISABLE.
40+- nvidia,lock: Integer. Lock the pin configuration against further changes
41+ until reset.
42+ enable: TEGRA_PIN_ENABLE.
43+ disable: TEGRA_PIN_DISABLE.
44+- nvidia,io-hv: Integer. Select high-voltage receivers.
45+ normal: TEGRA_PIN_DISABLE
46+ high: TEGRA_PIN_ENABLE
47+- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
48+ normal: TEGRA_PIN_DISABLE
49+ high: TEGRA_PIN_ENABLE
50+- nvidia,drive-type: Integer. Valid range 0...3.
51+- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
52+ The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
53+ Tegra TRM.
54+- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
55+ The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
56+ Tegra TRM.
57+
58+Valid values for pin and group names (nvidia,pin) are:
59+
60+ These correspond to Tegra PADCTL_* (pinmux) registers.
61+
62+ Mux groups:
63+
64+ These correspond to Tegra PADCTL_* (pinmux) registers. Any property
65+ that exists in those registers may be set for the following pin names.
66+
67+ pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1
68+
69+ Drive groups:
70+
71+ These registers controls a single pin for which a mux group exists.
72+ See the list above for the pin name to use when configuring the pinmux.
73+
74+ pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1
75+
76+Valid values for nvidia,functions are:
77+
78+ pe5
79+
80+Power Domain:
81+ pex_l5_clkreq_n_pgg0 and pex_l5_rst_n_pgg1 are part of PCIE C5 power
82+ partition. Client devices must enable this partition before accessing
83+ these pins here.
84+
85+
86+Example:
87+
88+ tegra_pinctrl: pinmux: pinmux@2430000 {
89+ compatible = "nvidia,tegra194-pinmux";
90+ reg = <0x2430000 0x17000
91+ 0xc300000 0x4000>;
92+
93+ pinctrl-names = "pex_rst";
94+ pinctrl-0 = <&pex_rst_c5_out_state>;
95+
96+ pex_rst_c5_out_state: pex_rst_c5_out {
97+ pex_rst {
98+ nvidia,pins = "pex_l5_rst_n_pgg1";
99+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
100+ nvidia,lpdr = <TEGRA_PIN_ENABLE>;
101+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
102+ nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
103+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
104+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
105+ };
106+ };
107+ };
Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt+0−172
@@ -1,172 +0,0 @@
1−======================
2−Aspeed Pin Controllers
3−======================
4−
5−The Aspeed SoCs vary in functionality inside a generation but have a common mux
6−device register layout.
7−
8−Required properties for g4:
9−- compatible : Should be one of the following:
10− "aspeed,ast2400-pinctrl"
11− "aspeed,g4-pinctrl"
12−
13−Required properties for g5:
14−- compatible : Should be one of the following:
15− "aspeed,ast2500-pinctrl"
16− "aspeed,g5-pinctrl"
17−
18−- aspeed,external-nodes: A cell of phandles to external controller nodes:
19− 0: compatible with "aspeed,ast2500-gfx", "syscon"
20− 1: compatible with "aspeed,ast2500-lhc", "syscon"
21−
22−The pin controller node should be the child of a syscon node with the required
23−property:
24−
25−- compatible : Should be one of the following:
26− "aspeed,ast2400-scu", "syscon", "simple-mfd"
27− "aspeed,g4-scu", "syscon", "simple-mfd"
28− "aspeed,ast2500-scu", "syscon", "simple-mfd"
29− "aspeed,g5-scu", "syscon", "simple-mfd"
30−
31−Refer to the the bindings described in
32−Documentation/devicetree/bindings/mfd/syscon.txt
33−
34−Subnode Format
35−==============
36−
37−The required properties of pinmux child nodes are:
38−- function: the mux function to select
39−- groups : the list of groups to select with this function
40−
41−Required properties of pinconf child nodes are:
42−- groups: A list of groups to select (either this or "pins" must be
43− specified)
44−- pins : A list of ball names as strings, eg "D14" (either this or "groups"
45− must be specified)
46−
47−Optional properties of pinconf child nodes are:
48−- bias-disable : disable any pin bias
49−- bias-pull-down: pull down the pin
50−- drive-strength: sink or source at most X mA
51−
52−Definitions are as specified in
53−Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt, with any
54−further limitations as described above.
55−
56−For pinmux, each mux function has only one associated pin group. Each group is
57−named by its function. The following values for the function and groups
58−properties are supported:
59−
60−aspeed,ast2400-pinctrl, aspeed,g4-pinctrl:
61−
62−ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6
63−ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT EXTRST FLACK FLBUSY FLWP GPID GPID0 GPID2
64−GPID4 GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4
65−I2C5 I2C6 I2C7 I2C8 I2C9 LPCPD LPCPME LPCRST LPCSMI MAC1LINK MAC2LINK MDIO1
66−MDIO2 NCTS1 NCTS2 NCTS3 NCTS4 NDCD1 NDCD2 NDCD3 NDCD4 NDSR1 NDSR2 NDSR3 NDSR4
67−NDTR1 NDTR2 NDTR3 NDTR4 NDTS4 NRI1 NRI2 NRI3 NRI4 NRTS1 NRTS2 NRTS3 OSCCLK PWM0
68−PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1
69−ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK
70−SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ
71−SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4
72−TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USB11D1 USB11H2 USB2D1
73−USB2H1 USBCKI VGABIOS_ROM VGAHS VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1
74−WDTRST2
75−
76−aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
77−
78−ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6
79−ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT ESPI FWSPICS1 FWSPICS2 GPID0 GPID2 GPID4
80−GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6
81−I2C7 I2C8 I2C9 LAD0 LAD1 LAD2 LAD3 LCLK LFRAME LPCHC LPCPD LPCPLUS LPCPME
82−LPCRST LPCSMI LSIRQ MAC1LINK MAC2LINK MDIO1 MDIO2 NCTS1 NCTS2 NCTS3 NCTS4 NDCD1
83−NDCD2 NDCD3 NDCD4 NDSR1 NDSR2 NDSR3 NDSR4 NDTR1 NDTR2 NDTR3 NDTR4 NRI1 NRI2
84−NRI3 NRI4 NRTS1 NRTS2 NRTS3 NRTS4 OSCCLK PEWAKE PNOR PWM0 PWM1 PWM2 PWM3 PWM4
85−PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 RXD1 RXD2 RXD3 RXD4 SALT1 SALT10
86−SALT11 SALT12 SALT13 SALT14 SALT2 SALT3 SALT4 SALT5 SALT6 SALT7 SALT8 SALT9
87−SCL1 SCL2 SD1 SD2 SDA1 SDA2 SGPS1 SGPS2 SIOONCTRL SIOPBI SIOPBO SIOPWREQ
88−SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1CS1 SPI1DEBUG SPI1PASSTHRU SPI2CK SPI2CS0
89−SPI2CS1 SPI2MISO SPI2MOSI TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2
90−TXD3 TXD4 UART6 USB11BHID USB2AD USB2AH USB2BD USB2BH USBCKI VGABIOSROM VGAHS
91−VGAVS VPI24 VPO WDTRST1 WDTRST2
92−
93−Examples
94−========
95−
96−g4 Example
97−----------
98−
99−syscon: scu@1e6e2000 {
100− compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
101− reg = <0x1e6e2000 0x1a8>;
102−
103− pinctrl: pinctrl {
104− compatible = "aspeed,g4-pinctrl";
105−
106− pinctrl_i2c3_default: i2c3_default {
107− function = "I2C3";
108− groups = "I2C3";
109− };
110−
111− pinctrl_gpioh0_unbiased_default: gpioh0 {
112− pins = "A8";
113− bias-disable;
114− };
115− };
116−};
117−
118−g5 Example
119−----------
120−
121−ahb {
122− apb {
123− syscon: scu@1e6e2000 {
124− compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
125− reg = <0x1e6e2000 0x1a8>;
126−
127− pinctrl: pinctrl {
128− compatible = "aspeed,g5-pinctrl";
129− aspeed,external-nodes = <&gfx &lhc>;
130−
131− pinctrl_i2c3_default: i2c3_default {
132− function = "I2C3";
133− groups = "I2C3";
134− };
135−
136− pinctrl_gpioh0_unbiased_default: gpioh0 {
137− pins = "A18";
138− bias-disable;
139− };
140− };
141− };
142−
143− gfx: display@1e6e6000 {
144− compatible = "aspeed,ast2500-gfx", "syscon";
145− reg = <0x1e6e6000 0x1000>;
146− };
147− };
148−
149− lpc: lpc@1e789000 {
150− compatible = "aspeed,ast2500-lpc", "simple-mfd";
151− reg = <0x1e789000 0x1000>;
152−
153− #address-cells = <1>;
154− #size-cells = <1>;
155− ranges = <0x0 0x1e789000 0x1000>;
156−
157− lpc_host: lpc-host@80 {
158− compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
159− reg = <0x80 0x1e0>;
160− reg-io-width = <4>;
161−
162− #address-cells = <1>;
163− #size-cells = <1>;
164− ranges = <0x0 0x80 0x1e0>;
165−
166− lhc: lhc@20 {
167− compatible = "aspeed,ast2500-lhc";
168− reg = <0x20 0x24 0x48 0x8>;
169− };
170− };
171− };
172−};
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt+3−0
@@ -258,6 +258,7 @@ drive-push-pull - drive actively high and low · 257 unmodified lines
258258 drive-open-drain - drive with open drain
259259 drive-open-source - drive with open source
260260 drive-strength - sink or source at most X mA
261+drive-strength-microamp - sink or source at most X uA
261262 input-enable - enable input on pin (no effect on output, such as
262263 enabling an input buffer)
263264 input-disable - disable input on pin (no effect on output, such as
@@ -326,6 +327,8 @@ arguments are described below. · 62 unmodified lines
326327
327328 - drive-strength takes as argument the target strength in mA.
328329
330+- drive-strength-microamp takes as argument the target strength in uA.
331+
329332 - input-debounce takes the debounce time in usec as argument
330333 or 0 to disable debouncing
331334
Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt+3−3
@@ -122,17 +122,17 @@ to specify in a pin configuration subnode: · 121 unmodified lines
122122 - bias-disable:
123123 Usage: optional
124124 Value type: <none>
125− Definition: The specified pins should be configued as no pull.
125+ Definition: The specified pins should be configured as no pull.
126126
127127 - bias-pull-down:
128128 Usage: optional
129129 Value type: <none>
130− Definition: The specified pins should be configued as pull down.
130+ Definition: The specified pins should be configured as pull down.
131131
132132 - bias-pull-up:
133133 Usage: optional
134134 Value type: <none>
135− Definition: The specified pins should be configued as pull up.
135+ Definition: The specified pins should be configured as pull up.
136136
137137 - output-high:
138138 Usage: optional
Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt+3−3
@@ -118,17 +118,17 @@ to specify in a pin configuration subnode: · 117 unmodified lines
118118 - bias-disable:
119119 Usage: optional
120120 Value type: <none>
121− Definition: The specified pins should be configued as no pull.
121+ Definition: The specified pins should be configured as no pull.
122122
123123 - bias-pull-down:
124124 Usage: optional
125125 Value type: <none>
126− Definition: The specified pins should be configued as pull down.
126+ Definition: The specified pins should be configured as pull down.
127127
128128 - bias-pull-up:
129129 Usage: optional
130130 Value type: <none>
131− Definition: The specified pins should be configued as pull up.
131+ Definition: The specified pins should be configured as pull up.
132132
133133 - output-high:
134134 Usage: optional
Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.txt+3−3
@@ -97,17 +97,17 @@ to specify in a pin configuration subnode: · 96 unmodified lines
9797 - bias-disable:
9898 Usage: optional
9999 Value type: <none>
100− Definition: The specified pins should be configued as no pull.
100+ Definition: The specified pins should be configured as no pull.
101101
102102 - bias-pull-down:
103103 Usage: optional
104104 Value type: <none>
105− Definition: The specified pins should be configued as pull down.
105+ Definition: The specified pins should be configured as pull down.
106106
107107 - bias-pull-up:
108108 Usage: optional
109109 Value type: <none>
110− Definition: The specified pins should be configued as pull up.
110+ Definition: The specified pins should be configured as pull up.
111111
112112 - output-high:
113113 Usage: optional
Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.txt+3−3
@@ -130,17 +130,17 @@ to specify in a pin configuration subnode: · 129 unmodified lines
130130 - bias-disable:
131131 Usage: optional
132132 Value type: <none>
133− Definition: The specified pins should be configued as no pull.
133+ Definition: The specified pins should be configured as no pull.
134134
135135 - bias-pull-down:
136136 Usage: optional
137137 Value type: <none>
138− Definition: The specified pins should be configued as pull down.
138+ Definition: The specified pins should be configured as pull down.
139139
140140 - bias-pull-up:
141141 Usage: optional
142142 Value type: <none>
143− Definition: The specified pins should be configued as pull up.
143+ Definition: The specified pins should be configured as pull up.
144144
145145 - output-high:
146146 Usage: optional
Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.txt+3−3
@@ -124,17 +124,17 @@ to specify in a pin configuration subnode: · 123 unmodified lines
124124 - bias-disable:
125125 Usage: optional
126126 Value type: <none>
127− Definition: The specified pins should be configued as no pull.
127+ Definition: The specified pins should be configured as no pull.
128128
129129 - bias-pull-down:
130130 Usage: optional
131131 Value type: <none>
132− Definition: The specified pins should be configued as pull down.
132+ Definition: The specified pins should be configured as pull down.
133133
134134 - bias-pull-up:
135135 Usage: optional
136136 Value type: <none>
137− Definition: The specified pins should be configued as pull up.
137+ Definition: The specified pins should be configured as pull up.
138138
139139 - output-high:
140140 Usage: optional
Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.txt+3−3
@@ -128,17 +128,17 @@ to specify in a pin configuration subnode: · 127 unmodified lines
128128 - bias-disable:
129129 Usage: optional
130130 Value type: <none>
131− Definition: The specified pins should be configued as no pull.
131+ Definition: The specified pins should be configured as no pull.
132132
133133 - bias-pull-down:
134134 Usage: optional
135135 Value type: <none>
136− Definition: The specified pins should be configued as pull down.
136+ Definition: The specified pins should be configured as pull down.
137137
138138 - bias-pull-up:
139139 Usage: optional
140140 Value type: <none>
141− Definition: The specified pins should be configued as pull up.
141+ Definition: The specified pins should be configured as pull up.
142142
143143 - output-high:
144144 Usage: optional
Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.txt+3−3
@@ -149,17 +149,17 @@ to specify in a pin configuration subnode: · 148 unmodified lines
149149 - bias-disable:
150150 Usage: optional
151151 Value type: <none>
152− Definition: The specified pins should be configued as no pull.
152+ Definition: The specified pins should be configured as no pull.
153153
154154 - bias-pull-down:
155155 Usage: optional
156156 Value type: <none>
157− Definition: The specified pins should be configued as pull down.
157+ Definition: The specified pins should be configured as pull down.
158158
159159 - bias-pull-up:
160160 Usage: optional
161161 Value type: <none>
162− Definition: The specified pins should be configued as pull up.
162+ Definition: The specified pins should be configured as pull up.
163163
164164 - output-high:
165165 Usage: optional
Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt+13−3
@@ -40,6 +40,14 @@ MSM8998 platform. · 39 unmodified lines
4040 Definition: must be 2. Specifying the pin number and flags, as defined
4141 in <dt-bindings/gpio/gpio.h>
4242
43+- gpio-ranges:
44+ Usage: required
45+ Definition: see ../gpio/gpio.txt
46+
47+- gpio-reserved-ranges:
48+ Usage: optional
49+ Definition: see ../gpio/gpio.txt
50+
4351 Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
4452 a general description of GPIO and interrupt bindings.
4553
@@ -135,17 +143,17 @@ to specify in a pin configuration subnode: · 89 unmodified lines
135143 - bias-disable:
136144 Usage: optional
137145 Value type: <none>
138− Definition: The specified pins should be configued as no pull.
146+ Definition: The specified pins should be configured as no pull.
139147
140148 - bias-pull-down:
141149 Usage: optional
142150 Value type: <none>
143− Definition: The specified pins should be configued as pull down.
151+ Definition: The specified pins should be configured as pull down.
144152
145153 - bias-pull-up:
146154 Usage: optional
147155 Value type: <none>
148− Definition: The specified pins should be configued as pull up.
156+ Definition: The specified pins should be configured as pull up.
149157
150158 - output-high:
151159 Usage: optional
@@ -175,6 +183,8 @@ Example: · 23 unmodified lines
175183 interrupts = <0 208 0>;
176184 gpio-controller;
177185 #gpio-cells = <2>;
186+ gpio-ranges = <&tlmm 0 0 175>;
187+ gpio-reserved-ranges = <0 4>, <81 4>;
178188 interrupt-controller;
179189 #interrupt-cells = <2>;
180190
Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.txt+3−3
@@ -150,17 +150,17 @@ to specify in a pin configuration subnode: · 149 unmodified lines
150150 - bias-disable:
151151 Usage: optional
152152 Value type: <none>
153− Definition: The specified pins should be configued as no pull.
153+ Definition: The specified pins should be configured as no pull.
154154
155155 - bias-pull-down:
156156 Usage: optional
157157 Value type: <none>
158− Definition: The specified pins should be configued as pull down.
158+ Definition: The specified pins should be configured as pull down.
159159
160160 - bias-pull-up:
161161 Usage: optional
162162 Value type: <none>
163− Definition: The specified pins should be configued as pull up.
163+ Definition: The specified pins should be configured as pull up.
164164
165165 - output-high:
166166 Usage: optional
Documentation/devicetree/bindings/pinctrl/qcom,sdm660-pinctrl.txt+3−3
@@ -142,17 +142,17 @@ to specify in a pin configuration subnode: · 141 unmodified lines
142142 - bias-disable:
143143 Usage: optional
144144 Value type: <none>
145− Definition: The specified pins should be configued as no pull.
145+ Definition: The specified pins should be configured as no pull.
146146
147147 - bias-pull-down:
148148 Usage: optional
149149 Value type: <none>
150− Definition: The specified pins should be configued as pull down.
150+ Definition: The specified pins should be configured as pull down.
151151
152152 - bias-pull-up:
153153 Usage: optional
154154 Value type: <none>
155− Definition: The specified pins should be configued as pull up.
155+ Definition: The specified pins should be configured as pull up.
156156
157157 - output-high:
158158 Usage: optional
Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt+4−4
@@ -79,7 +79,7 @@ to specify in a pin configuration subnode: · 78 unmodified lines
7979 gpio0-gpio149
8080 Supports mux, bias and drive-strength
8181
82− sdc2_clk, sdc2_cmd, sdc2_data
82+ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset
8383 Supports bias and drive-strength
8484
8585 - function:
@@ -118,17 +118,17 @@ to specify in a pin configuration subnode: · 32 unmodified lines
118118 - bias-disable:
119119 Usage: optional
120120 Value type: <none>
121− Definition: The specified pins should be configued as no pull.
121+ Definition: The specified pins should be configured as no pull.
122122
123123 - bias-pull-down:
124124 Usage: optional
125125 Value type: <none>
126− Definition: The specified pins should be configued as pull down.
126+ Definition: The specified pins should be configured as pull down.
127127
128128 - bias-pull-up:
129129 Usage: optional
130130 Value type: <none>
131− Definition: The specified pins should be configued as pull up.
131+ Definition: The specified pins should be configured as pull up.
132132
133133 - output-high:
134134 Usage: optional
Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.txt+190−0
@@ -0,0 +1,190 @@
1+Qualcomm SM8150 TLMM block
2+
3+This binding describes the Top Level Mode Multiplexer block found in the
4+QCS404 platform.
5+
6+- compatible:
7+ Usage: required
8+ Value type: <string>
9+ Definition: must be "qcom,sm8150-pinctrl"
10+
11+- reg:
12+ Usage: required
13+ Value type: <prop-encoded-array>
14+ Definition: the base address and size of the north, south, west
15+ and east TLMM tiles.
16+
17+- reg-names:
18+ Usage: required
19+ Value type: <prop-encoded-array>
20+ Defintiion: names for the cells of reg, must contain "north", "south"
21+ "west" and "east".
22+
23+- interrupts:
24+ Usage: required
25+ Value type: <prop-encoded-array>
26+ Definition: should specify the TLMM summary IRQ.
27+
28+- interrupt-controller:
29+ Usage: required
30+ Value type: <none>
31+ Definition: identifies this node as an interrupt controller
32+
33+- #interrupt-cells:
34+ Usage: required
35+ Value type: <u32>
36+ Definition: must be 2. Specifying the pin number and flags, as defined
37+ in <dt-bindings/interrupt-controller/irq.h>
38+
39+- gpio-controller:
40+ Usage: required
41+ Value type: <none>
42+ Definition: identifies this node as a gpio controller
43+
44+- #gpio-cells:
45+ Usage: required
46+ Value type: <u32>
47+ Definition: must be 2. Specifying the pin number and flags, as defined
48+ in <dt-bindings/gpio/gpio.h>
49+
50+- gpio-ranges:
51+ Usage: required
52+ Value type: <prop-encoded-array>
53+ Definition: see ../gpio/gpio.txt
54+
55+- gpio-reserved-ranges:
56+ Usage: optional
57+ Value type: <prop-encoded-array>
58+ Definition: see ../gpio/gpio.txt
59+
60+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
61+a general description of GPIO and interrupt bindings.
62+
63+Please refer to pinctrl-bindings.txt in this directory for details of the
64+common pinctrl bindings used by client devices, including the meaning of the
65+phrase "pin configuration node".
66+
67+The pin configuration nodes act as a container for an arbitrary number of
68+subnodes. Each of these subnodes represents some desired configuration for a
69+pin, a group, or a list of pins or groups. This configuration can include the
70+mux function to select on those pin(s)/group(s), and various pin configuration
71+parameters, such as pull-up, drive strength, etc.
72+
73+
74+PIN CONFIGURATION NODES:
75+
76+The name of each subnode is not important; all subnodes should be enumerated
77+and processed purely based on their content.
78+
79+Each subnode only affects those parameters that are explicitly listed. In
80+other words, a subnode that lists a mux function but no pin configuration
81+parameters implies no information about any pin configuration parameters.
82+Similarly, a pin subnode that describes a pullup parameter implies no
83+information about e.g. the mux function.
84+
85+
86+The following generic properties as defined in pinctrl-bindings.txt are valid
87+to specify in a pin configuration subnode:
88+
89+- pins:
90+ Usage: required
91+ Value type: <string-array>
92+ Definition: List of gpio pins affected by the properties specified in
93+ this subnode.
94+
95+ Valid pins are:
96+ gpio0-gpio149
97+ Supports mux, bias and drive-strength
98+
99+ sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
100+ sdc2_data sdc1_rclk
101+ Supports bias and drive-strength
102+
103+ ufs_reset
104+ Supports bias and drive-strength
105+
106+- function:
107+ Usage: required
108+ Value type: <string>
109+ Definition: Specify the alternative function to be configured for the
110+ specified pins. Functions are only valid for gpio pins.
111+ Valid values are:
112+
113+ adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char,
114+ atest_char0, atest_char1, atest_char2, atest_char3,
115+ audio_ref, atest_usb1, atest_usb2, atest_usb10,
116+ atest_usb11, atest_usb12, atest_usb13, atest_usb20,
117+ atest_usb21, atest_usb22, atest_usb2, atest_usb23,
118+ btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
119+ cci_timer1, cci_timer2, cci_timer3, cci_timer4,
120+ cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
121+ ddr_pxi0, ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd,
122+ emac_phy, emac_pps, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
123+ hs1_mi2s, hs2_mi2s, hs3_mi2s, jitter_bist,
124+ lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1,
125+ mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps,
126+ pa_indicator, pci_e0, phase_flag, pll_bypassnl,
127+ pll_bist, pci_e1, pll_reset, pri_mi2s, pri_mi2s_ws,
128+ prng_rosc, qdss, qdss_cti, qlink_request, qlink_enable,
129+ qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qua_mi2s,
130+ qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
131+ qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16,
132+ qup17, qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii,
133+ sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu, ter_mi2s,
134+ tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
135+ tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt,
136+ usb2phy_ac, usb_phy, vfr_1, vsense_trigger, wlan1_adc0,
137+ wlan1_adc1, wlan2_adc0, wlan2_adc1, wmss_reset
138+
139+- bias-disable:
140+ Usage: optional
141+ Value type: <none>
142+ Definition: The specified pins should be configued as no pull.
143+
144+- bias-pull-down:
145+ Usage: optional
146+ Value type: <none>
147+ Definition: The specified pins should be configued as pull down.
148+
149+- bias-pull-up:
150+ Usage: optional
151+ Value type: <none>
152+ Definition: The specified pins should be configued as pull up.
153+
154+- output-high:
155+ Usage: optional
156+ Value type: <none>
157+ Definition: The specified pins are configured in output mode, driven
158+ high.
159+ Not valid for sdc pins.
160+
161+- output-low:
162+ Usage: optional
163+ Value type: <none>
164+ Definition: The specified pins are configured in output mode, driven
165+ low.
166+ Not valid for sdc pins.
167+
168+- drive-strength:
169+ Usage: optional
170+ Value type: <u32>
171+ Definition: Selects the drive strength for the specified pins, in mA.
172+ Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
173+
174+Example:
175+
176+ tlmm: pinctrl@3000000 {
177+ compatible = "qcom,sm8150-pinctrl";
178+ reg = <0x03100000 0x300000>,
179+ <0x03500000 0x300000>,
180+ <0x03900000 0x300000>,
181+ <0x03D00000 0x300000>;
182+ reg-names = "west", "east", "north", "south";
183+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
184+ gpio-controller;
185+ #gpio-cells = <2>;
186+ gpio-ranges = <&tlmm 0 0 175>;
187+ gpio-reserved-ranges = <0 4>, <126 4>;
188+ interrupt-controller;
189+ #interrupt-cells = <2>;
190+ };
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt+0−208
@@ -1,208 +0,0 @@
1−* STM32 GPIO and Pin Mux/Config controller
2−
3−STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
4−controller. It controls the input/output settings on the available pins and
5−also provides ability to multiplex and configure the output of various on-chip
6−controllers onto these pads.
7−
8−Pin controller node:
9−Required properies:
10− - compatible: value should be one of the following:
11− "st,stm32f429-pinctrl"
12− "st,stm32f469-pinctrl"
13− "st,stm32f746-pinctrl"
14− "st,stm32f769-pinctrl"
15− "st,stm32h743-pinctrl"
16− "st,stm32mp157-pinctrl"
17− "st,stm32mp157-z-pinctrl"
18− - #address-cells: The value of this property must be 1
19− - #size-cells : The value of this property must be 1
20− - ranges : defines mapping between pin controller node (parent) to
21− gpio-bank node (children).
22− - pins-are-numbered: Specify the subnodes are using numbered pinmux to
23− specify pins.
24−
25−GPIO controller/bank node:
26−Required properties:
27− - gpio-controller : Indicates this device is a GPIO controller
28− - #gpio-cells : Should be two.
29− The first cell is the pin number
30− The second one is the polarity:
31− - 0 for active high
32− - 1 for active low
33− - reg : The gpio address range, relative to the pinctrl range
34− - clocks : clock that drives this bank
35− - st,bank-name : Should be a name string for this bank as specified in
36− the datasheet
37−
38−Optional properties:
39− - reset: : Reference to the reset controller
40− - st,syscfg: Should be phandle/offset/mask.
41− -The phandle to the syscon node which includes IRQ mux selection register.
42− -The offset of the IRQ mux selection register
43− -The field mask of IRQ mux, needed if different of 0xf.
44− - gpio-ranges: Define a dedicated mapping between a pin-controller and
45− a gpio controller. Format is <&phandle a b c> with:
46− -(phandle): phandle of pin-controller.
47− -(a): gpio base offset in range.
48− -(b): pin base offset in range.
49− -(c): gpio count in range
50− This entry has to be used either if there are holes inside a bank:
51− GPIOB0/B1/B2/B14/B15 (see example 2)
52− or if banks are not contiguous:
53− GPIOA/B/C/E...
54− NOTE: If "gpio-ranges" is used for a gpio controller, all gpio-controller
55− have to use a "gpio-ranges" entry.
56− More details in Documentation/devicetree/bindings/gpio/gpio.txt.
57− - st,bank-ioport: should correspond to the EXTI IOport selection (EXTI line
58− used to select GPIOs as interrupts).
59− - hwlocks: reference to a phandle of a hardware spinlock provider node.
60− - st,package: Indicates the SOC package used.
61− More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
62−
63−Example 1:
64−#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
65−...
66−
67− pin-controller {
68− #address-cells = <1>;
69− #size-cells = <1>;
70− compatible = "st,stm32f429-pinctrl";
71− ranges = <0 0x40020000 0x3000>;
72− pins-are-numbered;
73−
74− gpioa: gpio@40020000 {
75− gpio-controller;
76− #gpio-cells = <2>;
77− reg = <0x0 0x400>;
78− resets = <&reset_ahb1 0>;
79− st,bank-name = "GPIOA";
80− };
81− ...
82− pin-functions nodes follow...
83− };
84−
85−Example 2:
86−#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
87−...
88−
89− pinctrl: pin-controller {
90− #address-cells = <1>;
91− #size-cells = <1>;
92− compatible = "st,stm32f429-pinctrl";
93− ranges = <0 0x40020000 0x3000>;
94− pins-are-numbered;
95−
96− gpioa: gpio@40020000 {
97− gpio-controller;
98− #gpio-cells = <2>;
99− reg = <0x0 0x400>;
100− resets = <&reset_ahb1 0>;
101− st,bank-name = "GPIOA";
102− gpio-ranges = <&pinctrl 0 0 16>;
103− };
104−
105− gpiob: gpio@40020400 {
106− gpio-controller;
107− #gpio-cells = <2>;
108− reg = <0x0 0x400>;
109− resets = <&reset_ahb1 0>;
110− st,bank-name = "GPIOB";
111− ngpios = 4;
112− gpio-ranges = <&pinctrl 0 16 3>,
113− <&pinctrl 14 30 2>;
114− };
115−
116−
117− ...
118− pin-functions nodes follow...
119− };
120−
121−
122−Contents of function subnode node:
123−----------------------------------
124−Subnode format
125−A pinctrl node should contain at least one subnode representing the
126−pinctrl group available on the machine. Each subnode will list the
127−pins it needs, and how they should be configured, with regard to muxer
128−configuration, pullups, drive, output high/low and output speed.
129−
130− node {
131− pinmux = <PIN_NUMBER_PINMUX>;
132− GENERIC_PINCONFIG;
133− };
134−
135−Required properties:
136−- pinmux: integer array, represents gpio pin number and mux setting.
137− Supported pin number and mux varies for different SoCs, and are defined in
138− dt-bindings/pinctrl/<soc>-pinfunc.h directly.
139− These defines are calculated as:
140− ((port * 16 + line) << 8) | function
141− With:
142− - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
143− - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
144− - function: The function number, can be:
145− * 0 : GPIO
146− * 1 : Alternate Function 0
147− * 2 : Alternate Function 1
148− * 3 : Alternate Function 2
149− * ...
150− * 16 : Alternate Function 15
151− * 17 : Analog
152−
153− To simplify the usage, macro is available to generate "pinmux" field.
154− This macro is available here:
155− - include/dt-bindings/pinctrl/stm32-pinfunc.h
156−
157− Some examples of using macro:
158− /* GPIO A9 set as alernate function 2 */
159− ... {
160− pinmux = <STM32_PINMUX('A', 9, AF2)>;
161− };
162− /* GPIO A9 set as GPIO */
163− ... {
164− pinmux = <STM32_PINMUX('A', 9, GPIO)>;
165− };
166− /* GPIO A9 set as analog */
167− ... {
168− pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
169− };
170−
171−Optional properties:
172−- GENERIC_PINCONFIG: is the generic pinconfig options to use.
173− Available options are:
174− - bias-disable,
175− - bias-pull-down,
176− - bias-pull-up,
177− - drive-push-pull,
178− - drive-open-drain,
179− - output-low
180− - output-high
181− - slew-rate = <x>, with x being:
182− < 0 > : Low speed
183− < 1 > : Medium speed
184− < 2 > : Fast speed
185− < 3 > : High speed
186−
187−Example:
188−
189−pin-controller {
190−...
191− usart1_pins_a: usart1@0 {
192− pins1 {
193− pinmux = <STM32_PINMUX('A', 9, AF7)>;
194− bias-disable;
195− drive-push-pull;
196− slew-rate = <0>;
197− };
198− pins2 {
199− pinmux = <STM32_PINMUX('A', 10, AF7)>;
200− bias-disable;
201− };
202− };
203−};
204−
205−&usart1 {
206− pinctrl-0 = <&usart1_pins_a>;
207− pinctrl-names = "default";
208−};
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml+264−0
@@ -0,0 +1,264 @@
1+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2+# Copyright (C) STMicroelectronics 2019.
3+%YAML 1.2
4+---
5+$id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6+$schema: http://devicetree.org/meta-schemas/core.yaml#
7+
8+title: STM32 GPIO and Pin Mux/Config controller
9+
10+maintainers:
11+ - Alexandre TORGUE <alexandre.torgue@st.com>
12+
13+description: |
14+ STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
15+ controller. It controls the input/output settings on the available pins and
16+ also provides ability to multiplex and configure the output of various
17+ on-chip controllers onto these pads.
18+
19+properties:
20+ compatible:
21+ enum:
22+ - st,stm32f429-pinctrl
23+ - st,stm32f469-pinctrl
24+ - st,stm32f746-pinctrl
25+ - st,stm32f769-pinctrl
26+ - st,stm32h743-pinctrl
27+ - st,stm32mp157-pinctrl
28+ - st,stm32mp157-z-pinctrl
29+
30+ '#address-cells':
31+ const: 1
32+ '#size-cells':
33+ const: 1
34+
35+ ranges: true
36+ pins-are-numbered: true
37+ hwlocks: true
38+
39+ st,syscfg:
40+ $ref: "/schemas/types.yaml#/definitions/phandle-array"
41+ description: Should be phandle/offset/mask
42+ items:
43+ - description: Phandle to the syscon node which includes IRQ mux selection.
44+ - description: The offset of the IRQ mux selection register.
45+ - description: The field mask of IRQ mux, needed if different of 0xf.
46+
47+ st,package:
48+ allOf:
49+ - $ref: /schemas/types.yaml#/definitions/uint32
50+ - enum: [1, 2, 4, 8]
51+ description:
52+ Indicates the SOC package used.
53+ More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
54+
55+
56+patternProperties:
57+ '^gpio@[0-9a-f]*$':
58+ properties:
59+ gpio-controller: true
60+ '#gpio-cells':
61+ const: 2
62+
63+ reg:
64+ maxItems: 1
65+ clocks:
66+ maxItems: 1
67+ reset:
68+ minItems: 1
69+ maxItems: 1
70+ gpio-ranges:
71+ minItems: 1
72+ maxItems: 16
73+ ngpios:
74+ description:
75+ Number of available gpios in a bank.
76+ minimum: 1
77+ maximum: 16
78+
79+ st,bank-name:
80+ allOf:
81+ - $ref: "/schemas/types.yaml#/definitions/string"
82+ - enum:
83+ - GPIOA
84+ - GPIOB
85+ - GPIOC
86+ - GPIOD
87+ - GPIOE
88+ - GPIOF
89+ - GPIOG
90+ - GPIOH
91+ - GPIOI
92+ - GPIOJ
93+ - GPIOK
94+ - GPIOZ
95+ description:
96+ Should be a name string for this bank as specified in the datasheet.
97+
98+ st,bank-ioport:
99+ allOf:
100+ - $ref: "/schemas/types.yaml#/definitions/uint32"
101+ - minimum: 0
102+ - maximum: 11
103+
104+ description:
105+ Should correspond to the EXTI IOport selection (EXTI line used
106+ to select GPIOs as interrupts).
107+
108+ required:
109+ - gpio-controller
110+ - '#gpio-cells'
111+ - reg
112+ - clocks
113+ - st,bank-name
114+
115+ '-[0-9]*$':
116+ patternProperties:
117+ '^pins':
118+ description: |
119+ A pinctrl node should contain at least one subnode representing the
120+ pinctrl group available on the machine. Each subnode will list the
121+ pins it needs, and how they should be configured, with regard to muxer
122+ configuration, pullups, drive, output high/low and output speed.
123+ properties:
124+ pinmux:
125+ allOf:
126+ - $ref: "/schemas/types.yaml#/definitions/uint32-array"
127+ description: |
128+ Integer array, represents gpio pin number and mux setting.
129+ Supported pin number and mux varies for different SoCs, and are
130+ defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
131+ These defines are calculated as: ((port * 16 + line) << 8) | function
132+ With:
133+ - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
134+ - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
135+ - function: The function number, can be:
136+ * 0 : GPIO
137+ * 1 : Alternate Function 0
138+ * 2 : Alternate Function 1
139+ * 3 : Alternate Function 2
140+ * ...
141+ * 16 : Alternate Function 15
142+ * 17 : Analog
143+ To simplify the usage, macro is available to generate "pinmux" field.
144+ This macro is available here:
145+ - include/dt-bindings/pinctrl/stm32-pinfunc.h
146+ Some examples of using macro:
147+ /* GPIO A9 set as alernate function 2 */
148+ ... {
149+ pinmux = <STM32_PINMUX('A', 9, AF2)>;
150+ };
151+ /* GPIO A9 set as GPIO */
152+ ... {
153+ pinmux = <STM32_PINMUX('A', 9, GPIO)>;
154+ };
155+ /* GPIO A9 set as analog */
156+ ... {
157+ pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
158+ };
159+
160+ bias-disable:
161+ type: boolean
162+ bias-pull-down:
163+ type: boolean
164+ bias-pull-up:
165+ type: boolean
166+ drive-push-pull:
167+ type: boolean
168+ drive-open-drain:
169+ type: boolean
170+ output-low:
171+ type: boolean
172+ output-high:
173+ type: boolean
174+ slew-rate:
175+ description: |
176+ 0: Low speed
177+ 1: Medium speed
178+ 2: Fast speed
179+ 3: High speed
180+ allOf:
181+ - $ref: /schemas/types.yaml#/definitions/uint32
182+ - enum: [0, 1, 2, 3]
183+
184+ required:
185+ - pinmux
186+
187+required:
188+ - compatible
189+ - '#address-cells'
190+ - '#size-cells'
191+ - ranges
192+ - pins-are-numbered
193+
194+examples:
195+ - |
196+ #include <dt-bindings/pinctrl/stm32-pinfunc.h>
197+ //Example 1
198+ pinctrl@40020000 {
199+ #address-cells = <1>;
200+ #size-cells = <1>;
201+ compatible = "st,stm32f429-pinctrl";
202+ ranges = <0 0x40020000 0x3000>;
203+ pins-are-numbered;
204+
205+ gpioa: gpio@0 {
206+ gpio-controller;
207+ #gpio-cells = <2>;
208+ reg = <0x0 0x400>;
209+ resets = <&reset_ahb1 0>;
210+ st,bank-name = "GPIOA";
211+ };
212+ };
213+
214+ //Example 2 (using gpio-ranges)
215+ pinctrl@50020000 {
216+ #address-cells = <1>;
217+ #size-cells = <1>;
218+ compatible = "st,stm32f429-pinctrl";
219+ ranges = <0 0x50020000 0x3000>;
220+ pins-are-numbered;
221+
222+ gpiob: gpio@1000 {
223+ gpio-controller;
224+ #gpio-cells = <2>;
225+ reg = <0x1000 0x400>;
226+ resets = <&reset_ahb1 0>;
227+ st,bank-name = "GPIOB";
228+ gpio-ranges = <&pinctrl 0 0 16>;
229+ };
230+
231+ gpioc: gpio@2000 {
232+ gpio-controller;
233+ #gpio-cells = <2>;
234+ reg = <0x2000 0x400>;
235+ resets = <&reset_ahb1 0>;
236+ st,bank-name = "GPIOC";
237+ ngpios = <5>;
238+ gpio-ranges = <&pinctrl 0 16 3>,
239+ <&pinctrl 14 30 2>;
240+ };
241+ };
242+
243+ //Example 3 pin groups
244+ pinctrl@60020000 {
245+ usart1_pins_a: usart1-0 {
246+ pins1 {
247+ pinmux = <STM32_PINMUX('A', 9, AF7)>;
248+ bias-disable;
249+ drive-push-pull;
250+ slew-rate = <0>;
251+ };
252+ pins2 {
253+ pinmux = <STM32_PINMUX('A', 10, AF7)>;
254+ bias-disable;
255+ };
256+ };
257+ };
258+
259+ usart1 {
260+ pinctrl-0 = <&usart1_pins_a>;
261+ pinctrl-names = "default";
262+ };
263+
264+...
MAINTAINERS+9−0
@@ -2625,6 +2625,15 @@ S: Maintained · 2624 unmodified lines
26252625 F: Documentation/hwmon/asc7621.rst
26262626 F: drivers/hwmon/asc7621.c
26272627
2628+ASPEED PINCTRL DRIVERS
2629+M: Andrew Jeffery <andrew@aj.id.au>
2630+L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
2631+L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
2632+L: linux-gpio@vger.kernel.org
2633+S: Maintained
2634+F: drivers/pinctrl/aspeed/
2635+F: Documentation/devicetree/bindings/pinctrl/aspeed,*
2636+
26282637 ASPEED VIDEO ENGINE DRIVER
26292638 M: Eddie James <eajames@linux.ibm.com>
26302639 L: linux-media@vger.kernel.org
arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h+646−0
@@ -0,0 +1,646 @@
1+/* SPDX-License-Identifier: GPL-2.0+ */
2+/*
3+ * Copyright 2018-2019 NXP
4+ */
5+
6+#ifndef __DTS_IMX8MN_PINFUNC_H
7+#define __DTS_IMX8MN_PINFUNC_H
8+
9+/*
10+ * The pin function ID is a tuple of
11+ * <mux_reg conf_reg input_reg mux_mode input_val>
12+ */
13+
14+#define MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15+#define MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16+#define MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17+#define MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18+#define MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19+#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20+#define MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21+#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22+#define MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23+#define MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
24+#define MX8MN_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x000 0x5 0x0
25+#define MX8MN_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0
26+#define MX8MN_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0
27+#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0
28+#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0
29+#define MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0
30+#define MX8MN_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0
31+#define MX8MN_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0
32+#define MX8MN_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0
33+#define MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0
34+#define MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0
35+#define MX8MN_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0
36+#define MX8MN_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0
37+#define MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0
38+#define MX8MN_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0
39+#define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x4BC 0x5 0x0
40+#define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0
41+#define MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0
42+#define MX8MN_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0
43+#define MX8MN_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0
44+#define MX8MN_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0
45+#define MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0
46+#define MX8MN_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x4C0 0x1 0x0
47+#define MX8MN_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0
48+#define MX8MN_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0
49+#define MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0
50+#define MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0
51+#define MX8MN_IOMUXC_GPIO1_IO08_PWM1_OUT 0x048 0x2B0 0x000 0x2 0x0
52+#define MX8MN_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0
53+#define MX8MN_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0
54+#define MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0
55+#define MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0
56+#define MX8MN_IOMUXC_GPIO1_IO09_PWM2_OUT 0x04C 0x2B4 0x000 0x2 0x0
57+#define MX8MN_IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x04C 0x2B4 0x000 0x4 0x0
58+#define MX8MN_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0
59+#define MX8MN_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0
60+#define MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0
61+#define MX8MN_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0
62+#define MX8MN_IOMUXC_GPIO1_IO10_PWM3_OUT 0x050 0x2B8 0x000 0x2 0x0
63+#define MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0
64+#define MX8MN_IOMUXC_GPIO1_IO11_PWM2_OUT 0x054 0x2BC 0x000 0x1 0x0
65+#define MX8MN_IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x054 0x2BC 0x000 0x4 0x0
66+#define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1
67+#define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0
68+#define MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0
69+#define MX8MN_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0
70+#define MX8MN_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0
71+#define MX8MN_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0
72+#define MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0
73+#define MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0
74+#define MX8MN_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0
75+#define MX8MN_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0
76+#define MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0
77+#define MX8MN_IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x060 0x2C8 0x598 0x4 0x2
78+#define MX8MN_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0
79+#define MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0
80+#define MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0
81+#define MX8MN_IOMUXC_GPIO1_IO15_USDHC3_WP 0x064 0x2CC 0x5B8 0x4 0x2
82+#define MX8MN_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0
83+#define MX8MN_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0
84+#define MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0
85+#define MX8MN_IOMUXC_ENET_MDC_SAI6_TX_DATA0 0x068 0x2D0 0x000 0x2 0x0
86+#define MX8MN_IOMUXC_ENET_MDC_PDM_BIT_STREAM3 0x068 0x2D0 0x540 0x3 0x1
87+#define MX8MN_IOMUXC_ENET_MDC_SPDIF1_OUT 0x068 0x2D0 0x000 0x4 0x0
88+#define MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0
89+#define MX8MN_IOMUXC_ENET_MDC_USDHC3_STROBE 0x068 0x2D0 0x59C 0x6 0x1
90+#define MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1
91+#define MX8MN_IOMUXC_ENET_MDIO_SAI6_TX_SYNC 0x06C 0x2D4 0x000 0x2 0x0
92+#define MX8MN_IOMUXC_ENET_MDIO_PDM_BIT_STREAM2 0x06C 0x2D4 0x53C 0x3 0x1
93+#define MX8MN_IOMUXC_ENET_MDIO_SPDIF1_IN 0x06C 0x2D4 0x5CC 0x4 0x1
94+#define MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0
95+#define MX8MN_IOMUXC_ENET_MDIO_USDHC3_DATA5 0x06C 0x2D4 0x550 0x6 0x1
96+#define MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0
97+#define MX8MN_IOMUXC_ENET_TD3_SAI6_TX_BCLK 0x070 0x2D8 0x000 0x2 0x0
98+#define MX8MN_IOMUXC_ENET_TD3_PDM_BIT_STREAM1 0x070 0x2D8 0x538 0x3 0x1
99+#define MX8MN_IOMUXC_ENET_TD3_SPDIF1_EXT_CLK 0x070 0x2D8 0x568 0x4 0x1
100+#define MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0
101+#define MX8MN_IOMUXC_ENET_TD3_USDHC3_DATA6 0x070 0x2D8 0x584 0x6 0x1
102+#define MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0
103+#define MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x5A4 0x1 0x0
104+#define MX8MN_IOMUXC_ENET_TD2_CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x074 0x2DC 0x5A4 0x1 0x0
105+#define MX8MN_IOMUXC_ENET_TD2_SAI6_RX_DATA0 0x074 0x2DC 0x000 0x2 0x0
106+#define MX8MN_IOMUXC_ENET_TD2_PDM_BIT_STREAM3 0x074 0x2DC 0x540 0x3 0x2
107+#define MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0
108+#define MX8MN_IOMUXC_ENET_TD2_USDHC3_DATA7 0x074 0x2DC 0x54C 0x6 0x1
109+#define MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0
110+#define MX8MN_IOMUXC_ENET_TD1_SAI6_RX_SYNC 0x078 0x2E0 0x000 0x2 0x0
111+#define MX8MN_IOMUXC_ENET_TD1_PDM_BIT_STREAM2 0x078 0x2E0 0x53C 0x3 0x2
112+#define MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0
113+#define MX8MN_IOMUXC_ENET_TD1_USDHC3_CD_B 0x078 0x2E0 0x598 0x6 0x3
114+#define MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0
115+#define MX8MN_IOMUXC_ENET_TD0_SAI6_RX_BCLK 0x07C 0x2E4 0x000 0x2 0x0
116+#define MX8MN_IOMUXC_ENET_TD0_PDM_BIT_STREAM1 0x07C 0x2E4 0x538 0x3 0x2
117+#define MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0
118+#define MX8MN_IOMUXC_ENET_TD0_USDHC3_WP 0x07C 0x2E4 0x5B8 0x6 0x3
119+#define MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0
120+#define MX8MN_IOMUXC_ENET_TX_CTL_SAI6_MCLK 0x080 0x2E8 0x000 0x2 0x0
121+#define MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0
122+#define MX8MN_IOMUXC_ENET_TX_CTL_USDHC3_DATA0 0x080 0x2E8 0x5B4 0x6 0x1
123+#define MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0
124+#define MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0
125+#define MX8MN_IOMUXC_ENET_TXC_SAI7_TX_DATA0 0x084 0x2EC 0x000 0x2 0x0
126+#define MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0
127+#define MX8MN_IOMUXC_ENET_TXC_USDHC3_DATA1 0x084 0x2EC 0x5B0 0x6 0x1
128+#define MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x574 0x0 0x0
129+#define MX8MN_IOMUXC_ENET_RX_CTL_SAI7_TX_SYNC 0x088 0x2F0 0x000 0x2 0x0
130+#define MX8MN_IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM3 0x088 0x2F0 0x540 0x3 0x3
131+#define MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0
132+#define MX8MN_IOMUXC_ENET_RX_CTL_USDHC3_DATA2 0x088 0x2F0 0x5E4 0x6 0x1
133+#define MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0
134+#define MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x5C8 0x1 0x0
135+#define MX8MN_IOMUXC_ENET_RXC_SAI7_TX_BCLK 0x08C 0x2F4 0x000 0x2 0x0
136+#define MX8MN_IOMUXC_ENET_RXC_PDM_BIT_STREAM2 0x08C 0x2F4 0x53C 0x3 0x3
137+#define MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0
138+#define MX8MN_IOMUXC_ENET_RXC_USDHC3_DATA3 0x08C 0x2F4 0x5E0 0x6 0x1
139+#define MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x57C 0x0 0x0
140+#define MX8MN_IOMUXC_ENET_RD0_SAI7_RX_DATA0 0x090 0x2F8 0x000 0x2 0x0
141+#define MX8MN_IOMUXC_ENET_RD0_PDM_BIT_STREAM1 0x090 0x2F8 0x538 0x3 0x3
142+#define MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0
143+#define MX8MN_IOMUXC_ENET_RD0_USDHC3_DATA4 0x090 0x2F8 0x558 0x6 0x1
144+#define MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x554 0x0 0x0
145+#define MX8MN_IOMUXC_ENET_RD1_SAI7_RX_SYNC 0x094 0x2FC 0x000 0x2 0x0
146+#define MX8MN_IOMUXC_ENET_RD1_PDM_BIT_STREAM0 0x094 0x2FC 0x534 0x3 0x1
147+#define MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0
148+#define MX8MN_IOMUXC_ENET_RD1_USDHC3_RESET_B 0x094 0x2FC 0x000 0x6 0x0
149+#define MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0
150+#define MX8MN_IOMUXC_ENET_RD2_SAI7_RX_BCLK 0x098 0x300 0x000 0x2 0x0
151+#define MX8MN_IOMUXC_ENET_RD2_PDM_CLK 0x098 0x300 0x000 0x3 0x0
152+#define MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0
153+#define MX8MN_IOMUXC_ENET_RD2_USDHC3_CLK 0x098 0x300 0x5A0 0x6 0x1
154+#define MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0
155+#define MX8MN_IOMUXC_ENET_RD3_SAI7_MCLK 0x09C 0x304 0x000 0x2 0x0
156+#define MX8MN_IOMUXC_ENET_RD3_SPDIF1_IN 0x09C 0x304 0x5CC 0x3 0x5
157+#define MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0
158+#define MX8MN_IOMUXC_ENET_RD3_USDHC3_CMD 0x09C 0x304 0x5DC 0x6 0x1
159+#define MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0
160+#define MX8MN_IOMUXC_SD1_CLK_ENET1_MDC 0x0A0 0x308 0x000 0x1 0x0
161+#define MX8MN_IOMUXC_SD1_CLK_UART1_DCE_TX 0x0A0 0x308 0x000 0x4 0x0
162+#define MX8MN_IOMUXC_SD1_CLK_UART1_DTE_RX 0x0A0 0x308 0x4F4 0x4 0x4
163+#define MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0
164+#define MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
165+#define MX8MN_IOMUXC_SD1_CMD_ENET1_MDIO 0x0A4 0x30C 0x4C0 0x1 0x3
166+#define MX8MN_IOMUXC_SD1_CMD_UART1_DCE_RX 0x0A4 0x30C 0x4F4 0x4 0x5
167+#define MX8MN_IOMUXC_SD1_CMD_UART1_DTE_TX 0x0A4 0x30C 0x000 0x4 0x0
168+#define MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
169+#define MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
170+#define MX8MN_IOMUXC_SD1_DATA0_ENET1_RGMII_TD1 0x0A8 0x310 0x000 0x1 0x0
171+#define MX8MN_IOMUXC_SD1_DATA0_UART1_DCE_RTS_B 0x0A8 0x310 0x4F0 0x4 0x4
172+#define MX8MN_IOMUXC_SD1_DATA0_UART1_DTE_CTS_B 0x0A8 0x310 0x000 0x4 0x0
173+#define MX8MN_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0
174+#define MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
175+#define MX8MN_IOMUXC_SD1_DATA1_ENET1_RGMII_TD0 0x0AC 0x314 0x000 0x1 0x0
176+#define MX8MN_IOMUXC_SD1_DATA1_UART1_DCE_CTS_B 0x0AC 0x314 0x000 0x4 0x0
177+#define MX8MN_IOMUXC_SD1_DATA1_UART1_DTE_RTS_B 0x0AC 0x314 0x4F0 0x4 0x5
178+#define MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
179+#define MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
180+#define MX8MN_IOMUXC_SD1_DATA2_ENET1_RGMII_RD0 0x0B0 0x318 0x57C 0x1 0x1
181+#define MX8MN_IOMUXC_SD1_DATA2_UART2_DCE_TX 0x0B0 0x318 0x000 0x4 0x0
182+#define MX8MN_IOMUXC_SD1_DATA2_UART2_DTE_RX 0x0B0 0x318 0x4FC 0x4 0x4
183+#define MX8MN_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0
184+#define MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0
185+#define MX8MN_IOMUXC_SD1_DATA3_ENET1_RGMII_RD1 0x0B4 0x31C 0x554 0x1 0x1
186+#define MX8MN_IOMUXC_SD1_DATA3_UART2_DCE_RX 0x0B4 0x31C 0x4FC 0x4 0x5
187+#define MX8MN_IOMUXC_SD1_DATA3_UART2_DTE_TX 0x0B4 0x31C 0x000 0x4 0x0
188+#define MX8MN_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0
189+#define MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0
190+#define MX8MN_IOMUXC_SD1_DATA4_ENET1_RGMII_TX_CTL 0x0B8 0x320 0x000 0x1 0x0
191+#define MX8MN_IOMUXC_SD1_DATA4_I2C1_SCL 0x0B8 0x320 0x55C 0x3 0x1
192+#define MX8MN_IOMUXC_SD1_DATA4_UART2_DCE_RTS_B 0x0B8 0x320 0x4F8 0x4 0x4
193+#define MX8MN_IOMUXC_SD1_DATA4_UART2_DTE_CTS_B 0x0B8 0x320 0x000 0x4 0x0
194+#define MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0
195+#define MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0
196+#define MX8MN_IOMUXC_SD1_DATA5_ENET1_TX_ER 0x0BC 0x324 0x000 0x1 0x0
197+#define MX8MN_IOMUXC_SD1_DATA5_I2C1_SDA 0x0BC 0x324 0x56C 0x3 0x1
198+#define MX8MN_IOMUXC_SD1_DATA5_UART2_DCE_CTS_B 0x0BC 0x324 0x000 0x4 0x0
199+#define MX8MN_IOMUXC_SD1_DATA5_UART2_DTE_RTS_B 0x0BC 0x324 0x4F8 0x4 0x5
200+#define MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0
201+#define MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0
202+#define MX8MN_IOMUXC_SD1_DATA6_ENET1_RGMII_RX_CTL 0x0C0 0x328 0x574 0x1 0x1
203+#define MX8MN_IOMUXC_SD1_DATA6_I2C2_SCL 0x0C0 0x328 0x5D0 0x3 0x1
204+#define MX8MN_IOMUXC_SD1_DATA6_UART3_DCE_TX 0x0C0 0x328 0x000 0x4 0x0
205+#define MX8MN_IOMUXC_SD1_DATA6_UART3_DTE_RX 0x0C0 0x328 0x504 0x4 0x4
206+#define MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0
207+#define MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0
208+#define MX8MN_IOMUXC_SD1_DATA7_ENET1_RX_ER 0x0C4 0x32C 0x5C8 0x1 0x1
209+#define MX8MN_IOMUXC_SD1_DATA7_I2C2_SDA 0x0C4 0x32C 0x560 0x3 0x1
210+#define MX8MN_IOMUXC_SD1_DATA7_UART3_DCE_RX 0x0C4 0x32C 0x504 0x4 0x5
211+#define MX8MN_IOMUXC_SD1_DATA7_UART3_DTE_TX 0x0C4 0x32C 0x000 0x4 0x0
212+#define MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0
213+#define MX8MN_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0
214+#define MX8MN_IOMUXC_SD1_RESET_B_ENET1_TX_CLK 0x0C8 0x330 0x5A4 0x1 0x1
215+#define MX8MN_IOMUXC_SD1_RESET_B_CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x0C8 0x330 0x5A4 0x1 0x0
216+#define MX8MN_IOMUXC_SD1_RESET_B_I2C3_SCL 0x0C8 0x330 0x588 0x3 0x1
217+#define MX8MN_IOMUXC_SD1_RESET_B_UART3_DCE_RTS_B 0x0C8 0x330 0x500 0x4 0x2
218+#define MX8MN_IOMUXC_SD1_RESET_B_UART3_DTE_CTS_B 0x0C8 0x330 0x000 0x4 0x0
219+#define MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0
220+#define MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0
221+#define MX8MN_IOMUXC_SD1_STROBE_I2C3_SDA 0x0CC 0x334 0x5BC 0x3 0x1
222+#define MX8MN_IOMUXC_SD1_STROBE_UART3_DCE_CTS_B 0x0CC 0x334 0x000 0x4 0x0
223+#define MX8MN_IOMUXC_SD1_STROBE_UART3_DTE_RTS_B 0x0CC 0x334 0x500 0x4 0x3
224+#define MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0
225+#define MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0
226+#define MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0
227+#define MX8MN_IOMUXC_SD2_CD_B_CCMSRCGPCMIX_TESTER_ACK 0x0D0 0x338 0x000 0x6 0x0
228+#define MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0
229+#define MX8MN_IOMUXC_SD2_CLK_SAI5_RX_SYNC 0x0D4 0x33C 0x4E4 0x1 0x1
230+#define MX8MN_IOMUXC_SD2_CLK_ECSPI2_SCLK 0x0D4 0x33C 0x580 0x2 0x1
231+#define MX8MN_IOMUXC_SD2_CLK_UART4_DCE_RX 0x0D4 0x33C 0x50C 0x3 0x4
232+#define MX8MN_IOMUXC_SD2_CLK_UART4_DTE_TX 0x0D4 0x33C 0x000 0x3 0x0
233+#define MX8MN_IOMUXC_SD2_CLK_SAI5_MCLK 0x0D4 0x33C 0x594 0x4 0x1
234+#define MX8MN_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0
235+#define MX8MN_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0
236+#define MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0
237+#define MX8MN_IOMUXC_SD2_CMD_SAI5_RX_BCLK 0x0D8 0x340 0x4D0 0x1 0x1
238+#define MX8MN_IOMUXC_SD2_CMD_ECSPI2_MOSI 0x0D8 0x340 0x590 0x2 0x1
239+#define MX8MN_IOMUXC_SD2_CMD_UART4_DCE_TX 0x0D8 0x340 0x000 0x3 0x0
240+#define MX8MN_IOMUXC_SD2_CMD_UART4_DTE_RX 0x0D8 0x340 0x50C 0x3 0x5
241+#define MX8MN_IOMUXC_SD2_CMD_PDM_CLK 0x0D8 0x340 0x000 0x4 0x0
242+#define MX8MN_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0
243+#define MX8MN_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0
244+#define MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0
245+#define MX8MN_IOMUXC_SD2_DATA0_SAI5_RX_DATA0 0x0DC 0x344 0x4D4 0x1 0x1
246+#define MX8MN_IOMUXC_SD2_DATA0_I2C4_SDA 0x0DC 0x344 0x58C 0x2 0x1
247+#define MX8MN_IOMUXC_SD2_DATA0_UART2_DCE_RX 0x0DC 0x344 0x4FC 0x3 0x6
248+#define MX8MN_IOMUXC_SD2_DATA0_UART2_DTE_TX 0x0DC 0x344 0x000 0x3 0x0
249+#define MX8MN_IOMUXC_SD2_DATA0_PDM_BIT_STREAM0 0x0DC 0x344 0x534 0x4 0x2
250+#define MX8MN_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0
251+#define MX8MN_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0
252+#define MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0
253+#define MX8MN_IOMUXC_SD2_DATA1_SAI5_TX_SYNC 0x0E0 0x348 0x4EC 0x1 0x1
254+#define MX8MN_IOMUXC_SD2_DATA1_I2C4_SCL 0x0E0 0x348 0x5D4 0x2 0x1
255+#define MX8MN_IOMUXC_SD2_DATA1_UART2_DCE_TX 0x0E0 0x348 0x000 0x3 0x0
256+#define MX8MN_IOMUXC_SD2_DATA1_UART2_DTE_RX 0x0E0 0x348 0x4FC 0x3 0x7
257+#define MX8MN_IOMUXC_SD2_DATA1_PDM_BIT_STREAM1 0x0E0 0x348 0x538 0x4 0x4
258+#define MX8MN_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0
259+#define MX8MN_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0
260+#define MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0
261+#define MX8MN_IOMUXC_SD2_DATA2_SAI5_TX_BCLK 0x0E4 0x34C 0x4E8 0x1 0x1
262+#define MX8MN_IOMUXC_SD2_DATA2_ECSPI2_SS0 0x0E4 0x34C 0x570 0x2 0x2
263+#define MX8MN_IOMUXC_SD2_DATA2_SPDIF1_OUT 0x0E4 0x34C 0x000 0x3 0x0
264+#define MX8MN_IOMUXC_SD2_DATA2_PDM_BIT_STREAM2 0x0E4 0x34C 0x53C 0x4 0x4
265+#define MX8MN_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0
266+#define MX8MN_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0
267+#define MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0
268+#define MX8MN_IOMUXC_SD2_DATA3_SAI5_TX_DATA0 0x0E8 0x350 0x000 0x1 0x0
269+#define MX8MN_IOMUXC_SD2_DATA3_ECSPI2_MISO 0x0E8 0x350 0x578 0x2 0x1
270+#define MX8MN_IOMUXC_SD2_DATA3_SPDIF1_IN 0x0E8 0x350 0x5CC 0x3 0x2
271+#define MX8MN_IOMUXC_SD2_DATA3_PDM_BIT_STREAM3 0x0E8 0x350 0x540 0x4 0x4
272+#define MX8MN_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0
273+#define MX8MN_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0
274+#define MX8MN_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0
275+#define MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0
276+#define MX8MN_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0
277+#define MX8MN_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0
278+#define MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0
279+#define MX8MN_IOMUXC_SD2_WP_CORESIGHT_EVENTI 0x0F0 0x358 0x000 0x6 0x0
280+#define MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0
281+#define MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0
282+#define MX8MN_IOMUXC_NAND_ALE_PDM_BIT_STREAM0 0x0F4 0x35C 0x534 0x3 0x3
283+#define MX8MN_IOMUXC_NAND_ALE_UART3_DCE_RX 0x0F4 0x35C 0x504 0x4 0x6
284+#define MX8MN_IOMUXC_NAND_ALE_UART3_DTE_TX 0x0F4 0x35C 0x000 0x4 0x0
285+#define MX8MN_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0
286+#define MX8MN_IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK 0x0F4 0x35C 0x000 0x6 0x0
287+#define MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0
288+#define MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0
289+#define MX8MN_IOMUXC_NAND_CE0_B_PDM_BIT_STREAM1 0x0F8 0x360 0x538 0x3 0x5
290+#define MX8MN_IOMUXC_NAND_CE0_B_UART3_DCE_TX 0x0F8 0x360 0x000 0x4 0x0
291+#define MX8MN_IOMUXC_NAND_CE0_B_UART3_DTE_RX 0x0F8 0x360 0x504 0x4 0x7
292+#define MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0
293+#define MX8MN_IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL 0x0F8 0x360 0x000 0x6 0x0
294+#define MX8MN_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0
295+#define MX8MN_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0
296+#define MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x0FC 0x364 0x59C 0x2 0x0
297+#define MX8MN_IOMUXC_NAND_CE1_B_PDM_BIT_STREAM0 0x0FC 0x364 0x534 0x3 0x4
298+#define MX8MN_IOMUXC_NAND_CE1_B_I2C4_SCL 0x0FC 0x364 0x5D4 0x4 0x2
299+#define MX8MN_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0
300+#define MX8MN_IOMUXC_NAND_CE1_B_CORESIGHT_TRACE0 0x0FC 0x364 0x000 0x6 0x0
301+#define MX8MN_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0
302+#define MX8MN_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0
303+#define MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x100 0x368 0x550 0x2 0x0
304+#define MX8MN_IOMUXC_NAND_CE2_B_PDM_BIT_STREAM1 0x100 0x368 0x538 0x3 0x6
305+#define MX8MN_IOMUXC_NAND_CE2_B_I2C4_SDA 0x100 0x368 0x58C 0x4 0x2
306+#define MX8MN_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0
307+#define MX8MN_IOMUXC_NAND_CE2_B_CORESIGHT_TRACE1 0x100 0x368 0x000 0x6 0x0
308+#define MX8MN_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0
309+#define MX8MN_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0
310+#define MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x104 0x36C 0x584 0x2 0x0
311+#define MX8MN_IOMUXC_NAND_CE3_B_PDM_BIT_STREAM2 0x104 0x36C 0x53C 0x3 0x5
312+#define MX8MN_IOMUXC_NAND_CE3_B_I2C3_SDA 0x104 0x36C 0x5BC 0x4 0x2
313+#define MX8MN_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0
314+#define MX8MN_IOMUXC_NAND_CE3_B_CORESIGHT_TRACE2 0x104 0x36C 0x000 0x6 0x0
315+#define MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0
316+#define MX8MN_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0
317+#define MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x108 0x370 0x54C 0x2 0x0
318+#define MX8MN_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0
319+#define MX8MN_IOMUXC_NAND_CLE_CORESIGHT_TRACE3 0x108 0x370 0x000 0x6 0x0
320+#define MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0
321+#define MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0
322+#define MX8MN_IOMUXC_NAND_DATA00_PDM_BIT_STREAM2 0x10C 0x374 0x53C 0x3 0x6
323+#define MX8MN_IOMUXC_NAND_DATA00_UART4_DCE_RX 0x10C 0x374 0x50C 0x4 0x6
324+#define MX8MN_IOMUXC_NAND_DATA00_UART4_DTE_TX 0x10C 0x374 0x000 0x4 0x0
325+#define MX8MN_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0
326+#define MX8MN_IOMUXC_NAND_DATA00_CORESIGHT_TRACE4 0x10C 0x374 0x000 0x6 0x0
327+#define MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0
328+#define MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0
329+#define MX8MN_IOMUXC_NAND_DATA01_PDM_BIT_STREAM3 0x110 0x378 0x540 0x3 0x5
330+#define MX8MN_IOMUXC_NAND_DATA01_UART4_DCE_TX 0x110 0x378 0x000 0x4 0x0
331+#define MX8MN_IOMUXC_NAND_DATA01_UART4_DTE_RX 0x110 0x378 0x50C 0x4 0x7
332+#define MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0
333+#define MX8MN_IOMUXC_NAND_DATA01_CORESIGHT_TRACE5 0x110 0x378 0x000 0x6 0x0
334+#define MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0
335+#define MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0
336+#define MX8MN_IOMUXC_NAND_DATA02_USDHC3_CD_B 0x114 0x37C 0x598 0x2 0x0
337+#define MX8MN_IOMUXC_NAND_DATA02_I2C4_SDA 0x114 0x37C 0x58C 0x4 0x3
338+#define MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0
339+#define MX8MN_IOMUXC_NAND_DATA02_CORESIGHT_TRACE6 0x114 0x37C 0x000 0x6 0x0
340+#define MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0
341+#define MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0
342+#define MX8MN_IOMUXC_NAND_DATA03_USDHC3_WP 0x118 0x380 0x5B8 0x2 0x0
343+#define MX8MN_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0
344+#define MX8MN_IOMUXC_NAND_DATA03_CORESIGHT_TRACE7 0x118 0x380 0x000 0x6 0x0
345+#define MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0
346+#define MX8MN_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0
347+#define MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x11C 0x384 0x5B4 0x2 0x0
348+#define MX8MN_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0
349+#define MX8MN_IOMUXC_NAND_DATA04_CORESIGHT_TRACE8 0x11C 0x384 0x000 0x6 0x0
350+#define MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0
351+#define MX8MN_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0
352+#define MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x120 0x388 0x5B0 0x2 0x0
353+#define MX8MN_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0
354+#define MX8MN_IOMUXC_NAND_DATA05_CORESIGHT_TRACE9 0x120 0x388 0x000 0x6 0x0
355+#define MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0
356+#define MX8MN_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0
357+#define MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x124 0x38C 0x5E4 0x2 0x0
358+#define MX8MN_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0
359+#define MX8MN_IOMUXC_NAND_DATA06_CORESIGHT_TRACE10 0x124 0x38C 0x000 0x6 0x0
360+#define MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0
361+#define MX8MN_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0
362+#define MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x128 0x390 0x5E0 0x2 0x0
363+#define MX8MN_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0
364+#define MX8MN_IOMUXC_NAND_DATA07_CORESIGHT_TRACE11 0x128 0x390 0x000 0x6 0x0
365+#define MX8MN_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0
366+#define MX8MN_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0
367+#define MX8MN_IOMUXC_NAND_DQS_PDM_CLK 0x12C 0x394 0x000 0x3 0x0
368+#define MX8MN_IOMUXC_NAND_DQS_I2C3_SCL 0x12C 0x394 0x588 0x4 0x2
369+#define MX8MN_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0
370+#define MX8MN_IOMUXC_NAND_DQS_CORESIGHT_TRACE12 0x12C 0x394 0x000 0x6 0x0
371+#define MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0
372+#define MX8MN_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0
373+#define MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x130 0x398 0x558 0x2 0x0
374+#define MX8MN_IOMUXC_NAND_RE_B_PDM_BIT_STREAM1 0x130 0x398 0x538 0x3 0x7
375+#define MX8MN_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0
376+#define MX8MN_IOMUXC_NAND_RE_B_CORESIGHT_TRACE13 0x130 0x398 0x000 0x6 0x0
377+#define MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0
378+#define MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x134 0x39C 0x000 0x2 0x0
379+#define MX8MN_IOMUXC_NAND_READY_B_PDM_BIT_STREAM3 0x134 0x39C 0x540 0x3 0x6
380+#define MX8MN_IOMUXC_NAND_READY_B_I2C3_SCL 0x134 0x39C 0x588 0x4 0x3
381+#define MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0
382+#define MX8MN_IOMUXC_NAND_READY_B_CORESIGHT_TRACE14 0x134 0x39C 0x000 0x6 0x0
383+#define MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0
384+#define MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x138 0x3A0 0x5A0 0x2 0x0
385+#define MX8MN_IOMUXC_NAND_WE_B_I2C3_SDA 0x138 0x3A0 0x5BC 0x4 0x3
386+#define MX8MN_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0
387+#define MX8MN_IOMUXC_NAND_WE_B_CORESIGHT_TRACE15 0x138 0x3A0 0x000 0x6 0x0
388+#define MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0
389+#define MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x13C 0x3A4 0x5DC 0x2 0x0
390+#define MX8MN_IOMUXC_NAND_WP_B_I2C4_SDA 0x13C 0x3A4 0x58C 0x4 0x4
391+#define MX8MN_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0
392+#define MX8MN_IOMUXC_NAND_WP_B_CORESIGHT_EVENTO 0x13C 0x3A4 0x000 0x6 0x0
393+#define MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0
394+#define MX8MN_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0
395+#define MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0
396+#define MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0x144 0x3AC 0x000 0x4 0x0
397+#define MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0
398+#define MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0
399+#define MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x148 0x3B0 0x534 0x4 0x0
400+#define MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0
401+#define MX8MN_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0
402+#define MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0
403+#define MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x14C 0x3B4 0x538 0x4 0x0
404+#define MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0
405+#define MX8MN_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0
406+#define MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0
407+#define MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x150 0x3B8 0x53C 0x4 0x0
408+#define MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0
409+#define MX8MN_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0
410+#define MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0
411+#define MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x154 0x3BC 0x540 0x4 0x0
412+#define MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0
413+#define MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x594 0x0 0x0
414+#define MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0
415+#define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0
416+#define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2
417+#define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x1B0 0x418 0x000 0x2 0x0
418+#define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x1B0 0x418 0x5AC 0x3 0x0
419+#define MX8MN_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1B0 0x418 0x000 0x4 0x0
420+#define MX8MN_IOMUXC_SAI2_RXFS_UART1_DTE_RX 0x1B0 0x418 0x4F4 0x4 0x2
421+#define MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0
422+#define MX8MN_IOMUXC_SAI2_RXFS_PDM_BIT_STREAM2 0x1B0 0x418 0x53C 0x6 0x7
423+#define MX8MN_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0
424+#define MX8MN_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2
425+#define MX8MN_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1B4 0x41C 0x4F4 0x4 0x3
426+#define MX8MN_IOMUXC_SAI2_RXC_UART1_DTE_TX 0x1B4 0x41C 0x000 0x4 0x0
427+#define MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0
428+#define MX8MN_IOMUXC_SAI2_RXC_PDM_BIT_STREAM1 0x1B4 0x41C 0x538 0x6 0x8
429+#define MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0
430+#define MX8MN_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0
431+#define MX8MN_IOMUXC_SAI2_RXD0_SAI2_TX_DATA1 0x1B8 0x420 0x000 0x3 0x0
432+#define MX8MN_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x1B8 0x420 0x4F0 0x4 0x2
433+#define MX8MN_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B 0x1B8 0x420 0x000 0x4 0x0
434+#define MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0
435+#define MX8MN_IOMUXC_SAI2_RXD0_PDM_BIT_STREAM3 0x1B8 0x420 0x540 0x6 0x7
436+#define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0
437+#define MX8MN_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0
438+#define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x1BC 0x424 0x000 0x3 0x0
439+#define MX8MN_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x1BC 0x424 0x000 0x4 0x0
440+#define MX8MN_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B 0x1BC 0x424 0x4F0 0x4 0x3
441+#define MX8MN_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0
442+#define MX8MN_IOMUXC_SAI2_TXFS_PDM_BIT_STREAM2 0x1BC 0x424 0x53C 0x6 0x8
443+#define MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0
444+#define MX8MN_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0
445+#define MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0
446+#define MX8MN_IOMUXC_SAI2_TXC_PDM_BIT_STREAM1 0x1C0 0x428 0x538 0x6 0x9
447+#define MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0
448+#define MX8MN_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0
449+#define MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0
450+#define MX8MN_IOMUXC_SAI2_TXD0_CCMSRCGPCMIX_BOOT_MODE4 0x1C4 0x42C 0x540 0x6 0x8
451+#define MX8MN_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0
452+#define MX8MN_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x594 0x1 0x2
453+#define MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0
454+#define MX8MN_IOMUXC_SAI2_MCLK_SAI3_MCLK 0x1C8 0x430 0x5C0 0x6 0x1
455+#define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0
456+#define MX8MN_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x5F0 0x1 0x0
457+#define MX8MN_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2
458+#define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x1CC 0x434 0x000 0x3 0x0
459+#define MX8MN_IOMUXC_SAI3_RXFS_SPDIF1_IN 0x1CC 0x434 0x5CC 0x4 0x3
460+#define MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0
461+#define MX8MN_IOMUXC_SAI3_RXFS_PDM_BIT_STREAM0 0x1CC 0x434 0x534 0x6 0x5
462+#define MX8MN_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0
463+#define MX8MN_IOMUXC_SAI3_RXC_GPT1_CLK 0x1D0 0x438 0x5E8 0x1 0x0
464+#define MX8MN_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2
465+#define MX8MN_IOMUXC_SAI3_RXC_SAI2_RX_DATA1 0x1D0 0x438 0x5AC 0x3 0x2
466+#define MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1D0 0x438 0x000 0x4 0x0
467+#define MX8MN_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x1D0 0x438 0x4F8 0x4 0x2
468+#define MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0
469+#define MX8MN_IOMUXC_SAI3_RXC_PDM_CLK 0x1D0 0x438 0x000 0x6 0x0
470+#define MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0
471+#define MX8MN_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0
472+#define MX8MN_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2
473+#define MX8MN_IOMUXC_SAI3_RXD_SAI3_TX_DATA1 0x1D4 0x43C 0x000 0x3 0x0
474+#define MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1D4 0x43C 0x4F8 0x4 0x3
475+#define MX8MN_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x1D4 0x43C 0x000 0x4 0x0
476+#define MX8MN_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0
477+#define MX8MN_IOMUXC_SAI3_RXD_PDM_BIT_STREAM1 0x1D4 0x43C 0x538 0x6 0x10
478+#define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
479+#define MX8MN_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x5EC 0x1 0x0
480+#define MX8MN_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x1
481+#define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x1D8 0x440 0x000 0x3 0x0
482+#define MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4FC 0x4 0x2
483+#define MX8MN_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x1D8 0x440 0x000 0x4 0x0
484+#define MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
485+#define MX8MN_IOMUXC_SAI3_TXFS_PDM_BIT_STREAM3 0x1D8 0x440 0x540 0x6 0x9
486+#define MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0
487+#define MX8MN_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0
488+#define MX8MN_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x1
489+#define MX8MN_IOMUXC_SAI3_TXC_SAI2_TX_DATA1 0x1DC 0x444 0x000 0x3 0x0
490+#define MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1DC 0x444 0x000 0x4 0x0
491+#define MX8MN_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4FC 0x4 0x3
492+#define MX8MN_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0
493+#define MX8MN_IOMUXC_SAI3_TXC_PDM_BIT_STREAM2 0x1DC 0x444 0x53C 0x6 0x9
494+#define MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0
495+#define MX8MN_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0
496+#define MX8MN_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x1
497+#define MX8MN_IOMUXC_SAI3_TXD_SPDIF1_EXT_CLK 0x1E0 0x448 0x568 0x4 0x2
498+#define MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0
499+#define MX8MN_IOMUXC_SAI3_TXD_CCMSRCGPCMIX_BOOT_MODE5 0x1E0 0x448 0x000 0x6 0x0
500+#define MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x5C0 0x0 0x0
501+#define MX8MN_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0
502+#define MX8MN_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x594 0x2 0x3
503+#define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_OUT 0x1E4 0x44C 0x000 0x4 0x0
504+#define MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0
505+#define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_IN 0x1E4 0x44C 0x5CC 0x6 0x4
506+#define MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0
507+#define MX8MN_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0
508+#define MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0
509+#define MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x5CC 0x0 0x0
510+#define MX8MN_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0
511+#define MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0
512+#define MX8MN_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x568 0x0 0x0
513+#define MX8MN_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0
514+#define MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0
515+#define MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x5D8 0x0 0x0
516+#define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0
517+#define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0
518+#define MX8MN_IOMUXC_ECSPI1_SCLK_I2C1_SCL 0x1F4 0x45C 0x55C 0x2 0x2
519+#define MX8MN_IOMUXC_ECSPI1_SCLK_SAI5_RX_SYNC 0x1F4 0x45C 0x4DC 0x3 0x2
520+#define MX8MN_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0
521+#define MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x5A8 0x0 0x0
522+#define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0
523+#define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1
524+#define MX8MN_IOMUXC_ECSPI1_MOSI_I2C1_SDA 0x1F8 0x460 0x56C 0x2 0x2
525+#define MX8MN_IOMUXC_ECSPI1_MOSI_SAI5_RX_BCLK 0x1F8 0x460 0x4D0 0x3 0x3
526+#define MX8MN_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0
527+#define MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x5C4 0x0 0x0
528+#define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0
529+#define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0
530+#define MX8MN_IOMUXC_ECSPI1_MISO_I2C2_SCL 0x1FC 0x464 0x5D0 0x2 0x2
531+#define MX8MN_IOMUXC_ECSPI1_MISO_SAI5_RX_DATA0 0x1FC 0x464 0x4D4 0x3 0x3
532+#define MX8MN_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0
533+#define MX8MN_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x564 0x0 0x0
534+#define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1
535+#define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0
536+#define MX8MN_IOMUXC_ECSPI1_SS0_I2C2_SDA 0x200 0x468 0x560 0x2 0x2
537+#define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_RX_DATA1 0x200 0x468 0x4D8 0x3 0x2
538+#define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_TX_SYNC 0x200 0x468 0x4EC 0x4 0x3
539+#define MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0
540+#define MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x580 0x0 0x0
541+#define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0
542+#define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0
543+#define MX8MN_IOMUXC_ECSPI2_SCLK_I2C3_SCL 0x204 0x46C 0x588 0x2 0x4
544+#define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_RX_DATA2 0x204 0x46C 0x000 0x3 0x0
545+#define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_TX_BCLK 0x204 0x46C 0x4E8 0x4 0x3
546+#define MX8MN_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0
547+#define MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x590 0x0 0x0
548+#define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0
549+#define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1
550+#define MX8MN_IOMUXC_ECSPI2_MOSI_I2C3_SDA 0x208 0x470 0x5BC 0x2 0x4
551+#define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_RX_DATA3 0x208 0x470 0x4E0 0x3 0x2
552+#define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_TX_DATA0 0x208 0x470 0x000 0x4 0x0
553+#define MX8MN_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0
554+#define MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x578 0x0 0x0
555+#define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0
556+#define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0
557+#define MX8MN_IOMUXC_ECSPI2_MISO_I2C4_SCL 0x20C 0x474 0x5D4 0x2 0x3
558+#define MX8MN_IOMUXC_ECSPI2_MISO_SAI5_MCLK 0x20C 0x474 0x594 0x3 0x4
559+#define MX8MN_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0
560+#define MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x570 0x0 0x0
561+#define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1
562+#define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0
563+#define MX8MN_IOMUXC_ECSPI2_SS0_I2C4_SDA 0x210 0x478 0x58C 0x2 0x5
564+#define MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0
565+#define MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x55C 0x0 0x0
566+#define MX8MN_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0
567+#define MX8MN_IOMUXC_I2C1_SCL_ECSPI1_SCLK 0x214 0x47C 0x5D8 0x3 0x1
568+#define MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0
569+#define MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x56C 0x0 0x0
570+#define MX8MN_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2
571+#define MX8MN_IOMUXC_I2C1_SDA_ECSPI1_MOSI 0x218 0x480 0x5A8 0x3 0x1
572+#define MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0
573+#define MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x5D0 0x0 0x0
574+#define MX8MN_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0
575+#define MX8MN_IOMUXC_I2C2_SCL_USDHC3_CD_B 0x21C 0x484 0x598 0x2 0x1
576+#define MX8MN_IOMUXC_I2C2_SCL_ECSPI1_MISO 0x21C 0x484 0x5C4 0x3 0x1
577+#define MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0
578+#define MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x560 0x0 0x0
579+#define MX8MN_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0
580+#define MX8MN_IOMUXC_I2C2_SDA_USDHC3_WP 0x220 0x488 0x5B8 0x2 0x1
581+#define MX8MN_IOMUXC_I2C2_SDA_ECSPI1_SS0 0x220 0x488 0x564 0x3 0x1
582+#define MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0
583+#define MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x588 0x0 0x0
584+#define MX8MN_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0
585+#define MX8MN_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0
586+#define MX8MN_IOMUXC_I2C3_SCL_ECSPI2_SCLK 0x224 0x48C 0x580 0x3 0x2
587+#define MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0
588+#define MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x5BC 0x0 0x0
589+#define MX8MN_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0
590+#define MX8MN_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0
591+#define MX8MN_IOMUXC_I2C3_SDA_ECSPI2_MOSI 0x228 0x490 0x590 0x3 0x2
592+#define MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0
593+#define MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x5D4 0x0 0x0
594+#define MX8MN_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0
595+#define MX8MN_IOMUXC_I2C4_SCL_ECSPI2_MISO 0x22C 0x494 0x578 0x3 0x2
596+#define MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0
597+#define MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x58C 0x0 0x0
598+#define MX8MN_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0
599+#define MX8MN_IOMUXC_I2C4_SDA_ECSPI2_SS0 0x230 0x498 0x570 0x3 0x1
600+#define MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0
601+#define MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0
602+#define MX8MN_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0
603+#define MX8MN_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0
604+#define MX8MN_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0
605+#define MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0
606+#define MX8MN_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x1
607+#define MX8MN_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0
608+#define MX8MN_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0
609+#define MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0
610+#define MX8MN_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0
611+#define MX8MN_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0
612+#define MX8MN_IOMUXC_UART2_RXD_GPT1_COMPARE3 0x23C 0x4A4 0x000 0x3 0x0
613+#define MX8MN_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0
614+#define MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0
615+#define MX8MN_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1
616+#define MX8MN_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0
617+#define MX8MN_IOMUXC_UART2_TXD_GPT1_COMPARE2 0x240 0x4A8 0x000 0x3 0x0
618+#define MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0
619+#define MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2
620+#define MX8MN_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0
621+#define MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0
622+#define MX8MN_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0
623+#define MX8MN_IOMUXC_UART3_RXD_USDHC3_RESET_B 0x244 0x4AC 0x000 0x2 0x0
624+#define MX8MN_IOMUXC_UART3_RXD_GPT1_CAPTURE2 0x244 0x4AC 0x5EC 0x3 0x1
625+#define MX8MN_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0
626+#define MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0
627+#define MX8MN_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3
628+#define MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1
629+#define MX8MN_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0
630+#define MX8MN_IOMUXC_UART3_TXD_USDHC3_VSELECT 0x248 0x4B0 0x000 0x2 0x0
631+#define MX8MN_IOMUXC_UART3_TXD_GPT1_CLK 0x248 0x4B0 0x5E8 0x3 0x1
632+#define MX8MN_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0
633+#define MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2
634+#define MX8MN_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0
635+#define MX8MN_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0
636+#define MX8MN_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0
637+#define MX8MN_IOMUXC_UART4_RXD_GPT1_COMPARE1 0x24C 0x4B4 0x000 0x3 0x0
638+#define MX8MN_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0
639+#define MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0
640+#define MX8MN_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3
641+#define MX8MN_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1
642+#define MX8MN_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0
643+#define MX8MN_IOMUXC_UART4_TXD_GPT1_CAPTURE1 0x250 0x4B8 0x5F0 0x3 0x1
644+#define MX8MN_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0
645+
646+#endif /* __DTS_IMX8MN_PINFUNC_H */
drivers/pinctrl/aspeed/Makefile+1−1
@@ -2,6 +2,6 @@ · 1 unmodified line
22 # Aspeed pinctrl support
33
44 ccflags-y += $(call cc-option,-Woverride-init)
5−obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o
5+obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o pinmux-aspeed.o
66 obj-$(CONFIG_PINCTRL_ASPEED_G4) += pinctrl-aspeed-g4.o
77 obj-$(CONFIG_PINCTRL_ASPEED_G5) += pinctrl-aspeed-g5.o
drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c+90−4
@@ -18,8 +18,34 @@ · 17 unmodified lines
1818
1919 #include "../core.h"
2020 #include "../pinctrl-utils.h"
21+#include "pinmux-aspeed.h"
2122 #include "pinctrl-aspeed.h"
2223
24+/*
25+ * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
26+ * references registers by the device/offset mnemonic. The register macros
27+ * below are named the same way to ease transcription and verification (as
28+ * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
29+ * reference registers beyond those dedicated to pinmux, such as the system
30+ * reset control and MAC clock configuration registers.
31+ */
32+#define SCU2C 0x2C /* Misc. Control Register */
33+#define SCU3C 0x3C /* System Reset Control/Status Register */
34+#define SCU48 0x48 /* MAC Interface Clock Delay Setting */
35+#define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */
36+#define HW_REVISION_ID 0x7C /* Silicon revision ID register */
37+#define SCU80 0x80 /* Multi-function Pin Control #1 */
38+#define SCU84 0x84 /* Multi-function Pin Control #2 */
39+#define SCU88 0x88 /* Multi-function Pin Control #3 */
40+#define SCU8C 0x8C /* Multi-function Pin Control #4 */
41+#define SCU90 0x90 /* Multi-function Pin Control #5 */
42+#define SCU94 0x94 /* Multi-function Pin Control #6 */
43+#define SCUA0 0xA0 /* Multi-function Pin Control #7 */
44+#define SCUA4 0xA4 /* Multi-function Pin Control #8 */
45+#define SCUA8 0xA8 /* Multi-function Pin Control #9 */
46+#define SCUAC 0xAC /* Multi-function Pin Control #10 */
47+#define HW_STRAP2 0xD0 /* Strapping */
48+
2349 /*
2450 * Uses undefined macros for symbol naming and references, eg GPIOA0, MAC1LINK,
2551 * TIMER3 etc.
@@ -2386,13 +2412,73 @@ static const struct aspeed_pin_config aspeed_g4_configs[] = { · 2360 unmodified lines
23862412 { PIN_CONFIG_INPUT_DEBOUNCE, { C14, B14 }, SCUA8, 27 },
23872413 };
23882414
2415+static int aspeed_g4_sig_expr_set(const struct aspeed_pinmux_data *ctx,
2416+ const struct aspeed_sig_expr *expr,
2417+ bool enable)
2418+{
2419+ int ret;
2420+ int i;
2421+
2422+ for (i = 0; i < expr->ndescs; i++) {
2423+ const struct aspeed_sig_desc *desc = &expr->descs[i];
2424+ u32 pattern = enable ? desc->enable : desc->disable;
2425+ u32 val = (pattern << __ffs(desc->mask));
2426+
2427+ if (!ctx->maps[desc->ip])
2428+ return -ENODEV;
2429+
2430+ /*
2431+ * Strap registers are configured in hardware or by early-boot
2432+ * firmware. Treat them as read-only despite that we can write
2433+ * them. This may mean that certain functions cannot be
2434+ * deconfigured and is the reason we re-evaluate after writing
2435+ * all descriptor bits.
2436+ *
2437+ * Port D and port E GPIO loopback modes are the only exception
2438+ * as those are commonly used with front-panel buttons to allow
2439+ * normal operation of the host when the BMC is powered off or
2440+ * fails to boot. Once the BMC has booted, the loopback mode
2441+ * must be disabled for the BMC to control host power-on and
2442+ * reset.
2443+ */
2444+ if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 &&
2445+ !(desc->mask & (BIT(21) | BIT(22))))
2446+ continue;
2447+
2448+ if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2)
2449+ continue;
2450+
2451+ ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg,
2452+ desc->mask, val);
2453+
2454+ if (ret)
2455+ return ret;
2456+ }
2457+
2458+ ret = aspeed_sig_expr_eval(ctx, expr, enable);
2459+ if (ret < 0)
2460+ return ret;
2461+
2462+ if (!ret)
2463+ return -EPERM;
2464+
2465+ return 0;
2466+}
2467+
2468+static const struct aspeed_pinmux_ops aspeed_g4_ops = {
2469+ .set = aspeed_g4_sig_expr_set,
2470+};
2471+
23892472 static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = {
23902473 .pins = aspeed_g4_pins,
23912474 .npins = ARRAY_SIZE(aspeed_g4_pins),
2392− .groups = aspeed_g4_groups,
2393− .ngroups = ARRAY_SIZE(aspeed_g4_groups),
2394− .functions = aspeed_g4_functions,
2395− .nfunctions = ARRAY_SIZE(aspeed_g4_functions),
2475+ .pinmux = {
2476+ .ops = &aspeed_g4_ops,
2477+ .groups = aspeed_g4_groups,
2478+ .ngroups = ARRAY_SIZE(aspeed_g4_groups),
2479+ .functions = aspeed_g4_functions,
2480+ .nfunctions = ARRAY_SIZE(aspeed_g4_functions),
2481+ },
23962482 .configs = aspeed_g4_configs,
23972483 .nconfigs = ARRAY_SIZE(aspeed_g4_configs),
23982484 };
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c+121−6
@@ -21,6 +21,32 @@ · 20 unmodified lines
2121 #include "../pinctrl-utils.h"
2222 #include "pinctrl-aspeed.h"
2323
24+/*
25+ * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
26+ * references registers by the device/offset mnemonic. The register macros
27+ * below are named the same way to ease transcription and verification (as
28+ * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
29+ * reference registers beyond those dedicated to pinmux, such as the system
30+ * reset control and MAC clock configuration registers. The AST2500 goes a step
31+ * further and references registers in the graphics IP block.
32+ */
33+#define SCU2C 0x2C /* Misc. Control Register */
34+#define SCU3C 0x3C /* System Reset Control/Status Register */
35+#define SCU48 0x48 /* MAC Interface Clock Delay Setting */
36+#define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */
37+#define HW_REVISION_ID 0x7C /* Silicon revision ID register */
38+#define SCU80 0x80 /* Multi-function Pin Control #1 */
39+#define SCU84 0x84 /* Multi-function Pin Control #2 */
40+#define SCU88 0x88 /* Multi-function Pin Control #3 */
41+#define SCU8C 0x8C /* Multi-function Pin Control #4 */
42+#define SCU90 0x90 /* Multi-function Pin Control #5 */
43+#define SCU94 0x94 /* Multi-function Pin Control #6 */
44+#define SCUA0 0xA0 /* Multi-function Pin Control #7 */
45+#define SCUA4 0xA4 /* Multi-function Pin Control #8 */
46+#define SCUA8 0xA8 /* Multi-function Pin Control #9 */
47+#define SCUAC 0xAC /* Multi-function Pin Control #10 */
48+#define HW_STRAP2 0xD0 /* Strapping */
49+
2450 #define ASPEED_G5_NR_PINS 236
2551
2652 #define COND1 { ASPEED_IP_SCU, SCU90, BIT(6), 0, 0 }
@@ -573,6 +599,8 @@ SS_PIN_DECL(N3, GPIOJ2, SGPMO); · 546 unmodified lines
573599 SIG_EXPR_LIST_DECL_SINGLE(SGPMI, SGPM, SIG_DESC_SET(SCU84, 11));
574600 SS_PIN_DECL(N4, GPIOJ3, SGPMI);
575601
602+FUNC_GROUP_DECL(SGPM, R2, L2, N3, N4);
603+
576604 #define N5 76
577605 SIG_EXPR_LIST_DECL_SINGLE(VGAHS, VGAHS, SIG_DESC_SET(SCU84, 12));
578606 SIG_EXPR_LIST_DECL_SINGLE(DASHN5, DASHN5, SIG_DESC_SET(SCU94, 8));
@@ -2123,6 +2151,7 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = { · 1544 unmodified lines
21232151 ASPEED_PINCTRL_GROUP(SD2),
21242152 ASPEED_PINCTRL_GROUP(SDA1),
21252153 ASPEED_PINCTRL_GROUP(SDA2),
2154+ ASPEED_PINCTRL_GROUP(SGPM),
21262155 ASPEED_PINCTRL_GROUP(SGPS1),
21272156 ASPEED_PINCTRL_GROUP(SGPS2),
21282157 ASPEED_PINCTRL_GROUP(SIOONCTRL),
@@ -2292,6 +2321,7 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = { · 163 unmodified lines
22922321 ASPEED_PINCTRL_FUNC(SD2),
22932322 ASPEED_PINCTRL_FUNC(SDA1),
22942323 ASPEED_PINCTRL_FUNC(SDA2),
2324+ ASPEED_PINCTRL_FUNC(SGPM),
22952325 ASPEED_PINCTRL_FUNC(SGPS1),
22962326 ASPEED_PINCTRL_FUNC(SGPS2),
22972327 ASPEED_PINCTRL_FUNC(SIOONCTRL),
@@ -2477,13 +2507,98 @@ static struct aspeed_pin_config aspeed_g5_configs[] = { · 179 unmodified lines
24772507 { PIN_CONFIG_INPUT_DEBOUNCE, { A20, B19 }, SCUA8, 27 },
24782508 };
24792509
2510+/**
2511+ * Configure a pin's signal by applying an expression's descriptor state for
2512+ * all descriptors in the expression.
2513+ *
2514+ * @ctx: The pinmux context
2515+ * @expr: The expression associated with the function whose signal is to be
2516+ * configured
2517+ * @enable: true to enable an function's signal through a pin's signal
2518+ * expression, false to disable the function's signal
2519+ *
2520+ * Return: 0 if the expression is configured as requested and a negative error
2521+ * code otherwise
2522+ */
2523+static int aspeed_g5_sig_expr_set(const struct aspeed_pinmux_data *ctx,
2524+ const struct aspeed_sig_expr *expr,
2525+ bool enable)
2526+{
2527+ int ret;
2528+ int i;
2529+
2530+ for (i = 0; i < expr->ndescs; i++) {
2531+ const struct aspeed_sig_desc *desc = &expr->descs[i];
2532+ u32 pattern = enable ? desc->enable : desc->disable;
2533+ u32 val = (pattern << __ffs(desc->mask));
2534+
2535+ if (!ctx->maps[desc->ip])
2536+ return -ENODEV;
2537+
2538+ /*
2539+ * Strap registers are configured in hardware or by early-boot
2540+ * firmware. Treat them as read-only despite that we can write
2541+ * them. This may mean that certain functions cannot be
2542+ * deconfigured and is the reason we re-evaluate after writing
2543+ * all descriptor bits.
2544+ *
2545+ * Port D and port E GPIO loopback modes are the only exception
2546+ * as those are commonly used with front-panel buttons to allow
2547+ * normal operation of the host when the BMC is powered off or
2548+ * fails to boot. Once the BMC has booted, the loopback mode
2549+ * must be disabled for the BMC to control host power-on and
2550+ * reset.
2551+ */
2552+ if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 &&
2553+ !(desc->mask & (BIT(21) | BIT(22))))
2554+ continue;
2555+
2556+ if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2)
2557+ continue;
2558+
2559+ /* On AST2500, Set bits in SCU70 are cleared from SCU7C */
2560+ if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1) {
2561+ u32 value = ~val & desc->mask;
2562+
2563+ if (value) {
2564+ ret = regmap_write(ctx->maps[desc->ip],
2565+ HW_REVISION_ID, value);
2566+ if (ret < 0)
2567+ return ret;
2568+ }
2569+ }
2570+
2571+ ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg,
2572+ desc->mask, val);
2573+
2574+ if (ret)
2575+ return ret;
2576+ }
2577+
2578+ ret = aspeed_sig_expr_eval(ctx, expr, enable);
2579+ if (ret < 0)
2580+ return ret;
2581+
2582+ if (!ret)
2583+ return -EPERM;
2584+
2585+ return 0;
2586+}
2587+
2588+static const struct aspeed_pinmux_ops aspeed_g5_ops = {
2589+ .set = aspeed_g5_sig_expr_set,
2590+};
2591+
24802592 static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {
24812593 .pins = aspeed_g5_pins,
24822594 .npins = ARRAY_SIZE(aspeed_g5_pins),
2483− .groups = aspeed_g5_groups,
2484− .ngroups = ARRAY_SIZE(aspeed_g5_groups),
2485− .functions = aspeed_g5_functions,
2486− .nfunctions = ARRAY_SIZE(aspeed_g5_functions),
2595+ .pinmux = {
2596+ .ops = &aspeed_g5_ops,
2597+ .groups = aspeed_g5_groups,
2598+ .ngroups = ARRAY_SIZE(aspeed_g5_groups),
2599+ .functions = aspeed_g5_functions,
2600+ .nfunctions = ARRAY_SIZE(aspeed_g5_functions),
2601+ },
24872602 .configs = aspeed_g5_configs,
24882603 .nconfigs = ARRAY_SIZE(aspeed_g5_configs),
24892604 };
@@ -2539,7 +2654,7 @@ static int aspeed_g5_pinctrl_probe(struct platform_device *pdev) · 49 unmodified lines
25392654 dev_warn(&pdev->dev, "No GFX phandle found, some mux configurations may fail\n");
25402655 map = NULL;
25412656 }
2542− aspeed_g5_pinctrl_data.maps[ASPEED_IP_GFX] = map;
2657+ aspeed_g5_pinctrl_data.pinmux.maps[ASPEED_IP_GFX] = map;
25432658
25442659 node = of_parse_phandle(pdev->dev.of_node, "aspeed,external-nodes", 1);
25452660 if (node) {
@@ -2553,7 +2668,7 @@ static int aspeed_g5_pinctrl_probe(struct platform_device *pdev) · 7 unmodified lines
25532668 map = NULL;
25542669 }
25552670 of_node_put(node);
2556− aspeed_g5_pinctrl_data.maps[ASPEED_IP_LPC] = map;
2671+ aspeed_g5_pinctrl_data.pinmux.maps[ASPEED_IP_LPC] = map;
25572672
25582673 return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc,
25592674 &aspeed_g5_pinctrl_data);
drivers/pinctrl/aspeed/pinctrl-aspeed.c+37−209
@@ -10,17 +10,11 @@ · 9 unmodified lines
1010 #include "../core.h"
1111 #include "pinctrl-aspeed.h"
1212
13−static const char *const aspeed_pinmux_ips[] = {
14− [ASPEED_IP_SCU] = "SCU",
15− [ASPEED_IP_GFX] = "GFX",
16− [ASPEED_IP_LPC] = "LPC",
17−};
18−
1913 int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
2014 {
2115 struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
2216
23− return pdata->ngroups;
17+ return pdata->pinmux.ngroups;
2418 }
2519
2620 const char *aspeed_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
@@ -28,7 +22,7 @@ const char *aspeed_pinctrl_get_group_name(struct pinctrl_dev *pctldev, · 1 unmodified line
2822 {
2923 struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
3024
31− return pdata->groups[group].name;
25+ return pdata->pinmux.groups[group].name;
3226 }
3327
3428 int aspeed_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
@@ -37,8 +31,8 @@ int aspeed_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, · 2 unmodified lines
3731 {
3832 struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
3933
40− *pins = &pdata->groups[group].pins[0];
41− *npins = pdata->groups[group].npins;
34+ *pins = &pdata->pinmux.groups[group].pins[0];
35+ *npins = pdata->pinmux.groups[group].npins;
4236
4337 return 0;
4438 }
@@ -53,7 +47,7 @@ int aspeed_pinmux_get_fn_count(struct pinctrl_dev *pctldev) · 8 unmodified lines
5347 {
5448 struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
5549
56− return pdata->nfunctions;
50+ return pdata->pinmux.nfunctions;
5751 }
5852
5953 const char *aspeed_pinmux_get_fn_name(struct pinctrl_dev *pctldev,
@@ -61,7 +55,7 @@ const char *aspeed_pinmux_get_fn_name(struct pinctrl_dev *pctldev, · 1 unmodified line
6155 {
6256 struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
6357
64− return pdata->functions[function].name;
58+ return pdata->pinmux.functions[function].name;
6559 }
6660
6761 int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev,
@@ -71,208 +65,38 @@ int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev, · 3 unmodified lines
7165 {
7266 struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
7367
74− *groups = pdata->functions[function].groups;
75− *num_groups = pdata->functions[function].ngroups;
68+ *groups = pdata->pinmux.functions[function].groups;
69+ *num_groups = pdata->pinmux.functions[function].ngroups;
7670
7771 return 0;
7872 }
7973
80−static inline void aspeed_sig_desc_print_val(
81− const struct aspeed_sig_desc *desc, bool enable, u32 rv)
82−{
83− pr_debug("Want %s%X[0x%08X]=0x%X, got 0x%X from 0x%08X\n",
84− aspeed_pinmux_ips[desc->ip], desc->reg,
85− desc->mask, enable ? desc->enable : desc->disable,
86− (rv & desc->mask) >> __ffs(desc->mask), rv);
87−}
88−
89−/**
90− * Query the enabled or disabled state of a signal descriptor
91− *
92− * @desc: The signal descriptor of interest
93− * @enabled: True to query the enabled state, false to query disabled state
94− * @map: The IP block's regmap instance
95− *
96− * Return: 1 if the descriptor's bitfield is configured to the state
97− * selected by @enabled, 0 if not, and less than zero if an unrecoverable
98− * failure occurred
99− *
100− * Evaluation of descriptor state is non-trivial in that it is not a binary
101− * outcome: The bitfields can be greater than one bit in size and thus can take
102− * a value that is neither the enabled nor disabled state recorded in the
103− * descriptor (typically this means a different function to the one of interest
104− * is enabled). Thus we must explicitly test for either condition as required.
105− */
106−static int aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc,
107− bool enabled, struct regmap *map)
74+static int aspeed_sig_expr_enable(const struct aspeed_pinmux_data *ctx,
75+ const struct aspeed_sig_expr *expr)
10876 {
10977 int ret;
110− unsigned int raw;
111− u32 want;
11278
113− if (!map)
114− return -ENODEV;
115−
116− ret = regmap_read(map, desc->reg, &raw);
117− if (ret)
118− return ret;
119−
120− aspeed_sig_desc_print_val(desc, enabled, raw);
121− want = enabled ? desc->enable : desc->disable;
122−
123− return ((raw & desc->mask) >> __ffs(desc->mask)) == want;
124−}
125−
126−/**
127− * Query the enabled or disabled state for a mux function's signal on a pin
128− *
129− * @expr: An expression controlling the signal for a mux function on a pin
130− * @enabled: True to query the enabled state, false to query disabled state
131− * @maps: The list of regmap instances
132− *
133− * Return: 1 if the expression composed by @enabled evaluates true, 0 if not,
134− * and less than zero if an unrecoverable failure occurred.
135− *
136− * A mux function is enabled or disabled if the function's signal expression
137− * for each pin in the function's pin group evaluates true for the desired
138− * state. An signal expression evaluates true if all of its associated signal
139− * descriptors evaluate true for the desired state.
140− *
141− * If an expression's state is described by more than one bit, either through
142− * multi-bit bitfields in a single signal descriptor or through multiple signal
143− * descriptors of a single bit then it is possible for the expression to be in
144− * neither the enabled nor disabled state. Thus we must explicitly test for
145− * either condition as required.
146− */
147−static int aspeed_sig_expr_eval(const struct aspeed_sig_expr *expr,
148− bool enabled, struct regmap * const *maps)
149−{
150− int i;
151− int ret;
152−
153− for (i = 0; i < expr->ndescs; i++) {
154− const struct aspeed_sig_desc *desc = &expr->descs[i];
155−
156− ret = aspeed_sig_desc_eval(desc, enabled, maps[desc->ip]);
157− if (ret <= 0)
158− return ret;
159− }
160−
161− return 1;
162−}
163−
164−/**
165− * Configure a pin's signal by applying an expression's descriptor state for
166− * all descriptors in the expression.
167− *
168− * @expr: The expression associated with the function whose signal is to be
169− * configured
170− * @enable: true to enable an function's signal through a pin's signal
171− * expression, false to disable the function's signal
172− * @maps: The list of regmap instances for pinmux register access.
173− *
174− * Return: 0 if the expression is configured as requested and a negative error
175− * code otherwise
176− */
177−static int aspeed_sig_expr_set(const struct aspeed_sig_expr *expr,
178− bool enable, struct regmap * const *maps)
179−{
180− int ret;
181− int i;
182−
183− for (i = 0; i < expr->ndescs; i++) {
184− const struct aspeed_sig_desc *desc = &expr->descs[i];
185− u32 pattern = enable ? desc->enable : desc->disable;
186− u32 val = (pattern << __ffs(desc->mask));
187−
188− if (!maps[desc->ip])
189− return -ENODEV;
190−
191− /*
192− * Strap registers are configured in hardware or by early-boot
193− * firmware. Treat them as read-only despite that we can write
194− * them. This may mean that certain functions cannot be
195− * deconfigured and is the reason we re-evaluate after writing
196− * all descriptor bits.
197− *
198− * Port D and port E GPIO loopback modes are the only exception
199− * as those are commonly used with front-panel buttons to allow
200− * normal operation of the host when the BMC is powered off or
201− * fails to boot. Once the BMC has booted, the loopback mode
202− * must be disabled for the BMC to control host power-on and
203− * reset.
204− */
205− if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 &&
206− !(desc->mask & (BIT(21) | BIT(22))))
207− continue;
208−
209− if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2)
210− continue;
211−
212− /* On AST2500, Set bits in SCU7C are cleared from SCU70 */
213− if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1) {
214− unsigned int rev_id;
215−
216− ret = regmap_read(maps[ASPEED_IP_SCU],
217− HW_REVISION_ID, &rev_id);
218− if (ret < 0)
219− return ret;
220−
221− if (0x04 == (rev_id >> 24)) {
222− u32 value = ~val & desc->mask;
223−
224− if (value) {
225− ret = regmap_write(maps[desc->ip],
226− HW_REVISION_ID, value);
227− if (ret < 0)
228− return ret;
229− }
230− }
231− }
232−
233− ret = regmap_update_bits(maps[desc->ip], desc->reg,
234− desc->mask, val);
235−
236− if (ret)
237− return ret;
238− }
239−
240− ret = aspeed_sig_expr_eval(expr, enable, maps);
241− if (ret < 0)
242− return ret;
243−
244− if (!ret)
245− return -EPERM;
246−
247− return 0;
248−}
249−
250−static int aspeed_sig_expr_enable(const struct aspeed_sig_expr *expr,
251− struct regmap * const *maps)
252−{
253− int ret;
254−
255− ret = aspeed_sig_expr_eval(expr, true, maps);
79+ ret = aspeed_sig_expr_eval(ctx, expr, true);
25680 if (ret < 0)
25781 return ret;
25882
25983 if (!ret)
260− return aspeed_sig_expr_set(expr, true, maps);
84+ return aspeed_sig_expr_set(ctx, expr, true);
26185
26286 return 0;
26387 }
26488
265−static int aspeed_sig_expr_disable(const struct aspeed_sig_expr *expr,
266− struct regmap * const *maps)
89+static int aspeed_sig_expr_disable(const struct aspeed_pinmux_data *ctx,
90+ const struct aspeed_sig_expr *expr)
26791 {
26892 int ret;
26993
270− ret = aspeed_sig_expr_eval(expr, true, maps);
94+ ret = aspeed_sig_expr_eval(ctx, expr, true);
27195 if (ret < 0)
27296 return ret;
27397
27498 if (ret)
275− return aspeed_sig_expr_set(expr, false, maps);
99+ return aspeed_sig_expr_set(ctx, expr, false);
276100
277101 return 0;
278102 }
@@ -280,13 +104,13 @@ static int aspeed_sig_expr_disable(const struct aspeed_sig_expr *expr, · 1 unmodified line
280104 /**
281105 * Disable a signal on a pin by disabling all provided signal expressions.
282106 *
107+ * @ctx: The pinmux context
283108 * @exprs: The list of signal expressions (from a priority level on a pin)
284− * @maps: The list of regmap instances for pinmux register access.
285109 *
286110 * Return: 0 if all expressions are disabled, otherwise a negative error code
287111 */
288−static int aspeed_disable_sig(const struct aspeed_sig_expr **exprs,
289− struct regmap * const *maps)
112+static int aspeed_disable_sig(const struct aspeed_pinmux_data *ctx,
113+ const struct aspeed_sig_expr **exprs)
290114 {
291115 int ret = 0;
292116
@@ -294,7 +118,7 @@ static int aspeed_disable_sig(const struct aspeed_sig_expr **exprs, · 1 unmodified line
294118 return true;
295119
296120 while (*exprs && !ret) {
297− ret = aspeed_sig_expr_disable(*exprs, maps);
121+ ret = aspeed_sig_expr_disable(ctx, *exprs);
298122 exprs++;
299123 }
300124
@@ -395,9 +219,9 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, · 94 unmodified lines
395219 int ret;
396220 const struct aspeed_pinctrl_data *pdata =
397221 pinctrl_dev_get_drvdata(pctldev);
398− const struct aspeed_pin_group *pgroup = &pdata->groups[group];
222+ const struct aspeed_pin_group *pgroup = &pdata->pinmux.groups[group];
399223 const struct aspeed_pin_function *pfunc =
400− &pdata->functions[function];
224+ &pdata->pinmux.functions[function];
401225
402226 for (i = 0; i < pgroup->npins; i++) {
403227 int pin = pgroup->pins[i];
@@ -423,7 +247,7 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, · 19 unmodified lines
423247 if (expr)
424248 break;
425249
426− ret = aspeed_disable_sig(funcs, pdata->maps);
250+ ret = aspeed_disable_sig(&pdata->pinmux, funcs);
427251 if (ret)
428252 return ret;
429253
@@ -443,7 +267,7 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, · 13 unmodified lines
443267 return -ENXIO;
444268 }
445269
446− ret = aspeed_sig_expr_enable(expr, pdata->maps);
270+ ret = aspeed_sig_expr_enable(&pdata->pinmux, expr);
447271 if (ret)
448272 return ret;
449273 }
@@ -500,7 +324,7 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev, · 50 unmodified lines
500324 if (aspeed_gpio_in_exprs(funcs))
501325 break;
502326
503− ret = aspeed_disable_sig(funcs, pdata->maps);
327+ ret = aspeed_disable_sig(&pdata->pinmux, funcs);
504328 if (ret)
505329 return ret;
506330
@@ -531,7 +355,7 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev, · 24 unmodified lines
531355 * If GPIO is not the lowest priority signal type, assume there is only
532356 * one expression defined to enable the GPIO function
533357 */
534− return aspeed_sig_expr_enable(expr, pdata->maps);
358+ return aspeed_sig_expr_enable(&pdata->pinmux, expr);
535359 }
536360
537361 int aspeed_pinctrl_probe(struct platform_device *pdev,
@@ -547,12 +371,14 @@ int aspeed_pinctrl_probe(struct platform_device *pdev, · 9 unmodified lines
547371 return -ENODEV;
548372 }
549373
550− pdata->maps[ASPEED_IP_SCU] = syscon_node_to_regmap(parent->of_node);
551− if (IS_ERR(pdata->maps[ASPEED_IP_SCU])) {
374+ pdata->scu = syscon_node_to_regmap(parent->of_node);
375+ if (IS_ERR(pdata->scu)) {
552376 dev_err(&pdev->dev, "No regmap for syscon pincontroller parent\n");
553− return PTR_ERR(pdata->maps[ASPEED_IP_SCU]);
377+ return PTR_ERR(pdata->scu);
554378 }
555379
380+ pdata->pinmux.maps[ASPEED_IP_SCU] = pdata->scu;
381+
556382 pctl = pinctrl_register(pdesc, &pdev->dev, pdata);
557383
558384 if (IS_ERR(pctl)) {
@@ -587,7 +413,9 @@ static inline const struct aspeed_pin_config *find_pinconf_config( · 28 unmodified lines
587413 return NULL;
588414 }
589415
590−/**
416+/*
417+ * Aspeed pin configuration description.
418+ *
591419 * @param: pinconf configuration parameter
592420 * @arg: The supported argument for @param, or -1 if any value is supported
593421 * @val: The register value to write to configure @arg for @param
@@ -661,7 +489,7 @@ int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset, · 67 unmodified lines
661489 if (!pconf)
662490 return -ENOTSUPP;
663491
664− rc = regmap_read(pdata->maps[ASPEED_IP_SCU], pconf->reg, &val);
492+ rc = regmap_read(pdata->scu, pconf->reg, &val);
665493 if (rc < 0)
666494 return rc;
667495
@@ -716,8 +544,8 @@ int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset, · 48 unmodified lines
716544
717545 val = pmap->val << pconf->bit;
718546
719− rc = regmap_update_bits(pdata->maps[ASPEED_IP_SCU], pconf->reg,
720− BIT(pconf->bit), val);
547+ rc = regmap_update_bits(pdata->scu, pconf->reg,
548+ BIT(pconf->bit), val);
721549
722550 if (rc < 0)
723551 return rc;
drivers/pinctrl/aspeed/pinctrl-aspeed.h+9−533
@@ -12,504 +12,7 @@ · 11 unmodified lines
1212 #include <linux/pinctrl/pinconf-generic.h>
1313 #include <linux/regmap.h>
1414
15−/*
16− * The ASPEED SoCs provide typically more than 200 pins for GPIO and other
17− * functions. The SoC function enabled on a pin is determined on a priority
18− * basis where a given pin can provide a number of different signal types.
19− *
20− * The signal active on a pin is described by both a priority level and
21− * compound logical expressions involving multiple operators, registers and
22− * bits. Some difficulty arises as the pin's function bit masks for each
23− * priority level are frequently not the same (i.e. cannot just flip a bit to
24− * change from a high to low priority signal), or even in the same register.
25− * Further, not all signals can be unmuxed, as some expressions depend on
26− * values in the hardware strapping register (which is treated as read-only).
27− *
28− * SoC Multi-function Pin Expression Examples
29− * ------------------------------------------
30− *
31− * Here are some sample mux configurations from the AST2400 and AST2500
32− * datasheets to illustrate the corner cases, roughly in order of least to most
33− * corner. The signal priorities are in decending order from P0 (highest).
34− *
35− * D6 is a pin with a single function (beside GPIO); a high priority signal
36− * that participates in one function:
37− *
38− * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
39− * -----+---------+-----------+-----------------------------+-----------+---------------+----------
40− * D6 GPIOA0 MAC1LINK SCU80[0]=1 GPIOA0
41− * -----+---------+-----------+-----------------------------+-----------+---------------+----------
42− *
43− * C5 is a multi-signal pin (high and low priority signals). Here we touch
44− * different registers for the different functions that enable each signal:
45− *
46− * -----+---------+-----------+-----------------------------+-----------+---------------+----------
47− * C5 GPIOA4 SCL9 SCU90[22]=1 TIMER5 SCU80[4]=1 GPIOA4
48− * -----+---------+-----------+-----------------------------+-----------+---------------+----------
49− *
50− * E19 is a single-signal pin with two functions that influence the active
51− * signal. In this case both bits have the same meaning - enable a dedicated
52− * LPC reset pin. However it's not always the case that the bits in the
53− * OR-relationship have the same meaning.
54− *
55− * -----+---------+-----------+-----------------------------+-----------+---------------+----------
56− * E19 GPIOB4 LPCRST# SCU80[12]=1 | Strap[14]=1 GPIOB4
57− * -----+---------+-----------+-----------------------------+-----------+---------------+----------
58− *
59− * For example, pin B19 has a low-priority signal that's enabled by two
60− * distinct SoC functions: A specific SIOPBI bit in register SCUA4, and an ACPI
61− * bit in the STRAP register. The ACPI bit configures signals on pins in
62− * addition to B19. Both of the low priority functions as well as the high
63− * priority function must be disabled for GPIOF1 to be used.
64− *
65− * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
66− * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
67− * B19 GPIOF1 NDCD4 SCU80[25]=1 SIOPBI# SCUA4[12]=1 | Strap[19]=0 GPIOF1
68− * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
69− *
70− * For pin E18, the SoC ANDs the expected state of three bits to determine the
71− * pin's active signal:
72− *
73− * * SCU3C[3]: Enable external SOC reset function
74− * * SCU80[15]: Enable SPICS1# or EXTRST# function pin
75− * * SCU90[31]: Select SPI interface CS# output
76− *
77− * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
78− * E18 GPIOB7 EXTRST# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=0 SPICS1# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=1 GPIOB7
79− * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
80− *
81− * (Bits SCU3C[3] and SCU80[15] appear to only be used in the expressions for
82− * selecting the signals on pin E18)
83− *
84− * Pin T5 is a multi-signal pin with a more complex configuration:
85− *
86− * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
87− * -----+---------+-----------+------------------------------+-----------+---------------+----------
88− * T5 GPIOL1 VPIDE SCU90[5:4]!=0 & SCU84[17]=1 NDCD1 SCU84[17]=1 GPIOL1
89− * -----+---------+-----------+------------------------------+-----------+---------------+----------
90− *
91− * The high priority signal configuration is best thought of in terms of its
92− * exploded form, with reference to the SCU90[5:4] bits:
93− *
94− * * SCU90[5:4]=00: disable
95− * * SCU90[5:4]=01: 18 bits (R6/G6/B6) video mode.
96− * * SCU90[5:4]=10: 24 bits (R8/G8/B8) video mode.
97− * * SCU90[5:4]=11: 30 bits (R10/G10/B10) video mode.
98− *
99− * Re-writing:
100− *
101− * -----+---------+-----------+------------------------------+-----------+---------------+----------
102− * T5 GPIOL1 VPIDE (SCU90[5:4]=1 & SCU84[17]=1) NDCD1 SCU84[17]=1 GPIOL1
103− * | (SCU90[5:4]=2 & SCU84[17]=1)
104− * | (SCU90[5:4]=3 & SCU84[17]=1)
105− * -----+---------+-----------+------------------------------+-----------+---------------+----------
106− *
107− * For reference the SCU84[17] bit configure the "UART1 NDCD1 or Video VPIDE
108− * function pin", where the signal itself is determined by whether SCU94[5:4]
109− * is disabled or in one of the 18, 24 or 30bit video modes.
110− *
111− * Other video-input-related pins require an explicit state in SCU90[5:4], e.g.
112− * W1 and U5:
113− *
114− * -----+---------+-----------+------------------------------+-----------+---------------+----------
115− * W1 GPIOL6 VPIB0 SCU90[5:4]=3 & SCU84[22]=1 TXD1 SCU84[22]=1 GPIOL6
116− * U5 GPIOL7 VPIB1 SCU90[5:4]=3 & SCU84[23]=1 RXD1 SCU84[23]=1 GPIOL7
117− * -----+---------+-----------+------------------------------+-----------+---------------+----------
118− *
119− * The examples of T5 and W1 are particularly fertile, as they also demonstrate
120− * that despite operating as part of the video input bus each signal needs to
121− * be enabled individually via it's own SCU84 (in the cases of T5 and W1)
122− * register bit. This is a little crazy if the bus doesn't have optional
123− * signals, but is used to decent effect with some of the UARTs where not all
124− * signals are required. However, this isn't done consistently - UART1 is
125− * enabled on a per-pin basis, and by contrast, all signals for UART6 are
126− * enabled by a single bit.
127− *
128− * Further, the high and low priority signals listed in the table above share
129− * a configuration bit. The VPI signals should operate in concert in a single
130− * function, but the UART signals should retain the ability to be configured
131− * independently. This pushes the implementation down the path of tagging a
132− * signal's expressions with the function they participate in, rather than
133− * defining masks affecting multiple signals per function. The latter approach
134− * fails in this instance where applying the configuration for the UART pin of
135− * interest will stomp on the state of other UART signals when disabling the
136− * VPI functions on the current pin.
137− *
138− * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
139− * -----+------------+-----------+---------------------------+-----------+---------------+------------
140− * A12 RGMII1TXCK GPIOT0 SCUA0[0]=1 RMII1TXEN Strap[6]=0 RGMII1TXCK
141− * B12 RGMII1TXCTL GPIOT1 SCUA0[1]=1 – Strap[6]=0 RGMII1TXCTL
142− * -----+------------+-----------+---------------------------+-----------+---------------+------------
143− *
144− * A12 demonstrates that the "Other" signal isn't always GPIO - in this case
145− * GPIOT0 is a high-priority signal and RGMII1TXCK is Other. Thus, GPIO
146− * should be treated like any other signal type with full function expression
147− * requirements, and not assumed to be the default case. Separately, GPIOT0 and
148− * GPIOT1's signal descriptor bits are distinct, therefore we must iterate all
149− * pins in the function's group to disable the higher-priority signals such
150− * that the signal for the function of interest is correctly enabled.
151− *
152− * Finally, three priority levels aren't always enough; the AST2500 brings with
153− * it 18 pins of five priority levels, however the 18 pins only use three of
154− * the five priority levels.
155− *
156− * Ultimately the requirement to control pins in the examples above drive the
157− * design:
158− *
159− * * Pins provide signals according to functions activated in the mux
160− * configuration
161− *
162− * * Pins provide up to five signal types in a priority order
163− *
164− * * For priorities levels defined on a pin, each priority provides one signal
165− *
166− * * Enabling lower priority signals requires higher priority signals be
167− * disabled
168− *
169− * * A function represents a set of signals; functions are distinct if their
170− * sets of signals are not equal
171− *
172− * * Signals participate in one or more functions
173− *
174− * * A function is described by an expression of one or more signal
175− * descriptors, which compare bit values in a register
176− *
177− * * A signal expression is the smallest set of signal descriptors whose
178− * comparisons must evaluate 'true' for a signal to be enabled on a pin.
179− *
180− * * A function's signal is active on a pin if evaluating all signal
181− * descriptors in the pin's signal expression for the function yields a 'true'
182− * result
183− *
184− * * A signal at a given priority on a given pin is active if any of the
185− * functions in which the signal participates are active, and no higher
186− * priority signal on the pin is active
187− *
188− * * GPIO is configured per-pin
189− *
190− * And so:
191− *
192− * * To disable a signal, any function(s) activating the signal must be
193− * disabled
194− *
195− * * Each pin must know the signal expressions of functions in which it
196− * participates, for the purpose of enabling the Other function. This is done
197− * by deactivating all functions that activate higher priority signals on the
198− * pin.
199− *
200− * As a concrete example:
201− *
202− * * T5 provides three signals types: VPIDE, NDCD1 and GPIO
203− *
204− * * The VPIDE signal participates in 3 functions: VPI18, VPI24 and VPI30
205− *
206− * * The NDCD1 signal participates in just its own NDCD1 function
207− *
208− * * VPIDE is high priority, NDCD1 is low priority, and GPIOL1 is the least
209− * prioritised
210− *
211− * * The prerequisit for activating the NDCD1 signal is that the VPI18, VPI24
212− * and VPI30 functions all be disabled
213− *
214− * * Similarly, all of VPI18, VPI24, VPI30 and NDCD1 functions must be disabled
215− * to provide GPIOL6
216− *
217− * Considerations
218− * --------------
219− *
220− * If pinctrl allows us to allocate a pin we can configure a function without
221− * concern for the function of already allocated pins, if pin groups are
222− * created with respect to the SoC functions in which they participate. This is
223− * intuitive, but it did not feel obvious from the bit/pin relationships.
224− *
225− * Conversely, failing to allocate all pins in a group indicates some bits (as
226− * well as pins) required for the group's configuration will already be in use,
227− * likely in a way that's inconsistent with the requirements of the failed
228− * group.
229− */
230−
231−#define ASPEED_IP_SCU 0
232−#define ASPEED_IP_GFX 1
233−#define ASPEED_IP_LPC 2
234−#define ASPEED_NR_PINMUX_IPS 3
235−
236−/*
237− * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
238− * references registers by the device/offset mnemonic. The register macros
239− * below are named the same way to ease transcription and verification (as
240− * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
241− * reference registers beyond those dedicated to pinmux, such as the system
242− * reset control and MAC clock configuration registers. The AST2500 goes a step
243− * further and references registers in the graphics IP block, but that isn't
244− * handled yet.
245− */
246−#define SCU2C 0x2C /* Misc. Control Register */
247−#define SCU3C 0x3C /* System Reset Control/Status Register */
248−#define SCU48 0x48 /* MAC Interface Clock Delay Setting */
249−#define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */
250−#define HW_REVISION_ID 0x7C /* Silicon revision ID register */
251−#define SCU80 0x80 /* Multi-function Pin Control #1 */
252−#define SCU84 0x84 /* Multi-function Pin Control #2 */
253−#define SCU88 0x88 /* Multi-function Pin Control #3 */
254−#define SCU8C 0x8C /* Multi-function Pin Control #4 */
255−#define SCU90 0x90 /* Multi-function Pin Control #5 */
256−#define SCU94 0x94 /* Multi-function Pin Control #6 */
257−#define SCUA0 0xA0 /* Multi-function Pin Control #7 */
258−#define SCUA4 0xA4 /* Multi-function Pin Control #8 */
259−#define SCUA8 0xA8 /* Multi-function Pin Control #9 */
260−#define SCUAC 0xAC /* Multi-function Pin Control #10 */
261−#define HW_STRAP2 0xD0 /* Strapping */
262−
263− /**
264− * A signal descriptor, which describes the register, bits and the
265− * enable/disable values that should be compared or written.
266− *
267− * @ip: The IP block identifier, used as an index into the regmap array in
268− * struct aspeed_pinctrl_data
269− * @reg: The register offset with respect to the base address of the IP block
270− * @mask: The mask to apply to the register. The lowest set bit of the mask is
271− * used to derive the shift value.
272− * @enable: The value that enables the function. Value should be in the LSBs,
273− * not at the position of the mask.
274− * @disable: The value that disables the function. Value should be in the
275− * LSBs, not at the position of the mask.
276− */
277−struct aspeed_sig_desc {
278− unsigned int ip;
279− unsigned int reg;
280− u32 mask;
281− u32 enable;
282− u32 disable;
283−};
284−
285−/**
286− * Describes a signal expression. The expression is evaluated by ANDing the
287− * evaluation of the descriptors.
288− *
289− * @signal: The signal name for the priority level on the pin. If the signal
290− * type is GPIO, then the signal name must begin with the string
291− * "GPIO", e.g. GPIOA0, GPIOT4 etc.
292− * @function: The name of the function the signal participates in for the
293− * associated expression
294− * @ndescs: The number of signal descriptors in the expression
295− * @descs: Pointer to an array of signal descriptors that comprise the
296− * function expression
297− */
298−struct aspeed_sig_expr {
299− const char *signal;
300− const char *function;
301− int ndescs;
302− const struct aspeed_sig_desc *descs;
303−};
304−
305−/**
306− * A struct capturing the list of expressions enabling signals at each priority
307− * for a given pin. The signal configuration for a priority level is evaluated
308− * by ORing the evaluation of the signal expressions in the respective
309− * priority's list.
310− *
311− * @name: A name for the pin
312− * @prios: A pointer to an array of expression list pointers
313− *
314− */
315−struct aspeed_pin_desc {
316− const char *name;
317− const struct aspeed_sig_expr ***prios;
318−};
319−
320−/* Macro hell */
321−
322−#define SIG_DESC_IP_BIT(ip, reg, idx, val) \
323− { ip, reg, BIT_MASK(idx), val, (((val) + 1) & 1) }
324−
325−/**
326− * Short-hand macro for describing an SCU descriptor enabled by the state of
327− * one bit. The disable value is derived.
328− *
329− * @reg: The signal's associated register, offset from base
330− * @idx: The signal's bit index in the register
331− * @val: The value (0 or 1) that enables the function
332− */
333−#define SIG_DESC_BIT(reg, idx, val) \
334− SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, val)
335−
336−#define SIG_DESC_IP_SET(ip, reg, idx) SIG_DESC_IP_BIT(ip, reg, idx, 1)
337−
338−/**
339− * A further short-hand macro expanding to an SCU descriptor enabled by a set
340− * bit.
341− *
342− * @reg: The register, offset from base
343− * @idx: The bit index in the register
344− */
345−#define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1)
346−
347−#define SIG_DESC_LIST_SYM(sig, func) sig_descs_ ## sig ## _ ## func
348−#define SIG_DESC_LIST_DECL(sig, func, ...) \
349− static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, func)[] = \
350− { __VA_ARGS__ }
351−
352−#define SIG_EXPR_SYM(sig, func) sig_expr_ ## sig ## _ ## func
353−#define SIG_EXPR_DECL_(sig, func) \
354− static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, func) = \
355− { \
356− .signal = #sig, \
357− .function = #func, \
358− .ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, func)), \
359− .descs = &(SIG_DESC_LIST_SYM(sig, func))[0], \
360− }
361−
362−/**
363− * Declare a signal expression.
364− *
365− * @sig: A macro symbol name for the signal (is subjected to stringification
366− * and token pasting)
367− * @func: The function in which the signal is participating
368− * @...: Signal descriptors that define the signal expression
369− *
370− * For example, the following declares the ROMD8 signal for the ROM16 function:
371− *
372− * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
373− *
374− * And with multiple signal descriptors:
375− *
376− * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
377− * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
378− */
379−#define SIG_EXPR_DECL(sig, func, ...) \
380− SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \
381− SIG_EXPR_DECL_(sig, func)
382−
383−/**
384− * Declare a pointer to a signal expression
385− *
386− * @sig: The macro symbol name for the signal (subjected to token pasting)
387− * @func: The macro symbol name for the function (subjected to token pasting)
388− */
389−#define SIG_EXPR_PTR(sig, func) (&SIG_EXPR_SYM(sig, func))
390−
391−#define SIG_EXPR_LIST_SYM(sig) sig_exprs_ ## sig
392−
393−/**
394− * Declare a signal expression list for reference in a struct aspeed_pin_prio.
395− *
396− * @sig: A macro symbol name for the signal (is subjected to token pasting)
397− * @...: Signal expression structure pointers (use SIG_EXPR_PTR())
398− *
399− * For example, the 16-bit ROM bus can be enabled by one of two possible signal
400− * expressions:
401− *
402− * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
403− * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
404− * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
405− * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
406− * SIG_EXPR_PTR(ROMD8, ROM16S));
407− */
408−#define SIG_EXPR_LIST_DECL(sig, ...) \
409− static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig)[] = \
410− { __VA_ARGS__, NULL }
411−
412−/**
413− * A short-hand macro for declaring a function expression and an expression
414− * list with a single function.
415− *
416− * @func: A macro symbol name for the function (is subjected to token pasting)
417− * @...: Function descriptors that define the function expression
418− *
419− * For example, signal NCTS6 participates in its own function with one group:
420− *
421− * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
422− */
423−#define SIG_EXPR_LIST_DECL_SINGLE(sig, func, ...) \
424− SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \
425− SIG_EXPR_DECL_(sig, func); \
426− SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, func))
427−
428−#define SIG_EXPR_LIST_DECL_DUAL(sig, f0, f1) \
429− SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, f0), SIG_EXPR_PTR(sig, f1))
430−
431−#define SIG_EXPR_LIST_PTR(sig) (&SIG_EXPR_LIST_SYM(sig)[0])
432−
433−#define PIN_EXPRS_SYM(pin) pin_exprs_ ## pin
434−#define PIN_EXPRS_PTR(pin) (&PIN_EXPRS_SYM(pin)[0])
435−#define PIN_SYM(pin) pin_ ## pin
436−
437−#define MS_PIN_DECL_(pin, ...) \
438− static const struct aspeed_sig_expr **PIN_EXPRS_SYM(pin)[] = \
439− { __VA_ARGS__, NULL }; \
440− static const struct aspeed_pin_desc PIN_SYM(pin) = \
441− { #pin, PIN_EXPRS_PTR(pin) }
442−
443−/**
444− * Declare a multi-signal pin
445− *
446− * @pin: The pin number
447− * @other: Macro name for "other" functionality (subjected to stringification)
448− * @high: Macro name for the highest priority signal functions
449− * @low: Macro name for the low signal functions
450− *
451− * For example:
452− *
453− * #define A8 56
454− * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
455− * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
456− * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
457− * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
458− * SIG_EXPR_PTR(ROMD8, ROM16S));
459− * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
460− * MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6);
461− */
462−#define MS_PIN_DECL(pin, other, high, low) \
463− SIG_EXPR_LIST_DECL_SINGLE(other, other); \
464− MS_PIN_DECL_(pin, \
465− SIG_EXPR_LIST_PTR(high), \
466− SIG_EXPR_LIST_PTR(low), \
467− SIG_EXPR_LIST_PTR(other))
468−
469−#define PIN_GROUP_SYM(func) pins_ ## func
470−#define FUNC_GROUP_SYM(func) groups_ ## func
471−#define FUNC_GROUP_DECL(func, ...) \
472− static const int PIN_GROUP_SYM(func)[] = { __VA_ARGS__ }; \
473− static const char *FUNC_GROUP_SYM(func)[] = { #func }
474−
475−/**
476− * Declare a single signal pin
477− *
478− * @pin: The pin number
479− * @other: Macro name for "other" functionality (subjected to stringification)
480− * @sig: Macro name for the signal (subjected to stringification)
481− *
482− * For example:
483− *
484− * #define E3 80
485− * SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
486− * SS_PIN_DECL(E3, GPIOK0, SCL5);
487− */
488−#define SS_PIN_DECL(pin, other, sig) \
489− SIG_EXPR_LIST_DECL_SINGLE(other, other); \
490− MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other))
491−
492−/**
493− * Single signal, single function pin declaration
494− *
495− * @pin: The pin number
496− * @other: Macro name for "other" functionality (subjected to stringification)
497− * @sig: Macro name for the signal (subjected to stringification)
498− * @...: Signal descriptors that define the function expression
499− *
500− * For example:
501− *
502− * SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2));
503− */
504−#define SSSF_PIN_DECL(pin, other, sig, ...) \
505− SIG_EXPR_LIST_DECL_SINGLE(sig, sig, __VA_ARGS__); \
506− SIG_EXPR_LIST_DECL_SINGLE(other, other); \
507− MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other)); \
508− FUNC_GROUP_DECL(sig, pin)
509−
510−#define GPIO_PIN_DECL(pin, gpio) \
511− SIG_EXPR_LIST_DECL_SINGLE(gpio, gpio); \
512− MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(gpio))
15+#include "pinmux-aspeed.h"
51316
51417 /**
51518 * @param The pinconf parameter type
@@ -525,22 +28,6 @@ struct aspeed_pin_config { · 9 unmodified lines
52528 u8 value;
52629 };
52730
528−struct aspeed_pinctrl_data {
529− struct regmap *maps[ASPEED_NR_PINMUX_IPS];
530−
531− const struct pinctrl_pin_desc *pins;
532− const unsigned int npins;
533−
534− const struct aspeed_pin_group *groups;
535− const unsigned int ngroups;
536−
537− const struct aspeed_pin_function *functions;
538− const unsigned int nfunctions;
539−
540− const struct aspeed_pin_config *configs;
541− const unsigned int nconfigs;
542−};
543−
54431 #define ASPEED_PINCTRL_PIN(name_) \
54532 [name_] = { \
54633 .number = name_, \
@@ -548,30 +35,19 @@ struct aspeed_pinctrl_data { · 1 unmodified line
54835 .drv_data = (void *) &(PIN_SYM(name_)) \
54936 }
55037
551−struct aspeed_pin_group {
552− const char *name;
553− const unsigned int *pins;
38+struct aspeed_pinctrl_data {
39+ struct regmap *scu;
40+
41+ const struct pinctrl_pin_desc *pins;
55442 const unsigned int npins;
555−};
55643
557−#define ASPEED_PINCTRL_GROUP(name_) { \
558− .name = #name_, \
559− .pins = &(PIN_GROUP_SYM(name_))[0], \
560− .npins = ARRAY_SIZE(PIN_GROUP_SYM(name_)), \
561−}
44+ const struct aspeed_pin_config *configs;
45+ const unsigned int nconfigs;
56246
563−struct aspeed_pin_function {
564− const char *name;
565− const char *const *groups;
566− unsigned int ngroups;
47+ struct aspeed_pinmux_data pinmux;
56748 };
56849
569−#define ASPEED_PINCTRL_FUNC(name_, ...) { \
570− .name = #name_, \
571− .groups = &FUNC_GROUP_SYM(name_)[0], \
572− .ngroups = ARRAY_SIZE(FUNC_GROUP_SYM(name_)), \
573−}
574−
50+/* Aspeed pinctrl helpers */
57551 int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev);
57652 const char *aspeed_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
57753 unsigned int group);
drivers/pinctrl/aspeed/pinmux-aspeed.c+96−0
@@ -0,0 +1,96 @@
1+// SPDX-License-Identifier: GPL-2.0-or-later
2+/* Copyright (C) 2019 IBM Corp. */
3+
4+/* Pieces to enable drivers to implement the .set callback */
5+
6+#include "pinmux-aspeed.h"
7+
8+const char *const aspeed_pinmux_ips[] = {
9+ [ASPEED_IP_SCU] = "SCU",
10+ [ASPEED_IP_GFX] = "GFX",
11+ [ASPEED_IP_LPC] = "LPC",
12+};
13+
14+static inline void aspeed_sig_desc_print_val(
15+ const struct aspeed_sig_desc *desc, bool enable, u32 rv)
16+{
17+ pr_debug("Want %s%X[0x%08X]=0x%X, got 0x%X from 0x%08X\n",
18+ aspeed_pinmux_ips[desc->ip], desc->reg,
19+ desc->mask, enable ? desc->enable : desc->disable,
20+ (rv & desc->mask) >> __ffs(desc->mask), rv);
21+}
22+
23+/**
24+ * Query the enabled or disabled state of a signal descriptor
25+ *
26+ * @desc: The signal descriptor of interest
27+ * @enabled: True to query the enabled state, false to query disabled state
28+ * @map: The IP block's regmap instance
29+ *
30+ * Return: 1 if the descriptor's bitfield is configured to the state
31+ * selected by @enabled, 0 if not, and less than zero if an unrecoverable
32+ * failure occurred
33+ *
34+ * Evaluation of descriptor state is non-trivial in that it is not a binary
35+ * outcome: The bitfields can be greater than one bit in size and thus can take
36+ * a value that is neither the enabled nor disabled state recorded in the
37+ * descriptor (typically this means a different function to the one of interest
38+ * is enabled). Thus we must explicitly test for either condition as required.
39+ */
40+int aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc,
41+ bool enabled, struct regmap *map)
42+{
43+ int ret;
44+ unsigned int raw;
45+ u32 want;
46+
47+ if (!map)
48+ return -ENODEV;
49+
50+ ret = regmap_read(map, desc->reg, &raw);
51+ if (ret)
52+ return ret;
53+
54+ aspeed_sig_desc_print_val(desc, enabled, raw);
55+ want = enabled ? desc->enable : desc->disable;
56+
57+ return ((raw & desc->mask) >> __ffs(desc->mask)) == want;
58+}
59+
60+/**
61+ * Query the enabled or disabled state for a mux function's signal on a pin
62+ *
63+ * @ctx: The driver context for the pinctrl IP
64+ * @expr: An expression controlling the signal for a mux function on a pin
65+ * @enabled: True to query the enabled state, false to query disabled state
66+ *
67+ * Return: 1 if the expression composed by @enabled evaluates true, 0 if not,
68+ * and less than zero if an unrecoverable failure occurred.
69+ *
70+ * A mux function is enabled or disabled if the function's signal expression
71+ * for each pin in the function's pin group evaluates true for the desired
72+ * state. An signal expression evaluates true if all of its associated signal
73+ * descriptors evaluate true for the desired state.
74+ *
75+ * If an expression's state is described by more than one bit, either through
76+ * multi-bit bitfields in a single signal descriptor or through multiple signal
77+ * descriptors of a single bit then it is possible for the expression to be in
78+ * neither the enabled nor disabled state. Thus we must explicitly test for
79+ * either condition as required.
80+ */
81+int aspeed_sig_expr_eval(const struct aspeed_pinmux_data *ctx,
82+ const struct aspeed_sig_expr *expr, bool enabled)
83+{
84+ int i;
85+ int ret;
86+
87+ for (i = 0; i < expr->ndescs; i++) {
88+ const struct aspeed_sig_desc *desc = &expr->descs[i];
89+
90+ ret = aspeed_sig_desc_eval(desc, enabled, ctx->maps[desc->ip]);
91+ if (ret <= 0)
92+ return ret;
93+ }
94+
95+ return 1;
96+}
drivers/pinctrl/aspeed/pinmux-aspeed.h+735−0
@@ -0,0 +1,735 @@
1+/* SPDX-License-Identifier: GPL-2.0-or-later */
2+/* Copyright (C) 2019 IBM Corp. */
3+
4+#ifndef ASPEED_PINMUX_H
5+#define ASPEED_PINMUX_H
6+
7+#include <linux/regmap.h>
8+#include <stdbool.h>
9+
10+/*
11+ * The ASPEED SoCs provide typically more than 200 pins for GPIO and other
12+ * functions. The SoC function enabled on a pin is determined on a priority
13+ * basis where a given pin can provide a number of different signal types.
14+ *
15+ * The signal active on a pin is described by both a priority level and
16+ * compound logical expressions involving multiple operators, registers and
17+ * bits. Some difficulty arises as the pin's function bit masks for each
18+ * priority level are frequently not the same (i.e. cannot just flip a bit to
19+ * change from a high to low priority signal), or even in the same register.
20+ * Further, not all signals can be unmuxed, as some expressions depend on
21+ * values in the hardware strapping register (which may be treated as
22+ * read-only).
23+ *
24+ * SoC Multi-function Pin Expression Examples
25+ * ------------------------------------------
26+ *
27+ * Here are some sample mux configurations from the AST2400 and AST2500
28+ * datasheets to illustrate the corner cases, roughly in order of least to most
29+ * corner. The signal priorities are in decending order from P0 (highest).
30+ *
31+ * D6 is a pin with a single function (beside GPIO); a high priority signal
32+ * that participates in one function:
33+ *
34+ * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
35+ * -----+---------+-----------+-----------------------------+-----------+---------------+----------
36+ * D6 GPIOA0 MAC1LINK SCU80[0]=1 GPIOA0
37+ * -----+---------+-----------+-----------------------------+-----------+---------------+----------
38+ *
39+ * C5 is a multi-signal pin (high and low priority signals). Here we touch
40+ * different registers for the different functions that enable each signal:
41+ *
42+ * -----+---------+-----------+-----------------------------+-----------+---------------+----------
43+ * C5 GPIOA4 SCL9 SCU90[22]=1 TIMER5 SCU80[4]=1 GPIOA4
44+ * -----+---------+-----------+-----------------------------+-----------+---------------+----------
45+ *
46+ * E19 is a single-signal pin with two functions that influence the active
47+ * signal. In this case both bits have the same meaning - enable a dedicated
48+ * LPC reset pin. However it's not always the case that the bits in the
49+ * OR-relationship have the same meaning.
50+ *
51+ * -----+---------+-----------+-----------------------------+-----------+---------------+----------
52+ * E19 GPIOB4 LPCRST# SCU80[12]=1 | Strap[14]=1 GPIOB4
53+ * -----+---------+-----------+-----------------------------+-----------+---------------+----------
54+ *
55+ * For example, pin B19 has a low-priority signal that's enabled by two
56+ * distinct SoC functions: A specific SIOPBI bit in register SCUA4, and an ACPI
57+ * bit in the STRAP register. The ACPI bit configures signals on pins in
58+ * addition to B19. Both of the low priority functions as well as the high
59+ * priority function must be disabled for GPIOF1 to be used.
60+ *
61+ * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
62+ * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
63+ * B19 GPIOF1 NDCD4 SCU80[25]=1 SIOPBI# SCUA4[12]=1 | Strap[19]=0 GPIOF1
64+ * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
65+ *
66+ * For pin E18, the SoC ANDs the expected state of three bits to determine the
67+ * pin's active signal:
68+ *
69+ * * SCU3C[3]: Enable external SOC reset function
70+ * * SCU80[15]: Enable SPICS1# or EXTRST# function pin
71+ * * SCU90[31]: Select SPI interface CS# output
72+ *
73+ * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
74+ * E18 GPIOB7 EXTRST# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=0 SPICS1# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=1 GPIOB7
75+ * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
76+ *
77+ * (Bits SCU3C[3] and SCU80[15] appear to only be used in the expressions for
78+ * selecting the signals on pin E18)
79+ *
80+ * Pin T5 is a multi-signal pin with a more complex configuration:
81+ *
82+ * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
83+ * -----+---------+-----------+------------------------------+-----------+---------------+----------
84+ * T5 GPIOL1 VPIDE SCU90[5:4]!=0 & SCU84[17]=1 NDCD1 SCU84[17]=1 GPIOL1
85+ * -----+---------+-----------+------------------------------+-----------+---------------+----------
86+ *
87+ * The high priority signal configuration is best thought of in terms of its
88+ * exploded form, with reference to the SCU90[5:4] bits:
89+ *
90+ * * SCU90[5:4]=00: disable
91+ * * SCU90[5:4]=01: 18 bits (R6/G6/B6) video mode.
92+ * * SCU90[5:4]=10: 24 bits (R8/G8/B8) video mode.
93+ * * SCU90[5:4]=11: 30 bits (R10/G10/B10) video mode.
94+ *
95+ * Re-writing:
96+ *
97+ * -----+---------+-----------+------------------------------+-----------+---------------+----------
98+ * T5 GPIOL1 VPIDE (SCU90[5:4]=1 & SCU84[17]=1) NDCD1 SCU84[17]=1 GPIOL1
99+ * | (SCU90[5:4]=2 & SCU84[17]=1)
100+ * | (SCU90[5:4]=3 & SCU84[17]=1)
101+ * -----+---------+-----------+------------------------------+-----------+---------------+----------
102+ *
103+ * For reference the SCU84[17] bit configure the "UART1 NDCD1 or Video VPIDE
104+ * function pin", where the signal itself is determined by whether SCU94[5:4]
105+ * is disabled or in one of the 18, 24 or 30bit video modes.
106+ *
107+ * Other video-input-related pins require an explicit state in SCU90[5:4], e.g.
108+ * W1 and U5:
109+ *
110+ * -----+---------+-----------+------------------------------+-----------+---------------+----------
111+ * W1 GPIOL6 VPIB0 SCU90[5:4]=3 & SCU84[22]=1 TXD1 SCU84[22]=1 GPIOL6
112+ * U5 GPIOL7 VPIB1 SCU90[5:4]=3 & SCU84[23]=1 RXD1 SCU84[23]=1 GPIOL7
113+ * -----+---------+-----------+------------------------------+-----------+---------------+----------
114+ *
115+ * The examples of T5 and W1 are particularly fertile, as they also demonstrate
116+ * that despite operating as part of the video input bus each signal needs to
117+ * be enabled individually via it's own SCU84 (in the cases of T5 and W1)
118+ * register bit. This is a little crazy if the bus doesn't have optional
119+ * signals, but is used to decent effect with some of the UARTs where not all
120+ * signals are required. However, this isn't done consistently - UART1 is
121+ * enabled on a per-pin basis, and by contrast, all signals for UART6 are
122+ * enabled by a single bit.
123+ *
124+ * Further, the high and low priority signals listed in the table above share
125+ * a configuration bit. The VPI signals should operate in concert in a single
126+ * function, but the UART signals should retain the ability to be configured
127+ * independently. This pushes the implementation down the path of tagging a
128+ * signal's expressions with the function they participate in, rather than
129+ * defining masks affecting multiple signals per function. The latter approach
130+ * fails in this instance where applying the configuration for the UART pin of
131+ * interest will stomp on the state of other UART signals when disabling the
132+ * VPI functions on the current pin.
133+ *
134+ * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
135+ * -----+------------+-----------+---------------------------+-----------+---------------+------------
136+ * A12 RGMII1TXCK GPIOT0 SCUA0[0]=1 RMII1TXEN Strap[6]=0 RGMII1TXCK
137+ * B12 RGMII1TXCTL GPIOT1 SCUA0[1]=1 – Strap[6]=0 RGMII1TXCTL
138+ * -----+------------+-----------+---------------------------+-----------+---------------+------------
139+ *
140+ * A12 demonstrates that the "Other" signal isn't always GPIO - in this case
141+ * GPIOT0 is a high-priority signal and RGMII1TXCK is Other. Thus, GPIO
142+ * should be treated like any other signal type with full function expression
143+ * requirements, and not assumed to be the default case. Separately, GPIOT0 and
144+ * GPIOT1's signal descriptor bits are distinct, therefore we must iterate all
145+ * pins in the function's group to disable the higher-priority signals such
146+ * that the signal for the function of interest is correctly enabled.
147+ *
148+ * Finally, three priority levels aren't always enough; the AST2500 brings with
149+ * it 18 pins of five priority levels, however the 18 pins only use three of
150+ * the five priority levels.
151+ *
152+ * Ultimately the requirement to control pins in the examples above drive the
153+ * design:
154+ *
155+ * * Pins provide signals according to functions activated in the mux
156+ * configuration
157+ *
158+ * * Pins provide up to five signal types in a priority order
159+ *
160+ * * For priorities levels defined on a pin, each priority provides one signal
161+ *
162+ * * Enabling lower priority signals requires higher priority signals be
163+ * disabled
164+ *
165+ * * A function represents a set of signals; functions are distinct if their
166+ * sets of signals are not equal
167+ *
168+ * * Signals participate in one or more functions
169+ *
170+ * * A function is described by an expression of one or more signal
171+ * descriptors, which compare bit values in a register
172+ *
173+ * * A signal expression is the smallest set of signal descriptors whose
174+ * comparisons must evaluate 'true' for a signal to be enabled on a pin.
175+ *
176+ * * A signal participating in a function is active on a pin if evaluating all
177+ * signal descriptors in the pin's signal expression for the function yields
178+ * a 'true' result
179+ *
180+ * * A signal at a given priority on a given pin is active if any of the
181+ * functions in which the signal participates are active, and no higher
182+ * priority signal on the pin is active
183+ *
184+ * * GPIO is configured per-pin
185+ *
186+ * And so:
187+ *
188+ * * To disable a signal, any function(s) activating the signal must be
189+ * disabled
190+ *
191+ * * Each pin must know the signal expressions of functions in which it
192+ * participates, for the purpose of enabling the Other function. This is done
193+ * by deactivating all functions that activate higher priority signals on the
194+ * pin.
195+ *
196+ * As a concrete example:
197+ *
198+ * * T5 provides three signals types: VPIDE, NDCD1 and GPIO
199+ *
200+ * * The VPIDE signal participates in 3 functions: VPI18, VPI24 and VPI30
201+ *
202+ * * The NDCD1 signal participates in just its own NDCD1 function
203+ *
204+ * * VPIDE is high priority, NDCD1 is low priority, and GPIOL1 is the least
205+ * prioritised
206+ *
207+ * * The prerequisit for activating the NDCD1 signal is that the VPI18, VPI24
208+ * and VPI30 functions all be disabled
209+ *
210+ * * Similarly, all of VPI18, VPI24, VPI30 and NDCD1 functions must be disabled
211+ * to provide GPIOL6
212+ *
213+ * Considerations
214+ * --------------
215+ *
216+ * If pinctrl allows us to allocate a pin we can configure a function without
217+ * concern for the function of already allocated pins, if pin groups are
218+ * created with respect to the SoC functions in which they participate. This is
219+ * intuitive, but it did not feel obvious from the bit/pin relationships.
220+ *
221+ * Conversely, failing to allocate all pins in a group indicates some bits (as
222+ * well as pins) required for the group's configuration will already be in use,
223+ * likely in a way that's inconsistent with the requirements of the failed
224+ * group.
225+ *
226+ * Implementation
227+ * --------------
228+ *
229+ * Beyond the documentation below the various structures and helper macros that
230+ * allow the implementation to hang together are defined. The macros are fairly
231+ * dense, so below we walk through some raw examples of the configuration
232+ * tables in an effort to clarify the concepts.
233+ *
234+ * The complexity of configuring the mux combined with the scale of the pins
235+ * and functions was a concern, so the table design along with the macro jungle
236+ * is an attempt to address it. The rough principles of the approach are:
237+ *
238+ * 1. Use a data-driven solution rather than embedding state into code
239+ * 2. Minimise editing to the specifics of the given mux configuration
240+ * 3. Detect as many errors as possible at compile time
241+ *
242+ * Addressing point 3 leads to naming of symbols in terms of the four
243+ * properties associated with a given mux configuration: The pin, the signal,
244+ * the group and the function. In this way copy/paste errors cause duplicate
245+ * symbols to be defined, which prevents successful compilation. Failing to
246+ * properly parent the tables leads to unused symbol warnings, and use of
247+ * designated initialisers and additional warnings ensures that there are
248+ * no override errors in the pin, group and function arrays.
249+ *
250+ * Addressing point 2 drives the development of the macro jungle, as it
251+ * centralises the definition noise at the cost of taking some time to
252+ * understand.
253+ *
254+ * Here's a complete, concrete "pre-processed" example of the table structures
255+ * used to describe the D6 ball from the examples above:
256+ *
257+ * ```
258+ * static const struct aspeed_sig_desc sig_descs_MAC1LINK_MAC1LINK[] = {
259+ * {
260+ * .ip = ASPEED_IP_SCU,
261+ * .reg = 0x80,
262+ * .mask = BIT(0),
263+ * .enable = 1,
264+ * .disable = 0
265+ * },
266+ * };
267+ *
268+ * static const struct aspeed_sig_expr sig_expr_MAC1LINK_MAC1LINK = {
269+ * .signal = "MAC1LINK",
270+ * .function = "MAC1LINK",
271+ * .ndescs = ARRAY_SIZE(sig_descs_MAC1LINK_MAC1LINK),
272+ * .descs = &(sig_descs_MAC1LINK_MAC1LINK)[0],
273+ * };
274+ *
275+ * static const struct aspeed_sig_expr *sig_exprs_MAC1LINK_MAC1LINK[] = {
276+ * &sig_expr_MAC1LINK_MAC1LINK,
277+ * NULL,
278+ * };
279+ *
280+ * static const struct aspeed_sig_desc sig_descs_GPIOA0_GPIOA0[] = { };
281+ *
282+ * static const struct aspeed_sig_expr sig_expr_GPIOA0_GPIOA0 = {
283+ * .signal = "GPIOA0",
284+ * .function = "GPIOA0",
285+ * .ndescs = ARRAY_SIZE(sig_descs_GPIOA0_GPIOA0),
286+ * .descs = &(sig_descs_GPIOA0_GPIOA0)[0],
287+ * };
288+ *
289+ * static const struct aspeed_sig_expr *sig_exprs_GPIOA0_GPIOA0[] = {
290+ * &sig_expr_GPIOA0_GPIOA0,
291+ * NULL
292+ * };
293+ *
294+ * static const struct aspeed_sig_expr **pin_exprs_0[] = {
295+ * sig_exprs_MAC1LINK_MAC1LINK,
296+ * sig_exprs_GPIOA0_GPIOA0,
297+ * NULL
298+ * };
299+ *
300+ * static const struct aspeed_pin_desc pin_0 = { "0", (&pin_exprs_0[0]) };
301+ * static const int group_pins_MAC1LINK[] = { 0 };
302+ * static const char *func_groups_MAC1LINK[] = { "MAC1LINK" };
303+ *
304+ * static struct pinctrl_pin_desc aspeed_g4_pins[] = {
305+ * [0] = { .number = 0, .name = "D6", .drv_data = &pin_0 },
306+ * };
307+ *
308+ * static const struct aspeed_pin_group aspeed_g4_groups[] = {
309+ * {
310+ * .name = "MAC1LINK",
311+ * .pins = &(group_pins_MAC1LINK)[0],
312+ * .npins = ARRAY_SIZE(group_pins_MAC1LINK),
313+ * },
314+ * };
315+ *
316+ * static const struct aspeed_pin_function aspeed_g4_functions[] = {
317+ * {
318+ * .name = "MAC1LINK",
319+ * .groups = &func_groups_MAC1LINK[0],
320+ * .ngroups = ARRAY_SIZE(func_groups_MAC1LINK),
321+ * },
322+ * };
323+ * ```
324+ *
325+ * At the end of the day much of the above code is compressed into the
326+ * following two lines:
327+ *
328+ * ```
329+ * #define D6 0
330+ * SSSF_PIN_DECL(D6, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
331+ * ```
332+ *
333+ * The two examples below show just the differences from the example above.
334+ *
335+ * Ball E18 demonstrates a function, EXTRST, that requires multiple descriptors
336+ * be set for it to be muxed:
337+ *
338+ * ```
339+ * static const struct aspeed_sig_desc sig_descs_EXTRST_EXTRST[] = {
340+ * {
341+ * .ip = ASPEED_IP_SCU,
342+ * .reg = 0x3C,
343+ * .mask = BIT(3),
344+ * .enable = 1,
345+ * .disable = 0
346+ * },
347+ * {
348+ * .ip = ASPEED_IP_SCU,
349+ * .reg = 0x80,
350+ * .mask = BIT(15),
351+ * .enable = 1,
352+ * .disable = 0
353+ * },
354+ * {
355+ * .ip = ASPEED_IP_SCU,
356+ * .reg = 0x90,
357+ * .mask = BIT(31),
358+ * .enable = 0,
359+ * .disable = 1
360+ * },
361+ * };
362+ *
363+ * static const struct aspeed_sig_expr sig_expr_EXTRST_EXTRST = {
364+ * .signal = "EXTRST",
365+ * .function = "EXTRST",
366+ * .ndescs = ARRAY_SIZE(sig_descs_EXTRST_EXTRST),
367+ * .descs = &(sig_descs_EXTRST_EXTRST)[0],
368+ * };
369+ * ...
370+ * ```
371+ *
372+ * For ball E19, we have multiple functions enabling a single signal, LPCRST#.
373+ * The data structures look like:
374+ *
375+ * static const struct aspeed_sig_desc sig_descs_LPCRST_LPCRST[] = {
376+ * {
377+ * .ip = ASPEED_IP_SCU,
378+ * .reg = 0x80,
379+ * .mask = BIT(12),
380+ * .enable = 1,
381+ * .disable = 0
382+ * },
383+ * };
384+ *
385+ * static const struct aspeed_sig_expr sig_expr_LPCRST_LPCRST = {
386+ * .signal = "LPCRST",
387+ * .function = "LPCRST",
388+ * .ndescs = ARRAY_SIZE(sig_descs_LPCRST_LPCRST),
389+ * .descs = &(sig_descs_LPCRST_LPCRST)[0],
390+ * };
391+ *
392+ * static const struct aspeed_sig_desc sig_descs_LPCRST_LPCRSTS[] = {
393+ * {
394+ * .ip = ASPEED_IP_SCU,
395+ * .reg = 0x70,
396+ * .mask = BIT(14),
397+ * .enable = 1,
398+ * .disable = 0
399+ * },
400+ * };
401+ *
402+ * static const struct aspeed_sig_expr sig_expr_LPCRST_LPCRSTS = {
403+ * .signal = "LPCRST",
404+ * .function = "LPCRSTS",
405+ * .ndescs = ARRAY_SIZE(sig_descs_LPCRST_LPCRSTS),
406+ * .descs = &(sig_descs_LPCRST_LPCRSTS)[0],
407+ * };
408+ *
409+ * static const struct aspeed_sig_expr *sig_exprs_LPCRST_LPCRST[] = {
410+ * &sig_expr_LPCRST_LPCRST,
411+ * &sig_expr_LPCRST_LPCRSTS,
412+ * NULL,
413+ * };
414+ * ...
415+ * ```
416+ *
417+ * Both expressions listed in the sig_exprs_LPCRST_LPCRST array need to be set
418+ * to disabled for the associated GPIO to be muxed.
419+ *
420+ */
421+
422+#define ASPEED_IP_SCU 0
423+#define ASPEED_IP_GFX 1
424+#define ASPEED_IP_LPC 2
425+#define ASPEED_NR_PINMUX_IPS 3
426+
427+ /**
428+ * A signal descriptor, which describes the register, bits and the
429+ * enable/disable values that should be compared or written.
430+ *
431+ * @ip: The IP block identifier, used as an index into the regmap array in
432+ * struct aspeed_pinctrl_data
433+ * @reg: The register offset with respect to the base address of the IP block
434+ * @mask: The mask to apply to the register. The lowest set bit of the mask is
435+ * used to derive the shift value.
436+ * @enable: The value that enables the function. Value should be in the LSBs,
437+ * not at the position of the mask.
438+ * @disable: The value that disables the function. Value should be in the
439+ * LSBs, not at the position of the mask.
440+ */
441+struct aspeed_sig_desc {
442+ unsigned int ip;
443+ unsigned int reg;
444+ u32 mask;
445+ u32 enable;
446+ u32 disable;
447+};
448+
449+/**
450+ * Describes a signal expression. The expression is evaluated by ANDing the
451+ * evaluation of the descriptors.
452+ *
453+ * @signal: The signal name for the priority level on the pin. If the signal
454+ * type is GPIO, then the signal name must begin with the string
455+ * "GPIO", e.g. GPIOA0, GPIOT4 etc.
456+ * @function: The name of the function the signal participates in for the
457+ * associated expression
458+ * @ndescs: The number of signal descriptors in the expression
459+ * @descs: Pointer to an array of signal descriptors that comprise the
460+ * function expression
461+ */
462+struct aspeed_sig_expr {
463+ const char *signal;
464+ const char *function;
465+ int ndescs;
466+ const struct aspeed_sig_desc *descs;
467+};
468+
469+/**
470+ * A struct capturing the list of expressions enabling signals at each priority
471+ * for a given pin. The signal configuration for a priority level is evaluated
472+ * by ORing the evaluation of the signal expressions in the respective
473+ * priority's list.
474+ *
475+ * @name: A name for the pin
476+ * @prios: A pointer to an array of expression list pointers
477+ *
478+ */
479+struct aspeed_pin_desc {
480+ const char *name;
481+ const struct aspeed_sig_expr ***prios;
482+};
483+
484+/* Macro hell */
485+
486+#define SIG_DESC_IP_BIT(ip, reg, idx, val) \
487+ { ip, reg, BIT_MASK(idx), val, (((val) + 1) & 1) }
488+
489+/**
490+ * Short-hand macro for describing an SCU descriptor enabled by the state of
491+ * one bit. The disable value is derived.
492+ *
493+ * @reg: The signal's associated register, offset from base
494+ * @idx: The signal's bit index in the register
495+ * @val: The value (0 or 1) that enables the function
496+ */
497+#define SIG_DESC_BIT(reg, idx, val) \
498+ SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, val)
499+
500+#define SIG_DESC_IP_SET(ip, reg, idx) SIG_DESC_IP_BIT(ip, reg, idx, 1)
501+
502+/**
503+ * A further short-hand macro expanding to an SCU descriptor enabled by a set
504+ * bit.
505+ *
506+ * @reg: The register, offset from base
507+ * @idx: The bit index in the register
508+ */
509+#define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1)
510+
511+#define SIG_DESC_LIST_SYM(sig, func) sig_descs_ ## sig ## _ ## func
512+#define SIG_DESC_LIST_DECL(sig, func, ...) \
513+ static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, func)[] = \
514+ { __VA_ARGS__ }
515+
516+#define SIG_EXPR_SYM(sig, func) sig_expr_ ## sig ## _ ## func
517+#define SIG_EXPR_DECL_(sig, func) \
518+ static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, func) = \
519+ { \
520+ .signal = #sig, \
521+ .function = #func, \
522+ .ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, func)), \
523+ .descs = &(SIG_DESC_LIST_SYM(sig, func))[0], \
524+ }
525+
526+/**
527+ * Declare a signal expression.
528+ *
529+ * @sig: A macro symbol name for the signal (is subjected to stringification
530+ * and token pasting)
531+ * @func: The function in which the signal is participating
532+ * @...: Signal descriptors that define the signal expression
533+ *
534+ * For example, the following declares the ROMD8 signal for the ROM16 function:
535+ *
536+ * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
537+ *
538+ * And with multiple signal descriptors:
539+ *
540+ * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
541+ * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
542+ */
543+#define SIG_EXPR_DECL(sig, func, ...) \
544+ SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \
545+ SIG_EXPR_DECL_(sig, func)
546+
547+/**
548+ * Declare a pointer to a signal expression
549+ *
550+ * @sig: The macro symbol name for the signal (subjected to token pasting)
551+ * @func: The macro symbol name for the function (subjected to token pasting)
552+ */
553+#define SIG_EXPR_PTR(sig, func) (&SIG_EXPR_SYM(sig, func))
554+
555+#define SIG_EXPR_LIST_SYM(sig) sig_exprs_ ## sig
556+
557+/**
558+ * Declare a signal expression list for reference in a struct aspeed_pin_prio.
559+ *
560+ * @sig: A macro symbol name for the signal (is subjected to token pasting)
561+ * @...: Signal expression structure pointers (use SIG_EXPR_PTR())
562+ *
563+ * For example, the 16-bit ROM bus can be enabled by one of two possible signal
564+ * expressions:
565+ *
566+ * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
567+ * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
568+ * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
569+ * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
570+ * SIG_EXPR_PTR(ROMD8, ROM16S));
571+ */
572+#define SIG_EXPR_LIST_DECL(sig, ...) \
573+ static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig)[] = \
574+ { __VA_ARGS__, NULL }
575+
576+/**
577+ * A short-hand macro for declaring a function expression and an expression
578+ * list with a single function.
579+ *
580+ * @func: A macro symbol name for the function (is subjected to token pasting)
581+ * @...: Function descriptors that define the function expression
582+ *
583+ * For example, signal NCTS6 participates in its own function with one group:
584+ *
585+ * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
586+ */
587+#define SIG_EXPR_LIST_DECL_SINGLE(sig, func, ...) \
588+ SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \
589+ SIG_EXPR_DECL_(sig, func); \
590+ SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, func))
591+
592+#define SIG_EXPR_LIST_DECL_DUAL(sig, f0, f1) \
593+ SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, f0), SIG_EXPR_PTR(sig, f1))
594+
595+#define SIG_EXPR_LIST_PTR(sig) (&SIG_EXPR_LIST_SYM(sig)[0])
596+
597+#define PIN_EXPRS_SYM(pin) pin_exprs_ ## pin
598+#define PIN_EXPRS_PTR(pin) (&PIN_EXPRS_SYM(pin)[0])
599+#define PIN_SYM(pin) pin_ ## pin
600+
601+#define MS_PIN_DECL_(pin, ...) \
602+ static const struct aspeed_sig_expr **PIN_EXPRS_SYM(pin)[] = \
603+ { __VA_ARGS__, NULL }; \
604+ static const struct aspeed_pin_desc PIN_SYM(pin) = \
605+ { #pin, PIN_EXPRS_PTR(pin) }
606+
607+/**
608+ * Declare a multi-signal pin
609+ *
610+ * @pin: The pin number
611+ * @other: Macro name for "other" functionality (subjected to stringification)
612+ * @high: Macro name for the highest priority signal functions
613+ * @low: Macro name for the low signal functions
614+ *
615+ * For example:
616+ *
617+ * #define A8 56
618+ * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
619+ * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
620+ * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
621+ * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
622+ * SIG_EXPR_PTR(ROMD8, ROM16S));
623+ * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
624+ * MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6);
625+ */
626+#define MS_PIN_DECL(pin, other, high, low) \
627+ SIG_EXPR_LIST_DECL_SINGLE(other, other); \
628+ MS_PIN_DECL_(pin, \
629+ SIG_EXPR_LIST_PTR(high), \
630+ SIG_EXPR_LIST_PTR(low), \
631+ SIG_EXPR_LIST_PTR(other))
632+
633+#define PIN_GROUP_SYM(func) pins_ ## func
634+#define FUNC_GROUP_SYM(func) groups_ ## func
635+#define FUNC_GROUP_DECL(func, ...) \
636+ static const int PIN_GROUP_SYM(func)[] = { __VA_ARGS__ }; \
637+ static const char *FUNC_GROUP_SYM(func)[] = { #func }
638+
639+/**
640+ * Declare a single signal pin
641+ *
642+ * @pin: The pin number
643+ * @other: Macro name for "other" functionality (subjected to stringification)
644+ * @sig: Macro name for the signal (subjected to stringification)
645+ *
646+ * For example:
647+ *
648+ * #define E3 80
649+ * SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
650+ * SS_PIN_DECL(E3, GPIOK0, SCL5);
651+ */
652+#define SS_PIN_DECL(pin, other, sig) \
653+ SIG_EXPR_LIST_DECL_SINGLE(other, other); \
654+ MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other))
655+
656+/**
657+ * Single signal, single function pin declaration
658+ *
659+ * @pin: The pin number
660+ * @other: Macro name for "other" functionality (subjected to stringification)
661+ * @sig: Macro name for the signal (subjected to stringification)
662+ * @...: Signal descriptors that define the function expression
663+ *
664+ * For example:
665+ *
666+ * SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2));
667+ */
668+#define SSSF_PIN_DECL(pin, other, sig, ...) \
669+ SIG_EXPR_LIST_DECL_SINGLE(sig, sig, __VA_ARGS__); \
670+ SIG_EXPR_LIST_DECL_SINGLE(other, other); \
671+ MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other)); \
672+ FUNC_GROUP_DECL(sig, pin)
673+
674+#define GPIO_PIN_DECL(pin, gpio) \
675+ SIG_EXPR_LIST_DECL_SINGLE(gpio, gpio); \
676+ MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(gpio))
677+
678+struct aspeed_pin_group {
679+ const char *name;
680+ const unsigned int *pins;
681+ const unsigned int npins;
682+};
683+
684+#define ASPEED_PINCTRL_GROUP(name_) { \
685+ .name = #name_, \
686+ .pins = &(PIN_GROUP_SYM(name_))[0], \
687+ .npins = ARRAY_SIZE(PIN_GROUP_SYM(name_)), \
688+}
689+
690+struct aspeed_pin_function {
691+ const char *name;
692+ const char *const *groups;
693+ unsigned int ngroups;
694+};
695+
696+#define ASPEED_PINCTRL_FUNC(name_, ...) { \
697+ .name = #name_, \
698+ .groups = &FUNC_GROUP_SYM(name_)[0], \
699+ .ngroups = ARRAY_SIZE(FUNC_GROUP_SYM(name_)), \
700+}
701+
702+struct aspeed_pinmux_data;
703+
704+struct aspeed_pinmux_ops {
705+ int (*set)(const struct aspeed_pinmux_data *ctx,
706+ const struct aspeed_sig_expr *expr, bool enabled);
707+};
708+
709+struct aspeed_pinmux_data {
710+ struct regmap *maps[ASPEED_NR_PINMUX_IPS];
711+
712+ const struct aspeed_pinmux_ops *ops;
713+
714+ const struct aspeed_pin_group *groups;
715+ const unsigned int ngroups;
716+
717+ const struct aspeed_pin_function *functions;
718+ const unsigned int nfunctions;
719+};
720+
721+int aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc, bool enabled,
722+ struct regmap *map);
723+
724+int aspeed_sig_expr_eval(const struct aspeed_pinmux_data *ctx,
725+ const struct aspeed_sig_expr *expr,
726+ bool enabled);
727+
728+static inline int aspeed_sig_expr_set(const struct aspeed_pinmux_data *ctx,
729+ const struct aspeed_sig_expr *expr,
730+ bool enabled)
731+{
732+ return ctx->ops->set(ctx, expr, enabled);
733+}
734+
735+#endif /* ASPEED_PINMUX_H */
drivers/pinctrl/bcm/Kconfig+5−1
@@ -18,11 +18,15 @@ config PINCTRL_BCM281XX · 17 unmodified lines
1818 framework. GPIO is provided by a separate GPIO driver.
1919
2020 config PINCTRL_BCM2835
21− bool
21+ bool "Broadcom BCM2835 GPIO (with PINCONF) driver"
22+ depends on OF && (ARCH_BCM2835 || ARCH_BRCMSTB || COMPILE_TEST)
2223 select PINMUX
2324 select PINCONF
2425 select GENERIC_PINCONF
2526 select GPIOLIB_IRQCHIP
27+ default ARCH_BCM2835 || ARCH_BRCMSTB
28+ help
29+ Say Y here to enable the Broadcom BCM2835 GPIO driver.
2630
2731 config PINCTRL_IPROC_GPIO
2832 bool "Broadcom iProc GPIO (with PINCONF) driver"
drivers/pinctrl/bcm/pinctrl-ns2-mux.c+2−0
@@ -1048,6 +1048,8 @@ static int ns2_pinmux_probe(struct platform_device *pdev) · 1047 unmodified lines
10481048 return PTR_ERR(pinctrl->base0);
10491049
10501050 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1051+ if (!res)
1052+ return -EINVAL;
10511053 pinctrl->base1 = devm_ioremap_nocache(&pdev->dev, res->start,
10521054 resource_size(res));
10531055 if (!pinctrl->base1) {
drivers/pinctrl/cirrus/pinctrl-cs47l35.c+1−5
@@ -1,12 +1,8 @@
1−// SPDX-License-Identifier: GPL-2.0
1+// SPDX-License-Identifier: GPL-2.0-only
22 /*
33 * Pinctrl for Cirrus Logic CS47L35
44 *
55 * Copyright (C) 2016-2017 Cirrus Logic
6− *
7− * This program is free software; you can redistribute it and/or modify
8− * it under the terms of the GNU General Public License as published by the
9− * Free Software Foundation; version 2.
106 */
117
128 #include <linux/err.h>
drivers/pinctrl/cirrus/pinctrl-cs47l85.c+1−5
@@ -1,12 +1,8 @@
1−// SPDX-License-Identifier: GPL-2.0
1+// SPDX-License-Identifier: GPL-2.0-only
22 /*
33 * Pinctrl for Cirrus Logic CS47L85
44 *
55 * Copyright (C) 2016-2017 Cirrus Logic
6− *
7− * This program is free software; you can redistribute it and/or modify
8− * it under the terms of the GNU General Public License as published by the
9− * Free Software Foundation; version 2.
106 */
117
128 #include <linux/err.h>
drivers/pinctrl/cirrus/pinctrl-cs47l90.c+1−5
@@ -1,12 +1,8 @@
1−// SPDX-License-Identifier: GPL-2.0
1+// SPDX-License-Identifier: GPL-2.0-only
22 /*
33 * Pinctrl for Cirrus Logic CS47L90
44 *
55 * Copyright (C) 2016-2017 Cirrus Logic
6− *
7− * This program is free software; you can redistribute it and/or modify
8− * it under the terms of the GNU General Public License as published by the
9− * Free Software Foundation; version 2.
106 */
117
128 #include <linux/err.h>
drivers/pinctrl/cirrus/pinctrl-madera-core.c+1−5
@@ -1,12 +1,8 @@
1−// SPDX-License-Identifier: GPL-2.0
1+// SPDX-License-Identifier: GPL-2.0-only
22 /*
33 * Pinctrl for Cirrus Logic Madera codecs
44 *
55 * Copyright (C) 2016-2018 Cirrus Logic
6− *
7− * This program is free software; you can redistribute it and/or modify
8− * it under the terms of the GNU General Public License as published by the
9− * Free Software Foundation; version 2.
106 */
117
128 #include <linux/err.h>
drivers/pinctrl/cirrus/pinctrl-madera.h+1−5
@@ -1,12 +1,8 @@
1−// SPDX-License-Identifier: GPL-2.0
1+/* SPDX-License-Identifier: GPL-2.0-only */
22 /*
33 * Pinctrl for Cirrus Logic Madera codecs
44 *
55 * Copyright (C) 2016-2017 Cirrus Logic
6− *
7− * This program is free software; you can redistribute it and/or modify
8− * it under the terms of the GNU General Public License as published by the
9− * Free Software Foundation; version 2.
106 */
117
128 #ifndef PINCTRL_MADERA_H
drivers/pinctrl/core.c+17−27
@@ -98,7 +98,7 @@ EXPORT_SYMBOL_GPL(pinctrl_dev_get_drvdata); · 97 unmodified lines
9898 */
9999 struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *devname)
100100 {
101− struct pinctrl_dev *pctldev = NULL;
101+ struct pinctrl_dev *pctldev;
102102
103103 if (!devname)
104104 return NULL;
@@ -177,29 +177,6 @@ const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin) · 72 unmodified lines
177177 return desc->name;
178178 }
179179
180−/**
181− * pin_is_valid() - check if pin exists on controller
182− * @pctldev: the pin control device to check the pin on
183− * @pin: pin to check, use the local pin controller index number
184− *
185− * This tells us whether a certain pin exist on a certain pin controller or
186− * not. Pin lists may be sparse, so some pins may not exist.
187− */
188−bool pin_is_valid(struct pinctrl_dev *pctldev, int pin)
189−{
190− struct pin_desc *pindesc;
191−
192− if (pin < 0)
193− return false;
194−
195− mutex_lock(&pctldev->mutex);
196− pindesc = pin_desc_get(pctldev, pin);
197− mutex_unlock(&pctldev->mutex);
198−
199− return pindesc != NULL;
200−}
201−EXPORT_SYMBOL_GPL(pin_is_valid);
202−
203180 /* Deletes a range of pin descriptors */
204181 static void pinctrl_free_pindescs(struct pinctrl_dev *pctldev,
205182 const struct pinctrl_pin_desc *pins,
@@ -311,7 +288,7 @@ static inline int gpio_to_pin(struct pinctrl_gpio_range *range, · 105 unmodified lines
311288 static struct pinctrl_gpio_range *
312289 pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio)
313290 {
314− struct pinctrl_gpio_range *range = NULL;
291+ struct pinctrl_gpio_range *range;
315292
316293 mutex_lock(&pctldev->mutex);
317294 /* Loop over the ranges */
@@ -391,7 +368,7 @@ static int pinctrl_get_device_gpio_range(unsigned gpio, · 73 unmodified lines
391368 struct pinctrl_dev **outdev,
392369 struct pinctrl_gpio_range **outrange)
393370 {
394− struct pinctrl_dev *pctldev = NULL;
371+ struct pinctrl_dev *pctldev;
395372
396373 mutex_lock(&pinctrldev_list_mutex);
397374
@@ -1215,6 +1192,15 @@ struct pinctrl_state *pinctrl_lookup_state(struct pinctrl *p, · 817 unmodified lines
12151192 }
12161193 EXPORT_SYMBOL_GPL(pinctrl_lookup_state);
12171194
1195+static void pinctrl_link_add(struct pinctrl_dev *pctldev,
1196+ struct device *consumer)
1197+{
1198+ if (pctldev->desc->link_consumers)
1199+ device_link_add(consumer, pctldev->dev,
1200+ DL_FLAG_PM_RUNTIME |
1201+ DL_FLAG_AUTOREMOVE_CONSUMER);
1202+}
1203+
12181204 /**
12191205 * pinctrl_commit_state() - select/activate/program a pinctrl state to HW
12201206 * @p: the pinctrl handle for the device that requests configuration
@@ -1260,6 +1246,10 @@ static int pinctrl_commit_state(struct pinctrl *p, struct pinctrl_state *state) · 39 unmodified lines
12601246 if (ret < 0) {
12611247 goto unapply_new_state;
12621248 }
1249+
1250+ /* Do not link hogs (circular dependency) */
1251+ if (p != setting->pctldev->p)
1252+ pinctrl_link_add(setting->pctldev, p->dev);
12631253 }
12641254
12651255 p->state = state;
@@ -1665,7 +1655,7 @@ DEFINE_SHOW_ATTRIBUTE(pinctrl_groups); · 399 unmodified lines
16651655 static int pinctrl_gpioranges_show(struct seq_file *s, void *what)
16661656 {
16671657 struct pinctrl_dev *pctldev = s->private;
1668− struct pinctrl_gpio_range *range = NULL;
1658+ struct pinctrl_gpio_range *range;
16691659
16701660 seq_puts(s, "GPIO ranges handled:\n");
16711661
drivers/pinctrl/freescale/Kconfig+7−0
@@ -130,6 +130,13 @@ config PINCTRL_IMX8MM · 129 unmodified lines
130130 help
131131 Say Y here to enable the imx8mm pinctrl driver
132132
133+config PINCTRL_IMX8MN
134+ bool "IMX8MN pinctrl driver"
135+ depends on ARCH_MXC && ARM64
136+ select PINCTRL_IMX
137+ help
138+ Say Y here to enable the imx8mn pinctrl driver
139+
133140 config PINCTRL_IMX8MQ
134141 bool "IMX8MQ pinctrl driver"
135142 depends on ARCH_MXC && ARM64
drivers/pinctrl/freescale/Makefile+1−0
@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o · 18 unmodified lines
1919 obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
2020 obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
2121 obj-$(CONFIG_PINCTRL_IMX8MM) += pinctrl-imx8mm.o
22+obj-$(CONFIG_PINCTRL_IMX8MN) += pinctrl-imx8mn.o
2223 obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o
2324 obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o
2425 obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
drivers/pinctrl/freescale/pinctrl-imx8mn.c+348−0
@@ -0,0 +1,348 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright 2018-2019 NXP
4+ */
5+
6+#include <linux/err.h>
7+#include <linux/init.h>
8+#include <linux/of.h>
9+#include <linux/pinctrl/pinctrl.h>
10+#include <linux/platform_device.h>
11+
12+#include "pinctrl-imx.h"
13+
14+enum imx8mn_pads {
15+ MX8MN_PAD_RESERVE0 = 0,
16+ MX8MN_PAD_RESERVE1 = 1,
17+ MX8MN_PAD_RESERVE2 = 2,
18+ MX8MN_PAD_RESERVE3 = 3,
19+ MX8MN_PAD_RESERVE4 = 4,
20+ MX8MN_PAD_RESERVE5 = 5,
21+ MX8MN_PAD_RESERVE6 = 6,
22+ MX8MN_PAD_RESERVE7 = 7,
23+ MX8MN_IOMUXC_BOOT_MODE2 = 8,
24+ MX8MN_IOMUXC_BOOT_MODE3 = 9,
25+ MX8MN_IOMUXC_GPIO1_IO00 = 10,
26+ MX8MN_IOMUXC_GPIO1_IO01 = 11,
27+ MX8MN_IOMUXC_GPIO1_IO02 = 12,
28+ MX8MN_IOMUXC_GPIO1_IO03 = 13,
29+ MX8MN_IOMUXC_GPIO1_IO04 = 14,
30+ MX8MN_IOMUXC_GPIO1_IO05 = 15,
31+ MX8MN_IOMUXC_GPIO1_IO06 = 16,
32+ MX8MN_IOMUXC_GPIO1_IO07 = 17,
33+ MX8MN_IOMUXC_GPIO1_IO08 = 18,
34+ MX8MN_IOMUXC_GPIO1_IO09 = 19,
35+ MX8MN_IOMUXC_GPIO1_IO10 = 20,
36+ MX8MN_IOMUXC_GPIO1_IO11 = 21,
37+ MX8MN_IOMUXC_GPIO1_IO12 = 22,
38+ MX8MN_IOMUXC_GPIO1_IO13 = 23,
39+ MX8MN_IOMUXC_GPIO1_IO14 = 24,
40+ MX8MN_IOMUXC_GPIO1_IO15 = 25,
41+ MX8MN_IOMUXC_ENET_MDC = 26,
42+ MX8MN_IOMUXC_ENET_MDIO = 27,
43+ MX8MN_IOMUXC_ENET_TD3 = 28,
44+ MX8MN_IOMUXC_ENET_TD2 = 29,
45+ MX8MN_IOMUXC_ENET_TD1 = 30,
46+ MX8MN_IOMUXC_ENET_TD0 = 31,
47+ MX8MN_IOMUXC_ENET_TX_CTL = 32,
48+ MX8MN_IOMUXC_ENET_TXC = 33,
49+ MX8MN_IOMUXC_ENET_RX_CTL = 34,
50+ MX8MN_IOMUXC_ENET_RXC = 35,
51+ MX8MN_IOMUXC_ENET_RD0 = 36,
52+ MX8MN_IOMUXC_ENET_RD1 = 37,
53+ MX8MN_IOMUXC_ENET_RD2 = 38,
54+ MX8MN_IOMUXC_ENET_RD3 = 39,
55+ MX8MN_IOMUXC_SD1_CLK = 40,
56+ MX8MN_IOMUXC_SD1_CMD = 41,
57+ MX8MN_IOMUXC_SD1_DATA0 = 42,
58+ MX8MN_IOMUXC_SD1_DATA1 = 43,
59+ MX8MN_IOMUXC_SD1_DATA2 = 44,
60+ MX8MN_IOMUXC_SD1_DATA3 = 45,
61+ MX8MN_IOMUXC_SD1_DATA4 = 46,
62+ MX8MN_IOMUXC_SD1_DATA5 = 47,
63+ MX8MN_IOMUXC_SD1_DATA6 = 48,
64+ MX8MN_IOMUXC_SD1_DATA7 = 49,
65+ MX8MN_IOMUXC_SD1_RESET_B = 50,
66+ MX8MN_IOMUXC_SD1_STROBE = 51,
67+ MX8MN_IOMUXC_SD2_CD_B = 52,
68+ MX8MN_IOMUXC_SD2_CLK = 53,
69+ MX8MN_IOMUXC_SD2_CMD = 54,
70+ MX8MN_IOMUXC_SD2_DATA0 = 55,
71+ MX8MN_IOMUXC_SD2_DATA1 = 56,
72+ MX8MN_IOMUXC_SD2_DATA2 = 57,
73+ MX8MN_IOMUXC_SD2_DATA3 = 58,
74+ MX8MN_IOMUXC_SD2_RESET_B = 59,
75+ MX8MN_IOMUXC_SD2_WP = 60,
76+ MX8MN_IOMUXC_NAND_ALE = 61,
77+ MX8MN_IOMUXC_NAND_CE0 = 62,
78+ MX8MN_IOMUXC_NAND_CE1 = 63,
79+ MX8MN_IOMUXC_NAND_CE2 = 64,
80+ MX8MN_IOMUXC_NAND_CE3 = 65,
81+ MX8MN_IOMUXC_NAND_CLE = 66,
82+ MX8MN_IOMUXC_NAND_DATA00 = 67,
83+ MX8MN_IOMUXC_NAND_DATA01 = 68,
84+ MX8MN_IOMUXC_NAND_DATA02 = 69,
85+ MX8MN_IOMUXC_NAND_DATA03 = 70,
86+ MX8MN_IOMUXC_NAND_DATA04 = 71,
87+ MX8MN_IOMUXC_NAND_DATA05 = 72,
88+ MX8MN_IOMUXC_NAND_DATA06 = 73,
89+ MX8MN_IOMUXC_NAND_DATA07 = 74,
90+ MX8MN_IOMUXC_NAND_DQS = 75,
91+ MX8MN_IOMUXC_NAND_RE_B = 76,
92+ MX8MN_IOMUXC_NAND_READY_B = 77,
93+ MX8MN_IOMUXC_NAND_WE_B = 78,
94+ MX8MN_IOMUXC_NAND_WP_B = 79,
95+ MX8MN_IOMUXC_SAI5_RXFS = 80,
96+ MX8MN_IOMUXC_SAI5_RXC = 81,
97+ MX8MN_IOMUXC_SAI5_RXD0 = 82,
98+ MX8MN_IOMUXC_SAI5_RXD1 = 83,
99+ MX8MN_IOMUXC_SAI5_RXD2 = 84,
100+ MX8MN_IOMUXC_SAI5_RXD3 = 85,
101+ MX8MN_IOMUXC_SAI5_MCLK = 86,
102+ MX8MN_IOMUXC_SAI1_RXFS = 87,
103+ MX8MN_IOMUXC_SAI1_RXC = 88,
104+ MX8MN_IOMUXC_SAI1_RXD0 = 89,
105+ MX8MN_IOMUXC_SAI1_RXD1 = 90,
106+ MX8MN_IOMUXC_SAI1_RXD2 = 91,
107+ MX8MN_IOMUXC_SAI1_RXD3 = 92,
108+ MX8MN_IOMUXC_SAI1_RXD4 = 93,
109+ MX8MN_IOMUXC_SAI1_RXD5 = 94,
110+ MX8MN_IOMUXC_SAI1_RXD6 = 95,
111+ MX8MN_IOMUXC_SAI1_RXD7 = 96,
112+ MX8MN_IOMUXC_SAI1_TXFS = 97,
113+ MX8MN_IOMUXC_SAI1_TXC = 98,
114+ MX8MN_IOMUXC_SAI1_TXD0 = 99,
115+ MX8MN_IOMUXC_SAI1_TXD1 = 100,
116+ MX8MN_IOMUXC_SAI1_TXD2 = 101,
117+ MX8MN_IOMUXC_SAI1_TXD3 = 102,
118+ MX8MN_IOMUXC_SAI1_TXD4 = 103,
119+ MX8MN_IOMUXC_SAI1_TXD5 = 104,
120+ MX8MN_IOMUXC_SAI1_TXD6 = 105,
121+ MX8MN_IOMUXC_SAI1_TXD7 = 106,
122+ MX8MN_IOMUXC_SAI1_MCLK = 107,
123+ MX8MN_IOMUXC_SAI2_RXFS = 108,
124+ MX8MN_IOMUXC_SAI2_RXC = 109,
125+ MX8MN_IOMUXC_SAI2_RXD0 = 110,
126+ MX8MN_IOMUXC_SAI2_TXFS = 111,
127+ MX8MN_IOMUXC_SAI2_TXC = 112,
128+ MX8MN_IOMUXC_SAI2_TXD0 = 113,
129+ MX8MN_IOMUXC_SAI2_MCLK = 114,
130+ MX8MN_IOMUXC_SAI3_RXFS = 115,
131+ MX8MN_IOMUXC_SAI3_RXC = 116,
132+ MX8MN_IOMUXC_SAI3_RXD = 117,
133+ MX8MN_IOMUXC_SAI3_TXFS = 118,
134+ MX8MN_IOMUXC_SAI3_TXC = 119,
135+ MX8MN_IOMUXC_SAI3_TXD = 120,
136+ MX8MN_IOMUXC_SAI3_MCLK = 121,
137+ MX8MN_IOMUXC_SPDIF_TX = 122,
138+ MX8MN_IOMUXC_SPDIF_RX = 123,
139+ MX8MN_IOMUXC_SPDIF_EXT_CLK = 124,
140+ MX8MN_IOMUXC_ECSPI1_SCLK = 125,
141+ MX8MN_IOMUXC_ECSPI1_MOSI = 126,
142+ MX8MN_IOMUXC_ECSPI1_MISO = 127,
143+ MX8MN_IOMUXC_ECSPI1_SS0 = 128,
144+ MX8MN_IOMUXC_ECSPI2_SCLK = 129,
145+ MX8MN_IOMUXC_ECSPI2_MOSI = 130,
146+ MX8MN_IOMUXC_ECSPI2_MISO = 131,
147+ MX8MN_IOMUXC_ECSPI2_SS0 = 132,
148+ MX8MN_IOMUXC_I2C1_SCL = 133,
149+ MX8MN_IOMUXC_I2C1_SDA = 134,
150+ MX8MN_IOMUXC_I2C2_SCL = 135,
151+ MX8MN_IOMUXC_I2C2_SDA = 136,
152+ MX8MN_IOMUXC_I2C3_SCL = 137,
153+ MX8MN_IOMUXC_I2C3_SDA = 138,
154+ MX8MN_IOMUXC_I2C4_SCL = 139,
155+ MX8MN_IOMUXC_I2C4_SDA = 140,
156+ MX8MN_IOMUXC_UART1_RXD = 141,
157+ MX8MN_IOMUXC_UART1_TXD = 142,
158+ MX8MN_IOMUXC_UART2_RXD = 143,
159+ MX8MN_IOMUXC_UART2_TXD = 144,
160+ MX8MN_IOMUXC_UART3_RXD = 145,
161+ MX8MN_IOMUXC_UART3_TXD = 146,
162+ MX8MN_IOMUXC_UART4_RXD = 147,
163+ MX8MN_IOMUXC_UART4_TXD = 148,
164+};
165+
166+/* Pad names for the pinmux subsystem */
167+static const struct pinctrl_pin_desc imx8mn_pinctrl_pads[] = {
168+ IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE0),
169+ IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE1),
170+ IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE2),
171+ IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE3),
172+ IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE4),
173+ IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE5),
174+ IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE6),
175+ IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE7),
176+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_BOOT_MODE2),
177+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_BOOT_MODE3),
178+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO00),
179+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO01),
180+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO02),
181+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO03),
182+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO04),
183+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO05),
184+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO06),
185+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO07),
186+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO08),
187+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO09),
188+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO10),
189+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO11),
190+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO12),
191+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO13),
192+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO14),
193+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO15),
194+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_MDC),
195+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_MDIO),
196+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TD3),
197+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TD2),
198+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TD1),
199+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TD0),
200+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TX_CTL),
201+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TXC),
202+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RX_CTL),
203+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RXC),
204+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RD0),
205+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RD1),
206+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RD2),
207+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RD3),
208+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_CLK),
209+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_CMD),
210+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA0),
211+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA1),
212+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA2),
213+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA3),
214+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA4),
215+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA5),
216+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA6),
217+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA7),
218+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_RESET_B),
219+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_STROBE),
220+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_CD_B),
221+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_CLK),
222+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_CMD),
223+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_DATA0),
224+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_DATA1),
225+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_DATA2),
226+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_DATA3),
227+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_RESET_B),
228+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_WP),
229+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_ALE),
230+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_CE0),
231+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_CE1),
232+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_CE2),
233+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_CE3),
234+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_CLE),
235+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA00),
236+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA01),
237+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA02),
238+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA03),
239+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA04),
240+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA05),
241+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA06),
242+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA07),
243+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DQS),
244+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_RE_B),
245+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_READY_B),
246+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_WE_B),
247+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_WP_B),
248+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXFS),
249+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXC),
250+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXD0),
251+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXD1),
252+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXD2),
253+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXD3),
254+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_MCLK),
255+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXFS),
256+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXC),
257+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD0),
258+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD1),
259+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD2),
260+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD3),
261+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD4),
262+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD5),
263+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD6),
264+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD7),
265+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXFS),
266+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXC),
267+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD0),
268+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD1),
269+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD2),
270+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD3),
271+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD4),
272+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD5),
273+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD6),
274+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD7),
275+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_MCLK),
276+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_RXFS),
277+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_RXC),
278+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_RXD0),
279+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_TXFS),
280+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_TXC),
281+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_TXD0),
282+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_MCLK),
283+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_RXFS),
284+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_RXC),
285+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_RXD),
286+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_TXFS),
287+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_TXC),
288+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_TXD),
289+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_MCLK),
290+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SPDIF_TX),
291+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SPDIF_RX),
292+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_SPDIF_EXT_CLK),
293+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI1_SCLK),
294+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI1_MOSI),
295+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI1_MISO),
296+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI1_SS0),
297+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI2_SCLK),
298+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI2_MOSI),
299+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI2_MISO),
300+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI2_SS0),
301+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C1_SCL),
302+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C1_SDA),
303+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C2_SCL),
304+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C2_SDA),
305+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C3_SCL),
306+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C3_SDA),
307+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C4_SCL),
308+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C4_SDA),
309+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART1_RXD),
310+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART1_TXD),
311+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART2_RXD),
312+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART2_TXD),
313+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART3_RXD),
314+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART3_TXD),
315+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART4_RXD),
316+ IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART4_TXD),
317+};
318+
319+static struct imx_pinctrl_soc_info imx8mn_pinctrl_info = {
320+ .pins = imx8mn_pinctrl_pads,
321+ .npins = ARRAY_SIZE(imx8mn_pinctrl_pads),
322+ .gpr_compatible = "fsl,imx8mn-iomuxc-gpr",
323+};
324+
325+static const struct of_device_id imx8mn_pinctrl_of_match[] = {
326+ { .compatible = "fsl,imx8mn-iomuxc", .data = &imx8mn_pinctrl_info, },
327+ { /* sentinel */ }
328+};
329+
330+static int imx8mn_pinctrl_probe(struct platform_device *pdev)
331+{
332+ return imx_pinctrl_probe(pdev, &imx8mn_pinctrl_info);
333+}
334+
335+static struct platform_driver imx8mn_pinctrl_driver = {
336+ .driver = {
337+ .name = "imx8mn-pinctrl",
338+ .of_match_table = of_match_ptr(imx8mn_pinctrl_of_match),
339+ .suppress_bind_attrs = true,
340+ },
341+ .probe = imx8mn_pinctrl_probe,
342+};
343+
344+static int __init imx8mn_pinctrl_init(void)
345+{
346+ return platform_driver_register(&imx8mn_pinctrl_driver);
347+}
348+arch_initcall(imx8mn_pinctrl_init);
drivers/pinctrl/intel/pinctrl-baytrail.c+71−251
@@ -24,6 +24,8 @@ · 23 unmodified lines
2424 #include <linux/pinctrl/pinconf.h>
2525 #include <linux/pinctrl/pinconf-generic.h>
2626
27+#include "pinctrl-intel.h"
28+
2729 /* memory mapped register offsets */
2830 #define BYT_CONF0_REG 0x000
2931 #define BYT_CONF1_REG 0x004
@@ -35,6 +37,7 @@ · 5 unmodified lines
3537 /* BYT_CONF0_REG register bits */
3638 #define BYT_IODEN BIT(31)
3739 #define BYT_DIRECT_IRQ_EN BIT(27)
40+#define BYT_TRIG_MASK GENMASK(26, 24)
3841 #define BYT_TRIG_NEG BIT(26)
3942 #define BYT_TRIG_POS BIT(25)
4043 #define BYT_TRIG_LVL BIT(24)
@@ -43,31 +46,28 @@ · 2 unmodified lines
4346 #define BYT_GLITCH_F_SLOW_CLK BIT(17)
4447 #define BYT_GLITCH_F_FAST_CLK BIT(16)
4548 #define BYT_PULL_STR_SHIFT 9
46−#define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT)
49+#define BYT_PULL_STR_MASK GENMASK(10, 9)
4750 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
4851 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
4952 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
5053 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
5154 #define BYT_PULL_ASSIGN_SHIFT 7
52−#define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT)
55+#define BYT_PULL_ASSIGN_MASK GENMASK(8, 7)
5356 #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
5457 #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
55−#define BYT_PIN_MUX 0x07
58+#define BYT_PIN_MUX GENMASK(2, 0)
5659
5760 /* BYT_VAL_REG register bits */
61+#define BYT_DIR_MASK GENMASK(2, 1)
5862 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
5963 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
6064 #define BYT_LEVEL BIT(0)
6165
62−#define BYT_DIR_MASK (BIT(1) | BIT(2))
63−#define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24))
64−
65−#define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | \
66− BYT_PIN_MUX)
66+#define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX)
6767 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL)
6868
6969 /* BYT_DEBOUNCE_REG bits */
70−#define BYT_DEBOUNCE_PULSE_MASK 0x7
70+#define BYT_DEBOUNCE_PULSE_MASK GENMASK(2, 0)
7171 #define BYT_DEBOUNCE_PULSE_375US 1
7272 #define BYT_DEBOUNCE_PULSE_750US 2
7373 #define BYT_DEBOUNCE_PULSE_1500US 3
@@ -91,40 +91,13 @@ · 17 unmodified lines
9191 * does not find a match for the requested function.
9292 */
9393 #define BYT_DEFAULT_GPIO_MUX 0
94+#define BYT_ALTER_GPIO_MUX 1
9495
9596 struct byt_gpio_pin_context {
9697 u32 conf0;
9798 u32 val;
9899 };
99100
100−struct byt_simple_func_mux {
101− const char *name;
102− unsigned short func;
103−};
104−
105−struct byt_mixed_func_mux {
106− const char *name;
107− const unsigned short *func_values;
108−};
109−
110−struct byt_pingroup {
111− const char *name;
112− const unsigned int *pins;
113− size_t npins;
114− unsigned short has_simple_funcs;
115− union {
116− const struct byt_simple_func_mux *simple_funcs;
117− const struct byt_mixed_func_mux *mixed_funcs;
118− };
119− size_t nfuncs;
120−};
121−
122−struct byt_function {
123− const char *name;
124− const char * const *groups;
125− size_t ngroups;
126−};
127−
128101 struct byt_community {
129102 unsigned int pin_base;
130103 size_t npins;
@@ -132,47 +105,6 @@ struct byt_community { · 1 unmodified line
132105 void __iomem *reg_base;
133106 };
134107
135−#define SIMPLE_FUNC(n, f) \
136− { \
137− .name = (n), \
138− .func = (f), \
139− }
140−#define MIXED_FUNC(n, f) \
141− { \
142− .name = (n), \
143− .func_values = (f), \
144− }
145−
146−#define PIN_GROUP_SIMPLE(n, p, f) \
147− { \
148− .name = (n), \
149− .pins = (p), \
150− .npins = ARRAY_SIZE((p)), \
151− .has_simple_funcs = 1, \
152− { \
153− .simple_funcs = (f), \
154− }, \
155− .nfuncs = ARRAY_SIZE((f)), \
156− }
157−#define PIN_GROUP_MIXED(n, p, f) \
158− { \
159− .name = (n), \
160− .pins = (p), \
161− .npins = ARRAY_SIZE((p)), \
162− .has_simple_funcs = 0, \
163− { \
164− .mixed_funcs = (f), \
165− }, \
166− .nfuncs = ARRAY_SIZE((f)), \
167− }
168−
169−#define FUNCTION(n, g) \
170− { \
171− .name = (n), \
172− .groups = (g), \
173− .ngroups = ARRAY_SIZE((g)), \
174− }
175−
176108 #define COMMUNITY(p, n, map) \
177109 { \
178110 .pin_base = (p), \
@@ -184,9 +116,9 @@ struct byt_pinctrl_soc_data { · 5 unmodified lines
184116 const char *uid;
185117 const struct pinctrl_pin_desc *pins;
186118 size_t npins;
187− const struct byt_pingroup *groups;
119+ const struct intel_pingroup *groups;
188120 size_t ngroups;
189− const struct byt_function *functions;
121+ const struct intel_function *functions;
190122 size_t nfunctions;
191123 const struct byt_community *communities;
192124 size_t ncommunities;
@@ -326,20 +258,11 @@ static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = { · 133 unmodified lines
326258 /* SCORE groups */
327259 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
328260 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
329−static const struct byt_simple_func_mux byt_score_uart_mux[] = {
330− SIMPLE_FUNC("uart", 1),
331−};
332261
333262 static const unsigned int byt_score_pwm0_pins[] = { 94 };
334263 static const unsigned int byt_score_pwm1_pins[] = { 95 };
335−static const struct byt_simple_func_mux byt_score_pwm_mux[] = {
336− SIMPLE_FUNC("pwm", 1),
337−};
338264
339265 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
340−static const struct byt_simple_func_mux byt_score_spi_mux[] = {
341− SIMPLE_FUNC("spi", 1),
342−};
343266
344267 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
345268 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
@@ -348,50 +271,29 @@ static const unsigned int byt_score_i2c3_pins[] = { 84, 85 }; · 2 unmodified lines
348271 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
349272 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
350273 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
351−static const struct byt_simple_func_mux byt_score_i2c_mux[] = {
352− SIMPLE_FUNC("i2c", 1),
353−};
354274
355275 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
356276 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
357277 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
358−static const struct byt_simple_func_mux byt_score_ssp_mux[] = {
359− SIMPLE_FUNC("ssp", 1),
360−};
361278
362279 static const unsigned int byt_score_sdcard_pins[] = {
363280 7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
364281 };
365−static const unsigned short byt_score_sdcard_mux_values[] = {
282+static const unsigned int byt_score_sdcard_mux_values[] = {
366283 2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
367284 };
368−static const struct byt_mixed_func_mux byt_score_sdcard_mux[] = {
369− MIXED_FUNC("sdcard", byt_score_sdcard_mux_values),
370−};
371285
372286 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
373−static const struct byt_simple_func_mux byt_score_sdio_mux[] = {
374− SIMPLE_FUNC("sdio", 1),
375−};
376287
377288 static const unsigned int byt_score_emmc_pins[] = {
378289 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
379290 };
380−static const struct byt_simple_func_mux byt_score_emmc_mux[] = {
381− SIMPLE_FUNC("emmc", 1),
382−};
383291
384292 static const unsigned int byt_score_ilb_lpc_pins[] = {
385293 42, 43, 44, 45, 46, 47, 48, 49, 50,
386294 };
387−static const struct byt_simple_func_mux byt_score_lpc_mux[] = {
388− SIMPLE_FUNC("lpc", 1),
389−};
390295
391296 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
392−static const struct byt_simple_func_mux byt_score_sata_mux[] = {
393− SIMPLE_FUNC("sata", 1),
394−};
395297
396298 static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
397299 static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
@@ -399,70 +301,37 @@ static const unsigned int byt_score_plt_clk2_pins[] = { 98 }; · 1 unmodified line
399301 static const unsigned int byt_score_plt_clk3_pins[] = { 99 };
400302 static const unsigned int byt_score_plt_clk4_pins[] = { 100 };
401303 static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
402−static const struct byt_simple_func_mux byt_score_plt_clk_mux[] = {
403− SIMPLE_FUNC("plt_clk", 1),
404−};
405304
406305 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
407−static const struct byt_simple_func_mux byt_score_smbus_mux[] = {
408− SIMPLE_FUNC("smbus", 1),
409−};
410306
411−static const struct byt_pingroup byt_score_groups[] = {
412− PIN_GROUP_SIMPLE("uart1_grp",
413− byt_score_uart1_pins, byt_score_uart_mux),
414− PIN_GROUP_SIMPLE("uart2_grp",
415− byt_score_uart2_pins, byt_score_uart_mux),
416− PIN_GROUP_SIMPLE("pwm0_grp",
417− byt_score_pwm0_pins, byt_score_pwm_mux),
418− PIN_GROUP_SIMPLE("pwm1_grp",
419− byt_score_pwm1_pins, byt_score_pwm_mux),
420− PIN_GROUP_SIMPLE("ssp2_grp",
421− byt_score_ssp2_pins, byt_score_pwm_mux),
422− PIN_GROUP_SIMPLE("sio_spi_grp",
423− byt_score_sio_spi_pins, byt_score_spi_mux),
424− PIN_GROUP_SIMPLE("i2c5_grp",
425− byt_score_i2c5_pins, byt_score_i2c_mux),
426− PIN_GROUP_SIMPLE("i2c6_grp",
427− byt_score_i2c6_pins, byt_score_i2c_mux),
428− PIN_GROUP_SIMPLE("i2c4_grp",
429− byt_score_i2c4_pins, byt_score_i2c_mux),
430− PIN_GROUP_SIMPLE("i2c3_grp",
431− byt_score_i2c3_pins, byt_score_i2c_mux),
432− PIN_GROUP_SIMPLE("i2c2_grp",
433− byt_score_i2c2_pins, byt_score_i2c_mux),
434− PIN_GROUP_SIMPLE("i2c1_grp",
435− byt_score_i2c1_pins, byt_score_i2c_mux),
436− PIN_GROUP_SIMPLE("i2c0_grp",
437− byt_score_i2c0_pins, byt_score_i2c_mux),
438− PIN_GROUP_SIMPLE("ssp0_grp",
439− byt_score_ssp0_pins, byt_score_ssp_mux),
440− PIN_GROUP_SIMPLE("ssp1_grp",
441− byt_score_ssp1_pins, byt_score_ssp_mux),
442− PIN_GROUP_MIXED("sdcard_grp",
443− byt_score_sdcard_pins, byt_score_sdcard_mux),
444− PIN_GROUP_SIMPLE("sdio_grp",
445− byt_score_sdio_pins, byt_score_sdio_mux),
446− PIN_GROUP_SIMPLE("emmc_grp",
447− byt_score_emmc_pins, byt_score_emmc_mux),
448− PIN_GROUP_SIMPLE("lpc_grp",
449− byt_score_ilb_lpc_pins, byt_score_lpc_mux),
450− PIN_GROUP_SIMPLE("sata_grp",
451− byt_score_sata_pins, byt_score_sata_mux),
452− PIN_GROUP_SIMPLE("plt_clk0_grp",
453− byt_score_plt_clk0_pins, byt_score_plt_clk_mux),
454− PIN_GROUP_SIMPLE("plt_clk1_grp",
455− byt_score_plt_clk1_pins, byt_score_plt_clk_mux),
456− PIN_GROUP_SIMPLE("plt_clk2_grp",
457− byt_score_plt_clk2_pins, byt_score_plt_clk_mux),
458− PIN_GROUP_SIMPLE("plt_clk3_grp",
459− byt_score_plt_clk3_pins, byt_score_plt_clk_mux),
460− PIN_GROUP_SIMPLE("plt_clk4_grp",
461− byt_score_plt_clk4_pins, byt_score_plt_clk_mux),
462− PIN_GROUP_SIMPLE("plt_clk5_grp",
463− byt_score_plt_clk5_pins, byt_score_plt_clk_mux),
464− PIN_GROUP_SIMPLE("smbus_grp",
465− byt_score_smbus_pins, byt_score_smbus_mux),
307+static const struct intel_pingroup byt_score_groups[] = {
308+ PIN_GROUP("uart1_grp", byt_score_uart1_pins, 1),
309+ PIN_GROUP("uart2_grp", byt_score_uart2_pins, 1),
310+ PIN_GROUP("pwm0_grp", byt_score_pwm0_pins, 1),
311+ PIN_GROUP("pwm1_grp", byt_score_pwm1_pins, 1),
312+ PIN_GROUP("ssp2_grp", byt_score_ssp2_pins, 1),
313+ PIN_GROUP("sio_spi_grp", byt_score_sio_spi_pins, 1),
314+ PIN_GROUP("i2c5_grp", byt_score_i2c5_pins, 1),
315+ PIN_GROUP("i2c6_grp", byt_score_i2c6_pins, 1),
316+ PIN_GROUP("i2c4_grp", byt_score_i2c4_pins, 1),
317+ PIN_GROUP("i2c3_grp", byt_score_i2c3_pins, 1),
318+ PIN_GROUP("i2c2_grp", byt_score_i2c2_pins, 1),
319+ PIN_GROUP("i2c1_grp", byt_score_i2c1_pins, 1),
320+ PIN_GROUP("i2c0_grp", byt_score_i2c0_pins, 1),
321+ PIN_GROUP("ssp0_grp", byt_score_ssp0_pins, 1),
322+ PIN_GROUP("ssp1_grp", byt_score_ssp1_pins, 1),
323+ PIN_GROUP("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values),
324+ PIN_GROUP("sdio_grp", byt_score_sdio_pins, 1),
325+ PIN_GROUP("emmc_grp", byt_score_emmc_pins, 1),
326+ PIN_GROUP("lpc_grp", byt_score_ilb_lpc_pins, 1),
327+ PIN_GROUP("sata_grp", byt_score_sata_pins, 1),
328+ PIN_GROUP("plt_clk0_grp", byt_score_plt_clk0_pins, 1),
329+ PIN_GROUP("plt_clk1_grp", byt_score_plt_clk1_pins, 1),
330+ PIN_GROUP("plt_clk2_grp", byt_score_plt_clk2_pins, 1),
331+ PIN_GROUP("plt_clk3_grp", byt_score_plt_clk3_pins, 1),
332+ PIN_GROUP("plt_clk4_grp", byt_score_plt_clk4_pins, 1),
333+ PIN_GROUP("plt_clk5_grp", byt_score_plt_clk5_pins, 1),
334+ PIN_GROUP("smbus_grp", byt_score_smbus_pins, 1),
466335 };
467336
468337 static const char * const byt_score_uart_groups[] = {
@@ -496,10 +365,9 @@ static const char * const byt_score_gpio_groups[] = { · 27 unmodified lines
496365 "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
497366 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
498367 "plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
499−
500368 };
501369
502−static const struct byt_function byt_score_functions[] = {
370+static const struct intel_function byt_score_functions[] = {
503371 FUNCTION("uart", byt_score_uart_groups),
504372 FUNCTION("pwm", byt_score_pwm_groups),
505373 FUNCTION("ssp", byt_score_ssp_groups),
@@ -588,38 +456,30 @@ static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = { · 82 unmodified lines
588456 };
589457
590458 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
591−static const struct byt_simple_func_mux byt_sus_usb_oc_mux[] = {
592− SIMPLE_FUNC("usb", 0),
593− SIMPLE_FUNC("gpio", 1),
594−};
459+static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 };
460+static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 };
595461
596462 static const unsigned int byt_sus_usb_ulpi_pins[] = {
597463 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
598464 };
599−static const unsigned short byt_sus_usb_ulpi_mode_values[] = {
465+static const unsigned int byt_sus_usb_ulpi_mode_values[] = {
600466 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
601467 };
602−static const unsigned short byt_sus_usb_ulpi_gpio_mode_values[] = {
603− 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
604−};
605−static const struct byt_mixed_func_mux byt_sus_usb_ulpi_mux[] = {
606− MIXED_FUNC("usb", byt_sus_usb_ulpi_mode_values),
607− MIXED_FUNC("gpio", byt_sus_usb_ulpi_gpio_mode_values),
468+static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = {
469+ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
608470 };
609471
610472 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
611−static const struct byt_simple_func_mux byt_sus_pcu_spi_mux[] = {
612− SIMPLE_FUNC("spi", 0),
613− SIMPLE_FUNC("gpio", 1),
614−};
473+static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 };
474+static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 };
615475
616−static const struct byt_pingroup byt_sus_groups[] = {
617− PIN_GROUP_SIMPLE("usb_oc_grp",
618− byt_sus_usb_over_current_pins, byt_sus_usb_oc_mux),
619− PIN_GROUP_MIXED("usb_ulpi_grp",
620− byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mux),
621− PIN_GROUP_SIMPLE("pcu_spi_grp",
622− byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mux),
476+static const struct intel_pingroup byt_sus_groups[] = {
477+ PIN_GROUP("usb_oc_grp", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values),
478+ PIN_GROUP("usb_ulpi_grp", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values),
479+ PIN_GROUP("pcu_spi_grp", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values),
480+ PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values),
481+ PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values),
482+ PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values),
623483 };
624484
625485 static const char * const byt_sus_usb_groups[] = {
@@ -627,10 +487,10 @@ static const char * const byt_sus_usb_groups[] = { · 1 unmodified line
627487 };
628488 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
629489 static const char * const byt_sus_gpio_groups[] = {
630− "usb_oc_grp", "usb_ulpi_grp", "pcu_spi_grp",
490+ "usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio",
631491 };
632492
633−static const struct byt_function byt_sus_functions[] = {
493+static const struct intel_function byt_sus_functions[] = {
634494 FUNCTION("usb", byt_sus_usb_groups),
635495 FUNCTION("spi", byt_sus_spi_groups),
636496 FUNCTION("gpio", byt_sus_gpio_groups),
@@ -810,41 +670,9 @@ static int byt_get_function_groups(struct pinctrl_dev *pctldev, · 173 unmodified lines
810670 return 0;
811671 }
812672
813−static int byt_get_group_simple_mux(const struct byt_pingroup group,
814− const char *func_name,
815− unsigned short *func)
816−{
817− int i;
818−
819− for (i = 0; i < group.nfuncs; i++) {
820− if (!strcmp(group.simple_funcs[i].name, func_name)) {
821− *func = group.simple_funcs[i].func;
822− return 0;
823− }
824− }
825−
826− return 1;
827−}
828−
829−static int byt_get_group_mixed_mux(const struct byt_pingroup group,
830− const char *func_name,
831− const unsigned short **func)
832−{
833− int i;
834−
835− for (i = 0; i < group.nfuncs; i++) {
836− if (!strcmp(group.mixed_funcs[i].name, func_name)) {
837− *func = group.mixed_funcs[i].func_values;
838− return 0;
839− }
840− }
841−
842− return 1;
843−}
844−
845673 static void byt_set_group_simple_mux(struct byt_gpio *vg,
846− const struct byt_pingroup group,
847− unsigned short func)
674+ const struct intel_pingroup group,
675+ unsigned int func)
848676 {
849677 unsigned long flags;
850678 int i;
@@ -873,8 +701,8 @@ static void byt_set_group_simple_mux(struct byt_gpio *vg, · 22 unmodified lines
873701 }
874702
875703 static void byt_set_group_mixed_mux(struct byt_gpio *vg,
876− const struct byt_pingroup group,
877− const unsigned short *func)
704+ const struct intel_pingroup group,
705+ const unsigned int *func)
878706 {
879707 unsigned long flags;
880708 int i;
@@ -906,23 +734,15 @@ static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, · 25 unmodified lines
906734 unsigned int group_selector)
907735 {
908736 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
909− const struct byt_function func = vg->soc_data->functions[func_selector];
910− const struct byt_pingroup group = vg->soc_data->groups[group_selector];
911− const unsigned short *mixed_func;
912− unsigned short simple_func;
913− int ret = 1;
914−
915− if (group.has_simple_funcs)
916− ret = byt_get_group_simple_mux(group, func.name, &simple_func);
917− else
918− ret = byt_get_group_mixed_mux(group, func.name, &mixed_func);
737+ const struct intel_function func = vg->soc_data->functions[func_selector];
738+ const struct intel_pingroup group = vg->soc_data->groups[group_selector];
919739
920− if (ret)
740+ if (group.modes)
741+ byt_set_group_mixed_mux(vg, group, group.modes);
742+ else if (!strcmp(func.name, "gpio"))
921743 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
922− else if (group.has_simple_funcs)
923− byt_set_group_simple_mux(vg, group, simple_func);
924744 else
925− byt_set_group_mixed_mux(vg, group, mixed_func);
745+ byt_set_group_simple_mux(vg, group, group.mode);
926746
927747 return 0;
928748 }
@@ -932,14 +752,14 @@ static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned int offset) · 3 unmodified lines
932752 /* SCORE pin 92-93 */
933753 if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) &&
934754 offset >= 92 && offset <= 93)
935− return 1;
755+ return BYT_ALTER_GPIO_MUX;
936756
937757 /* SUS pin 11-21 */
938758 if (!strcmp(vg->soc_data->uid, BYT_SUS_ACPI_UID) &&
939759 offset >= 11 && offset <= 21)
940− return 1;
760+ return BYT_ALTER_GPIO_MUX;
941761
942− return 0;
762+ return BYT_DEFAULT_GPIO_MUX;
943763 }
944764
945765 static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset)
drivers/pinctrl/mediatek/pinctrl-mt8183.c+1−0
@@ -583,6 +583,7 @@ static struct platform_driver mt8183_pinctrl_driver = { · 582 unmodified lines
583583 .driver = {
584584 .name = "mt8183-pinctrl",
585585 .of_match_table = mt8183_pinctrl_of_match,
586+ .pm = &mtk_paris_pinctrl_pm_ops,
586587 },
587588 .probe = mt8183_pinctrl_probe,
588589 };
drivers/pinctrl/mediatek/pinctrl-paris.c+19−0
@@ -926,3 +926,22 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, · 925 unmodified lines
926926
927927 return 0;
928928 }
929+
930+static int mtk_paris_pinctrl_suspend(struct device *device)
931+{
932+ struct mtk_pinctrl *pctl = dev_get_drvdata(device);
933+
934+ return mtk_eint_do_suspend(pctl->eint);
935+}
936+
937+static int mtk_paris_pinctrl_resume(struct device *device)
938+{
939+ struct mtk_pinctrl *pctl = dev_get_drvdata(device);
940+
941+ return mtk_eint_do_resume(pctl->eint);
942+}
943+
944+const struct dev_pm_ops mtk_paris_pinctrl_pm_ops = {
945+ .suspend_noirq = mtk_paris_pinctrl_suspend,
946+ .resume_noirq = mtk_paris_pinctrl_resume,
947+};
drivers/pinctrl/mediatek/pinctrl-paris.h+2−0
@@ -60,4 +60,6 @@ · 59 unmodified lines
6060 int mtk_paris_pinctrl_probe(struct platform_device *pdev,
6161 const struct mtk_pin_soc *soc);
6262
63+extern const struct dev_pm_ops mtk_paris_pinctrl_pm_ops;
64+
6365 #endif /* __PINCTRL_PARIS_H */
drivers/pinctrl/meson/pinctrl-meson-g12a.c+18−18
@@ -1304,28 +1304,28 @@ static struct meson_pmx_func meson_g12a_aobus_functions[] = { · 1303 unmodified lines
13041304 };
13051305
13061306 static struct meson_bank meson_g12a_periphs_banks[] = {
1307− /* name first last irq pullen pull dir out in */
1308− BANK("Z", GPIOZ_0, GPIOZ_15, 12, 27,
1309− 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
1310− BANK("H", GPIOH_0, GPIOH_8, 28, 36,
1311− 3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
1312− BANK("BOOT", BOOT_0, BOOT_15, 37, 52,
1313− 0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
1314− BANK("C", GPIOC_0, GPIOC_7, 53, 60,
1315− 1, 0, 1, 0, 3, 0, 4, 0, 5, 0),
1316− BANK("A", GPIOA_0, GPIOA_15, 61, 76,
1317− 5, 0, 5, 0, 16, 0, 17, 0, 18, 0),
1318− BANK("X", GPIOX_0, GPIOX_19, 77, 96,
1319− 2, 0, 2, 0, 6, 0, 7, 0, 8, 0),
1307+ /* name first last irq pullen pull dir out in ds */
1308+ BANK_DS("Z", GPIOZ_0, GPIOZ_15, 12, 27,
1309+ 4, 0, 4, 0, 12, 0, 13, 0, 14, 0, 5, 0),
1310+ BANK_DS("H", GPIOH_0, GPIOH_8, 28, 36,
1311+ 3, 0, 3, 0, 9, 0, 10, 0, 11, 0, 4, 0),
1312+ BANK_DS("BOOT", BOOT_0, BOOT_15, 37, 52,
1313+ 0, 0, 0, 0, 0, 0, 1, 0, 2, 0, 0, 0),
1314+ BANK_DS("C", GPIOC_0, GPIOC_7, 53, 60,
1315+ 1, 0, 1, 0, 3, 0, 4, 0, 5, 0, 1, 0),
1316+ BANK_DS("A", GPIOA_0, GPIOA_15, 61, 76,
1317+ 5, 0, 5, 0, 16, 0, 17, 0, 18, 0, 6, 0),
1318+ BANK_DS("X", GPIOX_0, GPIOX_19, 77, 96,
1319+ 2, 0, 2, 0, 6, 0, 7, 0, 8, 0, 2, 0),
13201320 };
13211321
13221322 static struct meson_bank meson_g12a_aobus_banks[] = {
1323− /* name first last irq pullen pull dir out in */
1324− BANK("AO", GPIOAO_0, GPIOAO_11, 0, 11,
1325− 3, 0, 2, 0, 0, 0, 4, 0, 1, 0),
1323+ /* name first last irq pullen pull dir out in ds */
1324+ BANK_DS("AO", GPIOAO_0, GPIOAO_11, 0, 11, 3, 0, 2, 0, 0, 0, 4, 0, 1, 0,
1325+ 0, 0),
13261326 /* GPIOE actually located in the AO bank */
1327− BANK("E", GPIOE_0, GPIOE_2, 97, 99,
1328− 3, 16, 2, 16, 0, 16, 4, 16, 1, 16),
1327+ BANK_DS("E", GPIOE_0, GPIOE_2, 97, 99, 3, 16, 2, 16, 0, 16, 4, 16, 1,
1328+ 16, 1, 0),
13291329 };
13301330
13311331 static struct meson_pmx_bank meson_g12a_periphs_pmx_banks[] = {
drivers/pinctrl/meson/pinctrl-meson.c+267−83
@@ -168,68 +168,223 @@ int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, · 167 unmodified lines
168168 return 0;
169169 }
170170
171−static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
172− unsigned long *configs, unsigned num_configs)
171+static int meson_pinconf_set_gpio_bit(struct meson_pinctrl *pc,
172+ unsigned int pin,
173+ unsigned int reg_type,
174+ bool arg)
173175 {
174− struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
175176 struct meson_bank *bank;
176− enum pin_config_param param;
177177 unsigned int reg, bit;
178− int i, ret;
178+ int ret;
179+
180+ ret = meson_get_bank(pc, pin, &bank);
181+ if (ret)
182+ return ret;
183+
184+ meson_calc_reg_and_bit(bank, pin, reg_type, &reg, &bit);
185+ return regmap_update_bits(pc->reg_gpio, reg, BIT(bit),
186+ arg ? BIT(bit) : 0);
187+}
188+
189+static int meson_pinconf_get_gpio_bit(struct meson_pinctrl *pc,
190+ unsigned int pin,
191+ unsigned int reg_type)
192+{
193+ struct meson_bank *bank;
194+ unsigned int reg, bit, val;
195+ int ret;
179196
180197 ret = meson_get_bank(pc, pin, &bank);
181198 if (ret)
182199 return ret;
183200
201+ meson_calc_reg_and_bit(bank, pin, reg_type, &reg, &bit);
202+ ret = regmap_read(pc->reg_gpio, reg, &val);
203+ if (ret)
204+ return ret;
205+
206+ return BIT(bit) & val ? 1 : 0;
207+}
208+
209+static int meson_pinconf_set_output(struct meson_pinctrl *pc,
210+ unsigned int pin,
211+ bool out)
212+{
213+ return meson_pinconf_set_gpio_bit(pc, pin, REG_DIR, !out);
214+}
215+
216+static int meson_pinconf_get_output(struct meson_pinctrl *pc,
217+ unsigned int pin)
218+{
219+ int ret = meson_pinconf_get_gpio_bit(pc, pin, REG_DIR);
220+
221+ if (ret < 0)
222+ return ret;
223+
224+ return !ret;
225+}
226+
227+static int meson_pinconf_set_drive(struct meson_pinctrl *pc,
228+ unsigned int pin,
229+ bool high)
230+{
231+ return meson_pinconf_set_gpio_bit(pc, pin, REG_OUT, high);
232+}
233+
234+static int meson_pinconf_get_drive(struct meson_pinctrl *pc,
235+ unsigned int pin)
236+{
237+ return meson_pinconf_get_gpio_bit(pc, pin, REG_OUT);
238+}
239+
240+static int meson_pinconf_set_output_drive(struct meson_pinctrl *pc,
241+ unsigned int pin,
242+ bool high)
243+{
244+ int ret;
245+
246+ ret = meson_pinconf_set_output(pc, pin, true);
247+ if (ret)
248+ return ret;
249+
250+ return meson_pinconf_set_drive(pc, pin, high);
251+}
252+
253+static int meson_pinconf_disable_bias(struct meson_pinctrl *pc,
254+ unsigned int pin)
255+{
256+ struct meson_bank *bank;
257+ unsigned int reg, bit = 0;
258+ int ret;
259+
260+ ret = meson_get_bank(pc, pin, &bank);
261+ if (ret)
262+ return ret;
263+
264+ meson_calc_reg_and_bit(bank, pin, REG_PULLEN, &reg, &bit);
265+ ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), 0);
266+ if (ret)
267+ return ret;
268+
269+ return 0;
270+}
271+
272+static int meson_pinconf_enable_bias(struct meson_pinctrl *pc, unsigned int pin,
273+ bool pull_up)
274+{
275+ struct meson_bank *bank;
276+ unsigned int reg, bit, val = 0;
277+ int ret;
278+
279+ ret = meson_get_bank(pc, pin, &bank);
280+ if (ret)
281+ return ret;
282+
283+ meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
284+ if (pull_up)
285+ val = BIT(bit);
286+
287+ ret = regmap_update_bits(pc->reg_pull, reg, BIT(bit), val);
288+ if (ret)
289+ return ret;
290+
291+ meson_calc_reg_and_bit(bank, pin, REG_PULLEN, &reg, &bit);
292+ ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), BIT(bit));
293+ if (ret)
294+ return ret;
295+
296+ return 0;
297+}
298+
299+static int meson_pinconf_set_drive_strength(struct meson_pinctrl *pc,
300+ unsigned int pin,
301+ u16 drive_strength_ua)
302+{
303+ struct meson_bank *bank;
304+ unsigned int reg, bit, ds_val;
305+ int ret;
306+
307+ if (!pc->reg_ds) {
308+ dev_err(pc->dev, "drive-strength not supported\n");
309+ return -ENOTSUPP;
310+ }
311+
312+ ret = meson_get_bank(pc, pin, &bank);
313+ if (ret)
314+ return ret;
315+
316+ meson_calc_reg_and_bit(bank, pin, REG_DS, &reg, &bit);
317+ bit = bit << 1;
318+
319+ if (drive_strength_ua <= 500) {
320+ ds_val = MESON_PINCONF_DRV_500UA;
321+ } else if (drive_strength_ua <= 2500) {
322+ ds_val = MESON_PINCONF_DRV_2500UA;
323+ } else if (drive_strength_ua <= 3000) {
324+ ds_val = MESON_PINCONF_DRV_3000UA;
325+ } else if (drive_strength_ua <= 4000) {
326+ ds_val = MESON_PINCONF_DRV_4000UA;
327+ } else {
328+ dev_warn_once(pc->dev,
329+ "pin %u: invalid drive-strength : %d , default to 4mA\n",
330+ pin, drive_strength_ua);
331+ ds_val = MESON_PINCONF_DRV_4000UA;
332+ }
333+
334+ ret = regmap_update_bits(pc->reg_ds, reg, 0x3 << bit, ds_val << bit);
335+ if (ret)
336+ return ret;
337+
338+ return 0;
339+}
340+
341+static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
342+ unsigned long *configs, unsigned num_configs)
343+{
344+ struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
345+ enum pin_config_param param;
346+ unsigned int arg = 0;
347+ int i, ret;
348+
184349 for (i = 0; i < num_configs; i++) {
185350 param = pinconf_to_config_param(configs[i]);
186351
352+ switch (param) {
353+ case PIN_CONFIG_DRIVE_STRENGTH_UA:
354+ case PIN_CONFIG_OUTPUT_ENABLE:
355+ case PIN_CONFIG_OUTPUT:
356+ arg = pinconf_to_config_argument(configs[i]);
357+ break;
358+
359+ default:
360+ break;
361+ }
362+
187363 switch (param) {
188364 case PIN_CONFIG_BIAS_DISABLE:
189− dev_dbg(pc->dev, "pin %u: disable bias\n", pin);
190−
191− meson_calc_reg_and_bit(bank, pin, REG_PULLEN, &reg,
192− &bit);
193− ret = regmap_update_bits(pc->reg_pullen, reg,
194− BIT(bit), 0);
195− if (ret)
196− return ret;
365+ ret = meson_pinconf_disable_bias(pc, pin);
197366 break;
198367 case PIN_CONFIG_BIAS_PULL_UP:
199− dev_dbg(pc->dev, "pin %u: enable pull-up\n", pin);
200−
201− meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
202− &reg, &bit);
203− ret = regmap_update_bits(pc->reg_pullen, reg,
204− BIT(bit), BIT(bit));
205− if (ret)
206− return ret;
207−
208− meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
209− ret = regmap_update_bits(pc->reg_pull, reg,
210− BIT(bit), BIT(bit));
211− if (ret)
212− return ret;
368+ ret = meson_pinconf_enable_bias(pc, pin, true);
213369 break;
214370 case PIN_CONFIG_BIAS_PULL_DOWN:
215− dev_dbg(pc->dev, "pin %u: enable pull-down\n", pin);
216−
217− meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
218− &reg, &bit);
219− ret = regmap_update_bits(pc->reg_pullen, reg,
220− BIT(bit), BIT(bit));
221− if (ret)
222− return ret;
223−
224− meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
225− ret = regmap_update_bits(pc->reg_pull, reg,
226− BIT(bit), 0);
227− if (ret)
228− return ret;
371+ ret = meson_pinconf_enable_bias(pc, pin, false);
372+ break;
373+ case PIN_CONFIG_DRIVE_STRENGTH_UA:
374+ ret = meson_pinconf_set_drive_strength(pc, pin, arg);
375+ break;
376+ case PIN_CONFIG_OUTPUT_ENABLE:
377+ ret = meson_pinconf_set_output(pc, pin, arg);
378+ break;
379+ case PIN_CONFIG_OUTPUT:
380+ ret = meson_pinconf_set_output_drive(pc, pin, arg);
229381 break;
230382 default:
231− return -ENOTSUPP;
383+ ret = -ENOTSUPP;
232384 }
385+
386+ if (ret)
387+ return ret;
233388 }
234389
235390 return 0;
@@ -269,12 +424,55 @@ static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin) · 33 unmodified lines
269424 return conf;
270425 }
271426
427+static int meson_pinconf_get_drive_strength(struct meson_pinctrl *pc,
428+ unsigned int pin,
429+ u16 *drive_strength_ua)
430+{
431+ struct meson_bank *bank;
432+ unsigned int reg, bit;
433+ unsigned int val;
434+ int ret;
435+
436+ if (!pc->reg_ds)
437+ return -ENOTSUPP;
438+
439+ ret = meson_get_bank(pc, pin, &bank);
440+ if (ret)
441+ return ret;
442+
443+ meson_calc_reg_and_bit(bank, pin, REG_DS, &reg, &bit);
444+
445+ ret = regmap_read(pc->reg_ds, reg, &val);
446+ if (ret)
447+ return ret;
448+
449+ switch ((val >> bit) & 0x3) {
450+ case MESON_PINCONF_DRV_500UA:
451+ *drive_strength_ua = 500;
452+ break;
453+ case MESON_PINCONF_DRV_2500UA:
454+ *drive_strength_ua = 2500;
455+ break;
456+ case MESON_PINCONF_DRV_3000UA:
457+ *drive_strength_ua = 3000;
458+ break;
459+ case MESON_PINCONF_DRV_4000UA:
460+ *drive_strength_ua = 4000;
461+ break;
462+ default:
463+ return -EINVAL;
464+ }
465+
466+ return 0;
467+}
468+
272469 static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin,
273470 unsigned long *config)
274471 {
275472 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
276473 enum pin_config_param param = pinconf_to_config_param(*config);
277474 u16 arg;
475+ int ret;
278476
279477 switch (param) {
280478 case PIN_CONFIG_BIAS_DISABLE:
@@ -285,6 +483,29 @@ static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, · 4 unmodified lines
285483 else
286484 return -EINVAL;
287485 break;
486+ case PIN_CONFIG_DRIVE_STRENGTH_UA:
487+ ret = meson_pinconf_get_drive_strength(pc, pin, &arg);
488+ if (ret)
489+ return ret;
490+ break;
491+ case PIN_CONFIG_OUTPUT_ENABLE:
492+ ret = meson_pinconf_get_output(pc, pin);
493+ if (ret <= 0)
494+ return -EINVAL;
495+ arg = 1;
496+ break;
497+ case PIN_CONFIG_OUTPUT:
498+ ret = meson_pinconf_get_output(pc, pin);
499+ if (ret <= 0)
500+ return -EINVAL;
501+
502+ ret = meson_pinconf_get_drive(pc, pin);
503+ if (ret < 0)
504+ return -EINVAL;
505+
506+ arg = ret;
507+ break;
508+
288509 default:
289510 return -ENOTSUPP;
290511 }
@@ -329,56 +550,19 @@ static const struct pinconf_ops meson_pinconf_ops = { · 38 unmodified lines
329550
330551 static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
331552 {
332− struct meson_pinctrl *pc = gpiochip_get_data(chip);
333− unsigned int reg, bit;
334− struct meson_bank *bank;
335− int ret;
336−
337− ret = meson_get_bank(pc, gpio, &bank);
338− if (ret)
339− return ret;
340−
341− meson_calc_reg_and_bit(bank, gpio, REG_DIR, &reg, &bit);
342−
343− return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), BIT(bit));
553+ return meson_pinconf_set_output(gpiochip_get_data(chip), gpio, false);
344554 }
345555
346556 static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
347557 int value)
348558 {
349− struct meson_pinctrl *pc = gpiochip_get_data(chip);
350− unsigned int reg, bit;
351− struct meson_bank *bank;
352− int ret;
353−
354− ret = meson_get_bank(pc, gpio, &bank);
355− if (ret)
356− return ret;
357−
358− meson_calc_reg_and_bit(bank, gpio, REG_DIR, &reg, &bit);
359− ret = regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 0);
360− if (ret)
361− return ret;
362−
363− meson_calc_reg_and_bit(bank, gpio, REG_OUT, &reg, &bit);
364− return regmap_update_bits(pc->reg_gpio, reg, BIT(bit),
365− value ? BIT(bit) : 0);
559+ return meson_pinconf_set_output_drive(gpiochip_get_data(chip),
560+ gpio, value);
366561 }
367562
368563 static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
369564 {
370− struct meson_pinctrl *pc = gpiochip_get_data(chip);
371− unsigned int reg, bit;
372− struct meson_bank *bank;
373− int ret;
374−
375− ret = meson_get_bank(pc, gpio, &bank);
376− if (ret)
377− return;
378−
379− meson_calc_reg_and_bit(bank, gpio, REG_OUT, &reg, &bit);
380− regmap_update_bits(pc->reg_gpio, reg, BIT(bit),
381− value ? BIT(bit) : 0);
565+ meson_pinconf_set_drive(gpiochip_get_data(chip), gpio, value);
382566 }
383567
384568 static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
drivers/pinctrl/meson/pinctrl-meson.h+17−1
@@ -65,9 +65,20 @@ enum meson_reg_type { · 64 unmodified lines
6565 REG_DIR,
6666 REG_OUT,
6767 REG_IN,
68+ REG_DS,
6869 NUM_REG,
6970 };
7071
72+/**
73+ * enum meson_pinconf_drv - value of drive-strength supported
74+ */
75+enum meson_pinconf_drv {
76+ MESON_PINCONF_DRV_500UA,
77+ MESON_PINCONF_DRV_2500UA,
78+ MESON_PINCONF_DRV_3000UA,
79+ MESON_PINCONF_DRV_4000UA,
80+};
81+
7182 /**
7283 * struct meson bank
7384 *
@@ -126,7 +137,8 @@ struct meson_pinctrl { · 52 unmodified lines
126137 .num_groups = ARRAY_SIZE(fn ## _groups), \
127138 }
128139
129−#define BANK(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
140+#define BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, \
141+ dsr, dsb) \
130142 { \
131143 .name = n, \
132144 .first = f, \
@@ -139,9 +151,13 @@ struct meson_pinctrl { · 6 unmodified lines
139151 [REG_DIR] = { dr, db }, \
140152 [REG_OUT] = { or, ob }, \
141153 [REG_IN] = { ir, ib }, \
154+ [REG_DS] = { dsr, dsb }, \
142155 }, \
143156 }
144157
158+#define BANK(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
159+ BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, 0, 0)
160+
145161 #define MESON_PIN(x) PINCTRL_PIN(x, #x)
146162
147163 /* Common pmx functions */
drivers/pinctrl/mvebu/pinctrl-kirkwood.c+297−279
@@ -16,341 +16,347 @@ · 15 unmodified lines
1616
1717 #include "pinctrl-mvebu.h"
1818
19−#define V(f6180, f6190, f6192, f6281, f6282, dx4122) \
19+#define V(f6180, f6190, f6192, f6281, f6282, dx4122, dx1135) \
2020 ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \
21− (f6281 << 3) | (f6282 << 4) | (dx4122 << 5))
21+ (f6281 << 3) | (f6282 << 4) | (dx4122 << 5) | \
22+ (dx1135 << 6))
2223
2324 enum kirkwood_variant {
24− VARIANT_MV88F6180 = V(1, 0, 0, 0, 0, 0),
25− VARIANT_MV88F6190 = V(0, 1, 0, 0, 0, 0),
26− VARIANT_MV88F6192 = V(0, 0, 1, 0, 0, 0),
27− VARIANT_MV88F6281 = V(0, 0, 0, 1, 0, 0),
28− VARIANT_MV88F6282 = V(0, 0, 0, 0, 1, 0),
29− VARIANT_MV98DX4122 = V(0, 0, 0, 0, 0, 1),
25+ VARIANT_MV88F6180 = V(1, 0, 0, 0, 0, 0, 0),
26+ VARIANT_MV88F6190 = V(0, 1, 0, 0, 0, 0, 0),
27+ VARIANT_MV88F6192 = V(0, 0, 1, 0, 0, 0, 0),
28+ VARIANT_MV88F6281 = V(0, 0, 0, 1, 0, 0, 0),
29+ VARIANT_MV88F6282 = V(0, 0, 0, 0, 1, 0, 0),
30+ VARIANT_MV98DX4122 = V(0, 0, 0, 0, 0, 1, 0),
31+ VARIANT_MV98DX1135 = V(0, 0, 0, 0, 0, 0, 1),
3032 };
3133
3234 static struct mvebu_mpp_mode mv88f6xxx_mpp_modes[] = {
3335 MPP_MODE(0,
34− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
35− MPP_VAR_FUNCTION(0x1, "nand", "io2", V(1, 1, 1, 1, 1, 1)),
36− MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1, 1))),
36+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
37+ MPP_VAR_FUNCTION(0x1, "nand", "io2", V(1, 1, 1, 1, 1, 1, 1)),
38+ MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1, 1, 1))),
3739 MPP_MODE(1,
38− MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
39− MPP_VAR_FUNCTION(0x1, "nand", "io3", V(1, 1, 1, 1, 1, 1)),
40− MPP_VAR_FUNCTION(0x2, "spi", "mosi", V(1, 1, 1, 1, 1, 1))),
40+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1, 1)),
41+ MPP_VAR_FUNCTION(0x1, "nand", "io3", V(1, 1, 1, 1, 1, 1, 1)),
42+ MPP_VAR_FUNCTION(0x2, "spi", "mosi", V(1, 1, 1, 1, 1, 1, 1))),
4143 MPP_MODE(2,
42− MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
43− MPP_VAR_FUNCTION(0x1, "nand", "io4", V(1, 1, 1, 1, 1, 1)),
44− MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1, 1))),
44+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1, 1)),
45+ MPP_VAR_FUNCTION(0x1, "nand", "io4", V(1, 1, 1, 1, 1, 1, 1)),
46+ MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1, 1, 1))),
4547 MPP_MODE(3,
46− MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
47− MPP_VAR_FUNCTION(0x1, "nand", "io5", V(1, 1, 1, 1, 1, 1)),
48− MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1, 1))),
48+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1, 1)),
49+ MPP_VAR_FUNCTION(0x1, "nand", "io5", V(1, 1, 1, 1, 1, 1, 1)),
50+ MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1, 1, 1))),
4951 MPP_MODE(4,
50− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
51− MPP_VAR_FUNCTION(0x1, "nand", "io6", V(1, 1, 1, 1, 1, 1)),
52− MPP_VAR_FUNCTION(0x2, "uart0", "rxd", V(1, 1, 1, 1, 1, 1)),
53− MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1, 0)),
54− MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1, 0)),
55− MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0, 0))),
52+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
53+ MPP_VAR_FUNCTION(0x1, "nand", "io6", V(1, 1, 1, 1, 1, 1, 1)),
54+ MPP_VAR_FUNCTION(0x2, "uart0", "rxd", V(1, 1, 1, 1, 1, 1, 1)),
55+ MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1, 0, 0)),
56+ MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1, 0, 0)),
57+ MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0, 0, 0))),
5658 MPP_MODE(5,
57− MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
58− MPP_VAR_FUNCTION(0x1, "nand", "io7", V(1, 1, 1, 1, 1, 1)),
59− MPP_VAR_FUNCTION(0x2, "uart0", "txd", V(1, 1, 1, 1, 1, 1)),
60− MPP_VAR_FUNCTION(0x4, "ptp", "trig", V(1, 1, 1, 1, 0, 0)),
61− MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0)),
62− MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1, 0))),
59+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1, 1)),
60+ MPP_VAR_FUNCTION(0x1, "nand", "io7", V(1, 1, 1, 1, 1, 1, 1)),
61+ MPP_VAR_FUNCTION(0x2, "uart0", "txd", V(1, 1, 1, 1, 1, 1, 1)),
62+ MPP_VAR_FUNCTION(0x4, "ptp", "trig", V(1, 1, 1, 1, 0, 0, 0)),
63+ MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0, 0)),
64+ MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1, 0, 0))),
6365 MPP_MODE(6,
64− MPP_VAR_FUNCTION(0x1, "sysrst", "out", V(1, 1, 1, 1, 1, 1)),
65− MPP_VAR_FUNCTION(0x2, "spi", "mosi", V(1, 1, 1, 1, 1, 1)),
66− MPP_VAR_FUNCTION(0x3, "ptp", "trig", V(1, 1, 1, 1, 0, 0))),
66+ MPP_VAR_FUNCTION(0x1, "sysrst", "out", V(1, 1, 1, 1, 1, 1, 1)),
67+ MPP_VAR_FUNCTION(0x2, "spi", "mosi", V(1, 1, 1, 1, 1, 1, 1)),
68+ MPP_VAR_FUNCTION(0x3, "ptp", "trig", V(1, 1, 1, 1, 0, 0, 0))),
6769 MPP_MODE(7,
68− MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
69− MPP_VAR_FUNCTION(0x1, "pex", "rsto", V(1, 1, 1, 1, 0, 1)),
70− MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1, 1)),
71− MPP_VAR_FUNCTION(0x3, "ptp", "trig", V(1, 1, 1, 1, 0, 0)),
72− MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1, 0))),
70+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1, 1)),
71+ MPP_VAR_FUNCTION(0x1, "pex", "rsto", V(1, 1, 1, 1, 0, 1, 1)),
72+ MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1, 1, 1)),
73+ MPP_VAR_FUNCTION(0x3, "ptp", "trig", V(1, 1, 1, 1, 0, 0, 0)),
74+ MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1, 0, 0))),
7375 MPP_MODE(8,
74− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
75− MPP_VAR_FUNCTION(0x1, "twsi0", "sda", V(1, 1, 1, 1, 1, 1)),
76− MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1, 1)),
77− MPP_VAR_FUNCTION(0x3, "uart1", "rts", V(1, 1, 1, 1, 1, 1)),
78− MPP_VAR_FUNCTION(0x4, "mii-1", "rxerr", V(0, 1, 1, 1, 1, 0)),
79− MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1, 0)),
80− MPP_VAR_FUNCTION(0xc, "ptp", "clk", V(1, 1, 1, 1, 0, 0)),
81− MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1, 0))),
76+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
77+ MPP_VAR_FUNCTION(0x1, "twsi0", "sda", V(1, 1, 1, 1, 1, 1, 1)),
78+ MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1, 1, 1)),
79+ MPP_VAR_FUNCTION(0x3, "uart1", "rts", V(1, 1, 1, 1, 1, 1, 1)),
80+ MPP_VAR_FUNCTION(0x4, "mii-1", "rxerr", V(0, 1, 1, 1, 1, 0, 0)),
81+ MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1, 0, 0)),
82+ MPP_VAR_FUNCTION(0xc, "ptp", "clk", V(1, 1, 1, 1, 0, 0, 0)),
83+ MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1, 0, 0))),
8284 MPP_MODE(9,
83− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
84− MPP_VAR_FUNCTION(0x1, "twsi0", "sck", V(1, 1, 1, 1, 1, 1)),
85− MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1, 1)),
86− MPP_VAR_FUNCTION(0x3, "uart1", "cts", V(1, 1, 1, 1, 1, 1)),
87− MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1, 0)),
88− MPP_VAR_FUNCTION(0xc, "ptp", "evreq", V(1, 1, 1, 1, 0, 0)),
89− MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1, 0))),
85+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
86+ MPP_VAR_FUNCTION(0x1, "twsi0", "sck", V(1, 1, 1, 1, 1, 1, 1)),
87+ MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1, 1, 1)),
88+ MPP_VAR_FUNCTION(0x3, "uart1", "cts", V(1, 1, 1, 1, 1, 1, 1)),
89+ MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1, 0, 0)),
90+ MPP_VAR_FUNCTION(0xc, "ptp", "evreq", V(1, 1, 1, 1, 0, 0, 0)),
91+ MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1, 0, 0))),
9092 MPP_MODE(10,
91− MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
92− MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1, 1)),
93− MPP_VAR_FUNCTION(0X3, "uart0", "txd", V(1, 1, 1, 1, 1, 1)),
94− MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1, 0)),
95− MPP_VAR_FUNCTION(0xc, "ptp", "trig", V(1, 1, 1, 1, 0, 0))),
93+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1, 1)),
94+ MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1, 1, 1)),
95+ MPP_VAR_FUNCTION(0X3, "uart0", "txd", V(1, 1, 1, 1, 1, 1, 1)),
96+ MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1, 0, 0)),
97+ MPP_VAR_FUNCTION(0xc, "ptp", "trig", V(1, 1, 1, 1, 0, 0, 0))),
9698 MPP_MODE(11,
97− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
98− MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1, 1)),
99− MPP_VAR_FUNCTION(0x3, "uart0", "rxd", V(1, 1, 1, 1, 1, 1)),
100− MPP_VAR_FUNCTION(0x4, "ptp-1", "evreq", V(1, 1, 1, 1, 0, 0)),
101− MPP_VAR_FUNCTION(0xc, "ptp-2", "trig", V(1, 1, 1, 1, 0, 0)),
102− MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0, 0)),
103− MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0))),
99+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
100+ MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1, 1, 1)),
101+ MPP_VAR_FUNCTION(0x3, "uart0", "rxd", V(1, 1, 1, 1, 1, 1, 1)),
102+ MPP_VAR_FUNCTION(0x4, "ptp-1", "evreq", V(1, 1, 1, 1, 0, 0, 0)),
103+ MPP_VAR_FUNCTION(0xc, "ptp-2", "trig", V(1, 1, 1, 1, 0, 0, 0)),
104+ MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0, 0, 0)),
105+ MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0, 0))),
104106 MPP_MODE(12,
105− MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 0, 1, 0)),
106− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0, 0)),
107− MPP_VAR_FUNCTION(0x1, "sdio", "clk", V(1, 1, 1, 1, 1, 0)),
108− MPP_VAR_FUNCTION(0xa, "audio", "spdifo", V(0, 0, 0, 0, 1, 0)),
109− MPP_VAR_FUNCTION(0xb, "spi", "mosi", V(0, 0, 0, 0, 1, 0)),
110− MPP_VAR_FUNCTION(0xd, "twsi1", "sda", V(0, 0, 0, 0, 1, 0))),
107+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 0, 1, 0, 0)),
108+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0, 0, 0)),
109+ MPP_VAR_FUNCTION(0x1, "sdio", "clk", V(1, 1, 1, 1, 1, 0, 0)),
110+ MPP_VAR_FUNCTION(0xa, "audio", "spdifo", V(0, 0, 0, 0, 1, 0, 0)),
111+ MPP_VAR_FUNCTION(0xb, "spi", "mosi", V(0, 0, 0, 0, 1, 0, 0)),
112+ MPP_VAR_FUNCTION(0xd, "twsi1", "sda", V(0, 0, 0, 0, 1, 0, 0))),
111113 MPP_MODE(13,
112− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
113− MPP_VAR_FUNCTION(0x1, "sdio", "cmd", V(1, 1, 1, 1, 1, 0)),
114− MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1, 1)),
115− MPP_VAR_FUNCTION(0xa, "audio", "rmclk", V(0, 0, 0, 0, 1, 0)),
116− MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1, 0))),
114+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
115+ MPP_VAR_FUNCTION(0x1, "sdio", "cmd", V(1, 1, 1, 1, 1, 0, 0)),
116+ MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1, 1, 1)),
117+ MPP_VAR_FUNCTION(0xa, "audio", "rmclk", V(0, 0, 0, 0, 1, 0, 0)),
118+ MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1, 0, 0))),
117119 MPP_MODE(14,
118− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
119− MPP_VAR_FUNCTION(0x1, "sdio", "d0", V(1, 1, 1, 1, 1, 0)),
120− MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1, 1)),
121− MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V(0, 0, 1, 1, 1, 0)),
122− MPP_VAR_FUNCTION(0xa, "audio", "spdifi", V(0, 0, 0, 0, 1, 0)),
123− MPP_VAR_FUNCTION(0xb, "audio-1", "sdi", V(0, 0, 0, 0, 1, 0)),
124− MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1, 0))),
120+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
121+ MPP_VAR_FUNCTION(0x1, "sdio", "d0", V(1, 1, 1, 1, 1, 0, 0)),
122+ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1, 1, 1)),
123+ MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V(0, 0, 1, 1, 1, 0, 0)),
124+ MPP_VAR_FUNCTION(0xa, "audio", "spdifi", V(0, 0, 0, 0, 1, 0, 0)),
125+ MPP_VAR_FUNCTION(0xb, "audio-1", "sdi", V(0, 0, 0, 0, 1, 0, 0)),
126+ MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1, 0, 0))),
125127 MPP_MODE(15,
126− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
127− MPP_VAR_FUNCTION(0x1, "sdio", "d1", V(1, 1, 1, 1, 1, 0)),
128− MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1, 1)),
129− MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1, 0)),
130− MPP_VAR_FUNCTION(0x4, "sata0", "act", V(0, 1, 1, 1, 1, 0)),
131− MPP_VAR_FUNCTION(0xb, "spi", "cs", V(0, 0, 0, 0, 1, 0))),
128+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
129+ MPP_VAR_FUNCTION(0x1, "sdio", "d1", V(1, 1, 1, 1, 1, 0, 0)),
130+ MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1, 1, 1)),
131+ MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1, 0, 0)),
132+ MPP_VAR_FUNCTION(0x4, "sata0", "act", V(0, 1, 1, 1, 1, 0, 0)),
133+ MPP_VAR_FUNCTION(0xb, "spi", "cs", V(0, 0, 0, 0, 1, 0, 0))),
132134 MPP_MODE(16,
133− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
134− MPP_VAR_FUNCTION(0x1, "sdio", "d2", V(1, 1, 1, 1, 1, 0)),
135− MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1, 1)),
136− MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1, 0)),
137− MPP_VAR_FUNCTION(0x4, "sata1", "act", V(0, 0, 1, 1, 1, 0)),
138− MPP_VAR_FUNCTION(0xb, "lcd", "extclk", V(0, 0, 0, 0, 1, 0)),
139− MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1, 0))),
135+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
136+ MPP_VAR_FUNCTION(0x1, "sdio", "d2", V(1, 1, 1, 1, 1, 0, 0)),
137+ MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1, 1, 1)),
138+ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1, 0, 0)),
139+ MPP_VAR_FUNCTION(0x4, "sata1", "act", V(0, 0, 1, 1, 1, 0, 0)),
140+ MPP_VAR_FUNCTION(0xb, "lcd", "extclk", V(0, 0, 0, 0, 1, 0, 0)),
141+ MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1, 0, 0))),
140142 MPP_MODE(17,
141− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
142− MPP_VAR_FUNCTION(0x1, "sdio", "d3", V(1, 1, 1, 1, 1, 0)),
143− MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V(0, 1, 1, 1, 1, 0)),
144− MPP_VAR_FUNCTION(0xa, "sata1", "act", V(0, 0, 0, 0, 1, 0)),
145− MPP_VAR_FUNCTION(0xd, "twsi1", "sck", V(0, 0, 0, 0, 1, 0))),
143+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0, 0)),
144+ MPP_VAR_FUNCTION(0x1, "sdio", "d3", V(1, 1, 1, 1, 1, 0, 0)),
145+ MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V(0, 1, 1, 1, 1, 0, 0)),
146+ MPP_VAR_FUNCTION(0xa, "sata1", "act", V(0, 0, 0, 0, 1, 0, 0)),
147+ MPP_VAR_FUNCTION(0xd, "twsi1", "sck", V(0, 0, 0, 0, 1, 0, 0))),
146148 MPP_MODE(18,
147− MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
148− MPP_VAR_FUNCTION(0x1, "nand", "io0", V(1, 1, 1, 1, 1, 1)),
149− MPP_VAR_FUNCTION(0x2, "pex", "clkreq", V(0, 0, 0, 0, 1, 0))),
149+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1, 1)),
150+ MPP_VAR_FUNCTION(0x1, "nand", "io0", V(1, 1, 1, 1, 1, 1, 1)),
151+ MPP_VAR_FUNCTION(0x2, "pex", "clkreq", V(0, 0, 0, 0, 1, 0, 0))),
150152 MPP_MODE(19,
151− MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
152− MPP_VAR_FUNCTION(0x1, "nand", "io1", V(1, 1, 1, 1, 1, 1))),
153+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1, 1)),
154+ MPP_VAR_FUNCTION(0x1, "nand", "io1", V(1, 1, 1, 1, 1, 1, 1))),
153155 MPP_MODE(20,
154− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
155− MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 1, 1, 1, 0)),
156− MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1, 0)),
157− MPP_VAR_FUNCTION(0x3, "ge1", "txd0", V(0, 1, 1, 1, 1, 0)),
158− MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 1, 1, 1, 0)),
159− MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1, 0)),
160− MPP_VAR_FUNCTION(0xb, "lcd", "d0", V(0, 0, 0, 0, 1, 0)),
161− MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(0, 0, 0, 0, 0, 0))),
156+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 1)),
157+ MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 1, 1, 1, 0, 0)),
158+ MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1, 0, 0)),
159+ MPP_VAR_FUNCTION(0x3, "ge1", "txd0", V(0, 1, 1, 1, 1, 0, 0)),
160+ MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 1, 1, 1, 0, 0)),
161+ MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1, 0, 0)),
162+ MPP_VAR_FUNCTION(0xb, "lcd", "d0", V(0, 0, 0, 0, 1, 0, 0)),
163+ MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(0, 0, 0, 0, 0, 0, 0))),
162164 MPP_MODE(21,
163− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
164− MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 1, 1, 1, 0)),
165− MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 1, 1, 1, 0)),
166− MPP_VAR_FUNCTION(0x3, "ge1", "txd1", V(0, 1, 1, 1, 1, 0)),
167− MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 0, 0, 0, 0)),
168− MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 1, 1, 1, 0)),
169− MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0)),
170− MPP_VAR_FUNCTION(0xb, "lcd", "d1", V(0, 0, 0, 0, 1, 0))),
165+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 1)),
166+ MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 1, 1, 1, 0, 0)),
167+ MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 1, 1, 1, 0, 0)),
168+ MPP_VAR_FUNCTION(0x3, "ge1", "txd1", V(0, 1, 1, 1, 1, 0, 0)),
169+ MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 0, 0, 0, 0, 0)),
170+ MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 1, 1, 1, 0, 0)),
171+ MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0, 0)),
172+ MPP_VAR_FUNCTION(0xb, "lcd", "d1", V(0, 0, 0, 0, 1, 0, 0))),
171173 MPP_MODE(22,
172− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
173− MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 1, 1, 1, 0)),
174− MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 1, 1, 1, 0)),
175− MPP_VAR_FUNCTION(0x3, "ge1", "txd2", V(0, 1, 1, 1, 1, 0)),
176− MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 0, 0, 0, 0)),
177− MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 1, 1, 1, 0)),
178− MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1, 0)),
179− MPP_VAR_FUNCTION(0xb, "lcd", "d2", V(0, 0, 0, 0, 1, 0))),
174+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 1)),
175+ MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 1, 1, 1, 0, 0)),
176+ MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 1, 1, 1, 0, 0)),
177+ MPP_VAR_FUNCTION(0x3, "ge1", "txd2", V(0, 1, 1, 1, 1, 0, 0)),
178+ MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 0, 0, 0, 0, 0)),
179+ MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 1, 1, 1, 0, 0)),
180+ MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1, 0, 0)),
181+ MPP_VAR_FUNCTION(0xb, "lcd", "d2", V(0, 0, 0, 0, 1, 0, 0))),
180182 MPP_MODE(23,
181− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
182− MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 1, 1, 1, 0)),
183− MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 1, 1, 1, 0)),
184− MPP_VAR_FUNCTION(0x3, "ge1", "txd3", V(0, 1, 1, 1, 1, 0)),
185− MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 0, 0, 0, 0)),
186− MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 1, 1, 1, 0)),
187− MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1, 0)),
188− MPP_VAR_FUNCTION(0xb, "lcd", "d3", V(0, 0, 0, 0, 1, 0))),
183+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 1)),
184+ MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 1, 1, 1, 0, 0)),
185+ MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 1, 1, 1, 0, 0)),
186+ MPP_VAR_FUNCTION(0x3, "ge1", "txd3", V(0, 1, 1, 1, 1, 0, 0)),
187+ MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 0, 0, 0, 0, 0)),
188+ MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 1, 1, 1, 0, 0)),
189+ MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1, 0, 0)),
190+ MPP_VAR_FUNCTION(0xb, "lcd", "d3", V(0, 0, 0, 0, 1, 0, 0))),
189191 MPP_MODE(24,
190− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
191− MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 1, 1, 1, 0)),
192− MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 1, 1, 1, 0)),
193− MPP_VAR_FUNCTION(0x3, "ge1", "rxd0", V(0, 1, 1, 1, 1, 0)),
194− MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 0, 0, 0, 0)),
195− MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 1, 1, 1, 0)),
196− MPP_VAR_FUNCTION(0xb, "lcd", "d4", V(0, 0, 0, 0, 1, 0))),
192+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 1)),
193+ MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 1, 1, 1, 0, 0)),
194+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 1, 1, 1, 0, 0)),
195+ MPP_VAR_FUNCTION(0x3, "ge1", "rxd0", V(0, 1, 1, 1, 1, 0, 0)),
196+ MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 0, 0, 0, 0, 0)),
197+ MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 1, 1, 1, 0, 0)),
198+ MPP_VAR_FUNCTION(0xb, "lcd", "d4", V(0, 0, 0, 0, 1, 0, 0))),
197199 MPP_MODE(25,
198− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
199− MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 1, 1, 1, 0)),
200− MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 1, 1, 1, 0)),
201− MPP_VAR_FUNCTION(0x3, "ge1", "rxd1", V(0, 1, 1, 1, 1, 0)),
202− MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 0, 0, 0, 0)),
203− MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 1, 1, 1, 0)),
204− MPP_VAR_FUNCTION(0xb, "lcd", "d5", V(0, 0, 0, 0, 1, 0))),
200+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 1)),
201+ MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 1, 1, 1, 0, 0)),
202+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 1, 1, 1, 0, 0)),
203+ MPP_VAR_FUNCTION(0x3, "ge1", "rxd1", V(0, 1, 1, 1, 1, 0, 0)),
204+ MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 0, 0, 0, 0, 0)),
205+ MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 1, 1, 1, 0, 0)),
206+ MPP_VAR_FUNCTION(0xb, "lcd", "d5", V(0, 0, 0, 0, 1, 0, 0))),
205207 MPP_MODE(26,
206− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
207− MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 1, 1, 1, 0)),
208− MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 1, 1, 1, 0)),
209− MPP_VAR_FUNCTION(0x3, "ge1", "rxd2", V(0, 1, 1, 1, 1, 0)),
210− MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 0, 0, 0, 0)),
211− MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 1, 1, 1, 0)),
212− MPP_VAR_FUNCTION(0xb, "lcd", "d6", V(0, 0, 0, 0, 1, 0))),
208+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 1)),
209+ MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 1, 1, 1, 0, 0)),
210+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 1, 1, 1, 0, 0)),
211+ MPP_VAR_FUNCTION(0x3, "ge1", "rxd2", V(0, 1, 1, 1, 1, 0, 0)),
212+ MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 0, 0, 0, 0, 0)),
213+ MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 1, 1, 1, 0, 0)),
214+ MPP_VAR_FUNCTION(0xb, "lcd", "d6", V(0, 0, 0, 0, 1, 0, 0))),
213215 MPP_MODE(27,
214− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
215− MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 1, 1, 1, 0)),
216− MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 1, 1, 1, 0)),
217− MPP_VAR_FUNCTION(0x3, "ge1", "rxd3", V(0, 1, 1, 1, 1, 0)),
218− MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 0, 0, 0, 0)),
219− MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 1, 1, 1, 0)),
220− MPP_VAR_FUNCTION(0xb, "lcd", "d7", V(0, 0, 0, 0, 1, 0))),
216+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 1)),
217+ MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 1, 1, 1, 0, 0)),
218+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 1, 1, 1, 0, 0)),
219+ MPP_VAR_FUNCTION(0x3, "ge1", "rxd3", V(0, 1, 1, 1, 1, 0, 0)),
220+ MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 0, 0, 0, 0, 0)),
221+ MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 1, 1, 1, 0, 0)),
222+ MPP_VAR_FUNCTION(0xb, "lcd", "d7", V(0, 0, 0, 0, 1, 0, 0))),
221223 MPP_MODE(28,
222− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
223− MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 1, 1, 1, 0)),
224− MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 1, 1, 1, 0)),
225− MPP_VAR_FUNCTION(0x3, "ge1", "col", V(0, 1, 1, 1, 1, 0)),
226− MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 0, 0, 0, 0)),
227− MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 1, 1, 1, 0)),
228− MPP_VAR_FUNCTION(0xb, "lcd", "d8", V(0, 0, 0, 0, 1, 0))),
224+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 0)),
225+ MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 1, 1, 1, 0, 0)),
226+ MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 1, 1, 1, 0, 0)),
227+ MPP_VAR_FUNCTION(0x3, "ge1", "col", V(0, 1, 1, 1, 1, 0, 0)),
228+ MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 0, 0, 0, 0, 0)),
229+ MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 1, 1, 1, 0, 0)),
230+ MPP_VAR_FUNCTION(0xb, "lcd", "d8", V(0, 0, 0, 0, 1, 0, 0)),
231+ MPP_VAR_FUNCTION(0x1, "nand", "ren", V(0, 0, 0, 0, 0, 0, 1))),
229232 MPP_MODE(29,
230− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
231− MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 1, 1, 1, 0)),
232− MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 1, 1, 1, 0)),
233− MPP_VAR_FUNCTION(0x3, "ge1", "txclk", V(0, 1, 1, 1, 1, 0)),
234− MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 0, 0, 0, 0)),
235− MPP_VAR_FUNCTION(0xb, "lcd", "d9", V(0, 0, 0, 0, 1, 0))),
233+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 0)),
234+ MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 1, 1, 1, 0, 0)),
235+ MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 1, 1, 1, 0, 0)),
236+ MPP_VAR_FUNCTION(0x3, "ge1", "txclk", V(0, 1, 1, 1, 1, 0, 0)),
237+ MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 0, 0, 0, 0, 0)),
238+ MPP_VAR_FUNCTION(0xb, "lcd", "d9", V(0, 0, 0, 0, 1, 0, 0)),
239+ MPP_VAR_FUNCTION(0x1, "nand", "wen", V(0, 0, 0, 0, 0, 0, 1))),
236240 MPP_MODE(30,
237− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
238− MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 1, 1, 1, 0)),
239− MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 1, 1, 1, 0)),
240− MPP_VAR_FUNCTION(0x3, "ge1", "rxctl", V(0, 1, 1, 1, 1, 0)),
241− MPP_VAR_FUNCTION(0xb, "lcd", "d10", V(0, 0, 0, 0, 1, 0))),
241+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 1)),
242+ MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 1, 1, 1, 0, 0)),
243+ MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 1, 1, 1, 0, 0)),
244+ MPP_VAR_FUNCTION(0x3, "ge1", "rxctl", V(0, 1, 1, 1, 1, 0, 0)),
245+ MPP_VAR_FUNCTION(0xb, "lcd", "d10", V(0, 0, 0, 0, 1, 0, 0))),
242246 MPP_MODE(31,
243− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
244− MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 1, 1, 1, 0)),
245− MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 1, 1, 1, 0)),
246− MPP_VAR_FUNCTION(0x3, "ge1", "rxclk", V(0, 1, 1, 1, 1, 0)),
247− MPP_VAR_FUNCTION(0xb, "lcd", "d11", V(0, 0, 0, 0, 1, 0))),
247+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 1)),
248+ MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 1, 1, 1, 0, 0)),
249+ MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 1, 1, 1, 0, 0)),
250+ MPP_VAR_FUNCTION(0x3, "ge1", "rxclk", V(0, 1, 1, 1, 1, 0, 0)),
251+ MPP_VAR_FUNCTION(0xb, "lcd", "d11", V(0, 0, 0, 0, 1, 0, 0))),
248252 MPP_MODE(32,
249− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
250− MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 1, 1, 1, 0)),
251− MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 1, 1, 1, 0)),
252− MPP_VAR_FUNCTION(0x3, "ge1", "txclko", V(0, 1, 1, 1, 1, 0)),
253− MPP_VAR_FUNCTION(0xb, "lcd", "d12", V(0, 0, 0, 0, 1, 0))),
253+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 1)),
254+ MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 1, 1, 1, 0, 0)),
255+ MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 1, 1, 1, 0, 0)),
256+ MPP_VAR_FUNCTION(0x3, "ge1", "txclko", V(0, 1, 1, 1, 1, 0, 0)),
257+ MPP_VAR_FUNCTION(0xb, "lcd", "d12", V(0, 0, 0, 0, 1, 0, 0))),
254258 MPP_MODE(33,
255− MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 1, 1, 1, 1, 0)),
256− MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 1, 1, 1, 0)),
257− MPP_VAR_FUNCTION(0x3, "ge1", "txctl", V(0, 1, 1, 1, 1, 0)),
258− MPP_VAR_FUNCTION(0xb, "lcd", "d13", V(0, 0, 0, 0, 1, 0))),
259+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 1, 1, 1, 1, 0, 1)),
260+ MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 1, 1, 1, 0, 0)),
261+ MPP_VAR_FUNCTION(0x3, "ge1", "txctl", V(0, 1, 1, 1, 1, 0, 0)),
262+ MPP_VAR_FUNCTION(0xb, "lcd", "d13", V(0, 0, 0, 0, 1, 0, 0))),
259263 MPP_MODE(34,
260− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 1)),
261− MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 1, 1, 1, 0)),
262− MPP_VAR_FUNCTION(0x3, "ge1", "txen", V(0, 1, 1, 1, 1, 0)),
263− MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 0, 1, 1, 0)),
264− MPP_VAR_FUNCTION(0xb, "lcd", "d14", V(0, 0, 0, 0, 1, 0))),
264+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 1, 1)),
265+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 1, 1, 1, 0, 0)),
266+ MPP_VAR_FUNCTION(0x3, "ge1", "txen", V(0, 1, 1, 1, 1, 0, 0)),
267+ MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 0, 1, 1, 0, 0)),
268+ MPP_VAR_FUNCTION(0xb, "lcd", "d14", V(0, 0, 0, 0, 1, 0, 0)),
269+ MPP_VAR_FUNCTION(0x1, "nand", "ale", V(0, 0, 0, 0, 0, 0, 1))),
265270 MPP_MODE(35,
266− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
267− MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1, 0)),
268− MPP_VAR_FUNCTION(0x3, "ge1", "rxerr", V(0, 1, 1, 1, 1, 0)),
269− MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0)),
270− MPP_VAR_FUNCTION(0xb, "lcd", "d15", V(0, 0, 0, 0, 1, 0)),
271− MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(1, 1, 1, 1, 1, 0))),
271+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
272+ MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1, 0, 0)),
273+ MPP_VAR_FUNCTION(0x3, "ge1", "rxerr", V(0, 1, 1, 1, 1, 0, 0)),
274+ MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0, 0)),
275+ MPP_VAR_FUNCTION(0xb, "lcd", "d15", V(0, 0, 0, 0, 1, 0, 0)),
276+ MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(1, 1, 1, 1, 1, 0, 0)),
277+ MPP_VAR_FUNCTION(0x1, "nand", "cen", V(0, 0, 0, 0, 0, 0, 1))),
272278 MPP_MODE(36,
273− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1)),
274− MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 0, 1, 1, 0)),
275− MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 0, 1, 1, 0)),
276− MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(1, 0, 0, 1, 1, 0)),
277− MPP_VAR_FUNCTION(0xb, "twsi1", "sda", V(0, 0, 0, 0, 1, 0))),
279+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1, 1)),
280+ MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 0, 1, 1, 0, 0)),
281+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 0, 1, 1, 0, 0)),
282+ MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(1, 0, 0, 1, 1, 0, 0)),
283+ MPP_VAR_FUNCTION(0xb, "twsi1", "sda", V(0, 0, 0, 0, 1, 0, 0))),
278284 MPP_MODE(37,
279− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1)),
280− MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 0, 1, 1, 0)),
281− MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 0, 1, 1, 0)),
282− MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(1, 0, 0, 1, 1, 0)),
283− MPP_VAR_FUNCTION(0xb, "twsi1", "sck", V(0, 0, 0, 0, 1, 0))),
285+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1, 1)),
286+ MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 0, 1, 1, 0, 0)),
287+ MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 0, 1, 1, 0, 0)),
288+ MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(1, 0, 0, 1, 1, 0, 0)),
289+ MPP_VAR_FUNCTION(0xb, "twsi1", "sck", V(0, 0, 0, 0, 1, 0, 0))),
284290 MPP_MODE(38,
285− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1)),
286− MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 0, 1, 1, 0)),
287− MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 0, 1, 1, 0)),
288− MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(1, 0, 0, 1, 1, 0)),
289− MPP_VAR_FUNCTION(0xb, "lcd", "d18", V(0, 0, 0, 0, 1, 0))),
291+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1, 1)),
292+ MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 0, 1, 1, 0, 0)),
293+ MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 0, 1, 1, 0, 0)),
294+ MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(1, 0, 0, 1, 1, 0, 0)),
295+ MPP_VAR_FUNCTION(0xb, "lcd", "d18", V(0, 0, 0, 0, 1, 0, 0))),
290296 MPP_MODE(39,
291− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1)),
292− MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 0, 1, 1, 0)),
293− MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 0, 1, 1, 0)),
294− MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(1, 0, 0, 1, 1, 0)),
295− MPP_VAR_FUNCTION(0xb, "lcd", "d19", V(0, 0, 0, 0, 1, 0))),
297+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1, 1)),
298+ MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 0, 1, 1, 0, 0)),
299+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 0, 1, 1, 0, 0)),
300+ MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(1, 0, 0, 1, 1, 0, 0)),
301+ MPP_VAR_FUNCTION(0xb, "lcd", "d19", V(0, 0, 0, 0, 1, 0, 0))),
296302 MPP_MODE(40,
297− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1)),
298− MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 0, 1, 1, 0)),
299− MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 0, 1, 1, 0)),
300− MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(1, 0, 0, 1, 1, 0)),
301− MPP_VAR_FUNCTION(0xb, "lcd", "d20", V(0, 0, 0, 0, 1, 0))),
303+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1, 1)),
304+ MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 0, 1, 1, 0, 0)),
305+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 0, 1, 1, 0, 0)),
306+ MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(1, 0, 0, 1, 1, 0, 0)),
307+ MPP_VAR_FUNCTION(0xb, "lcd", "d20", V(0, 0, 0, 0, 1, 0, 0))),
302308 MPP_MODE(41,
303− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1)),
304− MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 0, 1, 1, 0)),
305− MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 0, 1, 1, 0)),
306− MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(1, 0, 0, 1, 1, 0)),
307− MPP_VAR_FUNCTION(0xb, "lcd", "d21", V(0, 0, 0, 0, 1, 0))),
309+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1, 1)),
310+ MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 0, 1, 1, 0, 0)),
311+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 0, 1, 1, 0, 0)),
312+ MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(1, 0, 0, 1, 1, 0, 0)),
313+ MPP_VAR_FUNCTION(0xb, "lcd", "d21", V(0, 0, 0, 0, 1, 0, 0))),
308314 MPP_MODE(42,
309− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1)),
310− MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 0, 1, 1, 0)),
311− MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 0, 1, 1, 0)),
312− MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(1, 0, 0, 1, 1, 0)),
313− MPP_VAR_FUNCTION(0xb, "lcd", "d22", V(0, 0, 0, 0, 1, 0))),
315+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1, 1)),
316+ MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 0, 1, 1, 0, 0)),
317+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 0, 1, 1, 0, 0)),
318+ MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(1, 0, 0, 1, 1, 0, 0)),
319+ MPP_VAR_FUNCTION(0xb, "lcd", "d22", V(0, 0, 0, 0, 1, 0, 0))),
314320 MPP_MODE(43,
315− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1)),
316− MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 0, 1, 1, 0)),
317− MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 0, 1, 1, 0)),
318− MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(1, 0, 0, 1, 1, 0)),
319− MPP_VAR_FUNCTION(0xb, "lcd", "d23", V(0, 0, 0, 0, 1, 0))),
321+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1, 1)),
322+ MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 0, 1, 1, 0, 0)),
323+ MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 0, 1, 1, 0, 0)),
324+ MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(1, 0, 0, 1, 1, 0, 0)),
325+ MPP_VAR_FUNCTION(0xb, "lcd", "d23", V(0, 0, 0, 0, 1, 0, 0))),
320326 MPP_MODE(44,
321− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1)),
322− MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 0, 1, 1, 0)),
323− MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 0, 1, 1, 0)),
324− MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(1, 0, 0, 1, 1, 0)),
325− MPP_VAR_FUNCTION(0xb, "lcd", "clk", V(0, 0, 0, 0, 1, 0))),
327+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1, 1)),
328+ MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 0, 1, 1, 0, 0)),
329+ MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 0, 1, 1, 0, 0)),
330+ MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(1, 0, 0, 1, 1, 0, 0)),
331+ MPP_VAR_FUNCTION(0xb, "lcd", "clk", V(0, 0, 0, 0, 1, 0, 0))),
326332 MPP_MODE(45,
327− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
328− MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 1, 0)),
329− MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 0, 1, 1, 0)),
330− MPP_VAR_FUNCTION(0xb, "lcd", "e", V(0, 0, 0, 0, 1, 0))),
333+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1, 1)),
334+ MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 1, 0, 0)),
335+ MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 0, 1, 1, 0, 0)),
336+ MPP_VAR_FUNCTION(0xb, "lcd", "e", V(0, 0, 0, 0, 1, 0, 0))),
331337 MPP_MODE(46,
332− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 0)),
333− MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 0, 1, 1, 0)),
334− MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 0, 1, 1, 0)),
335− MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1, 0))),
338+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 0, 0)),
339+ MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 0, 1, 1, 0, 0)),
340+ MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 0, 1, 1, 0, 0)),
341+ MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1, 0, 0))),
336342 MPP_MODE(47,
337− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 0)),
338− MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 0, 1, 1, 0)),
339− MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 0, 1, 1, 0)),
340− MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1, 0))),
343+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 0, 0)),
344+ MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 0, 1, 1, 0, 0)),
345+ MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 0, 1, 1, 0, 0)),
346+ MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1, 0, 0))),
341347 MPP_MODE(48,
342− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 0)),
343− MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 0, 1, 1, 0)),
344− MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 0, 1, 1, 0)),
345− MPP_VAR_FUNCTION(0xb, "lcd", "d16", V(0, 0, 0, 0, 1, 0))),
348+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 0, 0)),
349+ MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 0, 1, 1, 0, 0)),
350+ MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 0, 1, 1, 0, 0)),
351+ MPP_VAR_FUNCTION(0xb, "lcd", "d16", V(0, 0, 0, 0, 1, 0, 0))),
346352 MPP_MODE(49,
347− MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0, 1)),
348− MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 0, 0, 0, 1, 0)),
349− MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 0, 0)),
350− MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 0, 1, 1, 0)),
351− MPP_VAR_FUNCTION(0x5, "ptp", "clk", V(0, 0, 0, 1, 0, 0)),
352− MPP_VAR_FUNCTION(0xa, "pex", "clkreq", V(0, 0, 0, 0, 1, 0)),
353− MPP_VAR_FUNCTION(0xb, "lcd", "d17", V(0, 0, 0, 0, 1, 0))),
353+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0, 1, 1)),
354+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 0, 0, 0, 1, 0, 0)),
355+ MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 0, 0, 0)),
356+ MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 0, 1, 1, 0, 0)),
357+ MPP_VAR_FUNCTION(0x5, "ptp", "clk", V(0, 0, 0, 1, 0, 0, 0)),
358+ MPP_VAR_FUNCTION(0xa, "pex", "clkreq", V(0, 0, 0, 0, 1, 0, 0)),
359+ MPP_VAR_FUNCTION(0xb, "lcd", "d17", V(0, 0, 0, 0, 1, 0, 0))),
354360 };
355361
356362 static const struct mvebu_mpp_ctrl mv88f6180_mpp_controls[] = {
@@ -440,6 +446,17 @@ static struct mvebu_pinctrl_soc_info mv98dx4122_info = { · 83 unmodified lines
440446 .ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges),
441447 };
442448
449+static struct mvebu_pinctrl_soc_info mv98dx1135_info = {
450+ .variant = VARIANT_MV98DX1135,
451+ .controls = mv88f628x_mpp_controls,
452+ .ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls),
453+ .modes = mv88f6xxx_mpp_modes,
454+ .nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
455+ .gpioranges = mv88f628x_gpio_ranges,
456+ .ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges),
457+};
458+
459+
443460 static const struct of_device_id kirkwood_pinctrl_of_match[] = {
444461 { .compatible = "marvell,88f6180-pinctrl", .data = &mv88f6180_info },
445462 { .compatible = "marvell,88f6190-pinctrl", .data = &mv88f6190_info },
@@ -447,6 +464,7 @@ static const struct of_device_id kirkwood_pinctrl_of_match[] = { · 1 unmodified line
447464 { .compatible = "marvell,88f6281-pinctrl", .data = &mv88f6281_info },
448465 { .compatible = "marvell,88f6282-pinctrl", .data = &mv88f6282_info },
449466 { .compatible = "marvell,98dx4122-pinctrl", .data = &mv98dx4122_info },
467+ { .compatible = "marvell,98dx1135-pinctrl", .data = &mv98dx1135_info },
450468 { }
451469 };
452470
drivers/pinctrl/pinconf-generic.c+2−0
@@ -38,6 +38,7 @@ static const struct pin_config_item conf_items[] = { · 37 unmodified lines
3838 PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL, false),
3939 PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL, false),
4040 PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH, "output drive strength", "mA", true),
41+ PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH_UA, "output drive strength", "uA", true),
4142 PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "usec", true),
4243 PCONFDUMP(PIN_CONFIG_INPUT_ENABLE, "input enabled", NULL, false),
4344 PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL, false),
@@ -166,6 +167,7 @@ static const struct pinconf_generic_params dt_params[] = { · 122 unmodified lines
166167 { "drive-open-source", PIN_CONFIG_DRIVE_OPEN_SOURCE, 0 },
167168 { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 },
168169 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
170+ { "drive-strength-microamp", PIN_CONFIG_DRIVE_STRENGTH_UA, 0 },
169171 { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 },
170172 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
171173 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
drivers/pinctrl/pinctrl-bm1880.c+563−170
@@ -27,6 +27,7 @@ · 26 unmodified lines
2727 * @ngroups: Number of @groups
2828 * @funcs: Pinmux functions
2929 * @nfuncs: Number of @funcs
30+ * @pconf: Pinconf data
3031 */
3132 struct bm1880_pinctrl {
3233 void __iomem *base;
@@ -35,6 +36,7 @@ struct bm1880_pinctrl { · 2 unmodified lines
3536 unsigned int ngroups;
3637 const struct bm1880_pinmux_function *funcs;
3738 unsigned int nfuncs;
39+ const struct bm1880_pinconf_data *pinconf;
3840 };
3941
4042 /**
@@ -55,7 +57,6 @@ struct bm1880_pctrl_group { · 14 unmodified lines
5557 * @groups: List of pingroups for this function.
5658 * @ngroups: Number of entries in @groups.
5759 * @mux_val: Selector for this function
58− * @mux_mask: Mask for function specific selector
5960 * @mux: Offset of function specific mux
6061 * @mux_shift: Shift for function specific selector
6162 */
@@ -64,11 +65,18 @@ struct bm1880_pinmux_function { · 2 unmodified lines
6465 const char * const *groups;
6566 unsigned int ngroups;
6667 u32 mux_val;
67− u32 mux_mask;
6868 u32 mux;
6969 u8 mux_shift;
7070 };
7171
72+/**
73+ * struct bm1880_pinconf_data - pinconf data
74+ * @drv_bits: Drive strength bit width
75+ */
76+struct bm1880_pinconf_data {
77+ u32 drv_bits;
78+};
79+
7280 static const struct pinctrl_pin_desc bm1880_pins[] = {
7381 PINCTRL_PIN(0, "MIO0"),
7482 PINCTRL_PIN(1, "MIO1"),
@@ -636,165 +644,273 @@ static const char * const i2s1_group[] = { "i2s1_grp" }; · 561 unmodified lines
636644 static const char * const i2s1_mclkin_group[] = { "i2s1_mclkin_grp" };
637645 static const char * const spi0_group[] = { "spi0_grp" };
638646
639−#define BM1880_PINMUX_FUNCTION(fname, mval, mask) \
647+#define BM1880_PINMUX_FUNCTION(fname, mval) \
640648 [F_##fname] = { \
641649 .name = #fname, \
642650 .groups = fname##_group, \
643651 .ngroups = ARRAY_SIZE(fname##_group), \
644652 .mux_val = mval, \
645− .mux_mask = mask, \
646653 }
647654
648−#define BM1880_PINMUX_FUNCTION_MUX(fname, mval, mask, offset, shift)\
649− [F_##fname] = { \
650− .name = #fname, \
651− .groups = fname##_group, \
652− .ngroups = ARRAY_SIZE(fname##_group), \
653− .mux_val = mval, \
654− .mux_mask = mask, \
655− .mux = offset, \
656− .mux_shift = shift, \
655+static const struct bm1880_pinmux_function bm1880_pmux_functions[] = {
656+ BM1880_PINMUX_FUNCTION(nand, 2),
657+ BM1880_PINMUX_FUNCTION(spi, 0),
658+ BM1880_PINMUX_FUNCTION(emmc, 1),
659+ BM1880_PINMUX_FUNCTION(sdio, 0),
660+ BM1880_PINMUX_FUNCTION(eth0, 0),
661+ BM1880_PINMUX_FUNCTION(pwm0, 2),
662+ BM1880_PINMUX_FUNCTION(pwm1, 2),
663+ BM1880_PINMUX_FUNCTION(pwm2, 2),
664+ BM1880_PINMUX_FUNCTION(pwm3, 2),
665+ BM1880_PINMUX_FUNCTION(pwm4, 2),
666+ BM1880_PINMUX_FUNCTION(pwm5, 2),
667+ BM1880_PINMUX_FUNCTION(pwm6, 2),
668+ BM1880_PINMUX_FUNCTION(pwm7, 2),
669+ BM1880_PINMUX_FUNCTION(pwm8, 2),
670+ BM1880_PINMUX_FUNCTION(pwm9, 2),
671+ BM1880_PINMUX_FUNCTION(pwm10, 2),
672+ BM1880_PINMUX_FUNCTION(pwm11, 2),
673+ BM1880_PINMUX_FUNCTION(pwm12, 2),
674+ BM1880_PINMUX_FUNCTION(pwm13, 2),
675+ BM1880_PINMUX_FUNCTION(pwm14, 2),
676+ BM1880_PINMUX_FUNCTION(pwm15, 2),
677+ BM1880_PINMUX_FUNCTION(pwm16, 2),
678+ BM1880_PINMUX_FUNCTION(pwm17, 2),
679+ BM1880_PINMUX_FUNCTION(pwm18, 2),
680+ BM1880_PINMUX_FUNCTION(pwm19, 2),
681+ BM1880_PINMUX_FUNCTION(pwm20, 2),
682+ BM1880_PINMUX_FUNCTION(pwm21, 2),
683+ BM1880_PINMUX_FUNCTION(pwm22, 2),
684+ BM1880_PINMUX_FUNCTION(pwm23, 2),
685+ BM1880_PINMUX_FUNCTION(pwm24, 2),
686+ BM1880_PINMUX_FUNCTION(pwm25, 2),
687+ BM1880_PINMUX_FUNCTION(pwm26, 2),
688+ BM1880_PINMUX_FUNCTION(pwm27, 2),
689+ BM1880_PINMUX_FUNCTION(pwm28, 2),
690+ BM1880_PINMUX_FUNCTION(pwm29, 2),
691+ BM1880_PINMUX_FUNCTION(pwm30, 2),
692+ BM1880_PINMUX_FUNCTION(pwm31, 2),
693+ BM1880_PINMUX_FUNCTION(pwm32, 2),
694+ BM1880_PINMUX_FUNCTION(pwm33, 2),
695+ BM1880_PINMUX_FUNCTION(pwm34, 2),
696+ BM1880_PINMUX_FUNCTION(pwm35, 2),
697+ BM1880_PINMUX_FUNCTION(pwm36, 2),
698+ BM1880_PINMUX_FUNCTION(pwm37, 2),
699+ BM1880_PINMUX_FUNCTION(i2c0, 1),
700+ BM1880_PINMUX_FUNCTION(i2c1, 1),
701+ BM1880_PINMUX_FUNCTION(i2c2, 1),
702+ BM1880_PINMUX_FUNCTION(i2c3, 1),
703+ BM1880_PINMUX_FUNCTION(i2c4, 1),
704+ BM1880_PINMUX_FUNCTION(uart0, 3),
705+ BM1880_PINMUX_FUNCTION(uart1, 3),
706+ BM1880_PINMUX_FUNCTION(uart2, 3),
707+ BM1880_PINMUX_FUNCTION(uart3, 3),
708+ BM1880_PINMUX_FUNCTION(uart4, 1),
709+ BM1880_PINMUX_FUNCTION(uart5, 1),
710+ BM1880_PINMUX_FUNCTION(uart6, 1),
711+ BM1880_PINMUX_FUNCTION(uart7, 1),
712+ BM1880_PINMUX_FUNCTION(uart8, 1),
713+ BM1880_PINMUX_FUNCTION(uart9, 1),
714+ BM1880_PINMUX_FUNCTION(uart10, 1),
715+ BM1880_PINMUX_FUNCTION(uart11, 1),
716+ BM1880_PINMUX_FUNCTION(uart12, 3),
717+ BM1880_PINMUX_FUNCTION(uart13, 3),
718+ BM1880_PINMUX_FUNCTION(uart14, 3),
719+ BM1880_PINMUX_FUNCTION(uart15, 3),
720+ BM1880_PINMUX_FUNCTION(gpio0, 0),
721+ BM1880_PINMUX_FUNCTION(gpio1, 0),
722+ BM1880_PINMUX_FUNCTION(gpio2, 0),
723+ BM1880_PINMUX_FUNCTION(gpio3, 0),
724+ BM1880_PINMUX_FUNCTION(gpio4, 0),
725+ BM1880_PINMUX_FUNCTION(gpio5, 0),
726+ BM1880_PINMUX_FUNCTION(gpio6, 0),
727+ BM1880_PINMUX_FUNCTION(gpio7, 0),
728+ BM1880_PINMUX_FUNCTION(gpio8, 0),
729+ BM1880_PINMUX_FUNCTION(gpio9, 0),
730+ BM1880_PINMUX_FUNCTION(gpio10, 0),
731+ BM1880_PINMUX_FUNCTION(gpio11, 0),
732+ BM1880_PINMUX_FUNCTION(gpio12, 1),
733+ BM1880_PINMUX_FUNCTION(gpio13, 1),
734+ BM1880_PINMUX_FUNCTION(gpio14, 0),
735+ BM1880_PINMUX_FUNCTION(gpio15, 0),
736+ BM1880_PINMUX_FUNCTION(gpio16, 0),
737+ BM1880_PINMUX_FUNCTION(gpio17, 0),
738+ BM1880_PINMUX_FUNCTION(gpio18, 0),
739+ BM1880_PINMUX_FUNCTION(gpio19, 0),
740+ BM1880_PINMUX_FUNCTION(gpio20, 0),
741+ BM1880_PINMUX_FUNCTION(gpio21, 0),
742+ BM1880_PINMUX_FUNCTION(gpio22, 0),
743+ BM1880_PINMUX_FUNCTION(gpio23, 0),
744+ BM1880_PINMUX_FUNCTION(gpio24, 0),
745+ BM1880_PINMUX_FUNCTION(gpio25, 0),
746+ BM1880_PINMUX_FUNCTION(gpio26, 0),
747+ BM1880_PINMUX_FUNCTION(gpio27, 0),
748+ BM1880_PINMUX_FUNCTION(gpio28, 0),
749+ BM1880_PINMUX_FUNCTION(gpio29, 0),
750+ BM1880_PINMUX_FUNCTION(gpio30, 0),
751+ BM1880_PINMUX_FUNCTION(gpio31, 0),
752+ BM1880_PINMUX_FUNCTION(gpio32, 0),
753+ BM1880_PINMUX_FUNCTION(gpio33, 0),
754+ BM1880_PINMUX_FUNCTION(gpio34, 0),
755+ BM1880_PINMUX_FUNCTION(gpio35, 0),
756+ BM1880_PINMUX_FUNCTION(gpio36, 0),
757+ BM1880_PINMUX_FUNCTION(gpio37, 0),
758+ BM1880_PINMUX_FUNCTION(gpio38, 0),
759+ BM1880_PINMUX_FUNCTION(gpio39, 0),
760+ BM1880_PINMUX_FUNCTION(gpio40, 0),
761+ BM1880_PINMUX_FUNCTION(gpio41, 0),
762+ BM1880_PINMUX_FUNCTION(gpio42, 0),
763+ BM1880_PINMUX_FUNCTION(gpio43, 0),
764+ BM1880_PINMUX_FUNCTION(gpio44, 0),
765+ BM1880_PINMUX_FUNCTION(gpio45, 0),
766+ BM1880_PINMUX_FUNCTION(gpio46, 0),
767+ BM1880_PINMUX_FUNCTION(gpio47, 0),
768+ BM1880_PINMUX_FUNCTION(gpio48, 0),
769+ BM1880_PINMUX_FUNCTION(gpio49, 0),
770+ BM1880_PINMUX_FUNCTION(gpio50, 0),
771+ BM1880_PINMUX_FUNCTION(gpio51, 0),
772+ BM1880_PINMUX_FUNCTION(gpio52, 0),
773+ BM1880_PINMUX_FUNCTION(gpio53, 0),
774+ BM1880_PINMUX_FUNCTION(gpio54, 0),
775+ BM1880_PINMUX_FUNCTION(gpio55, 0),
776+ BM1880_PINMUX_FUNCTION(gpio56, 0),
777+ BM1880_PINMUX_FUNCTION(gpio57, 0),
778+ BM1880_PINMUX_FUNCTION(gpio58, 0),
779+ BM1880_PINMUX_FUNCTION(gpio59, 0),
780+ BM1880_PINMUX_FUNCTION(gpio60, 0),
781+ BM1880_PINMUX_FUNCTION(gpio61, 0),
782+ BM1880_PINMUX_FUNCTION(gpio62, 0),
783+ BM1880_PINMUX_FUNCTION(gpio63, 0),
784+ BM1880_PINMUX_FUNCTION(gpio64, 0),
785+ BM1880_PINMUX_FUNCTION(gpio65, 0),
786+ BM1880_PINMUX_FUNCTION(gpio66, 0),
787+ BM1880_PINMUX_FUNCTION(gpio67, 0),
788+ BM1880_PINMUX_FUNCTION(eth1, 1),
789+ BM1880_PINMUX_FUNCTION(i2s0, 2),
790+ BM1880_PINMUX_FUNCTION(i2s0_mclkin, 1),
791+ BM1880_PINMUX_FUNCTION(i2s1, 2),
792+ BM1880_PINMUX_FUNCTION(i2s1_mclkin, 1),
793+ BM1880_PINMUX_FUNCTION(spi0, 1),
794+};
795+
796+#define BM1880_PINCONF_DAT(_width) \
797+ { \
798+ .drv_bits = _width, \
657799 }
658800
659−static const struct bm1880_pinmux_function bm1880_pmux_functions[] = {
660− BM1880_PINMUX_FUNCTION(nand, 2, 0x03),
661− BM1880_PINMUX_FUNCTION(spi, 0, 0x03),
662− BM1880_PINMUX_FUNCTION(emmc, 1, 0x03),
663− BM1880_PINMUX_FUNCTION(sdio, 0, 0x03),
664− BM1880_PINMUX_FUNCTION(eth0, 0, 0x03),
665− BM1880_PINMUX_FUNCTION_MUX(pwm0, 2, 0x0F, 0x50, 0x00),
666− BM1880_PINMUX_FUNCTION_MUX(pwm1, 2, 0x0F, 0x50, 0x04),
667− BM1880_PINMUX_FUNCTION_MUX(pwm2, 2, 0x0F, 0x50, 0x08),
668− BM1880_PINMUX_FUNCTION_MUX(pwm3, 2, 0x0F, 0x50, 0x0C),
669− BM1880_PINMUX_FUNCTION_MUX(pwm4, 2, 0x0F, 0x50, 0x10),
670− BM1880_PINMUX_FUNCTION_MUX(pwm5, 2, 0x0F, 0x50, 0x14),
671− BM1880_PINMUX_FUNCTION_MUX(pwm6, 2, 0x0F, 0x50, 0x18),
672− BM1880_PINMUX_FUNCTION_MUX(pwm7, 2, 0x0F, 0x50, 0x1C),
673− BM1880_PINMUX_FUNCTION_MUX(pwm8, 2, 0x0F, 0x54, 0x00),
674− BM1880_PINMUX_FUNCTION_MUX(pwm9, 2, 0x0F, 0x54, 0x04),
675− BM1880_PINMUX_FUNCTION_MUX(pwm10, 2, 0x0F, 0x54, 0x08),
676− BM1880_PINMUX_FUNCTION_MUX(pwm11, 2, 0x0F, 0x54, 0x0C),
677− BM1880_PINMUX_FUNCTION_MUX(pwm12, 2, 0x0F, 0x54, 0x10),
678− BM1880_PINMUX_FUNCTION_MUX(pwm13, 2, 0x0F, 0x54, 0x14),
679− BM1880_PINMUX_FUNCTION_MUX(pwm14, 2, 0x0F, 0x54, 0x18),
680− BM1880_PINMUX_FUNCTION_MUX(pwm15, 2, 0x0F, 0x54, 0x1C),
681− BM1880_PINMUX_FUNCTION_MUX(pwm16, 2, 0x0F, 0x58, 0x00),
682− BM1880_PINMUX_FUNCTION_MUX(pwm17, 2, 0x0F, 0x58, 0x04),
683− BM1880_PINMUX_FUNCTION_MUX(pwm18, 2, 0x0F, 0x58, 0x08),
684− BM1880_PINMUX_FUNCTION_MUX(pwm19, 2, 0x0F, 0x58, 0x0C),
685− BM1880_PINMUX_FUNCTION_MUX(pwm20, 2, 0x0F, 0x58, 0x10),
686− BM1880_PINMUX_FUNCTION_MUX(pwm21, 2, 0x0F, 0x58, 0x14),
687− BM1880_PINMUX_FUNCTION_MUX(pwm22, 2, 0x0F, 0x58, 0x18),
688− BM1880_PINMUX_FUNCTION_MUX(pwm23, 2, 0x0F, 0x58, 0x1C),
689− BM1880_PINMUX_FUNCTION_MUX(pwm24, 2, 0x0F, 0x5C, 0x00),
690− BM1880_PINMUX_FUNCTION_MUX(pwm25, 2, 0x0F, 0x5C, 0x04),
691− BM1880_PINMUX_FUNCTION_MUX(pwm26, 2, 0x0F, 0x5C, 0x08),
692− BM1880_PINMUX_FUNCTION_MUX(pwm27, 2, 0x0F, 0x5C, 0x0C),
693− BM1880_PINMUX_FUNCTION_MUX(pwm28, 2, 0x0F, 0x5C, 0x10),
694− BM1880_PINMUX_FUNCTION_MUX(pwm29, 2, 0x0F, 0x5C, 0x14),
695− BM1880_PINMUX_FUNCTION_MUX(pwm30, 2, 0x0F, 0x5C, 0x18),
696− BM1880_PINMUX_FUNCTION_MUX(pwm31, 2, 0x0F, 0x5C, 0x1C),
697− BM1880_PINMUX_FUNCTION_MUX(pwm32, 2, 0x0F, 0x60, 0x00),
698− BM1880_PINMUX_FUNCTION_MUX(pwm33, 2, 0x0F, 0x60, 0x04),
699− BM1880_PINMUX_FUNCTION_MUX(pwm34, 2, 0x0F, 0x60, 0x08),
700− BM1880_PINMUX_FUNCTION_MUX(pwm35, 2, 0x0F, 0x60, 0x0C),
701− BM1880_PINMUX_FUNCTION_MUX(pwm36, 2, 0x0F, 0x60, 0x10),
702− BM1880_PINMUX_FUNCTION_MUX(pwm37, 2, 0x0F, 0x60, 0x1C),
703− BM1880_PINMUX_FUNCTION(i2c0, 1, 0x03),
704− BM1880_PINMUX_FUNCTION(i2c1, 1, 0x03),
705− BM1880_PINMUX_FUNCTION(i2c2, 1, 0x03),
706− BM1880_PINMUX_FUNCTION(i2c3, 1, 0x03),
707− BM1880_PINMUX_FUNCTION(i2c4, 1, 0x03),
708− BM1880_PINMUX_FUNCTION(uart0, 1, 0x03),
709− BM1880_PINMUX_FUNCTION(uart1, 1, 0x03),
710− BM1880_PINMUX_FUNCTION(uart2, 1, 0x03),
711− BM1880_PINMUX_FUNCTION(uart3, 1, 0x03),
712− BM1880_PINMUX_FUNCTION(uart4, 1, 0x03),
713− BM1880_PINMUX_FUNCTION(uart5, 1, 0x03),
714− BM1880_PINMUX_FUNCTION(uart6, 1, 0x03),
715− BM1880_PINMUX_FUNCTION(uart7, 1, 0x03),
716− BM1880_PINMUX_FUNCTION(uart8, 1, 0x03),
717− BM1880_PINMUX_FUNCTION(uart9, 1, 0x03),
718− BM1880_PINMUX_FUNCTION(uart10, 1, 0x03),
719− BM1880_PINMUX_FUNCTION(uart11, 1, 0x03),
720− BM1880_PINMUX_FUNCTION(uart12, 3, 0x03),
721− BM1880_PINMUX_FUNCTION(uart13, 3, 0x03),
722− BM1880_PINMUX_FUNCTION(uart14, 3, 0x03),
723− BM1880_PINMUX_FUNCTION(uart15, 3, 0x03),
724− BM1880_PINMUX_FUNCTION_MUX(gpio0, 0, 0x03, 0x4E0, 0x14),
725− BM1880_PINMUX_FUNCTION_MUX(gpio1, 0, 0x03, 0x4E4, 0x04),
726− BM1880_PINMUX_FUNCTION_MUX(gpio2, 0, 0x03, 0x4E4, 0x14),
727− BM1880_PINMUX_FUNCTION_MUX(gpio3, 0, 0x03, 0x4E8, 0x04),
728− BM1880_PINMUX_FUNCTION_MUX(gpio4, 0, 0x03, 0x4E8, 0x14),
729− BM1880_PINMUX_FUNCTION_MUX(gpio5, 0, 0x03, 0x4EC, 0x04),
730− BM1880_PINMUX_FUNCTION_MUX(gpio6, 0, 0x03, 0x4EC, 0x14),
731− BM1880_PINMUX_FUNCTION_MUX(gpio7, 0, 0x03, 0x4F0, 0x04),
732− BM1880_PINMUX_FUNCTION_MUX(gpio8, 0, 0x03, 0x4F0, 0x14),
733− BM1880_PINMUX_FUNCTION_MUX(gpio9, 0, 0x03, 0x4F4, 0x04),
734− BM1880_PINMUX_FUNCTION_MUX(gpio10, 0, 0x03, 0x4F4, 0x14),
735− BM1880_PINMUX_FUNCTION_MUX(gpio11, 0, 0x03, 0x4F8, 0x04),
736− BM1880_PINMUX_FUNCTION_MUX(gpio12, 1, 0x03, 0x4F8, 0x14),
737− BM1880_PINMUX_FUNCTION_MUX(gpio13, 1, 0x03, 0x4FC, 0x04),
738− BM1880_PINMUX_FUNCTION_MUX(gpio14, 0, 0x03, 0x474, 0x14),
739− BM1880_PINMUX_FUNCTION_MUX(gpio15, 0, 0x03, 0x478, 0x04),
740− BM1880_PINMUX_FUNCTION_MUX(gpio16, 0, 0x03, 0x478, 0x14),
741− BM1880_PINMUX_FUNCTION_MUX(gpio17, 0, 0x03, 0x47C, 0x04),
742− BM1880_PINMUX_FUNCTION_MUX(gpio18, 0, 0x03, 0x47C, 0x14),
743− BM1880_PINMUX_FUNCTION_MUX(gpio19, 0, 0x03, 0x480, 0x04),
744− BM1880_PINMUX_FUNCTION_MUX(gpio20, 0, 0x03, 0x480, 0x14),
745− BM1880_PINMUX_FUNCTION_MUX(gpio21, 0, 0x03, 0x484, 0x04),
746− BM1880_PINMUX_FUNCTION_MUX(gpio22, 0, 0x03, 0x484, 0x14),
747− BM1880_PINMUX_FUNCTION_MUX(gpio23, 0, 0x03, 0x488, 0x04),
748− BM1880_PINMUX_FUNCTION_MUX(gpio24, 0, 0x03, 0x488, 0x14),
749− BM1880_PINMUX_FUNCTION_MUX(gpio25, 0, 0x03, 0x48C, 0x04),
750− BM1880_PINMUX_FUNCTION_MUX(gpio26, 0, 0x03, 0x48C, 0x14),
751− BM1880_PINMUX_FUNCTION_MUX(gpio27, 0, 0x03, 0x490, 0x04),
752− BM1880_PINMUX_FUNCTION_MUX(gpio28, 0, 0x03, 0x490, 0x14),
753− BM1880_PINMUX_FUNCTION_MUX(gpio29, 0, 0x03, 0x494, 0x04),
754− BM1880_PINMUX_FUNCTION_MUX(gpio30, 0, 0x03, 0x494, 0x14),
755− BM1880_PINMUX_FUNCTION_MUX(gpio31, 0, 0x03, 0x498, 0x04),
756− BM1880_PINMUX_FUNCTION_MUX(gpio32, 0, 0x03, 0x498, 0x14),
757− BM1880_PINMUX_FUNCTION_MUX(gpio33, 0, 0x03, 0x49C, 0x04),
758− BM1880_PINMUX_FUNCTION_MUX(gpio34, 0, 0x03, 0x49C, 0x14),
759− BM1880_PINMUX_FUNCTION_MUX(gpio35, 0, 0x03, 0x4A0, 0x04),
760− BM1880_PINMUX_FUNCTION_MUX(gpio36, 0, 0x03, 0x4A0, 0x14),
761− BM1880_PINMUX_FUNCTION_MUX(gpio37, 0, 0x03, 0x4A4, 0x04),
762− BM1880_PINMUX_FUNCTION_MUX(gpio38, 0, 0x03, 0x4A4, 0x14),
763− BM1880_PINMUX_FUNCTION_MUX(gpio39, 0, 0x03, 0x4A8, 0x04),
764− BM1880_PINMUX_FUNCTION_MUX(gpio40, 0, 0x03, 0x4A8, 0x14),
765− BM1880_PINMUX_FUNCTION_MUX(gpio41, 0, 0x03, 0x4AC, 0x04),
766− BM1880_PINMUX_FUNCTION_MUX(gpio42, 0, 0x03, 0x4AC, 0x14),
767− BM1880_PINMUX_FUNCTION_MUX(gpio43, 0, 0x03, 0x4B0, 0x04),
768− BM1880_PINMUX_FUNCTION_MUX(gpio44, 0, 0x03, 0x4B0, 0x14),
769− BM1880_PINMUX_FUNCTION_MUX(gpio45, 0, 0x03, 0x4B4, 0x04),
770− BM1880_PINMUX_FUNCTION_MUX(gpio46, 0, 0x03, 0x4B4, 0x14),
771− BM1880_PINMUX_FUNCTION_MUX(gpio47, 0, 0x03, 0x4B8, 0x04),
772− BM1880_PINMUX_FUNCTION_MUX(gpio48, 0, 0x03, 0x4B8, 0x14),
773− BM1880_PINMUX_FUNCTION_MUX(gpio49, 0, 0x03, 0x4BC, 0x04),
774− BM1880_PINMUX_FUNCTION_MUX(gpio50, 0, 0x03, 0x4BC, 0x14),
775− BM1880_PINMUX_FUNCTION_MUX(gpio51, 0, 0x03, 0x4C0, 0x04),
776− BM1880_PINMUX_FUNCTION_MUX(gpio52, 0, 0x03, 0x4C0, 0x14),
777− BM1880_PINMUX_FUNCTION_MUX(gpio53, 0, 0x03, 0x4C4, 0x04),
778− BM1880_PINMUX_FUNCTION_MUX(gpio54, 0, 0x03, 0x4C4, 0x14),
779− BM1880_PINMUX_FUNCTION_MUX(gpio55, 0, 0x03, 0x4C8, 0x04),
780− BM1880_PINMUX_FUNCTION_MUX(gpio56, 0, 0x03, 0x4C8, 0x14),
781− BM1880_PINMUX_FUNCTION_MUX(gpio57, 0, 0x03, 0x4CC, 0x04),
782− BM1880_PINMUX_FUNCTION_MUX(gpio58, 0, 0x03, 0x4CC, 0x14),
783− BM1880_PINMUX_FUNCTION_MUX(gpio59, 0, 0x03, 0x4D0, 0x04),
784− BM1880_PINMUX_FUNCTION_MUX(gpio60, 0, 0x03, 0x4D0, 0x14),
785− BM1880_PINMUX_FUNCTION_MUX(gpio61, 0, 0x03, 0x4D4, 0x04),
786− BM1880_PINMUX_FUNCTION_MUX(gpio62, 0, 0x03, 0x4D4, 0x14),
787− BM1880_PINMUX_FUNCTION_MUX(gpio63, 0, 0x03, 0x4D8, 0x04),
788− BM1880_PINMUX_FUNCTION_MUX(gpio64, 0, 0x03, 0x4D8, 0x14),
789− BM1880_PINMUX_FUNCTION_MUX(gpio65, 0, 0x03, 0x4DC, 0x04),
790− BM1880_PINMUX_FUNCTION_MUX(gpio66, 0, 0x03, 0x4DC, 0x14),
791− BM1880_PINMUX_FUNCTION_MUX(gpio67, 0, 0x03, 0x4E0, 0x04),
792− BM1880_PINMUX_FUNCTION(eth1, 1, 0x03),
793− BM1880_PINMUX_FUNCTION(i2s0, 2, 0x03),
794− BM1880_PINMUX_FUNCTION(i2s0_mclkin, 1, 0x03),
795− BM1880_PINMUX_FUNCTION(i2s1, 2, 0x03),
796− BM1880_PINMUX_FUNCTION(i2s1_mclkin, 1, 0x03),
797− BM1880_PINMUX_FUNCTION(spi0, 1, 0x03),
801+static const struct bm1880_pinconf_data bm1880_pinconf[] = {
802+ BM1880_PINCONF_DAT(0x03),
803+ BM1880_PINCONF_DAT(0x03),
804+ BM1880_PINCONF_DAT(0x03),
805+ BM1880_PINCONF_DAT(0x03),
806+ BM1880_PINCONF_DAT(0x03),
807+ BM1880_PINCONF_DAT(0x03),
808+ BM1880_PINCONF_DAT(0x03),
809+ BM1880_PINCONF_DAT(0x03),
810+ BM1880_PINCONF_DAT(0x03),
811+ BM1880_PINCONF_DAT(0x03),
812+ BM1880_PINCONF_DAT(0x03),
813+ BM1880_PINCONF_DAT(0x03),
814+ BM1880_PINCONF_DAT(0x03),
815+ BM1880_PINCONF_DAT(0x03),
816+ BM1880_PINCONF_DAT(0x03),
817+ BM1880_PINCONF_DAT(0x03),
818+ BM1880_PINCONF_DAT(0x03),
819+ BM1880_PINCONF_DAT(0x03),
820+ BM1880_PINCONF_DAT(0x03),
821+ BM1880_PINCONF_DAT(0x03),
822+ BM1880_PINCONF_DAT(0x03),
823+ BM1880_PINCONF_DAT(0x03),
824+ BM1880_PINCONF_DAT(0x03),
825+ BM1880_PINCONF_DAT(0x03),
826+ BM1880_PINCONF_DAT(0x03),
827+ BM1880_PINCONF_DAT(0x03),
828+ BM1880_PINCONF_DAT(0x03),
829+ BM1880_PINCONF_DAT(0x03),
830+ BM1880_PINCONF_DAT(0x03),
831+ BM1880_PINCONF_DAT(0x03),
832+ BM1880_PINCONF_DAT(0x03),
833+ BM1880_PINCONF_DAT(0x03),
834+ BM1880_PINCONF_DAT(0x03),
835+ BM1880_PINCONF_DAT(0x03),
836+ BM1880_PINCONF_DAT(0x03),
837+ BM1880_PINCONF_DAT(0x03),
838+ BM1880_PINCONF_DAT(0x03),
839+ BM1880_PINCONF_DAT(0x03),
840+ BM1880_PINCONF_DAT(0x03),
841+ BM1880_PINCONF_DAT(0x03),
842+ BM1880_PINCONF_DAT(0x03),
843+ BM1880_PINCONF_DAT(0x03),
844+ BM1880_PINCONF_DAT(0x03),
845+ BM1880_PINCONF_DAT(0x03),
846+ BM1880_PINCONF_DAT(0x03),
847+ BM1880_PINCONF_DAT(0x03),
848+ BM1880_PINCONF_DAT(0x03),
849+ BM1880_PINCONF_DAT(0x03),
850+ BM1880_PINCONF_DAT(0x03),
851+ BM1880_PINCONF_DAT(0x03),
852+ BM1880_PINCONF_DAT(0x03),
853+ BM1880_PINCONF_DAT(0x03),
854+ BM1880_PINCONF_DAT(0x03),
855+ BM1880_PINCONF_DAT(0x03),
856+ BM1880_PINCONF_DAT(0x03),
857+ BM1880_PINCONF_DAT(0x03),
858+ BM1880_PINCONF_DAT(0x03),
859+ BM1880_PINCONF_DAT(0x03),
860+ BM1880_PINCONF_DAT(0x03),
861+ BM1880_PINCONF_DAT(0x03),
862+ BM1880_PINCONF_DAT(0x02),
863+ BM1880_PINCONF_DAT(0x02),
864+ BM1880_PINCONF_DAT(0x02),
865+ BM1880_PINCONF_DAT(0x02),
866+ BM1880_PINCONF_DAT(0x02),
867+ BM1880_PINCONF_DAT(0x02),
868+ BM1880_PINCONF_DAT(0x02),
869+ BM1880_PINCONF_DAT(0x02),
870+ BM1880_PINCONF_DAT(0x02),
871+ BM1880_PINCONF_DAT(0x02),
872+ BM1880_PINCONF_DAT(0x02),
873+ BM1880_PINCONF_DAT(0x02),
874+ BM1880_PINCONF_DAT(0x02),
875+ BM1880_PINCONF_DAT(0x02),
876+ BM1880_PINCONF_DAT(0x02),
877+ BM1880_PINCONF_DAT(0x02),
878+ BM1880_PINCONF_DAT(0x02),
879+ BM1880_PINCONF_DAT(0x02),
880+ BM1880_PINCONF_DAT(0x02),
881+ BM1880_PINCONF_DAT(0x02),
882+ BM1880_PINCONF_DAT(0x02),
883+ BM1880_PINCONF_DAT(0x02),
884+ BM1880_PINCONF_DAT(0x02),
885+ BM1880_PINCONF_DAT(0x02),
886+ BM1880_PINCONF_DAT(0x02),
887+ BM1880_PINCONF_DAT(0x02),
888+ BM1880_PINCONF_DAT(0x02),
889+ BM1880_PINCONF_DAT(0x02),
890+ BM1880_PINCONF_DAT(0x02),
891+ BM1880_PINCONF_DAT(0x02),
892+ BM1880_PINCONF_DAT(0x02),
893+ BM1880_PINCONF_DAT(0x02),
894+ BM1880_PINCONF_DAT(0x02),
895+ BM1880_PINCONF_DAT(0x02),
896+ BM1880_PINCONF_DAT(0x02),
897+ BM1880_PINCONF_DAT(0x02),
898+ BM1880_PINCONF_DAT(0x02),
899+ BM1880_PINCONF_DAT(0x02),
900+ BM1880_PINCONF_DAT(0x02),
901+ BM1880_PINCONF_DAT(0x02),
902+ BM1880_PINCONF_DAT(0x02),
903+ BM1880_PINCONF_DAT(0x02),
904+ BM1880_PINCONF_DAT(0x02),
905+ BM1880_PINCONF_DAT(0x02),
906+ BM1880_PINCONF_DAT(0x02),
907+ BM1880_PINCONF_DAT(0x02),
908+ BM1880_PINCONF_DAT(0x02),
909+ BM1880_PINCONF_DAT(0x02),
910+ BM1880_PINCONF_DAT(0x02),
911+ BM1880_PINCONF_DAT(0x02),
912+ BM1880_PINCONF_DAT(0x02),
913+ BM1880_PINCONF_DAT(0x02),
798914 };
799915
800916 static int bm1880_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
@@ -870,33 +986,308 @@ static int bm1880_pinmux_set_mux(struct pinctrl_dev *pctldev, · 69 unmodified lines
870986 const struct bm1880_pinmux_function *func = &pctrl->funcs[function];
871987 int i;
872988
873− if (func->mux) {
989+ for (i = 0; i < pgrp->npins; i++) {
990+ unsigned int pin = pgrp->pins[i];
991+ u32 offset = (pin >> 1) << 2;
992+ u32 mux_offset = ((!((pin + 1) & 1) << 4) + 4);
874993 u32 regval = readl_relaxed(pctrl->base + BM1880_REG_MUX +
875− func->mux);
994+ offset);
995+
996+ regval &= ~(0x03 << mux_offset);
997+ regval |= func->mux_val << mux_offset;
998+
999+ writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset);
1000+ }
1001+
1002+ return 0;
1003+}
1004+
1005+#define BM1880_PINCONF(pin, idx) ((!((pin + 1) & 1) << 4) + idx)
1006+#define BM1880_PINCONF_PULLCTRL(pin) BM1880_PINCONF(pin, 0)
1007+#define BM1880_PINCONF_PULLUP(pin) BM1880_PINCONF(pin, 1)
1008+#define BM1880_PINCONF_PULLDOWN(pin) BM1880_PINCONF(pin, 2)
1009+#define BM1880_PINCONF_DRV(pin) BM1880_PINCONF(pin, 6)
1010+#define BM1880_PINCONF_SCHMITT(pin) BM1880_PINCONF(pin, 9)
1011+#define BM1880_PINCONF_SLEW(pin) BM1880_PINCONF(pin, 10)
1012+
1013+static int bm1880_pinconf_drv_set(unsigned int mA, u32 width,
1014+ u32 *regval, u32 bit_offset)
1015+{
1016+ u32 _regval;
1017+
1018+ _regval = *regval;
1019+
1020+ /*
1021+ * There are two sets of drive strength bit width exposed by the
1022+ * SoC at 4mA step, hence we need to handle them separately.
1023+ */
1024+ if (width == 0x03) {
1025+ switch (mA) {
1026+ case 4:
1027+ _regval &= ~(width << bit_offset);
1028+ _regval |= (0 << bit_offset);
1029+ break;
1030+ case 8:
1031+ _regval &= ~(width << bit_offset);
1032+ _regval |= (1 << bit_offset);
1033+ break;
1034+ case 12:
1035+ _regval &= ~(width << bit_offset);
1036+ _regval |= (2 << bit_offset);
1037+ break;
1038+ case 16:
1039+ _regval &= ~(width << bit_offset);
1040+ _regval |= (3 << bit_offset);
1041+ break;
1042+ case 20:
1043+ _regval &= ~(width << bit_offset);
1044+ _regval |= (4 << bit_offset);
1045+ break;
1046+ case 24:
1047+ _regval &= ~(width << bit_offset);
1048+ _regval |= (5 << bit_offset);
1049+ break;
1050+ case 28:
1051+ _regval &= ~(width << bit_offset);
1052+ _regval |= (6 << bit_offset);
1053+ break;
1054+ case 32:
1055+ _regval &= ~(width << bit_offset);
1056+ _regval |= (7 << bit_offset);
1057+ break;
1058+ default:
1059+ return -EINVAL;
1060+ }
1061+ } else {
1062+ switch (mA) {
1063+ case 4:
1064+ _regval &= ~(width << bit_offset);
1065+ _regval |= (0 << bit_offset);
1066+ break;
1067+ case 8:
1068+ _regval &= ~(width << bit_offset);
1069+ _regval |= (1 << bit_offset);
1070+ break;
1071+ case 12:
1072+ _regval &= ~(width << bit_offset);
1073+ _regval |= (2 << bit_offset);
1074+ break;
1075+ case 16:
1076+ _regval &= ~(width << bit_offset);
1077+ _regval |= (3 << bit_offset);
1078+ break;
1079+ default:
1080+ return -EINVAL;
1081+ }
1082+ }
1083+
1084+ *regval = _regval;
1085+
1086+ return 0;
1087+}
1088+
1089+static int bm1880_pinconf_drv_get(u32 width, u32 drv)
1090+{
1091+ int ret = -ENOTSUPP;
8761092
877− regval &= ~(func->mux_mask << func->mux_shift);
878− regval |= func->mux_val << func->mux_shift;
879− writel_relaxed(regval, pctrl->base + BM1880_REG_MUX +
880− func->mux);
1093+ /*
1094+ * There are two sets of drive strength bit width exposed by the
1095+ * SoC at 4mA step, hence we need to handle them separately.
1096+ */
1097+ if (width == 0x03) {
1098+ switch (drv) {
1099+ case 0:
1100+ ret = 4;
1101+ break;
1102+ case 1:
1103+ ret = 8;
1104+ break;
1105+ case 2:
1106+ ret = 12;
1107+ break;
1108+ case 3:
1109+ ret = 16;
1110+ break;
1111+ case 4:
1112+ ret = 20;
1113+ break;
1114+ case 5:
1115+ ret = 24;
1116+ break;
1117+ case 6:
1118+ ret = 28;
1119+ break;
1120+ case 7:
1121+ ret = 32;
1122+ break;
1123+ default:
1124+ break;
1125+ }
8811126 } else {
882− for (i = 0; i < pgrp->npins; i++) {
883− unsigned int pin = pgrp->pins[i];
884− u32 offset = (pin >> 1) << 2;
885− u32 mux_offset = ((!((pin + 1) & 1) << 4) + 4);
886− u32 regval = readl_relaxed(pctrl->base +
887− BM1880_REG_MUX + offset);
888−
889− regval &= ~(func->mux_mask << mux_offset);
890− regval |= func->mux_val << mux_offset;
891−
892− writel_relaxed(regval, pctrl->base +
893− BM1880_REG_MUX + offset);
1127+ switch (drv) {
1128+ case 0:
1129+ ret = 4;
1130+ break;
1131+ case 1:
1132+ ret = 8;
1133+ break;
1134+ case 2:
1135+ ret = 12;
1136+ break;
1137+ case 3:
1138+ ret = 16;
1139+ break;
1140+ default:
1141+ break;
1142+ }
1143+ }
1144+
1145+ return ret;
1146+}
1147+
1148+static int bm1880_pinconf_cfg_get(struct pinctrl_dev *pctldev,
1149+ unsigned int pin,
1150+ unsigned long *config)
1151+{
1152+ struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1153+ unsigned int param = pinconf_to_config_param(*config);
1154+ unsigned int arg = 0;
1155+ u32 regval, offset, bit_offset;
1156+ int ret;
1157+
1158+ offset = (pin >> 1) << 2;
1159+ regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset);
1160+
1161+ switch (param) {
1162+ case PIN_CONFIG_BIAS_PULL_UP:
1163+ bit_offset = BM1880_PINCONF_PULLUP(pin);
1164+ arg = !!(regval & BIT(bit_offset));
1165+ break;
1166+ case PIN_CONFIG_BIAS_PULL_DOWN:
1167+ bit_offset = BM1880_PINCONF_PULLDOWN(pin);
1168+ arg = !!(regval & BIT(bit_offset));
1169+ break;
1170+ case PIN_CONFIG_BIAS_DISABLE:
1171+ bit_offset = BM1880_PINCONF_PULLCTRL(pin);
1172+ arg = !!(regval & BIT(bit_offset));
1173+ break;
1174+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1175+ bit_offset = BM1880_PINCONF_SCHMITT(pin);
1176+ arg = !!(regval & BIT(bit_offset));
1177+ break;
1178+ case PIN_CONFIG_SLEW_RATE:
1179+ bit_offset = BM1880_PINCONF_SLEW(pin);
1180+ arg = !!(regval & BIT(bit_offset));
1181+ break;
1182+ case PIN_CONFIG_DRIVE_STRENGTH:
1183+ bit_offset = BM1880_PINCONF_DRV(pin);
1184+ ret = bm1880_pinconf_drv_get(pctrl->pinconf[pin].drv_bits,
1185+ !!(regval & BIT(bit_offset)));
1186+ if (ret < 0)
1187+ return ret;
1188+
1189+ arg = ret;
1190+ break;
1191+ default:
1192+ return -ENOTSUPP;
1193+ }
1194+
1195+ *config = pinconf_to_config_packed(param, arg);
1196+
1197+ return 0;
1198+}
1199+
1200+static int bm1880_pinconf_cfg_set(struct pinctrl_dev *pctldev,
1201+ unsigned int pin,
1202+ unsigned long *configs,
1203+ unsigned int num_configs)
1204+{
1205+ struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1206+ u32 regval, offset, bit_offset;
1207+ int i, ret;
1208+
1209+ offset = (pin >> 1) << 2;
1210+ regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset);
1211+
1212+ for (i = 0; i < num_configs; i++) {
1213+ unsigned int param = pinconf_to_config_param(configs[i]);
1214+ unsigned int arg = pinconf_to_config_argument(configs[i]);
1215+
1216+ switch (param) {
1217+ case PIN_CONFIG_BIAS_PULL_UP:
1218+ bit_offset = BM1880_PINCONF_PULLUP(pin);
1219+ regval |= BIT(bit_offset);
1220+ break;
1221+ case PIN_CONFIG_BIAS_PULL_DOWN:
1222+ bit_offset = BM1880_PINCONF_PULLDOWN(pin);
1223+ regval |= BIT(bit_offset);
1224+ break;
1225+ case PIN_CONFIG_BIAS_DISABLE:
1226+ bit_offset = BM1880_PINCONF_PULLCTRL(pin);
1227+ regval |= BIT(bit_offset);
1228+ break;
1229+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1230+ bit_offset = BM1880_PINCONF_SCHMITT(pin);
1231+ if (arg)
1232+ regval |= BIT(bit_offset);
1233+ else
1234+ regval &= ~BIT(bit_offset);
1235+ break;
1236+ case PIN_CONFIG_SLEW_RATE:
1237+ bit_offset = BM1880_PINCONF_SLEW(pin);
1238+ if (arg)
1239+ regval |= BIT(bit_offset);
1240+ else
1241+ regval &= ~BIT(bit_offset);
1242+ break;
1243+ case PIN_CONFIG_DRIVE_STRENGTH:
1244+ bit_offset = BM1880_PINCONF_DRV(pin);
1245+ ret = bm1880_pinconf_drv_set(arg,
1246+ pctrl->pinconf[pin].drv_bits,
1247+ &regval, bit_offset);
1248+ if (ret < 0)
1249+ return ret;
1250+
1251+ break;
1252+ default:
1253+ dev_warn(pctldev->dev,
1254+ "unsupported configuration parameter '%u'\n",
1255+ param);
1256+ continue;
8941257 }
1258+
1259+ writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset);
8951260 }
8961261
8971262 return 0;
8981263 }
8991264
1265+static int bm1880_pinconf_group_set(struct pinctrl_dev *pctldev,
1266+ unsigned int selector,
1267+ unsigned long *configs,
1268+ unsigned int num_configs)
1269+{
1270+ int i, ret;
1271+ struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1272+ const struct bm1880_pctrl_group *pgrp = &pctrl->groups[selector];
1273+
1274+ for (i = 0; i < pgrp->npins; i++) {
1275+ ret = bm1880_pinconf_cfg_set(pctldev, pgrp->pins[i], configs,
1276+ num_configs);
1277+ if (ret)
1278+ return ret;
1279+ }
1280+
1281+ return 0;
1282+}
1283+
1284+static const struct pinconf_ops bm1880_pinconf_ops = {
1285+ .is_generic = true,
1286+ .pin_config_get = bm1880_pinconf_cfg_get,
1287+ .pin_config_set = bm1880_pinconf_cfg_set,
1288+ .pin_config_group_set = bm1880_pinconf_group_set,
1289+};
1290+
9001291 static const struct pinmux_ops bm1880_pinmux_ops = {
9011292 .get_functions_count = bm1880_pmux_get_functions_count,
9021293 .get_function_name = bm1880_pmux_get_function_name,
@@ -910,6 +1301,7 @@ static struct pinctrl_desc bm1880_desc = { · 7 unmodified lines
9101301 .npins = ARRAY_SIZE(bm1880_pins),
9111302 .pctlops = &bm1880_pctrl_ops,
9121303 .pmxops = &bm1880_pinmux_ops,
1304+ .confops = &bm1880_pinconf_ops,
9131305 .owner = THIS_MODULE,
9141306 };
9151307
@@ -932,6 +1324,7 @@ static int bm1880_pinctrl_probe(struct platform_device *pdev) · 16 unmodified lines
9321324 pctrl->ngroups = ARRAY_SIZE(bm1880_pctrl_groups);
9331325 pctrl->funcs = bm1880_pmux_functions;
9341326 pctrl->nfuncs = ARRAY_SIZE(bm1880_pmux_functions);
1327+ pctrl->pinconf = bm1880_pinconf;
9351328
9361329 pctrl->pctrldev = devm_pinctrl_register(&pdev->dev, &bm1880_desc,
9371330 pctrl);
drivers/pinctrl/pinctrl-rockchip.c+1−0
@@ -3204,6 +3204,7 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, · 3203 unmodified lines
32043204 base,
32053205 &rockchip_regmap_config);
32063206 }
3207+ of_node_put(node);
32073208 }
32083209
32093210 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
drivers/pinctrl/pinctrl-stmfx.c+1−0
@@ -622,6 +622,7 @@ static int stmfx_pinctrl_probe(struct platform_device *pdev) · 621 unmodified lines
622622 pctl->pctl_desc.pins = stmfx_pins;
623623 pctl->pctl_desc.npins = ARRAY_SIZE(stmfx_pins);
624624 pctl->pctl_desc.owner = THIS_MODULE;
625+ pctl->pctl_desc.link_consumers = true;
625626
626627 ret = devm_pinctrl_register_and_init(pctl->dev, &pctl->pctl_desc,
627628 pctl, &pctl->pctl_dev);
drivers/pinctrl/pinctrl-tb10x.c+5−7
@@ -471,22 +471,22 @@ struct tb10x_port { · 470 unmodified lines
471471 * @base: register set base address.
472472 * @pingroups: pointer to an array of the pin groups this driver manages.
473473 * @pinfuncgrpcnt: number of pingroups in @pingroups.
474− * @pinfuncs: pointer to an array of pin functions this driver manages.
475474 * @pinfuncnt: number of pin functions in @pinfuncs.
476475 * @mutex: mutex for exclusive access to a pin controller's state.
477476 * @ports: current state of each port.
478477 * @gpios: Indicates if a given pin is currently used as GPIO (1) or not (0).
478+ * @pinfuncs: flexible array of pin functions this driver manages.
479479 */
480480 struct tb10x_pinctrl {
481481 struct pinctrl_dev *pctl;
482482 void *base;
483483 const struct tb10x_pinfuncgrp *pingroups;
484484 unsigned int pinfuncgrpcnt;
485− struct tb10x_of_pinfunc *pinfuncs;
486485 unsigned int pinfuncnt;
487486 struct mutex mutex;
488487 struct tb10x_port ports[TB10X_PORTS];
489488 DECLARE_BITMAP(gpios, MAX_PIN + 1);
489+ struct tb10x_of_pinfunc pinfuncs[];
490490 };
491491
492492 static inline void tb10x_pinctrl_set_config(struct tb10x_pinctrl *state,
@@ -759,15 +759,13 @@ static int tb10x_pinctrl_probe(struct platform_device *pdev) · 266 unmodified lines
759759 return -EINVAL;
760760 }
761761
762− state = devm_kzalloc(dev, sizeof(struct tb10x_pinctrl) +
763− of_get_child_count(of_node)
764− * sizeof(struct tb10x_of_pinfunc),
765− GFP_KERNEL);
762+ state = devm_kzalloc(dev, struct_size(state, pinfuncs,
763+ of_get_child_count(of_node)),
764+ GFP_KERNEL);
766765 if (!state)
767766 return -ENOMEM;
768767
769768 platform_set_drvdata(pdev, state);
770− state->pinfuncs = (struct tb10x_of_pinfunc *)(state + 1);
771769 mutex_init(&state->mutex);
772770
773771 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
drivers/pinctrl/qcom/Kconfig+10−1
@@ -169,11 +169,20 @@ config PINCTRL_SDM660 · 168 unmodified lines
169169
170170 config PINCTRL_SDM845
171171 tristate "Qualcomm Technologies Inc SDM845 pin controller driver"
172− depends on GPIOLIB && OF
172+ depends on GPIOLIB && (OF || ACPI)
173173 select PINCTRL_MSM
174174 help
175175 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
176176 Qualcomm Technologies Inc TLMM block found on the Qualcomm
177177 Technologies Inc SDM845 platform.
178178
179+config PINCTRL_SM8150
180+ tristate "Qualcomm Technologies Inc SM8150 pin controller driver"
181+ depends on GPIOLIB && OF
182+ select PINCTRL_MSM
183+ help
184+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
185+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
186+ Technologies Inc SM8150 platform.
187+
179188 endif
drivers/pinctrl/qcom/Makefile+1−0
@@ -22,3 +22,4 @@ obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o · 21 unmodified lines
2222 obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
2323 obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
2424 obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
25+obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
drivers/pinctrl/qcom/pinctrl-msm.c+42−1
@@ -599,8 +599,23 @@ static int msm_gpio_init_valid_mask(struct gpio_chip *chip) · 598 unmodified lines
599599 int ret;
600600 unsigned int len, i;
601601 unsigned int max_gpios = pctrl->soc->ngpios;
602+ const int *reserved = pctrl->soc->reserved_gpios;
602603 u16 *tmp;
603604
605+ /* Driver provided reserved list overrides DT and ACPI */
606+ if (reserved) {
607+ bitmap_fill(chip->valid_mask, max_gpios);
608+ for (i = 0; reserved[i] >= 0; i++) {
609+ if (i >= max_gpios || reserved[i] >= max_gpios) {
610+ dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");
611+ return -EINVAL;
612+ }
613+ clear_bit(reserved[i], chip->valid_mask);
614+ }
615+
616+ return 0;
617+ }
618+
604619 /* The number of GPIOs in the ACPI tables */
605620 len = ret = device_property_read_u16_array(pctrl->dev, "gpios", NULL,
606621 0);
@@ -729,7 +744,7 @@ static void msm_gpio_irq_mask(struct irq_data *d) · 122 unmodified lines
729744 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
730745 }
731746
732−static void msm_gpio_irq_unmask(struct irq_data *d)
747+static void msm_gpio_irq_clear_unmask(struct irq_data *d, bool status_clear)
733748 {
734749 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
735750 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
@@ -741,6 +756,17 @@ static void msm_gpio_irq_unmask(struct irq_data *d) · 5 unmodified lines
741756
742757 raw_spin_lock_irqsave(&pctrl->lock, flags);
743758
759+ if (status_clear) {
760+ /*
761+ * clear the interrupt status bit before unmask to avoid
762+ * any erroneous interrupts that would have got latched
763+ * when the interrupt is not in use.
764+ */
765+ val = msm_readl_intr_status(pctrl, g);
766+ val &= ~BIT(g->intr_status_bit);
767+ msm_writel_intr_status(val, pctrl, g);
768+ }
769+
744770 val = msm_readl_intr_cfg(pctrl, g);
745771 val |= BIT(g->intr_raw_status_bit);
746772 val |= BIT(g->intr_enable_bit);
@@ -751,6 +777,17 @@ static void msm_gpio_irq_unmask(struct irq_data *d) · 4 unmodified lines
751777 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
752778 }
753779
780+static void msm_gpio_irq_enable(struct irq_data *d)
781+{
782+
783+ msm_gpio_irq_clear_unmask(d, true);
784+}
785+
786+static void msm_gpio_irq_unmask(struct irq_data *d)
787+{
788+ msm_gpio_irq_clear_unmask(d, false);
789+}
790+
754791 static void msm_gpio_irq_ack(struct irq_data *d)
755792 {
756793 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
@@ -956,6 +993,9 @@ static void msm_gpio_irq_handler(struct irq_desc *desc) · 199 unmodified lines
956993
957994 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
958995 {
996+ if (pctrl->soc->reserved_gpios)
997+ return true;
998+
959999 return device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0) > 0;
9601000 }
9611001
@@ -978,6 +1018,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) · 16 unmodified lines
9781018 chip->need_valid_mask = msm_gpio_needs_valid_mask(pctrl);
9791019
9801020 pctrl->irq_chip.name = "msmgpio";
1021+ pctrl->irq_chip.irq_enable = msm_gpio_irq_enable;
9811022 pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;
9821023 pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;
9831024 pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;
drivers/pinctrl/qcom/pinctrl-msm.h+1−0
@@ -113,6 +113,7 @@ struct msm_pinctrl_soc_data { · 112 unmodified lines
113113 bool pull_no_keeper;
114114 const char *const *tiles;
115115 unsigned int ntiles;
116+ const int *reserved_gpios;
116117 };
117118
118119 extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;
drivers/pinctrl/qcom/pinctrl-sdm845.c+40−6
@@ -3,6 +3,7 @@ · 2 unmodified lines
33 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
44 */
55
6+#include <linux/acpi.h>
67 #include <linux/module.h>
78 #include <linux/of.h>
89 #include <linux/platform_device.h>
@@ -420,10 +421,10 @@ DECLARE_MSM_GPIO_PINS(147); · 411 unmodified lines
420421 DECLARE_MSM_GPIO_PINS(148);
421422 DECLARE_MSM_GPIO_PINS(149);
422423
423−static const unsigned int sdc2_clk_pins[] = { 150 };
424−static const unsigned int sdc2_cmd_pins[] = { 151 };
425−static const unsigned int sdc2_data_pins[] = { 152 };
426−static const unsigned int ufs_reset_pins[] = { 153 };
424+static const unsigned int ufs_reset_pins[] = { 150 };
425+static const unsigned int sdc2_clk_pins[] = { 151 };
426+static const unsigned int sdc2_cmd_pins[] = { 152 };
427+static const unsigned int sdc2_data_pins[] = { 153 };
427428
428429 enum sdm845_functions {
429430 msm_mux_gpio,
@@ -1271,10 +1272,14 @@ static const struct msm_pingroup sdm845_groups[] = { · 841 unmodified lines
12711272 PINGROUP(147, NORTH, _, _, _, _, _, _, _, _, _, _),
12721273 PINGROUP(148, NORTH, _, _, _, _, _, _, _, _, _, _),
12731274 PINGROUP(149, NORTH, _, _, _, _, _, _, _, _, _, _),
1275+ UFS_RESET(ufs_reset, 0x99f000),
12741276 SDC_QDSD_PINGROUP(sdc2_clk, 0x99a000, 14, 6),
12751277 SDC_QDSD_PINGROUP(sdc2_cmd, 0x99a000, 11, 3),
12761278 SDC_QDSD_PINGROUP(sdc2_data, 0x99a000, 9, 0),
1277− UFS_RESET(ufs_reset, 0x99f000),
1279+};
1280+
1281+static const int sdm845_acpi_reserved_gpios[] = {
1282+ 0, 1, 2, 3, 81, 82, 83, 84, -1
12781283 };
12791284
12801285 static const struct msm_pinctrl_soc_data sdm845_pinctrl = {
@@ -1284,14 +1289,42 @@ static const struct msm_pinctrl_soc_data sdm845_pinctrl = { · 3 unmodified lines
12841289 .nfunctions = ARRAY_SIZE(sdm845_functions),
12851290 .groups = sdm845_groups,
12861291 .ngroups = ARRAY_SIZE(sdm845_groups),
1292+ .ngpios = 151,
1293+};
1294+
1295+static const struct msm_pinctrl_soc_data sdm845_acpi_pinctrl = {
1296+ .pins = sdm845_pins,
1297+ .npins = ARRAY_SIZE(sdm845_pins),
1298+ .groups = sdm845_groups,
1299+ .ngroups = ARRAY_SIZE(sdm845_groups),
1300+ .reserved_gpios = sdm845_acpi_reserved_gpios,
12871301 .ngpios = 150,
12881302 };
12891303
12901304 static int sdm845_pinctrl_probe(struct platform_device *pdev)
12911305 {
1292− return msm_pinctrl_probe(pdev, &sdm845_pinctrl);
1306+ int ret;
1307+
1308+ if (pdev->dev.of_node) {
1309+ ret = msm_pinctrl_probe(pdev, &sdm845_pinctrl);
1310+ } else if (has_acpi_companion(&pdev->dev)) {
1311+ ret = msm_pinctrl_probe(pdev, &sdm845_acpi_pinctrl);
1312+ } else {
1313+ dev_err(&pdev->dev, "DT and ACPI disabled\n");
1314+ return -EINVAL;
1315+ }
1316+
1317+ return ret;
12931318 }
12941319
1320+#ifdef CONFIG_ACPI
1321+static const struct acpi_device_id sdm845_pinctrl_acpi_match[] = {
1322+ { "QCOM0217"},
1323+ { },
1324+};
1325+MODULE_DEVICE_TABLE(acpi, sdm845_pinctrl_acpi_match);
1326+#endif
1327+
12951328 static const struct of_device_id sdm845_pinctrl_of_match[] = {
12961329 { .compatible = "qcom,sdm845-pinctrl", },
12971330 { },
@@ -1302,6 +1335,7 @@ static struct platform_driver sdm845_pinctrl_driver = { · 4 unmodified lines
13021335 .name = "sdm845-pinctrl",
13031336 .pm = &msm_pinctrl_dev_pm_ops,
13041337 .of_match_table = sdm845_pinctrl_of_match,
1338+ .acpi_match_table = ACPI_PTR(sdm845_pinctrl_acpi_match),
13051339 },
13061340 .probe = sdm845_pinctrl_probe,
13071341 .remove = msm_pinctrl_remove,
drivers/pinctrl/qcom/pinctrl-sm8150.c+1548−0
@@ -0,0 +1,1548 @@
1+// SPDX-License-Identifier: GPL-2.0
2+// Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
3+
4+#include <linux/module.h>
5+#include <linux/of.h>
6+#include <linux/platform_device.h>
7+#include <linux/pinctrl/pinctrl.h>
8+
9+#include "pinctrl-msm.h"
10+
11+static const char * const sm8150_tiles[] = {
12+ "north",
13+ "south",
14+ "east",
15+ "west"
16+};
17+
18+enum {
19+ NORTH,
20+ SOUTH,
21+ EAST,
22+ WEST
23+};
24+
25+#define FUNCTION(fname) \
26+ [msm_mux_##fname] = { \
27+ .name = #fname, \
28+ .groups = fname##_groups, \
29+ .ngroups = ARRAY_SIZE(fname##_groups), \
30+ }
31+
32+#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
33+ { \
34+ .name = "gpio" #id, \
35+ .pins = gpio##id##_pins, \
36+ .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
37+ .funcs = (int[]){ \
38+ msm_mux_gpio, /* gpio mode */ \
39+ msm_mux_##f1, \
40+ msm_mux_##f2, \
41+ msm_mux_##f3, \
42+ msm_mux_##f4, \
43+ msm_mux_##f5, \
44+ msm_mux_##f6, \
45+ msm_mux_##f7, \
46+ msm_mux_##f8, \
47+ msm_mux_##f9 \
48+ }, \
49+ .nfuncs = 10, \
50+ .ctl_reg = 0x1000 * id, \
51+ .io_reg = 0x1000 * id + 0x4, \
52+ .intr_cfg_reg = 0x1000 * id + 0x8, \
53+ .intr_status_reg = 0x1000 * id + 0xc, \
54+ .intr_target_reg = 0x1000 * id + 0x8, \
55+ .tile = _tile, \
56+ .mux_bit = 2, \
57+ .pull_bit = 0, \
58+ .drv_bit = 6, \
59+ .oe_bit = 9, \
60+ .in_bit = 0, \
61+ .out_bit = 1, \
62+ .intr_enable_bit = 0, \
63+ .intr_status_bit = 0, \
64+ .intr_target_bit = 5, \
65+ .intr_target_kpss_val = 3, \
66+ .intr_raw_status_bit = 4, \
67+ .intr_polarity_bit = 1, \
68+ .intr_detection_bit = 2, \
69+ .intr_detection_width = 2, \
70+ }
71+
72+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
73+ { \
74+ .name = #pg_name, \
75+ .pins = pg_name##_pins, \
76+ .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
77+ .ctl_reg = ctl, \
78+ .io_reg = 0, \
79+ .intr_cfg_reg = 0, \
80+ .intr_status_reg = 0, \
81+ .intr_target_reg = 0, \
82+ .tile = NORTH, \
83+ .mux_bit = -1, \
84+ .pull_bit = pull, \
85+ .drv_bit = drv, \
86+ .oe_bit = -1, \
87+ .in_bit = -1, \
88+ .out_bit = -1, \
89+ .intr_enable_bit = -1, \
90+ .intr_status_bit = -1, \
91+ .intr_target_bit = -1, \
92+ .intr_raw_status_bit = -1, \
93+ .intr_polarity_bit = -1, \
94+ .intr_detection_bit = -1, \
95+ .intr_detection_width = -1, \
96+ }
97+
98+#define UFS_RESET(pg_name, offset) \
99+ { \
100+ .name = #pg_name, \
101+ .pins = pg_name##_pins, \
102+ .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
103+ .ctl_reg = offset, \
104+ .io_reg = offset + 0x4, \
105+ .intr_cfg_reg = 0, \
106+ .intr_status_reg = 0, \
107+ .intr_target_reg = 0, \
108+ .tile = SOUTH, \
109+ .mux_bit = -1, \
110+ .pull_bit = 3, \
111+ .drv_bit = 0, \
112+ .oe_bit = -1, \
113+ .in_bit = -1, \
114+ .out_bit = 0, \
115+ .intr_enable_bit = -1, \
116+ .intr_status_bit = -1, \
117+ .intr_target_bit = -1, \
118+ .intr_raw_status_bit = -1, \
119+ .intr_polarity_bit = -1, \
120+ .intr_detection_bit = -1, \
121+ .intr_detection_width = -1, \
122+ }
123+
124+static const struct pinctrl_pin_desc sm8150_pins[] = {
125+ PINCTRL_PIN(0, "GPIO_0"),
126+ PINCTRL_PIN(1, "GPIO_1"),
127+ PINCTRL_PIN(2, "GPIO_2"),
128+ PINCTRL_PIN(3, "GPIO_3"),
129+ PINCTRL_PIN(4, "GPIO_4"),
130+ PINCTRL_PIN(5, "GPIO_5"),
131+ PINCTRL_PIN(6, "GPIO_6"),
132+ PINCTRL_PIN(7, "GPIO_7"),
133+ PINCTRL_PIN(8, "GPIO_8"),
134+ PINCTRL_PIN(9, "GPIO_9"),
135+ PINCTRL_PIN(10, "GPIO_10"),
136+ PINCTRL_PIN(11, "GPIO_11"),
137+ PINCTRL_PIN(12, "GPIO_12"),
138+ PINCTRL_PIN(13, "GPIO_13"),
139+ PINCTRL_PIN(14, "GPIO_14"),
140+ PINCTRL_PIN(15, "GPIO_15"),
141+ PINCTRL_PIN(16, "GPIO_16"),
142+ PINCTRL_PIN(17, "GPIO_17"),
143+ PINCTRL_PIN(18, "GPIO_18"),
144+ PINCTRL_PIN(19, "GPIO_19"),
145+ PINCTRL_PIN(20, "GPIO_20"),
146+ PINCTRL_PIN(21, "GPIO_21"),
147+ PINCTRL_PIN(22, "GPIO_22"),
148+ PINCTRL_PIN(23, "GPIO_23"),
149+ PINCTRL_PIN(24, "GPIO_24"),
150+ PINCTRL_PIN(25, "GPIO_25"),
151+ PINCTRL_PIN(26, "GPIO_26"),
152+ PINCTRL_PIN(27, "GPIO_27"),
153+ PINCTRL_PIN(28, "GPIO_28"),
154+ PINCTRL_PIN(29, "GPIO_29"),
155+ PINCTRL_PIN(30, "GPIO_30"),
156+ PINCTRL_PIN(31, "GPIO_31"),
157+ PINCTRL_PIN(32, "GPIO_32"),
158+ PINCTRL_PIN(33, "GPIO_33"),
159+ PINCTRL_PIN(34, "GPIO_34"),
160+ PINCTRL_PIN(35, "GPIO_35"),
161+ PINCTRL_PIN(36, "GPIO_36"),
162+ PINCTRL_PIN(37, "GPIO_37"),
163+ PINCTRL_PIN(38, "GPIO_38"),
164+ PINCTRL_PIN(39, "GPIO_39"),
165+ PINCTRL_PIN(40, "GPIO_40"),
166+ PINCTRL_PIN(41, "GPIO_41"),
167+ PINCTRL_PIN(42, "GPIO_42"),
168+ PINCTRL_PIN(43, "GPIO_43"),
169+ PINCTRL_PIN(44, "GPIO_44"),
170+ PINCTRL_PIN(45, "GPIO_45"),
171+ PINCTRL_PIN(46, "GPIO_46"),
172+ PINCTRL_PIN(47, "GPIO_47"),
173+ PINCTRL_PIN(48, "GPIO_48"),
174+ PINCTRL_PIN(49, "GPIO_49"),
175+ PINCTRL_PIN(50, "GPIO_50"),
176+ PINCTRL_PIN(51, "GPIO_51"),
177+ PINCTRL_PIN(52, "GPIO_52"),
178+ PINCTRL_PIN(53, "GPIO_53"),
179+ PINCTRL_PIN(54, "GPIO_54"),
180+ PINCTRL_PIN(55, "GPIO_55"),
181+ PINCTRL_PIN(56, "GPIO_56"),
182+ PINCTRL_PIN(57, "GPIO_57"),
183+ PINCTRL_PIN(58, "GPIO_58"),
184+ PINCTRL_PIN(59, "GPIO_59"),
185+ PINCTRL_PIN(60, "GPIO_60"),
186+ PINCTRL_PIN(61, "GPIO_61"),
187+ PINCTRL_PIN(62, "GPIO_62"),
188+ PINCTRL_PIN(63, "GPIO_63"),
189+ PINCTRL_PIN(64, "GPIO_64"),
190+ PINCTRL_PIN(65, "GPIO_65"),
191+ PINCTRL_PIN(66, "GPIO_66"),
192+ PINCTRL_PIN(67, "GPIO_67"),
193+ PINCTRL_PIN(68, "GPIO_68"),
194+ PINCTRL_PIN(69, "GPIO_69"),
195+ PINCTRL_PIN(70, "GPIO_70"),
196+ PINCTRL_PIN(71, "GPIO_71"),
197+ PINCTRL_PIN(72, "GPIO_72"),
198+ PINCTRL_PIN(73, "GPIO_73"),
199+ PINCTRL_PIN(74, "GPIO_74"),
200+ PINCTRL_PIN(75, "GPIO_75"),
201+ PINCTRL_PIN(76, "GPIO_76"),
202+ PINCTRL_PIN(77, "GPIO_77"),
203+ PINCTRL_PIN(78, "GPIO_78"),
204+ PINCTRL_PIN(79, "GPIO_79"),
205+ PINCTRL_PIN(80, "GPIO_80"),
206+ PINCTRL_PIN(81, "GPIO_81"),
207+ PINCTRL_PIN(82, "GPIO_82"),
208+ PINCTRL_PIN(83, "GPIO_83"),
209+ PINCTRL_PIN(84, "GPIO_84"),
210+ PINCTRL_PIN(85, "GPIO_85"),
211+ PINCTRL_PIN(86, "GPIO_86"),
212+ PINCTRL_PIN(87, "GPIO_87"),
213+ PINCTRL_PIN(88, "GPIO_88"),
214+ PINCTRL_PIN(89, "GPIO_89"),
215+ PINCTRL_PIN(90, "GPIO_90"),
216+ PINCTRL_PIN(91, "GPIO_91"),
217+ PINCTRL_PIN(92, "GPIO_92"),
218+ PINCTRL_PIN(93, "GPIO_93"),
219+ PINCTRL_PIN(94, "GPIO_94"),
220+ PINCTRL_PIN(95, "GPIO_95"),
221+ PINCTRL_PIN(96, "GPIO_96"),
222+ PINCTRL_PIN(97, "GPIO_97"),
223+ PINCTRL_PIN(98, "GPIO_98"),
224+ PINCTRL_PIN(99, "GPIO_99"),
225+ PINCTRL_PIN(100, "GPIO_100"),
226+ PINCTRL_PIN(101, "GPIO_101"),
227+ PINCTRL_PIN(102, "GPIO_102"),
228+ PINCTRL_PIN(103, "GPIO_103"),
229+ PINCTRL_PIN(104, "GPIO_104"),
230+ PINCTRL_PIN(105, "GPIO_105"),
231+ PINCTRL_PIN(106, "GPIO_106"),
232+ PINCTRL_PIN(107, "GPIO_107"),
233+ PINCTRL_PIN(108, "GPIO_108"),
234+ PINCTRL_PIN(109, "GPIO_109"),
235+ PINCTRL_PIN(110, "GPIO_110"),
236+ PINCTRL_PIN(111, "GPIO_111"),
237+ PINCTRL_PIN(112, "GPIO_112"),
238+ PINCTRL_PIN(113, "GPIO_113"),
239+ PINCTRL_PIN(114, "GPIO_114"),
240+ PINCTRL_PIN(115, "GPIO_115"),
241+ PINCTRL_PIN(116, "GPIO_116"),
242+ PINCTRL_PIN(117, "GPIO_117"),
243+ PINCTRL_PIN(118, "GPIO_118"),
244+ PINCTRL_PIN(119, "GPIO_119"),
245+ PINCTRL_PIN(120, "GPIO_120"),
246+ PINCTRL_PIN(121, "GPIO_121"),
247+ PINCTRL_PIN(122, "GPIO_122"),
248+ PINCTRL_PIN(123, "GPIO_123"),
249+ PINCTRL_PIN(124, "GPIO_124"),
250+ PINCTRL_PIN(125, "GPIO_125"),
251+ PINCTRL_PIN(126, "GPIO_126"),
252+ PINCTRL_PIN(127, "GPIO_127"),
253+ PINCTRL_PIN(128, "GPIO_128"),
254+ PINCTRL_PIN(129, "GPIO_129"),
255+ PINCTRL_PIN(130, "GPIO_130"),
256+ PINCTRL_PIN(131, "GPIO_131"),
257+ PINCTRL_PIN(132, "GPIO_132"),
258+ PINCTRL_PIN(133, "GPIO_133"),
259+ PINCTRL_PIN(134, "GPIO_134"),
260+ PINCTRL_PIN(135, "GPIO_135"),
261+ PINCTRL_PIN(136, "GPIO_136"),
262+ PINCTRL_PIN(137, "GPIO_137"),
263+ PINCTRL_PIN(138, "GPIO_138"),
264+ PINCTRL_PIN(139, "GPIO_139"),
265+ PINCTRL_PIN(140, "GPIO_140"),
266+ PINCTRL_PIN(141, "GPIO_141"),
267+ PINCTRL_PIN(142, "GPIO_142"),
268+ PINCTRL_PIN(143, "GPIO_143"),
269+ PINCTRL_PIN(144, "GPIO_144"),
270+ PINCTRL_PIN(145, "GPIO_145"),
271+ PINCTRL_PIN(146, "GPIO_146"),
272+ PINCTRL_PIN(147, "GPIO_147"),
273+ PINCTRL_PIN(148, "GPIO_148"),
274+ PINCTRL_PIN(149, "GPIO_149"),
275+ PINCTRL_PIN(150, "GPIO_150"),
276+ PINCTRL_PIN(151, "GPIO_151"),
277+ PINCTRL_PIN(152, "GPIO_152"),
278+ PINCTRL_PIN(153, "GPIO_153"),
279+ PINCTRL_PIN(154, "GPIO_154"),
280+ PINCTRL_PIN(155, "GPIO_155"),
281+ PINCTRL_PIN(156, "GPIO_156"),
282+ PINCTRL_PIN(157, "GPIO_157"),
283+ PINCTRL_PIN(158, "GPIO_158"),
284+ PINCTRL_PIN(159, "GPIO_159"),
285+ PINCTRL_PIN(160, "GPIO_160"),
286+ PINCTRL_PIN(161, "GPIO_161"),
287+ PINCTRL_PIN(162, "GPIO_162"),
288+ PINCTRL_PIN(163, "GPIO_163"),
289+ PINCTRL_PIN(164, "GPIO_164"),
290+ PINCTRL_PIN(165, "GPIO_165"),
291+ PINCTRL_PIN(166, "GPIO_166"),
292+ PINCTRL_PIN(167, "GPIO_167"),
293+ PINCTRL_PIN(168, "GPIO_168"),
294+ PINCTRL_PIN(169, "GPIO_169"),
295+ PINCTRL_PIN(170, "GPIO_170"),
296+ PINCTRL_PIN(171, "GPIO_171"),
297+ PINCTRL_PIN(172, "GPIO_172"),
298+ PINCTRL_PIN(173, "GPIO_173"),
299+ PINCTRL_PIN(174, "GPIO_174"),
300+ PINCTRL_PIN(175, "UFS_RESET"),
301+ PINCTRL_PIN(176, "SDC2_CLK"),
302+ PINCTRL_PIN(177, "SDC2_CMD"),
303+ PINCTRL_PIN(178, "SDC2_DATA"),
304+};
305+
306+#define DECLARE_MSM_GPIO_PINS(pin) \
307+ static const unsigned int gpio##pin##_pins[] = { pin }
308+DECLARE_MSM_GPIO_PINS(0);
309+DECLARE_MSM_GPIO_PINS(1);
310+DECLARE_MSM_GPIO_PINS(2);
311+DECLARE_MSM_GPIO_PINS(3);
312+DECLARE_MSM_GPIO_PINS(4);
313+DECLARE_MSM_GPIO_PINS(5);
314+DECLARE_MSM_GPIO_PINS(6);
315+DECLARE_MSM_GPIO_PINS(7);
316+DECLARE_MSM_GPIO_PINS(8);
317+DECLARE_MSM_GPIO_PINS(9);
318+DECLARE_MSM_GPIO_PINS(10);
319+DECLARE_MSM_GPIO_PINS(11);
320+DECLARE_MSM_GPIO_PINS(12);
321+DECLARE_MSM_GPIO_PINS(13);
322+DECLARE_MSM_GPIO_PINS(14);
323+DECLARE_MSM_GPIO_PINS(15);
324+DECLARE_MSM_GPIO_PINS(16);
325+DECLARE_MSM_GPIO_PINS(17);
326+DECLARE_MSM_GPIO_PINS(18);
327+DECLARE_MSM_GPIO_PINS(19);
328+DECLARE_MSM_GPIO_PINS(20);
329+DECLARE_MSM_GPIO_PINS(21);
330+DECLARE_MSM_GPIO_PINS(22);
331+DECLARE_MSM_GPIO_PINS(23);
332+DECLARE_MSM_GPIO_PINS(24);
333+DECLARE_MSM_GPIO_PINS(25);
334+DECLARE_MSM_GPIO_PINS(26);
335+DECLARE_MSM_GPIO_PINS(27);
336+DECLARE_MSM_GPIO_PINS(28);
337+DECLARE_MSM_GPIO_PINS(29);
338+DECLARE_MSM_GPIO_PINS(30);
339+DECLARE_MSM_GPIO_PINS(31);
340+DECLARE_MSM_GPIO_PINS(32);
341+DECLARE_MSM_GPIO_PINS(33);
342+DECLARE_MSM_GPIO_PINS(34);
343+DECLARE_MSM_GPIO_PINS(35);
344+DECLARE_MSM_GPIO_PINS(36);
345+DECLARE_MSM_GPIO_PINS(37);
346+DECLARE_MSM_GPIO_PINS(38);
347+DECLARE_MSM_GPIO_PINS(39);
348+DECLARE_MSM_GPIO_PINS(40);
349+DECLARE_MSM_GPIO_PINS(41);
350+DECLARE_MSM_GPIO_PINS(42);
351+DECLARE_MSM_GPIO_PINS(43);
352+DECLARE_MSM_GPIO_PINS(44);
353+DECLARE_MSM_GPIO_PINS(45);
354+DECLARE_MSM_GPIO_PINS(46);
355+DECLARE_MSM_GPIO_PINS(47);
356+DECLARE_MSM_GPIO_PINS(48);
357+DECLARE_MSM_GPIO_PINS(49);
358+DECLARE_MSM_GPIO_PINS(50);
359+DECLARE_MSM_GPIO_PINS(51);
360+DECLARE_MSM_GPIO_PINS(52);
361+DECLARE_MSM_GPIO_PINS(53);
362+DECLARE_MSM_GPIO_PINS(54);
363+DECLARE_MSM_GPIO_PINS(55);
364+DECLARE_MSM_GPIO_PINS(56);
365+DECLARE_MSM_GPIO_PINS(57);
366+DECLARE_MSM_GPIO_PINS(58);
367+DECLARE_MSM_GPIO_PINS(59);
368+DECLARE_MSM_GPIO_PINS(60);
369+DECLARE_MSM_GPIO_PINS(61);
370+DECLARE_MSM_GPIO_PINS(62);
371+DECLARE_MSM_GPIO_PINS(63);
372+DECLARE_MSM_GPIO_PINS(64);
373+DECLARE_MSM_GPIO_PINS(65);
374+DECLARE_MSM_GPIO_PINS(66);
375+DECLARE_MSM_GPIO_PINS(67);
376+DECLARE_MSM_GPIO_PINS(68);
377+DECLARE_MSM_GPIO_PINS(69);
378+DECLARE_MSM_GPIO_PINS(70);
379+DECLARE_MSM_GPIO_PINS(71);
380+DECLARE_MSM_GPIO_PINS(72);
381+DECLARE_MSM_GPIO_PINS(73);
382+DECLARE_MSM_GPIO_PINS(74);
383+DECLARE_MSM_GPIO_PINS(75);
384+DECLARE_MSM_GPIO_PINS(76);
385+DECLARE_MSM_GPIO_PINS(77);
386+DECLARE_MSM_GPIO_PINS(78);
387+DECLARE_MSM_GPIO_PINS(79);
388+DECLARE_MSM_GPIO_PINS(80);
389+DECLARE_MSM_GPIO_PINS(81);
390+DECLARE_MSM_GPIO_PINS(82);
391+DECLARE_MSM_GPIO_PINS(83);
392+DECLARE_MSM_GPIO_PINS(84);
393+DECLARE_MSM_GPIO_PINS(85);
394+DECLARE_MSM_GPIO_PINS(86);
395+DECLARE_MSM_GPIO_PINS(87);
396+DECLARE_MSM_GPIO_PINS(88);
397+DECLARE_MSM_GPIO_PINS(89);
398+DECLARE_MSM_GPIO_PINS(90);
399+DECLARE_MSM_GPIO_PINS(91);
400+DECLARE_MSM_GPIO_PINS(92);
401+DECLARE_MSM_GPIO_PINS(93);
402+DECLARE_MSM_GPIO_PINS(94);
403+DECLARE_MSM_GPIO_PINS(95);
404+DECLARE_MSM_GPIO_PINS(96);
405+DECLARE_MSM_GPIO_PINS(97);
406+DECLARE_MSM_GPIO_PINS(98);
407+DECLARE_MSM_GPIO_PINS(99);
408+DECLARE_MSM_GPIO_PINS(100);
409+DECLARE_MSM_GPIO_PINS(101);
410+DECLARE_MSM_GPIO_PINS(102);
411+DECLARE_MSM_GPIO_PINS(103);
412+DECLARE_MSM_GPIO_PINS(104);
413+DECLARE_MSM_GPIO_PINS(105);
414+DECLARE_MSM_GPIO_PINS(106);
415+DECLARE_MSM_GPIO_PINS(107);
416+DECLARE_MSM_GPIO_PINS(108);
417+DECLARE_MSM_GPIO_PINS(109);
418+DECLARE_MSM_GPIO_PINS(110);
419+DECLARE_MSM_GPIO_PINS(111);
420+DECLARE_MSM_GPIO_PINS(112);
421+DECLARE_MSM_GPIO_PINS(113);
422+DECLARE_MSM_GPIO_PINS(114);
423+DECLARE_MSM_GPIO_PINS(115);
424+DECLARE_MSM_GPIO_PINS(116);
425+DECLARE_MSM_GPIO_PINS(117);
426+DECLARE_MSM_GPIO_PINS(118);
427+DECLARE_MSM_GPIO_PINS(119);
428+DECLARE_MSM_GPIO_PINS(120);
429+DECLARE_MSM_GPIO_PINS(121);
430+DECLARE_MSM_GPIO_PINS(122);
431+DECLARE_MSM_GPIO_PINS(123);
432+DECLARE_MSM_GPIO_PINS(124);
433+DECLARE_MSM_GPIO_PINS(125);
434+DECLARE_MSM_GPIO_PINS(126);
435+DECLARE_MSM_GPIO_PINS(127);
436+DECLARE_MSM_GPIO_PINS(128);
437+DECLARE_MSM_GPIO_PINS(129);
438+DECLARE_MSM_GPIO_PINS(130);
439+DECLARE_MSM_GPIO_PINS(131);
440+DECLARE_MSM_GPIO_PINS(132);
441+DECLARE_MSM_GPIO_PINS(133);
442+DECLARE_MSM_GPIO_PINS(134);
443+DECLARE_MSM_GPIO_PINS(135);
444+DECLARE_MSM_GPIO_PINS(136);
445+DECLARE_MSM_GPIO_PINS(137);
446+DECLARE_MSM_GPIO_PINS(138);
447+DECLARE_MSM_GPIO_PINS(139);
448+DECLARE_MSM_GPIO_PINS(140);
449+DECLARE_MSM_GPIO_PINS(141);
450+DECLARE_MSM_GPIO_PINS(142);
451+DECLARE_MSM_GPIO_PINS(143);
452+DECLARE_MSM_GPIO_PINS(144);
453+DECLARE_MSM_GPIO_PINS(145);
454+DECLARE_MSM_GPIO_PINS(146);
455+DECLARE_MSM_GPIO_PINS(147);
456+DECLARE_MSM_GPIO_PINS(148);
457+DECLARE_MSM_GPIO_PINS(149);
458+DECLARE_MSM_GPIO_PINS(150);
459+DECLARE_MSM_GPIO_PINS(151);
460+DECLARE_MSM_GPIO_PINS(152);
461+DECLARE_MSM_GPIO_PINS(153);
462+DECLARE_MSM_GPIO_PINS(154);
463+DECLARE_MSM_GPIO_PINS(155);
464+DECLARE_MSM_GPIO_PINS(156);
465+DECLARE_MSM_GPIO_PINS(157);
466+DECLARE_MSM_GPIO_PINS(158);
467+DECLARE_MSM_GPIO_PINS(159);
468+DECLARE_MSM_GPIO_PINS(160);
469+DECLARE_MSM_GPIO_PINS(161);
470+DECLARE_MSM_GPIO_PINS(162);
471+DECLARE_MSM_GPIO_PINS(163);
472+DECLARE_MSM_GPIO_PINS(164);
473+DECLARE_MSM_GPIO_PINS(165);
474+DECLARE_MSM_GPIO_PINS(166);
475+DECLARE_MSM_GPIO_PINS(167);
476+DECLARE_MSM_GPIO_PINS(168);
477+DECLARE_MSM_GPIO_PINS(169);
478+DECLARE_MSM_GPIO_PINS(170);
479+DECLARE_MSM_GPIO_PINS(171);
480+DECLARE_MSM_GPIO_PINS(172);
481+DECLARE_MSM_GPIO_PINS(173);
482+DECLARE_MSM_GPIO_PINS(174);
483+
484+static const unsigned int ufs_reset_pins[] = { 175 };
485+static const unsigned int sdc2_clk_pins[] = { 176 };
486+static const unsigned int sdc2_cmd_pins[] = { 177 };
487+static const unsigned int sdc2_data_pins[] = { 178 };
488+
489+enum sm8150_functions {
490+ msm_mux_adsp_ext,
491+ msm_mux_agera_pll,
492+ msm_mux_aoss_cti,
493+ msm_mux_atest_char,
494+ msm_mux_atest_char0,
495+ msm_mux_atest_char1,
496+ msm_mux_atest_char2,
497+ msm_mux_atest_char3,
498+ msm_mux_atest_usb1,
499+ msm_mux_atest_usb2,
500+ msm_mux_atest_usb10,
501+ msm_mux_atest_usb11,
502+ msm_mux_atest_usb12,
503+ msm_mux_atest_usb13,
504+ msm_mux_atest_usb20,
505+ msm_mux_atest_usb21,
506+ msm_mux_atest_usb22,
507+ msm_mux_atest_usb23,
508+ msm_mux_audio_ref,
509+ msm_mux_btfm_slimbus,
510+ msm_mux_cam_mclk,
511+ msm_mux_cci_async,
512+ msm_mux_cci_i2c,
513+ msm_mux_cci_timer0,
514+ msm_mux_cci_timer1,
515+ msm_mux_cci_timer2,
516+ msm_mux_cci_timer3,
517+ msm_mux_cci_timer4,
518+ msm_mux_cri_trng,
519+ msm_mux_cri_trng0,
520+ msm_mux_cri_trng1,
521+ msm_mux_dbg_out,
522+ msm_mux_ddr_bist,
523+ msm_mux_ddr_pxi0,
524+ msm_mux_ddr_pxi1,
525+ msm_mux_ddr_pxi2,
526+ msm_mux_ddr_pxi3,
527+ msm_mux_edp_hot,
528+ msm_mux_edp_lcd,
529+ msm_mux_emac_phy,
530+ msm_mux_emac_pps,
531+ msm_mux_gcc_gp1,
532+ msm_mux_gcc_gp2,
533+ msm_mux_gcc_gp3,
534+ msm_mux_gpio,
535+ msm_mux_jitter_bist,
536+ msm_mux_hs1_mi2s,
537+ msm_mux_hs2_mi2s,
538+ msm_mux_hs3_mi2s,
539+ msm_mux_lpass_slimbus,
540+ msm_mux_mdp_vsync,
541+ msm_mux_mdp_vsync0,
542+ msm_mux_mdp_vsync1,
543+ msm_mux_mdp_vsync2,
544+ msm_mux_mdp_vsync3,
545+ msm_mux_mss_lte,
546+ msm_mux_m_voc,
547+ msm_mux_nav_pps,
548+ msm_mux_pa_indicator,
549+ msm_mux_pci_e0,
550+ msm_mux_pci_e1,
551+ msm_mux_phase_flag,
552+ msm_mux_pll_bist,
553+ msm_mux_pll_bypassnl,
554+ msm_mux_pll_reset,
555+ msm_mux_pri_mi2s,
556+ msm_mux_pri_mi2s_ws,
557+ msm_mux_prng_rosc,
558+ msm_mux_qdss,
559+ msm_mux_qdss_cti,
560+ msm_mux_qlink_enable,
561+ msm_mux_qlink_request,
562+ msm_mux_qspi0,
563+ msm_mux_qspi1,
564+ msm_mux_qspi2,
565+ msm_mux_qspi3,
566+ msm_mux_qspi_clk,
567+ msm_mux_qspi_cs,
568+ msm_mux_qua_mi2s,
569+ msm_mux_qup0,
570+ msm_mux_qup1,
571+ msm_mux_qup2,
572+ msm_mux_qup3,
573+ msm_mux_qup4,
574+ msm_mux_qup5,
575+ msm_mux_qup6,
576+ msm_mux_qup7,
577+ msm_mux_qup8,
578+ msm_mux_qup9,
579+ msm_mux_qup10,
580+ msm_mux_qup11,
581+ msm_mux_qup12,
582+ msm_mux_qup13,
583+ msm_mux_qup14,
584+ msm_mux_qup15,
585+ msm_mux_qup16,
586+ msm_mux_qup17,
587+ msm_mux_qup18,
588+ msm_mux_qup19,
589+ msm_mux_qup_l4,
590+ msm_mux_qup_l5,
591+ msm_mux_qup_l6,
592+ msm_mux_rgmii,
593+ msm_mux_sdc4,
594+ msm_mux_sd_write,
595+ msm_mux_sec_mi2s,
596+ msm_mux_spkr_i2s,
597+ msm_mux_sp_cmu,
598+ msm_mux_ter_mi2s,
599+ msm_mux_tgu_ch0,
600+ msm_mux_tgu_ch2,
601+ msm_mux_tgu_ch1,
602+ msm_mux_tgu_ch3,
603+ msm_mux_tsense_pwm1,
604+ msm_mux_tsense_pwm2,
605+ msm_mux_tsif1,
606+ msm_mux_tsif2,
607+ msm_mux_uim1,
608+ msm_mux_uim2,
609+ msm_mux_uim_batt,
610+ msm_mux_usb2phy_ac,
611+ msm_mux_usb_phy,
612+ msm_mux_vfr_1,
613+ msm_mux_vsense_trigger,
614+ msm_mux_wlan1_adc1,
615+ msm_mux_wlan1_adc0,
616+ msm_mux_wlan2_adc1,
617+ msm_mux_wlan2_adc0,
618+ msm_mux_wmss_reset,
619+ msm_mux__,
620+};
621+
622+static const char * const phase_flag_groups[] = {
623+ "gpio18", "gpio19", "gpio20", "gpio55", "gpio56",
624+ "gpio57", "gpio59", "gpio64", "gpio68", "gpio76",
625+ "gpio79", "gpio80", "gpio90", "gpio91", "gpio92",
626+ "gpio93", "gpio94", "gpio96", "gpio114", "gpio115",
627+ "gpio116", "gpio117", "gpio118", "gpio119", "gpio120",
628+ "gpio121", "gpio122", "gpio126", "gpio127", "gpio128",
629+ "gpio144", "gpio145",
630+};
631+
632+static const char * const emac_pps_groups[] = {
633+ "gpio81",
634+};
635+
636+static const char * const qup12_groups[] = {
637+ "gpio83", "gpio84", "gpio85", "gpio86",
638+};
639+
640+static const char * const qup16_groups[] = {
641+ "gpio83", "gpio84", "gpio85", "gpio86",
642+};
643+
644+static const char * const tsif1_groups[] = {
645+ "gpio88", "gpio89", "gpio90", "gpio91", "gpio97",
646+};
647+
648+static const char * const qup8_groups[] = {
649+ "gpio88", "gpio89", "gpio90", "gpio91",
650+};
651+
652+static const char * const qspi_cs_groups[] = {
653+ "gpio88", "gpio94",
654+};
655+
656+static const char * const tgu_ch3_groups[] = {
657+ "gpio88",
658+};
659+
660+static const char * const qspi0_groups[] = {
661+ "gpio89",
662+};
663+
664+static const char * const mdp_vsync0_groups[] = {
665+ "gpio89",
666+};
667+
668+static const char * const mdp_vsync1_groups[] = {
669+ "gpio89",
670+};
671+
672+static const char * const mdp_vsync2_groups[] = {
673+ "gpio89",
674+};
675+
676+static const char * const mdp_vsync3_groups[] = {
677+ "gpio89",
678+};
679+
680+static const char * const tgu_ch0_groups[] = {
681+ "gpio89",
682+};
683+
684+static const char * const qspi1_groups[] = {
685+ "gpio90",
686+};
687+
688+static const char * const sdc4_groups[] = {
689+ "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95",
690+};
691+
692+static const char * const tgu_ch1_groups[] = {
693+ "gpio90",
694+};
695+
696+static const char * const wlan1_adc1_groups[] = {
697+ "gpio90",
698+};
699+
700+static const char * const qspi2_groups[] = {
701+ "gpio91",
702+};
703+
704+static const char * const vfr_1_groups[] = {
705+ "gpio91",
706+};
707+
708+static const char * const tgu_ch2_groups[] = {
709+ "gpio91",
710+};
711+
712+static const char * const wlan1_adc0_groups[] = {
713+ "gpio91",
714+};
715+
716+static const char * const tsif2_groups[] = {
717+ "gpio92", "gpio93", "gpio94", "gpio95", "gpio96",
718+};
719+
720+static const char * const qup11_groups[] = {
721+ "gpio92", "gpio93", "gpio94", "gpio95",
722+};
723+
724+static const char * const qspi_clk_groups[] = {
725+ "gpio92",
726+};
727+
728+static const char * const wlan2_adc1_groups[] = {
729+ "gpio92",
730+};
731+
732+static const char * const qspi3_groups[] = {
733+ "gpio93",
734+};
735+
736+static const char * const wlan2_adc0_groups[] = {
737+ "gpio93",
738+};
739+
740+static const char * const sd_write_groups[] = {
741+ "gpio97",
742+};
743+
744+static const char * const qup7_groups[] = {
745+ "gpio98", "gpio99", "gpio100", "gpio101",
746+};
747+
748+static const char * const ddr_bist_groups[] = {
749+ "gpio98", "gpio99", "gpio145", "gpio146",
750+};
751+
752+static const char * const ddr_pxi3_groups[] = {
753+ "gpio98", "gpio101",
754+};
755+
756+static const char * const atest_usb13_groups[] = {
757+ "gpio99",
758+};
759+
760+static const char * const ddr_pxi1_groups[] = {
761+ "gpio99", "gpio100",
762+};
763+
764+static const char * const pll_bypassnl_groups[] = {
765+ "gpio100",
766+};
767+
768+static const char * const atest_usb12_groups[] = {
769+ "gpio100",
770+};
771+
772+static const char * const pll_reset_groups[] = {
773+ "gpio101",
774+};
775+
776+static const char * const pci_e1_groups[] = {
777+ "gpio102", "gpio103",
778+};
779+
780+static const char * const uim2_groups[] = {
781+ "gpio105", "gpio106", "gpio107", "gpio108",
782+};
783+
784+static const char * const uim1_groups[] = {
785+ "gpio109", "gpio110", "gpio111", "gpio112",
786+};
787+
788+static const char * const uim_batt_groups[] = {
789+ "gpio113",
790+};
791+
792+static const char * const usb2phy_ac_groups[] = {
793+ "gpio113", "gpio123",
794+};
795+
796+static const char * const aoss_cti_groups[] = {
797+ "gpio113",
798+};
799+
800+static const char * const qup1_groups[] = {
801+ "gpio114", "gpio115", "gpio116", "gpio117",
802+};
803+
804+static const char * const rgmii_groups[] = {
805+ "gpio4", "gpio5", "gpio6", "gpio7", "gpio59",
806+ "gpio114", "gpio115", "gpio116", "gpio117",
807+ "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
808+};
809+
810+static const char * const adsp_ext_groups[] = {
811+ "gpio115",
812+};
813+
814+static const char * const qup5_groups[] = {
815+ "gpio119", "gpio120", "gpio121", "gpio122",
816+};
817+
818+static const char * const atest_usb22_groups[] = {
819+ "gpio123",
820+};
821+
822+static const char * const emac_phy_groups[] = {
823+ "gpio124",
824+};
825+
826+static const char * const hs3_mi2s_groups[] = {
827+ "gpio125", "gpio165", "gpio166", "gpio167", "gpio168",
828+};
829+
830+static const char * const sec_mi2s_groups[] = {
831+ "gpio126", "gpio127", "gpio128", "gpio129", "gpio130",
832+};
833+
834+static const char * const qup2_groups[] = {
835+ "gpio126", "gpio127", "gpio128", "gpio129",
836+};
837+
838+static const char * const jitter_bist_groups[] = {
839+ "gpio129",
840+};
841+
842+static const char * const atest_usb21_groups[] = {
843+ "gpio129",
844+};
845+
846+static const char * const pll_bist_groups[] = {
847+ "gpio130",
848+};
849+
850+static const char * const atest_usb20_groups[] = {
851+ "gpio130",
852+};
853+
854+static const char * const atest_char0_groups[] = {
855+ "gpio130",
856+};
857+
858+static const char * const ter_mi2s_groups[] = {
859+ "gpio131", "gpio132", "gpio133", "gpio134", "gpio135",
860+};
861+
862+static const char * const gcc_gp1_groups[] = {
863+ "gpio131", "gpio136",
864+};
865+
866+static const char * const atest_char1_groups[] = {
867+ "gpio133",
868+};
869+
870+static const char * const atest_char2_groups[] = {
871+ "gpio134",
872+};
873+
874+static const char * const atest_char3_groups[] = {
875+ "gpio135",
876+};
877+
878+static const char * const qua_mi2s_groups[] = {
879+ "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", "gpio141",
880+ "gpio142",
881+};
882+
883+static const char * const pri_mi2s_groups[] = {
884+ "gpio143", "gpio144", "gpio146", "gpio147",
885+};
886+
887+static const char * const qup3_groups[] = {
888+ "gpio144", "gpio145", "gpio146", "gpio147",
889+};
890+
891+static const char * const ddr_pxi0_groups[] = {
892+ "gpio144", "gpio145",
893+};
894+
895+static const char * const pri_mi2s_ws_groups[] = {
896+ "gpio145",
897+};
898+
899+static const char * const vsense_trigger_groups[] = {
900+ "gpio145",
901+};
902+
903+static const char * const atest_usb1_groups[] = {
904+ "gpio145",
905+};
906+
907+static const char * const atest_usb11_groups[] = {
908+ "gpio146",
909+};
910+
911+static const char * const ddr_pxi2_groups[] = {
912+ "gpio146", "gpio147",
913+};
914+
915+static const char * const dbg_out_groups[] = {
916+ "gpio147",
917+};
918+
919+static const char * const atest_usb10_groups[] = {
920+ "gpio147",
921+};
922+
923+static const char * const spkr_i2s_groups[] = {
924+ "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
925+};
926+
927+static const char * const audio_ref_groups[] = {
928+ "gpio148",
929+};
930+
931+static const char * const lpass_slimbus_groups[] = {
932+ "gpio149", "gpio150", "gpio151", "gpio152",
933+};
934+
935+static const char * const tsense_pwm1_groups[] = {
936+ "gpio150",
937+};
938+
939+static const char * const tsense_pwm2_groups[] = {
940+ "gpio150",
941+};
942+
943+static const char * const btfm_slimbus_groups[] = {
944+ "gpio153", "gpio154",
945+};
946+
947+static const char * const hs1_mi2s_groups[] = {
948+ "gpio155", "gpio156", "gpio157", "gpio158", "gpio159",
949+};
950+
951+static const char * const cri_trng0_groups[] = {
952+ "gpio159",
953+};
954+
955+static const char * const hs2_mi2s_groups[] = {
956+ "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
957+};
958+
959+static const char * const cri_trng1_groups[] = {
960+ "gpio160",
961+};
962+
963+static const char * const cri_trng_groups[] = {
964+ "gpio161",
965+};
966+
967+static const char * const sp_cmu_groups[] = {
968+ "gpio162",
969+};
970+
971+static const char * const prng_rosc_groups[] = {
972+ "gpio163",
973+};
974+
975+static const char * const qup0_groups[] = {
976+ "gpio0", "gpio1", "gpio2", "gpio3",
977+};
978+
979+static const char * const gpio_groups[] = {
980+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
981+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
982+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
983+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
984+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
985+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
986+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
987+ "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
988+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
989+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
990+ "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
991+ "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
992+ "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
993+ "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
994+ "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
995+ "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
996+ "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
997+ "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
998+ "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
999+ "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
1000+ "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
1001+ "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
1002+ "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
1003+ "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158",
1004+ "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
1005+ "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
1006+ "gpio171", "gpio172", "gpio173", "gpio174",
1007+};
1008+
1009+static const char * const qup6_groups[] = {
1010+ "gpio4", "gpio5", "gpio6", "gpio7",
1011+};
1012+
1013+static const char * const qup_l6_groups[] = {
1014+ "gpio6", "gpio34", "gpio97", "gpio123",
1015+};
1016+
1017+static const char * const qup_l5_groups[] = {
1018+ "gpio7", "gpio33", "gpio82", "gpio96",
1019+};
1020+
1021+static const char * const mdp_vsync_groups[] = {
1022+ "gpio8", "gpio9", "gpio10", "gpio81", "gpio82",
1023+};
1024+
1025+static const char * const edp_lcd_groups[] = {
1026+ "gpio9",
1027+};
1028+
1029+static const char * const qup10_groups[] = {
1030+ "gpio9", "gpio10", "gpio11", "gpio12",
1031+};
1032+
1033+static const char * const m_voc_groups[] = {
1034+ "gpio10",
1035+};
1036+
1037+static const char * const edp_hot_groups[] = {
1038+ "gpio10",
1039+};
1040+
1041+static const char * const cam_mclk_groups[] = {
1042+ "gpio13", "gpio14", "gpio15", "gpio16",
1043+};
1044+
1045+static const char * const qdss_groups[] = {
1046+ "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
1047+ "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
1048+ "gpio23", "gpio24", "gpio25", "gpio26", "gpio27",
1049+ "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
1050+ "gpio33", "gpio39", "gpio40", "gpio41", "gpio42",
1051+ "gpio47", "gpio48", "gpio83", "gpio117", "gpio118",
1052+ "gpio119", "gpio120", "gpio121", "gpio132",
1053+ "gpio133", "gpio134",
1054+};
1055+
1056+static const char * const cci_i2c_groups[] = {
1057+ "gpio17", "gpio18", "gpio19", "gpio20", "gpio31", "gpio32", "gpio33",
1058+ "gpio34",
1059+};
1060+
1061+static const char * const cci_timer0_groups[] = {
1062+ "gpio21",
1063+};
1064+
1065+static const char * const gcc_gp2_groups[] = {
1066+ "gpio21", "gpio137",
1067+};
1068+
1069+static const char * const cci_timer1_groups[] = {
1070+ "gpio22",
1071+};
1072+
1073+static const char * const gcc_gp3_groups[] = {
1074+ "gpio22", "gpio138",
1075+};
1076+
1077+static const char * const cci_timer2_groups[] = {
1078+ "gpio23",
1079+};
1080+
1081+static const char * const qup18_groups[] = {
1082+ "gpio23", "gpio24", "gpio25", "gpio26",
1083+};
1084+
1085+static const char * const cci_timer3_groups[] = {
1086+ "gpio24",
1087+};
1088+
1089+static const char * const cci_async_groups[] = {
1090+ "gpio24", "gpio25", "gpio26",
1091+};
1092+
1093+static const char * const cci_timer4_groups[] = {
1094+ "gpio25",
1095+};
1096+
1097+static const char * const qup15_groups[] = {
1098+ "gpio27", "gpio28", "gpio29", "gpio30",
1099+};
1100+
1101+static const char * const pci_e0_groups[] = {
1102+ "gpio35", "gpio36",
1103+};
1104+
1105+static const char * const qup_l4_groups[] = {
1106+ "gpio37", "gpio59", "gpio81", "gpio95",
1107+};
1108+
1109+static const char * const agera_pll_groups[] = {
1110+ "gpio37",
1111+};
1112+
1113+static const char * const usb_phy_groups[] = {
1114+ "gpio38",
1115+};
1116+
1117+static const char * const qup9_groups[] = {
1118+ "gpio39", "gpio40", "gpio41", "gpio42",
1119+};
1120+
1121+static const char * const qup13_groups[] = {
1122+ "gpio43", "gpio44", "gpio45", "gpio46",
1123+};
1124+
1125+static const char * const qdss_cti_groups[] = {
1126+ "gpio45", "gpio46", "gpio49", "gpio50", "gpio56", "gpio57", "gpio58",
1127+ "gpio58",
1128+};
1129+
1130+static const char * const qup14_groups[] = {
1131+ "gpio47", "gpio48", "gpio49", "gpio50",
1132+};
1133+
1134+static const char * const qup4_groups[] = {
1135+ "gpio51", "gpio52", "gpio53", "gpio54",
1136+};
1137+
1138+static const char * const qup17_groups[] = {
1139+ "gpio55", "gpio56", "gpio57", "gpio58",
1140+};
1141+
1142+static const char * const qup19_groups[] = {
1143+ "gpio55", "gpio56", "gpio57", "gpio58",
1144+};
1145+
1146+static const char * const atest_char_groups[] = {
1147+ "gpio59",
1148+};
1149+
1150+static const char * const nav_pps_groups[] = {
1151+ "gpio60", "gpio60", "gpio76", "gpio76", "gpio77", "gpio77", "gpio81",
1152+ "gpio81", "gpio82", "gpio82",
1153+};
1154+
1155+static const char * const atest_usb2_groups[] = {
1156+ "gpio60",
1157+};
1158+
1159+static const char * const qlink_request_groups[] = {
1160+ "gpio61",
1161+};
1162+
1163+static const char * const qlink_enable_groups[] = {
1164+ "gpio62",
1165+};
1166+
1167+static const char * const wmss_reset_groups[] = {
1168+ "gpio63",
1169+};
1170+
1171+static const char * const atest_usb23_groups[] = {
1172+ "gpio63",
1173+};
1174+
1175+static const char * const pa_indicator_groups[] = {
1176+ "gpio68",
1177+};
1178+
1179+static const char * const mss_lte_groups[] = {
1180+ "gpio69", "gpio70",
1181+};
1182+
1183+static const struct msm_function sm8150_functions[] = {
1184+ FUNCTION(adsp_ext),
1185+ FUNCTION(agera_pll),
1186+ FUNCTION(aoss_cti),
1187+ FUNCTION(ddr_pxi2),
1188+ FUNCTION(atest_char),
1189+ FUNCTION(atest_char0),
1190+ FUNCTION(atest_char1),
1191+ FUNCTION(atest_char2),
1192+ FUNCTION(atest_char3),
1193+ FUNCTION(audio_ref),
1194+ FUNCTION(atest_usb1),
1195+ FUNCTION(atest_usb2),
1196+ FUNCTION(atest_usb10),
1197+ FUNCTION(atest_usb11),
1198+ FUNCTION(atest_usb12),
1199+ FUNCTION(atest_usb13),
1200+ FUNCTION(atest_usb20),
1201+ FUNCTION(atest_usb21),
1202+ FUNCTION(atest_usb22),
1203+ FUNCTION(atest_usb23),
1204+ FUNCTION(btfm_slimbus),
1205+ FUNCTION(cam_mclk),
1206+ FUNCTION(cci_async),
1207+ FUNCTION(cci_i2c),
1208+ FUNCTION(cci_timer0),
1209+ FUNCTION(cci_timer1),
1210+ FUNCTION(cci_timer2),
1211+ FUNCTION(cci_timer3),
1212+ FUNCTION(cci_timer4),
1213+ FUNCTION(cri_trng),
1214+ FUNCTION(cri_trng0),
1215+ FUNCTION(cri_trng1),
1216+ FUNCTION(dbg_out),
1217+ FUNCTION(ddr_bist),
1218+ FUNCTION(ddr_pxi0),
1219+ FUNCTION(ddr_pxi1),
1220+ FUNCTION(ddr_pxi3),
1221+ FUNCTION(edp_hot),
1222+ FUNCTION(edp_lcd),
1223+ FUNCTION(emac_phy),
1224+ FUNCTION(emac_pps),
1225+ FUNCTION(gcc_gp1),
1226+ FUNCTION(gcc_gp2),
1227+ FUNCTION(gcc_gp3),
1228+ FUNCTION(gpio),
1229+ FUNCTION(hs1_mi2s),
1230+ FUNCTION(hs2_mi2s),
1231+ FUNCTION(hs3_mi2s),
1232+ FUNCTION(jitter_bist),
1233+ FUNCTION(lpass_slimbus),
1234+ FUNCTION(mdp_vsync),
1235+ FUNCTION(mdp_vsync0),
1236+ FUNCTION(mdp_vsync1),
1237+ FUNCTION(mdp_vsync2),
1238+ FUNCTION(mdp_vsync3),
1239+ FUNCTION(mss_lte),
1240+ FUNCTION(m_voc),
1241+ FUNCTION(nav_pps),
1242+ FUNCTION(pa_indicator),
1243+ FUNCTION(pci_e0),
1244+ FUNCTION(phase_flag),
1245+ FUNCTION(pll_bypassnl),
1246+ FUNCTION(pll_bist),
1247+ FUNCTION(pci_e1),
1248+ FUNCTION(pll_reset),
1249+ FUNCTION(pri_mi2s),
1250+ FUNCTION(pri_mi2s_ws),
1251+ FUNCTION(prng_rosc),
1252+ FUNCTION(qdss),
1253+ FUNCTION(qdss_cti),
1254+ FUNCTION(qlink_request),
1255+ FUNCTION(qlink_enable),
1256+ FUNCTION(qspi0),
1257+ FUNCTION(qspi1),
1258+ FUNCTION(qspi2),
1259+ FUNCTION(qspi3),
1260+ FUNCTION(qspi_clk),
1261+ FUNCTION(qspi_cs),
1262+ FUNCTION(qua_mi2s),
1263+ FUNCTION(qup0),
1264+ FUNCTION(qup1),
1265+ FUNCTION(qup2),
1266+ FUNCTION(qup3),
1267+ FUNCTION(qup4),
1268+ FUNCTION(qup5),
1269+ FUNCTION(qup6),
1270+ FUNCTION(qup7),
1271+ FUNCTION(qup8),
1272+ FUNCTION(qup9),
1273+ FUNCTION(qup10),
1274+ FUNCTION(qup11),
1275+ FUNCTION(qup12),
1276+ FUNCTION(qup13),
1277+ FUNCTION(qup14),
1278+ FUNCTION(qup15),
1279+ FUNCTION(qup16),
1280+ FUNCTION(qup17),
1281+ FUNCTION(qup18),
1282+ FUNCTION(qup19),
1283+ FUNCTION(qup_l4),
1284+ FUNCTION(qup_l5),
1285+ FUNCTION(qup_l6),
1286+ FUNCTION(rgmii),
1287+ FUNCTION(sdc4),
1288+ FUNCTION(sd_write),
1289+ FUNCTION(sec_mi2s),
1290+ FUNCTION(spkr_i2s),
1291+ FUNCTION(sp_cmu),
1292+ FUNCTION(ter_mi2s),
1293+ FUNCTION(tgu_ch0),
1294+ FUNCTION(tgu_ch1),
1295+ FUNCTION(tgu_ch2),
1296+ FUNCTION(tgu_ch3),
1297+ FUNCTION(tsense_pwm1),
1298+ FUNCTION(tsense_pwm2),
1299+ FUNCTION(tsif1),
1300+ FUNCTION(tsif2),
1301+ FUNCTION(uim1),
1302+ FUNCTION(uim2),
1303+ FUNCTION(uim_batt),
1304+ FUNCTION(usb2phy_ac),
1305+ FUNCTION(usb_phy),
1306+ FUNCTION(vfr_1),
1307+ FUNCTION(vsense_trigger),
1308+ FUNCTION(wlan1_adc0),
1309+ FUNCTION(wlan1_adc1),
1310+ FUNCTION(wlan2_adc0),
1311+ FUNCTION(wlan2_adc1),
1312+ FUNCTION(wmss_reset),
1313+};
1314+
1315+/*
1316+ * Every pin is maintained as a single group, and missing or non-existing pin
1317+ * would be maintained as dummy group to synchronize pin group index with
1318+ * pin descriptor registered with pinctrl core.
1319+ * Clients would not be able to request these dummy pin groups.
1320+ */
1321+static const struct msm_pingroup sm8150_groups[] = {
1322+ [0] = PINGROUP(0, SOUTH, qup0, _, _, _, _, _, _, _, _),
1323+ [1] = PINGROUP(1, SOUTH, qup0, _, _, _, _, _, _, _, _),
1324+ [2] = PINGROUP(2, SOUTH, qup0, _, _, _, _, _, _, _, _),
1325+ [3] = PINGROUP(3, SOUTH, qup0, _, _, _, _, _, _, _, _),
1326+ [4] = PINGROUP(4, SOUTH, qup6, rgmii, _, _, _, _, _, _, _),
1327+ [5] = PINGROUP(5, SOUTH, qup6, rgmii, _, _, _, _, _, _, _),
1328+ [6] = PINGROUP(6, SOUTH, qup6, rgmii, qup_l6, _, _, _, _, _, _),
1329+ [7] = PINGROUP(7, SOUTH, qup6, rgmii, qup_l5, _, _, _, _, _, _),
1330+ [8] = PINGROUP(8, NORTH, mdp_vsync, _, _, _, _, _, _, _, _),
1331+ [9] = PINGROUP(9, NORTH, mdp_vsync, edp_lcd, qup10, _, _, _, _, _, _),
1332+ [10] = PINGROUP(10, NORTH, mdp_vsync, m_voc, edp_hot, qup10, _, _, _, _, _),
1333+ [11] = PINGROUP(11, NORTH, qup10, _, _, _, _, _, _, _, _),
1334+ [12] = PINGROUP(12, NORTH, qup10, _, _, _, _, _, _, _, _),
1335+ [13] = PINGROUP(13, NORTH, cam_mclk, qdss, _, _, _, _, _, _, _),
1336+ [14] = PINGROUP(14, NORTH, cam_mclk, qdss, _, _, _, _, _, _, _),
1337+ [15] = PINGROUP(15, NORTH, cam_mclk, qdss, _, _, _, _, _, _, _),
1338+ [16] = PINGROUP(16, NORTH, cam_mclk, qdss, _, _, _, _, _, _, _),
1339+ [17] = PINGROUP(17, NORTH, cci_i2c, qdss, _, _, _, _, _, _, _),
1340+ [18] = PINGROUP(18, NORTH, cci_i2c, phase_flag, _, qdss, _, _, _, _, _),
1341+ [19] = PINGROUP(19, NORTH, cci_i2c, phase_flag, _, qdss, _, _, _, _, _),
1342+ [20] = PINGROUP(20, NORTH, cci_i2c, phase_flag, _, qdss, _, _, _, _, _),
1343+ [21] = PINGROUP(21, EAST, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _),
1344+ [22] = PINGROUP(22, EAST, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _),
1345+ [23] = PINGROUP(23, EAST, cci_timer2, qup18, qdss, _, _, _, _, _, _),
1346+ [24] = PINGROUP(24, EAST, cci_timer3, cci_async, qup18, qdss, _, _, _, _, _),
1347+ [25] = PINGROUP(25, EAST, cci_timer4, cci_async, qup18, qdss, _, _, _, _, _),
1348+ [26] = PINGROUP(26, EAST, cci_async, qup18, qdss, _, _, _, _, _, _),
1349+ [27] = PINGROUP(27, EAST, qup15, _, qdss, _, _, _, _, _, _),
1350+ [28] = PINGROUP(28, EAST, qup15, qdss, _, _, _, _, _, _, _),
1351+ [29] = PINGROUP(29, EAST, qup15, qdss, _, _, _, _, _, _, _),
1352+ [30] = PINGROUP(30, EAST, qup15, qdss, _, _, _, _, _, _, _),
1353+ [31] = PINGROUP(31, NORTH, cci_i2c, qdss, _, _, _, _, _, _, _),
1354+ [32] = PINGROUP(32, NORTH, cci_i2c, qdss, _, _, _, _, _, _, _),
1355+ [33] = PINGROUP(33, NORTH, cci_i2c, qup_l5, qdss, _, _, _, _, _, _),
1356+ [34] = PINGROUP(34, NORTH, cci_i2c, qup_l6, _, _, _, _, _, _, _),
1357+ [35] = PINGROUP(35, NORTH, pci_e0, _, _, _, _, _, _, _, _),
1358+ [36] = PINGROUP(36, NORTH, pci_e0, _, _, _, _, _, _, _, _),
1359+ [37] = PINGROUP(37, NORTH, qup_l4, agera_pll, _, _, _, _, _, _, _),
1360+ [38] = PINGROUP(38, SOUTH, usb_phy, _, _, _, _, _, _, _, _),
1361+ [39] = PINGROUP(39, NORTH, qup9, qdss, _, _, _, _, _, _, _),
1362+ [40] = PINGROUP(40, NORTH, qup9, qdss, _, _, _, _, _, _, _),
1363+ [41] = PINGROUP(41, NORTH, qup9, qdss, _, _, _, _, _, _, _),
1364+ [42] = PINGROUP(42, NORTH, qup9, qdss, _, _, _, _, _, _, _),
1365+ [43] = PINGROUP(43, EAST, qup13, _, _, _, _, _, _, _, _),
1366+ [44] = PINGROUP(44, EAST, qup13, _, _, _, _, _, _, _, _),
1367+ [45] = PINGROUP(45, EAST, qup13, qdss_cti, _, _, _, _, _, _, _),
1368+ [46] = PINGROUP(46, EAST, qup13, qdss_cti, _, _, _, _, _, _, _),
1369+ [47] = PINGROUP(47, EAST, qup14, qdss, _, _, _, _, _, _, _),
1370+ [48] = PINGROUP(48, EAST, qup14, qdss, _, _, _, _, _, _, _),
1371+ [49] = PINGROUP(49, EAST, qup14, _, qdss_cti, _, _, _, _, _, _),
1372+ [50] = PINGROUP(50, EAST, qup14, qdss_cti, _, _, _, _, _, _, _),
1373+ [51] = PINGROUP(51, SOUTH, qup4, _, _, _, _, _, _, _, _),
1374+ [52] = PINGROUP(52, SOUTH, qup4, _, _, _, _, _, _, _, _),
1375+ [53] = PINGROUP(53, SOUTH, qup4, _, _, _, _, _, _, _, _),
1376+ [54] = PINGROUP(54, SOUTH, qup4, _, _, _, _, _, _, _, _),
1377+ [55] = PINGROUP(55, SOUTH, qup17, qup19, phase_flag, _, _, _, _, _, _),
1378+ [56] = PINGROUP(56, SOUTH, qup17, qup19, qdss_cti, phase_flag, _, _, _, _, _),
1379+ [57] = PINGROUP(57, SOUTH, qup17, qup19, qdss_cti, phase_flag, _, _, _, _, _),
1380+ [58] = PINGROUP(58, SOUTH, qup17, qup19, qdss_cti, phase_flag, _, _, _, _, _),
1381+ [59] = PINGROUP(59, SOUTH, rgmii, qup_l4, phase_flag, _, atest_char, _, _, _, _),
1382+ [60] = PINGROUP(60, SOUTH, _, nav_pps, nav_pps, atest_usb2, _, _, _, _, _),
1383+ [61] = PINGROUP(61, SOUTH, qlink_request, _, _, _, _, _, _, _, _),
1384+ [62] = PINGROUP(62, SOUTH, qlink_enable, _, _, _, _, _, _, _, _),
1385+ [63] = PINGROUP(63, SOUTH, wmss_reset, atest_usb23, _, _, _, _, _, _, _),
1386+ [64] = PINGROUP(64, SOUTH, _, phase_flag, _, _, _, _, _, _, _),
1387+ [65] = PINGROUP(65, SOUTH, _, _, _, _, _, _, _, _, _),
1388+ [66] = PINGROUP(66, SOUTH, _, _, _, _, _, _, _, _, _),
1389+ [67] = PINGROUP(67, SOUTH, _, _, _, _, _, _, _, _, _),
1390+ [68] = PINGROUP(68, SOUTH, _, pa_indicator, phase_flag, _, _, _, _, _, _),
1391+ [69] = PINGROUP(69, SOUTH, mss_lte, _, _, _, _, _, _, _, _),
1392+ [70] = PINGROUP(70, SOUTH, mss_lte, _, _, _, _, _, _, _, _),
1393+ [71] = PINGROUP(71, SOUTH, _, _, _, _, _, _, _, _, _),
1394+ [72] = PINGROUP(72, SOUTH, _, _, _, _, _, _, _, _, _),
1395+ [73] = PINGROUP(73, SOUTH, _, _, _, _, _, _, _, _, _),
1396+ [74] = PINGROUP(74, SOUTH, _, _, _, _, _, _, _, _, _),
1397+ [75] = PINGROUP(75, SOUTH, _, _, _, _, _, _, _, _, _),
1398+ [76] = PINGROUP(76, SOUTH, _, _, _, nav_pps, nav_pps, phase_flag, _, _, _),
1399+ [77] = PINGROUP(77, SOUTH, _, _, _, nav_pps, nav_pps, _, _, _, _),
1400+ [78] = PINGROUP(78, SOUTH, _, _, _, _, _, _, _, _, _),
1401+ [79] = PINGROUP(79, SOUTH, _, _, phase_flag, _, _, _, _, _, _),
1402+ [80] = PINGROUP(80, SOUTH, _, _, phase_flag, _, _, _, _, _, _),
1403+ [81] = PINGROUP(81, SOUTH, _, _, _, nav_pps, nav_pps, qup_l4, mdp_vsync, emac_pps, _),
1404+ [82] = PINGROUP(82, SOUTH, _, _, _, nav_pps, nav_pps, qup_l5, mdp_vsync, _, _),
1405+ [83] = PINGROUP(83, NORTH, qup12, qup16, _, qdss, _, _, _, _, _),
1406+ [84] = PINGROUP(84, NORTH, qup12, qup16, _, _, _, _, _, _, _),
1407+ [85] = PINGROUP(85, NORTH, qup12, qup16, _, _, _, _, _, _, _),
1408+ [86] = PINGROUP(86, NORTH, qup12, qup16, _, _, _, _, _, _, _),
1409+ [87] = PINGROUP(87, EAST, _, _, _, _, _, _, _, _, _),
1410+ [88] = PINGROUP(88, NORTH, tsif1, qup8, qspi_cs, tgu_ch3, _, _, _, _, _),
1411+ [89] = PINGROUP(89, NORTH, tsif1, qup8, qspi0, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, tgu_ch0, _),
1412+ [90] = PINGROUP(90, NORTH, tsif1, qup8, qspi1, sdc4, phase_flag, tgu_ch1, _, _, wlan1_adc1),
1413+ [91] = PINGROUP(91, NORTH, tsif1, qup8, qspi2, sdc4, vfr_1, phase_flag, tgu_ch2, _, _),
1414+ [92] = PINGROUP(92, NORTH, tsif2, qup11, qspi_clk, sdc4, phase_flag, _, wlan2_adc1, _, _),
1415+ [93] = PINGROUP(93, NORTH, tsif2, qup11, qspi3, sdc4, phase_flag, _, wlan2_adc0, _, _),
1416+ [94] = PINGROUP(94, NORTH, tsif2, qup11, qspi_cs, sdc4, phase_flag, _, _, _, _),
1417+ [95] = PINGROUP(95, NORTH, tsif2, qup11, sdc4, qup_l4, _, _, _, _, _),
1418+ [96] = PINGROUP(96, NORTH, tsif2, qup_l5, phase_flag, _, _, _, _, _, _),
1419+ [97] = PINGROUP(97, NORTH, sd_write, tsif1, qup_l6, _, _, _, _, _, _),
1420+ [98] = PINGROUP(98, SOUTH, qup7, ddr_bist, ddr_pxi3, _, _, _, _, _, _),
1421+ [99] = PINGROUP(99, SOUTH, qup7, ddr_bist, atest_usb13, ddr_pxi1, _, _, _, _, _),
1422+ [100] = PINGROUP(100, SOUTH, qup7, pll_bypassnl, atest_usb12, ddr_pxi1, _, _, _, _, _),
1423+ [101] = PINGROUP(101, SOUTH, qup7, pll_reset, ddr_pxi3, _, _, _, _, _, _),
1424+ [102] = PINGROUP(102, NORTH, pci_e1, _, _, _, _, _, _, _, _),
1425+ [103] = PINGROUP(103, NORTH, pci_e1, _, _, _, _, _, _, _, _),
1426+ [104] = PINGROUP(104, NORTH, _, _, _, _, _, _, _, _, _),
1427+ [105] = PINGROUP(105, WEST, uim2, _, _, _, _, _, _, _, _),
1428+ [106] = PINGROUP(106, WEST, uim2, _, _, _, _, _, _, _, _),
1429+ [107] = PINGROUP(107, WEST, uim2, _, _, _, _, _, _, _, _),
1430+ [108] = PINGROUP(108, WEST, uim2, _, _, _, _, _, _, _, _),
1431+ [109] = PINGROUP(109, WEST, uim1, _, _, _, _, _, _, _, _),
1432+ [110] = PINGROUP(110, WEST, uim1, _, _, _, _, _, _, _, _),
1433+ [111] = PINGROUP(111, WEST, uim1, _, _, _, _, _, _, _, _),
1434+ [112] = PINGROUP(112, WEST, uim1, _, _, _, _, _, _, _, _),
1435+ [113] = PINGROUP(113, WEST, uim_batt, usb2phy_ac, aoss_cti, _, _, _, _, _, _),
1436+ [114] = PINGROUP(114, SOUTH, qup1, rgmii, phase_flag, _, _, _, _, _, _),
1437+ [115] = PINGROUP(115, SOUTH, qup1, rgmii, phase_flag, adsp_ext, _, _, _, _, _),
1438+ [116] = PINGROUP(116, SOUTH, qup1, rgmii, phase_flag, _, _, _, _, _, _),
1439+ [117] = PINGROUP(117, SOUTH, qup1, rgmii, phase_flag, _, qdss, _, _, _, _),
1440+ [118] = PINGROUP(118, SOUTH, rgmii, phase_flag, _, qdss, _, _, _, _, _),
1441+ [119] = PINGROUP(119, SOUTH, qup5, rgmii, phase_flag, _, qdss, _, _, _, _),
1442+ [120] = PINGROUP(120, SOUTH, qup5, rgmii, phase_flag, _, qdss, _, _, _, _),
1443+ [121] = PINGROUP(121, SOUTH, qup5, rgmii, phase_flag, _, qdss, _, _, _, _),
1444+ [122] = PINGROUP(122, SOUTH, qup5, rgmii, phase_flag, _, _, _, _, _, _),
1445+ [123] = PINGROUP(123, SOUTH, usb2phy_ac, qup_l6, atest_usb22, _, _, _, _, _, _),
1446+ [124] = PINGROUP(124, SOUTH, emac_phy, _, _, _, _, _, _, _, _),
1447+ [125] = PINGROUP(125, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
1448+ [126] = PINGROUP(126, SOUTH, sec_mi2s, qup2, phase_flag, _, _, _, _, _, _),
1449+ [127] = PINGROUP(127, SOUTH, sec_mi2s, qup2, phase_flag, _, _, _, _, _, _),
1450+ [128] = PINGROUP(128, SOUTH, sec_mi2s, qup2, phase_flag, _, _, _, _, _, _),
1451+ [129] = PINGROUP(129, SOUTH, sec_mi2s, qup2, jitter_bist, atest_usb21, _, _, _, _, _),
1452+ [130] = PINGROUP(130, SOUTH, sec_mi2s, pll_bist, atest_usb20, atest_char0, _, _, _, _, _),
1453+ [131] = PINGROUP(131, SOUTH, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _),
1454+ [132] = PINGROUP(132, SOUTH, ter_mi2s, _, qdss, _, _, _, _, _, _),
1455+ [133] = PINGROUP(133, SOUTH, ter_mi2s, qdss, atest_char1, _, _, _, _, _, _),
1456+ [134] = PINGROUP(134, SOUTH, ter_mi2s, qdss, atest_char2, _, _, _, _, _, _),
1457+ [135] = PINGROUP(135, SOUTH, ter_mi2s, atest_char3, _, _, _, _, _, _, _),
1458+ [136] = PINGROUP(136, SOUTH, qua_mi2s, gcc_gp1, _, _, _, _, _, _, _),
1459+ [137] = PINGROUP(137, SOUTH, qua_mi2s, gcc_gp2, _, _, _, _, _, _, _),
1460+ [138] = PINGROUP(138, SOUTH, qua_mi2s, gcc_gp3, _, _, _, _, _, _, _),
1461+ [139] = PINGROUP(139, SOUTH, qua_mi2s, _, _, _, _, _, _, _, _),
1462+ [140] = PINGROUP(140, SOUTH, qua_mi2s, _, _, _, _, _, _, _, _),
1463+ [141] = PINGROUP(141, SOUTH, qua_mi2s, _, _, _, _, _, _, _, _),
1464+ [142] = PINGROUP(142, SOUTH, qua_mi2s, _, _, _, _, _, _, _, _),
1465+ [143] = PINGROUP(143, SOUTH, pri_mi2s, _, _, _, _, _, _, _, _),
1466+ [144] = PINGROUP(144, SOUTH, pri_mi2s, qup3, phase_flag, _, ddr_pxi0, _, _, _, _),
1467+ [145] = PINGROUP(145, SOUTH, pri_mi2s_ws, qup3, phase_flag, ddr_bist, _, vsense_trigger, atest_usb1, ddr_pxi0, _),
1468+ [146] = PINGROUP(146, SOUTH, pri_mi2s, qup3, ddr_bist, atest_usb11, ddr_pxi2, _, _, _, _),
1469+ [147] = PINGROUP(147, SOUTH, pri_mi2s, qup3, dbg_out, atest_usb10, ddr_pxi2, _, _, _, _),
1470+ [148] = PINGROUP(148, SOUTH, spkr_i2s, audio_ref, _, _, _, _, _, _, _),
1471+ [149] = PINGROUP(149, SOUTH, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _),
1472+ [150] = PINGROUP(150, SOUTH, lpass_slimbus, spkr_i2s, tsense_pwm1, tsense_pwm2, _, _, _, _, _),
1473+ [151] = PINGROUP(151, SOUTH, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _),
1474+ [152] = PINGROUP(152, SOUTH, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _),
1475+ [153] = PINGROUP(153, SOUTH, btfm_slimbus, _, _, _, _, _, _, _, _),
1476+ [154] = PINGROUP(154, SOUTH, btfm_slimbus, _, _, _, _, _, _, _, _),
1477+ [155] = PINGROUP(155, WEST, hs1_mi2s, _, _, _, _, _, _, _, _),
1478+ [156] = PINGROUP(156, WEST, hs1_mi2s, _, _, _, _, _, _, _, _),
1479+ [157] = PINGROUP(157, WEST, hs1_mi2s, _, _, _, _, _, _, _, _),
1480+ [158] = PINGROUP(158, WEST, hs1_mi2s, _, _, _, _, _, _, _, _),
1481+ [159] = PINGROUP(159, WEST, hs1_mi2s, cri_trng0, _, _, _, _, _, _, _),
1482+ [160] = PINGROUP(160, WEST, hs2_mi2s, cri_trng1, _, _, _, _, _, _, _),
1483+ [161] = PINGROUP(161, WEST, hs2_mi2s, cri_trng, _, _, _, _, _, _, _),
1484+ [162] = PINGROUP(162, WEST, hs2_mi2s, sp_cmu, _, _, _, _, _, _, _),
1485+ [163] = PINGROUP(163, WEST, hs2_mi2s, prng_rosc, _, _, _, _, _, _, _),
1486+ [164] = PINGROUP(164, WEST, hs2_mi2s, _, _, _, _, _, _, _, _),
1487+ [165] = PINGROUP(165, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
1488+ [166] = PINGROUP(166, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
1489+ [167] = PINGROUP(167, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
1490+ [168] = PINGROUP(168, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
1491+ [169] = PINGROUP(169, NORTH, _, _, _, _, _, _, _, _, _),
1492+ [170] = PINGROUP(170, NORTH, _, _, _, _, _, _, _, _, _),
1493+ [171] = PINGROUP(171, NORTH, _, _, _, _, _, _, _, _, _),
1494+ [172] = PINGROUP(172, NORTH, _, _, _, _, _, _, _, _, _),
1495+ [173] = PINGROUP(173, NORTH, _, _, _, _, _, _, _, _, _),
1496+ [174] = PINGROUP(174, NORTH, _, _, _, _, _, _, _, _, _),
1497+ [175] = UFS_RESET(ufs_reset, 0xB6000),
1498+ [176] = SDC_QDSD_PINGROUP(sdc2_clk, 0xB2000, 14, 6),
1499+ [177] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xB2000, 11, 3),
1500+ [178] = SDC_QDSD_PINGROUP(sdc2_data, 0xB2000, 9, 0),
1501+};
1502+
1503+static const struct msm_pinctrl_soc_data sm8150_pinctrl = {
1504+ .pins = sm8150_pins,
1505+ .npins = ARRAY_SIZE(sm8150_pins),
1506+ .functions = sm8150_functions,
1507+ .nfunctions = ARRAY_SIZE(sm8150_functions),
1508+ .groups = sm8150_groups,
1509+ .ngroups = ARRAY_SIZE(sm8150_groups),
1510+ .ngpios = 176,
1511+ .tiles = sm8150_tiles,
1512+ .ntiles = ARRAY_SIZE(sm8150_tiles),
1513+};
1514+
1515+static int sm8150_pinctrl_probe(struct platform_device *pdev)
1516+{
1517+ return msm_pinctrl_probe(pdev, &sm8150_pinctrl);
1518+}
1519+
1520+static const struct of_device_id sm8150_pinctrl_of_match[] = {
1521+ { .compatible = "qcom,sm8150-pinctrl", },
1522+ { },
1523+};
1524+
1525+static struct platform_driver sm8150_pinctrl_driver = {
1526+ .driver = {
1527+ .name = "sm8150-pinctrl",
1528+ .of_match_table = sm8150_pinctrl_of_match,
1529+ },
1530+ .probe = sm8150_pinctrl_probe,
1531+ .remove = msm_pinctrl_remove,
1532+};
1533+
1534+static int __init sm8150_pinctrl_init(void)
1535+{
1536+ return platform_driver_register(&sm8150_pinctrl_driver);
1537+}
1538+arch_initcall(sm8150_pinctrl_init);
1539+
1540+static void __exit sm8150_pinctrl_exit(void)
1541+{
1542+ platform_driver_unregister(&sm8150_pinctrl_driver);
1543+}
1544+module_exit(sm8150_pinctrl_exit);
1545+
1546+MODULE_DESCRIPTION("QTI sm8150 pinctrl driver");
1547+MODULE_LICENSE("GPL v2");
1548+MODULE_DEVICE_TABLE(of, sm8150_pinctrl_of_match);
drivers/pinctrl/sh-pfc/core.c+50−10
@@ -717,7 +717,7 @@ static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; } · 716 unmodified lines
717717 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
718718
719719 #ifdef DEBUG
720−static bool is0s(const u16 *enum_ids, unsigned int n)
720+static bool __init is0s(const u16 *enum_ids, unsigned int n)
721721 {
722722 unsigned int i;
723723
@@ -728,11 +728,11 @@ static bool is0s(const u16 *enum_ids, unsigned int n) · 4 unmodified lines
728728 return true;
729729 }
730730
731−static unsigned int sh_pfc_errors;
732−static unsigned int sh_pfc_warnings;
731+static unsigned int sh_pfc_errors __initdata = 0;
732+static unsigned int sh_pfc_warnings __initdata = 0;
733733
734−static void sh_pfc_check_cfg_reg(const char *drvname,
735− const struct pinmux_cfg_reg *cfg_reg)
734+static void __init sh_pfc_check_cfg_reg(const char *drvname,
735+ const struct pinmux_cfg_reg *cfg_reg)
736736 {
737737 unsigned int i, n, rw, fw;
738738
@@ -764,7 +764,7 @@ static void sh_pfc_check_cfg_reg(const char *drvname, · 25 unmodified lines
764764 }
765765 }
766766
767−static void sh_pfc_check_info(const struct sh_pfc_soc_info *info)
767+static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
768768 {
769769 const struct sh_pfc_function *func;
770770 const char *drvname = info->name;
@@ -773,6 +773,35 @@ static void sh_pfc_check_info(const struct sh_pfc_soc_info *info) · 2 unmodified lines
773773
774774 pr_info("Checking %s\n", drvname);
775775
776+ /* Check pins */
777+ for (i = 0; i < info->nr_pins; i++) {
778+ for (j = 0; j < i; j++) {
779+ if (!strcmp(info->pins[i].name, info->pins[j].name)) {
780+ pr_err("%s: pin %s/%s: name conflict\n",
781+ drvname, info->pins[i].name,
782+ info->pins[j].name);
783+ sh_pfc_errors++;
784+ }
785+
786+ if (info->pins[i].pin != (u16)-1 &&
787+ info->pins[i].pin == info->pins[j].pin) {
788+ pr_err("%s: pin %s/%s: pin %u conflict\n",
789+ drvname, info->pins[i].name,
790+ info->pins[j].name, info->pins[i].pin);
791+ sh_pfc_errors++;
792+ }
793+
794+ if (info->pins[i].enum_id &&
795+ info->pins[i].enum_id == info->pins[j].enum_id) {
796+ pr_err("%s: pin %s/%s: enum_id %u conflict\n",
797+ drvname, info->pins[i].name,
798+ info->pins[j].name,
799+ info->pins[i].enum_id);
800+ sh_pfc_errors++;
801+ }
802+ }
803+ }
804+
776805 /* Check groups and functions */
777806 refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL);
778807 if (!refcnts)
@@ -780,9 +809,15 @@ static void sh_pfc_check_info(const struct sh_pfc_soc_info *info) · 1 unmodified line
780809
781810 for (i = 0; i < info->nr_functions; i++) {
782811 func = &info->functions[i];
812+ if (!func->name) {
813+ pr_err("%s: empty function %u\n", drvname, i);
814+ sh_pfc_errors++;
815+ continue;
816+ }
783817 for (j = 0; j < func->nr_groups; j++) {
784818 for (k = 0; k < info->nr_groups; k++) {
785− if (!strcmp(func->groups[j],
819+ if (info->groups[k].name &&
820+ !strcmp(func->groups[j],
786821 info->groups[k].name)) {
787822 refcnts[k]++;
788823 break;
@@ -798,13 +833,18 @@ static void sh_pfc_check_info(const struct sh_pfc_soc_info *info) · 9 unmodified lines
798833 }
799834
800835 for (i = 0; i < info->nr_groups; i++) {
836+ if (!info->groups[i].name) {
837+ pr_err("%s: empty group %u\n", drvname, i);
838+ sh_pfc_errors++;
839+ continue;
840+ }
801841 if (!refcnts[i]) {
802842 pr_err("%s: orphan group %s\n", drvname,
803843 info->groups[i].name);
804844 sh_pfc_errors++;
805845 } else if (refcnts[i] > 1) {
806− pr_err("%s: group %s referred by %u functions\n",
807− drvname, info->groups[i].name, refcnts[i]);
846+ pr_warn("%s: group %s referenced by %u functions\n",
847+ drvname, info->groups[i].name, refcnts[i]);
808848 sh_pfc_warnings++;
809849 }
810850 }
@@ -816,7 +856,7 @@ static void sh_pfc_check_info(const struct sh_pfc_soc_info *info) · 5 unmodified lines
816856 sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
817857 }
818858
819−static void sh_pfc_check_driver(const struct platform_driver *pdrv)
859+static void __init sh_pfc_check_driver(const struct platform_driver *pdrv)
820860 {
821861 unsigned int i;
822862
drivers/pinctrl/sh-pfc/pfc-emev2.c+34−36
@@ -19,6 +19,20 @@ · 18 unmodified lines
1919 PORT_1(155, fn, pfx##155, sfx), PORT_1(156, fn, pfx##156, sfx), \
2020 PORT_1(157, fn, pfx##157, sfx), PORT_1(158, fn, pfx##158, sfx)
2121
22+#define CPU_ALL_NOGP(fn) \
23+ PIN_NOGP(LCD3_B2, "B15", fn), \
24+ PIN_NOGP(LCD3_B3, "C15", fn), \
25+ PIN_NOGP(LCD3_B4, "D15", fn), \
26+ PIN_NOGP(LCD3_B5, "B14", fn), \
27+ PIN_NOGP(LCD3_B6, "C14", fn), \
28+ PIN_NOGP(LCD3_B7, "D14", fn), \
29+ PIN_NOGP(LCD3_G2, "B17", fn), \
30+ PIN_NOGP(LCD3_G3, "C17", fn), \
31+ PIN_NOGP(LCD3_G4, "D17", fn), \
32+ PIN_NOGP(LCD3_G5, "B16", fn), \
33+ PIN_NOGP(LCD3_G6, "C16", fn), \
34+ PIN_NOGP(LCD3_G7, "D16", fn)
35+
2236 enum {
2337 PINMUX_RESERVED = 0,
2438
@@ -218,10 +232,13 @@ enum { · 193 unmodified lines
218232 PINMUX_MARK_END,
219233 };
220234
221−/* Pin numbers for pins without a corresponding GPIO port number are computed
222− * from the row and column numbers with a 1000 offset to avoid collisions with
223− * GPIO port numbers. */
224−#define PIN_NUMBER(row, col) (1000+((row)-1)*23+(col)-1)
235+/*
236+ * Pins not associated with a GPIO port.
237+ */
238+enum {
239+ PORT_ASSIGN_LAST(),
240+ NOGP_ALL(),
241+};
225242
226243 /* Expand to a list of sh_pfc_pin entries (named PORT#).
227244 * NOTE: No config are recorded since the driver do not handle pinconf. */
@@ -230,20 +247,7 @@ enum { · 2 unmodified lines
230247
231248 static const struct sh_pfc_pin pinmux_pins[] = {
232249 PINMUX_EMEV_GPIO_ALL(),
233−
234− /* Pins not associated with a GPIO port */
235− SH_PFC_PIN_NAMED(2, 14, B14),
236− SH_PFC_PIN_NAMED(2, 15, B15),
237− SH_PFC_PIN_NAMED(2, 16, B16),
238− SH_PFC_PIN_NAMED(2, 17, B17),
239− SH_PFC_PIN_NAMED(3, 14, C14),
240− SH_PFC_PIN_NAMED(3, 15, C15),
241− SH_PFC_PIN_NAMED(3, 16, C16),
242− SH_PFC_PIN_NAMED(3, 17, C17),
243− SH_PFC_PIN_NAMED(4, 14, D14),
244− SH_PFC_PIN_NAMED(4, 15, D15),
245− SH_PFC_PIN_NAMED(4, 16, D16),
246− SH_PFC_PIN_NAMED(4, 17, D17),
250+ PINMUX_NOGP_ALL(),
247251 };
248252
249253 /* Expand to a list of name_DATA, name_FN marks */
@@ -829,12 +833,10 @@ static const unsigned int lcd3_rgb888_pins[] = { · 579 unmodified lines
829833 /* R[0:7], G[0:7], B[0:7] */
830834 32, 33, 34, 35,
831835 36, 37, 38, 39,
832− 40, 41, PIN_NUMBER(2, 17), PIN_NUMBER(3, 17),
833− PIN_NUMBER(4, 17), PIN_NUMBER(2, 16), PIN_NUMBER(3, 16),
834− PIN_NUMBER(4, 16),
835− 42, 43, PIN_NUMBER(2, 15), PIN_NUMBER(3, 15),
836− PIN_NUMBER(4, 15), PIN_NUMBER(2, 14), PIN_NUMBER(3, 14),
837− PIN_NUMBER(4, 14)
836+ 40, 41, PIN_LCD3_G2, PIN_LCD3_G3,
837+ PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7,
838+ 42, 43, PIN_LCD3_B2, PIN_LCD3_B3,
839+ PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7
838840 };
839841 static const unsigned int lcd3_rgb888_mux[] = {
840842 LCD3_R0_MARK, LCD3_R1_MARK, LCD3_R2_MARK, LCD3_R3_MARK,
@@ -850,12 +852,10 @@ static const unsigned int yuv3_pins[] = { · 9 unmodified lines
850852 /* CLK_O, HS, VS, DE */
851853 18, 21, 22, 23,
852854 /* YUV3_D[0:15] */
853− 40, 41, PIN_NUMBER(2, 17), PIN_NUMBER(3, 17),
854− PIN_NUMBER(4, 17), PIN_NUMBER(2, 16), PIN_NUMBER(3, 16),
855− PIN_NUMBER(4, 16),
856− 42, 43, PIN_NUMBER(2, 15), PIN_NUMBER(3, 15),
857− PIN_NUMBER(4, 15), PIN_NUMBER(2, 14), PIN_NUMBER(3, 14),
858− PIN_NUMBER(4, 14),
855+ 40, 41, PIN_LCD3_G2, PIN_LCD3_G3,
856+ PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7,
857+ 42, 43, PIN_LCD3_B2, PIN_LCD3_B3,
858+ PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7,
859859 };
860860 static const unsigned int yuv3_mux[] = {
861861 YUV3_CLK_O_MARK, YUV3_HS_MARK, YUV3_VS_MARK, YUV3_DE_MARK,
@@ -972,12 +972,10 @@ static const unsigned int tp33_pins[] = { · 110 unmodified lines
972972 /* CLK, CTRL */
973973 38, 39,
974974 /* TP33_DATA[0:15] */
975− 40, 41, PIN_NUMBER(2, 17), PIN_NUMBER(3, 17),
976− PIN_NUMBER(4, 17), PIN_NUMBER(2, 16), PIN_NUMBER(3, 16),
977− PIN_NUMBER(4, 16),
978− 42, 43, PIN_NUMBER(2, 15), PIN_NUMBER(3, 15),
979− PIN_NUMBER(4, 15), PIN_NUMBER(2, 14), PIN_NUMBER(3, 14),
980− PIN_NUMBER(4, 14),
975+ 40, 41, PIN_LCD3_G2, PIN_LCD3_G3,
976+ PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7,
977+ 42, 43, PIN_LCD3_B2, PIN_LCD3_B3,
978+ PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7,
981979 };
982980 static const unsigned int tp33_mux[] = {
983981 TP33_CLK_MARK, TP33_CTRL_MARK,
drivers/pinctrl/sh-pfc/pfc-r8a73a4.c+1−1
@@ -1252,7 +1252,7 @@ static const u16 pinmux_data[] = { · 1251 unmodified lines
12521252
12531253 #define __O (SH_PFC_PIN_CFG_OUTPUT)
12541254 #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1255−#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1255+#define __PUD (SH_PFC_PIN_CFG_PULL_UP_DOWN)
12561256
12571257 #define R8A73A4_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
12581258 #define R8A73A4_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
drivers/pinctrl/sh-pfc/pfc-r8a7740.c+1−1
@@ -1515,7 +1515,7 @@ static const u16 pinmux_data[] = { · 1514 unmodified lines
15151515 #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
15161516 #define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
15171517 #define __PU (SH_PFC_PIN_CFG_PULL_UP)
1518−#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1518+#define __PUD (SH_PFC_PIN_CFG_PULL_UP_DOWN)
15191519
15201520 #define R8A7740_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
15211521 #define R8A7740_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)
drivers/pinctrl/sh-pfc/pfc-r8a77470.c+1−1
@@ -10,7 +10,7 @@ · 9 unmodified lines
1010
1111 #include "sh_pfc.h"
1212
13−#define CPU_ALL_PORT(fn, sfx) \
13+#define CPU_ALL_GP(fn, sfx) \
1414 PORT_GP_4(0, fn, sfx), \
1515 PORT_GP_1(0, 4, fn, sfx), \
1616 PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
drivers/pinctrl/sh-pfc/pfc-r8a7778.c+55−70
@@ -22,28 +22,17 @@ · 21 unmodified lines
2222 #define PORT_GP_PUP_1(bank, pin, fn, sfx) \
2323 PORT_GP_CFG_1(bank, pin, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
2424
25−#define PORT_GP_PUP_27(bank, fn, sfx) \
26− PORT_GP_PUP_1(bank, 0, fn, sfx), PORT_GP_PUP_1(bank, 1, fn, sfx), \
27− PORT_GP_PUP_1(bank, 2, fn, sfx), PORT_GP_PUP_1(bank, 3, fn, sfx), \
28− PORT_GP_PUP_1(bank, 4, fn, sfx), PORT_GP_PUP_1(bank, 5, fn, sfx), \
29− PORT_GP_PUP_1(bank, 6, fn, sfx), PORT_GP_PUP_1(bank, 7, fn, sfx), \
30− PORT_GP_PUP_1(bank, 8, fn, sfx), PORT_GP_PUP_1(bank, 9, fn, sfx), \
31− PORT_GP_PUP_1(bank, 10, fn, sfx), PORT_GP_PUP_1(bank, 11, fn, sfx), \
32− PORT_GP_PUP_1(bank, 12, fn, sfx), PORT_GP_PUP_1(bank, 13, fn, sfx), \
33− PORT_GP_PUP_1(bank, 14, fn, sfx), PORT_GP_PUP_1(bank, 15, fn, sfx), \
34− PORT_GP_PUP_1(bank, 16, fn, sfx), PORT_GP_PUP_1(bank, 17, fn, sfx), \
35− PORT_GP_PUP_1(bank, 18, fn, sfx), PORT_GP_PUP_1(bank, 19, fn, sfx), \
36− PORT_GP_PUP_1(bank, 20, fn, sfx), PORT_GP_PUP_1(bank, 21, fn, sfx), \
37− PORT_GP_PUP_1(bank, 22, fn, sfx), PORT_GP_PUP_1(bank, 23, fn, sfx), \
38− PORT_GP_PUP_1(bank, 24, fn, sfx), PORT_GP_PUP_1(bank, 25, fn, sfx), \
39− PORT_GP_PUP_1(bank, 26, fn, sfx)
40−
41−#define CPU_ALL_PORT(fn, sfx) \
25+#define CPU_ALL_GP(fn, sfx) \
4226 PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
4327 PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
4428 PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
4529 PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
46− PORT_GP_PUP_27(4, fn, sfx)
30+ PORT_GP_CFG_27(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
31+
32+#define CPU_ALL_NOGP(fn) \
33+ PIN_NOGP(CLKOUT, "B25", fn), \
34+ PIN_NOGP(CS0, "A20", fn), \
35+ PIN_NOGP(CS1_A26, "C20", fn)
4736
4837 enum {
4938 PINMUX_RESERVED = 0,
@@ -1253,19 +1242,17 @@ static const u16 pinmux_data[] = { · 1203 unmodified lines
12531242 PINMUX_IPSR_MSEL(IP10_24_22, CAN_CLK_C, SEL_CANCLK_C),
12541243 };
12551244
1256−/* Pin numbers for pins without a corresponding GPIO port number are computed
1257− * from the row and column numbers with a 1000 offset to avoid collisions with
1258− * GPIO port numbers.
1245+/*
1246+ * Pins not associated with a GPIO port.
12591247 */
1260−#define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1)
1248+enum {
1249+ GP_ASSIGN_LAST(),
1250+ NOGP_ALL(),
1251+};
12611252
12621253 static const struct sh_pfc_pin pinmux_pins[] = {
12631254 PINMUX_GPIO_GP_ALL(),
1264−
1265− /* Pins not associated with a GPIO port */
1266− SH_PFC_PIN_NAMED(3, 20, C20),
1267− SH_PFC_PIN_NAMED(1, 20, A20),
1268− SH_PFC_PIN_NAMED(2, 25, B25),
1255+ PINMUX_NOGP_ALL(),
12691256 };
12701257
12711258 /* - macro */
@@ -1400,7 +1387,7 @@ HSPI_PFC_DAT(hspi1_a, HSPI_CLK1_A, HSPI_CS1_A, · 128 unmodified lines
14001387 HSPI_RX1_A, HSPI_TX1_A);
14011388
14021389 HSPI_PFC_PIN(hspi1_b, RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 26),
1403− PIN_NUMBER(1, 20), PIN_NUMBER(2, 25));
1390+ PIN_CS0, PIN_CLKOUT);
14041391 HSPI_PFC_DAT(hspi1_b, HSPI_CLK1_B, HSPI_CS1_B,
14051392 HSPI_RX1_B, HSPI_TX1_B);
14061393
@@ -1426,7 +1413,7 @@ I2C_PFC_PIN(i2c1_b, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18)); · 19 unmodified lines
14261413 I2C_PFC_MUX(i2c1_b, SDA1_B, SCL1_B);
14271414
14281415 /* - I2C2 ------------------------------------------------------------------ */
1429−I2C_PFC_PIN(i2c2_a, PIN_NUMBER(3, 20), RCAR_GP_PIN(1, 3));
1416+I2C_PFC_PIN(i2c2_a, PIN_CS1_A26, RCAR_GP_PIN(1, 3));
14301417 I2C_PFC_MUX(i2c2_a, SDA2_A, SCL2_A);
14311418 I2C_PFC_PIN(i2c2_b, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4));
14321419 I2C_PFC_MUX(i2c2_b, SDA2_B, SCL2_B);
@@ -1516,7 +1503,7 @@ SCIF_PFC_PIN(scif2_data_e, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4)); · 83 unmodified lines
15161503 SCIF_PFC_DAT(scif2_data_e, TX2_E, RX2_E);
15171504 SCIF_PFC_PIN(scif2_clk_a, RCAR_GP_PIN(3, 9));
15181505 SCIF_PFC_CLK(scif2_clk_a, SCK2_A);
1519−SCIF_PFC_PIN(scif2_clk_b, PIN_NUMBER(3, 20));
1506+SCIF_PFC_PIN(scif2_clk_b, PIN_CS1_A26);
15201507 SCIF_PFC_CLK(scif2_clk_b, SCK2_B);
15211508 SCIF_PFC_PIN(scif2_clk_c, RCAR_GP_PIN(4, 12));
15221509 SCIF_PFC_CLK(scif2_clk_c, SCK2_C);
@@ -1631,7 +1618,7 @@ SSI_PFC_PINS(ssi0_data, RCAR_GP_PIN(3, 10)); · 108 unmodified lines
16311618 SSI_PFC_DATA(ssi0_data, SSI_SDATA0);
16321619 SSI_PFC_PINS(ssi1_a_ctrl, RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21));
16331620 SSI_PFC_CTRL(ssi1_a_ctrl, SSI_SCK1_A, SSI_WS1_A);
1634−SSI_PFC_PINS(ssi1_b_ctrl, PIN_NUMBER(3, 20), RCAR_GP_PIN(1, 3));
1621+SSI_PFC_PINS(ssi1_b_ctrl, PIN_CS1_A26, RCAR_GP_PIN(1, 3));
16351622 SSI_PFC_CTRL(ssi1_b_ctrl, SSI_SCK1_B, SSI_WS1_B);
16361623 SSI_PFC_PINS(ssi1_data, RCAR_GP_PIN(3, 9));
16371624 SSI_PFC_DATA(ssi1_data, SSI_SDATA1);
@@ -2921,8 +2908,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { · 1283 unmodified lines
29212908 { },
29222909 };
29232910
2924−#define PIN_NONE U16_MAX
2925−
29262911 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
29272912 { PINMUX_BIAS_REG("PUPR0", 0x100, "N/A", 0) {
29282913 [ 0] = RCAR_GP_PIN(0, 6), /* A0 */
@@ -2969,28 +2954,28 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 40 unmodified lines
29692954 [ 7] = RCAR_GP_PIN(1, 10), /* DACK0 */
29702955 [ 8] = RCAR_GP_PIN(1, 12), /* IRQ0 */
29712956 [ 9] = RCAR_GP_PIN(1, 13), /* IRQ1 */
2972− [10] = PIN_NONE,
2973− [11] = PIN_NONE,
2974− [12] = PIN_NONE,
2975− [13] = PIN_NONE,
2976− [14] = PIN_NONE,
2977− [15] = PIN_NONE,
2978− [16] = PIN_NONE,
2979− [17] = PIN_NONE,
2980− [18] = PIN_NONE,
2981− [19] = PIN_NONE,
2982− [20] = PIN_NONE,
2983− [21] = PIN_NONE,
2984− [22] = PIN_NONE,
2985− [23] = PIN_NONE,
2986− [24] = PIN_NONE,
2987− [25] = PIN_NONE,
2988− [26] = PIN_NONE,
2989− [27] = PIN_NONE,
2990− [28] = PIN_NONE,
2991− [29] = PIN_NONE,
2992− [30] = PIN_NONE,
2993− [31] = PIN_NONE,
2957+ [10] = SH_PFC_PIN_NONE,
2958+ [11] = SH_PFC_PIN_NONE,
2959+ [12] = SH_PFC_PIN_NONE,
2960+ [13] = SH_PFC_PIN_NONE,
2961+ [14] = SH_PFC_PIN_NONE,
2962+ [15] = SH_PFC_PIN_NONE,
2963+ [16] = SH_PFC_PIN_NONE,
2964+ [17] = SH_PFC_PIN_NONE,
2965+ [18] = SH_PFC_PIN_NONE,
2966+ [19] = SH_PFC_PIN_NONE,
2967+ [20] = SH_PFC_PIN_NONE,
2968+ [21] = SH_PFC_PIN_NONE,
2969+ [22] = SH_PFC_PIN_NONE,
2970+ [23] = SH_PFC_PIN_NONE,
2971+ [24] = SH_PFC_PIN_NONE,
2972+ [25] = SH_PFC_PIN_NONE,
2973+ [26] = SH_PFC_PIN_NONE,
2974+ [27] = SH_PFC_PIN_NONE,
2975+ [28] = SH_PFC_PIN_NONE,
2976+ [29] = SH_PFC_PIN_NONE,
2977+ [30] = SH_PFC_PIN_NONE,
2978+ [31] = SH_PFC_PIN_NONE,
29942979 } },
29952980 { PINMUX_BIAS_REG("PUPR2", 0x108, "N/A", 0) {
29962981 [ 0] = RCAR_GP_PIN(1, 22), /* DU0_DR0 */
@@ -3112,21 +3097,21 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 115 unmodified lines
31123097 [14] = RCAR_GP_PIN(4, 20), /* ETH_MAGIC */
31133098 [15] = RCAR_GP_PIN(4, 25), /* AVS1 */
31143099 [16] = RCAR_GP_PIN(4, 26), /* AVS2 */
3115− [17] = PIN_NONE,
3116− [18] = PIN_NONE,
3117− [19] = PIN_NONE,
3118− [20] = PIN_NONE,
3119− [21] = PIN_NONE,
3120− [22] = PIN_NONE,
3121− [23] = PIN_NONE,
3122− [24] = PIN_NONE,
3123− [25] = PIN_NONE,
3124− [26] = PIN_NONE,
3125− [27] = PIN_NONE,
3126− [28] = PIN_NONE,
3127− [29] = PIN_NONE,
3128− [30] = PIN_NONE,
3129− [31] = PIN_NONE,
3100+ [17] = SH_PFC_PIN_NONE,
3101+ [18] = SH_PFC_PIN_NONE,
3102+ [19] = SH_PFC_PIN_NONE,
3103+ [20] = SH_PFC_PIN_NONE,
3104+ [21] = SH_PFC_PIN_NONE,
3105+ [22] = SH_PFC_PIN_NONE,
3106+ [23] = SH_PFC_PIN_NONE,
3107+ [24] = SH_PFC_PIN_NONE,
3108+ [25] = SH_PFC_PIN_NONE,
3109+ [26] = SH_PFC_PIN_NONE,
3110+ [27] = SH_PFC_PIN_NONE,
3111+ [28] = SH_PFC_PIN_NONE,
3112+ [29] = SH_PFC_PIN_NONE,
3113+ [30] = SH_PFC_PIN_NONE,
3114+ [31] = SH_PFC_PIN_NONE,
31303115 } },
31313116 { /* sentinel */ },
31323117 };
drivers/pinctrl/sh-pfc/pfc-r8a7779.c+1−1
@@ -11,7 +11,7 @@ · 10 unmodified lines
1111
1212 #include "sh_pfc.h"
1313
14−#define CPU_ALL_PORT(fn, sfx) \
14+#define CPU_ALL_GP(fn, sfx) \
1515 PORT_GP_32(0, fn, sfx), \
1616 PORT_GP_32(1, fn, sfx), \
1717 PORT_GP_32(2, fn, sfx), \
drivers/pinctrl/sh-pfc/pfc-r8a7790.c+20−16
@@ -20,7 +20,7 @@ · 19 unmodified lines
2020 * All pins assigned to GPIO bank 3 can be used for SD interfaces in
2121 * which case they support both 3.3V and 1.8V signalling.
2222 */
23−#define CPU_ALL_PORT(fn, sfx) \
23+#define CPU_ALL_GP(fn, sfx) \
2424 PORT_GP_32(0, fn, sfx), \
2525 PORT_GP_30(1, fn, sfx), \
2626 PORT_GP_30(2, fn, sfx), \
@@ -28,6 +28,12 @@ · 1 unmodified line
2828 PORT_GP_32(4, fn, sfx), \
2929 PORT_GP_32(5, fn, sfx)
3030
31+#define CPU_ALL_NOGP(fn) \
32+ PIN_NOGP(IIC0_SDA, "AF15", fn), \
33+ PIN_NOGP(IIC0_SCL, "AG15", fn), \
34+ PIN_NOGP(IIC3_SDA, "AH15", fn), \
35+ PIN_NOGP(IIC3_SCL, "AJ15", fn)
36+
3137 enum {
3238 PINMUX_RESERVED = 0,
3339
@@ -1727,19 +1733,17 @@ static const u16 pinmux_data[] = { · 1693 unmodified lines
17271733 PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
17281734 };
17291735
1730−/* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */
1731−#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1732−#define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200)
1733−#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1736+/*
1737+ * Pins not associated with a GPIO port.
1738+ */
1739+enum {
1740+ GP_ASSIGN_LAST(),
1741+ NOGP_ALL(),
1742+};
17341743
17351744 static const struct sh_pfc_pin pinmux_pins[] = {
17361745 PINMUX_GPIO_GP_ALL(),
1737−
1738− /* Pins not associated with a GPIO port */
1739− SH_PFC_PIN_NAMED(ROW_GROUP_A('F'), 15, AF15),
1740− SH_PFC_PIN_NAMED(ROW_GROUP_A('G'), 15, AG15),
1741− SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15),
1742− SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15),
1746+ PINMUX_NOGP_ALL(),
17431747 };
17441748
17451749 /* - AUDIO CLOCK ------------------------------------------------------------ */
@@ -2135,7 +2139,7 @@ static const unsigned int hscif1_ctrl_b_mux[] = { · 389 unmodified lines
21352139 /* - I2C0 ------------------------------------------------------------------- */
21362140 static const unsigned int i2c0_pins[] = {
21372141 /* SCL, SDA */
2138− PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
2142+ PIN_IIC0_SCL, PIN_IIC0_SDA,
21392143 };
21402144 static const unsigned int i2c0_mux[] = {
21412145 I2C0_SCL_MARK, I2C0_SDA_MARK,
@@ -2201,7 +2205,7 @@ static const unsigned int i2c2_e_mux[] = { · 59 unmodified lines
22012205 /* - I2C3 ------------------------------------------------------------------- */
22022206 static const unsigned int i2c3_pins[] = {
22032207 /* SCL, SDA */
2204− PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2208+ PIN_IIC3_SCL, PIN_IIC3_SDA,
22052209 };
22062210 static const unsigned int i2c3_mux[] = {
22072211 I2C3_SCL_MARK, I2C3_SDA_MARK,
@@ -2209,7 +2213,7 @@ static const unsigned int i2c3_mux[] = { · 1 unmodified line
22092213 /* - IIC0 (I2C4) ------------------------------------------------------------ */
22102214 static const unsigned int iic0_pins[] = {
22112215 /* SCL, SDA */
2212− PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
2216+ PIN_IIC0_SCL, PIN_IIC0_SDA,
22132217 };
22142218 static const unsigned int iic0_mux[] = {
22152219 IIC0_SCL_MARK, IIC0_SDA_MARK,
@@ -2274,8 +2278,8 @@ static const unsigned int iic2_e_mux[] = { · 58 unmodified lines
22742278 };
22752279 /* - IIC3 (I2C7) ------------------------------------------------------------ */
22762280 static const unsigned int iic3_pins[] = {
2277−/* SCL, SDA */
2278− PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2281+ /* SCL, SDA */
2282+ PIN_IIC3_SCL, PIN_IIC3_SDA,
22792283 };
22802284 static const unsigned int iic3_mux[] = {
22812285 IIC3_SCL_MARK, IIC3_SDA_MARK,
drivers/pinctrl/sh-pfc/pfc-r8a7791.c+1−1
@@ -15,7 +15,7 @@ · 14 unmodified lines
1515 * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
1616 * which case they support both 3.3V and 1.8V signalling.
1717 */
18−#define CPU_ALL_PORT(fn, sfx) \
18+#define CPU_ALL_GP(fn, sfx) \
1919 PORT_GP_32(0, fn, sfx), \
2020 PORT_GP_26(1, fn, sfx), \
2121 PORT_GP_32(2, fn, sfx), \
drivers/pinctrl/sh-pfc/pfc-r8a7792.c+1−1
@@ -11,7 +11,7 @@ · 10 unmodified lines
1111 #include "core.h"
1212 #include "sh_pfc.h"
1313
14−#define CPU_ALL_PORT(fn, sfx) \
14+#define CPU_ALL_GP(fn, sfx) \
1515 PORT_GP_29(0, fn, sfx), \
1616 PORT_GP_23(1, fn, sfx), \
1717 PORT_GP_32(2, fn, sfx), \
drivers/pinctrl/sh-pfc/pfc-r8a7794.c+1−1
@@ -14,7 +14,7 @@ · 13 unmodified lines
1414 #include "core.h"
1515 #include "sh_pfc.h"
1616
17−#define CPU_ALL_PORT(fn, sfx) \
17+#define CPU_ALL_GP(fn, sfx) \
1818 PORT_GP_32(0, fn, sfx), \
1919 PORT_GP_26(1, fn, sfx), \
2020 PORT_GP_32(2, fn, sfx), \
drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c+233−201
@@ -11,11 +11,9 @@ · 10 unmodified lines
1111 #include "core.h"
1212 #include "sh_pfc.h"
1313
14−#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
15− SH_PFC_PIN_CFG_PULL_UP | \
16− SH_PFC_PIN_CFG_PULL_DOWN)
14+#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
1715
18−#define CPU_ALL_PORT(fn, sfx) \
16+#define CPU_ALL_GP(fn, sfx) \
1917 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
2018 PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
2119 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
@@ -28,6 +26,53 @@ · 6 unmodified lines
2826 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
2927 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
3028 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
29+
30+#define CPU_ALL_NOGP(fn) \
31+ PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
32+ PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
33+ PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
34+ PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
35+ PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
36+ PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
37+ PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
38+ PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
39+ PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
40+ PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
41+ PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
42+ PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
43+ PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
44+ PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
45+ PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
46+ PIN_NOGP_CFG(CLKOUT, "CLKOUT", fn, CFG_FLAGS), \
47+ PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
48+ PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
49+ PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
50+ PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
51+ PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
52+ PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \
53+ PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
54+ PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
55+ PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
56+ PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
57+ PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
58+ PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
59+ PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
60+ PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
61+ PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
62+ PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
63+ PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
64+ PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
65+ PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
66+ PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
67+ PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
68+ PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
69+ PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
70+ PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
71+ PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
72+ PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
73+ PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
74+ PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
75+
3176 /*
3277 * F_() : just information
3378 * FM() : macro for FN_xxx / xxx_MARK
@@ -1447,69 +1492,16 @@ static const u16 pinmux_data[] = { · 1413 unmodified lines
14471492 };
14481493
14491494 /*
1450− * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1451− * Physical layout rows: A - AW, cols: 1 - 39.
1495+ * Pins not associated with a GPIO port.
14521496 */
1453−#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1454−#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1455−#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1456−#define PIN_NONE U16_MAX
1497+enum {
1498+ GP_ASSIGN_LAST(),
1499+ NOGP_ALL(),
1500+};
14571501
14581502 static const struct sh_pfc_pin pinmux_pins[] = {
14591503 PINMUX_GPIO_GP_ALL(),
1460−
1461− /*
1462− * Pins not associated with a GPIO port.
1463− *
1464− * The pin positions are different between different r8a7795
1465− * packages, all that is needed for the pfc driver is a unique
1466− * number for each pin. To this end use the pin layout from
1467− * R-Car H3SiP to calculate a unique number for each pin.
1468− */
1469− SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1470− SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1471− SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1472− SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1473− SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1474− SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1475− SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1476− SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1477− SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1478− SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1479− SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1480− SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1481− SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1482− SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1483− SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1484− SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS),
1485− SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1486− SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1487− SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1488− SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1489− SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1490− SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1491− SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1492− SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1493− SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1494− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1495− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1496− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1497− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1498− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1499− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1500− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1501− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1502− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1503− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1504− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1505− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
1506− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1507− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1508− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1509− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1510− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1511− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1512− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1504+ PINMUX_NOGP_ALL(),
15131505 };
15141506
15151507 /* - AUDIO CLOCK ------------------------------------------------------------ */
@@ -1658,7 +1650,7 @@ static const unsigned int avb_phy_int_mux[] = { · 142 unmodified lines
16581650 };
16591651 static const unsigned int avb_mdio_pins[] = {
16601652 /* AVB_MDC, AVB_MDIO */
1661− RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1653+ RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
16621654 };
16631655 static const unsigned int avb_mdio_mux[] = {
16641656 AVB_MDC_MARK, AVB_MDIO_MARK,
@@ -1671,11 +1663,11 @@ static const unsigned int avb_mii_pins[] = { · 6 unmodified lines
16711663 * AVB_RD1, AVB_RD2, AVB_RD3,
16721664 * AVB_TXCREFCLK
16731665 */
1674− PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1675− PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1676− PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1677− PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1678− PIN_NUMBER('A', 12),
1666+ PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1667+ PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1668+ PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1669+ PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1670+ PIN_AVB_TXCREFCLK,
16791671
16801672 };
16811673 static const unsigned int avb_mii_mux[] = {
@@ -3137,22 +3129,21 @@ static const unsigned int pwm6_b_mux[] = { · 1455 unmodified lines
31373129 /* - QSPI0 ------------------------------------------------------------------ */
31383130 static const unsigned int qspi0_ctrl_pins[] = {
31393131 /* QSPI0_SPCLK, QSPI0_SSL */
3140− PIN_NUMBER('W', 3), PIN_NUMBER('Y', 3),
3132+ PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
31413133 };
31423134 static const unsigned int qspi0_ctrl_mux[] = {
31433135 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
31443136 };
31453137 static const unsigned int qspi0_data2_pins[] = {
31463138 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3147− PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4),
3139+ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
31483140 };
31493141 static const unsigned int qspi0_data2_mux[] = {
31503142 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
31513143 };
31523144 static const unsigned int qspi0_data4_pins[] = {
31533145 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */
3154− PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4),
3155− PIN_NUMBER('Y', 6), PIN_A_NUMBER('B', 6),
3146+ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, PIN_QSPI0_IO2, PIN_QSPI0_IO3,
31563147 };
31573148 static const unsigned int qspi0_data4_mux[] = {
31583149 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
@@ -3161,22 +3152,21 @@ static const unsigned int qspi0_data4_mux[] = { · 2 unmodified lines
31613152 /* - QSPI1 ------------------------------------------------------------------ */
31623153 static const unsigned int qspi1_ctrl_pins[] = {
31633154 /* QSPI1_SPCLK, QSPI1_SSL */
3164− PIN_NUMBER('V', 3), PIN_NUMBER('V', 5),
3155+ PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
31653156 };
31663157 static const unsigned int qspi1_ctrl_mux[] = {
31673158 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
31683159 };
31693160 static const unsigned int qspi1_data2_pins[] = {
31703161 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3171− PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5),
3162+ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
31723163 };
31733164 static const unsigned int qspi1_data2_mux[] = {
31743165 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
31753166 };
31763167 static const unsigned int qspi1_data4_pins[] = {
31773168 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */
3178− PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5),
3179− PIN_A_NUMBER('E', 4), PIN_A_NUMBER('C', 3),
3169+ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, PIN_QSPI1_IO2, PIN_QSPI1_IO3,
31803170 };
31813171 static const unsigned int qspi1_data4_mux[] = {
31823172 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
@@ -3812,6 +3802,36 @@ static const unsigned int tmu_tclk2_b_mux[] = { · 629 unmodified lines
38123802 TCLK2_B_MARK,
38133803 };
38143804
3805+/* - TPU ------------------------------------------------------------------- */
3806+static const unsigned int tpu_to0_pins[] = {
3807+ /* TPU0TO0 */
3808+ RCAR_GP_PIN(6, 28),
3809+};
3810+static const unsigned int tpu_to0_mux[] = {
3811+ TPU0TO0_MARK,
3812+};
3813+static const unsigned int tpu_to1_pins[] = {
3814+ /* TPU0TO1 */
3815+ RCAR_GP_PIN(6, 29),
3816+};
3817+static const unsigned int tpu_to1_mux[] = {
3818+ TPU0TO1_MARK,
3819+};
3820+static const unsigned int tpu_to2_pins[] = {
3821+ /* TPU0TO2 */
3822+ RCAR_GP_PIN(6, 30),
3823+};
3824+static const unsigned int tpu_to2_mux[] = {
3825+ TPU0TO2_MARK,
3826+};
3827+static const unsigned int tpu_to3_pins[] = {
3828+ /* TPU0TO3 */
3829+ RCAR_GP_PIN(6, 31),
3830+};
3831+static const unsigned int tpu_to3_mux[] = {
3832+ TPU0TO3_MARK,
3833+};
3834+
38153835 /* - USB0 ------------------------------------------------------------------- */
38163836 static const unsigned int usb0_pins[] = {
38173837 /* PWEN, OVC */
@@ -4165,6 +4185,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 347 unmodified lines
41654185 SH_PFC_PIN_GROUP(tmu_tclk1_b),
41664186 SH_PFC_PIN_GROUP(tmu_tclk2_a),
41674187 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4188+ SH_PFC_PIN_GROUP(tpu_to0),
4189+ SH_PFC_PIN_GROUP(tpu_to1),
4190+ SH_PFC_PIN_GROUP(tpu_to2),
4191+ SH_PFC_PIN_GROUP(tpu_to3),
41684192 SH_PFC_PIN_GROUP(usb0),
41694193 SH_PFC_PIN_GROUP(usb1),
41704194 SH_PFC_PIN_GROUP(usb2),
@@ -4635,6 +4659,13 @@ static const char * const tmu_groups[] = { · 464 unmodified lines
46354659 "tmu_tclk2_b",
46364660 };
46374661
4662+static const char * const tpu_groups[] = {
4663+ "tpu_to0",
4664+ "tpu_to1",
4665+ "tpu_to2",
4666+ "tpu_to3",
4667+};
4668+
46384669 static const char * const usb0_groups[] = {
46394670 "usb0",
46404671 };
@@ -4707,6 +4738,7 @@ static const struct sh_pfc_function pinmux_functions[] = { · 66 unmodified lines
47074738 SH_PFC_FUNCTION(sdhi3),
47084739 SH_PFC_FUNCTION(ssi),
47094740 SH_PFC_FUNCTION(tmu),
4741+ SH_PFC_FUNCTION(tpu),
47104742 SH_PFC_FUNCTION(usb0),
47114743 SH_PFC_FUNCTION(usb1),
47124744 SH_PFC_FUNCTION(usb2),
@@ -5272,44 +5304,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { · 559 unmodified lines
52725304
52735305 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
52745306 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5275− { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5276− { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5277− { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5278− { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5279− { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5280− { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5281− { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5282− { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5307+ { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
5308+ { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
5309+ { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
5310+ { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
5311+ { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
5312+ { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
5313+ { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
5314+ { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
52835315 } },
52845316 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5285− { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5286− { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5287− { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5288− { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5289− { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5290− { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5291− { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5292− { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5317+ { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
5318+ { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
5319+ { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
5320+ { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
5321+ { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
5322+ { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
5323+ { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
5324+ { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
52935325 } },
52945326 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5295− { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5296− { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5297− { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5298− { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5299− { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5300− { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5301− { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5302− { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5327+ { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
5328+ { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
5329+ { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
5330+ { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
5331+ { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
5332+ { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
5333+ { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
5334+ { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
53035335 } },
53045336 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5305− { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5306− { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5307− { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5308− { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5309− { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5310− { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5311− { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5312− { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5337+ { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
5338+ { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
5339+ { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
5340+ { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
5341+ { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
5342+ { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5343+ { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5344+ { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
53135345 } },
53145346 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
53155347 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
@@ -5352,7 +5384,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { · 36 unmodified lines
53525384 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
53535385 } },
53545386 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5355− { PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */
5387+ { PIN_CLKOUT, 28, 3 }, /* CLKOUT */
53565388 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
53575389 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
53585390 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
@@ -5363,7 +5395,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { · 4 unmodified lines
53635395 } },
53645396 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
53655397 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5366− { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
5398+ { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
53675399 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
53685400 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
53695401 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
@@ -5382,30 +5414,30 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { · 12 unmodified lines
53825414 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
53835415 } },
53845416 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5385− { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5386− { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5387− { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5388− { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5389− { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5390− { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5391− { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5392− { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5417+ { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5418+ { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5419+ { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5420+ { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5421+ { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5422+ { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5423+ { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
5424+ { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
53935425 } },
53945426 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5395− { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
5396− { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
5397− { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
5398− { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
5427+ { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
5428+ { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
5429+ { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */
5430+ { PIN_TMS, 4, 2 }, /* TMS */
53995431 } },
54005432 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5401− { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5402− { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5403− { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5404− { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5405− { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5406− { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5407− { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5408− { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5433+ { PIN_TDO, 28, 2 }, /* TDO */
5434+ { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
5435+ { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5436+ { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5437+ { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5438+ { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5439+ { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5440+ { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
54095441 } },
54105442 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
54115443 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
@@ -5474,7 +5506,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { · 62 unmodified lines
54745506 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
54755507 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
54765508 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5477− { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
5509+ { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
54785510 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
54795511 } },
54805512 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
@@ -5548,35 +5580,35 @@ static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, · 67 unmodified lines
55485580
55495581 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
55505582 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5551− [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
5552− [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
5553− [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
5554− [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
5555− [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
5556− [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
5557− [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
5558− [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
5559− [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
5560− [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
5561− [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
5562− [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
5563− [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
5564− [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
5565− [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
5566− [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
5567− [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
5568− [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
5569− [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
5570− [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
5571− [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
5572− [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
5573− [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
5574− [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
5575− [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
5576− [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
5577− [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
5578− [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
5579− [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
5583+ [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
5584+ [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
5585+ [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
5586+ [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
5587+ [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
5588+ [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
5589+ [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
5590+ [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
5591+ [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
5592+ [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
5593+ [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
5594+ [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
5595+ [12] = PIN_RPC_INT_N, /* RPC_INT# */
5596+ [13] = PIN_RPC_WP_N, /* RPC_WP# */
5597+ [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
5598+ [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
5599+ [16] = PIN_AVB_RXC, /* AVB_RXC */
5600+ [17] = PIN_AVB_RD0, /* AVB_RD0 */
5601+ [18] = PIN_AVB_RD1, /* AVB_RD1 */
5602+ [19] = PIN_AVB_RD2, /* AVB_RD2 */
5603+ [20] = PIN_AVB_RD3, /* AVB_RD3 */
5604+ [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
5605+ [22] = PIN_AVB_TXC, /* AVB_TXC */
5606+ [23] = PIN_AVB_TD0, /* AVB_TD0 */
5607+ [24] = PIN_AVB_TD1, /* AVB_TD1 */
5608+ [25] = PIN_AVB_TD2, /* AVB_TD2 */
5609+ [26] = PIN_AVB_TD3, /* AVB_TD3 */
5610+ [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
5611+ [28] = PIN_AVB_MDIO, /* AVB_MDIO */
55805612 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
55815613 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
55825614 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
@@ -5616,7 +5648,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 33 unmodified lines
56165648 [31] = RCAR_GP_PIN(1, 19), /* A19 */
56175649 } },
56185650 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5619− [ 0] = PIN_NUMBER('F', 1), /* CLKOUT */
5651+ [ 0] = PIN_CLKOUT, /* CLKOUT */
56205652 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
56215653 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N_A26 */
56225654 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
@@ -5625,7 +5657,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 2 unmodified lines
56255657 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
56265658 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
56275659 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5628− [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
5660+ [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
56295661 [10] = RCAR_GP_PIN(0, 0), /* D0 */
56305662 [11] = RCAR_GP_PIN(0, 1), /* D1 */
56315663 [12] = RCAR_GP_PIN(0, 2), /* D2 */
@@ -5646,20 +5678,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 14 unmodified lines
56465678 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
56475679 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
56485680 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
5649− [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
5650− [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
5681+ [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
5682+ [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
56515683 } },
56525684 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5653− [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */
5654− [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
5655− [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */
5656− [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
5657− [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
5658− [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
5659− [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
5660− [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
5661− [ 8] = PIN_NONE,
5662− [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
5685+ [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
5686+ [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
5687+ [ 2] = PIN_FSCLKST_N, /* FSCLKST# */
5688+ [ 3] = PIN_EXTALR, /* EXTALR*/
5689+ [ 4] = PIN_TRST_N, /* TRST# */
5690+ [ 5] = PIN_TCK, /* TCK */
5691+ [ 6] = PIN_TMS, /* TMS */
5692+ [ 7] = PIN_TDI, /* TDI */
5693+ [ 8] = SH_PFC_PIN_NONE,
5694+ [ 9] = PIN_ASEBRK, /* ASEBRK */
56635695 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
56645696 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
56655697 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
@@ -5724,7 +5756,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 58 unmodified lines
57245756 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
57255757 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
57265758 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
5727− [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
5759+ [ 6] = PIN_MLB_REF, /* MLB_REF */
57285760 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
57295761 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
57305762 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
@@ -5759,31 +5791,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 28 unmodified lines
57595791 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
57605792 [ 5] = RCAR_GP_PIN(6, 30), /* USB31_PWEN */
57615793 [ 6] = RCAR_GP_PIN(6, 31), /* USB31_OVC */
5762− [ 7] = PIN_NONE,
5763− [ 8] = PIN_NONE,
5764− [ 9] = PIN_NONE,
5765− [10] = PIN_NONE,
5766− [11] = PIN_NONE,
5767− [12] = PIN_NONE,
5768− [13] = PIN_NONE,
5769− [14] = PIN_NONE,
5770− [15] = PIN_NONE,
5771− [16] = PIN_NONE,
5772− [17] = PIN_NONE,
5773− [18] = PIN_NONE,
5774− [19] = PIN_NONE,
5775− [20] = PIN_NONE,
5776− [21] = PIN_NONE,
5777− [22] = PIN_NONE,
5778− [23] = PIN_NONE,
5779− [24] = PIN_NONE,
5780− [25] = PIN_NONE,
5781− [26] = PIN_NONE,
5782− [27] = PIN_NONE,
5783− [28] = PIN_NONE,
5784− [29] = PIN_NONE,
5785− [30] = PIN_NONE,
5786− [31] = PIN_NONE,
5794+ [ 7] = SH_PFC_PIN_NONE,
5795+ [ 8] = SH_PFC_PIN_NONE,
5796+ [ 9] = SH_PFC_PIN_NONE,
5797+ [10] = SH_PFC_PIN_NONE,
5798+ [11] = SH_PFC_PIN_NONE,
5799+ [12] = SH_PFC_PIN_NONE,
5800+ [13] = SH_PFC_PIN_NONE,
5801+ [14] = SH_PFC_PIN_NONE,
5802+ [15] = SH_PFC_PIN_NONE,
5803+ [16] = SH_PFC_PIN_NONE,
5804+ [17] = SH_PFC_PIN_NONE,
5805+ [18] = SH_PFC_PIN_NONE,
5806+ [19] = SH_PFC_PIN_NONE,
5807+ [20] = SH_PFC_PIN_NONE,
5808+ [21] = SH_PFC_PIN_NONE,
5809+ [22] = SH_PFC_PIN_NONE,
5810+ [23] = SH_PFC_PIN_NONE,
5811+ [24] = SH_PFC_PIN_NONE,
5812+ [25] = SH_PFC_PIN_NONE,
5813+ [26] = SH_PFC_PIN_NONE,
5814+ [27] = SH_PFC_PIN_NONE,
5815+ [28] = SH_PFC_PIN_NONE,
5816+ [29] = SH_PFC_PIN_NONE,
5817+ [30] = SH_PFC_PIN_NONE,
5818+ [31] = SH_PFC_PIN_NONE,
57875819 } },
57885820 { /* sentinel */ },
57895821 };
drivers/pinctrl/sh-pfc/pfc-r8a7795.c+224−190
@@ -12,11 +12,9 @@ · 11 unmodified lines
1212 #include "core.h"
1313 #include "sh_pfc.h"
1414
15−#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
16− SH_PFC_PIN_CFG_PULL_UP | \
17− SH_PFC_PIN_CFG_PULL_DOWN)
15+#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
1816
19−#define CPU_ALL_PORT(fn, sfx) \
17+#define CPU_ALL_GP(fn, sfx) \
2018 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
2119 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
2220 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
@@ -29,6 +27,52 @@ · 6 unmodified lines
2927 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
3028 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
3129 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
30+
31+#define CPU_ALL_NOGP(fn) \
32+ PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
33+ PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
34+ PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
35+ PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
36+ PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
37+ PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
38+ PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
39+ PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
40+ PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
41+ PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
42+ PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
43+ PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
44+ PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
45+ PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
46+ PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
47+ PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
48+ PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
49+ PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
50+ PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
51+ PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
52+ PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \
53+ PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
54+ PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
55+ PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
56+ PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
57+ PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
58+ PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
59+ PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
60+ PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
61+ PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
62+ PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
63+ PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
64+ PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
65+ PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
66+ PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
67+ PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
68+ PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
69+ PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
70+ PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
71+ PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
72+ PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
73+ PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
74+ PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
75+
3276 /*
3377 * F_() : just information
3478 * FM() : macro for FN_xxx / xxx_MARK
@@ -1508,68 +1552,16 @@ static const u16 pinmux_data[] = { · 1473 unmodified lines
15081552 };
15091553
15101554 /*
1511− * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1512− * Physical layout rows: A - AW, cols: 1 - 39.
1555+ * Pins not associated with a GPIO port.
15131556 */
1514−#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1515−#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1516−#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1517−#define PIN_NONE U16_MAX
1557+enum {
1558+ GP_ASSIGN_LAST(),
1559+ NOGP_ALL(),
1560+};
15181561
15191562 static const struct sh_pfc_pin pinmux_pins[] = {
15201563 PINMUX_GPIO_GP_ALL(),
1521−
1522− /*
1523− * Pins not associated with a GPIO port.
1524− *
1525− * The pin positions are different between different r8a7795
1526− * packages, all that is needed for the pfc driver is a unique
1527− * number for each pin. To this end use the pin layout from
1528− * R-Car H3SiP to calculate a unique number for each pin.
1529− */
1530− SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1531− SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1532− SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1533− SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1534− SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1535− SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1536− SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1537− SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1538− SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1539− SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1540− SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1541− SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1542− SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1543− SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1544− SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1545− SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1546− SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1547− SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1548− SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1549− SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1550− SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1551− SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1552− SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1553− SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1554− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1555− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1556− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1557− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1558− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1559− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1560− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1561− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1562− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1563− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1564− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1565− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
1566− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1567− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1568− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1569− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1570− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1572− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1564+ PINMUX_NOGP_ALL(),
15731565 };
15741566
15751567 /* - AUDIO CLOCK ------------------------------------------------------------ */
@@ -1717,7 +1709,7 @@ static const unsigned int avb_phy_int_mux[] = { · 141 unmodified lines
17171709 };
17181710 static const unsigned int avb_mdio_pins[] = {
17191711 /* AVB_MDC, AVB_MDIO */
1720− RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1712+ RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
17211713 };
17221714 static const unsigned int avb_mdio_mux[] = {
17231715 AVB_MDC_MARK, AVB_MDIO_MARK,
@@ -1730,11 +1722,11 @@ static const unsigned int avb_mii_pins[] = { · 6 unmodified lines
17301722 * AVB_RD1, AVB_RD2, AVB_RD3,
17311723 * AVB_TXCREFCLK
17321724 */
1733− PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1734− PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1735− PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1736− PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1737− PIN_NUMBER('A', 12),
1725+ PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1726+ PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1727+ PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1728+ PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1729+ PIN_AVB_TXCREFCLK,
17381730
17391731 };
17401732 static const unsigned int avb_mii_mux[] = {
@@ -3901,6 +3893,36 @@ static const unsigned int tmu_tclk2_b_mux[] = { · 2160 unmodified lines
39013893 TCLK2_B_MARK,
39023894 };
39033895
3896+/* - TPU ------------------------------------------------------------------- */
3897+static const unsigned int tpu_to0_pins[] = {
3898+ /* TPU0TO0 */
3899+ RCAR_GP_PIN(6, 28),
3900+};
3901+static const unsigned int tpu_to0_mux[] = {
3902+ TPU0TO0_MARK,
3903+};
3904+static const unsigned int tpu_to1_pins[] = {
3905+ /* TPU0TO1 */
3906+ RCAR_GP_PIN(6, 29),
3907+};
3908+static const unsigned int tpu_to1_mux[] = {
3909+ TPU0TO1_MARK,
3910+};
3911+static const unsigned int tpu_to2_pins[] = {
3912+ /* TPU0TO2 */
3913+ RCAR_GP_PIN(6, 30),
3914+};
3915+static const unsigned int tpu_to2_mux[] = {
3916+ TPU0TO2_MARK,
3917+};
3918+static const unsigned int tpu_to3_pins[] = {
3919+ /* TPU0TO3 */
3920+ RCAR_GP_PIN(6, 31),
3921+};
3922+static const unsigned int tpu_to3_mux[] = {
3923+ TPU0TO3_MARK,
3924+};
3925+
39043926 /* - USB0 ------------------------------------------------------------------- */
39053927 static const unsigned int usb0_pins[] = {
39063928 /* PWEN, OVC */
@@ -4451,6 +4473,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 544 unmodified lines
44514473 SH_PFC_PIN_GROUP(tmu_tclk1_b),
44524474 SH_PFC_PIN_GROUP(tmu_tclk2_a),
44534475 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4476+ SH_PFC_PIN_GROUP(tpu_to0),
4477+ SH_PFC_PIN_GROUP(tpu_to1),
4478+ SH_PFC_PIN_GROUP(tpu_to2),
4479+ SH_PFC_PIN_GROUP(tpu_to3),
44544480 SH_PFC_PIN_GROUP(usb0),
44554481 SH_PFC_PIN_GROUP(usb1),
44564482 SH_PFC_PIN_GROUP(usb2),
@@ -4946,6 +4972,13 @@ static const char * const tmu_groups[] = { · 489 unmodified lines
49464972 "tmu_tclk2_b",
49474973 };
49484974
4975+static const char * const tpu_groups[] = {
4976+ "tpu_to0",
4977+ "tpu_to1",
4978+ "tpu_to2",
4979+ "tpu_to3",
4980+};
4981+
49494982 static const char * const usb0_groups[] = {
49504983 "usb0",
49514984 };
@@ -5048,6 +5081,7 @@ static const struct sh_pfc_function pinmux_functions[] = { · 96 unmodified lines
50485081 SH_PFC_FUNCTION(sdhi3),
50495082 SH_PFC_FUNCTION(ssi),
50505083 SH_PFC_FUNCTION(tmu),
5084+ SH_PFC_FUNCTION(tpu),
50515085 SH_PFC_FUNCTION(usb0),
50525086 SH_PFC_FUNCTION(usb1),
50535087 SH_PFC_FUNCTION(usb2),
@@ -5623,44 +5657,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { · 569 unmodified lines
56235657
56245658 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
56255659 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5626− { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5627− { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5628− { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5629− { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5630− { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5631− { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5632− { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5633− { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5660+ { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
5661+ { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
5662+ { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
5663+ { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
5664+ { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
5665+ { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
5666+ { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
5667+ { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
56345668 } },
56355669 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5636− { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5637− { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5638− { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5639− { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5640− { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5641− { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5642− { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5643− { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5670+ { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
5671+ { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
5672+ { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
5673+ { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
5674+ { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
5675+ { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
5676+ { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
5677+ { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
56445678 } },
56455679 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5646− { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5647− { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5648− { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5649− { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5650− { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5651− { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5652− { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5653− { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5680+ { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
5681+ { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
5682+ { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
5683+ { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
5684+ { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
5685+ { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
5686+ { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
5687+ { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
56545688 } },
56555689 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5656− { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5657− { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5658− { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5659− { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5660− { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5661− { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5662− { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5663− { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5690+ { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
5691+ { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
5692+ { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
5693+ { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
5694+ { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
5695+ { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5696+ { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5697+ { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
56645698 } },
56655699 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
56665700 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
@@ -5714,7 +5748,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { · 47 unmodified lines
57145748 } },
57155749 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
57165750 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5717− { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
5751+ { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
57185752 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
57195753 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
57205754 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
@@ -5733,30 +5767,30 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { · 12 unmodified lines
57335767 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
57345768 } },
57355769 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5736− { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5737− { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5738− { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5739− { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5740− { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5741− { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5742− { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5743− { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5770+ { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5771+ { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5772+ { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5773+ { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5774+ { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5775+ { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5776+ { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
5777+ { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
57445778 } },
57455779 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5746− { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
5747− { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
5748− { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
5749− { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
5780+ { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
5781+ { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
5782+ { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */
5783+ { PIN_TMS, 4, 2 }, /* TMS */
57505784 } },
57515785 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5752− { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5753− { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5754− { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5755− { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5756− { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5757− { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5758− { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5759− { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5786+ { PIN_TDO, 28, 2 }, /* TDO */
5787+ { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
5788+ { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5789+ { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5790+ { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5791+ { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5792+ { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5793+ { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
57605794 } },
57615795 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
57625796 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
@@ -5825,7 +5859,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { · 62 unmodified lines
58255859 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
58265860 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
58275861 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5828− { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
5862+ { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
58295863 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
58305864 } },
58315865 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
@@ -5898,35 +5932,35 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc · 66 unmodified lines
58985932
58995933 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
59005934 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5901− [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
5902− [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
5903− [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
5904− [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
5905− [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
5906− [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
5907− [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
5908− [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
5909− [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
5910− [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
5911− [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
5912− [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
5913− [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
5914− [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
5915− [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
5916− [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
5917− [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
5918− [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
5919− [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
5920− [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
5921− [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
5922− [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
5923− [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
5924− [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
5925− [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
5926− [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
5927− [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
5928− [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
5929− [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
5935+ [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
5936+ [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
5937+ [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
5938+ [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
5939+ [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
5940+ [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
5941+ [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
5942+ [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
5943+ [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
5944+ [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
5945+ [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
5946+ [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
5947+ [12] = PIN_RPC_INT_N, /* RPC_INT# */
5948+ [13] = PIN_RPC_WP_N, /* RPC_WP# */
5949+ [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
5950+ [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
5951+ [16] = PIN_AVB_RXC, /* AVB_RXC */
5952+ [17] = PIN_AVB_RD0, /* AVB_RD0 */
5953+ [18] = PIN_AVB_RD1, /* AVB_RD1 */
5954+ [19] = PIN_AVB_RD2, /* AVB_RD2 */
5955+ [20] = PIN_AVB_RD3, /* AVB_RD3 */
5956+ [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
5957+ [22] = PIN_AVB_TXC, /* AVB_TXC */
5958+ [23] = PIN_AVB_TD0, /* AVB_TD0 */
5959+ [24] = PIN_AVB_TD1, /* AVB_TD1 */
5960+ [25] = PIN_AVB_TD2, /* AVB_TD2 */
5961+ [26] = PIN_AVB_TD3, /* AVB_TD3 */
5962+ [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
5963+ [28] = PIN_AVB_MDIO, /* AVB_MDIO */
59305964 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
59315965 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
59325966 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
@@ -5975,7 +6009,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 42 unmodified lines
59756009 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
59766010 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
59776011 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5978− [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
6012+ [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
59796013 [10] = RCAR_GP_PIN(0, 0), /* D0 */
59806014 [11] = RCAR_GP_PIN(0, 1), /* D1 */
59816015 [12] = RCAR_GP_PIN(0, 2), /* D2 */
@@ -5996,20 +6030,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 14 unmodified lines
59966030 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
59976031 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
59986032 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
5999− [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
6000− [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
6033+ [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
6034+ [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
60016035 } },
60026036 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6003− [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */
6004− [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
6005− [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */
6006− [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
6007− [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
6008− [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
6009− [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
6010− [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
6011− [ 8] = PIN_NONE,
6012− [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
6037+ [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
6038+ [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
6039+ [ 2] = PIN_FSCLKST_N, /* FSCLKST# */
6040+ [ 3] = PIN_EXTALR, /* EXTALR*/
6041+ [ 4] = PIN_TRST_N, /* TRST# */
6042+ [ 5] = PIN_TCK, /* TCK */
6043+ [ 6] = PIN_TMS, /* TMS */
6044+ [ 7] = PIN_TDI, /* TDI */
6045+ [ 8] = SH_PFC_PIN_NONE,
6046+ [ 9] = PIN_ASEBRK, /* ASEBRK */
60136047 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
60146048 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
60156049 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
@@ -6074,7 +6108,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 58 unmodified lines
60746108 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
60756109 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
60766110 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
6077− [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
6111+ [ 6] = PIN_MLB_REF, /* MLB_REF */
60786112 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
60796113 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
60806114 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
@@ -6109,31 +6143,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 28 unmodified lines
61096143 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
61106144 [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
61116145 [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
6112− [ 7] = PIN_NONE,
6113− [ 8] = PIN_NONE,
6114− [ 9] = PIN_NONE,
6115− [10] = PIN_NONE,
6116− [11] = PIN_NONE,
6117− [12] = PIN_NONE,
6118− [13] = PIN_NONE,
6119− [14] = PIN_NONE,
6120− [15] = PIN_NONE,
6121− [16] = PIN_NONE,
6122− [17] = PIN_NONE,
6123− [18] = PIN_NONE,
6124− [19] = PIN_NONE,
6125− [20] = PIN_NONE,
6126− [21] = PIN_NONE,
6127− [22] = PIN_NONE,
6128− [23] = PIN_NONE,
6129− [24] = PIN_NONE,
6130− [25] = PIN_NONE,
6131− [26] = PIN_NONE,
6132− [27] = PIN_NONE,
6133− [28] = PIN_NONE,
6134− [29] = PIN_NONE,
6135− [30] = PIN_NONE,
6136− [31] = PIN_NONE,
6146+ [ 7] = SH_PFC_PIN_NONE,
6147+ [ 8] = SH_PFC_PIN_NONE,
6148+ [ 9] = SH_PFC_PIN_NONE,
6149+ [10] = SH_PFC_PIN_NONE,
6150+ [11] = SH_PFC_PIN_NONE,
6151+ [12] = SH_PFC_PIN_NONE,
6152+ [13] = SH_PFC_PIN_NONE,
6153+ [14] = SH_PFC_PIN_NONE,
6154+ [15] = SH_PFC_PIN_NONE,
6155+ [16] = SH_PFC_PIN_NONE,
6156+ [17] = SH_PFC_PIN_NONE,
6157+ [18] = SH_PFC_PIN_NONE,
6158+ [19] = SH_PFC_PIN_NONE,
6159+ [20] = SH_PFC_PIN_NONE,
6160+ [21] = SH_PFC_PIN_NONE,
6161+ [22] = SH_PFC_PIN_NONE,
6162+ [23] = SH_PFC_PIN_NONE,
6163+ [24] = SH_PFC_PIN_NONE,
6164+ [25] = SH_PFC_PIN_NONE,
6165+ [26] = SH_PFC_PIN_NONE,
6166+ [27] = SH_PFC_PIN_NONE,
6167+ [28] = SH_PFC_PIN_NONE,
6168+ [29] = SH_PFC_PIN_NONE,
6169+ [30] = SH_PFC_PIN_NONE,
6170+ [31] = SH_PFC_PIN_NONE,
61376171 } },
61386172 { /* sentinel */ },
61396173 };
drivers/pinctrl/sh-pfc/pfc-r8a7796.c+224−190
@@ -17,11 +17,9 @@ · 16 unmodified lines
1717 #include "core.h"
1818 #include "sh_pfc.h"
1919
20−#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
21− SH_PFC_PIN_CFG_PULL_UP | \
22− SH_PFC_PIN_CFG_PULL_DOWN)
20+#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
2321
24−#define CPU_ALL_PORT(fn, sfx) \
22+#define CPU_ALL_GP(fn, sfx) \
2523 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
2624 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
2725 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
@@ -34,6 +32,51 @@ · 6 unmodified lines
3432 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
3533 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
3634 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
35+
36+#define CPU_ALL_NOGP(fn) \
37+ PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
38+ PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
39+ PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
40+ PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
41+ PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
42+ PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
43+ PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
44+ PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
45+ PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
46+ PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
47+ PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
48+ PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
49+ PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
50+ PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
51+ PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
52+ PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
53+ PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
54+ PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
55+ PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
56+ PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
57+ PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
58+ PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
59+ PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
60+ PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
61+ PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
62+ PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
63+ PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
64+ PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
65+ PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
66+ PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
67+ PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
68+ PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
69+ PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
70+ PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
71+ PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
72+ PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
73+ PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
74+ PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
75+ PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
76+ PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
77+ PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
78+ PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
79+
3780 /*
3881 * F_() : just information
3982 * FM() : macro for FN_xxx / xxx_MARK
@@ -1512,67 +1555,16 @@ static const u16 pinmux_data[] = { · 1472 unmodified lines
15121555 };
15131556
15141557 /*
1515− * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1516− * Physical layout rows: A - AW, cols: 1 - 39.
1558+ * Pins not associated with a GPIO port.
15171559 */
1518−#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1519−#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1520−#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1521−#define PIN_NONE U16_MAX
1560+enum {
1561+ GP_ASSIGN_LAST(),
1562+ NOGP_ALL(),
1563+};
15221564
15231565 static const struct sh_pfc_pin pinmux_pins[] = {
15241566 PINMUX_GPIO_GP_ALL(),
1525−
1526− /*
1527− * Pins not associated with a GPIO port.
1528− *
1529− * The pin positions are different between different r8a7796
1530− * packages, all that is needed for the pfc driver is a unique
1531− * number for each pin. To this end use the pin layout from
1532− * R-Car M3SiP to calculate a unique number for each pin.
1533− */
1534− SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1535− SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1536− SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1537− SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1538− SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1539− SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1540− SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1541− SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1542− SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1543− SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1544− SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1545− SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1546− SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1547− SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1548− SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1549− SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1550− SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1551− SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1552− SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1553− SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1554− SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1555− SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1556− SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1557− SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1558− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1559− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1560− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1561− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1562− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1563− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1564− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1565− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1566− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1567− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1568− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1569− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS),
1570− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1573− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1574− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1575− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1567+ PINMUX_NOGP_ALL(),
15761568 };
15771569
15781570 /* - AUDIO CLOCK ------------------------------------------------------------ */
@@ -1721,7 +1713,7 @@ static const unsigned int avb_phy_int_mux[] = { · 142 unmodified lines
17211713 };
17221714 static const unsigned int avb_mdio_pins[] = {
17231715 /* AVB_MDC, AVB_MDIO */
1724− RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1716+ RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
17251717 };
17261718 static const unsigned int avb_mdio_mux[] = {
17271719 AVB_MDC_MARK, AVB_MDIO_MARK,
@@ -1734,11 +1726,11 @@ static const unsigned int avb_mii_pins[] = { · 6 unmodified lines
17341726 * AVB_RD1, AVB_RD2, AVB_RD3,
17351727 * AVB_TXCREFCLK
17361728 */
1737− PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1738− PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1739− PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1740− PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1741− PIN_NUMBER('A', 12),
1729+ PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1730+ PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1731+ PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1732+ PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1733+ PIN_AVB_TXCREFCLK,
17421734
17431735 };
17441736 static const unsigned int avb_mii_mux[] = {
@@ -3891,6 +3883,36 @@ static const unsigned int tmu_tclk2_b_mux[] = { · 2146 unmodified lines
38913883 TCLK2_B_MARK,
38923884 };
38933885
3886+/* - TPU ------------------------------------------------------------------- */
3887+static const unsigned int tpu_to0_pins[] = {
3888+ /* TPU0TO0 */
3889+ RCAR_GP_PIN(6, 28),
3890+};
3891+static const unsigned int tpu_to0_mux[] = {
3892+ TPU0TO0_MARK,
3893+};
3894+static const unsigned int tpu_to1_pins[] = {
3895+ /* TPU0TO1 */
3896+ RCAR_GP_PIN(6, 29),
3897+};
3898+static const unsigned int tpu_to1_mux[] = {
3899+ TPU0TO1_MARK,
3900+};
3901+static const unsigned int tpu_to2_pins[] = {
3902+ /* TPU0TO2 */
3903+ RCAR_GP_PIN(6, 30),
3904+};
3905+static const unsigned int tpu_to2_mux[] = {
3906+ TPU0TO2_MARK,
3907+};
3908+static const unsigned int tpu_to3_pins[] = {
3909+ /* TPU0TO3 */
3910+ RCAR_GP_PIN(6, 31),
3911+};
3912+static const unsigned int tpu_to3_mux[] = {
3913+ TPU0TO3_MARK,
3914+};
3915+
38943916 /* - USB0 ------------------------------------------------------------------- */
38953917 static const unsigned int usb0_pins[] = {
38963918 /* PWEN, OVC */
@@ -4110,7 +4132,7 @@ static const unsigned int vin5_clk_mux[] = { · 213 unmodified lines
41104132 };
41114133
41124134 static const struct {
4113− struct sh_pfc_pin_group common[312];
4135+ struct sh_pfc_pin_group common[316];
41144136 struct sh_pfc_pin_group automotive[30];
41154137 } pinmux_groups = {
41164138 .common = {
@@ -4397,6 +4419,10 @@ static const struct { · 280 unmodified lines
43974419 SH_PFC_PIN_GROUP(tmu_tclk1_b),
43984420 SH_PFC_PIN_GROUP(tmu_tclk2_a),
43994421 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4422+ SH_PFC_PIN_GROUP(tpu_to0),
4423+ SH_PFC_PIN_GROUP(tpu_to1),
4424+ SH_PFC_PIN_GROUP(tpu_to2),
4425+ SH_PFC_PIN_GROUP(tpu_to3),
44004426 SH_PFC_PIN_GROUP(usb0),
44014427 SH_PFC_PIN_GROUP(usb1),
44024428 SH_PFC_PIN_GROUP(usb30),
@@ -4918,6 +4944,13 @@ static const char * const tmu_groups[] = { · 515 unmodified lines
49184944 "tmu_tclk2_b",
49194945 };
49204946
4947+static const char * const tpu_groups[] = {
4948+ "tpu_to0",
4949+ "tpu_to1",
4950+ "tpu_to2",
4951+ "tpu_to3",
4952+};
4953+
49214954 static const char * const usb0_groups[] = {
49224955 "usb0",
49234956 };
@@ -4963,7 +4996,7 @@ static const char * const vin5_groups[] = { · 39 unmodified lines
49634996 };
49644997
49654998 static const struct {
4966− struct sh_pfc_function common[49];
4999+ struct sh_pfc_function common[50];
49675000 struct sh_pfc_function automotive[4];
49685001 } pinmux_functions = {
49695002 .common = {
@@ -5011,6 +5044,7 @@ static const struct { · 41 unmodified lines
50115044 SH_PFC_FUNCTION(sdhi3),
50125045 SH_PFC_FUNCTION(ssi),
50135046 SH_PFC_FUNCTION(tmu),
5047+ SH_PFC_FUNCTION(tpu),
50145048 SH_PFC_FUNCTION(usb0),
50155049 SH_PFC_FUNCTION(usb1),
50165050 SH_PFC_FUNCTION(usb30),
@@ -5590,44 +5624,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { · 573 unmodified lines
55905624
55915625 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
55925626 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5593− { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5594− { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5595− { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5596− { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5597− { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5598− { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5599− { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5600− { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5627+ { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
5628+ { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
5629+ { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
5630+ { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
5631+ { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
5632+ { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
5633+ { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
5634+ { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
56015635 } },
56025636 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5603− { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5604− { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5605− { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5606− { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5607− { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5608− { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5609− { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5610− { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5637+ { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
5638+ { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
5639+ { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
5640+ { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
5641+ { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
5642+ { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
5643+ { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
5644+ { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
56115645 } },
56125646 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5613− { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5614− { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5615− { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5616− { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5617− { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5618− { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5619− { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5620− { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5647+ { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
5648+ { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
5649+ { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
5650+ { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
5651+ { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
5652+ { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
5653+ { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
5654+ { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
56215655 } },
56225656 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5623− { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5624− { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5625− { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5626− { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5627− { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5628− { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5629− { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5630− { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5657+ { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
5658+ { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
5659+ { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
5660+ { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
5661+ { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
5662+ { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5663+ { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5664+ { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
56315665 } },
56325666 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
56335667 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
@@ -5681,7 +5715,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { · 47 unmodified lines
56815715 } },
56825716 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
56835717 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5684− { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
5718+ { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
56855719 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
56865720 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
56875721 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
@@ -5700,29 +5734,29 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { · 12 unmodified lines
57005734 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
57015735 } },
57025736 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5703− { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5704− { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5705− { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5706− { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5707− { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5708− { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5709− { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5710− { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5737+ { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5738+ { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5739+ { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5740+ { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5741+ { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5742+ { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5743+ { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
5744+ { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
57115745 } },
57125746 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5713− { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN2 */
5714− { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
5715− { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
5747+ { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
5748+ { PIN_FSCLKST, 20, 2 }, /* FSCLKST */
5749+ { PIN_TMS, 4, 2 }, /* TMS */
57165750 } },
57175751 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5718− { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5719− { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5720− { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5721− { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5722− { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5723− { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5724− { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5725− { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5752+ { PIN_TDO, 28, 2 }, /* TDO */
5753+ { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
5754+ { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5755+ { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5756+ { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5757+ { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5758+ { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5759+ { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
57265760 } },
57275761 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
57285762 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
@@ -5791,7 +5825,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { · 62 unmodified lines
57915825 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
57925826 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
57935827 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5794− { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
5828+ { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
57955829 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
57965830 } },
57975831 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
@@ -5864,35 +5898,35 @@ static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc · 66 unmodified lines
58645898
58655899 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
58665900 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5867− [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
5868− [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
5869− [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
5870− [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
5871− [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
5872− [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
5873− [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
5874− [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
5875− [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
5876− [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
5877− [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
5878− [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
5879− [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
5880− [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
5881− [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
5882− [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
5883− [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
5884− [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
5885− [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
5886− [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
5887− [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
5888− [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
5889− [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
5890− [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
5891− [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
5892− [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
5893− [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
5894− [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
5895− [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
5901+ [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
5902+ [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
5903+ [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
5904+ [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
5905+ [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
5906+ [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
5907+ [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
5908+ [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
5909+ [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
5910+ [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
5911+ [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
5912+ [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
5913+ [12] = PIN_RPC_INT_N, /* RPC_INT# */
5914+ [13] = PIN_RPC_WP_N, /* RPC_WP# */
5915+ [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
5916+ [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
5917+ [16] = PIN_AVB_RXC, /* AVB_RXC */
5918+ [17] = PIN_AVB_RD0, /* AVB_RD0 */
5919+ [18] = PIN_AVB_RD1, /* AVB_RD1 */
5920+ [19] = PIN_AVB_RD2, /* AVB_RD2 */
5921+ [20] = PIN_AVB_RD3, /* AVB_RD3 */
5922+ [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
5923+ [22] = PIN_AVB_TXC, /* AVB_TXC */
5924+ [23] = PIN_AVB_TD0, /* AVB_TD0 */
5925+ [24] = PIN_AVB_TD1, /* AVB_TD1 */
5926+ [25] = PIN_AVB_TD2, /* AVB_TD2 */
5927+ [26] = PIN_AVB_TD3, /* AVB_TD3 */
5928+ [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
5929+ [28] = PIN_AVB_MDIO, /* AVB_MDIO */
58965930 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
58975931 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
58985932 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
@@ -5941,7 +5975,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 42 unmodified lines
59415975 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
59425976 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
59435977 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5944− [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
5978+ [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
59455979 [10] = RCAR_GP_PIN(0, 0), /* D0 */
59465980 [11] = RCAR_GP_PIN(0, 1), /* D1 */
59475981 [12] = RCAR_GP_PIN(0, 2), /* D2 */
@@ -5962,20 +5996,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 14 unmodified lines
59625996 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
59635997 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
59645998 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
5965− [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
5966− [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
5999+ [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
6000+ [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
59676001 } },
59686002 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5969− [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */
5970− [ 1] = PIN_NONE,
5971− [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
5972− [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
5973− [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
5974− [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
5975− [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
5976− [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
5977− [ 8] = PIN_NONE,
5978− [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
6003+ [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
6004+ [ 1] = SH_PFC_PIN_NONE,
6005+ [ 2] = PIN_FSCLKST, /* FSCLKST */
6006+ [ 3] = PIN_EXTALR, /* EXTALR*/
6007+ [ 4] = PIN_TRST_N, /* TRST# */
6008+ [ 5] = PIN_TCK, /* TCK */
6009+ [ 6] = PIN_TMS, /* TMS */
6010+ [ 7] = PIN_TDI, /* TDI */
6011+ [ 8] = SH_PFC_PIN_NONE,
6012+ [ 9] = PIN_ASEBRK, /* ASEBRK */
59796013 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
59806014 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
59816015 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
@@ -6040,7 +6074,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 58 unmodified lines
60406074 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
60416075 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
60426076 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
6043− [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
6077+ [ 6] = PIN_MLB_REF, /* MLB_REF */
60446078 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
60456079 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
60466080 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
@@ -6075,31 +6109,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 28 unmodified lines
60756109 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
60766110 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
60776111 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
6078− [ 7] = PIN_NONE,
6079− [ 8] = PIN_NONE,
6080− [ 9] = PIN_NONE,
6081− [10] = PIN_NONE,
6082− [11] = PIN_NONE,
6083− [12] = PIN_NONE,
6084− [13] = PIN_NONE,
6085− [14] = PIN_NONE,
6086− [15] = PIN_NONE,
6087− [16] = PIN_NONE,
6088− [17] = PIN_NONE,
6089− [18] = PIN_NONE,
6090− [19] = PIN_NONE,
6091− [20] = PIN_NONE,
6092− [21] = PIN_NONE,
6093− [22] = PIN_NONE,
6094− [23] = PIN_NONE,
6095− [24] = PIN_NONE,
6096− [25] = PIN_NONE,
6097− [26] = PIN_NONE,
6098− [27] = PIN_NONE,
6099− [28] = PIN_NONE,
6100− [29] = PIN_NONE,
6101− [30] = PIN_NONE,
6102− [31] = PIN_NONE,
6112+ [ 7] = SH_PFC_PIN_NONE,
6113+ [ 8] = SH_PFC_PIN_NONE,
6114+ [ 9] = SH_PFC_PIN_NONE,
6115+ [10] = SH_PFC_PIN_NONE,
6116+ [11] = SH_PFC_PIN_NONE,
6117+ [12] = SH_PFC_PIN_NONE,
6118+ [13] = SH_PFC_PIN_NONE,
6119+ [14] = SH_PFC_PIN_NONE,
6120+ [15] = SH_PFC_PIN_NONE,
6121+ [16] = SH_PFC_PIN_NONE,
6122+ [17] = SH_PFC_PIN_NONE,
6123+ [18] = SH_PFC_PIN_NONE,
6124+ [19] = SH_PFC_PIN_NONE,
6125+ [20] = SH_PFC_PIN_NONE,
6126+ [21] = SH_PFC_PIN_NONE,
6127+ [22] = SH_PFC_PIN_NONE,
6128+ [23] = SH_PFC_PIN_NONE,
6129+ [24] = SH_PFC_PIN_NONE,
6130+ [25] = SH_PFC_PIN_NONE,
6131+ [26] = SH_PFC_PIN_NONE,
6132+ [27] = SH_PFC_PIN_NONE,
6133+ [28] = SH_PFC_PIN_NONE,
6134+ [29] = SH_PFC_PIN_NONE,
6135+ [30] = SH_PFC_PIN_NONE,
6136+ [31] = SH_PFC_PIN_NONE,
61036137 } },
61046138 { /* sentinel */ },
61056139 };
drivers/pinctrl/sh-pfc/pfc-r8a77965.c+222−188
@@ -18,11 +18,9 @@ · 17 unmodified lines
1818 #include "core.h"
1919 #include "sh_pfc.h"
2020
21−#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
22− SH_PFC_PIN_CFG_PULL_UP | \
23− SH_PFC_PIN_CFG_PULL_DOWN)
21+#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
2422
25−#define CPU_ALL_PORT(fn, sfx) \
23+#define CPU_ALL_GP(fn, sfx) \
2624 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
2725 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
2826 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
@@ -35,6 +33,51 @@ · 6 unmodified lines
3533 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
3634 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
3735 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
36+
37+#define CPU_ALL_NOGP(fn) \
38+ PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
39+ PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
40+ PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
41+ PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
42+ PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
43+ PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
44+ PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
45+ PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
46+ PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
47+ PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
48+ PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
49+ PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
50+ PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
51+ PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
52+ PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
53+ PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
54+ PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
55+ PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
56+ PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
57+ PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
58+ PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
59+ PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
60+ PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
61+ PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
62+ PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
63+ PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
64+ PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
65+ PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
66+ PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
67+ PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
68+ PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
69+ PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
70+ PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
71+ PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
72+ PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
73+ PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
74+ PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
75+ PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
76+ PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
77+ PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
78+ PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
79+ PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
80+
3881 /*
3982 * F_() : just information
4083 * FM() : macro for FN_xxx / xxx_MARK
@@ -1517,67 +1560,16 @@ static const u16 pinmux_data[] = { · 1476 unmodified lines
15171560 };
15181561
15191562 /*
1520− * R8A77965 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1521− * Physical layout rows: A - AW, cols: 1 - 39.
1563+ * Pins not associated with a GPIO port.
15221564 */
1523−#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1524−#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1525−#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1526−#define PIN_NONE U16_MAX
1565+enum {
1566+ GP_ASSIGN_LAST(),
1567+ NOGP_ALL(),
1568+};
15271569
15281570 static const struct sh_pfc_pin pinmux_pins[] = {
15291571 PINMUX_GPIO_GP_ALL(),
1530−
1531− /*
1532− * Pins not associated with a GPIO port.
1533− *
1534− * The pin positions are different between different r8a77965
1535− * packages, all that is needed for the pfc driver is a unique
1536− * number for each pin. To this end use the pin layout from
1537− * R-Car M3SiP to calculate a unique number for each pin.
1538− */
1539− SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1540− SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1541− SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1542− SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1543− SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1544− SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1545− SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1546− SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1547− SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1548− SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1549− SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1550− SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1551− SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1552− SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1553− SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1554− SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1555− SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1556− SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1557− SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1558− SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1559− SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1560− SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1561− SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1562− SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1563− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1564− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1565− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1566− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1567− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1568− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1569− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1570− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1571− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1572− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1573− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1574− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1575− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1576− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1577− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1578− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1579− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1580− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1572+ PINMUX_NOGP_ALL(),
15811573 };
15821574
15831575 /* - AUDIO CLOCK ------------------------------------------------------------ */
@@ -1726,7 +1718,7 @@ static const unsigned int avb_phy_int_mux[] = { · 142 unmodified lines
17261718 };
17271719 static const unsigned int avb_mdio_pins[] = {
17281720 /* AVB_MDC, AVB_MDIO */
1729− RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1721+ RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
17301722 };
17311723 static const unsigned int avb_mdio_mux[] = {
17321724 AVB_MDC_MARK, AVB_MDIO_MARK,
@@ -1739,11 +1731,11 @@ static const unsigned int avb_mii_pins[] = { · 6 unmodified lines
17391731 * AVB_RD1, AVB_RD2, AVB_RD3,
17401732 * AVB_TXCREFCLK
17411733 */
1742− PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1743− PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1744− PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1745− PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1746− PIN_NUMBER('A', 12),
1734+ PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1735+ PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1736+ PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1737+ PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1738+ PIN_AVB_TXCREFCLK,
17471739
17481740 };
17491741 static const unsigned int avb_mii_mux[] = {
@@ -4116,6 +4108,36 @@ static const unsigned int tmu_tclk2_b_mux[] = { · 2366 unmodified lines
41164108 TCLK2_B_MARK,
41174109 };
41184110
4111+/* - TPU ------------------------------------------------------------------- */
4112+static const unsigned int tpu_to0_pins[] = {
4113+ /* TPU0TO0 */
4114+ RCAR_GP_PIN(6, 28),
4115+};
4116+static const unsigned int tpu_to0_mux[] = {
4117+ TPU0TO0_MARK,
4118+};
4119+static const unsigned int tpu_to1_pins[] = {
4120+ /* TPU0TO1 */
4121+ RCAR_GP_PIN(6, 29),
4122+};
4123+static const unsigned int tpu_to1_mux[] = {
4124+ TPU0TO1_MARK,
4125+};
4126+static const unsigned int tpu_to2_pins[] = {
4127+ /* TPU0TO2 */
4128+ RCAR_GP_PIN(6, 30),
4129+};
4130+static const unsigned int tpu_to2_mux[] = {
4131+ TPU0TO2_MARK,
4132+};
4133+static const unsigned int tpu_to3_pins[] = {
4134+ /* TPU0TO3 */
4135+ RCAR_GP_PIN(6, 31),
4136+};
4137+static const unsigned int tpu_to3_mux[] = {
4138+ TPU0TO3_MARK,
4139+};
4140+
41194141 /* - USB0 ------------------------------------------------------------------- */
41204142 static const unsigned int usb0_pins[] = {
41214143 /* PWEN, OVC */
@@ -4672,6 +4694,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 550 unmodified lines
46724694 SH_PFC_PIN_GROUP(tmu_tclk1_b),
46734695 SH_PFC_PIN_GROUP(tmu_tclk2_a),
46744696 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4697+ SH_PFC_PIN_GROUP(tpu_to0),
4698+ SH_PFC_PIN_GROUP(tpu_to1),
4699+ SH_PFC_PIN_GROUP(tpu_to2),
4700+ SH_PFC_PIN_GROUP(tpu_to3),
46754701 SH_PFC_PIN_GROUP(usb0),
46764702 SH_PFC_PIN_GROUP(usb1),
46774703 SH_PFC_PIN_GROUP(usb30),
@@ -5164,6 +5190,13 @@ static const char * const tmu_groups[] = { · 486 unmodified lines
51645190 "tmu_tclk2_b",
51655191 };
51665192
5193+static const char * const tpu_groups[] = {
5194+ "tpu_to0",
5195+ "tpu_to1",
5196+ "tpu_to2",
5197+ "tpu_to3",
5198+};
5199+
51675200 static const char * const usb0_groups[] = {
51685201 "usb0",
51695202 };
@@ -5258,6 +5291,7 @@ static const struct sh_pfc_function pinmux_functions[] = { · 88 unmodified lines
52585291 SH_PFC_FUNCTION(sdhi3),
52595292 SH_PFC_FUNCTION(ssi),
52605293 SH_PFC_FUNCTION(tmu),
5294+ SH_PFC_FUNCTION(tpu),
52615295 SH_PFC_FUNCTION(usb0),
52625296 SH_PFC_FUNCTION(usb1),
52635297 SH_PFC_FUNCTION(usb30),
@@ -5830,44 +5864,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { · 566 unmodified lines
58305864
58315865 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
58325866 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5833− { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5834− { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5835− { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5836− { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5837− { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5838− { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5839− { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5840− { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5867+ { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
5868+ { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
5869+ { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
5870+ { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
5871+ { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
5872+ { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
5873+ { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
5874+ { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
58415875 } },
58425876 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5843− { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5844− { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5845− { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5846− { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5847− { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5848− { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5849− { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5850− { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5877+ { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
5878+ { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
5879+ { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
5880+ { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
5881+ { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
5882+ { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
5883+ { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
5884+ { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
58515885 } },
58525886 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5853− { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5854− { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5855− { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5856− { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5857− { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5858− { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5859− { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5860− { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5887+ { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
5888+ { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
5889+ { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
5890+ { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
5891+ { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
5892+ { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
5893+ { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
5894+ { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
58615895 } },
58625896 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5863− { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5864− { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5865− { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5866− { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5867− { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5868− { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5869− { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5870− { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5897+ { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
5898+ { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
5899+ { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
5900+ { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
5901+ { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
5902+ { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5903+ { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5904+ { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
58715905 } },
58725906 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
58735907 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
@@ -5921,7 +5955,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { · 47 unmodified lines
59215955 } },
59225956 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
59235957 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5924− { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
5958+ { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
59255959 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
59265960 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
59275961 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
@@ -5940,29 +5974,29 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { · 12 unmodified lines
59405974 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
59415975 } },
59425976 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5943− { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5944− { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5945− { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5946− { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5947− { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5948− { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5949− { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5950− { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5977+ { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5978+ { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5979+ { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5980+ { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5981+ { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5982+ { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5983+ { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
5984+ { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
59515985 } },
59525986 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5953− { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN3 */
5954− { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
5955− { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
5987+ { PIN_DU_DOTCLKIN3, 28, 2 }, /* DU_DOTCLKIN3 */
5988+ { PIN_FSCLKST, 20, 2 }, /* FSCLKST */
5989+ { PIN_TMS, 4, 2 }, /* TMS */
59565990 } },
59575991 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5958− { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5959− { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5960− { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5961− { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5962− { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5963− { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5964− { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5965− { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5992+ { PIN_TDO, 28, 2 }, /* TDO */
5993+ { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
5994+ { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5995+ { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5996+ { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5997+ { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5998+ { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5999+ { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
59666000 } },
59676001 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
59686002 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
@@ -6031,7 +6065,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { · 62 unmodified lines
60316065 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
60326066 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
60336067 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
6034− { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
6068+ { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
60356069 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
60366070 } },
60376071 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
@@ -6104,35 +6138,35 @@ static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *po · 66 unmodified lines
61046138
61056139 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
61066140 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
6107− [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
6108− [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
6109− [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
6110− [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
6111− [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
6112− [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
6113− [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
6114− [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
6115− [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
6116− [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
6117− [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
6118− [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
6119− [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
6120− [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
6121− [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
6122− [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
6123− [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
6124− [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
6125− [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
6126− [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
6127− [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
6128− [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
6129− [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
6130− [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
6131− [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
6132− [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
6133− [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
6134− [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
6135− [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
6141+ [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
6142+ [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
6143+ [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
6144+ [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
6145+ [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
6146+ [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
6147+ [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
6148+ [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
6149+ [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
6150+ [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
6151+ [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
6152+ [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
6153+ [12] = PIN_RPC_INT_N, /* RPC_INT# */
6154+ [13] = PIN_RPC_WP_N, /* RPC_WP# */
6155+ [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
6156+ [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
6157+ [16] = PIN_AVB_RXC, /* AVB_RXC */
6158+ [17] = PIN_AVB_RD0, /* AVB_RD0 */
6159+ [18] = PIN_AVB_RD1, /* AVB_RD1 */
6160+ [19] = PIN_AVB_RD2, /* AVB_RD2 */
6161+ [20] = PIN_AVB_RD3, /* AVB_RD3 */
6162+ [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
6163+ [22] = PIN_AVB_TXC, /* AVB_TXC */
6164+ [23] = PIN_AVB_TD0, /* AVB_TD0 */
6165+ [24] = PIN_AVB_TD1, /* AVB_TD1 */
6166+ [25] = PIN_AVB_TD2, /* AVB_TD2 */
6167+ [26] = PIN_AVB_TD3, /* AVB_TD3 */
6168+ [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
6169+ [28] = PIN_AVB_MDIO, /* AVB_MDIO */
61366170 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
61376171 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
61386172 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
@@ -6181,7 +6215,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 42 unmodified lines
61816215 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
61826216 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
61836217 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
6184− [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
6218+ [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
61856219 [10] = RCAR_GP_PIN(0, 0), /* D0 */
61866220 [11] = RCAR_GP_PIN(0, 1), /* D1 */
61876221 [12] = RCAR_GP_PIN(0, 2), /* D2 */
@@ -6202,20 +6236,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 14 unmodified lines
62026236 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
62036237 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
62046238 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
6205− [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
6206− [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
6239+ [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
6240+ [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
62076241 } },
62086242 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6209− [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
6210− [ 1] = PIN_NONE,
6211− [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
6212− [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
6213− [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
6214− [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
6215− [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
6216− [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
6217− [ 8] = PIN_NONE,
6218− [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
6243+ [ 0] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
6244+ [ 1] = SH_PFC_PIN_NONE,
6245+ [ 2] = PIN_FSCLKST, /* FSCLKST */
6246+ [ 3] = PIN_EXTALR, /* EXTALR*/
6247+ [ 4] = PIN_TRST_N, /* TRST# */
6248+ [ 5] = PIN_TCK, /* TCK */
6249+ [ 6] = PIN_TMS, /* TMS */
6250+ [ 7] = PIN_TDI, /* TDI */
6251+ [ 8] = SH_PFC_PIN_NONE,
6252+ [ 9] = PIN_ASEBRK, /* ASEBRK */
62196253 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
62206254 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
62216255 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
@@ -6280,7 +6314,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 58 unmodified lines
62806314 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
62816315 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
62826316 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
6283− [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
6317+ [ 6] = PIN_MLB_REF, /* MLB_REF */
62846318 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
62856319 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
62866320 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
@@ -6315,31 +6349,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 28 unmodified lines
63156349 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
63166350 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
63176351 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
6318− [ 7] = PIN_NONE,
6319− [ 8] = PIN_NONE,
6320− [ 9] = PIN_NONE,
6321− [10] = PIN_NONE,
6322− [11] = PIN_NONE,
6323− [12] = PIN_NONE,
6324− [13] = PIN_NONE,
6325− [14] = PIN_NONE,
6326− [15] = PIN_NONE,
6327− [16] = PIN_NONE,
6328− [17] = PIN_NONE,
6329− [18] = PIN_NONE,
6330− [19] = PIN_NONE,
6331− [20] = PIN_NONE,
6332− [21] = PIN_NONE,
6333− [22] = PIN_NONE,
6334− [23] = PIN_NONE,
6335− [24] = PIN_NONE,
6336− [25] = PIN_NONE,
6337− [26] = PIN_NONE,
6338− [27] = PIN_NONE,
6339− [28] = PIN_NONE,
6340− [29] = PIN_NONE,
6341− [30] = PIN_NONE,
6342− [31] = PIN_NONE,
6352+ [ 7] = SH_PFC_PIN_NONE,
6353+ [ 8] = SH_PFC_PIN_NONE,
6354+ [ 9] = SH_PFC_PIN_NONE,
6355+ [10] = SH_PFC_PIN_NONE,
6356+ [11] = SH_PFC_PIN_NONE,
6357+ [12] = SH_PFC_PIN_NONE,
6358+ [13] = SH_PFC_PIN_NONE,
6359+ [14] = SH_PFC_PIN_NONE,
6360+ [15] = SH_PFC_PIN_NONE,
6361+ [16] = SH_PFC_PIN_NONE,
6362+ [17] = SH_PFC_PIN_NONE,
6363+ [18] = SH_PFC_PIN_NONE,
6364+ [19] = SH_PFC_PIN_NONE,
6365+ [20] = SH_PFC_PIN_NONE,
6366+ [21] = SH_PFC_PIN_NONE,
6367+ [22] = SH_PFC_PIN_NONE,
6368+ [23] = SH_PFC_PIN_NONE,
6369+ [24] = SH_PFC_PIN_NONE,
6370+ [25] = SH_PFC_PIN_NONE,
6371+ [26] = SH_PFC_PIN_NONE,
6372+ [27] = SH_PFC_PIN_NONE,
6373+ [28] = SH_PFC_PIN_NONE,
6374+ [29] = SH_PFC_PIN_NONE,
6375+ [30] = SH_PFC_PIN_NONE,
6376+ [31] = SH_PFC_PIN_NONE,
63436377 } },
63446378 { /* sentinel */ },
63456379 };
drivers/pinctrl/sh-pfc/pfc-r8a77970.c+3−23
@@ -19,7 +19,7 @@ · 18 unmodified lines
1919 #include "core.h"
2020 #include "sh_pfc.h"
2121
22−#define CPU_ALL_PORT(fn, sfx) \
22+#define CPU_ALL_GP(fn, sfx) \
2323 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
2424 PORT_GP_28(1, fn, sfx), \
2525 PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
@@ -205,8 +205,8 @@ · 179 unmodified lines
205205 #define IP6_19_16 FM(VI1_DATA8) F_(0, 0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206206 #define IP6_23_20 FM(VI1_DATA9) F_(0, 0) FM(RTS4_N) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207207 #define IP6_27_24 FM(VI1_DATA10) F_(0, 0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208−#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209−#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208+#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209+#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210210 #define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211211 #define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212212 #define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -631,14 +631,12 @@ static const u16 pinmux_data[] = { · 418 unmodified lines
631631 PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
632632 PINMUX_IPSR_GPSR(IP6_31_28, IRQ4),
633633 PINMUX_IPSR_GPSR(IP6_31_28, D14),
634− PINMUX_IPSR_GPSR(IP6_31_28, MMC_WP),
635634
636635 /* IPSR7 */
637636 PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
638637 PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
639638 PINMUX_IPSR_GPSR(IP7_3_0, IRQ5),
640639 PINMUX_IPSR_GPSR(IP7_3_0, D15),
641− PINMUX_IPSR_GPSR(IP7_3_0, MMC_CD),
642640
643641 PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
644642 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR0),
@@ -1121,20 +1119,6 @@ static const unsigned int mmc_ctrl_pins[] = { · 476 unmodified lines
11211119 static const unsigned int mmc_ctrl_mux[] = {
11221120 MMC_CLK_MARK, MMC_CMD_MARK,
11231121 };
1124−static const unsigned int mmc_cd_pins[] = {
1125− /* CD */
1126− RCAR_GP_PIN(3, 16),
1127−};
1128−static const unsigned int mmc_cd_mux[] = {
1129− MMC_CD_MARK,
1130−};
1131−static const unsigned int mmc_wp_pins[] = {
1132− /* WP */
1133− RCAR_GP_PIN(3, 15),
1134−};
1135−static const unsigned int mmc_wp_mux[] = {
1136− MMC_WP_MARK,
1137−};
11381122
11391123 /* - MSIOF0 ----------------------------------------------------------------- */
11401124 static const unsigned int msiof0_clk_pins[] = {
@@ -1726,8 +1710,6 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { · 585 unmodified lines
17261710 SH_PFC_PIN_GROUP(mmc_data4),
17271711 SH_PFC_PIN_GROUP(mmc_data8),
17281712 SH_PFC_PIN_GROUP(mmc_ctrl),
1729− SH_PFC_PIN_GROUP(mmc_cd),
1730− SH_PFC_PIN_GROUP(mmc_wp),
17311713 SH_PFC_PIN_GROUP(msiof0_clk),
17321714 SH_PFC_PIN_GROUP(msiof0_sync),
17331715 SH_PFC_PIN_GROUP(msiof0_ss1),
@@ -1897,8 +1879,6 @@ static const char * const mmc_groups[] = { · 163 unmodified lines
18971879 "mmc_data4",
18981880 "mmc_data8",
18991881 "mmc_ctrl",
1900− "mmc_cd",
1901− "mmc_wp",
19021882 };
19031883
19041884 static const char * const msiof0_groups[] = {
drivers/pinctrl/sh-pfc/pfc-r8a77980.c+1−1
@@ -19,7 +19,7 @@ · 18 unmodified lines
1919 #include "core.h"
2020 #include "sh_pfc.h"
2121
22−#define CPU_ALL_PORT(fn, sfx) \
22+#define CPU_ALL_GP(fn, sfx) \
2323 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
2424 PORT_GP_28(1, fn, sfx), \
2525 PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
drivers/pinctrl/sh-pfc/pfc-r8a77990.c+87−94
@@ -17,10 +17,9 @@ · 16 unmodified lines
1717 #include "core.h"
1818 #include "sh_pfc.h"
1919
20−#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP | \
21− SH_PFC_PIN_CFG_PULL_DOWN)
20+#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP_DOWN)
2221
23−#define CPU_ALL_PORT(fn, sfx) \
22+#define CPU_ALL_GP(fn, sfx) \
2423 PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
2524 PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
2625 PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
@@ -41,6 +40,25 @@ · 14 unmodified lines
4140 PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \
4241 PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \
4342 PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS)
43+
44+#define CPU_ALL_NOGP(fn) \
45+ PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
46+ PIN_NOGP_CFG(AVB_MDC, "AVB_MDC", fn, CFG_FLAGS), \
47+ PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
48+ PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
49+ PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
50+ PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
51+ PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
52+ PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
53+ PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
54+ PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS), \
55+ PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
56+ PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS), \
57+ PIN_NOGP_CFG(TCK, "TCK", fn, CFG_FLAGS), \
58+ PIN_NOGP_CFG(TDI, "TDI", fn, CFG_FLAGS), \
59+ PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
60+ PIN_NOGP_CFG(TRST_N, "TRST_N", fn, CFG_FLAGS)
61+
4462 /*
4563 * F_() : just information
4664 * FM() : macro for FN_xxx / xxx_MARK
@@ -1277,41 +1295,16 @@ static const u16 pinmux_data[] = { · 1230 unmodified lines
12771295 };
12781296
12791297 /*
1280− * R8A77990 has 7 banks with 32 GPIOs in each => 224 GPIOs.
1281− * Physical layout rows: A - AE, cols: 1 - 25.
1298+ * Pins not associated with a GPIO port.
12821299 */
1283−#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1284−#define PIN_NUMBER(r, c) (((r) - 'A') * 25 + (c) + 300)
1285−#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1286−#define PIN_NONE U16_MAX
1300+enum {
1301+ GP_ASSIGN_LAST(),
1302+ NOGP_ALL(),
1303+};
12871304
12881305 static const struct sh_pfc_pin pinmux_pins[] = {
12891306 PINMUX_GPIO_GP_ALL(),
1290−
1291− /*
1292− * Pins not associated with a GPIO port.
1293− *
1294− * The pin positions are different between different R8A77990
1295− * packages, all that is needed for the pfc driver is a unique
1296− * number for each pin. To this end use the pin layout from
1297− * R8A77990 to calculate a unique number for each pin.
1298− */
1299− SH_PFC_PIN_NAMED_CFG('F', 1, TRST_N, CFG_FLAGS),
1300− SH_PFC_PIN_NAMED_CFG('F', 3, TMS, CFG_FLAGS),
1301− SH_PFC_PIN_NAMED_CFG('F', 4, TCK, CFG_FLAGS),
1302− SH_PFC_PIN_NAMED_CFG('G', 2, TDI, CFG_FLAGS),
1303− SH_PFC_PIN_NAMED_CFG('G', 3, FSCLKST_N, CFG_FLAGS),
1304− SH_PFC_PIN_NAMED_CFG('H', 1, ASEBRK, CFG_FLAGS),
1305− SH_PFC_PIN_NAMED_CFG('N', 1, AVB_TXC, CFG_FLAGS),
1306− SH_PFC_PIN_NAMED_CFG('N', 2, AVB_TD0, CFG_FLAGS),
1307− SH_PFC_PIN_NAMED_CFG('N', 3, AVB_TD1, CFG_FLAGS),
1308− SH_PFC_PIN_NAMED_CFG('N', 5, AVB_TD2, CFG_FLAGS),
1309− SH_PFC_PIN_NAMED_CFG('N', 6, AVB_TD3, CFG_FLAGS),
1310− SH_PFC_PIN_NAMED_CFG('P', 3, AVB_TX_CTL, CFG_FLAGS),
1311− SH_PFC_PIN_NAMED_CFG('P', 4, AVB_MDIO, CFG_FLAGS),
1312− SH_PFC_PIN_NAMED_CFG('P', 5, AVB_MDC, CFG_FLAGS),
1313− SH_PFC_PIN_NAMED_CFG('T', 21, MLB_REF, CFG_FLAGS),
1314− SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS),
1307+ PINMUX_NOGP_ALL(),
13151308 };
13161309
13171310 /* - AUDIO CLOCK ------------------------------------------------------------ */
@@ -5026,15 +5019,15 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 3708 unmodified lines
50265019 [0] = RCAR_GP_PIN(2, 23), /* RD# */
50275020 [1] = RCAR_GP_PIN(2, 22), /* BS# */
50285021 [2] = RCAR_GP_PIN(2, 21), /* AVB_PHY_INT */
5029− [3] = PIN_NUMBER('P', 5), /* AVB_MDC */
5030− [4] = PIN_NUMBER('P', 4), /* AVB_MDIO */
5022+ [3] = PIN_AVB_MDC, /* AVB_MDC */
5023+ [4] = PIN_AVB_MDIO, /* AVB_MDIO */
50315024 [5] = RCAR_GP_PIN(2, 20), /* AVB_TXCREFCLK */
5032− [6] = PIN_NUMBER('N', 6), /* AVB_TD3 */
5033− [7] = PIN_NUMBER('N', 5), /* AVB_TD2 */
5034− [8] = PIN_NUMBER('N', 3), /* AVB_TD1 */
5035− [9] = PIN_NUMBER('N', 2), /* AVB_TD0 */
5036− [10] = PIN_NUMBER('N', 1), /* AVB_TXC */
5037− [11] = PIN_NUMBER('P', 3), /* AVB_TX_CTL */
5025+ [6] = PIN_AVB_TD3, /* AVB_TD3 */
5026+ [7] = PIN_AVB_TD2, /* AVB_TD2 */
5027+ [8] = PIN_AVB_TD1, /* AVB_TD1 */
5028+ [9] = PIN_AVB_TD0, /* AVB_TD0 */
5029+ [10] = PIN_AVB_TXC, /* AVB_TXC */
5030+ [11] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
50385031 [12] = RCAR_GP_PIN(2, 19), /* AVB_RD3 */
50395032 [13] = RCAR_GP_PIN(2, 18), /* AVB_RD2 */
50405033 [14] = RCAR_GP_PIN(2, 17), /* AVB_RD1 */
@@ -5085,33 +5078,33 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 44 unmodified lines
50855078 [25] = RCAR_GP_PIN(1, 2), /* A2 */
50865079 [26] = RCAR_GP_PIN(1, 1), /* A1 */
50875080 [27] = RCAR_GP_PIN(1, 0), /* A0 */
5088− [28] = PIN_NONE,
5089− [29] = PIN_NONE,
5081+ [28] = SH_PFC_PIN_NONE,
5082+ [29] = SH_PFC_PIN_NONE,
50905083 [30] = RCAR_GP_PIN(2, 25), /* PUEN_EX_WAIT0 */
50915084 [31] = RCAR_GP_PIN(2, 24), /* PUEN_RD/WR# */
50925085 } },
50935086 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
50945087 [0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
50955088 [1] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
5096− [2] = PIN_NUMBER('H', 1), /* ASEBRK */
5097− [3] = PIN_NONE,
5098− [4] = PIN_NUMBER('G', 2), /* TDI */
5099− [5] = PIN_NUMBER('F', 3), /* TMS */
5100− [6] = PIN_NUMBER('F', 4), /* TCK */
5101− [7] = PIN_NUMBER('F', 1), /* TRST# */
5102− [8] = PIN_NONE,
5103− [9] = PIN_NONE,
5104− [10] = PIN_NONE,
5105− [11] = PIN_NONE,
5106− [12] = PIN_NONE,
5107− [13] = PIN_NONE,
5108− [14] = PIN_NONE,
5109− [15] = PIN_NUMBER('G', 3), /* FSCLKST# */
5089+ [2] = PIN_ASEBRK, /* ASEBRK */
5090+ [3] = SH_PFC_PIN_NONE,
5091+ [4] = PIN_TDI, /* TDI */
5092+ [5] = PIN_TMS, /* TMS */
5093+ [6] = PIN_TCK, /* TCK */
5094+ [7] = PIN_TRST_N, /* TRST# */
5095+ [8] = SH_PFC_PIN_NONE,
5096+ [9] = SH_PFC_PIN_NONE,
5097+ [10] = SH_PFC_PIN_NONE,
5098+ [11] = SH_PFC_PIN_NONE,
5099+ [12] = SH_PFC_PIN_NONE,
5100+ [13] = SH_PFC_PIN_NONE,
5101+ [14] = SH_PFC_PIN_NONE,
5102+ [15] = PIN_FSCLKST_N, /* FSCLKST# */
51105103 [16] = RCAR_GP_PIN(0, 17), /* SDA4 */
51115104 [17] = RCAR_GP_PIN(0, 16), /* SCL4 */
5112− [18] = PIN_NONE,
5113− [19] = PIN_NONE,
5114− [20] = PIN_A_NUMBER('D', 3), /* PRESETOUT# */
5105+ [18] = SH_PFC_PIN_NONE,
5106+ [19] = SH_PFC_PIN_NONE,
5107+ [20] = PIN_PRESETOUT_N, /* PRESETOUT# */
51155108 [21] = RCAR_GP_PIN(0, 15), /* D15 */
51165109 [22] = RCAR_GP_PIN(0, 14), /* D14 */
51175110 [23] = RCAR_GP_PIN(0, 13), /* D13 */
@@ -5130,8 +5123,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 12 unmodified lines
51305123 [2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */
51315124 [3] = RCAR_GP_PIN(5, 2), /* TX0_A */
51325125 [4] = RCAR_GP_PIN(5, 1), /* RX0_A */
5133− [5] = PIN_NONE,
5134− [6] = PIN_NONE,
5126+ [5] = SH_PFC_PIN_NONE,
5127+ [6] = SH_PFC_PIN_NONE,
51355128 [7] = RCAR_GP_PIN(3, 15), /* SD1_WP */
51365129 [8] = RCAR_GP_PIN(3, 14), /* SD1_CD */
51375130 [9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
@@ -5175,7 +5168,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 37 unmodified lines
51755168 [13] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
51765169 [14] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
51775170 [15] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
5178− [16] = PIN_NUMBER('T', 21), /* MLB_REF */
5171+ [16] = PIN_MLB_REF, /* MLB_REF */
51795172 [17] = RCAR_GP_PIN(5, 19), /* MLB_DAT */
51805173 [18] = RCAR_GP_PIN(5, 18), /* MLB_SIG */
51815174 [19] = RCAR_GP_PIN(5, 17), /* MLB_CLK */
@@ -5193,36 +5186,36 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 11 unmodified lines
51935186 [31] = RCAR_GP_PIN(5, 5), /* RX1 */
51945187 } },
51955188 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5196− [0] = PIN_NONE,
5197− [1] = PIN_NONE,
5198− [2] = PIN_NONE,
5199− [3] = PIN_NONE,
5200− [4] = PIN_NONE,
5201− [5] = PIN_NONE,
5202− [6] = PIN_NONE,
5203− [7] = PIN_NONE,
5204− [8] = PIN_NONE,
5205− [9] = PIN_NONE,
5206− [10] = PIN_NONE,
5207− [11] = PIN_NONE,
5208− [12] = PIN_NONE,
5209− [13] = PIN_NONE,
5210− [14] = PIN_NONE,
5211− [15] = PIN_NONE,
5212− [16] = PIN_NONE,
5213− [17] = PIN_NONE,
5214− [18] = PIN_NONE,
5215− [19] = PIN_NONE,
5216− [20] = PIN_NONE,
5217− [21] = PIN_NONE,
5218− [22] = PIN_NONE,
5219− [23] = PIN_NONE,
5220− [24] = PIN_NONE,
5221− [25] = PIN_NONE,
5222− [26] = PIN_NONE,
5223− [27] = PIN_NONE,
5224− [28] = PIN_NONE,
5225− [29] = PIN_NONE,
5189+ [0] = SH_PFC_PIN_NONE,
5190+ [1] = SH_PFC_PIN_NONE,
5191+ [2] = SH_PFC_PIN_NONE,
5192+ [3] = SH_PFC_PIN_NONE,
5193+ [4] = SH_PFC_PIN_NONE,
5194+ [5] = SH_PFC_PIN_NONE,
5195+ [6] = SH_PFC_PIN_NONE,
5196+ [7] = SH_PFC_PIN_NONE,
5197+ [8] = SH_PFC_PIN_NONE,
5198+ [9] = SH_PFC_PIN_NONE,
5199+ [10] = SH_PFC_PIN_NONE,
5200+ [11] = SH_PFC_PIN_NONE,
5201+ [12] = SH_PFC_PIN_NONE,
5202+ [13] = SH_PFC_PIN_NONE,
5203+ [14] = SH_PFC_PIN_NONE,
5204+ [15] = SH_PFC_PIN_NONE,
5205+ [16] = SH_PFC_PIN_NONE,
5206+ [17] = SH_PFC_PIN_NONE,
5207+ [18] = SH_PFC_PIN_NONE,
5208+ [19] = SH_PFC_PIN_NONE,
5209+ [20] = SH_PFC_PIN_NONE,
5210+ [21] = SH_PFC_PIN_NONE,
5211+ [22] = SH_PFC_PIN_NONE,
5212+ [23] = SH_PFC_PIN_NONE,
5213+ [24] = SH_PFC_PIN_NONE,
5214+ [25] = SH_PFC_PIN_NONE,
5215+ [26] = SH_PFC_PIN_NONE,
5216+ [27] = SH_PFC_PIN_NONE,
5217+ [28] = SH_PFC_PIN_NONE,
5218+ [29] = SH_PFC_PIN_NONE,
52265219 [30] = RCAR_GP_PIN(6, 9), /* PUEN_USB30_OVC */
52275220 [31] = RCAR_GP_PIN(6, 17), /* PUEN_USB30_PWEN */
52285221 } },
drivers/pinctrl/sh-pfc/pfc-r8a77995.c+1−1
@@ -17,7 +17,7 @@ · 16 unmodified lines
1717 #include "core.h"
1818 #include "sh_pfc.h"
1919
20−#define CPU_ALL_PORT(fn, sfx) \
20+#define CPU_ALL_GP(fn, sfx) \
2121 PORT_GP_9(0, fn, sfx), \
2222 PORT_GP_32(1, fn, sfx), \
2323 PORT_GP_32(2, fn, sfx), \
drivers/pinctrl/sh-pfc/pfc-sh73a0.c+13−8
@@ -43,6 +43,9 @@ · 42 unmodified lines
4343 PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \
4444 PORT_10(290, fn, pfx##29, sfx), PORT_10(300, fn, pfx##30, sfx)
4545
46+#define CPU_ALL_NOGP(fn) \
47+ PIN_NOGP(A11, "F26", fn)
48+
4649 enum {
4750 PINMUX_RESERVED = 0,
4851
@@ -1147,7 +1150,7 @@ static const u16 pinmux_data[] = { · 1098 unmodified lines
11471150 #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
11481151 #define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
11491152 #define __PU (SH_PFC_PIN_CFG_PULL_UP)
1150−#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1153+#define __PUD (SH_PFC_PIN_CFG_PULL_UP_DOWN)
11511154
11521155 #define SH73A0_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
11531156 #define SH73A0_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)
@@ -1158,11 +1161,13 @@ static const u16 pinmux_data[] = { · 4 unmodified lines
11581161 #define SH73A0_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
11591162 #define SH73A0_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
11601163
1161−/* Pin numbers for pins without a corresponding GPIO port number are computed
1162− * from the row and column numbers with a 1000 offset to avoid collisions with
1163− * GPIO port numbers.
1164+/*
1165+ * Pins not associated with a GPIO port.
11641166 */
1165−#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1)
1167+enum {
1168+ PORT_ASSIGN_LAST(),
1169+ NOGP_ALL(),
1170+};
11661171
11671172 static const struct sh_pfc_pin pinmux_pins[] = {
11681173 /* Table 25-1 (I/O and Pull U/D) */
@@ -1437,7 +1442,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { · 268 unmodified lines
14371442 SH73A0_PIN_O(309),
14381443
14391444 /* Pins not associated with a GPIO port */
1440− SH_PFC_PIN_NAMED(6, 26, F26),
1445+ PINMUX_NOGP_ALL(),
14411446 };
14421447
14431448 /* - BSC -------------------------------------------------------------------- */
@@ -1863,7 +1868,7 @@ static const unsigned int keysc_out7_2_mux[] = { · 419 unmodified lines
18631868 };
18641869 static const unsigned int keysc_out8_0_pins[] = {
18651870 /* KEYOUT8 */
1866− PIN_NUMBER(6, 26),
1871+ PIN_A11,
18671872 };
18681873 static const unsigned int keysc_out8_0_mux[] = {
18691874 KEYOUT8_MARK,
@@ -3073,7 +3078,7 @@ static const unsigned int tpu4_to2_mux[] = { · 1203 unmodified lines
30733078 };
30743079 static const unsigned int tpu4_to3_pins[] = {
30753080 /* TO */
3076− PIN_NUMBER(6, 26),
3081+ PIN_A11,
30773082 };
30783083 static const unsigned int tpu4_to3_mux[] = {
30793084 TPU4TO3_MARK,
drivers/pinctrl/sh-pfc/pfc-sh7734.c+1−1
@@ -11,7 +11,7 @@ · 10 unmodified lines
1111
1212 #include "sh_pfc.h"
1313
14−#define CPU_ALL_PORT(fn, sfx) \
14+#define CPU_ALL_GP(fn, sfx) \
1515 PORT_GP_32(0, fn, sfx), \
1616 PORT_GP_32(1, fn, sfx), \
1717 PORT_GP_32(2, fn, sfx), \
drivers/pinctrl/sh-pfc/pinctrl.c+1−2
@@ -569,8 +569,7 @@ static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin, · 568 unmodified lines
569569
570570 switch (param) {
571571 case PIN_CONFIG_BIAS_DISABLE:
572− return pin->configs &
573− (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
572+ return pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN;
574573
575574 case PIN_CONFIG_BIAS_PULL_UP:
576575 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
drivers/pinctrl/sh-pfc/sh_pfc.h+69−21
@@ -21,10 +21,14 @@ enum { · 20 unmodified lines
2121 PINMUX_TYPE_INPUT,
2222 };
2323
24+#define SH_PFC_PIN_NONE U16_MAX
25+
2426 #define SH_PFC_PIN_CFG_INPUT (1 << 0)
2527 #define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
2628 #define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
2729 #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
30+#define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \
31+ SH_PFC_PIN_CFG_PULL_DOWN)
2832 #define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
2933 #define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
3034 #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
@@ -542,9 +546,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; · 511 unmodified lines
542546 PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
543547 #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
544548
545−#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
549+#define PORT_GP_CFG_27(bank, fn, sfx, cfg) \
546550 PORT_GP_CFG_26(bank, fn, sfx, cfg), \
547− PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \
551+ PORT_GP_CFG_1(bank, 26, fn, sfx, cfg)
552+#define PORT_GP_27(bank, fn, sfx) PORT_GP_CFG_27(bank, fn, sfx, 0)
553+
554+#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
555+ PORT_GP_CFG_27(bank, fn, sfx, cfg), \
548556 PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
549557 #define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
550558
@@ -584,7 +592,7 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; · 33 unmodified lines
584592
585593 /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
586594 #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
587−#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
595+#define GP_ALL(str) CPU_ALL_GP(_GP_ALL, str)
588596
589597 /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
590598 #define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
@@ -594,11 +602,29 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; · 3 unmodified lines
594602 .enum_id = _name##_DATA, \
595603 .configs = cfg, \
596604 }
597−#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
605+#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
598606
599607 /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
600608 #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
601−#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
609+#define PINMUX_DATA_GP_ALL() CPU_ALL_GP(_GP_DATA, unused)
610+
611+/*
612+ * GP_ASSIGN_LAST() - Expand to an enum definition for the last GP pin
613+ *
614+ * The largest GP pin index is obtained by taking the size of a union,
615+ * containing one array per GP pin, sized by the corresponding pin index.
616+ * As the fields in the CPU_ALL_GP() macro definition are separated by commas,
617+ * while the members of a union must be terminated by semicolons, the commas
618+ * are absorbed by wrapping them inside dummy attributes.
619+ */
620+#define _GP_ENTRY(bank, pin, name, sfx, cfg) \
621+ deprecated)); char name[(bank * 32) + pin] __attribute__((deprecated
622+#define GP_ASSIGN_LAST() \
623+ GP_LAST = sizeof(union { \
624+ char dummy[0] __attribute__((deprecated, \
625+ CPU_ALL_GP(_GP_ENTRY, unused), \
626+ deprecated)); \
627+ })
602628
603629 /*
604630 * PORT style (linear pin space)
@@ -641,22 +667,6 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; · 36 unmodified lines
641667 .configs = cfgs, \
642668 }
643669
644−/* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
645−#define SH_PFC_PIN_NAMED(row, col, _name) \
646− { \
647− .pin = PIN_NUMBER(row, col), \
648− .name = __stringify(PIN_##_name), \
649− .configs = SH_PFC_PIN_CFG_NO_GPIO, \
650− }
651−
652−/* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */
653−#define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \
654− { \
655− .pin = PIN_NUMBER(row, col), \
656− .name = __stringify(PIN_##_name), \
657− .configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs, \
658− }
659−
660670 /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
661671 * PORT_name_OUT, PORT_name_IN marks
662672 */
@@ -665,6 +675,24 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; · 2 unmodified lines
665675 PORT##pfx##_OUT, PORT##pfx##_IN)
666676 #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
667677
678+/*
679+ * PORT_ASSIGN_LAST() - Expand to an enum definition for the last PORT pin
680+ *
681+ * The largest PORT pin index is obtained by taking the size of a union,
682+ * containing one array per PORT pin, sized by the corresponding pin index.
683+ * As the fields in the CPU_ALL_PORT() macro definition are separated by
684+ * commas, while the members of a union must be terminated by semicolons, the
685+ * commas are absorbed by wrapping them inside dummy attributes.
686+ */
687+#define _PORT_ENTRY(pn, pfx, sfx) \
688+ deprecated)); char pfx[pn] __attribute__((deprecated
689+#define PORT_ASSIGN_LAST() \
690+ PORT_LAST = sizeof(union { \
691+ char dummy[0] __attribute__((deprecated, \
692+ CPU_ALL_PORT(_PORT_ENTRY, PORT, unused), \
693+ deprecated)); \
694+ })
695+
668696 /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
669697 #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
670698 [gpio - (base)] = { \
@@ -674,6 +702,26 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; · 3 unmodified lines
674702 #define GPIO_FN(str) \
675703 PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
676704
705+/*
706+ * Pins not associated with a GPIO port
707+ */
708+
709+#define PIN_NOGP_CFG(pin, name, fn, cfg) fn(pin, name, cfg)
710+#define PIN_NOGP(pin, name, fn) fn(pin, name, 0)
711+
712+/* NOGP_ALL - Expand to a list of PIN_id */
713+#define _NOGP_ALL(pin, name, cfg) PIN_##pin
714+#define NOGP_ALL() CPU_ALL_NOGP(_NOGP_ALL)
715+
716+/* PINMUX_NOGP_ALL - Expand to a list of sh_pfc_pin entries */
717+#define _NOGP_PINMUX(_pin, _name, cfg) \
718+ { \
719+ .pin = PIN_##_pin, \
720+ .name = "PIN_" _name, \
721+ .configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \
722+ }
723+#define PINMUX_NOGP_ALL() CPU_ALL_NOGP(_NOGP_PINMUX)
724+
677725 /*
678726 * PORTnCR helper macro for SH-Mobile/R-Mobile
679727 */
drivers/pinctrl/stm32/pinctrl-stm32.c+183−1
@@ -44,6 +44,18 @@ · 43 unmodified lines
4444 #define STM32_GPIO_AFRL 0x20
4545 #define STM32_GPIO_AFRH 0x24
4646
47+/* custom bitfield to backup pin status */
48+#define STM32_GPIO_BKP_MODE_SHIFT 0
49+#define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0)
50+#define STM32_GPIO_BKP_ALT_SHIFT 2
51+#define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2)
52+#define STM32_GPIO_BKP_SPEED_SHIFT 6
53+#define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6)
54+#define STM32_GPIO_BKP_PUPD_SHIFT 8
55+#define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8)
56+#define STM32_GPIO_BKP_TYPE 10
57+#define STM32_GPIO_BKP_VAL 11
58+
4759 #define STM32_GPIO_PINS_PER_BANK 16
4860 #define STM32_GPIO_IRQ_LINE 16
4961
@@ -79,6 +91,7 @@ struct stm32_gpio_bank { · 29 unmodified lines
7991 struct irq_domain *domain;
8092 u32 bank_nr;
8193 u32 bank_ioport_nr;
94+ u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
8295 };
8396
8497 struct stm32_pinctrl {
@@ -98,6 +111,8 @@ struct stm32_pinctrl { · 13 unmodified lines
98111 struct stm32_desc_pin *pins;
99112 u32 npins;
100113 u32 pkg;
114+ u16 irqmux_map;
115+ spinlock_t irqmux_lock;
101116 };
102117
103118 static inline int stm32_gpio_pin(int gpio)
@@ -133,11 +148,50 @@ static inline u32 stm32_gpio_get_alt(u32 function) · 29 unmodified lines
133148 return 0;
134149 }
135150
151+static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
152+ u32 offset, u32 value)
153+{
154+ bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
155+ bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;
156+}
157+
158+static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
159+ u32 mode, u32 alt)
160+{
161+ bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |
162+ STM32_GPIO_BKP_ALT_MASK);
163+ bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;
164+ bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;
165+}
166+
167+static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
168+ u32 drive)
169+{
170+ bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
171+ bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;
172+}
173+
174+static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
175+ u32 speed)
176+{
177+ bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
178+ bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;
179+}
180+
181+static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
182+ u32 bias)
183+{
184+ bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
185+ bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
186+}
187+
136188 /* GPIO functions */
137189
138190 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
139191 unsigned offset, int value)
140192 {
193+ stm32_gpio_backup_value(bank, offset, value);
194+
141195 if (!value)
142196 offset += STM32_GPIO_PINS_PER_BANK;
143197
@@ -307,9 +361,53 @@ static int stm32_gpio_domain_activate(struct irq_domain *d, · 163 unmodified lines
307361 {
308362 struct stm32_gpio_bank *bank = d->host_data;
309363 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
364+ unsigned long flags;
365+ int ret = 0;
366+
367+ /*
368+ * gpio irq mux is shared between several banks, a lock has to be done
369+ * to avoid overriding.
370+ */
371+ spin_lock_irqsave(&pctl->irqmux_lock, flags);
372+ if (pctl->hwlock)
373+ ret = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
374+
375+ if (ret) {
376+ dev_err(pctl->dev, "Can't get hwspinlock\n");
377+ goto unlock;
378+ }
379+
380+ if (pctl->irqmux_map & BIT(irq_data->hwirq)) {
381+ dev_err(pctl->dev, "irq line %ld already requested.\n",
382+ irq_data->hwirq);
383+ ret = -EBUSY;
384+ if (pctl->hwlock)
385+ hwspin_unlock(pctl->hwlock);
386+ goto unlock;
387+ } else {
388+ pctl->irqmux_map |= BIT(irq_data->hwirq);
389+ }
310390
311391 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
312− return 0;
392+
393+ if (pctl->hwlock)
394+ hwspin_unlock(pctl->hwlock);
395+
396+unlock:
397+ spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
398+ return ret;
399+}
400+
401+static void stm32_gpio_domain_deactivate(struct irq_domain *d,
402+ struct irq_data *irq_data)
403+{
404+ struct stm32_gpio_bank *bank = d->host_data;
405+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
406+ unsigned long flags;
407+
408+ spin_lock_irqsave(&pctl->irqmux_lock, flags);
409+ pctl->irqmux_map &= ~BIT(irq_data->hwirq);
410+ spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
313411 }
314412
315413 static int stm32_gpio_domain_alloc(struct irq_domain *d,
@@ -338,6 +436,7 @@ static const struct irq_domain_ops stm32_gpio_domain_ops = { · 22 unmodified lines
338436 .alloc = stm32_gpio_domain_alloc,
339437 .free = irq_domain_free_irqs_common,
340438 .activate = stm32_gpio_domain_activate,
439+ .deactivate = stm32_gpio_domain_deactivate,
341440 };
342441
343442 /* Pinctrl functions */
@@ -620,6 +719,8 @@ static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank, · 276 unmodified lines
620719 if (pctl->hwlock)
621720 hwspin_unlock(pctl->hwlock);
622721
722+ stm32_gpio_backup_mode(bank, pin, mode, alt);
723+
623724 unlock:
624725 spin_unlock_irqrestore(&bank->lock, flags);
625726 clk_disable(bank->clk);
@@ -732,6 +833,8 @@ static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank, · 106 unmodified lines
732833 if (pctl->hwlock)
733834 hwspin_unlock(pctl->hwlock);
734835
836+ stm32_gpio_backup_driving(bank, offset, drive);
837+
735838 unlock:
736839 spin_unlock_irqrestore(&bank->lock, flags);
737840 clk_disable(bank->clk);
@@ -784,6 +887,8 @@ static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank, · 46 unmodified lines
784887 if (pctl->hwlock)
785888 hwspin_unlock(pctl->hwlock);
786889
890+ stm32_gpio_backup_speed(bank, offset, speed);
891+
787892 unlock:
788893 spin_unlock_irqrestore(&bank->lock, flags);
789894 clk_disable(bank->clk);
@@ -836,6 +941,8 @@ static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank, · 46 unmodified lines
836941 if (pctl->hwlock)
837942 hwspin_unlock(pctl->hwlock);
838943
944+ stm32_gpio_backup_bias(bank, offset, bias);
945+
839946 unlock:
840947 spin_unlock_irqrestore(&bank->lock, flags);
841948 clk_disable(bank->clk);
@@ -1290,6 +1397,8 @@ int stm32_pctl_probe(struct platform_device *pdev) · 448 unmodified lines
12901397 pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
12911398 }
12921399
1400+ spin_lock_init(&pctl->irqmux_lock);
1401+
12931402 pctl->dev = dev;
12941403 pctl->match_data = match->data;
12951404
@@ -1329,6 +1438,7 @@ int stm32_pctl_probe(struct platform_device *pdev) · 33 unmodified lines
13291438 pctl->pctl_desc.owner = THIS_MODULE;
13301439 pctl->pctl_desc.pins = pins;
13311440 pctl->pctl_desc.npins = pctl->npins;
1441+ pctl->pctl_desc.link_consumers = true;
13321442 pctl->pctl_desc.confops = &stm32_pconf_ops;
13331443 pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
13341444 pctl->pctl_desc.pmxops = &stm32_pmx_ops;
@@ -1369,3 +1479,75 @@ int stm32_pctl_probe(struct platform_device *pdev) · 34 unmodified lines
13691479
13701480 return 0;
13711481 }
1482+
1483+static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
1484+ struct stm32_pinctrl *pctl, u32 pin)
1485+{
1486+ const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
1487+ u32 val, alt, mode, offset = stm32_gpio_pin(pin);
1488+ struct pinctrl_gpio_range *range;
1489+ struct stm32_gpio_bank *bank;
1490+ bool pin_is_irq;
1491+ int ret;
1492+
1493+ range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);
1494+ if (!range)
1495+ return 0;
1496+
1497+ pin_is_irq = gpiochip_line_is_irq(range->gc, offset);
1498+
1499+ if (!desc || (!pin_is_irq && !desc->gpio_owner))
1500+ return 0;
1501+
1502+ bank = gpiochip_get_data(range->gc);
1503+
1504+ alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
1505+ alt >>= STM32_GPIO_BKP_ALT_SHIFT;
1506+ mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
1507+ mode >>= STM32_GPIO_BKP_MODE_SHIFT;
1508+
1509+ ret = stm32_pmx_set_mode(bank, offset, mode, alt);
1510+ if (ret)
1511+ return ret;
1512+
1513+ if (mode == 1) {
1514+ val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
1515+ val = val >> STM32_GPIO_BKP_VAL;
1516+ __stm32_gpio_set(bank, offset, val);
1517+ }
1518+
1519+ val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
1520+ val >>= STM32_GPIO_BKP_TYPE;
1521+ ret = stm32_pconf_set_driving(bank, offset, val);
1522+ if (ret)
1523+ return ret;
1524+
1525+ val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
1526+ val >>= STM32_GPIO_BKP_SPEED_SHIFT;
1527+ ret = stm32_pconf_set_speed(bank, offset, val);
1528+ if (ret)
1529+ return ret;
1530+
1531+ val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
1532+ val >>= STM32_GPIO_BKP_PUPD_SHIFT;
1533+ ret = stm32_pconf_set_bias(bank, offset, val);
1534+ if (ret)
1535+ return ret;
1536+
1537+ if (pin_is_irq)
1538+ regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
1539+
1540+ return 0;
1541+}
1542+
1543+int __maybe_unused stm32_pinctrl_resume(struct device *dev)
1544+{
1545+ struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1546+ struct stm32_pinctrl_group *g = pctl->groups;
1547+ int i;
1548+
1549+ for (i = g->pin; i < g->pin + pctl->ngroups; i++)
1550+ stm32_pinctrl_restore_gpio_regs(pctl, i);
1551+
1552+ return 0;
1553+}
drivers/pinctrl/stm32/pinctrl-stm32.h+2−0
@@ -65,5 +65,7 @@ struct stm32_gpio_bank; · 64 unmodified lines
6565 int stm32_pctl_probe(struct platform_device *pdev);
6666 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank,
6767 int pin, u32 *mode, u32 *alt);
68+int stm32_pinctrl_resume(struct device *dev);
69+
6870 #endif /* __PINCTRL_STM32_H */
6971
drivers/pinctrl/stm32/pinctrl-stm32mp157.c+5−0
@@ -2342,11 +2342,16 @@ static const struct of_device_id stm32mp157_pctrl_match[] = { · 2341 unmodified lines
23422342 { }
23432343 };
23442344
2345+static const struct dev_pm_ops stm32_pinctrl_dev_pm_ops = {
2346+ SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, stm32_pinctrl_resume)
2347+};
2348+
23452349 static struct platform_driver stm32mp157_pinctrl_driver = {
23462350 .probe = stm32_pctl_probe,
23472351 .driver = {
23482352 .name = "stm32mp157-pinctrl",
23492353 .of_match_table = stm32mp157_pctrl_match,
2354+ .pm = &stm32_pinctrl_dev_pm_ops,
23502355 },
23512356 };
23522357
drivers/pinctrl/tegra/Kconfig+4−0
@@ -24,6 +24,10 @@ config PINCTRL_TEGRA210 · 23 unmodified lines
2424 bool
2525 select PINCTRL_TEGRA
2626
27+config PINCTRL_TEGRA194
28+ bool
29+ select PINCTRL_TEGRA
30+
2731 config PINCTRL_TEGRA_XUSB
2832 def_bool y if ARCH_TEGRA
2933 select GENERIC_PHY
drivers/pinctrl/tegra/Makefile+1−0
@@ -5,4 +5,5 @@ obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o · 4 unmodified lines
55 obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o
66 obj-$(CONFIG_PINCTRL_TEGRA124) += pinctrl-tegra124.o
77 obj-$(CONFIG_PINCTRL_TEGRA210) += pinctrl-tegra210.o
8+obj-$(CONFIG_PINCTRL_TEGRA194) += pinctrl-tegra194.o
89 obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o
drivers/pinctrl/tegra/pinctrl-tegra.c+18−8
@@ -284,7 +284,7 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx, · 283 unmodified lines
284284 const struct tegra_pingroup *g,
285285 enum tegra_pinconf_param param,
286286 bool report_err,
287− s8 *bank, s16 *reg, s8 *bit, s8 *width)
287+ s8 *bank, s32 *reg, s8 *bit, s8 *width)
288288 {
289289 switch (param) {
290290 case TEGRA_PINCONF_PARAM_PULL:
@@ -443,7 +443,7 @@ static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev, · 152 unmodified lines
443443 const struct tegra_pingroup *g;
444444 int ret;
445445 s8 bank, bit, width;
446− s16 reg;
446+ s32 reg;
447447 u32 val, mask;
448448
449449 g = &pmx->soc->groups[group];
@@ -472,7 +472,7 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, · 22 unmodified lines
472472 const struct tegra_pingroup *g;
473473 int ret, i;
474474 s8 bank, bit, width;
475− s16 reg;
475+ s32 reg;
476476 u32 val, mask;
477477
478478 g = &pmx->soc->groups[group];
@@ -540,7 +540,7 @@ static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, · 61 unmodified lines
540540 const struct tegra_pingroup *g;
541541 int i, ret;
542542 s8 bank, bit, width;
543− s16 reg;
543+ s32 reg;
544544 u32 val;
545545
546546 g = &pmx->soc->groups[group];
@@ -613,10 +613,20 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx) · 66 unmodified lines
613613
614614 for (i = 0; i < pmx->soc->ngroups; ++i) {
615615 g = &pmx->soc->groups[i];
616− if (g->parked_bit >= 0) {
617− val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
618− val &= ~(1 << g->parked_bit);
619− pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
616+ if (g->parked_bitmask > 0) {
617+ unsigned int bank, reg;
618+
619+ if (g->mux_reg != -1) {
620+ bank = g->mux_bank;
621+ reg = g->mux_reg;
622+ } else {
623+ bank = g->drv_bank;
624+ reg = g->drv_reg;
625+ }
626+
627+ val = pmx_readl(pmx, bank, reg);
628+ val &= ~g->parked_bitmask;
629+ pmx_writel(pmx, val, bank, reg);
620630 }
621631 }
622632 }
drivers/pinctrl/tegra/pinctrl-tegra.h+6−6
@@ -96,7 +96,6 @@ struct tegra_function { · 95 unmodified lines
9696 * @tri_reg: Tri-state register offset.
9797 * @tri_bank: Tri-state register bank.
9898 * @tri_bit: Tri-state register bit.
99− * @parked_bit: Parked register bit. -1 if unsupported.
10099 * @einput_bit: Enable-input register bit.
101100 * @odrain_bit: Open-drain register bit.
102101 * @lock_bit: Lock register bit.
@@ -118,6 +117,7 @@ struct tegra_function { · 15 unmodified lines
118117 * @slwf_bit: Slew Falling register bit.
119118 * @slwf_width: Slew Falling field width.
120119 * @drvtype_bit: Drive type register bit.
120+ * @parked_bitmask: Parked register mask. 0 if unsupported.
121121 *
122122 * -1 in a *_reg field means that feature is unsupported for this group.
123123 * *_bank and *_reg values are irrelevant when *_reg is -1.
@@ -135,10 +135,10 @@ struct tegra_pingroup { · 11 unmodified lines
135135 const unsigned *pins;
136136 u8 npins;
137137 u8 funcs[4];
138− s16 mux_reg;
139− s16 pupd_reg;
140− s16 tri_reg;
141− s16 drv_reg;
138+ s32 mux_reg;
139+ s32 pupd_reg;
140+ s32 tri_reg;
141+ s32 drv_reg;
142142 u32 mux_bank:2;
143143 u32 pupd_bank:2;
144144 u32 tri_bank:2;
@@ -146,7 +146,6 @@ struct tegra_pingroup { · 1 unmodified line
146146 s32 mux_bit:6;
147147 s32 pupd_bit:6;
148148 s32 tri_bit:6;
149− s32 parked_bit:6;
150149 s32 einput_bit:6;
151150 s32 odrain_bit:6;
152151 s32 lock_bit:6;
@@ -164,6 +163,7 @@ struct tegra_pingroup { · 11 unmodified lines
164163 s32 drvup_width:6;
165164 s32 slwr_width:6;
166165 s32 slwf_width:6;
166+ u32 parked_bitmask;
167167 };
168168
169169 /**
drivers/pinctrl/tegra/pinctrl-tegra114.c+3−3
@@ -1572,8 +1572,8 @@ static struct tegra_function tegra114_functions[] = { · 1571 unmodified lines
15721572 .lock_bit = 7, \
15731573 .ioreset_bit = PINGROUP_BIT_##ior(8), \
15741574 .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
1575− .parked_bit = -1, \
15761575 .drv_reg = -1, \
1576+ .parked_bitmask = 0, \
15771577 }
15781578
15791579 #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
@@ -1593,7 +1593,6 @@ static struct tegra_function tegra114_functions[] = { · 13 unmodified lines
15931593 .rcv_sel_bit = -1, \
15941594 .drv_reg = DRV_PINGROUP_REG(r), \
15951595 .drv_bank = 0, \
1596− .parked_bit = -1, \
15971596 .hsm_bit = hsm_b, \
15981597 .schmitt_bit = schmitt_b, \
15991598 .lpmd_bit = lpmd_b, \
@@ -1606,6 +1605,7 @@ static struct tegra_function tegra114_functions[] = { · 6 unmodified lines
16061605 .slwf_bit = slwf_b, \
16071606 .slwf_width = slwf_w, \
16081607 .drvtype_bit = PINGROUP_BIT_##drvtype(6), \
1608+ .parked_bitmask = 0, \
16091609 }
16101610
16111611 static const struct tegra_pingroup tegra114_groups[] = {
@@ -1831,7 +1831,7 @@ static const struct tegra_pingroup tegra114_groups[] = { · 219 unmodified lines
18311831
18321832 static const struct tegra_pinctrl_soc_data tegra114_pinctrl = {
18331833 .ngpios = NUM_GPIOS,
1834− .gpio_compatible = "nvidia,tegra30-gpio",
1834+ .gpio_compatible = "nvidia,tegra114-gpio",
18351835 .pins = tegra114_pins,
18361836 .npins = ARRAY_SIZE(tegra114_pins),
18371837 .functions = tegra114_functions,
drivers/pinctrl/tegra/pinctrl-tegra124.c+3−3
@@ -1741,8 +1741,8 @@ static struct tegra_function tegra124_functions[] = { · 1740 unmodified lines
17411741 .lock_bit = 7, \
17421742 .ioreset_bit = PINGROUP_BIT_##ior(8), \
17431743 .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
1744− .parked_bit = -1, \
17451744 .drv_reg = -1, \
1745+ .parked_bitmask = 0, \
17461746 }
17471747
17481748 #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
@@ -1762,7 +1762,6 @@ static struct tegra_function tegra124_functions[] = { · 13 unmodified lines
17621762 .rcv_sel_bit = -1, \
17631763 .drv_reg = DRV_PINGROUP_REG(r), \
17641764 .drv_bank = 0, \
1765− .parked_bit = -1, \
17661765 .hsm_bit = hsm_b, \
17671766 .schmitt_bit = schmitt_b, \
17681767 .lpmd_bit = lpmd_b, \
@@ -1775,6 +1774,7 @@ static struct tegra_function tegra124_functions[] = { · 6 unmodified lines
17751774 .slwf_bit = slwf_b, \
17761775 .slwf_width = slwf_w, \
17771776 .drvtype_bit = PINGROUP_BIT_##drvtype(6), \
1777+ .parked_bitmask = 0, \
17781778 }
17791779
17801780 #define MIPI_PAD_CTRL_PINGROUP(pg_name, r, b, f0, f1) \
@@ -2043,7 +2043,7 @@ static const struct tegra_pingroup tegra124_groups[] = { · 262 unmodified lines
20432043
20442044 static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
20452045 .ngpios = NUM_GPIOS,
2046− .gpio_compatible = "nvidia,tegra30-gpio",
2046+ .gpio_compatible = "nvidia,tegra124-gpio",
20472047 .pins = tegra124_pins,
20482048 .npins = ARRAY_SIZE(tegra124_pins),
20492049 .functions = tegra124_functions,
drivers/pinctrl/tegra/pinctrl-tegra194.c+170−0
@@ -0,0 +1,170 @@
1+// SPDX-License-Identifier: GPL-2.0+
2+/*
3+ * Pinctrl data for the NVIDIA Tegra194 pinmux
4+ *
5+ * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
6+ *
7+ * This program is free software; you can redistribute it and/or modify it
8+ * under the terms and conditions of the GNU General Public License,
9+ * version 2, as published by the Free Software Foundation.
10+ *
11+ * This program is distributed in the hope it will be useful, but WITHOUT
12+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14+ * more details.
15+ */
16+
17+#include <linux/init.h>
18+#include <linux/of.h>
19+#include <linux/platform_device.h>
20+#include <linux/pinctrl/pinctrl.h>
21+#include <linux/pinctrl/pinmux.h>
22+
23+#include "pinctrl-tegra.h"
24+
25+/* Define unique ID for each pins */
26+enum pin_id {
27+ TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0 = 256,
28+ TEGRA_PIN_PEX_L5_RST_N_PGG1 = 257,
29+ TEGRA_PIN_NUM_GPIOS = 258,
30+};
31+
32+/* Table for pin descriptor */
33+static const struct pinctrl_pin_desc tegra194_pins[] = {
34+ PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
35+ "TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0"),
36+ PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1,
37+ "TEGRA_PIN_PEX_L5_RST_N_PGG1"),
38+};
39+
40+static const unsigned int pex_l5_clkreq_n_pgg0_pins[] = {
41+ TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
42+};
43+
44+static const unsigned int pex_l5_rst_n_pgg1_pins[] = {
45+ TEGRA_PIN_PEX_L5_RST_N_PGG1,
46+};
47+
48+/* Define unique ID for each function */
49+enum tegra_mux_dt {
50+ TEGRA_MUX_RSVD0,
51+ TEGRA_MUX_RSVD1,
52+ TEGRA_MUX_RSVD2,
53+ TEGRA_MUX_RSVD3,
54+ TEGRA_MUX_PE5,
55+};
56+
57+/* Make list of each function name */
58+#define TEGRA_PIN_FUNCTION(lid) \
59+ { \
60+ .name = #lid, \
61+ }
62+static struct tegra_function tegra194_functions[] = {
63+ TEGRA_PIN_FUNCTION(rsvd0),
64+ TEGRA_PIN_FUNCTION(rsvd1),
65+ TEGRA_PIN_FUNCTION(rsvd2),
66+ TEGRA_PIN_FUNCTION(rsvd3),
67+ TEGRA_PIN_FUNCTION(pe5),
68+};
69+
70+#define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b, \
71+ drvup_w, slwr_b, slwr_w, slwf_b, \
72+ slwf_w, bank) \
73+ .drv_reg = ((r)), \
74+ .drv_bank = bank, \
75+ .drvdn_bit = drvdn_b, \
76+ .drvdn_width = drvdn_w, \
77+ .drvup_bit = drvup_b, \
78+ .drvup_width = drvup_w, \
79+ .slwr_bit = slwr_b, \
80+ .slwr_width = slwr_w, \
81+ .slwf_bit = slwf_b, \
82+ .slwf_width = slwf_w
83+
84+#define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk, e_input, \
85+ e_od, schmitt_b, drvtype) \
86+ .mux_reg = ((r)), \
87+ .lpmd_bit = -1, \
88+ .lock_bit = -1, \
89+ .hsm_bit = -1, \
90+ .mux_bank = bank, \
91+ .mux_bit = 0, \
92+ .pupd_reg = ((r)), \
93+ .pupd_bank = bank, \
94+ .pupd_bit = 2, \
95+ .tri_reg = ((r)), \
96+ .tri_bank = bank, \
97+ .tri_bit = 4, \
98+ .einput_bit = e_input, \
99+ .odrain_bit = e_od, \
100+ .schmitt_bit = schmitt_b, \
101+ .drvtype_bit = 13, \
102+ .drv_reg = -1, \
103+ .parked_bitmask = 0
104+
105+#define drive_pex_l5_clkreq_n_pgg0 \
106+ DRV_PINGROUP_ENTRY_Y(0x14004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
107+#define drive_pex_l5_rst_n_pgg1 \
108+ DRV_PINGROUP_ENTRY_Y(0x1400c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
109+
110+#define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_lpbk, \
111+ e_input, e_lpdr, e_od, schmitt_b, drvtype, io_rail) \
112+ { \
113+ .name = #pg_name, \
114+ .pins = pg_name##_pins, \
115+ .npins = ARRAY_SIZE(pg_name##_pins), \
116+ .funcs = { \
117+ TEGRA_MUX_##f0, \
118+ TEGRA_MUX_##f1, \
119+ TEGRA_MUX_##f2, \
120+ TEGRA_MUX_##f3, \
121+ }, \
122+ PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk, \
123+ e_input, e_od, \
124+ schmitt_b, drvtype), \
125+ drive_##pg_name, \
126+ }
127+
128+static const struct tegra_pingroup tegra194_groups[] = {
129+ PINGROUP(pex_l5_clkreq_n_pgg0, PE5, RSVD1, RSVD2, RSVD3, 0x14000, 0,
130+ Y, -1, 6, 8, 11, 12, N, "vddio_pex_ctl_2"),
131+ PINGROUP(pex_l5_rst_n_pgg1, PE5, RSVD1, RSVD2, RSVD3, 0x14008, 0,
132+ Y, -1, 6, 8, 11, 12, N, "vddio_pex_ctl_2"),
133+};
134+
135+static const struct tegra_pinctrl_soc_data tegra194_pinctrl = {
136+ .ngpios = TEGRA_PIN_NUM_GPIOS,
137+ .pins = tegra194_pins,
138+ .npins = ARRAY_SIZE(tegra194_pins),
139+ .functions = tegra194_functions,
140+ .nfunctions = ARRAY_SIZE(tegra194_functions),
141+ .groups = tegra194_groups,
142+ .ngroups = ARRAY_SIZE(tegra194_groups),
143+ .hsm_in_mux = true,
144+ .schmitt_in_mux = true,
145+ .drvtype_in_mux = true,
146+};
147+
148+static int tegra194_pinctrl_probe(struct platform_device *pdev)
149+{
150+ return tegra_pinctrl_probe(pdev, &tegra194_pinctrl);
151+}
152+
153+static const struct of_device_id tegra194_pinctrl_of_match[] = {
154+ { .compatible = "nvidia,tegra194-pinmux", },
155+ { },
156+};
157+
158+static struct platform_driver tegra194_pinctrl_driver = {
159+ .driver = {
160+ .name = "tegra194-pinctrl",
161+ .of_match_table = tegra194_pinctrl_of_match,
162+ },
163+ .probe = tegra194_pinctrl_probe,
164+};
165+
166+static int __init tegra194_pinctrl_init(void)
167+{
168+ return platform_driver_register(&tegra194_pinctrl_driver);
169+}
170+arch_initcall(tegra194_pinctrl_init);
drivers/pinctrl/tegra/pinctrl-tegra20.c+3−3
@@ -1989,13 +1989,13 @@ static struct tegra_function tegra20_functions[] = { · 1988 unmodified lines
19891989 .tri_reg = ((tri_r) - TRISTATE_REG_A), \
19901990 .tri_bank = 0, \
19911991 .tri_bit = tri_b, \
1992− .parked_bit = -1, \
19931992 .einput_bit = -1, \
19941993 .odrain_bit = -1, \
19951994 .lock_bit = -1, \
19961995 .ioreset_bit = -1, \
19971996 .rcv_sel_bit = -1, \
19981997 .drv_reg = -1, \
1998+ .parked_bitmask = 0, \
19991999 }
20002000
20012001 /* Pin groups with only pull up and pull down control */
@@ -2009,7 +2009,7 @@ static struct tegra_function tegra20_functions[] = { · 7 unmodified lines
20092009 .pupd_bank = 2, \
20102010 .pupd_bit = pupd_b, \
20112011 .drv_reg = -1, \
2012− .parked_bit = -1, \
2012+ .parked_bitmask = 0, \
20132013 }
20142014
20152015 /* Pin groups for drive strength registers (configurable version) */
@@ -2025,7 +2025,7 @@ static struct tegra_function tegra20_functions[] = { · 9 unmodified lines
20252025 .tri_reg = -1, \
20262026 .drv_reg = ((r) - PINGROUP_REG_A), \
20272027 .drv_bank = 3, \
2028− .parked_bit = -1, \
2028+ .parked_bitmask = 0, \
20292029 .hsm_bit = hsm_b, \
20302030 .schmitt_bit = schmitt_b, \
20312031 .lpmd_bit = lpmd_b, \
drivers/pinctrl/tegra/pinctrl-tegra210.c+31−31
@@ -1302,7 +1302,6 @@ static struct tegra_function tegra210_functions[] = { · 1301 unmodified lines
13021302 .lock_bit = 7, \
13031303 .ioreset_bit = -1, \
13041304 .rcv_sel_bit = PINGROUP_BIT_##e_io_hv(10), \
1305− .parked_bit = 5, \
13061305 .hsm_bit = PINGROUP_BIT_##hsm(9), \
13071306 .schmitt_bit = 12, \
13081307 .drvtype_bit = PINGROUP_BIT_##drvtype(13), \
@@ -1317,10 +1316,11 @@ static struct tegra_function tegra210_functions[] = { · 8 unmodified lines
13171316 .slwr_width = slwr_w, \
13181317 .slwf_bit = slwf_b, \
13191318 .slwf_width = slwf_w, \
1319+ .parked_bitmask = BIT(5), \
13201320 }
13211321
1322−#define DRV_PINGROUP(pg_name, r, drvdn_b, drvdn_w, drvup_b, drvup_w, \
1323− slwr_b, slwr_w, slwf_b, slwf_w) \
1322+#define DRV_PINGROUP(pg_name, r, prk_mask, drvdn_b, drvdn_w, drvup_b, \
1323+ drvup_w, slwr_b, slwr_w, slwf_b, slwf_w) \
13241324 { \
13251325 .name = "drive_" #pg_name, \
13261326 .pins = drive_##pg_name##_pins, \
@@ -1335,7 +1335,6 @@ static struct tegra_function tegra210_functions[] = { · 8 unmodified lines
13351335 .rcv_sel_bit = -1, \
13361336 .drv_reg = DRV_PINGROUP_REG(r), \
13371337 .drv_bank = 0, \
1338− .parked_bit = -1, \
13391338 .hsm_bit = -1, \
13401339 .schmitt_bit = -1, \
13411340 .lpmd_bit = -1, \
@@ -1348,6 +1347,7 @@ static struct tegra_function tegra210_functions[] = { · 6 unmodified lines
13481347 .slwf_bit = slwf_b, \
13491348 .slwf_width = slwf_w, \
13501349 .drvtype_bit = -1, \
1350+ .parked_bitmask = prk_mask, \
13511351 }
13521352
13531353 static const struct tegra_pingroup tegra210_groups[] = {
@@ -1515,37 +1515,37 @@ static const struct tegra_pingroup tegra210_groups[] = { · 161 unmodified lines
15151515 PINGROUP(pz4, SDMMC1, RSVD1, RSVD2, RSVD3, 0x328c, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
15161516 PINGROUP(pz5, SOC, RSVD1, RSVD2, RSVD3, 0x3290, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
15171517
1518− /* pg_name, r, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */
1519− DRV_PINGROUP(pa6, 0x9c0, 12, 5, 20, 5, -1, -1, -1, -1),
1520− DRV_PINGROUP(pcc7, 0x9c4, 12, 5, 20, 5, -1, -1, -1, -1),
1521− DRV_PINGROUP(pe6, 0x9c8, 12, 5, 20, 5, -1, -1, -1, -1),
1522− DRV_PINGROUP(pe7, 0x9cc, 12, 5, 20, 5, -1, -1, -1, -1),
1523− DRV_PINGROUP(ph6, 0x9d0, 12, 5, 20, 5, -1, -1, -1, -1),
1524− DRV_PINGROUP(pk0, 0x9d4, -1, -1, -1, -1, 28, 2, 30, 2),
1525− DRV_PINGROUP(pk1, 0x9d8, -1, -1, -1, -1, 28, 2, 30, 2),
1526− DRV_PINGROUP(pk2, 0x9dc, -1, -1, -1, -1, 28, 2, 30, 2),
1527− DRV_PINGROUP(pk3, 0x9e0, -1, -1, -1, -1, 28, 2, 30, 2),
1528− DRV_PINGROUP(pk4, 0x9e4, -1, -1, -1, -1, 28, 2, 30, 2),
1529− DRV_PINGROUP(pk5, 0x9e8, -1, -1, -1, -1, 28, 2, 30, 2),
1530− DRV_PINGROUP(pk6, 0x9ec, -1, -1, -1, -1, 28, 2, 30, 2),
1531− DRV_PINGROUP(pk7, 0x9f0, -1, -1, -1, -1, 28, 2, 30, 2),
1532− DRV_PINGROUP(pl0, 0x9f4, -1, -1, -1, -1, 28, 2, 30, 2),
1533− DRV_PINGROUP(pl1, 0x9f8, -1, -1, -1, -1, 28, 2, 30, 2),
1534− DRV_PINGROUP(pz0, 0x9fc, 12, 7, 20, 7, -1, -1, -1, -1),
1535− DRV_PINGROUP(pz1, 0xa00, 12, 7, 20, 7, -1, -1, -1, -1),
1536− DRV_PINGROUP(pz2, 0xa04, 12, 7, 20, 7, -1, -1, -1, -1),
1537− DRV_PINGROUP(pz3, 0xa08, 12, 7, 20, 7, -1, -1, -1, -1),
1538− DRV_PINGROUP(pz4, 0xa0c, 12, 7, 20, 7, -1, -1, -1, -1),
1539− DRV_PINGROUP(pz5, 0xa10, 12, 7, 20, 7, -1, -1, -1, -1),
1540− DRV_PINGROUP(sdmmc1, 0xa98, 12, 7, 20, 7, 28, 2, 30, 2),
1541− DRV_PINGROUP(sdmmc2, 0xa9c, 2, 6, 8, 6, 28, 2, 30, 2),
1542− DRV_PINGROUP(sdmmc3, 0xab0, 12, 7, 20, 7, 28, 2, 30, 2),
1543− DRV_PINGROUP(sdmmc4, 0xab4, 2, 6, 8, 6, 28, 2, 30, 2),
1518+ /* pg_name, r, prk_mask, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */
1519+ DRV_PINGROUP(pa6, 0x9c0, 0x0, 12, 5, 20, 5, -1, -1, -1, -1),
1520+ DRV_PINGROUP(pcc7, 0x9c4, 0x0, 12, 5, 20, 5, -1, -1, -1, -1),
1521+ DRV_PINGROUP(pe6, 0x9c8, 0x0, 12, 5, 20, 5, -1, -1, -1, -1),
1522+ DRV_PINGROUP(pe7, 0x9cc, 0x0, 12, 5, 20, 5, -1, -1, -1, -1),
1523+ DRV_PINGROUP(ph6, 0x9d0, 0x0, 12, 5, 20, 5, -1, -1, -1, -1),
1524+ DRV_PINGROUP(pk0, 0x9d4, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
1525+ DRV_PINGROUP(pk1, 0x9d8, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
1526+ DRV_PINGROUP(pk2, 0x9dc, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
1527+ DRV_PINGROUP(pk3, 0x9e0, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
1528+ DRV_PINGROUP(pk4, 0x9e4, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
1529+ DRV_PINGROUP(pk5, 0x9e8, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
1530+ DRV_PINGROUP(pk6, 0x9ec, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
1531+ DRV_PINGROUP(pk7, 0x9f0, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
1532+ DRV_PINGROUP(pl0, 0x9f4, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
1533+ DRV_PINGROUP(pl1, 0x9f8, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
1534+ DRV_PINGROUP(pz0, 0x9fc, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
1535+ DRV_PINGROUP(pz1, 0xa00, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
1536+ DRV_PINGROUP(pz2, 0xa04, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
1537+ DRV_PINGROUP(pz3, 0xa08, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
1538+ DRV_PINGROUP(pz4, 0xa0c, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
1539+ DRV_PINGROUP(pz5, 0xa10, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
1540+ DRV_PINGROUP(sdmmc1, 0xa98, 0x0, 12, 7, 20, 7, 28, 2, 30, 2),
1541+ DRV_PINGROUP(sdmmc2, 0xa9c, 0x7ffc000, 2, 6, 8, 6, 28, 2, 30, 2),
1542+ DRV_PINGROUP(sdmmc3, 0xab0, 0x0, 12, 7, 20, 7, 28, 2, 30, 2),
1543+ DRV_PINGROUP(sdmmc4, 0xab4, 0x7ffc000, 2, 6, 8, 6, 28, 2, 30, 2),
15441544 };
15451545
15461546 static const struct tegra_pinctrl_soc_data tegra210_pinctrl = {
15471547 .ngpios = NUM_GPIOS,
1548− .gpio_compatible = "nvidia,tegra30-gpio",
1548+ .gpio_compatible = "nvidia,tegra210-gpio",
15491549 .pins = tegra210_pins,
15501550 .npins = ARRAY_SIZE(tegra210_pins),
15511551 .functions = tegra210_functions,
drivers/pinctrl/tegra/pinctrl-tegra30.c+2−2
@@ -2133,8 +2133,8 @@ static struct tegra_function tegra30_functions[] = { · 2132 unmodified lines
21332133 .lock_bit = 7, \
21342134 .ioreset_bit = PINGROUP_BIT_##ior(8), \
21352135 .rcv_sel_bit = -1, \
2136− .parked_bit = -1, \
21372136 .drv_reg = -1, \
2137+ .parked_bitmask = 0, \
21382138 }
21392139
21402140 #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
@@ -2154,7 +2154,6 @@ static struct tegra_function tegra30_functions[] = { · 13 unmodified lines
21542154 .rcv_sel_bit = -1, \
21552155 .drv_reg = DRV_PINGROUP_REG(r), \
21562156 .drv_bank = 0, \
2157− .parked_bit = -1, \
21582157 .hsm_bit = hsm_b, \
21592158 .schmitt_bit = schmitt_b, \
21602159 .lpmd_bit = lpmd_b, \
@@ -2167,6 +2166,7 @@ static struct tegra_function tegra30_functions[] = { · 6 unmodified lines
21672166 .slwf_bit = slwf_b, \
21682167 .slwf_width = slwf_w, \
21692168 .drvtype_bit = -1, \
2169+ .parked_bitmask = 0, \
21702170 }
21712171
21722172 static const struct tegra_pingroup tegra30_groups[] = {
include/linux/gpio.h+1−0
@@ -106,6 +106,7 @@ void devm_gpio_free(struct device *dev, unsigned int gpio); · 105 unmodified lines
106106
107107 struct device;
108108 struct gpio_chip;
109+struct pinctrl_dev;
109110
110111 static inline bool gpio_is_valid(int number)
111112 {
include/linux/gpio/driver.h+2−0
@@ -586,6 +586,8 @@ void gpiochip_remove_pin_ranges(struct gpio_chip *chip); · 585 unmodified lines
586586
587587 #else /* ! CONFIG_PINCTRL */
588588
589+struct pinctrl_dev;
590+
589591 static inline int
590592 gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
591593 unsigned int gpio_offset, unsigned int pin_offset,
include/linux/pinctrl/pinconf-generic.h+9−14
@@ -11,6 +11,12 @@ · 10 unmodified lines
1111 #ifndef __LINUX_PINCTRL_PINCONF_GENERIC_H
1212 #define __LINUX_PINCTRL_PINCONF_GENERIC_H
1313
14+#include <linux/device.h>
15+#include <linux/pinctrl/machine.h>
16+
17+struct pinctrl_dev;
18+struct pinctrl_map;
19+
1420 /**
1521 * enum pin_config_param - possible pin configuration parameters
1622 * @PIN_CONFIG_BIAS_BUS_HOLD: the pin will be set to weakly latch so that it
@@ -54,6 +60,8 @@ · 37 unmodified lines
5460 * push-pull mode, the argument is ignored.
5561 * @PIN_CONFIG_DRIVE_STRENGTH: the pin will sink or source at most the current
5662 * passed as argument. The argument is in mA.
63+ * @PIN_CONFIG_DRIVE_STRENGTH_UA: the pin will sink or source at most the current
64+ * passed as argument. The argument is in uA.
5765 * @PIN_CONFIG_INPUT_DEBOUNCE: this will configure the pin to debounce mode,
5866 * which means it will wait for signals to settle when reading inputs. The
5967 * argument gives the debounce time in usecs. Setting the
@@ -111,6 +119,7 @@ enum pin_config_param { · 51 unmodified lines
111119 PIN_CONFIG_DRIVE_OPEN_SOURCE,
112120 PIN_CONFIG_DRIVE_PUSH_PULL,
113121 PIN_CONFIG_DRIVE_STRENGTH,
122+ PIN_CONFIG_DRIVE_STRENGTH_UA,
114123 PIN_CONFIG_INPUT_DEBOUNCE,
115124 PIN_CONFIG_INPUT_ENABLE,
116125 PIN_CONFIG_INPUT_SCHMITT,
@@ -155,9 +164,6 @@ static inline unsigned long pinconf_to_config_packed(enum pin_config_param param · 38 unmodified lines
155164 return PIN_CONF_PACKED(param, argument);
156165 }
157166
158−#ifdef CONFIG_GENERIC_PINCONF
159−
160−#ifdef CONFIG_DEBUG_FS
161167 #define PCONFDUMP(a, b, c, d) { \
162168 .param = a, .display = b, .format = c, .has_arg = d \
163169 }
@@ -168,14 +174,6 @@ struct pin_config_item { · 4 unmodified lines
168174 const char * const format;
169175 bool has_arg;
170176 };
171−#endif /* CONFIG_DEBUG_FS */
172−
173−#ifdef CONFIG_OF
174−
175−#include <linux/device.h>
176−#include <linux/pinctrl/machine.h>
177−struct pinctrl_dev;
178−struct pinctrl_map;
179177
180178 struct pinconf_generic_params {
181179 const char * const property;
@@ -220,8 +218,5 @@ static inline int pinconf_generic_dt_node_to_map_all( · 38 unmodified lines
220218 return pinconf_generic_dt_node_to_map(pctldev, np_config, map, num_maps,
221219 PIN_MAP_TYPE_INVALID);
222220 }
223−#endif
224−
225−#endif /* CONFIG_GENERIC_PINCONF */
226221
227222 #endif /* __LINUX_PINCTRL_PINCONF_GENERIC_H */
include/linux/pinctrl/pinconf.h+1−3
@@ -11,7 +11,7 @@ · 10 unmodified lines
1111 #ifndef __LINUX_PINCTRL_PINCONF_H
1212 #define __LINUX_PINCTRL_PINCONF_H
1313
14−#ifdef CONFIG_PINCONF
14+#include <linux/types.h>
1515
1616 struct pinctrl_dev;
1717 struct seq_file;
@@ -64,6 +64,4 @@ struct pinconf_ops { · 46 unmodified lines
6464 unsigned long config);
6565 };
6666
67−#endif
68−
6967 #endif /* __LINUX_PINCTRL_PINCONF_H */
include/linux/pinctrl/pinctrl-state.h+5−0
@@ -3,6 +3,9 @@ · 2 unmodified lines
33 * Standard pin control state definitions
44 */
55
6+#ifndef __LINUX_PINCTRL_PINCTRL_STATE_H
7+#define __LINUX_PINCTRL_PINCTRL_STATE_H
8+
69 /**
710 * @PINCTRL_STATE_DEFAULT: the state the pinctrl handle shall be put
811 * into as default, usually this means the pins are up and ready to
@@ -31,3 +34,5 @@ · 22 unmodified lines
3134 #define PINCTRL_STATE_INIT "init"
3235 #define PINCTRL_STATE_IDLE "idle"
3336 #define PINCTRL_STATE_SLEEP "sleep"
37+
38+#endif /* __LINUX_PINCTRL_PINCTRL_STATE_H */
include/linux/pinctrl/pinctrl.h+5−14
@@ -11,8 +11,6 @@ · 10 unmodified lines
1111 #ifndef __LINUX_PINCTRL_PINCTRL_H
1212 #define __LINUX_PINCTRL_PINCTRL_H
1313
14−#ifdef CONFIG_PINCTRL
15−
1614 #include <linux/radix-tree.h>
1715 #include <linux/list.h>
1816 #include <linux/seq_file.h>
@@ -124,6 +122,10 @@ struct pinctrl_ops { · 105 unmodified lines
124122 * the hardware description
125123 * @custom_conf_items: Information how to print @params in debugfs, must be
126124 * the same size as the @custom_params, i.e. @num_custom_params
125+ * @link_consumers: If true create a device link between pinctrl and its
126+ * consumers (i.e. the devices requesting pin control states). This is
127+ * sometimes necessary to ascertain the right suspend/resume order for
128+ * example.
127129 */
128130 struct pinctrl_desc {
129131 const char *name;
@@ -138,6 +140,7 @@ struct pinctrl_desc { · 8 unmodified lines
138140 const struct pinconf_generic_params *custom_params;
139141 const struct pin_config_item *custom_conf_items;
140142 #endif
143+ bool link_consumers;
141144 };
142145
143146 /* External interface to pin controller */
@@ -166,7 +169,6 @@ extern struct pinctrl_dev *devm_pinctrl_register(struct device *dev, · 22 unmodified lines
166169 extern void devm_pinctrl_unregister(struct device *dev,
167170 struct pinctrl_dev *pctldev);
168171
169−extern bool pin_is_valid(struct pinctrl_dev *pctldev, int pin);
170172 extern void pinctrl_add_gpio_range(struct pinctrl_dev *pctldev,
171173 struct pinctrl_gpio_range *range);
172174 extern void pinctrl_add_gpio_ranges(struct pinctrl_dev *pctldev,
@@ -197,16 +199,5 @@ struct pinctrl_dev *of_pinctrl_get(struct device_node *np) · 24 unmodified lines
197199 extern const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev);
198200 extern const char *pinctrl_dev_get_devname(struct pinctrl_dev *pctldev);
199201 extern void *pinctrl_dev_get_drvdata(struct pinctrl_dev *pctldev);
200−#else
201−
202−struct pinctrl_dev;
203−
204−/* Sufficiently stupid default functions when pinctrl is not in use */
205−static inline bool pin_is_valid(struct pinctrl_dev *pctldev, int pin)
206−{
207− return pin >= 0;
208−}
209−
210−#endif /* !CONFIG_PINCTRL */
211202
212203 #endif /* __LINUX_PINCTRL_PINCTRL_H */
include/linux/pinctrl/pinmux.h+0−4
@@ -15,8 +15,6 @@ · 14 unmodified lines
1515 #include <linux/seq_file.h>
1616 #include <linux/pinctrl/pinctrl.h>
1717
18−#ifdef CONFIG_PINMUX
19−
2018 struct pinctrl_dev;
2119
2220 /**
@@ -84,6 +82,4 @@ struct pinmux_ops { · 61 unmodified lines
8482 bool strict;
8583 };
8684
87−#endif /* CONFIG_PINMUX */
88−
8985 #endif /* __LINUX_PINCTRL_PINMUX_H */

Keyboard shortcuts

General

Show keyboard shortcuts
?
Focus the current search
/

Issues and pull requests

Open filters
f

Issues, pull requests and Inbox

Select next item
j↓
Select previous item
k↑
Open selected item
Enter
Dismiss filters or clear selection
Esc

Repository code

Go to file
t