Remove IA-64 architecture support Fix the IA-64 build before removing the architecture support completely. This makes v6.6 LTS the final Linux release with IA-64/Itanium support. * tag 'tag-remove-ia64' of git://git.kernel.org/pub/scm/linux/kernel/git/ardb/linux: Documentation: Drop or replace remaining mentions of IA64 lib/raid6: Drop IA64 support Documentation: Drop IA64 from feature descriptions kernel: Drop IA64 support from sig_fault handlers arch: Remove Itanium (IA-64) architecture acpi: Provide ia64 dummy implementation of acpi_proc_quirk_mwait_check()
Unified · Split
| @@ -354,9 +354,6 @@ Description: Parameters for the CPU cache attributes · 353 unmodified lines | ||
| 354 | 354 | - ReadWriteAllocate: |
| 355 | 355 | both writeallocate and readallocate |
| 356 | 356 | |
| 357 | − attributes: | |
| 358 | − LEGACY used only on IA64 and is same as write_policy | |
| 359 | − | |
| 360 | 357 | coherency_line_size: |
| 361 | 358 | the minimum amount of data in bytes that gets |
| 362 | 359 | transferred from memory to cache |
| @@ -2,7 +2,7 @@ What: /sys/firmware/dmi/entries/ · 1 unmodified line | ||
| 2 | 2 | Date: February 2011 |
| 3 | 3 | Contact: Mike Waychison <mikew@google.com> |
| 4 | 4 | Description: |
| 5 | − Many machines' firmware (x86 and ia64) export DMI / | |
| 5 | + Many machines' firmware (x86 and arm64) export DMI / | |
| 6 | 6 | SMBIOS tables to the operating system. Getting at this |
| 7 | 7 | information is often valuable to userland, especially in |
| 8 | 8 | cases where there are OEM extensions used. |
| @@ -17,7 +17,7 @@ You can use common commands, such as cp, scp or makedumpfile to copy · 16 unmodified lines | ||
| 17 | 17 | the memory image to a dump file on the local disk, or across the network |
| 18 | 18 | to a remote system. |
| 19 | 19 | |
| 20 | −Kdump and kexec are currently supported on the x86, x86_64, ppc64, ia64, | |
| 20 | +Kdump and kexec are currently supported on the x86, x86_64, ppc64, | |
| 21 | 21 | s390x, arm and arm64 architectures. |
| 22 | 22 | |
| 23 | 23 | When the system kernel boots, it reserves a small section of memory for |
| @@ -113,7 +113,7 @@ There are two possible methods of using Kdump. · 89 unmodified lines | ||
| 113 | 113 | 2) Or use the system kernel binary itself as dump-capture kernel and there is |
| 114 | 114 | no need to build a separate dump-capture kernel. This is possible |
| 115 | 115 | only with the architectures which support a relocatable kernel. As |
| 116 | − of today, i386, x86_64, ppc64, ia64, arm and arm64 architectures support | |
| 116 | + of today, i386, x86_64, ppc64, arm and arm64 architectures support | |
| 117 | 117 | relocatable kernel. |
| 118 | 118 | |
| 119 | 119 | Building a relocatable kernel is advantageous from the point of view that |
| @@ -236,24 +236,6 @@ Dump-capture kernel config options (Arch Dependent, ppc64) · 116 unmodified lines | ||
| 236 | 236 | |
| 237 | 237 | Make and install the kernel and its modules. |
| 238 | 238 | |
| 239 | −Dump-capture kernel config options (Arch Dependent, ia64) | |
| 240 | −---------------------------------------------------------- | |
| 241 | − | |
| 242 | −- No specific options are required to create a dump-capture kernel | |
| 243 | − for ia64, other than those specified in the arch independent section | |
| 244 | − above. This means that it is possible to use the system kernel | |
| 245 | − as a dump-capture kernel if desired. | |
| 246 | − | |
| 247 | − The crashkernel region can be automatically placed by the system | |
| 248 | − kernel at runtime. This is done by specifying the base address as 0, | |
| 249 | − or omitting it all together:: | |
| 250 | − | |
| 251 | − crashkernel=256M@0 | |
| 252 | − | |
| 253 | − or:: | |
| 254 | − | |
| 255 | − crashkernel=256M | |
| 256 | − | |
| 257 | 239 | Dump-capture kernel config options (Arch Dependent, arm) |
| 258 | 240 | ---------------------------------------------------------- |
| 259 | 241 | |
| @@ -348,11 +330,6 @@ Boot into System Kernel · 88 unmodified lines | ||
| 348 | 330 | |
| 349 | 331 | On ppc64, use "crashkernel=128M@32M". |
| 350 | 332 | |
| 351 | − On ia64, 256M@256M is a generous value that typically works. | |
| 352 | − The region may be automatically placed on ia64, see the | |
| 353 | − dump-capture kernel config option notes above. | |
| 354 | − If use sparse memory, the size should be rounded to GRANULE boundaries. | |
| 355 | − | |
| 356 | 333 | On s390x, typically use "crashkernel=xxM". The value of xx is dependent |
| 357 | 334 | on the memory consumption of the kdump system. In general this is not |
| 358 | 335 | dependent on the memory size of the production system. |
| @@ -383,10 +360,6 @@ For ppc64: · 24 unmodified lines | ||
| 383 | 360 | |
| 384 | 361 | - Use vmlinux |
| 385 | 362 | |
| 386 | −For ia64: | |
| 387 | − | |
| 388 | − - Use vmlinux or vmlinuz.gz | |
| 389 | − | |
| 390 | 363 | For s390x: |
| 391 | 364 | |
| 392 | 365 | - Use image or bzImage |
| @@ -428,14 +401,10 @@ to load dump-capture kernel:: · 35 unmodified lines | ||
| 428 | 401 | --initrd=<initrd-for-dump-capture-kernel> \ |
| 429 | 402 | --append="root=<root-dev> <arch-specific-options>" |
| 430 | 403 | |
| 431 | −Please note, that --args-linux does not need to be specified for ia64. | |
| 432 | −It is planned to make this a no-op on that architecture, but for now | |
| 433 | −it should be omitted | |
| 434 | − | |
| 435 | 404 | Following are the arch specific command line options to be used while |
| 436 | 405 | loading dump-capture kernel. |
| 437 | 406 | |
| 438 | −For i386, x86_64 and ia64: | |
| 407 | +For i386 and x86_64: | |
| 439 | 408 | |
| 440 | 409 | "1 irqpoll nr_cpus=1 reset_devices" |
| 441 | 410 | |
| @@ -413,36 +413,6 @@ of a higher page table lookup overhead, and also consumes more page · 412 unmodified lines | ||
| 413 | 413 | table space per process. Used to check whether PAE was enabled in the |
| 414 | 414 | crash kernel when converting virtual addresses to physical addresses. |
| 415 | 415 | |
| 416 | −ia64 | |
| 417 | −==== | |
| 418 | − | |
| 419 | −pgdat_list|(pgdat_list, MAX_NUMNODES) | |
| 420 | −------------------------------------- | |
| 421 | − | |
| 422 | −pg_data_t array storing all NUMA nodes information. MAX_NUMNODES | |
| 423 | −indicates the number of the nodes. | |
| 424 | − | |
| 425 | −node_memblk|(node_memblk, NR_NODE_MEMBLKS) | |
| 426 | −------------------------------------------ | |
| 427 | − | |
| 428 | −List of node memory chunks. Filled when parsing the SRAT table to obtain | |
| 429 | −information about memory nodes. NR_NODE_MEMBLKS indicates the number of | |
| 430 | −node memory chunks. | |
| 431 | − | |
| 432 | −These values are used to compute the number of nodes the crashed kernel used. | |
| 433 | − | |
| 434 | −node_memblk_s|(node_memblk_s, start_paddr)|(node_memblk_s, size) | |
| 435 | −---------------------------------------------------------------- | |
| 436 | − | |
| 437 | −The size of a struct node_memblk_s and the offsets of the | |
| 438 | −node_memblk_s's members. Used to compute the number of nodes. | |
| 439 | − | |
| 440 | −PGTABLE_3|PGTABLE_4 | |
| 441 | −------------------- | |
| 442 | − | |
| 443 | −User-space tools need to know whether the crash kernel was in 3-level or | |
| 444 | −4-level paging mode. Used to distinguish the page table. | |
| 445 | − | |
| 446 | 416 | ARM64 |
| 447 | 417 | ===== |
| 448 | 418 | |
| @@ -1449,7 +1449,7 @@ · 1448 unmodified lines | ||
| 1449 | 1449 | See comment before function elanfreq_setup() in |
| 1450 | 1450 | arch/x86/kernel/cpu/cpufreq/elanfreq.c. |
| 1451 | 1451 | |
| 1452 | − elfcorehdr=[size[KMG]@]offset[KMG] [IA64,PPC,SH,X86,S390] | |
| 1452 | + elfcorehdr=[size[KMG]@]offset[KMG] [PPC,SH,X86,S390] | |
| 1453 | 1453 | Specifies physical address of start of kernel core |
| 1454 | 1454 | image elf header and optionally the size. Generally |
| 1455 | 1455 | kexec loader will pass this option to capture kernel. |
| @@ -1512,12 +1512,6 @@ · 56 unmodified lines | ||
| 1512 | 1512 | floppy= [HW] |
| 1513 | 1513 | See Documentation/admin-guide/blockdev/floppy.rst. |
| 1514 | 1514 | |
| 1515 | − force_pal_cache_flush | |
| 1516 | − [IA-64] Avoid check_sal_cache_flush which may hang on | |
| 1517 | − buggy SAL_CACHE_FLUSH implementations. Using this | |
| 1518 | − parameter will force ia64_sal_cache_flush to call | |
| 1519 | − ia64_pal_cache_flush instead of SAL_CACHE_FLUSH. | |
| 1520 | − | |
| 1521 | 1515 | forcepae [X86-32] |
| 1522 | 1516 | Forcefully enable Physical Address Extension (PAE). |
| 1523 | 1517 | Many Pentium M systems disable PAE but may have a |
| @@ -33,7 +33,7 @@ used to expose persistent memory, other performance-differentiated memory and · 32 unmodified lines | ||
| 33 | 33 | reserved memory regions as ordinary system RAM to Linux. |
| 34 | 34 | |
| 35 | 35 | Linux only supports memory hot(un)plug on selected 64 bit architectures, such as |
| 36 | −x86_64, arm64, ppc64, s390x and ia64. | |
| 36 | +x86_64, arm64, ppc64 and s390x. | |
| 37 | 37 | |
| 38 | 38 | Memory Hot(Un)Plug Granularity |
| 39 | 39 | ------------------------------ |
| @@ -436,7 +436,7 @@ ignore-unaligned-usertrap · 435 unmodified lines | ||
| 436 | 436 | |
| 437 | 437 | On architectures where unaligned accesses cause traps, and where this |
| 438 | 438 | feature is supported (``CONFIG_SYSCTL_ARCH_UNALIGN_NO_WARN``; |
| 439 | −currently, ``arc``, ``ia64`` and ``loongarch``), controls whether all | |
| 439 | +currently, ``arc`` and ``loongarch``), controls whether all | |
| 440 | 440 | unaligned traps are logged. |
| 441 | 441 | |
| 442 | 442 | = ============================================================= |
| @@ -445,10 +445,7 @@ unaligned traps are logged. · 2 unmodified lines | ||
| 445 | 445 | setting. |
| 446 | 446 | = ============================================================= |
| 447 | 447 | |
| 448 | −See also `unaligned-trap`_ and `unaligned-dump-stack`_. On ``ia64``, | |
| 449 | −this allows system administrators to override the | |
| 450 | −``IA64_THREAD_UAC_NOPRINT`` ``prctl`` and avoid logs being flooded. | |
| 451 | − | |
| 448 | +See also `unaligned-trap`_. | |
| 452 | 449 | |
| 453 | 450 | io_uring_disabled |
| 454 | 451 | ================= |
| @@ -1538,22 +1535,6 @@ See Documentation/admin-guide/kernel-parameters.rst and · 1083 unmodified lines | ||
| 1538 | 1535 | Documentation/trace/boottime-trace.rst. |
| 1539 | 1536 | |
| 1540 | 1537 | |
| 1541 | −.. _unaligned-dump-stack: | |
| 1542 | − | |
| 1543 | −unaligned-dump-stack (ia64) | |
| 1544 | −=========================== | |
| 1545 | − | |
| 1546 | −When logging unaligned accesses, controls whether the stack is | |
| 1547 | −dumped. | |
| 1548 | − | |
| 1549 | −= =================================================== | |
| 1550 | −0 Do not dump the stack. This is the default setting. | |
| 1551 | −1 Dump the stack. | |
| 1552 | −= =================================================== | |
| 1553 | − | |
| 1554 | −See also `ignore-unaligned-usertrap`_. | |
| 1555 | − | |
| 1556 | − | |
| 1557 | 1538 | unaligned-trap |
| 1558 | 1539 | ============== |
| 1559 | 1540 | |
| @@ -1,246 +0,0 @@ | ||
| 1 | −================================== | |
| 2 | −Memory Attribute Aliasing on IA-64 | |
| 3 | −================================== | |
| 4 | − | |
| 5 | −Bjorn Helgaas <bjorn.helgaas@hp.com> | |
| 6 | − | |
| 7 | −May 4, 2006 | |
| 8 | − | |
| 9 | − | |
| 10 | −Memory Attributes | |
| 11 | −================= | |
| 12 | − | |
| 13 | − Itanium supports several attributes for virtual memory references. | |
| 14 | − The attribute is part of the virtual translation, i.e., it is | |
| 15 | − contained in the TLB entry. The ones of most interest to the Linux | |
| 16 | − kernel are: | |
| 17 | − | |
| 18 | − == ====================== | |
| 19 | − WB Write-back (cacheable) | |
| 20 | − UC Uncacheable | |
| 21 | − WC Write-coalescing | |
| 22 | − == ====================== | |
| 23 | − | |
| 24 | − System memory typically uses the WB attribute. The UC attribute is | |
| 25 | − used for memory-mapped I/O devices. The WC attribute is uncacheable | |
| 26 | − like UC is, but writes may be delayed and combined to increase | |
| 27 | − performance for things like frame buffers. | |
| 28 | − | |
| 29 | − The Itanium architecture requires that we avoid accessing the same | |
| 30 | − page with both a cacheable mapping and an uncacheable mapping[1]. | |
| 31 | − | |
| 32 | − The design of the chipset determines which attributes are supported | |
| 33 | − on which regions of the address space. For example, some chipsets | |
| 34 | − support either WB or UC access to main memory, while others support | |
| 35 | − only WB access. | |
| 36 | − | |
| 37 | −Memory Map | |
| 38 | −========== | |
| 39 | − | |
| 40 | − Platform firmware describes the physical memory map and the | |
| 41 | − supported attributes for each region. At boot-time, the kernel uses | |
| 42 | − the EFI GetMemoryMap() interface. ACPI can also describe memory | |
| 43 | − devices and the attributes they support, but Linux/ia64 currently | |
| 44 | − doesn't use this information. | |
| 45 | − | |
| 46 | − The kernel uses the efi_memmap table returned from GetMemoryMap() to | |
| 47 | − learn the attributes supported by each region of physical address | |
| 48 | − space. Unfortunately, this table does not completely describe the | |
| 49 | − address space because some machines omit some or all of the MMIO | |
| 50 | − regions from the map. | |
| 51 | − | |
| 52 | − The kernel maintains another table, kern_memmap, which describes the | |
| 53 | − memory Linux is actually using and the attribute for each region. | |
| 54 | − This contains only system memory; it does not contain MMIO space. | |
| 55 | − | |
| 56 | − The kern_memmap table typically contains only a subset of the system | |
| 57 | − memory described by the efi_memmap. Linux/ia64 can't use all memory | |
| 58 | − in the system because of constraints imposed by the identity mapping | |
| 59 | − scheme. | |
| 60 | − | |
| 61 | − The efi_memmap table is preserved unmodified because the original | |
| 62 | − boot-time information is required for kexec. | |
| 63 | − | |
| 64 | −Kernel Identity Mappings | |
| 65 | −======================== | |
| 66 | − | |
| 67 | − Linux/ia64 identity mappings are done with large pages, currently | |
| 68 | − either 16MB or 64MB, referred to as "granules." Cacheable mappings | |
| 69 | − are speculative[2], so the processor can read any location in the | |
| 70 | − page at any time, independent of the programmer's intentions. This | |
| 71 | − means that to avoid attribute aliasing, Linux can create a cacheable | |
| 72 | − identity mapping only when the entire granule supports cacheable | |
| 73 | − access. | |
| 74 | − | |
| 75 | − Therefore, kern_memmap contains only full granule-sized regions that | |
| 76 | − can referenced safely by an identity mapping. | |
| 77 | − | |
| 78 | − Uncacheable mappings are not speculative, so the processor will | |
| 79 | − generate UC accesses only to locations explicitly referenced by | |
| 80 | − software. This allows UC identity mappings to cover granules that | |
| 81 | − are only partially populated, or populated with a combination of UC | |
| 82 | − and WB regions. | |
| 83 | − | |
| 84 | −User Mappings | |
| 85 | −============= | |
| 86 | − | |
| 87 | − User mappings are typically done with 16K or 64K pages. The smaller | |
| 88 | − page size allows more flexibility because only 16K or 64K has to be | |
| 89 | − homogeneous with respect to memory attributes. | |
| 90 | − | |
| 91 | −Potential Attribute Aliasing Cases | |
| 92 | −================================== | |
| 93 | − | |
| 94 | − There are several ways the kernel creates new mappings: | |
| 95 | − | |
| 96 | −mmap of /dev/mem | |
| 97 | −---------------- | |
| 98 | − | |
| 99 | − This uses remap_pfn_range(), which creates user mappings. These | |
| 100 | − mappings may be either WB or UC. If the region being mapped | |
| 101 | − happens to be in kern_memmap, meaning that it may also be mapped | |
| 102 | − by a kernel identity mapping, the user mapping must use the same | |
| 103 | − attribute as the kernel mapping. | |
| 104 | − | |
| 105 | − If the region is not in kern_memmap, the user mapping should use | |
| 106 | − an attribute reported as being supported in the EFI memory map. | |
| 107 | − | |
| 108 | − Since the EFI memory map does not describe MMIO on some | |
| 109 | − machines, this should use an uncacheable mapping as a fallback. | |
| 110 | − | |
| 111 | −mmap of /sys/class/pci_bus/.../legacy_mem | |
| 112 | −----------------------------------------- | |
| 113 | − | |
| 114 | − This is very similar to mmap of /dev/mem, except that legacy_mem | |
| 115 | − only allows mmap of the one megabyte "legacy MMIO" area for a | |
| 116 | − specific PCI bus. Typically this is the first megabyte of | |
| 117 | − physical address space, but it may be different on machines with | |
| 118 | − several VGA devices. | |
| 119 | − | |
| 120 | − "X" uses this to access VGA frame buffers. Using legacy_mem | |
| 121 | − rather than /dev/mem allows multiple instances of X to talk to | |
| 122 | − different VGA cards. | |
| 123 | − | |
| 124 | − The /dev/mem mmap constraints apply. | |
| 125 | − | |
| 126 | −mmap of /proc/bus/pci/.../??.? | |
| 127 | −------------------------------ | |
| 128 | − | |
| 129 | − This is an MMIO mmap of PCI functions, which additionally may or | |
| 130 | − may not be requested as using the WC attribute. | |
| 131 | − | |
| 132 | − If WC is requested, and the region in kern_memmap is either WC | |
| 133 | − or UC, and the EFI memory map designates the region as WC, then | |
| 134 | − the WC mapping is allowed. | |
| 135 | − | |
| 136 | − Otherwise, the user mapping must use the same attribute as the | |
| 137 | − kernel mapping. | |
| 138 | − | |
| 139 | −read/write of /dev/mem | |
| 140 | −---------------------- | |
| 141 | − | |
| 142 | − This uses copy_from_user(), which implicitly uses a kernel | |
| 143 | − identity mapping. This is obviously safe for things in | |
| 144 | − kern_memmap. | |
| 145 | − | |
| 146 | − There may be corner cases of things that are not in kern_memmap, | |
| 147 | − but could be accessed this way. For example, registers in MMIO | |
| 148 | − space are not in kern_memmap, but could be accessed with a UC | |
| 149 | − mapping. This would not cause attribute aliasing. But | |
| 150 | − registers typically can be accessed only with four-byte or | |
| 151 | − eight-byte accesses, and the copy_from_user() path doesn't allow | |
| 152 | − any control over the access size, so this would be dangerous. | |
| 153 | − | |
| 154 | −ioremap() | |
| 155 | −--------- | |
| 156 | − | |
| 157 | − This returns a mapping for use inside the kernel. | |
| 158 | − | |
| 159 | − If the region is in kern_memmap, we should use the attribute | |
| 160 | − specified there. | |
| 161 | − | |
| 162 | − If the EFI memory map reports that the entire granule supports | |
| 163 | − WB, we should use that (granules that are partially reserved | |
| 164 | − or occupied by firmware do not appear in kern_memmap). | |
| 165 | − | |
| 166 | − If the granule contains non-WB memory, but we can cover the | |
| 167 | − region safely with kernel page table mappings, we can use | |
| 168 | − ioremap_page_range() as most other architectures do. | |
| 169 | − | |
| 170 | − Failing all of the above, we have to fall back to a UC mapping. | |
| 171 | − | |
| 172 | −Past Problem Cases | |
| 173 | −================== | |
| 174 | − | |
| 175 | −mmap of various MMIO regions from /dev/mem by "X" on Intel platforms | |
| 176 | −-------------------------------------------------------------------- | |
| 177 | − | |
| 178 | − The EFI memory map may not report these MMIO regions. | |
| 179 | − | |
| 180 | − These must be allowed so that X will work. This means that | |
| 181 | − when the EFI memory map is incomplete, every /dev/mem mmap must | |
| 182 | − succeed. It may create either WB or UC user mappings, depending | |
| 183 | − on whether the region is in kern_memmap or the EFI memory map. | |
| 184 | − | |
| 185 | −mmap of 0x0-0x9FFFF /dev/mem by "hwinfo" on HP sx1000 with VGA enabled | |
| 186 | −---------------------------------------------------------------------- | |
| 187 | − | |
| 188 | − The EFI memory map reports the following attributes: | |
| 189 | − | |
| 190 | − =============== ======= ================== | |
| 191 | − 0x00000-0x9FFFF WB only | |
| 192 | − 0xA0000-0xBFFFF UC only (VGA frame buffer) | |
| 193 | − 0xC0000-0xFFFFF WB only | |
| 194 | − =============== ======= ================== | |
| 195 | − | |
| 196 | − This mmap is done with user pages, not kernel identity mappings, | |
| 197 | − so it is safe to use WB mappings. | |
| 198 | − | |
| 199 | − The kernel VGA driver may ioremap the VGA frame buffer at 0xA0000, | |
| 200 | − which uses a granule-sized UC mapping. This granule will cover some | |
| 201 | − WB-only memory, but since UC is non-speculative, the processor will | |
| 202 | − never generate an uncacheable reference to the WB-only areas unless | |
| 203 | − the driver explicitly touches them. | |
| 204 | − | |
| 205 | −mmap of 0x0-0xFFFFF legacy_mem by "X" | |
| 206 | −------------------------------------- | |
| 207 | − | |
| 208 | − If the EFI memory map reports that the entire range supports the | |
| 209 | − same attributes, we can allow the mmap (and we will prefer WB if | |
| 210 | − supported, as is the case with HP sx[12]000 machines with VGA | |
| 211 | − disabled). | |
| 212 | − | |
| 213 | − If EFI reports the range as partly WB and partly UC (as on sx[12]000 | |
| 214 | − machines with VGA enabled), we must fail the mmap because there's no | |
| 215 | − safe attribute to use. | |
| 216 | − | |
| 217 | − If EFI reports some of the range but not all (as on Intel firmware | |
| 218 | − that doesn't report the VGA frame buffer at all), we should fail the | |
| 219 | − mmap and force the user to map just the specific region of interest. | |
| 220 | − | |
| 221 | −mmap of 0xA0000-0xBFFFF legacy_mem by "X" on HP sx1000 with VGA disabled | |
| 222 | −------------------------------------------------------------------------ | |
| 223 | − | |
| 224 | − The EFI memory map reports the following attributes:: | |
| 225 | − | |
| 226 | − 0x00000-0xFFFFF WB only (no VGA MMIO hole) | |
| 227 | − | |
| 228 | − This is a special case of the previous case, and the mmap should | |
| 229 | − fail for the same reason as above. | |
| 230 | − | |
| 231 | −read of /sys/devices/.../rom | |
| 232 | −---------------------------- | |
| 233 | − | |
| 234 | − For VGA devices, this may cause an ioremap() of 0xC0000. This | |
| 235 | − used to be done with a UC mapping, because the VGA frame buffer | |
| 236 | − at 0xA0000 prevents use of a WB granule. The UC mapping causes | |
| 237 | − an MCA on HP sx[12]000 chipsets. | |
| 238 | − | |
| 239 | − We should use WB page table mappings to avoid covering the VGA | |
| 240 | − frame buffer. | |
| 241 | − | |
| 242 | −Notes | |
| 243 | −===== | |
| 244 | − | |
| 245 | − [1] SDM rev 2.2, vol 2, sec 4.4.1. | |
| 246 | − [2] SDM rev 2.2, vol 2, sec 4.4.6. | |
| @@ -1,144 +0,0 @@ | ||
| 1 | −========================== | |
| 2 | −EFI Real Time Clock driver | |
| 3 | −========================== | |
| 4 | − | |
| 5 | −S. Eranian <eranian@hpl.hp.com> | |
| 6 | − | |
| 7 | −March 2000 | |
| 8 | − | |
| 9 | −1. Introduction | |
| 10 | −=============== | |
| 11 | − | |
| 12 | −This document describes the efirtc.c driver has provided for | |
| 13 | −the IA-64 platform. | |
| 14 | − | |
| 15 | −The purpose of this driver is to supply an API for kernel and user applications | |
| 16 | −to get access to the Time Service offered by EFI version 0.92. | |
| 17 | − | |
| 18 | −EFI provides 4 calls one can make once the OS is booted: GetTime(), | |
| 19 | −SetTime(), GetWakeupTime(), SetWakeupTime() which are all supported by this | |
| 20 | −driver. We describe those calls as well the design of the driver in the | |
| 21 | −following sections. | |
| 22 | − | |
| 23 | −2. Design Decisions | |
| 24 | −=================== | |
| 25 | − | |
| 26 | −The original ideas was to provide a very simple driver to get access to, | |
| 27 | −at first, the time of day service. This is required in order to access, in a | |
| 28 | −portable way, the CMOS clock. A program like /sbin/hwclock uses such a clock | |
| 29 | −to initialize the system view of the time during boot. | |
| 30 | − | |
| 31 | −Because we wanted to minimize the impact on existing user-level apps using | |
| 32 | −the CMOS clock, we decided to expose an API that was very similar to the one | |
| 33 | −used today with the legacy RTC driver (driver/char/rtc.c). However, because | |
| 34 | −EFI provides a simpler services, not all ioctl() are available. Also | |
| 35 | −new ioctl()s have been introduced for things that EFI provides but not the | |
| 36 | −legacy. | |
| 37 | − | |
| 38 | −EFI uses a slightly different way of representing the time, noticeably | |
| 39 | −the reference date is different. Year is the using the full 4-digit format. | |
| 40 | −The Epoch is January 1st 1998. For backward compatibility reasons we don't | |
| 41 | −expose this new way of representing time. Instead we use something very | |
| 42 | −similar to the struct tm, i.e. struct rtc_time, as used by hwclock. | |
| 43 | −One of the reasons for doing it this way is to allow for EFI to still evolve | |
| 44 | −without necessarily impacting any of the user applications. The decoupling | |
| 45 | −enables flexibility and permits writing wrapper code is ncase things change. | |
| 46 | − | |
| 47 | −The driver exposes two interfaces, one via the device file and a set of | |
| 48 | −ioctl()s. The other is read-only via the /proc filesystem. | |
| 49 | − | |
| 50 | −As of today we don't offer a /proc/sys interface. | |
| 51 | − | |
| 52 | −To allow for a uniform interface between the legacy RTC and EFI time service, | |
| 53 | −we have created the include/linux/rtc.h header file to contain only the | |
| 54 | −"public" API of the two drivers. The specifics of the legacy RTC are still | |
| 55 | −in include/linux/mc146818rtc.h. | |
| 56 | − | |
| 57 | − | |
| 58 | −3. Time of day service | |
| 59 | −====================== | |
| 60 | − | |
| 61 | −The part of the driver gives access to the time of day service of EFI. | |
| 62 | −Two ioctl()s, compatible with the legacy RTC calls: | |
| 63 | − | |
| 64 | − Read the CMOS clock:: | |
| 65 | − | |
| 66 | − ioctl(d, RTC_RD_TIME, &rtc); | |
| 67 | − | |
| 68 | − Write the CMOS clock:: | |
| 69 | − | |
| 70 | − ioctl(d, RTC_SET_TIME, &rtc); | |
| 71 | − | |
| 72 | −The rtc is a pointer to a data structure defined in rtc.h which is close | |
| 73 | −to a struct tm:: | |
| 74 | − | |
| 75 | − struct rtc_time { | |
| 76 | − int tm_sec; | |
| 77 | − int tm_min; | |
| 78 | − int tm_hour; | |
| 79 | − int tm_mday; | |
| 80 | − int tm_mon; | |
| 81 | − int tm_year; | |
| 82 | − int tm_wday; | |
| 83 | − int tm_yday; | |
| 84 | − int tm_isdst; | |
| 85 | − }; | |
| 86 | − | |
| 87 | −The driver takes care of converting back an forth between the EFI time and | |
| 88 | −this format. | |
| 89 | − | |
| 90 | −Those two ioctl()s can be exercised with the hwclock command: | |
| 91 | − | |
| 92 | −For reading:: | |
| 93 | − | |
| 94 | − # /sbin/hwclock --show | |
| 95 | − Mon Mar 6 15:32:32 2000 -0.910248 seconds | |
| 96 | − | |
| 97 | −For setting:: | |
| 98 | − | |
| 99 | − # /sbin/hwclock --systohc | |
| 100 | − | |
| 101 | −Root privileges are required to be able to set the time of day. | |
| 102 | − | |
| 103 | −4. Wakeup Alarm service | |
| 104 | −======================= | |
| 105 | − | |
| 106 | −EFI provides an API by which one can program when a machine should wakeup, | |
| 107 | −i.e. reboot. This is very different from the alarm provided by the legacy | |
| 108 | −RTC which is some kind of interval timer alarm. For this reason we don't use | |
| 109 | −the same ioctl()s to get access to the service. Instead we have | |
| 110 | −introduced 2 news ioctl()s to the interface of an RTC. | |
| 111 | − | |
| 112 | −We have added 2 new ioctl()s that are specific to the EFI driver: | |
| 113 | − | |
| 114 | − Read the current state of the alarm:: | |
| 115 | − | |
| 116 | − ioctl(d, RTC_WKALM_RD, &wkt) | |
| 117 | − | |
| 118 | − Set the alarm or change its status:: | |
| 119 | − | |
| 120 | − ioctl(d, RTC_WKALM_SET, &wkt) | |
| 121 | − | |
| 122 | −The wkt structure encapsulates a struct rtc_time + 2 extra fields to get | |
| 123 | −status information:: | |
| 124 | − | |
| 125 | − struct rtc_wkalrm { | |
| 126 | − | |
| 127 | − unsigned char enabled; /* =1 if alarm is enabled */ | |
| 128 | − unsigned char pending; /* =1 if alarm is pending */ | |
| 129 | − | |
| 130 | − struct rtc_time time; | |
| 131 | − } | |
| 132 | − | |
| 133 | −As of today, none of the existing user-level apps supports this feature. | |
| 134 | −However writing such a program should be hard by simply using those two | |
| 135 | −ioctl(). | |
| 136 | − | |
| 137 | −Root privileges are required to be able to set the alarm. | |
| 138 | − | |
| 139 | −5. References | |
| 140 | −============= | |
| 141 | − | |
| 142 | −Checkout the following Web site for more information on EFI: | |
| 143 | − | |
| 144 | −http://developer.intel.com/technology/efi/ | |
| @@ -1,1067 +0,0 @@ | ||
| 1 | −======================================== | |
| 2 | −IPF Machine Check (MC) error inject tool | |
| 3 | −======================================== | |
| 4 | − | |
| 5 | −IPF Machine Check (MC) error inject tool is used to inject MC | |
| 6 | −errors from Linux. The tool is a test bed for IPF MC work flow including | |
| 7 | −hardware correctable error handling, OS recoverable error handling, MC | |
| 8 | −event logging, etc. | |
| 9 | − | |
| 10 | −The tool includes two parts: a kernel driver and a user application | |
| 11 | −sample. The driver provides interface to PAL to inject error | |
| 12 | −and query error injection capabilities. The driver code is in | |
| 13 | −arch/ia64/kernel/err_inject.c. The application sample (shown below) | |
| 14 | −provides a combination of various errors and calls the driver's interface | |
| 15 | −(sysfs interface) to inject errors or query error injection capabilities. | |
| 16 | − | |
| 17 | −The tool can be used to test Intel IPF machine MC handling capabilities. | |
| 18 | −It's especially useful for people who can not access hardware MC injection | |
| 19 | −tool to inject error. It's also very useful to integrate with other | |
| 20 | −software test suits to do stressful testing on IPF. | |
| 21 | − | |
| 22 | −Below is a sample application as part of the whole tool. The sample | |
| 23 | −can be used as a working test tool. Or it can be expanded to include | |
| 24 | −more features. It also can be a integrated into a library or other user | |
| 25 | −application to have more thorough test. | |
| 26 | − | |
| 27 | −The sample application takes err.conf as error configuration input. GCC | |
| 28 | −compiles the code. After you install err_inject driver, you can run | |
| 29 | −this sample application to inject errors. | |
| 30 | − | |
| 31 | −Errata: Itanium 2 Processors Specification Update lists some errata against | |
| 32 | −the pal_mc_error_inject PAL procedure. The following err.conf has been tested | |
| 33 | −on latest Montecito PAL. | |
| 34 | − | |
| 35 | −err.conf:: | |
| 36 | − | |
| 37 | − #This is configuration file for err_inject_tool. | |
| 38 | − #The format of the each line is: | |
| 39 | − #cpu, loop, interval, err_type_info, err_struct_info, err_data_buffer | |
| 40 | − #where | |
| 41 | − # cpu: logical cpu number the error will be inject in. | |
| 42 | − # loop: times the error will be injected. | |
| 43 | − # interval: In second. every so often one error is injected. | |
| 44 | − # err_type_info, err_struct_info: PAL parameters. | |
| 45 | − # | |
| 46 | − #Note: All values are hex w/o or w/ 0x prefix. | |
| 47 | − | |
| 48 | − | |
| 49 | − #On cpu2, inject only total 0x10 errors, interval 5 seconds | |
| 50 | − #corrected, data cache, hier-2, physical addr(assigned by tool code). | |
| 51 | − #working on Montecito latest PAL. | |
| 52 | − 2, 10, 5, 4101, 95 | |
| 53 | − | |
| 54 | − #On cpu4, inject and consume total 0x10 errors, interval 5 seconds | |
| 55 | − #corrected, data cache, hier-2, physical addr(assigned by tool code). | |
| 56 | − #working on Montecito latest PAL. | |
| 57 | − 4, 10, 5, 4109, 95 | |
| 58 | − | |
| 59 | − #On cpu15, inject and consume total 0x10 errors, interval 5 seconds | |
| 60 | − #recoverable, DTR0, hier-2. | |
| 61 | − #working on Montecito latest PAL. | |
| 62 | − 0xf, 0x10, 5, 4249, 15 | |
| 63 | − | |
| 64 | −The sample application source code: | |
| 65 | − | |
| 66 | −err_injection_tool.c:: | |
| 67 | − | |
| 68 | − /* | |
| 69 | − * This program is free software; you can redistribute it and/or modify | |
| 70 | − * it under the terms of the GNU General Public License as published by | |
| 71 | − * the Free Software Foundation; either version 2 of the License, or | |
| 72 | − * (at your option) any later version. | |
| 73 | − * | |
| 74 | − * This program is distributed in the hope that it will be useful, but | |
| 75 | − * WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 76 | − * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
| 77 | − * NON INFRINGEMENT. See the GNU General Public License for more | |
| 78 | − * details. | |
| 79 | − * | |
| 80 | − * You should have received a copy of the GNU General Public License | |
| 81 | − * along with this program; if not, write to the Free Software | |
| 82 | − * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
| 83 | − * | |
| 84 | − * Copyright (C) 2006 Intel Co | |
| 85 | − * Fenghua Yu <fenghua.yu@intel.com> | |
| 86 | − * | |
| 87 | − */ | |
| 88 | − #include <sys/types.h> | |
| 89 | − #include <sys/stat.h> | |
| 90 | − #include <fcntl.h> | |
| 91 | − #include <stdio.h> | |
| 92 | − #include <sched.h> | |
| 93 | − #include <unistd.h> | |
| 94 | − #include <stdlib.h> | |
| 95 | − #include <stdarg.h> | |
| 96 | − #include <string.h> | |
| 97 | − #include <errno.h> | |
| 98 | − #include <time.h> | |
| 99 | − #include <sys/ipc.h> | |
| 100 | − #include <sys/sem.h> | |
| 101 | − #include <sys/wait.h> | |
| 102 | − #include <sys/mman.h> | |
| 103 | − #include <sys/shm.h> | |
| 104 | − | |
| 105 | − #define MAX_FN_SIZE 256 | |
| 106 | − #define MAX_BUF_SIZE 256 | |
| 107 | − #define DATA_BUF_SIZE 256 | |
| 108 | − #define NR_CPUS 512 | |
| 109 | − #define MAX_TASK_NUM 2048 | |
| 110 | − #define MIN_INTERVAL 5 // seconds | |
| 111 | − #define ERR_DATA_BUFFER_SIZE 3 // Three 8-byte. | |
| 112 | − #define PARA_FIELD_NUM 5 | |
| 113 | − #define MASK_SIZE (NR_CPUS/64) | |
| 114 | − #define PATH_FORMAT "/sys/devices/system/cpu/cpu%d/err_inject/" | |
| 115 | − | |
| 116 | − int sched_setaffinity(pid_t pid, unsigned int len, unsigned long *mask); | |
| 117 | − | |
| 118 | − int verbose; | |
| 119 | − #define vbprintf if (verbose) printf | |
| 120 | − | |
| 121 | − int log_info(int cpu, const char *fmt, ...) | |
| 122 | − { | |
| 123 | − FILE *log; | |
| 124 | − char fn[MAX_FN_SIZE]; | |
| 125 | − char buf[MAX_BUF_SIZE]; | |
| 126 | − va_list args; | |
| 127 | − | |
| 128 | − sprintf(fn, "%d.log", cpu); | |
| 129 | − log=fopen(fn, "a+"); | |
| 130 | − if (log==NULL) { | |
| 131 | − perror("Error open:"); | |
| 132 | − return -1; | |
| 133 | − } | |
| 134 | − | |
| 135 | − va_start(args, fmt); | |
| 136 | − vprintf(fmt, args); | |
| 137 | − memset(buf, 0, MAX_BUF_SIZE); | |
| 138 | − vsprintf(buf, fmt, args); | |
| 139 | − va_end(args); | |
| 140 | − | |
| 141 | − fwrite(buf, sizeof(buf), 1, log); | |
| 142 | − fclose(log); | |
| 143 | − | |
| 144 | − return 0; | |
| 145 | − } | |
| 146 | − | |
| 147 | − typedef unsigned long u64; | |
| 148 | − typedef unsigned int u32; | |
| 149 | − | |
| 150 | − typedef union err_type_info_u { | |
| 151 | − struct { | |
| 152 | − u64 mode : 3, /* 0-2 */ | |
| 153 | − err_inj : 3, /* 3-5 */ | |
| 154 | − err_sev : 2, /* 6-7 */ | |
| 155 | − err_struct : 5, /* 8-12 */ | |
| 156 | − struct_hier : 3, /* 13-15 */ | |
| 157 | − reserved : 48; /* 16-63 */ | |
| 158 | − } err_type_info_u; | |
| 159 | − u64 err_type_info; | |
| 160 | − } err_type_info_t; | |
| 161 | − | |
| 162 | − typedef union err_struct_info_u { | |
| 163 | − struct { | |
| 164 | − u64 siv : 1, /* 0 */ | |
| 165 | − c_t : 2, /* 1-2 */ | |
| 166 | − cl_p : 3, /* 3-5 */ | |
| 167 | − cl_id : 3, /* 6-8 */ | |
| 168 | − cl_dp : 1, /* 9 */ | |
| 169 | − reserved1 : 22, /* 10-31 */ | |
| 170 | − tiv : 1, /* 32 */ | |
| 171 | − trigger : 4, /* 33-36 */ | |
| 172 | − trigger_pl : 3, /* 37-39 */ | |
| 173 | − reserved2 : 24; /* 40-63 */ | |
| 174 | − } err_struct_info_cache; | |
| 175 | − struct { | |
| 176 | − u64 siv : 1, /* 0 */ | |
| 177 | − tt : 2, /* 1-2 */ | |
| 178 | − tc_tr : 2, /* 3-4 */ | |
| 179 | − tr_slot : 8, /* 5-12 */ | |
| 180 | − reserved1 : 19, /* 13-31 */ | |
| 181 | − tiv : 1, /* 32 */ | |
| 182 | − trigger : 4, /* 33-36 */ | |
| 183 | − trigger_pl : 3, /* 37-39 */ | |
| 184 | − reserved2 : 24; /* 40-63 */ | |
| 185 | − } err_struct_info_tlb; | |
| 186 | − struct { | |
| 187 | − u64 siv : 1, /* 0 */ | |
| 188 | − regfile_id : 4, /* 1-4 */ | |
| 189 | − reg_num : 7, /* 5-11 */ | |
| 190 | − reserved1 : 20, /* 12-31 */ | |
| 191 | − tiv : 1, /* 32 */ | |
| 192 | − trigger : 4, /* 33-36 */ | |
| 193 | − trigger_pl : 3, /* 37-39 */ | |
| 194 | − reserved2 : 24; /* 40-63 */ | |
| 195 | − } err_struct_info_register; | |
| 196 | − struct { | |
| 197 | − u64 reserved; | |
| 198 | − } err_struct_info_bus_processor_interconnect; | |
| 199 | − u64 err_struct_info; | |
| 200 | − } err_struct_info_t; | |
| 201 | − | |
| 202 | − typedef union err_data_buffer_u { | |
| 203 | − struct { | |
| 204 | − u64 trigger_addr; /* 0-63 */ | |
| 205 | − u64 inj_addr; /* 64-127 */ | |
| 206 | − u64 way : 5, /* 128-132 */ | |
| 207 | − index : 20, /* 133-152 */ | |
| 208 | − : 39; /* 153-191 */ | |
| 209 | − } err_data_buffer_cache; | |
| 210 | − struct { | |
| 211 | − u64 trigger_addr; /* 0-63 */ | |
| 212 | − u64 inj_addr; /* 64-127 */ | |
| 213 | − u64 way : 5, /* 128-132 */ | |
| 214 | − index : 20, /* 133-152 */ | |
| 215 | − reserved : 39; /* 153-191 */ | |
| 216 | − } err_data_buffer_tlb; | |
| 217 | − struct { | |
| 218 | − u64 trigger_addr; /* 0-63 */ | |
| 219 | − } err_data_buffer_register; | |
| 220 | − struct { | |
| 221 | − u64 reserved; /* 0-63 */ | |
| 222 | − } err_data_buffer_bus_processor_interconnect; | |
| 223 | − u64 err_data_buffer[ERR_DATA_BUFFER_SIZE]; | |
| 224 | − } err_data_buffer_t; | |
| 225 | − | |
| 226 | − typedef union capabilities_u { | |
| 227 | − struct { | |
| 228 | − u64 i : 1, | |
| 229 | − d : 1, | |
| 230 | − rv : 1, | |
| 231 | − tag : 1, | |
| 232 | − data : 1, | |
| 233 | − mesi : 1, | |
| 234 | − dp : 1, | |
| 235 | − reserved1 : 3, | |
| 236 | − pa : 1, | |
| 237 | − va : 1, | |
| 238 | − wi : 1, | |
| 239 | − reserved2 : 20, | |
| 240 | − trigger : 1, | |
| 241 | − trigger_pl : 1, | |
| 242 | − reserved3 : 30; | |
| 243 | − } capabilities_cache; | |
| 244 | − struct { | |
| 245 | − u64 d : 1, | |
| 246 | − i : 1, | |
| 247 | − rv : 1, | |
| 248 | − tc : 1, | |
| 249 | − tr : 1, | |
| 250 | − reserved1 : 27, | |
| 251 | − trigger : 1, | |
| 252 | − trigger_pl : 1, | |
| 253 | − reserved2 : 30; | |
| 254 | − } capabilities_tlb; | |
| 255 | − struct { | |
| 256 | − u64 gr_b0 : 1, | |
| 257 | − gr_b1 : 1, | |
| 258 | − fr : 1, | |
| 259 | − br : 1, | |
| 260 | − pr : 1, | |
| 261 | − ar : 1, | |
| 262 | − cr : 1, | |
| 263 | − rr : 1, | |
| 264 | − pkr : 1, | |
| 265 | − dbr : 1, | |
| 266 | − ibr : 1, | |
| 267 | − pmc : 1, | |
| 268 | − pmd : 1, | |
| 269 | − reserved1 : 3, | |
| 270 | − regnum : 1, | |
| 271 | − reserved2 : 15, | |
| 272 | − trigger : 1, | |
| 273 | − trigger_pl : 1, | |
| 274 | − reserved3 : 30; | |
| 275 | − } capabilities_register; | |
| 276 | − struct { | |
| 277 | − u64 reserved; | |
| 278 | − } capabilities_bus_processor_interconnect; | |
| 279 | − } capabilities_t; | |
| 280 | − | |
| 281 | − typedef struct resources_s { | |
| 282 | − u64 ibr0 : 1, | |
| 283 | − ibr2 : 1, | |
| 284 | − ibr4 : 1, | |
| 285 | − ibr6 : 1, | |
| 286 | − dbr0 : 1, | |
| 287 | − dbr2 : 1, | |
| 288 | − dbr4 : 1, | |
| 289 | − dbr6 : 1, | |
| 290 | − reserved : 48; | |
| 291 | − } resources_t; | |
| 292 | − | |
| 293 | − | |
| 294 | − long get_page_size(void) | |
| 295 | − { | |
| 296 | − long page_size=sysconf(_SC_PAGESIZE); | |
| 297 | − return page_size; | |
| 298 | − } | |
| 299 | − | |
| 300 | − #define PAGE_SIZE (get_page_size()==-1?0x4000:get_page_size()) | |
| 301 | − #define SHM_SIZE (2*PAGE_SIZE*NR_CPUS) | |
| 302 | − #define SHM_VA 0x2000000100000000 | |
| 303 | − | |
| 304 | − int shmid; | |
| 305 | − void *shmaddr; | |
| 306 | − | |
| 307 | − int create_shm(void) | |
| 308 | − { | |
| 309 | − key_t key; | |
| 310 | − char fn[MAX_FN_SIZE]; | |
| 311 | − | |
| 312 | − /* cpu0 is always existing */ | |
| 313 | − sprintf(fn, PATH_FORMAT, 0); | |
| 314 | − if ((key = ftok(fn, 's')) == -1) { | |
| 315 | − perror("ftok"); | |
| 316 | − return -1; | |
| 317 | − } | |
| 318 | − | |
| 319 | − shmid = shmget(key, SHM_SIZE, 0644 | IPC_CREAT); | |
| 320 | − if (shmid == -1) { | |
| 321 | − if (errno==EEXIST) { | |
| 322 | − shmid = shmget(key, SHM_SIZE, 0); | |
| 323 | − if (shmid == -1) { | |
| 324 | − perror("shmget"); | |
| 325 | − return -1; | |
| 326 | − } | |
| 327 | − } | |
| 328 | − else { | |
| 329 | − perror("shmget"); | |
| 330 | − return -1; | |
| 331 | − } | |
| 332 | − } | |
| 333 | − vbprintf("shmid=%d", shmid); | |
| 334 | − | |
| 335 | − /* connect to the segment: */ | |
| 336 | − shmaddr = shmat(shmid, (void *)SHM_VA, 0); | |
| 337 | − if (shmaddr == (void*)-1) { | |
| 338 | − perror("shmat"); | |
| 339 | − return -1; | |
| 340 | − } | |
| 341 | − | |
| 342 | − memset(shmaddr, 0, SHM_SIZE); | |
| 343 | − mlock(shmaddr, SHM_SIZE); | |
| 344 | − | |
| 345 | − return 0; | |
| 346 | − } | |
| 347 | − | |
| 348 | − int free_shm() | |
| 349 | − { | |
| 350 | − munlock(shmaddr, SHM_SIZE); | |
| 351 | − shmdt(shmaddr); | |
| 352 | − semctl(shmid, 0, IPC_RMID); | |
| 353 | − | |
| 354 | − return 0; | |
| 355 | − } | |
| 356 | − | |
| 357 | − #ifdef _SEM_SEMUN_UNDEFINED | |
| 358 | − union semun | |
| 359 | − { | |
| 360 | − int val; | |
| 361 | − struct semid_ds *buf; | |
| 362 | − unsigned short int *array; | |
| 363 | − struct seminfo *__buf; | |
| 364 | − }; | |
| 365 | − #endif | |
| 366 | − | |
| 367 | − u32 mode=1; /* 1: physical mode; 2: virtual mode. */ | |
| 368 | − int one_lock=1; | |
| 369 | − key_t key[NR_CPUS]; | |
| 370 | − int semid[NR_CPUS]; | |
| 371 | − | |
| 372 | − int create_sem(int cpu) | |
| 373 | − { | |
| 374 | − union semun arg; | |
| 375 | − char fn[MAX_FN_SIZE]; | |
| 376 | − int sid; | |
| 377 | − | |
| 378 | − sprintf(fn, PATH_FORMAT, cpu); | |
| 379 | − sprintf(fn, "%s/%s", fn, "err_type_info"); | |
| 380 | − if ((key[cpu] = ftok(fn, 'e')) == -1) { | |
| 381 | − perror("ftok"); | |
| 382 | − return -1; | |
| 383 | − } | |
| 384 | − | |
| 385 | − if (semid[cpu]!=0) | |
| 386 | − return 0; | |
| 387 | − | |
| 388 | − /* clear old semaphore */ | |
| 389 | − if ((sid = semget(key[cpu], 1, 0)) != -1) | |
| 390 | − semctl(sid, 0, IPC_RMID); | |
| 391 | − | |
| 392 | − /* get one semaphore */ | |
| 393 | − if ((semid[cpu] = semget(key[cpu], 1, IPC_CREAT | IPC_EXCL)) == -1) { | |
| 394 | − perror("semget"); | |
| 395 | − printf("Please remove semaphore with key=0x%lx, then run the tool.\n", | |
| 396 | − (u64)key[cpu]); | |
| 397 | − return -1; | |
| 398 | − } | |
| 399 | − | |
| 400 | − vbprintf("semid[%d]=0x%lx, key[%d]=%lx\n",cpu,(u64)semid[cpu],cpu, | |
| 401 | − (u64)key[cpu]); | |
| 402 | − /* initialize the semaphore to 1: */ | |
| 403 | − arg.val = 1; | |
| 404 | − if (semctl(semid[cpu], 0, SETVAL, arg) == -1) { | |
| 405 | − perror("semctl"); | |
| 406 | − return -1; | |
| 407 | − } | |
| 408 | − | |
| 409 | − return 0; | |
| 410 | − } | |
| 411 | − | |
| 412 | − static int lock(int cpu) | |
| 413 | − { | |
| 414 | − struct sembuf lock; | |
| 415 | − | |
| 416 | − lock.sem_num = cpu; | |
| 417 | − lock.sem_op = 1; | |
| 418 | − semop(semid[cpu], &lock, 1); | |
| 419 | − | |
| 420 | − return 0; | |
| 421 | − } | |
| 422 | − | |
| 423 | − static int unlock(int cpu) | |
| 424 | − { | |
| 425 | − struct sembuf unlock; | |
| 426 | − | |
| 427 | − unlock.sem_num = cpu; | |
| 428 | − unlock.sem_op = -1; | |
| 429 | − semop(semid[cpu], &unlock, 1); | |
| 430 | − | |
| 431 | − return 0; | |
| 432 | − } | |
| 433 | − | |
| 434 | − void free_sem(int cpu) | |
| 435 | − { | |
| 436 | − semctl(semid[cpu], 0, IPC_RMID); | |
| 437 | − } | |
| 438 | − | |
| 439 | − int wr_multi(char *fn, unsigned long *data, int size) | |
| 440 | − { | |
| 441 | − int fd; | |
| 442 | − char buf[MAX_BUF_SIZE]; | |
| 443 | − int ret; | |
| 444 | − | |
| 445 | − if (size==1) | |
| 446 | − sprintf(buf, "%lx", *data); | |
| 447 | − else if (size==3) | |
| 448 | − sprintf(buf, "%lx,%lx,%lx", data[0], data[1], data[2]); | |
| 449 | − else { | |
| 450 | − fprintf(stderr,"write to file with wrong size!\n"); | |
| 451 | − return -1; | |
| 452 | − } | |
| 453 | − | |
| 454 | − fd=open(fn, O_RDWR); | |
| 455 | − if (!fd) { | |
| 456 | − perror("Error:"); | |
| 457 | − return -1; | |
| 458 | − } | |
| 459 | − ret=write(fd, buf, sizeof(buf)); | |
| 460 | − close(fd); | |
| 461 | − return ret; | |
| 462 | − } | |
| 463 | − | |
| 464 | − int wr(char *fn, unsigned long data) | |
| 465 | − { | |
| 466 | − return wr_multi(fn, &data, 1); | |
| 467 | − } | |
| 468 | − | |
| 469 | − int rd(char *fn, unsigned long *data) | |
| 470 | − { | |
| 471 | − int fd; | |
| 472 | − char buf[MAX_BUF_SIZE]; | |
| 473 | − | |
| 474 | − fd=open(fn, O_RDONLY); | |
| 475 | − if (fd<0) { | |
| 476 | − perror("Error:"); | |
| 477 | − return -1; | |
| 478 | − } | |
| 479 | − read(fd, buf, MAX_BUF_SIZE); | |
| 480 | − *data=strtoul(buf, NULL, 16); | |
| 481 | − close(fd); | |
| 482 | − return 0; | |
| 483 | − } | |
| 484 | − | |
| 485 | − int rd_status(char *path, int *status) | |
| 486 | − { | |
| 487 | − char fn[MAX_FN_SIZE]; | |
| 488 | − sprintf(fn, "%s/status", path); | |
| 489 | − if (rd(fn, (u64*)status)<0) { | |
| 490 | − perror("status reading error.\n"); | |
| 491 | − return -1; | |
| 492 | − } | |
| 493 | − | |
| 494 | − return 0; | |
| 495 | − } | |
| 496 | − | |
| 497 | − int rd_capabilities(char *path, u64 *capabilities) | |
| 498 | − { | |
| 499 | − char fn[MAX_FN_SIZE]; | |
| 500 | − sprintf(fn, "%s/capabilities", path); | |
| 501 | − if (rd(fn, capabilities)<0) { | |
| 502 | − perror("capabilities reading error.\n"); | |
| 503 | − return -1; | |
| 504 | − } | |
| 505 | − | |
| 506 | − return 0; | |
| 507 | − } | |
| 508 | − | |
| 509 | − int rd_all(char *path) | |
| 510 | − { | |
| 511 | − unsigned long err_type_info, err_struct_info, err_data_buffer; | |
| 512 | − int status; | |
| 513 | − unsigned long capabilities, resources; | |
| 514 | − char fn[MAX_FN_SIZE]; | |
| 515 | − | |
| 516 | − sprintf(fn, "%s/err_type_info", path); | |
| 517 | − if (rd(fn, &err_type_info)<0) { | |
| 518 | − perror("err_type_info reading error.\n"); | |
| 519 | − return -1; | |
| 520 | − } | |
| 521 | − printf("err_type_info=%lx\n", err_type_info); | |
| 522 | − | |
| 523 | − sprintf(fn, "%s/err_struct_info", path); | |
| 524 | − if (rd(fn, &err_struct_info)<0) { | |
| 525 | − perror("err_struct_info reading error.\n"); | |
| 526 | − return -1; | |
| 527 | − } | |
| 528 | − printf("err_struct_info=%lx\n", err_struct_info); | |
| 529 | − | |
| 530 | − sprintf(fn, "%s/err_data_buffer", path); | |
| 531 | − if (rd(fn, &err_data_buffer)<0) { | |
| 532 | − perror("err_data_buffer reading error.\n"); | |
| 533 | − return -1; | |
| 534 | − } | |
| 535 | − printf("err_data_buffer=%lx\n", err_data_buffer); | |
| 536 | − | |
| 537 | − sprintf(fn, "%s/status", path); | |
| 538 | − if (rd("status", (u64*)&status)<0) { | |
| 539 | − perror("status reading error.\n"); | |
| 540 | − return -1; | |
| 541 | − } | |
| 542 | − printf("status=%d\n", status); | |
| 543 | − | |
| 544 | − sprintf(fn, "%s/capabilities", path); | |
| 545 | − if (rd(fn,&capabilities)<0) { | |
| 546 | − perror("capabilities reading error.\n"); | |
| 547 | − return -1; | |
| 548 | − } | |
| 549 | − printf("capabilities=%lx\n", capabilities); | |
| 550 | − | |
| 551 | − sprintf(fn, "%s/resources", path); | |
| 552 | − if (rd(fn, &resources)<0) { | |
| 553 | − perror("resources reading error.\n"); | |
| 554 | − return -1; | |
| 555 | − } | |
| 556 | − printf("resources=%lx\n", resources); | |
| 557 | − | |
| 558 | − return 0; | |
| 559 | − } | |
| 560 | − | |
| 561 | − int query_capabilities(char *path, err_type_info_t err_type_info, | |
| 562 | − u64 *capabilities) | |
| 563 | − { | |
| 564 | − char fn[MAX_FN_SIZE]; | |
| 565 | − err_struct_info_t err_struct_info; | |
| 566 | − err_data_buffer_t err_data_buffer; | |
| 567 | − | |
| 568 | − err_struct_info.err_struct_info=0; | |
| 569 | − memset(err_data_buffer.err_data_buffer, -1, ERR_DATA_BUFFER_SIZE*8); | |
| 570 | − | |
| 571 | − sprintf(fn, "%s/err_type_info", path); | |
| 572 | − wr(fn, err_type_info.err_type_info); | |
| 573 | − sprintf(fn, "%s/err_struct_info", path); | |
| 574 | − wr(fn, 0x0); | |
| 575 | − sprintf(fn, "%s/err_data_buffer", path); | |
| 576 | − wr_multi(fn, err_data_buffer.err_data_buffer, ERR_DATA_BUFFER_SIZE); | |
| 577 | − | |
| 578 | − // Fire pal_mc_error_inject procedure. | |
| 579 | − sprintf(fn, "%s/call_start", path); | |
| 580 | − wr(fn, mode); | |
| 581 | − | |
| 582 | − if (rd_capabilities(path, capabilities)<0) | |
| 583 | − return -1; | |
| 584 | − | |
| 585 | − return 0; | |
| 586 | − } | |
| 587 | − | |
| 588 | − int query_all_capabilities() | |
| 589 | − { | |
| 590 | − int status; | |
| 591 | − err_type_info_t err_type_info; | |
| 592 | − int err_sev, err_struct, struct_hier; | |
| 593 | − int cap=0; | |
| 594 | − u64 capabilities; | |
| 595 | − char path[MAX_FN_SIZE]; | |
| 596 | − | |
| 597 | − err_type_info.err_type_info=0; // Initial | |
| 598 | − err_type_info.err_type_info_u.mode=0; // Query mode; | |
| 599 | − err_type_info.err_type_info_u.err_inj=0; | |
| 600 | − | |
| 601 | − printf("All capabilities implemented in pal_mc_error_inject:\n"); | |
| 602 | − sprintf(path, PATH_FORMAT ,0); | |
| 603 | − for (err_sev=0;err_sev<3;err_sev++) | |
| 604 | − for (err_struct=0;err_struct<5;err_struct++) | |
| 605 | − for (struct_hier=0;struct_hier<5;struct_hier++) | |
| 606 | − { | |
| 607 | − status=-1; | |
| 608 | − capabilities=0; | |
| 609 | − err_type_info.err_type_info_u.err_sev=err_sev; | |
| 610 | − err_type_info.err_type_info_u.err_struct=err_struct; | |
| 611 | − err_type_info.err_type_info_u.struct_hier=struct_hier; | |
| 612 | − | |
| 613 | − if (query_capabilities(path, err_type_info, &capabilities)<0) | |
| 614 | − continue; | |
| 615 | − | |
| 616 | − if (rd_status(path, &status)<0) | |
| 617 | − continue; | |
| 618 | − | |
| 619 | − if (status==0) { | |
| 620 | − cap=1; | |
| 621 | − printf("For err_sev=%d, err_struct=%d, struct_hier=%d: ", | |
| 622 | − err_sev, err_struct, struct_hier); | |
| 623 | − printf("capabilities 0x%lx\n", capabilities); | |
| 624 | − } | |
| 625 | − } | |
| 626 | − if (!cap) { | |
| 627 | − printf("No capabilities supported.\n"); | |
| 628 | − return 0; | |
| 629 | − } | |
| 630 | − | |
| 631 | − return 0; | |
| 632 | − } | |
| 633 | − | |
| 634 | − int err_inject(int cpu, char *path, err_type_info_t err_type_info, | |
| 635 | − err_struct_info_t err_struct_info, | |
| 636 | − err_data_buffer_t err_data_buffer) | |
| 637 | − { | |
| 638 | − int status; | |
| 639 | − char fn[MAX_FN_SIZE]; | |
| 640 | − | |
| 641 | − log_info(cpu, "err_type_info=%lx, err_struct_info=%lx, ", | |
| 642 | − err_type_info.err_type_info, | |
| 643 | − err_struct_info.err_struct_info); | |
| 644 | − log_info(cpu,"err_data_buffer=[%lx,%lx,%lx]\n", | |
| 645 | − err_data_buffer.err_data_buffer[0], | |
| 646 | − err_data_buffer.err_data_buffer[1], | |
| 647 | − err_data_buffer.err_data_buffer[2]); | |
| 648 | − sprintf(fn, "%s/err_type_info", path); | |
| 649 | − wr(fn, err_type_info.err_type_info); | |
| 650 | − sprintf(fn, "%s/err_struct_info", path); | |
| 651 | − wr(fn, err_struct_info.err_struct_info); | |
| 652 | − sprintf(fn, "%s/err_data_buffer", path); | |
| 653 | − wr_multi(fn, err_data_buffer.err_data_buffer, ERR_DATA_BUFFER_SIZE); | |
| 654 | − | |
| 655 | − // Fire pal_mc_error_inject procedure. | |
| 656 | − sprintf(fn, "%s/call_start", path); | |
| 657 | − wr(fn,mode); | |
| 658 | − | |
| 659 | − if (rd_status(path, &status)<0) { | |
| 660 | − vbprintf("fail: read status\n"); | |
| 661 | − return -100; | |
| 662 | − } | |
| 663 | − | |
| 664 | − if (status!=0) { | |
| 665 | − log_info(cpu, "fail: status=%d\n", status); | |
| 666 | − return status; | |
| 667 | − } | |
| 668 | − | |
| 669 | − return status; | |
| 670 | − } | |
| 671 | − | |
| 672 | − static int construct_data_buf(char *path, err_type_info_t err_type_info, | |
| 673 | − err_struct_info_t err_struct_info, | |
| 674 | − err_data_buffer_t *err_data_buffer, | |
| 675 | − void *va1) | |
| 676 | − { | |
| 677 | − char fn[MAX_FN_SIZE]; | |
| 678 | − u64 virt_addr=0, phys_addr=0; | |
| 679 | − | |
| 680 | − vbprintf("va1=%lx\n", (u64)va1); | |
| 681 | − memset(&err_data_buffer->err_data_buffer_cache, 0, ERR_DATA_BUFFER_SIZE*8); | |
| 682 | − | |
| 683 | − switch (err_type_info.err_type_info_u.err_struct) { | |
| 684 | − case 1: // Cache | |
| 685 | − switch (err_struct_info.err_struct_info_cache.cl_id) { | |
| 686 | − case 1: //Virtual addr | |
| 687 | − err_data_buffer->err_data_buffer_cache.inj_addr=(u64)va1; | |
| 688 | − break; | |
| 689 | − case 2: //Phys addr | |
| 690 | − sprintf(fn, "%s/virtual_to_phys", path); | |
| 691 | − virt_addr=(u64)va1; | |
| 692 | − if (wr(fn,virt_addr)<0) | |
| 693 | − return -1; | |
| 694 | − rd(fn, &phys_addr); | |
| 695 | − err_data_buffer->err_data_buffer_cache.inj_addr=phys_addr; | |
| 696 | − break; | |
| 697 | − default: | |
| 698 | − printf("Not supported cl_id\n"); | |
| 699 | − break; | |
| 700 | − } | |
| 701 | − break; | |
| 702 | − case 2: // TLB | |
| 703 | − break; | |
| 704 | − case 3: // Register file | |
| 705 | − break; | |
| 706 | − case 4: // Bus/system interconnect | |
| 707 | − default: | |
| 708 | − printf("Not supported err_struct\n"); | |
| 709 | − break; | |
| 710 | − } | |
| 711 | − | |
| 712 | − return 0; | |
| 713 | − } | |
| 714 | − | |
| 715 | − typedef struct { | |
| 716 | − u64 cpu; | |
| 717 | − u64 loop; | |
| 718 | − u64 interval; | |
| 719 | − u64 err_type_info; | |
| 720 | − u64 err_struct_info; | |
| 721 | − u64 err_data_buffer[ERR_DATA_BUFFER_SIZE]; | |
| 722 | − } parameters_t; | |
| 723 | − | |
| 724 | − parameters_t line_para; | |
| 725 | − int para; | |
| 726 | − | |
| 727 | − static int empty_data_buffer(u64 *err_data_buffer) | |
| 728 | − { | |
| 729 | − int empty=1; | |
| 730 | − int i; | |
| 731 | − | |
| 732 | − for (i=0;i<ERR_DATA_BUFFER_SIZE; i++) | |
| 733 | − if (err_data_buffer[i]!=-1) | |
| 734 | − empty=0; | |
| 735 | − | |
| 736 | − return empty; | |
| 737 | − } | |
| 738 | − | |
| 739 | − int err_inj() | |
| 740 | − { | |
| 741 | − err_type_info_t err_type_info; | |
| 742 | − err_struct_info_t err_struct_info; | |
| 743 | − err_data_buffer_t err_data_buffer; | |
| 744 | − int count; | |
| 745 | − FILE *fp; | |
| 746 | − unsigned long cpu, loop, interval, err_type_info_conf, err_struct_info_conf; | |
| 747 | − u64 err_data_buffer_conf[ERR_DATA_BUFFER_SIZE]; | |
| 748 | − int num; | |
| 749 | − int i; | |
| 750 | − char path[MAX_FN_SIZE]; | |
| 751 | − parameters_t parameters[MAX_TASK_NUM]={}; | |
| 752 | − pid_t child_pid[MAX_TASK_NUM]; | |
| 753 | − time_t current_time; | |
| 754 | − int status; | |
| 755 | − | |
| 756 | − if (!para) { | |
| 757 | − fp=fopen("err.conf", "r"); | |
| 758 | − if (fp==NULL) { | |
| 759 | − perror("Error open err.conf"); | |
| 760 | − return -1; | |
| 761 | − } | |
| 762 | − | |
| 763 | − num=0; | |
| 764 | − while (!feof(fp)) { | |
| 765 | − char buf[256]; | |
| 766 | − memset(buf,0,256); | |
| 767 | − fgets(buf, 256, fp); | |
| 768 | − count=sscanf(buf, "%lx, %lx, %lx, %lx, %lx, %lx, %lx, %lx\n", | |
| 769 | − &cpu, &loop, &interval,&err_type_info_conf, | |
| 770 | − &err_struct_info_conf, | |
| 771 | − &err_data_buffer_conf[0], | |
| 772 | − &err_data_buffer_conf[1], | |
| 773 | − &err_data_buffer_conf[2]); | |
| 774 | − if (count!=PARA_FIELD_NUM+3) { | |
| 775 | − err_data_buffer_conf[0]=-1; | |
| 776 | − err_data_buffer_conf[1]=-1; | |
| 777 | − err_data_buffer_conf[2]=-1; | |
| 778 | − count=sscanf(buf, "%lx, %lx, %lx, %lx, %lx\n", | |
| 779 | − &cpu, &loop, &interval,&err_type_info_conf, | |
| 780 | − &err_struct_info_conf); | |
| 781 | − if (count!=PARA_FIELD_NUM) | |
| 782 | − continue; | |
| 783 | − } | |
| 784 | − | |
| 785 | − parameters[num].cpu=cpu; | |
| 786 | − parameters[num].loop=loop; | |
| 787 | − parameters[num].interval= interval>MIN_INTERVAL | |
| 788 | − ?interval:MIN_INTERVAL; | |
| 789 | − parameters[num].err_type_info=err_type_info_conf; | |
| 790 | − parameters[num].err_struct_info=err_struct_info_conf; | |
| 791 | − memcpy(parameters[num++].err_data_buffer, | |
| 792 | − err_data_buffer_conf,ERR_DATA_BUFFER_SIZE*8) ; | |
| 793 | − | |
| 794 | − if (num>=MAX_TASK_NUM) | |
| 795 | − break; | |
| 796 | − } | |
| 797 | − } | |
| 798 | − else { | |
| 799 | − parameters[0].cpu=line_para.cpu; | |
| 800 | − parameters[0].loop=line_para.loop; | |
| 801 | − parameters[0].interval= line_para.interval>MIN_INTERVAL | |
| 802 | − ?line_para.interval:MIN_INTERVAL; | |
| 803 | − parameters[0].err_type_info=line_para.err_type_info; | |
| 804 | − parameters[0].err_struct_info=line_para.err_struct_info; | |
| 805 | − memcpy(parameters[0].err_data_buffer, | |
| 806 | − line_para.err_data_buffer,ERR_DATA_BUFFER_SIZE*8) ; | |
| 807 | − | |
| 808 | − num=1; | |
| 809 | − } | |
| 810 | − | |
| 811 | − /* Create semaphore: If one_lock, one semaphore for all processors. | |
| 812 | − Otherwise, one semaphore for each processor. */ | |
| 813 | − if (one_lock) { | |
| 814 | − if (create_sem(0)) { | |
| 815 | − printf("Can not create semaphore...exit\n"); | |
| 816 | − free_sem(0); | |
| 817 | − return -1; | |
| 818 | − } | |
| 819 | − } | |
| 820 | − else { | |
| 821 | − for (i=0;i<num;i++) { | |
| 822 | − if (create_sem(parameters[i].cpu)) { | |
| 823 | − printf("Can not create semaphore for cpu%d...exit\n",i); | |
| 824 | − free_sem(parameters[num].cpu); | |
| 825 | − return -1; | |
| 826 | − } | |
| 827 | − } | |
| 828 | − } | |
| 829 | − | |
| 830 | − /* Create a shm segment which will be used to inject/consume errors on.*/ | |
| 831 | − if (create_shm()==-1) { | |
| 832 | − printf("Error to create shm...exit\n"); | |
| 833 | − return -1; | |
| 834 | − } | |
| 835 | − | |
| 836 | − for (i=0;i<num;i++) { | |
| 837 | − pid_t pid; | |
| 838 | − | |
| 839 | − current_time=time(NULL); | |
| 840 | − log_info(parameters[i].cpu, "\nBegine at %s", ctime(¤t_time)); | |
| 841 | − log_info(parameters[i].cpu, "Configurations:\n"); | |
| 842 | − log_info(parameters[i].cpu,"On cpu%ld: loop=%lx, interval=%lx(s)", | |
| 843 | − parameters[i].cpu, | |
| 844 | − parameters[i].loop, | |
| 845 | − parameters[i].interval); | |
| 846 | − log_info(parameters[i].cpu," err_type_info=%lx,err_struct_info=%lx\n", | |
| 847 | − parameters[i].err_type_info, | |
| 848 | − parameters[i].err_struct_info); | |
| 849 | − | |
| 850 | − sprintf(path, PATH_FORMAT, (int)parameters[i].cpu); | |
| 851 | − err_type_info.err_type_info=parameters[i].err_type_info; | |
| 852 | − err_struct_info.err_struct_info=parameters[i].err_struct_info; | |
| 853 | − memcpy(err_data_buffer.err_data_buffer, | |
| 854 | − parameters[i].err_data_buffer, | |
| 855 | − ERR_DATA_BUFFER_SIZE*8); | |
| 856 | − | |
| 857 | − pid=fork(); | |
| 858 | − if (pid==0) { | |
| 859 | − unsigned long mask[MASK_SIZE]; | |
| 860 | − int j, k; | |
| 861 | − | |
| 862 | − void *va1, *va2; | |
| 863 | − | |
| 864 | − /* Allocate two memory areas va1 and va2 in shm */ | |
| 865 | − va1=shmaddr+parameters[i].cpu*PAGE_SIZE; | |
| 866 | − va2=shmaddr+parameters[i].cpu*PAGE_SIZE+PAGE_SIZE; | |
| 867 | − | |
| 868 | − vbprintf("va1=%lx, va2=%lx\n", (u64)va1, (u64)va2); | |
| 869 | − memset(va1, 0x1, PAGE_SIZE); | |
| 870 | − memset(va2, 0x2, PAGE_SIZE); | |
| 871 | − | |
| 872 | − if (empty_data_buffer(err_data_buffer.err_data_buffer)) | |
| 873 | − /* If not specified yet, construct data buffer | |
| 874 | − * with va1 | |
| 875 | − */ | |
| 876 | − construct_data_buf(path, err_type_info, | |
| 877 | − err_struct_info, &err_data_buffer,va1); | |
| 878 | − | |
| 879 | − for (j=0;j<MASK_SIZE;j++) | |
| 880 | − mask[j]=0; | |
| 881 | − | |
| 882 | − cpu=parameters[i].cpu; | |
| 883 | − k = cpu%64; | |
| 884 | − j = cpu/64; | |
| 885 | − mask[j] = 1UL << k; | |
| 886 | − | |
| 887 | − if (sched_setaffinity(0, MASK_SIZE*8, mask)==-1) { | |
| 888 | − perror("Error sched_setaffinity:"); | |
| 889 | − return -1; | |
| 890 | − } | |
| 891 | − | |
| 892 | − for (j=0; j<parameters[i].loop; j++) { | |
| 893 | − log_info(parameters[i].cpu,"Injection "); | |
| 894 | − log_info(parameters[i].cpu,"on cpu%ld: #%d/%ld ", | |
| 895 | − | |
| 896 | − parameters[i].cpu,j+1, parameters[i].loop); | |
| 897 | − | |
| 898 | − /* Hold the lock */ | |
| 899 | − if (one_lock) | |
| 900 | − lock(0); | |
| 901 | − else | |
| 902 | − /* Hold lock on this cpu */ | |
| 903 | − lock(parameters[i].cpu); | |
| 904 | − | |
| 905 | − if ((status=err_inject(parameters[i].cpu, | |
| 906 | − path, err_type_info, | |
| 907 | − err_struct_info, err_data_buffer)) | |
| 908 | − ==0) { | |
| 909 | − /* consume the error for "inject only"*/ | |
| 910 | − memcpy(va2, va1, PAGE_SIZE); | |
| 911 | − memcpy(va1, va2, PAGE_SIZE); | |
| 912 | − log_info(parameters[i].cpu, | |
| 913 | − "successful\n"); | |
| 914 | − } | |
| 915 | − else { | |
| 916 | − log_info(parameters[i].cpu,"fail:"); | |
| 917 | − log_info(parameters[i].cpu, | |
| 918 | − "status=%d\n", status); | |
| 919 | − unlock(parameters[i].cpu); | |
| 920 | − break; | |
| 921 | − } | |
| 922 | − if (one_lock) | |
| 923 | − /* Release the lock */ | |
| 924 | − unlock(0); | |
| 925 | − /* Release lock on this cpu */ | |
| 926 | − else | |
| 927 | − unlock(parameters[i].cpu); | |
| 928 | − | |
| 929 | − if (j < parameters[i].loop-1) | |
| 930 | − sleep(parameters[i].interval); | |
| 931 | − } | |
| 932 | − current_time=time(NULL); | |
| 933 | − log_info(parameters[i].cpu, "Done at %s", ctime(¤t_time)); | |
| 934 | − return 0; | |
| 935 | − } | |
| 936 | − else if (pid<0) { | |
| 937 | − perror("Error fork:"); | |
| 938 | − continue; | |
| 939 | − } | |
| 940 | − child_pid[i]=pid; | |
| 941 | − } | |
| 942 | − for (i=0;i<num;i++) | |
| 943 | − waitpid(child_pid[i], NULL, 0); | |
| 944 | − | |
| 945 | − if (one_lock) | |
| 946 | − free_sem(0); | |
| 947 | − else | |
| 948 | − for (i=0;i<num;i++) | |
| 949 | − free_sem(parameters[i].cpu); | |
| 950 | − | |
| 951 | − printf("All done.\n"); | |
| 952 | − | |
| 953 | − return 0; | |
| 954 | − } | |
| 955 | − | |
| 956 | − void help() | |
| 957 | − { | |
| 958 | − printf("err_inject_tool:\n"); | |
| 959 | − printf("\t-q: query all capabilities. default: off\n"); | |
| 960 | − printf("\t-m: procedure mode. 1: physical 2: virtual. default: 1\n"); | |
| 961 | − printf("\t-i: inject errors. default: off\n"); | |
| 962 | − printf("\t-l: one lock per cpu. default: one lock for all\n"); | |
| 963 | − printf("\t-e: error parameters:\n"); | |
| 964 | − printf("\t\tcpu,loop,interval,err_type_info,err_struct_info[,err_data_buffer[0],err_data_buffer[1],err_data_buffer[2]]\n"); | |
| 965 | − printf("\t\t cpu: logical cpu number the error will be inject in.\n"); | |
| 966 | − printf("\t\t loop: times the error will be injected.\n"); | |
| 967 | − printf("\t\t interval: In second. every so often one error is injected.\n"); | |
| 968 | − printf("\t\t err_type_info, err_struct_info: PAL parameters.\n"); | |
| 969 | − printf("\t\t err_data_buffer: PAL parameter. Optional. If not present,\n"); | |
| 970 | − printf("\t\t it's constructed by tool automatically. Be\n"); | |
| 971 | − printf("\t\t careful to provide err_data_buffer and make\n"); | |
| 972 | − printf("\t\t sure it's working with the environment.\n"); | |
| 973 | − printf("\t Note:no space between error parameters.\n"); | |
| 974 | − printf("\t default: Take error parameters from err.conf instead of command line.\n"); | |
| 975 | − printf("\t-v: verbose. default: off\n"); | |
| 976 | − printf("\t-h: help\n\n"); | |
| 977 | − printf("The tool will take err.conf file as "); | |
| 978 | − printf("input to inject single or multiple errors "); | |
| 979 | − printf("on one or multiple cpus in parallel.\n"); | |
| 980 | − } | |
| 981 | − | |
| 982 | − int main(int argc, char **argv) | |
| 983 | − { | |
| 984 | − char c; | |
| 985 | − int do_err_inj=0; | |
| 986 | − int do_query_all=0; | |
| 987 | − int count; | |
| 988 | − u32 m; | |
| 989 | − | |
| 990 | − /* Default one lock for all cpu's */ | |
| 991 | − one_lock=1; | |
| 992 | − while ((c = getopt(argc, argv, "m:iqvhle:")) != EOF) | |
| 993 | − switch (c) { | |
| 994 | − case 'm': /* Procedure mode. 1: phys 2: virt */ | |
| 995 | − count=sscanf(optarg, "%x", &m); | |
| 996 | − if (count!=1 || (m!=1 && m!=2)) { | |
| 997 | − printf("Wrong mode number.\n"); | |
| 998 | − help(); | |
| 999 | − return -1; | |
| 1000 | − } | |
| 1001 | − mode=m; | |
| 1002 | − break; | |
| 1003 | − case 'i': /* Inject errors */ | |
| 1004 | − do_err_inj=1; | |
| 1005 | − break; | |
| 1006 | − case 'q': /* Query */ | |
| 1007 | − do_query_all=1; | |
| 1008 | − break; | |
| 1009 | − case 'v': /* Verbose */ | |
| 1010 | − verbose=1; | |
| 1011 | − break; | |
| 1012 | − case 'l': /* One lock per cpu */ | |
| 1013 | − one_lock=0; | |
| 1014 | − break; | |
| 1015 | − case 'e': /* error arguments */ | |
| 1016 | − /* Take parameters: | |
| 1017 | − * #cpu, loop, interval, err_type_info, err_struct_info[, err_data_buffer] | |
| 1018 | − * err_data_buffer is optional. Recommend not to specify | |
| 1019 | − * err_data_buffer. Better to use tool to generate it. | |
| 1020 | − */ | |
| 1021 | − count=sscanf(optarg, | |
| 1022 | − "%lx, %lx, %lx, %lx, %lx, %lx, %lx, %lx\n", | |
| 1023 | − &line_para.cpu, | |
| 1024 | − &line_para.loop, | |
| 1025 | − &line_para.interval, | |
| 1026 | − &line_para.err_type_info, | |
| 1027 | − &line_para.err_struct_info, | |
| 1028 | − &line_para.err_data_buffer[0], | |
| 1029 | − &line_para.err_data_buffer[1], | |
| 1030 | − &line_para.err_data_buffer[2]); | |
| 1031 | − if (count!=PARA_FIELD_NUM+3) { | |
| 1032 | − line_para.err_data_buffer[0]=-1, | |
| 1033 | − line_para.err_data_buffer[1]=-1, | |
| 1034 | − line_para.err_data_buffer[2]=-1; | |
| 1035 | − count=sscanf(optarg, "%lx, %lx, %lx, %lx, %lx\n", | |
| 1036 | − &line_para.cpu, | |
| 1037 | − &line_para.loop, | |
| 1038 | − &line_para.interval, | |
| 1039 | − &line_para.err_type_info, | |
| 1040 | − &line_para.err_struct_info); | |
| 1041 | − if (count!=PARA_FIELD_NUM) { | |
| 1042 | − printf("Wrong error arguments.\n"); | |
| 1043 | − help(); | |
| 1044 | − return -1; | |
| 1045 | − } | |
| 1046 | − } | |
| 1047 | − para=1; | |
| 1048 | − break; | |
| 1049 | − continue; | |
| 1050 | − break; | |
| 1051 | − case 'h': | |
| 1052 | − help(); | |
| 1053 | − return 0; | |
| 1054 | − default: | |
| 1055 | − break; | |
| 1056 | − } | |
| 1057 | − | |
| 1058 | − if (do_query_all) | |
| 1059 | − query_all_capabilities(); | |
| 1060 | − if (do_err_inj) | |
| 1061 | − err_inj(); | |
| 1062 | − | |
| 1063 | − if (!do_query_all && !do_err_inj) | |
| 1064 | − help(); | |
| 1065 | − | |
| 1066 | − return 0; | |
| 1067 | − } | |
| @@ -1,3 +0,0 @@ | ||
| 1 | −.. SPDX-License-Identifier: GPL-2.0 | |
| 2 | − | |
| 3 | −.. kernel-feat:: $srctree/Documentation/features ia64 | |
| @@ -1,303 +0,0 @@ | ||
| 1 | −=================================== | |
| 2 | −Light-weight System Calls for IA-64 | |
| 3 | −=================================== | |
| 4 | − | |
| 5 | − Started: 13-Jan-2003 | |
| 6 | − | |
| 7 | − Last update: 27-Sep-2003 | |
| 8 | − | |
| 9 | − David Mosberger-Tang | |
| 10 | − <davidm@hpl.hp.com> | |
| 11 | − | |
| 12 | −Using the "epc" instruction effectively introduces a new mode of | |
| 13 | −execution to the ia64 linux kernel. We call this mode the | |
| 14 | −"fsys-mode". To recap, the normal states of execution are: | |
| 15 | − | |
| 16 | − - kernel mode: | |
| 17 | − Both the register stack and the memory stack have been | |
| 18 | − switched over to kernel memory. The user-level state is saved | |
| 19 | − in a pt-regs structure at the top of the kernel memory stack. | |
| 20 | − | |
| 21 | − - user mode: | |
| 22 | − Both the register stack and the kernel stack are in | |
| 23 | − user memory. The user-level state is contained in the | |
| 24 | − CPU registers. | |
| 25 | − | |
| 26 | − - bank 0 interruption-handling mode: | |
| 27 | − This is the non-interruptible state which all | |
| 28 | − interruption-handlers start execution in. The user-level | |
| 29 | − state remains in the CPU registers and some kernel state may | |
| 30 | − be stored in bank 0 of registers r16-r31. | |
| 31 | − | |
| 32 | −In contrast, fsys-mode has the following special properties: | |
| 33 | − | |
| 34 | − - execution is at privilege level 0 (most-privileged) | |
| 35 | − | |
| 36 | − - CPU registers may contain a mixture of user-level and kernel-level | |
| 37 | − state (it is the responsibility of the kernel to ensure that no | |
| 38 | − security-sensitive kernel-level state is leaked back to | |
| 39 | − user-level) | |
| 40 | − | |
| 41 | − - execution is interruptible and preemptible (an fsys-mode handler | |
| 42 | − can disable interrupts and avoid all other interruption-sources | |
| 43 | − to avoid preemption) | |
| 44 | − | |
| 45 | − - neither the memory-stack nor the register-stack can be trusted while | |
| 46 | − in fsys-mode (they point to the user-level stacks, which may | |
| 47 | − be invalid, or completely bogus addresses) | |
| 48 | − | |
| 49 | −In summary, fsys-mode is much more similar to running in user-mode | |
| 50 | −than it is to running in kernel-mode. Of course, given that the | |
| 51 | −privilege level is at level 0, this means that fsys-mode requires some | |
| 52 | −care (see below). | |
| 53 | − | |
| 54 | − | |
| 55 | −How to tell fsys-mode | |
| 56 | −===================== | |
| 57 | − | |
| 58 | −Linux operates in fsys-mode when (a) the privilege level is 0 (most | |
| 59 | −privileged) and (b) the stacks have NOT been switched to kernel memory | |
| 60 | −yet. For convenience, the header file <asm-ia64/ptrace.h> provides | |
| 61 | −three macros:: | |
| 62 | − | |
| 63 | − user_mode(regs) | |
| 64 | − user_stack(task,regs) | |
| 65 | − fsys_mode(task,regs) | |
| 66 | − | |
| 67 | −The "regs" argument is a pointer to a pt_regs structure. The "task" | |
| 68 | −argument is a pointer to the task structure to which the "regs" | |
| 69 | −pointer belongs to. user_mode() returns TRUE if the CPU state pointed | |
| 70 | −to by "regs" was executing in user mode (privilege level 3). | |
| 71 | −user_stack() returns TRUE if the state pointed to by "regs" was | |
| 72 | −executing on the user-level stack(s). Finally, fsys_mode() returns | |
| 73 | −TRUE if the CPU state pointed to by "regs" was executing in fsys-mode. | |
| 74 | −The fsys_mode() macro is equivalent to the expression:: | |
| 75 | − | |
| 76 | − !user_mode(regs) && user_stack(task,regs) | |
| 77 | − | |
| 78 | −How to write an fsyscall handler | |
| 79 | −================================ | |
| 80 | − | |
| 81 | −The file arch/ia64/kernel/fsys.S contains a table of fsyscall-handlers | |
| 82 | −(fsyscall_table). This table contains one entry for each system call. | |
| 83 | −By default, a system call is handled by fsys_fallback_syscall(). This | |
| 84 | −routine takes care of entering (full) kernel mode and calling the | |
| 85 | −normal Linux system call handler. For performance-critical system | |
| 86 | −calls, it is possible to write a hand-tuned fsyscall_handler. For | |
| 87 | −example, fsys.S contains fsys_getpid(), which is a hand-tuned version | |
| 88 | −of the getpid() system call. | |
| 89 | − | |
| 90 | −The entry and exit-state of an fsyscall handler is as follows: | |
| 91 | − | |
| 92 | −Machine state on entry to fsyscall handler | |
| 93 | −------------------------------------------ | |
| 94 | − | |
| 95 | − ========= =============================================================== | |
| 96 | − r10 0 | |
| 97 | − r11 saved ar.pfs (a user-level value) | |
| 98 | − r15 system call number | |
| 99 | − r16 "current" task pointer (in normal kernel-mode, this is in r13) | |
| 100 | − r32-r39 system call arguments | |
| 101 | − b6 return address (a user-level value) | |
| 102 | − ar.pfs previous frame-state (a user-level value) | |
| 103 | − PSR.be cleared to zero (i.e., little-endian byte order is in effect) | |
| 104 | − - all other registers may contain values passed in from user-mode | |
| 105 | − ========= =============================================================== | |
| 106 | − | |
| 107 | −Required machine state on exit to fsyscall handler | |
| 108 | −-------------------------------------------------- | |
| 109 | − | |
| 110 | − ========= =========================================================== | |
| 111 | − r11 saved ar.pfs (as passed into the fsyscall handler) | |
| 112 | − r15 system call number (as passed into the fsyscall handler) | |
| 113 | − r32-r39 system call arguments (as passed into the fsyscall handler) | |
| 114 | − b6 return address (as passed into the fsyscall handler) | |
| 115 | − ar.pfs previous frame-state (as passed into the fsyscall handler) | |
| 116 | − ========= =========================================================== | |
| 117 | − | |
| 118 | −Fsyscall handlers can execute with very little overhead, but with that | |
| 119 | −speed comes a set of restrictions: | |
| 120 | − | |
| 121 | − * Fsyscall-handlers MUST check for any pending work in the flags | |
| 122 | − member of the thread-info structure and if any of the | |
| 123 | − TIF_ALLWORK_MASK flags are set, the handler needs to fall back on | |
| 124 | − doing a full system call (by calling fsys_fallback_syscall). | |
| 125 | − | |
| 126 | − * Fsyscall-handlers MUST preserve incoming arguments (r32-r39, r11, | |
| 127 | − r15, b6, and ar.pfs) because they will be needed in case of a | |
| 128 | − system call restart. Of course, all "preserved" registers also | |
| 129 | − must be preserved, in accordance to the normal calling conventions. | |
| 130 | − | |
| 131 | − * Fsyscall-handlers MUST check argument registers for containing a | |
| 132 | − NaT value before using them in any way that could trigger a | |
| 133 | − NaT-consumption fault. If a system call argument is found to | |
| 134 | − contain a NaT value, an fsyscall-handler may return immediately | |
| 135 | − with r8=EINVAL, r10=-1. | |
| 136 | − | |
| 137 | − * Fsyscall-handlers MUST NOT use the "alloc" instruction or perform | |
| 138 | − any other operation that would trigger mandatory RSE | |
| 139 | − (register-stack engine) traffic. | |
| 140 | − | |
| 141 | − * Fsyscall-handlers MUST NOT write to any stacked registers because | |
| 142 | − it is not safe to assume that user-level called a handler with the | |
| 143 | − proper number of arguments. | |
| 144 | − | |
| 145 | − * Fsyscall-handlers need to be careful when accessing per-CPU variables: | |
| 146 | − unless proper safe-guards are taken (e.g., interruptions are avoided), | |
| 147 | − execution may be pre-empted and resumed on another CPU at any given | |
| 148 | − time. | |
| 149 | − | |
| 150 | − * Fsyscall-handlers must be careful not to leak sensitive kernel' | |
| 151 | − information back to user-level. In particular, before returning to | |
| 152 | − user-level, care needs to be taken to clear any scratch registers | |
| 153 | − that could contain sensitive information (note that the current | |
| 154 | − task pointer is not considered sensitive: it's already exposed | |
| 155 | − through ar.k6). | |
| 156 | − | |
| 157 | − * Fsyscall-handlers MUST NOT access user-memory without first | |
| 158 | − validating access-permission (this can be done typically via | |
| 159 | − probe.r.fault and/or probe.w.fault) and without guarding against | |
| 160 | − memory access exceptions (this can be done with the EX() macros | |
| 161 | − defined by asmmacro.h). | |
| 162 | − | |
| 163 | −The above restrictions may seem draconian, but remember that it's | |
| 164 | −possible to trade off some of the restrictions by paying a slightly | |
| 165 | −higher overhead. For example, if an fsyscall-handler could benefit | |
| 166 | −from the shadow register bank, it could temporarily disable PSR.i and | |
| 167 | −PSR.ic, switch to bank 0 (bsw.0) and then use the shadow registers as | |
| 168 | −needed. In other words, following the above rules yields extremely | |
| 169 | −fast system call execution (while fully preserving system call | |
| 170 | −semantics), but there is also a lot of flexibility in handling more | |
| 171 | −complicated cases. | |
| 172 | − | |
| 173 | −Signal handling | |
| 174 | −=============== | |
| 175 | − | |
| 176 | −The delivery of (asynchronous) signals must be delayed until fsys-mode | |
| 177 | −is exited. This is accomplished with the help of the lower-privilege | |
| 178 | −transfer trap: arch/ia64/kernel/process.c:do_notify_resume_user() | |
| 179 | −checks whether the interrupted task was in fsys-mode and, if so, sets | |
| 180 | −PSR.lp and returns immediately. When fsys-mode is exited via the | |
| 181 | −"br.ret" instruction that lowers the privilege level, a trap will | |
| 182 | −occur. The trap handler clears PSR.lp again and returns immediately. | |
| 183 | −The kernel exit path then checks for and delivers any pending signals. | |
| 184 | − | |
| 185 | −PSR Handling | |
| 186 | −============ | |
| 187 | − | |
| 188 | −The "epc" instruction doesn't change the contents of PSR at all. This | |
| 189 | −is in contrast to a regular interruption, which clears almost all | |
| 190 | −bits. Because of that, some care needs to be taken to ensure things | |
| 191 | −work as expected. The following discussion describes how each PSR bit | |
| 192 | −is handled. | |
| 193 | − | |
| 194 | −======= ======================================================================= | |
| 195 | −PSR.be Cleared when entering fsys-mode. A srlz.d instruction is used | |
| 196 | − to ensure the CPU is in little-endian mode before the first | |
| 197 | − load/store instruction is executed. PSR.be is normally NOT | |
| 198 | − restored upon return from an fsys-mode handler. In other | |
| 199 | − words, user-level code must not rely on PSR.be being preserved | |
| 200 | − across a system call. | |
| 201 | −PSR.up Unchanged. | |
| 202 | −PSR.ac Unchanged. | |
| 203 | −PSR.mfl Unchanged. Note: fsys-mode handlers must not write-registers! | |
| 204 | −PSR.mfh Unchanged. Note: fsys-mode handlers must not write-registers! | |
| 205 | −PSR.ic Unchanged. Note: fsys-mode handlers can clear the bit, if needed. | |
| 206 | −PSR.i Unchanged. Note: fsys-mode handlers can clear the bit, if needed. | |
| 207 | −PSR.pk Unchanged. | |
| 208 | −PSR.dt Unchanged. | |
| 209 | −PSR.dfl Unchanged. Note: fsys-mode handlers must not write-registers! | |
| 210 | −PSR.dfh Unchanged. Note: fsys-mode handlers must not write-registers! | |
| 211 | −PSR.sp Unchanged. | |
| 212 | −PSR.pp Unchanged. | |
| 213 | −PSR.di Unchanged. | |
| 214 | −PSR.si Unchanged. | |
| 215 | −PSR.db Unchanged. The kernel prevents user-level from setting a hardware | |
| 216 | − breakpoint that triggers at any privilege level other than | |
| 217 | − 3 (user-mode). | |
| 218 | −PSR.lp Unchanged. | |
| 219 | −PSR.tb Lazy redirect. If a taken-branch trap occurs while in | |
| 220 | − fsys-mode, the trap-handler modifies the saved machine state | |
| 221 | − such that execution resumes in the gate page at | |
| 222 | − syscall_via_break(), with privilege level 3. Note: the | |
| 223 | − taken branch would occur on the branch invoking the | |
| 224 | − fsyscall-handler, at which point, by definition, a syscall | |
| 225 | − restart is still safe. If the system call number is invalid, | |
| 226 | − the fsys-mode handler will return directly to user-level. This | |
| 227 | − return will trigger a taken-branch trap, but since the trap is | |
| 228 | − taken _after_ restoring the privilege level, the CPU has already | |
| 229 | − left fsys-mode, so no special treatment is needed. | |
| 230 | −PSR.rt Unchanged. | |
| 231 | −PSR.cpl Cleared to 0. | |
| 232 | −PSR.is Unchanged (guaranteed to be 0 on entry to the gate page). | |
| 233 | −PSR.mc Unchanged. | |
| 234 | −PSR.it Unchanged (guaranteed to be 1). | |
| 235 | −PSR.id Unchanged. Note: the ia64 linux kernel never sets this bit. | |
| 236 | −PSR.da Unchanged. Note: the ia64 linux kernel never sets this bit. | |
| 237 | −PSR.dd Unchanged. Note: the ia64 linux kernel never sets this bit. | |
| 238 | −PSR.ss Lazy redirect. If set, "epc" will cause a Single Step Trap to | |
| 239 | − be taken. The trap handler then modifies the saved machine | |
| 240 | − state such that execution resumes in the gate page at | |
| 241 | − syscall_via_break(), with privilege level 3. | |
| 242 | −PSR.ri Unchanged. | |
| 243 | −PSR.ed Unchanged. Note: This bit could only have an effect if an fsys-mode | |
| 244 | − handler performed a speculative load that gets NaTted. If so, this | |
| 245 | − would be the normal & expected behavior, so no special treatment is | |
| 246 | − needed. | |
| 247 | −PSR.bn Unchanged. Note: fsys-mode handlers may clear the bit, if needed. | |
| 248 | − Doing so requires clearing PSR.i and PSR.ic as well. | |
| 249 | −PSR.ia Unchanged. Note: the ia64 linux kernel never sets this bit. | |
| 250 | −======= ======================================================================= | |
| 251 | − | |
| 252 | −Using fast system calls | |
| 253 | −======================= | |
| 254 | − | |
| 255 | −To use fast system calls, userspace applications need simply call | |
| 256 | −__kernel_syscall_via_epc(). For example | |
| 257 | − | |
| 258 | −-- example fgettimeofday() call -- | |
| 259 | − | |
| 260 | −-- fgettimeofday.S -- | |
| 261 | − | |
| 262 | −:: | |
| 263 | − | |
| 264 | − #include <asm/asmmacro.h> | |
| 265 | − | |
| 266 | − GLOBAL_ENTRY(fgettimeofday) | |
| 267 | − .prologue | |
| 268 | − .save ar.pfs, r11 | |
| 269 | − mov r11 = ar.pfs | |
| 270 | − .body | |
| 271 | − | |
| 272 | − mov r2 = 0xa000000000020660;; // gate address | |
| 273 | − // found by inspection of System.map for the | |
| 274 | − // __kernel_syscall_via_epc() function. See | |
| 275 | − // below for how to do this for real. | |
| 276 | − | |
| 277 | − mov b7 = r2 | |
| 278 | − mov r15 = 1087 // gettimeofday syscall | |
| 279 | − ;; | |
| 280 | − br.call.sptk.many b6 = b7 | |
| 281 | − ;; | |
| 282 | − | |
| 283 | − .restore sp | |
| 284 | − | |
| 285 | − mov ar.pfs = r11 | |
| 286 | − br.ret.sptk.many rp;; // return to caller | |
| 287 | − END(fgettimeofday) | |
| 288 | − | |
| 289 | −-- end fgettimeofday.S -- | |
| 290 | − | |
| 291 | −In reality, getting the gate address is accomplished by two extra | |
| 292 | −values passed via the ELF auxiliary vector (include/asm-ia64/elf.h) | |
| 293 | − | |
| 294 | − * AT_SYSINFO : is the address of __kernel_syscall_via_epc() | |
| 295 | − * AT_SYSINFO_EHDR : is the address of the kernel gate ELF DSO | |
| 296 | − | |
| 297 | −The ELF DSO is a pre-linked library that is mapped in by the kernel at | |
| 298 | −the gate page. It is a proper ELF shared object so, with a dynamic | |
| 299 | −loader that recognises the library, you should be able to make calls to | |
| 300 | −the exported functions within it as with any other shared library. | |
| 301 | −AT_SYSINFO points into the kernel DSO at the | |
| 302 | −__kernel_syscall_via_epc() function for historical reasons (it was | |
| 303 | −used before the kernel DSO) and as a convenience. | |
| @@ -1,49 +0,0 @@ | ||
| 1 | −=========================================== | |
| 2 | −Linux kernel release for the IA-64 Platform | |
| 3 | −=========================================== | |
| 4 | − | |
| 5 | − These are the release notes for Linux since version 2.4 for IA-64 | |
| 6 | − platform. This document provides information specific to IA-64 | |
| 7 | − ONLY, to get additional information about the Linux kernel also | |
| 8 | − read the original Linux README provided with the kernel. | |
| 9 | − | |
| 10 | −Installing the Kernel | |
| 11 | −===================== | |
| 12 | − | |
| 13 | − - IA-64 kernel installation is the same as the other platforms, see | |
| 14 | − original README for details. | |
| 15 | − | |
| 16 | − | |
| 17 | −Software Requirements | |
| 18 | −===================== | |
| 19 | − | |
| 20 | − Compiling and running this kernel requires an IA-64 compliant GCC | |
| 21 | − compiler. And various software packages also compiled with an | |
| 22 | − IA-64 compliant GCC compiler. | |
| 23 | − | |
| 24 | − | |
| 25 | −Configuring the Kernel | |
| 26 | −====================== | |
| 27 | − | |
| 28 | − Configuration is the same, see original README for details. | |
| 29 | − | |
| 30 | − | |
| 31 | −Compiling the Kernel: | |
| 32 | − | |
| 33 | − - Compiling this kernel doesn't differ from other platform so read | |
| 34 | − the original README for details BUT make sure you have an IA-64 | |
| 35 | − compliant GCC compiler. | |
| 36 | − | |
| 37 | −IA-64 Specifics | |
| 38 | −=============== | |
| 39 | − | |
| 40 | − - General issues: | |
| 41 | − | |
| 42 | − * Hardly any performance tuning has been done. Obvious targets | |
| 43 | − include the library routines (IP checksum, etc.). Less | |
| 44 | − obvious targets include making sure we don't flush the TLB | |
| 45 | − needlessly, etc. | |
| 46 | − | |
| 47 | − * SMP locks cleanup/optimization | |
| 48 | − | |
| 49 | − * IA32 support. Currently experimental. It mostly works. | |
| @@ -1,19 +0,0 @@ | ||
| 1 | −.. SPDX-License-Identifier: GPL-2.0 | |
| 2 | − | |
| 3 | −================== | |
| 4 | −IA-64 Architecture | |
| 5 | −================== | |
| 6 | − | |
| 7 | −.. toctree:: | |
| 8 | − :maxdepth: 1 | |
| 9 | − | |
| 10 | − ia64 | |
| 11 | − aliasing | |
| 12 | − efirtc | |
| 13 | − err_inject | |
| 14 | − fsys | |
| 15 | − irq-redir | |
| 16 | − mca | |
| 17 | − serial | |
| 18 | − | |
| 19 | − features | |
| @@ -1,80 +0,0 @@ | ||
| 1 | −============================== | |
| 2 | −IRQ affinity on IA64 platforms | |
| 3 | −============================== | |
| 4 | − | |
| 5 | −07.01.2002, Erich Focht <efocht@ess.nec.de> | |
| 6 | − | |
| 7 | − | |
| 8 | −By writing to /proc/irq/IRQ#/smp_affinity the interrupt routing can be | |
| 9 | −controlled. The behavior on IA64 platforms is slightly different from | |
| 10 | −that described in Documentation/core-api/irq/irq-affinity.rst for i386 systems. | |
| 11 | − | |
| 12 | −Because of the usage of SAPIC mode and physical destination mode the | |
| 13 | −IRQ target is one particular CPU and cannot be a mask of several | |
| 14 | −CPUs. Only the first non-zero bit is taken into account. | |
| 15 | − | |
| 16 | − | |
| 17 | −Usage examples | |
| 18 | −============== | |
| 19 | − | |
| 20 | −The target CPU has to be specified as a hexadecimal CPU mask. The | |
| 21 | −first non-zero bit is the selected CPU. This format has been kept for | |
| 22 | −compatibility reasons with i386. | |
| 23 | − | |
| 24 | −Set the delivery mode of interrupt 41 to fixed and route the | |
| 25 | −interrupts to CPU #3 (logical CPU number) (2^3=0x08):: | |
| 26 | − | |
| 27 | − echo "8" >/proc/irq/41/smp_affinity | |
| 28 | − | |
| 29 | −Set the default route for IRQ number 41 to CPU 6 in lowest priority | |
| 30 | −delivery mode (redirectable):: | |
| 31 | − | |
| 32 | − echo "r 40" >/proc/irq/41/smp_affinity | |
| 33 | − | |
| 34 | −The output of the command:: | |
| 35 | − | |
| 36 | − cat /proc/irq/IRQ#/smp_affinity | |
| 37 | − | |
| 38 | −gives the target CPU mask for the specified interrupt vector. If the CPU | |
| 39 | −mask is preceded by the character "r", the interrupt is redirectable | |
| 40 | −(i.e. lowest priority mode routing is used), otherwise its route is | |
| 41 | −fixed. | |
| 42 | − | |
| 43 | − | |
| 44 | − | |
| 45 | −Initialization and default behavior | |
| 46 | −=================================== | |
| 47 | − | |
| 48 | −If the platform features IRQ redirection (info provided by SAL) all | |
| 49 | −IO-SAPIC interrupts are initialized with CPU#0 as their default target | |
| 50 | −and the routing is the so called "lowest priority mode" (actually | |
| 51 | −fixed SAPIC mode with hint). The XTP chipset registers are used as hints | |
| 52 | −for the IRQ routing. Currently in Linux XTP registers can have three | |
| 53 | −values: | |
| 54 | − | |
| 55 | − - minimal for an idle task, | |
| 56 | − - normal if any other task runs, | |
| 57 | − - maximal if the CPU is going to be switched off. | |
| 58 | − | |
| 59 | −The IRQ is routed to the CPU with lowest XTP register value, the | |
| 60 | −search begins at the default CPU. Therefore most of the interrupts | |
| 61 | −will be handled by CPU #0. | |
| 62 | − | |
| 63 | −If the platform doesn't feature interrupt redirection IOSAPIC fixed | |
| 64 | −routing is used. The target CPUs are distributed in a round robin | |
| 65 | −manner. IRQs will be routed only to the selected target CPUs. Check | |
| 66 | −with:: | |
| 67 | − | |
| 68 | − cat /proc/interrupts | |
| 69 | − | |
| 70 | − | |
| 71 | − | |
| 72 | −Comments | |
| 73 | −======== | |
| 74 | − | |
| 75 | −On large (multi-node) systems it is recommended to route the IRQs to | |
| 76 | −the node to which the corresponding device is connected. | |
| 77 | −For systems like the NEC AzusA we get IRQ node-affinity for free. This | |
| 78 | −is because usually the chipsets on each node redirect the interrupts | |
| 79 | −only to their own CPUs (as they cannot see the XTP registers on the | |
| 80 | −other nodes). | |
| @@ -1,198 +0,0 @@ | ||
| 1 | −============================================================= | |
| 2 | −An ad-hoc collection of notes on IA64 MCA and INIT processing | |
| 3 | −============================================================= | |
| 4 | − | |
| 5 | −Feel free to update it with notes about any area that is not clear. | |
| 6 | − | |
| 7 | −--- | |
| 8 | − | |
| 9 | −MCA/INIT are completely asynchronous. They can occur at any time, when | |
| 10 | −the OS is in any state. Including when one of the cpus is already | |
| 11 | −holding a spinlock. Trying to get any lock from MCA/INIT state is | |
| 12 | −asking for deadlock. Also the state of structures that are protected | |
| 13 | −by locks is indeterminate, including linked lists. | |
| 14 | − | |
| 15 | −--- | |
| 16 | − | |
| 17 | −The complicated ia64 MCA process. All of this is mandated by Intel's | |
| 18 | −specification for ia64 SAL, error recovery and unwind, it is not as | |
| 19 | −if we have a choice here. | |
| 20 | − | |
| 21 | −* MCA occurs on one cpu, usually due to a double bit memory error. | |
| 22 | − This is the monarch cpu. | |
| 23 | − | |
| 24 | −* SAL sends an MCA rendezvous interrupt (which is a normal interrupt) | |
| 25 | − to all the other cpus, the slaves. | |
| 26 | − | |
| 27 | −* Slave cpus that receive the MCA interrupt call down into SAL, they | |
| 28 | − end up spinning disabled while the MCA is being serviced. | |
| 29 | − | |
| 30 | −* If any slave cpu was already spinning disabled when the MCA occurred | |
| 31 | − then it cannot service the MCA interrupt. SAL waits ~20 seconds then | |
| 32 | − sends an unmaskable INIT event to the slave cpus that have not | |
| 33 | − already rendezvoused. | |
| 34 | − | |
| 35 | −* Because MCA/INIT can be delivered at any time, including when the cpu | |
| 36 | − is down in PAL in physical mode, the registers at the time of the | |
| 37 | − event are _completely_ undefined. In particular the MCA/INIT | |
| 38 | − handlers cannot rely on the thread pointer, PAL physical mode can | |
| 39 | − (and does) modify TP. It is allowed to do that as long as it resets | |
| 40 | − TP on return. However MCA/INIT events expose us to these PAL | |
| 41 | − internal TP changes. Hence curr_task(). | |
| 42 | − | |
| 43 | −* If an MCA/INIT event occurs while the kernel was running (not user | |
| 44 | − space) and the kernel has called PAL then the MCA/INIT handler cannot | |
| 45 | − assume that the kernel stack is in a fit state to be used. Mainly | |
| 46 | − because PAL may or may not maintain the stack pointer internally. | |
| 47 | − Because the MCA/INIT handlers cannot trust the kernel stack, they | |
| 48 | − have to use their own, per-cpu stacks. The MCA/INIT stacks are | |
| 49 | − preformatted with just enough task state to let the relevant handlers | |
| 50 | − do their job. | |
| 51 | − | |
| 52 | −* Unlike most other architectures, the ia64 struct task is embedded in | |
| 53 | − the kernel stack[1]. So switching to a new kernel stack means that | |
| 54 | − we switch to a new task as well. Because various bits of the kernel | |
| 55 | − assume that current points into the struct task, switching to a new | |
| 56 | − stack also means a new value for current. | |
| 57 | − | |
| 58 | −* Once all slaves have rendezvoused and are spinning disabled, the | |
| 59 | − monarch is entered. The monarch now tries to diagnose the problem | |
| 60 | − and decide if it can recover or not. | |
| 61 | − | |
| 62 | −* Part of the monarch's job is to look at the state of all the other | |
| 63 | − tasks. The only way to do that on ia64 is to call the unwinder, | |
| 64 | − as mandated by Intel. | |
| 65 | − | |
| 66 | −* The starting point for the unwind depends on whether a task is | |
| 67 | − running or not. That is, whether it is on a cpu or is blocked. The | |
| 68 | − monarch has to determine whether or not a task is on a cpu before it | |
| 69 | − knows how to start unwinding it. The tasks that received an MCA or | |
| 70 | − INIT event are no longer running, they have been converted to blocked | |
| 71 | − tasks. But (and its a big but), the cpus that received the MCA | |
| 72 | − rendezvous interrupt are still running on their normal kernel stacks! | |
| 73 | − | |
| 74 | −* To distinguish between these two cases, the monarch must know which | |
| 75 | − tasks are on a cpu and which are not. Hence each slave cpu that | |
| 76 | − switches to an MCA/INIT stack, registers its new stack using | |
| 77 | − set_curr_task(), so the monarch can tell that the _original_ task is | |
| 78 | − no longer running on that cpu. That gives us a decent chance of | |
| 79 | − getting a valid backtrace of the _original_ task. | |
| 80 | − | |
| 81 | −* MCA/INIT can be nested, to a depth of 2 on any cpu. In the case of a | |
| 82 | − nested error, we want diagnostics on the MCA/INIT handler that | |
| 83 | − failed, not on the task that was originally running. Again this | |
| 84 | − requires set_curr_task() so the MCA/INIT handlers can register their | |
| 85 | − own stack as running on that cpu. Then a recursive error gets a | |
| 86 | − trace of the failing handler's "task". | |
| 87 | − | |
| 88 | −[1] | |
| 89 | − My (Keith Owens) original design called for ia64 to separate its | |
| 90 | − struct task and the kernel stacks. Then the MCA/INIT data would be | |
| 91 | − chained stacks like i386 interrupt stacks. But that required | |
| 92 | − radical surgery on the rest of ia64, plus extra hard wired TLB | |
| 93 | − entries with its associated performance degradation. David | |
| 94 | − Mosberger vetoed that approach. Which meant that separate kernel | |
| 95 | − stacks meant separate "tasks" for the MCA/INIT handlers. | |
| 96 | − | |
| 97 | −--- | |
| 98 | − | |
| 99 | −INIT is less complicated than MCA. Pressing the nmi button or using | |
| 100 | −the equivalent command on the management console sends INIT to all | |
| 101 | −cpus. SAL picks one of the cpus as the monarch and the rest are | |
| 102 | −slaves. All the OS INIT handlers are entered at approximately the same | |
| 103 | −time. The OS monarch prints the state of all tasks and returns, after | |
| 104 | −which the slaves return and the system resumes. | |
| 105 | − | |
| 106 | −At least that is what is supposed to happen. Alas there are broken | |
| 107 | −versions of SAL out there. Some drive all the cpus as monarchs. Some | |
| 108 | −drive them all as slaves. Some drive one cpu as monarch, wait for that | |
| 109 | −cpu to return from the OS then drive the rest as slaves. Some versions | |
| 110 | −of SAL cannot even cope with returning from the OS, they spin inside | |
| 111 | −SAL on resume. The OS INIT code has workarounds for some of these | |
| 112 | −broken SAL symptoms, but some simply cannot be fixed from the OS side. | |
| 113 | − | |
| 114 | −--- | |
| 115 | − | |
| 116 | −The scheduler hooks used by ia64 (curr_task, set_curr_task) are layer | |
| 117 | −violations. Unfortunately MCA/INIT start off as massive layer | |
| 118 | −violations (can occur at _any_ time) and they build from there. | |
| 119 | − | |
| 120 | −At least ia64 makes an attempt at recovering from hardware errors, but | |
| 121 | −it is a difficult problem because of the asynchronous nature of these | |
| 122 | −errors. When processing an unmaskable interrupt we sometimes need | |
| 123 | −special code to cope with our inability to take any locks. | |
| 124 | − | |
| 125 | −--- | |
| 126 | − | |
| 127 | −How is ia64 MCA/INIT different from x86 NMI? | |
| 128 | − | |
| 129 | −* x86 NMI typically gets delivered to one cpu. MCA/INIT gets sent to | |
| 130 | − all cpus. | |
| 131 | − | |
| 132 | −* x86 NMI cannot be nested. MCA/INIT can be nested, to a depth of 2 | |
| 133 | − per cpu. | |
| 134 | − | |
| 135 | −* x86 has a separate struct task which points to one of multiple kernel | |
| 136 | − stacks. ia64 has the struct task embedded in the single kernel | |
| 137 | − stack, so switching stack means switching task. | |
| 138 | − | |
| 139 | −* x86 does not call the BIOS so the NMI handler does not have to worry | |
| 140 | − about any registers having changed. MCA/INIT can occur while the cpu | |
| 141 | − is in PAL in physical mode, with undefined registers and an undefined | |
| 142 | − kernel stack. | |
| 143 | − | |
| 144 | −* i386 backtrace is not very sensitive to whether a process is running | |
| 145 | − or not. ia64 unwind is very, very sensitive to whether a process is | |
| 146 | − running or not. | |
| 147 | − | |
| 148 | −--- | |
| 149 | − | |
| 150 | −What happens when MCA/INIT is delivered what a cpu is running user | |
| 151 | −space code? | |
| 152 | − | |
| 153 | −The user mode registers are stored in the RSE area of the MCA/INIT on | |
| 154 | −entry to the OS and are restored from there on return to SAL, so user | |
| 155 | −mode registers are preserved across a recoverable MCA/INIT. Since the | |
| 156 | −OS has no idea what unwind data is available for the user space stack, | |
| 157 | −MCA/INIT never tries to backtrace user space. Which means that the OS | |
| 158 | −does not bother making the user space process look like a blocked task, | |
| 159 | −i.e. the OS does not copy pt_regs and switch_stack to the user space | |
| 160 | −stack. Also the OS has no idea how big the user space RSE and memory | |
| 161 | −stacks are, which makes it too risky to copy the saved state to a user | |
| 162 | −mode stack. | |
| 163 | − | |
| 164 | −--- | |
| 165 | − | |
| 166 | −How do we get a backtrace on the tasks that were running when MCA/INIT | |
| 167 | −was delivered? | |
| 168 | − | |
| 169 | −mca.c:::ia64_mca_modify_original_stack(). That identifies and | |
| 170 | −verifies the original kernel stack, copies the dirty registers from | |
| 171 | −the MCA/INIT stack's RSE to the original stack's RSE, copies the | |
| 172 | −skeleton struct pt_regs and switch_stack to the original stack, fills | |
| 173 | −in the skeleton structures from the PAL minstate area and updates the | |
| 174 | −original stack's thread.ksp. That makes the original stack look | |
| 175 | −exactly like any other blocked task, i.e. it now appears to be | |
| 176 | −sleeping. To get a backtrace, just start with thread.ksp for the | |
| 177 | −original task and unwind like any other sleeping task. | |
| 178 | − | |
| 179 | −--- | |
| 180 | − | |
| 181 | −How do we identify the tasks that were running when MCA/INIT was | |
| 182 | −delivered? | |
| 183 | − | |
| 184 | −If the previous task has been verified and converted to a blocked | |
| 185 | −state, then sos->prev_task on the MCA/INIT stack is updated to point to | |
| 186 | −the previous task. You can look at that field in dumps or debuggers. | |
| 187 | −To help distinguish between the handler and the original tasks, | |
| 188 | −handlers have _TIF_MCA_INIT set in thread_info.flags. | |
| 189 | − | |
| 190 | −The sos data is always in the MCA/INIT handler stack, at offset | |
| 191 | −MCA_SOS_OFFSET. You can get that value from mca_asm.h or calculate it | |
| 192 | −as KERNEL_STACK_SIZE - sizeof(struct pt_regs) - sizeof(struct | |
| 193 | −ia64_sal_os_state), with 16 byte alignment for all structures. | |
| 194 | − | |
| 195 | −Also the comm field of the MCA/INIT task is modified to include the pid | |
| 196 | −of the original task, for humans to use. For example, a comm field of | |
| 197 | −'MCA 12159' means that pid 12159 was running when the MCA was | |
| 198 | −delivered. | |
| @@ -1,165 +0,0 @@ | ||
| 1 | −============== | |
| 2 | −Serial Devices | |
| 3 | −============== | |
| 4 | − | |
| 5 | −Serial Device Naming | |
| 6 | −==================== | |
| 7 | − | |
| 8 | − As of 2.6.10, serial devices on ia64 are named based on the | |
| 9 | − order of ACPI and PCI enumeration. The first device in the | |
| 10 | − ACPI namespace (if any) becomes /dev/ttyS0, the second becomes | |
| 11 | − /dev/ttyS1, etc., and PCI devices are named sequentially | |
| 12 | − starting after the ACPI devices. | |
| 13 | − | |
| 14 | − Prior to 2.6.10, there were confusing exceptions to this: | |
| 15 | − | |
| 16 | − - Firmware on some machines (mostly from HP) provides an HCDP | |
| 17 | − table[1] that tells the kernel about devices that can be used | |
| 18 | − as a serial console. If the user specified "console=ttyS0" | |
| 19 | − or the EFI ConOut path contained only UART devices, the | |
| 20 | − kernel registered the device described by the HCDP as | |
| 21 | − /dev/ttyS0. | |
| 22 | − | |
| 23 | − - If there was no HCDP, we assumed there were UARTs at the | |
| 24 | − legacy COM port addresses (I/O ports 0x3f8 and 0x2f8), so | |
| 25 | − the kernel registered those as /dev/ttyS0 and /dev/ttyS1. | |
| 26 | − | |
| 27 | − Any additional ACPI or PCI devices were registered sequentially | |
| 28 | − after /dev/ttyS0 as they were discovered. | |
| 29 | − | |
| 30 | − With an HCDP, device names changed depending on EFI configuration | |
| 31 | − and "console=" arguments. Without an HCDP, device names didn't | |
| 32 | − change, but we registered devices that might not really exist. | |
| 33 | − | |
| 34 | − For example, an HP rx1600 with a single built-in serial port | |
| 35 | − (described in the ACPI namespace) plus an MP[2] (a PCI device) has | |
| 36 | − these ports: | |
| 37 | − | |
| 38 | − ========== ========== ============ ============ ======= | |
| 39 | − Type MMIO pre-2.6.10 pre-2.6.10 2.6.10+ | |
| 40 | − address | |
| 41 | − (EFI console (EFI console | |
| 42 | − on builtin) on MP port) | |
| 43 | − ========== ========== ============ ============ ======= | |
| 44 | − builtin 0xff5e0000 ttyS0 ttyS1 ttyS0 | |
| 45 | − MP UPS 0xf8031000 ttyS1 ttyS2 ttyS1 | |
| 46 | − MP Console 0xf8030000 ttyS2 ttyS0 ttyS2 | |
| 47 | − MP 2 0xf8030010 ttyS3 ttyS3 ttyS3 | |
| 48 | − MP 3 0xf8030038 ttyS4 ttyS4 ttyS4 | |
| 49 | − ========== ========== ============ ============ ======= | |
| 50 | − | |
| 51 | −Console Selection | |
| 52 | −================= | |
| 53 | − | |
| 54 | − EFI knows what your console devices are, but it doesn't tell the | |
| 55 | − kernel quite enough to actually locate them. The DIG64 HCDP | |
| 56 | − table[1] does tell the kernel where potential serial console | |
| 57 | − devices are, but not all firmware supplies it. Also, EFI supports | |
| 58 | − multiple simultaneous consoles and doesn't tell the kernel which | |
| 59 | − should be the "primary" one. | |
| 60 | − | |
| 61 | − So how do you tell Linux which console device to use? | |
| 62 | − | |
| 63 | − - If your firmware supplies the HCDP, it is simplest to | |
| 64 | − configure EFI with a single device (either a UART or a VGA | |
| 65 | − card) as the console. Then you don't need to tell Linux | |
| 66 | − anything; the kernel will automatically use the EFI console. | |
| 67 | − | |
| 68 | − (This works only in 2.6.6 or later; prior to that you had | |
| 69 | − to specify "console=ttyS0" to get a serial console.) | |
| 70 | − | |
| 71 | − - Without an HCDP, Linux defaults to a VGA console unless you | |
| 72 | − specify a "console=" argument. | |
| 73 | − | |
| 74 | − NOTE: Don't assume that a serial console device will be /dev/ttyS0. | |
| 75 | − It might be ttyS1, ttyS2, etc. Make sure you have the appropriate | |
| 76 | − entries in /etc/inittab (for getty) and /etc/securetty (to allow | |
| 77 | − root login). | |
| 78 | − | |
| 79 | −Early Serial Console | |
| 80 | −==================== | |
| 81 | − | |
| 82 | − The kernel can't start using a serial console until it knows where | |
| 83 | − the device lives. Normally this happens when the driver enumerates | |
| 84 | − all the serial devices, which can happen a minute or more after the | |
| 85 | − kernel starts booting. | |
| 86 | − | |
| 87 | − 2.6.10 and later kernels have an "early uart" driver that works | |
| 88 | − very early in the boot process. The kernel will automatically use | |
| 89 | − this if the user supplies an argument like "console=uart,io,0x3f8", | |
| 90 | − or if the EFI console path contains only a UART device and the | |
| 91 | − firmware supplies an HCDP. | |
| 92 | − | |
| 93 | −Troubleshooting Serial Console Problems | |
| 94 | −======================================= | |
| 95 | − | |
| 96 | − No kernel output after elilo prints "Uncompressing Linux... done": | |
| 97 | − | |
| 98 | − - You specified "console=ttyS0" but Linux changed the device | |
| 99 | − to which ttyS0 refers. Configure exactly one EFI console | |
| 100 | − device[3] and remove the "console=" option. | |
| 101 | − | |
| 102 | − - The EFI console path contains both a VGA device and a UART. | |
| 103 | − EFI and elilo use both, but Linux defaults to VGA. Remove | |
| 104 | − the VGA device from the EFI console path[3]. | |
| 105 | − | |
| 106 | − - Multiple UARTs selected as EFI console devices. EFI and | |
| 107 | − elilo use all selected devices, but Linux uses only one. | |
| 108 | − Make sure only one UART is selected in the EFI console | |
| 109 | − path[3]. | |
| 110 | − | |
| 111 | − - You're connected to an HP MP port[2] but have a non-MP UART | |
| 112 | − selected as EFI console device. EFI uses the MP as a | |
| 113 | − console device even when it isn't explicitly selected. | |
| 114 | − Either move the console cable to the non-MP UART, or change | |
| 115 | − the EFI console path[3] to the MP UART. | |
| 116 | − | |
| 117 | − Long pause (60+ seconds) between "Uncompressing Linux... done" and | |
| 118 | − start of kernel output: | |
| 119 | − | |
| 120 | − - No early console because you used "console=ttyS<n>". Remove | |
| 121 | − the "console=" option if your firmware supplies an HCDP. | |
| 122 | − | |
| 123 | − - If you don't have an HCDP, the kernel doesn't know where | |
| 124 | − your console lives until the driver discovers serial | |
| 125 | − devices. Use "console=uart,io,0x3f8" (or appropriate | |
| 126 | − address for your machine). | |
| 127 | − | |
| 128 | − Kernel and init script output works fine, but no "login:" prompt: | |
| 129 | − | |
| 130 | − - Add getty entry to /etc/inittab for console tty. Look for | |
| 131 | − the "Adding console on ttyS<n>" message that tells you which | |
| 132 | − device is the console. | |
| 133 | − | |
| 134 | − "login:" prompt, but can't login as root: | |
| 135 | − | |
| 136 | − - Add entry to /etc/securetty for console tty. | |
| 137 | − | |
| 138 | − No ACPI serial devices found in 2.6.17 or later: | |
| 139 | − | |
| 140 | − - Turn on CONFIG_PNP and CONFIG_PNPACPI. Prior to 2.6.17, ACPI | |
| 141 | − serial devices were discovered by 8250_acpi. In 2.6.17, | |
| 142 | − 8250_acpi was replaced by the combination of 8250_pnp and | |
| 143 | − CONFIG_PNPACPI. | |
| 144 | − | |
| 145 | − | |
| 146 | − | |
| 147 | −[1] | |
| 148 | − http://www.dig64.org/specifications/agreement | |
| 149 | − The table was originally defined as the "HCDP" for "Headless | |
| 150 | − Console/Debug Port." The current version is the "PCDP" for | |
| 151 | − "Primary Console and Debug Port Devices." | |
| 152 | − | |
| 153 | −[2] | |
| 154 | − The HP MP (management processor) is a PCI device that provides | |
| 155 | − several UARTs. One of the UARTs is often used as a console; the | |
| 156 | − EFI Boot Manager identifies it as "Acpi(HWP0002,700)/Pci(...)/Uart". | |
| 157 | − The external connection is usually a 25-pin connector, and a | |
| 158 | − special dongle converts that to three 9-pin connectors, one of | |
| 159 | − which is labelled "Console." | |
| 160 | − | |
| 161 | −[3] | |
| 162 | − EFI console devices are configured using the EFI Boot Manager | |
| 163 | − "Boot option maintenance" menu. You may have to interrupt the | |
| 164 | − boot sequence to use this menu, and you will have to reset the | |
| 165 | − box after changing console configuration. | |
| @@ -12,7 +12,6 @@ implementation. · 11 unmodified lines | ||
| 12 | 12 | arc/index |
| 13 | 13 | arm/index |
| 14 | 14 | arm64/index |
| 15 | − ia64/index | |
| 16 | 15 | loongarch/index |
| 17 | 16 | m68k/index |
| 18 | 17 | mips/index |
| @@ -80,9 +80,6 @@ ionice.c tool:: · 79 unmodified lines | ||
| 80 | 80 | #elif defined(__x86_64__) |
| 81 | 81 | #define __NR_ioprio_set 251 |
| 82 | 82 | #define __NR_ioprio_get 252 |
| 83 | − #elif defined(__ia64__) | |
| 84 | − #define __NR_ioprio_set 1274 | |
| 85 | − #define __NR_ioprio_get 1275 | |
| 86 | 83 | #else |
| 87 | 84 | #error "Unsupported arch" |
| 88 | 85 | #endif |
| @@ -40,12 +40,6 @@ Command Line Switches · 39 unmodified lines | ||
| 40 | 40 | supplied here is lower than the number of physically available CPUs, then |
| 41 | 41 | those CPUs can not be brought online later. |
| 42 | 42 | |
| 43 | −``additional_cpus=n`` | |
| 44 | − Use this to limit hotpluggable CPUs. This option sets | |
| 45 | − ``cpu_possible_mask = cpu_present_mask + additional_cpus`` | |
| 46 | − | |
| 47 | − This option is limited to the IA64 architecture. | |
| 48 | − | |
| 49 | 43 | ``possible_cpus=n`` |
| 50 | 44 | This option sets ``possible_cpus`` bits in ``cpu_possible_mask``. |
| 51 | 45 | |
| @@ -23,9 +23,9 @@ Retrieving a full system memory dump is also possible over the FireWire, · 22 unmodified lines | ||
| 23 | 23 | using data transfer rates in the order of 10MB/s or more. |
| 24 | 24 | |
| 25 | 25 | With most FireWire controllers, memory access is limited to the low 4 GB |
| 26 | −of physical address space. This can be a problem on IA64 machines where | |
| 27 | −memory is located mostly above that limit, but it is rarely a problem on | |
| 28 | −more common hardware such as x86, x86-64 and PowerPC. | |
| 26 | +of physical address space. This can be a problem on machines where memory is | |
| 27 | +located mostly above that limit, but it is rarely a problem on more common | |
| 28 | +hardware such as x86, x86-64 and PowerPC. | |
| 29 | 29 | |
| 30 | 30 | At least LSI FW643e and FW643e2 controllers are known to support access to |
| 31 | 31 | physical addresses above 4 GB, but this feature is currently not enabled by |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | TODO | |
| 13 | 13 | | csky: | TODO | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | TODO | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | TODO | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | ok | |
| 14 | 14 | | hexagon: | ok | |
| 15 | − | ia64: | ok | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | ok | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | TODO | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | TODO | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | ok | |
| 14 | 14 | | hexagon: | ok | |
| 15 | − | ia64: | ok | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | TODO | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | TODO | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | TODO | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | ok | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | TODO | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | ok | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | TODO | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | TODO | |
| 14 | 14 | | hexagon: | ok | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | ok | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | ok | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | ok | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | TODO | |
| 13 | 13 | | csky: | ok | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | ok | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | ok | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | ok | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | ok | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | TODO | |
| 13 | 13 | | csky: | TODO | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | TODO | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | ok | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | ok | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | TODO | |
| 13 | 13 | | csky: | TODO | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | TODO | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | ok | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | ok | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | TODO | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | TODO | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | ok | |
| 14 | 14 | | hexagon: | ok | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | ok | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | ok | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | ok | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | ok | |
| 14 | 14 | | hexagon: | ok | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | ok | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | ok | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -35,7 +35,6 @@ · 34 unmodified lines | ||
| 35 | 35 | | arm64: | ok | |
| 36 | 36 | | csky: | TODO | |
| 37 | 37 | | hexagon: | TODO | |
| 38 | − | ia64: | TODO | | |
| 39 | 38 | | loongarch: | TODO | |
| 40 | 39 | | m68k: | TODO | |
| 41 | 40 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | .. | |
| 14 | 14 | | hexagon: | .. | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | .. | |
| 18 | 17 | | microblaze: | .. | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | ok | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | ok | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | TODO | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | ok | |
| 14 | 14 | | hexagon: | ok | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | ok | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | ok | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | TODO | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | .. | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | ok | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | ok | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -13,7 +13,6 @@ · 12 unmodified lines | ||
| 13 | 13 | | arm64: | ok | |
| 14 | 14 | | csky: | ok | |
| 15 | 15 | | hexagon: | TODO | |
| 16 | − | ia64: | TODO | | |
| 17 | 16 | | loongarch: | ok | |
| 18 | 17 | | m68k: | TODO | |
| 19 | 18 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | TODO | |
| 13 | 13 | | csky: | TODO | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | ok | | |
| 16 | 15 | | loongarch: | TODO | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | .. | |
| 14 | 14 | | hexagon: | .. | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | .. | |
| 18 | 17 | | microblaze: | .. | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | TODO | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | TODO | |
| 17 | 16 | | m68k: | .. | |
| 18 | 17 | | microblaze: | .. | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | TODO | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | TODO | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | TODO | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -12,7 +12,6 @@ · 11 unmodified lines | ||
| 12 | 12 | | arm64: | ok | |
| 13 | 13 | | csky: | TODO | |
| 14 | 14 | | hexagon: | TODO | |
| 15 | − | ia64: | TODO | | |
| 16 | 15 | | loongarch: | ok | |
| 17 | 16 | | m68k: | TODO | |
| 18 | 17 | | microblaze: | TODO | |
| @@ -53,7 +53,7 @@ knowledge about the kernel Makefiles, plus detailed knowledge about the · 52 unmodified lines | ||
| 53 | 53 | public interface for kbuild. |
| 54 | 54 | |
| 55 | 55 | *Arch developers* are people who work on an entire architecture, such |
| 56 | −as sparc or ia64. Arch developers need to know about the arch Makefile | |
| 56 | +as sparc or x86. Arch developers need to know about the arch Makefile | |
| 57 | 57 | as well as kbuild Makefiles. |
| 58 | 58 | |
| 59 | 59 | *Kbuild developers* are people who work on the kernel build system itself. |
| @@ -64,8 +64,8 @@ c. Multi-buffer receive mode. Scattering of packet across multiple · 63 unmodified lines | ||
| 64 | 64 | IBM xSeries). |
| 65 | 65 | |
| 66 | 66 | d. MSI/MSI-X. Can be enabled on platforms which support this feature |
| 67 | − (IA64, Xeon) resulting in noticeable performance improvement(up to 7% | |
| 68 | − on certain platforms). | |
| 67 | + resulting in noticeable performance improvement (up to 7% on certain | |
| 68 | + platforms). | |
| 69 | 69 | |
| 70 | 70 | e. Statistics. Comprehensive MAC-level and software statistics displayed |
| 71 | 71 | using "ethtool -S" option. |
| @@ -10,7 +10,7 @@ Context switch · 9 unmodified lines | ||
| 10 | 10 | By default, the switch_to arch function is called with the runqueue |
| 11 | 11 | locked. This is usually not a problem unless switch_to may need to |
| 12 | 12 | take the runqueue lock. This is usually due to a wake up operation in |
| 13 | −the context switch. See arch/ia64/include/asm/switch_to.h for an example. | |
| 13 | +the context switch. | |
| 14 | 14 | |
| 15 | 15 | To request the scheduler call switch_to with the runqueue unlocked, |
| 16 | 16 | you must `#define __ARCH_WANT_UNLOCKED_CTXSW` in a header file |
| @@ -68,7 +68,5 @@ Possible arch/ problems · 51 unmodified lines | ||
| 68 | 68 | |
| 69 | 69 | Possible arch problems I found (and either tried to fix or didn't): |
| 70 | 70 | |
| 71 | −ia64 - is safe_halt call racy vs interrupts? (does it sleep?) (See #4a) | |
| 72 | − | |
| 73 | 71 | sparc - IRQs on at this point(?), change local_irq_save to _disable. |
| 74 | 72 | - TODO: needs secondary CPUs to disable preempt (See #1) |
| @@ -315,7 +315,6 @@ architectures: · 314 unmodified lines | ||
| 315 | 315 | - i386 (Supports jump optimization) |
| 316 | 316 | - x86_64 (AMD-64, EM64T) (Supports jump optimization) |
| 317 | 317 | - ppc64 |
| 318 | −- ia64 (Does not support probes on instruction slot1.) | |
| 319 | 318 | - sparc64 (Return probes not yet implemented.) |
| 320 | 319 | - arm |
| 321 | 320 | - ppc |
| @@ -18,7 +18,6 @@ · 17 unmodified lines | ||
| 18 | 18 | TODOList: |
| 19 | 19 | |
| 20 | 20 | * arm/index |
| 21 | −* ia64/index | |
| 22 | 21 | * m68k/index |
| 23 | 22 | * nios2/index |
| 24 | 23 | * powerpc/index |
| @@ -49,12 +49,6 @@ CPU热拔插支持的一个更新颖的用途是它在SMP的暂停恢复支持 · 48 unmodified lines | ||
| 49 | 49 | 限制内核将支持的CPU总量。如果这里提供的数量低于实际可用的CPU数量，那么其他CPU |
| 50 | 50 | 以后就不能上线了。 |
| 51 | 51 | |
| 52 | −``additional_cpus=n`` | |
| 53 | − 使用它来限制可热插拔的CPU。该选项设置 | |
| 54 | − ``cpu_possible_mask = cpu_present_mask + additional_cpus`` | |
| 55 | − | |
| 56 | − 这个选项只限于IA64架构。 | |
| 57 | − | |
| 58 | 52 | ``possible_cpus=n`` |
| 59 | 53 | 这个选项设置 ``cpu_possible_mask`` 中的 ``possible_cpus`` 位。 |
| 60 | 54 | |
| @@ -20,8 +20,7 @@ · 19 unmodified lines | ||
| 20 | 20 | ========== |
| 21 | 21 | 1. 运行队列锁 |
| 22 | 22 | 默认情况下，switch_to arch函数在调用时锁定了运行队列。这通常不是一个问题，除非 |
| 23 | −switch_to可能需要获取运行队列锁。这通常是由于上下文切换中的唤醒操作造成的。见 | |
| 24 | −arch/ia64/include/asm/switch_to.h的例子。 | |
| 23 | +switch_to可能需要获取运行队列锁。这通常是由于上下文切换中的唤醒操作造成的。 | |
| 25 | 24 | |
| 26 | 25 | 为了要求调度器在运行队列解锁的情况下调用switch_to，你必须在头文件 |
| 27 | 26 | 中`#define __ARCH_WANT_UNLOCKED_CTXSW`(通常是定义switch_to的那个文件）。 |
| @@ -68,7 +67,5 @@ arch/x86/kernel/process.c有轮询和睡眠空闲函数的例子。 · 40 unmodified lines | ||
| 68 | 67 | |
| 69 | 68 | 我发现的可能的arch问题（并试图解决或没有解决）。: |
| 70 | 69 | |
| 71 | −ia64 - safe_halt的调用与中断相比，是否很荒谬？ (它睡眠了吗) (参考 #4a) | |
| 72 | − | |
| 73 | 70 | sparc - 在这一点上，IRQ是开着的（？），把local_irq_save改为_disable。 |
| 74 | 71 | - 待办事项: 需要第二个CPU来禁用抢占 (参考 #1) |
| @@ -9935,12 +9935,6 @@ F: Documentation/driver-api/i3c · 9934 unmodified lines | ||
| 9935 | 9935 | F: drivers/i3c/ |
| 9936 | 9936 | F: include/linux/i3c/ |
| 9937 | 9937 | |
| 9938 | −IA64 (Itanium) PLATFORM | |
| 9939 | −L: linux-ia64@vger.kernel.org | |
| 9940 | −S: Orphan | |
| 9941 | −F: Documentation/arch/ia64/ | |
| 9942 | −F: arch/ia64/ | |
| 9943 | − | |
| 9944 | 9938 | IBM Operation Panel Input Driver |
| 9945 | 9939 | M: Eddie James <eajames@linux.ibm.com> |
| 9946 | 9940 | L: linux-input@vger.kernel.org |
| @@ -16269,11 +16263,6 @@ L: linux-i2c@vger.kernel.org · 6322 unmodified lines | ||
| 16269 | 16263 | S: Maintained |
| 16270 | 16264 | F: drivers/i2c/muxes/i2c-mux-pca9541.c |
| 16271 | 16265 | |
| 16272 | −PCDP - PRIMARY CONSOLE AND DEBUG PORT | |
| 16273 | −M: Khalid Aziz <khalid@gonehiking.org> | |
| 16274 | −S: Maintained | |
| 16275 | −F: drivers/firmware/pcdp.* | |
| 16276 | − | |
| 16277 | 16266 | PCI DRIVER FOR AARDVARK (Marvell Armada 3700) |
| 16278 | 16267 | M: Thomas Petazzoni <thomas.petazzoni@bootlin.com> |
| 16279 | 16268 | M: Pali Rohár <pali@kernel.org> |
| @@ -378,7 +378,7 @@ include $(srctree)/scripts/subarch.include · 377 unmodified lines | ||
| 378 | 378 | # When performing cross compilation for other architectures ARCH shall be set |
| 379 | 379 | # to the target architecture. (See arch/* for the possibilities). |
| 380 | 380 | # ARCH can be set during invocation of make: |
| 381 | −# make ARCH=ia64 | |
| 381 | +# make ARCH=arm64 | |
| 382 | 382 | # Another way is to have ARCH set in the environment. |
| 383 | 383 | # The default ARCH is the host where make is executed. |
| 384 | 384 | |
| @@ -386,7 +386,7 @@ include $(srctree)/scripts/subarch.include · 1 unmodified line | ||
| 386 | 386 | # during compilation. Only gcc and related bin-utils executables |
| 387 | 387 | # are prefixed with $(CROSS_COMPILE). |
| 388 | 388 | # CROSS_COMPILE can be set on the command line |
| 389 | −# make CROSS_COMPILE=ia64-linux- | |
| 389 | +# make CROSS_COMPILE=aarch64-linux-gnu- | |
| 390 | 390 | # Alternatively CROSS_COMPILE can be set in the environment. |
| 391 | 391 | # Default value for CROSS_COMPILE is not to prefix executables |
| 392 | 392 | # Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile |
| @@ -1088,7 +1088,6 @@ config HAVE_ARCH_COMPAT_MMAP_BASES · 1087 unmodified lines | ||
| 1088 | 1088 | config PAGE_SIZE_LESS_THAN_64KB |
| 1089 | 1089 | def_bool y |
| 1090 | 1090 | depends on !ARM64_64K_PAGES |
| 1091 | − depends on !IA64_PAGE_SIZE_64KB | |
| 1092 | 1091 | depends on !PAGE_SIZE_64KB |
| 1093 | 1092 | depends on !PARISC_PAGE_SIZE_64KB |
| 1094 | 1093 | depends on PAGE_SIZE_LESS_THAN_256KB |
| @@ -1,3 +0,0 @@ | ||
| 1 | −# SPDX-License-Identifier: GPL-2.0-only | |
| 2 | −obj-y += kernel/ mm/ | |
| 3 | −obj-$(CONFIG_IA64_SGI_UV) += uv/ | |
| @@ -1,394 +0,0 @@ | ||
| 1 | −# SPDX-License-Identifier: GPL-2.0 | |
| 2 | −config PGTABLE_LEVELS | |
| 3 | − int "Page Table Levels" if !IA64_PAGE_SIZE_64KB | |
| 4 | − range 3 4 if !IA64_PAGE_SIZE_64KB | |
| 5 | − default 3 | |
| 6 | − | |
| 7 | −menu "Processor type and features" | |
| 8 | − | |
| 9 | −config IA64 | |
| 10 | − bool | |
| 11 | − select ARCH_BINFMT_ELF_EXTRA_PHDRS | |
| 12 | − select ARCH_HAS_CPU_FINALIZE_INIT | |
| 13 | − select ARCH_HAS_DMA_MARK_CLEAN | |
| 14 | − select ARCH_HAS_STRNCPY_FROM_USER | |
| 15 | − select ARCH_HAS_STRNLEN_USER | |
| 16 | − select ARCH_MIGHT_HAVE_PC_PARPORT | |
| 17 | − select ARCH_MIGHT_HAVE_PC_SERIO | |
| 18 | − select ACPI | |
| 19 | − select ACPI_NUMA if NUMA | |
| 20 | − select ARCH_ENABLE_MEMORY_HOTPLUG | |
| 21 | − select ARCH_ENABLE_MEMORY_HOTREMOVE | |
| 22 | − select ARCH_SUPPORTS_ACPI | |
| 23 | − select ACPI_SYSTEM_POWER_STATES_SUPPORT if ACPI | |
| 24 | − select ARCH_MIGHT_HAVE_ACPI_PDC if ACPI | |
| 25 | − select FORCE_PCI | |
| 26 | − select PCI_DOMAINS if PCI | |
| 27 | − select PCI_MSI | |
| 28 | − select PCI_SYSCALL if PCI | |
| 29 | − select HAS_IOPORT | |
| 30 | − select HAVE_ASM_MODVERSIONS | |
| 31 | − select HAVE_UNSTABLE_SCHED_CLOCK | |
| 32 | − select HAVE_EXIT_THREAD | |
| 33 | − select HAVE_KPROBES | |
| 34 | − select HAVE_KRETPROBES | |
| 35 | − select HAVE_FTRACE_MCOUNT_RECORD | |
| 36 | − select HAVE_DYNAMIC_FTRACE if (!ITANIUM) | |
| 37 | − select HAVE_FUNCTION_TRACER | |
| 38 | − select HAVE_SETUP_PER_CPU_AREA | |
| 39 | − select TTY | |
| 40 | − select HAVE_ARCH_TRACEHOOK | |
| 41 | − select HAVE_FUNCTION_DESCRIPTORS | |
| 42 | − select HAVE_VIRT_CPU_ACCOUNTING | |
| 43 | − select HUGETLB_PAGE_SIZE_VARIABLE if HUGETLB_PAGE | |
| 44 | − select GENERIC_IRQ_PROBE | |
| 45 | − select GENERIC_PENDING_IRQ if SMP | |
| 46 | − select GENERIC_IRQ_SHOW | |
| 47 | − select GENERIC_IRQ_LEGACY | |
| 48 | − select ARCH_HAVE_NMI_SAFE_CMPXCHG | |
| 49 | − select GENERIC_IOMAP | |
| 50 | − select GENERIC_IOREMAP | |
| 51 | − select GENERIC_SMP_IDLE_THREAD | |
| 52 | − select ARCH_TASK_STRUCT_ON_STACK | |
| 53 | − select ARCH_TASK_STRUCT_ALLOCATOR | |
| 54 | − select ARCH_THREAD_STACK_ALLOCATOR | |
| 55 | − select ARCH_CLOCKSOURCE_DATA | |
| 56 | − select GENERIC_TIME_VSYSCALL | |
| 57 | − select LEGACY_TIMER_TICK | |
| 58 | − select SWIOTLB | |
| 59 | − select SYSCTL_ARCH_UNALIGN_NO_WARN | |
| 60 | − select HAVE_MOD_ARCH_SPECIFIC | |
| 61 | − select MODULES_USE_ELF_RELA | |
| 62 | − select ARCH_USE_CMPXCHG_LOCKREF | |
| 63 | − select HAVE_ARCH_AUDITSYSCALL | |
| 64 | − select NEED_DMA_MAP_STATE | |
| 65 | − select NEED_SG_DMA_LENGTH | |
| 66 | − select NUMA if !FLATMEM | |
| 67 | − select PCI_MSI_ARCH_FALLBACKS if PCI_MSI | |
| 68 | − select ZONE_DMA32 | |
| 69 | − select FUNCTION_ALIGNMENT_32B | |
| 70 | − default y | |
| 71 | − help | |
| 72 | − The Itanium Processor Family is Intel's 64-bit successor to | |
| 73 | − the 32-bit X86 line. The IA-64 Linux project has a home | |
| 74 | − page at <http://www.linuxia64.org/> and a mailing list at | |
| 75 | − <linux-ia64@vger.kernel.org>. | |
| 76 | − | |
| 77 | −config 64BIT | |
| 78 | − bool | |
| 79 | − select ATA_NONSTANDARD if ATA | |
| 80 | − default y | |
| 81 | − | |
| 82 | −config MMU | |
| 83 | − bool | |
| 84 | − default y | |
| 85 | − | |
| 86 | −config STACKTRACE_SUPPORT | |
| 87 | − def_bool y | |
| 88 | − | |
| 89 | −config GENERIC_LOCKBREAK | |
| 90 | − def_bool n | |
| 91 | − | |
| 92 | −config GENERIC_CALIBRATE_DELAY | |
| 93 | − bool | |
| 94 | − default y | |
| 95 | − | |
| 96 | −config DMI | |
| 97 | − bool | |
| 98 | − default y | |
| 99 | − select DMI_SCAN_MACHINE_NON_EFI_FALLBACK | |
| 100 | − | |
| 101 | −config EFI | |
| 102 | − bool | |
| 103 | − select UCS2_STRING | |
| 104 | − default y | |
| 105 | − | |
| 106 | −config SCHED_OMIT_FRAME_POINTER | |
| 107 | − bool | |
| 108 | − default y | |
| 109 | − | |
| 110 | −config IA64_UNCACHED_ALLOCATOR | |
| 111 | − bool | |
| 112 | − select GENERIC_ALLOCATOR | |
| 113 | − | |
| 114 | −config ARCH_USES_PG_UNCACHED | |
| 115 | − def_bool y | |
| 116 | − depends on IA64_UNCACHED_ALLOCATOR | |
| 117 | − | |
| 118 | −config AUDIT_ARCH | |
| 119 | − bool | |
| 120 | − default y | |
| 121 | − | |
| 122 | −choice | |
| 123 | − prompt "Processor type" | |
| 124 | − default ITANIUM | |
| 125 | − | |
| 126 | −config ITANIUM | |
| 127 | − bool "Itanium" | |
| 128 | − help | |
| 129 | − Select your IA-64 processor type. The default is Itanium. | |
| 130 | − This choice is safe for all IA-64 systems, but may not perform | |
| 131 | − optimally on systems with, say, Itanium 2 or newer processors. | |
| 132 | − | |
| 133 | −config MCKINLEY | |
| 134 | − bool "Itanium 2" | |
| 135 | − help | |
| 136 | − Select this to configure for an Itanium 2 (McKinley) processor. | |
| 137 | − | |
| 138 | −endchoice | |
| 139 | − | |
| 140 | −choice | |
| 141 | − prompt "Kernel page size" | |
| 142 | − default IA64_PAGE_SIZE_16KB | |
| 143 | − | |
| 144 | −config IA64_PAGE_SIZE_4KB | |
| 145 | − bool "4KB" | |
| 146 | − help | |
| 147 | − This lets you select the page size of the kernel. For best IA-64 | |
| 148 | − performance, a page size of 8KB or 16KB is recommended. For best | |
| 149 | − IA-32 compatibility, a page size of 4KB should be selected (the vast | |
| 150 | − majority of IA-32 binaries work perfectly fine with a larger page | |
| 151 | − size). For Itanium 2 or newer systems, a page size of 64KB can also | |
| 152 | − be selected. | |
| 153 | − | |
| 154 | − 4KB For best IA-32 compatibility | |
| 155 | − 8KB For best IA-64 performance | |
| 156 | − 16KB For best IA-64 performance | |
| 157 | − 64KB Requires Itanium 2 or newer processor. | |
| 158 | − | |
| 159 | − If you don't know what to do, choose 16KB. | |
| 160 | − | |
| 161 | −config IA64_PAGE_SIZE_8KB | |
| 162 | − bool "8KB" | |
| 163 | − | |
| 164 | −config IA64_PAGE_SIZE_16KB | |
| 165 | − bool "16KB" | |
| 166 | − | |
| 167 | −config IA64_PAGE_SIZE_64KB | |
| 168 | − depends on !ITANIUM | |
| 169 | − bool "64KB" | |
| 170 | − | |
| 171 | −endchoice | |
| 172 | − | |
| 173 | −source "kernel/Kconfig.hz" | |
| 174 | − | |
| 175 | −config IA64_BRL_EMU | |
| 176 | − bool | |
| 177 | − depends on ITANIUM | |
| 178 | − default y | |
| 179 | − | |
| 180 | −# align cache-sensitive data to 128 bytes | |
| 181 | −config IA64_L1_CACHE_SHIFT | |
| 182 | − int | |
| 183 | − default "7" if MCKINLEY | |
| 184 | − default "6" if ITANIUM | |
| 185 | − | |
| 186 | −config IA64_SGI_UV | |
| 187 | − bool "SGI-UV support" | |
| 188 | − help | |
| 189 | − Selecting this option will add specific support for running on SGI | |
| 190 | − UV based systems. If you have an SGI UV system or are building a | |
| 191 | − distro kernel, select this option. | |
| 192 | − | |
| 193 | −config IA64_HP_SBA_IOMMU | |
| 194 | − bool "HP SBA IOMMU support" | |
| 195 | − select DMA_OPS | |
| 196 | − default y | |
| 197 | − help | |
| 198 | − Say Y here to add support for the SBA IOMMU found on HP zx1 and | |
| 199 | − sx1000 systems. If you're unsure, answer Y. | |
| 200 | − | |
| 201 | −config IA64_CYCLONE | |
| 202 | − bool "Cyclone (EXA) Time Source support" | |
| 203 | − help | |
| 204 | − Say Y here to enable support for IBM EXA Cyclone time source. | |
| 205 | − If you're unsure, answer N. | |
| 206 | − | |
| 207 | −config ARCH_FORCE_MAX_ORDER | |
| 208 | − int | |
| 209 | − default "16" if HUGETLB_PAGE | |
| 210 | − default "10" | |
| 211 | − | |
| 212 | −config SMP | |
| 213 | − bool "Symmetric multi-processing support" | |
| 214 | − help | |
| 215 | − This enables support for systems with more than one CPU. If you have | |
| 216 | − a system with only one CPU, say N. If you have a system with more | |
| 217 | − than one CPU, say Y. | |
| 218 | − | |
| 219 | − If you say N here, the kernel will run on single and multiprocessor | |
| 220 | − systems, but will use only one CPU of a multiprocessor system. If | |
| 221 | − you say Y here, the kernel will run on many, but not all, | |
| 222 | − single processor systems. On a single processor system, the kernel | |
| 223 | − will run faster if you say N here. | |
| 224 | − | |
| 225 | − See also the SMP-HOWTO available at | |
| 226 | − <http://www.tldp.org/docs.html#howto>. | |
| 227 | − | |
| 228 | − If you don't know what to do here, say N. | |
| 229 | − | |
| 230 | −config NR_CPUS | |
| 231 | − int "Maximum number of CPUs (2-4096)" | |
| 232 | − range 2 4096 | |
| 233 | − depends on SMP | |
| 234 | − default "4096" | |
| 235 | − help | |
| 236 | − You should set this to the number of CPUs in your system, but | |
| 237 | − keep in mind that a kernel compiled for, e.g., 2 CPUs will boot but | |
| 238 | − only use 2 CPUs on a >2 CPU system. Setting this to a value larger | |
| 239 | − than 64 will cause the use of a CPU mask array, causing a small | |
| 240 | − performance hit. | |
| 241 | − | |
| 242 | −config HOTPLUG_CPU | |
| 243 | − bool "Support for hot-pluggable CPUs" | |
| 244 | − depends on SMP | |
| 245 | − default n | |
| 246 | − help | |
| 247 | − Say Y here to experiment with turning CPUs off and on. CPUs | |
| 248 | − can be controlled through /sys/devices/system/cpu/cpu#. | |
| 249 | − Say N if you want to disable CPU hotplug. | |
| 250 | − | |
| 251 | −config SCHED_SMT | |
| 252 | − bool "SMT scheduler support" | |
| 253 | − depends on SMP | |
| 254 | − help | |
| 255 | − Improves the CPU scheduler's decision making when dealing with | |
| 256 | − Intel IA64 chips with MultiThreading at a cost of slightly increased | |
| 257 | − overhead in some places. If unsure say N here. | |
| 258 | − | |
| 259 | −config PERMIT_BSP_REMOVE | |
| 260 | − bool "Support removal of Bootstrap Processor" | |
| 261 | − depends on HOTPLUG_CPU | |
| 262 | − default n | |
| 263 | − help | |
| 264 | − Say Y here if your platform SAL will support removal of BSP with HOTPLUG_CPU | |
| 265 | − support. | |
| 266 | − | |
| 267 | −config FORCE_CPEI_RETARGET | |
| 268 | − bool "Force assumption that CPEI can be re-targeted" | |
| 269 | − depends on PERMIT_BSP_REMOVE | |
| 270 | − default n | |
| 271 | − help | |
| 272 | − Say Y if you need to force the assumption that CPEI can be re-targeted to | |
| 273 | − any cpu in the system. This hint is available via ACPI 3.0 specifications. | |
| 274 | − Tiger4 systems are capable of re-directing CPEI to any CPU other than BSP. | |
| 275 | − This option it useful to enable this feature on older BIOS's as well. | |
| 276 | − You can also enable this by using boot command line option force_cpei=1. | |
| 277 | − | |
| 278 | −config ARCH_SELECT_MEMORY_MODEL | |
| 279 | − def_bool y | |
| 280 | − | |
| 281 | −config ARCH_FLATMEM_ENABLE | |
| 282 | − def_bool y | |
| 283 | − | |
| 284 | −config ARCH_SPARSEMEM_ENABLE | |
| 285 | − def_bool y | |
| 286 | − select SPARSEMEM_VMEMMAP_ENABLE | |
| 287 | − | |
| 288 | −config ARCH_SPARSEMEM_DEFAULT | |
| 289 | − def_bool y | |
| 290 | − depends on ARCH_SPARSEMEM_ENABLE | |
| 291 | − | |
| 292 | −config NUMA | |
| 293 | − bool "NUMA support" | |
| 294 | − depends on !FLATMEM | |
| 295 | − select SMP | |
| 296 | − select USE_PERCPU_NUMA_NODE_ID | |
| 297 | − help | |
| 298 | − Say Y to compile the kernel to support NUMA (Non-Uniform Memory | |
| 299 | − Access). This option is for configuring high-end multiprocessor | |
| 300 | − server systems. If in doubt, say N. | |
| 301 | − | |
| 302 | −config NODES_SHIFT | |
| 303 | − int "Max num nodes shift(3-10)" | |
| 304 | − range 3 10 | |
| 305 | − default "10" | |
| 306 | − depends on NUMA | |
| 307 | − help | |
| 308 | − This option specifies the maximum number of nodes in your SSI system. | |
| 309 | − MAX_NUMNODES will be 2^(This value). | |
| 310 | − If in doubt, use the default. | |
| 311 | − | |
| 312 | −config HAVE_ARCH_NODEDATA_EXTENSION | |
| 313 | − def_bool y | |
| 314 | − depends on NUMA | |
| 315 | − | |
| 316 | −config HAVE_MEMORYLESS_NODES | |
| 317 | − def_bool NUMA | |
| 318 | − | |
| 319 | −config ARCH_PROC_KCORE_TEXT | |
| 320 | − def_bool y | |
| 321 | − depends on PROC_KCORE | |
| 322 | − | |
| 323 | −config IA64_MCA_RECOVERY | |
| 324 | − bool "MCA recovery from errors other than TLB." | |
| 325 | − | |
| 326 | −config IA64_PALINFO | |
| 327 | − tristate "/proc/pal support" | |
| 328 | − help | |
| 329 | − If you say Y here, you are able to get PAL (Processor Abstraction | |
| 330 | − Layer) information in /proc/pal. This contains useful information | |
| 331 | − about the processors in your systems, such as cache and TLB sizes | |
| 332 | − and the PAL firmware version in use. | |
| 333 | − | |
| 334 | − To use this option, you have to ensure that the "/proc file system | |
| 335 | − support" (CONFIG_PROC_FS) is enabled, too. | |
| 336 | − | |
| 337 | −config IA64_MC_ERR_INJECT | |
| 338 | − tristate "MC error injection support" | |
| 339 | − help | |
| 340 | − Adds support for MC error injection. If enabled, the kernel | |
| 341 | − will provide a sysfs interface for user applications to | |
| 342 | − call MC error injection PAL procedures to inject various errors. | |
| 343 | − This is a useful tool for MCA testing. | |
| 344 | − | |
| 345 | − If you're unsure, do not select this option. | |
| 346 | − | |
| 347 | −config IA64_ESI | |
| 348 | − bool "ESI (Extensible SAL Interface) support" | |
| 349 | − help | |
| 350 | − If you say Y here, support is built into the kernel to | |
| 351 | − make ESI calls. ESI calls are used to support vendor-specific | |
| 352 | − firmware extensions, such as the ability to inject memory-errors | |
| 353 | − for test-purposes. If you're unsure, say N. | |
| 354 | − | |
| 355 | −config IA64_HP_AML_NFW | |
| 356 | − bool "Support ACPI AML calls to native firmware" | |
| 357 | − help | |
| 358 | − This driver installs a global ACPI Operation Region handler for | |
| 359 | − region 0xA1. AML methods can use this OpRegion to call arbitrary | |
| 360 | − native firmware functions. The driver installs the OpRegion | |
| 361 | − handler if there is an HPQ5001 device or if the user supplies | |
| 362 | − the "force" module parameter, e.g., with the "aml_nfw.force" | |
| 363 | − kernel command line option. | |
| 364 | − | |
| 365 | −endmenu | |
| 366 | − | |
| 367 | −config ARCH_SUPPORTS_KEXEC | |
| 368 | − def_bool !SMP || HOTPLUG_CPU | |
| 369 | − | |
| 370 | −config ARCH_SUPPORTS_CRASH_DUMP | |
| 371 | − def_bool IA64_MCA_RECOVERY && (!SMP || HOTPLUG_CPU) | |
| 372 | − | |
| 373 | −menu "Power management and ACPI options" | |
| 374 | − | |
| 375 | −source "kernel/power/Kconfig" | |
| 376 | − | |
| 377 | −source "drivers/acpi/Kconfig" | |
| 378 | − | |
| 379 | −if PM | |
| 380 | −menu "CPU Frequency scaling" | |
| 381 | −source "drivers/cpufreq/Kconfig" | |
| 382 | −endmenu | |
| 383 | −endif | |
| 384 | − | |
| 385 | −endmenu | |
| 386 | − | |
| 387 | −config MSPEC | |
| 388 | − tristate "Memory special operations driver" | |
| 389 | − depends on IA64 | |
| 390 | − select IA64_UNCACHED_ALLOCATOR | |
| 391 | − help | |
| 392 | − If you have an ia64 and you want to enable memory special | |
| 393 | − operations support (formerly known as fetchop), say Y here, | |
| 394 | − otherwise say N. | |
| @@ -1,55 +0,0 @@ | ||
| 1 | −# SPDX-License-Identifier: GPL-2.0 | |
| 2 | − | |
| 3 | −choice | |
| 4 | − prompt "Physical memory granularity" | |
| 5 | − default IA64_GRANULE_64MB | |
| 6 | − | |
| 7 | −config IA64_GRANULE_16MB | |
| 8 | − bool "16MB" | |
| 9 | − help | |
| 10 | − IA-64 identity-mapped regions use a large page size called "granules". | |
| 11 | − | |
| 12 | − Select "16MB" for a small granule size. | |
| 13 | − Select "64MB" for a large granule size. This is the current default. | |
| 14 | − | |
| 15 | −config IA64_GRANULE_64MB | |
| 16 | − bool "64MB" | |
| 17 | − depends on BROKEN | |
| 18 | − | |
| 19 | −endchoice | |
| 20 | − | |
| 21 | −config IA64_PRINT_HAZARDS | |
| 22 | − bool "Print possible IA-64 dependency violations to console" | |
| 23 | − depends on DEBUG_KERNEL | |
| 24 | − help | |
| 25 | − Selecting this option prints more information for Illegal Dependency | |
| 26 | − Faults, that is, for Read-after-Write (RAW), Write-after-Write (WAW), | |
| 27 | − or Write-after-Read (WAR) violations. This option is ignored if you | |
| 28 | − are compiling for an Itanium A step processor | |
| 29 | − (CONFIG_ITANIUM_ASTEP_SPECIFIC). If you're unsure, select Y. | |
| 30 | − | |
| 31 | −config DISABLE_VHPT | |
| 32 | − bool "Disable VHPT" | |
| 33 | − depends on DEBUG_KERNEL | |
| 34 | − help | |
| 35 | − The Virtual Hash Page Table (VHPT) enhances virtual address | |
| 36 | − translation performance. Normally you want the VHPT active but you | |
| 37 | − can select this option to disable the VHPT for debugging. If you're | |
| 38 | − unsure, answer N. | |
| 39 | − | |
| 40 | −config IA64_DEBUG_CMPXCHG | |
| 41 | − bool "Turn on compare-and-exchange bug checking (slow!)" | |
| 42 | − depends on DEBUG_KERNEL && PRINTK | |
| 43 | − help | |
| 44 | − Selecting this option turns on bug checking for the IA-64 | |
| 45 | − compare-and-exchange instructions. This is slow! Itaniums | |
| 46 | − from step B3 or later don't have this problem. If you're unsure, | |
| 47 | − select N. | |
| 48 | − | |
| 49 | −config IA64_DEBUG_IRQ | |
| 50 | − bool "Turn on irq debug checks (slow!)" | |
| 51 | − depends on DEBUG_KERNEL | |
| 52 | − help | |
| 53 | − Selecting this option turns on bug checking for the IA-64 irq_save | |
| 54 | − and restore instructions. It's useful for tracking down spinlock | |
| 55 | − problems, but slow! If you're unsure, select N. | |
| @@ -1,82 +0,0 @@ | ||
| 1 | −# | |
| 2 | −# ia64/Makefile | |
| 3 | −# | |
| 4 | −# This file is included by the global makefile so that you can add your own | |
| 5 | −# architecture-specific flags and dependencies. | |
| 6 | −# | |
| 7 | −# This file is subject to the terms and conditions of the GNU General Public | |
| 8 | −# License. See the file "COPYING" in the main directory of this archive | |
| 9 | −# for more details. | |
| 10 | −# | |
| 11 | −# Copyright (C) 1998-2004 by David Mosberger-Tang <davidm@hpl.hp.com> | |
| 12 | −# | |
| 13 | − | |
| 14 | −KBUILD_DEFCONFIG := generic_defconfig | |
| 15 | − | |
| 16 | −NM := $(CROSS_COMPILE)nm -B | |
| 17 | − | |
| 18 | −CHECKFLAGS += -D__ia64=1 -D__ia64__=1 -D_LP64 -D__LP64__ | |
| 19 | − | |
| 20 | −OBJCOPYFLAGS := --strip-all | |
| 21 | −LDFLAGS_vmlinux := -static | |
| 22 | −KBUILD_AFLAGS_KERNEL := -mconstant-gp | |
| 23 | −EXTRA := | |
| 24 | − | |
| 25 | −cflags-y := -pipe $(EXTRA) -ffixed-r13 -mfixed-range=f12-f15,f32-f127 \ | |
| 26 | − -frename-registers -fno-optimize-sibling-calls | |
| 27 | −KBUILD_CFLAGS_KERNEL := -mconstant-gp | |
| 28 | − | |
| 29 | −GAS_STATUS = $(shell $(srctree)/arch/ia64/scripts/check-gas "$(CC)" "$(OBJDUMP)") | |
| 30 | −KBUILD_CPPFLAGS += $(shell $(srctree)/arch/ia64/scripts/toolchain-flags "$(CC)" "$(OBJDUMP)" "$(READELF)") | |
| 31 | − | |
| 32 | −ifeq ($(GAS_STATUS),buggy) | |
| 33 | −$(error Sorry, you need a newer version of the assember, one that is built from \ | |
| 34 | − a source-tree that post-dates 18-Dec-2002. You can find a pre-compiled \ | |
| 35 | − static binary of such an assembler at: \ | |
| 36 | − \ | |
| 37 | − ftp://ftp.hpl.hp.com/pub/linux-ia64/gas-030124.tar.gz) | |
| 38 | −endif | |
| 39 | − | |
| 40 | −quiet_cmd_gzip = GZIP $@ | |
| 41 | −cmd_gzip = cat $(real-prereqs) | $(KGZIP) -n -f -9 > $@ | |
| 42 | − | |
| 43 | −quiet_cmd_objcopy = OBJCOPY $@ | |
| 44 | −cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@ | |
| 45 | − | |
| 46 | −KBUILD_CFLAGS += $(cflags-y) | |
| 47 | − | |
| 48 | −libs-y += arch/ia64/lib/ | |
| 49 | − | |
| 50 | −drivers-y += arch/ia64/pci/ arch/ia64/hp/common/ | |
| 51 | − | |
| 52 | −PHONY += compressed check | |
| 53 | − | |
| 54 | −all: compressed unwcheck | |
| 55 | − | |
| 56 | −compressed: vmlinux.gz | |
| 57 | − | |
| 58 | −vmlinuz: vmlinux.gz | |
| 59 | − | |
| 60 | −vmlinux.gz: vmlinux.bin FORCE | |
| 61 | − $(call if_changed,gzip) | |
| 62 | − | |
| 63 | −vmlinux.bin: vmlinux FORCE | |
| 64 | − $(call if_changed,objcopy) | |
| 65 | − | |
| 66 | −unwcheck: vmlinux | |
| 67 | − -$(Q)READELF=$(READELF) $(PYTHON3) $(srctree)/arch/ia64/scripts/unwcheck.py $< | |
| 68 | − | |
| 69 | −archheaders: | |
| 70 | − $(Q)$(MAKE) $(build)=arch/ia64/kernel/syscalls all | |
| 71 | − | |
| 72 | −CLEAN_FILES += vmlinux.gz | |
| 73 | − | |
| 74 | −install: KBUILD_IMAGE := vmlinux.gz | |
| 75 | −install: | |
| 76 | − $(call cmd,install) | |
| 77 | − | |
| 78 | −define archhelp | |
| 79 | − echo '* compressed - Build compressed kernel image' | |
| 80 | − echo ' install - Install compressed kernel image' | |
| 81 | − echo '* unwcheck - Check vmlinux for invalid unwind info' | |
| 82 | −endef | |
| @@ -1,102 +0,0 @@ | ||
| 1 | −CONFIG_SYSVIPC=y | |
| 2 | −CONFIG_POSIX_MQUEUE=y | |
| 3 | −CONFIG_LOG_BUF_SHIFT=16 | |
| 4 | −CONFIG_PROFILING=y | |
| 5 | −CONFIG_MODULES=y | |
| 6 | −CONFIG_MODULE_UNLOAD=y | |
| 7 | −CONFIG_PARTITION_ADVANCED=y | |
| 8 | −CONFIG_SGI_PARTITION=y | |
| 9 | −CONFIG_SMP=y | |
| 10 | −CONFIG_NR_CPUS=2 | |
| 11 | −CONFIG_PREEMPT=y | |
| 12 | −CONFIG_IA64_PALINFO=y | |
| 13 | −CONFIG_BINFMT_MISC=m | |
| 14 | −CONFIG_ACPI_BUTTON=m | |
| 15 | −CONFIG_ACPI_FAN=m | |
| 16 | −CONFIG_ACPI_PROCESSOR=m | |
| 17 | −CONFIG_NET=y | |
| 18 | −CONFIG_PACKET=y | |
| 19 | −CONFIG_UNIX=y | |
| 20 | −CONFIG_INET=y | |
| 21 | −# CONFIG_IPV6 is not set | |
| 22 | −CONFIG_BLK_DEV_LOOP=m | |
| 23 | −CONFIG_BLK_DEV_NBD=m | |
| 24 | −CONFIG_BLK_DEV_RAM=m | |
| 25 | −CONFIG_ATA=m | |
| 26 | −CONFIG_ATA_GENERIC=m | |
| 27 | −CONFIG_ATA_PIIX=m | |
| 28 | −CONFIG_SCSI=y | |
| 29 | −CONFIG_BLK_DEV_SD=y | |
| 30 | −CONFIG_SCSI_CONSTANTS=y | |
| 31 | −CONFIG_SCSI_LOGGING=y | |
| 32 | −CONFIG_SCSI_SPI_ATTRS=m | |
| 33 | −CONFIG_SCSI_QLOGIC_1280=y | |
| 34 | −CONFIG_MD=y | |
| 35 | −CONFIG_BLK_DEV_MD=m | |
| 36 | −CONFIG_MD_LINEAR=m | |
| 37 | −CONFIG_MD_RAID0=m | |
| 38 | −CONFIG_MD_RAID1=m | |
| 39 | −CONFIG_MD_RAID10=m | |
| 40 | −CONFIG_MD_MULTIPATH=m | |
| 41 | −CONFIG_BLK_DEV_DM=m | |
| 42 | −CONFIG_DM_CRYPT=m | |
| 43 | −CONFIG_DM_SNAPSHOT=m | |
| 44 | −CONFIG_DM_MIRROR=m | |
| 45 | −CONFIG_DM_ZERO=m | |
| 46 | −CONFIG_NETDEVICES=y | |
| 47 | −CONFIG_DUMMY=y | |
| 48 | −CONFIG_INPUT_EVDEV=y | |
| 49 | −CONFIG_SERIAL_8250=y | |
| 50 | −CONFIG_SERIAL_8250_CONSOLE=y | |
| 51 | −CONFIG_SERIAL_8250_EXTENDED=y | |
| 52 | −CONFIG_SERIAL_8250_SHARE_IRQ=y | |
| 53 | −# CONFIG_HW_RANDOM is not set | |
| 54 | −CONFIG_RTC_CLASS=y | |
| 55 | −CONFIG_RTC_DRV_EFI=y | |
| 56 | −CONFIG_I2C=y | |
| 57 | −CONFIG_I2C_CHARDEV=y | |
| 58 | −CONFIG_AGP=m | |
| 59 | −CONFIG_AGP_I460=m | |
| 60 | −CONFIG_DRM=m | |
| 61 | −CONFIG_DRM_R128=m | |
| 62 | −CONFIG_SOUND=m | |
| 63 | −CONFIG_SND=m | |
| 64 | −CONFIG_SND_SEQUENCER=m | |
| 65 | −CONFIG_SND_MIXER_OSS=m | |
| 66 | −CONFIG_SND_PCM_OSS=m | |
| 67 | −CONFIG_SND_CS4281=m | |
| 68 | −CONFIG_USB_HIDDEV=y | |
| 69 | −CONFIG_USB=m | |
| 70 | −CONFIG_USB_MON=m | |
| 71 | −CONFIG_USB_UHCI_HCD=m | |
| 72 | −CONFIG_USB_ACM=m | |
| 73 | −CONFIG_USB_PRINTER=m | |
| 74 | −CONFIG_USB_STORAGE=m | |
| 75 | −CONFIG_EXT2_FS=y | |
| 76 | −CONFIG_EXT3_FS=y | |
| 77 | −CONFIG_XFS_FS=y | |
| 78 | −CONFIG_XFS_QUOTA=y | |
| 79 | −CONFIG_XFS_POSIX_ACL=y | |
| 80 | −CONFIG_AUTOFS_FS=m | |
| 81 | −CONFIG_ISO9660_FS=m | |
| 82 | −CONFIG_JOLIET=y | |
| 83 | −CONFIG_UDF_FS=m | |
| 84 | −CONFIG_VFAT_FS=y | |
| 85 | −CONFIG_PROC_KCORE=y | |
| 86 | −CONFIG_TMPFS=y | |
| 87 | −CONFIG_HUGETLBFS=y | |
| 88 | −CONFIG_NFS_FS=m | |
| 89 | −CONFIG_NFS_V4=m | |
| 90 | −CONFIG_NFSD=m | |
| 91 | −CONFIG_NFSD_V4=y | |
| 92 | −CONFIG_CIFS=m | |
| 93 | −CONFIG_CIFS_XATTR=y | |
| 94 | −CONFIG_CIFS_POSIX=y | |
| 95 | −CONFIG_NLS_CODEPAGE_437=y | |
| 96 | −CONFIG_NLS_ISO8859_1=y | |
| 97 | −CONFIG_NLS_UTF8=m | |
| 98 | −CONFIG_MAGIC_SYSRQ=y | |
| 99 | −CONFIG_DEBUG_KERNEL=y | |
| 100 | −CONFIG_DEBUG_MUTEXES=y | |
| 101 | −CONFIG_CRYPTO_MD5=y | |
| 102 | −CONFIG_CRYPTO_DES=y | |
| @@ -1,206 +0,0 @@ | ||
| 1 | −CONFIG_SYSVIPC=y | |
| 2 | −CONFIG_POSIX_MQUEUE=y | |
| 3 | −CONFIG_IKCONFIG=y | |
| 4 | −CONFIG_IKCONFIG_PROC=y | |
| 5 | −CONFIG_LOG_BUF_SHIFT=20 | |
| 6 | −CONFIG_CGROUPS=y | |
| 7 | −CONFIG_CPUSETS=y | |
| 8 | −CONFIG_BLK_DEV_INITRD=y | |
| 9 | −CONFIG_KALLSYMS_ALL=y | |
| 10 | −CONFIG_MODULES=y | |
| 11 | −CONFIG_MODULE_UNLOAD=y | |
| 12 | −CONFIG_MODVERSIONS=y | |
| 13 | −CONFIG_PARTITION_ADVANCED=y | |
| 14 | −CONFIG_SGI_PARTITION=y | |
| 15 | −CONFIG_MCKINLEY=y | |
| 16 | −CONFIG_IA64_PAGE_SIZE_64KB=y | |
| 17 | −CONFIG_IA64_CYCLONE=y | |
| 18 | −CONFIG_SMP=y | |
| 19 | −CONFIG_HOTPLUG_CPU=y | |
| 20 | −CONFIG_IA64_MCA_RECOVERY=y | |
| 21 | −CONFIG_IA64_PALINFO=y | |
| 22 | −CONFIG_KEXEC=y | |
| 23 | −CONFIG_CRASH_DUMP=y | |
| 24 | −CONFIG_BINFMT_MISC=m | |
| 25 | −CONFIG_ACPI_BUTTON=m | |
| 26 | −CONFIG_ACPI_FAN=m | |
| 27 | −CONFIG_ACPI_DOCK=y | |
| 28 | −CONFIG_ACPI_PROCESSOR=m | |
| 29 | −CONFIG_HOTPLUG_PCI=y | |
| 30 | −CONFIG_HOTPLUG_PCI_ACPI=y | |
| 31 | −CONFIG_NET=y | |
| 32 | −CONFIG_PACKET=y | |
| 33 | −CONFIG_UNIX=y | |
| 34 | −CONFIG_INET=y | |
| 35 | −CONFIG_IP_MULTICAST=y | |
| 36 | −CONFIG_SYN_COOKIES=y | |
| 37 | −# CONFIG_IPV6 is not set | |
| 38 | −CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | |
| 39 | −CONFIG_CONNECTOR=y | |
| 40 | −# CONFIG_PNP_DEBUG_MESSAGES is not set | |
| 41 | −CONFIG_BLK_DEV_LOOP=m | |
| 42 | −CONFIG_BLK_DEV_NBD=m | |
| 43 | −CONFIG_BLK_DEV_RAM=y | |
| 44 | −CONFIG_SGI_XP=m | |
| 45 | −CONFIG_ATA=y | |
| 46 | −CONFIG_ATA_GENERIC=y | |
| 47 | −CONFIG_PATA_CMD64X=y | |
| 48 | −CONFIG_ATA_PIIX=y | |
| 49 | −CONFIG_BLK_DEV_SD=y | |
| 50 | −CONFIG_CHR_DEV_ST=m | |
| 51 | −CONFIG_BLK_DEV_SR=m | |
| 52 | −CONFIG_CHR_DEV_SG=m | |
| 53 | −CONFIG_SCSI_FC_ATTRS=y | |
| 54 | −CONFIG_SCSI_SYM53C8XX_2=y | |
| 55 | −CONFIG_SCSI_QLOGIC_1280=y | |
| 56 | −CONFIG_SATA_VITESSE=y | |
| 57 | −CONFIG_MD=y | |
| 58 | −CONFIG_BLK_DEV_MD=m | |
| 59 | −CONFIG_MD_LINEAR=m | |
| 60 | −CONFIG_MD_RAID0=m | |
| 61 | −CONFIG_MD_RAID1=m | |
| 62 | −CONFIG_MD_MULTIPATH=m | |
| 63 | −CONFIG_BLK_DEV_DM=m | |
| 64 | −CONFIG_DM_CRYPT=m | |
| 65 | −CONFIG_DM_SNAPSHOT=m | |
| 66 | −CONFIG_DM_MIRROR=m | |
| 67 | −CONFIG_DM_ZERO=m | |
| 68 | −CONFIG_DM_MULTIPATH=m | |
| 69 | −CONFIG_FUSION=y | |
| 70 | −CONFIG_FUSION_SPI=y | |
| 71 | −CONFIG_FUSION_FC=m | |
| 72 | −CONFIG_FUSION_SAS=y | |
| 73 | −CONFIG_NETDEVICES=y | |
| 74 | −CONFIG_DUMMY=m | |
| 75 | −CONFIG_NETCONSOLE=y | |
| 76 | −CONFIG_TIGON3=y | |
| 77 | −CONFIG_NET_TULIP=y | |
| 78 | −CONFIG_TULIP=m | |
| 79 | −CONFIG_E100=m | |
| 80 | −CONFIG_E1000=y | |
| 81 | −CONFIG_IGB=y | |
| 82 | −# CONFIG_SERIO_SERPORT is not set | |
| 83 | −CONFIG_GAMEPORT=m | |
| 84 | −CONFIG_SERIAL_NONSTANDARD=y | |
| 85 | −CONFIG_SERIAL_8250=y | |
| 86 | −CONFIG_SERIAL_8250_CONSOLE=y | |
| 87 | −CONFIG_SERIAL_8250_NR_UARTS=6 | |
| 88 | −CONFIG_SERIAL_8250_EXTENDED=y | |
| 89 | −CONFIG_SERIAL_8250_SHARE_IRQ=y | |
| 90 | −# CONFIG_HW_RANDOM is not set | |
| 91 | −CONFIG_RTC_CLASS=y | |
| 92 | −CONFIG_RTC_DRV_EFI=y | |
| 93 | −CONFIG_HPET=y | |
| 94 | −CONFIG_AGP=m | |
| 95 | −CONFIG_AGP_I460=m | |
| 96 | −CONFIG_AGP_HP_ZX1=m | |
| 97 | −CONFIG_DRM=m | |
| 98 | −CONFIG_DRM_TDFX=m | |
| 99 | −CONFIG_DRM_R128=m | |
| 100 | −CONFIG_DRM_RADEON=m | |
| 101 | −CONFIG_DRM_MGA=m | |
| 102 | −CONFIG_DRM_SIS=m | |
| 103 | −CONFIG_SOUND=m | |
| 104 | −CONFIG_SND=m | |
| 105 | −CONFIG_SND_SEQUENCER=m | |
| 106 | −CONFIG_SND_SEQ_DUMMY=m | |
| 107 | −CONFIG_SND_MIXER_OSS=m | |
| 108 | −CONFIG_SND_PCM_OSS=m | |
| 109 | −CONFIG_SND_SEQUENCER_OSS=y | |
| 110 | −CONFIG_SND_VERBOSE_PRINTK=y | |
| 111 | −CONFIG_SND_DUMMY=m | |
| 112 | −CONFIG_SND_VIRMIDI=m | |
| 113 | −CONFIG_SND_MTPAV=m | |
| 114 | −CONFIG_SND_SERIAL_U16550=m | |
| 115 | −CONFIG_SND_MPU401=m | |
| 116 | −CONFIG_SND_CS4281=m | |
| 117 | −CONFIG_SND_CS46XX=m | |
| 118 | −CONFIG_SND_EMU10K1=m | |
| 119 | −CONFIG_SND_FM801=m | |
| 120 | −CONFIG_HID_GYRATION=m | |
| 121 | −CONFIG_HID_PANTHERLORD=m | |
| 122 | −CONFIG_HID_PETALYNX=m | |
| 123 | −CONFIG_HID_SAMSUNG=m | |
| 124 | −CONFIG_HID_SONY=m | |
| 125 | −CONFIG_HID_SUNPLUS=m | |
| 126 | −CONFIG_USB=m | |
| 127 | −CONFIG_USB_MON=m | |
| 128 | −CONFIG_USB_EHCI_HCD=m | |
| 129 | −CONFIG_USB_OHCI_HCD=m | |
| 130 | −CONFIG_USB_UHCI_HCD=m | |
| 131 | −CONFIG_USB_STORAGE=m | |
| 132 | −CONFIG_INFINIBAND=m | |
| 133 | −CONFIG_INFINIBAND_MTHCA=m | |
| 134 | −CONFIG_INFINIBAND_IPOIB=m | |
| 135 | −CONFIG_INTEL_IOMMU=y | |
| 136 | −CONFIG_MSPEC=m | |
| 137 | −CONFIG_EXT2_FS=y | |
| 138 | −CONFIG_EXT2_FS_XATTR=y | |
| 139 | −CONFIG_EXT2_FS_POSIX_ACL=y | |
| 140 | −CONFIG_EXT2_FS_SECURITY=y | |
| 141 | −CONFIG_EXT3_FS=y | |
| 142 | −CONFIG_EXT3_FS_POSIX_ACL=y | |
| 143 | −CONFIG_EXT3_FS_SECURITY=y | |
| 144 | −CONFIG_REISERFS_FS=y | |
| 145 | −CONFIG_REISERFS_FS_XATTR=y | |
| 146 | −CONFIG_REISERFS_FS_POSIX_ACL=y | |
| 147 | −CONFIG_REISERFS_FS_SECURITY=y | |
| 148 | −CONFIG_XFS_FS=y | |
| 149 | −CONFIG_AUTOFS_FS=m | |
| 150 | −CONFIG_ISO9660_FS=m | |
| 151 | −CONFIG_JOLIET=y | |
| 152 | −CONFIG_UDF_FS=m | |
| 153 | −CONFIG_VFAT_FS=y | |
| 154 | −CONFIG_NTFS_FS=m | |
| 155 | −CONFIG_PROC_KCORE=y | |
| 156 | −CONFIG_TMPFS=y | |
| 157 | −CONFIG_HUGETLBFS=y | |
| 158 | −CONFIG_NFS_FS=m | |
| 159 | −CONFIG_NFS_V4=m | |
| 160 | −CONFIG_NFSD=m | |
| 161 | −CONFIG_NFSD_V4=y | |
| 162 | −CONFIG_CIFS=m | |
| 163 | −CONFIG_NLS_CODEPAGE_437=y | |
| 164 | −CONFIG_NLS_CODEPAGE_737=m | |
| 165 | −CONFIG_NLS_CODEPAGE_775=m | |
| 166 | −CONFIG_NLS_CODEPAGE_850=m | |
| 167 | −CONFIG_NLS_CODEPAGE_852=m | |
| 168 | −CONFIG_NLS_CODEPAGE_855=m | |
| 169 | −CONFIG_NLS_CODEPAGE_857=m | |
| 170 | −CONFIG_NLS_CODEPAGE_860=m | |
| 171 | −CONFIG_NLS_CODEPAGE_861=m | |
| 172 | −CONFIG_NLS_CODEPAGE_862=m | |
| 173 | −CONFIG_NLS_CODEPAGE_863=m | |
| 174 | −CONFIG_NLS_CODEPAGE_864=m | |
| 175 | −CONFIG_NLS_CODEPAGE_865=m | |
| 176 | −CONFIG_NLS_CODEPAGE_866=m | |
| 177 | −CONFIG_NLS_CODEPAGE_869=m | |
| 178 | −CONFIG_NLS_CODEPAGE_936=m | |
| 179 | −CONFIG_NLS_CODEPAGE_950=m | |
| 180 | −CONFIG_NLS_CODEPAGE_932=m | |
| 181 | −CONFIG_NLS_CODEPAGE_949=m | |
| 182 | −CONFIG_NLS_CODEPAGE_874=m | |
| 183 | −CONFIG_NLS_ISO8859_8=m | |
| 184 | −CONFIG_NLS_CODEPAGE_1250=m | |
| 185 | −CONFIG_NLS_CODEPAGE_1251=m | |
| 186 | −CONFIG_NLS_ISO8859_1=y | |
| 187 | −CONFIG_NLS_ISO8859_2=m | |
| 188 | −CONFIG_NLS_ISO8859_3=m | |
| 189 | −CONFIG_NLS_ISO8859_4=m | |
| 190 | −CONFIG_NLS_ISO8859_5=m | |
| 191 | −CONFIG_NLS_ISO8859_6=m | |
| 192 | −CONFIG_NLS_ISO8859_7=m | |
| 193 | −CONFIG_NLS_ISO8859_9=m | |
| 194 | −CONFIG_NLS_ISO8859_13=m | |
| 195 | −CONFIG_NLS_ISO8859_14=m | |
| 196 | −CONFIG_NLS_ISO8859_15=m | |
| 197 | −CONFIG_NLS_KOI8_R=m | |
| 198 | −CONFIG_NLS_KOI8_U=m | |
| 199 | −CONFIG_NLS_UTF8=m | |
| 200 | −CONFIG_MAGIC_SYSRQ=y | |
| 201 | −CONFIG_DEBUG_KERNEL=y | |
| 202 | −CONFIG_DEBUG_MUTEXES=y | |
| 203 | −CONFIG_CRYPTO_PCBC=m | |
| 204 | −CONFIG_CRYPTO_MD5=y | |
| 205 | −# CONFIG_CRYPTO_ANSI_CPRNG is not set | |
| 206 | −CONFIG_CRC_T10DIF=y | |
| @@ -1,184 +0,0 @@ | ||
| 1 | −CONFIG_SYSVIPC=y | |
| 2 | −CONFIG_POSIX_MQUEUE=y | |
| 3 | −CONFIG_IKCONFIG=y | |
| 4 | −CONFIG_IKCONFIG_PROC=y | |
| 5 | −CONFIG_LOG_BUF_SHIFT=20 | |
| 6 | −CONFIG_BLK_DEV_INITRD=y | |
| 7 | −CONFIG_KALLSYMS_ALL=y | |
| 8 | −CONFIG_MODULES=y | |
| 9 | −CONFIG_MODULE_UNLOAD=y | |
| 10 | −CONFIG_MODVERSIONS=y | |
| 11 | −CONFIG_PARTITION_ADVANCED=y | |
| 12 | −CONFIG_SGI_PARTITION=y | |
| 13 | −CONFIG_MCKINLEY=y | |
| 14 | −CONFIG_IA64_CYCLONE=y | |
| 15 | −CONFIG_SMP=y | |
| 16 | −CONFIG_NR_CPUS=512 | |
| 17 | −CONFIG_HOTPLUG_CPU=y | |
| 18 | −CONFIG_SPARSEMEM_MANUAL=y | |
| 19 | −CONFIG_IA64_MCA_RECOVERY=y | |
| 20 | −CONFIG_IA64_PALINFO=y | |
| 21 | −CONFIG_BINFMT_MISC=m | |
| 22 | −CONFIG_ACPI_BUTTON=m | |
| 23 | −CONFIG_ACPI_FAN=m | |
| 24 | −CONFIG_ACPI_PROCESSOR=m | |
| 25 | −CONFIG_HOTPLUG_PCI=y | |
| 26 | −CONFIG_NET=y | |
| 27 | −CONFIG_PACKET=y | |
| 28 | −CONFIG_UNIX=y | |
| 29 | −CONFIG_INET=y | |
| 30 | −CONFIG_IP_MULTICAST=y | |
| 31 | −CONFIG_SYN_COOKIES=y | |
| 32 | −# CONFIG_IPV6 is not set | |
| 33 | −CONFIG_BLK_DEV_LOOP=m | |
| 34 | −CONFIG_BLK_DEV_NBD=m | |
| 35 | −CONFIG_BLK_DEV_RAM=y | |
| 36 | −CONFIG_ATA=y | |
| 37 | −CONFIG_ATA_GENERIC=y | |
| 38 | −CONFIG_PATA_CMD64X=y | |
| 39 | −CONFIG_ATA_PIIX=y | |
| 40 | −CONFIG_SCSI=y | |
| 41 | −CONFIG_BLK_DEV_SD=y | |
| 42 | −CONFIG_CHR_DEV_ST=m | |
| 43 | −CONFIG_BLK_DEV_SR=m | |
| 44 | −CONFIG_CHR_DEV_SG=m | |
| 45 | −CONFIG_SCSI_FC_ATTRS=y | |
| 46 | −CONFIG_SCSI_SYM53C8XX_2=y | |
| 47 | −CONFIG_SCSI_QLOGIC_1280=y | |
| 48 | −CONFIG_MD=y | |
| 49 | −CONFIG_BLK_DEV_MD=m | |
| 50 | −CONFIG_MD_LINEAR=m | |
| 51 | −CONFIG_MD_RAID0=m | |
| 52 | −CONFIG_MD_RAID1=m | |
| 53 | −CONFIG_MD_MULTIPATH=m | |
| 54 | −CONFIG_BLK_DEV_DM=m | |
| 55 | −CONFIG_DM_CRYPT=m | |
| 56 | −CONFIG_DM_SNAPSHOT=m | |
| 57 | −CONFIG_DM_MIRROR=m | |
| 58 | −CONFIG_DM_ZERO=m | |
| 59 | −CONFIG_DM_MULTIPATH=m | |
| 60 | −CONFIG_FUSION=y | |
| 61 | −CONFIG_FUSION_SPI=y | |
| 62 | −CONFIG_FUSION_FC=m | |
| 63 | −CONFIG_NETDEVICES=y | |
| 64 | −CONFIG_DUMMY=m | |
| 65 | −CONFIG_NETCONSOLE=y | |
| 66 | −CONFIG_TIGON3=y | |
| 67 | −CONFIG_NET_TULIP=y | |
| 68 | −CONFIG_TULIP=m | |
| 69 | −CONFIG_E100=m | |
| 70 | −CONFIG_E1000=y | |
| 71 | −# CONFIG_SERIO_SERPORT is not set | |
| 72 | −CONFIG_GAMEPORT=m | |
| 73 | −CONFIG_SERIAL_NONSTANDARD=y | |
| 74 | −CONFIG_SERIAL_8250=y | |
| 75 | −CONFIG_SERIAL_8250_CONSOLE=y | |
| 76 | −CONFIG_SERIAL_8250_NR_UARTS=6 | |
| 77 | −CONFIG_SERIAL_8250_EXTENDED=y | |
| 78 | −CONFIG_SERIAL_8250_SHARE_IRQ=y | |
| 79 | −# CONFIG_HW_RANDOM is not set | |
| 80 | −CONFIG_RTC_CLASS=y | |
| 81 | −CONFIG_RTC_DRV_EFI=y | |
| 82 | −CONFIG_HPET=y | |
| 83 | −CONFIG_AGP=m | |
| 84 | −CONFIG_AGP_I460=m | |
| 85 | −CONFIG_AGP_HP_ZX1=m | |
| 86 | −CONFIG_DRM=m | |
| 87 | −CONFIG_DRM_TDFX=m | |
| 88 | −CONFIG_DRM_R128=m | |
| 89 | −CONFIG_DRM_RADEON=m | |
| 90 | −CONFIG_DRM_MGA=m | |
| 91 | −CONFIG_DRM_SIS=m | |
| 92 | −CONFIG_SOUND=m | |
| 93 | −CONFIG_SND=m | |
| 94 | −CONFIG_SND_SEQUENCER=m | |
| 95 | −CONFIG_SND_SEQ_DUMMY=m | |
| 96 | −CONFIG_SND_MIXER_OSS=m | |
| 97 | −CONFIG_SND_PCM_OSS=m | |
| 98 | −CONFIG_SND_SEQUENCER_OSS=y | |
| 99 | −CONFIG_SND_VERBOSE_PRINTK=y | |
| 100 | −CONFIG_SND_DUMMY=m | |
| 101 | −CONFIG_SND_VIRMIDI=m | |
| 102 | −CONFIG_SND_MTPAV=m | |
| 103 | −CONFIG_SND_SERIAL_U16550=m | |
| 104 | −CONFIG_SND_MPU401=m | |
| 105 | −CONFIG_SND_CS4281=m | |
| 106 | −CONFIG_SND_CS46XX=m | |
| 107 | −CONFIG_SND_EMU10K1=m | |
| 108 | −CONFIG_SND_FM801=m | |
| 109 | −CONFIG_USB=m | |
| 110 | −CONFIG_USB_MON=m | |
| 111 | −CONFIG_USB_EHCI_HCD=m | |
| 112 | −CONFIG_USB_OHCI_HCD=m | |
| 113 | −CONFIG_USB_UHCI_HCD=m | |
| 114 | −CONFIG_USB_STORAGE=m | |
| 115 | −CONFIG_INFINIBAND=m | |
| 116 | −CONFIG_INFINIBAND_MTHCA=m | |
| 117 | −CONFIG_INFINIBAND_IPOIB=m | |
| 118 | −CONFIG_EXT2_FS=y | |
| 119 | −CONFIG_EXT2_FS_XATTR=y | |
| 120 | −CONFIG_EXT2_FS_POSIX_ACL=y | |
| 121 | −CONFIG_EXT2_FS_SECURITY=y | |
| 122 | −CONFIG_EXT3_FS=y | |
| 123 | −CONFIG_EXT3_FS_POSIX_ACL=y | |
| 124 | −CONFIG_EXT3_FS_SECURITY=y | |
| 125 | −CONFIG_REISERFS_FS=y | |
| 126 | −CONFIG_REISERFS_FS_XATTR=y | |
| 127 | −CONFIG_REISERFS_FS_POSIX_ACL=y | |
| 128 | −CONFIG_REISERFS_FS_SECURITY=y | |
| 129 | −CONFIG_XFS_FS=y | |
| 130 | −CONFIG_AUTOFS_FS=y | |
| 131 | −CONFIG_ISO9660_FS=m | |
| 132 | −CONFIG_JOLIET=y | |
| 133 | −CONFIG_UDF_FS=m | |
| 134 | −CONFIG_VFAT_FS=y | |
| 135 | −CONFIG_NTFS_FS=m | |
| 136 | −CONFIG_PROC_KCORE=y | |
| 137 | −CONFIG_TMPFS=y | |
| 138 | −CONFIG_HUGETLBFS=y | |
| 139 | −CONFIG_NFS_FS=m | |
| 140 | −CONFIG_NFS_V4=m | |
| 141 | −CONFIG_NFSD=m | |
| 142 | −CONFIG_NFSD_V4=y | |
| 143 | −CONFIG_CIFS=m | |
| 144 | −CONFIG_NLS_CODEPAGE_437=y | |
| 145 | −CONFIG_NLS_CODEPAGE_737=m | |
| 146 | −CONFIG_NLS_CODEPAGE_775=m | |
| 147 | −CONFIG_NLS_CODEPAGE_850=m | |
| 148 | −CONFIG_NLS_CODEPAGE_852=m | |
| 149 | −CONFIG_NLS_CODEPAGE_855=m | |
| 150 | −CONFIG_NLS_CODEPAGE_857=m | |
| 151 | −CONFIG_NLS_CODEPAGE_860=m | |
| 152 | −CONFIG_NLS_CODEPAGE_861=m | |
| 153 | −CONFIG_NLS_CODEPAGE_862=m | |
| 154 | −CONFIG_NLS_CODEPAGE_863=m | |
| 155 | −CONFIG_NLS_CODEPAGE_864=m | |
| 156 | −CONFIG_NLS_CODEPAGE_865=m | |
| 157 | −CONFIG_NLS_CODEPAGE_866=m | |
| 158 | −CONFIG_NLS_CODEPAGE_869=m | |
| 159 | −CONFIG_NLS_CODEPAGE_936=m | |
| 160 | −CONFIG_NLS_CODEPAGE_950=m | |
| 161 | −CONFIG_NLS_CODEPAGE_932=m | |
| 162 | −CONFIG_NLS_CODEPAGE_949=m | |
| 163 | −CONFIG_NLS_CODEPAGE_874=m | |
| 164 | −CONFIG_NLS_ISO8859_8=m | |
| 165 | −CONFIG_NLS_CODEPAGE_1250=m | |
| 166 | −CONFIG_NLS_CODEPAGE_1251=m | |
| 167 | −CONFIG_NLS_ISO8859_1=y | |
| 168 | −CONFIG_NLS_ISO8859_2=m | |
| 169 | −CONFIG_NLS_ISO8859_3=m | |
| 170 | −CONFIG_NLS_ISO8859_4=m | |
| 171 | −CONFIG_NLS_ISO8859_5=m | |
| 172 | −CONFIG_NLS_ISO8859_6=m | |
| 173 | −CONFIG_NLS_ISO8859_7=m | |
| 174 | −CONFIG_NLS_ISO8859_9=m | |
| 175 | −CONFIG_NLS_ISO8859_13=m | |
| 176 | −CONFIG_NLS_ISO8859_14=m | |
| 177 | −CONFIG_NLS_ISO8859_15=m | |
| 178 | −CONFIG_NLS_KOI8_R=m | |
| 179 | −CONFIG_NLS_KOI8_U=m | |
| 180 | −CONFIG_NLS_UTF8=m | |
| 181 | −CONFIG_MAGIC_SYSRQ=y | |
| 182 | −CONFIG_DEBUG_KERNEL=y | |
| 183 | −CONFIG_DEBUG_MUTEXES=y | |
| 184 | −CONFIG_CRYPTO_MD5=y | |
| @@ -1,169 +0,0 @@ | ||
| 1 | −CONFIG_SYSVIPC=y | |
| 2 | −CONFIG_POSIX_MQUEUE=y | |
| 3 | −CONFIG_IKCONFIG=y | |
| 4 | −CONFIG_IKCONFIG_PROC=y | |
| 5 | −CONFIG_LOG_BUF_SHIFT=20 | |
| 6 | −CONFIG_BLK_DEV_INITRD=y | |
| 7 | −CONFIG_KALLSYMS_ALL=y | |
| 8 | −CONFIG_MODULES=y | |
| 9 | −CONFIG_MODULE_UNLOAD=y | |
| 10 | −CONFIG_MODVERSIONS=y | |
| 11 | −CONFIG_MODULE_SRCVERSION_ALL=y | |
| 12 | −# CONFIG_BLK_DEV_BSG is not set | |
| 13 | −CONFIG_PARTITION_ADVANCED=y | |
| 14 | −CONFIG_SGI_PARTITION=y | |
| 15 | −CONFIG_MCKINLEY=y | |
| 16 | −CONFIG_IA64_PAGE_SIZE_64KB=y | |
| 17 | −CONFIG_IA64_CYCLONE=y | |
| 18 | −CONFIG_SMP=y | |
| 19 | −CONFIG_NR_CPUS=16 | |
| 20 | −CONFIG_HOTPLUG_CPU=y | |
| 21 | −CONFIG_PERMIT_BSP_REMOVE=y | |
| 22 | −CONFIG_FORCE_CPEI_RETARGET=y | |
| 23 | −CONFIG_IA64_MCA_RECOVERY=y | |
| 24 | −CONFIG_IA64_PALINFO=y | |
| 25 | −CONFIG_KEXEC=y | |
| 26 | −CONFIG_BINFMT_MISC=m | |
| 27 | −CONFIG_ACPI_BUTTON=m | |
| 28 | −CONFIG_ACPI_FAN=m | |
| 29 | −CONFIG_ACPI_PROCESSOR=m | |
| 30 | −CONFIG_HOTPLUG_PCI=y | |
| 31 | −CONFIG_NET=y | |
| 32 | −CONFIG_PACKET=y | |
| 33 | −CONFIG_UNIX=y | |
| 34 | −CONFIG_INET=y | |
| 35 | −CONFIG_IP_MULTICAST=y | |
| 36 | −CONFIG_SYN_COOKIES=y | |
| 37 | −# CONFIG_IPV6 is not set | |
| 38 | −CONFIG_BLK_DEV_LOOP=m | |
| 39 | −CONFIG_BLK_DEV_NBD=m | |
| 40 | −CONFIG_BLK_DEV_RAM=y | |
| 41 | −CONFIG_ATA=y | |
| 42 | −CONFIG_ATA_GENERIC=y | |
| 43 | −CONFIG_PATA_CMD64X=y | |
| 44 | −CONFIG_ATA_PIIX=y | |
| 45 | −CONFIG_SCSI=y | |
| 46 | −CONFIG_BLK_DEV_SD=y | |
| 47 | −CONFIG_CHR_DEV_ST=m | |
| 48 | −CONFIG_BLK_DEV_SR=m | |
| 49 | −CONFIG_CHR_DEV_SG=m | |
| 50 | −CONFIG_SCSI_FC_ATTRS=y | |
| 51 | −CONFIG_SCSI_SYM53C8XX_2=y | |
| 52 | −CONFIG_SCSI_QLOGIC_1280=y | |
| 53 | −CONFIG_MD=y | |
| 54 | −CONFIG_BLK_DEV_MD=m | |
| 55 | −CONFIG_MD_LINEAR=m | |
| 56 | −CONFIG_MD_RAID0=m | |
| 57 | −CONFIG_MD_RAID1=m | |
| 58 | −CONFIG_MD_MULTIPATH=m | |
| 59 | −CONFIG_BLK_DEV_DM=m | |
| 60 | −CONFIG_DM_CRYPT=m | |
| 61 | −CONFIG_DM_SNAPSHOT=m | |
| 62 | −CONFIG_DM_MIRROR=m | |
| 63 | −CONFIG_DM_ZERO=m | |
| 64 | −CONFIG_FUSION=y | |
| 65 | −CONFIG_FUSION_SPI=y | |
| 66 | −CONFIG_FUSION_FC=y | |
| 67 | −CONFIG_FUSION_CTL=y | |
| 68 | −CONFIG_NETDEVICES=y | |
| 69 | −CONFIG_DUMMY=m | |
| 70 | −CONFIG_NETCONSOLE=y | |
| 71 | −CONFIG_TIGON3=y | |
| 72 | −CONFIG_NET_TULIP=y | |
| 73 | −CONFIG_TULIP=m | |
| 74 | −CONFIG_E100=m | |
| 75 | −CONFIG_E1000=y | |
| 76 | −# CONFIG_SERIO_SERPORT is not set | |
| 77 | −CONFIG_GAMEPORT=m | |
| 78 | −CONFIG_SERIAL_NONSTANDARD=y | |
| 79 | −CONFIG_SERIAL_8250=y | |
| 80 | −CONFIG_SERIAL_8250_CONSOLE=y | |
| 81 | −CONFIG_SERIAL_8250_NR_UARTS=6 | |
| 82 | −CONFIG_SERIAL_8250_EXTENDED=y | |
| 83 | −CONFIG_SERIAL_8250_SHARE_IRQ=y | |
| 84 | −# CONFIG_HW_RANDOM is not set | |
| 85 | −CONFIG_RTC_CLASS=y | |
| 86 | −CONFIG_RTC_DRV_EFI=y | |
| 87 | −CONFIG_HPET=y | |
| 88 | −CONFIG_AGP=m | |
| 89 | −CONFIG_AGP_I460=m | |
| 90 | −CONFIG_DRM=m | |
| 91 | −CONFIG_DRM_TDFX=m | |
| 92 | −CONFIG_DRM_R128=m | |
| 93 | −CONFIG_DRM_RADEON=m | |
| 94 | −CONFIG_DRM_MGA=m | |
| 95 | −CONFIG_DRM_SIS=m | |
| 96 | −CONFIG_USB=y | |
| 97 | −CONFIG_USB_EHCI_HCD=m | |
| 98 | −CONFIG_USB_OHCI_HCD=m | |
| 99 | −CONFIG_USB_UHCI_HCD=y | |
| 100 | −CONFIG_USB_STORAGE=m | |
| 101 | −CONFIG_EXT2_FS=y | |
| 102 | −CONFIG_EXT2_FS_XATTR=y | |
| 103 | −CONFIG_EXT2_FS_POSIX_ACL=y | |
| 104 | −CONFIG_EXT2_FS_SECURITY=y | |
| 105 | −CONFIG_EXT3_FS=y | |
| 106 | −CONFIG_EXT3_FS_POSIX_ACL=y | |
| 107 | −CONFIG_EXT3_FS_SECURITY=y | |
| 108 | −CONFIG_REISERFS_FS=y | |
| 109 | −CONFIG_REISERFS_FS_XATTR=y | |
| 110 | −CONFIG_REISERFS_FS_POSIX_ACL=y | |
| 111 | −CONFIG_REISERFS_FS_SECURITY=y | |
| 112 | −CONFIG_XFS_FS=y | |
| 113 | −CONFIG_AUTOFS_FS=y | |
| 114 | −CONFIG_ISO9660_FS=m | |
| 115 | −CONFIG_JOLIET=y | |
| 116 | −CONFIG_UDF_FS=m | |
| 117 | −CONFIG_VFAT_FS=y | |
| 118 | −CONFIG_NTFS_FS=m | |
| 119 | −CONFIG_PROC_KCORE=y | |
| 120 | −CONFIG_TMPFS=y | |
| 121 | −CONFIG_HUGETLBFS=y | |
| 122 | −CONFIG_NFS_FS=m | |
| 123 | −CONFIG_NFS_V4=m | |
| 124 | −CONFIG_NFSD=m | |
| 125 | −CONFIG_NFSD_V4=y | |
| 126 | −CONFIG_CIFS=m | |
| 127 | −CONFIG_NLS_CODEPAGE_437=y | |
| 128 | −CONFIG_NLS_CODEPAGE_737=m | |
| 129 | −CONFIG_NLS_CODEPAGE_775=m | |
| 130 | −CONFIG_NLS_CODEPAGE_850=m | |
| 131 | −CONFIG_NLS_CODEPAGE_852=m | |
| 132 | −CONFIG_NLS_CODEPAGE_855=m | |
| 133 | −CONFIG_NLS_CODEPAGE_857=m | |
| 134 | −CONFIG_NLS_CODEPAGE_860=m | |
| 135 | −CONFIG_NLS_CODEPAGE_861=m | |
| 136 | −CONFIG_NLS_CODEPAGE_862=m | |
| 137 | −CONFIG_NLS_CODEPAGE_863=m | |
| 138 | −CONFIG_NLS_CODEPAGE_864=m | |
| 139 | −CONFIG_NLS_CODEPAGE_865=m | |
| 140 | −CONFIG_NLS_CODEPAGE_866=m | |
| 141 | −CONFIG_NLS_CODEPAGE_869=m | |
| 142 | −CONFIG_NLS_CODEPAGE_936=m | |
| 143 | −CONFIG_NLS_CODEPAGE_950=m | |
| 144 | −CONFIG_NLS_CODEPAGE_932=m | |
| 145 | −CONFIG_NLS_CODEPAGE_949=m | |
| 146 | −CONFIG_NLS_CODEPAGE_874=m | |
| 147 | −CONFIG_NLS_ISO8859_8=m | |
| 148 | −CONFIG_NLS_CODEPAGE_1250=m | |
| 149 | −CONFIG_NLS_CODEPAGE_1251=m | |
| 150 | −CONFIG_NLS_ISO8859_1=y | |
| 151 | −CONFIG_NLS_ISO8859_2=m | |
| 152 | −CONFIG_NLS_ISO8859_3=m | |
| 153 | −CONFIG_NLS_ISO8859_4=m | |
| 154 | −CONFIG_NLS_ISO8859_5=m | |
| 155 | −CONFIG_NLS_ISO8859_6=m | |
| 156 | −CONFIG_NLS_ISO8859_7=m | |
| 157 | −CONFIG_NLS_ISO8859_9=m | |
| 158 | −CONFIG_NLS_ISO8859_13=m | |
| 159 | −CONFIG_NLS_ISO8859_14=m | |
| 160 | −CONFIG_NLS_ISO8859_15=m | |
| 161 | −CONFIG_NLS_KOI8_R=m | |
| 162 | −CONFIG_NLS_KOI8_U=m | |
| 163 | −CONFIG_NLS_UTF8=m | |
| 164 | −CONFIG_MAGIC_SYSRQ=y | |
| 165 | −CONFIG_DEBUG_KERNEL=y | |
| 166 | −CONFIG_DEBUG_MUTEXES=y | |
| 167 | −CONFIG_IA64_GRANULE_16MB=y | |
| 168 | −CONFIG_CRYPTO_PCBC=m | |
| 169 | −CONFIG_CRYPTO_MD5=y | |
| @@ -1,148 +0,0 @@ | ||
| 1 | −CONFIG_SYSVIPC=y | |
| 2 | −CONFIG_BSD_PROCESS_ACCT=y | |
| 3 | −CONFIG_BLK_DEV_INITRD=y | |
| 4 | −CONFIG_KPROBES=y | |
| 5 | −CONFIG_MODULES=y | |
| 6 | −CONFIG_PARTITION_ADVANCED=y | |
| 7 | −CONFIG_MCKINLEY=y | |
| 8 | −CONFIG_SMP=y | |
| 9 | −CONFIG_NR_CPUS=16 | |
| 10 | −CONFIG_HOTPLUG_CPU=y | |
| 11 | −CONFIG_FLATMEM_MANUAL=y | |
| 12 | −CONFIG_IA64_MCA_RECOVERY=y | |
| 13 | −CONFIG_IA64_PALINFO=y | |
| 14 | −CONFIG_CRASH_DUMP=y | |
| 15 | −CONFIG_BINFMT_MISC=y | |
| 16 | −CONFIG_HOTPLUG_PCI=y | |
| 17 | −CONFIG_HOTPLUG_PCI_ACPI=y | |
| 18 | −CONFIG_NET=y | |
| 19 | −CONFIG_PACKET=y | |
| 20 | −CONFIG_UNIX=y | |
| 21 | −CONFIG_INET=y | |
| 22 | −CONFIG_IP_MULTICAST=y | |
| 23 | −# CONFIG_IPV6 is not set | |
| 24 | −CONFIG_NETFILTER=y | |
| 25 | −CONFIG_BLK_DEV_LOOP=y | |
| 26 | −CONFIG_BLK_DEV_RAM=y | |
| 27 | −CONFIG_ATA=y | |
| 28 | −CONFIG_ATA_GENERIC=y | |
| 29 | −CONFIG_PATA_CMD64X=y | |
| 30 | −CONFIG_SCSI=y | |
| 31 | −CONFIG_BLK_DEV_SD=y | |
| 32 | −CONFIG_CHR_DEV_ST=y | |
| 33 | −CONFIG_BLK_DEV_SR=y | |
| 34 | −CONFIG_CHR_DEV_SG=y | |
| 35 | −CONFIG_SCSI_CONSTANTS=y | |
| 36 | −CONFIG_SCSI_LOGGING=y | |
| 37 | −CONFIG_SCSI_FC_ATTRS=y | |
| 38 | −CONFIG_SCSI_SYM53C8XX_2=y | |
| 39 | −CONFIG_SCSI_QLOGIC_1280=y | |
| 40 | −CONFIG_FUSION=y | |
| 41 | −CONFIG_FUSION_SPI=y | |
| 42 | −CONFIG_FUSION_FC=y | |
| 43 | −CONFIG_FUSION_CTL=m | |
| 44 | −CONFIG_NETDEVICES=y | |
| 45 | −CONFIG_DUMMY=y | |
| 46 | −CONFIG_TIGON3=y | |
| 47 | −CONFIG_NET_TULIP=y | |
| 48 | −CONFIG_TULIP=y | |
| 49 | −CONFIG_TULIP_MWI=y | |
| 50 | −CONFIG_TULIP_MMIO=y | |
| 51 | −CONFIG_TULIP_NAPI=y | |
| 52 | −CONFIG_TULIP_NAPI_HW_MITIGATION=y | |
| 53 | −CONFIG_E100=y | |
| 54 | −CONFIG_E1000=y | |
| 55 | −CONFIG_INPUT_JOYDEV=y | |
| 56 | −CONFIG_INPUT_EVDEV=y | |
| 57 | −# CONFIG_INPUT_KEYBOARD is not set | |
| 58 | −# CONFIG_INPUT_MOUSE is not set | |
| 59 | −# CONFIG_SERIO_I8042 is not set | |
| 60 | −# CONFIG_SERIO_SERPORT is not set | |
| 61 | −CONFIG_SERIAL_8250=y | |
| 62 | −CONFIG_SERIAL_8250_CONSOLE=y | |
| 63 | −CONFIG_SERIAL_8250_NR_UARTS=8 | |
| 64 | −CONFIG_SERIAL_8250_EXTENDED=y | |
| 65 | −CONFIG_SERIAL_8250_SHARE_IRQ=y | |
| 66 | −# CONFIG_HW_RANDOM is not set | |
| 67 | −CONFIG_RTC_CLASS=y | |
| 68 | −CONFIG_RTC_DRV_EFI=y | |
| 69 | −CONFIG_I2C_CHARDEV=y | |
| 70 | −CONFIG_AGP=y | |
| 71 | −CONFIG_AGP_HP_ZX1=y | |
| 72 | −CONFIG_DRM=y | |
| 73 | −CONFIG_DRM_RADEON=y | |
| 74 | −CONFIG_FB_RADEON=y | |
| 75 | −CONFIG_FB_RADEON_DEBUG=y | |
| 76 | −CONFIG_LOGO=y | |
| 77 | −# CONFIG_LOGO_LINUX_MONO is not set | |
| 78 | −# CONFIG_LOGO_LINUX_VGA16 is not set | |
| 79 | −CONFIG_SOUND=y | |
| 80 | −CONFIG_SND=y | |
| 81 | −CONFIG_SND_SEQUENCER=y | |
| 82 | −CONFIG_SND_MIXER_OSS=y | |
| 83 | −CONFIG_SND_PCM_OSS=y | |
| 84 | −CONFIG_SND_SEQUENCER_OSS=y | |
| 85 | −CONFIG_SND_FM801=y | |
| 86 | −CONFIG_USB_HIDDEV=y | |
| 87 | −CONFIG_USB=y | |
| 88 | −CONFIG_USB_MON=y | |
| 89 | −CONFIG_USB_EHCI_HCD=y | |
| 90 | −CONFIG_USB_OHCI_HCD=y | |
| 91 | −CONFIG_USB_UHCI_HCD=y | |
| 92 | −CONFIG_USB_STORAGE=y | |
| 93 | −CONFIG_EXT2_FS=y | |
| 94 | −CONFIG_EXT2_FS_XATTR=y | |
| 95 | −CONFIG_EXT3_FS=y | |
| 96 | −CONFIG_ISO9660_FS=y | |
| 97 | −CONFIG_JOLIET=y | |
| 98 | −CONFIG_UDF_FS=y | |
| 99 | −CONFIG_MSDOS_FS=y | |
| 100 | −CONFIG_VFAT_FS=y | |
| 101 | −CONFIG_PROC_KCORE=y | |
| 102 | −CONFIG_TMPFS=y | |
| 103 | −CONFIG_HUGETLBFS=y | |
| 104 | −CONFIG_NFS_FS=y | |
| 105 | −CONFIG_NFS_V4=y | |
| 106 | −CONFIG_NFSD=y | |
| 107 | −CONFIG_NLS_CODEPAGE_437=y | |
| 108 | −CONFIG_NLS_CODEPAGE_737=y | |
| 109 | −CONFIG_NLS_CODEPAGE_775=y | |
| 110 | −CONFIG_NLS_CODEPAGE_850=y | |
| 111 | −CONFIG_NLS_CODEPAGE_852=y | |
| 112 | −CONFIG_NLS_CODEPAGE_855=y | |
| 113 | −CONFIG_NLS_CODEPAGE_857=y | |
| 114 | −CONFIG_NLS_CODEPAGE_860=y | |
| 115 | −CONFIG_NLS_CODEPAGE_861=y | |
| 116 | −CONFIG_NLS_CODEPAGE_862=y | |
| 117 | −CONFIG_NLS_CODEPAGE_863=y | |
| 118 | −CONFIG_NLS_CODEPAGE_864=y | |
| 119 | −CONFIG_NLS_CODEPAGE_865=y | |
| 120 | −CONFIG_NLS_CODEPAGE_866=y | |
| 121 | −CONFIG_NLS_CODEPAGE_869=y | |
| 122 | −CONFIG_NLS_CODEPAGE_936=y | |
| 123 | −CONFIG_NLS_CODEPAGE_950=y | |
| 124 | −CONFIG_NLS_CODEPAGE_932=y | |
| 125 | −CONFIG_NLS_CODEPAGE_949=y | |
| 126 | −CONFIG_NLS_CODEPAGE_874=y | |
| 127 | −CONFIG_NLS_ISO8859_8=y | |
| 128 | −CONFIG_NLS_CODEPAGE_1251=y | |
| 129 | −CONFIG_NLS_ISO8859_1=y | |
| 130 | −CONFIG_NLS_ISO8859_2=y | |
| 131 | −CONFIG_NLS_ISO8859_3=y | |
| 132 | −CONFIG_NLS_ISO8859_4=y | |
| 133 | −CONFIG_NLS_ISO8859_5=y | |
| 134 | −CONFIG_NLS_ISO8859_6=y | |
| 135 | −CONFIG_NLS_ISO8859_7=y | |
| 136 | −CONFIG_NLS_ISO8859_9=y | |
| 137 | −CONFIG_NLS_ISO8859_13=y | |
| 138 | −CONFIG_NLS_ISO8859_14=y | |
| 139 | −CONFIG_NLS_ISO8859_15=y | |
| 140 | −CONFIG_NLS_KOI8_R=y | |
| 141 | −CONFIG_NLS_KOI8_U=y | |
| 142 | −CONFIG_NLS_UTF8=y | |
| 143 | −CONFIG_MAGIC_SYSRQ=y | |
| 144 | −CONFIG_DEBUG_KERNEL=y | |
| 145 | −CONFIG_DEBUG_MUTEXES=y | |
| 146 | −CONFIG_IA64_PRINT_HAZARDS=y | |
| 147 | −CONFIG_CRYPTO_ECB=m | |
| 148 | −CONFIG_CRYPTO_PCBC=m | |
| @@ -1,10 +0,0 @@ | ||
| 1 | −# SPDX-License-Identifier: GPL-2.0-only | |
| 2 | −# | |
| 3 | −# ia64/platform/hp/common/Makefile | |
| 4 | −# | |
| 5 | −# Copyright (C) 2002 Hewlett Packard | |
| 6 | −# Copyright (C) Alex Williamson (alex_williamson@hp.com) | |
| 7 | −# | |
| 8 | − | |
| 9 | −obj-$(CONFIG_IA64_HP_SBA_IOMMU) += sba_iommu.o | |
| 10 | −obj-$(CONFIG_IA64_HP_AML_NFW) += aml_nfw.o | |
| @@ -1,232 +0,0 @@ | ||
| 1 | −// SPDX-License-Identifier: GPL-2.0-only | |
| 2 | −/* | |
| 3 | − * OpRegion handler to allow AML to call native firmware | |
| 4 | − * | |
| 5 | − * (c) Copyright 2007 Hewlett-Packard Development Company, L.P. | |
| 6 | − * Bjorn Helgaas <bjorn.helgaas@hp.com> | |
| 7 | − * | |
| 8 | − * This driver implements HP Open Source Review Board proposal 1842, | |
| 9 | − * which was approved on 9/20/2006. | |
| 10 | − * | |
| 11 | − * For technical documentation, see the HP SPPA Firmware EAS, Appendix F. | |
| 12 | − * | |
| 13 | − * ACPI does not define a mechanism for AML methods to call native firmware | |
| 14 | − * interfaces such as PAL or SAL. This OpRegion handler adds such a mechanism. | |
| 15 | − * After the handler is installed, an AML method can call native firmware by | |
| 16 | − * storing the arguments and firmware entry point to specific offsets in the | |
| 17 | − * OpRegion. When AML reads the "return value" offset from the OpRegion, this | |
| 18 | − * handler loads up the arguments, makes the firmware call, and returns the | |
| 19 | − * result. | |
| 20 | − */ | |
| 21 | − | |
| 22 | −#include <linux/module.h> | |
| 23 | −#include <linux/acpi.h> | |
| 24 | −#include <asm/sal.h> | |
| 25 | − | |
| 26 | −MODULE_AUTHOR("Bjorn Helgaas <bjorn.helgaas@hp.com>"); | |
| 27 | −MODULE_LICENSE("GPL"); | |
| 28 | −MODULE_DESCRIPTION("ACPI opregion handler for native firmware calls"); | |
| 29 | − | |
| 30 | −static bool force_register; | |
| 31 | −module_param_named(force, force_register, bool, 0); | |
| 32 | −MODULE_PARM_DESC(force, "Install opregion handler even without HPQ5001 device"); | |
| 33 | − | |
| 34 | −#define AML_NFW_SPACE 0xA1 | |
| 35 | − | |
| 36 | −struct ia64_pdesc { | |
| 37 | − void *ip; | |
| 38 | − void *gp; | |
| 39 | −}; | |
| 40 | − | |
| 41 | −/* | |
| 42 | − * N.B. The layout of this structure is defined in the HP SPPA FW EAS, and | |
| 43 | − * the member offsets are embedded in AML methods. | |
| 44 | − */ | |
| 45 | −struct ia64_nfw_context { | |
| 46 | − u64 arg[8]; | |
| 47 | − struct ia64_sal_retval ret; | |
| 48 | − u64 ip; | |
| 49 | − u64 gp; | |
| 50 | − u64 pad[2]; | |
| 51 | −}; | |
| 52 | − | |
| 53 | −static void *virt_map(u64 address) | |
| 54 | −{ | |
| 55 | − if (address & (1UL << 63)) | |
| 56 | − return (void *) (__IA64_UNCACHED_OFFSET | address); | |
| 57 | − | |
| 58 | − return __va(address); | |
| 59 | −} | |
| 60 | − | |
| 61 | −static void aml_nfw_execute(struct ia64_nfw_context *c) | |
| 62 | −{ | |
| 63 | − struct ia64_pdesc virt_entry; | |
| 64 | − ia64_sal_handler entry; | |
| 65 | − | |
| 66 | − virt_entry.ip = virt_map(c->ip); | |
| 67 | − virt_entry.gp = virt_map(c->gp); | |
| 68 | − | |
| 69 | − entry = (ia64_sal_handler) &virt_entry; | |
| 70 | − | |
| 71 | − IA64_FW_CALL(entry, c->ret, | |
| 72 | − c->arg[0], c->arg[1], c->arg[2], c->arg[3], | |
| 73 | − c->arg[4], c->arg[5], c->arg[6], c->arg[7]); | |
| 74 | −} | |
| 75 | − | |
| 76 | −static void aml_nfw_read_arg(u8 *offset, u32 bit_width, u64 *value) | |
| 77 | −{ | |
| 78 | − switch (bit_width) { | |
| 79 | − case 8: | |
| 80 | − *value = *(u8 *)offset; | |
| 81 | − break; | |
| 82 | − case 16: | |
| 83 | − *value = *(u16 *)offset; | |
| 84 | − break; | |
| 85 | − case 32: | |
| 86 | − *value = *(u32 *)offset; | |
| 87 | − break; | |
| 88 | − case 64: | |
| 89 | − *value = *(u64 *)offset; | |
| 90 | − break; | |
| 91 | − } | |
| 92 | −} | |
| 93 | − | |
| 94 | −static void aml_nfw_write_arg(u8 *offset, u32 bit_width, u64 *value) | |
| 95 | −{ | |
| 96 | − switch (bit_width) { | |
| 97 | − case 8: | |
| 98 | − *(u8 *) offset = *value; | |
| 99 | − break; | |
| 100 | − case 16: | |
| 101 | − *(u16 *) offset = *value; | |
| 102 | − break; | |
| 103 | − case 32: | |
| 104 | − *(u32 *) offset = *value; | |
| 105 | − break; | |
| 106 | − case 64: | |
| 107 | − *(u64 *) offset = *value; | |
| 108 | − break; | |
| 109 | − } | |
| 110 | −} | |
| 111 | − | |
| 112 | −static acpi_status aml_nfw_handler(u32 function, acpi_physical_address address, | |
| 113 | − u32 bit_width, u64 *value, void *handler_context, | |
| 114 | − void *region_context) | |
| 115 | −{ | |
| 116 | − struct ia64_nfw_context *context = handler_context; | |
| 117 | − u8 *offset = (u8 *) context + address; | |
| 118 | − | |
| 119 | − if (bit_width != 8 && bit_width != 16 && | |
| 120 | − bit_width != 32 && bit_width != 64) | |
| 121 | − return AE_BAD_PARAMETER; | |
| 122 | − | |
| 123 | − if (address + (bit_width >> 3) > sizeof(struct ia64_nfw_context)) | |
| 124 | − return AE_BAD_PARAMETER; | |
| 125 | − | |
| 126 | − switch (function) { | |
| 127 | − case ACPI_READ: | |
| 128 | − if (address == offsetof(struct ia64_nfw_context, ret)) | |
| 129 | − aml_nfw_execute(context); | |
| 130 | − aml_nfw_read_arg(offset, bit_width, value); | |
| 131 | − break; | |
| 132 | − case ACPI_WRITE: | |
| 133 | − aml_nfw_write_arg(offset, bit_width, value); | |
| 134 | − break; | |
| 135 | − } | |
| 136 | − | |
| 137 | − return AE_OK; | |
| 138 | −} | |
| 139 | − | |
| 140 | −static struct ia64_nfw_context global_context; | |
| 141 | −static int global_handler_registered; | |
| 142 | − | |
| 143 | −static int aml_nfw_add_global_handler(void) | |
| 144 | −{ | |
| 145 | − acpi_status status; | |
| 146 | − | |
| 147 | − if (global_handler_registered) | |
| 148 | − return 0; | |
| 149 | − | |
| 150 | − status = acpi_install_address_space_handler(ACPI_ROOT_OBJECT, | |
| 151 | − AML_NFW_SPACE, aml_nfw_handler, NULL, &global_context); | |
| 152 | − if (ACPI_FAILURE(status)) | |
| 153 | − return -ENODEV; | |
| 154 | − | |
| 155 | − global_handler_registered = 1; | |
| 156 | − printk(KERN_INFO "Global 0x%02X opregion handler registered\n", | |
| 157 | − AML_NFW_SPACE); | |
| 158 | − return 0; | |
| 159 | −} | |
| 160 | − | |
| 161 | −static int aml_nfw_remove_global_handler(void) | |
| 162 | −{ | |
| 163 | − acpi_status status; | |
| 164 | − | |
| 165 | − if (!global_handler_registered) | |
| 166 | − return 0; | |
| 167 | − | |
| 168 | − status = acpi_remove_address_space_handler(ACPI_ROOT_OBJECT, | |
| 169 | − AML_NFW_SPACE, aml_nfw_handler); | |
| 170 | − if (ACPI_FAILURE(status)) | |
| 171 | − return -ENODEV; | |
| 172 | − | |
| 173 | − global_handler_registered = 0; | |
| 174 | − printk(KERN_INFO "Global 0x%02X opregion handler removed\n", | |
| 175 | − AML_NFW_SPACE); | |
| 176 | − return 0; | |
| 177 | −} | |
| 178 | − | |
| 179 | −static int aml_nfw_add(struct acpi_device *device) | |
| 180 | −{ | |
| 181 | − /* | |
| 182 | − * We would normally allocate a new context structure and install | |
| 183 | − * the address space handler for the specific device we found. | |
| 184 | − * But the HP-UX implementation shares a single global context | |
| 185 | − * and always puts the handler at the root, so we'll do the same. | |
| 186 | − */ | |
| 187 | − return aml_nfw_add_global_handler(); | |
| 188 | −} | |
| 189 | − | |
| 190 | −static void aml_nfw_remove(struct acpi_device *device) | |
| 191 | −{ | |
| 192 | − aml_nfw_remove_global_handler(); | |
| 193 | −} | |
| 194 | − | |
| 195 | −static const struct acpi_device_id aml_nfw_ids[] = { | |
| 196 | − {"HPQ5001", 0}, | |
| 197 | − {"", 0} | |
| 198 | −}; | |
| 199 | − | |
| 200 | −static struct acpi_driver acpi_aml_nfw_driver = { | |
| 201 | − .name = "native firmware", | |
| 202 | − .ids = aml_nfw_ids, | |
| 203 | − .ops = { | |
| 204 | − .add = aml_nfw_add, | |
| 205 | − .remove = aml_nfw_remove, | |
| 206 | − }, | |
| 207 | −}; | |
| 208 | − | |
| 209 | −static int __init aml_nfw_init(void) | |
| 210 | −{ | |
| 211 | − int result; | |
| 212 | − | |
| 213 | − if (force_register) | |
| 214 | − aml_nfw_add_global_handler(); | |
| 215 | − | |
| 216 | − result = acpi_bus_register_driver(&acpi_aml_nfw_driver); | |
| 217 | − if (result < 0) { | |
| 218 | − aml_nfw_remove_global_handler(); | |
| 219 | − return result; | |
| 220 | − } | |
| 221 | − | |
| 222 | − return 0; | |
| 223 | −} | |
| 224 | − | |
| 225 | −static void __exit aml_nfw_exit(void) | |
| 226 | −{ | |
| 227 | − acpi_bus_unregister_driver(&acpi_aml_nfw_driver); | |
| 228 | − aml_nfw_remove_global_handler(); | |
| 229 | −} | |
| 230 | − | |
| 231 | −module_init(aml_nfw_init); | |
| 232 | −module_exit(aml_nfw_exit); | |
| @@ -1,2155 +0,0 @@ | ||
| 1 | −// SPDX-License-Identifier: GPL-2.0-or-later | |
| 2 | −/* | |
| 3 | −** IA64 System Bus Adapter (SBA) I/O MMU manager | |
| 4 | −** | |
| 5 | −** (c) Copyright 2002-2005 Alex Williamson | |
| 6 | −** (c) Copyright 2002-2003 Grant Grundler | |
| 7 | −** (c) Copyright 2002-2005 Hewlett-Packard Company | |
| 8 | −** | |
| 9 | −** Portions (c) 2000 Grant Grundler (from parisc I/O MMU code) | |
| 10 | −** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code) | |
| 11 | −** | |
| 12 | −** | |
| 13 | −** | |
| 14 | −** This module initializes the IOC (I/O Controller) found on HP | |
| 15 | −** McKinley machines and their successors. | |
| 16 | −** | |
| 17 | −*/ | |
| 18 | − | |
| 19 | −#include <linux/types.h> | |
| 20 | −#include <linux/kernel.h> | |
| 21 | −#include <linux/module.h> | |
| 22 | −#include <linux/spinlock.h> | |
| 23 | −#include <linux/slab.h> | |
| 24 | −#include <linux/init.h> | |
| 25 | −#include <linux/mm.h> | |
| 26 | −#include <linux/string.h> | |
| 27 | −#include <linux/pci.h> | |
| 28 | −#include <linux/proc_fs.h> | |
| 29 | −#include <linux/seq_file.h> | |
| 30 | −#include <linux/acpi.h> | |
| 31 | −#include <linux/efi.h> | |
| 32 | −#include <linux/nodemask.h> | |
| 33 | −#include <linux/bitops.h> /* hweight64() */ | |
| 34 | −#include <linux/crash_dump.h> | |
| 35 | −#include <linux/iommu-helper.h> | |
| 36 | −#include <linux/dma-map-ops.h> | |
| 37 | −#include <linux/prefetch.h> | |
| 38 | −#include <linux/swiotlb.h> | |
| 39 | − | |
| 40 | −#include <asm/delay.h> /* ia64_get_itc() */ | |
| 41 | −#include <asm/io.h> | |
| 42 | −#include <asm/page.h> /* PAGE_OFFSET */ | |
| 43 | −#include <asm/dma.h> | |
| 44 | − | |
| 45 | −#include <asm/acpi-ext.h> | |
| 46 | − | |
| 47 | −#define PFX "IOC: " | |
| 48 | − | |
| 49 | −/* | |
| 50 | −** Enabling timing search of the pdir resource map. Output in /proc. | |
| 51 | −** Disabled by default to optimize performance. | |
| 52 | −*/ | |
| 53 | −#undef PDIR_SEARCH_TIMING | |
| 54 | − | |
| 55 | −/* | |
| 56 | −** This option allows cards capable of 64bit DMA to bypass the IOMMU. If | |
| 57 | −** not defined, all DMA will be 32bit and go through the TLB. | |
| 58 | −** There's potentially a conflict in the bio merge code with us | |
| 59 | −** advertising an iommu, but then bypassing it. Since I/O MMU bypassing | |
| 60 | −** appears to give more performance than bio-level virtual merging, we'll | |
| 61 | −** do the former for now. NOTE: BYPASS_SG also needs to be undef'd to | |
| 62 | −** completely restrict DMA to the IOMMU. | |
| 63 | −*/ | |
| 64 | −#define ALLOW_IOV_BYPASS | |
| 65 | − | |
| 66 | −/* | |
| 67 | −** This option specifically allows/disallows bypassing scatterlists with | |
| 68 | −** multiple entries. Coalescing these entries can allow better DMA streaming | |
| 69 | −** and in some cases shows better performance than entirely bypassing the | |
| 70 | −** IOMMU. Performance increase on the order of 1-2% sequential output/input | |
| 71 | −** using bonnie++ on a RAID0 MD device (sym2 & mpt). | |
| 72 | −*/ | |
| 73 | −#undef ALLOW_IOV_BYPASS_SG | |
| 74 | − | |
| 75 | −/* | |
| 76 | −** If a device prefetches beyond the end of a valid pdir entry, it will cause | |
| 77 | −** a hard failure, ie. MCA. Version 3.0 and later of the zx1 LBA should | |
| 78 | −** disconnect on 4k boundaries and prevent such issues. If the device is | |
| 79 | −** particularly aggressive, this option will keep the entire pdir valid such | |
| 80 | −** that prefetching will hit a valid address. This could severely impact | |
| 81 | −** error containment, and is therefore off by default. The page that is | |
| 82 | −** used for spill-over is poisoned, so that should help debugging somewhat. | |
| 83 | −*/ | |
| 84 | −#undef FULL_VALID_PDIR | |
| 85 | − | |
| 86 | −#define ENABLE_MARK_CLEAN | |
| 87 | − | |
| 88 | −/* | |
| 89 | −** The number of debug flags is a clue - this code is fragile. NOTE: since | |
| 90 | −** tightening the use of res_lock the resource bitmap and actual pdir are no | |
| 91 | −** longer guaranteed to stay in sync. The sanity checking code isn't going to | |
| 92 | −** like that. | |
| 93 | −*/ | |
| 94 | −#undef DEBUG_SBA_INIT | |
| 95 | −#undef DEBUG_SBA_RUN | |
| 96 | −#undef DEBUG_SBA_RUN_SG | |
| 97 | −#undef DEBUG_SBA_RESOURCE | |
| 98 | −#undef ASSERT_PDIR_SANITY | |
| 99 | −#undef DEBUG_LARGE_SG_ENTRIES | |
| 100 | −#undef DEBUG_BYPASS | |
| 101 | − | |
| 102 | −#if defined(FULL_VALID_PDIR) && defined(ASSERT_PDIR_SANITY) | |
| 103 | −#error FULL_VALID_PDIR and ASSERT_PDIR_SANITY are mutually exclusive | |
| 104 | −#endif | |
| 105 | − | |
| 106 | −#define SBA_INLINE __inline__ | |
| 107 | −/* #define SBA_INLINE */ | |
| 108 | − | |
| 109 | −#ifdef DEBUG_SBA_INIT | |
| 110 | −#define DBG_INIT(x...) printk(x) | |
| 111 | −#else | |
| 112 | −#define DBG_INIT(x...) | |
| 113 | −#endif | |
| 114 | − | |
| 115 | −#ifdef DEBUG_SBA_RUN | |
| 116 | −#define DBG_RUN(x...) printk(x) | |
| 117 | −#else | |
| 118 | −#define DBG_RUN(x...) | |
| 119 | −#endif | |
| 120 | − | |
| 121 | −#ifdef DEBUG_SBA_RUN_SG | |
| 122 | −#define DBG_RUN_SG(x...) printk(x) | |
| 123 | −#else | |
| 124 | −#define DBG_RUN_SG(x...) | |
| 125 | −#endif | |
| 126 | − | |
| 127 | − | |
| 128 | −#ifdef DEBUG_SBA_RESOURCE | |
| 129 | −#define DBG_RES(x...) printk(x) | |
| 130 | −#else | |
| 131 | −#define DBG_RES(x...) | |
| 132 | −#endif | |
| 133 | − | |
| 134 | −#ifdef DEBUG_BYPASS | |
| 135 | −#define DBG_BYPASS(x...) printk(x) | |
| 136 | −#else | |
| 137 | −#define DBG_BYPASS(x...) | |
| 138 | −#endif | |
| 139 | − | |
| 140 | −#ifdef ASSERT_PDIR_SANITY | |
| 141 | −#define ASSERT(expr) \ | |
| 142 | − if(!(expr)) { \ | |
| 143 | − printk( "\n" __FILE__ ":%d: Assertion " #expr " failed!\n",__LINE__); \ | |
| 144 | − panic(#expr); \ | |
| 145 | − } | |
| 146 | −#else | |
| 147 | −#define ASSERT(expr) | |
| 148 | −#endif | |
| 149 | − | |
| 150 | −/* | |
| 151 | −** The number of pdir entries to "free" before issuing | |
| 152 | −** a read to PCOM register to flush out PCOM writes. | |
| 153 | −** Interacts with allocation granularity (ie 4 or 8 entries | |
| 154 | −** allocated and free'd/purged at a time might make this | |
| 155 | −** less interesting). | |
| 156 | −*/ | |
| 157 | −#define DELAYED_RESOURCE_CNT 64 | |
| 158 | − | |
| 159 | −#define PCI_DEVICE_ID_HP_SX2000_IOC 0x12ec | |
| 160 | − | |
| 161 | −#define ZX1_IOC_ID ((PCI_DEVICE_ID_HP_ZX1_IOC << 16) | PCI_VENDOR_ID_HP) | |
| 162 | −#define ZX2_IOC_ID ((PCI_DEVICE_ID_HP_ZX2_IOC << 16) | PCI_VENDOR_ID_HP) | |
| 163 | −#define REO_IOC_ID ((PCI_DEVICE_ID_HP_REO_IOC << 16) | PCI_VENDOR_ID_HP) | |
| 164 | −#define SX1000_IOC_ID ((PCI_DEVICE_ID_HP_SX1000_IOC << 16) | PCI_VENDOR_ID_HP) | |
| 165 | −#define SX2000_IOC_ID ((PCI_DEVICE_ID_HP_SX2000_IOC << 16) | PCI_VENDOR_ID_HP) | |
| 166 | − | |
| 167 | −#define ZX1_IOC_OFFSET 0x1000 /* ACPI reports SBA, we want IOC */ | |
| 168 | − | |
| 169 | −#define IOC_FUNC_ID 0x000 | |
| 170 | −#define IOC_FCLASS 0x008 /* function class, bist, header, rev... */ | |
| 171 | −#define IOC_IBASE 0x300 /* IO TLB */ | |
| 172 | −#define IOC_IMASK 0x308 | |
| 173 | −#define IOC_PCOM 0x310 | |
| 174 | −#define IOC_TCNFG 0x318 | |
| 175 | −#define IOC_PDIR_BASE 0x320 | |
| 176 | − | |
| 177 | −#define IOC_ROPE0_CFG 0x500 | |
| 178 | −#define IOC_ROPE_AO 0x10 /* Allow "Relaxed Ordering" */ | |
| 179 | − | |
| 180 | − | |
| 181 | −/* AGP GART driver looks for this */ | |
| 182 | −#define ZX1_SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL | |
| 183 | − | |
| 184 | −/* | |
| 185 | −** The zx1 IOC supports 4/8/16/64KB page sizes (see TCNFG register) | |
| 186 | −** | |
| 187 | −** Some IOCs (sx1000) can run at the above pages sizes, but are | |
| 188 | −** really only supported using the IOC at a 4k page size. | |
| 189 | −** | |
| 190 | −** iovp_size could only be greater than PAGE_SIZE if we are | |
| 191 | −** confident the drivers really only touch the next physical | |
| 192 | −** page iff that driver instance owns it. | |
| 193 | −*/ | |
| 194 | −static unsigned long iovp_size; | |
| 195 | −static unsigned long iovp_shift; | |
| 196 | −static unsigned long iovp_mask; | |
| 197 | − | |
| 198 | −struct ioc { | |
| 199 | − void __iomem *ioc_hpa; /* I/O MMU base address */ | |
| 200 | − char *res_map; /* resource map, bit == pdir entry */ | |
| 201 | − u64 *pdir_base; /* physical base address */ | |
| 202 | − unsigned long ibase; /* pdir IOV Space base */ | |
| 203 | − unsigned long imask; /* pdir IOV Space mask */ | |
| 204 | − | |
| 205 | − unsigned long *res_hint; /* next avail IOVP - circular search */ | |
| 206 | − unsigned long dma_mask; | |
| 207 | − spinlock_t res_lock; /* protects the resource bitmap, but must be held when */ | |
| 208 | − /* clearing pdir to prevent races with allocations. */ | |
| 209 | − unsigned int res_bitshift; /* from the RIGHT! */ | |
| 210 | − unsigned int res_size; /* size of resource map in bytes */ | |
| 211 | −#ifdef CONFIG_NUMA | |
| 212 | − unsigned int node; /* node where this IOC lives */ | |
| 213 | −#endif | |
| 214 | −#if DELAYED_RESOURCE_CNT > 0 | |
| 215 | − spinlock_t saved_lock; /* may want to try to get this on a separate cacheline */ | |
| 216 | − /* than res_lock for bigger systems. */ | |
| 217 | − int saved_cnt; | |
| 218 | − struct sba_dma_pair { | |
| 219 | − dma_addr_t iova; | |
| 220 | − size_t size; | |
| 221 | − } saved[DELAYED_RESOURCE_CNT]; | |
| 222 | −#endif | |
| 223 | − | |
| 224 | −#ifdef PDIR_SEARCH_TIMING | |
| 225 | −#define SBA_SEARCH_SAMPLE 0x100 | |
| 226 | − unsigned long avg_search[SBA_SEARCH_SAMPLE]; | |
| 227 | − unsigned long avg_idx; /* current index into avg_search */ | |
| 228 | −#endif | |
| 229 | − | |
| 230 | − /* Stuff we don't need in performance path */ | |
| 231 | − struct ioc *next; /* list of IOC's in system */ | |
| 232 | − acpi_handle handle; /* for multiple IOC's */ | |
| 233 | − const char *name; | |
| 234 | − unsigned int func_id; | |
| 235 | − unsigned int rev; /* HW revision of chip */ | |
| 236 | − u32 iov_size; | |
| 237 | − unsigned int pdir_size; /* in bytes, determined by IOV Space size */ | |
| 238 | − struct pci_dev *sac_only_dev; | |
| 239 | −}; | |
| 240 | − | |
| 241 | −static struct ioc *ioc_list, *ioc_found; | |
| 242 | −static int reserve_sba_gart = 1; | |
| 243 | − | |
| 244 | −static SBA_INLINE void sba_mark_invalid(struct ioc *, dma_addr_t, size_t); | |
| 245 | −static SBA_INLINE void sba_free_range(struct ioc *, dma_addr_t, size_t); | |
| 246 | − | |
| 247 | −#define sba_sg_address(sg) sg_virt((sg)) | |
| 248 | − | |
| 249 | −#ifdef FULL_VALID_PDIR | |
| 250 | −static u64 prefetch_spill_page; | |
| 251 | −#endif | |
| 252 | − | |
| 253 | −#define GET_IOC(dev) ((dev_is_pci(dev)) \ | |
| 254 | − ? ((struct ioc *) PCI_CONTROLLER(to_pci_dev(dev))->iommu) : NULL) | |
| 255 | − | |
| 256 | −/* | |
| 257 | −** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up | |
| 258 | −** (or rather not merge) DMAs into manageable chunks. | |
| 259 | −** On parisc, this is more of the software/tuning constraint | |
| 260 | −** rather than the HW. I/O MMU allocation algorithms can be | |
| 261 | −** faster with smaller sizes (to some degree). | |
| 262 | −*/ | |
| 263 | −#define DMA_CHUNK_SIZE (BITS_PER_LONG*iovp_size) | |
| 264 | − | |
| 265 | −#define ROUNDUP(x,y) ((x + ((y)-1)) & ~((y)-1)) | |
| 266 | − | |
| 267 | −/************************************ | |
| 268 | −** SBA register read and write support | |
| 269 | −** | |
| 270 | −** BE WARNED: register writes are posted. | |
| 271 | −** (ie follow writes which must reach HW with a read) | |
| 272 | −** | |
| 273 | −*/ | |
| 274 | −#define READ_REG(addr) __raw_readq(addr) | |
| 275 | −#define WRITE_REG(val, addr) __raw_writeq(val, addr) | |
| 276 | − | |
| 277 | −#ifdef DEBUG_SBA_INIT | |
| 278 | − | |
| 279 | −/** | |
| 280 | − * sba_dump_tlb - debugging only - print IOMMU operating parameters | |
| 281 | − * @hpa: base address of the IOMMU | |
| 282 | − * | |
| 283 | − * Print the size/location of the IO MMU PDIR. | |
| 284 | − */ | |
| 285 | −static void | |
| 286 | −sba_dump_tlb(char *hpa) | |
| 287 | −{ | |
| 288 | − DBG_INIT("IO TLB at 0x%p\n", (void *)hpa); | |
| 289 | − DBG_INIT("IOC_IBASE : %016lx\n", READ_REG(hpa+IOC_IBASE)); | |
| 290 | − DBG_INIT("IOC_IMASK : %016lx\n", READ_REG(hpa+IOC_IMASK)); | |
| 291 | − DBG_INIT("IOC_TCNFG : %016lx\n", READ_REG(hpa+IOC_TCNFG)); | |
| 292 | − DBG_INIT("IOC_PDIR_BASE: %016lx\n", READ_REG(hpa+IOC_PDIR_BASE)); | |
| 293 | − DBG_INIT("\n"); | |
| 294 | −} | |
| 295 | −#endif | |
| 296 | − | |
| 297 | − | |
| 298 | −#ifdef ASSERT_PDIR_SANITY | |
| 299 | − | |
| 300 | −/** | |
| 301 | − * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry | |
| 302 | − * @ioc: IO MMU structure which owns the pdir we are interested in. | |
| 303 | − * @msg: text to print ont the output line. | |
| 304 | − * @pide: pdir index. | |
| 305 | − * | |
| 306 | − * Print one entry of the IO MMU PDIR in human readable form. | |
| 307 | − */ | |
| 308 | −static void | |
| 309 | −sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide) | |
| 310 | −{ | |
| 311 | − /* start printing from lowest pde in rval */ | |
| 312 | − u64 *ptr = &ioc->pdir_base[pide & ~(BITS_PER_LONG - 1)]; | |
| 313 | − unsigned long *rptr = (unsigned long *) &ioc->res_map[(pide >>3) & -sizeof(unsigned long)]; | |
| 314 | − uint rcnt; | |
| 315 | − | |
| 316 | − printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n", | |
| 317 | − msg, rptr, pide & (BITS_PER_LONG - 1), *rptr); | |
| 318 | − | |
| 319 | − rcnt = 0; | |
| 320 | − while (rcnt < BITS_PER_LONG) { | |
| 321 | − printk(KERN_DEBUG "%s %2d %p %016Lx\n", | |
| 322 | − (rcnt == (pide & (BITS_PER_LONG - 1))) | |
| 323 | − ? " -->" : " ", | |
| 324 | − rcnt, ptr, (unsigned long long) *ptr ); | |
| 325 | − rcnt++; | |
| 326 | − ptr++; | |
| 327 | − } | |
| 328 | − printk(KERN_DEBUG "%s", msg); | |
| 329 | −} | |
| 330 | − | |
| 331 | − | |
| 332 | −/** | |
| 333 | − * sba_check_pdir - debugging only - consistency checker | |
| 334 | − * @ioc: IO MMU structure which owns the pdir we are interested in. | |
| 335 | − * @msg: text to print ont the output line. | |
| 336 | − * | |
| 337 | − * Verify the resource map and pdir state is consistent | |
| 338 | − */ | |
| 339 | −static int | |
| 340 | −sba_check_pdir(struct ioc *ioc, char *msg) | |
| 341 | −{ | |
| 342 | − u64 *rptr_end = (u64 *) &(ioc->res_map[ioc->res_size]); | |
| 343 | − u64 *rptr = (u64 *) ioc->res_map; /* resource map ptr */ | |
| 344 | − u64 *pptr = ioc->pdir_base; /* pdir ptr */ | |
| 345 | − uint pide = 0; | |
| 346 | − | |
| 347 | − while (rptr < rptr_end) { | |
| 348 | − u64 rval; | |
| 349 | − int rcnt; /* number of bits we might check */ | |
| 350 | − | |
| 351 | − rval = *rptr; | |
| 352 | − rcnt = 64; | |
| 353 | − | |
| 354 | − while (rcnt) { | |
| 355 | − /* Get last byte and highest bit from that */ | |
| 356 | − u32 pde = ((u32)((*pptr >> (63)) & 0x1)); | |
| 357 | − if ((rval & 0x1) ^ pde) | |
| 358 | − { | |
| 359 | − /* | |
| 360 | − ** BUMMER! -- res_map != pdir -- | |
| 361 | − ** Dump rval and matching pdir entries | |
| 362 | − */ | |
| 363 | − sba_dump_pdir_entry(ioc, msg, pide); | |
| 364 | − return(1); | |
| 365 | − } | |
| 366 | − rcnt--; | |
| 367 | − rval >>= 1; /* try the next bit */ | |
| 368 | − pptr++; | |
| 369 | − pide++; | |
| 370 | − } | |
| 371 | − rptr++; /* look at next word of res_map */ | |
| 372 | − } | |
| 373 | − /* It'd be nice if we always got here :^) */ | |
| 374 | − return 0; | |
| 375 | −} | |
| 376 | − | |
| 377 | − | |
| 378 | −/** | |
| 379 | − * sba_dump_sg - debugging only - print Scatter-Gather list | |
| 380 | − * @ioc: IO MMU structure which owns the pdir we are interested in. | |
| 381 | − * @startsg: head of the SG list | |
| 382 | − * @nents: number of entries in SG list | |
| 383 | − * | |
| 384 | − * print the SG list so we can verify it's correct by hand. | |
| 385 | − */ | |
| 386 | −static void | |
| 387 | −sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents) | |
| 388 | −{ | |
| 389 | − while (nents-- > 0) { | |
| 390 | − printk(KERN_DEBUG " %d : DMA %08lx/%05x CPU %p\n", nents, | |
| 391 | − startsg->dma_address, startsg->dma_length, | |
| 392 | − sba_sg_address(startsg)); | |
| 393 | − startsg = sg_next(startsg); | |
| 394 | − } | |
| 395 | −} | |
| 396 | − | |
| 397 | −static void | |
| 398 | −sba_check_sg( struct ioc *ioc, struct scatterlist *startsg, int nents) | |
| 399 | −{ | |
| 400 | − struct scatterlist *the_sg = startsg; | |
| 401 | − int the_nents = nents; | |
| 402 | − | |
| 403 | − while (the_nents-- > 0) { | |
| 404 | − if (sba_sg_address(the_sg) == 0x0UL) | |
| 405 | − sba_dump_sg(NULL, startsg, nents); | |
| 406 | − the_sg = sg_next(the_sg); | |
| 407 | − } | |
| 408 | −} | |
| 409 | − | |
| 410 | −#endif /* ASSERT_PDIR_SANITY */ | |
| 411 | − | |
| 412 | − | |
| 413 | − | |
| 414 | − | |
| 415 | −/************************************************************** | |
| 416 | −* | |
| 417 | −* I/O Pdir Resource Management | |
| 418 | −* | |
| 419 | −* Bits set in the resource map are in use. | |
| 420 | −* Each bit can represent a number of pages. | |
| 421 | −* LSbs represent lower addresses (IOVA's). | |
| 422 | −* | |
| 423 | −***************************************************************/ | |
| 424 | −#define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */ | |
| 425 | − | |
| 426 | −/* Convert from IOVP to IOVA and vice versa. */ | |
| 427 | −#define SBA_IOVA(ioc,iovp,offset) ((ioc->ibase) | (iovp) | (offset)) | |
| 428 | −#define SBA_IOVP(ioc,iova) ((iova) & ~(ioc->ibase)) | |
| 429 | − | |
| 430 | −#define PDIR_ENTRY_SIZE sizeof(u64) | |
| 431 | − | |
| 432 | −#define PDIR_INDEX(iovp) ((iovp)>>iovp_shift) | |
| 433 | − | |
| 434 | −#define RESMAP_MASK(n) ~(~0UL << (n)) | |
| 435 | −#define RESMAP_IDX_MASK (sizeof(unsigned long) - 1) | |
| 436 | − | |
| 437 | − | |
| 438 | −/** | |
| 439 | − * For most cases the normal get_order is sufficient, however it limits us | |
| 440 | − * to PAGE_SIZE being the minimum mapping alignment and TC flush granularity. | |
| 441 | − * It only incurs about 1 clock cycle to use this one with the static variable | |
| 442 | − * and makes the code more intuitive. | |
| 443 | − */ | |
| 444 | −static SBA_INLINE int | |
| 445 | −get_iovp_order (unsigned long size) | |
| 446 | −{ | |
| 447 | − long double d = size - 1; | |
| 448 | − long order; | |
| 449 | − | |
| 450 | − order = ia64_getf_exp(d); | |
| 451 | − order = order - iovp_shift - 0xffff + 1; | |
| 452 | − if (order < 0) | |
| 453 | − order = 0; | |
| 454 | − return order; | |
| 455 | −} | |
| 456 | − | |
| 457 | −static unsigned long ptr_to_pide(struct ioc *ioc, unsigned long *res_ptr, | |
| 458 | − unsigned int bitshiftcnt) | |
| 459 | −{ | |
| 460 | − return (((unsigned long)res_ptr - (unsigned long)ioc->res_map) << 3) | |
| 461 | − + bitshiftcnt; | |
| 462 | −} | |
| 463 | − | |
| 464 | −/** | |
| 465 | − * sba_search_bitmap - find free space in IO PDIR resource bitmap | |
| 466 | − * @ioc: IO MMU structure which owns the pdir we are interested in. | |
| 467 | − * @bits_wanted: number of entries we need. | |
| 468 | − * @use_hint: use res_hint to indicate where to start looking | |
| 469 | − * | |
| 470 | − * Find consecutive free bits in resource bitmap. | |
| 471 | − * Each bit represents one entry in the IO Pdir. | |
| 472 | − * Cool perf optimization: search for log2(size) bits at a time. | |
| 473 | − */ | |
| 474 | −static SBA_INLINE unsigned long | |
| 475 | −sba_search_bitmap(struct ioc *ioc, struct device *dev, | |
| 476 | − unsigned long bits_wanted, int use_hint) | |
| 477 | −{ | |
| 478 | − unsigned long *res_ptr; | |
| 479 | − unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]); | |
| 480 | − unsigned long flags, pide = ~0UL, tpide; | |
| 481 | − unsigned long boundary_size; | |
| 482 | − unsigned long shift; | |
| 483 | − int ret; | |
| 484 | − | |
| 485 | − ASSERT(((unsigned long) ioc->res_hint & (sizeof(unsigned long) - 1UL)) == 0); | |
| 486 | − ASSERT(res_ptr < res_end); | |
| 487 | − | |
| 488 | − boundary_size = dma_get_seg_boundary_nr_pages(dev, iovp_shift); | |
| 489 | − | |
| 490 | − BUG_ON(ioc->ibase & ~iovp_mask); | |
| 491 | − shift = ioc->ibase >> iovp_shift; | |
| 492 | − | |
| 493 | − spin_lock_irqsave(&ioc->res_lock, flags); | |
| 494 | − | |
| 495 | − /* Allow caller to force a search through the entire resource space */ | |
| 496 | − if (likely(use_hint)) { | |
| 497 | − res_ptr = ioc->res_hint; | |
| 498 | − } else { | |
| 499 | − res_ptr = (ulong *)ioc->res_map; | |
| 500 | − ioc->res_bitshift = 0; | |
| 501 | − } | |
| 502 | − | |
| 503 | − /* | |
| 504 | − * N.B. REO/Grande defect AR2305 can cause TLB fetch timeouts | |
| 505 | − * if a TLB entry is purged while in use. sba_mark_invalid() | |
| 506 | − * purges IOTLB entries in power-of-two sizes, so we also | |
| 507 | − * allocate IOVA space in power-of-two sizes. | |
| 508 | − */ | |
| 509 | − bits_wanted = 1UL << get_iovp_order(bits_wanted << iovp_shift); | |
| 510 | − | |
| 511 | − if (likely(bits_wanted == 1)) { | |
| 512 | − unsigned int bitshiftcnt; | |
| 513 | − for(; res_ptr < res_end ; res_ptr++) { | |
| 514 | − if (likely(*res_ptr != ~0UL)) { | |
| 515 | − bitshiftcnt = ffz(*res_ptr); | |
| 516 | − *res_ptr |= (1UL << bitshiftcnt); | |
| 517 | − pide = ptr_to_pide(ioc, res_ptr, bitshiftcnt); | |
| 518 | − ioc->res_bitshift = bitshiftcnt + bits_wanted; | |
| 519 | − goto found_it; | |
| 520 | − } | |
| 521 | − } | |
| 522 | − goto not_found; | |
| 523 | − | |
| 524 | − } | |
| 525 | − | |
| 526 | − if (likely(bits_wanted <= BITS_PER_LONG/2)) { | |
| 527 | − /* | |
| 528 | − ** Search the resource bit map on well-aligned values. | |
| 529 | − ** "o" is the alignment. | |
| 530 | − ** We need the alignment to invalidate I/O TLB using | |
| 531 | − ** SBA HW features in the unmap path. | |
| 532 | − */ | |
| 533 | − unsigned long o = 1 << get_iovp_order(bits_wanted << iovp_shift); | |
| 534 | − uint bitshiftcnt = ROUNDUP(ioc->res_bitshift, o); | |
| 535 | − unsigned long mask, base_mask; | |
| 536 | − | |
| 537 | − base_mask = RESMAP_MASK(bits_wanted); | |
| 538 | − mask = base_mask << bitshiftcnt; | |
| 539 | − | |
| 540 | − DBG_RES("%s() o %ld %p", __func__, o, res_ptr); | |
| 541 | − for(; res_ptr < res_end ; res_ptr++) | |
| 542 | − { | |
| 543 | − DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr); | |
| 544 | − ASSERT(0 != mask); | |
| 545 | − for (; mask ; mask <<= o, bitshiftcnt += o) { | |
| 546 | − tpide = ptr_to_pide(ioc, res_ptr, bitshiftcnt); | |
| 547 | − ret = iommu_is_span_boundary(tpide, bits_wanted, | |
| 548 | − shift, | |
| 549 | − boundary_size); | |
| 550 | − if ((0 == ((*res_ptr) & mask)) && !ret) { | |
| 551 | − *res_ptr |= mask; /* mark resources busy! */ | |
| 552 | − pide = tpide; | |
| 553 | − ioc->res_bitshift = bitshiftcnt + bits_wanted; | |
| 554 | − goto found_it; | |
| 555 | − } | |
| 556 | − } | |
| 557 | − | |
| 558 | − bitshiftcnt = 0; | |
| 559 | − mask = base_mask; | |
| 560 | − | |
| 561 | − } | |
| 562 | − | |
| 563 | − } else { | |
| 564 | − int qwords, bits, i; | |
| 565 | − unsigned long *end; | |
| 566 | − | |
| 567 | − qwords = bits_wanted >> 6; /* /64 */ | |
| 568 | − bits = bits_wanted - (qwords * BITS_PER_LONG); | |
| 569 | − | |
| 570 | − end = res_end - qwords; | |
| 571 | − | |
| 572 | − for (; res_ptr < end; res_ptr++) { | |
| 573 | − tpide = ptr_to_pide(ioc, res_ptr, 0); | |
| 574 | − ret = iommu_is_span_boundary(tpide, bits_wanted, | |
| 575 | − shift, boundary_size); | |
| 576 | − if (ret) | |
| 577 | − goto next_ptr; | |
| 578 | − for (i = 0 ; i < qwords ; i++) { | |
| 579 | − if (res_ptr[i] != 0) | |
| 580 | − goto next_ptr; | |
| 581 | − } | |
| 582 | − if (bits && res_ptr[i] && (__ffs(res_ptr[i]) < bits)) | |
| 583 | − continue; | |
| 584 | − | |
| 585 | − /* Found it, mark it */ | |
| 586 | − for (i = 0 ; i < qwords ; i++) | |
| 587 | − res_ptr[i] = ~0UL; | |
| 588 | − res_ptr[i] |= RESMAP_MASK(bits); | |
| 589 | − | |
| 590 | − pide = tpide; | |
| 591 | − res_ptr += qwords; | |
| 592 | − ioc->res_bitshift = bits; | |
| 593 | − goto found_it; | |
| 594 | −next_ptr: | |
| 595 | − ; | |
| 596 | − } | |
| 597 | − } | |
| 598 | − | |
| 599 | −not_found: | |
| 600 | − prefetch(ioc->res_map); | |
| 601 | − ioc->res_hint = (unsigned long *) ioc->res_map; | |
| 602 | − ioc->res_bitshift = 0; | |
| 603 | − spin_unlock_irqrestore(&ioc->res_lock, flags); | |
| 604 | − return (pide); | |
| 605 | − | |
| 606 | −found_it: | |
| 607 | − ioc->res_hint = res_ptr; | |
| 608 | − spin_unlock_irqrestore(&ioc->res_lock, flags); | |
| 609 | − return (pide); | |
| 610 | −} | |
| 611 | − | |
| 612 | − | |
| 613 | −/** | |
| 614 | − * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap | |
| 615 | − * @ioc: IO MMU structure which owns the pdir we are interested in. | |
| 616 | − * @size: number of bytes to create a mapping for | |
| 617 | − * | |
| 618 | − * Given a size, find consecutive unmarked and then mark those bits in the | |
| 619 | − * resource bit map. | |
| 620 | − */ | |
| 621 | −static int | |
| 622 | −sba_alloc_range(struct ioc *ioc, struct device *dev, size_t size) | |
| 623 | −{ | |
| 624 | − unsigned int pages_needed = size >> iovp_shift; | |
| 625 | −#ifdef PDIR_SEARCH_TIMING | |
| 626 | − unsigned long itc_start; | |
| 627 | −#endif | |
| 628 | − unsigned long pide; | |
| 629 | − | |
| 630 | − ASSERT(pages_needed); | |
| 631 | − ASSERT(0 == (size & ~iovp_mask)); | |
| 632 | − | |
| 633 | −#ifdef PDIR_SEARCH_TIMING | |
| 634 | − itc_start = ia64_get_itc(); | |
| 635 | −#endif | |
| 636 | − /* | |
| 637 | − ** "seek and ye shall find"...praying never hurts either... | |
| 638 | − */ | |
| 639 | − pide = sba_search_bitmap(ioc, dev, pages_needed, 1); | |
| 640 | − if (unlikely(pide >= (ioc->res_size << 3))) { | |
| 641 | − pide = sba_search_bitmap(ioc, dev, pages_needed, 0); | |
| 642 | − if (unlikely(pide >= (ioc->res_size << 3))) { | |
| 643 | −#if DELAYED_RESOURCE_CNT > 0 | |
| 644 | − unsigned long flags; | |
| 645 | − | |
| 646 | − /* | |
| 647 | − ** With delayed resource freeing, we can give this one more shot. We're | |
| 648 | − ** getting close to being in trouble here, so do what we can to make this | |
| 649 | − ** one count. | |
| 650 | − */ | |
| 651 | − spin_lock_irqsave(&ioc->saved_lock, flags); | |
| 652 | − if (ioc->saved_cnt > 0) { | |
| 653 | − struct sba_dma_pair *d; | |
| 654 | − int cnt = ioc->saved_cnt; | |
| 655 | − | |
| 656 | − d = &(ioc->saved[ioc->saved_cnt - 1]); | |
| 657 | − | |
| 658 | − spin_lock(&ioc->res_lock); | |
| 659 | − while (cnt--) { | |
| 660 | − sba_mark_invalid(ioc, d->iova, d->size); | |
| 661 | − sba_free_range(ioc, d->iova, d->size); | |
| 662 | − d--; | |
| 663 | − } | |
| 664 | − ioc->saved_cnt = 0; | |
| 665 | − READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ | |
| 666 | − spin_unlock(&ioc->res_lock); | |
| 667 | − } | |
| 668 | − spin_unlock_irqrestore(&ioc->saved_lock, flags); | |
| 669 | − | |
| 670 | − pide = sba_search_bitmap(ioc, dev, pages_needed, 0); | |
| 671 | − if (unlikely(pide >= (ioc->res_size << 3))) { | |
| 672 | − printk(KERN_WARNING "%s: I/O MMU @ %p is" | |
| 673 | − "out of mapping resources, %u %u %lx\n", | |
| 674 | − __func__, ioc->ioc_hpa, ioc->res_size, | |
| 675 | − pages_needed, dma_get_seg_boundary(dev)); | |
| 676 | − return -1; | |
| 677 | − } | |
| 678 | −#else | |
| 679 | − printk(KERN_WARNING "%s: I/O MMU @ %p is" | |
| 680 | − "out of mapping resources, %u %u %lx\n", | |
| 681 | − __func__, ioc->ioc_hpa, ioc->res_size, | |
| 682 | − pages_needed, dma_get_seg_boundary(dev)); | |
| 683 | − return -1; | |
| 684 | −#endif | |
| 685 | − } | |
| 686 | − } | |
| 687 | − | |
| 688 | −#ifdef PDIR_SEARCH_TIMING | |
| 689 | − ioc->avg_search[ioc->avg_idx++] = (ia64_get_itc() - itc_start) / pages_needed; | |
| 690 | − ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1; | |
| 691 | −#endif | |
| 692 | − | |
| 693 | − prefetchw(&(ioc->pdir_base[pide])); | |
| 694 | − | |
| 695 | −#ifdef ASSERT_PDIR_SANITY | |
| 696 | − /* verify the first enable bit is clear */ | |
| 697 | − if(0x00 != ((u8 *) ioc->pdir_base)[pide*PDIR_ENTRY_SIZE + 7]) { | |
| 698 | − sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide); | |
| 699 | − } | |
| 700 | −#endif | |
| 701 | − | |
| 702 | − DBG_RES("%s(%x) %d -> %lx hint %x/%x\n", | |
| 703 | − __func__, size, pages_needed, pide, | |
| 704 | − (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map), | |
| 705 | − ioc->res_bitshift ); | |
| 706 | − | |
| 707 | − return (pide); | |
| 708 | −} | |
| 709 | − | |
| 710 | − | |
| 711 | −/** | |
| 712 | − * sba_free_range - unmark bits in IO PDIR resource bitmap | |
| 713 | − * @ioc: IO MMU structure which owns the pdir we are interested in. | |
| 714 | − * @iova: IO virtual address which was previously allocated. | |
| 715 | − * @size: number of bytes to create a mapping for | |
| 716 | − * | |
| 717 | − * clear bits in the ioc's resource map | |
| 718 | − */ | |
| 719 | −static SBA_INLINE void | |
| 720 | −sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size) | |
| 721 | −{ | |
| 722 | − unsigned long iovp = SBA_IOVP(ioc, iova); | |
| 723 | − unsigned int pide = PDIR_INDEX(iovp); | |
| 724 | − unsigned int ridx = pide >> 3; /* convert bit to byte address */ | |
| 725 | − unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]); | |
| 726 | − int bits_not_wanted = size >> iovp_shift; | |
| 727 | − unsigned long m; | |
| 728 | − | |
| 729 | − /* Round up to power-of-two size: see AR2305 note above */ | |
| 730 | − bits_not_wanted = 1UL << get_iovp_order(bits_not_wanted << iovp_shift); | |
| 731 | − for (; bits_not_wanted > 0 ; res_ptr++) { | |
| 732 | − | |
| 733 | − if (unlikely(bits_not_wanted > BITS_PER_LONG)) { | |
| 734 | − | |
| 735 | − /* these mappings start 64bit aligned */ | |
| 736 | − *res_ptr = 0UL; | |
| 737 | − bits_not_wanted -= BITS_PER_LONG; | |
| 738 | − pide += BITS_PER_LONG; | |
| 739 | − | |
| 740 | − } else { | |
| 741 | − | |
| 742 | − /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */ | |
| 743 | − m = RESMAP_MASK(bits_not_wanted) << (pide & (BITS_PER_LONG - 1)); | |
| 744 | − bits_not_wanted = 0; | |
| 745 | − | |
| 746 | − DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n", __func__, (uint) iova, size, | |
| 747 | − bits_not_wanted, m, pide, res_ptr, *res_ptr); | |
| 748 | − | |
| 749 | − ASSERT(m != 0); | |
| 750 | − ASSERT(bits_not_wanted); | |
| 751 | − ASSERT((*res_ptr & m) == m); /* verify same bits are set */ | |
| 752 | − *res_ptr &= ~m; | |
| 753 | − } | |
| 754 | − } | |
| 755 | −} | |
| 756 | − | |
| 757 | − | |
| 758 | −/************************************************************** | |
| 759 | −* | |
| 760 | −* "Dynamic DMA Mapping" support (aka "Coherent I/O") | |
| 761 | −* | |
| 762 | −***************************************************************/ | |
| 763 | − | |
| 764 | −/** | |
| 765 | − * sba_io_pdir_entry - fill in one IO PDIR entry | |
| 766 | − * @pdir_ptr: pointer to IO PDIR entry | |
| 767 | − * @vba: Virtual CPU address of buffer to map | |
| 768 | − * | |
| 769 | − * SBA Mapping Routine | |
| 770 | − * | |
| 771 | − * Given a virtual address (vba, arg1) sba_io_pdir_entry() | |
| 772 | − * loads the I/O PDIR entry pointed to by pdir_ptr (arg0). | |
| 773 | − * Each IO Pdir entry consists of 8 bytes as shown below | |
| 774 | − * (LSB == bit 0): | |
| 775 | − * | |
| 776 | − * 63 40 11 7 0 | |
| 777 | − * +-+---------------------+----------------------------------+----+--------+ | |
| 778 | − * |V| U | PPN[39:12] | U | FF | | |
| 779 | − * +-+---------------------+----------------------------------+----+--------+ | |
| 780 | − * | |
| 781 | − * V == Valid Bit | |
| 782 | − * U == Unused | |
| 783 | − * PPN == Physical Page Number | |
| 784 | − * | |
| 785 | − * The physical address fields are filled with the results of virt_to_phys() | |
| 786 | − * on the vba. | |
| 787 | − */ | |
| 788 | − | |
| 789 | −#if 1 | |
| 790 | −#define sba_io_pdir_entry(pdir_ptr, vba) *pdir_ptr = ((vba & ~0xE000000000000FFFULL) \ | |
| 791 | − | 0x8000000000000000ULL) | |
| 792 | −#else | |
| 793 | −void SBA_INLINE | |
| 794 | −sba_io_pdir_entry(u64 *pdir_ptr, unsigned long vba) | |
| 795 | −{ | |
| 796 | − *pdir_ptr = ((vba & ~0xE000000000000FFFULL) | 0x80000000000000FFULL); | |
| 797 | −} | |
| 798 | −#endif | |
| 799 | − | |
| 800 | −#ifdef ENABLE_MARK_CLEAN | |
| 801 | −/* | |
| 802 | − * Since DMA is i-cache coherent, any (complete) pages that were written via | |
| 803 | − * DMA can be marked as "clean" so that lazy_mmu_prot_update() doesn't have to | |
| 804 | − * flush them when they get mapped into an executable vm-area. | |
| 805 | − */ | |
| 806 | −static void mark_clean(void *addr, size_t size) | |
| 807 | −{ | |
| 808 | − struct folio *folio = virt_to_folio(addr); | |
| 809 | − ssize_t left = size; | |
| 810 | − size_t offset = offset_in_folio(folio, addr); | |
| 811 | − | |
| 812 | − if (offset) { | |
| 813 | − left -= folio_size(folio) - offset; | |
| 814 | − if (left <= 0) | |
| 815 | − return; | |
| 816 | − folio = folio_next(folio); | |
| 817 | − } | |
| 818 | − | |
| 819 | − while (left >= folio_size(folio)) { | |
| 820 | − left -= folio_size(folio); | |
| 821 | − set_bit(PG_arch_1, &folio->flags); | |
| 822 | − if (!left) | |
| 823 | − break; | |
| 824 | − folio = folio_next(folio); | |
| 825 | − } | |
| 826 | −} | |
| 827 | −#endif | |
| 828 | − | |
| 829 | −/** | |
| 830 | − * sba_mark_invalid - invalidate one or more IO PDIR entries | |
| 831 | − * @ioc: IO MMU structure which owns the pdir we are interested in. | |
| 832 | − * @iova: IO Virtual Address mapped earlier | |
| 833 | − * @byte_cnt: number of bytes this mapping covers. | |
| 834 | − * | |
| 835 | − * Marking the IO PDIR entry(ies) as Invalid and invalidate | |
| 836 | − * corresponding IO TLB entry. The PCOM (Purge Command Register) | |
| 837 | − * is to purge stale entries in the IO TLB when unmapping entries. | |
| 838 | − * | |
| 839 | − * The PCOM register supports purging of multiple pages, with a minium | |
| 840 | − * of 1 page and a maximum of 2GB. Hardware requires the address be | |
| 841 | − * aligned to the size of the range being purged. The size of the range | |
| 842 | − * must be a power of 2. The "Cool perf optimization" in the | |
| 843 | − * allocation routine helps keep that true. | |
| 844 | − */ | |
| 845 | −static SBA_INLINE void | |
| 846 | −sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt) | |
| 847 | −{ | |
| 848 | − u32 iovp = (u32) SBA_IOVP(ioc,iova); | |
| 849 | − | |
| 850 | − int off = PDIR_INDEX(iovp); | |
| 851 | − | |
| 852 | − /* Must be non-zero and rounded up */ | |
| 853 | − ASSERT(byte_cnt > 0); | |
| 854 | − ASSERT(0 == (byte_cnt & ~iovp_mask)); | |
| 855 | − | |
| 856 | −#ifdef ASSERT_PDIR_SANITY | |
| 857 | − /* Assert first pdir entry is set */ | |
| 858 | − if (!(ioc->pdir_base[off] >> 60)) { | |
| 859 | − sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp)); | |
| 860 | − } | |
| 861 | −#endif | |
| 862 | − | |
| 863 | − if (byte_cnt <= iovp_size) | |
| 864 | − { | |
| 865 | − ASSERT(off < ioc->pdir_size); | |
| 866 | − | |
| 867 | − iovp |= iovp_shift; /* set "size" field for PCOM */ | |
| 868 | − | |
| 869 | −#ifndef FULL_VALID_PDIR | |
| 870 | − /* | |
| 871 | − ** clear I/O PDIR entry "valid" bit | |
| 872 | − ** Do NOT clear the rest - save it for debugging. | |
| 873 | − ** We should only clear bits that have previously | |
| 874 | − ** been enabled. | |
| 875 | − */ | |
| 876 | − ioc->pdir_base[off] &= ~(0x80000000000000FFULL); | |
| 877 | −#else | |
| 878 | − /* | |
| 879 | − ** If we want to maintain the PDIR as valid, put in | |
| 880 | − ** the spill page so devices prefetching won't | |
| 881 | − ** cause a hard fail. | |
| 882 | − */ | |
| 883 | − ioc->pdir_base[off] = (0x80000000000000FFULL | prefetch_spill_page); | |
| 884 | −#endif | |
| 885 | − } else { | |
| 886 | − u32 t = get_iovp_order(byte_cnt) + iovp_shift; | |
| 887 | − | |
| 888 | − iovp |= t; | |
| 889 | − ASSERT(t <= 31); /* 2GB! Max value of "size" field */ | |
| 890 | − | |
| 891 | − do { | |
| 892 | − /* verify this pdir entry is enabled */ | |
| 893 | − ASSERT(ioc->pdir_base[off] >> 63); | |
| 894 | −#ifndef FULL_VALID_PDIR | |
| 895 | − /* clear I/O Pdir entry "valid" bit first */ | |
| 896 | − ioc->pdir_base[off] &= ~(0x80000000000000FFULL); | |
| 897 | −#else | |
| 898 | − ioc->pdir_base[off] = (0x80000000000000FFULL | prefetch_spill_page); | |
| 899 | −#endif | |
| 900 | − off++; | |
| 901 | − byte_cnt -= iovp_size; | |
| 902 | − } while (byte_cnt > 0); | |
| 903 | − } | |
| 904 | − | |
| 905 | − WRITE_REG(iovp | ioc->ibase, ioc->ioc_hpa+IOC_PCOM); | |
| 906 | −} | |
| 907 | − | |
| 908 | −/** | |
| 909 | − * sba_map_page - map one buffer and return IOVA for DMA | |
| 910 | − * @dev: instance of PCI owned by the driver that's asking. | |
| 911 | − * @page: page to map | |
| 912 | − * @poff: offset into page | |
| 913 | − * @size: number of bytes to map | |
| 914 | − * @dir: dma direction | |
| 915 | − * @attrs: optional dma attributes | |
| 916 | − * | |
| 917 | − * See Documentation/core-api/dma-api-howto.rst | |
| 918 | − */ | |
| 919 | −static dma_addr_t sba_map_page(struct device *dev, struct page *page, | |
| 920 | − unsigned long poff, size_t size, | |
| 921 | − enum dma_data_direction dir, | |
| 922 | − unsigned long attrs) | |
| 923 | −{ | |
| 924 | − struct ioc *ioc; | |
| 925 | − void *addr = page_address(page) + poff; | |
| 926 | − dma_addr_t iovp; | |
| 927 | − dma_addr_t offset; | |
| 928 | − u64 *pdir_start; | |
| 929 | − int pide; | |
| 930 | −#ifdef ASSERT_PDIR_SANITY | |
| 931 | − unsigned long flags; | |
| 932 | −#endif | |
| 933 | −#ifdef ALLOW_IOV_BYPASS | |
| 934 | − unsigned long pci_addr = virt_to_phys(addr); | |
| 935 | −#endif | |
| 936 | − | |
| 937 | −#ifdef ALLOW_IOV_BYPASS | |
| 938 | − ASSERT(to_pci_dev(dev)->dma_mask); | |
| 939 | − /* | |
| 940 | − ** Check if the PCI device can DMA to ptr... if so, just return ptr | |
| 941 | − */ | |
| 942 | − if (likely((pci_addr & ~to_pci_dev(dev)->dma_mask) == 0)) { | |
| 943 | − /* | |
| 944 | − ** Device is bit capable of DMA'ing to the buffer... | |
| 945 | − ** just return the PCI address of ptr | |
| 946 | − */ | |
| 947 | − DBG_BYPASS("sba_map_page() bypass mask/addr: " | |
| 948 | − "0x%lx/0x%lx\n", | |
| 949 | − to_pci_dev(dev)->dma_mask, pci_addr); | |
| 950 | − return pci_addr; | |
| 951 | − } | |
| 952 | −#endif | |
| 953 | − ioc = GET_IOC(dev); | |
| 954 | − ASSERT(ioc); | |
| 955 | − | |
| 956 | − prefetch(ioc->res_hint); | |
| 957 | − | |
| 958 | − ASSERT(size > 0); | |
| 959 | − ASSERT(size <= DMA_CHUNK_SIZE); | |
| 960 | − | |
| 961 | − /* save offset bits */ | |
| 962 | − offset = ((dma_addr_t) (long) addr) & ~iovp_mask; | |
| 963 | − | |
| 964 | − /* round up to nearest iovp_size */ | |
| 965 | − size = (size + offset + ~iovp_mask) & iovp_mask; | |
| 966 | − | |
| 967 | −#ifdef ASSERT_PDIR_SANITY | |
| 968 | − spin_lock_irqsave(&ioc->res_lock, flags); | |
| 969 | − if (sba_check_pdir(ioc,"Check before sba_map_page()")) | |
| 970 | − panic("Sanity check failed"); | |
| 971 | − spin_unlock_irqrestore(&ioc->res_lock, flags); | |
| 972 | −#endif | |
| 973 | − | |
| 974 | − pide = sba_alloc_range(ioc, dev, size); | |
| 975 | − if (pide < 0) | |
| 976 | − return DMA_MAPPING_ERROR; | |
| 977 | − | |
| 978 | − iovp = (dma_addr_t) pide << iovp_shift; | |
| 979 | − | |
| 980 | − DBG_RUN("%s() 0x%p -> 0x%lx\n", __func__, addr, (long) iovp | offset); | |
| 981 | − | |
| 982 | − pdir_start = &(ioc->pdir_base[pide]); | |
| 983 | − | |
| 984 | − while (size > 0) { | |
| 985 | − ASSERT(((u8 *)pdir_start)[7] == 0); /* verify availability */ | |
| 986 | − sba_io_pdir_entry(pdir_start, (unsigned long) addr); | |
| 987 | − | |
| 988 | − DBG_RUN(" pdir 0x%p %lx\n", pdir_start, *pdir_start); | |
| 989 | − | |
| 990 | − addr += iovp_size; | |
| 991 | − size -= iovp_size; | |
| 992 | − pdir_start++; | |
| 993 | − } | |
| 994 | − /* force pdir update */ | |
| 995 | − wmb(); | |
| 996 | − | |
| 997 | − /* form complete address */ | |
| 998 | −#ifdef ASSERT_PDIR_SANITY | |
| 999 | − spin_lock_irqsave(&ioc->res_lock, flags); | |
| 1000 | − sba_check_pdir(ioc,"Check after sba_map_page()"); | |
| 1001 | − spin_unlock_irqrestore(&ioc->res_lock, flags); | |
| 1002 | −#endif | |
| 1003 | − return SBA_IOVA(ioc, iovp, offset); | |
| 1004 | −} | |
| 1005 | − | |
| 1006 | −#ifdef ENABLE_MARK_CLEAN | |
| 1007 | −static SBA_INLINE void | |
| 1008 | −sba_mark_clean(struct ioc *ioc, dma_addr_t iova, size_t size) | |
| 1009 | −{ | |
| 1010 | − u32 iovp = (u32) SBA_IOVP(ioc,iova); | |
| 1011 | − int off = PDIR_INDEX(iovp); | |
| 1012 | − void *addr; | |
| 1013 | − | |
| 1014 | − if (size <= iovp_size) { | |
| 1015 | − addr = phys_to_virt(ioc->pdir_base[off] & | |
| 1016 | − ~0xE000000000000FFFULL); | |
| 1017 | − mark_clean(addr, size); | |
| 1018 | − } else { | |
| 1019 | − do { | |
| 1020 | − addr = phys_to_virt(ioc->pdir_base[off] & | |
| 1021 | − ~0xE000000000000FFFULL); | |
| 1022 | − mark_clean(addr, min(size, iovp_size)); | |
| 1023 | − off++; | |
| 1024 | − size -= iovp_size; | |
| 1025 | − } while (size > 0); | |
| 1026 | − } | |
| 1027 | −} | |
| 1028 | −#endif | |
| 1029 | − | |
| 1030 | −/** | |
| 1031 | − * sba_unmap_page - unmap one IOVA and free resources | |
| 1032 | − * @dev: instance of PCI owned by the driver that's asking. | |
| 1033 | − * @iova: IOVA of driver buffer previously mapped. | |
| 1034 | − * @size: number of bytes mapped in driver buffer. | |
| 1035 | − * @dir: R/W or both. | |
| 1036 | − * @attrs: optional dma attributes | |
| 1037 | − * | |
| 1038 | − * See Documentation/core-api/dma-api-howto.rst | |
| 1039 | − */ | |
| 1040 | −static void sba_unmap_page(struct device *dev, dma_addr_t iova, size_t size, | |
| 1041 | − enum dma_data_direction dir, unsigned long attrs) | |
| 1042 | −{ | |
| 1043 | − struct ioc *ioc; | |
| 1044 | −#if DELAYED_RESOURCE_CNT > 0 | |
| 1045 | − struct sba_dma_pair *d; | |
| 1046 | −#endif | |
| 1047 | − unsigned long flags; | |
| 1048 | − dma_addr_t offset; | |
| 1049 | − | |
| 1050 | − ioc = GET_IOC(dev); | |
| 1051 | − ASSERT(ioc); | |
| 1052 | − | |
| 1053 | −#ifdef ALLOW_IOV_BYPASS | |
| 1054 | − if (likely((iova & ioc->imask) != ioc->ibase)) { | |
| 1055 | − /* | |
| 1056 | − ** Address does not fall w/in IOVA, must be bypassing | |
| 1057 | − */ | |
| 1058 | − DBG_BYPASS("sba_unmap_page() bypass addr: 0x%lx\n", | |
| 1059 | − iova); | |
| 1060 | − | |
| 1061 | −#ifdef ENABLE_MARK_CLEAN | |
| 1062 | − if (dir == DMA_FROM_DEVICE) { | |
| 1063 | − mark_clean(phys_to_virt(iova), size); | |
| 1064 | − } | |
| 1065 | −#endif | |
| 1066 | − return; | |
| 1067 | − } | |
| 1068 | −#endif | |
| 1069 | − offset = iova & ~iovp_mask; | |
| 1070 | − | |
| 1071 | − DBG_RUN("%s() iovp 0x%lx/%x\n", __func__, (long) iova, size); | |
| 1072 | − | |
| 1073 | − iova ^= offset; /* clear offset bits */ | |
| 1074 | − size += offset; | |
| 1075 | − size = ROUNDUP(size, iovp_size); | |
| 1076 | − | |
| 1077 | −#ifdef ENABLE_MARK_CLEAN | |
| 1078 | − if (dir == DMA_FROM_DEVICE) | |
| 1079 | − sba_mark_clean(ioc, iova, size); | |
| 1080 | −#endif | |
| 1081 | − | |
| 1082 | −#if DELAYED_RESOURCE_CNT > 0 | |
| 1083 | − spin_lock_irqsave(&ioc->saved_lock, flags); | |
| 1084 | − d = &(ioc->saved[ioc->saved_cnt]); | |
| 1085 | − d->iova = iova; | |
| 1086 | − d->size = size; | |
| 1087 | − if (unlikely(++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT)) { | |
| 1088 | − int cnt = ioc->saved_cnt; | |
| 1089 | − spin_lock(&ioc->res_lock); | |
| 1090 | − while (cnt--) { | |
| 1091 | − sba_mark_invalid(ioc, d->iova, d->size); | |
| 1092 | − sba_free_range(ioc, d->iova, d->size); | |
| 1093 | − d--; | |
| 1094 | − } | |
| 1095 | − ioc->saved_cnt = 0; | |
| 1096 | − READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ | |
| 1097 | − spin_unlock(&ioc->res_lock); | |
| 1098 | − } | |
| 1099 | − spin_unlock_irqrestore(&ioc->saved_lock, flags); | |
| 1100 | −#else /* DELAYED_RESOURCE_CNT == 0 */ | |
| 1101 | − spin_lock_irqsave(&ioc->res_lock, flags); | |
| 1102 | − sba_mark_invalid(ioc, iova, size); | |
| 1103 | − sba_free_range(ioc, iova, size); | |
| 1104 | − READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ | |
| 1105 | − spin_unlock_irqrestore(&ioc->res_lock, flags); | |
| 1106 | −#endif /* DELAYED_RESOURCE_CNT == 0 */ | |
| 1107 | −} | |
| 1108 | − | |
| 1109 | −/** | |
| 1110 | − * sba_alloc_coherent - allocate/map shared mem for DMA | |
| 1111 | − * @dev: instance of PCI owned by the driver that's asking. | |
| 1112 | − * @size: number of bytes mapped in driver buffer. | |
| 1113 | − * @dma_handle: IOVA of new buffer. | |
| 1114 | − * | |
| 1115 | − * See Documentation/core-api/dma-api-howto.rst | |
| 1116 | − */ | |
| 1117 | −static void * | |
| 1118 | −sba_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, | |
| 1119 | − gfp_t flags, unsigned long attrs) | |
| 1120 | −{ | |
| 1121 | − struct page *page; | |
| 1122 | − struct ioc *ioc; | |
| 1123 | − int node = -1; | |
| 1124 | − void *addr; | |
| 1125 | − | |
| 1126 | − ioc = GET_IOC(dev); | |
| 1127 | − ASSERT(ioc); | |
| 1128 | −#ifdef CONFIG_NUMA | |
| 1129 | − node = ioc->node; | |
| 1130 | −#endif | |
| 1131 | − | |
| 1132 | − page = alloc_pages_node(node, flags, get_order(size)); | |
| 1133 | − if (unlikely(!page)) | |
| 1134 | − return NULL; | |
| 1135 | − | |
| 1136 | − addr = page_address(page); | |
| 1137 | − memset(addr, 0, size); | |
| 1138 | − *dma_handle = page_to_phys(page); | |
| 1139 | − | |
| 1140 | −#ifdef ALLOW_IOV_BYPASS | |
| 1141 | − ASSERT(dev->coherent_dma_mask); | |
| 1142 | − /* | |
| 1143 | − ** Check if the PCI device can DMA to ptr... if so, just return ptr | |
| 1144 | − */ | |
| 1145 | − if (likely((*dma_handle & ~dev->coherent_dma_mask) == 0)) { | |
| 1146 | − DBG_BYPASS("sba_alloc_coherent() bypass mask/addr: 0x%lx/0x%lx\n", | |
| 1147 | − dev->coherent_dma_mask, *dma_handle); | |
| 1148 | − | |
| 1149 | − return addr; | |
| 1150 | − } | |
| 1151 | −#endif | |
| 1152 | − | |
| 1153 | − /* | |
| 1154 | − * If device can't bypass or bypass is disabled, pass the 32bit fake | |
| 1155 | − * device to map single to get an iova mapping. | |
| 1156 | − */ | |
| 1157 | − *dma_handle = sba_map_page(&ioc->sac_only_dev->dev, page, 0, size, | |
| 1158 | − DMA_BIDIRECTIONAL, 0); | |
| 1159 | − if (dma_mapping_error(dev, *dma_handle)) | |
| 1160 | − return NULL; | |
| 1161 | − return addr; | |
| 1162 | −} | |
| 1163 | − | |
| 1164 | − | |
| 1165 | −/** | |
| 1166 | − * sba_free_coherent - free/unmap shared mem for DMA | |
| 1167 | − * @dev: instance of PCI owned by the driver that's asking. | |
| 1168 | − * @size: number of bytes mapped in driver buffer. | |
| 1169 | − * @vaddr: virtual address IOVA of "consistent" buffer. | |
| 1170 | − * @dma_handler: IO virtual address of "consistent" buffer. | |
| 1171 | − * | |
| 1172 | − * See Documentation/core-api/dma-api-howto.rst | |
| 1173 | − */ | |
| 1174 | −static void sba_free_coherent(struct device *dev, size_t size, void *vaddr, | |
| 1175 | − dma_addr_t dma_handle, unsigned long attrs) | |
| 1176 | −{ | |
| 1177 | − sba_unmap_page(dev, dma_handle, size, 0, 0); | |
| 1178 | − free_pages((unsigned long) vaddr, get_order(size)); | |
| 1179 | −} | |
| 1180 | − | |
| 1181 | − | |
| 1182 | −/* | |
| 1183 | −** Since 0 is a valid pdir_base index value, can't use that | |
| 1184 | −** to determine if a value is valid or not. Use a flag to indicate | |
| 1185 | −** the SG list entry contains a valid pdir index. | |
| 1186 | −*/ | |
| 1187 | −#define PIDE_FLAG 0x1UL | |
| 1188 | − | |
| 1189 | −#ifdef DEBUG_LARGE_SG_ENTRIES | |
| 1190 | −int dump_run_sg = 0; | |
| 1191 | −#endif | |
| 1192 | − | |
| 1193 | − | |
| 1194 | −/** | |
| 1195 | − * sba_fill_pdir - write allocated SG entries into IO PDIR | |
| 1196 | − * @ioc: IO MMU structure which owns the pdir we are interested in. | |
| 1197 | − * @startsg: list of IOVA/size pairs | |
| 1198 | − * @nents: number of entries in startsg list | |
| 1199 | − * | |
| 1200 | − * Take preprocessed SG list and write corresponding entries | |
| 1201 | − * in the IO PDIR. | |
| 1202 | − */ | |
| 1203 | − | |
| 1204 | −static SBA_INLINE int | |
| 1205 | −sba_fill_pdir( | |
| 1206 | − struct ioc *ioc, | |
| 1207 | − struct scatterlist *startsg, | |
| 1208 | − int nents) | |
| 1209 | −{ | |
| 1210 | − struct scatterlist *dma_sg = startsg; /* pointer to current DMA */ | |
| 1211 | − int n_mappings = 0; | |
| 1212 | − u64 *pdirp = NULL; | |
| 1213 | − unsigned long dma_offset = 0; | |
| 1214 | − | |
| 1215 | − while (nents-- > 0) { | |
| 1216 | − int cnt = startsg->dma_length; | |
| 1217 | − startsg->dma_length = 0; | |
| 1218 | − | |
| 1219 | −#ifdef DEBUG_LARGE_SG_ENTRIES | |
| 1220 | − if (dump_run_sg) | |
| 1221 | − printk(" %2d : %08lx/%05x %p\n", | |
| 1222 | − nents, startsg->dma_address, cnt, | |
| 1223 | − sba_sg_address(startsg)); | |
| 1224 | −#else | |
| 1225 | − DBG_RUN_SG(" %d : %08lx/%05x %p\n", | |
| 1226 | − nents, startsg->dma_address, cnt, | |
| 1227 | − sba_sg_address(startsg)); | |
| 1228 | −#endif | |
| 1229 | − /* | |
| 1230 | − ** Look for the start of a new DMA stream | |
| 1231 | − */ | |
| 1232 | − if (startsg->dma_address & PIDE_FLAG) { | |
| 1233 | − u32 pide = startsg->dma_address & ~PIDE_FLAG; | |
| 1234 | − dma_offset = (unsigned long) pide & ~iovp_mask; | |
| 1235 | − startsg->dma_address = 0; | |
| 1236 | − if (n_mappings) | |
| 1237 | − dma_sg = sg_next(dma_sg); | |
| 1238 | − dma_sg->dma_address = pide | ioc->ibase; | |
| 1239 | − pdirp = &(ioc->pdir_base[pide >> iovp_shift]); | |
| 1240 | − n_mappings++; | |
| 1241 | − } | |
| 1242 | − | |
| 1243 | − /* | |
| 1244 | − ** Look for a VCONTIG chunk | |
| 1245 | − */ | |
| 1246 | − if (cnt) { | |
| 1247 | − unsigned long vaddr = (unsigned long) sba_sg_address(startsg); | |
| 1248 | − ASSERT(pdirp); | |
| 1249 | − | |
| 1250 | − /* Since multiple Vcontig blocks could make up | |
| 1251 | − ** one DMA stream, *add* cnt to dma_len. | |
| 1252 | − */ | |
| 1253 | − dma_sg->dma_length += cnt; | |
| 1254 | − cnt += dma_offset; | |
| 1255 | − dma_offset=0; /* only want offset on first chunk */ | |
| 1256 | − cnt = ROUNDUP(cnt, iovp_size); | |
| 1257 | − do { | |
| 1258 | − sba_io_pdir_entry(pdirp, vaddr); | |
| 1259 | − vaddr += iovp_size; | |
| 1260 | − cnt -= iovp_size; | |
| 1261 | − pdirp++; | |
| 1262 | − } while (cnt > 0); | |
| 1263 | − } | |
| 1264 | − startsg = sg_next(startsg); | |
| 1265 | − } | |
| 1266 | − /* force pdir update */ | |
| 1267 | − wmb(); | |
| 1268 | − | |
| 1269 | −#ifdef DEBUG_LARGE_SG_ENTRIES | |
| 1270 | − dump_run_sg = 0; | |
| 1271 | −#endif | |
| 1272 | − return(n_mappings); | |
| 1273 | −} | |
| 1274 | − | |
| 1275 | − | |
| 1276 | −/* | |
| 1277 | −** Two address ranges are DMA contiguous *iff* "end of prev" and | |
| 1278 | −** "start of next" are both on an IOV page boundary. | |
| 1279 | −** | |
| 1280 | −** (shift left is a quick trick to mask off upper bits) | |
| 1281 | −*/ | |
| 1282 | −#define DMA_CONTIG(__X, __Y) \ | |
| 1283 | − (((((unsigned long) __X) | ((unsigned long) __Y)) << (BITS_PER_LONG - iovp_shift)) == 0UL) | |
| 1284 | − | |
| 1285 | − | |
| 1286 | −/** | |
| 1287 | − * sba_coalesce_chunks - preprocess the SG list | |
| 1288 | − * @ioc: IO MMU structure which owns the pdir we are interested in. | |
| 1289 | − * @startsg: list of IOVA/size pairs | |
| 1290 | − * @nents: number of entries in startsg list | |
| 1291 | − * | |
| 1292 | − * First pass is to walk the SG list and determine where the breaks are | |
| 1293 | − * in the DMA stream. Allocates PDIR entries but does not fill them. | |
| 1294 | − * Returns the number of DMA chunks. | |
| 1295 | − * | |
| 1296 | − * Doing the fill separate from the coalescing/allocation keeps the | |
| 1297 | − * code simpler. Future enhancement could make one pass through | |
| 1298 | − * the sglist do both. | |
| 1299 | − */ | |
| 1300 | −static SBA_INLINE int | |
| 1301 | −sba_coalesce_chunks(struct ioc *ioc, struct device *dev, | |
| 1302 | − struct scatterlist *startsg, | |
| 1303 | − int nents) | |
| 1304 | −{ | |
| 1305 | − struct scatterlist *vcontig_sg; /* VCONTIG chunk head */ | |
| 1306 | − unsigned long vcontig_len; /* len of VCONTIG chunk */ | |
| 1307 | − unsigned long vcontig_end; | |
| 1308 | − struct scatterlist *dma_sg; /* next DMA stream head */ | |
| 1309 | − unsigned long dma_offset, dma_len; /* start/len of DMA stream */ | |
| 1310 | − int n_mappings = 0; | |
| 1311 | − unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
| 1312 | − int idx; | |
| 1313 | − | |
| 1314 | − while (nents > 0) { | |
| 1315 | − unsigned long vaddr = (unsigned long) sba_sg_address(startsg); | |
| 1316 | − | |
| 1317 | − /* | |
| 1318 | − ** Prepare for first/next DMA stream | |
| 1319 | − */ | |
| 1320 | − dma_sg = vcontig_sg = startsg; | |
| 1321 | − dma_len = vcontig_len = vcontig_end = startsg->length; | |
| 1322 | − vcontig_end += vaddr; | |
| 1323 | − dma_offset = vaddr & ~iovp_mask; | |
| 1324 | − | |
| 1325 | − /* PARANOID: clear entries */ | |
| 1326 | − startsg->dma_address = startsg->dma_length = 0; | |
| 1327 | − | |
| 1328 | − /* | |
| 1329 | − ** This loop terminates one iteration "early" since | |
| 1330 | − ** it's always looking one "ahead". | |
| 1331 | − */ | |
| 1332 | − while (--nents > 0) { | |
| 1333 | − unsigned long vaddr; /* tmp */ | |
| 1334 | − | |
| 1335 | − startsg = sg_next(startsg); | |
| 1336 | − | |
| 1337 | − /* PARANOID */ | |
| 1338 | − startsg->dma_address = startsg->dma_length = 0; | |
| 1339 | − | |
| 1340 | − /* catch brokenness in SCSI layer */ | |
| 1341 | − ASSERT(startsg->length <= DMA_CHUNK_SIZE); | |
| 1342 | − | |
| 1343 | − /* | |
| 1344 | − ** First make sure current dma stream won't | |
| 1345 | − ** exceed DMA_CHUNK_SIZE if we coalesce the | |
| 1346 | − ** next entry. | |
| 1347 | − */ | |
| 1348 | − if (((dma_len + dma_offset + startsg->length + ~iovp_mask) & iovp_mask) | |
| 1349 | − > DMA_CHUNK_SIZE) | |
| 1350 | − break; | |
| 1351 | − | |
| 1352 | − if (dma_len + startsg->length > max_seg_size) | |
| 1353 | − break; | |
| 1354 | − | |
| 1355 | − /* | |
| 1356 | − ** Then look for virtually contiguous blocks. | |
| 1357 | − ** | |
| 1358 | − ** append the next transaction? | |
| 1359 | − */ | |
| 1360 | − vaddr = (unsigned long) sba_sg_address(startsg); | |
| 1361 | − if (vcontig_end == vaddr) | |
| 1362 | − { | |
| 1363 | − vcontig_len += startsg->length; | |
| 1364 | − vcontig_end += startsg->length; | |
| 1365 | − dma_len += startsg->length; | |
| 1366 | − continue; | |
| 1367 | − } | |
| 1368 | − | |
| 1369 | −#ifdef DEBUG_LARGE_SG_ENTRIES | |
| 1370 | − dump_run_sg = (vcontig_len > iovp_size); | |
| 1371 | −#endif | |
| 1372 | − | |
| 1373 | − /* | |
| 1374 | − ** Not virtually contiguous. | |
| 1375 | − ** Terminate prev chunk. | |
| 1376 | − ** Start a new chunk. | |
| 1377 | − ** | |
| 1378 | − ** Once we start a new VCONTIG chunk, dma_offset | |
| 1379 | − ** can't change. And we need the offset from the first | |
| 1380 | − ** chunk - not the last one. Ergo Successive chunks | |
| 1381 | − ** must start on page boundaries and dove tail | |
| 1382 | − ** with it's predecessor. | |
| 1383 | − */ | |
| 1384 | − vcontig_sg->dma_length = vcontig_len; | |
| 1385 | − | |
| 1386 | − vcontig_sg = startsg; | |
| 1387 | − vcontig_len = startsg->length; | |
| 1388 | − | |
| 1389 | − /* | |
| 1390 | − ** 3) do the entries end/start on page boundaries? | |
| 1391 | − ** Don't update vcontig_end until we've checked. | |
| 1392 | − */ | |
| 1393 | − if (DMA_CONTIG(vcontig_end, vaddr)) | |
| 1394 | − { | |
| 1395 | − vcontig_end = vcontig_len + vaddr; | |
| 1396 | − dma_len += vcontig_len; | |
| 1397 | − continue; | |
| 1398 | − } else { | |
| 1399 | − break; | |
| 1400 | − } | |
| 1401 | − } | |
| 1402 | − | |
| 1403 | − /* | |
| 1404 | − ** End of DMA Stream | |
| 1405 | − ** Terminate last VCONTIG block. | |
| 1406 | − ** Allocate space for DMA stream. | |
| 1407 | − */ | |
| 1408 | − vcontig_sg->dma_length = vcontig_len; | |
| 1409 | − dma_len = (dma_len + dma_offset + ~iovp_mask) & iovp_mask; | |
| 1410 | − ASSERT(dma_len <= DMA_CHUNK_SIZE); | |
| 1411 | − idx = sba_alloc_range(ioc, dev, dma_len); | |
| 1412 | − if (idx < 0) { | |
| 1413 | − dma_sg->dma_length = 0; | |
| 1414 | − return -1; | |
| 1415 | − } | |
| 1416 | − dma_sg->dma_address = (dma_addr_t)(PIDE_FLAG | (idx << iovp_shift) | |
| 1417 | − | dma_offset); | |
| 1418 | − n_mappings++; | |
| 1419 | − } | |
| 1420 | − | |
| 1421 | − return n_mappings; | |
| 1422 | −} | |
| 1423 | − | |
| 1424 | −static void sba_unmap_sg_attrs(struct device *dev, struct scatterlist *sglist, | |
| 1425 | − int nents, enum dma_data_direction dir, | |
| 1426 | − unsigned long attrs); | |
| 1427 | −/** | |
| 1428 | − * sba_map_sg - map Scatter/Gather list | |
| 1429 | − * @dev: instance of PCI owned by the driver that's asking. | |
| 1430 | − * @sglist: array of buffer/length pairs | |
| 1431 | − * @nents: number of entries in list | |
| 1432 | − * @dir: R/W or both. | |
| 1433 | − * @attrs: optional dma attributes | |
| 1434 | − * | |
| 1435 | − * See Documentation/core-api/dma-api-howto.rst | |
| 1436 | − */ | |
| 1437 | −static int sba_map_sg_attrs(struct device *dev, struct scatterlist *sglist, | |
| 1438 | − int nents, enum dma_data_direction dir, | |
| 1439 | − unsigned long attrs) | |
| 1440 | −{ | |
| 1441 | − struct ioc *ioc; | |
| 1442 | − int coalesced, filled = 0; | |
| 1443 | −#ifdef ASSERT_PDIR_SANITY | |
| 1444 | − unsigned long flags; | |
| 1445 | −#endif | |
| 1446 | −#ifdef ALLOW_IOV_BYPASS_SG | |
| 1447 | − struct scatterlist *sg; | |
| 1448 | −#endif | |
| 1449 | − | |
| 1450 | − DBG_RUN_SG("%s() START %d entries\n", __func__, nents); | |
| 1451 | − ioc = GET_IOC(dev); | |
| 1452 | − ASSERT(ioc); | |
| 1453 | − | |
| 1454 | −#ifdef ALLOW_IOV_BYPASS_SG | |
| 1455 | − ASSERT(to_pci_dev(dev)->dma_mask); | |
| 1456 | − if (likely((ioc->dma_mask & ~to_pci_dev(dev)->dma_mask) == 0)) { | |
| 1457 | − for_each_sg(sglist, sg, nents, filled) { | |
| 1458 | − sg->dma_length = sg->length; | |
| 1459 | − sg->dma_address = virt_to_phys(sba_sg_address(sg)); | |
| 1460 | − } | |
| 1461 | − return filled; | |
| 1462 | − } | |
| 1463 | −#endif | |
| 1464 | − /* Fast path single entry scatterlists. */ | |
| 1465 | − if (nents == 1) { | |
| 1466 | − sglist->dma_length = sglist->length; | |
| 1467 | − sglist->dma_address = sba_map_page(dev, sg_page(sglist), | |
| 1468 | − sglist->offset, sglist->length, dir, attrs); | |
| 1469 | − if (dma_mapping_error(dev, sglist->dma_address)) | |
| 1470 | − return -EIO; | |
| 1471 | − return 1; | |
| 1472 | − } | |
| 1473 | − | |
| 1474 | −#ifdef ASSERT_PDIR_SANITY | |
| 1475 | − spin_lock_irqsave(&ioc->res_lock, flags); | |
| 1476 | − if (sba_check_pdir(ioc,"Check before sba_map_sg_attrs()")) | |
| 1477 | − { | |
| 1478 | − sba_dump_sg(ioc, sglist, nents); | |
| 1479 | − panic("Check before sba_map_sg_attrs()"); | |
| 1480 | − } | |
| 1481 | − spin_unlock_irqrestore(&ioc->res_lock, flags); | |
| 1482 | −#endif | |
| 1483 | − | |
| 1484 | − prefetch(ioc->res_hint); | |
| 1485 | − | |
| 1486 | − /* | |
| 1487 | − ** First coalesce the chunks and allocate I/O pdir space | |
| 1488 | − ** | |
| 1489 | − ** If this is one DMA stream, we can properly map using the | |
| 1490 | − ** correct virtual address associated with each DMA page. | |
| 1491 | − ** w/o this association, we wouldn't have coherent DMA! | |
| 1492 | − ** Access to the virtual address is what forces a two pass algorithm. | |
| 1493 | − */ | |
| 1494 | − coalesced = sba_coalesce_chunks(ioc, dev, sglist, nents); | |
| 1495 | − if (coalesced < 0) { | |
| 1496 | − sba_unmap_sg_attrs(dev, sglist, nents, dir, attrs); | |
| 1497 | − return -ENOMEM; | |
| 1498 | − } | |
| 1499 | − | |
| 1500 | − /* | |
| 1501 | − ** Program the I/O Pdir | |
| 1502 | − ** | |
| 1503 | − ** map the virtual addresses to the I/O Pdir | |
| 1504 | − ** o dma_address will contain the pdir index | |
| 1505 | − ** o dma_len will contain the number of bytes to map | |
| 1506 | − ** o address contains the virtual address. | |
| 1507 | − */ | |
| 1508 | − filled = sba_fill_pdir(ioc, sglist, nents); | |
| 1509 | − | |
| 1510 | −#ifdef ASSERT_PDIR_SANITY | |
| 1511 | − spin_lock_irqsave(&ioc->res_lock, flags); | |
| 1512 | − if (sba_check_pdir(ioc,"Check after sba_map_sg_attrs()")) | |
| 1513 | − { | |
| 1514 | − sba_dump_sg(ioc, sglist, nents); | |
| 1515 | − panic("Check after sba_map_sg_attrs()\n"); | |
| 1516 | − } | |
| 1517 | − spin_unlock_irqrestore(&ioc->res_lock, flags); | |
| 1518 | −#endif | |
| 1519 | − | |
| 1520 | − ASSERT(coalesced == filled); | |
| 1521 | − DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled); | |
| 1522 | − | |
| 1523 | − return filled; | |
| 1524 | −} | |
| 1525 | − | |
| 1526 | −/** | |
| 1527 | − * sba_unmap_sg_attrs - unmap Scatter/Gather list | |
| 1528 | − * @dev: instance of PCI owned by the driver that's asking. | |
| 1529 | − * @sglist: array of buffer/length pairs | |
| 1530 | − * @nents: number of entries in list | |
| 1531 | − * @dir: R/W or both. | |
| 1532 | − * @attrs: optional dma attributes | |
| 1533 | − * | |
| 1534 | − * See Documentation/core-api/dma-api-howto.rst | |
| 1535 | − */ | |
| 1536 | −static void sba_unmap_sg_attrs(struct device *dev, struct scatterlist *sglist, | |
| 1537 | − int nents, enum dma_data_direction dir, | |
| 1538 | − unsigned long attrs) | |
| 1539 | −{ | |
| 1540 | −#ifdef ASSERT_PDIR_SANITY | |
| 1541 | − struct ioc *ioc; | |
| 1542 | − unsigned long flags; | |
| 1543 | −#endif | |
| 1544 | − | |
| 1545 | − DBG_RUN_SG("%s() START %d entries, %p,%x\n", | |
| 1546 | − __func__, nents, sba_sg_address(sglist), sglist->length); | |
| 1547 | − | |
| 1548 | −#ifdef ASSERT_PDIR_SANITY | |
| 1549 | − ioc = GET_IOC(dev); | |
| 1550 | − ASSERT(ioc); | |
| 1551 | − | |
| 1552 | − spin_lock_irqsave(&ioc->res_lock, flags); | |
| 1553 | − sba_check_pdir(ioc,"Check before sba_unmap_sg_attrs()"); | |
| 1554 | − spin_unlock_irqrestore(&ioc->res_lock, flags); | |
| 1555 | −#endif | |
| 1556 | − | |
| 1557 | − while (nents && sglist->dma_length) { | |
| 1558 | − | |
| 1559 | − sba_unmap_page(dev, sglist->dma_address, sglist->dma_length, | |
| 1560 | − dir, attrs); | |
| 1561 | − sglist = sg_next(sglist); | |
| 1562 | − nents--; | |
| 1563 | − } | |
| 1564 | − | |
| 1565 | − DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents); | |
| 1566 | − | |
| 1567 | −#ifdef ASSERT_PDIR_SANITY | |
| 1568 | − spin_lock_irqsave(&ioc->res_lock, flags); | |
| 1569 | − sba_check_pdir(ioc,"Check after sba_unmap_sg_attrs()"); | |
| 1570 | − spin_unlock_irqrestore(&ioc->res_lock, flags); | |
| 1571 | −#endif | |
| 1572 | − | |
| 1573 | −} | |
| 1574 | − | |
| 1575 | −/************************************************************** | |
| 1576 | −* | |
| 1577 | −* Initialization and claim | |
| 1578 | −* | |
| 1579 | −***************************************************************/ | |
| 1580 | − | |
| 1581 | −static void | |
| 1582 | −ioc_iova_init(struct ioc *ioc) | |
| 1583 | −{ | |
| 1584 | − int tcnfg; | |
| 1585 | − int agp_found = 0; | |
| 1586 | − struct pci_dev *device = NULL; | |
| 1587 | −#ifdef FULL_VALID_PDIR | |
| 1588 | − unsigned long index; | |
| 1589 | −#endif | |
| 1590 | − | |
| 1591 | − /* | |
| 1592 | − ** Firmware programs the base and size of a "safe IOVA space" | |
| 1593 | − ** (one that doesn't overlap memory or LMMIO space) in the | |
| 1594 | − ** IBASE and IMASK registers. | |
| 1595 | − */ | |
| 1596 | − ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE) & ~0x1UL; | |
| 1597 | − ioc->imask = READ_REG(ioc->ioc_hpa + IOC_IMASK) | 0xFFFFFFFF00000000UL; | |
| 1598 | − | |
| 1599 | − ioc->iov_size = ~ioc->imask + 1; | |
| 1600 | − | |
| 1601 | − DBG_INIT("%s() hpa %p IOV base 0x%lx mask 0x%lx (%dMB)\n", | |
| 1602 | − __func__, ioc->ioc_hpa, ioc->ibase, ioc->imask, | |
| 1603 | − ioc->iov_size >> 20); | |
| 1604 | − | |
| 1605 | − switch (iovp_size) { | |
| 1606 | − case 4*1024: tcnfg = 0; break; | |
| 1607 | − case 8*1024: tcnfg = 1; break; | |
| 1608 | − case 16*1024: tcnfg = 2; break; | |
| 1609 | − case 64*1024: tcnfg = 3; break; | |
| 1610 | − default: | |
| 1611 | − panic(PFX "Unsupported IOTLB page size %ldK", | |
| 1612 | − iovp_size >> 10); | |
| 1613 | − break; | |
| 1614 | − } | |
| 1615 | − WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG); | |
| 1616 | − | |
| 1617 | − ioc->pdir_size = (ioc->iov_size / iovp_size) * PDIR_ENTRY_SIZE; | |
| 1618 | − ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL, | |
| 1619 | − get_order(ioc->pdir_size)); | |
| 1620 | − if (!ioc->pdir_base) | |
| 1621 | − panic(PFX "Couldn't allocate I/O Page Table\n"); | |
| 1622 | − | |
| 1623 | − memset(ioc->pdir_base, 0, ioc->pdir_size); | |
| 1624 | − | |
| 1625 | − DBG_INIT("%s() IOV page size %ldK pdir %p size %x\n", __func__, | |
| 1626 | − iovp_size >> 10, ioc->pdir_base, ioc->pdir_size); | |
| 1627 | − | |
| 1628 | − ASSERT(ALIGN((unsigned long) ioc->pdir_base, 4*1024) == (unsigned long) ioc->pdir_base); | |
| 1629 | − WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); | |
| 1630 | − | |
| 1631 | − /* | |
| 1632 | − ** If an AGP device is present, only use half of the IOV space | |
| 1633 | − ** for PCI DMA. Unfortunately we can't know ahead of time | |
| 1634 | − ** whether GART support will actually be used, for now we | |
| 1635 | − ** can just key on an AGP device found in the system. | |
| 1636 | − ** We program the next pdir index after we stop w/ a key for | |
| 1637 | − ** the GART code to handshake on. | |
| 1638 | − */ | |
| 1639 | − for_each_pci_dev(device) | |
| 1640 | − agp_found |= pci_find_capability(device, PCI_CAP_ID_AGP); | |
| 1641 | − | |
| 1642 | − if (agp_found && reserve_sba_gart) { | |
| 1643 | − printk(KERN_INFO PFX "reserving %dMb of IOVA space at 0x%lx for agpgart\n", | |
| 1644 | − ioc->iov_size/2 >> 20, ioc->ibase + ioc->iov_size/2); | |
| 1645 | − ioc->pdir_size /= 2; | |
| 1646 | − ((u64 *)ioc->pdir_base)[PDIR_INDEX(ioc->iov_size/2)] = ZX1_SBA_IOMMU_COOKIE; | |
| 1647 | − } | |
| 1648 | −#ifdef FULL_VALID_PDIR | |
| 1649 | − /* | |
| 1650 | − ** Check to see if the spill page has been allocated, we don't need more than | |
| 1651 | − ** one across multiple SBAs. | |
| 1652 | − */ | |
| 1653 | − if (!prefetch_spill_page) { | |
| 1654 | − char *spill_poison = "SBAIOMMU POISON"; | |
| 1655 | − int poison_size = 16; | |
| 1656 | − void *poison_addr, *addr; | |
| 1657 | − | |
| 1658 | − addr = (void *)__get_free_pages(GFP_KERNEL, get_order(iovp_size)); | |
| 1659 | − if (!addr) | |
| 1660 | − panic(PFX "Couldn't allocate PDIR spill page\n"); | |
| 1661 | − | |
| 1662 | − poison_addr = addr; | |
| 1663 | − for ( ; (u64) poison_addr < addr + iovp_size; poison_addr += poison_size) | |
| 1664 | − memcpy(poison_addr, spill_poison, poison_size); | |
| 1665 | − | |
| 1666 | − prefetch_spill_page = virt_to_phys(addr); | |
| 1667 | − | |
| 1668 | − DBG_INIT("%s() prefetch spill addr: 0x%lx\n", __func__, prefetch_spill_page); | |
| 1669 | − } | |
| 1670 | − /* | |
| 1671 | − ** Set all the PDIR entries valid w/ the spill page as the target | |
| 1672 | − */ | |
| 1673 | − for (index = 0 ; index < (ioc->pdir_size / PDIR_ENTRY_SIZE) ; index++) | |
| 1674 | − ((u64 *)ioc->pdir_base)[index] = (0x80000000000000FF | prefetch_spill_page); | |
| 1675 | −#endif | |
| 1676 | − | |
| 1677 | − /* Clear I/O TLB of any possible entries */ | |
| 1678 | − WRITE_REG(ioc->ibase | (get_iovp_order(ioc->iov_size) + iovp_shift), ioc->ioc_hpa + IOC_PCOM); | |
| 1679 | − READ_REG(ioc->ioc_hpa + IOC_PCOM); | |
| 1680 | − | |
| 1681 | − /* Enable IOVA translation */ | |
| 1682 | − WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE); | |
| 1683 | − READ_REG(ioc->ioc_hpa + IOC_IBASE); | |
| 1684 | −} | |
| 1685 | − | |
| 1686 | −static void __init | |
| 1687 | −ioc_resource_init(struct ioc *ioc) | |
| 1688 | −{ | |
| 1689 | − spin_lock_init(&ioc->res_lock); | |
| 1690 | −#if DELAYED_RESOURCE_CNT > 0 | |
| 1691 | − spin_lock_init(&ioc->saved_lock); | |
| 1692 | −#endif | |
| 1693 | − | |
| 1694 | − /* resource map size dictated by pdir_size */ | |
| 1695 | − ioc->res_size = ioc->pdir_size / PDIR_ENTRY_SIZE; /* entries */ | |
| 1696 | − ioc->res_size >>= 3; /* convert bit count to byte count */ | |
| 1697 | − DBG_INIT("%s() res_size 0x%x\n", __func__, ioc->res_size); | |
| 1698 | − | |
| 1699 | − ioc->res_map = (char *) __get_free_pages(GFP_KERNEL, | |
| 1700 | − get_order(ioc->res_size)); | |
| 1701 | − if (!ioc->res_map) | |
| 1702 | − panic(PFX "Couldn't allocate resource map\n"); | |
| 1703 | − | |
| 1704 | − memset(ioc->res_map, 0, ioc->res_size); | |
| 1705 | − /* next available IOVP - circular search */ | |
| 1706 | − ioc->res_hint = (unsigned long *) ioc->res_map; | |
| 1707 | − | |
| 1708 | −#ifdef ASSERT_PDIR_SANITY | |
| 1709 | − /* Mark first bit busy - ie no IOVA 0 */ | |
| 1710 | − ioc->res_map[0] = 0x1; | |
| 1711 | − ioc->pdir_base[0] = 0x8000000000000000ULL | ZX1_SBA_IOMMU_COOKIE; | |
| 1712 | −#endif | |
| 1713 | −#ifdef FULL_VALID_PDIR | |
| 1714 | − /* Mark the last resource used so we don't prefetch beyond IOVA space */ | |
| 1715 | − ioc->res_map[ioc->res_size - 1] |= 0x80UL; /* res_map is chars */ | |
| 1716 | − ioc->pdir_base[(ioc->pdir_size / PDIR_ENTRY_SIZE) - 1] = (0x80000000000000FF | |
| 1717 | − | prefetch_spill_page); | |
| 1718 | −#endif | |
| 1719 | − | |
| 1720 | − DBG_INIT("%s() res_map %x %p\n", __func__, | |
| 1721 | − ioc->res_size, (void *) ioc->res_map); | |
| 1722 | −} | |
| 1723 | − | |
| 1724 | −static void __init | |
| 1725 | −ioc_sac_init(struct ioc *ioc) | |
| 1726 | −{ | |
| 1727 | − struct pci_dev *sac = NULL; | |
| 1728 | − struct pci_controller *controller = NULL; | |
| 1729 | − | |
| 1730 | − /* | |
| 1731 | − * pci_alloc_coherent() must return a DMA address which is | |
| 1732 | − * SAC (single address cycle) addressable, so allocate a | |
| 1733 | − * pseudo-device to enforce that. | |
| 1734 | − */ | |
| 1735 | − sac = kzalloc(sizeof(*sac), GFP_KERNEL); | |
| 1736 | − if (!sac) | |
| 1737 | − panic(PFX "Couldn't allocate struct pci_dev"); | |
| 1738 | − | |
| 1739 | − controller = kzalloc(sizeof(*controller), GFP_KERNEL); | |
| 1740 | − if (!controller) | |
| 1741 | − panic(PFX "Couldn't allocate struct pci_controller"); | |
| 1742 | − | |
| 1743 | − controller->iommu = ioc; | |
| 1744 | − sac->sysdata = controller; | |
| 1745 | − sac->dma_mask = 0xFFFFFFFFUL; | |
| 1746 | − sac->dev.bus = &pci_bus_type; | |
| 1747 | − ioc->sac_only_dev = sac; | |
| 1748 | −} | |
| 1749 | − | |
| 1750 | −static void __init | |
| 1751 | −ioc_zx1_init(struct ioc *ioc) | |
| 1752 | −{ | |
| 1753 | − unsigned long rope_config; | |
| 1754 | − unsigned int i; | |
| 1755 | − | |
| 1756 | − if (ioc->rev < 0x20) | |
| 1757 | − panic(PFX "IOC 2.0 or later required for IOMMU support\n"); | |
| 1758 | − | |
| 1759 | − /* 38 bit memory controller + extra bit for range displaced by MMIO */ | |
| 1760 | − ioc->dma_mask = (0x1UL << 39) - 1; | |
| 1761 | − | |
| 1762 | − /* | |
| 1763 | − ** Clear ROPE(N)_CONFIG AO bit. | |
| 1764 | − ** Disables "NT Ordering" (~= !"Relaxed Ordering") | |
| 1765 | − ** Overrides bit 1 in DMA Hint Sets. | |
| 1766 | − ** Improves netperf UDP_STREAM by ~10% for tg3 on bcm5701. | |
| 1767 | − */ | |
| 1768 | − for (i=0; i<(8*8); i+=8) { | |
| 1769 | − rope_config = READ_REG(ioc->ioc_hpa + IOC_ROPE0_CFG + i); | |
| 1770 | − rope_config &= ~IOC_ROPE_AO; | |
| 1771 | − WRITE_REG(rope_config, ioc->ioc_hpa + IOC_ROPE0_CFG + i); | |
| 1772 | − } | |
| 1773 | −} | |
| 1774 | − | |
| 1775 | −typedef void (initfunc)(struct ioc *); | |
| 1776 | − | |
| 1777 | −struct ioc_iommu { | |
| 1778 | − u32 func_id; | |
| 1779 | − char *name; | |
| 1780 | − initfunc *init; | |
| 1781 | −}; | |
| 1782 | − | |
| 1783 | −static struct ioc_iommu ioc_iommu_info[] __initdata = { | |
| 1784 | − { ZX1_IOC_ID, "zx1", ioc_zx1_init }, | |
| 1785 | − { ZX2_IOC_ID, "zx2", NULL }, | |
| 1786 | − { SX1000_IOC_ID, "sx1000", NULL }, | |
| 1787 | − { SX2000_IOC_ID, "sx2000", NULL }, | |
| 1788 | −}; | |
| 1789 | − | |
| 1790 | −static void __init ioc_init(unsigned long hpa, struct ioc *ioc) | |
| 1791 | −{ | |
| 1792 | − struct ioc_iommu *info; | |
| 1793 | − | |
| 1794 | − ioc->next = ioc_list; | |
| 1795 | − ioc_list = ioc; | |
| 1796 | − | |
| 1797 | − ioc->ioc_hpa = ioremap(hpa, 0x1000); | |
| 1798 | − | |
| 1799 | − ioc->func_id = READ_REG(ioc->ioc_hpa + IOC_FUNC_ID); | |
| 1800 | − ioc->rev = READ_REG(ioc->ioc_hpa + IOC_FCLASS) & 0xFFUL; | |
| 1801 | − ioc->dma_mask = 0xFFFFFFFFFFFFFFFFUL; /* conservative */ | |
| 1802 | − | |
| 1803 | − for (info = ioc_iommu_info; info < ioc_iommu_info + ARRAY_SIZE(ioc_iommu_info); info++) { | |
| 1804 | − if (ioc->func_id == info->func_id) { | |
| 1805 | − ioc->name = info->name; | |
| 1806 | − if (info->init) | |
| 1807 | − (info->init)(ioc); | |
| 1808 | − } | |
| 1809 | − } | |
| 1810 | − | |
| 1811 | − iovp_size = (1 << iovp_shift); | |
| 1812 | − iovp_mask = ~(iovp_size - 1); | |
| 1813 | − | |
| 1814 | − DBG_INIT("%s: PAGE_SIZE %ldK, iovp_size %ldK\n", __func__, | |
| 1815 | − PAGE_SIZE >> 10, iovp_size >> 10); | |
| 1816 | − | |
| 1817 | − if (!ioc->name) { | |
| 1818 | − ioc->name = kmalloc(24, GFP_KERNEL); | |
| 1819 | − if (ioc->name) | |
| 1820 | − sprintf((char *) ioc->name, "Unknown (%04x:%04x)", | |
| 1821 | − ioc->func_id & 0xFFFF, (ioc->func_id >> 16) & 0xFFFF); | |
| 1822 | − else | |
| 1823 | − ioc->name = "Unknown"; | |
| 1824 | − } | |
| 1825 | − | |
| 1826 | − ioc_iova_init(ioc); | |
| 1827 | − ioc_resource_init(ioc); | |
| 1828 | − ioc_sac_init(ioc); | |
| 1829 | − | |
| 1830 | − printk(KERN_INFO PFX | |
| 1831 | − "%s %d.%d HPA 0x%lx IOVA space %dMb at 0x%lx\n", | |
| 1832 | − ioc->name, (ioc->rev >> 4) & 0xF, ioc->rev & 0xF, | |
| 1833 | − hpa, ioc->iov_size >> 20, ioc->ibase); | |
| 1834 | −} | |
| 1835 | − | |
| 1836 | − | |
| 1837 | − | |
| 1838 | −/************************************************************************** | |
| 1839 | −** | |
| 1840 | −** SBA initialization code (HW and SW) | |
| 1841 | −** | |
| 1842 | −** o identify SBA chip itself | |
| 1843 | −** o FIXME: initialize DMA hints for reasonable defaults | |
| 1844 | −** | |
| 1845 | −**************************************************************************/ | |
| 1846 | − | |
| 1847 | −#ifdef CONFIG_PROC_FS | |
| 1848 | −static void * | |
| 1849 | −ioc_start(struct seq_file *s, loff_t *pos) | |
| 1850 | −{ | |
| 1851 | − struct ioc *ioc; | |
| 1852 | − loff_t n = *pos; | |
| 1853 | − | |
| 1854 | − for (ioc = ioc_list; ioc; ioc = ioc->next) | |
| 1855 | − if (!n--) | |
| 1856 | − return ioc; | |
| 1857 | − | |
| 1858 | − return NULL; | |
| 1859 | −} | |
| 1860 | − | |
| 1861 | −static void * | |
| 1862 | −ioc_next(struct seq_file *s, void *v, loff_t *pos) | |
| 1863 | −{ | |
| 1864 | − struct ioc *ioc = v; | |
| 1865 | − | |
| 1866 | − ++*pos; | |
| 1867 | − return ioc->next; | |
| 1868 | −} | |
| 1869 | − | |
| 1870 | −static void | |
| 1871 | −ioc_stop(struct seq_file *s, void *v) | |
| 1872 | −{ | |
| 1873 | −} | |
| 1874 | − | |
| 1875 | −static int | |
| 1876 | −ioc_show(struct seq_file *s, void *v) | |
| 1877 | −{ | |
| 1878 | − struct ioc *ioc = v; | |
| 1879 | − unsigned long *res_ptr = (unsigned long *)ioc->res_map; | |
| 1880 | − int i, used = 0; | |
| 1881 | − | |
| 1882 | − seq_printf(s, "Hewlett Packard %s IOC rev %d.%d\n", | |
| 1883 | − ioc->name, ((ioc->rev >> 4) & 0xF), (ioc->rev & 0xF)); | |
| 1884 | −#ifdef CONFIG_NUMA | |
| 1885 | − if (ioc->node != NUMA_NO_NODE) | |
| 1886 | − seq_printf(s, "NUMA node : %d\n", ioc->node); | |
| 1887 | −#endif | |
| 1888 | − seq_printf(s, "IOVA size : %ld MB\n", ((ioc->pdir_size >> 3) * iovp_size)/(1024*1024)); | |
| 1889 | − seq_printf(s, "IOVA page size : %ld kb\n", iovp_size/1024); | |
| 1890 | − | |
| 1891 | − for (i = 0; i < (ioc->res_size / sizeof(unsigned long)); ++i, ++res_ptr) | |
| 1892 | − used += hweight64(*res_ptr); | |
| 1893 | − | |
| 1894 | − seq_printf(s, "PDIR size : %d entries\n", ioc->pdir_size >> 3); | |
| 1895 | − seq_printf(s, "PDIR used : %d entries\n", used); | |
| 1896 | − | |
| 1897 | −#ifdef PDIR_SEARCH_TIMING | |
| 1898 | − { | |
| 1899 | − unsigned long i = 0, avg = 0, min, max; | |
| 1900 | − min = max = ioc->avg_search[0]; | |
| 1901 | − for (i = 0; i < SBA_SEARCH_SAMPLE; i++) { | |
| 1902 | − avg += ioc->avg_search[i]; | |
| 1903 | − if (ioc->avg_search[i] > max) max = ioc->avg_search[i]; | |
| 1904 | − if (ioc->avg_search[i] < min) min = ioc->avg_search[i]; | |
| 1905 | − } | |
| 1906 | − avg /= SBA_SEARCH_SAMPLE; | |
| 1907 | − seq_printf(s, "Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles/IOVA page)\n", | |
| 1908 | − min, avg, max); | |
| 1909 | − } | |
| 1910 | −#endif | |
| 1911 | −#ifndef ALLOW_IOV_BYPASS | |
| 1912 | − seq_printf(s, "IOVA bypass disabled\n"); | |
| 1913 | −#endif | |
| 1914 | − return 0; | |
| 1915 | −} | |
| 1916 | − | |
| 1917 | −static const struct seq_operations ioc_seq_ops = { | |
| 1918 | − .start = ioc_start, | |
| 1919 | − .next = ioc_next, | |
| 1920 | − .stop = ioc_stop, | |
| 1921 | − .show = ioc_show | |
| 1922 | −}; | |
| 1923 | − | |
| 1924 | −static void __init | |
| 1925 | −ioc_proc_init(void) | |
| 1926 | −{ | |
| 1927 | − struct proc_dir_entry *dir; | |
| 1928 | − | |
| 1929 | − dir = proc_mkdir("bus/mckinley", NULL); | |
| 1930 | − if (!dir) | |
| 1931 | − return; | |
| 1932 | − | |
| 1933 | − proc_create_seq(ioc_list->name, 0, dir, &ioc_seq_ops); | |
| 1934 | −} | |
| 1935 | −#endif | |
| 1936 | − | |
| 1937 | −static void | |
| 1938 | −sba_connect_bus(struct pci_bus *bus) | |
| 1939 | −{ | |
| 1940 | − acpi_handle handle, parent; | |
| 1941 | − acpi_status status; | |
| 1942 | − struct ioc *ioc; | |
| 1943 | − | |
| 1944 | − if (!PCI_CONTROLLER(bus)) | |
| 1945 | − panic(PFX "no sysdata on bus %d!\n", bus->number); | |
| 1946 | − | |
| 1947 | − if (PCI_CONTROLLER(bus)->iommu) | |
| 1948 | − return; | |
| 1949 | − | |
| 1950 | − handle = acpi_device_handle(PCI_CONTROLLER(bus)->companion); | |
| 1951 | − if (!handle) | |
| 1952 | − return; | |
| 1953 | − | |
| 1954 | − /* | |
| 1955 | − * The IOC scope encloses PCI root bridges in the ACPI | |
| 1956 | − * namespace, so work our way out until we find an IOC we | |
| 1957 | − * claimed previously. | |
| 1958 | − */ | |
| 1959 | − do { | |
| 1960 | − for (ioc = ioc_list; ioc; ioc = ioc->next) | |
| 1961 | − if (ioc->handle == handle) { | |
| 1962 | − PCI_CONTROLLER(bus)->iommu = ioc; | |
| 1963 | − return; | |
| 1964 | − } | |
| 1965 | − | |
| 1966 | − status = acpi_get_parent(handle, &parent); | |
| 1967 | − handle = parent; | |
| 1968 | − } while (ACPI_SUCCESS(status)); | |
| 1969 | − | |
| 1970 | − printk(KERN_WARNING "No IOC for PCI Bus %04x:%02x in ACPI\n", pci_domain_nr(bus), bus->number); | |
| 1971 | −} | |
| 1972 | − | |
| 1973 | −static void __init | |
| 1974 | −sba_map_ioc_to_node(struct ioc *ioc, acpi_handle handle) | |
| 1975 | −{ | |
| 1976 | −#ifdef CONFIG_NUMA | |
| 1977 | − unsigned int node; | |
| 1978 | − | |
| 1979 | − node = acpi_get_node(handle); | |
| 1980 | − if (node != NUMA_NO_NODE && !node_online(node)) | |
| 1981 | − node = NUMA_NO_NODE; | |
| 1982 | − | |
| 1983 | − ioc->node = node; | |
| 1984 | −#endif | |
| 1985 | −} | |
| 1986 | − | |
| 1987 | −static void __init acpi_sba_ioc_add(struct ioc *ioc) | |
| 1988 | −{ | |
| 1989 | − acpi_handle handle = ioc->handle; | |
| 1990 | − acpi_status status; | |
| 1991 | − u64 hpa, length; | |
| 1992 | − struct acpi_device_info *adi; | |
| 1993 | − | |
| 1994 | − ioc_found = ioc->next; | |
| 1995 | − status = hp_acpi_csr_space(handle, &hpa, &length); | |
| 1996 | − if (ACPI_FAILURE(status)) | |
| 1997 | − goto err; | |
| 1998 | − | |
| 1999 | − status = acpi_get_object_info(handle, &adi); | |
| 2000 | − if (ACPI_FAILURE(status)) | |
| 2001 | − goto err; | |
| 2002 | − | |
| 2003 | − /* | |
| 2004 | − * For HWP0001, only SBA appears in ACPI namespace. It encloses the PCI | |
| 2005 | − * root bridges, and its CSR space includes the IOC function. | |
| 2006 | − */ | |
| 2007 | − if (strncmp("HWP0001", adi->hardware_id.string, 7) == 0) { | |
| 2008 | − hpa += ZX1_IOC_OFFSET; | |
| 2009 | − /* zx1 based systems default to kernel page size iommu pages */ | |
| 2010 | − if (!iovp_shift) | |
| 2011 | − iovp_shift = min(PAGE_SHIFT, 16); | |
| 2012 | − } | |
| 2013 | − kfree(adi); | |
| 2014 | − | |
| 2015 | − /* | |
| 2016 | − * default anything not caught above or specified on cmdline to 4k | |
| 2017 | − * iommu page size | |
| 2018 | − */ | |
| 2019 | − if (!iovp_shift) | |
| 2020 | − iovp_shift = 12; | |
| 2021 | − | |
| 2022 | − ioc_init(hpa, ioc); | |
| 2023 | − /* setup NUMA node association */ | |
| 2024 | − sba_map_ioc_to_node(ioc, handle); | |
| 2025 | − return; | |
| 2026 | − | |
| 2027 | − err: | |
| 2028 | − kfree(ioc); | |
| 2029 | −} | |
| 2030 | − | |
| 2031 | −static const struct acpi_device_id hp_ioc_iommu_device_ids[] = { | |
| 2032 | − {"HWP0001", 0}, | |
| 2033 | − {"HWP0004", 0}, | |
| 2034 | − {"", 0}, | |
| 2035 | −}; | |
| 2036 | − | |
| 2037 | −static int acpi_sba_ioc_attach(struct acpi_device *device, | |
| 2038 | − const struct acpi_device_id *not_used) | |
| 2039 | −{ | |
| 2040 | − struct ioc *ioc; | |
| 2041 | − | |
| 2042 | − ioc = kzalloc(sizeof(*ioc), GFP_KERNEL); | |
| 2043 | − if (!ioc) | |
| 2044 | − return -ENOMEM; | |
| 2045 | − | |
| 2046 | − ioc->next = ioc_found; | |
| 2047 | − ioc_found = ioc; | |
| 2048 | − ioc->handle = device->handle; | |
| 2049 | − return 1; | |
| 2050 | −} | |
| 2051 | − | |
| 2052 | − | |
| 2053 | −static struct acpi_scan_handler acpi_sba_ioc_handler = { | |
| 2054 | − .ids = hp_ioc_iommu_device_ids, | |
| 2055 | − .attach = acpi_sba_ioc_attach, | |
| 2056 | −}; | |
| 2057 | − | |
| 2058 | −static int __init acpi_sba_ioc_init_acpi(void) | |
| 2059 | −{ | |
| 2060 | − return acpi_scan_add_handler(&acpi_sba_ioc_handler); | |
| 2061 | −} | |
| 2062 | −/* This has to run before acpi_scan_init(). */ | |
| 2063 | −arch_initcall(acpi_sba_ioc_init_acpi); | |
| 2064 | − | |
| 2065 | −static int sba_dma_supported (struct device *dev, u64 mask) | |
| 2066 | −{ | |
| 2067 | − /* make sure it's at least 32bit capable */ | |
| 2068 | − return ((mask & 0xFFFFFFFFUL) == 0xFFFFFFFFUL); | |
| 2069 | −} | |
| 2070 | − | |
| 2071 | −static const struct dma_map_ops sba_dma_ops = { | |
| 2072 | − .alloc = sba_alloc_coherent, | |
| 2073 | − .free = sba_free_coherent, | |
| 2074 | − .map_page = sba_map_page, | |
| 2075 | − .unmap_page = sba_unmap_page, | |
| 2076 | − .map_sg = sba_map_sg_attrs, | |
| 2077 | − .unmap_sg = sba_unmap_sg_attrs, | |
| 2078 | − .dma_supported = sba_dma_supported, | |
| 2079 | − .mmap = dma_common_mmap, | |
| 2080 | − .get_sgtable = dma_common_get_sgtable, | |
| 2081 | − .alloc_pages = dma_common_alloc_pages, | |
| 2082 | − .free_pages = dma_common_free_pages, | |
| 2083 | −}; | |
| 2084 | − | |
| 2085 | −static int __init | |
| 2086 | −sba_init(void) | |
| 2087 | −{ | |
| 2088 | − /* | |
| 2089 | − * If we are booting a kdump kernel, the sba_iommu will cause devices | |
| 2090 | − * that were not shutdown properly to MCA as soon as they are turned | |
| 2091 | − * back on. Our only option for a successful kdump kernel boot is to | |
| 2092 | − * use swiotlb. | |
| 2093 | − */ | |
| 2094 | − if (is_kdump_kernel()) | |
| 2095 | − return 0; | |
| 2096 | − | |
| 2097 | − /* | |
| 2098 | − * ioc_found should be populated by the acpi_sba_ioc_handler's .attach() | |
| 2099 | − * routine, but that only happens if acpi_scan_init() has already run. | |
| 2100 | − */ | |
| 2101 | − while (ioc_found) | |
| 2102 | − acpi_sba_ioc_add(ioc_found); | |
| 2103 | − | |
| 2104 | − if (!ioc_list) | |
| 2105 | − return 0; | |
| 2106 | − | |
| 2107 | − { | |
| 2108 | − struct pci_bus *b = NULL; | |
| 2109 | − while ((b = pci_find_next_bus(b)) != NULL) | |
| 2110 | − sba_connect_bus(b); | |
| 2111 | − } | |
| 2112 | − | |
| 2113 | − /* no need for swiotlb with the iommu */ | |
| 2114 | − swiotlb_exit(); | |
| 2115 | − dma_ops = &sba_dma_ops; | |
| 2116 | − | |
| 2117 | −#ifdef CONFIG_PROC_FS | |
| 2118 | − ioc_proc_init(); | |
| 2119 | −#endif | |
| 2120 | − return 0; | |
| 2121 | −} | |
| 2122 | − | |
| 2123 | −subsys_initcall(sba_init); /* must be initialized after ACPI etc., but before any drivers... */ | |
| 2124 | − | |
| 2125 | −static int __init | |
| 2126 | −nosbagart(char *str) | |
| 2127 | −{ | |
| 2128 | − reserve_sba_gart = 0; | |
| 2129 | − return 1; | |
| 2130 | −} | |
| 2131 | − | |
| 2132 | −__setup("nosbagart", nosbagart); | |
| 2133 | − | |
| 2134 | −static int __init | |
| 2135 | −sba_page_override(char *str) | |
| 2136 | −{ | |
| 2137 | − unsigned long page_size; | |
| 2138 | − | |
| 2139 | − page_size = memparse(str, &str); | |
| 2140 | − switch (page_size) { | |
| 2141 | − case 4096: | |
| 2142 | − case 8192: | |
| 2143 | − case 16384: | |
| 2144 | − case 65536: | |
| 2145 | − iovp_shift = ffs(page_size) - 1; | |
| 2146 | − break; | |
| 2147 | − default: | |
| 2148 | − printk("%s: unknown/unsupported iommu page size %ld\n", | |
| 2149 | − __func__, page_size); | |
| 2150 | − } | |
| 2151 | − | |
| 2152 | − return 1; | |
| 2153 | −} | |
| 2154 | − | |
| 2155 | −__setup("sbapagesize=",sba_page_override); | |
| @@ -1,6 +0,0 @@ | ||
| 1 | −# SPDX-License-Identifier: GPL-2.0 | |
| 2 | −generated-y += syscall_table.h | |
| 3 | −generic-y += agp.h | |
| 4 | −generic-y += kvm_para.h | |
| 5 | −generic-y += mcs_spinlock.h | |
| 6 | −generic-y += vtime.h | |
| @@ -1,49 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0-only */ | |
| 2 | −/* | |
| 3 | − * IA64 specific ACPICA environments and implementation | |
| 4 | − * | |
| 5 | − * Copyright (C) 2014, Intel Corporation | |
| 6 | − * Author: Lv Zheng <lv.zheng@intel.com> | |
| 7 | − */ | |
| 8 | − | |
| 9 | −#ifndef _ASM_IA64_ACENV_H | |
| 10 | −#define _ASM_IA64_ACENV_H | |
| 11 | − | |
| 12 | −#include <asm/intrinsics.h> | |
| 13 | − | |
| 14 | −#define COMPILER_DEPENDENT_INT64 long | |
| 15 | −#define COMPILER_DEPENDENT_UINT64 unsigned long | |
| 16 | − | |
| 17 | −/* Asm macros */ | |
| 18 | − | |
| 19 | −static inline int | |
| 20 | −ia64_acpi_acquire_global_lock(unsigned int *lock) | |
| 21 | −{ | |
| 22 | − unsigned int old, new, val; | |
| 23 | − do { | |
| 24 | − old = *lock; | |
| 25 | − new = (((old & ~0x3) + 2) + ((old >> 1) & 0x1)); | |
| 26 | − val = ia64_cmpxchg4_acq(lock, new, old); | |
| 27 | − } while (unlikely (val != old)); | |
| 28 | − return (new < 3) ? -1 : 0; | |
| 29 | −} | |
| 30 | − | |
| 31 | −static inline int | |
| 32 | −ia64_acpi_release_global_lock(unsigned int *lock) | |
| 33 | −{ | |
| 34 | − unsigned int old, new, val; | |
| 35 | − do { | |
| 36 | − old = *lock; | |
| 37 | − new = old & ~0x3; | |
| 38 | − val = ia64_cmpxchg4_acq(lock, new, old); | |
| 39 | − } while (unlikely (val != old)); | |
| 40 | − return old & 0x1; | |
| 41 | −} | |
| 42 | − | |
| 43 | −#define ACPI_ACQUIRE_GLOBAL_LOCK(facs, Acq) \ | |
| 44 | − ((Acq) = ia64_acpi_acquire_global_lock(&facs->global_lock)) | |
| 45 | − | |
| 46 | −#define ACPI_RELEASE_GLOBAL_LOCK(facs, Acq) \ | |
| 47 | − ((Acq) = ia64_acpi_release_global_lock(&facs->global_lock)) | |
| 48 | − | |
| 49 | −#endif /* _ASM_IA64_ACENV_H */ | |
| @@ -1,17 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0-only */ | |
| 2 | −/* | |
| 3 | − * (c) Copyright 2003, 2006 Hewlett-Packard Development Company, L.P. | |
| 4 | − * Alex Williamson <alex.williamson@hp.com> | |
| 5 | − * Bjorn Helgaas <bjorn.helgaas@hp.com> | |
| 6 | − * | |
| 7 | − * Vendor specific extensions to ACPI. | |
| 8 | − */ | |
| 9 | − | |
| 10 | −#ifndef _ASM_IA64_ACPI_EXT_H | |
| 11 | −#define _ASM_IA64_ACPI_EXT_H | |
| 12 | − | |
| 13 | −#include <linux/types.h> | |
| 14 | − | |
| 15 | −extern acpi_status hp_acpi_csr_space (acpi_handle, u64 *base, u64 *length); | |
| 16 | − | |
| 17 | −#endif /* _ASM_IA64_ACPI_EXT_H */ | |
| @@ -1,110 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0-or-later */ | |
| 2 | −/* | |
| 3 | − * Copyright (C) 1999 VA Linux Systems | |
| 4 | − * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> | |
| 5 | − * Copyright (C) 2000,2001 J.I. Lee <jung-ik.lee@intel.com> | |
| 6 | − * Copyright (C) 2001,2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
| 7 | − */ | |
| 8 | − | |
| 9 | −#ifndef _ASM_ACPI_H | |
| 10 | −#define _ASM_ACPI_H | |
| 11 | − | |
| 12 | −#ifdef __KERNEL__ | |
| 13 | − | |
| 14 | −#include <acpi/proc_cap_intel.h> | |
| 15 | − | |
| 16 | −#include <linux/init.h> | |
| 17 | −#include <linux/numa.h> | |
| 18 | −#include <asm/numa.h> | |
| 19 | − | |
| 20 | − | |
| 21 | −extern int acpi_lapic; | |
| 22 | −#define acpi_disabled 0 /* ACPI always enabled on IA64 */ | |
| 23 | −#define acpi_noirq 0 /* ACPI always enabled on IA64 */ | |
| 24 | −#define acpi_pci_disabled 0 /* ACPI PCI always enabled on IA64 */ | |
| 25 | −#define acpi_strict 1 /* no ACPI spec workarounds on IA64 */ | |
| 26 | − | |
| 27 | −static inline bool acpi_has_cpu_in_madt(void) | |
| 28 | −{ | |
| 29 | − return !!acpi_lapic; | |
| 30 | −} | |
| 31 | − | |
| 32 | −#define acpi_processor_cstate_check(x) (x) /* no idle limits on IA64 :) */ | |
| 33 | −static inline void disable_acpi(void) { } | |
| 34 | − | |
| 35 | −int acpi_request_vector (u32 int_type); | |
| 36 | −int acpi_gsi_to_irq (u32 gsi, unsigned int *irq); | |
| 37 | − | |
| 38 | −/* Low-level suspend routine. */ | |
| 39 | −extern int acpi_suspend_lowlevel(void); | |
| 40 | − | |
| 41 | −static inline unsigned long acpi_get_wakeup_address(void) | |
| 42 | −{ | |
| 43 | − return 0; | |
| 44 | −} | |
| 45 | − | |
| 46 | −/* | |
| 47 | − * Record the cpei override flag and current logical cpu. This is | |
| 48 | − * useful for CPU removal. | |
| 49 | − */ | |
| 50 | −extern unsigned int can_cpei_retarget(void); | |
| 51 | −extern unsigned int is_cpu_cpei_target(unsigned int cpu); | |
| 52 | −extern void set_cpei_target_cpu(unsigned int cpu); | |
| 53 | −extern unsigned int get_cpei_target_cpu(void); | |
| 54 | −extern void prefill_possible_map(void); | |
| 55 | −#ifdef CONFIG_ACPI_HOTPLUG_CPU | |
| 56 | −extern int additional_cpus; | |
| 57 | −#else | |
| 58 | −#define additional_cpus 0 | |
| 59 | −#endif | |
| 60 | − | |
| 61 | −#ifdef CONFIG_ACPI_NUMA | |
| 62 | −#if MAX_NUMNODES > 256 | |
| 63 | −#define MAX_PXM_DOMAINS MAX_NUMNODES | |
| 64 | −#else | |
| 65 | −#define MAX_PXM_DOMAINS (256) | |
| 66 | −#endif | |
| 67 | −extern int pxm_to_nid_map[MAX_PXM_DOMAINS]; | |
| 68 | −extern int __initdata nid_to_pxm_map[MAX_NUMNODES]; | |
| 69 | −#endif | |
| 70 | − | |
| 71 | −static inline bool arch_has_acpi_pdc(void) { return true; } | |
| 72 | −static inline void arch_acpi_set_proc_cap_bits(u32 *cap) | |
| 73 | −{ | |
| 74 | − *cap |= ACPI_PROC_CAP_EST_CAPABILITY_SMP; | |
| 75 | −} | |
| 76 | − | |
| 77 | −#ifdef CONFIG_ACPI_NUMA | |
| 78 | −extern cpumask_t early_cpu_possible_map; | |
| 79 | −#define for_each_possible_early_cpu(cpu) \ | |
| 80 | − for_each_cpu((cpu), &early_cpu_possible_map) | |
| 81 | − | |
| 82 | −static inline void per_cpu_scan_finalize(int min_cpus, int reserve_cpus) | |
| 83 | −{ | |
| 84 | − int low_cpu, high_cpu; | |
| 85 | − int cpu; | |
| 86 | − int next_nid = 0; | |
| 87 | − | |
| 88 | − low_cpu = cpumask_weight(&early_cpu_possible_map); | |
| 89 | − | |
| 90 | − high_cpu = max(low_cpu, min_cpus); | |
| 91 | − high_cpu = min(high_cpu + reserve_cpus, NR_CPUS); | |
| 92 | − | |
| 93 | − for (cpu = low_cpu; cpu < high_cpu; cpu++) { | |
| 94 | − cpumask_set_cpu(cpu, &early_cpu_possible_map); | |
| 95 | − if (node_cpuid[cpu].nid == NUMA_NO_NODE) { | |
| 96 | − node_cpuid[cpu].nid = next_nid; | |
| 97 | − next_nid++; | |
| 98 | − if (next_nid >= num_online_nodes()) | |
| 99 | − next_nid = 0; | |
| 100 | − } | |
| 101 | − } | |
| 102 | −} | |
| 103 | − | |
| 104 | −extern void acpi_numa_fixup(void); | |
| 105 | − | |
| 106 | −#endif /* CONFIG_ACPI_NUMA */ | |
| 107 | − | |
| 108 | −#endif /*__KERNEL__*/ | |
| 109 | − | |
| 110 | −#endif /*_ASM_ACPI_H*/ | |
| @@ -1 +0,0 @@ | ||
| 1 | −#include <generated/asm-offsets.h> | |
| @@ -1,30 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_ASM_PROTOTYPES_H | |
| 3 | −#define _ASM_IA64_ASM_PROTOTYPES_H | |
| 4 | − | |
| 5 | −#include <asm/cacheflush.h> | |
| 6 | −#include <asm/checksum.h> | |
| 7 | −#include <asm/esi.h> | |
| 8 | −#include <asm/ftrace.h> | |
| 9 | −#include <asm/page.h> | |
| 10 | −#include <asm/pal.h> | |
| 11 | −#include <asm/string.h> | |
| 12 | −#include <linux/uaccess.h> | |
| 13 | −#include <asm/unwind.h> | |
| 14 | −#include <asm/xor.h> | |
| 15 | − | |
| 16 | −extern const char ia64_ivt[]; | |
| 17 | − | |
| 18 | −signed int __divsi3(signed int, unsigned int); | |
| 19 | −signed int __modsi3(signed int, unsigned int); | |
| 20 | − | |
| 21 | −signed long long __divdi3(signed long long, unsigned long long); | |
| 22 | −signed long long __moddi3(signed long long, unsigned long long); | |
| 23 | − | |
| 24 | −unsigned int __udivsi3(unsigned int, unsigned int); | |
| 25 | −unsigned int __umodsi3(unsigned int, unsigned int); | |
| 26 | − | |
| 27 | −unsigned long long __udivdi3(unsigned long long, unsigned long long); | |
| 28 | −unsigned long long __umoddi3(unsigned long long, unsigned long long); | |
| 29 | − | |
| 30 | −#endif /* _ASM_IA64_ASM_PROTOTYPES_H */ | |
| @@ -1,136 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_ASMMACRO_H | |
| 3 | −#define _ASM_IA64_ASMMACRO_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Copyright (C) 2000-2001, 2003-2004 Hewlett-Packard Co | |
| 7 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 8 | − */ | |
| 9 | − | |
| 10 | − | |
| 11 | −#define ENTRY(name) \ | |
| 12 | − .align 32; \ | |
| 13 | − .proc name; \ | |
| 14 | −name: | |
| 15 | − | |
| 16 | −#define ENTRY_MIN_ALIGN(name) \ | |
| 17 | − .align 16; \ | |
| 18 | − .proc name; \ | |
| 19 | −name: | |
| 20 | − | |
| 21 | −#define GLOBAL_ENTRY(name) \ | |
| 22 | − .global name; \ | |
| 23 | − ENTRY(name) | |
| 24 | − | |
| 25 | −#define END(name) \ | |
| 26 | − .endp name | |
| 27 | − | |
| 28 | −/* | |
| 29 | − * Helper macros to make unwind directives more readable: | |
| 30 | − */ | |
| 31 | − | |
| 32 | −/* prologue_gr: */ | |
| 33 | −#define ASM_UNW_PRLG_RP 0x8 | |
| 34 | −#define ASM_UNW_PRLG_PFS 0x4 | |
| 35 | −#define ASM_UNW_PRLG_PSP 0x2 | |
| 36 | −#define ASM_UNW_PRLG_PR 0x1 | |
| 37 | −#define ASM_UNW_PRLG_GRSAVE(ninputs) (32+(ninputs)) | |
| 38 | − | |
| 39 | −/* | |
| 40 | − * Helper macros for accessing user memory. | |
| 41 | − * | |
| 42 | − * When adding any new .section/.previous entries here, make sure to | |
| 43 | − * also add it to the DISCARD section in arch/ia64/kernel/gate.lds.S or | |
| 44 | − * unpleasant things will happen. | |
| 45 | − */ | |
| 46 | − | |
| 47 | − .section "__ex_table", "a" // declare section & section attributes | |
| 48 | − .previous | |
| 49 | − | |
| 50 | −# define EX(y,x...) \ | |
| 51 | − .xdata4 "__ex_table", 99f-., y-.; \ | |
| 52 | − [99:] x | |
| 53 | −# define EXCLR(y,x...) \ | |
| 54 | − .xdata4 "__ex_table", 99f-., y-.+4; \ | |
| 55 | − [99:] x | |
| 56 | − | |
| 57 | −/* | |
| 58 | − * Tag MCA recoverable instruction ranges. | |
| 59 | − */ | |
| 60 | − | |
| 61 | − .section "__mca_table", "a" // declare section & section attributes | |
| 62 | − .previous | |
| 63 | − | |
| 64 | −# define MCA_RECOVER_RANGE(y) \ | |
| 65 | − .xdata4 "__mca_table", y-., 99f-.; \ | |
| 66 | − [99:] | |
| 67 | − | |
| 68 | −/* | |
| 69 | − * Mark instructions that need a load of a virtual address patched to be | |
| 70 | − * a load of a physical address. We use this either in critical performance | |
| 71 | − * path (ivt.S - TLB miss processing) or in places where it might not be | |
| 72 | − * safe to use a "tpa" instruction (mca_asm.S - error recovery). | |
| 73 | − */ | |
| 74 | − .section ".data..patch.vtop", "a" // declare section & section attributes | |
| 75 | − .previous | |
| 76 | − | |
| 77 | −#define LOAD_PHYSICAL(pr, reg, obj) \ | |
| 78 | −[1:](pr)movl reg = obj; \ | |
| 79 | − .xdata4 ".data..patch.vtop", 1b-. | |
| 80 | − | |
| 81 | −/* | |
| 82 | − * For now, we always put in the McKinley E9 workaround. On CPUs that don't need it, | |
| 83 | − * we'll patch out the work-around bundles with NOPs, so their impact is minimal. | |
| 84 | − */ | |
| 85 | −#define DO_MCKINLEY_E9_WORKAROUND | |
| 86 | − | |
| 87 | −#ifdef DO_MCKINLEY_E9_WORKAROUND | |
| 88 | − .section ".data..patch.mckinley_e9", "a" | |
| 89 | − .previous | |
| 90 | −/* workaround for Itanium 2 Errata 9: */ | |
| 91 | −# define FSYS_RETURN \ | |
| 92 | − .xdata4 ".data..patch.mckinley_e9", 1f-.; \ | |
| 93 | −1:{ .mib; \ | |
| 94 | − nop.m 0; \ | |
| 95 | − mov r16=ar.pfs; \ | |
| 96 | − br.call.sptk.many b7=2f;; \ | |
| 97 | − }; \ | |
| 98 | −2:{ .mib; \ | |
| 99 | − nop.m 0; \ | |
| 100 | − mov ar.pfs=r16; \ | |
| 101 | − br.ret.sptk.many b6;; \ | |
| 102 | − } | |
| 103 | −#else | |
| 104 | −# define FSYS_RETURN br.ret.sptk.many b6 | |
| 105 | −#endif | |
| 106 | − | |
| 107 | −/* | |
| 108 | − * If physical stack register size is different from DEF_NUM_STACK_REG, | |
| 109 | − * dynamically patch the kernel for correct size. | |
| 110 | − */ | |
| 111 | − .section ".data..patch.phys_stack_reg", "a" | |
| 112 | − .previous | |
| 113 | −#define LOAD_PHYS_STACK_REG_SIZE(reg) \ | |
| 114 | −[1:] adds reg=IA64_NUM_PHYS_STACK_REG*8+8,r0; \ | |
| 115 | − .xdata4 ".data..patch.phys_stack_reg", 1b-. | |
| 116 | − | |
| 117 | −/* | |
| 118 | − * Up until early 2004, use of .align within a function caused bad unwind info. | |
| 119 | − * TEXT_ALIGN(n) expands into ".align n" if a fixed GAS is available or into nothing | |
| 120 | − * otherwise. | |
| 121 | − */ | |
| 122 | −#ifdef HAVE_WORKING_TEXT_ALIGN | |
| 123 | −# define TEXT_ALIGN(n) .align n | |
| 124 | −#else | |
| 125 | −# define TEXT_ALIGN(n) | |
| 126 | −#endif | |
| 127 | − | |
| 128 | −#ifdef HAVE_SERIALIZE_DIRECTIVE | |
| 129 | −# define dv_serialize_data .serialize.data | |
| 130 | −# define dv_serialize_instruction .serialize.instruction | |
| 131 | −#else | |
| 132 | −# define dv_serialize_data | |
| 133 | −# define dv_serialize_instruction | |
| 134 | −#endif | |
| 135 | − | |
| 136 | −#endif /* _ASM_IA64_ASMMACRO_H */ | |
| @@ -1,216 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_ATOMIC_H | |
| 3 | −#define _ASM_IA64_ATOMIC_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Atomic operations that C can't guarantee us. Useful for | |
| 7 | − * resource counting etc.. | |
| 8 | − * | |
| 9 | − * NOTE: don't mess with the types below! The "unsigned long" and | |
| 10 | − * "int" types were carefully placed so as to ensure proper operation | |
| 11 | − * of the macros. | |
| 12 | − * | |
| 13 | − * Copyright (C) 1998, 1999, 2002-2003 Hewlett-Packard Co | |
| 14 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 15 | − */ | |
| 16 | −#include <linux/types.h> | |
| 17 | − | |
| 18 | −#include <asm/intrinsics.h> | |
| 19 | −#include <asm/barrier.h> | |
| 20 | − | |
| 21 | − | |
| 22 | −#define ATOMIC64_INIT(i) { (i) } | |
| 23 | − | |
| 24 | −#define arch_atomic_read(v) READ_ONCE((v)->counter) | |
| 25 | −#define arch_atomic64_read(v) READ_ONCE((v)->counter) | |
| 26 | − | |
| 27 | −#define arch_atomic_set(v,i) WRITE_ONCE(((v)->counter), (i)) | |
| 28 | −#define arch_atomic64_set(v,i) WRITE_ONCE(((v)->counter), (i)) | |
| 29 | − | |
| 30 | −#define ATOMIC_OP(op, c_op) \ | |
| 31 | −static __inline__ int \ | |
| 32 | −ia64_atomic_##op (int i, atomic_t *v) \ | |
| 33 | −{ \ | |
| 34 | − __s32 old, new; \ | |
| 35 | − CMPXCHG_BUGCHECK_DECL \ | |
| 36 | − \ | |
| 37 | − do { \ | |
| 38 | − CMPXCHG_BUGCHECK(v); \ | |
| 39 | − old = arch_atomic_read(v); \ | |
| 40 | − new = old c_op i; \ | |
| 41 | − } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic_t)) != old); \ | |
| 42 | − return new; \ | |
| 43 | −} | |
| 44 | − | |
| 45 | −#define ATOMIC_FETCH_OP(op, c_op) \ | |
| 46 | −static __inline__ int \ | |
| 47 | −ia64_atomic_fetch_##op (int i, atomic_t *v) \ | |
| 48 | −{ \ | |
| 49 | − __s32 old, new; \ | |
| 50 | − CMPXCHG_BUGCHECK_DECL \ | |
| 51 | − \ | |
| 52 | − do { \ | |
| 53 | − CMPXCHG_BUGCHECK(v); \ | |
| 54 | − old = arch_atomic_read(v); \ | |
| 55 | − new = old c_op i; \ | |
| 56 | − } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic_t)) != old); \ | |
| 57 | − return old; \ | |
| 58 | −} | |
| 59 | − | |
| 60 | −#define ATOMIC_OPS(op, c_op) \ | |
| 61 | − ATOMIC_OP(op, c_op) \ | |
| 62 | − ATOMIC_FETCH_OP(op, c_op) | |
| 63 | − | |
| 64 | −ATOMIC_OPS(add, +) | |
| 65 | −ATOMIC_OPS(sub, -) | |
| 66 | − | |
| 67 | −#ifdef __OPTIMIZE__ | |
| 68 | −#define __ia64_atomic_const(i) \ | |
| 69 | − static const int __ia64_atomic_p = __builtin_constant_p(i) ? \ | |
| 70 | − ((i) == 1 || (i) == 4 || (i) == 8 || (i) == 16 || \ | |
| 71 | − (i) == -1 || (i) == -4 || (i) == -8 || (i) == -16) : 0;\ | |
| 72 | − __ia64_atomic_p | |
| 73 | −#else | |
| 74 | −#define __ia64_atomic_const(i) 0 | |
| 75 | −#endif | |
| 76 | − | |
| 77 | −#define arch_atomic_add_return(i,v) \ | |
| 78 | −({ \ | |
| 79 | − int __ia64_aar_i = (i); \ | |
| 80 | − __ia64_atomic_const(i) \ | |
| 81 | − ? ia64_fetch_and_add(__ia64_aar_i, &(v)->counter) \ | |
| 82 | − : ia64_atomic_add(__ia64_aar_i, v); \ | |
| 83 | −}) | |
| 84 | − | |
| 85 | −#define arch_atomic_sub_return(i,v) \ | |
| 86 | −({ \ | |
| 87 | − int __ia64_asr_i = (i); \ | |
| 88 | − __ia64_atomic_const(i) \ | |
| 89 | − ? ia64_fetch_and_add(-__ia64_asr_i, &(v)->counter) \ | |
| 90 | − : ia64_atomic_sub(__ia64_asr_i, v); \ | |
| 91 | −}) | |
| 92 | − | |
| 93 | −#define arch_atomic_fetch_add(i,v) \ | |
| 94 | −({ \ | |
| 95 | − int __ia64_aar_i = (i); \ | |
| 96 | − __ia64_atomic_const(i) \ | |
| 97 | − ? ia64_fetchadd(__ia64_aar_i, &(v)->counter, acq) \ | |
| 98 | − : ia64_atomic_fetch_add(__ia64_aar_i, v); \ | |
| 99 | −}) | |
| 100 | − | |
| 101 | −#define arch_atomic_fetch_sub(i,v) \ | |
| 102 | −({ \ | |
| 103 | − int __ia64_asr_i = (i); \ | |
| 104 | − __ia64_atomic_const(i) \ | |
| 105 | − ? ia64_fetchadd(-__ia64_asr_i, &(v)->counter, acq) \ | |
| 106 | − : ia64_atomic_fetch_sub(__ia64_asr_i, v); \ | |
| 107 | −}) | |
| 108 | − | |
| 109 | −ATOMIC_FETCH_OP(and, &) | |
| 110 | −ATOMIC_FETCH_OP(or, |) | |
| 111 | −ATOMIC_FETCH_OP(xor, ^) | |
| 112 | − | |
| 113 | −#define arch_atomic_and(i,v) (void)ia64_atomic_fetch_and(i,v) | |
| 114 | −#define arch_atomic_or(i,v) (void)ia64_atomic_fetch_or(i,v) | |
| 115 | −#define arch_atomic_xor(i,v) (void)ia64_atomic_fetch_xor(i,v) | |
| 116 | − | |
| 117 | −#define arch_atomic_fetch_and(i,v) ia64_atomic_fetch_and(i,v) | |
| 118 | −#define arch_atomic_fetch_or(i,v) ia64_atomic_fetch_or(i,v) | |
| 119 | −#define arch_atomic_fetch_xor(i,v) ia64_atomic_fetch_xor(i,v) | |
| 120 | − | |
| 121 | −#undef ATOMIC_OPS | |
| 122 | −#undef ATOMIC_FETCH_OP | |
| 123 | −#undef ATOMIC_OP | |
| 124 | − | |
| 125 | −#define ATOMIC64_OP(op, c_op) \ | |
| 126 | −static __inline__ s64 \ | |
| 127 | −ia64_atomic64_##op (s64 i, atomic64_t *v) \ | |
| 128 | −{ \ | |
| 129 | − s64 old, new; \ | |
| 130 | − CMPXCHG_BUGCHECK_DECL \ | |
| 131 | − \ | |
| 132 | − do { \ | |
| 133 | − CMPXCHG_BUGCHECK(v); \ | |
| 134 | − old = arch_atomic64_read(v); \ | |
| 135 | − new = old c_op i; \ | |
| 136 | − } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) != old); \ | |
| 137 | − return new; \ | |
| 138 | −} | |
| 139 | − | |
| 140 | −#define ATOMIC64_FETCH_OP(op, c_op) \ | |
| 141 | −static __inline__ s64 \ | |
| 142 | −ia64_atomic64_fetch_##op (s64 i, atomic64_t *v) \ | |
| 143 | −{ \ | |
| 144 | − s64 old, new; \ | |
| 145 | − CMPXCHG_BUGCHECK_DECL \ | |
| 146 | − \ | |
| 147 | − do { \ | |
| 148 | − CMPXCHG_BUGCHECK(v); \ | |
| 149 | − old = arch_atomic64_read(v); \ | |
| 150 | − new = old c_op i; \ | |
| 151 | − } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) != old); \ | |
| 152 | − return old; \ | |
| 153 | −} | |
| 154 | − | |
| 155 | −#define ATOMIC64_OPS(op, c_op) \ | |
| 156 | − ATOMIC64_OP(op, c_op) \ | |
| 157 | − ATOMIC64_FETCH_OP(op, c_op) | |
| 158 | − | |
| 159 | −ATOMIC64_OPS(add, +) | |
| 160 | −ATOMIC64_OPS(sub, -) | |
| 161 | − | |
| 162 | −#define arch_atomic64_add_return(i,v) \ | |
| 163 | −({ \ | |
| 164 | − s64 __ia64_aar_i = (i); \ | |
| 165 | − __ia64_atomic_const(i) \ | |
| 166 | − ? ia64_fetch_and_add(__ia64_aar_i, &(v)->counter) \ | |
| 167 | − : ia64_atomic64_add(__ia64_aar_i, v); \ | |
| 168 | −}) | |
| 169 | − | |
| 170 | −#define arch_atomic64_sub_return(i,v) \ | |
| 171 | −({ \ | |
| 172 | − s64 __ia64_asr_i = (i); \ | |
| 173 | − __ia64_atomic_const(i) \ | |
| 174 | − ? ia64_fetch_and_add(-__ia64_asr_i, &(v)->counter) \ | |
| 175 | − : ia64_atomic64_sub(__ia64_asr_i, v); \ | |
| 176 | −}) | |
| 177 | − | |
| 178 | −#define arch_atomic64_fetch_add(i,v) \ | |
| 179 | −({ \ | |
| 180 | − s64 __ia64_aar_i = (i); \ | |
| 181 | − __ia64_atomic_const(i) \ | |
| 182 | − ? ia64_fetchadd(__ia64_aar_i, &(v)->counter, acq) \ | |
| 183 | − : ia64_atomic64_fetch_add(__ia64_aar_i, v); \ | |
| 184 | −}) | |
| 185 | − | |
| 186 | −#define arch_atomic64_fetch_sub(i,v) \ | |
| 187 | −({ \ | |
| 188 | − s64 __ia64_asr_i = (i); \ | |
| 189 | − __ia64_atomic_const(i) \ | |
| 190 | − ? ia64_fetchadd(-__ia64_asr_i, &(v)->counter, acq) \ | |
| 191 | − : ia64_atomic64_fetch_sub(__ia64_asr_i, v); \ | |
| 192 | −}) | |
| 193 | − | |
| 194 | −ATOMIC64_FETCH_OP(and, &) | |
| 195 | −ATOMIC64_FETCH_OP(or, |) | |
| 196 | −ATOMIC64_FETCH_OP(xor, ^) | |
| 197 | − | |
| 198 | −#define arch_atomic64_and(i,v) (void)ia64_atomic64_fetch_and(i,v) | |
| 199 | −#define arch_atomic64_or(i,v) (void)ia64_atomic64_fetch_or(i,v) | |
| 200 | −#define arch_atomic64_xor(i,v) (void)ia64_atomic64_fetch_xor(i,v) | |
| 201 | − | |
| 202 | −#define arch_atomic64_fetch_and(i,v) ia64_atomic64_fetch_and(i,v) | |
| 203 | −#define arch_atomic64_fetch_or(i,v) ia64_atomic64_fetch_or(i,v) | |
| 204 | −#define arch_atomic64_fetch_xor(i,v) ia64_atomic64_fetch_xor(i,v) | |
| 205 | − | |
| 206 | −#undef ATOMIC64_OPS | |
| 207 | −#undef ATOMIC64_FETCH_OP | |
| 208 | −#undef ATOMIC64_OP | |
| 209 | − | |
| 210 | −#define arch_atomic_add(i,v) (void)arch_atomic_add_return((i), (v)) | |
| 211 | −#define arch_atomic_sub(i,v) (void)arch_atomic_sub_return((i), (v)) | |
| 212 | − | |
| 213 | −#define arch_atomic64_add(i,v) (void)arch_atomic64_add_return((i), (v)) | |
| 214 | −#define arch_atomic64_sub(i,v) (void)arch_atomic64_sub_return((i), (v)) | |
| 215 | − | |
| 216 | −#endif /* _ASM_IA64_ATOMIC_H */ | |
| @@ -1,79 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −/* | |
| 3 | − * Memory barrier definitions. This is based on information published | |
| 4 | − * in the Processor Abstraction Layer and the System Abstraction Layer | |
| 5 | − * manual. | |
| 6 | − * | |
| 7 | − * Copyright (C) 1998-2003 Hewlett-Packard Co | |
| 8 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 9 | − * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> | |
| 10 | − * Copyright (C) 1999 Don Dugger <don.dugger@intel.com> | |
| 11 | − */ | |
| 12 | −#ifndef _ASM_IA64_BARRIER_H | |
| 13 | −#define _ASM_IA64_BARRIER_H | |
| 14 | − | |
| 15 | −#include <linux/compiler.h> | |
| 16 | − | |
| 17 | −/* | |
| 18 | − * Macros to force memory ordering. In these descriptions, "previous" | |
| 19 | − * and "subsequent" refer to program order; "visible" means that all | |
| 20 | − * architecturally visible effects of a memory access have occurred | |
| 21 | − * (at a minimum, this means the memory has been read or written). | |
| 22 | − * | |
| 23 | − * wmb(): Guarantees that all preceding stores to memory- | |
| 24 | − * like regions are visible before any subsequent | |
| 25 | − * stores and that all following stores will be | |
| 26 | − * visible only after all previous stores. | |
| 27 | − * rmb(): Like wmb(), but for reads. | |
| 28 | − * mb(): wmb()/rmb() combo, i.e., all previous memory | |
| 29 | − * accesses are visible before all subsequent | |
| 30 | − * accesses and vice versa. This is also known as | |
| 31 | − * a "fence." | |
| 32 | − * | |
| 33 | − * Note: "mb()" and its variants cannot be used as a fence to order | |
| 34 | − * accesses to memory mapped I/O registers. For that, mf.a needs to | |
| 35 | − * be used. However, we don't want to always use mf.a because (a) | |
| 36 | − * it's (presumably) much slower than mf and (b) mf.a is supported for | |
| 37 | − * sequential memory pages only. | |
| 38 | − */ | |
| 39 | −#define mb() ia64_mf() | |
| 40 | −#define rmb() mb() | |
| 41 | −#define wmb() mb() | |
| 42 | − | |
| 43 | −#define dma_rmb() mb() | |
| 44 | −#define dma_wmb() mb() | |
| 45 | − | |
| 46 | −# define __smp_mb() mb() | |
| 47 | − | |
| 48 | −#define __smp_mb__before_atomic() barrier() | |
| 49 | −#define __smp_mb__after_atomic() barrier() | |
| 50 | − | |
| 51 | −/* | |
| 52 | − * IA64 GCC turns volatile stores into st.rel and volatile loads into ld.acq no | |
| 53 | − * need for asm trickery! | |
| 54 | − */ | |
| 55 | − | |
| 56 | −#define __smp_store_release(p, v) \ | |
| 57 | −do { \ | |
| 58 | − compiletime_assert_atomic_type(*p); \ | |
| 59 | − barrier(); \ | |
| 60 | − WRITE_ONCE(*p, v); \ | |
| 61 | −} while (0) | |
| 62 | − | |
| 63 | −#define __smp_load_acquire(p) \ | |
| 64 | −({ \ | |
| 65 | − typeof(*p) ___p1 = READ_ONCE(*p); \ | |
| 66 | − compiletime_assert_atomic_type(*p); \ | |
| 67 | − barrier(); \ | |
| 68 | − ___p1; \ | |
| 69 | −}) | |
| 70 | − | |
| 71 | −/* | |
| 72 | − * The group barrier in front of the rsm & ssm are necessary to ensure | |
| 73 | − * that none of the previous instructions in the same group are | |
| 74 | − * affected by the rsm/ssm. | |
| 75 | − */ | |
| 76 | − | |
| 77 | −#include <asm-generic/barrier.h> | |
| 78 | − | |
| 79 | −#endif /* _ASM_IA64_BARRIER_H */ | |
| @@ -1,453 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_BITOPS_H | |
| 3 | −#define _ASM_IA64_BITOPS_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Copyright (C) 1998-2003 Hewlett-Packard Co | |
| 7 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 8 | − * | |
| 9 | − * 02/06/02 find_next_bit() and find_first_bit() added from Erich Focht's ia64 | |
| 10 | − * O(1) scheduler patch | |
| 11 | − */ | |
| 12 | − | |
| 13 | −#ifndef _LINUX_BITOPS_H | |
| 14 | −#error only <linux/bitops.h> can be included directly | |
| 15 | −#endif | |
| 16 | − | |
| 17 | −#include <linux/compiler.h> | |
| 18 | −#include <linux/types.h> | |
| 19 | −#include <asm/intrinsics.h> | |
| 20 | −#include <asm/barrier.h> | |
| 21 | − | |
| 22 | −/** | |
| 23 | − * set_bit - Atomically set a bit in memory | |
| 24 | − * @nr: the bit to set | |
| 25 | − * @addr: the address to start counting from | |
| 26 | − * | |
| 27 | − * This function is atomic and may not be reordered. See __set_bit() | |
| 28 | − * if you do not require the atomic guarantees. | |
| 29 | − * Note that @nr may be almost arbitrarily large; this function is not | |
| 30 | − * restricted to acting on a single-word quantity. | |
| 31 | − * | |
| 32 | − * The address must be (at least) "long" aligned. | |
| 33 | − * Note that there are driver (e.g., eepro100) which use these operations to | |
| 34 | − * operate on hw-defined data-structures, so we can't easily change these | |
| 35 | − * operations to force a bigger alignment. | |
| 36 | − * | |
| 37 | − * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). | |
| 38 | − */ | |
| 39 | −static __inline__ void | |
| 40 | −set_bit (int nr, volatile void *addr) | |
| 41 | −{ | |
| 42 | − __u32 bit, old, new; | |
| 43 | − volatile __u32 *m; | |
| 44 | − CMPXCHG_BUGCHECK_DECL | |
| 45 | − | |
| 46 | − m = (volatile __u32 *) addr + (nr >> 5); | |
| 47 | − bit = 1 << (nr & 31); | |
| 48 | − do { | |
| 49 | − CMPXCHG_BUGCHECK(m); | |
| 50 | − old = *m; | |
| 51 | − new = old | bit; | |
| 52 | − } while (cmpxchg_acq(m, old, new) != old); | |
| 53 | −} | |
| 54 | − | |
| 55 | −/** | |
| 56 | − * arch___set_bit - Set a bit in memory | |
| 57 | − * @nr: the bit to set | |
| 58 | − * @addr: the address to start counting from | |
| 59 | − * | |
| 60 | − * Unlike set_bit(), this function is non-atomic and may be reordered. | |
| 61 | − * If it's called on the same region of memory simultaneously, the effect | |
| 62 | − * may be that only one operation succeeds. | |
| 63 | − */ | |
| 64 | −static __always_inline void | |
| 65 | −arch___set_bit(unsigned long nr, volatile unsigned long *addr) | |
| 66 | −{ | |
| 67 | − *((__u32 *) addr + (nr >> 5)) |= (1 << (nr & 31)); | |
| 68 | −} | |
| 69 | − | |
| 70 | −/** | |
| 71 | − * clear_bit - Clears a bit in memory | |
| 72 | − * @nr: Bit to clear | |
| 73 | − * @addr: Address to start counting from | |
| 74 | − * | |
| 75 | − * clear_bit() is atomic and may not be reordered. However, it does | |
| 76 | − * not contain a memory barrier, so if it is used for locking purposes, | |
| 77 | − * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic() | |
| 78 | − * in order to ensure changes are visible on other processors. | |
| 79 | − */ | |
| 80 | −static __inline__ void | |
| 81 | −clear_bit (int nr, volatile void *addr) | |
| 82 | −{ | |
| 83 | − __u32 mask, old, new; | |
| 84 | − volatile __u32 *m; | |
| 85 | − CMPXCHG_BUGCHECK_DECL | |
| 86 | − | |
| 87 | − m = (volatile __u32 *) addr + (nr >> 5); | |
| 88 | − mask = ~(1 << (nr & 31)); | |
| 89 | − do { | |
| 90 | − CMPXCHG_BUGCHECK(m); | |
| 91 | − old = *m; | |
| 92 | − new = old & mask; | |
| 93 | − } while (cmpxchg_acq(m, old, new) != old); | |
| 94 | −} | |
| 95 | − | |
| 96 | −/** | |
| 97 | − * clear_bit_unlock - Clears a bit in memory with release | |
| 98 | − * @nr: Bit to clear | |
| 99 | − * @addr: Address to start counting from | |
| 100 | − * | |
| 101 | − * clear_bit_unlock() is atomic and may not be reordered. It does | |
| 102 | − * contain a memory barrier suitable for unlock type operations. | |
| 103 | − */ | |
| 104 | −static __inline__ void | |
| 105 | −clear_bit_unlock (int nr, volatile void *addr) | |
| 106 | −{ | |
| 107 | − __u32 mask, old, new; | |
| 108 | − volatile __u32 *m; | |
| 109 | − CMPXCHG_BUGCHECK_DECL | |
| 110 | − | |
| 111 | − m = (volatile __u32 *) addr + (nr >> 5); | |
| 112 | − mask = ~(1 << (nr & 31)); | |
| 113 | − do { | |
| 114 | − CMPXCHG_BUGCHECK(m); | |
| 115 | − old = *m; | |
| 116 | − new = old & mask; | |
| 117 | − } while (cmpxchg_rel(m, old, new) != old); | |
| 118 | −} | |
| 119 | − | |
| 120 | −/** | |
| 121 | − * __clear_bit_unlock - Non-atomically clears a bit in memory with release | |
| 122 | − * @nr: Bit to clear | |
| 123 | − * @addr: Address to start counting from | |
| 124 | − * | |
| 125 | − * Similarly to clear_bit_unlock, the implementation uses a store | |
| 126 | − * with release semantics. See also arch_spin_unlock(). | |
| 127 | − */ | |
| 128 | −static __inline__ void | |
| 129 | −__clear_bit_unlock(int nr, void *addr) | |
| 130 | −{ | |
| 131 | − __u32 * const m = (__u32 *) addr + (nr >> 5); | |
| 132 | − __u32 const new = *m & ~(1 << (nr & 31)); | |
| 133 | − | |
| 134 | − ia64_st4_rel_nta(m, new); | |
| 135 | −} | |
| 136 | − | |
| 137 | −/** | |
| 138 | − * arch___clear_bit - Clears a bit in memory (non-atomic version) | |
| 139 | − * @nr: the bit to clear | |
| 140 | − * @addr: the address to start counting from | |
| 141 | − * | |
| 142 | − * Unlike clear_bit(), this function is non-atomic and may be reordered. | |
| 143 | − * If it's called on the same region of memory simultaneously, the effect | |
| 144 | − * may be that only one operation succeeds. | |
| 145 | − */ | |
| 146 | −static __always_inline void | |
| 147 | −arch___clear_bit(unsigned long nr, volatile unsigned long *addr) | |
| 148 | −{ | |
| 149 | − *((__u32 *) addr + (nr >> 5)) &= ~(1 << (nr & 31)); | |
| 150 | −} | |
| 151 | − | |
| 152 | −/** | |
| 153 | − * change_bit - Toggle a bit in memory | |
| 154 | − * @nr: Bit to toggle | |
| 155 | − * @addr: Address to start counting from | |
| 156 | − * | |
| 157 | − * change_bit() is atomic and may not be reordered. | |
| 158 | − * Note that @nr may be almost arbitrarily large; this function is not | |
| 159 | − * restricted to acting on a single-word quantity. | |
| 160 | − */ | |
| 161 | −static __inline__ void | |
| 162 | −change_bit (int nr, volatile void *addr) | |
| 163 | −{ | |
| 164 | − __u32 bit, old, new; | |
| 165 | − volatile __u32 *m; | |
| 166 | − CMPXCHG_BUGCHECK_DECL | |
| 167 | − | |
| 168 | − m = (volatile __u32 *) addr + (nr >> 5); | |
| 169 | − bit = (1 << (nr & 31)); | |
| 170 | − do { | |
| 171 | − CMPXCHG_BUGCHECK(m); | |
| 172 | − old = *m; | |
| 173 | − new = old ^ bit; | |
| 174 | − } while (cmpxchg_acq(m, old, new) != old); | |
| 175 | −} | |
| 176 | − | |
| 177 | −/** | |
| 178 | − * arch___change_bit - Toggle a bit in memory | |
| 179 | − * @nr: the bit to toggle | |
| 180 | − * @addr: the address to start counting from | |
| 181 | − * | |
| 182 | − * Unlike change_bit(), this function is non-atomic and may be reordered. | |
| 183 | − * If it's called on the same region of memory simultaneously, the effect | |
| 184 | − * may be that only one operation succeeds. | |
| 185 | − */ | |
| 186 | −static __always_inline void | |
| 187 | −arch___change_bit(unsigned long nr, volatile unsigned long *addr) | |
| 188 | −{ | |
| 189 | − *((__u32 *) addr + (nr >> 5)) ^= (1 << (nr & 31)); | |
| 190 | −} | |
| 191 | − | |
| 192 | −/** | |
| 193 | − * test_and_set_bit - Set a bit and return its old value | |
| 194 | − * @nr: Bit to set | |
| 195 | − * @addr: Address to count from | |
| 196 | − * | |
| 197 | − * This operation is atomic and cannot be reordered. | |
| 198 | − * It also implies the acquisition side of the memory barrier. | |
| 199 | − */ | |
| 200 | −static __inline__ int | |
| 201 | −test_and_set_bit (int nr, volatile void *addr) | |
| 202 | −{ | |
| 203 | − __u32 bit, old, new; | |
| 204 | − volatile __u32 *m; | |
| 205 | − CMPXCHG_BUGCHECK_DECL | |
| 206 | − | |
| 207 | − m = (volatile __u32 *) addr + (nr >> 5); | |
| 208 | − bit = 1 << (nr & 31); | |
| 209 | − do { | |
| 210 | − CMPXCHG_BUGCHECK(m); | |
| 211 | − old = *m; | |
| 212 | − new = old | bit; | |
| 213 | − } while (cmpxchg_acq(m, old, new) != old); | |
| 214 | − return (old & bit) != 0; | |
| 215 | −} | |
| 216 | − | |
| 217 | −/** | |
| 218 | − * test_and_set_bit_lock - Set a bit and return its old value for lock | |
| 219 | − * @nr: Bit to set | |
| 220 | − * @addr: Address to count from | |
| 221 | − * | |
| 222 | − * This is the same as test_and_set_bit on ia64 | |
| 223 | − */ | |
| 224 | −#define test_and_set_bit_lock test_and_set_bit | |
| 225 | − | |
| 226 | −/** | |
| 227 | − * arch___test_and_set_bit - Set a bit and return its old value | |
| 228 | − * @nr: Bit to set | |
| 229 | − * @addr: Address to count from | |
| 230 | − * | |
| 231 | − * This operation is non-atomic and can be reordered. | |
| 232 | − * If two examples of this operation race, one can appear to succeed | |
| 233 | − * but actually fail. You must protect multiple accesses with a lock. | |
| 234 | − */ | |
| 235 | −static __always_inline bool | |
| 236 | −arch___test_and_set_bit(unsigned long nr, volatile unsigned long *addr) | |
| 237 | −{ | |
| 238 | − __u32 *p = (__u32 *) addr + (nr >> 5); | |
| 239 | − __u32 m = 1 << (nr & 31); | |
| 240 | − int oldbitset = (*p & m) != 0; | |
| 241 | − | |
| 242 | − *p |= m; | |
| 243 | − return oldbitset; | |
| 244 | −} | |
| 245 | − | |
| 246 | −/** | |
| 247 | − * test_and_clear_bit - Clear a bit and return its old value | |
| 248 | − * @nr: Bit to clear | |
| 249 | − * @addr: Address to count from | |
| 250 | − * | |
| 251 | − * This operation is atomic and cannot be reordered. | |
| 252 | − * It also implies the acquisition side of the memory barrier. | |
| 253 | − */ | |
| 254 | −static __inline__ int | |
| 255 | −test_and_clear_bit (int nr, volatile void *addr) | |
| 256 | −{ | |
| 257 | − __u32 mask, old, new; | |
| 258 | − volatile __u32 *m; | |
| 259 | − CMPXCHG_BUGCHECK_DECL | |
| 260 | − | |
| 261 | − m = (volatile __u32 *) addr + (nr >> 5); | |
| 262 | − mask = ~(1 << (nr & 31)); | |
| 263 | − do { | |
| 264 | − CMPXCHG_BUGCHECK(m); | |
| 265 | − old = *m; | |
| 266 | − new = old & mask; | |
| 267 | − } while (cmpxchg_acq(m, old, new) != old); | |
| 268 | − return (old & ~mask) != 0; | |
| 269 | −} | |
| 270 | − | |
| 271 | −/** | |
| 272 | − * arch___test_and_clear_bit - Clear a bit and return its old value | |
| 273 | − * @nr: Bit to clear | |
| 274 | − * @addr: Address to count from | |
| 275 | − * | |
| 276 | − * This operation is non-atomic and can be reordered. | |
| 277 | − * If two examples of this operation race, one can appear to succeed | |
| 278 | − * but actually fail. You must protect multiple accesses with a lock. | |
| 279 | − */ | |
| 280 | −static __always_inline bool | |
| 281 | −arch___test_and_clear_bit(unsigned long nr, volatile unsigned long *addr) | |
| 282 | −{ | |
| 283 | − __u32 *p = (__u32 *) addr + (nr >> 5); | |
| 284 | − __u32 m = 1 << (nr & 31); | |
| 285 | − int oldbitset = (*p & m) != 0; | |
| 286 | − | |
| 287 | − *p &= ~m; | |
| 288 | − return oldbitset; | |
| 289 | −} | |
| 290 | − | |
| 291 | −/** | |
| 292 | − * test_and_change_bit - Change a bit and return its old value | |
| 293 | − * @nr: Bit to change | |
| 294 | − * @addr: Address to count from | |
| 295 | − * | |
| 296 | − * This operation is atomic and cannot be reordered. | |
| 297 | − * It also implies the acquisition side of the memory barrier. | |
| 298 | − */ | |
| 299 | −static __inline__ int | |
| 300 | −test_and_change_bit (int nr, volatile void *addr) | |
| 301 | −{ | |
| 302 | − __u32 bit, old, new; | |
| 303 | − volatile __u32 *m; | |
| 304 | − CMPXCHG_BUGCHECK_DECL | |
| 305 | − | |
| 306 | − m = (volatile __u32 *) addr + (nr >> 5); | |
| 307 | − bit = (1 << (nr & 31)); | |
| 308 | − do { | |
| 309 | − CMPXCHG_BUGCHECK(m); | |
| 310 | − old = *m; | |
| 311 | − new = old ^ bit; | |
| 312 | − } while (cmpxchg_acq(m, old, new) != old); | |
| 313 | − return (old & bit) != 0; | |
| 314 | −} | |
| 315 | − | |
| 316 | −/** | |
| 317 | − * arch___test_and_change_bit - Change a bit and return its old value | |
| 318 | − * @nr: Bit to change | |
| 319 | − * @addr: Address to count from | |
| 320 | − * | |
| 321 | − * This operation is non-atomic and can be reordered. | |
| 322 | − */ | |
| 323 | −static __always_inline bool | |
| 324 | −arch___test_and_change_bit(unsigned long nr, volatile unsigned long *addr) | |
| 325 | −{ | |
| 326 | − __u32 old, bit = (1 << (nr & 31)); | |
| 327 | − __u32 *m = (__u32 *) addr + (nr >> 5); | |
| 328 | − | |
| 329 | − old = *m; | |
| 330 | − *m = old ^ bit; | |
| 331 | − return (old & bit) != 0; | |
| 332 | −} | |
| 333 | − | |
| 334 | −#define arch_test_bit generic_test_bit | |
| 335 | −#define arch_test_bit_acquire generic_test_bit_acquire | |
| 336 | − | |
| 337 | −/** | |
| 338 | − * ffz - find the first zero bit in a long word | |
| 339 | − * @x: The long word to find the bit in | |
| 340 | − * | |
| 341 | − * Returns the bit-number (0..63) of the first (least significant) zero bit. | |
| 342 | − * Undefined if no zero exists, so code should check against ~0UL first... | |
| 343 | − */ | |
| 344 | −static inline unsigned long | |
| 345 | −ffz (unsigned long x) | |
| 346 | −{ | |
| 347 | − unsigned long result; | |
| 348 | − | |
| 349 | − result = ia64_popcnt(x & (~x - 1)); | |
| 350 | − return result; | |
| 351 | −} | |
| 352 | − | |
| 353 | −/** | |
| 354 | − * __ffs - find first bit in word. | |
| 355 | − * @x: The word to search | |
| 356 | − * | |
| 357 | − * Undefined if no bit exists, so code should check against 0 first. | |
| 358 | − */ | |
| 359 | −static __inline__ unsigned long | |
| 360 | −__ffs (unsigned long x) | |
| 361 | −{ | |
| 362 | − unsigned long result; | |
| 363 | − | |
| 364 | − result = ia64_popcnt((x-1) & ~x); | |
| 365 | − return result; | |
| 366 | −} | |
| 367 | − | |
| 368 | −#ifdef __KERNEL__ | |
| 369 | − | |
| 370 | −/* | |
| 371 | − * Return bit number of last (most-significant) bit set. Undefined | |
| 372 | − * for x==0. Bits are numbered from 0..63 (e.g., ia64_fls(9) == 3). | |
| 373 | − */ | |
| 374 | −static inline unsigned long | |
| 375 | −ia64_fls (unsigned long x) | |
| 376 | −{ | |
| 377 | − long double d = x; | |
| 378 | − long exp; | |
| 379 | − | |
| 380 | − exp = ia64_getf_exp(d); | |
| 381 | − return exp - 0xffff; | |
| 382 | −} | |
| 383 | − | |
| 384 | −/* | |
| 385 | − * Find the last (most significant) bit set. Returns 0 for x==0 and | |
| 386 | − * bits are numbered from 1..32 (e.g., fls(9) == 4). | |
| 387 | − */ | |
| 388 | −static inline int fls(unsigned int t) | |
| 389 | −{ | |
| 390 | − unsigned long x = t & 0xffffffffu; | |
| 391 | − | |
| 392 | − if (!x) | |
| 393 | − return 0; | |
| 394 | − x |= x >> 1; | |
| 395 | − x |= x >> 2; | |
| 396 | − x |= x >> 4; | |
| 397 | − x |= x >> 8; | |
| 398 | − x |= x >> 16; | |
| 399 | − return ia64_popcnt(x); | |
| 400 | −} | |
| 401 | − | |
| 402 | −/* | |
| 403 | − * Find the last (most significant) bit set. Undefined for x==0. | |
| 404 | − * Bits are numbered from 0..63 (e.g., __fls(9) == 3). | |
| 405 | − */ | |
| 406 | −static inline unsigned long | |
| 407 | −__fls (unsigned long x) | |
| 408 | −{ | |
| 409 | − x |= x >> 1; | |
| 410 | − x |= x >> 2; | |
| 411 | − x |= x >> 4; | |
| 412 | − x |= x >> 8; | |
| 413 | − x |= x >> 16; | |
| 414 | − x |= x >> 32; | |
| 415 | − return ia64_popcnt(x) - 1; | |
| 416 | −} | |
| 417 | − | |
| 418 | −#include <asm-generic/bitops/fls64.h> | |
| 419 | − | |
| 420 | −#include <asm-generic/bitops/builtin-ffs.h> | |
| 421 | − | |
| 422 | −/* | |
| 423 | − * hweightN: returns the hamming weight (i.e. the number | |
| 424 | − * of bits set) of a N-bit word | |
| 425 | − */ | |
| 426 | −static __inline__ unsigned long __arch_hweight64(unsigned long x) | |
| 427 | −{ | |
| 428 | − unsigned long result; | |
| 429 | − result = ia64_popcnt(x); | |
| 430 | − return result; | |
| 431 | −} | |
| 432 | − | |
| 433 | −#define __arch_hweight32(x) ((unsigned int) __arch_hweight64((x) & 0xfffffffful)) | |
| 434 | −#define __arch_hweight16(x) ((unsigned int) __arch_hweight64((x) & 0xfffful)) | |
| 435 | −#define __arch_hweight8(x) ((unsigned int) __arch_hweight64((x) & 0xfful)) | |
| 436 | − | |
| 437 | −#include <asm-generic/bitops/const_hweight.h> | |
| 438 | − | |
| 439 | −#endif /* __KERNEL__ */ | |
| 440 | − | |
| 441 | −#ifdef __KERNEL__ | |
| 442 | − | |
| 443 | −#include <asm-generic/bitops/non-instrumented-non-atomic.h> | |
| 444 | − | |
| 445 | −#include <asm-generic/bitops/le.h> | |
| 446 | − | |
| 447 | −#include <asm-generic/bitops/ext2-atomic-setbit.h> | |
| 448 | − | |
| 449 | −#include <asm-generic/bitops/sched.h> | |
| 450 | − | |
| 451 | −#endif /* __KERNEL__ */ | |
| 452 | − | |
| 453 | −#endif /* _ASM_IA64_BITOPS_H */ | |
| @@ -1,19 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_BUG_H | |
| 3 | −#define _ASM_IA64_BUG_H | |
| 4 | − | |
| 5 | −#ifdef CONFIG_BUG | |
| 6 | −#define ia64_abort() __builtin_trap() | |
| 7 | −#define BUG() do { \ | |
| 8 | − printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \ | |
| 9 | − barrier_before_unreachable(); \ | |
| 10 | − ia64_abort(); \ | |
| 11 | −} while (0) | |
| 12 | − | |
| 13 | −/* should this BUG be made generic? */ | |
| 14 | −#define HAVE_ARCH_BUG | |
| 15 | −#endif | |
| 16 | − | |
| 17 | −#include <asm-generic/bug.h> | |
| 18 | − | |
| 19 | −#endif | |
| @@ -1,30 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_CACHE_H | |
| 3 | −#define _ASM_IA64_CACHE_H | |
| 4 | − | |
| 5 | − | |
| 6 | −/* | |
| 7 | − * Copyright (C) 1998-2000 Hewlett-Packard Co | |
| 8 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 9 | − */ | |
| 10 | − | |
| 11 | −/* Bytes per L1 (data) cache line. */ | |
| 12 | −#define L1_CACHE_SHIFT CONFIG_IA64_L1_CACHE_SHIFT | |
| 13 | −#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) | |
| 14 | − | |
| 15 | −#ifdef CONFIG_SMP | |
| 16 | −# define SMP_CACHE_SHIFT L1_CACHE_SHIFT | |
| 17 | −# define SMP_CACHE_BYTES L1_CACHE_BYTES | |
| 18 | −#else | |
| 19 | − /* | |
| 20 | − * The "aligned" directive can only _increase_ alignment, so this is | |
| 21 | − * safe and provides an easy way to avoid wasting space on a | |
| 22 | − * uni-processor: | |
| 23 | − */ | |
| 24 | −# define SMP_CACHE_SHIFT 3 | |
| 25 | −# define SMP_CACHE_BYTES (1 << 3) | |
| 26 | −#endif | |
| 27 | − | |
| 28 | −#define __read_mostly __section(".data..read_mostly") | |
| 29 | − | |
| 30 | −#endif /* _ASM_IA64_CACHE_H */ | |
| @@ -1,39 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_CACHEFLUSH_H | |
| 3 | −#define _ASM_IA64_CACHEFLUSH_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Copyright (C) 2002 Hewlett-Packard Co | |
| 7 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 8 | − */ | |
| 9 | − | |
| 10 | −#include <linux/page-flags.h> | |
| 11 | −#include <linux/bitops.h> | |
| 12 | − | |
| 13 | −#include <asm/page.h> | |
| 14 | − | |
| 15 | −#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 | |
| 16 | −static inline void flush_dcache_folio(struct folio *folio) | |
| 17 | −{ | |
| 18 | − clear_bit(PG_arch_1, &folio->flags); | |
| 19 | −} | |
| 20 | −#define flush_dcache_folio flush_dcache_folio | |
| 21 | − | |
| 22 | −static inline void flush_dcache_page(struct page *page) | |
| 23 | −{ | |
| 24 | − flush_dcache_folio(page_folio(page)); | |
| 25 | −} | |
| 26 | − | |
| 27 | −extern void flush_icache_range(unsigned long start, unsigned long end); | |
| 28 | −#define flush_icache_range flush_icache_range | |
| 29 | −extern void clflush_cache_range(void *addr, int size); | |
| 30 | − | |
| 31 | −#define flush_icache_user_page(vma, page, user_addr, len) \ | |
| 32 | −do { \ | |
| 33 | − unsigned long _addr = (unsigned long) page_address(page) + ((user_addr) & ~PAGE_MASK); \ | |
| 34 | − flush_icache_range(_addr, _addr + (len)); \ | |
| 35 | −} while (0) | |
| 36 | − | |
| 37 | −#include <asm-generic/cacheflush.h> | |
| 38 | − | |
| 39 | −#endif /* _ASM_IA64_CACHEFLUSH_H */ | |
| @@ -1,63 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_CHECKSUM_H | |
| 3 | −#define _ASM_IA64_CHECKSUM_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Modified 1998, 1999 | |
| 7 | − * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co | |
| 8 | − */ | |
| 9 | − | |
| 10 | −/* | |
| 11 | − * This is a version of ip_compute_csum() optimized for IP headers, | |
| 12 | − * which always checksum on 4 octet boundaries. | |
| 13 | − */ | |
| 14 | −extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl); | |
| 15 | − | |
| 16 | −/* | |
| 17 | − * Computes the checksum of the TCP/UDP pseudo-header returns a 16-bit | |
| 18 | − * checksum, already complemented | |
| 19 | − */ | |
| 20 | −extern __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr, | |
| 21 | − __u32 len, __u8 proto, __wsum sum); | |
| 22 | − | |
| 23 | −extern __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr, | |
| 24 | − __u32 len, __u8 proto, __wsum sum); | |
| 25 | − | |
| 26 | −/* | |
| 27 | − * Computes the checksum of a memory block at buff, length len, | |
| 28 | − * and adds in "sum" (32-bit) | |
| 29 | − * | |
| 30 | − * returns a 32-bit number suitable for feeding into itself | |
| 31 | − * or csum_tcpudp_magic | |
| 32 | − * | |
| 33 | − * this function must be called with even lengths, except | |
| 34 | − * for the last fragment, which may be odd | |
| 35 | − * | |
| 36 | − * it's best to have buff aligned on a 32-bit boundary | |
| 37 | − */ | |
| 38 | −extern __wsum csum_partial(const void *buff, int len, __wsum sum); | |
| 39 | − | |
| 40 | −/* | |
| 41 | − * This routine is used for miscellaneous IP-like checksums, mainly in | |
| 42 | − * icmp.c | |
| 43 | − */ | |
| 44 | −extern __sum16 ip_compute_csum(const void *buff, int len); | |
| 45 | − | |
| 46 | −/* | |
| 47 | − * Fold a partial checksum without adding pseudo headers. | |
| 48 | − */ | |
| 49 | −static inline __sum16 csum_fold(__wsum csum) | |
| 50 | −{ | |
| 51 | − u32 sum = (__force u32)csum; | |
| 52 | − sum = (sum & 0xffff) + (sum >> 16); | |
| 53 | − sum = (sum & 0xffff) + (sum >> 16); | |
| 54 | − return (__force __sum16)~sum; | |
| 55 | −} | |
| 56 | − | |
| 57 | −#define _HAVE_ARCH_IPV6_CSUM 1 | |
| 58 | −struct in6_addr; | |
| 59 | −extern __sum16 csum_ipv6_magic(const struct in6_addr *saddr, | |
| 60 | − const struct in6_addr *daddr, | |
| 61 | − __u32 len, __u8 proto, __wsum csum); | |
| 62 | − | |
| 63 | −#endif /* _ASM_IA64_CHECKSUM_H */ | |
| @@ -1,11 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −/* IA64-specific clocksource additions */ | |
| 3 | − | |
| 4 | −#ifndef _ASM_IA64_CLOCKSOURCE_H | |
| 5 | −#define _ASM_IA64_CLOCKSOURCE_H | |
| 6 | − | |
| 7 | −struct arch_clocksource_data { | |
| 8 | − void *fsys_mmio; /* used by fsyscall asm code */ | |
| 9 | −}; | |
| 10 | − | |
| 11 | −#endif /* _ASM_IA64_CLOCKSOURCE_H */ | |
| @@ -1,33 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_CMPXCHG_H | |
| 3 | −#define _ASM_IA64_CMPXCHG_H | |
| 4 | − | |
| 5 | −#include <uapi/asm/cmpxchg.h> | |
| 6 | − | |
| 7 | −#define arch_xchg(ptr, x) \ | |
| 8 | −({(__typeof__(*(ptr))) __arch_xchg((unsigned long) (x), (ptr), sizeof(*(ptr)));}) | |
| 9 | − | |
| 10 | −#define arch_cmpxchg(ptr, o, n) cmpxchg_acq((ptr), (o), (n)) | |
| 11 | −#define arch_cmpxchg64(ptr, o, n) cmpxchg_acq((ptr), (o), (n)) | |
| 12 | − | |
| 13 | −#define arch_cmpxchg_local arch_cmpxchg | |
| 14 | −#define arch_cmpxchg64_local arch_cmpxchg64 | |
| 15 | − | |
| 16 | −#ifdef CONFIG_IA64_DEBUG_CMPXCHG | |
| 17 | −# define CMPXCHG_BUGCHECK_DECL int _cmpxchg_bugcheck_count = 128; | |
| 18 | −# define CMPXCHG_BUGCHECK(v) \ | |
| 19 | −do { \ | |
| 20 | − if (_cmpxchg_bugcheck_count-- <= 0) { \ | |
| 21 | − void *ip; \ | |
| 22 | − extern int _printk(const char *fmt, ...); \ | |
| 23 | − ip = (void *) ia64_getreg(_IA64_REG_IP); \ | |
| 24 | − _printk("CMPXCHG_BUGCHECK: stuck at %p on word %p\n", ip, (v));\ | |
| 25 | − break; \ | |
| 26 | − } \ | |
| 27 | −} while (0) | |
| 28 | −#else /* !CONFIG_IA64_DEBUG_CMPXCHG */ | |
| 29 | −# define CMPXCHG_BUGCHECK_DECL | |
| 30 | −# define CMPXCHG_BUGCHECK(v) | |
| 31 | −#endif /* !CONFIG_IA64_DEBUG_CMPXCHG */ | |
| 32 | − | |
| 33 | −#endif /* _ASM_IA64_CMPXCHG_H */ | |
| @@ -1,23 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_CPU_H_ | |
| 3 | −#define _ASM_IA64_CPU_H_ | |
| 4 | − | |
| 5 | −#include <linux/device.h> | |
| 6 | −#include <linux/cpu.h> | |
| 7 | −#include <linux/topology.h> | |
| 8 | −#include <linux/percpu.h> | |
| 9 | − | |
| 10 | −struct ia64_cpu { | |
| 11 | − struct cpu cpu; | |
| 12 | −}; | |
| 13 | − | |
| 14 | −DECLARE_PER_CPU(struct ia64_cpu, cpu_devices); | |
| 15 | − | |
| 16 | −DECLARE_PER_CPU(int, cpu_state); | |
| 17 | − | |
| 18 | −#ifdef CONFIG_HOTPLUG_CPU | |
| 19 | −extern int arch_register_cpu(int num); | |
| 20 | −extern void arch_unregister_cpu(int); | |
| 21 | −#endif | |
| 22 | − | |
| 23 | −#endif /* _ASM_IA64_CPU_H_ */ | |
| @@ -1,21 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0-or-later */ | |
| 2 | −/* | |
| 3 | − * Definitions for measuring cputime on ia64 machines. | |
| 4 | − * | |
| 5 | − * Based on <asm-powerpc/cputime.h>. | |
| 6 | − * | |
| 7 | − * Copyright (C) 2007 FUJITSU LIMITED | |
| 8 | − * Copyright (C) 2007 Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> | |
| 9 | − * | |
| 10 | − * If we have CONFIG_VIRT_CPU_ACCOUNTING_NATIVE, we measure cpu time in nsec. | |
| 11 | − * Otherwise we measure cpu time in jiffies using the generic definitions. | |
| 12 | − */ | |
| 13 | − | |
| 14 | −#ifndef __IA64_CPUTIME_H | |
| 15 | −#define __IA64_CPUTIME_H | |
| 16 | − | |
| 17 | −#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE | |
| 18 | −extern void arch_vtime_task_switch(struct task_struct *tsk); | |
| 19 | −#endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */ | |
| 20 | − | |
| 21 | −#endif /* __IA64_CPUTIME_H */ | |
| @@ -1,18 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_CURRENT_H | |
| 3 | −#define _ASM_IA64_CURRENT_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Modified 1998-2000 | |
| 7 | − * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co | |
| 8 | − */ | |
| 9 | − | |
| 10 | −#include <asm/intrinsics.h> | |
| 11 | − | |
| 12 | −/* | |
| 13 | − * In kernel mode, thread pointer (r13) is used to point to the current task | |
| 14 | − * structure. | |
| 15 | − */ | |
| 16 | −#define current ((struct task_struct *) ia64_getreg(_IA64_REG_TP)) | |
| 17 | − | |
| 18 | −#endif /* _ASM_IA64_CURRENT_H */ | |
| @@ -1,16 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef ASM_IA64_CYCLONE_H | |
| 3 | −#define ASM_IA64_CYCLONE_H | |
| 4 | − | |
| 5 | −#ifdef CONFIG_IA64_CYCLONE | |
| 6 | −extern int use_cyclone; | |
| 7 | −extern void __init cyclone_setup(void); | |
| 8 | −#else /* CONFIG_IA64_CYCLONE */ | |
| 9 | −#define use_cyclone 0 | |
| 10 | −static inline void cyclone_setup(void) | |
| 11 | −{ | |
| 12 | − printk(KERN_ERR "Cyclone Counter: System not configured" | |
| 13 | − " w/ CONFIG_IA64_CYCLONE.\n"); | |
| 14 | −} | |
| 15 | −#endif /* CONFIG_IA64_CYCLONE */ | |
| 16 | −#endif /* !ASM_IA64_CYCLONE_H */ | |
| @@ -1,89 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_DELAY_H | |
| 3 | −#define _ASM_IA64_DELAY_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Delay routines using a pre-computed "cycles/usec" value. | |
| 7 | − * | |
| 8 | − * Copyright (C) 1998, 1999 Hewlett-Packard Co | |
| 9 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 10 | − * Copyright (C) 1999 VA Linux Systems | |
| 11 | − * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> | |
| 12 | − * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> | |
| 13 | − * Copyright (C) 1999 Don Dugger <don.dugger@intel.com> | |
| 14 | − */ | |
| 15 | − | |
| 16 | −#include <linux/kernel.h> | |
| 17 | −#include <linux/sched.h> | |
| 18 | −#include <linux/compiler.h> | |
| 19 | − | |
| 20 | −#include <asm/intrinsics.h> | |
| 21 | −#include <asm/processor.h> | |
| 22 | − | |
| 23 | −static __inline__ void | |
| 24 | −ia64_set_itm (unsigned long val) | |
| 25 | −{ | |
| 26 | − ia64_setreg(_IA64_REG_CR_ITM, val); | |
| 27 | − ia64_srlz_d(); | |
| 28 | −} | |
| 29 | − | |
| 30 | −static __inline__ unsigned long | |
| 31 | −ia64_get_itm (void) | |
| 32 | −{ | |
| 33 | − unsigned long result; | |
| 34 | − | |
| 35 | − result = ia64_getreg(_IA64_REG_CR_ITM); | |
| 36 | − ia64_srlz_d(); | |
| 37 | − return result; | |
| 38 | −} | |
| 39 | − | |
| 40 | −static __inline__ void | |
| 41 | −ia64_set_itv (unsigned long val) | |
| 42 | −{ | |
| 43 | − ia64_setreg(_IA64_REG_CR_ITV, val); | |
| 44 | − ia64_srlz_d(); | |
| 45 | −} | |
| 46 | − | |
| 47 | −static __inline__ unsigned long | |
| 48 | −ia64_get_itv (void) | |
| 49 | −{ | |
| 50 | − return ia64_getreg(_IA64_REG_CR_ITV); | |
| 51 | −} | |
| 52 | − | |
| 53 | −static __inline__ void | |
| 54 | −ia64_set_itc (unsigned long val) | |
| 55 | −{ | |
| 56 | − ia64_setreg(_IA64_REG_AR_ITC, val); | |
| 57 | − ia64_srlz_d(); | |
| 58 | −} | |
| 59 | − | |
| 60 | −static __inline__ unsigned long | |
| 61 | −ia64_get_itc (void) | |
| 62 | −{ | |
| 63 | − unsigned long result; | |
| 64 | − | |
| 65 | − result = ia64_getreg(_IA64_REG_AR_ITC); | |
| 66 | − ia64_barrier(); | |
| 67 | −#ifdef CONFIG_ITANIUM | |
| 68 | − while (unlikely((__s32) result == -1)) { | |
| 69 | − result = ia64_getreg(_IA64_REG_AR_ITC); | |
| 70 | − ia64_barrier(); | |
| 71 | − } | |
| 72 | −#endif | |
| 73 | − return result; | |
| 74 | −} | |
| 75 | − | |
| 76 | −extern void ia64_delay_loop (unsigned long loops); | |
| 77 | − | |
| 78 | −static __inline__ void | |
| 79 | −__delay (unsigned long loops) | |
| 80 | −{ | |
| 81 | − if (unlikely(loops < 1)) | |
| 82 | − return; | |
| 83 | − | |
| 84 | − ia64_delay_loop (loops - 1); | |
| 85 | −} | |
| 86 | − | |
| 87 | −extern void udelay (unsigned long usecs); | |
| 88 | − | |
| 89 | −#endif /* _ASM_IA64_DELAY_H */ | |
| @@ -1,14 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0-only */ | |
| 2 | −/* | |
| 3 | − * Arch specific extensions to struct device | |
| 4 | − */ | |
| 5 | −#ifndef _ASM_IA64_DEVICE_H | |
| 6 | −#define _ASM_IA64_DEVICE_H | |
| 7 | − | |
| 8 | −struct dev_archdata { | |
| 9 | −}; | |
| 10 | − | |
| 11 | −struct pdev_archdata { | |
| 12 | −}; | |
| 13 | − | |
| 14 | −#endif /* _ASM_IA64_DEVICE_H */ | |
| @@ -1 +0,0 @@ | ||
| 1 | −#include <asm-generic/div64.h> | |
| @@ -1,16 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_DMA_MAPPING_H | |
| 3 | −#define _ASM_IA64_DMA_MAPPING_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Copyright (C) 2003-2004 Hewlett-Packard Co | |
| 7 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 8 | − */ | |
| 9 | −extern const struct dma_map_ops *dma_ops; | |
| 10 | − | |
| 11 | −static inline const struct dma_map_ops *get_arch_dma_ops(void) | |
| 12 | −{ | |
| 13 | − return dma_ops; | |
| 14 | −} | |
| 15 | − | |
| 16 | −#endif /* _ASM_IA64_DMA_MAPPING_H */ | |
| @@ -1,17 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_DMA_H | |
| 3 | −#define _ASM_IA64_DMA_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Copyright (C) 1998-2002 Hewlett-Packard Co | |
| 7 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 8 | − */ | |
| 9 | − | |
| 10 | − | |
| 11 | −#include <asm/io.h> /* need byte IO */ | |
| 12 | − | |
| 13 | −extern unsigned long MAX_DMA_ADDRESS; | |
| 14 | − | |
| 15 | −#define free_dma(x) | |
| 16 | − | |
| 17 | −#endif /* _ASM_IA64_DMA_H */ | |
| @@ -1,15 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_DMI_H | |
| 3 | −#define _ASM_DMI_H 1 | |
| 4 | − | |
| 5 | −#include <linux/slab.h> | |
| 6 | −#include <asm/io.h> | |
| 7 | − | |
| 8 | −/* Use normal IO mappings for DMI */ | |
| 9 | −#define dmi_early_remap ioremap | |
| 10 | −#define dmi_early_unmap(x, l) iounmap(x) | |
| 11 | −#define dmi_remap ioremap | |
| 12 | −#define dmi_unmap iounmap | |
| 13 | −#define dmi_alloc(l) kzalloc(l, GFP_ATOMIC) | |
| 14 | − | |
| 15 | −#endif | |
| @@ -1,11 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_EARLY_IOREMAP_H | |
| 3 | −#define _ASM_IA64_EARLY_IOREMAP_H | |
| 4 | − | |
| 5 | −extern void __iomem * early_ioremap (unsigned long phys_addr, unsigned long size); | |
| 6 | −#define early_memremap(phys_addr, size) early_ioremap(phys_addr, size) | |
| 7 | − | |
| 8 | −extern void early_iounmap (volatile void __iomem *addr, unsigned long size); | |
| 9 | −#define early_memunmap(addr, size) early_iounmap(addr, size) | |
| 10 | − | |
| 11 | −#endif | |
| @@ -1,13 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_EFI_H | |
| 3 | −#define _ASM_EFI_H | |
| 4 | − | |
| 5 | −typedef int (*efi_freemem_callback_t) (u64 start, u64 end, void *arg); | |
| 6 | − | |
| 7 | −void *efi_get_pal_addr(void); | |
| 8 | −void efi_map_pal_code(void); | |
| 9 | −void efi_memmap_walk(efi_freemem_callback_t, void *); | |
| 10 | −void efi_memmap_walk_uc(efi_freemem_callback_t, void *); | |
| 11 | −void efi_gettimeofday(struct timespec64 *ts); | |
| 12 | − | |
| 13 | −#endif | |
| @@ -1,233 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_ELF_H | |
| 3 | −#define _ASM_IA64_ELF_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * ELF-specific definitions. | |
| 7 | − * | |
| 8 | − * Copyright (C) 1998-1999, 2002-2004 Hewlett-Packard Co | |
| 9 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 10 | − */ | |
| 11 | − | |
| 12 | − | |
| 13 | −#include <asm/fpu.h> | |
| 14 | −#include <asm/page.h> | |
| 15 | −#include <asm/auxvec.h> | |
| 16 | − | |
| 17 | −/* | |
| 18 | − * This is used to ensure we don't load something for the wrong architecture. | |
| 19 | − */ | |
| 20 | −#define elf_check_arch(x) ((x)->e_machine == EM_IA_64) | |
| 21 | − | |
| 22 | −/* | |
| 23 | − * These are used to set parameters in the core dumps. | |
| 24 | − */ | |
| 25 | −#define ELF_CLASS ELFCLASS64 | |
| 26 | −#define ELF_DATA ELFDATA2LSB | |
| 27 | −#define ELF_ARCH EM_IA_64 | |
| 28 | − | |
| 29 | −#define CORE_DUMP_USE_REGSET | |
| 30 | − | |
| 31 | −/* Least-significant four bits of ELF header's e_flags are OS-specific. The bits are | |
| 32 | − interpreted as follows by Linux: */ | |
| 33 | −#define EF_IA_64_LINUX_EXECUTABLE_STACK 0x1 /* is stack (& heap) executable by default? */ | |
| 34 | − | |
| 35 | −#define ELF_EXEC_PAGESIZE PAGE_SIZE | |
| 36 | − | |
| 37 | −/* | |
| 38 | − * This is the location that an ET_DYN program is loaded if exec'ed. | |
| 39 | − * Typical use of this is to invoke "./ld.so someprog" to test out a | |
| 40 | − * new version of the loader. We need to make sure that it is out of | |
| 41 | − * the way of the program that it will "exec", and that there is | |
| 42 | − * sufficient room for the brk. | |
| 43 | − */ | |
| 44 | −#define ELF_ET_DYN_BASE (TASK_UNMAPPED_BASE + 0x800000000UL) | |
| 45 | − | |
| 46 | −#define PT_IA_64_UNWIND 0x70000001 | |
| 47 | − | |
| 48 | −/* IA-64 relocations: */ | |
| 49 | −#define R_IA64_NONE 0x00 /* none */ | |
| 50 | −#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ | |
| 51 | −#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ | |
| 52 | −#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ | |
| 53 | −#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ | |
| 54 | −#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ | |
| 55 | −#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ | |
| 56 | −#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ | |
| 57 | −#define R_IA64_GPREL22 0x2a /* @gprel(sym+add), add imm22 */ | |
| 58 | −#define R_IA64_GPREL64I 0x2b /* @gprel(sym+add), mov imm64 */ | |
| 59 | −#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym+add), data4 MSB */ | |
| 60 | −#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym+add), data4 LSB */ | |
| 61 | −#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym+add), data8 MSB */ | |
| 62 | −#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym+add), data8 LSB */ | |
| 63 | −#define R_IA64_LTOFF22 0x32 /* @ltoff(sym+add), add imm22 */ | |
| 64 | −#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym+add), mov imm64 */ | |
| 65 | −#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym+add), add imm22 */ | |
| 66 | −#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym+add), mov imm64 */ | |
| 67 | −#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym+add), data8 MSB */ | |
| 68 | −#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym+add), data8 LSB */ | |
| 69 | −#define R_IA64_FPTR64I 0x43 /* @fptr(sym+add), mov imm64 */ | |
| 70 | −#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym+add), data4 MSB */ | |
| 71 | −#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym+add), data4 LSB */ | |
| 72 | −#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym+add), data8 MSB */ | |
| 73 | −#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym+add), data8 LSB */ | |
| 74 | −#define R_IA64_PCREL60B 0x48 /* @pcrel(sym+add), brl */ | |
| 75 | −#define R_IA64_PCREL21B 0x49 /* @pcrel(sym+add), ptb, call */ | |
| 76 | −#define R_IA64_PCREL21M 0x4a /* @pcrel(sym+add), chk.s */ | |
| 77 | −#define R_IA64_PCREL21F 0x4b /* @pcrel(sym+add), fchkf */ | |
| 78 | −#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym+add), data4 MSB */ | |
| 79 | −#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym+add), data4 LSB */ | |
| 80 | −#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym+add), data8 MSB */ | |
| 81 | −#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym+add), data8 LSB */ | |
| 82 | −#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ | |
| 83 | −#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ | |
| 84 | −#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), 4 MSB */ | |
| 85 | −#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), 4 LSB */ | |
| 86 | −#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), 8 MSB */ | |
| 87 | −#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), 8 LSB */ | |
| 88 | −#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym+add), data4 MSB */ | |
| 89 | −#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym+add), data4 LSB */ | |
| 90 | −#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym+add), data8 MSB */ | |
| 91 | −#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym+add), data8 LSB */ | |
| 92 | −#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym+add), data4 MSB */ | |
| 93 | −#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym+add), data4 LSB */ | |
| 94 | −#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym+add), data8 MSB */ | |
| 95 | −#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym+add), data8 LSB */ | |
| 96 | −#define R_IA64_REL32MSB 0x6c /* data 4 + REL */ | |
| 97 | −#define R_IA64_REL32LSB 0x6d /* data 4 + REL */ | |
| 98 | −#define R_IA64_REL64MSB 0x6e /* data 8 + REL */ | |
| 99 | −#define R_IA64_REL64LSB 0x6f /* data 8 + REL */ | |
| 100 | −#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */ | |
| 101 | −#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */ | |
| 102 | −#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */ | |
| 103 | −#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */ | |
| 104 | −#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym+add), ptb, call */ | |
| 105 | −#define R_IA64_PCREL22 0x7a /* @pcrel(sym+add), imm22 */ | |
| 106 | −#define R_IA64_PCREL64I 0x7b /* @pcrel(sym+add), imm64 */ | |
| 107 | −#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ | |
| 108 | −#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ | |
| 109 | −#define R_IA64_COPY 0x84 /* dynamic reloc, data copy */ | |
| 110 | −#define R_IA64_SUB 0x85 /* -symbol + addend, add imm22 */ | |
| 111 | −#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ | |
| 112 | −#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ | |
| 113 | −#define R_IA64_TPREL14 0x91 /* @tprel(sym+add), add imm14 */ | |
| 114 | −#define R_IA64_TPREL22 0x92 /* @tprel(sym+add), add imm22 */ | |
| 115 | −#define R_IA64_TPREL64I 0x93 /* @tprel(sym+add), add imm64 */ | |
| 116 | −#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym+add), data8 MSB */ | |
| 117 | −#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym+add), data8 LSB */ | |
| 118 | −#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), add imm22 */ | |
| 119 | −#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym+add), data8 MSB */ | |
| 120 | −#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym+add), data8 LSB */ | |
| 121 | −#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(s+a)), imm22 */ | |
| 122 | −#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym+add), imm14 */ | |
| 123 | −#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym+add), imm22 */ | |
| 124 | −#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym+add), imm64 */ | |
| 125 | −#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym+add), data4 MSB */ | |
| 126 | −#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym+add), data4 LSB */ | |
| 127 | −#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym+add), data8 MSB */ | |
| 128 | −#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym+add), data8 LSB */ | |
| 129 | −#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ | |
| 130 | − | |
| 131 | −/* IA-64 specific section flags: */ | |
| 132 | −#define SHF_IA_64_SHORT 0x10000000 /* section near gp */ | |
| 133 | − | |
| 134 | −/* | |
| 135 | − * We use (abuse?) this macro to insert the (empty) vm_area that is | |
| 136 | − * used to map the register backing store. I don't see any better | |
| 137 | − * place to do this, but we should discuss this with Linus once we can | |
| 138 | − * talk to him... | |
| 139 | − */ | |
| 140 | −extern void ia64_init_addr_space (void); | |
| 141 | −#define ELF_PLAT_INIT(_r, load_addr) ia64_init_addr_space() | |
| 142 | − | |
| 143 | −/* ELF register definitions. This is needed for core dump support. */ | |
| 144 | − | |
| 145 | −/* | |
| 146 | − * elf_gregset_t contains the application-level state in the following order: | |
| 147 | − * r0-r31 | |
| 148 | − * NaT bits (for r0-r31; bit N == 1 iff rN is a NaT) | |
| 149 | − * predicate registers (p0-p63) | |
| 150 | − * b0-b7 | |
| 151 | − * ip cfm psr | |
| 152 | − * ar.rsc ar.bsp ar.bspstore ar.rnat | |
| 153 | − * ar.ccv ar.unat ar.fpsr ar.pfs ar.lc ar.ec ar.csd ar.ssd | |
| 154 | − */ | |
| 155 | −#define ELF_NGREG 128 /* we really need just 72 but let's leave some headroom... */ | |
| 156 | −#define ELF_NFPREG 128 /* f0 and f1 could be omitted, but so what... */ | |
| 157 | − | |
| 158 | −/* elf_gregset_t register offsets */ | |
| 159 | −#define ELF_GR_0_OFFSET 0 | |
| 160 | −#define ELF_NAT_OFFSET (32 * sizeof(elf_greg_t)) | |
| 161 | −#define ELF_PR_OFFSET (33 * sizeof(elf_greg_t)) | |
| 162 | −#define ELF_BR_0_OFFSET (34 * sizeof(elf_greg_t)) | |
| 163 | −#define ELF_CR_IIP_OFFSET (42 * sizeof(elf_greg_t)) | |
| 164 | −#define ELF_CFM_OFFSET (43 * sizeof(elf_greg_t)) | |
| 165 | −#define ELF_CR_IPSR_OFFSET (44 * sizeof(elf_greg_t)) | |
| 166 | −#define ELF_GR_OFFSET(i) (ELF_GR_0_OFFSET + i * sizeof(elf_greg_t)) | |
| 167 | −#define ELF_BR_OFFSET(i) (ELF_BR_0_OFFSET + i * sizeof(elf_greg_t)) | |
| 168 | −#define ELF_AR_RSC_OFFSET (45 * sizeof(elf_greg_t)) | |
| 169 | −#define ELF_AR_BSP_OFFSET (46 * sizeof(elf_greg_t)) | |
| 170 | −#define ELF_AR_BSPSTORE_OFFSET (47 * sizeof(elf_greg_t)) | |
| 171 | −#define ELF_AR_RNAT_OFFSET (48 * sizeof(elf_greg_t)) | |
| 172 | −#define ELF_AR_CCV_OFFSET (49 * sizeof(elf_greg_t)) | |
| 173 | −#define ELF_AR_UNAT_OFFSET (50 * sizeof(elf_greg_t)) | |
| 174 | −#define ELF_AR_FPSR_OFFSET (51 * sizeof(elf_greg_t)) | |
| 175 | −#define ELF_AR_PFS_OFFSET (52 * sizeof(elf_greg_t)) | |
| 176 | −#define ELF_AR_LC_OFFSET (53 * sizeof(elf_greg_t)) | |
| 177 | −#define ELF_AR_EC_OFFSET (54 * sizeof(elf_greg_t)) | |
| 178 | −#define ELF_AR_CSD_OFFSET (55 * sizeof(elf_greg_t)) | |
| 179 | −#define ELF_AR_SSD_OFFSET (56 * sizeof(elf_greg_t)) | |
| 180 | −#define ELF_AR_END_OFFSET (57 * sizeof(elf_greg_t)) | |
| 181 | − | |
| 182 | −typedef unsigned long elf_greg_t; | |
| 183 | −typedef elf_greg_t elf_gregset_t[ELF_NGREG]; | |
| 184 | − | |
| 185 | −typedef struct ia64_fpreg elf_fpreg_t; | |
| 186 | −typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; | |
| 187 | − | |
| 188 | − | |
| 189 | − | |
| 190 | −struct pt_regs; /* forward declaration... */ | |
| 191 | −extern void ia64_elf_core_copy_regs (struct pt_regs *src, elf_gregset_t dst); | |
| 192 | −#define ELF_CORE_COPY_REGS(_dest,_regs) ia64_elf_core_copy_regs(_regs, _dest); | |
| 193 | − | |
| 194 | −/* This macro yields a bitmask that programs can use to figure out | |
| 195 | − what instruction set this CPU supports. */ | |
| 196 | −#define ELF_HWCAP 0 | |
| 197 | − | |
| 198 | −/* This macro yields a string that ld.so will use to load | |
| 199 | − implementation specific libraries for optimization. Not terribly | |
| 200 | − relevant until we have real hardware to play with... */ | |
| 201 | −#define ELF_PLATFORM NULL | |
| 202 | − | |
| 203 | −#define elf_read_implies_exec(ex, executable_stack) \ | |
| 204 | − ((executable_stack!=EXSTACK_DISABLE_X) && ((ex).e_flags & EF_IA_64_LINUX_EXECUTABLE_STACK) != 0) | |
| 205 | − | |
| 206 | −struct task_struct; | |
| 207 | − | |
| 208 | −#define GATE_EHDR ((const struct elfhdr *) GATE_ADDR) | |
| 209 | − | |
| 210 | −/* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */ | |
| 211 | −#define ARCH_DLINFO \ | |
| 212 | −do { \ | |
| 213 | − extern char __kernel_syscall_via_epc[]; \ | |
| 214 | − NEW_AUX_ENT(AT_SYSINFO, (unsigned long) __kernel_syscall_via_epc); \ | |
| 215 | − NEW_AUX_ENT(AT_SYSINFO_EHDR, (unsigned long) GATE_EHDR); \ | |
| 216 | −} while (0) | |
| 217 | − | |
| 218 | −/* | |
| 219 | − * format for entries in the Global Offset Table | |
| 220 | − */ | |
| 221 | −struct got_entry { | |
| 222 | − uint64_t val; | |
| 223 | −}; | |
| 224 | − | |
| 225 | −/* | |
| 226 | − * Layout of the Function Descriptor | |
| 227 | − */ | |
| 228 | −struct fdesc { | |
| 229 | − uint64_t addr; | |
| 230 | − uint64_t gp; | |
| 231 | −}; | |
| 232 | − | |
| 233 | −#endif /* _ASM_IA64_ELF_H */ | |
| @@ -1,6 +0,0 @@ | ||
| 1 | −#ifndef _ASM_EMERGENCY_RESTART_H | |
| 2 | −#define _ASM_EMERGENCY_RESTART_H | |
| 3 | − | |
| 4 | −#include <asm-generic/emergency-restart.h> | |
| 5 | − | |
| 6 | −#endif /* _ASM_EMERGENCY_RESTART_H */ | |
| @@ -1,30 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −/* | |
| 3 | − * ESI service calls. | |
| 4 | − * | |
| 5 | − * Copyright (c) Copyright 2005-2006 Hewlett-Packard Development Company, L.P. | |
| 6 | − * Alex Williamson <alex.williamson@hp.com> | |
| 7 | − */ | |
| 8 | −#ifndef esi_h | |
| 9 | −#define esi_h | |
| 10 | − | |
| 11 | −#include <linux/efi.h> | |
| 12 | − | |
| 13 | −#define ESI_QUERY 0x00000001 | |
| 14 | −#define ESI_OPEN_HANDLE 0x02000000 | |
| 15 | −#define ESI_CLOSE_HANDLE 0x02000001 | |
| 16 | − | |
| 17 | −enum esi_proc_type { | |
| 18 | − ESI_PROC_SERIALIZED, /* calls need to be serialized */ | |
| 19 | − ESI_PROC_MP_SAFE, /* MP-safe, but not reentrant */ | |
| 20 | − ESI_PROC_REENTRANT /* MP-safe and reentrant */ | |
| 21 | −}; | |
| 22 | − | |
| 23 | −extern struct ia64_sal_retval esi_call_phys (void *, u64 *); | |
| 24 | −extern int ia64_esi_call(efi_guid_t, struct ia64_sal_retval *, | |
| 25 | − enum esi_proc_type, | |
| 26 | − u64, u64, u64, u64, u64, u64, u64, u64); | |
| 27 | −extern int ia64_esi_call_phys(efi_guid_t, struct ia64_sal_retval *, u64, u64, | |
| 28 | − u64, u64, u64, u64, u64, u64); | |
| 29 | − | |
| 30 | −#endif /* esi_h */ | |
| @@ -1,23 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0-only */ | |
| 2 | −#ifndef __ASM_EXCEPTION_H | |
| 3 | −#define __ASM_EXCEPTION_H | |
| 4 | − | |
| 5 | −struct pt_regs; | |
| 6 | −struct exception_table_entry; | |
| 7 | − | |
| 8 | −extern void ia64_handle_exception(struct pt_regs *regs, | |
| 9 | − const struct exception_table_entry *e); | |
| 10 | − | |
| 11 | −#define ia64_done_with_exception(regs) \ | |
| 12 | −({ \ | |
| 13 | − int __ex_ret = 0; \ | |
| 14 | − const struct exception_table_entry *e; \ | |
| 15 | − e = search_exception_tables((regs)->cr_iip + ia64_psr(regs)->ri); \ | |
| 16 | − if (e) { \ | |
| 17 | − ia64_handle_exception(regs, e); \ | |
| 18 | − __ex_ret = 1; \ | |
| 19 | − } \ | |
| 20 | − __ex_ret; \ | |
| 21 | −}) | |
| 22 | − | |
| 23 | −#endif /* __ASM_EXCEPTION_H */ | |
| @@ -1,12 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_EXTABLE_H | |
| 3 | −#define _ASM_IA64_EXTABLE_H | |
| 4 | − | |
| 5 | −#define ARCH_HAS_RELATIVE_EXTABLE | |
| 6 | − | |
| 7 | −struct exception_table_entry { | |
| 8 | − int insn; /* location-relative address of insn this fixup is for */ | |
| 9 | − int fixup; /* location-relative continuation addr.; if bit 2 is set, r9 is set to 0 */ | |
| 10 | −}; | |
| 11 | − | |
| 12 | −#endif | |
| @@ -1,43 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_FB_H_ | |
| 3 | −#define _ASM_FB_H_ | |
| 4 | − | |
| 5 | −#include <linux/compiler.h> | |
| 6 | −#include <linux/efi.h> | |
| 7 | −#include <linux/string.h> | |
| 8 | − | |
| 9 | −#include <asm/page.h> | |
| 10 | − | |
| 11 | −struct file; | |
| 12 | − | |
| 13 | −static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma, | |
| 14 | − unsigned long off) | |
| 15 | −{ | |
| 16 | − if (efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start)) | |
| 17 | − vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); | |
| 18 | − else | |
| 19 | − vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
| 20 | −} | |
| 21 | −#define fb_pgprotect fb_pgprotect | |
| 22 | − | |
| 23 | −static inline void fb_memcpy_fromio(void *to, const volatile void __iomem *from, size_t n) | |
| 24 | −{ | |
| 25 | − memcpy(to, (void __force *)from, n); | |
| 26 | −} | |
| 27 | −#define fb_memcpy_fromio fb_memcpy_fromio | |
| 28 | − | |
| 29 | −static inline void fb_memcpy_toio(volatile void __iomem *to, const void *from, size_t n) | |
| 30 | −{ | |
| 31 | − memcpy((void __force *)to, from, n); | |
| 32 | −} | |
| 33 | −#define fb_memcpy_toio fb_memcpy_toio | |
| 34 | − | |
| 35 | −static inline void fb_memset_io(volatile void __iomem *addr, int c, size_t n) | |
| 36 | −{ | |
| 37 | − memset((void __force *)addr, c, n); | |
| 38 | −} | |
| 39 | −#define fb_memset fb_memset_io | |
| 40 | − | |
| 41 | −#include <asm-generic/fb.h> | |
| 42 | − | |
| 43 | −#endif /* _ASM_FB_H_ */ | |
| @@ -1,74 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_FPSWA_H | |
| 3 | −#define _ASM_IA64_FPSWA_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Floating-point Software Assist | |
| 7 | − * | |
| 8 | − * Copyright (C) 1999 Intel Corporation. | |
| 9 | − * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> | |
| 10 | − * Copyright (C) 1999 Goutham Rao <goutham.rao@intel.com> | |
| 11 | − */ | |
| 12 | − | |
| 13 | −typedef struct { | |
| 14 | − /* 4 * 128 bits */ | |
| 15 | − unsigned long fp_lp[4*2]; | |
| 16 | −} fp_state_low_preserved_t; | |
| 17 | − | |
| 18 | −typedef struct { | |
| 19 | − /* 10 * 128 bits */ | |
| 20 | − unsigned long fp_lv[10 * 2]; | |
| 21 | −} fp_state_low_volatile_t; | |
| 22 | − | |
| 23 | −typedef struct { | |
| 24 | − /* 16 * 128 bits */ | |
| 25 | − unsigned long fp_hp[16 * 2]; | |
| 26 | −} fp_state_high_preserved_t; | |
| 27 | − | |
| 28 | −typedef struct { | |
| 29 | − /* 96 * 128 bits */ | |
| 30 | − unsigned long fp_hv[96 * 2]; | |
| 31 | −} fp_state_high_volatile_t; | |
| 32 | − | |
| 33 | −/** | |
| 34 | − * floating point state to be passed to the FP emulation library by | |
| 35 | − * the trap/fault handler | |
| 36 | − */ | |
| 37 | −typedef struct { | |
| 38 | − unsigned long bitmask_low64; | |
| 39 | − unsigned long bitmask_high64; | |
| 40 | − fp_state_low_preserved_t *fp_state_low_preserved; | |
| 41 | − fp_state_low_volatile_t *fp_state_low_volatile; | |
| 42 | − fp_state_high_preserved_t *fp_state_high_preserved; | |
| 43 | − fp_state_high_volatile_t *fp_state_high_volatile; | |
| 44 | −} fp_state_t; | |
| 45 | − | |
| 46 | −typedef struct { | |
| 47 | − unsigned long status; | |
| 48 | − unsigned long err0; | |
| 49 | − unsigned long err1; | |
| 50 | − unsigned long err2; | |
| 51 | −} fpswa_ret_t; | |
| 52 | − | |
| 53 | −/** | |
| 54 | − * function header for the Floating Point software assist | |
| 55 | − * library. This function is invoked by the Floating point software | |
| 56 | − * assist trap/fault handler. | |
| 57 | − */ | |
| 58 | −typedef fpswa_ret_t (*efi_fpswa_t) (unsigned long trap_type, void *bundle, unsigned long *ipsr, | |
| 59 | − unsigned long *fsr, unsigned long *isr, unsigned long *preds, | |
| 60 | − unsigned long *ifs, fp_state_t *fp_state); | |
| 61 | − | |
| 62 | −/** | |
| 63 | − * This is the FPSWA library interface as defined by EFI. We need to pass a | |
| 64 | − * pointer to the interface itself on a call to the assist library | |
| 65 | − */ | |
| 66 | −typedef struct { | |
| 67 | − unsigned int revision; | |
| 68 | − unsigned int reserved; | |
| 69 | − efi_fpswa_t fpswa; | |
| 70 | −} fpswa_interface_t; | |
| 71 | − | |
| 72 | −extern fpswa_interface_t *fpswa_interface; | |
| 73 | − | |
| 74 | −#endif /* _ASM_IA64_FPSWA_H */ | |
| @@ -1,28 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_FTRACE_H | |
| 3 | −#define _ASM_IA64_FTRACE_H | |
| 4 | − | |
| 5 | −#ifdef CONFIG_FUNCTION_TRACER | |
| 6 | −#define MCOUNT_INSN_SIZE 32 /* sizeof mcount call */ | |
| 7 | − | |
| 8 | −#ifndef __ASSEMBLY__ | |
| 9 | −extern void _mcount(unsigned long pfs, unsigned long r1, unsigned long b0, unsigned long r0); | |
| 10 | −#define mcount _mcount | |
| 11 | − | |
| 12 | −/* In IA64, MCOUNT_ADDR is set in link time, so it's not a constant at compile time */ | |
| 13 | −#define MCOUNT_ADDR (((struct fnptr *)mcount)->ip) | |
| 14 | −#define FTRACE_ADDR (((struct fnptr *)ftrace_caller)->ip) | |
| 15 | − | |
| 16 | −static inline unsigned long ftrace_call_adjust(unsigned long addr) | |
| 17 | −{ | |
| 18 | − /* second bundle, insn 2 */ | |
| 19 | − return addr - 0x12; | |
| 20 | −} | |
| 21 | − | |
| 22 | −struct dyn_arch_ftrace { | |
| 23 | −}; | |
| 24 | −#endif | |
| 25 | − | |
| 26 | −#endif /* CONFIG_FUNCTION_TRACER */ | |
| 27 | − | |
| 28 | −#endif /* _ASM_IA64_FTRACE_H */ | |
| @@ -1,109 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_FUTEX_H | |
| 3 | −#define _ASM_FUTEX_H | |
| 4 | − | |
| 5 | −#include <linux/futex.h> | |
| 6 | −#include <linux/uaccess.h> | |
| 7 | −#include <asm/errno.h> | |
| 8 | − | |
| 9 | −#define __futex_atomic_op1(insn, ret, oldval, uaddr, oparg) \ | |
| 10 | −do { \ | |
| 11 | − register unsigned long r8 __asm ("r8") = 0; \ | |
| 12 | − __asm__ __volatile__( \ | |
| 13 | − " mf;; \n" \ | |
| 14 | − "[1:] " insn ";; \n" \ | |
| 15 | − " .xdata4 \"__ex_table\", 1b-., 2f-. \n" \ | |
| 16 | − "[2:]" \ | |
| 17 | − : "+r" (r8), "=r" (oldval) \ | |
| 18 | − : "r" (uaddr), "r" (oparg) \ | |
| 19 | − : "memory"); \ | |
| 20 | − ret = r8; \ | |
| 21 | −} while (0) | |
| 22 | − | |
| 23 | −#define __futex_atomic_op2(insn, ret, oldval, uaddr, oparg) \ | |
| 24 | −do { \ | |
| 25 | − register unsigned long r8 __asm ("r8") = 0; \ | |
| 26 | − int val, newval; \ | |
| 27 | − do { \ | |
| 28 | − __asm__ __volatile__( \ | |
| 29 | − " mf;; \n" \ | |
| 30 | − "[1:] ld4 %3=[%4];; \n" \ | |
| 31 | − " mov %2=%3 \n" \ | |
| 32 | − insn ";; \n" \ | |
| 33 | − " mov ar.ccv=%2;; \n" \ | |
| 34 | − "[2:] cmpxchg4.acq %1=[%4],%3,ar.ccv;; \n" \ | |
| 35 | − " .xdata4 \"__ex_table\", 1b-., 3f-.\n" \ | |
| 36 | − " .xdata4 \"__ex_table\", 2b-., 3f-.\n" \ | |
| 37 | − "[3:]" \ | |
| 38 | − : "+r" (r8), "=r" (val), "=&r" (oldval), \ | |
| 39 | − "=&r" (newval) \ | |
| 40 | − : "r" (uaddr), "r" (oparg) \ | |
| 41 | − : "memory"); \ | |
| 42 | − if (unlikely (r8)) \ | |
| 43 | − break; \ | |
| 44 | − } while (unlikely (val != oldval)); \ | |
| 45 | − ret = r8; \ | |
| 46 | −} while (0) | |
| 47 | − | |
| 48 | −static inline int | |
| 49 | −arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr) | |
| 50 | −{ | |
| 51 | − int oldval = 0, ret; | |
| 52 | − | |
| 53 | − if (!access_ok(uaddr, sizeof(u32))) | |
| 54 | − return -EFAULT; | |
| 55 | − | |
| 56 | − switch (op) { | |
| 57 | − case FUTEX_OP_SET: | |
| 58 | − __futex_atomic_op1("xchg4 %1=[%2],%3", ret, oldval, uaddr, | |
| 59 | − oparg); | |
| 60 | − break; | |
| 61 | − case FUTEX_OP_ADD: | |
| 62 | − __futex_atomic_op2("add %3=%3,%5", ret, oldval, uaddr, oparg); | |
| 63 | − break; | |
| 64 | − case FUTEX_OP_OR: | |
| 65 | − __futex_atomic_op2("or %3=%3,%5", ret, oldval, uaddr, oparg); | |
| 66 | − break; | |
| 67 | − case FUTEX_OP_ANDN: | |
| 68 | − __futex_atomic_op2("and %3=%3,%5", ret, oldval, uaddr, | |
| 69 | − ~oparg); | |
| 70 | − break; | |
| 71 | − case FUTEX_OP_XOR: | |
| 72 | − __futex_atomic_op2("xor %3=%3,%5", ret, oldval, uaddr, oparg); | |
| 73 | − break; | |
| 74 | − default: | |
| 75 | − ret = -ENOSYS; | |
| 76 | − } | |
| 77 | − | |
| 78 | − if (!ret) | |
| 79 | − *oval = oldval; | |
| 80 | − | |
| 81 | − return ret; | |
| 82 | −} | |
| 83 | − | |
| 84 | −static inline int | |
| 85 | −futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, | |
| 86 | − u32 oldval, u32 newval) | |
| 87 | −{ | |
| 88 | − if (!access_ok(uaddr, sizeof(u32))) | |
| 89 | − return -EFAULT; | |
| 90 | − | |
| 91 | − { | |
| 92 | − register unsigned long r8 __asm ("r8") = 0; | |
| 93 | − unsigned long prev; | |
| 94 | − __asm__ __volatile__( | |
| 95 | − " mf;; \n" | |
| 96 | − " mov ar.ccv=%4;; \n" | |
| 97 | − "[1:] cmpxchg4.acq %1=[%2],%3,ar.ccv \n" | |
| 98 | − " .xdata4 \"__ex_table\", 1b-., 2f-. \n" | |
| 99 | − "[2:]" | |
| 100 | − : "+r" (r8), "=&r" (prev) | |
| 101 | − : "r" (uaddr), "r" (newval), | |
| 102 | − "rO" ((long) (unsigned) oldval) | |
| 103 | − : "memory"); | |
| 104 | − *uval = prev; | |
| 105 | − return r8; | |
| 106 | − } | |
| 107 | −} | |
| 108 | − | |
| 109 | −#endif /* _ASM_FUTEX_H */ | |
| @@ -1,13 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −/* | |
| 3 | − * | |
| 4 | − * Copyright (C) 2002,2003 Jun Nakajima <jun.nakajima@intel.com> | |
| 5 | − * Copyright (C) 2002,2003 Suresh Siddha <suresh.b.siddha@intel.com> | |
| 6 | − */ | |
| 7 | −#ifndef _ASM_IA64_GCC_INTRIN_H | |
| 8 | −#define _ASM_IA64_GCC_INTRIN_H | |
| 9 | − | |
| 10 | −#include <uapi/asm/gcc_intrin.h> | |
| 11 | − | |
| 12 | −register unsigned long ia64_r13 asm ("r13") __used; | |
| 13 | −#endif /* _ASM_IA64_GCC_INTRIN_H */ | |
| @@ -1,27 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_HARDIRQ_H | |
| 3 | −#define _ASM_IA64_HARDIRQ_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Modified 1998-2002, 2004 Hewlett-Packard Co | |
| 7 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 8 | − */ | |
| 9 | − | |
| 10 | −/* | |
| 11 | − * No irq_cpustat_t for IA-64. The data is held in the per-CPU data structure. | |
| 12 | − */ | |
| 13 | − | |
| 14 | −#define __ARCH_IRQ_STAT 1 | |
| 15 | − | |
| 16 | −#define local_softirq_pending_ref ia64_cpu_info.softirq_pending | |
| 17 | − | |
| 18 | −#include <linux/threads.h> | |
| 19 | −#include <linux/irq.h> | |
| 20 | − | |
| 21 | −#include <asm/processor.h> | |
| 22 | − | |
| 23 | −extern void __iomem *ipi_base_addr; | |
| 24 | − | |
| 25 | −void ack_bad_irq(unsigned int irq); | |
| 26 | − | |
| 27 | −#endif /* _ASM_IA64_HARDIRQ_H */ | |
| @@ -1,34 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_HUGETLB_H | |
| 3 | −#define _ASM_IA64_HUGETLB_H | |
| 4 | − | |
| 5 | −#include <asm/page.h> | |
| 6 | − | |
| 7 | −#define __HAVE_ARCH_HUGETLB_FREE_PGD_RANGE | |
| 8 | −void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr, | |
| 9 | − unsigned long end, unsigned long floor, | |
| 10 | − unsigned long ceiling); | |
| 11 | − | |
| 12 | −#define __HAVE_ARCH_PREPARE_HUGEPAGE_RANGE | |
| 13 | −int prepare_hugepage_range(struct file *file, | |
| 14 | − unsigned long addr, unsigned long len); | |
| 15 | − | |
| 16 | −static inline int is_hugepage_only_range(struct mm_struct *mm, | |
| 17 | − unsigned long addr, | |
| 18 | − unsigned long len) | |
| 19 | −{ | |
| 20 | − return (REGION_NUMBER(addr) == RGN_HPAGE || | |
| 21 | − REGION_NUMBER((addr)+(len)-1) == RGN_HPAGE); | |
| 22 | −} | |
| 23 | −#define is_hugepage_only_range is_hugepage_only_range | |
| 24 | − | |
| 25 | −#define __HAVE_ARCH_HUGE_PTEP_CLEAR_FLUSH | |
| 26 | −static inline pte_t huge_ptep_clear_flush(struct vm_area_struct *vma, | |
| 27 | − unsigned long addr, pte_t *ptep) | |
| 28 | −{ | |
| 29 | − return *ptep; | |
| 30 | −} | |
| 31 | − | |
| 32 | −#include <asm-generic/hugetlb.h> | |
| 33 | − | |
| 34 | −#endif /* _ASM_IA64_HUGETLB_H */ | |
| @@ -1,167 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_HW_IRQ_H | |
| 3 | −#define _ASM_IA64_HW_IRQ_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Copyright (C) 2001-2003 Hewlett-Packard Co | |
| 7 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 8 | − */ | |
| 9 | − | |
| 10 | −#include <linux/interrupt.h> | |
| 11 | −#include <linux/sched.h> | |
| 12 | −#include <linux/types.h> | |
| 13 | −#include <linux/profile.h> | |
| 14 | − | |
| 15 | −#include <asm/ptrace.h> | |
| 16 | −#include <asm/smp.h> | |
| 17 | − | |
| 18 | −typedef u8 ia64_vector; | |
| 19 | − | |
| 20 | −/* | |
| 21 | − * 0 special | |
| 22 | − * | |
| 23 | − * 1,3-14 are reserved from firmware | |
| 24 | − * | |
| 25 | − * 16-255 (vectored external interrupts) are available | |
| 26 | − * | |
| 27 | − * 15 spurious interrupt (see IVR) | |
| 28 | − * | |
| 29 | − * 16 lowest priority, 255 highest priority | |
| 30 | − * | |
| 31 | − * 15 classes of 16 interrupts each. | |
| 32 | − */ | |
| 33 | −#define IA64_MIN_VECTORED_IRQ 16 | |
| 34 | −#define IA64_MAX_VECTORED_IRQ 255 | |
| 35 | −#define IA64_NUM_VECTORS 256 | |
| 36 | − | |
| 37 | −#define AUTO_ASSIGN -1 | |
| 38 | − | |
| 39 | −#define IA64_SPURIOUS_INT_VECTOR 0x0f | |
| 40 | − | |
| 41 | −/* | |
| 42 | − * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI. | |
| 43 | − */ | |
| 44 | −#define IA64_CPEP_VECTOR 0x1c /* corrected platform error polling vector */ | |
| 45 | −#define IA64_CMCP_VECTOR 0x1d /* corrected machine-check polling vector */ | |
| 46 | −#define IA64_CPE_VECTOR 0x1e /* corrected platform error interrupt vector */ | |
| 47 | −#define IA64_CMC_VECTOR 0x1f /* corrected machine-check interrupt vector */ | |
| 48 | −/* | |
| 49 | − * Vectors 0x20-0x2f are reserved for legacy ISA IRQs. | |
| 50 | − * Use vectors 0x30-0xe7 as the default device vector range for ia64. | |
| 51 | − * Platforms may choose to reduce this range in platform_irq_setup, but the | |
| 52 | − * platform range must fall within | |
| 53 | − * [IA64_DEF_FIRST_DEVICE_VECTOR..IA64_DEF_LAST_DEVICE_VECTOR] | |
| 54 | − */ | |
| 55 | −extern int ia64_first_device_vector; | |
| 56 | −extern int ia64_last_device_vector; | |
| 57 | − | |
| 58 | −#ifdef CONFIG_SMP | |
| 59 | −/* Reserve the lower priority vector than device vectors for "move IRQ" IPI */ | |
| 60 | −#define IA64_IRQ_MOVE_VECTOR 0x30 /* "move IRQ" IPI */ | |
| 61 | −#define IA64_DEF_FIRST_DEVICE_VECTOR 0x31 | |
| 62 | −#else | |
| 63 | −#define IA64_DEF_FIRST_DEVICE_VECTOR 0x30 | |
| 64 | −#endif | |
| 65 | −#define IA64_DEF_LAST_DEVICE_VECTOR 0xe7 | |
| 66 | −#define IA64_FIRST_DEVICE_VECTOR ia64_first_device_vector | |
| 67 | −#define IA64_LAST_DEVICE_VECTOR ia64_last_device_vector | |
| 68 | −#define IA64_MAX_DEVICE_VECTORS (IA64_DEF_LAST_DEVICE_VECTOR - IA64_DEF_FIRST_DEVICE_VECTOR + 1) | |
| 69 | −#define IA64_NUM_DEVICE_VECTORS (IA64_LAST_DEVICE_VECTOR - IA64_FIRST_DEVICE_VECTOR + 1) | |
| 70 | − | |
| 71 | −#define IA64_MCA_RENDEZ_VECTOR 0xe8 /* MCA rendez interrupt */ | |
| 72 | −#define IA64_TIMER_VECTOR 0xef /* use highest-prio group 15 interrupt for timer */ | |
| 73 | −#define IA64_MCA_WAKEUP_VECTOR 0xf0 /* MCA wakeup (must be >MCA_RENDEZ_VECTOR) */ | |
| 74 | −#define IA64_IPI_LOCAL_TLB_FLUSH 0xfc /* SMP flush local TLB */ | |
| 75 | −#define IA64_IPI_RESCHEDULE 0xfd /* SMP reschedule */ | |
| 76 | −#define IA64_IPI_VECTOR 0xfe /* inter-processor interrupt vector */ | |
| 77 | − | |
| 78 | −/* Used for encoding redirected irqs */ | |
| 79 | − | |
| 80 | −#define IA64_IRQ_REDIRECTED (1 << 31) | |
| 81 | − | |
| 82 | −/* IA64 inter-cpu interrupt related definitions */ | |
| 83 | − | |
| 84 | −#define IA64_IPI_DEFAULT_BASE_ADDR 0xfee00000 | |
| 85 | − | |
| 86 | −/* Delivery modes for inter-cpu interrupts */ | |
| 87 | −enum { | |
| 88 | − IA64_IPI_DM_INT = 0x0, /* pend an external interrupt */ | |
| 89 | − IA64_IPI_DM_PMI = 0x2, /* pend a PMI */ | |
| 90 | − IA64_IPI_DM_NMI = 0x4, /* pend an NMI (vector 2) */ | |
| 91 | − IA64_IPI_DM_INIT = 0x5, /* pend an INIT interrupt */ | |
| 92 | − IA64_IPI_DM_EXTINT = 0x7, /* pend an 8259-compatible interrupt. */ | |
| 93 | −}; | |
| 94 | − | |
| 95 | −extern __u8 isa_irq_to_vector_map[16]; | |
| 96 | −#define isa_irq_to_vector(x) isa_irq_to_vector_map[(x)] | |
| 97 | − | |
| 98 | −struct irq_cfg { | |
| 99 | − ia64_vector vector; | |
| 100 | − cpumask_t domain; | |
| 101 | − cpumask_t old_domain; | |
| 102 | − unsigned move_cleanup_count; | |
| 103 | − u8 move_in_progress : 1; | |
| 104 | −}; | |
| 105 | −extern spinlock_t vector_lock; | |
| 106 | −extern struct irq_cfg irq_cfg[NR_IRQS]; | |
| 107 | −#define irq_to_domain(x) irq_cfg[(x)].domain | |
| 108 | −DECLARE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq); | |
| 109 | − | |
| 110 | −extern struct irq_chip irq_type_ia64_lsapic; /* CPU-internal interrupt controller */ | |
| 111 | − | |
| 112 | −#define ia64_register_ipi ia64_native_register_ipi | |
| 113 | −#define assign_irq_vector ia64_native_assign_irq_vector | |
| 114 | −#define free_irq_vector ia64_native_free_irq_vector | |
| 115 | −#define ia64_resend_irq ia64_native_resend_irq | |
| 116 | − | |
| 117 | −extern void ia64_native_register_ipi(void); | |
| 118 | −extern int bind_irq_vector(int irq, int vector, cpumask_t domain); | |
| 119 | −extern int ia64_native_assign_irq_vector (int irq); /* allocate a free vector */ | |
| 120 | −extern void ia64_native_free_irq_vector (int vector); | |
| 121 | −extern int reserve_irq_vector (int vector); | |
| 122 | −extern void __setup_vector_irq(int cpu); | |
| 123 | −extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect); | |
| 124 | −extern void destroy_and_reserve_irq (unsigned int irq); | |
| 125 | − | |
| 126 | −#ifdef CONFIG_SMP | |
| 127 | −extern int irq_prepare_move(int irq, int cpu); | |
| 128 | −extern void irq_complete_move(unsigned int irq); | |
| 129 | −#else | |
| 130 | −static inline int irq_prepare_move(int irq, int cpu) { return 0; } | |
| 131 | −static inline void irq_complete_move(unsigned int irq) {} | |
| 132 | −#endif | |
| 133 | − | |
| 134 | −static inline void ia64_native_resend_irq(unsigned int vector) | |
| 135 | −{ | |
| 136 | − ia64_send_ipi(smp_processor_id(), vector, IA64_IPI_DM_INT, 0); | |
| 137 | −} | |
| 138 | − | |
| 139 | −/* | |
| 140 | − * Next follows the irq descriptor interface. On IA-64, each CPU supports 256 interrupt | |
| 141 | − * vectors. On smaller systems, there is a one-to-one correspondence between interrupt | |
| 142 | − * vectors and the Linux irq numbers. However, larger systems may have multiple interrupt | |
| 143 | − * domains meaning that the translation from vector number to irq number depends on the | |
| 144 | − * interrupt domain that a CPU belongs to. This API abstracts such platform-dependent | |
| 145 | − * differences and provides a uniform means to translate between vector and irq numbers | |
| 146 | − * and to obtain the irq descriptor for a given irq number. | |
| 147 | − */ | |
| 148 | − | |
| 149 | −/* Extract the IA-64 vector that corresponds to IRQ. */ | |
| 150 | −static inline ia64_vector | |
| 151 | −irq_to_vector (int irq) | |
| 152 | −{ | |
| 153 | − return irq_cfg[irq].vector; | |
| 154 | −} | |
| 155 | − | |
| 156 | −/* | |
| 157 | − * Convert the local IA-64 vector to the corresponding irq number. This translation is | |
| 158 | − * done in the context of the interrupt domain that the currently executing CPU belongs | |
| 159 | − * to. | |
| 160 | − */ | |
| 161 | −static inline unsigned int | |
| 162 | −local_vector_to_irq (ia64_vector vec) | |
| 163 | −{ | |
| 164 | − return __this_cpu_read(vector_irq[vec]); | |
| 165 | −} | |
| 166 | − | |
| 167 | −#endif /* _ASM_IA64_HW_IRQ_H */ | |
| @@ -1,8 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_IDLE_H | |
| 3 | −#define _ASM_IA64_IDLE_H | |
| 4 | − | |
| 5 | −static inline void enter_idle(void) { } | |
| 6 | −static inline void exit_idle(void) { } | |
| 7 | − | |
| 8 | −#endif /* _ASM_IA64_IDLE_H */ | |
| @@ -1,13 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −/* | |
| 3 | − * Compiler-dependent intrinsics. | |
| 4 | − * | |
| 5 | − * Copyright (C) 2002-2003 Hewlett-Packard Co | |
| 6 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 7 | − */ | |
| 8 | −#ifndef _ASM_IA64_INTRINSICS_H | |
| 9 | −#define _ASM_IA64_INTRINSICS_H | |
| 10 | − | |
| 11 | −#include <uapi/asm/intrinsics.h> | |
| 12 | − | |
| 13 | −#endif /* _ASM_IA64_INTRINSICS_H */ | |
| @@ -1,271 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_IO_H | |
| 3 | −#define _ASM_IA64_IO_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * This file contains the definitions for the emulated IO instructions | |
| 7 | − * inb/inw/inl/outb/outw/outl and the "string versions" of the same | |
| 8 | − * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" | |
| 9 | − * versions of the single-IO instructions (inb_p/inw_p/..). | |
| 10 | − * | |
| 11 | − * This file is not meant to be obfuscating: it's just complicated to | |
| 12 | − * (a) handle it all in a way that makes gcc able to optimize it as | |
| 13 | − * well as possible and (b) trying to avoid writing the same thing | |
| 14 | − * over and over again with slight variations and possibly making a | |
| 15 | − * mistake somewhere. | |
| 16 | − * | |
| 17 | − * Copyright (C) 1998-2003 Hewlett-Packard Co | |
| 18 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 19 | − * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> | |
| 20 | − * Copyright (C) 1999 Don Dugger <don.dugger@intel.com> | |
| 21 | − */ | |
| 22 | − | |
| 23 | −#include <asm/unaligned.h> | |
| 24 | −#include <asm/early_ioremap.h> | |
| 25 | − | |
| 26 | −#define __IA64_UNCACHED_OFFSET RGN_BASE(RGN_UNCACHED) | |
| 27 | − | |
| 28 | −/* | |
| 29 | − * The legacy I/O space defined by the ia64 architecture supports only 65536 ports, but | |
| 30 | − * large machines may have multiple other I/O spaces so we can't place any a priori limit | |
| 31 | − * on IO_SPACE_LIMIT. These additional spaces are described in ACPI. | |
| 32 | − */ | |
| 33 | −#define IO_SPACE_LIMIT 0xffffffffffffffffUL | |
| 34 | − | |
| 35 | −#define MAX_IO_SPACES_BITS 8 | |
| 36 | −#define MAX_IO_SPACES (1UL << MAX_IO_SPACES_BITS) | |
| 37 | −#define IO_SPACE_BITS 24 | |
| 38 | −#define IO_SPACE_SIZE (1UL << IO_SPACE_BITS) | |
| 39 | − | |
| 40 | −#define IO_SPACE_NR(port) ((port) >> IO_SPACE_BITS) | |
| 41 | −#define IO_SPACE_BASE(space) ((space) << IO_SPACE_BITS) | |
| 42 | −#define IO_SPACE_PORT(port) ((port) & (IO_SPACE_SIZE - 1)) | |
| 43 | − | |
| 44 | −#define IO_SPACE_SPARSE_ENCODING(p) ((((p) >> 2) << 12) | ((p) & 0xfff)) | |
| 45 | − | |
| 46 | −struct io_space { | |
| 47 | − unsigned long mmio_base; /* base in MMIO space */ | |
| 48 | − int sparse; | |
| 49 | −}; | |
| 50 | − | |
| 51 | −extern struct io_space io_space[]; | |
| 52 | −extern unsigned int num_io_spaces; | |
| 53 | − | |
| 54 | −# ifdef __KERNEL__ | |
| 55 | − | |
| 56 | −/* | |
| 57 | − * All MMIO iomem cookies are in region 6; anything less is a PIO cookie: | |
| 58 | − * 0xCxxxxxxxxxxxxxxx MMIO cookie (return from ioremap) | |
| 59 | − * 0x000000001SPPPPPP PIO cookie (S=space number, P..P=port) | |
| 60 | − * | |
| 61 | − * ioread/writeX() uses the leading 1 in PIO cookies (PIO_OFFSET) to catch | |
| 62 | − * code that uses bare port numbers without the prerequisite pci_iomap(). | |
| 63 | − */ | |
| 64 | −#define PIO_OFFSET (1UL << (MAX_IO_SPACES_BITS + IO_SPACE_BITS)) | |
| 65 | −#define PIO_MASK (PIO_OFFSET - 1) | |
| 66 | −#define PIO_RESERVED __IA64_UNCACHED_OFFSET | |
| 67 | −#define HAVE_ARCH_PIO_SIZE | |
| 68 | − | |
| 69 | −#include <asm/intrinsics.h> | |
| 70 | −#include <asm/page.h> | |
| 71 | −#include <asm-generic/iomap.h> | |
| 72 | − | |
| 73 | −/* | |
| 74 | − * Change virtual addresses to physical addresses and vv. | |
| 75 | − */ | |
| 76 | −static inline unsigned long | |
| 77 | −virt_to_phys (volatile void *address) | |
| 78 | −{ | |
| 79 | − return (unsigned long) address - PAGE_OFFSET; | |
| 80 | −} | |
| 81 | −#define virt_to_phys virt_to_phys | |
| 82 | − | |
| 83 | −static inline void* | |
| 84 | −phys_to_virt (unsigned long address) | |
| 85 | −{ | |
| 86 | − return (void *) (address + PAGE_OFFSET); | |
| 87 | −} | |
| 88 | −#define phys_to_virt phys_to_virt | |
| 89 | − | |
| 90 | −#define ARCH_HAS_VALID_PHYS_ADDR_RANGE | |
| 91 | −extern u64 kern_mem_attribute (unsigned long phys_addr, unsigned long size); | |
| 92 | −extern int valid_phys_addr_range (phys_addr_t addr, size_t count); /* efi.c */ | |
| 93 | −extern int valid_mmap_phys_addr_range (unsigned long pfn, size_t count); | |
| 94 | − | |
| 95 | −# endif /* KERNEL */ | |
| 96 | − | |
| 97 | −/* | |
| 98 | − * Memory fence w/accept. This should never be used in code that is | |
| 99 | − * not IA-64 specific. | |
| 100 | − */ | |
| 101 | −#define __ia64_mf_a() ia64_mfa() | |
| 102 | − | |
| 103 | −static inline void* | |
| 104 | −__ia64_mk_io_addr (unsigned long port) | |
| 105 | −{ | |
| 106 | − struct io_space *space; | |
| 107 | − unsigned long offset; | |
| 108 | − | |
| 109 | − space = &io_space[IO_SPACE_NR(port)]; | |
| 110 | − port = IO_SPACE_PORT(port); | |
| 111 | − if (space->sparse) | |
| 112 | − offset = IO_SPACE_SPARSE_ENCODING(port); | |
| 113 | − else | |
| 114 | − offset = port; | |
| 115 | − | |
| 116 | − return (void *) (space->mmio_base | offset); | |
| 117 | −} | |
| 118 | − | |
| 119 | −/* | |
| 120 | − * For the in/out routines, we need to do "mf.a" _after_ doing the I/O access to ensure | |
| 121 | − * that the access has completed before executing other I/O accesses. Since we're doing | |
| 122 | − * the accesses through an uncachable (UC) translation, the CPU will execute them in | |
| 123 | − * program order. However, we still need to tell the compiler not to shuffle them around | |
| 124 | − * during optimization, which is why we use "volatile" pointers. | |
| 125 | − */ | |
| 126 | − | |
| 127 | −#define inb inb | |
| 128 | −static inline unsigned int inb(unsigned long port) | |
| 129 | −{ | |
| 130 | − volatile unsigned char *addr = __ia64_mk_io_addr(port); | |
| 131 | − unsigned char ret; | |
| 132 | − | |
| 133 | − ret = *addr; | |
| 134 | − __ia64_mf_a(); | |
| 135 | − return ret; | |
| 136 | −} | |
| 137 | − | |
| 138 | −#define inw inw | |
| 139 | −static inline unsigned int inw(unsigned long port) | |
| 140 | −{ | |
| 141 | − volatile unsigned short *addr = __ia64_mk_io_addr(port); | |
| 142 | − unsigned short ret; | |
| 143 | − | |
| 144 | − ret = *addr; | |
| 145 | − __ia64_mf_a(); | |
| 146 | − return ret; | |
| 147 | −} | |
| 148 | − | |
| 149 | −#define inl inl | |
| 150 | −static inline unsigned int inl(unsigned long port) | |
| 151 | −{ | |
| 152 | − volatile unsigned int *addr = __ia64_mk_io_addr(port); | |
| 153 | − unsigned int ret; | |
| 154 | − | |
| 155 | − ret = *addr; | |
| 156 | − __ia64_mf_a(); | |
| 157 | − return ret; | |
| 158 | −} | |
| 159 | − | |
| 160 | −#define outb outb | |
| 161 | −static inline void outb(unsigned char val, unsigned long port) | |
| 162 | −{ | |
| 163 | − volatile unsigned char *addr = __ia64_mk_io_addr(port); | |
| 164 | − | |
| 165 | − *addr = val; | |
| 166 | − __ia64_mf_a(); | |
| 167 | −} | |
| 168 | − | |
| 169 | −#define outw outw | |
| 170 | −static inline void outw(unsigned short val, unsigned long port) | |
| 171 | −{ | |
| 172 | − volatile unsigned short *addr = __ia64_mk_io_addr(port); | |
| 173 | − | |
| 174 | − *addr = val; | |
| 175 | − __ia64_mf_a(); | |
| 176 | −} | |
| 177 | − | |
| 178 | −#define outl outl | |
| 179 | −static inline void outl(unsigned int val, unsigned long port) | |
| 180 | −{ | |
| 181 | − volatile unsigned int *addr = __ia64_mk_io_addr(port); | |
| 182 | − | |
| 183 | − *addr = val; | |
| 184 | − __ia64_mf_a(); | |
| 185 | −} | |
| 186 | − | |
| 187 | −#define insb insb | |
| 188 | −static inline void insb(unsigned long port, void *dst, unsigned long count) | |
| 189 | −{ | |
| 190 | − unsigned char *dp = dst; | |
| 191 | − | |
| 192 | − while (count--) | |
| 193 | − *dp++ = inb(port); | |
| 194 | −} | |
| 195 | − | |
| 196 | −#define insw insw | |
| 197 | −static inline void insw(unsigned long port, void *dst, unsigned long count) | |
| 198 | −{ | |
| 199 | − unsigned short *dp = dst; | |
| 200 | − | |
| 201 | − while (count--) | |
| 202 | − put_unaligned(inw(port), dp++); | |
| 203 | −} | |
| 204 | − | |
| 205 | −#define insl insl | |
| 206 | −static inline void insl(unsigned long port, void *dst, unsigned long count) | |
| 207 | −{ | |
| 208 | − unsigned int *dp = dst; | |
| 209 | − | |
| 210 | − while (count--) | |
| 211 | − put_unaligned(inl(port), dp++); | |
| 212 | −} | |
| 213 | − | |
| 214 | −#define outsb outsb | |
| 215 | −static inline void outsb(unsigned long port, const void *src, | |
| 216 | − unsigned long count) | |
| 217 | −{ | |
| 218 | − const unsigned char *sp = src; | |
| 219 | − | |
| 220 | − while (count--) | |
| 221 | − outb(*sp++, port); | |
| 222 | −} | |
| 223 | − | |
| 224 | −#define outsw outsw | |
| 225 | −static inline void outsw(unsigned long port, const void *src, | |
| 226 | − unsigned long count) | |
| 227 | −{ | |
| 228 | − const unsigned short *sp = src; | |
| 229 | − | |
| 230 | − while (count--) | |
| 231 | − outw(get_unaligned(sp++), port); | |
| 232 | −} | |
| 233 | − | |
| 234 | −#define outsl outsl | |
| 235 | −static inline void outsl(unsigned long port, const void *src, | |
| 236 | − unsigned long count) | |
| 237 | −{ | |
| 238 | − const unsigned int *sp = src; | |
| 239 | − | |
| 240 | − while (count--) | |
| 241 | − outl(get_unaligned(sp++), port); | |
| 242 | −} | |
| 243 | − | |
| 244 | −# ifdef __KERNEL__ | |
| 245 | − | |
| 246 | −#define _PAGE_IOREMAP pgprot_val(PAGE_KERNEL) | |
| 247 | − | |
| 248 | −extern void __iomem * ioremap_uc(unsigned long offset, unsigned long size); | |
| 249 | − | |
| 250 | −#define ioremap_prot ioremap_prot | |
| 251 | −#define ioremap_cache ioremap | |
| 252 | −#define ioremap_uc ioremap_uc | |
| 253 | −#define iounmap iounmap | |
| 254 | − | |
| 255 | −/* | |
| 256 | − * String version of IO memory access ops: | |
| 257 | − */ | |
| 258 | −extern void memcpy_fromio(void *dst, const volatile void __iomem *src, long n); | |
| 259 | −extern void memcpy_toio(volatile void __iomem *dst, const void *src, long n); | |
| 260 | −extern void memset_io(volatile void __iomem *s, int c, long n); | |
| 261 | − | |
| 262 | −#define memcpy_fromio memcpy_fromio | |
| 263 | −#define memcpy_toio memcpy_toio | |
| 264 | −#define memset_io memset_io | |
| 265 | −#define xlate_dev_mem_ptr xlate_dev_mem_ptr | |
| 266 | −#include <asm-generic/io.h> | |
| 267 | −#undef PCI_IOBASE | |
| 268 | − | |
| 269 | −# endif /* __KERNEL__ */ | |
| 270 | − | |
| 271 | −#endif /* _ASM_IA64_IO_H */ | |
| @@ -1,22 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_IOMMU_H | |
| 3 | −#define _ASM_IA64_IOMMU_H 1 | |
| 4 | − | |
| 5 | −#include <linux/acpi.h> | |
| 6 | − | |
| 7 | −/* 10 seconds */ | |
| 8 | −#define DMAR_OPERATION_TIMEOUT (((cycles_t) local_cpu_data->itc_freq)*10) | |
| 9 | − | |
| 10 | −extern void no_iommu_init(void); | |
| 11 | −#ifdef CONFIG_INTEL_IOMMU | |
| 12 | −extern int force_iommu, no_iommu; | |
| 13 | −extern int iommu_detected; | |
| 14 | − | |
| 15 | −static inline int __init | |
| 16 | −arch_rmrr_sanity_check(struct acpi_dmar_reserved_memory *rmrr) { return 0; } | |
| 17 | −#else | |
| 18 | −#define no_iommu (1) | |
| 19 | −#define iommu_detected (0) | |
| 20 | −#endif | |
| 21 | − | |
| 22 | −#endif | |
| @@ -1,106 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef __ASM_IA64_IOSAPIC_H | |
| 3 | −#define __ASM_IA64_IOSAPIC_H | |
| 4 | − | |
| 5 | −#define IOSAPIC_REG_SELECT 0x0 | |
| 6 | −#define IOSAPIC_WINDOW 0x10 | |
| 7 | −#define IOSAPIC_EOI 0x40 | |
| 8 | − | |
| 9 | −#define IOSAPIC_VERSION 0x1 | |
| 10 | − | |
| 11 | −/* | |
| 12 | − * Redirection table entry | |
| 13 | − */ | |
| 14 | −#define IOSAPIC_RTE_LOW(i) (0x10+i*2) | |
| 15 | −#define IOSAPIC_RTE_HIGH(i) (0x11+i*2) | |
| 16 | − | |
| 17 | −#define IOSAPIC_DEST_SHIFT 16 | |
| 18 | − | |
| 19 | −/* | |
| 20 | − * Delivery mode | |
| 21 | − */ | |
| 22 | −#define IOSAPIC_DELIVERY_SHIFT 8 | |
| 23 | −#define IOSAPIC_FIXED 0x0 | |
| 24 | −#define IOSAPIC_LOWEST_PRIORITY 0x1 | |
| 25 | −#define IOSAPIC_PMI 0x2 | |
| 26 | −#define IOSAPIC_NMI 0x4 | |
| 27 | −#define IOSAPIC_INIT 0x5 | |
| 28 | −#define IOSAPIC_EXTINT 0x7 | |
| 29 | − | |
| 30 | −/* | |
| 31 | − * Interrupt polarity | |
| 32 | − */ | |
| 33 | −#define IOSAPIC_POLARITY_SHIFT 13 | |
| 34 | −#define IOSAPIC_POL_HIGH 0 | |
| 35 | −#define IOSAPIC_POL_LOW 1 | |
| 36 | − | |
| 37 | −/* | |
| 38 | − * Trigger mode | |
| 39 | − */ | |
| 40 | −#define IOSAPIC_TRIGGER_SHIFT 15 | |
| 41 | −#define IOSAPIC_EDGE 0 | |
| 42 | −#define IOSAPIC_LEVEL 1 | |
| 43 | − | |
| 44 | −/* | |
| 45 | − * Mask bit | |
| 46 | − */ | |
| 47 | − | |
| 48 | −#define IOSAPIC_MASK_SHIFT 16 | |
| 49 | −#define IOSAPIC_MASK (1<<IOSAPIC_MASK_SHIFT) | |
| 50 | − | |
| 51 | −#define IOSAPIC_VECTOR_MASK 0xffffff00 | |
| 52 | − | |
| 53 | −#ifndef __ASSEMBLY__ | |
| 54 | − | |
| 55 | −#define NR_IOSAPICS 256 | |
| 56 | − | |
| 57 | −#define iosapic_pcat_compat_init ia64_native_iosapic_pcat_compat_init | |
| 58 | −#define __iosapic_read __ia64_native_iosapic_read | |
| 59 | −#define __iosapic_write __ia64_native_iosapic_write | |
| 60 | −#define iosapic_get_irq_chip ia64_native_iosapic_get_irq_chip | |
| 61 | − | |
| 62 | −extern void __init ia64_native_iosapic_pcat_compat_init(void); | |
| 63 | −extern struct irq_chip *ia64_native_iosapic_get_irq_chip(unsigned long trigger); | |
| 64 | − | |
| 65 | −static inline unsigned int | |
| 66 | −__ia64_native_iosapic_read(char __iomem *iosapic, unsigned int reg) | |
| 67 | −{ | |
| 68 | − writel(reg, iosapic + IOSAPIC_REG_SELECT); | |
| 69 | − return readl(iosapic + IOSAPIC_WINDOW); | |
| 70 | −} | |
| 71 | − | |
| 72 | −static inline void | |
| 73 | −__ia64_native_iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val) | |
| 74 | −{ | |
| 75 | − writel(reg, iosapic + IOSAPIC_REG_SELECT); | |
| 76 | − writel(val, iosapic + IOSAPIC_WINDOW); | |
| 77 | −} | |
| 78 | − | |
| 79 | −static inline void iosapic_eoi(char __iomem *iosapic, u32 vector) | |
| 80 | −{ | |
| 81 | − writel(vector, iosapic + IOSAPIC_EOI); | |
| 82 | −} | |
| 83 | − | |
| 84 | −extern void __init iosapic_system_init (int pcat_compat); | |
| 85 | −extern int iosapic_init (unsigned long address, unsigned int gsi_base); | |
| 86 | −extern int iosapic_remove (unsigned int gsi_base); | |
| 87 | −extern int gsi_to_irq (unsigned int gsi); | |
| 88 | −extern int iosapic_register_intr (unsigned int gsi, unsigned long polarity, | |
| 89 | − unsigned long trigger); | |
| 90 | −extern void iosapic_unregister_intr (unsigned int irq); | |
| 91 | −extern void iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi, | |
| 92 | − unsigned long polarity, | |
| 93 | − unsigned long trigger); | |
| 94 | −extern int __init iosapic_register_platform_intr (u32 int_type, | |
| 95 | − unsigned int gsi, | |
| 96 | − int pmi_vector, | |
| 97 | − u16 eid, u16 id, | |
| 98 | − unsigned long polarity, | |
| 99 | − unsigned long trigger); | |
| 100 | − | |
| 101 | −#ifdef CONFIG_NUMA | |
| 102 | −extern void map_iosapic_to_node (unsigned int, int); | |
| 103 | −#endif | |
| 104 | − | |
| 105 | −# endif /* !__ASSEMBLY__ */ | |
| 106 | −#endif /* __ASM_IA64_IOSAPIC_H */ | |
| @@ -1,37 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_IRQ_H | |
| 3 | −#define _ASM_IA64_IRQ_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Copyright (C) 1999-2000, 2002 Hewlett-Packard Co | |
| 7 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 8 | − * Stephane Eranian <eranian@hpl.hp.com> | |
| 9 | − * | |
| 10 | − * 11/24/98 S.Eranian updated TIMER_IRQ and irq_canonicalize | |
| 11 | − * 01/20/99 S.Eranian added keyboard interrupt | |
| 12 | − * 02/29/00 D.Mosberger moved most things into hw_irq.h | |
| 13 | − */ | |
| 14 | − | |
| 15 | −#include <linux/types.h> | |
| 16 | −#include <linux/cpumask.h> | |
| 17 | −#include <asm/native/irq.h> | |
| 18 | − | |
| 19 | −#define NR_IRQS IA64_NATIVE_NR_IRQS | |
| 20 | − | |
| 21 | −static __inline__ int | |
| 22 | −irq_canonicalize (int irq) | |
| 23 | −{ | |
| 24 | − /* | |
| 25 | − * We do the legacy thing here of pretending that irqs < 16 | |
| 26 | − * are 8259 irqs. This really shouldn't be necessary at all, | |
| 27 | − * but we keep it here as serial.c still uses it... | |
| 28 | − */ | |
| 29 | − return ((irq == 2) ? 9 : irq); | |
| 30 | −} | |
| 31 | − | |
| 32 | −extern void set_irq_affinity_info (unsigned int irq, int dest, int redir); | |
| 33 | − | |
| 34 | −int create_irq(void); | |
| 35 | −void destroy_irq(unsigned int irq); | |
| 36 | − | |
| 37 | −#endif /* _ASM_IA64_IRQ_H */ | |
| @@ -1 +0,0 @@ | ||
| 1 | −#include <asm-generic/irq_regs.h> | |
| @@ -1,5 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef __IA64_INTR_REMAPPING_H | |
| 3 | −#define __IA64_INTR_REMAPPING_H | |
| 4 | −#define irq_remapping_enabled 0 | |
| 5 | −#endif | |
| @@ -1,95 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −/* | |
| 3 | − * IRQ flags defines. | |
| 4 | − * | |
| 5 | − * Copyright (C) 1998-2003 Hewlett-Packard Co | |
| 6 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 7 | − * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> | |
| 8 | − * Copyright (C) 1999 Don Dugger <don.dugger@intel.com> | |
| 9 | − */ | |
| 10 | − | |
| 11 | −#ifndef _ASM_IA64_IRQFLAGS_H | |
| 12 | −#define _ASM_IA64_IRQFLAGS_H | |
| 13 | − | |
| 14 | −#include <asm/pal.h> | |
| 15 | −#include <asm/kregs.h> | |
| 16 | − | |
| 17 | −#ifdef CONFIG_IA64_DEBUG_IRQ | |
| 18 | −extern unsigned long last_cli_ip; | |
| 19 | −static inline void arch_maybe_save_ip(unsigned long flags) | |
| 20 | −{ | |
| 21 | − if (flags & IA64_PSR_I) | |
| 22 | − last_cli_ip = ia64_getreg(_IA64_REG_IP); | |
| 23 | −} | |
| 24 | −#else | |
| 25 | −#define arch_maybe_save_ip(flags) do {} while (0) | |
| 26 | −#endif | |
| 27 | − | |
| 28 | −/* | |
| 29 | − * - clearing psr.i is implicitly serialized (visible by next insn) | |
| 30 | − * - setting psr.i requires data serialization | |
| 31 | − * - we need a stop-bit before reading PSR because we sometimes | |
| 32 | − * write a floating-point register right before reading the PSR | |
| 33 | − * and that writes to PSR.mfl | |
| 34 | − */ | |
| 35 | − | |
| 36 | −static inline unsigned long arch_local_save_flags(void) | |
| 37 | −{ | |
| 38 | − ia64_stop(); | |
| 39 | − return ia64_getreg(_IA64_REG_PSR); | |
| 40 | −} | |
| 41 | − | |
| 42 | −static inline unsigned long arch_local_irq_save(void) | |
| 43 | −{ | |
| 44 | − unsigned long flags = arch_local_save_flags(); | |
| 45 | − | |
| 46 | − ia64_stop(); | |
| 47 | − ia64_rsm(IA64_PSR_I); | |
| 48 | − arch_maybe_save_ip(flags); | |
| 49 | − return flags; | |
| 50 | −} | |
| 51 | − | |
| 52 | −static inline void arch_local_irq_disable(void) | |
| 53 | −{ | |
| 54 | −#ifdef CONFIG_IA64_DEBUG_IRQ | |
| 55 | − arch_local_irq_save(); | |
| 56 | −#else | |
| 57 | − ia64_stop(); | |
| 58 | − ia64_rsm(IA64_PSR_I); | |
| 59 | −#endif | |
| 60 | −} | |
| 61 | − | |
| 62 | −static inline void arch_local_irq_enable(void) | |
| 63 | −{ | |
| 64 | − ia64_stop(); | |
| 65 | − ia64_ssm(IA64_PSR_I); | |
| 66 | − ia64_srlz_d(); | |
| 67 | −} | |
| 68 | − | |
| 69 | −static inline void arch_local_irq_restore(unsigned long flags) | |
| 70 | −{ | |
| 71 | −#ifdef CONFIG_IA64_DEBUG_IRQ | |
| 72 | − unsigned long old_psr = arch_local_save_flags(); | |
| 73 | −#endif | |
| 74 | − ia64_intrin_local_irq_restore(flags & IA64_PSR_I); | |
| 75 | − arch_maybe_save_ip(old_psr & ~flags); | |
| 76 | −} | |
| 77 | − | |
| 78 | −static inline bool arch_irqs_disabled_flags(unsigned long flags) | |
| 79 | −{ | |
| 80 | − return (flags & IA64_PSR_I) == 0; | |
| 81 | −} | |
| 82 | − | |
| 83 | −static inline bool arch_irqs_disabled(void) | |
| 84 | −{ | |
| 85 | − return arch_irqs_disabled_flags(arch_local_save_flags()); | |
| 86 | −} | |
| 87 | − | |
| 88 | −static inline void arch_safe_halt(void) | |
| 89 | −{ | |
| 90 | − arch_local_irq_enable(); | |
| 91 | − ia64_pal_halt_light(); /* PAL_HALT_LIGHT */ | |
| 92 | −} | |
| 93 | − | |
| 94 | − | |
| 95 | −#endif /* _ASM_IA64_IRQFLAGS_H */ | |
| @@ -1,45 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0-or-later */ | |
| 2 | −#ifndef _IA64_KDEBUG_H | |
| 3 | −#define _IA64_KDEBUG_H 1 | |
| 4 | −/* | |
| 5 | − * | |
| 6 | − * Copyright (C) Intel Corporation, 2005 | |
| 7 | − * | |
| 8 | − * 2005-Apr Rusty Lynch <rusty.lynch@intel.com> and Anil S Keshavamurthy | |
| 9 | − * <anil.s.keshavamurthy@intel.com> adopted from | |
| 10 | − * include/asm-x86_64/kdebug.h | |
| 11 | − * | |
| 12 | − * 2005-Oct Keith Owens <kaos@sgi.com>. Expand notify_die to cover more | |
| 13 | − * events. | |
| 14 | − */ | |
| 15 | − | |
| 16 | −enum die_val { | |
| 17 | − DIE_BREAK = 1, | |
| 18 | − DIE_FAULT, | |
| 19 | − DIE_OOPS, | |
| 20 | − DIE_MACHINE_HALT, | |
| 21 | − DIE_MACHINE_RESTART, | |
| 22 | − DIE_MCA_MONARCH_ENTER, | |
| 23 | − DIE_MCA_MONARCH_PROCESS, | |
| 24 | − DIE_MCA_MONARCH_LEAVE, | |
| 25 | − DIE_MCA_SLAVE_ENTER, | |
| 26 | − DIE_MCA_SLAVE_PROCESS, | |
| 27 | − DIE_MCA_SLAVE_LEAVE, | |
| 28 | − DIE_MCA_RENDZVOUS_ENTER, | |
| 29 | − DIE_MCA_RENDZVOUS_PROCESS, | |
| 30 | − DIE_MCA_RENDZVOUS_LEAVE, | |
| 31 | − DIE_MCA_NEW_TIMEOUT, | |
| 32 | − DIE_INIT_ENTER, | |
| 33 | − DIE_INIT_MONARCH_ENTER, | |
| 34 | − DIE_INIT_MONARCH_PROCESS, | |
| 35 | − DIE_INIT_MONARCH_LEAVE, | |
| 36 | − DIE_INIT_SLAVE_ENTER, | |
| 37 | − DIE_INIT_SLAVE_PROCESS, | |
| 38 | − DIE_INIT_SLAVE_LEAVE, | |
| 39 | − DIE_KDEBUG_ENTER, | |
| 40 | − DIE_KDEBUG_LEAVE, | |
| 41 | − DIE_KDUMP_ENTER, | |
| 42 | − DIE_KDUMP_LEAVE, | |
| 43 | −}; | |
| 44 | − | |
| 45 | −#endif | |
| @@ -1,46 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_KEXEC_H | |
| 3 | −#define _ASM_IA64_KEXEC_H | |
| 4 | − | |
| 5 | −#include <asm/setup.h> | |
| 6 | − | |
| 7 | −/* Maximum physical address we can use pages from */ | |
| 8 | −#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL) | |
| 9 | −/* Maximum address we can reach in physical address mode */ | |
| 10 | −#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL) | |
| 11 | −/* Maximum address we can use for the control code buffer */ | |
| 12 | −#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE | |
| 13 | − | |
| 14 | −#define KEXEC_CONTROL_PAGE_SIZE (8192 + 8192 + 4096) | |
| 15 | − | |
| 16 | −/* The native architecture */ | |
| 17 | −#define KEXEC_ARCH KEXEC_ARCH_IA_64 | |
| 18 | − | |
| 19 | −#define kexec_flush_icache_page(page) do { \ | |
| 20 | − unsigned long page_addr = (unsigned long)page_address(page); \ | |
| 21 | − flush_icache_range(page_addr, page_addr + PAGE_SIZE); \ | |
| 22 | − } while(0) | |
| 23 | − | |
| 24 | −extern struct kimage *ia64_kimage; | |
| 25 | −extern const unsigned int relocate_new_kernel_size; | |
| 26 | −extern void relocate_new_kernel(unsigned long, unsigned long, | |
| 27 | − struct ia64_boot_param *, unsigned long); | |
| 28 | −static inline void | |
| 29 | −crash_setup_regs(struct pt_regs *newregs, struct pt_regs *oldregs) | |
| 30 | −{ | |
| 31 | −} | |
| 32 | −extern struct resource efi_memmap_res; | |
| 33 | −extern struct resource boot_param_res; | |
| 34 | −extern void kdump_smp_send_stop(void); | |
| 35 | −extern void kdump_smp_send_init(void); | |
| 36 | −extern void kexec_disable_iosapic(void); | |
| 37 | −extern void crash_save_this_cpu(void); | |
| 38 | −struct rsvd_region; | |
| 39 | −extern unsigned long kdump_find_rsvd_region(unsigned long size, | |
| 40 | − struct rsvd_region *rsvd_regions, int n); | |
| 41 | −extern void kdump_cpu_freeze(struct unw_frame_info *info, void *arg); | |
| 42 | −extern int kdump_status[]; | |
| 43 | −extern atomic_t kdump_cpu_freezed; | |
| 44 | −extern atomic_t kdump_in_progress; | |
| 45 | − | |
| 46 | −#endif /* _ASM_IA64_KEXEC_H */ | |
| @@ -1,116 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0-or-later */ | |
| 2 | −#ifndef _ASM_KPROBES_H | |
| 3 | −#define _ASM_KPROBES_H | |
| 4 | −/* | |
| 5 | − * Kernel Probes (KProbes) | |
| 6 | − * | |
| 7 | − * Copyright (C) IBM Corporation, 2002, 2004 | |
| 8 | − * Copyright (C) Intel Corporation, 2005 | |
| 9 | − * | |
| 10 | − * 2005-Apr Rusty Lynch <rusty.lynch@intel.com> and Anil S Keshavamurthy | |
| 11 | − * <anil.s.keshavamurthy@intel.com> adapted from i386 | |
| 12 | − */ | |
| 13 | −#include <asm-generic/kprobes.h> | |
| 14 | −#include <asm/break.h> | |
| 15 | − | |
| 16 | −#define BREAK_INST (long)(__IA64_BREAK_KPROBE << 6) | |
| 17 | − | |
| 18 | −#ifdef CONFIG_KPROBES | |
| 19 | − | |
| 20 | −#include <linux/types.h> | |
| 21 | −#include <linux/ptrace.h> | |
| 22 | −#include <linux/percpu.h> | |
| 23 | − | |
| 24 | −#define __ARCH_WANT_KPROBES_INSN_SLOT | |
| 25 | −#define MAX_INSN_SIZE 2 /* last half is for kprobe-booster */ | |
| 26 | −#define NOP_M_INST (long)(1<<27) | |
| 27 | −#define BRL_INST(i1, i2) ((long)((0xcL << 37) | /* brl */ \ | |
| 28 | − (0x1L << 12) | /* many */ \ | |
| 29 | − (((i1) & 1) << 36) | ((i2) << 13))) /* imm */ | |
| 30 | − | |
| 31 | −typedef union cmp_inst { | |
| 32 | − struct { | |
| 33 | − unsigned long long qp : 6; | |
| 34 | − unsigned long long p1 : 6; | |
| 35 | − unsigned long long c : 1; | |
| 36 | − unsigned long long r2 : 7; | |
| 37 | − unsigned long long r3 : 7; | |
| 38 | − unsigned long long p2 : 6; | |
| 39 | − unsigned long long ta : 1; | |
| 40 | − unsigned long long x2 : 2; | |
| 41 | − unsigned long long tb : 1; | |
| 42 | − unsigned long long opcode : 4; | |
| 43 | − unsigned long long reserved : 23; | |
| 44 | − }f; | |
| 45 | − unsigned long long l; | |
| 46 | −} cmp_inst_t; | |
| 47 | − | |
| 48 | −struct kprobe; | |
| 49 | − | |
| 50 | −typedef struct _bundle { | |
| 51 | − struct { | |
| 52 | − unsigned long long template : 5; | |
| 53 | − unsigned long long slot0 : 41; | |
| 54 | − unsigned long long slot1_p0 : 64-46; | |
| 55 | − } quad0; | |
| 56 | − struct { | |
| 57 | − unsigned long long slot1_p1 : 41 - (64-46); | |
| 58 | − unsigned long long slot2 : 41; | |
| 59 | − } quad1; | |
| 60 | −} __attribute__((__aligned__(16))) bundle_t; | |
| 61 | − | |
| 62 | −struct prev_kprobe { | |
| 63 | − struct kprobe *kp; | |
| 64 | − unsigned long status; | |
| 65 | −}; | |
| 66 | − | |
| 67 | −#define MAX_PARAM_RSE_SIZE (0x60+0x60/0x3f) | |
| 68 | −/* per-cpu kprobe control block */ | |
| 69 | −#define ARCH_PREV_KPROBE_SZ 2 | |
| 70 | −struct kprobe_ctlblk { | |
| 71 | − unsigned long kprobe_status; | |
| 72 | − unsigned long *bsp; | |
| 73 | − unsigned long cfm; | |
| 74 | − atomic_t prev_kprobe_index; | |
| 75 | − struct prev_kprobe prev_kprobe[ARCH_PREV_KPROBE_SZ]; | |
| 76 | −}; | |
| 77 | − | |
| 78 | −#define kretprobe_blacklist_size 0 | |
| 79 | − | |
| 80 | −#define SLOT0_OPCODE_SHIFT (37) | |
| 81 | −#define SLOT1_p1_OPCODE_SHIFT (37 - (64-46)) | |
| 82 | −#define SLOT2_OPCODE_SHIFT (37) | |
| 83 | − | |
| 84 | −#define INDIRECT_CALL_OPCODE (1) | |
| 85 | −#define IP_RELATIVE_CALL_OPCODE (5) | |
| 86 | −#define IP_RELATIVE_BRANCH_OPCODE (4) | |
| 87 | −#define IP_RELATIVE_PREDICT_OPCODE (7) | |
| 88 | −#define LONG_BRANCH_OPCODE (0xC) | |
| 89 | −#define LONG_CALL_OPCODE (0xD) | |
| 90 | −#define flush_insn_slot(p) do { } while (0) | |
| 91 | − | |
| 92 | −typedef struct kprobe_opcode { | |
| 93 | − bundle_t bundle; | |
| 94 | −} kprobe_opcode_t; | |
| 95 | − | |
| 96 | −/* Architecture specific copy of original instruction*/ | |
| 97 | −struct arch_specific_insn { | |
| 98 | − /* copy of the instruction to be emulated */ | |
| 99 | − kprobe_opcode_t *insn; | |
| 100 | − #define INST_FLAG_FIX_RELATIVE_IP_ADDR 1 | |
| 101 | − #define INST_FLAG_FIX_BRANCH_REG 2 | |
| 102 | − #define INST_FLAG_BREAK_INST 4 | |
| 103 | − #define INST_FLAG_BOOSTABLE 8 | |
| 104 | − unsigned long inst_flag; | |
| 105 | − unsigned short target_br_reg; | |
| 106 | − unsigned short slot; | |
| 107 | −}; | |
| 108 | − | |
| 109 | −extern int kprobe_fault_handler(struct pt_regs *regs, int trapnr); | |
| 110 | −extern int kprobe_exceptions_notify(struct notifier_block *self, | |
| 111 | − unsigned long val, void *data); | |
| 112 | − | |
| 113 | −extern void arch_remove_kprobe(struct kprobe *p); | |
| 114 | − | |
| 115 | −#endif /* CONFIG_KPROBES */ | |
| 116 | −#endif /* _ASM_KPROBES_H */ | |
| @@ -1,166 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_KREGS_H | |
| 3 | −#define _ASM_IA64_KREGS_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Copyright (C) 2001-2002 Hewlett-Packard Co | |
| 7 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 8 | − */ | |
| 9 | −/* | |
| 10 | − * This file defines the kernel register usage convention used by Linux/ia64. | |
| 11 | − */ | |
| 12 | − | |
| 13 | −/* | |
| 14 | − * Kernel registers: | |
| 15 | − */ | |
| 16 | −#define IA64_KR_IO_BASE 0 /* ar.k0: legacy I/O base address */ | |
| 17 | −#define IA64_KR_TSSD 1 /* ar.k1: IVE uses this as the TSSD */ | |
| 18 | −#define IA64_KR_PER_CPU_DATA 3 /* ar.k3: physical per-CPU base */ | |
| 19 | −#define IA64_KR_CURRENT_STACK 4 /* ar.k4: what's mapped in IA64_TR_CURRENT_STACK */ | |
| 20 | −#define IA64_KR_FPU_OWNER 5 /* ar.k5: fpu-owner (UP only, at the moment) */ | |
| 21 | −#define IA64_KR_CURRENT 6 /* ar.k6: "current" task pointer */ | |
| 22 | −#define IA64_KR_PT_BASE 7 /* ar.k7: page table base address (physical) */ | |
| 23 | − | |
| 24 | −#define _IA64_KR_PASTE(x,y) x##y | |
| 25 | −#define _IA64_KR_PREFIX(n) _IA64_KR_PASTE(ar.k, n) | |
| 26 | −#define IA64_KR(n) _IA64_KR_PREFIX(IA64_KR_##n) | |
| 27 | − | |
| 28 | −/* | |
| 29 | − * Translation registers: | |
| 30 | − */ | |
| 31 | −#define IA64_TR_KERNEL 0 /* itr0, dtr0: maps kernel image (code & data) */ | |
| 32 | −#define IA64_TR_PALCODE 1 /* itr1: maps PALcode as required by EFI */ | |
| 33 | −#define IA64_TR_CURRENT_STACK 1 /* dtr1: maps kernel's memory- & register-stacks */ | |
| 34 | − | |
| 35 | −#define IA64_TR_ALLOC_BASE 2 /* itr&dtr: Base of dynamic TR resource*/ | |
| 36 | −#define IA64_TR_ALLOC_MAX 64 /* Max number for dynamic use*/ | |
| 37 | − | |
| 38 | −/* Processor status register bits: */ | |
| 39 | −#define IA64_PSR_BE_BIT 1 | |
| 40 | −#define IA64_PSR_UP_BIT 2 | |
| 41 | −#define IA64_PSR_AC_BIT 3 | |
| 42 | −#define IA64_PSR_MFL_BIT 4 | |
| 43 | −#define IA64_PSR_MFH_BIT 5 | |
| 44 | −#define IA64_PSR_IC_BIT 13 | |
| 45 | −#define IA64_PSR_I_BIT 14 | |
| 46 | −#define IA64_PSR_PK_BIT 15 | |
| 47 | −#define IA64_PSR_DT_BIT 17 | |
| 48 | −#define IA64_PSR_DFL_BIT 18 | |
| 49 | −#define IA64_PSR_DFH_BIT 19 | |
| 50 | −#define IA64_PSR_SP_BIT 20 | |
| 51 | −#define IA64_PSR_PP_BIT 21 | |
| 52 | −#define IA64_PSR_DI_BIT 22 | |
| 53 | −#define IA64_PSR_SI_BIT 23 | |
| 54 | −#define IA64_PSR_DB_BIT 24 | |
| 55 | −#define IA64_PSR_LP_BIT 25 | |
| 56 | −#define IA64_PSR_TB_BIT 26 | |
| 57 | −#define IA64_PSR_RT_BIT 27 | |
| 58 | −/* The following are not affected by save_flags()/restore_flags(): */ | |
| 59 | −#define IA64_PSR_CPL0_BIT 32 | |
| 60 | −#define IA64_PSR_CPL1_BIT 33 | |
| 61 | −#define IA64_PSR_IS_BIT 34 | |
| 62 | −#define IA64_PSR_MC_BIT 35 | |
| 63 | −#define IA64_PSR_IT_BIT 36 | |
| 64 | −#define IA64_PSR_ID_BIT 37 | |
| 65 | −#define IA64_PSR_DA_BIT 38 | |
| 66 | −#define IA64_PSR_DD_BIT 39 | |
| 67 | −#define IA64_PSR_SS_BIT 40 | |
| 68 | −#define IA64_PSR_RI_BIT 41 | |
| 69 | −#define IA64_PSR_ED_BIT 43 | |
| 70 | −#define IA64_PSR_BN_BIT 44 | |
| 71 | −#define IA64_PSR_IA_BIT 45 | |
| 72 | − | |
| 73 | −/* A mask of PSR bits that we generally don't want to inherit across a clone2() or an | |
| 74 | − execve(). Only list flags here that need to be cleared/set for BOTH clone2() and | |
| 75 | − execve(). */ | |
| 76 | −#define IA64_PSR_BITS_TO_CLEAR (IA64_PSR_MFL | IA64_PSR_MFH | IA64_PSR_DB | IA64_PSR_LP | \ | |
| 77 | − IA64_PSR_TB | IA64_PSR_ID | IA64_PSR_DA | IA64_PSR_DD | \ | |
| 78 | − IA64_PSR_SS | IA64_PSR_ED | IA64_PSR_IA) | |
| 79 | −#define IA64_PSR_BITS_TO_SET (IA64_PSR_DFH | IA64_PSR_SP) | |
| 80 | − | |
| 81 | −#define IA64_PSR_BE (__IA64_UL(1) << IA64_PSR_BE_BIT) | |
| 82 | −#define IA64_PSR_UP (__IA64_UL(1) << IA64_PSR_UP_BIT) | |
| 83 | −#define IA64_PSR_AC (__IA64_UL(1) << IA64_PSR_AC_BIT) | |
| 84 | −#define IA64_PSR_MFL (__IA64_UL(1) << IA64_PSR_MFL_BIT) | |
| 85 | −#define IA64_PSR_MFH (__IA64_UL(1) << IA64_PSR_MFH_BIT) | |
| 86 | −#define IA64_PSR_IC (__IA64_UL(1) << IA64_PSR_IC_BIT) | |
| 87 | −#define IA64_PSR_I (__IA64_UL(1) << IA64_PSR_I_BIT) | |
| 88 | −#define IA64_PSR_PK (__IA64_UL(1) << IA64_PSR_PK_BIT) | |
| 89 | −#define IA64_PSR_DT (__IA64_UL(1) << IA64_PSR_DT_BIT) | |
| 90 | −#define IA64_PSR_DFL (__IA64_UL(1) << IA64_PSR_DFL_BIT) | |
| 91 | −#define IA64_PSR_DFH (__IA64_UL(1) << IA64_PSR_DFH_BIT) | |
| 92 | −#define IA64_PSR_SP (__IA64_UL(1) << IA64_PSR_SP_BIT) | |
| 93 | −#define IA64_PSR_PP (__IA64_UL(1) << IA64_PSR_PP_BIT) | |
| 94 | −#define IA64_PSR_DI (__IA64_UL(1) << IA64_PSR_DI_BIT) | |
| 95 | −#define IA64_PSR_SI (__IA64_UL(1) << IA64_PSR_SI_BIT) | |
| 96 | −#define IA64_PSR_DB (__IA64_UL(1) << IA64_PSR_DB_BIT) | |
| 97 | −#define IA64_PSR_LP (__IA64_UL(1) << IA64_PSR_LP_BIT) | |
| 98 | −#define IA64_PSR_TB (__IA64_UL(1) << IA64_PSR_TB_BIT) | |
| 99 | −#define IA64_PSR_RT (__IA64_UL(1) << IA64_PSR_RT_BIT) | |
| 100 | −/* The following are not affected by save_flags()/restore_flags(): */ | |
| 101 | −#define IA64_PSR_CPL (__IA64_UL(3) << IA64_PSR_CPL0_BIT) | |
| 102 | −#define IA64_PSR_IS (__IA64_UL(1) << IA64_PSR_IS_BIT) | |
| 103 | −#define IA64_PSR_MC (__IA64_UL(1) << IA64_PSR_MC_BIT) | |
| 104 | −#define IA64_PSR_IT (__IA64_UL(1) << IA64_PSR_IT_BIT) | |
| 105 | −#define IA64_PSR_ID (__IA64_UL(1) << IA64_PSR_ID_BIT) | |
| 106 | −#define IA64_PSR_DA (__IA64_UL(1) << IA64_PSR_DA_BIT) | |
| 107 | −#define IA64_PSR_DD (__IA64_UL(1) << IA64_PSR_DD_BIT) | |
| 108 | −#define IA64_PSR_SS (__IA64_UL(1) << IA64_PSR_SS_BIT) | |
| 109 | −#define IA64_PSR_RI (__IA64_UL(3) << IA64_PSR_RI_BIT) | |
| 110 | −#define IA64_PSR_ED (__IA64_UL(1) << IA64_PSR_ED_BIT) | |
| 111 | −#define IA64_PSR_BN (__IA64_UL(1) << IA64_PSR_BN_BIT) | |
| 112 | −#define IA64_PSR_IA (__IA64_UL(1) << IA64_PSR_IA_BIT) | |
| 113 | − | |
| 114 | −/* User mask bits: */ | |
| 115 | −#define IA64_PSR_UM (IA64_PSR_BE | IA64_PSR_UP | IA64_PSR_AC | IA64_PSR_MFL | IA64_PSR_MFH) | |
| 116 | − | |
| 117 | −/* Default Control Register */ | |
| 118 | −#define IA64_DCR_PP_BIT 0 /* privileged performance monitor default */ | |
| 119 | −#define IA64_DCR_BE_BIT 1 /* big-endian default */ | |
| 120 | −#define IA64_DCR_LC_BIT 2 /* ia32 lock-check enable */ | |
| 121 | −#define IA64_DCR_DM_BIT 8 /* defer TLB miss faults */ | |
| 122 | −#define IA64_DCR_DP_BIT 9 /* defer page-not-present faults */ | |
| 123 | −#define IA64_DCR_DK_BIT 10 /* defer key miss faults */ | |
| 124 | −#define IA64_DCR_DX_BIT 11 /* defer key permission faults */ | |
| 125 | −#define IA64_DCR_DR_BIT 12 /* defer access right faults */ | |
| 126 | −#define IA64_DCR_DA_BIT 13 /* defer access bit faults */ | |
| 127 | −#define IA64_DCR_DD_BIT 14 /* defer debug faults */ | |
| 128 | − | |
| 129 | −#define IA64_DCR_PP (__IA64_UL(1) << IA64_DCR_PP_BIT) | |
| 130 | −#define IA64_DCR_BE (__IA64_UL(1) << IA64_DCR_BE_BIT) | |
| 131 | −#define IA64_DCR_LC (__IA64_UL(1) << IA64_DCR_LC_BIT) | |
| 132 | −#define IA64_DCR_DM (__IA64_UL(1) << IA64_DCR_DM_BIT) | |
| 133 | −#define IA64_DCR_DP (__IA64_UL(1) << IA64_DCR_DP_BIT) | |
| 134 | −#define IA64_DCR_DK (__IA64_UL(1) << IA64_DCR_DK_BIT) | |
| 135 | −#define IA64_DCR_DX (__IA64_UL(1) << IA64_DCR_DX_BIT) | |
| 136 | −#define IA64_DCR_DR (__IA64_UL(1) << IA64_DCR_DR_BIT) | |
| 137 | −#define IA64_DCR_DA (__IA64_UL(1) << IA64_DCR_DA_BIT) | |
| 138 | −#define IA64_DCR_DD (__IA64_UL(1) << IA64_DCR_DD_BIT) | |
| 139 | − | |
| 140 | −/* Interrupt Status Register */ | |
| 141 | −#define IA64_ISR_X_BIT 32 /* execute access */ | |
| 142 | −#define IA64_ISR_W_BIT 33 /* write access */ | |
| 143 | −#define IA64_ISR_R_BIT 34 /* read access */ | |
| 144 | −#define IA64_ISR_NA_BIT 35 /* non-access */ | |
| 145 | −#define IA64_ISR_SP_BIT 36 /* speculative load exception */ | |
| 146 | −#define IA64_ISR_RS_BIT 37 /* mandatory register-stack exception */ | |
| 147 | −#define IA64_ISR_IR_BIT 38 /* invalid register frame exception */ | |
| 148 | −#define IA64_ISR_CODE_MASK 0xf | |
| 149 | − | |
| 150 | −#define IA64_ISR_X (__IA64_UL(1) << IA64_ISR_X_BIT) | |
| 151 | −#define IA64_ISR_W (__IA64_UL(1) << IA64_ISR_W_BIT) | |
| 152 | −#define IA64_ISR_R (__IA64_UL(1) << IA64_ISR_R_BIT) | |
| 153 | −#define IA64_ISR_NA (__IA64_UL(1) << IA64_ISR_NA_BIT) | |
| 154 | −#define IA64_ISR_SP (__IA64_UL(1) << IA64_ISR_SP_BIT) | |
| 155 | −#define IA64_ISR_RS (__IA64_UL(1) << IA64_ISR_RS_BIT) | |
| 156 | −#define IA64_ISR_IR (__IA64_UL(1) << IA64_ISR_IR_BIT) | |
| 157 | − | |
| 158 | −/* ISR code field for non-access instructions */ | |
| 159 | −#define IA64_ISR_CODE_TPA 0 | |
| 160 | −#define IA64_ISR_CODE_FC 1 | |
| 161 | −#define IA64_ISR_CODE_PROBE 2 | |
| 162 | −#define IA64_ISR_CODE_TAK 3 | |
| 163 | −#define IA64_ISR_CODE_LFETCH 4 | |
| 164 | −#define IA64_ISR_CODE_PROBEF 5 | |
| 165 | − | |
| 166 | −#endif /* _ASM_IA64_kREGS_H */ | |
| @@ -1,9 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef __ASM_IA64_LIBATA_PORTMAP_H | |
| 3 | −#define __ASM_IA64_LIBATA_PORTMAP_H | |
| 4 | − | |
| 5 | −#define ATA_PRIMARY_IRQ(dev) isa_irq_to_vector(14) | |
| 6 | − | |
| 7 | −#define ATA_SECONDARY_IRQ(dev) isa_irq_to_vector(15) | |
| 8 | − | |
| 9 | −#endif | |
| @@ -1,19 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef __ASM_LINKAGE_H | |
| 3 | −#define __ASM_LINKAGE_H | |
| 4 | − | |
| 5 | −#ifndef __ASSEMBLY__ | |
| 6 | − | |
| 7 | −#define asmlinkage CPP_ASMLINKAGE __attribute__((syscall_linkage)) | |
| 8 | − | |
| 9 | −#else | |
| 10 | − | |
| 11 | −#include <asm/asmmacro.h> | |
| 12 | − | |
| 13 | −#endif | |
| 14 | − | |
| 15 | −#define cond_syscall(x) asm(".weak\t" #x "#\n" #x "#\t=\tsys_ni_syscall#") | |
| 16 | −#define SYSCALL_ALIAS(alias, name) \ | |
| 17 | − asm ( #alias "# = " #name "#\n\t.globl " #alias "#") | |
| 18 | − | |
| 19 | −#endif | |
| @@ -1 +0,0 @@ | ||
| 1 | −#include <asm-generic/local.h> | |
| @@ -1,185 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −/* | |
| 3 | − * File: mca.h | |
| 4 | − * Purpose: Machine check handling specific defines | |
| 5 | − * | |
| 6 | − * Copyright (C) 1999, 2004 Silicon Graphics, Inc. | |
| 7 | − * Copyright (C) Vijay Chander <vijay@engr.sgi.com> | |
| 8 | − * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com> | |
| 9 | − * Copyright (C) Russ Anderson <rja@sgi.com> | |
| 10 | − */ | |
| 11 | − | |
| 12 | −#ifndef _ASM_IA64_MCA_H | |
| 13 | −#define _ASM_IA64_MCA_H | |
| 14 | − | |
| 15 | −#if !defined(__ASSEMBLY__) | |
| 16 | − | |
| 17 | −#include <linux/percpu.h> | |
| 18 | −#include <linux/threads.h> | |
| 19 | −#include <linux/types.h> | |
| 20 | −#include <asm/ptrace.h> | |
| 21 | − | |
| 22 | −#define IA64_MCA_RENDEZ_TIMEOUT (20 * 1000) /* value in milliseconds - 20 seconds */ | |
| 23 | − | |
| 24 | −typedef struct ia64_fptr { | |
| 25 | − unsigned long fp; | |
| 26 | − unsigned long gp; | |
| 27 | −} ia64_fptr_t; | |
| 28 | − | |
| 29 | −typedef union cmcv_reg_u { | |
| 30 | − u64 cmcv_regval; | |
| 31 | − struct { | |
| 32 | − u64 cmcr_vector : 8; | |
| 33 | − u64 cmcr_reserved1 : 4; | |
| 34 | − u64 cmcr_ignored1 : 1; | |
| 35 | − u64 cmcr_reserved2 : 3; | |
| 36 | − u64 cmcr_mask : 1; | |
| 37 | − u64 cmcr_ignored2 : 47; | |
| 38 | − } cmcv_reg_s; | |
| 39 | − | |
| 40 | −} cmcv_reg_t; | |
| 41 | − | |
| 42 | −#define cmcv_mask cmcv_reg_s.cmcr_mask | |
| 43 | −#define cmcv_vector cmcv_reg_s.cmcr_vector | |
| 44 | − | |
| 45 | −enum { | |
| 46 | − IA64_MCA_RENDEZ_CHECKIN_NOTDONE = 0x0, | |
| 47 | − IA64_MCA_RENDEZ_CHECKIN_DONE = 0x1, | |
| 48 | − IA64_MCA_RENDEZ_CHECKIN_INIT = 0x2, | |
| 49 | − IA64_MCA_RENDEZ_CHECKIN_CONCURRENT_MCA = 0x3, | |
| 50 | −}; | |
| 51 | − | |
| 52 | −/* Information maintained by the MC infrastructure */ | |
| 53 | −typedef struct ia64_mc_info_s { | |
| 54 | − u64 imi_mca_handler; | |
| 55 | − size_t imi_mca_handler_size; | |
| 56 | − u64 imi_monarch_init_handler; | |
| 57 | − size_t imi_monarch_init_handler_size; | |
| 58 | − u64 imi_slave_init_handler; | |
| 59 | − size_t imi_slave_init_handler_size; | |
| 60 | − u8 imi_rendez_checkin[NR_CPUS]; | |
| 61 | − | |
| 62 | −} ia64_mc_info_t; | |
| 63 | − | |
| 64 | −/* Handover state from SAL to OS and vice versa, for both MCA and INIT events. | |
| 65 | − * Besides the handover state, it also contains some saved registers from the | |
| 66 | − * time of the event. | |
| 67 | − * Note: mca_asm.S depends on the precise layout of this structure. | |
| 68 | − */ | |
| 69 | − | |
| 70 | −struct ia64_sal_os_state { | |
| 71 | − | |
| 72 | − /* SAL to OS */ | |
| 73 | − unsigned long os_gp; /* GP of the os registered with the SAL, physical */ | |
| 74 | − unsigned long pal_proc; /* PAL_PROC entry point, physical */ | |
| 75 | − unsigned long sal_proc; /* SAL_PROC entry point, physical */ | |
| 76 | − unsigned long rv_rc; /* MCA - Rendezvous state, INIT - reason code */ | |
| 77 | − unsigned long proc_state_param; /* from R18 */ | |
| 78 | − unsigned long monarch; /* 1 for a monarch event, 0 for a slave */ | |
| 79 | − | |
| 80 | − /* common */ | |
| 81 | − unsigned long sal_ra; /* Return address in SAL, physical */ | |
| 82 | − unsigned long sal_gp; /* GP of the SAL - physical */ | |
| 83 | − struct pal_min_state_area *pal_min_state; /* from R17. physical in asm, virtual in C */ | |
| 84 | − /* Previous values of IA64_KR(CURRENT) and IA64_KR(CURRENT_STACK). | |
| 85 | − * Note: if the MCA/INIT recovery code wants to resume to a new context | |
| 86 | − * then it must change these values to reflect the new kernel stack. | |
| 87 | − */ | |
| 88 | − unsigned long prev_IA64_KR_CURRENT; /* previous value of IA64_KR(CURRENT) */ | |
| 89 | − unsigned long prev_IA64_KR_CURRENT_STACK; | |
| 90 | − struct task_struct *prev_task; /* previous task, NULL if it is not useful */ | |
| 91 | − /* Some interrupt registers are not saved in minstate, pt_regs or | |
| 92 | − * switch_stack. Because MCA/INIT can occur when interrupts are | |
| 93 | − * disabled, we need to save the additional interrupt registers over | |
| 94 | − * MCA/INIT and resume. | |
| 95 | − */ | |
| 96 | − unsigned long isr; | |
| 97 | − unsigned long ifa; | |
| 98 | − unsigned long itir; | |
| 99 | − unsigned long iipa; | |
| 100 | − unsigned long iim; | |
| 101 | − unsigned long iha; | |
| 102 | − | |
| 103 | − /* OS to SAL */ | |
| 104 | − unsigned long os_status; /* OS status to SAL, enum below */ | |
| 105 | − unsigned long context; /* 0 if return to same context | |
| 106 | − 1 if return to new context */ | |
| 107 | − | |
| 108 | − /* I-resources */ | |
| 109 | − unsigned long iip; | |
| 110 | − unsigned long ipsr; | |
| 111 | − unsigned long ifs; | |
| 112 | −}; | |
| 113 | − | |
| 114 | −enum { | |
| 115 | − IA64_MCA_CORRECTED = 0x0, /* Error has been corrected by OS_MCA */ | |
| 116 | − IA64_MCA_WARM_BOOT = -1, /* Warm boot of the system need from SAL */ | |
| 117 | − IA64_MCA_COLD_BOOT = -2, /* Cold boot of the system need from SAL */ | |
| 118 | − IA64_MCA_HALT = -3 /* System to be halted by SAL */ | |
| 119 | −}; | |
| 120 | − | |
| 121 | −enum { | |
| 122 | − IA64_INIT_RESUME = 0x0, /* Resume after return from INIT */ | |
| 123 | − IA64_INIT_WARM_BOOT = -1, /* Warm boot of the system need from SAL */ | |
| 124 | −}; | |
| 125 | − | |
| 126 | −enum { | |
| 127 | − IA64_MCA_SAME_CONTEXT = 0x0, /* SAL to return to same context */ | |
| 128 | − IA64_MCA_NEW_CONTEXT = -1 /* SAL to return to new context */ | |
| 129 | −}; | |
| 130 | − | |
| 131 | −/* Per-CPU MCA state that is too big for normal per-CPU variables. */ | |
| 132 | − | |
| 133 | −struct ia64_mca_cpu { | |
| 134 | − u64 mca_stack[KERNEL_STACK_SIZE/8]; | |
| 135 | − u64 init_stack[KERNEL_STACK_SIZE/8]; | |
| 136 | −}; | |
| 137 | − | |
| 138 | −/* Array of physical addresses of each CPU's MCA area. */ | |
| 139 | −extern unsigned long __per_cpu_mca[NR_CPUS]; | |
| 140 | − | |
| 141 | −extern int cpe_vector; | |
| 142 | −extern int ia64_cpe_irq; | |
| 143 | −extern void ia64_mca_init(void); | |
| 144 | −extern void ia64_mca_irq_init(void); | |
| 145 | −extern void ia64_mca_cpu_init(void *); | |
| 146 | −extern void ia64_os_mca_dispatch(void); | |
| 147 | −extern void ia64_os_mca_dispatch_end(void); | |
| 148 | −extern void ia64_mca_ucmc_handler(struct pt_regs *, struct ia64_sal_os_state *); | |
| 149 | −extern void ia64_init_handler(struct pt_regs *, | |
| 150 | − struct switch_stack *, | |
| 151 | − struct ia64_sal_os_state *); | |
| 152 | −extern void ia64_os_init_on_kdump(void); | |
| 153 | −extern void ia64_monarch_init_handler(void); | |
| 154 | −extern void ia64_slave_init_handler(void); | |
| 155 | −extern void ia64_mca_cmc_vector_setup(void); | |
| 156 | −extern int ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *)); | |
| 157 | −extern void ia64_unreg_MCA_extension(void); | |
| 158 | −extern unsigned long ia64_get_rnat(unsigned long *); | |
| 159 | −extern void ia64_set_psr_mc(void); | |
| 160 | −extern void ia64_mca_printk(const char * fmt, ...) | |
| 161 | − __attribute__ ((format (printf, 1, 2))); | |
| 162 | − | |
| 163 | −struct ia64_mca_notify_die { | |
| 164 | − struct ia64_sal_os_state *sos; | |
| 165 | − int *monarch_cpu; | |
| 166 | − int *data; | |
| 167 | −}; | |
| 168 | − | |
| 169 | −DECLARE_PER_CPU(u64, ia64_mca_pal_base); | |
| 170 | − | |
| 171 | −#else /* __ASSEMBLY__ */ | |
| 172 | − | |
| 173 | −#define IA64_MCA_CORRECTED 0x0 /* Error has been corrected by OS_MCA */ | |
| 174 | −#define IA64_MCA_WARM_BOOT -1 /* Warm boot of the system need from SAL */ | |
| 175 | −#define IA64_MCA_COLD_BOOT -2 /* Cold boot of the system need from SAL */ | |
| 176 | −#define IA64_MCA_HALT -3 /* System to be halted by SAL */ | |
| 177 | − | |
| 178 | −#define IA64_INIT_RESUME 0x0 /* Resume after return from INIT */ | |
| 179 | −#define IA64_INIT_WARM_BOOT -1 /* Warm boot of the system need from SAL */ | |
| 180 | − | |
| 181 | −#define IA64_MCA_SAME_CONTEXT 0x0 /* SAL to return to same context */ | |
| 182 | −#define IA64_MCA_NEW_CONTEXT -1 /* SAL to return to new context */ | |
| 183 | − | |
| 184 | −#endif /* !__ASSEMBLY__ */ | |
| 185 | −#endif /* _ASM_IA64_MCA_H */ | |
| @@ -1,245 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −/* | |
| 3 | − * File: mca_asm.h | |
| 4 | − * Purpose: Machine check handling specific defines | |
| 5 | − * | |
| 6 | − * Copyright (C) 1999 Silicon Graphics, Inc. | |
| 7 | − * Copyright (C) Vijay Chander <vijay@engr.sgi.com> | |
| 8 | − * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com> | |
| 9 | − * Copyright (C) 2000 Hewlett-Packard Co. | |
| 10 | − * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com> | |
| 11 | − * Copyright (C) 2002 Intel Corp. | |
| 12 | − * Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com> | |
| 13 | − * Copyright (C) 2005 Silicon Graphics, Inc | |
| 14 | − * Copyright (C) 2005 Keith Owens <kaos@sgi.com> | |
| 15 | − */ | |
| 16 | −#ifndef _ASM_IA64_MCA_ASM_H | |
| 17 | −#define _ASM_IA64_MCA_ASM_H | |
| 18 | − | |
| 19 | −#include <asm/percpu.h> | |
| 20 | − | |
| 21 | −#define PSR_IC 13 | |
| 22 | −#define PSR_I 14 | |
| 23 | −#define PSR_DT 17 | |
| 24 | −#define PSR_RT 27 | |
| 25 | −#define PSR_MC 35 | |
| 26 | −#define PSR_IT 36 | |
| 27 | −#define PSR_BN 44 | |
| 28 | − | |
| 29 | −/* | |
| 30 | − * This macro converts a instruction virtual address to a physical address | |
| 31 | − * Right now for simulation purposes the virtual addresses are | |
| 32 | − * direct mapped to physical addresses. | |
| 33 | − * 1. Lop off bits 61 thru 63 in the virtual address | |
| 34 | − */ | |
| 35 | −#define INST_VA_TO_PA(addr) \ | |
| 36 | − dep addr = 0, addr, 61, 3 | |
| 37 | −/* | |
| 38 | − * This macro converts a data virtual address to a physical address | |
| 39 | − * Right now for simulation purposes the virtual addresses are | |
| 40 | − * direct mapped to physical addresses. | |
| 41 | − * 1. Lop off bits 61 thru 63 in the virtual address | |
| 42 | − */ | |
| 43 | −#define DATA_VA_TO_PA(addr) \ | |
| 44 | − tpa addr = addr | |
| 45 | −/* | |
| 46 | − * This macro converts a data physical address to a virtual address | |
| 47 | − * Right now for simulation purposes the virtual addresses are | |
| 48 | − * direct mapped to physical addresses. | |
| 49 | − * 1. Put 0x7 in bits 61 thru 63. | |
| 50 | − */ | |
| 51 | −#define DATA_PA_TO_VA(addr,temp) \ | |
| 52 | − mov temp = 0x7 ;; \ | |
| 53 | − dep addr = temp, addr, 61, 3 | |
| 54 | − | |
| 55 | −#define GET_THIS_PADDR(reg, var) \ | |
| 56 | − mov reg = IA64_KR(PER_CPU_DATA);; \ | |
| 57 | − addl reg = THIS_CPU(var), reg | |
| 58 | − | |
| 59 | −/* | |
| 60 | − * This macro jumps to the instruction at the given virtual address | |
| 61 | − * and starts execution in physical mode with all the address | |
| 62 | − * translations turned off. | |
| 63 | − * 1. Save the current psr | |
| 64 | − * 2. Make sure that all the upper 32 bits are off | |
| 65 | − * | |
| 66 | − * 3. Clear the interrupt enable and interrupt state collection bits | |
| 67 | − * in the psr before updating the ipsr and iip. | |
| 68 | − * | |
| 69 | − * 4. Turn off the instruction, data and rse translation bits of the psr | |
| 70 | − * and store the new value into ipsr | |
| 71 | − * Also make sure that the interrupts are disabled. | |
| 72 | − * Ensure that we are in little endian mode. | |
| 73 | − * [psr.{rt, it, dt, i, be} = 0] | |
| 74 | − * | |
| 75 | − * 5. Get the physical address corresponding to the virtual address | |
| 76 | − * of the next instruction bundle and put it in iip. | |
| 77 | − * (Using magic numbers 24 and 40 in the deposint instruction since | |
| 78 | − * the IA64_SDK code directly maps to lower 24bits as physical address | |
| 79 | − * from a virtual address). | |
| 80 | − * | |
| 81 | − * 6. Do an rfi to move the values from ipsr to psr and iip to ip. | |
| 82 | − */ | |
| 83 | −#define PHYSICAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \ | |
| 84 | − mov old_psr = psr; \ | |
| 85 | − ;; \ | |
| 86 | − dep old_psr = 0, old_psr, 32, 32; \ | |
| 87 | − \ | |
| 88 | − mov ar.rsc = 0 ; \ | |
| 89 | − ;; \ | |
| 90 | − srlz.d; \ | |
| 91 | − mov temp2 = ar.bspstore; \ | |
| 92 | − ;; \ | |
| 93 | − DATA_VA_TO_PA(temp2); \ | |
| 94 | − ;; \ | |
| 95 | − mov temp1 = ar.rnat; \ | |
| 96 | − ;; \ | |
| 97 | − mov ar.bspstore = temp2; \ | |
| 98 | − ;; \ | |
| 99 | − mov ar.rnat = temp1; \ | |
| 100 | − mov temp1 = psr; \ | |
| 101 | − mov temp2 = psr; \ | |
| 102 | − ;; \ | |
| 103 | − \ | |
| 104 | − dep temp2 = 0, temp2, PSR_IC, 2; \ | |
| 105 | − ;; \ | |
| 106 | − mov psr.l = temp2; \ | |
| 107 | − ;; \ | |
| 108 | − srlz.d; \ | |
| 109 | − dep temp1 = 0, temp1, 32, 32; \ | |
| 110 | − ;; \ | |
| 111 | − dep temp1 = 0, temp1, PSR_IT, 1; \ | |
| 112 | − ;; \ | |
| 113 | − dep temp1 = 0, temp1, PSR_DT, 1; \ | |
| 114 | − ;; \ | |
| 115 | − dep temp1 = 0, temp1, PSR_RT, 1; \ | |
| 116 | − ;; \ | |
| 117 | − dep temp1 = 0, temp1, PSR_I, 1; \ | |
| 118 | − ;; \ | |
| 119 | − dep temp1 = 0, temp1, PSR_IC, 1; \ | |
| 120 | − ;; \ | |
| 121 | − dep temp1 = -1, temp1, PSR_MC, 1; \ | |
| 122 | − ;; \ | |
| 123 | − mov cr.ipsr = temp1; \ | |
| 124 | − ;; \ | |
| 125 | − LOAD_PHYSICAL(p0, temp2, start_addr); \ | |
| 126 | − ;; \ | |
| 127 | − mov cr.iip = temp2; \ | |
| 128 | − mov cr.ifs = r0; \ | |
| 129 | − DATA_VA_TO_PA(sp); \ | |
| 130 | − DATA_VA_TO_PA(gp); \ | |
| 131 | − ;; \ | |
| 132 | − srlz.i; \ | |
| 133 | − ;; \ | |
| 134 | − nop 1; \ | |
| 135 | − nop 2; \ | |
| 136 | − nop 1; \ | |
| 137 | − nop 2; \ | |
| 138 | − rfi; \ | |
| 139 | − ;; | |
| 140 | − | |
| 141 | −/* | |
| 142 | − * This macro jumps to the instruction at the given virtual address | |
| 143 | − * and starts execution in virtual mode with all the address | |
| 144 | − * translations turned on. | |
| 145 | − * 1. Get the old saved psr | |
| 146 | − * | |
| 147 | − * 2. Clear the interrupt state collection bit in the current psr. | |
| 148 | − * | |
| 149 | − * 3. Set the instruction translation bit back in the old psr | |
| 150 | − * Note we have to do this since we are right now saving only the | |
| 151 | − * lower 32-bits of old psr.(Also the old psr has the data and | |
| 152 | − * rse translation bits on) | |
| 153 | − * | |
| 154 | − * 4. Set ipsr to this old_psr with "it" bit set and "bn" = 1. | |
| 155 | − * | |
| 156 | − * 5. Reset the current thread pointer (r13). | |
| 157 | − * | |
| 158 | − * 6. Set iip to the virtual address of the next instruction bundle. | |
| 159 | − * | |
| 160 | − * 7. Do an rfi to move ipsr to psr and iip to ip. | |
| 161 | − */ | |
| 162 | − | |
| 163 | −#define VIRTUAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \ | |
| 164 | − mov temp2 = psr; \ | |
| 165 | − ;; \ | |
| 166 | − mov old_psr = temp2; \ | |
| 167 | − ;; \ | |
| 168 | − dep temp2 = 0, temp2, PSR_IC, 2; \ | |
| 169 | − ;; \ | |
| 170 | − mov psr.l = temp2; \ | |
| 171 | − mov ar.rsc = 0; \ | |
| 172 | − ;; \ | |
| 173 | − srlz.d; \ | |
| 174 | − mov r13 = ar.k6; \ | |
| 175 | − mov temp2 = ar.bspstore; \ | |
| 176 | − ;; \ | |
| 177 | − DATA_PA_TO_VA(temp2,temp1); \ | |
| 178 | − ;; \ | |
| 179 | − mov temp1 = ar.rnat; \ | |
| 180 | − ;; \ | |
| 181 | − mov ar.bspstore = temp2; \ | |
| 182 | − ;; \ | |
| 183 | − mov ar.rnat = temp1; \ | |
| 184 | − ;; \ | |
| 185 | − mov temp1 = old_psr; \ | |
| 186 | − ;; \ | |
| 187 | − mov temp2 = 1; \ | |
| 188 | − ;; \ | |
| 189 | − dep temp1 = temp2, temp1, PSR_IC, 1; \ | |
| 190 | − ;; \ | |
| 191 | − dep temp1 = temp2, temp1, PSR_IT, 1; \ | |
| 192 | − ;; \ | |
| 193 | − dep temp1 = temp2, temp1, PSR_DT, 1; \ | |
| 194 | − ;; \ | |
| 195 | − dep temp1 = temp2, temp1, PSR_RT, 1; \ | |
| 196 | − ;; \ | |
| 197 | − dep temp1 = temp2, temp1, PSR_BN, 1; \ | |
| 198 | − ;; \ | |
| 199 | − \ | |
| 200 | − mov cr.ipsr = temp1; \ | |
| 201 | − movl temp2 = start_addr; \ | |
| 202 | − ;; \ | |
| 203 | − mov cr.iip = temp2; \ | |
| 204 | − movl gp = __gp \ | |
| 205 | − ;; \ | |
| 206 | − DATA_PA_TO_VA(sp, temp1); \ | |
| 207 | − srlz.i; \ | |
| 208 | − ;; \ | |
| 209 | − nop 1; \ | |
| 210 | − nop 2; \ | |
| 211 | − nop 1; \ | |
| 212 | − rfi \ | |
| 213 | − ;; | |
| 214 | − | |
| 215 | −/* | |
| 216 | − * The MCA and INIT stacks in struct ia64_mca_cpu look like normal kernel | |
| 217 | − * stacks, except that the SAL/OS state and a switch_stack are stored near the | |
| 218 | − * top of the MCA/INIT stack. To support concurrent entry to MCA or INIT, as | |
| 219 | − * well as MCA over INIT, each event needs its own SAL/OS state. All entries | |
| 220 | − * are 16 byte aligned. | |
| 221 | − * | |
| 222 | − * +---------------------------+ | |
| 223 | − * | pt_regs | | |
| 224 | − * +---------------------------+ | |
| 225 | − * | switch_stack | | |
| 226 | − * +---------------------------+ | |
| 227 | − * | SAL/OS state | | |
| 228 | − * +---------------------------+ | |
| 229 | − * | 16 byte scratch area | | |
| 230 | − * +---------------------------+ <-------- SP at start of C MCA handler | |
| 231 | − * | ..... | | |
| 232 | − * +---------------------------+ | |
| 233 | − * | RBS for MCA/INIT handler | | |
| 234 | − * +---------------------------+ | |
| 235 | − * | struct task for MCA/INIT | | |
| 236 | − * +---------------------------+ <-------- Bottom of MCA/INIT stack | |
| 237 | − */ | |
| 238 | − | |
| 239 | −#define ALIGN16(x) ((x)&~15) | |
| 240 | −#define MCA_PT_REGS_OFFSET ALIGN16(KERNEL_STACK_SIZE-IA64_PT_REGS_SIZE) | |
| 241 | −#define MCA_SWITCH_STACK_OFFSET ALIGN16(MCA_PT_REGS_OFFSET-IA64_SWITCH_STACK_SIZE) | |
| 242 | −#define MCA_SOS_OFFSET ALIGN16(MCA_SWITCH_STACK_OFFSET-IA64_SAL_OS_STATE_SIZE) | |
| 243 | −#define MCA_SP_OFFSET ALIGN16(MCA_SOS_OFFSET-16) | |
| 244 | − | |
| 245 | −#endif /* _ASM_IA64_MCA_ASM_H */ | |
| @@ -1,59 +0,0 @@ | ||
| 1 | −#ifndef meminit_h | |
| 2 | −#define meminit_h | |
| 3 | − | |
| 4 | −/* | |
| 5 | − * This file is subject to the terms and conditions of the GNU General Public | |
| 6 | − * License. See the file "COPYING" in the main directory of this archive | |
| 7 | − * for more details. | |
| 8 | − */ | |
| 9 | − | |
| 10 | − | |
| 11 | −/* | |
| 12 | − * Entries defined so far: | |
| 13 | − * - boot param structure itself | |
| 14 | − * - memory map | |
| 15 | − * - initrd (optional) | |
| 16 | − * - command line string | |
| 17 | − * - kernel code & data | |
| 18 | − * - crash dumping code reserved region | |
| 19 | − * - Kernel memory map built from EFI memory map | |
| 20 | − * - ELF core header | |
| 21 | − * | |
| 22 | − * More could be added if necessary | |
| 23 | − */ | |
| 24 | −#define IA64_MAX_RSVD_REGIONS 9 | |
| 25 | − | |
| 26 | −struct rsvd_region { | |
| 27 | − u64 start; /* virtual address of beginning of element */ | |
| 28 | − u64 end; /* virtual address of end of element + 1 */ | |
| 29 | −}; | |
| 30 | − | |
| 31 | −extern struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1]; | |
| 32 | − | |
| 33 | −extern void find_memory (void); | |
| 34 | −extern void reserve_memory (void); | |
| 35 | −extern void find_initrd (void); | |
| 36 | −extern int filter_rsvd_memory (u64 start, u64 end, void *arg); | |
| 37 | −extern int filter_memory (u64 start, u64 end, void *arg); | |
| 38 | −extern unsigned long efi_memmap_init(u64 *s, u64 *e); | |
| 39 | −extern int find_max_min_low_pfn (u64, u64, void *); | |
| 40 | − | |
| 41 | −extern unsigned long vmcore_find_descriptor_size(unsigned long address); | |
| 42 | − | |
| 43 | −/* | |
| 44 | − * For rounding an address to the next IA64_GRANULE_SIZE or order | |
| 45 | − */ | |
| 46 | −#define GRANULEROUNDDOWN(n) ((n) & ~(IA64_GRANULE_SIZE-1)) | |
| 47 | −#define GRANULEROUNDUP(n) (((n)+IA64_GRANULE_SIZE-1) & ~(IA64_GRANULE_SIZE-1)) | |
| 48 | − | |
| 49 | −#ifdef CONFIG_NUMA | |
| 50 | − extern void call_pernode_memory (unsigned long start, unsigned long len, void *func); | |
| 51 | −#else | |
| 52 | −# define call_pernode_memory(start, len, func) (*func)(start, len, 0) | |
| 53 | −#endif | |
| 54 | − | |
| 55 | −#define IGNORE_PFN0 1 /* XXX fix me: ignore pfn 0 until TLB miss handler is updated... */ | |
| 56 | − | |
| 57 | −extern int register_active_ranges(u64 start, u64 len, int nid); | |
| 58 | − | |
| 59 | −#endif /* meminit_h */ | |
| @@ -1,18 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −/* | |
| 3 | − * Based on <asm-i386/mman.h>. | |
| 4 | − * | |
| 5 | − * Modified 1998-2000, 2002 | |
| 6 | − * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co | |
| 7 | − */ | |
| 8 | −#ifndef _ASM_IA64_MMAN_H | |
| 9 | −#define _ASM_IA64_MMAN_H | |
| 10 | − | |
| 11 | −#include <uapi/asm/mman.h> | |
| 12 | − | |
| 13 | −#ifndef __ASSEMBLY__ | |
| 14 | −#define arch_mmap_check ia64_mmap_check | |
| 15 | −int ia64_mmap_check(unsigned long addr, unsigned long len, | |
| 16 | − unsigned long flags); | |
| 17 | −#endif | |
| 18 | −#endif /* _ASM_IA64_MMAN_H */ | |
| @@ -1,17 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | − | |
| 3 | −#ifndef _ASM_IA64_MMIOWB_H | |
| 4 | −#define _ASM_IA64_MMIOWB_H | |
| 5 | − | |
| 6 | −/** | |
| 7 | − * mmiowb - I/O write barrier | |
| 8 | − * | |
| 9 | − * Ensure ordering of I/O space writes. This will make sure that writes | |
| 10 | − * following the barrier will arrive after all previous writes. For most | |
| 11 | − * ia64 platforms, this is a simple 'mf.a' instruction. | |
| 12 | − */ | |
| 13 | −#define mmiowb() ia64_mfa() | |
| 14 | − | |
| 15 | −#include <asm-generic/mmiowb.h> | |
| 16 | − | |
| 17 | −#endif /* _ASM_IA64_MMIOWB_H */ | |
| @@ -1,14 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef __MMU_H | |
| 3 | −#define __MMU_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Type for a context number. We declare it volatile to ensure proper | |
| 7 | − * ordering when it's accessed outside of spinlock'd critical sections | |
| 8 | − * (e.g., as done in activate_mm() and init_new_context()). | |
| 9 | − */ | |
| 10 | −typedef volatile unsigned long mm_context_t; | |
| 11 | − | |
| 12 | −typedef unsigned long nv_mm_context_t; | |
| 13 | − | |
| 14 | −#endif | |
| @@ -1,194 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_MMU_CONTEXT_H | |
| 3 | −#define _ASM_IA64_MMU_CONTEXT_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Copyright (C) 1998-2002 Hewlett-Packard Co | |
| 7 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 8 | − */ | |
| 9 | − | |
| 10 | −/* | |
| 11 | − * Routines to manage the allocation of task context numbers. Task context | |
| 12 | − * numbers are used to reduce or eliminate the need to perform TLB flushes | |
| 13 | − * due to context switches. Context numbers are implemented using ia-64 | |
| 14 | − * region ids. Since the IA-64 TLB does not consider the region number when | |
| 15 | − * performing a TLB lookup, we need to assign a unique region id to each | |
| 16 | − * region in a process. We use the least significant three bits in aregion | |
| 17 | − * id for this purpose. | |
| 18 | − */ | |
| 19 | − | |
| 20 | −#define IA64_REGION_ID_KERNEL 0 /* the kernel's region id (tlb.c depends on this being 0) */ | |
| 21 | − | |
| 22 | −#define ia64_rid(ctx,addr) (((ctx) << 3) | (addr >> 61)) | |
| 23 | − | |
| 24 | −# include <asm/page.h> | |
| 25 | −# ifndef __ASSEMBLY__ | |
| 26 | − | |
| 27 | −#include <linux/compiler.h> | |
| 28 | −#include <linux/percpu.h> | |
| 29 | −#include <linux/sched.h> | |
| 30 | −#include <linux/mm_types.h> | |
| 31 | −#include <linux/spinlock.h> | |
| 32 | − | |
| 33 | −#include <asm/processor.h> | |
| 34 | −#include <asm-generic/mm_hooks.h> | |
| 35 | − | |
| 36 | −struct ia64_ctx { | |
| 37 | − spinlock_t lock; | |
| 38 | − unsigned int next; /* next context number to use */ | |
| 39 | − unsigned int limit; /* available free range */ | |
| 40 | − unsigned int max_ctx; /* max. context value supported by all CPUs */ | |
| 41 | − /* call wrap_mmu_context when next >= max */ | |
| 42 | − unsigned long *bitmap; /* bitmap size is max_ctx+1 */ | |
| 43 | − unsigned long *flushmap;/* pending rid to be flushed */ | |
| 44 | −}; | |
| 45 | − | |
| 46 | −extern struct ia64_ctx ia64_ctx; | |
| 47 | −DECLARE_PER_CPU(u8, ia64_need_tlb_flush); | |
| 48 | − | |
| 49 | −extern void mmu_context_init (void); | |
| 50 | −extern void wrap_mmu_context (struct mm_struct *mm); | |
| 51 | − | |
| 52 | −/* | |
| 53 | − * When the context counter wraps around all TLBs need to be flushed because | |
| 54 | − * an old context number might have been reused. This is signalled by the | |
| 55 | − * ia64_need_tlb_flush per-CPU variable, which is checked in the routine | |
| 56 | − * below. Called by activate_mm(). <efocht@ess.nec.de> | |
| 57 | − */ | |
| 58 | −static inline void | |
| 59 | −delayed_tlb_flush (void) | |
| 60 | −{ | |
| 61 | − extern void local_flush_tlb_all (void); | |
| 62 | − unsigned long flags; | |
| 63 | − | |
| 64 | − if (unlikely(__ia64_per_cpu_var(ia64_need_tlb_flush))) { | |
| 65 | − spin_lock_irqsave(&ia64_ctx.lock, flags); | |
| 66 | − if (__ia64_per_cpu_var(ia64_need_tlb_flush)) { | |
| 67 | − local_flush_tlb_all(); | |
| 68 | − __ia64_per_cpu_var(ia64_need_tlb_flush) = 0; | |
| 69 | − } | |
| 70 | − spin_unlock_irqrestore(&ia64_ctx.lock, flags); | |
| 71 | − } | |
| 72 | −} | |
| 73 | − | |
| 74 | −static inline nv_mm_context_t | |
| 75 | −get_mmu_context (struct mm_struct *mm) | |
| 76 | −{ | |
| 77 | − unsigned long flags; | |
| 78 | − nv_mm_context_t context = mm->context; | |
| 79 | − | |
| 80 | − if (likely(context)) | |
| 81 | − goto out; | |
| 82 | − | |
| 83 | − spin_lock_irqsave(&ia64_ctx.lock, flags); | |
| 84 | − /* re-check, now that we've got the lock: */ | |
| 85 | − context = mm->context; | |
| 86 | − if (context == 0) { | |
| 87 | − cpumask_clear(mm_cpumask(mm)); | |
| 88 | − if (ia64_ctx.next >= ia64_ctx.limit) { | |
| 89 | − ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap, | |
| 90 | − ia64_ctx.max_ctx, ia64_ctx.next); | |
| 91 | − ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap, | |
| 92 | − ia64_ctx.max_ctx, ia64_ctx.next); | |
| 93 | − if (ia64_ctx.next >= ia64_ctx.max_ctx) | |
| 94 | − wrap_mmu_context(mm); | |
| 95 | − } | |
| 96 | − mm->context = context = ia64_ctx.next++; | |
| 97 | − __set_bit(context, ia64_ctx.bitmap); | |
| 98 | − } | |
| 99 | − spin_unlock_irqrestore(&ia64_ctx.lock, flags); | |
| 100 | −out: | |
| 101 | − /* | |
| 102 | − * Ensure we're not starting to use "context" before any old | |
| 103 | − * uses of it are gone from our TLB. | |
| 104 | − */ | |
| 105 | − delayed_tlb_flush(); | |
| 106 | − | |
| 107 | − return context; | |
| 108 | −} | |
| 109 | − | |
| 110 | −/* | |
| 111 | − * Initialize context number to some sane value. MM is guaranteed to be a | |
| 112 | − * brand-new address-space, so no TLB flushing is needed, ever. | |
| 113 | − */ | |
| 114 | −#define init_new_context init_new_context | |
| 115 | −static inline int | |
| 116 | −init_new_context (struct task_struct *p, struct mm_struct *mm) | |
| 117 | −{ | |
| 118 | − mm->context = 0; | |
| 119 | − return 0; | |
| 120 | −} | |
| 121 | − | |
| 122 | −static inline void | |
| 123 | −reload_context (nv_mm_context_t context) | |
| 124 | −{ | |
| 125 | − unsigned long rid; | |
| 126 | − unsigned long rid_incr = 0; | |
| 127 | − unsigned long rr0, rr1, rr2, rr3, rr4; | |
| 128 | − | |
| 129 | −#ifdef CONFIG_HUGETLB_PAGE | |
| 130 | − unsigned long old_rr4; | |
| 131 | − old_rr4 = ia64_get_rr(RGN_BASE(RGN_HPAGE)); | |
| 132 | −#endif | |
| 133 | − rid = context << 3; /* make space for encoding the region number */ | |
| 134 | − rid_incr = 1 << 8; | |
| 135 | − | |
| 136 | − /* encode the region id, preferred page size, and VHPT enable bit: */ | |
| 137 | − rr0 = (rid << 8) | (PAGE_SHIFT << 2) | 1; | |
| 138 | − rr1 = rr0 + 1*rid_incr; | |
| 139 | − rr2 = rr0 + 2*rid_incr; | |
| 140 | − rr3 = rr0 + 3*rid_incr; | |
| 141 | − rr4 = rr0 + 4*rid_incr; | |
| 142 | −#ifdef CONFIG_HUGETLB_PAGE | |
| 143 | − rr4 = (rr4 & (~(0xfcUL))) | (old_rr4 & 0xfc); | |
| 144 | − | |
| 145 | −# if RGN_HPAGE != 4 | |
| 146 | −# error "reload_context assumes RGN_HPAGE is 4" | |
| 147 | −# endif | |
| 148 | −#endif | |
| 149 | − | |
| 150 | − ia64_set_rr0_to_rr4(rr0, rr1, rr2, rr3, rr4); | |
| 151 | − ia64_srlz_i(); /* srlz.i implies srlz.d */ | |
| 152 | −} | |
| 153 | − | |
| 154 | −/* | |
| 155 | − * Must be called with preemption off | |
| 156 | − */ | |
| 157 | −static inline void | |
| 158 | −activate_context (struct mm_struct *mm) | |
| 159 | −{ | |
| 160 | − nv_mm_context_t context; | |
| 161 | − | |
| 162 | − do { | |
| 163 | − context = get_mmu_context(mm); | |
| 164 | − if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) | |
| 165 | − cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm)); | |
| 166 | − reload_context(context); | |
| 167 | − /* | |
| 168 | − * in the unlikely event of a TLB-flush by another thread, | |
| 169 | − * redo the load. | |
| 170 | − */ | |
| 171 | − } while (unlikely(context != mm->context)); | |
| 172 | −} | |
| 173 | − | |
| 174 | −/* | |
| 175 | − * Switch from address space PREV to address space NEXT. | |
| 176 | − */ | |
| 177 | −#define activate_mm activate_mm | |
| 178 | −static inline void | |
| 179 | −activate_mm (struct mm_struct *prev, struct mm_struct *next) | |
| 180 | −{ | |
| 181 | − /* | |
| 182 | − * We may get interrupts here, but that's OK because interrupt | |
| 183 | − * handlers cannot touch user-space. | |
| 184 | − */ | |
| 185 | − ia64_set_kr(IA64_KR_PT_BASE, __pa(next->pgd)); | |
| 186 | − activate_context(next); | |
| 187 | −} | |
| 188 | − | |
| 189 | −#define switch_mm(prev_mm,next_mm,next_task) activate_mm(prev_mm, next_mm) | |
| 190 | − | |
| 191 | −#include <asm-generic/mmu_context.h> | |
| 192 | − | |
| 193 | −# endif /* ! __ASSEMBLY__ */ | |
| 194 | −#endif /* _ASM_IA64_MMU_CONTEXT_H */ | |
| @@ -1,35 +0,0 @@ | ||
| 1 | −/* | |
| 2 | − * This file is subject to the terms and conditions of the GNU General Public | |
| 3 | − * License. See the file "COPYING" in the main directory of this archive | |
| 4 | − * for more details. | |
| 5 | − * | |
| 6 | − * Copyright (c) 2000,2003 Silicon Graphics, Inc. All rights reserved. | |
| 7 | − * Copyright (c) 2002 NEC Corp. | |
| 8 | − * Copyright (c) 2002 Erich Focht <efocht@ess.nec.de> | |
| 9 | − * Copyright (c) 2002 Kimio Suganuma <k-suganuma@da.jp.nec.com> | |
| 10 | − */ | |
| 11 | −#ifndef _ASM_IA64_MMZONE_H | |
| 12 | −#define _ASM_IA64_MMZONE_H | |
| 13 | − | |
| 14 | −#include <linux/numa.h> | |
| 15 | −#include <asm/page.h> | |
| 16 | −#include <asm/meminit.h> | |
| 17 | − | |
| 18 | −#ifdef CONFIG_NUMA | |
| 19 | − | |
| 20 | −static inline int pfn_to_nid(unsigned long pfn) | |
| 21 | −{ | |
| 22 | − extern int paddr_to_nid(unsigned long); | |
| 23 | − int nid = paddr_to_nid(pfn << PAGE_SHIFT); | |
| 24 | − if (nid < 0) | |
| 25 | − return 0; | |
| 26 | − else | |
| 27 | − return nid; | |
| 28 | −} | |
| 29 | − | |
| 30 | −#define MAX_PHYSNODE_ID 2048 | |
| 31 | −#endif /* CONFIG_NUMA */ | |
| 32 | − | |
| 33 | −#define NR_NODE_MEMBLKS (MAX_NUMNODES * 4) | |
| 34 | − | |
| 35 | −#endif /* _ASM_IA64_MMZONE_H */ | |
| @@ -1,35 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_MODULE_H | |
| 3 | −#define _ASM_IA64_MODULE_H | |
| 4 | − | |
| 5 | −#include <asm-generic/module.h> | |
| 6 | − | |
| 7 | −/* | |
| 8 | − * IA-64-specific support for kernel module loader. | |
| 9 | − * | |
| 10 | − * Copyright (C) 2003 Hewlett-Packard Co | |
| 11 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 12 | − */ | |
| 13 | − | |
| 14 | −struct elf64_shdr; /* forward declration */ | |
| 15 | − | |
| 16 | −struct mod_arch_specific { | |
| 17 | − /* Used only at module load time. */ | |
| 18 | − struct elf64_shdr *core_plt; /* core PLT section */ | |
| 19 | − struct elf64_shdr *init_plt; /* init PLT section */ | |
| 20 | − struct elf64_shdr *got; /* global offset table */ | |
| 21 | − struct elf64_shdr *opd; /* official procedure descriptors */ | |
| 22 | − struct elf64_shdr *unwind; /* unwind-table section */ | |
| 23 | − unsigned long gp; /* global-pointer for module */ | |
| 24 | − unsigned int next_got_entry; /* index of next available got entry */ | |
| 25 | − | |
| 26 | − /* Used at module run and cleanup time. */ | |
| 27 | − void *core_unw_table; /* core unwind-table cookie returned by unwinder */ | |
| 28 | − void *init_unw_table; /* init unwind-table cookie returned by unwinder */ | |
| 29 | − void *opd_addr; /* symbolize uses .opd to get to actual function */ | |
| 30 | − unsigned long opd_size; | |
| 31 | −}; | |
| 32 | − | |
| 33 | −#define ARCH_SHF_SMALL SHF_IA_64_SHORT | |
| 34 | − | |
| 35 | −#endif /* _ASM_IA64_MODULE_H */ | |
| @@ -1,14 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −SECTIONS { | |
| 3 | − /* Group unwind sections into a single section: */ | |
| 4 | − .IA_64.unwind_info : { *(.IA_64.unwind_info*) } | |
| 5 | − .IA_64.unwind : { *(.IA_64.unwind*) } | |
| 6 | − /* | |
| 7 | − * Create place-holder sections to hold the PLTs, GOT, and | |
| 8 | − * official procedure-descriptors (.opd). | |
| 9 | − */ | |
| 10 | − .core.plt : { BYTE(0) } | |
| 11 | − .init.plt : { BYTE(0) } | |
| 12 | − .got : { BYTE(0) } | |
| 13 | − .opd : { BYTE(0) } | |
| 14 | −} | |
| @@ -1,43 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _IA64_MSI_DEF_H | |
| 3 | −#define _IA64_MSI_DEF_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Shifts for APIC-based data | |
| 7 | − */ | |
| 8 | − | |
| 9 | −#define MSI_DATA_VECTOR_SHIFT 0 | |
| 10 | −#define MSI_DATA_VECTOR(v) (((u8)v) << MSI_DATA_VECTOR_SHIFT) | |
| 11 | −#define MSI_DATA_VECTOR_MASK 0xffffff00 | |
| 12 | − | |
| 13 | −#define MSI_DATA_DELIVERY_MODE_SHIFT 8 | |
| 14 | −#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_MODE_SHIFT) | |
| 15 | −#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_MODE_SHIFT) | |
| 16 | − | |
| 17 | −#define MSI_DATA_LEVEL_SHIFT 14 | |
| 18 | −#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT) | |
| 19 | −#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT) | |
| 20 | − | |
| 21 | −#define MSI_DATA_TRIGGER_SHIFT 15 | |
| 22 | −#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT) | |
| 23 | −#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT) | |
| 24 | − | |
| 25 | −/* | |
| 26 | − * Shift/mask fields for APIC-based bus address | |
| 27 | − */ | |
| 28 | − | |
| 29 | −#define MSI_ADDR_DEST_ID_SHIFT 4 | |
| 30 | −#define MSI_ADDR_HEADER 0xfee00000 | |
| 31 | − | |
| 32 | −#define MSI_ADDR_DEST_ID_MASK 0xfff0000f | |
| 33 | −#define MSI_ADDR_DEST_ID_CPU(cpu) ((cpu) << MSI_ADDR_DEST_ID_SHIFT) | |
| 34 | − | |
| 35 | −#define MSI_ADDR_DEST_MODE_SHIFT 2 | |
| 36 | −#define MSI_ADDR_DEST_MODE_PHYS (0 << MSI_ADDR_DEST_MODE_SHIFT) | |
| 37 | −#define MSI_ADDR_DEST_MODE_LOGIC (1 << MSI_ADDR_DEST_MODE_SHIFT) | |
| 38 | − | |
| 39 | −#define MSI_ADDR_REDIRECTION_SHIFT 3 | |
| 40 | −#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT) | |
| 41 | −#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT) | |
| 42 | − | |
| 43 | −#endif/* _IA64_MSI_DEF_H */ | |
| @@ -1,119 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0-or-later */ | |
| 2 | −/****************************************************************************** | |
| 3 | − * arch/ia64/include/asm/native/inst.h | |
| 4 | − * | |
| 5 | − * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp> | |
| 6 | − * VA Linux Systems Japan K.K. | |
| 7 | − */ | |
| 8 | − | |
| 9 | −#define DO_SAVE_MIN IA64_NATIVE_DO_SAVE_MIN | |
| 10 | − | |
| 11 | −#define MOV_FROM_IFA(reg) \ | |
| 12 | − mov reg = cr.ifa | |
| 13 | − | |
| 14 | −#define MOV_FROM_ITIR(reg) \ | |
| 15 | − mov reg = cr.itir | |
| 16 | − | |
| 17 | −#define MOV_FROM_ISR(reg) \ | |
| 18 | − mov reg = cr.isr | |
| 19 | − | |
| 20 | −#define MOV_FROM_IHA(reg) \ | |
| 21 | − mov reg = cr.iha | |
| 22 | − | |
| 23 | −#define MOV_FROM_IPSR(pred, reg) \ | |
| 24 | −(pred) mov reg = cr.ipsr | |
| 25 | − | |
| 26 | −#define MOV_FROM_IIM(reg) \ | |
| 27 | − mov reg = cr.iim | |
| 28 | − | |
| 29 | −#define MOV_FROM_IIP(reg) \ | |
| 30 | − mov reg = cr.iip | |
| 31 | − | |
| 32 | −#define MOV_FROM_IVR(reg, clob) \ | |
| 33 | − mov reg = cr.ivr | |
| 34 | − | |
| 35 | −#define MOV_FROM_PSR(pred, reg, clob) \ | |
| 36 | −(pred) mov reg = psr | |
| 37 | − | |
| 38 | −#define MOV_FROM_ITC(pred, pred_clob, reg, clob) \ | |
| 39 | −(pred) mov reg = ar.itc | |
| 40 | − | |
| 41 | −#define MOV_TO_IFA(reg, clob) \ | |
| 42 | − mov cr.ifa = reg | |
| 43 | − | |
| 44 | −#define MOV_TO_ITIR(pred, reg, clob) \ | |
| 45 | −(pred) mov cr.itir = reg | |
| 46 | − | |
| 47 | −#define MOV_TO_IHA(pred, reg, clob) \ | |
| 48 | −(pred) mov cr.iha = reg | |
| 49 | − | |
| 50 | −#define MOV_TO_IPSR(pred, reg, clob) \ | |
| 51 | −(pred) mov cr.ipsr = reg | |
| 52 | − | |
| 53 | −#define MOV_TO_IFS(pred, reg, clob) \ | |
| 54 | −(pred) mov cr.ifs = reg | |
| 55 | − | |
| 56 | −#define MOV_TO_IIP(reg, clob) \ | |
| 57 | − mov cr.iip = reg | |
| 58 | − | |
| 59 | −#define MOV_TO_KR(kr, reg, clob0, clob1) \ | |
| 60 | − mov IA64_KR(kr) = reg | |
| 61 | − | |
| 62 | −#define ITC_I(pred, reg, clob) \ | |
| 63 | −(pred) itc.i reg | |
| 64 | − | |
| 65 | −#define ITC_D(pred, reg, clob) \ | |
| 66 | −(pred) itc.d reg | |
| 67 | − | |
| 68 | −#define ITC_I_AND_D(pred_i, pred_d, reg, clob) \ | |
| 69 | −(pred_i) itc.i reg; \ | |
| 70 | −(pred_d) itc.d reg | |
| 71 | − | |
| 72 | −#define THASH(pred, reg0, reg1, clob) \ | |
| 73 | −(pred) thash reg0 = reg1 | |
| 74 | − | |
| 75 | −#define SSM_PSR_IC_AND_DEFAULT_BITS_AND_SRLZ_I(clob0, clob1) \ | |
| 76 | − ssm psr.ic | PSR_DEFAULT_BITS \ | |
| 77 | − ;; \ | |
| 78 | − srlz.i /* guarantee that interruption collectin is on */ \ | |
| 79 | − ;; | |
| 80 | − | |
| 81 | −#define SSM_PSR_IC_AND_SRLZ_D(clob0, clob1) \ | |
| 82 | − ssm psr.ic \ | |
| 83 | − ;; \ | |
| 84 | − srlz.d | |
| 85 | − | |
| 86 | −#define RSM_PSR_IC(clob) \ | |
| 87 | − rsm psr.ic | |
| 88 | − | |
| 89 | −#define SSM_PSR_I(pred, pred_clob, clob) \ | |
| 90 | −(pred) ssm psr.i | |
| 91 | − | |
| 92 | −#define RSM_PSR_I(pred, clob0, clob1) \ | |
| 93 | −(pred) rsm psr.i | |
| 94 | − | |
| 95 | −#define RSM_PSR_I_IC(clob0, clob1, clob2) \ | |
| 96 | − rsm psr.i | psr.ic | |
| 97 | − | |
| 98 | −#define RSM_PSR_DT \ | |
| 99 | − rsm psr.dt | |
| 100 | − | |
| 101 | −#define RSM_PSR_BE_I(clob0, clob1) \ | |
| 102 | − rsm psr.be | psr.i | |
| 103 | − | |
| 104 | −#define SSM_PSR_DT_AND_SRLZ_I \ | |
| 105 | − ssm psr.dt \ | |
| 106 | − ;; \ | |
| 107 | − srlz.i | |
| 108 | − | |
| 109 | −#define BSW_0(clob0, clob1, clob2) \ | |
| 110 | − bsw.0 | |
| 111 | − | |
| 112 | −#define BSW_1(clob0, clob1) \ | |
| 113 | − bsw.1 | |
| 114 | − | |
| 115 | −#define COVER \ | |
| 116 | − cover | |
| 117 | − | |
| 118 | −#define RFI \ | |
| 119 | − rfi | |
| @@ -1,20 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0-or-later */ | |
| 2 | −/****************************************************************************** | |
| 3 | − * arch/ia64/include/asm/native/irq.h | |
| 4 | − * | |
| 5 | − * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp> | |
| 6 | − * VA Linux Systems Japan K.K. | |
| 7 | − */ | |
| 8 | − | |
| 9 | −#ifndef _ASM_IA64_NATIVE_IRQ_H | |
| 10 | −#define _ASM_IA64_NATIVE_IRQ_H | |
| 11 | − | |
| 12 | −#define NR_VECTORS 256 | |
| 13 | − | |
| 14 | −#if (NR_VECTORS + 32 * NR_CPUS) < 1024 | |
| 15 | −#define IA64_NATIVE_NR_IRQS (NR_VECTORS + 32 * NR_CPUS) | |
| 16 | −#else | |
| 17 | −#define IA64_NATIVE_NR_IRQS 1024 | |
| 18 | −#endif | |
| 19 | − | |
| 20 | −#endif /* _ASM_IA64_NATIVE_IRQ_H */ | |
| @@ -1,24 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0-or-later */ | |
| 2 | −/****************************************************************************** | |
| 3 | − * arch/ia64/include/asm/native/inst.h | |
| 4 | − * | |
| 5 | − * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp> | |
| 6 | − * VA Linux Systems Japan K.K. | |
| 7 | − */ | |
| 8 | − | |
| 9 | −#define __paravirt_start_gate_fsyscall_patchlist \ | |
| 10 | − __ia64_native_start_gate_fsyscall_patchlist | |
| 11 | −#define __paravirt_end_gate_fsyscall_patchlist \ | |
| 12 | − __ia64_native_end_gate_fsyscall_patchlist | |
| 13 | −#define __paravirt_start_gate_brl_fsys_bubble_down_patchlist \ | |
| 14 | − __ia64_native_start_gate_brl_fsys_bubble_down_patchlist | |
| 15 | −#define __paravirt_end_gate_brl_fsys_bubble_down_patchlist \ | |
| 16 | − __ia64_native_end_gate_brl_fsys_bubble_down_patchlist | |
| 17 | −#define __paravirt_start_gate_vtop_patchlist \ | |
| 18 | − __ia64_native_start_gate_vtop_patchlist | |
| 19 | −#define __paravirt_end_gate_vtop_patchlist \ | |
| 20 | − __ia64_native_end_gate_vtop_patchlist | |
| 21 | −#define __paravirt_start_gate_mckinley_e9_patchlist \ | |
| 22 | − __ia64_native_start_gate_mckinley_e9_patchlist | |
| 23 | −#define __paravirt_end_gate_mckinley_e9_patchlist \ | |
| 24 | − __ia64_native_end_gate_mckinley_e9_patchlist | |
| @@ -1,63 +0,0 @@ | ||
| 1 | −/* | |
| 2 | − * This file is subject to the terms and conditions of the GNU General Public | |
| 3 | − * License. See the file "COPYING" in the main directory of this archive | |
| 4 | − * for more details. | |
| 5 | − * | |
| 6 | − * Copyright (c) 2000 Silicon Graphics, Inc. All rights reserved. | |
| 7 | − * Copyright (c) 2002 NEC Corp. | |
| 8 | − * Copyright (c) 2002 Erich Focht <efocht@ess.nec.de> | |
| 9 | − * Copyright (c) 2002 Kimio Suganuma <k-suganuma@da.jp.nec.com> | |
| 10 | − */ | |
| 11 | −#ifndef _ASM_IA64_NODEDATA_H | |
| 12 | −#define _ASM_IA64_NODEDATA_H | |
| 13 | − | |
| 14 | −#include <linux/numa.h> | |
| 15 | − | |
| 16 | −#include <asm/percpu.h> | |
| 17 | −#include <asm/mmzone.h> | |
| 18 | − | |
| 19 | −#ifdef CONFIG_NUMA | |
| 20 | − | |
| 21 | −/* | |
| 22 | − * Node Data. One of these structures is located on each node of a NUMA system. | |
| 23 | − */ | |
| 24 | − | |
| 25 | −struct pglist_data; | |
| 26 | −struct ia64_node_data { | |
| 27 | − short active_cpu_count; | |
| 28 | − short node; | |
| 29 | − struct pglist_data *pg_data_ptrs[MAX_NUMNODES]; | |
| 30 | −}; | |
| 31 | − | |
| 32 | − | |
| 33 | −/* | |
| 34 | − * Return a pointer to the node_data structure for the executing cpu. | |
| 35 | − */ | |
| 36 | −#define local_node_data (local_cpu_data->node_data) | |
| 37 | − | |
| 38 | −/* | |
| 39 | − * Given a node id, return a pointer to the pg_data_t for the node. | |
| 40 | − * | |
| 41 | − * NODE_DATA - should be used in all code not related to system | |
| 42 | − * initialization. It uses pernode data structures to minimize | |
| 43 | − * offnode memory references. However, these structure are not | |
| 44 | − * present during boot. This macro can be used once cpu_init | |
| 45 | − * completes. | |
| 46 | − */ | |
| 47 | −#define NODE_DATA(nid) (local_node_data->pg_data_ptrs[nid]) | |
| 48 | − | |
| 49 | −/* | |
| 50 | − * LOCAL_DATA_ADDR - This is to calculate the address of other node's | |
| 51 | − * "local_node_data" at hot-plug phase. The local_node_data | |
| 52 | − * is pointed by per_cpu_page. Kernel usually use it for | |
| 53 | − * just executing cpu. However, when new node is hot-added, | |
| 54 | − * the addresses of local data for other nodes are necessary | |
| 55 | − * to update all of them. | |
| 56 | − */ | |
| 57 | −#define LOCAL_DATA_ADDR(pgdat) \ | |
| 58 | − ((struct ia64_node_data *)((u64)(pgdat) + \ | |
| 59 | − L1_CACHE_ALIGN(sizeof(struct pglist_data)))) | |
| 60 | − | |
| 61 | −#endif /* CONFIG_NUMA */ | |
| 62 | − | |
| 63 | −#endif /* _ASM_IA64_NODEDATA_H */ | |
| @@ -1,83 +0,0 @@ | ||
| 1 | −/* | |
| 2 | − * This file is subject to the terms and conditions of the GNU General Public | |
| 3 | − * License. See the file "COPYING" in the main directory of this archive | |
| 4 | − * for more details. | |
| 5 | − * | |
| 6 | − * This file contains NUMA specific prototypes and definitions. | |
| 7 | − * | |
| 8 | − * 2002/08/05 Erich Focht <efocht@ess.nec.de> | |
| 9 | − * | |
| 10 | − */ | |
| 11 | −#ifndef _ASM_IA64_NUMA_H | |
| 12 | −#define _ASM_IA64_NUMA_H | |
| 13 | − | |
| 14 | − | |
| 15 | −#ifdef CONFIG_NUMA | |
| 16 | − | |
| 17 | −#include <linux/cache.h> | |
| 18 | −#include <linux/cpumask.h> | |
| 19 | −#include <linux/numa.h> | |
| 20 | −#include <linux/smp.h> | |
| 21 | −#include <linux/threads.h> | |
| 22 | − | |
| 23 | −#include <asm/mmzone.h> | |
| 24 | − | |
| 25 | −extern u16 cpu_to_node_map[NR_CPUS] __cacheline_aligned; | |
| 26 | −extern cpumask_t node_to_cpu_mask[MAX_NUMNODES] __cacheline_aligned; | |
| 27 | −extern pg_data_t *pgdat_list[MAX_NUMNODES]; | |
| 28 | − | |
| 29 | −/* Stuff below this line could be architecture independent */ | |
| 30 | − | |
| 31 | −extern int num_node_memblks; /* total number of memory chunks */ | |
| 32 | − | |
| 33 | −/* | |
| 34 | − * List of node memory chunks. Filled when parsing SRAT table to | |
| 35 | − * obtain information about memory nodes. | |
| 36 | −*/ | |
| 37 | − | |
| 38 | −struct node_memblk_s { | |
| 39 | − unsigned long start_paddr; | |
| 40 | − unsigned long size; | |
| 41 | − int nid; /* which logical node contains this chunk? */ | |
| 42 | − int bank; /* which mem bank on this node */ | |
| 43 | −}; | |
| 44 | − | |
| 45 | −struct node_cpuid_s { | |
| 46 | − u16 phys_id; /* id << 8 | eid */ | |
| 47 | − int nid; /* logical node containing this CPU */ | |
| 48 | −}; | |
| 49 | − | |
| 50 | −extern struct node_memblk_s node_memblk[NR_NODE_MEMBLKS]; | |
| 51 | −extern struct node_cpuid_s node_cpuid[NR_CPUS]; | |
| 52 | − | |
| 53 | −/* | |
| 54 | − * ACPI 2.0 SLIT (System Locality Information Table) | |
| 55 | − * http://devresource.hp.com/devresource/Docs/TechPapers/IA64/slit.pdf | |
| 56 | − * | |
| 57 | − * This is a matrix with "distances" between nodes, they should be | |
| 58 | − * proportional to the memory access latency ratios. | |
| 59 | − */ | |
| 60 | − | |
| 61 | −extern u8 numa_slit[MAX_NUMNODES * MAX_NUMNODES]; | |
| 62 | −#define slit_distance(from,to) (numa_slit[(from) * MAX_NUMNODES + (to)]) | |
| 63 | −extern int __node_distance(int from, int to); | |
| 64 | −#define node_distance(from,to) __node_distance(from, to) | |
| 65 | − | |
| 66 | −extern int paddr_to_nid(unsigned long paddr); | |
| 67 | − | |
| 68 | −#define local_nodeid (cpu_to_node_map[smp_processor_id()]) | |
| 69 | − | |
| 70 | −#define numa_off 0 | |
| 71 | − | |
| 72 | −extern void map_cpu_to_node(int cpu, int nid); | |
| 73 | −extern void unmap_cpu_from_node(int cpu, int nid); | |
| 74 | −extern void numa_clear_node(int cpu); | |
| 75 | − | |
| 76 | −#else /* !CONFIG_NUMA */ | |
| 77 | −#define map_cpu_to_node(cpu, nid) do{}while(0) | |
| 78 | −#define unmap_cpu_from_node(cpu, nid) do{}while(0) | |
| 79 | −#define paddr_to_nid(addr) 0 | |
| 80 | −#define numa_clear_node(cpu) do { } while (0) | |
| 81 | −#endif /* CONFIG_NUMA */ | |
| 82 | − | |
| 83 | −#endif /* _ASM_IA64_NUMA_H */ | |
| @@ -1,208 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_PAGE_H | |
| 3 | −#define _ASM_IA64_PAGE_H | |
| 4 | −/* | |
| 5 | − * Pagetable related stuff. | |
| 6 | − * | |
| 7 | − * Copyright (C) 1998, 1999, 2002 Hewlett-Packard Co | |
| 8 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 9 | − */ | |
| 10 | − | |
| 11 | −#include <asm/intrinsics.h> | |
| 12 | −#include <asm/types.h> | |
| 13 | − | |
| 14 | −/* | |
| 15 | − * The top three bits of an IA64 address are its Region Number. | |
| 16 | − * Different regions are assigned to different purposes. | |
| 17 | − */ | |
| 18 | −#define RGN_SHIFT (61) | |
| 19 | −#define RGN_BASE(r) (__IA64_UL_CONST(r)<<RGN_SHIFT) | |
| 20 | −#define RGN_BITS (RGN_BASE(-1)) | |
| 21 | − | |
| 22 | −#define RGN_KERNEL 7 /* Identity mapped region */ | |
| 23 | −#define RGN_UNCACHED 6 /* Identity mapped I/O region */ | |
| 24 | −#define RGN_GATE 5 /* Gate page, Kernel text, etc */ | |
| 25 | −#define RGN_HPAGE 4 /* For Huge TLB pages */ | |
| 26 | − | |
| 27 | −/* | |
| 28 | − * PAGE_SHIFT determines the actual kernel page size. | |
| 29 | − */ | |
| 30 | −#if defined(CONFIG_IA64_PAGE_SIZE_4KB) | |
| 31 | −# define PAGE_SHIFT 12 | |
| 32 | −#elif defined(CONFIG_IA64_PAGE_SIZE_8KB) | |
| 33 | −# define PAGE_SHIFT 13 | |
| 34 | −#elif defined(CONFIG_IA64_PAGE_SIZE_16KB) | |
| 35 | −# define PAGE_SHIFT 14 | |
| 36 | −#elif defined(CONFIG_IA64_PAGE_SIZE_64KB) | |
| 37 | −# define PAGE_SHIFT 16 | |
| 38 | −#else | |
| 39 | −# error Unsupported page size! | |
| 40 | −#endif | |
| 41 | − | |
| 42 | −#define PAGE_SIZE (__IA64_UL_CONST(1) << PAGE_SHIFT) | |
| 43 | −#define PAGE_MASK (~(PAGE_SIZE - 1)) | |
| 44 | − | |
| 45 | −#define PERCPU_PAGE_SHIFT 18 /* log2() of max. size of per-CPU area */ | |
| 46 | −#define PERCPU_PAGE_SIZE (__IA64_UL_CONST(1) << PERCPU_PAGE_SHIFT) | |
| 47 | − | |
| 48 | − | |
| 49 | −#ifdef CONFIG_HUGETLB_PAGE | |
| 50 | −# define HPAGE_REGION_BASE RGN_BASE(RGN_HPAGE) | |
| 51 | −# define HPAGE_SHIFT hpage_shift | |
| 52 | −# define HPAGE_SHIFT_DEFAULT 28 /* check ia64 SDM for architecture supported size */ | |
| 53 | −# define HPAGE_SIZE (__IA64_UL_CONST(1) << HPAGE_SHIFT) | |
| 54 | −# define HPAGE_MASK (~(HPAGE_SIZE - 1)) | |
| 55 | − | |
| 56 | −# define HAVE_ARCH_HUGETLB_UNMAPPED_AREA | |
| 57 | −#endif /* CONFIG_HUGETLB_PAGE */ | |
| 58 | − | |
| 59 | −#ifdef __ASSEMBLY__ | |
| 60 | −# define __pa(x) ((x) - PAGE_OFFSET) | |
| 61 | −# define __va(x) ((x) + PAGE_OFFSET) | |
| 62 | −#else /* !__ASSEMBLY */ | |
| 63 | −# define STRICT_MM_TYPECHECKS | |
| 64 | − | |
| 65 | −extern void clear_page (void *page); | |
| 66 | −extern void copy_page (void *to, void *from); | |
| 67 | − | |
| 68 | −/* | |
| 69 | − * clear_user_page() and copy_user_page() can't be inline functions because | |
| 70 | − * flush_dcache_page() can't be defined until later... | |
| 71 | − */ | |
| 72 | −#define clear_user_page(addr, vaddr, page) \ | |
| 73 | −do { \ | |
| 74 | − clear_page(addr); \ | |
| 75 | − flush_dcache_page(page); \ | |
| 76 | −} while (0) | |
| 77 | − | |
| 78 | −#define copy_user_page(to, from, vaddr, page) \ | |
| 79 | −do { \ | |
| 80 | − copy_page((to), (from)); \ | |
| 81 | − flush_dcache_page(page); \ | |
| 82 | −} while (0) | |
| 83 | − | |
| 84 | − | |
| 85 | −#define vma_alloc_zeroed_movable_folio(vma, vaddr) \ | |
| 86 | −({ \ | |
| 87 | − struct folio *folio = vma_alloc_folio( \ | |
| 88 | − GFP_HIGHUSER_MOVABLE | __GFP_ZERO, 0, vma, vaddr, false); \ | |
| 89 | − if (folio) \ | |
| 90 | − flush_dcache_folio(folio); \ | |
| 91 | − folio; \ | |
| 92 | −}) | |
| 93 | − | |
| 94 | −#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) | |
| 95 | − | |
| 96 | −#include <asm-generic/memory_model.h> | |
| 97 | − | |
| 98 | −#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) | |
| 99 | −#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) | |
| 100 | −#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) | |
| 101 | − | |
| 102 | −typedef union ia64_va { | |
| 103 | − struct { | |
| 104 | − unsigned long off : 61; /* intra-region offset */ | |
| 105 | − unsigned long reg : 3; /* region number */ | |
| 106 | − } f; | |
| 107 | − unsigned long l; | |
| 108 | − void *p; | |
| 109 | −} ia64_va; | |
| 110 | − | |
| 111 | −/* | |
| 112 | − * Note: These macros depend on the fact that PAGE_OFFSET has all | |
| 113 | − * region bits set to 1 and all other bits set to zero. They are | |
| 114 | − * expressed in this way to ensure they result in a single "dep" | |
| 115 | − * instruction. | |
| 116 | − */ | |
| 117 | −#define __pa(x) ({ia64_va _v; _v.l = (long) (x); _v.f.reg = 0; _v.l;}) | |
| 118 | −#define __va(x) ({ia64_va _v; _v.l = (long) (x); _v.f.reg = -1; _v.p;}) | |
| 119 | − | |
| 120 | −#define REGION_NUMBER(x) ({ia64_va _v; _v.l = (long) (x); _v.f.reg;}) | |
| 121 | −#define REGION_OFFSET(x) ({ia64_va _v; _v.l = (long) (x); _v.f.off;}) | |
| 122 | − | |
| 123 | −#ifdef CONFIG_HUGETLB_PAGE | |
| 124 | −# define htlbpage_to_page(x) (((unsigned long) REGION_NUMBER(x) << 61) \ | |
| 125 | − | (REGION_OFFSET(x) >> (HPAGE_SHIFT-PAGE_SHIFT))) | |
| 126 | −# define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) | |
| 127 | −extern unsigned int hpage_shift; | |
| 128 | −#endif | |
| 129 | − | |
| 130 | −static __inline__ int | |
| 131 | −get_order (unsigned long size) | |
| 132 | −{ | |
| 133 | − long double d = size - 1; | |
| 134 | − long order; | |
| 135 | − | |
| 136 | − order = ia64_getf_exp(d); | |
| 137 | − order = order - PAGE_SHIFT - 0xffff + 1; | |
| 138 | − if (order < 0) | |
| 139 | − order = 0; | |
| 140 | − return order; | |
| 141 | −} | |
| 142 | − | |
| 143 | −#endif /* !__ASSEMBLY__ */ | |
| 144 | − | |
| 145 | −#ifdef STRICT_MM_TYPECHECKS | |
| 146 | − /* | |
| 147 | − * These are used to make use of C type-checking.. | |
| 148 | − */ | |
| 149 | − typedef struct { unsigned long pte; } pte_t; | |
| 150 | − typedef struct { unsigned long pmd; } pmd_t; | |
| 151 | −#if CONFIG_PGTABLE_LEVELS == 4 | |
| 152 | − typedef struct { unsigned long pud; } pud_t; | |
| 153 | −#endif | |
| 154 | − typedef struct { unsigned long pgd; } pgd_t; | |
| 155 | − typedef struct { unsigned long pgprot; } pgprot_t; | |
| 156 | − typedef struct page *pgtable_t; | |
| 157 | − | |
| 158 | −# define pte_val(x) ((x).pte) | |
| 159 | −# define pmd_val(x) ((x).pmd) | |
| 160 | −#if CONFIG_PGTABLE_LEVELS == 4 | |
| 161 | −# define pud_val(x) ((x).pud) | |
| 162 | −#endif | |
| 163 | −# define pgd_val(x) ((x).pgd) | |
| 164 | −# define pgprot_val(x) ((x).pgprot) | |
| 165 | − | |
| 166 | −# define __pte(x) ((pte_t) { (x) } ) | |
| 167 | −# define __pmd(x) ((pmd_t) { (x) } ) | |
| 168 | −# define __pgprot(x) ((pgprot_t) { (x) } ) | |
| 169 | − | |
| 170 | −#else /* !STRICT_MM_TYPECHECKS */ | |
| 171 | − /* | |
| 172 | − * .. while these make it easier on the compiler | |
| 173 | − */ | |
| 174 | −# ifndef __ASSEMBLY__ | |
| 175 | − typedef unsigned long pte_t; | |
| 176 | − typedef unsigned long pmd_t; | |
| 177 | − typedef unsigned long pgd_t; | |
| 178 | − typedef unsigned long pgprot_t; | |
| 179 | − typedef struct page *pgtable_t; | |
| 180 | −# endif | |
| 181 | − | |
| 182 | −# define pte_val(x) (x) | |
| 183 | −# define pmd_val(x) (x) | |
| 184 | −# define pgd_val(x) (x) | |
| 185 | −# define pgprot_val(x) (x) | |
| 186 | − | |
| 187 | −# define __pte(x) (x) | |
| 188 | −# define __pgd(x) (x) | |
| 189 | −# define __pgprot(x) (x) | |
| 190 | −#endif /* !STRICT_MM_TYPECHECKS */ | |
| 191 | − | |
| 192 | −#define PAGE_OFFSET RGN_BASE(RGN_KERNEL) | |
| 193 | − | |
| 194 | −#define VM_DATA_DEFAULT_FLAGS VM_DATA_FLAGS_TSK_EXEC | |
| 195 | − | |
| 196 | −#define GATE_ADDR RGN_BASE(RGN_GATE) | |
| 197 | − | |
| 198 | −/* | |
| 199 | − * 0xa000000000000000+2*PERCPU_PAGE_SIZE | |
| 200 | − * - 0xa000000000000000+3*PERCPU_PAGE_SIZE remain unmapped (guard page) | |
| 201 | − */ | |
| 202 | −#define KERNEL_START (GATE_ADDR+__IA64_UL_CONST(0x100000000)) | |
| 203 | −#define PERCPU_ADDR (-PERCPU_PAGE_SIZE) | |
| 204 | −#define LOAD_OFFSET (KERNEL_START - KERNEL_TR_PAGE_SIZE) | |
| 205 | − | |
| 206 | −#define __HAVE_ARCH_GATE_AREA 1 | |
| 207 | − | |
| 208 | −#endif /* _ASM_IA64_PAGE_H */ | |
| @@ -1,1827 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_PAL_H | |
| 3 | −#define _ASM_IA64_PAL_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Processor Abstraction Layer definitions. | |
| 7 | − * | |
| 8 | − * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0 | |
| 9 | − * chapter 11 IA-64 Processor Abstraction Layer | |
| 10 | − * | |
| 11 | − * Copyright (C) 1998-2001 Hewlett-Packard Co | |
| 12 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 13 | − * Stephane Eranian <eranian@hpl.hp.com> | |
| 14 | − * Copyright (C) 1999 VA Linux Systems | |
| 15 | − * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> | |
| 16 | − * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com> | |
| 17 | − * Copyright (C) 2008 Silicon Graphics, Inc. (SGI) | |
| 18 | − * | |
| 19 | − * 99/10/01 davidm Make sure we pass zero for reserved parameters. | |
| 20 | − * 00/03/07 davidm Updated pal_cache_flush() to be in sync with PAL v2.6. | |
| 21 | − * 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info | |
| 22 | − * 00/05/24 eranian Updated to latest PAL spec, fix structures bugs, added | |
| 23 | − * 00/05/25 eranian Support for stack calls, and static physical calls | |
| 24 | − * 00/06/18 eranian Support for stacked physical calls | |
| 25 | − * 06/10/26 rja Support for Intel Itanium Architecture Software Developer's | |
| 26 | − * Manual Rev 2.2 (Jan 2006) | |
| 27 | − */ | |
| 28 | − | |
| 29 | −/* | |
| 30 | − * Note that some of these calls use a static-register only calling | |
| 31 | − * convention which has nothing to do with the regular calling | |
| 32 | − * convention. | |
| 33 | − */ | |
| 34 | −#define PAL_CACHE_FLUSH 1 /* flush i/d cache */ | |
| 35 | −#define PAL_CACHE_INFO 2 /* get detailed i/d cache info */ | |
| 36 | −#define PAL_CACHE_INIT 3 /* initialize i/d cache */ | |
| 37 | −#define PAL_CACHE_SUMMARY 4 /* get summary of cache hierarchy */ | |
| 38 | −#define PAL_MEM_ATTRIB 5 /* list supported memory attributes */ | |
| 39 | −#define PAL_PTCE_INFO 6 /* purge TLB info */ | |
| 40 | −#define PAL_VM_INFO 7 /* return supported virtual memory features */ | |
| 41 | −#define PAL_VM_SUMMARY 8 /* return summary on supported vm features */ | |
| 42 | −#define PAL_BUS_GET_FEATURES 9 /* return processor bus interface features settings */ | |
| 43 | −#define PAL_BUS_SET_FEATURES 10 /* set processor bus features */ | |
| 44 | −#define PAL_DEBUG_INFO 11 /* get number of debug registers */ | |
| 45 | −#define PAL_FIXED_ADDR 12 /* get fixed component of processors's directed address */ | |
| 46 | −#define PAL_FREQ_BASE 13 /* base frequency of the platform */ | |
| 47 | −#define PAL_FREQ_RATIOS 14 /* ratio of processor, bus and ITC frequency */ | |
| 48 | −#define PAL_PERF_MON_INFO 15 /* return performance monitor info */ | |
| 49 | −#define PAL_PLATFORM_ADDR 16 /* set processor interrupt block and IO port space addr */ | |
| 50 | −#define PAL_PROC_GET_FEATURES 17 /* get configurable processor features & settings */ | |
| 51 | −#define PAL_PROC_SET_FEATURES 18 /* enable/disable configurable processor features */ | |
| 52 | −#define PAL_RSE_INFO 19 /* return rse information */ | |
| 53 | −#define PAL_VERSION 20 /* return version of PAL code */ | |
| 54 | −#define PAL_MC_CLEAR_LOG 21 /* clear all processor log info */ | |
| 55 | −#define PAL_MC_DRAIN 22 /* drain operations which could result in an MCA */ | |
| 56 | −#define PAL_MC_EXPECTED 23 /* set/reset expected MCA indicator */ | |
| 57 | −#define PAL_MC_DYNAMIC_STATE 24 /* get processor dynamic state */ | |
| 58 | −#define PAL_MC_ERROR_INFO 25 /* get processor MCA info and static state */ | |
| 59 | −#define PAL_MC_RESUME 26 /* Return to interrupted process */ | |
| 60 | −#define PAL_MC_REGISTER_MEM 27 /* Register memory for PAL to use during MCAs and inits */ | |
| 61 | −#define PAL_HALT 28 /* enter the low power HALT state */ | |
| 62 | −#define PAL_HALT_LIGHT 29 /* enter the low power light halt state*/ | |
| 63 | −#define PAL_COPY_INFO 30 /* returns info needed to relocate PAL */ | |
| 64 | −#define PAL_CACHE_LINE_INIT 31 /* init tags & data of cache line */ | |
| 65 | −#define PAL_PMI_ENTRYPOINT 32 /* register PMI memory entry points with the processor */ | |
| 66 | −#define PAL_ENTER_IA_32_ENV 33 /* enter IA-32 system environment */ | |
| 67 | −#define PAL_VM_PAGE_SIZE 34 /* return vm TC and page walker page sizes */ | |
| 68 | − | |
| 69 | −#define PAL_MEM_FOR_TEST 37 /* get amount of memory needed for late processor test */ | |
| 70 | −#define PAL_CACHE_PROT_INFO 38 /* get i/d cache protection info */ | |
| 71 | −#define PAL_REGISTER_INFO 39 /* return AR and CR register information*/ | |
| 72 | −#define PAL_SHUTDOWN 40 /* enter processor shutdown state */ | |
| 73 | −#define PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */ | |
| 74 | −#define PAL_LOGICAL_TO_PHYSICAL 42 /* returns information on logical to physical processor mapping */ | |
| 75 | −#define PAL_CACHE_SHARED_INFO 43 /* returns information on caches shared by logical processor */ | |
| 76 | −#define PAL_GET_HW_POLICY 48 /* Get current hardware resource sharing policy */ | |
| 77 | −#define PAL_SET_HW_POLICY 49 /* Set current hardware resource sharing policy */ | |
| 78 | −#define PAL_VP_INFO 50 /* Information about virtual processor features */ | |
| 79 | −#define PAL_MC_HW_TRACKING 51 /* Hardware tracking status */ | |
| 80 | − | |
| 81 | −#define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */ | |
| 82 | −#define PAL_HALT_INFO 257 /* return the low power capabilities of processor */ | |
| 83 | −#define PAL_TEST_PROC 258 /* perform late processor self-test */ | |
| 84 | −#define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */ | |
| 85 | −#define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */ | |
| 86 | −#define PAL_VM_TR_READ 261 /* read contents of translation register */ | |
| 87 | −#define PAL_GET_PSTATE 262 /* get the current P-state */ | |
| 88 | −#define PAL_SET_PSTATE 263 /* set the P-state */ | |
| 89 | −#define PAL_BRAND_INFO 274 /* Processor branding information */ | |
| 90 | − | |
| 91 | −#define PAL_GET_PSTATE_TYPE_LASTSET 0 | |
| 92 | −#define PAL_GET_PSTATE_TYPE_AVGANDRESET 1 | |
| 93 | −#define PAL_GET_PSTATE_TYPE_AVGNORESET 2 | |
| 94 | −#define PAL_GET_PSTATE_TYPE_INSTANT 3 | |
| 95 | − | |
| 96 | −#define PAL_MC_ERROR_INJECT 276 /* Injects processor error or returns injection capabilities */ | |
| 97 | − | |
| 98 | −#ifndef __ASSEMBLY__ | |
| 99 | − | |
| 100 | −#include <linux/types.h> | |
| 101 | −#include <asm/fpu.h> | |
| 102 | −#include <asm/intrinsics.h> | |
| 103 | − | |
| 104 | −/* | |
| 105 | − * Data types needed to pass information into PAL procedures and | |
| 106 | − * interpret information returned by them. | |
| 107 | − */ | |
| 108 | − | |
| 109 | −/* Return status from the PAL procedure */ | |
| 110 | −typedef s64 pal_status_t; | |
| 111 | − | |
| 112 | −#define PAL_STATUS_SUCCESS 0 /* No error */ | |
| 113 | −#define PAL_STATUS_UNIMPLEMENTED (-1) /* Unimplemented procedure */ | |
| 114 | −#define PAL_STATUS_EINVAL (-2) /* Invalid argument */ | |
| 115 | −#define PAL_STATUS_ERROR (-3) /* Error */ | |
| 116 | −#define PAL_STATUS_CACHE_INIT_FAIL (-4) /* Could not initialize the | |
| 117 | − * specified level and type of | |
| 118 | − * cache without sideeffects | |
| 119 | − * and "restrict" was 1 | |
| 120 | − */ | |
| 121 | −#define PAL_STATUS_REQUIRES_MEMORY (-9) /* Call requires PAL memory buffer */ | |
| 122 | − | |
| 123 | −/* Processor cache level in the hierarchy */ | |
| 124 | −typedef u64 pal_cache_level_t; | |
| 125 | −#define PAL_CACHE_LEVEL_L0 0 /* L0 */ | |
| 126 | −#define PAL_CACHE_LEVEL_L1 1 /* L1 */ | |
| 127 | −#define PAL_CACHE_LEVEL_L2 2 /* L2 */ | |
| 128 | − | |
| 129 | − | |
| 130 | −/* Processor cache type at a particular level in the hierarchy */ | |
| 131 | − | |
| 132 | −typedef u64 pal_cache_type_t; | |
| 133 | −#define PAL_CACHE_TYPE_INSTRUCTION 1 /* Instruction cache */ | |
| 134 | −#define PAL_CACHE_TYPE_DATA 2 /* Data or unified cache */ | |
| 135 | −#define PAL_CACHE_TYPE_INSTRUCTION_DATA 3 /* Both Data & Instruction */ | |
| 136 | − | |
| 137 | − | |
| 138 | −#define PAL_CACHE_FLUSH_INVALIDATE 1 /* Invalidate clean lines */ | |
| 139 | −#define PAL_CACHE_FLUSH_CHK_INTRS 2 /* check for interrupts/mc while flushing */ | |
| 140 | − | |
| 141 | −/* Processor cache line size in bytes */ | |
| 142 | −typedef int pal_cache_line_size_t; | |
| 143 | − | |
| 144 | −/* Processor cache line state */ | |
| 145 | −typedef u64 pal_cache_line_state_t; | |
| 146 | −#define PAL_CACHE_LINE_STATE_INVALID 0 /* Invalid */ | |
| 147 | −#define PAL_CACHE_LINE_STATE_SHARED 1 /* Shared */ | |
| 148 | −#define PAL_CACHE_LINE_STATE_EXCLUSIVE 2 /* Exclusive */ | |
| 149 | −#define PAL_CACHE_LINE_STATE_MODIFIED 3 /* Modified */ | |
| 150 | − | |
| 151 | −typedef struct pal_freq_ratio { | |
| 152 | − u32 den, num; /* numerator & denominator */ | |
| 153 | −} itc_ratio, proc_ratio; | |
| 154 | − | |
| 155 | −typedef union pal_cache_config_info_1_s { | |
| 156 | − struct { | |
| 157 | − u64 u : 1, /* 0 Unified cache ? */ | |
| 158 | − at : 2, /* 2-1 Cache mem attr*/ | |
| 159 | − reserved : 5, /* 7-3 Reserved */ | |
| 160 | − associativity : 8, /* 16-8 Associativity*/ | |
| 161 | − line_size : 8, /* 23-17 Line size */ | |
| 162 | − stride : 8, /* 31-24 Stride */ | |
| 163 | − store_latency : 8, /*39-32 Store latency*/ | |
| 164 | − load_latency : 8, /* 47-40 Load latency*/ | |
| 165 | − store_hints : 8, /* 55-48 Store hints*/ | |
| 166 | − load_hints : 8; /* 63-56 Load hints */ | |
| 167 | − } pcci1_bits; | |
| 168 | − u64 pcci1_data; | |
| 169 | −} pal_cache_config_info_1_t; | |
| 170 | − | |
| 171 | −typedef union pal_cache_config_info_2_s { | |
| 172 | − struct { | |
| 173 | − u32 cache_size; /*cache size in bytes*/ | |
| 174 | − | |
| 175 | − | |
| 176 | − u32 alias_boundary : 8, /* 39-32 aliased addr | |
| 177 | − * separation for max | |
| 178 | − * performance. | |
| 179 | − */ | |
| 180 | − tag_ls_bit : 8, /* 47-40 LSb of addr*/ | |
| 181 | − tag_ms_bit : 8, /* 55-48 MSb of addr*/ | |
| 182 | − reserved : 8; /* 63-56 Reserved */ | |
| 183 | − } pcci2_bits; | |
| 184 | − u64 pcci2_data; | |
| 185 | −} pal_cache_config_info_2_t; | |
| 186 | − | |
| 187 | − | |
| 188 | −typedef struct pal_cache_config_info_s { | |
| 189 | − pal_status_t pcci_status; | |
| 190 | − pal_cache_config_info_1_t pcci_info_1; | |
| 191 | − pal_cache_config_info_2_t pcci_info_2; | |
| 192 | − u64 pcci_reserved; | |
| 193 | −} pal_cache_config_info_t; | |
| 194 | − | |
| 195 | −#define pcci_ld_hints pcci_info_1.pcci1_bits.load_hints | |
| 196 | −#define pcci_st_hints pcci_info_1.pcci1_bits.store_hints | |
| 197 | −#define pcci_ld_latency pcci_info_1.pcci1_bits.load_latency | |
| 198 | −#define pcci_st_latency pcci_info_1.pcci1_bits.store_latency | |
| 199 | −#define pcci_stride pcci_info_1.pcci1_bits.stride | |
| 200 | −#define pcci_line_size pcci_info_1.pcci1_bits.line_size | |
| 201 | −#define pcci_assoc pcci_info_1.pcci1_bits.associativity | |
| 202 | −#define pcci_cache_attr pcci_info_1.pcci1_bits.at | |
| 203 | −#define pcci_unified pcci_info_1.pcci1_bits.u | |
| 204 | −#define pcci_tag_msb pcci_info_2.pcci2_bits.tag_ms_bit | |
| 205 | −#define pcci_tag_lsb pcci_info_2.pcci2_bits.tag_ls_bit | |
| 206 | −#define pcci_alias_boundary pcci_info_2.pcci2_bits.alias_boundary | |
| 207 | −#define pcci_cache_size pcci_info_2.pcci2_bits.cache_size | |
| 208 | − | |
| 209 | − | |
| 210 | − | |
| 211 | −/* Possible values for cache attributes */ | |
| 212 | − | |
| 213 | −#define PAL_CACHE_ATTR_WT 0 /* Write through cache */ | |
| 214 | −#define PAL_CACHE_ATTR_WB 1 /* Write back cache */ | |
| 215 | −#define PAL_CACHE_ATTR_WT_OR_WB 2 /* Either write thru or write | |
| 216 | − * back depending on TLB | |
| 217 | − * memory attributes | |
| 218 | − */ | |
| 219 | − | |
| 220 | − | |
| 221 | −/* Possible values for cache hints */ | |
| 222 | − | |
| 223 | −#define PAL_CACHE_HINT_TEMP_1 0 /* Temporal level 1 */ | |
| 224 | −#define PAL_CACHE_HINT_NTEMP_1 1 /* Non-temporal level 1 */ | |
| 225 | −#define PAL_CACHE_HINT_NTEMP_ALL 3 /* Non-temporal all levels */ | |
| 226 | − | |
| 227 | −/* Processor cache protection information */ | |
| 228 | −typedef union pal_cache_protection_element_u { | |
| 229 | − u32 pcpi_data; | |
| 230 | − struct { | |
| 231 | − u32 data_bits : 8, /* # data bits covered by | |
| 232 | − * each unit of protection | |
| 233 | − */ | |
| 234 | − | |
| 235 | − tagprot_lsb : 6, /* Least -do- */ | |
| 236 | − tagprot_msb : 6, /* Most Sig. tag address | |
| 237 | − * bit that this | |
| 238 | − * protection covers. | |
| 239 | − */ | |
| 240 | − prot_bits : 6, /* # of protection bits */ | |
| 241 | − method : 4, /* Protection method */ | |
| 242 | − t_d : 2; /* Indicates which part | |
| 243 | − * of the cache this | |
| 244 | − * protection encoding | |
| 245 | − * applies. | |
| 246 | − */ | |
| 247 | − } pcp_info; | |
| 248 | −} pal_cache_protection_element_t; | |
| 249 | − | |
| 250 | −#define pcpi_cache_prot_part pcp_info.t_d | |
| 251 | −#define pcpi_prot_method pcp_info.method | |
| 252 | −#define pcpi_prot_bits pcp_info.prot_bits | |
| 253 | −#define pcpi_tagprot_msb pcp_info.tagprot_msb | |
| 254 | −#define pcpi_tagprot_lsb pcp_info.tagprot_lsb | |
| 255 | −#define pcpi_data_bits pcp_info.data_bits | |
| 256 | − | |
| 257 | −/* Processor cache part encodings */ | |
| 258 | −#define PAL_CACHE_PROT_PART_DATA 0 /* Data protection */ | |
| 259 | −#define PAL_CACHE_PROT_PART_TAG 1 /* Tag protection */ | |
| 260 | −#define PAL_CACHE_PROT_PART_TAG_DATA 2 /* Tag+data protection (tag is | |
| 261 | − * more significant ) | |
| 262 | − */ | |
| 263 | −#define PAL_CACHE_PROT_PART_DATA_TAG 3 /* Data+tag protection (data is | |
| 264 | − * more significant ) | |
| 265 | − */ | |
| 266 | −#define PAL_CACHE_PROT_PART_MAX 6 | |
| 267 | − | |
| 268 | − | |
| 269 | −typedef struct pal_cache_protection_info_s { | |
| 270 | − pal_status_t pcpi_status; | |
| 271 | − pal_cache_protection_element_t pcp_info[PAL_CACHE_PROT_PART_MAX]; | |
| 272 | −} pal_cache_protection_info_t; | |
| 273 | − | |
| 274 | − | |
| 275 | −/* Processor cache protection method encodings */ | |
| 276 | −#define PAL_CACHE_PROT_METHOD_NONE 0 /* No protection */ | |
| 277 | −#define PAL_CACHE_PROT_METHOD_ODD_PARITY 1 /* Odd parity */ | |
| 278 | −#define PAL_CACHE_PROT_METHOD_EVEN_PARITY 2 /* Even parity */ | |
| 279 | −#define PAL_CACHE_PROT_METHOD_ECC 3 /* ECC protection */ | |
| 280 | − | |
| 281 | − | |
| 282 | −/* Processor cache line identification in the hierarchy */ | |
| 283 | −typedef union pal_cache_line_id_u { | |
| 284 | − u64 pclid_data; | |
| 285 | − struct { | |
| 286 | − u64 cache_type : 8, /* 7-0 cache type */ | |
| 287 | − level : 8, /* 15-8 level of the | |
| 288 | − * cache in the | |
| 289 | − * hierarchy. | |
| 290 | − */ | |
| 291 | − way : 8, /* 23-16 way in the set | |
| 292 | − */ | |
| 293 | − part : 8, /* 31-24 part of the | |
| 294 | − * cache | |
| 295 | − */ | |
| 296 | − reserved : 32; /* 63-32 is reserved*/ | |
| 297 | − } pclid_info_read; | |
| 298 | − struct { | |
| 299 | − u64 cache_type : 8, /* 7-0 cache type */ | |
| 300 | − level : 8, /* 15-8 level of the | |
| 301 | − * cache in the | |
| 302 | − * hierarchy. | |
| 303 | − */ | |
| 304 | − way : 8, /* 23-16 way in the set | |
| 305 | − */ | |
| 306 | − part : 8, /* 31-24 part of the | |
| 307 | − * cache | |
| 308 | − */ | |
| 309 | − mesi : 8, /* 39-32 cache line | |
| 310 | − * state | |
| 311 | − */ | |
| 312 | − start : 8, /* 47-40 lsb of data to | |
| 313 | − * invert | |
| 314 | − */ | |
| 315 | − length : 8, /* 55-48 #bits to | |
| 316 | − * invert | |
| 317 | − */ | |
| 318 | − trigger : 8; /* 63-56 Trigger error | |
| 319 | − * by doing a load | |
| 320 | − * after the write | |
| 321 | − */ | |
| 322 | − | |
| 323 | − } pclid_info_write; | |
| 324 | −} pal_cache_line_id_u_t; | |
| 325 | − | |
| 326 | −#define pclid_read_part pclid_info_read.part | |
| 327 | −#define pclid_read_way pclid_info_read.way | |
| 328 | −#define pclid_read_level pclid_info_read.level | |
| 329 | −#define pclid_read_cache_type pclid_info_read.cache_type | |
| 330 | − | |
| 331 | −#define pclid_write_trigger pclid_info_write.trigger | |
| 332 | −#define pclid_write_length pclid_info_write.length | |
| 333 | −#define pclid_write_start pclid_info_write.start | |
| 334 | −#define pclid_write_mesi pclid_info_write.mesi | |
| 335 | −#define pclid_write_part pclid_info_write.part | |
| 336 | −#define pclid_write_way pclid_info_write.way | |
| 337 | −#define pclid_write_level pclid_info_write.level | |
| 338 | −#define pclid_write_cache_type pclid_info_write.cache_type | |
| 339 | − | |
| 340 | −/* Processor cache line part encodings */ | |
| 341 | −#define PAL_CACHE_LINE_ID_PART_DATA 0 /* Data */ | |
| 342 | −#define PAL_CACHE_LINE_ID_PART_TAG 1 /* Tag */ | |
| 343 | −#define PAL_CACHE_LINE_ID_PART_DATA_PROT 2 /* Data protection */ | |
| 344 | −#define PAL_CACHE_LINE_ID_PART_TAG_PROT 3 /* Tag protection */ | |
| 345 | −#define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT 4 /* Data+tag | |
| 346 | − * protection | |
| 347 | − */ | |
| 348 | −typedef struct pal_cache_line_info_s { | |
| 349 | − pal_status_t pcli_status; /* Return status of the read cache line | |
| 350 | − * info call. | |
| 351 | − */ | |
| 352 | − u64 pcli_data; /* 64-bit data, tag, protection bits .. */ | |
| 353 | − u64 pcli_data_len; /* data length in bits */ | |
| 354 | − pal_cache_line_state_t pcli_cache_line_state; /* mesi state */ | |
| 355 | − | |
| 356 | −} pal_cache_line_info_t; | |
| 357 | − | |
| 358 | − | |
| 359 | −/* Machine Check related crap */ | |
| 360 | − | |
| 361 | −/* Pending event status bits */ | |
| 362 | −typedef u64 pal_mc_pending_events_t; | |
| 363 | − | |
| 364 | −#define PAL_MC_PENDING_MCA (1 << 0) | |
| 365 | −#define PAL_MC_PENDING_INIT (1 << 1) | |
| 366 | − | |
| 367 | −/* Error information type */ | |
| 368 | −typedef u64 pal_mc_info_index_t; | |
| 369 | − | |
| 370 | −#define PAL_MC_INFO_PROCESSOR 0 /* Processor */ | |
| 371 | −#define PAL_MC_INFO_CACHE_CHECK 1 /* Cache check */ | |
| 372 | −#define PAL_MC_INFO_TLB_CHECK 2 /* Tlb check */ | |
| 373 | −#define PAL_MC_INFO_BUS_CHECK 3 /* Bus check */ | |
| 374 | −#define PAL_MC_INFO_REQ_ADDR 4 /* Requestor address */ | |
| 375 | −#define PAL_MC_INFO_RESP_ADDR 5 /* Responder address */ | |
| 376 | −#define PAL_MC_INFO_TARGET_ADDR 6 /* Target address */ | |
| 377 | −#define PAL_MC_INFO_IMPL_DEP 7 /* Implementation | |
| 378 | − * dependent | |
| 379 | − */ | |
| 380 | − | |
| 381 | −#define PAL_TLB_CHECK_OP_PURGE 8 | |
| 382 | − | |
| 383 | −typedef struct pal_process_state_info_s { | |
| 384 | − u64 reserved1 : 2, | |
| 385 | − rz : 1, /* PAL_CHECK processor | |
| 386 | − * rendezvous | |
| 387 | − * successful. | |
| 388 | − */ | |
| 389 | − | |
| 390 | − ra : 1, /* PAL_CHECK attempted | |
| 391 | − * a rendezvous. | |
| 392 | − */ | |
| 393 | − me : 1, /* Distinct multiple | |
| 394 | − * errors occurred | |
| 395 | − */ | |
| 396 | − | |
| 397 | − mn : 1, /* Min. state save | |
| 398 | − * area has been | |
| 399 | − * registered with PAL | |
| 400 | − */ | |
| 401 | − | |
| 402 | − sy : 1, /* Storage integrity | |
| 403 | − * synched | |
| 404 | − */ | |
| 405 | − | |
| 406 | − | |
| 407 | − co : 1, /* Continuable */ | |
| 408 | − ci : 1, /* MC isolated */ | |
| 409 | − us : 1, /* Uncontained storage | |
| 410 | − * damage. | |
| 411 | − */ | |
| 412 | − | |
| 413 | − | |
| 414 | − hd : 1, /* Non-essential hw | |
| 415 | − * lost (no loss of | |
| 416 | − * functionality) | |
| 417 | − * causing the | |
| 418 | − * processor to run in | |
| 419 | − * degraded mode. | |
| 420 | − */ | |
| 421 | − | |
| 422 | − tl : 1, /* 1 => MC occurred | |
| 423 | − * after an instr was | |
| 424 | − * executed but before | |
| 425 | − * the trap that | |
| 426 | − * resulted from instr | |
| 427 | − * execution was | |
| 428 | − * generated. | |
| 429 | − * (Trap Lost ) | |
| 430 | − */ | |
| 431 | − mi : 1, /* More information available | |
| 432 | − * call PAL_MC_ERROR_INFO | |
| 433 | − */ | |
| 434 | − pi : 1, /* Precise instruction pointer */ | |
| 435 | − pm : 1, /* Precise min-state save area */ | |
| 436 | − | |
| 437 | − dy : 1, /* Processor dynamic | |
| 438 | − * state valid | |
| 439 | − */ | |
| 440 | − | |
| 441 | − | |
| 442 | − in : 1, /* 0 = MC, 1 = INIT */ | |
| 443 | − rs : 1, /* RSE valid */ | |
| 444 | − cm : 1, /* MC corrected */ | |
| 445 | − ex : 1, /* MC is expected */ | |
| 446 | − cr : 1, /* Control regs valid*/ | |
| 447 | − pc : 1, /* Perf cntrs valid */ | |
| 448 | − dr : 1, /* Debug regs valid */ | |
| 449 | − tr : 1, /* Translation regs | |
| 450 | − * valid | |
| 451 | − */ | |
| 452 | − rr : 1, /* Region regs valid */ | |
| 453 | − ar : 1, /* App regs valid */ | |
| 454 | − br : 1, /* Branch regs valid */ | |
| 455 | − pr : 1, /* Predicate registers | |
| 456 | − * valid | |
| 457 | − */ | |
| 458 | − | |
| 459 | − fp : 1, /* fp registers valid*/ | |
| 460 | − b1 : 1, /* Preserved bank one | |
| 461 | − * general registers | |
| 462 | − * are valid | |
| 463 | − */ | |
| 464 | − b0 : 1, /* Preserved bank zero | |
| 465 | − * general registers | |
| 466 | − * are valid | |
| 467 | − */ | |
| 468 | − gr : 1, /* General registers | |
| 469 | − * are valid | |
| 470 | − * (excl. banked regs) | |
| 471 | − */ | |
| 472 | − dsize : 16, /* size of dynamic | |
| 473 | − * state returned | |
| 474 | − * by the processor | |
| 475 | − */ | |
| 476 | − | |
| 477 | − se : 1, /* Shared error. MCA in a | |
| 478 | − shared structure */ | |
| 479 | − reserved2 : 10, | |
| 480 | − cc : 1, /* Cache check */ | |
| 481 | − tc : 1, /* TLB check */ | |
| 482 | − bc : 1, /* Bus check */ | |
| 483 | − rc : 1, /* Register file check */ | |
| 484 | − uc : 1; /* Uarch check */ | |
| 485 | − | |
| 486 | −} pal_processor_state_info_t; | |
| 487 | − | |
| 488 | −typedef struct pal_cache_check_info_s { | |
| 489 | − u64 op : 4, /* Type of cache | |
| 490 | − * operation that | |
| 491 | − * caused the machine | |
| 492 | − * check. | |
| 493 | − */ | |
| 494 | − level : 2, /* Cache level */ | |
| 495 | − reserved1 : 2, | |
| 496 | − dl : 1, /* Failure in data part | |
| 497 | − * of cache line | |
| 498 | − */ | |
| 499 | − tl : 1, /* Failure in tag part | |
| 500 | − * of cache line | |
| 501 | − */ | |
| 502 | − dc : 1, /* Failure in dcache */ | |
| 503 | − ic : 1, /* Failure in icache */ | |
| 504 | − mesi : 3, /* Cache line state */ | |
| 505 | − mv : 1, /* mesi valid */ | |
| 506 | − way : 5, /* Way in which the | |
| 507 | − * error occurred | |
| 508 | − */ | |
| 509 | − wiv : 1, /* Way field valid */ | |
| 510 | − reserved2 : 1, | |
| 511 | − dp : 1, /* Data poisoned on MBE */ | |
| 512 | − reserved3 : 6, | |
| 513 | − hlth : 2, /* Health indicator */ | |
| 514 | − | |
| 515 | − index : 20, /* Cache line index */ | |
| 516 | − reserved4 : 2, | |
| 517 | − | |
| 518 | − is : 1, /* instruction set (1 == ia32) */ | |
| 519 | − iv : 1, /* instruction set field valid */ | |
| 520 | − pl : 2, /* privilege level */ | |
| 521 | − pv : 1, /* privilege level field valid */ | |
| 522 | − mcc : 1, /* Machine check corrected */ | |
| 523 | − tv : 1, /* Target address | |
| 524 | − * structure is valid | |
| 525 | − */ | |
| 526 | − rq : 1, /* Requester identifier | |
| 527 | − * structure is valid | |
| 528 | − */ | |
| 529 | − rp : 1, /* Responder identifier | |
| 530 | − * structure is valid | |
| 531 | − */ | |
| 532 | − pi : 1; /* Precise instruction pointer | |
| 533 | − * structure is valid | |
| 534 | − */ | |
| 535 | −} pal_cache_check_info_t; | |
| 536 | − | |
| 537 | −typedef struct pal_tlb_check_info_s { | |
| 538 | − | |
| 539 | − u64 tr_slot : 8, /* Slot# of TR where | |
| 540 | − * error occurred | |
| 541 | − */ | |
| 542 | − trv : 1, /* tr_slot field is valid */ | |
| 543 | − reserved1 : 1, | |
| 544 | − level : 2, /* TLB level where failure occurred */ | |
| 545 | − reserved2 : 4, | |
| 546 | − dtr : 1, /* Fail in data TR */ | |
| 547 | − itr : 1, /* Fail in inst TR */ | |
| 548 | − dtc : 1, /* Fail in data TC */ | |
| 549 | − itc : 1, /* Fail in inst. TC */ | |
| 550 | − op : 4, /* Cache operation */ | |
| 551 | − reserved3 : 6, | |
| 552 | − hlth : 2, /* Health indicator */ | |
| 553 | − reserved4 : 22, | |
| 554 | − | |
| 555 | − is : 1, /* instruction set (1 == ia32) */ | |
| 556 | − iv : 1, /* instruction set field valid */ | |
| 557 | − pl : 2, /* privilege level */ | |
| 558 | − pv : 1, /* privilege level field valid */ | |
| 559 | − mcc : 1, /* Machine check corrected */ | |
| 560 | − tv : 1, /* Target address | |
| 561 | − * structure is valid | |
| 562 | − */ | |
| 563 | − rq : 1, /* Requester identifier | |
| 564 | − * structure is valid | |
| 565 | − */ | |
| 566 | − rp : 1, /* Responder identifier | |
| 567 | − * structure is valid | |
| 568 | − */ | |
| 569 | − pi : 1; /* Precise instruction pointer | |
| 570 | − * structure is valid | |
| 571 | − */ | |
| 572 | −} pal_tlb_check_info_t; | |
| 573 | − | |
| 574 | −typedef struct pal_bus_check_info_s { | |
| 575 | − u64 size : 5, /* Xaction size */ | |
| 576 | − ib : 1, /* Internal bus error */ | |
| 577 | − eb : 1, /* External bus error */ | |
| 578 | − cc : 1, /* Error occurred | |
| 579 | − * during cache-cache | |
| 580 | − * transfer. | |
| 581 | − */ | |
| 582 | − type : 8, /* Bus xaction type*/ | |
| 583 | − sev : 5, /* Bus error severity*/ | |
| 584 | − hier : 2, /* Bus hierarchy level */ | |
| 585 | − dp : 1, /* Data poisoned on MBE */ | |
| 586 | − bsi : 8, /* Bus error status | |
| 587 | − * info | |
| 588 | − */ | |
| 589 | − reserved2 : 22, | |
| 590 | − | |
| 591 | − is : 1, /* instruction set (1 == ia32) */ | |
| 592 | − iv : 1, /* instruction set field valid */ | |
| 593 | − pl : 2, /* privilege level */ | |
| 594 | − pv : 1, /* privilege level field valid */ | |
| 595 | − mcc : 1, /* Machine check corrected */ | |
| 596 | − tv : 1, /* Target address | |
| 597 | − * structure is valid | |
| 598 | − */ | |
| 599 | − rq : 1, /* Requester identifier | |
| 600 | − * structure is valid | |
| 601 | − */ | |
| 602 | − rp : 1, /* Responder identifier | |
| 603 | − * structure is valid | |
| 604 | − */ | |
| 605 | − pi : 1; /* Precise instruction pointer | |
| 606 | − * structure is valid | |
| 607 | − */ | |
| 608 | −} pal_bus_check_info_t; | |
| 609 | − | |
| 610 | −typedef struct pal_reg_file_check_info_s { | |
| 611 | − u64 id : 4, /* Register file identifier */ | |
| 612 | − op : 4, /* Type of register | |
| 613 | − * operation that | |
| 614 | − * caused the machine | |
| 615 | − * check. | |
| 616 | − */ | |
| 617 | − reg_num : 7, /* Register number */ | |
| 618 | − rnv : 1, /* reg_num valid */ | |
| 619 | − reserved2 : 38, | |
| 620 | − | |
| 621 | − is : 1, /* instruction set (1 == ia32) */ | |
| 622 | − iv : 1, /* instruction set field valid */ | |
| 623 | − pl : 2, /* privilege level */ | |
| 624 | − pv : 1, /* privilege level field valid */ | |
| 625 | − mcc : 1, /* Machine check corrected */ | |
| 626 | − reserved3 : 3, | |
| 627 | − pi : 1; /* Precise instruction pointer | |
| 628 | − * structure is valid | |
| 629 | − */ | |
| 630 | −} pal_reg_file_check_info_t; | |
| 631 | − | |
| 632 | −typedef struct pal_uarch_check_info_s { | |
| 633 | − u64 sid : 5, /* Structure identification */ | |
| 634 | − level : 3, /* Level of failure */ | |
| 635 | − array_id : 4, /* Array identification */ | |
| 636 | − op : 4, /* Type of | |
| 637 | − * operation that | |
| 638 | − * caused the machine | |
| 639 | − * check. | |
| 640 | − */ | |
| 641 | − way : 6, /* Way of structure */ | |
| 642 | − wv : 1, /* way valid */ | |
| 643 | − xv : 1, /* index valid */ | |
| 644 | − reserved1 : 6, | |
| 645 | − hlth : 2, /* Health indicator */ | |
| 646 | − index : 8, /* Index or set of the uarch | |
| 647 | − * structure that failed. | |
| 648 | − */ | |
| 649 | − reserved2 : 24, | |
| 650 | − | |
| 651 | − is : 1, /* instruction set (1 == ia32) */ | |
| 652 | − iv : 1, /* instruction set field valid */ | |
| 653 | − pl : 2, /* privilege level */ | |
| 654 | − pv : 1, /* privilege level field valid */ | |
| 655 | − mcc : 1, /* Machine check corrected */ | |
| 656 | − tv : 1, /* Target address | |
| 657 | − * structure is valid | |
| 658 | − */ | |
| 659 | − rq : 1, /* Requester identifier | |
| 660 | − * structure is valid | |
| 661 | − */ | |
| 662 | − rp : 1, /* Responder identifier | |
| 663 | − * structure is valid | |
| 664 | − */ | |
| 665 | − pi : 1; /* Precise instruction pointer | |
| 666 | − * structure is valid | |
| 667 | − */ | |
| 668 | −} pal_uarch_check_info_t; | |
| 669 | − | |
| 670 | −typedef union pal_mc_error_info_u { | |
| 671 | − u64 pmei_data; | |
| 672 | − pal_processor_state_info_t pme_processor; | |
| 673 | − pal_cache_check_info_t pme_cache; | |
| 674 | − pal_tlb_check_info_t pme_tlb; | |
| 675 | − pal_bus_check_info_t pme_bus; | |
| 676 | − pal_reg_file_check_info_t pme_reg_file; | |
| 677 | − pal_uarch_check_info_t pme_uarch; | |
| 678 | −} pal_mc_error_info_t; | |
| 679 | − | |
| 680 | −#define pmci_proc_unknown_check pme_processor.uc | |
| 681 | −#define pmci_proc_bus_check pme_processor.bc | |
| 682 | −#define pmci_proc_tlb_check pme_processor.tc | |
| 683 | −#define pmci_proc_cache_check pme_processor.cc | |
| 684 | −#define pmci_proc_dynamic_state_size pme_processor.dsize | |
| 685 | −#define pmci_proc_gpr_valid pme_processor.gr | |
| 686 | −#define pmci_proc_preserved_bank0_gpr_valid pme_processor.b0 | |
| 687 | −#define pmci_proc_preserved_bank1_gpr_valid pme_processor.b1 | |
| 688 | −#define pmci_proc_fp_valid pme_processor.fp | |
| 689 | −#define pmci_proc_predicate_regs_valid pme_processor.pr | |
| 690 | −#define pmci_proc_branch_regs_valid pme_processor.br | |
| 691 | −#define pmci_proc_app_regs_valid pme_processor.ar | |
| 692 | −#define pmci_proc_region_regs_valid pme_processor.rr | |
| 693 | −#define pmci_proc_translation_regs_valid pme_processor.tr | |
| 694 | −#define pmci_proc_debug_regs_valid pme_processor.dr | |
| 695 | −#define pmci_proc_perf_counters_valid pme_processor.pc | |
| 696 | −#define pmci_proc_control_regs_valid pme_processor.cr | |
| 697 | −#define pmci_proc_machine_check_expected pme_processor.ex | |
| 698 | −#define pmci_proc_machine_check_corrected pme_processor.cm | |
| 699 | −#define pmci_proc_rse_valid pme_processor.rs | |
| 700 | −#define pmci_proc_machine_check_or_init pme_processor.in | |
| 701 | −#define pmci_proc_dynamic_state_valid pme_processor.dy | |
| 702 | −#define pmci_proc_operation pme_processor.op | |
| 703 | −#define pmci_proc_trap_lost pme_processor.tl | |
| 704 | −#define pmci_proc_hardware_damage pme_processor.hd | |
| 705 | −#define pmci_proc_uncontained_storage_damage pme_processor.us | |
| 706 | −#define pmci_proc_machine_check_isolated pme_processor.ci | |
| 707 | −#define pmci_proc_continuable pme_processor.co | |
| 708 | −#define pmci_proc_storage_intergrity_synced pme_processor.sy | |
| 709 | −#define pmci_proc_min_state_save_area_regd pme_processor.mn | |
| 710 | −#define pmci_proc_distinct_multiple_errors pme_processor.me | |
| 711 | −#define pmci_proc_pal_attempted_rendezvous pme_processor.ra | |
| 712 | −#define pmci_proc_pal_rendezvous_complete pme_processor.rz | |
| 713 | − | |
| 714 | − | |
| 715 | −#define pmci_cache_level pme_cache.level | |
| 716 | −#define pmci_cache_line_state pme_cache.mesi | |
| 717 | −#define pmci_cache_line_state_valid pme_cache.mv | |
| 718 | −#define pmci_cache_line_index pme_cache.index | |
| 719 | −#define pmci_cache_instr_cache_fail pme_cache.ic | |
| 720 | −#define pmci_cache_data_cache_fail pme_cache.dc | |
| 721 | −#define pmci_cache_line_tag_fail pme_cache.tl | |
| 722 | −#define pmci_cache_line_data_fail pme_cache.dl | |
| 723 | −#define pmci_cache_operation pme_cache.op | |
| 724 | −#define pmci_cache_way_valid pme_cache.wv | |
| 725 | −#define pmci_cache_target_address_valid pme_cache.tv | |
| 726 | −#define pmci_cache_way pme_cache.way | |
| 727 | −#define pmci_cache_mc pme_cache.mc | |
| 728 | − | |
| 729 | −#define pmci_tlb_instr_translation_cache_fail pme_tlb.itc | |
| 730 | −#define pmci_tlb_data_translation_cache_fail pme_tlb.dtc | |
| 731 | −#define pmci_tlb_instr_translation_reg_fail pme_tlb.itr | |
| 732 | −#define pmci_tlb_data_translation_reg_fail pme_tlb.dtr | |
| 733 | −#define pmci_tlb_translation_reg_slot pme_tlb.tr_slot | |
| 734 | −#define pmci_tlb_mc pme_tlb.mc | |
| 735 | − | |
| 736 | −#define pmci_bus_status_info pme_bus.bsi | |
| 737 | −#define pmci_bus_req_address_valid pme_bus.rq | |
| 738 | −#define pmci_bus_resp_address_valid pme_bus.rp | |
| 739 | −#define pmci_bus_target_address_valid pme_bus.tv | |
| 740 | −#define pmci_bus_error_severity pme_bus.sev | |
| 741 | −#define pmci_bus_transaction_type pme_bus.type | |
| 742 | −#define pmci_bus_cache_cache_transfer pme_bus.cc | |
| 743 | −#define pmci_bus_transaction_size pme_bus.size | |
| 744 | −#define pmci_bus_internal_error pme_bus.ib | |
| 745 | −#define pmci_bus_external_error pme_bus.eb | |
| 746 | −#define pmci_bus_mc pme_bus.mc | |
| 747 | − | |
| 748 | −/* | |
| 749 | − * NOTE: this min_state_save area struct only includes the 1KB | |
| 750 | − * architectural state save area. The other 3 KB is scratch space | |
| 751 | − * for PAL. | |
| 752 | − */ | |
| 753 | − | |
| 754 | −struct pal_min_state_area { | |
| 755 | − u64 pmsa_nat_bits; /* nat bits for saved GRs */ | |
| 756 | − u64 pmsa_gr[15]; /* GR1 - GR15 */ | |
| 757 | − u64 pmsa_bank0_gr[16]; /* GR16 - GR31 */ | |
| 758 | − u64 pmsa_bank1_gr[16]; /* GR16 - GR31 */ | |
| 759 | − u64 pmsa_pr; /* predicate registers */ | |
| 760 | − u64 pmsa_br0; /* branch register 0 */ | |
| 761 | − u64 pmsa_rsc; /* ar.rsc */ | |
| 762 | − u64 pmsa_iip; /* cr.iip */ | |
| 763 | − u64 pmsa_ipsr; /* cr.ipsr */ | |
| 764 | − u64 pmsa_ifs; /* cr.ifs */ | |
| 765 | − u64 pmsa_xip; /* previous iip */ | |
| 766 | − u64 pmsa_xpsr; /* previous psr */ | |
| 767 | − u64 pmsa_xfs; /* previous ifs */ | |
| 768 | − u64 pmsa_br1; /* branch register 1 */ | |
| 769 | − u64 pmsa_reserved[70]; /* pal_min_state_area should total to 1KB */ | |
| 770 | −}; | |
| 771 | − | |
| 772 | − | |
| 773 | −struct ia64_pal_retval { | |
| 774 | − /* | |
| 775 | − * A zero status value indicates call completed without error. | |
| 776 | − * A negative status value indicates reason of call failure. | |
| 777 | − * A positive status value indicates success but an | |
| 778 | − * informational value should be printed (e.g., "reboot for | |
| 779 | − * change to take effect"). | |
| 780 | − */ | |
| 781 | − s64 status; | |
| 782 | − u64 v0; | |
| 783 | − u64 v1; | |
| 784 | − u64 v2; | |
| 785 | −}; | |
| 786 | − | |
| 787 | −/* | |
| 788 | − * Note: Currently unused PAL arguments are generally labeled | |
| 789 | − * "reserved" so the value specified in the PAL documentation | |
| 790 | − * (generally 0) MUST be passed. Reserved parameters are not optional | |
| 791 | − * parameters. | |
| 792 | − */ | |
| 793 | −extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64); | |
| 794 | −extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64); | |
| 795 | −extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64); | |
| 796 | −extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64); | |
| 797 | −extern void ia64_save_scratch_fpregs (struct ia64_fpreg *); | |
| 798 | −extern void ia64_load_scratch_fpregs (struct ia64_fpreg *); | |
| 799 | − | |
| 800 | −#define PAL_CALL(iprv,a0,a1,a2,a3) do { \ | |
| 801 | − struct ia64_fpreg fr[6]; \ | |
| 802 | − ia64_save_scratch_fpregs(fr); \ | |
| 803 | − iprv = ia64_pal_call_static(a0, a1, a2, a3); \ | |
| 804 | − ia64_load_scratch_fpregs(fr); \ | |
| 805 | −} while (0) | |
| 806 | − | |
| 807 | −#define PAL_CALL_STK(iprv,a0,a1,a2,a3) do { \ | |
| 808 | − struct ia64_fpreg fr[6]; \ | |
| 809 | − ia64_save_scratch_fpregs(fr); \ | |
| 810 | − iprv = ia64_pal_call_stacked(a0, a1, a2, a3); \ | |
| 811 | − ia64_load_scratch_fpregs(fr); \ | |
| 812 | −} while (0) | |
| 813 | − | |
| 814 | −#define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do { \ | |
| 815 | − struct ia64_fpreg fr[6]; \ | |
| 816 | − ia64_save_scratch_fpregs(fr); \ | |
| 817 | − iprv = ia64_pal_call_phys_static(a0, a1, a2, a3); \ | |
| 818 | − ia64_load_scratch_fpregs(fr); \ | |
| 819 | −} while (0) | |
| 820 | − | |
| 821 | −#define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do { \ | |
| 822 | − struct ia64_fpreg fr[6]; \ | |
| 823 | − ia64_save_scratch_fpregs(fr); \ | |
| 824 | − iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3); \ | |
| 825 | − ia64_load_scratch_fpregs(fr); \ | |
| 826 | −} while (0) | |
| 827 | − | |
| 828 | −typedef int (*ia64_pal_handler) (u64, ...); | |
| 829 | −extern ia64_pal_handler ia64_pal; | |
| 830 | −extern void ia64_pal_handler_init (void *); | |
| 831 | − | |
| 832 | −extern ia64_pal_handler ia64_pal; | |
| 833 | − | |
| 834 | −extern pal_cache_config_info_t l0d_cache_config_info; | |
| 835 | −extern pal_cache_config_info_t l0i_cache_config_info; | |
| 836 | −extern pal_cache_config_info_t l1_cache_config_info; | |
| 837 | −extern pal_cache_config_info_t l2_cache_config_info; | |
| 838 | − | |
| 839 | −extern pal_cache_protection_info_t l0d_cache_protection_info; | |
| 840 | −extern pal_cache_protection_info_t l0i_cache_protection_info; | |
| 841 | −extern pal_cache_protection_info_t l1_cache_protection_info; | |
| 842 | −extern pal_cache_protection_info_t l2_cache_protection_info; | |
| 843 | − | |
| 844 | −extern pal_cache_config_info_t pal_cache_config_info_get(pal_cache_level_t, | |
| 845 | − pal_cache_type_t); | |
| 846 | − | |
| 847 | −extern pal_cache_protection_info_t pal_cache_protection_info_get(pal_cache_level_t, | |
| 848 | − pal_cache_type_t); | |
| 849 | − | |
| 850 | − | |
| 851 | −extern void pal_error(int); | |
| 852 | − | |
| 853 | − | |
| 854 | −/* Useful wrappers for the current list of pal procedures */ | |
| 855 | − | |
| 856 | −typedef union pal_bus_features_u { | |
| 857 | − u64 pal_bus_features_val; | |
| 858 | − struct { | |
| 859 | − u64 pbf_reserved1 : 29; | |
| 860 | − u64 pbf_req_bus_parking : 1; | |
| 861 | − u64 pbf_bus_lock_mask : 1; | |
| 862 | − u64 pbf_enable_half_xfer_rate : 1; | |
| 863 | − u64 pbf_reserved2 : 20; | |
| 864 | − u64 pbf_enable_shared_line_replace : 1; | |
| 865 | − u64 pbf_enable_exclusive_line_replace : 1; | |
| 866 | − u64 pbf_disable_xaction_queueing : 1; | |
| 867 | − u64 pbf_disable_resp_err_check : 1; | |
| 868 | − u64 pbf_disable_berr_check : 1; | |
| 869 | − u64 pbf_disable_bus_req_internal_err_signal : 1; | |
| 870 | − u64 pbf_disable_bus_req_berr_signal : 1; | |
| 871 | − u64 pbf_disable_bus_init_event_check : 1; | |
| 872 | − u64 pbf_disable_bus_init_event_signal : 1; | |
| 873 | − u64 pbf_disable_bus_addr_err_check : 1; | |
| 874 | − u64 pbf_disable_bus_addr_err_signal : 1; | |
| 875 | − u64 pbf_disable_bus_data_err_check : 1; | |
| 876 | − } pal_bus_features_s; | |
| 877 | −} pal_bus_features_u_t; | |
| 878 | − | |
| 879 | −extern void pal_bus_features_print (u64); | |
| 880 | − | |
| 881 | −/* Provide information about configurable processor bus features */ | |
| 882 | −static inline s64 | |
| 883 | −ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail, | |
| 884 | − pal_bus_features_u_t *features_status, | |
| 885 | − pal_bus_features_u_t *features_control) | |
| 886 | −{ | |
| 887 | − struct ia64_pal_retval iprv; | |
| 888 | − PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0); | |
| 889 | − if (features_avail) | |
| 890 | − features_avail->pal_bus_features_val = iprv.v0; | |
| 891 | − if (features_status) | |
| 892 | − features_status->pal_bus_features_val = iprv.v1; | |
| 893 | − if (features_control) | |
| 894 | − features_control->pal_bus_features_val = iprv.v2; | |
| 895 | − return iprv.status; | |
| 896 | −} | |
| 897 | − | |
| 898 | −/* Enables/disables specific processor bus features */ | |
| 899 | −static inline s64 | |
| 900 | −ia64_pal_bus_set_features (pal_bus_features_u_t feature_select) | |
| 901 | −{ | |
| 902 | − struct ia64_pal_retval iprv; | |
| 903 | − PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0); | |
| 904 | − return iprv.status; | |
| 905 | −} | |
| 906 | − | |
| 907 | −/* Get detailed cache information */ | |
| 908 | −static inline s64 | |
| 909 | −ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf) | |
| 910 | −{ | |
| 911 | − struct ia64_pal_retval iprv; | |
| 912 | − | |
| 913 | − PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0); | |
| 914 | − | |
| 915 | − if (iprv.status == 0) { | |
| 916 | − conf->pcci_status = iprv.status; | |
| 917 | − conf->pcci_info_1.pcci1_data = iprv.v0; | |
| 918 | − conf->pcci_info_2.pcci2_data = iprv.v1; | |
| 919 | − conf->pcci_reserved = iprv.v2; | |
| 920 | − } | |
| 921 | − return iprv.status; | |
| 922 | − | |
| 923 | −} | |
| 924 | − | |
| 925 | −/* Get detailed cche protection information */ | |
| 926 | −static inline s64 | |
| 927 | −ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot) | |
| 928 | −{ | |
| 929 | − struct ia64_pal_retval iprv; | |
| 930 | − | |
| 931 | − PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0); | |
| 932 | − | |
| 933 | − if (iprv.status == 0) { | |
| 934 | − prot->pcpi_status = iprv.status; | |
| 935 | − prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff; | |
| 936 | − prot->pcp_info[1].pcpi_data = iprv.v0 >> 32; | |
| 937 | − prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff; | |
| 938 | − prot->pcp_info[3].pcpi_data = iprv.v1 >> 32; | |
| 939 | − prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff; | |
| 940 | − prot->pcp_info[5].pcpi_data = iprv.v2 >> 32; | |
| 941 | − } | |
| 942 | − return iprv.status; | |
| 943 | −} | |
| 944 | − | |
| 945 | −/* | |
| 946 | − * Flush the processor instruction or data caches. *PROGRESS must be | |
| 947 | − * initialized to zero before calling this for the first time.. | |
| 948 | − */ | |
| 949 | −static inline s64 | |
| 950 | −ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector) | |
| 951 | −{ | |
| 952 | − struct ia64_pal_retval iprv; | |
| 953 | − PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress); | |
| 954 | − if (vector) | |
| 955 | − *vector = iprv.v0; | |
| 956 | − *progress = iprv.v1; | |
| 957 | − return iprv.status; | |
| 958 | −} | |
| 959 | − | |
| 960 | − | |
| 961 | −/* Initialize the processor controlled caches */ | |
| 962 | −static inline s64 | |
| 963 | −ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest) | |
| 964 | −{ | |
| 965 | − struct ia64_pal_retval iprv; | |
| 966 | − PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest); | |
| 967 | − return iprv.status; | |
| 968 | −} | |
| 969 | − | |
| 970 | −/* Initialize the tags and data of a data or unified cache line of | |
| 971 | − * processor controlled cache to known values without the availability | |
| 972 | − * of backing memory. | |
| 973 | − */ | |
| 974 | −static inline s64 | |
| 975 | −ia64_pal_cache_line_init (u64 physical_addr, u64 data_value) | |
| 976 | −{ | |
| 977 | − struct ia64_pal_retval iprv; | |
| 978 | − PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0); | |
| 979 | − return iprv.status; | |
| 980 | −} | |
| 981 | − | |
| 982 | − | |
| 983 | −/* Read the data and tag of a processor controlled cache line for diags */ | |
| 984 | −static inline s64 | |
| 985 | −ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr) | |
| 986 | −{ | |
| 987 | − struct ia64_pal_retval iprv; | |
| 988 | − PAL_CALL_PHYS_STK(iprv, PAL_CACHE_READ, line_id.pclid_data, | |
| 989 | − physical_addr, 0); | |
| 990 | − return iprv.status; | |
| 991 | −} | |
| 992 | − | |
| 993 | −/* Return summary information about the hierarchy of caches controlled by the processor */ | |
| 994 | −static inline long ia64_pal_cache_summary(unsigned long *cache_levels, | |
| 995 | − unsigned long *unique_caches) | |
| 996 | −{ | |
| 997 | − struct ia64_pal_retval iprv; | |
| 998 | − PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0); | |
| 999 | − if (cache_levels) | |
| 1000 | − *cache_levels = iprv.v0; | |
| 1001 | − if (unique_caches) | |
| 1002 | − *unique_caches = iprv.v1; | |
| 1003 | − return iprv.status; | |
| 1004 | −} | |
| 1005 | − | |
| 1006 | −/* Write the data and tag of a processor-controlled cache line for diags */ | |
| 1007 | −static inline s64 | |
| 1008 | −ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data) | |
| 1009 | −{ | |
| 1010 | − struct ia64_pal_retval iprv; | |
| 1011 | − PAL_CALL_PHYS_STK(iprv, PAL_CACHE_WRITE, line_id.pclid_data, | |
| 1012 | − physical_addr, data); | |
| 1013 | − return iprv.status; | |
| 1014 | −} | |
| 1015 | − | |
| 1016 | − | |
| 1017 | −/* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */ | |
| 1018 | −static inline s64 | |
| 1019 | −ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics, | |
| 1020 | − u64 *buffer_size, u64 *buffer_align) | |
| 1021 | −{ | |
| 1022 | − struct ia64_pal_retval iprv; | |
| 1023 | − PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics); | |
| 1024 | − if (buffer_size) | |
| 1025 | − *buffer_size = iprv.v0; | |
| 1026 | − if (buffer_align) | |
| 1027 | − *buffer_align = iprv.v1; | |
| 1028 | − return iprv.status; | |
| 1029 | −} | |
| 1030 | − | |
| 1031 | −/* Copy relocatable PAL procedures from ROM to memory */ | |
| 1032 | −static inline s64 | |
| 1033 | −ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset) | |
| 1034 | −{ | |
| 1035 | − struct ia64_pal_retval iprv; | |
| 1036 | − PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor); | |
| 1037 | − if (pal_proc_offset) | |
| 1038 | − *pal_proc_offset = iprv.v0; | |
| 1039 | − return iprv.status; | |
| 1040 | −} | |
| 1041 | − | |
| 1042 | −/* Return the number of instruction and data debug register pairs */ | |
| 1043 | −static inline long ia64_pal_debug_info(unsigned long *inst_regs, | |
| 1044 | − unsigned long *data_regs) | |
| 1045 | −{ | |
| 1046 | − struct ia64_pal_retval iprv; | |
| 1047 | − PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0); | |
| 1048 | − if (inst_regs) | |
| 1049 | − *inst_regs = iprv.v0; | |
| 1050 | − if (data_regs) | |
| 1051 | − *data_regs = iprv.v1; | |
| 1052 | − | |
| 1053 | − return iprv.status; | |
| 1054 | −} | |
| 1055 | − | |
| 1056 | −#ifdef TBD | |
| 1057 | −/* Switch from IA64-system environment to IA-32 system environment */ | |
| 1058 | −static inline s64 | |
| 1059 | −ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3) | |
| 1060 | −{ | |
| 1061 | − struct ia64_pal_retval iprv; | |
| 1062 | − PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3); | |
| 1063 | − return iprv.status; | |
| 1064 | −} | |
| 1065 | −#endif | |
| 1066 | − | |
| 1067 | −/* Get unique geographical address of this processor on its bus */ | |
| 1068 | −static inline s64 | |
| 1069 | −ia64_pal_fixed_addr (u64 *global_unique_addr) | |
| 1070 | −{ | |
| 1071 | − struct ia64_pal_retval iprv; | |
| 1072 | − PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0); | |
| 1073 | − if (global_unique_addr) | |
| 1074 | − *global_unique_addr = iprv.v0; | |
| 1075 | − return iprv.status; | |
| 1076 | −} | |
| 1077 | − | |
| 1078 | −/* Get base frequency of the platform if generated by the processor */ | |
| 1079 | −static inline long ia64_pal_freq_base(unsigned long *platform_base_freq) | |
| 1080 | −{ | |
| 1081 | − struct ia64_pal_retval iprv; | |
| 1082 | − PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0); | |
| 1083 | − if (platform_base_freq) | |
| 1084 | − *platform_base_freq = iprv.v0; | |
| 1085 | − return iprv.status; | |
| 1086 | −} | |
| 1087 | − | |
| 1088 | −/* | |
| 1089 | − * Get the ratios for processor frequency, bus frequency and interval timer to | |
| 1090 | − * the base frequency of the platform | |
| 1091 | − */ | |
| 1092 | −static inline s64 | |
| 1093 | −ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio, | |
| 1094 | − struct pal_freq_ratio *itc_ratio) | |
| 1095 | −{ | |
| 1096 | − struct ia64_pal_retval iprv; | |
| 1097 | − PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0); | |
| 1098 | − if (proc_ratio) | |
| 1099 | − *(u64 *)proc_ratio = iprv.v0; | |
| 1100 | − if (bus_ratio) | |
| 1101 | − *(u64 *)bus_ratio = iprv.v1; | |
| 1102 | − if (itc_ratio) | |
| 1103 | − *(u64 *)itc_ratio = iprv.v2; | |
| 1104 | − return iprv.status; | |
| 1105 | −} | |
| 1106 | − | |
| 1107 | −/* | |
| 1108 | − * Get the current hardware resource sharing policy of the processor | |
| 1109 | − */ | |
| 1110 | −static inline s64 | |
| 1111 | −ia64_pal_get_hw_policy (u64 proc_num, u64 *cur_policy, u64 *num_impacted, | |
| 1112 | − u64 *la) | |
| 1113 | −{ | |
| 1114 | − struct ia64_pal_retval iprv; | |
| 1115 | − PAL_CALL(iprv, PAL_GET_HW_POLICY, proc_num, 0, 0); | |
| 1116 | − if (cur_policy) | |
| 1117 | − *cur_policy = iprv.v0; | |
| 1118 | − if (num_impacted) | |
| 1119 | − *num_impacted = iprv.v1; | |
| 1120 | − if (la) | |
| 1121 | − *la = iprv.v2; | |
| 1122 | − return iprv.status; | |
| 1123 | −} | |
| 1124 | − | |
| 1125 | −/* Make the processor enter HALT or one of the implementation dependent low | |
| 1126 | − * power states where prefetching and execution are suspended and cache and | |
| 1127 | − * TLB coherency is not maintained. | |
| 1128 | − */ | |
| 1129 | −static inline s64 | |
| 1130 | −ia64_pal_halt (u64 halt_state) | |
| 1131 | −{ | |
| 1132 | − struct ia64_pal_retval iprv; | |
| 1133 | − PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0); | |
| 1134 | − return iprv.status; | |
| 1135 | −} | |
| 1136 | − | |
| 1137 | −typedef union pal_power_mgmt_info_u { | |
| 1138 | − u64 ppmi_data; | |
| 1139 | − struct { | |
| 1140 | − u64 exit_latency : 16, | |
| 1141 | − entry_latency : 16, | |
| 1142 | − power_consumption : 28, | |
| 1143 | − im : 1, | |
| 1144 | − co : 1, | |
| 1145 | − reserved : 2; | |
| 1146 | − } pal_power_mgmt_info_s; | |
| 1147 | −} pal_power_mgmt_info_u_t; | |
| 1148 | − | |
| 1149 | −/* Return information about processor's optional power management capabilities. */ | |
| 1150 | −static inline s64 | |
| 1151 | −ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf) | |
| 1152 | −{ | |
| 1153 | − struct ia64_pal_retval iprv; | |
| 1154 | − PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0); | |
| 1155 | − return iprv.status; | |
| 1156 | −} | |
| 1157 | − | |
| 1158 | −/* Get the current P-state information */ | |
| 1159 | −static inline s64 | |
| 1160 | −ia64_pal_get_pstate (u64 *pstate_index, unsigned long type) | |
| 1161 | −{ | |
| 1162 | − struct ia64_pal_retval iprv; | |
| 1163 | − PAL_CALL_STK(iprv, PAL_GET_PSTATE, type, 0, 0); | |
| 1164 | − *pstate_index = iprv.v0; | |
| 1165 | − return iprv.status; | |
| 1166 | −} | |
| 1167 | − | |
| 1168 | −/* Set the P-state */ | |
| 1169 | −static inline s64 | |
| 1170 | −ia64_pal_set_pstate (u64 pstate_index) | |
| 1171 | −{ | |
| 1172 | − struct ia64_pal_retval iprv; | |
| 1173 | − PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0); | |
| 1174 | − return iprv.status; | |
| 1175 | −} | |
| 1176 | − | |
| 1177 | −/* Processor branding information*/ | |
| 1178 | −static inline s64 | |
| 1179 | −ia64_pal_get_brand_info (char *brand_info) | |
| 1180 | −{ | |
| 1181 | − struct ia64_pal_retval iprv; | |
| 1182 | − PAL_CALL_STK(iprv, PAL_BRAND_INFO, 0, (u64)brand_info, 0); | |
| 1183 | − return iprv.status; | |
| 1184 | −} | |
| 1185 | − | |
| 1186 | −/* Cause the processor to enter LIGHT HALT state, where prefetching and execution are | |
| 1187 | − * suspended, but cache and TLB coherency is maintained. | |
| 1188 | − */ | |
| 1189 | −static inline s64 | |
| 1190 | −ia64_pal_halt_light (void) | |
| 1191 | −{ | |
| 1192 | − struct ia64_pal_retval iprv; | |
| 1193 | − PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0); | |
| 1194 | − return iprv.status; | |
| 1195 | −} | |
| 1196 | − | |
| 1197 | −/* Clear all the processor error logging registers and reset the indicator that allows | |
| 1198 | − * the error logging registers to be written. This procedure also checks the pending | |
| 1199 | − * machine check bit and pending INIT bit and reports their states. | |
| 1200 | − */ | |
| 1201 | −static inline s64 | |
| 1202 | −ia64_pal_mc_clear_log (u64 *pending_vector) | |
| 1203 | −{ | |
| 1204 | − struct ia64_pal_retval iprv; | |
| 1205 | − PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0); | |
| 1206 | − if (pending_vector) | |
| 1207 | − *pending_vector = iprv.v0; | |
| 1208 | − return iprv.status; | |
| 1209 | −} | |
| 1210 | − | |
| 1211 | −/* Ensure that all outstanding transactions in a processor are completed or that any | |
| 1212 | − * MCA due to thes outstanding transaction is taken. | |
| 1213 | − */ | |
| 1214 | −static inline s64 | |
| 1215 | −ia64_pal_mc_drain (void) | |
| 1216 | −{ | |
| 1217 | − struct ia64_pal_retval iprv; | |
| 1218 | − PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0); | |
| 1219 | − return iprv.status; | |
| 1220 | −} | |
| 1221 | − | |
| 1222 | −/* Return the machine check dynamic processor state */ | |
| 1223 | −static inline s64 | |
| 1224 | −ia64_pal_mc_dynamic_state (u64 info_type, u64 dy_buffer, u64 *size) | |
| 1225 | −{ | |
| 1226 | − struct ia64_pal_retval iprv; | |
| 1227 | − PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, info_type, dy_buffer, 0); | |
| 1228 | − if (size) | |
| 1229 | − *size = iprv.v0; | |
| 1230 | − return iprv.status; | |
| 1231 | −} | |
| 1232 | − | |
| 1233 | −/* Return processor machine check information */ | |
| 1234 | −static inline s64 | |
| 1235 | −ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info) | |
| 1236 | −{ | |
| 1237 | − struct ia64_pal_retval iprv; | |
| 1238 | − PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0); | |
| 1239 | − if (size) | |
| 1240 | − *size = iprv.v0; | |
| 1241 | − if (error_info) | |
| 1242 | − *error_info = iprv.v1; | |
| 1243 | − return iprv.status; | |
| 1244 | −} | |
| 1245 | − | |
| 1246 | −/* Injects the requested processor error or returns info on | |
| 1247 | − * supported injection capabilities for current processor implementation | |
| 1248 | − */ | |
| 1249 | −static inline s64 | |
| 1250 | −ia64_pal_mc_error_inject_phys (u64 err_type_info, u64 err_struct_info, | |
| 1251 | − u64 err_data_buffer, u64 *capabilities, u64 *resources) | |
| 1252 | −{ | |
| 1253 | − struct ia64_pal_retval iprv; | |
| 1254 | − PAL_CALL_PHYS_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info, | |
| 1255 | − err_struct_info, err_data_buffer); | |
| 1256 | − if (capabilities) | |
| 1257 | − *capabilities= iprv.v0; | |
| 1258 | − if (resources) | |
| 1259 | − *resources= iprv.v1; | |
| 1260 | − return iprv.status; | |
| 1261 | −} | |
| 1262 | − | |
| 1263 | −static inline s64 | |
| 1264 | −ia64_pal_mc_error_inject_virt (u64 err_type_info, u64 err_struct_info, | |
| 1265 | − u64 err_data_buffer, u64 *capabilities, u64 *resources) | |
| 1266 | −{ | |
| 1267 | − struct ia64_pal_retval iprv; | |
| 1268 | − PAL_CALL_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info, | |
| 1269 | − err_struct_info, err_data_buffer); | |
| 1270 | − if (capabilities) | |
| 1271 | − *capabilities= iprv.v0; | |
| 1272 | − if (resources) | |
| 1273 | − *resources= iprv.v1; | |
| 1274 | − return iprv.status; | |
| 1275 | −} | |
| 1276 | − | |
| 1277 | −/* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot | |
| 1278 | − * attempt to correct any expected machine checks. | |
| 1279 | − */ | |
| 1280 | −static inline s64 | |
| 1281 | −ia64_pal_mc_expected (u64 expected, u64 *previous) | |
| 1282 | −{ | |
| 1283 | − struct ia64_pal_retval iprv; | |
| 1284 | − PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0); | |
| 1285 | − if (previous) | |
| 1286 | − *previous = iprv.v0; | |
| 1287 | − return iprv.status; | |
| 1288 | −} | |
| 1289 | − | |
| 1290 | −typedef union pal_hw_tracking_u { | |
| 1291 | − u64 pht_data; | |
| 1292 | − struct { | |
| 1293 | − u64 itc :4, /* Instruction cache tracking */ | |
| 1294 | − dct :4, /* Date cache tracking */ | |
| 1295 | − itt :4, /* Instruction TLB tracking */ | |
| 1296 | − ddt :4, /* Data TLB tracking */ | |
| 1297 | − reserved:48; | |
| 1298 | − } pal_hw_tracking_s; | |
| 1299 | −} pal_hw_tracking_u_t; | |
| 1300 | − | |
| 1301 | −/* | |
| 1302 | − * Hardware tracking status. | |
| 1303 | − */ | |
| 1304 | −static inline s64 | |
| 1305 | −ia64_pal_mc_hw_tracking (u64 *status) | |
| 1306 | −{ | |
| 1307 | − struct ia64_pal_retval iprv; | |
| 1308 | − PAL_CALL(iprv, PAL_MC_HW_TRACKING, 0, 0, 0); | |
| 1309 | − if (status) | |
| 1310 | − *status = iprv.v0; | |
| 1311 | − return iprv.status; | |
| 1312 | −} | |
| 1313 | − | |
| 1314 | −/* Register a platform dependent location with PAL to which it can save | |
| 1315 | − * minimal processor state in the event of a machine check or initialization | |
| 1316 | − * event. | |
| 1317 | − */ | |
| 1318 | −static inline s64 | |
| 1319 | −ia64_pal_mc_register_mem (u64 physical_addr, u64 size, u64 *req_size) | |
| 1320 | −{ | |
| 1321 | − struct ia64_pal_retval iprv; | |
| 1322 | − PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, size, 0); | |
| 1323 | − if (req_size) | |
| 1324 | − *req_size = iprv.v0; | |
| 1325 | − return iprv.status; | |
| 1326 | −} | |
| 1327 | − | |
| 1328 | −/* Restore minimal architectural processor state, set CMC interrupt if necessary | |
| 1329 | − * and resume execution | |
| 1330 | − */ | |
| 1331 | −static inline s64 | |
| 1332 | −ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr) | |
| 1333 | −{ | |
| 1334 | − struct ia64_pal_retval iprv; | |
| 1335 | − PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0); | |
| 1336 | − return iprv.status; | |
| 1337 | −} | |
| 1338 | − | |
| 1339 | −/* Return the memory attributes implemented by the processor */ | |
| 1340 | −static inline s64 | |
| 1341 | −ia64_pal_mem_attrib (u64 *mem_attrib) | |
| 1342 | −{ | |
| 1343 | − struct ia64_pal_retval iprv; | |
| 1344 | − PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0); | |
| 1345 | − if (mem_attrib) | |
| 1346 | − *mem_attrib = iprv.v0 & 0xff; | |
| 1347 | − return iprv.status; | |
| 1348 | −} | |
| 1349 | − | |
| 1350 | −/* Return the amount of memory needed for second phase of processor | |
| 1351 | − * self-test and the required alignment of memory. | |
| 1352 | − */ | |
| 1353 | −static inline s64 | |
| 1354 | −ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment) | |
| 1355 | −{ | |
| 1356 | − struct ia64_pal_retval iprv; | |
| 1357 | − PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0); | |
| 1358 | − if (bytes_needed) | |
| 1359 | − *bytes_needed = iprv.v0; | |
| 1360 | − if (alignment) | |
| 1361 | − *alignment = iprv.v1; | |
| 1362 | − return iprv.status; | |
| 1363 | −} | |
| 1364 | − | |
| 1365 | −typedef union pal_perf_mon_info_u { | |
| 1366 | − u64 ppmi_data; | |
| 1367 | − struct { | |
| 1368 | − u64 generic : 8, | |
| 1369 | − width : 8, | |
| 1370 | − cycles : 8, | |
| 1371 | − retired : 8, | |
| 1372 | − reserved : 32; | |
| 1373 | − } pal_perf_mon_info_s; | |
| 1374 | −} pal_perf_mon_info_u_t; | |
| 1375 | − | |
| 1376 | −/* Return the performance monitor information about what can be counted | |
| 1377 | − * and how to configure the monitors to count the desired events. | |
| 1378 | − */ | |
| 1379 | −static inline s64 | |
| 1380 | −ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info) | |
| 1381 | −{ | |
| 1382 | − struct ia64_pal_retval iprv; | |
| 1383 | − PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0); | |
| 1384 | − if (pm_info) | |
| 1385 | − pm_info->ppmi_data = iprv.v0; | |
| 1386 | − return iprv.status; | |
| 1387 | −} | |
| 1388 | − | |
| 1389 | −/* Specifies the physical address of the processor interrupt block | |
| 1390 | − * and I/O port space. | |
| 1391 | − */ | |
| 1392 | −static inline s64 | |
| 1393 | −ia64_pal_platform_addr (u64 type, u64 physical_addr) | |
| 1394 | −{ | |
| 1395 | − struct ia64_pal_retval iprv; | |
| 1396 | − PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0); | |
| 1397 | − return iprv.status; | |
| 1398 | −} | |
| 1399 | − | |
| 1400 | −/* Set the SAL PMI entrypoint in memory */ | |
| 1401 | −static inline s64 | |
| 1402 | −ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr) | |
| 1403 | −{ | |
| 1404 | − struct ia64_pal_retval iprv; | |
| 1405 | − PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0); | |
| 1406 | − return iprv.status; | |
| 1407 | −} | |
| 1408 | − | |
| 1409 | −struct pal_features_s; | |
| 1410 | −/* Provide information about configurable processor features */ | |
| 1411 | −static inline s64 | |
| 1412 | −ia64_pal_proc_get_features (u64 *features_avail, | |
| 1413 | − u64 *features_status, | |
| 1414 | − u64 *features_control, | |
| 1415 | − u64 features_set) | |
| 1416 | −{ | |
| 1417 | − struct ia64_pal_retval iprv; | |
| 1418 | − PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, features_set, 0); | |
| 1419 | − if (iprv.status == 0) { | |
| 1420 | − *features_avail = iprv.v0; | |
| 1421 | − *features_status = iprv.v1; | |
| 1422 | − *features_control = iprv.v2; | |
| 1423 | − } | |
| 1424 | − return iprv.status; | |
| 1425 | −} | |
| 1426 | − | |
| 1427 | −/* Enable/disable processor dependent features */ | |
| 1428 | −static inline s64 | |
| 1429 | −ia64_pal_proc_set_features (u64 feature_select) | |
| 1430 | −{ | |
| 1431 | − struct ia64_pal_retval iprv; | |
| 1432 | − PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0); | |
| 1433 | − return iprv.status; | |
| 1434 | −} | |
| 1435 | − | |
| 1436 | −/* | |
| 1437 | − * Put everything in a struct so we avoid the global offset table whenever | |
| 1438 | − * possible. | |
| 1439 | − */ | |
| 1440 | −typedef struct ia64_ptce_info_s { | |
| 1441 | − unsigned long base; | |
| 1442 | − u32 count[2]; | |
| 1443 | − u32 stride[2]; | |
| 1444 | −} ia64_ptce_info_t; | |
| 1445 | − | |
| 1446 | −/* Return the information required for the architected loop used to purge | |
| 1447 | − * (initialize) the entire TC | |
| 1448 | − */ | |
| 1449 | −static inline s64 | |
| 1450 | −ia64_get_ptce (ia64_ptce_info_t *ptce) | |
| 1451 | −{ | |
| 1452 | − struct ia64_pal_retval iprv; | |
| 1453 | − | |
| 1454 | − if (!ptce) | |
| 1455 | − return -1; | |
| 1456 | − | |
| 1457 | − PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0); | |
| 1458 | − if (iprv.status == 0) { | |
| 1459 | − ptce->base = iprv.v0; | |
| 1460 | − ptce->count[0] = iprv.v1 >> 32; | |
| 1461 | − ptce->count[1] = iprv.v1 & 0xffffffff; | |
| 1462 | − ptce->stride[0] = iprv.v2 >> 32; | |
| 1463 | − ptce->stride[1] = iprv.v2 & 0xffffffff; | |
| 1464 | − } | |
| 1465 | − return iprv.status; | |
| 1466 | −} | |
| 1467 | − | |
| 1468 | −/* Return info about implemented application and control registers. */ | |
| 1469 | −static inline s64 | |
| 1470 | −ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2) | |
| 1471 | −{ | |
| 1472 | − struct ia64_pal_retval iprv; | |
| 1473 | − PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0); | |
| 1474 | − if (reg_info_1) | |
| 1475 | − *reg_info_1 = iprv.v0; | |
| 1476 | − if (reg_info_2) | |
| 1477 | − *reg_info_2 = iprv.v1; | |
| 1478 | − return iprv.status; | |
| 1479 | −} | |
| 1480 | − | |
| 1481 | −typedef union pal_hints_u { | |
| 1482 | − unsigned long ph_data; | |
| 1483 | − struct { | |
| 1484 | − unsigned long si : 1, | |
| 1485 | − li : 1, | |
| 1486 | − reserved : 62; | |
| 1487 | − } pal_hints_s; | |
| 1488 | −} pal_hints_u_t; | |
| 1489 | − | |
| 1490 | −/* Return information about the register stack and RSE for this processor | |
| 1491 | − * implementation. | |
| 1492 | − */ | |
| 1493 | −static inline long ia64_pal_rse_info(unsigned long *num_phys_stacked, | |
| 1494 | − pal_hints_u_t *hints) | |
| 1495 | −{ | |
| 1496 | − struct ia64_pal_retval iprv; | |
| 1497 | − PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0); | |
| 1498 | − if (num_phys_stacked) | |
| 1499 | − *num_phys_stacked = iprv.v0; | |
| 1500 | − if (hints) | |
| 1501 | − hints->ph_data = iprv.v1; | |
| 1502 | − return iprv.status; | |
| 1503 | −} | |
| 1504 | − | |
| 1505 | −/* | |
| 1506 | − * Set the current hardware resource sharing policy of the processor | |
| 1507 | − */ | |
| 1508 | −static inline s64 | |
| 1509 | −ia64_pal_set_hw_policy (u64 policy) | |
| 1510 | −{ | |
| 1511 | − struct ia64_pal_retval iprv; | |
| 1512 | − PAL_CALL(iprv, PAL_SET_HW_POLICY, policy, 0, 0); | |
| 1513 | − return iprv.status; | |
| 1514 | −} | |
| 1515 | − | |
| 1516 | −/* Cause the processor to enter SHUTDOWN state, where prefetching and execution are | |
| 1517 | − * suspended, but cause cache and TLB coherency to be maintained. | |
| 1518 | − * This is usually called in IA-32 mode. | |
| 1519 | − */ | |
| 1520 | −static inline s64 | |
| 1521 | −ia64_pal_shutdown (void) | |
| 1522 | −{ | |
| 1523 | − struct ia64_pal_retval iprv; | |
| 1524 | − PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0); | |
| 1525 | − return iprv.status; | |
| 1526 | −} | |
| 1527 | − | |
| 1528 | −/* Perform the second phase of processor self-test. */ | |
| 1529 | −static inline s64 | |
| 1530 | −ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state) | |
| 1531 | −{ | |
| 1532 | − struct ia64_pal_retval iprv; | |
| 1533 | − PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes); | |
| 1534 | − if (self_test_state) | |
| 1535 | − *self_test_state = iprv.v0; | |
| 1536 | − return iprv.status; | |
| 1537 | −} | |
| 1538 | − | |
| 1539 | −typedef union pal_version_u { | |
| 1540 | − u64 pal_version_val; | |
| 1541 | − struct { | |
| 1542 | − u64 pv_pal_b_rev : 8; | |
| 1543 | − u64 pv_pal_b_model : 8; | |
| 1544 | − u64 pv_reserved1 : 8; | |
| 1545 | − u64 pv_pal_vendor : 8; | |
| 1546 | − u64 pv_pal_a_rev : 8; | |
| 1547 | − u64 pv_pal_a_model : 8; | |
| 1548 | − u64 pv_reserved2 : 16; | |
| 1549 | − } pal_version_s; | |
| 1550 | −} pal_version_u_t; | |
| 1551 | − | |
| 1552 | − | |
| 1553 | −/* | |
| 1554 | − * Return PAL version information. While the documentation states that | |
| 1555 | − * PAL_VERSION can be called in either physical or virtual mode, some | |
| 1556 | − * implementations only allow physical calls. We don't call it very often, | |
| 1557 | − * so the overhead isn't worth eliminating. | |
| 1558 | − */ | |
| 1559 | −static inline s64 | |
| 1560 | −ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version) | |
| 1561 | −{ | |
| 1562 | − struct ia64_pal_retval iprv; | |
| 1563 | − PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0); | |
| 1564 | − if (pal_min_version) | |
| 1565 | − pal_min_version->pal_version_val = iprv.v0; | |
| 1566 | − | |
| 1567 | − if (pal_cur_version) | |
| 1568 | − pal_cur_version->pal_version_val = iprv.v1; | |
| 1569 | − | |
| 1570 | − return iprv.status; | |
| 1571 | −} | |
| 1572 | − | |
| 1573 | −typedef union pal_tc_info_u { | |
| 1574 | − u64 pti_val; | |
| 1575 | − struct { | |
| 1576 | − u64 num_sets : 8, | |
| 1577 | − associativity : 8, | |
| 1578 | − num_entries : 16, | |
| 1579 | − pf : 1, | |
| 1580 | − unified : 1, | |
| 1581 | − reduce_tr : 1, | |
| 1582 | − reserved : 29; | |
| 1583 | − } pal_tc_info_s; | |
| 1584 | −} pal_tc_info_u_t; | |
| 1585 | − | |
| 1586 | −#define tc_reduce_tr pal_tc_info_s.reduce_tr | |
| 1587 | −#define tc_unified pal_tc_info_s.unified | |
| 1588 | −#define tc_pf pal_tc_info_s.pf | |
| 1589 | −#define tc_num_entries pal_tc_info_s.num_entries | |
| 1590 | −#define tc_associativity pal_tc_info_s.associativity | |
| 1591 | −#define tc_num_sets pal_tc_info_s.num_sets | |
| 1592 | − | |
| 1593 | − | |
| 1594 | −/* Return information about the virtual memory characteristics of the processor | |
| 1595 | − * implementation. | |
| 1596 | − */ | |
| 1597 | −static inline s64 | |
| 1598 | −ia64_pal_vm_info (u64 tc_level, u64 tc_type, pal_tc_info_u_t *tc_info, u64 *tc_pages) | |
| 1599 | −{ | |
| 1600 | − struct ia64_pal_retval iprv; | |
| 1601 | − PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0); | |
| 1602 | − if (tc_info) | |
| 1603 | − tc_info->pti_val = iprv.v0; | |
| 1604 | − if (tc_pages) | |
| 1605 | − *tc_pages = iprv.v1; | |
| 1606 | − return iprv.status; | |
| 1607 | −} | |
| 1608 | − | |
| 1609 | −/* Get page size information about the virtual memory characteristics of the processor | |
| 1610 | − * implementation. | |
| 1611 | − */ | |
| 1612 | −static inline s64 ia64_pal_vm_page_size(u64 *tr_pages, u64 *vw_pages) | |
| 1613 | −{ | |
| 1614 | − struct ia64_pal_retval iprv; | |
| 1615 | − PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0); | |
| 1616 | − if (tr_pages) | |
| 1617 | − *tr_pages = iprv.v0; | |
| 1618 | − if (vw_pages) | |
| 1619 | − *vw_pages = iprv.v1; | |
| 1620 | − return iprv.status; | |
| 1621 | −} | |
| 1622 | − | |
| 1623 | −typedef union pal_vm_info_1_u { | |
| 1624 | − u64 pvi1_val; | |
| 1625 | − struct { | |
| 1626 | − u64 vw : 1, | |
| 1627 | − phys_add_size : 7, | |
| 1628 | − key_size : 8, | |
| 1629 | − max_pkr : 8, | |
| 1630 | − hash_tag_id : 8, | |
| 1631 | − max_dtr_entry : 8, | |
| 1632 | − max_itr_entry : 8, | |
| 1633 | − max_unique_tcs : 8, | |
| 1634 | − num_tc_levels : 8; | |
| 1635 | − } pal_vm_info_1_s; | |
| 1636 | −} pal_vm_info_1_u_t; | |
| 1637 | − | |
| 1638 | −#define PAL_MAX_PURGES 0xFFFF /* all ones is means unlimited */ | |
| 1639 | − | |
| 1640 | −typedef union pal_vm_info_2_u { | |
| 1641 | − u64 pvi2_val; | |
| 1642 | − struct { | |
| 1643 | − u64 impl_va_msb : 8, | |
| 1644 | − rid_size : 8, | |
| 1645 | − max_purges : 16, | |
| 1646 | − reserved : 32; | |
| 1647 | − } pal_vm_info_2_s; | |
| 1648 | −} pal_vm_info_2_u_t; | |
| 1649 | − | |
| 1650 | −/* Get summary information about the virtual memory characteristics of the processor | |
| 1651 | − * implementation. | |
| 1652 | − */ | |
| 1653 | −static inline s64 | |
| 1654 | −ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2) | |
| 1655 | −{ | |
| 1656 | − struct ia64_pal_retval iprv; | |
| 1657 | − PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0); | |
| 1658 | − if (vm_info_1) | |
| 1659 | − vm_info_1->pvi1_val = iprv.v0; | |
| 1660 | − if (vm_info_2) | |
| 1661 | − vm_info_2->pvi2_val = iprv.v1; | |
| 1662 | − return iprv.status; | |
| 1663 | −} | |
| 1664 | − | |
| 1665 | −typedef union pal_vp_info_u { | |
| 1666 | − u64 pvi_val; | |
| 1667 | − struct { | |
| 1668 | − u64 index: 48, /* virtual feature set info */ | |
| 1669 | − vmm_id: 16; /* feature set id */ | |
| 1670 | − } pal_vp_info_s; | |
| 1671 | −} pal_vp_info_u_t; | |
| 1672 | − | |
| 1673 | −/* | |
| 1674 | − * Returns information about virtual processor features | |
| 1675 | − */ | |
| 1676 | −static inline s64 | |
| 1677 | −ia64_pal_vp_info (u64 feature_set, u64 vp_buffer, u64 *vp_info, u64 *vmm_id) | |
| 1678 | −{ | |
| 1679 | − struct ia64_pal_retval iprv; | |
| 1680 | − PAL_CALL(iprv, PAL_VP_INFO, feature_set, vp_buffer, 0); | |
| 1681 | − if (vp_info) | |
| 1682 | − *vp_info = iprv.v0; | |
| 1683 | − if (vmm_id) | |
| 1684 | − *vmm_id = iprv.v1; | |
| 1685 | − return iprv.status; | |
| 1686 | −} | |
| 1687 | − | |
| 1688 | −typedef union pal_itr_valid_u { | |
| 1689 | − u64 piv_val; | |
| 1690 | − struct { | |
| 1691 | − u64 access_rights_valid : 1, | |
| 1692 | − priv_level_valid : 1, | |
| 1693 | − dirty_bit_valid : 1, | |
| 1694 | − mem_attr_valid : 1, | |
| 1695 | − reserved : 60; | |
| 1696 | − } pal_tr_valid_s; | |
| 1697 | −} pal_tr_valid_u_t; | |
| 1698 | − | |
| 1699 | −/* Read a translation register */ | |
| 1700 | −static inline s64 | |
| 1701 | −ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid) | |
| 1702 | −{ | |
| 1703 | − struct ia64_pal_retval iprv; | |
| 1704 | − PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer)); | |
| 1705 | − if (tr_valid) | |
| 1706 | − tr_valid->piv_val = iprv.v0; | |
| 1707 | − return iprv.status; | |
| 1708 | −} | |
| 1709 | − | |
| 1710 | −/* | |
| 1711 | − * PAL_PREFETCH_VISIBILITY transaction types | |
| 1712 | − */ | |
| 1713 | −#define PAL_VISIBILITY_VIRTUAL 0 | |
| 1714 | −#define PAL_VISIBILITY_PHYSICAL 1 | |
| 1715 | − | |
| 1716 | −/* | |
| 1717 | − * PAL_PREFETCH_VISIBILITY return codes | |
| 1718 | − */ | |
| 1719 | −#define PAL_VISIBILITY_OK 1 | |
| 1720 | −#define PAL_VISIBILITY_OK_REMOTE_NEEDED 0 | |
| 1721 | −#define PAL_VISIBILITY_INVAL_ARG -2 | |
| 1722 | −#define PAL_VISIBILITY_ERROR -3 | |
| 1723 | − | |
| 1724 | −static inline s64 | |
| 1725 | −ia64_pal_prefetch_visibility (s64 trans_type) | |
| 1726 | −{ | |
| 1727 | − struct ia64_pal_retval iprv; | |
| 1728 | − PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0); | |
| 1729 | − return iprv.status; | |
| 1730 | −} | |
| 1731 | − | |
| 1732 | −/* data structure for getting information on logical to physical mappings */ | |
| 1733 | −typedef union pal_log_overview_u { | |
| 1734 | − struct { | |
| 1735 | − u64 num_log :16, /* Total number of logical | |
| 1736 | − * processors on this die | |
| 1737 | − */ | |
| 1738 | − tpc :8, /* Threads per core */ | |
| 1739 | − reserved3 :8, /* Reserved */ | |
| 1740 | − cpp :8, /* Cores per processor */ | |
| 1741 | − reserved2 :8, /* Reserved */ | |
| 1742 | − ppid :8, /* Physical processor ID */ | |
| 1743 | − reserved1 :8; /* Reserved */ | |
| 1744 | − } overview_bits; | |
| 1745 | − u64 overview_data; | |
| 1746 | −} pal_log_overview_t; | |
| 1747 | − | |
| 1748 | −typedef union pal_proc_n_log_info1_u{ | |
| 1749 | − struct { | |
| 1750 | − u64 tid :16, /* Thread id */ | |
| 1751 | − reserved2 :16, /* Reserved */ | |
| 1752 | − cid :16, /* Core id */ | |
| 1753 | − reserved1 :16; /* Reserved */ | |
| 1754 | − } ppli1_bits; | |
| 1755 | − u64 ppli1_data; | |
| 1756 | −} pal_proc_n_log_info1_t; | |
| 1757 | − | |
| 1758 | −typedef union pal_proc_n_log_info2_u { | |
| 1759 | − struct { | |
| 1760 | − u64 la :16, /* Logical address */ | |
| 1761 | − reserved :48; /* Reserved */ | |
| 1762 | − } ppli2_bits; | |
| 1763 | − u64 ppli2_data; | |
| 1764 | −} pal_proc_n_log_info2_t; | |
| 1765 | − | |
| 1766 | −typedef struct pal_logical_to_physical_s | |
| 1767 | −{ | |
| 1768 | − pal_log_overview_t overview; | |
| 1769 | − pal_proc_n_log_info1_t ppli1; | |
| 1770 | − pal_proc_n_log_info2_t ppli2; | |
| 1771 | −} pal_logical_to_physical_t; | |
| 1772 | − | |
| 1773 | −#define overview_num_log overview.overview_bits.num_log | |
| 1774 | −#define overview_tpc overview.overview_bits.tpc | |
| 1775 | −#define overview_cpp overview.overview_bits.cpp | |
| 1776 | −#define overview_ppid overview.overview_bits.ppid | |
| 1777 | −#define log1_tid ppli1.ppli1_bits.tid | |
| 1778 | −#define log1_cid ppli1.ppli1_bits.cid | |
| 1779 | −#define log2_la ppli2.ppli2_bits.la | |
| 1780 | − | |
| 1781 | −/* Get information on logical to physical processor mappings. */ | |
| 1782 | −static inline s64 | |
| 1783 | −ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping) | |
| 1784 | −{ | |
| 1785 | − struct ia64_pal_retval iprv; | |
| 1786 | − | |
| 1787 | − PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0); | |
| 1788 | − | |
| 1789 | − if (iprv.status == PAL_STATUS_SUCCESS) | |
| 1790 | − { | |
| 1791 | − mapping->overview.overview_data = iprv.v0; | |
| 1792 | − mapping->ppli1.ppli1_data = iprv.v1; | |
| 1793 | − mapping->ppli2.ppli2_data = iprv.v2; | |
| 1794 | − } | |
| 1795 | − | |
| 1796 | − return iprv.status; | |
| 1797 | −} | |
| 1798 | − | |
| 1799 | −typedef struct pal_cache_shared_info_s | |
| 1800 | −{ | |
| 1801 | − u64 num_shared; | |
| 1802 | − pal_proc_n_log_info1_t ppli1; | |
| 1803 | − pal_proc_n_log_info2_t ppli2; | |
| 1804 | −} pal_cache_shared_info_t; | |
| 1805 | − | |
| 1806 | −/* Get information on logical to physical processor mappings. */ | |
| 1807 | −static inline s64 | |
| 1808 | −ia64_pal_cache_shared_info(u64 level, | |
| 1809 | − u64 type, | |
| 1810 | − u64 proc_number, | |
| 1811 | − pal_cache_shared_info_t *info) | |
| 1812 | −{ | |
| 1813 | − struct ia64_pal_retval iprv; | |
| 1814 | − | |
| 1815 | − PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number); | |
| 1816 | − | |
| 1817 | − if (iprv.status == PAL_STATUS_SUCCESS) { | |
| 1818 | − info->num_shared = iprv.v0; | |
| 1819 | − info->ppli1.ppli1_data = iprv.v1; | |
| 1820 | − info->ppli2.ppli2_data = iprv.v2; | |
| 1821 | − } | |
| 1822 | − | |
| 1823 | − return iprv.status; | |
| 1824 | −} | |
| 1825 | −#endif /* __ASSEMBLY__ */ | |
| 1826 | − | |
| 1827 | −#endif /* _ASM_IA64_PAL_H */ | |
| @@ -1,18 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −/* | |
| 3 | − * Fundamental kernel parameters. | |
| 4 | − * | |
| 5 | − * Based on <asm-i386/param.h>. | |
| 6 | − * | |
| 7 | − * Modified 1998, 1999, 2002-2003 | |
| 8 | − * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co | |
| 9 | − */ | |
| 10 | −#ifndef _ASM_IA64_PARAM_H | |
| 11 | −#define _ASM_IA64_PARAM_H | |
| 12 | − | |
| 13 | −#include <uapi/asm/param.h> | |
| 14 | − | |
| 15 | −# define HZ CONFIG_HZ | |
| 16 | −# define USER_HZ HZ | |
| 17 | −# define CLOCKS_PER_SEC HZ /* frequency at which times() counts */ | |
| 18 | −#endif /* _ASM_IA64_PARAM_H */ | |
| @@ -1,20 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −/* | |
| 3 | − * parport.h: platform-specific PC-style parport initialisation | |
| 4 | − * | |
| 5 | − * Copyright (C) 1999, 2000 Tim Waugh <tim@cyberelk.demon.co.uk> | |
| 6 | − * | |
| 7 | − * This file should only be included by drivers/parport/parport_pc.c. | |
| 8 | − */ | |
| 9 | − | |
| 10 | −#ifndef _ASM_IA64_PARPORT_H | |
| 11 | −#define _ASM_IA64_PARPORT_H 1 | |
| 12 | − | |
| 13 | −static int parport_pc_find_isa_ports(int autoirq, int autodma); | |
| 14 | − | |
| 15 | −static int parport_pc_find_nonpci_ports(int autoirq, int autodma) | |
| 16 | −{ | |
| 17 | − return parport_pc_find_isa_ports(autoirq, autodma); | |
| 18 | −} | |
| 19 | − | |
| 20 | −#endif /* _ASM_IA64_PARPORT_H */ | |
| @@ -1,28 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_PATCH_H | |
| 3 | −#define _ASM_IA64_PATCH_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Copyright (C) 2003 Hewlett-Packard Co | |
| 7 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 8 | − * | |
| 9 | − * There are a number of reasons for patching instructions. Rather than duplicating code | |
| 10 | − * all over the place, we put the common stuff here. Reasons for patching: in-kernel | |
| 11 | − * module-loader, virtual-to-physical patch-list, McKinley Errata 9 workaround, and gate | |
| 12 | − * shared library. Undoubtedly, some of these reasons will disappear and others will | |
| 13 | − * be added over time. | |
| 14 | − */ | |
| 15 | −#include <linux/elf.h> | |
| 16 | −#include <linux/types.h> | |
| 17 | − | |
| 18 | −extern void ia64_patch (u64 insn_addr, u64 mask, u64 val); /* patch any insn slot */ | |
| 19 | −extern void ia64_patch_imm64 (u64 insn_addr, u64 val); /* patch "movl" w/abs. value*/ | |
| 20 | −extern void ia64_patch_imm60 (u64 insn_addr, u64 val); /* patch "brl" w/ip-rel value */ | |
| 21 | − | |
| 22 | −extern void ia64_patch_mckinley_e9 (unsigned long start, unsigned long end); | |
| 23 | −extern void ia64_patch_vtop (unsigned long start, unsigned long end); | |
| 24 | −extern void ia64_patch_phys_stack_reg(unsigned long val); | |
| 25 | −extern void ia64_patch_rse (unsigned long start, unsigned long end); | |
| 26 | −extern void ia64_patch_gate (void); | |
| 27 | − | |
| 28 | −#endif /* _ASM_IA64_PATCH_H */ | |
| @@ -1,66 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_PCI_H | |
| 3 | −#define _ASM_IA64_PCI_H | |
| 4 | − | |
| 5 | −#include <linux/mm.h> | |
| 6 | −#include <linux/slab.h> | |
| 7 | −#include <linux/spinlock.h> | |
| 8 | −#include <linux/string.h> | |
| 9 | −#include <linux/types.h> | |
| 10 | −#include <linux/scatterlist.h> | |
| 11 | − | |
| 12 | −#include <asm/io.h> | |
| 13 | −#include <asm/hw_irq.h> | |
| 14 | − | |
| 15 | −struct pci_vector_struct { | |
| 16 | − __u16 segment; /* PCI Segment number */ | |
| 17 | − __u16 bus; /* PCI Bus number */ | |
| 18 | − __u32 pci_id; /* ACPI split 16 bits device, 16 bits function (see section 6.1.1) */ | |
| 19 | − __u8 pin; /* PCI PIN (0 = A, 1 = B, 2 = C, 3 = D) */ | |
| 20 | − __u32 irq; /* IRQ assigned */ | |
| 21 | −}; | |
| 22 | − | |
| 23 | −/* | |
| 24 | − * Can be used to override the logic in pci_scan_bus for skipping already-configured bus | |
| 25 | − * numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the | |
| 26 | − * loader. | |
| 27 | − */ | |
| 28 | −#define pcibios_assign_all_busses() 0 | |
| 29 | − | |
| 30 | −#define PCIBIOS_MIN_IO 0x1000 | |
| 31 | −#define PCIBIOS_MIN_MEM 0x10000000 | |
| 32 | − | |
| 33 | −#define HAVE_PCI_MMAP | |
| 34 | −#define ARCH_GENERIC_PCI_MMAP_RESOURCE | |
| 35 | −#define arch_can_pci_mmap_wc() 1 | |
| 36 | − | |
| 37 | −#define HAVE_PCI_LEGACY | |
| 38 | −extern int pci_mmap_legacy_page_range(struct pci_bus *bus, | |
| 39 | − struct vm_area_struct *vma, | |
| 40 | − enum pci_mmap_state mmap_state); | |
| 41 | − | |
| 42 | −char *pci_get_legacy_mem(struct pci_bus *bus); | |
| 43 | −int pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size); | |
| 44 | −int pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size); | |
| 45 | − | |
| 46 | −struct pci_controller { | |
| 47 | − struct acpi_device *companion; | |
| 48 | − void *iommu; | |
| 49 | − int segment; | |
| 50 | − int node; /* nearest node with memory or NUMA_NO_NODE for global allocation */ | |
| 51 | − | |
| 52 | − void *platform_data; | |
| 53 | −}; | |
| 54 | − | |
| 55 | − | |
| 56 | −#define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata) | |
| 57 | −#define pci_domain_nr(busdev) (PCI_CONTROLLER(busdev)->segment) | |
| 58 | − | |
| 59 | −extern struct pci_ops pci_root_ops; | |
| 60 | − | |
| 61 | −static inline int pci_proc_domain(struct pci_bus *bus) | |
| 62 | −{ | |
| 63 | − return (pci_domain_nr(bus) != 0); | |
| 64 | −} | |
| 65 | − | |
| 66 | −#endif /* _ASM_IA64_PCI_H */ | |
| @@ -1,53 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_PERCPU_H | |
| 3 | −#define _ASM_IA64_PERCPU_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Copyright (C) 2002-2003 Hewlett-Packard Co | |
| 7 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 8 | − */ | |
| 9 | − | |
| 10 | −#ifdef __ASSEMBLY__ | |
| 11 | −# define THIS_CPU(var) (var) /* use this to mark accesses to per-CPU variables... */ | |
| 12 | −#else /* !__ASSEMBLY__ */ | |
| 13 | − | |
| 14 | − | |
| 15 | −#include <linux/threads.h> | |
| 16 | − | |
| 17 | −#ifdef CONFIG_SMP | |
| 18 | − | |
| 19 | −#ifdef HAVE_MODEL_SMALL_ATTRIBUTE | |
| 20 | −# define PER_CPU_ATTRIBUTES __attribute__((__model__ (__small__))) | |
| 21 | −#endif | |
| 22 | − | |
| 23 | −#define __my_cpu_offset __ia64_per_cpu_var(local_per_cpu_offset) | |
| 24 | − | |
| 25 | −extern void *per_cpu_init(void); | |
| 26 | − | |
| 27 | −#else /* ! SMP */ | |
| 28 | − | |
| 29 | −#define per_cpu_init() (__phys_per_cpu_start) | |
| 30 | − | |
| 31 | −#endif /* SMP */ | |
| 32 | − | |
| 33 | −#define PER_CPU_BASE_SECTION ".data..percpu" | |
| 34 | − | |
| 35 | −/* | |
| 36 | − * Be extremely careful when taking the address of this variable! Due to virtual | |
| 37 | − * remapping, it is different from the canonical address returned by this_cpu_ptr(&var)! | |
| 38 | − * On the positive side, using __ia64_per_cpu_var() instead of this_cpu_ptr() is slightly | |
| 39 | − * more efficient. | |
| 40 | − */ | |
| 41 | −#define __ia64_per_cpu_var(var) (*({ \ | |
| 42 | − __verify_pcpu_ptr(&(var)); \ | |
| 43 | − ((typeof(var) __kernel __force *)&(var)); \ | |
| 44 | −})) | |
| 45 | − | |
| 46 | −#include <asm-generic/percpu.h> | |
| 47 | − | |
| 48 | −/* Equal to __per_cpu_offset[smp_processor_id()], but faster to access: */ | |
| 49 | −DECLARE_PER_CPU(unsigned long, local_per_cpu_offset); | |
| 50 | − | |
| 51 | −#endif /* !__ASSEMBLY__ */ | |
| 52 | − | |
| 53 | −#endif /* _ASM_IA64_PERCPU_H */ | |
| @@ -1,64 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_PGALLOC_H | |
| 3 | −#define _ASM_IA64_PGALLOC_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * This file contains the functions and defines necessary to allocate | |
| 7 | − * page tables. | |
| 8 | − * | |
| 9 | − * This hopefully works with any (fixed) ia-64 page-size, as defined | |
| 10 | − * in <asm/page.h> (currently 8192). | |
| 11 | − * | |
| 12 | − * Copyright (C) 1998-2001 Hewlett-Packard Co | |
| 13 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 14 | − * Copyright (C) 2000, Goutham Rao <goutham.rao@intel.com> | |
| 15 | − */ | |
| 16 | − | |
| 17 | − | |
| 18 | −#include <linux/compiler.h> | |
| 19 | −#include <linux/mm.h> | |
| 20 | −#include <linux/page-flags.h> | |
| 21 | −#include <linux/threads.h> | |
| 22 | − | |
| 23 | −#include <asm-generic/pgalloc.h> | |
| 24 | − | |
| 25 | −#include <asm/mmu_context.h> | |
| 26 | − | |
| 27 | −static inline pgd_t *pgd_alloc(struct mm_struct *mm) | |
| 28 | −{ | |
| 29 | − return (pgd_t *)__get_free_page(GFP_KERNEL | __GFP_ZERO); | |
| 30 | −} | |
| 31 | − | |
| 32 | −#if CONFIG_PGTABLE_LEVELS == 4 | |
| 33 | −static inline void | |
| 34 | −p4d_populate(struct mm_struct *mm, p4d_t * p4d_entry, pud_t * pud) | |
| 35 | −{ | |
| 36 | − p4d_val(*p4d_entry) = __pa(pud); | |
| 37 | −} | |
| 38 | − | |
| 39 | −#define __pud_free_tlb(tlb, pud, address) pud_free((tlb)->mm, pud) | |
| 40 | −#endif /* CONFIG_PGTABLE_LEVELS == 4 */ | |
| 41 | − | |
| 42 | −static inline void | |
| 43 | −pud_populate(struct mm_struct *mm, pud_t * pud_entry, pmd_t * pmd) | |
| 44 | −{ | |
| 45 | − pud_val(*pud_entry) = __pa(pmd); | |
| 46 | −} | |
| 47 | − | |
| 48 | −#define __pmd_free_tlb(tlb, pmd, address) pmd_free((tlb)->mm, pmd) | |
| 49 | − | |
| 50 | −static inline void | |
| 51 | −pmd_populate(struct mm_struct *mm, pmd_t * pmd_entry, pgtable_t pte) | |
| 52 | −{ | |
| 53 | − pmd_val(*pmd_entry) = page_to_phys(pte); | |
| 54 | −} | |
| 55 | − | |
| 56 | −static inline void | |
| 57 | −pmd_populate_kernel(struct mm_struct *mm, pmd_t * pmd_entry, pte_t * pte) | |
| 58 | −{ | |
| 59 | − pmd_val(*pmd_entry) = __pa(pte); | |
| 60 | −} | |
| 61 | − | |
| 62 | −#define __pte_free_tlb(tlb, pte, address) pte_free((tlb)->mm, pte) | |
| 63 | − | |
| 64 | −#endif /* _ASM_IA64_PGALLOC_H */ | |
| @@ -1,545 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_PGTABLE_H | |
| 3 | −#define _ASM_IA64_PGTABLE_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * This file contains the functions and defines necessary to modify and use | |
| 7 | − * the IA-64 page table tree. | |
| 8 | − * | |
| 9 | − * This hopefully works with any (fixed) IA-64 page-size, as defined | |
| 10 | − * in <asm/page.h>. | |
| 11 | − * | |
| 12 | − * Copyright (C) 1998-2005 Hewlett-Packard Co | |
| 13 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 14 | − */ | |
| 15 | − | |
| 16 | − | |
| 17 | −#include <asm/mman.h> | |
| 18 | −#include <asm/page.h> | |
| 19 | −#include <asm/processor.h> | |
| 20 | −#include <asm/types.h> | |
| 21 | − | |
| 22 | −#define IA64_MAX_PHYS_BITS 50 /* max. number of physical address bits (architected) */ | |
| 23 | − | |
| 24 | −/* | |
| 25 | − * First, define the various bits in a PTE. Note that the PTE format | |
| 26 | − * matches the VHPT short format, the firt doubleword of the VHPD long | |
| 27 | − * format, and the first doubleword of the TLB insertion format. | |
| 28 | − */ | |
| 29 | −#define _PAGE_P_BIT 0 | |
| 30 | −#define _PAGE_A_BIT 5 | |
| 31 | −#define _PAGE_D_BIT 6 | |
| 32 | − | |
| 33 | −#define _PAGE_P (1 << _PAGE_P_BIT) /* page present bit */ | |
| 34 | −#define _PAGE_MA_WB (0x0 << 2) /* write back memory attribute */ | |
| 35 | −#define _PAGE_MA_UC (0x4 << 2) /* uncacheable memory attribute */ | |
| 36 | −#define _PAGE_MA_UCE (0x5 << 2) /* UC exported attribute */ | |
| 37 | −#define _PAGE_MA_WC (0x6 << 2) /* write coalescing memory attribute */ | |
| 38 | −#define _PAGE_MA_NAT (0x7 << 2) /* not-a-thing attribute */ | |
| 39 | −#define _PAGE_MA_MASK (0x7 << 2) | |
| 40 | −#define _PAGE_PL_0 (0 << 7) /* privilege level 0 (kernel) */ | |
| 41 | −#define _PAGE_PL_1 (1 << 7) /* privilege level 1 (unused) */ | |
| 42 | −#define _PAGE_PL_2 (2 << 7) /* privilege level 2 (unused) */ | |
| 43 | −#define _PAGE_PL_3 (3 << 7) /* privilege level 3 (user) */ | |
| 44 | −#define _PAGE_PL_MASK (3 << 7) | |
| 45 | −#define _PAGE_AR_R (0 << 9) /* read only */ | |
| 46 | −#define _PAGE_AR_RX (1 << 9) /* read & execute */ | |
| 47 | −#define _PAGE_AR_RW (2 << 9) /* read & write */ | |
| 48 | −#define _PAGE_AR_RWX (3 << 9) /* read, write & execute */ | |
| 49 | −#define _PAGE_AR_R_RW (4 << 9) /* read / read & write */ | |
| 50 | −#define _PAGE_AR_RX_RWX (5 << 9) /* read & exec / read, write & exec */ | |
| 51 | −#define _PAGE_AR_RWX_RW (6 << 9) /* read, write & exec / read & write */ | |
| 52 | −#define _PAGE_AR_X_RX (7 << 9) /* exec & promote / read & exec */ | |
| 53 | −#define _PAGE_AR_MASK (7 << 9) | |
| 54 | −#define _PAGE_AR_SHIFT 9 | |
| 55 | −#define _PAGE_A (1 << _PAGE_A_BIT) /* page accessed bit */ | |
| 56 | −#define _PAGE_D (1 << _PAGE_D_BIT) /* page dirty bit */ | |
| 57 | −#define _PAGE_PPN_MASK (((__IA64_UL(1) << IA64_MAX_PHYS_BITS) - 1) & ~0xfffUL) | |
| 58 | −#define _PAGE_ED (__IA64_UL(1) << 52) /* exception deferral */ | |
| 59 | −#define _PAGE_PROTNONE (__IA64_UL(1) << 63) | |
| 60 | − | |
| 61 | −/* We borrow bit 7 to store the exclusive marker in swap PTEs. */ | |
| 62 | −#define _PAGE_SWP_EXCLUSIVE (1 << 7) | |
| 63 | − | |
| 64 | −#define _PFN_MASK _PAGE_PPN_MASK | |
| 65 | −/* Mask of bits which may be changed by pte_modify(); the odd bits are there for _PAGE_PROTNONE */ | |
| 66 | −#define _PAGE_CHG_MASK (_PAGE_P | _PAGE_PROTNONE | _PAGE_PL_MASK | _PAGE_AR_MASK | _PAGE_ED) | |
| 67 | − | |
| 68 | −#define _PAGE_SIZE_4K 12 | |
| 69 | −#define _PAGE_SIZE_8K 13 | |
| 70 | −#define _PAGE_SIZE_16K 14 | |
| 71 | −#define _PAGE_SIZE_64K 16 | |
| 72 | −#define _PAGE_SIZE_256K 18 | |
| 73 | −#define _PAGE_SIZE_1M 20 | |
| 74 | −#define _PAGE_SIZE_4M 22 | |
| 75 | −#define _PAGE_SIZE_16M 24 | |
| 76 | −#define _PAGE_SIZE_64M 26 | |
| 77 | −#define _PAGE_SIZE_256M 28 | |
| 78 | −#define _PAGE_SIZE_1G 30 | |
| 79 | −#define _PAGE_SIZE_4G 32 | |
| 80 | − | |
| 81 | −#define __ACCESS_BITS _PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_MA_WB | |
| 82 | −#define __DIRTY_BITS_NO_ED _PAGE_A | _PAGE_P | _PAGE_D | _PAGE_MA_WB | |
| 83 | −#define __DIRTY_BITS _PAGE_ED | __DIRTY_BITS_NO_ED | |
| 84 | − | |
| 85 | −/* | |
| 86 | − * How many pointers will a page table level hold expressed in shift | |
| 87 | − */ | |
| 88 | −#define PTRS_PER_PTD_SHIFT (PAGE_SHIFT-3) | |
| 89 | − | |
| 90 | −/* | |
| 91 | − * Definitions for fourth level: | |
| 92 | − */ | |
| 93 | −#define PTRS_PER_PTE (__IA64_UL(1) << (PTRS_PER_PTD_SHIFT)) | |
| 94 | − | |
| 95 | −/* | |
| 96 | − * Definitions for third level: | |
| 97 | − * | |
| 98 | − * PMD_SHIFT determines the size of the area a third-level page table | |
| 99 | − * can map. | |
| 100 | − */ | |
| 101 | −#define PMD_SHIFT (PAGE_SHIFT + (PTRS_PER_PTD_SHIFT)) | |
| 102 | −#define PMD_SIZE (1UL << PMD_SHIFT) | |
| 103 | −#define PMD_MASK (~(PMD_SIZE-1)) | |
| 104 | −#define PTRS_PER_PMD (1UL << (PTRS_PER_PTD_SHIFT)) | |
| 105 | − | |
| 106 | −#if CONFIG_PGTABLE_LEVELS == 4 | |
| 107 | −/* | |
| 108 | − * Definitions for second level: | |
| 109 | − * | |
| 110 | − * PUD_SHIFT determines the size of the area a second-level page table | |
| 111 | − * can map. | |
| 112 | − */ | |
| 113 | −#define PUD_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT)) | |
| 114 | −#define PUD_SIZE (1UL << PUD_SHIFT) | |
| 115 | −#define PUD_MASK (~(PUD_SIZE-1)) | |
| 116 | −#define PTRS_PER_PUD (1UL << (PTRS_PER_PTD_SHIFT)) | |
| 117 | −#endif | |
| 118 | − | |
| 119 | −/* | |
| 120 | − * Definitions for first level: | |
| 121 | − * | |
| 122 | − * PGDIR_SHIFT determines what a first-level page table entry can map. | |
| 123 | − */ | |
| 124 | −#if CONFIG_PGTABLE_LEVELS == 4 | |
| 125 | −#define PGDIR_SHIFT (PUD_SHIFT + (PTRS_PER_PTD_SHIFT)) | |
| 126 | −#else | |
| 127 | −#define PGDIR_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT)) | |
| 128 | −#endif | |
| 129 | −#define PGDIR_SIZE (__IA64_UL(1) << PGDIR_SHIFT) | |
| 130 | −#define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
| 131 | −#define PTRS_PER_PGD_SHIFT PTRS_PER_PTD_SHIFT | |
| 132 | −#define PTRS_PER_PGD (1UL << PTRS_PER_PGD_SHIFT) | |
| 133 | −#define USER_PTRS_PER_PGD (5*PTRS_PER_PGD/8) /* regions 0-4 are user regions */ | |
| 134 | − | |
| 135 | −/* | |
| 136 | − * All the normal masks have the "page accessed" bits on, as any time | |
| 137 | − * they are used, the page is accessed. They are cleared only by the | |
| 138 | − * page-out routines. | |
| 139 | − */ | |
| 140 | −#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_A) | |
| 141 | −#define PAGE_SHARED __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW) | |
| 142 | −#define PAGE_READONLY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R) | |
| 143 | −#define PAGE_COPY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R) | |
| 144 | −#define PAGE_COPY_EXEC __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX) | |
| 145 | −#define PAGE_GATE __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX) | |
| 146 | −#define PAGE_KERNEL __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX) | |
| 147 | −#define PAGE_KERNELRX __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_RX) | |
| 148 | −#define PAGE_KERNEL_UC __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX | \ | |
| 149 | − _PAGE_MA_UC) | |
| 150 | − | |
| 151 | −# ifndef __ASSEMBLY__ | |
| 152 | − | |
| 153 | −#include <linux/sched/mm.h> /* for mm_struct */ | |
| 154 | −#include <linux/bitops.h> | |
| 155 | −#include <asm/cacheflush.h> | |
| 156 | −#include <asm/mmu_context.h> | |
| 157 | − | |
| 158 | −/* | |
| 159 | − * Next come the mappings that determine how mmap() protection bits | |
| 160 | − * (PROT_EXEC, PROT_READ, PROT_WRITE, PROT_NONE) get implemented. The | |
| 161 | − * _P version gets used for a private shared memory segment, the _S | |
| 162 | − * version gets used for a shared memory segment with MAP_SHARED on. | |
| 163 | − * In a private shared memory segment, we do a copy-on-write if a task | |
| 164 | − * attempts to write to the page. | |
| 165 | − */ | |
| 166 | − /* xwr */ | |
| 167 | −#define pgd_ERROR(e) printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) | |
| 168 | −#if CONFIG_PGTABLE_LEVELS == 4 | |
| 169 | −#define pud_ERROR(e) printk("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e)) | |
| 170 | −#endif | |
| 171 | −#define pmd_ERROR(e) printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) | |
| 172 | −#define pte_ERROR(e) printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) | |
| 173 | − | |
| 174 | − | |
| 175 | −/* | |
| 176 | − * Some definitions to translate between mem_map, PTEs, and page addresses: | |
| 177 | − */ | |
| 178 | − | |
| 179 | − | |
| 180 | −/* Quick test to see if ADDR is a (potentially) valid physical address. */ | |
| 181 | −static inline long | |
| 182 | −ia64_phys_addr_valid (unsigned long addr) | |
| 183 | −{ | |
| 184 | − return (addr & (local_cpu_data->unimpl_pa_mask)) == 0; | |
| 185 | −} | |
| 186 | − | |
| 187 | −/* | |
| 188 | − * Now come the defines and routines to manage and access the three-level | |
| 189 | − * page table. | |
| 190 | − */ | |
| 191 | − | |
| 192 | − | |
| 193 | −#define VMALLOC_START (RGN_BASE(RGN_GATE) + 0x200000000UL) | |
| 194 | −#if defined(CONFIG_SPARSEMEM) && defined(CONFIG_SPARSEMEM_VMEMMAP) | |
| 195 | −/* SPARSEMEM_VMEMMAP uses half of vmalloc... */ | |
| 196 | −# define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 10))) | |
| 197 | −# define vmemmap ((struct page *)VMALLOC_END) | |
| 198 | −#else | |
| 199 | −# define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9))) | |
| 200 | −#endif | |
| 201 | − | |
| 202 | −/* fs/proc/kcore.c */ | |
| 203 | −#define kc_vaddr_to_offset(v) ((v) - RGN_BASE(RGN_GATE)) | |
| 204 | −#define kc_offset_to_vaddr(o) ((o) + RGN_BASE(RGN_GATE)) | |
| 205 | − | |
| 206 | −#define RGN_MAP_SHIFT (PGDIR_SHIFT + PTRS_PER_PGD_SHIFT - 3) | |
| 207 | −#define RGN_MAP_LIMIT ((1UL << RGN_MAP_SHIFT) - PAGE_SIZE) /* per region addr limit */ | |
| 208 | − | |
| 209 | −#define PFN_PTE_SHIFT PAGE_SHIFT | |
| 210 | −/* | |
| 211 | − * Conversion functions: convert page frame number (pfn) and a protection value to a page | |
| 212 | − * table entry (pte). | |
| 213 | − */ | |
| 214 | −#define pfn_pte(pfn, pgprot) \ | |
| 215 | −({ pte_t __pte; pte_val(__pte) = ((pfn) << PAGE_SHIFT) | pgprot_val(pgprot); __pte; }) | |
| 216 | − | |
| 217 | −/* Extract pfn from pte. */ | |
| 218 | −#define pte_pfn(_pte) ((pte_val(_pte) & _PFN_MASK) >> PAGE_SHIFT) | |
| 219 | − | |
| 220 | −#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) | |
| 221 | − | |
| 222 | −/* This takes a physical page address that is used by the remapping functions */ | |
| 223 | −#define mk_pte_phys(physpage, pgprot) \ | |
| 224 | −({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; }) | |
| 225 | − | |
| 226 | −#define pte_modify(_pte, newprot) \ | |
| 227 | − (__pte((pte_val(_pte) & ~_PAGE_CHG_MASK) | (pgprot_val(newprot) & _PAGE_CHG_MASK))) | |
| 228 | − | |
| 229 | −#define pte_none(pte) (!pte_val(pte)) | |
| 230 | −#define pte_present(pte) (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE)) | |
| 231 | −#define pte_clear(mm,addr,pte) (pte_val(*(pte)) = 0UL) | |
| 232 | −/* pte_page() returns the "struct page *" corresponding to the PTE: */ | |
| 233 | −#define pte_page(pte) virt_to_page(((pte_val(pte) & _PFN_MASK) + PAGE_OFFSET)) | |
| 234 | − | |
| 235 | −#define pmd_none(pmd) (!pmd_val(pmd)) | |
| 236 | −#define pmd_bad(pmd) (!ia64_phys_addr_valid(pmd_val(pmd))) | |
| 237 | −#define pmd_present(pmd) (pmd_val(pmd) != 0UL) | |
| 238 | −#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL) | |
| 239 | −#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & _PFN_MASK)) | |
| 240 | −#define pmd_pfn(pmd) ((pmd_val(pmd) & _PFN_MASK) >> PAGE_SHIFT) | |
| 241 | −#define pmd_page(pmd) virt_to_page((pmd_val(pmd) + PAGE_OFFSET)) | |
| 242 | − | |
| 243 | −#define pud_none(pud) (!pud_val(pud)) | |
| 244 | −#define pud_bad(pud) (!ia64_phys_addr_valid(pud_val(pud))) | |
| 245 | −#define pud_present(pud) (pud_val(pud) != 0UL) | |
| 246 | −#define pud_clear(pudp) (pud_val(*(pudp)) = 0UL) | |
| 247 | −#define pud_pgtable(pud) ((pmd_t *) __va(pud_val(pud) & _PFN_MASK)) | |
| 248 | −#define pud_page(pud) virt_to_page((pud_val(pud) + PAGE_OFFSET)) | |
| 249 | − | |
| 250 | −#if CONFIG_PGTABLE_LEVELS == 4 | |
| 251 | −#define p4d_none(p4d) (!p4d_val(p4d)) | |
| 252 | −#define p4d_bad(p4d) (!ia64_phys_addr_valid(p4d_val(p4d))) | |
| 253 | −#define p4d_present(p4d) (p4d_val(p4d) != 0UL) | |
| 254 | −#define p4d_clear(p4dp) (p4d_val(*(p4dp)) = 0UL) | |
| 255 | −#define p4d_pgtable(p4d) ((pud_t *) __va(p4d_val(p4d) & _PFN_MASK)) | |
| 256 | −#define p4d_page(p4d) virt_to_page((p4d_val(p4d) + PAGE_OFFSET)) | |
| 257 | −#endif | |
| 258 | − | |
| 259 | −/* | |
| 260 | − * The following have defined behavior only work if pte_present() is true. | |
| 261 | − */ | |
| 262 | −#define pte_write(pte) ((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) <= 4) | |
| 263 | −#define pte_exec(pte) ((pte_val(pte) & _PAGE_AR_RX) != 0) | |
| 264 | −#define pte_dirty(pte) ((pte_val(pte) & _PAGE_D) != 0) | |
| 265 | −#define pte_young(pte) ((pte_val(pte) & _PAGE_A) != 0) | |
| 266 | − | |
| 267 | −/* | |
| 268 | − * Note: we convert AR_RWX to AR_RX and AR_RW to AR_R by clearing the 2nd bit in the | |
| 269 | − * access rights: | |
| 270 | − */ | |
| 271 | −#define pte_wrprotect(pte) (__pte(pte_val(pte) & ~_PAGE_AR_RW)) | |
| 272 | −#define pte_mkwrite_novma(pte) (__pte(pte_val(pte) | _PAGE_AR_RW)) | |
| 273 | −#define pte_mkold(pte) (__pte(pte_val(pte) & ~_PAGE_A)) | |
| 274 | −#define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_A)) | |
| 275 | −#define pte_mkclean(pte) (__pte(pte_val(pte) & ~_PAGE_D)) | |
| 276 | −#define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_D)) | |
| 277 | −#define pte_mkhuge(pte) (__pte(pte_val(pte))) | |
| 278 | − | |
| 279 | −/* | |
| 280 | − * Because ia64's Icache and Dcache is not coherent (on a cpu), we need to | |
| 281 | − * sync icache and dcache when we insert *new* executable page. | |
| 282 | − * __ia64_sync_icache_dcache() check Pg_arch_1 bit and flush icache | |
| 283 | − * if necessary. | |
| 284 | − * | |
| 285 | − * set_pte() is also called by the kernel, but we can expect that the kernel | |
| 286 | − * flushes icache explicitly if necessary. | |
| 287 | − */ | |
| 288 | −#define pte_present_exec_user(pte)\ | |
| 289 | − ((pte_val(pte) & (_PAGE_P | _PAGE_PL_MASK | _PAGE_AR_RX)) == \ | |
| 290 | − (_PAGE_P | _PAGE_PL_3 | _PAGE_AR_RX)) | |
| 291 | − | |
| 292 | −extern void __ia64_sync_icache_dcache(pte_t pteval); | |
| 293 | −static inline void set_pte(pte_t *ptep, pte_t pteval) | |
| 294 | −{ | |
| 295 | − /* page is present && page is user && page is executable | |
| 296 | − * && (page swapin or new page or page migration | |
| 297 | − * || copy_on_write with page copying.) | |
| 298 | − */ | |
| 299 | − if (pte_present_exec_user(pteval) && | |
| 300 | − (!pte_present(*ptep) || | |
| 301 | − pte_pfn(*ptep) != pte_pfn(pteval))) | |
| 302 | − /* load_module() calles flush_icache_range() explicitly*/ | |
| 303 | − __ia64_sync_icache_dcache(pteval); | |
| 304 | − *ptep = pteval; | |
| 305 | −} | |
| 306 | − | |
| 307 | −/* | |
| 308 | − * Make page protection values cacheable, uncacheable, or write- | |
| 309 | − * combining. Note that "protection" is really a misnomer here as the | |
| 310 | − * protection value contains the memory attribute bits, dirty bits, and | |
| 311 | − * various other bits as well. | |
| 312 | − */ | |
| 313 | −#define pgprot_cacheable(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WB) | |
| 314 | −#define pgprot_noncached(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_UC) | |
| 315 | −#define pgprot_writecombine(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WC) | |
| 316 | − | |
| 317 | −struct file; | |
| 318 | −extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | |
| 319 | − unsigned long size, pgprot_t vma_prot); | |
| 320 | −#define __HAVE_PHYS_MEM_ACCESS_PROT | |
| 321 | − | |
| 322 | −static inline unsigned long | |
| 323 | −pgd_index (unsigned long address) | |
| 324 | −{ | |
| 325 | − unsigned long region = address >> 61; | |
| 326 | − unsigned long l1index = (address >> PGDIR_SHIFT) & ((PTRS_PER_PGD >> 3) - 1); | |
| 327 | − | |
| 328 | − return (region << (PAGE_SHIFT - 6)) | l1index; | |
| 329 | −} | |
| 330 | −#define pgd_index pgd_index | |
| 331 | − | |
| 332 | −/* | |
| 333 | − * In the kernel's mapped region we know everything is in region number 5, so | |
| 334 | − * as an optimisation its PGD already points to the area for that region. | |
| 335 | − * However, this also means that we cannot use pgd_index() and we must | |
| 336 | − * never add the region here. | |
| 337 | − */ | |
| 338 | −#define pgd_offset_k(addr) \ | |
| 339 | − (init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))) | |
| 340 | − | |
| 341 | −/* Look up a pgd entry in the gate area. On IA-64, the gate-area | |
| 342 | − resides in the kernel-mapped segment, hence we use pgd_offset_k() | |
| 343 | − here. */ | |
| 344 | −#define pgd_offset_gate(mm, addr) pgd_offset_k(addr) | |
| 345 | − | |
| 346 | −/* atomic versions of the some PTE manipulations: */ | |
| 347 | − | |
| 348 | −static inline int | |
| 349 | −ptep_test_and_clear_young (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep) | |
| 350 | −{ | |
| 351 | −#ifdef CONFIG_SMP | |
| 352 | − if (!pte_young(*ptep)) | |
| 353 | − return 0; | |
| 354 | − return test_and_clear_bit(_PAGE_A_BIT, ptep); | |
| 355 | −#else | |
| 356 | − pte_t pte = *ptep; | |
| 357 | − if (!pte_young(pte)) | |
| 358 | − return 0; | |
| 359 | − set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte)); | |
| 360 | − return 1; | |
| 361 | −#endif | |
| 362 | −} | |
| 363 | − | |
| 364 | −static inline pte_t | |
| 365 | −ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) | |
| 366 | −{ | |
| 367 | −#ifdef CONFIG_SMP | |
| 368 | − return __pte(xchg((long *) ptep, 0)); | |
| 369 | −#else | |
| 370 | − pte_t pte = *ptep; | |
| 371 | − pte_clear(mm, addr, ptep); | |
| 372 | − return pte; | |
| 373 | −#endif | |
| 374 | −} | |
| 375 | − | |
| 376 | −static inline void | |
| 377 | −ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) | |
| 378 | −{ | |
| 379 | −#ifdef CONFIG_SMP | |
| 380 | − unsigned long new, old; | |
| 381 | − | |
| 382 | − do { | |
| 383 | − old = pte_val(*ptep); | |
| 384 | − new = pte_val(pte_wrprotect(__pte (old))); | |
| 385 | − } while (cmpxchg((unsigned long *) ptep, old, new) != old); | |
| 386 | −#else | |
| 387 | − pte_t old_pte = *ptep; | |
| 388 | − set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte)); | |
| 389 | −#endif | |
| 390 | −} | |
| 391 | − | |
| 392 | −static inline int | |
| 393 | −pte_same (pte_t a, pte_t b) | |
| 394 | −{ | |
| 395 | − return pte_val(a) == pte_val(b); | |
| 396 | −} | |
| 397 | − | |
| 398 | −#define update_mmu_cache_range(vmf, vma, address, ptep, nr) do { } while (0) | |
| 399 | −#define update_mmu_cache(vma, address, ptep) do { } while (0) | |
| 400 | − | |
| 401 | −extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; | |
| 402 | −extern void paging_init (void); | |
| 403 | − | |
| 404 | −/* | |
| 405 | − * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that | |
| 406 | − * are !pte_none() && !pte_present(). | |
| 407 | − * | |
| 408 | − * Note: The macros below rely on the fact that MAX_SWAPFILES_SHIFT <= number of | |
| 409 | − * bits in the swap-type field of the swap pte. It would be nice to | |
| 410 | − * enforce that, but we can't easily include <linux/swap.h> here. | |
| 411 | − * (Of course, better still would be to define MAX_SWAPFILES_SHIFT here...). | |
| 412 | − * | |
| 413 | − * Format of swap pte: | |
| 414 | − * bit 0 : present bit (must be zero) | |
| 415 | − * bits 1- 6: swap type | |
| 416 | − * bit 7 : exclusive marker | |
| 417 | − * bits 8-62: swap offset | |
| 418 | − * bit 63 : _PAGE_PROTNONE bit | |
| 419 | − */ | |
| 420 | −#define __swp_type(entry) (((entry).val >> 1) & 0x3f) | |
| 421 | −#define __swp_offset(entry) (((entry).val << 1) >> 9) | |
| 422 | −#define __swp_entry(type, offset) ((swp_entry_t) { ((type & 0x3f) << 1) | \ | |
| 423 | − ((long) (offset) << 8) }) | |
| 424 | −#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
| 425 | −#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | |
| 426 | − | |
| 427 | −static inline int pte_swp_exclusive(pte_t pte) | |
| 428 | −{ | |
| 429 | − return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; | |
| 430 | −} | |
| 431 | − | |
| 432 | −static inline pte_t pte_swp_mkexclusive(pte_t pte) | |
| 433 | −{ | |
| 434 | − pte_val(pte) |= _PAGE_SWP_EXCLUSIVE; | |
| 435 | − return pte; | |
| 436 | −} | |
| 437 | − | |
| 438 | −static inline pte_t pte_swp_clear_exclusive(pte_t pte) | |
| 439 | −{ | |
| 440 | − pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE; | |
| 441 | − return pte; | |
| 442 | −} | |
| 443 | − | |
| 444 | −/* | |
| 445 | − * ZERO_PAGE is a global shared page that is always zero: used | |
| 446 | − * for zero-mapped memory areas etc.. | |
| 447 | − */ | |
| 448 | −extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)]; | |
| 449 | −extern struct page *zero_page_memmap_ptr; | |
| 450 | −#define ZERO_PAGE(vaddr) (zero_page_memmap_ptr) | |
| 451 | − | |
| 452 | −/* We provide our own get_unmapped_area to cope with VA holes for userland */ | |
| 453 | −#define HAVE_ARCH_UNMAPPED_AREA | |
| 454 | − | |
| 455 | −#ifdef CONFIG_HUGETLB_PAGE | |
| 456 | −#define HUGETLB_PGDIR_SHIFT (HPAGE_SHIFT + 2*(PAGE_SHIFT-3)) | |
| 457 | −#define HUGETLB_PGDIR_SIZE (__IA64_UL(1) << HUGETLB_PGDIR_SHIFT) | |
| 458 | −#define HUGETLB_PGDIR_MASK (~(HUGETLB_PGDIR_SIZE-1)) | |
| 459 | −#endif | |
| 460 | − | |
| 461 | − | |
| 462 | −#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS | |
| 463 | −/* | |
| 464 | − * Update PTEP with ENTRY, which is guaranteed to be a less | |
| 465 | − * restrictive PTE. That is, ENTRY may have the ACCESSED, DIRTY, and | |
| 466 | − * WRITABLE bits turned on, when the value at PTEP did not. The | |
| 467 | − * WRITABLE bit may only be turned if SAFELY_WRITABLE is TRUE. | |
| 468 | − * | |
| 469 | − * SAFELY_WRITABLE is TRUE if we can update the value at PTEP without | |
| 470 | − * having to worry about races. On SMP machines, there are only two | |
| 471 | − * cases where this is true: | |
| 472 | − * | |
| 473 | − * (1) *PTEP has the PRESENT bit turned OFF | |
| 474 | − * (2) ENTRY has the DIRTY bit turned ON | |
| 475 | − * | |
| 476 | − * On ia64, we could implement this routine with a cmpxchg()-loop | |
| 477 | − * which ORs in the _PAGE_A/_PAGE_D bit if they're set in ENTRY. | |
| 478 | − * However, like on x86, we can get a more streamlined version by | |
| 479 | − * observing that it is OK to drop ACCESSED bit updates when | |
| 480 | − * SAFELY_WRITABLE is FALSE. Besides being rare, all that would do is | |
| 481 | − * result in an extra Access-bit fault, which would then turn on the | |
| 482 | − * ACCESSED bit in the low-level fault handler (iaccess_bit or | |
| 483 | − * daccess_bit in ivt.S). | |
| 484 | − */ | |
| 485 | −#ifdef CONFIG_SMP | |
| 486 | −# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \ | |
| 487 | −({ \ | |
| 488 | − int __changed = !pte_same(*(__ptep), __entry); \ | |
| 489 | − if (__changed && __safely_writable) { \ | |
| 490 | − set_pte(__ptep, __entry); \ | |
| 491 | − flush_tlb_page(__vma, __addr); \ | |
| 492 | − } \ | |
| 493 | − __changed; \ | |
| 494 | −}) | |
| 495 | −#else | |
| 496 | −# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \ | |
| 497 | −({ \ | |
| 498 | − int __changed = !pte_same(*(__ptep), __entry); \ | |
| 499 | − if (__changed) { \ | |
| 500 | − set_pte_at((__vma)->vm_mm, (__addr), __ptep, __entry); \ | |
| 501 | − flush_tlb_page(__vma, __addr); \ | |
| 502 | − } \ | |
| 503 | − __changed; \ | |
| 504 | −}) | |
| 505 | −#endif | |
| 506 | −# endif /* !__ASSEMBLY__ */ | |
| 507 | − | |
| 508 | −/* | |
| 509 | − * Identity-mapped regions use a large page size. We'll call such large pages | |
| 510 | − * "granules". If you can think of a better name that's unambiguous, let me | |
| 511 | − * know... | |
| 512 | − */ | |
| 513 | −#if defined(CONFIG_IA64_GRANULE_64MB) | |
| 514 | −# define IA64_GRANULE_SHIFT _PAGE_SIZE_64M | |
| 515 | −#elif defined(CONFIG_IA64_GRANULE_16MB) | |
| 516 | −# define IA64_GRANULE_SHIFT _PAGE_SIZE_16M | |
| 517 | −#endif | |
| 518 | −#define IA64_GRANULE_SIZE (1 << IA64_GRANULE_SHIFT) | |
| 519 | −/* | |
| 520 | − * log2() of the page size we use to map the kernel image (IA64_TR_KERNEL): | |
| 521 | − */ | |
| 522 | −#define KERNEL_TR_PAGE_SHIFT _PAGE_SIZE_64M | |
| 523 | −#define KERNEL_TR_PAGE_SIZE (1 << KERNEL_TR_PAGE_SHIFT) | |
| 524 | − | |
| 525 | −/* These tell get_user_pages() that the first gate page is accessible from user-level. */ | |
| 526 | −#define FIXADDR_USER_START GATE_ADDR | |
| 527 | −#ifdef HAVE_BUGGY_SEGREL | |
| 528 | −# define FIXADDR_USER_END (GATE_ADDR + 2*PAGE_SIZE) | |
| 529 | −#else | |
| 530 | −# define FIXADDR_USER_END (GATE_ADDR + 2*PERCPU_PAGE_SIZE) | |
| 531 | −#endif | |
| 532 | − | |
| 533 | −#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG | |
| 534 | −#define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
| 535 | −#define __HAVE_ARCH_PTEP_SET_WRPROTECT | |
| 536 | −#define __HAVE_ARCH_PTE_SAME | |
| 537 | −#define __HAVE_ARCH_PGD_OFFSET_GATE | |
| 538 | − | |
| 539 | − | |
| 540 | −#if CONFIG_PGTABLE_LEVELS == 3 | |
| 541 | −#include <asm-generic/pgtable-nopud.h> | |
| 542 | −#endif | |
| 543 | −#include <asm-generic/pgtable-nop4d.h> | |
| 544 | − | |
| 545 | −#endif /* _ASM_IA64_PGTABLE_H */ | |
| @@ -1,660 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_PROCESSOR_H | |
| 3 | −#define _ASM_IA64_PROCESSOR_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Copyright (C) 1998-2004 Hewlett-Packard Co | |
| 7 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 8 | − * Stephane Eranian <eranian@hpl.hp.com> | |
| 9 | − * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> | |
| 10 | − * Copyright (C) 1999 Don Dugger <don.dugger@intel.com> | |
| 11 | − * | |
| 12 | − * 11/24/98 S.Eranian added ia64_set_iva() | |
| 13 | − * 12/03/99 D. Mosberger implement thread_saved_pc() via kernel unwind API | |
| 14 | − * 06/16/00 A. Mallick added csd/ssd/tssd for ia32 support | |
| 15 | − */ | |
| 16 | − | |
| 17 | − | |
| 18 | −#include <asm/intrinsics.h> | |
| 19 | −#include <asm/kregs.h> | |
| 20 | −#include <asm/ptrace.h> | |
| 21 | −#include <asm/ustack.h> | |
| 22 | − | |
| 23 | −#define IA64_NUM_PHYS_STACK_REG 96 | |
| 24 | −#define IA64_NUM_DBG_REGS 8 | |
| 25 | − | |
| 26 | −#define DEFAULT_MAP_BASE __IA64_UL_CONST(0x2000000000000000) | |
| 27 | −#define DEFAULT_TASK_SIZE __IA64_UL_CONST(0xa000000000000000) | |
| 28 | − | |
| 29 | −/* | |
| 30 | − * TASK_SIZE really is a mis-named. It really is the maximum user | |
| 31 | − * space address (plus one). On IA-64, there are five regions of 2TB | |
| 32 | − * each (assuming 8KB page size), for a total of 8TB of user virtual | |
| 33 | − * address space. | |
| 34 | − */ | |
| 35 | −#define TASK_SIZE DEFAULT_TASK_SIZE | |
| 36 | − | |
| 37 | −/* | |
| 38 | − * This decides where the kernel will search for a free chunk of vm | |
| 39 | − * space during mmap's. | |
| 40 | − */ | |
| 41 | −#define TASK_UNMAPPED_BASE (current->thread.map_base) | |
| 42 | − | |
| 43 | −#define IA64_THREAD_FPH_VALID (__IA64_UL(1) << 0) /* floating-point high state valid? */ | |
| 44 | −#define IA64_THREAD_DBG_VALID (__IA64_UL(1) << 1) /* debug registers valid? */ | |
| 45 | −#define IA64_THREAD_PM_VALID (__IA64_UL(1) << 2) /* performance registers valid? */ | |
| 46 | −#define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3) /* don't log unaligned accesses */ | |
| 47 | −#define IA64_THREAD_UAC_SIGBUS (__IA64_UL(1) << 4) /* generate SIGBUS on unaligned acc. */ | |
| 48 | −#define IA64_THREAD_MIGRATION (__IA64_UL(1) << 5) /* require migration | |
| 49 | − sync at ctx sw */ | |
| 50 | −#define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6) /* don't log any fpswa faults */ | |
| 51 | −#define IA64_THREAD_FPEMU_SIGFPE (__IA64_UL(1) << 7) /* send a SIGFPE for fpswa faults */ | |
| 52 | − | |
| 53 | −#define IA64_THREAD_UAC_SHIFT 3 | |
| 54 | −#define IA64_THREAD_UAC_MASK (IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS) | |
| 55 | −#define IA64_THREAD_FPEMU_SHIFT 6 | |
| 56 | −#define IA64_THREAD_FPEMU_MASK (IA64_THREAD_FPEMU_NOPRINT | IA64_THREAD_FPEMU_SIGFPE) | |
| 57 | − | |
| 58 | − | |
| 59 | −/* | |
| 60 | − * This shift should be large enough to be able to represent 1000000000/itc_freq with good | |
| 61 | − * accuracy while being small enough to fit 10*1000000000<<IA64_NSEC_PER_CYC_SHIFT in 64 bits | |
| 62 | − * (this will give enough slack to represent 10 seconds worth of time as a scaled number). | |
| 63 | − */ | |
| 64 | −#define IA64_NSEC_PER_CYC_SHIFT 30 | |
| 65 | − | |
| 66 | −#ifndef __ASSEMBLY__ | |
| 67 | − | |
| 68 | −#include <linux/cache.h> | |
| 69 | −#include <linux/compiler.h> | |
| 70 | −#include <linux/threads.h> | |
| 71 | −#include <linux/types.h> | |
| 72 | −#include <linux/bitops.h> | |
| 73 | − | |
| 74 | −#include <asm/fpu.h> | |
| 75 | −#include <asm/page.h> | |
| 76 | −#include <asm/percpu.h> | |
| 77 | −#include <asm/rse.h> | |
| 78 | −#include <asm/unwind.h> | |
| 79 | −#include <linux/atomic.h> | |
| 80 | −#ifdef CONFIG_NUMA | |
| 81 | −#include <asm/nodedata.h> | |
| 82 | −#endif | |
| 83 | − | |
| 84 | −/* like above but expressed as bitfields for more efficient access: */ | |
| 85 | −struct ia64_psr { | |
| 86 | − __u64 reserved0 : 1; | |
| 87 | − __u64 be : 1; | |
| 88 | − __u64 up : 1; | |
| 89 | − __u64 ac : 1; | |
| 90 | − __u64 mfl : 1; | |
| 91 | − __u64 mfh : 1; | |
| 92 | − __u64 reserved1 : 7; | |
| 93 | − __u64 ic : 1; | |
| 94 | − __u64 i : 1; | |
| 95 | − __u64 pk : 1; | |
| 96 | − __u64 reserved2 : 1; | |
| 97 | − __u64 dt : 1; | |
| 98 | − __u64 dfl : 1; | |
| 99 | − __u64 dfh : 1; | |
| 100 | − __u64 sp : 1; | |
| 101 | − __u64 pp : 1; | |
| 102 | − __u64 di : 1; | |
| 103 | − __u64 si : 1; | |
| 104 | − __u64 db : 1; | |
| 105 | − __u64 lp : 1; | |
| 106 | − __u64 tb : 1; | |
| 107 | − __u64 rt : 1; | |
| 108 | − __u64 reserved3 : 4; | |
| 109 | − __u64 cpl : 2; | |
| 110 | − __u64 is : 1; | |
| 111 | − __u64 mc : 1; | |
| 112 | − __u64 it : 1; | |
| 113 | − __u64 id : 1; | |
| 114 | − __u64 da : 1; | |
| 115 | − __u64 dd : 1; | |
| 116 | − __u64 ss : 1; | |
| 117 | − __u64 ri : 2; | |
| 118 | − __u64 ed : 1; | |
| 119 | − __u64 bn : 1; | |
| 120 | − __u64 reserved4 : 19; | |
| 121 | −}; | |
| 122 | − | |
| 123 | −union ia64_isr { | |
| 124 | − __u64 val; | |
| 125 | − struct { | |
| 126 | − __u64 code : 16; | |
| 127 | − __u64 vector : 8; | |
| 128 | − __u64 reserved1 : 8; | |
| 129 | − __u64 x : 1; | |
| 130 | − __u64 w : 1; | |
| 131 | − __u64 r : 1; | |
| 132 | − __u64 na : 1; | |
| 133 | − __u64 sp : 1; | |
| 134 | − __u64 rs : 1; | |
| 135 | − __u64 ir : 1; | |
| 136 | − __u64 ni : 1; | |
| 137 | − __u64 so : 1; | |
| 138 | − __u64 ei : 2; | |
| 139 | − __u64 ed : 1; | |
| 140 | − __u64 reserved2 : 20; | |
| 141 | − }; | |
| 142 | −}; | |
| 143 | − | |
| 144 | −union ia64_lid { | |
| 145 | − __u64 val; | |
| 146 | − struct { | |
| 147 | − __u64 rv : 16; | |
| 148 | − __u64 eid : 8; | |
| 149 | − __u64 id : 8; | |
| 150 | − __u64 ig : 32; | |
| 151 | − }; | |
| 152 | −}; | |
| 153 | − | |
| 154 | −union ia64_tpr { | |
| 155 | − __u64 val; | |
| 156 | − struct { | |
| 157 | − __u64 ig0 : 4; | |
| 158 | − __u64 mic : 4; | |
| 159 | − __u64 rsv : 8; | |
| 160 | − __u64 mmi : 1; | |
| 161 | − __u64 ig1 : 47; | |
| 162 | − }; | |
| 163 | −}; | |
| 164 | − | |
| 165 | −union ia64_itir { | |
| 166 | − __u64 val; | |
| 167 | − struct { | |
| 168 | − __u64 rv3 : 2; /* 0-1 */ | |
| 169 | − __u64 ps : 6; /* 2-7 */ | |
| 170 | − __u64 key : 24; /* 8-31 */ | |
| 171 | − __u64 rv4 : 32; /* 32-63 */ | |
| 172 | − }; | |
| 173 | −}; | |
| 174 | − | |
| 175 | −union ia64_rr { | |
| 176 | − __u64 val; | |
| 177 | − struct { | |
| 178 | − __u64 ve : 1; /* enable hw walker */ | |
| 179 | − __u64 reserved0: 1; /* reserved */ | |
| 180 | − __u64 ps : 6; /* log page size */ | |
| 181 | − __u64 rid : 24; /* region id */ | |
| 182 | − __u64 reserved1: 32; /* reserved */ | |
| 183 | − }; | |
| 184 | −}; | |
| 185 | − | |
| 186 | −/* | |
| 187 | − * CPU type, hardware bug flags, and per-CPU state. Frequently used | |
| 188 | − * state comes earlier: | |
| 189 | − */ | |
| 190 | −struct cpuinfo_ia64 { | |
| 191 | − unsigned int softirq_pending; | |
| 192 | − unsigned long itm_delta; /* # of clock cycles between clock ticks */ | |
| 193 | − unsigned long itm_next; /* interval timer mask value to use for next clock tick */ | |
| 194 | − unsigned long nsec_per_cyc; /* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */ | |
| 195 | − unsigned long unimpl_va_mask; /* mask of unimplemented virtual address bits (from PAL) */ | |
| 196 | − unsigned long unimpl_pa_mask; /* mask of unimplemented physical address bits (from PAL) */ | |
| 197 | − unsigned long itc_freq; /* frequency of ITC counter */ | |
| 198 | − unsigned long proc_freq; /* frequency of processor */ | |
| 199 | − unsigned long cyc_per_usec; /* itc_freq/1000000 */ | |
| 200 | − unsigned long ptce_base; | |
| 201 | − unsigned int ptce_count[2]; | |
| 202 | − unsigned int ptce_stride[2]; | |
| 203 | − struct task_struct *ksoftirqd; /* kernel softirq daemon for this CPU */ | |
| 204 | − | |
| 205 | −#ifdef CONFIG_SMP | |
| 206 | − unsigned long loops_per_jiffy; | |
| 207 | − int cpu; | |
| 208 | − unsigned int socket_id; /* physical processor socket id */ | |
| 209 | − unsigned short core_id; /* core id */ | |
| 210 | − unsigned short thread_id; /* thread id */ | |
| 211 | − unsigned short num_log; /* Total number of logical processors on | |
| 212 | − * this socket that were successfully booted */ | |
| 213 | − unsigned char cores_per_socket; /* Cores per processor socket */ | |
| 214 | − unsigned char threads_per_core; /* Threads per core */ | |
| 215 | −#endif | |
| 216 | − | |
| 217 | − /* CPUID-derived information: */ | |
| 218 | − unsigned long ppn; | |
| 219 | − unsigned long features; | |
| 220 | − unsigned char number; | |
| 221 | − unsigned char revision; | |
| 222 | − unsigned char model; | |
| 223 | − unsigned char family; | |
| 224 | − unsigned char archrev; | |
| 225 | − char vendor[16]; | |
| 226 | − char *model_name; | |
| 227 | − | |
| 228 | −#ifdef CONFIG_NUMA | |
| 229 | − struct ia64_node_data *node_data; | |
| 230 | −#endif | |
| 231 | −}; | |
| 232 | − | |
| 233 | −DECLARE_PER_CPU(struct cpuinfo_ia64, ia64_cpu_info); | |
| 234 | − | |
| 235 | −/* | |
| 236 | − * The "local" data variable. It refers to the per-CPU data of the currently executing | |
| 237 | − * CPU, much like "current" points to the per-task data of the currently executing task. | |
| 238 | − * Do not use the address of local_cpu_data, since it will be different from | |
| 239 | − * cpu_data(smp_processor_id())! | |
| 240 | − */ | |
| 241 | −#define local_cpu_data (&__ia64_per_cpu_var(ia64_cpu_info)) | |
| 242 | −#define cpu_data(cpu) (&per_cpu(ia64_cpu_info, cpu)) | |
| 243 | − | |
| 244 | −extern void print_cpu_info (struct cpuinfo_ia64 *); | |
| 245 | − | |
| 246 | −#define SET_UNALIGN_CTL(task,value) \ | |
| 247 | −({ \ | |
| 248 | − (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK) \ | |
| 249 | − | (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK)); \ | |
| 250 | − 0; \ | |
| 251 | −}) | |
| 252 | −#define GET_UNALIGN_CTL(task,addr) \ | |
| 253 | −({ \ | |
| 254 | − put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT, \ | |
| 255 | − (int __user *) (addr)); \ | |
| 256 | −}) | |
| 257 | − | |
| 258 | −#define SET_FPEMU_CTL(task,value) \ | |
| 259 | −({ \ | |
| 260 | − (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_FPEMU_MASK) \ | |
| 261 | − | (((value) << IA64_THREAD_FPEMU_SHIFT) & IA64_THREAD_FPEMU_MASK)); \ | |
| 262 | − 0; \ | |
| 263 | −}) | |
| 264 | −#define GET_FPEMU_CTL(task,addr) \ | |
| 265 | −({ \ | |
| 266 | − put_user(((task)->thread.flags & IA64_THREAD_FPEMU_MASK) >> IA64_THREAD_FPEMU_SHIFT, \ | |
| 267 | − (int __user *) (addr)); \ | |
| 268 | −}) | |
| 269 | − | |
| 270 | −struct thread_struct { | |
| 271 | − __u32 flags; /* various thread flags (see IA64_THREAD_*) */ | |
| 272 | − /* writing on_ustack is performance-critical, so it's worth spending 8 bits on it... */ | |
| 273 | − __u8 on_ustack; /* executing on user-stacks? */ | |
| 274 | − __u8 pad[3]; | |
| 275 | − __u64 ksp; /* kernel stack pointer */ | |
| 276 | − __u64 map_base; /* base address for get_unmapped_area() */ | |
| 277 | − __u64 rbs_bot; /* the base address for the RBS */ | |
| 278 | − int last_fph_cpu; /* CPU that may hold the contents of f32-f127 */ | |
| 279 | − unsigned long dbr[IA64_NUM_DBG_REGS]; | |
| 280 | − unsigned long ibr[IA64_NUM_DBG_REGS]; | |
| 281 | − struct ia64_fpreg fph[96]; /* saved/loaded on demand */ | |
| 282 | −}; | |
| 283 | − | |
| 284 | −#define INIT_THREAD { \ | |
| 285 | − .flags = 0, \ | |
| 286 | − .on_ustack = 0, \ | |
| 287 | − .ksp = 0, \ | |
| 288 | − .map_base = DEFAULT_MAP_BASE, \ | |
| 289 | − .rbs_bot = STACK_TOP - DEFAULT_USER_STACK_SIZE, \ | |
| 290 | − .last_fph_cpu = -1, \ | |
| 291 | − .dbr = {0, }, \ | |
| 292 | − .ibr = {0, }, \ | |
| 293 | − .fph = {{{{0}}}, } \ | |
| 294 | −} | |
| 295 | − | |
| 296 | −#define start_thread(regs,new_ip,new_sp) do { \ | |
| 297 | − regs->cr_ipsr = ((regs->cr_ipsr | (IA64_PSR_BITS_TO_SET | IA64_PSR_CPL)) \ | |
| 298 | − & ~(IA64_PSR_BITS_TO_CLEAR | IA64_PSR_RI | IA64_PSR_IS)); \ | |
| 299 | − regs->cr_iip = new_ip; \ | |
| 300 | − regs->ar_rsc = 0xf; /* eager mode, privilege level 3 */ \ | |
| 301 | − regs->ar_rnat = 0; \ | |
| 302 | − regs->ar_bspstore = current->thread.rbs_bot; \ | |
| 303 | − regs->ar_fpsr = FPSR_DEFAULT; \ | |
| 304 | − regs->loadrs = 0; \ | |
| 305 | − regs->r8 = get_dumpable(current->mm); /* set "don't zap registers" flag */ \ | |
| 306 | − regs->r12 = new_sp - 16; /* allocate 16 byte scratch area */ \ | |
| 307 | − if (unlikely(get_dumpable(current->mm) != SUID_DUMP_USER)) { \ | |
| 308 | − /* \ | |
| 309 | − * Zap scratch regs to avoid leaking bits between processes with different \ | |
| 310 | − * uid/privileges. \ | |
| 311 | − */ \ | |
| 312 | − regs->ar_pfs = 0; regs->b0 = 0; regs->pr = 0; \ | |
| 313 | − regs->r1 = 0; regs->r9 = 0; regs->r11 = 0; regs->r13 = 0; regs->r15 = 0; \ | |
| 314 | − } \ | |
| 315 | −} while (0) | |
| 316 | − | |
| 317 | −/* Forward declarations, a strange C thing... */ | |
| 318 | −struct mm_struct; | |
| 319 | −struct task_struct; | |
| 320 | − | |
| 321 | −/* Get wait channel for task P. */ | |
| 322 | −extern unsigned long __get_wchan (struct task_struct *p); | |
| 323 | − | |
| 324 | −/* Return instruction pointer of blocked task TSK. */ | |
| 325 | −#define KSTK_EIP(tsk) \ | |
| 326 | − ({ \ | |
| 327 | − struct pt_regs *_regs = task_pt_regs(tsk); \ | |
| 328 | − _regs->cr_iip + ia64_psr(_regs)->ri; \ | |
| 329 | − }) | |
| 330 | − | |
| 331 | −/* Return stack pointer of blocked task TSK. */ | |
| 332 | −#define KSTK_ESP(tsk) ((tsk)->thread.ksp) | |
| 333 | − | |
| 334 | −extern void ia64_getreg_unknown_kr (void); | |
| 335 | −extern void ia64_setreg_unknown_kr (void); | |
| 336 | − | |
| 337 | −#define ia64_get_kr(regnum) \ | |
| 338 | −({ \ | |
| 339 | − unsigned long r = 0; \ | |
| 340 | − \ | |
| 341 | − switch (regnum) { \ | |
| 342 | − case 0: r = ia64_getreg(_IA64_REG_AR_KR0); break; \ | |
| 343 | − case 1: r = ia64_getreg(_IA64_REG_AR_KR1); break; \ | |
| 344 | − case 2: r = ia64_getreg(_IA64_REG_AR_KR2); break; \ | |
| 345 | − case 3: r = ia64_getreg(_IA64_REG_AR_KR3); break; \ | |
| 346 | − case 4: r = ia64_getreg(_IA64_REG_AR_KR4); break; \ | |
| 347 | − case 5: r = ia64_getreg(_IA64_REG_AR_KR5); break; \ | |
| 348 | − case 6: r = ia64_getreg(_IA64_REG_AR_KR6); break; \ | |
| 349 | − case 7: r = ia64_getreg(_IA64_REG_AR_KR7); break; \ | |
| 350 | − default: ia64_getreg_unknown_kr(); break; \ | |
| 351 | − } \ | |
| 352 | − r; \ | |
| 353 | −}) | |
| 354 | − | |
| 355 | −#define ia64_set_kr(regnum, r) \ | |
| 356 | −({ \ | |
| 357 | − switch (regnum) { \ | |
| 358 | − case 0: ia64_setreg(_IA64_REG_AR_KR0, r); break; \ | |
| 359 | − case 1: ia64_setreg(_IA64_REG_AR_KR1, r); break; \ | |
| 360 | − case 2: ia64_setreg(_IA64_REG_AR_KR2, r); break; \ | |
| 361 | − case 3: ia64_setreg(_IA64_REG_AR_KR3, r); break; \ | |
| 362 | − case 4: ia64_setreg(_IA64_REG_AR_KR4, r); break; \ | |
| 363 | − case 5: ia64_setreg(_IA64_REG_AR_KR5, r); break; \ | |
| 364 | − case 6: ia64_setreg(_IA64_REG_AR_KR6, r); break; \ | |
| 365 | − case 7: ia64_setreg(_IA64_REG_AR_KR7, r); break; \ | |
| 366 | − default: ia64_setreg_unknown_kr(); break; \ | |
| 367 | − } \ | |
| 368 | −}) | |
| 369 | − | |
| 370 | −/* | |
| 371 | − * The following three macros can't be inline functions because we don't have struct | |
| 372 | − * task_struct at this point. | |
| 373 | − */ | |
| 374 | − | |
| 375 | −/* | |
| 376 | − * Return TRUE if task T owns the fph partition of the CPU we're running on. | |
| 377 | − * Must be called from code that has preemption disabled. | |
| 378 | − */ | |
| 379 | −#define ia64_is_local_fpu_owner(t) \ | |
| 380 | −({ \ | |
| 381 | − struct task_struct *__ia64_islfo_task = (t); \ | |
| 382 | − (__ia64_islfo_task->thread.last_fph_cpu == smp_processor_id() \ | |
| 383 | − && __ia64_islfo_task == (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER)); \ | |
| 384 | −}) | |
| 385 | − | |
| 386 | −/* | |
| 387 | − * Mark task T as owning the fph partition of the CPU we're running on. | |
| 388 | − * Must be called from code that has preemption disabled. | |
| 389 | − */ | |
| 390 | −#define ia64_set_local_fpu_owner(t) do { \ | |
| 391 | − struct task_struct *__ia64_slfo_task = (t); \ | |
| 392 | − __ia64_slfo_task->thread.last_fph_cpu = smp_processor_id(); \ | |
| 393 | − ia64_set_kr(IA64_KR_FPU_OWNER, (unsigned long) __ia64_slfo_task); \ | |
| 394 | −} while (0) | |
| 395 | − | |
| 396 | −/* Mark the fph partition of task T as being invalid on all CPUs. */ | |
| 397 | −#define ia64_drop_fpu(t) ((t)->thread.last_fph_cpu = -1) | |
| 398 | − | |
| 399 | −extern void __ia64_init_fpu (void); | |
| 400 | −extern void __ia64_save_fpu (struct ia64_fpreg *fph); | |
| 401 | −extern void __ia64_load_fpu (struct ia64_fpreg *fph); | |
| 402 | −extern void ia64_save_debug_regs (unsigned long *save_area); | |
| 403 | −extern void ia64_load_debug_regs (unsigned long *save_area); | |
| 404 | − | |
| 405 | −#define ia64_fph_enable() do { ia64_rsm(IA64_PSR_DFH); ia64_srlz_d(); } while (0) | |
| 406 | −#define ia64_fph_disable() do { ia64_ssm(IA64_PSR_DFH); ia64_srlz_d(); } while (0) | |
| 407 | − | |
| 408 | −/* load fp 0.0 into fph */ | |
| 409 | −static inline void | |
| 410 | −ia64_init_fpu (void) { | |
| 411 | − ia64_fph_enable(); | |
| 412 | − __ia64_init_fpu(); | |
| 413 | − ia64_fph_disable(); | |
| 414 | −} | |
| 415 | − | |
| 416 | −/* save f32-f127 at FPH */ | |
| 417 | −static inline void | |
| 418 | −ia64_save_fpu (struct ia64_fpreg *fph) { | |
| 419 | − ia64_fph_enable(); | |
| 420 | − __ia64_save_fpu(fph); | |
| 421 | − ia64_fph_disable(); | |
| 422 | −} | |
| 423 | − | |
| 424 | −/* load f32-f127 from FPH */ | |
| 425 | −static inline void | |
| 426 | −ia64_load_fpu (struct ia64_fpreg *fph) { | |
| 427 | − ia64_fph_enable(); | |
| 428 | − __ia64_load_fpu(fph); | |
| 429 | − ia64_fph_disable(); | |
| 430 | −} | |
| 431 | − | |
| 432 | −static inline __u64 | |
| 433 | −ia64_clear_ic (void) | |
| 434 | −{ | |
| 435 | − __u64 psr; | |
| 436 | − psr = ia64_getreg(_IA64_REG_PSR); | |
| 437 | − ia64_stop(); | |
| 438 | − ia64_rsm(IA64_PSR_I | IA64_PSR_IC); | |
| 439 | − ia64_srlz_i(); | |
| 440 | − return psr; | |
| 441 | −} | |
| 442 | − | |
| 443 | −/* | |
| 444 | − * Restore the psr. | |
| 445 | − */ | |
| 446 | −static inline void | |
| 447 | −ia64_set_psr (__u64 psr) | |
| 448 | −{ | |
| 449 | − ia64_stop(); | |
| 450 | − ia64_setreg(_IA64_REG_PSR_L, psr); | |
| 451 | − ia64_srlz_i(); | |
| 452 | −} | |
| 453 | − | |
| 454 | −/* | |
| 455 | − * Insert a translation into an instruction and/or data translation | |
| 456 | − * register. | |
| 457 | − */ | |
| 458 | −static inline void | |
| 459 | −ia64_itr (__u64 target_mask, __u64 tr_num, | |
| 460 | − __u64 vmaddr, __u64 pte, | |
| 461 | − __u64 log_page_size) | |
| 462 | −{ | |
| 463 | − ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2)); | |
| 464 | − ia64_setreg(_IA64_REG_CR_IFA, vmaddr); | |
| 465 | − ia64_stop(); | |
| 466 | − if (target_mask & 0x1) | |
| 467 | − ia64_itri(tr_num, pte); | |
| 468 | − if (target_mask & 0x2) | |
| 469 | − ia64_itrd(tr_num, pte); | |
| 470 | −} | |
| 471 | − | |
| 472 | −/* | |
| 473 | − * Insert a translation into the instruction and/or data translation | |
| 474 | − * cache. | |
| 475 | − */ | |
| 476 | −static inline void | |
| 477 | −ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte, | |
| 478 | − __u64 log_page_size) | |
| 479 | −{ | |
| 480 | − ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2)); | |
| 481 | − ia64_setreg(_IA64_REG_CR_IFA, vmaddr); | |
| 482 | − ia64_stop(); | |
| 483 | − /* as per EAS2.6, itc must be the last instruction in an instruction group */ | |
| 484 | − if (target_mask & 0x1) | |
| 485 | − ia64_itci(pte); | |
| 486 | − if (target_mask & 0x2) | |
| 487 | − ia64_itcd(pte); | |
| 488 | −} | |
| 489 | − | |
| 490 | −/* | |
| 491 | − * Purge a range of addresses from instruction and/or data translation | |
| 492 | − * register(s). | |
| 493 | − */ | |
| 494 | −static inline void | |
| 495 | −ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size) | |
| 496 | −{ | |
| 497 | − if (target_mask & 0x1) | |
| 498 | − ia64_ptri(vmaddr, (log_size << 2)); | |
| 499 | − if (target_mask & 0x2) | |
| 500 | − ia64_ptrd(vmaddr, (log_size << 2)); | |
| 501 | −} | |
| 502 | − | |
| 503 | −/* Set the interrupt vector address. The address must be suitably aligned (32KB). */ | |
| 504 | −static inline void | |
| 505 | −ia64_set_iva (void *ivt_addr) | |
| 506 | −{ | |
| 507 | − ia64_setreg(_IA64_REG_CR_IVA, (__u64) ivt_addr); | |
| 508 | − ia64_srlz_i(); | |
| 509 | −} | |
| 510 | − | |
| 511 | −/* Set the page table address and control bits. */ | |
| 512 | −static inline void | |
| 513 | −ia64_set_pta (__u64 pta) | |
| 514 | −{ | |
| 515 | − /* Note: srlz.i implies srlz.d */ | |
| 516 | − ia64_setreg(_IA64_REG_CR_PTA, pta); | |
| 517 | − ia64_srlz_i(); | |
| 518 | −} | |
| 519 | − | |
| 520 | −static inline void | |
| 521 | −ia64_eoi (void) | |
| 522 | −{ | |
| 523 | − ia64_setreg(_IA64_REG_CR_EOI, 0); | |
| 524 | − ia64_srlz_d(); | |
| 525 | −} | |
| 526 | − | |
| 527 | −#define cpu_relax() ia64_hint(ia64_hint_pause) | |
| 528 | − | |
| 529 | −static inline int | |
| 530 | −ia64_get_irr(unsigned int vector) | |
| 531 | −{ | |
| 532 | − unsigned int reg = vector / 64; | |
| 533 | − unsigned int bit = vector % 64; | |
| 534 | − unsigned long irr; | |
| 535 | − | |
| 536 | − switch (reg) { | |
| 537 | − case 0: irr = ia64_getreg(_IA64_REG_CR_IRR0); break; | |
| 538 | − case 1: irr = ia64_getreg(_IA64_REG_CR_IRR1); break; | |
| 539 | − case 2: irr = ia64_getreg(_IA64_REG_CR_IRR2); break; | |
| 540 | − case 3: irr = ia64_getreg(_IA64_REG_CR_IRR3); break; | |
| 541 | − } | |
| 542 | − | |
| 543 | − return test_bit(bit, &irr); | |
| 544 | −} | |
| 545 | − | |
| 546 | −static inline void | |
| 547 | −ia64_set_lrr0 (unsigned long val) | |
| 548 | −{ | |
| 549 | − ia64_setreg(_IA64_REG_CR_LRR0, val); | |
| 550 | − ia64_srlz_d(); | |
| 551 | −} | |
| 552 | − | |
| 553 | −static inline void | |
| 554 | −ia64_set_lrr1 (unsigned long val) | |
| 555 | −{ | |
| 556 | − ia64_setreg(_IA64_REG_CR_LRR1, val); | |
| 557 | − ia64_srlz_d(); | |
| 558 | −} | |
| 559 | − | |
| 560 | − | |
| 561 | −/* | |
| 562 | − * Given the address to which a spill occurred, return the unat bit | |
| 563 | − * number that corresponds to this address. | |
| 564 | − */ | |
| 565 | −static inline __u64 | |
| 566 | −ia64_unat_pos (void *spill_addr) | |
| 567 | −{ | |
| 568 | − return ((__u64) spill_addr >> 3) & 0x3f; | |
| 569 | −} | |
| 570 | − | |
| 571 | −/* | |
| 572 | − * Set the NaT bit of an integer register which was spilled at address | |
| 573 | − * SPILL_ADDR. UNAT is the mask to be updated. | |
| 574 | − */ | |
| 575 | −static inline void | |
| 576 | −ia64_set_unat (__u64 *unat, void *spill_addr, unsigned long nat) | |
| 577 | −{ | |
| 578 | − __u64 bit = ia64_unat_pos(spill_addr); | |
| 579 | − __u64 mask = 1UL << bit; | |
| 580 | − | |
| 581 | − *unat = (*unat & ~mask) | (nat << bit); | |
| 582 | −} | |
| 583 | − | |
| 584 | −static inline __u64 | |
| 585 | −ia64_get_ivr (void) | |
| 586 | −{ | |
| 587 | − __u64 r; | |
| 588 | − ia64_srlz_d(); | |
| 589 | − r = ia64_getreg(_IA64_REG_CR_IVR); | |
| 590 | − ia64_srlz_d(); | |
| 591 | − return r; | |
| 592 | −} | |
| 593 | − | |
| 594 | −static inline void | |
| 595 | −ia64_set_dbr (__u64 regnum, __u64 value) | |
| 596 | −{ | |
| 597 | − __ia64_set_dbr(regnum, value); | |
| 598 | −#ifdef CONFIG_ITANIUM | |
| 599 | − ia64_srlz_d(); | |
| 600 | −#endif | |
| 601 | −} | |
| 602 | − | |
| 603 | −static inline __u64 | |
| 604 | −ia64_get_dbr (__u64 regnum) | |
| 605 | −{ | |
| 606 | − __u64 retval; | |
| 607 | − | |
| 608 | − retval = __ia64_get_dbr(regnum); | |
| 609 | −#ifdef CONFIG_ITANIUM | |
| 610 | − ia64_srlz_d(); | |
| 611 | −#endif | |
| 612 | − return retval; | |
| 613 | −} | |
| 614 | − | |
| 615 | −static inline __u64 | |
| 616 | −ia64_rotr (__u64 w, __u64 n) | |
| 617 | −{ | |
| 618 | − return (w >> n) | (w << (64 - n)); | |
| 619 | −} | |
| 620 | − | |
| 621 | −#define ia64_rotl(w,n) ia64_rotr((w), (64) - (n)) | |
| 622 | − | |
| 623 | −/* | |
| 624 | − * Take a mapped kernel address and return the equivalent address | |
| 625 | − * in the region 7 identity mapped virtual area. | |
| 626 | − */ | |
| 627 | −static inline void * | |
| 628 | −ia64_imva (void *addr) | |
| 629 | −{ | |
| 630 | − void *result; | |
| 631 | − result = (void *) ia64_tpa(addr); | |
| 632 | − return __va(result); | |
| 633 | −} | |
| 634 | − | |
| 635 | −#define ARCH_HAS_PREFETCH | |
| 636 | −#define ARCH_HAS_PREFETCHW | |
| 637 | −#define PREFETCH_STRIDE L1_CACHE_BYTES | |
| 638 | − | |
| 639 | −static inline void | |
| 640 | −prefetch (const void *x) | |
| 641 | −{ | |
| 642 | − ia64_lfetch(ia64_lfhint_none, x); | |
| 643 | −} | |
| 644 | − | |
| 645 | −static inline void | |
| 646 | −prefetchw (const void *x) | |
| 647 | −{ | |
| 648 | − ia64_lfetch_excl(ia64_lfhint_none, x); | |
| 649 | −} | |
| 650 | − | |
| 651 | −extern unsigned long boot_option_idle_override; | |
| 652 | − | |
| 653 | −enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_FORCE_MWAIT, | |
| 654 | − IDLE_NOMWAIT, IDLE_POLL}; | |
| 655 | − | |
| 656 | −void default_idle(void); | |
| 657 | − | |
| 658 | −#endif /* !__ASSEMBLY__ */ | |
| 659 | − | |
| 660 | −#endif /* _ASM_IA64_PROCESSOR_H */ | |
| @@ -1,146 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −/* | |
| 3 | − * Copyright (C) 1998-2004 Hewlett-Packard Co | |
| 4 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 5 | − * Stephane Eranian <eranian@hpl.hp.com> | |
| 6 | − * Copyright (C) 2003 Intel Co | |
| 7 | − * Suresh Siddha <suresh.b.siddha@intel.com> | |
| 8 | − * Fenghua Yu <fenghua.yu@intel.com> | |
| 9 | − * Arun Sharma <arun.sharma@intel.com> | |
| 10 | − * | |
| 11 | − * 12/07/98 S. Eranian added pt_regs & switch_stack | |
| 12 | − * 12/21/98 D. Mosberger updated to match latest code | |
| 13 | − * 6/17/99 D. Mosberger added second unat member to "struct switch_stack" | |
| 14 | − * | |
| 15 | − */ | |
| 16 | −#ifndef _ASM_IA64_PTRACE_H | |
| 17 | −#define _ASM_IA64_PTRACE_H | |
| 18 | − | |
| 19 | −#ifndef ASM_OFFSETS_C | |
| 20 | −#include <asm/asm-offsets.h> | |
| 21 | −#endif | |
| 22 | −#include <uapi/asm/ptrace.h> | |
| 23 | − | |
| 24 | −/* | |
| 25 | − * Base-2 logarithm of number of pages to allocate per task structure | |
| 26 | − * (including register backing store and memory stack): | |
| 27 | − */ | |
| 28 | −#if defined(CONFIG_IA64_PAGE_SIZE_4KB) | |
| 29 | −# define KERNEL_STACK_SIZE_ORDER 3 | |
| 30 | −#elif defined(CONFIG_IA64_PAGE_SIZE_8KB) | |
| 31 | −# define KERNEL_STACK_SIZE_ORDER 2 | |
| 32 | −#elif defined(CONFIG_IA64_PAGE_SIZE_16KB) | |
| 33 | −# define KERNEL_STACK_SIZE_ORDER 1 | |
| 34 | −#else | |
| 35 | −# define KERNEL_STACK_SIZE_ORDER 0 | |
| 36 | −#endif | |
| 37 | − | |
| 38 | −#define IA64_RBS_OFFSET ((IA64_TASK_SIZE + IA64_THREAD_INFO_SIZE + 31) & ~31) | |
| 39 | −#define IA64_STK_OFFSET ((1 << KERNEL_STACK_SIZE_ORDER)*PAGE_SIZE) | |
| 40 | − | |
| 41 | −#define KERNEL_STACK_SIZE IA64_STK_OFFSET | |
| 42 | − | |
| 43 | −#ifndef __ASSEMBLY__ | |
| 44 | − | |
| 45 | −#include <asm/current.h> | |
| 46 | −#include <asm/page.h> | |
| 47 | − | |
| 48 | −/* | |
| 49 | − * We use the ia64_psr(regs)->ri to determine which of the three | |
| 50 | − * instructions in bundle (16 bytes) took the sample. Generate | |
| 51 | − * the canonical representation by adding to instruction pointer. | |
| 52 | − */ | |
| 53 | −# define instruction_pointer(regs) ((regs)->cr_iip + ia64_psr(regs)->ri) | |
| 54 | −# define instruction_pointer_set(regs, val) \ | |
| 55 | −({ \ | |
| 56 | − ia64_psr(regs)->ri = (val & 0xf); \ | |
| 57 | − regs->cr_iip = (val & ~0xfULL); \ | |
| 58 | −}) | |
| 59 | − | |
| 60 | −static inline unsigned long user_stack_pointer(struct pt_regs *regs) | |
| 61 | −{ | |
| 62 | − return regs->r12; | |
| 63 | −} | |
| 64 | − | |
| 65 | −static inline int is_syscall_success(struct pt_regs *regs) | |
| 66 | −{ | |
| 67 | − return regs->r10 != -1; | |
| 68 | −} | |
| 69 | − | |
| 70 | −static inline long regs_return_value(struct pt_regs *regs) | |
| 71 | −{ | |
| 72 | − if (is_syscall_success(regs)) | |
| 73 | − return regs->r8; | |
| 74 | − else | |
| 75 | − return -regs->r8; | |
| 76 | −} | |
| 77 | − | |
| 78 | −/* Conserve space in histogram by encoding slot bits in address | |
| 79 | − * bits 2 and 3 rather than bits 0 and 1. | |
| 80 | − */ | |
| 81 | −#define profile_pc(regs) \ | |
| 82 | −({ \ | |
| 83 | − unsigned long __ip = instruction_pointer(regs); \ | |
| 84 | − (__ip & ~3UL) + ((__ip & 3UL) << 2); \ | |
| 85 | −}) | |
| 86 | − | |
| 87 | − /* given a pointer to a task_struct, return the user's pt_regs */ | |
| 88 | −# define task_pt_regs(t) (((struct pt_regs *) ((char *) (t) + IA64_STK_OFFSET)) - 1) | |
| 89 | −# define ia64_psr(regs) ((struct ia64_psr *) &(regs)->cr_ipsr) | |
| 90 | −# define user_mode(regs) (((struct ia64_psr *) &(regs)->cr_ipsr)->cpl != 0) | |
| 91 | −# define user_stack(task,regs) ((long) regs - (long) task == IA64_STK_OFFSET - sizeof(*regs)) | |
| 92 | −# define fsys_mode(task,regs) \ | |
| 93 | − ({ \ | |
| 94 | − struct task_struct *_task = (task); \ | |
| 95 | − struct pt_regs *_regs = (regs); \ | |
| 96 | − !user_mode(_regs) && user_stack(_task, _regs); \ | |
| 97 | − }) | |
| 98 | − | |
| 99 | − /* | |
| 100 | − * System call handlers that, upon successful completion, need to return a negative value | |
| 101 | − * should call force_successful_syscall_return() right before returning. On architectures | |
| 102 | − * where the syscall convention provides for a separate error flag (e.g., alpha, ia64, | |
| 103 | − * ppc{,64}, sparc{,64}, possibly others), this macro can be used to ensure that the error | |
| 104 | − * flag will not get set. On architectures which do not support a separate error flag, | |
| 105 | − * the macro is a no-op and the spurious error condition needs to be filtered out by some | |
| 106 | − * other means (e.g., in user-level, by passing an extra argument to the syscall handler, | |
| 107 | − * or something along those lines). | |
| 108 | − * | |
| 109 | − * On ia64, we can clear the user's pt_regs->r8 to force a successful syscall. | |
| 110 | − */ | |
| 111 | −# define force_successful_syscall_return() (task_pt_regs(current)->r8 = 0) | |
| 112 | − | |
| 113 | − struct task_struct; /* forward decl */ | |
| 114 | − struct unw_frame_info; /* forward decl */ | |
| 115 | − | |
| 116 | − extern unsigned long ia64_get_user_rbs_end (struct task_struct *, struct pt_regs *, | |
| 117 | − unsigned long *); | |
| 118 | − extern long ia64_peek (struct task_struct *, struct switch_stack *, unsigned long, | |
| 119 | − unsigned long, long *); | |
| 120 | − extern long ia64_poke (struct task_struct *, struct switch_stack *, unsigned long, | |
| 121 | − unsigned long, long); | |
| 122 | − extern void ia64_flush_fph (struct task_struct *); | |
| 123 | − extern void ia64_sync_fph (struct task_struct *); | |
| 124 | − extern void ia64_sync_krbs(void); | |
| 125 | − extern long ia64_sync_user_rbs (struct task_struct *, struct switch_stack *, | |
| 126 | − unsigned long, unsigned long); | |
| 127 | − | |
| 128 | − /* get nat bits for scratch registers such that bit N==1 iff scratch register rN is a NaT */ | |
| 129 | − extern unsigned long ia64_get_scratch_nat_bits (struct pt_regs *pt, unsigned long scratch_unat); | |
| 130 | − /* put nat bits for scratch registers such that scratch register rN is a NaT iff bit N==1 */ | |
| 131 | − extern unsigned long ia64_put_scratch_nat_bits (struct pt_regs *pt, unsigned long nat); | |
| 132 | − | |
| 133 | − extern void ia64_increment_ip (struct pt_regs *pt); | |
| 134 | − extern void ia64_decrement_ip (struct pt_regs *pt); | |
| 135 | − | |
| 136 | − extern void ia64_ptrace_stop(void); | |
| 137 | − #define arch_ptrace_stop() \ | |
| 138 | − ia64_ptrace_stop() | |
| 139 | − #define arch_ptrace_stop_needed() \ | |
| 140 | − (!test_thread_flag(TIF_RESTORE_RSE)) | |
| 141 | − | |
| 142 | − #define arch_has_single_step() (1) | |
| 143 | − #define arch_has_block_step() (1) | |
| 144 | − | |
| 145 | −#endif /* !__ASSEMBLY__ */ | |
| 146 | −#endif /* _ASM_IA64_PTRACE_H */ | |
| @@ -1,919 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_SAL_H | |
| 3 | −#define _ASM_IA64_SAL_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * System Abstraction Layer definitions. | |
| 7 | − * | |
| 8 | − * This is based on version 2.5 of the manual "IA-64 System | |
| 9 | − * Abstraction Layer". | |
| 10 | − * | |
| 11 | − * Copyright (C) 2001 Intel | |
| 12 | − * Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com> | |
| 13 | − * Copyright (C) 2001 Fred Lewis <frederick.v.lewis@intel.com> | |
| 14 | − * Copyright (C) 1998, 1999, 2001, 2003 Hewlett-Packard Co | |
| 15 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 16 | − * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com> | |
| 17 | − * | |
| 18 | − * 02/01/04 J. Hall Updated Error Record Structures to conform to July 2001 | |
| 19 | − * revision of the SAL spec. | |
| 20 | − * 01/01/03 fvlewis Updated Error Record Structures to conform with Nov. 2000 | |
| 21 | − * revision of the SAL spec. | |
| 22 | − * 99/09/29 davidm Updated for SAL 2.6. | |
| 23 | − * 00/03/29 cfleck Updated SAL Error Logging info for processor (SAL 2.6) | |
| 24 | − * (plus examples of platform error info structures from smariset @ Intel) | |
| 25 | − */ | |
| 26 | − | |
| 27 | −#define IA64_SAL_PLATFORM_FEATURE_BUS_LOCK_BIT 0 | |
| 28 | −#define IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT_BIT 1 | |
| 29 | −#define IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT_BIT 2 | |
| 30 | −#define IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT_BIT 3 | |
| 31 | − | |
| 32 | −#define IA64_SAL_PLATFORM_FEATURE_BUS_LOCK (1<<IA64_SAL_PLATFORM_FEATURE_BUS_LOCK_BIT) | |
| 33 | −#define IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT (1<<IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT_BIT) | |
| 34 | −#define IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT (1<<IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT_BIT) | |
| 35 | −#define IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT (1<<IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT_BIT) | |
| 36 | − | |
| 37 | −#ifndef __ASSEMBLY__ | |
| 38 | − | |
| 39 | −#include <linux/bcd.h> | |
| 40 | −#include <linux/spinlock.h> | |
| 41 | −#include <linux/efi.h> | |
| 42 | − | |
| 43 | −#include <asm/pal.h> | |
| 44 | −#include <asm/fpu.h> | |
| 45 | − | |
| 46 | −extern unsigned long sal_systab_phys; | |
| 47 | −extern spinlock_t sal_lock; | |
| 48 | − | |
| 49 | −/* SAL spec _requires_ eight args for each call. */ | |
| 50 | −#define __IA64_FW_CALL(entry,result,a0,a1,a2,a3,a4,a5,a6,a7) \ | |
| 51 | − result = (*entry)(a0,a1,a2,a3,a4,a5,a6,a7) | |
| 52 | − | |
| 53 | −# define IA64_FW_CALL(entry,result,args...) do { \ | |
| 54 | − unsigned long __ia64_sc_flags; \ | |
| 55 | − struct ia64_fpreg __ia64_sc_fr[6]; \ | |
| 56 | − ia64_save_scratch_fpregs(__ia64_sc_fr); \ | |
| 57 | − spin_lock_irqsave(&sal_lock, __ia64_sc_flags); \ | |
| 58 | − __IA64_FW_CALL(entry, result, args); \ | |
| 59 | − spin_unlock_irqrestore(&sal_lock, __ia64_sc_flags); \ | |
| 60 | − ia64_load_scratch_fpregs(__ia64_sc_fr); \ | |
| 61 | −} while (0) | |
| 62 | − | |
| 63 | −# define SAL_CALL(result,args...) \ | |
| 64 | − IA64_FW_CALL(ia64_sal, result, args); | |
| 65 | − | |
| 66 | −# define SAL_CALL_NOLOCK(result,args...) do { \ | |
| 67 | − unsigned long __ia64_scn_flags; \ | |
| 68 | − struct ia64_fpreg __ia64_scn_fr[6]; \ | |
| 69 | − ia64_save_scratch_fpregs(__ia64_scn_fr); \ | |
| 70 | − local_irq_save(__ia64_scn_flags); \ | |
| 71 | − __IA64_FW_CALL(ia64_sal, result, args); \ | |
| 72 | − local_irq_restore(__ia64_scn_flags); \ | |
| 73 | − ia64_load_scratch_fpregs(__ia64_scn_fr); \ | |
| 74 | −} while (0) | |
| 75 | − | |
| 76 | −# define SAL_CALL_REENTRANT(result,args...) do { \ | |
| 77 | − struct ia64_fpreg __ia64_scs_fr[6]; \ | |
| 78 | − ia64_save_scratch_fpregs(__ia64_scs_fr); \ | |
| 79 | − preempt_disable(); \ | |
| 80 | − __IA64_FW_CALL(ia64_sal, result, args); \ | |
| 81 | − preempt_enable(); \ | |
| 82 | − ia64_load_scratch_fpregs(__ia64_scs_fr); \ | |
| 83 | −} while (0) | |
| 84 | − | |
| 85 | −#define SAL_SET_VECTORS 0x01000000 | |
| 86 | −#define SAL_GET_STATE_INFO 0x01000001 | |
| 87 | −#define SAL_GET_STATE_INFO_SIZE 0x01000002 | |
| 88 | −#define SAL_CLEAR_STATE_INFO 0x01000003 | |
| 89 | −#define SAL_MC_RENDEZ 0x01000004 | |
| 90 | −#define SAL_MC_SET_PARAMS 0x01000005 | |
| 91 | −#define SAL_REGISTER_PHYSICAL_ADDR 0x01000006 | |
| 92 | − | |
| 93 | −#define SAL_CACHE_FLUSH 0x01000008 | |
| 94 | −#define SAL_CACHE_INIT 0x01000009 | |
| 95 | −#define SAL_PCI_CONFIG_READ 0x01000010 | |
| 96 | −#define SAL_PCI_CONFIG_WRITE 0x01000011 | |
| 97 | −#define SAL_FREQ_BASE 0x01000012 | |
| 98 | −#define SAL_PHYSICAL_ID_INFO 0x01000013 | |
| 99 | − | |
| 100 | −#define SAL_UPDATE_PAL 0x01000020 | |
| 101 | − | |
| 102 | −struct ia64_sal_retval { | |
| 103 | − /* | |
| 104 | − * A zero status value indicates call completed without error. | |
| 105 | − * A negative status value indicates reason of call failure. | |
| 106 | − * A positive status value indicates success but an | |
| 107 | − * informational value should be printed (e.g., "reboot for | |
| 108 | − * change to take effect"). | |
| 109 | − */ | |
| 110 | − long status; | |
| 111 | − unsigned long v0; | |
| 112 | − unsigned long v1; | |
| 113 | − unsigned long v2; | |
| 114 | −}; | |
| 115 | − | |
| 116 | −typedef struct ia64_sal_retval (*ia64_sal_handler) (u64, ...); | |
| 117 | − | |
| 118 | −enum { | |
| 119 | − SAL_FREQ_BASE_PLATFORM = 0, | |
| 120 | − SAL_FREQ_BASE_INTERVAL_TIMER = 1, | |
| 121 | − SAL_FREQ_BASE_REALTIME_CLOCK = 2 | |
| 122 | −}; | |
| 123 | − | |
| 124 | −/* | |
| 125 | − * The SAL system table is followed by a variable number of variable | |
| 126 | − * length descriptors. The structure of these descriptors follows | |
| 127 | − * below. | |
| 128 | − * The defininition follows SAL specs from July 2000 | |
| 129 | − */ | |
| 130 | −struct ia64_sal_systab { | |
| 131 | − u8 signature[4]; /* should be "SST_" */ | |
| 132 | − u32 size; /* size of this table in bytes */ | |
| 133 | − u8 sal_rev_minor; | |
| 134 | − u8 sal_rev_major; | |
| 135 | − u16 entry_count; /* # of entries in variable portion */ | |
| 136 | − u8 checksum; | |
| 137 | − u8 reserved1[7]; | |
| 138 | − u8 sal_a_rev_minor; | |
| 139 | − u8 sal_a_rev_major; | |
| 140 | − u8 sal_b_rev_minor; | |
| 141 | − u8 sal_b_rev_major; | |
| 142 | − /* oem_id & product_id: terminating NUL is missing if string is exactly 32 bytes long. */ | |
| 143 | − u8 oem_id[32]; | |
| 144 | − u8 product_id[32]; /* ASCII product id */ | |
| 145 | − u8 reserved2[8]; | |
| 146 | −}; | |
| 147 | − | |
| 148 | −enum sal_systab_entry_type { | |
| 149 | − SAL_DESC_ENTRY_POINT = 0, | |
| 150 | − SAL_DESC_MEMORY = 1, | |
| 151 | − SAL_DESC_PLATFORM_FEATURE = 2, | |
| 152 | − SAL_DESC_TR = 3, | |
| 153 | − SAL_DESC_PTC = 4, | |
| 154 | − SAL_DESC_AP_WAKEUP = 5 | |
| 155 | −}; | |
| 156 | − | |
| 157 | −/* | |
| 158 | − * Entry type: Size: | |
| 159 | − * 0 48 | |
| 160 | − * 1 32 | |
| 161 | − * 2 16 | |
| 162 | − * 3 32 | |
| 163 | − * 4 16 | |
| 164 | − * 5 16 | |
| 165 | − */ | |
| 166 | −#define SAL_DESC_SIZE(type) "\060\040\020\040\020\020"[(unsigned) type] | |
| 167 | − | |
| 168 | −typedef struct ia64_sal_desc_entry_point { | |
| 169 | − u8 type; | |
| 170 | − u8 reserved1[7]; | |
| 171 | − u64 pal_proc; | |
| 172 | − u64 sal_proc; | |
| 173 | − u64 gp; | |
| 174 | − u8 reserved2[16]; | |
| 175 | −}ia64_sal_desc_entry_point_t; | |
| 176 | − | |
| 177 | −typedef struct ia64_sal_desc_memory { | |
| 178 | − u8 type; | |
| 179 | − u8 used_by_sal; /* needs to be mapped for SAL? */ | |
| 180 | − u8 mem_attr; /* current memory attribute setting */ | |
| 181 | − u8 access_rights; /* access rights set up by SAL */ | |
| 182 | − u8 mem_attr_mask; /* mask of supported memory attributes */ | |
| 183 | − u8 reserved1; | |
| 184 | − u8 mem_type; /* memory type */ | |
| 185 | − u8 mem_usage; /* memory usage */ | |
| 186 | − u64 addr; /* physical address of memory */ | |
| 187 | − u32 length; /* length (multiple of 4KB pages) */ | |
| 188 | − u32 reserved2; | |
| 189 | − u8 oem_reserved[8]; | |
| 190 | −} ia64_sal_desc_memory_t; | |
| 191 | − | |
| 192 | −typedef struct ia64_sal_desc_platform_feature { | |
| 193 | − u8 type; | |
| 194 | − u8 feature_mask; | |
| 195 | − u8 reserved1[14]; | |
| 196 | −} ia64_sal_desc_platform_feature_t; | |
| 197 | − | |
| 198 | −typedef struct ia64_sal_desc_tr { | |
| 199 | − u8 type; | |
| 200 | − u8 tr_type; /* 0 == instruction, 1 == data */ | |
| 201 | − u8 regnum; /* translation register number */ | |
| 202 | − u8 reserved1[5]; | |
| 203 | − u64 addr; /* virtual address of area covered */ | |
| 204 | − u64 page_size; /* encoded page size */ | |
| 205 | − u8 reserved2[8]; | |
| 206 | −} ia64_sal_desc_tr_t; | |
| 207 | − | |
| 208 | −typedef struct ia64_sal_desc_ptc { | |
| 209 | − u8 type; | |
| 210 | − u8 reserved1[3]; | |
| 211 | − u32 num_domains; /* # of coherence domains */ | |
| 212 | − u64 domain_info; /* physical address of domain info table */ | |
| 213 | −} ia64_sal_desc_ptc_t; | |
| 214 | − | |
| 215 | −typedef struct ia64_sal_ptc_domain_info { | |
| 216 | − u64 proc_count; /* number of processors in domain */ | |
| 217 | − u64 proc_list; /* physical address of LID array */ | |
| 218 | −} ia64_sal_ptc_domain_info_t; | |
| 219 | − | |
| 220 | −typedef struct ia64_sal_ptc_domain_proc_entry { | |
| 221 | − u64 id : 8; /* id of processor */ | |
| 222 | − u64 eid : 8; /* eid of processor */ | |
| 223 | −} ia64_sal_ptc_domain_proc_entry_t; | |
| 224 | − | |
| 225 | − | |
| 226 | −#define IA64_SAL_AP_EXTERNAL_INT 0 | |
| 227 | − | |
| 228 | −typedef struct ia64_sal_desc_ap_wakeup { | |
| 229 | − u8 type; | |
| 230 | − u8 mechanism; /* 0 == external interrupt */ | |
| 231 | − u8 reserved1[6]; | |
| 232 | − u64 vector; /* interrupt vector in range 0x10-0xff */ | |
| 233 | −} ia64_sal_desc_ap_wakeup_t ; | |
| 234 | − | |
| 235 | −extern ia64_sal_handler ia64_sal; | |
| 236 | −extern struct ia64_sal_desc_ptc *ia64_ptc_domain_info; | |
| 237 | − | |
| 238 | −extern unsigned short sal_revision; /* supported SAL spec revision */ | |
| 239 | −extern unsigned short sal_version; /* SAL version; OEM dependent */ | |
| 240 | −#define SAL_VERSION_CODE(major, minor) ((bin2bcd(major) << 8) | bin2bcd(minor)) | |
| 241 | − | |
| 242 | −extern const char *ia64_sal_strerror (long status); | |
| 243 | −extern void ia64_sal_init (struct ia64_sal_systab *sal_systab); | |
| 244 | − | |
| 245 | −/* SAL information type encodings */ | |
| 246 | −enum { | |
| 247 | − SAL_INFO_TYPE_MCA = 0, /* Machine check abort information */ | |
| 248 | − SAL_INFO_TYPE_INIT = 1, /* Init information */ | |
| 249 | − SAL_INFO_TYPE_CMC = 2, /* Corrected machine check information */ | |
| 250 | − SAL_INFO_TYPE_CPE = 3 /* Corrected platform error information */ | |
| 251 | −}; | |
| 252 | − | |
| 253 | −/* Encodings for machine check parameter types */ | |
| 254 | −enum { | |
| 255 | − SAL_MC_PARAM_RENDEZ_INT = 1, /* Rendezvous interrupt */ | |
| 256 | − SAL_MC_PARAM_RENDEZ_WAKEUP = 2, /* Wakeup */ | |
| 257 | − SAL_MC_PARAM_CPE_INT = 3 /* Corrected Platform Error Int */ | |
| 258 | −}; | |
| 259 | − | |
| 260 | −/* Encodings for rendezvous mechanisms */ | |
| 261 | −enum { | |
| 262 | − SAL_MC_PARAM_MECHANISM_INT = 1, /* Use interrupt */ | |
| 263 | − SAL_MC_PARAM_MECHANISM_MEM = 2 /* Use memory synchronization variable*/ | |
| 264 | −}; | |
| 265 | − | |
| 266 | −/* Encodings for vectors which can be registered by the OS with SAL */ | |
| 267 | −enum { | |
| 268 | − SAL_VECTOR_OS_MCA = 0, | |
| 269 | − SAL_VECTOR_OS_INIT = 1, | |
| 270 | − SAL_VECTOR_OS_BOOT_RENDEZ = 2 | |
| 271 | −}; | |
| 272 | − | |
| 273 | −/* Encodings for mca_opt parameter sent to SAL_MC_SET_PARAMS */ | |
| 274 | −#define SAL_MC_PARAM_RZ_ALWAYS 0x1 | |
| 275 | −#define SAL_MC_PARAM_BINIT_ESCALATE 0x10 | |
| 276 | − | |
| 277 | −/* | |
| 278 | − * Definition of the SAL Error Log from the SAL spec | |
| 279 | − */ | |
| 280 | − | |
| 281 | −/* SAL Error Record Section GUID Definitions */ | |
| 282 | −#define SAL_PROC_DEV_ERR_SECT_GUID \ | |
| 283 | − EFI_GUID(0xe429faf1, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81) | |
| 284 | −#define SAL_PLAT_MEM_DEV_ERR_SECT_GUID \ | |
| 285 | − EFI_GUID(0xe429faf2, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81) | |
| 286 | −#define SAL_PLAT_SEL_DEV_ERR_SECT_GUID \ | |
| 287 | − EFI_GUID(0xe429faf3, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81) | |
| 288 | −#define SAL_PLAT_PCI_BUS_ERR_SECT_GUID \ | |
| 289 | − EFI_GUID(0xe429faf4, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81) | |
| 290 | −#define SAL_PLAT_SMBIOS_DEV_ERR_SECT_GUID \ | |
| 291 | − EFI_GUID(0xe429faf5, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81) | |
| 292 | −#define SAL_PLAT_PCI_COMP_ERR_SECT_GUID \ | |
| 293 | − EFI_GUID(0xe429faf6, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81) | |
| 294 | −#define SAL_PLAT_SPECIFIC_ERR_SECT_GUID \ | |
| 295 | − EFI_GUID(0xe429faf7, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81) | |
| 296 | −#define SAL_PLAT_HOST_CTLR_ERR_SECT_GUID \ | |
| 297 | − EFI_GUID(0xe429faf8, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81) | |
| 298 | −#define SAL_PLAT_BUS_ERR_SECT_GUID \ | |
| 299 | − EFI_GUID(0xe429faf9, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81) | |
| 300 | −#define PROCESSOR_ABSTRACTION_LAYER_OVERWRITE_GUID \ | |
| 301 | − EFI_GUID(0x6cb0a200, 0x893a, 0x11da, 0x96, 0xd2, 0x0, 0x10, 0x83, 0xff, \ | |
| 302 | − 0xca, 0x4d) | |
| 303 | − | |
| 304 | −#define MAX_CACHE_ERRORS 6 | |
| 305 | −#define MAX_TLB_ERRORS 6 | |
| 306 | −#define MAX_BUS_ERRORS 1 | |
| 307 | − | |
| 308 | −/* Definition of version according to SAL spec for logging purposes */ | |
| 309 | −typedef struct sal_log_revision { | |
| 310 | − u8 minor; /* BCD (0..99) */ | |
| 311 | − u8 major; /* BCD (0..99) */ | |
| 312 | −} sal_log_revision_t; | |
| 313 | − | |
| 314 | −/* Definition of timestamp according to SAL spec for logging purposes */ | |
| 315 | −typedef struct sal_log_timestamp { | |
| 316 | − u8 slh_second; /* Second (0..59) */ | |
| 317 | − u8 slh_minute; /* Minute (0..59) */ | |
| 318 | − u8 slh_hour; /* Hour (0..23) */ | |
| 319 | − u8 slh_reserved; | |
| 320 | − u8 slh_day; /* Day (1..31) */ | |
| 321 | − u8 slh_month; /* Month (1..12) */ | |
| 322 | − u8 slh_year; /* Year (00..99) */ | |
| 323 | − u8 slh_century; /* Century (19, 20, 21, ...) */ | |
| 324 | −} sal_log_timestamp_t; | |
| 325 | − | |
| 326 | −/* Definition of log record header structures */ | |
| 327 | −typedef struct sal_log_record_header { | |
| 328 | − u64 id; /* Unique monotonically increasing ID */ | |
| 329 | − sal_log_revision_t revision; /* Major and Minor revision of header */ | |
| 330 | − u8 severity; /* Error Severity */ | |
| 331 | − u8 validation_bits; /* 0: platform_guid, 1: !timestamp */ | |
| 332 | − u32 len; /* Length of this error log in bytes */ | |
| 333 | − sal_log_timestamp_t timestamp; /* Timestamp */ | |
| 334 | − efi_guid_t platform_guid; /* Unique OEM Platform ID */ | |
| 335 | −} sal_log_record_header_t; | |
| 336 | − | |
| 337 | −#define sal_log_severity_recoverable 0 | |
| 338 | −#define sal_log_severity_fatal 1 | |
| 339 | −#define sal_log_severity_corrected 2 | |
| 340 | − | |
| 341 | −/* | |
| 342 | − * Error Recovery Info (ERI) bit decode. From SAL Spec section B.2.2 Table B-3 | |
| 343 | − * Error Section Error_Recovery_Info Field Definition. | |
| 344 | − */ | |
| 345 | −#define ERI_NOT_VALID 0x0 /* Error Recovery Field is not valid */ | |
| 346 | −#define ERI_NOT_ACCESSIBLE 0x30 /* Resource not accessible */ | |
| 347 | −#define ERI_CONTAINMENT_WARN 0x22 /* Corrupt data propagated */ | |
| 348 | −#define ERI_UNCORRECTED_ERROR 0x20 /* Uncorrected error */ | |
| 349 | −#define ERI_COMPONENT_RESET 0x24 /* Component must be reset */ | |
| 350 | −#define ERI_CORR_ERROR_LOG 0x21 /* Corrected error, needs logging */ | |
| 351 | −#define ERI_CORR_ERROR_THRESH 0x29 /* Corrected error threshold exceeded */ | |
| 352 | − | |
| 353 | −/* Definition of log section header structures */ | |
| 354 | −typedef struct sal_log_sec_header { | |
| 355 | − efi_guid_t guid; /* Unique Section ID */ | |
| 356 | − sal_log_revision_t revision; /* Major and Minor revision of Section */ | |
| 357 | − u8 error_recovery_info; /* Platform error recovery status */ | |
| 358 | − u8 reserved; | |
| 359 | − u32 len; /* Section length */ | |
| 360 | −} sal_log_section_hdr_t; | |
| 361 | − | |
| 362 | −typedef struct sal_log_mod_error_info { | |
| 363 | − struct { | |
| 364 | − u64 check_info : 1, | |
| 365 | − requestor_identifier : 1, | |
| 366 | − responder_identifier : 1, | |
| 367 | − target_identifier : 1, | |
| 368 | − precise_ip : 1, | |
| 369 | − reserved : 59; | |
| 370 | − } valid; | |
| 371 | − u64 check_info; | |
| 372 | − u64 requestor_identifier; | |
| 373 | − u64 responder_identifier; | |
| 374 | − u64 target_identifier; | |
| 375 | − u64 precise_ip; | |
| 376 | −} sal_log_mod_error_info_t; | |
| 377 | − | |
| 378 | −typedef struct sal_processor_static_info { | |
| 379 | − struct { | |
| 380 | − u64 minstate : 1, | |
| 381 | − br : 1, | |
| 382 | − cr : 1, | |
| 383 | − ar : 1, | |
| 384 | − rr : 1, | |
| 385 | − fr : 1, | |
| 386 | − reserved : 58; | |
| 387 | − } valid; | |
| 388 | − struct pal_min_state_area min_state_area; | |
| 389 | − u64 br[8]; | |
| 390 | − u64 cr[128]; | |
| 391 | − u64 ar[128]; | |
| 392 | − u64 rr[8]; | |
| 393 | − struct ia64_fpreg __attribute__ ((packed)) fr[128]; | |
| 394 | −} sal_processor_static_info_t; | |
| 395 | − | |
| 396 | −struct sal_cpuid_info { | |
| 397 | − u64 regs[5]; | |
| 398 | − u64 reserved; | |
| 399 | −}; | |
| 400 | − | |
| 401 | −typedef struct sal_log_processor_info { | |
| 402 | − sal_log_section_hdr_t header; | |
| 403 | − struct { | |
| 404 | − u64 proc_error_map : 1, | |
| 405 | − proc_state_param : 1, | |
| 406 | − proc_cr_lid : 1, | |
| 407 | − psi_static_struct : 1, | |
| 408 | − num_cache_check : 4, | |
| 409 | − num_tlb_check : 4, | |
| 410 | − num_bus_check : 4, | |
| 411 | − num_reg_file_check : 4, | |
| 412 | − num_ms_check : 4, | |
| 413 | − cpuid_info : 1, | |
| 414 | − reserved1 : 39; | |
| 415 | − } valid; | |
| 416 | − u64 proc_error_map; | |
| 417 | − u64 proc_state_parameter; | |
| 418 | − u64 proc_cr_lid; | |
| 419 | − /* | |
| 420 | − * The rest of this structure consists of variable-length arrays, which can't be | |
| 421 | − * expressed in C. | |
| 422 | − */ | |
| 423 | − sal_log_mod_error_info_t info[]; | |
| 424 | − /* | |
| 425 | − * This is what the rest looked like if C supported variable-length arrays: | |
| 426 | − * | |
| 427 | − * sal_log_mod_error_info_t cache_check_info[.valid.num_cache_check]; | |
| 428 | − * sal_log_mod_error_info_t tlb_check_info[.valid.num_tlb_check]; | |
| 429 | − * sal_log_mod_error_info_t bus_check_info[.valid.num_bus_check]; | |
| 430 | − * sal_log_mod_error_info_t reg_file_check_info[.valid.num_reg_file_check]; | |
| 431 | − * sal_log_mod_error_info_t ms_check_info[.valid.num_ms_check]; | |
| 432 | − * struct sal_cpuid_info cpuid_info; | |
| 433 | − * sal_processor_static_info_t processor_static_info; | |
| 434 | − */ | |
| 435 | −} sal_log_processor_info_t; | |
| 436 | − | |
| 437 | −/* Given a sal_log_processor_info_t pointer, return a pointer to the processor_static_info: */ | |
| 438 | −#define SAL_LPI_PSI_INFO(l) \ | |
| 439 | −({ sal_log_processor_info_t *_l = (l); \ | |
| 440 | − ((sal_processor_static_info_t *) \ | |
| 441 | − ((char *) _l->info + ((_l->valid.num_cache_check + _l->valid.num_tlb_check \ | |
| 442 | − + _l->valid.num_bus_check + _l->valid.num_reg_file_check \ | |
| 443 | − + _l->valid.num_ms_check) * sizeof(sal_log_mod_error_info_t) \ | |
| 444 | − + sizeof(struct sal_cpuid_info)))); \ | |
| 445 | −}) | |
| 446 | − | |
| 447 | −/* platform error log structures */ | |
| 448 | − | |
| 449 | −typedef struct sal_log_mem_dev_err_info { | |
| 450 | − sal_log_section_hdr_t header; | |
| 451 | − struct { | |
| 452 | − u64 error_status : 1, | |
| 453 | − physical_addr : 1, | |
| 454 | − addr_mask : 1, | |
| 455 | − node : 1, | |
| 456 | − card : 1, | |
| 457 | − module : 1, | |
| 458 | − bank : 1, | |
| 459 | − device : 1, | |
| 460 | − row : 1, | |
| 461 | − column : 1, | |
| 462 | − bit_position : 1, | |
| 463 | − requestor_id : 1, | |
| 464 | − responder_id : 1, | |
| 465 | − target_id : 1, | |
| 466 | − bus_spec_data : 1, | |
| 467 | − oem_id : 1, | |
| 468 | − oem_data : 1, | |
| 469 | − reserved : 47; | |
| 470 | − } valid; | |
| 471 | − u64 error_status; | |
| 472 | − u64 physical_addr; | |
| 473 | − u64 addr_mask; | |
| 474 | − u16 node; | |
| 475 | − u16 card; | |
| 476 | − u16 module; | |
| 477 | − u16 bank; | |
| 478 | − u16 device; | |
| 479 | − u16 row; | |
| 480 | − u16 column; | |
| 481 | − u16 bit_position; | |
| 482 | − u64 requestor_id; | |
| 483 | − u64 responder_id; | |
| 484 | − u64 target_id; | |
| 485 | − u64 bus_spec_data; | |
| 486 | − u8 oem_id[16]; | |
| 487 | − u8 oem_data[1]; /* Variable length data */ | |
| 488 | −} sal_log_mem_dev_err_info_t; | |
| 489 | − | |
| 490 | −typedef struct sal_log_sel_dev_err_info { | |
| 491 | − sal_log_section_hdr_t header; | |
| 492 | − struct { | |
| 493 | − u64 record_id : 1, | |
| 494 | − record_type : 1, | |
| 495 | − generator_id : 1, | |
| 496 | − evm_rev : 1, | |
| 497 | − sensor_type : 1, | |
| 498 | − sensor_num : 1, | |
| 499 | − event_dir : 1, | |
| 500 | − event_data1 : 1, | |
| 501 | − event_data2 : 1, | |
| 502 | − event_data3 : 1, | |
| 503 | − reserved : 54; | |
| 504 | − } valid; | |
| 505 | − u16 record_id; | |
| 506 | − u8 record_type; | |
| 507 | − u8 timestamp[4]; | |
| 508 | − u16 generator_id; | |
| 509 | − u8 evm_rev; | |
| 510 | − u8 sensor_type; | |
| 511 | − u8 sensor_num; | |
| 512 | − u8 event_dir; | |
| 513 | − u8 event_data1; | |
| 514 | − u8 event_data2; | |
| 515 | − u8 event_data3; | |
| 516 | −} sal_log_sel_dev_err_info_t; | |
| 517 | − | |
| 518 | −typedef struct sal_log_pci_bus_err_info { | |
| 519 | − sal_log_section_hdr_t header; | |
| 520 | − struct { | |
| 521 | − u64 err_status : 1, | |
| 522 | − err_type : 1, | |
| 523 | − bus_id : 1, | |
| 524 | − bus_address : 1, | |
| 525 | − bus_data : 1, | |
| 526 | − bus_cmd : 1, | |
| 527 | − requestor_id : 1, | |
| 528 | − responder_id : 1, | |
| 529 | − target_id : 1, | |
| 530 | − oem_data : 1, | |
| 531 | − reserved : 54; | |
| 532 | − } valid; | |
| 533 | − u64 err_status; | |
| 534 | − u16 err_type; | |
| 535 | − u16 bus_id; | |
| 536 | − u32 reserved; | |
| 537 | − u64 bus_address; | |
| 538 | − u64 bus_data; | |
| 539 | − u64 bus_cmd; | |
| 540 | − u64 requestor_id; | |
| 541 | − u64 responder_id; | |
| 542 | − u64 target_id; | |
| 543 | − u8 oem_data[1]; /* Variable length data */ | |
| 544 | −} sal_log_pci_bus_err_info_t; | |
| 545 | − | |
| 546 | −typedef struct sal_log_smbios_dev_err_info { | |
| 547 | − sal_log_section_hdr_t header; | |
| 548 | − struct { | |
| 549 | − u64 event_type : 1, | |
| 550 | − length : 1, | |
| 551 | − time_stamp : 1, | |
| 552 | − data : 1, | |
| 553 | − reserved1 : 60; | |
| 554 | − } valid; | |
| 555 | − u8 event_type; | |
| 556 | − u8 length; | |
| 557 | − u8 time_stamp[6]; | |
| 558 | − u8 data[1]; /* data of variable length, length == slsmb_length */ | |
| 559 | −} sal_log_smbios_dev_err_info_t; | |
| 560 | − | |
| 561 | −typedef struct sal_log_pci_comp_err_info { | |
| 562 | − sal_log_section_hdr_t header; | |
| 563 | − struct { | |
| 564 | − u64 err_status : 1, | |
| 565 | − comp_info : 1, | |
| 566 | − num_mem_regs : 1, | |
| 567 | − num_io_regs : 1, | |
| 568 | − reg_data_pairs : 1, | |
| 569 | − oem_data : 1, | |
| 570 | − reserved : 58; | |
| 571 | − } valid; | |
| 572 | − u64 err_status; | |
| 573 | − struct { | |
| 574 | − u16 vendor_id; | |
| 575 | − u16 device_id; | |
| 576 | − u8 class_code[3]; | |
| 577 | − u8 func_num; | |
| 578 | − u8 dev_num; | |
| 579 | − u8 bus_num; | |
| 580 | − u8 seg_num; | |
| 581 | − u8 reserved[5]; | |
| 582 | − } comp_info; | |
| 583 | − u32 num_mem_regs; | |
| 584 | − u32 num_io_regs; | |
| 585 | − u64 reg_data_pairs[1]; | |
| 586 | − /* | |
| 587 | − * array of address/data register pairs is num_mem_regs + num_io_regs elements | |
| 588 | − * long. Each array element consists of a u64 address followed by a u64 data | |
| 589 | − * value. The oem_data array immediately follows the reg_data_pairs array | |
| 590 | − */ | |
| 591 | − u8 oem_data[1]; /* Variable length data */ | |
| 592 | −} sal_log_pci_comp_err_info_t; | |
| 593 | − | |
| 594 | −typedef struct sal_log_plat_specific_err_info { | |
| 595 | − sal_log_section_hdr_t header; | |
| 596 | − struct { | |
| 597 | − u64 err_status : 1, | |
| 598 | − guid : 1, | |
| 599 | − oem_data : 1, | |
| 600 | − reserved : 61; | |
| 601 | − } valid; | |
| 602 | − u64 err_status; | |
| 603 | − efi_guid_t guid; | |
| 604 | − u8 oem_data[1]; /* platform specific variable length data */ | |
| 605 | −} sal_log_plat_specific_err_info_t; | |
| 606 | − | |
| 607 | −typedef struct sal_log_host_ctlr_err_info { | |
| 608 | − sal_log_section_hdr_t header; | |
| 609 | − struct { | |
| 610 | − u64 err_status : 1, | |
| 611 | − requestor_id : 1, | |
| 612 | − responder_id : 1, | |
| 613 | − target_id : 1, | |
| 614 | − bus_spec_data : 1, | |
| 615 | − oem_data : 1, | |
| 616 | − reserved : 58; | |
| 617 | − } valid; | |
| 618 | − u64 err_status; | |
| 619 | − u64 requestor_id; | |
| 620 | − u64 responder_id; | |
| 621 | − u64 target_id; | |
| 622 | − u64 bus_spec_data; | |
| 623 | − u8 oem_data[1]; /* Variable length OEM data */ | |
| 624 | −} sal_log_host_ctlr_err_info_t; | |
| 625 | − | |
| 626 | −typedef struct sal_log_plat_bus_err_info { | |
| 627 | − sal_log_section_hdr_t header; | |
| 628 | − struct { | |
| 629 | − u64 err_status : 1, | |
| 630 | − requestor_id : 1, | |
| 631 | − responder_id : 1, | |
| 632 | − target_id : 1, | |
| 633 | − bus_spec_data : 1, | |
| 634 | − oem_data : 1, | |
| 635 | − reserved : 58; | |
| 636 | − } valid; | |
| 637 | − u64 err_status; | |
| 638 | − u64 requestor_id; | |
| 639 | − u64 responder_id; | |
| 640 | − u64 target_id; | |
| 641 | − u64 bus_spec_data; | |
| 642 | − u8 oem_data[1]; /* Variable length OEM data */ | |
| 643 | −} sal_log_plat_bus_err_info_t; | |
| 644 | − | |
| 645 | −/* Overall platform error section structure */ | |
| 646 | −typedef union sal_log_platform_err_info { | |
| 647 | − sal_log_mem_dev_err_info_t mem_dev_err; | |
| 648 | − sal_log_sel_dev_err_info_t sel_dev_err; | |
| 649 | − sal_log_pci_bus_err_info_t pci_bus_err; | |
| 650 | − sal_log_smbios_dev_err_info_t smbios_dev_err; | |
| 651 | − sal_log_pci_comp_err_info_t pci_comp_err; | |
| 652 | − sal_log_plat_specific_err_info_t plat_specific_err; | |
| 653 | − sal_log_host_ctlr_err_info_t host_ctlr_err; | |
| 654 | − sal_log_plat_bus_err_info_t plat_bus_err; | |
| 655 | −} sal_log_platform_err_info_t; | |
| 656 | − | |
| 657 | −/* SAL log over-all, multi-section error record structure (processor+platform) */ | |
| 658 | −typedef struct err_rec { | |
| 659 | − sal_log_record_header_t sal_elog_header; | |
| 660 | − sal_log_processor_info_t proc_err; | |
| 661 | − sal_log_platform_err_info_t plat_err; | |
| 662 | − u8 oem_data_pad[1024]; | |
| 663 | −} ia64_err_rec_t; | |
| 664 | − | |
| 665 | −/* | |
| 666 | − * Now define a couple of inline functions for improved type checking | |
| 667 | − * and convenience. | |
| 668 | − */ | |
| 669 | − | |
| 670 | −extern s64 ia64_sal_cache_flush (u64 cache_type); | |
| 671 | −extern void __init check_sal_cache_flush (void); | |
| 672 | − | |
| 673 | −/* Initialize all the processor and platform level instruction and data caches */ | |
| 674 | −static inline s64 | |
| 675 | −ia64_sal_cache_init (void) | |
| 676 | −{ | |
| 677 | − struct ia64_sal_retval isrv; | |
| 678 | − SAL_CALL(isrv, SAL_CACHE_INIT, 0, 0, 0, 0, 0, 0, 0); | |
| 679 | − return isrv.status; | |
| 680 | −} | |
| 681 | − | |
| 682 | −/* | |
| 683 | − * Clear the processor and platform information logged by SAL with respect to the machine | |
| 684 | − * state at the time of MCA's, INITs, CMCs, or CPEs. | |
| 685 | − */ | |
| 686 | −static inline s64 | |
| 687 | −ia64_sal_clear_state_info (u64 sal_info_type) | |
| 688 | −{ | |
| 689 | − struct ia64_sal_retval isrv; | |
| 690 | − SAL_CALL_REENTRANT(isrv, SAL_CLEAR_STATE_INFO, sal_info_type, 0, | |
| 691 | − 0, 0, 0, 0, 0); | |
| 692 | − return isrv.status; | |
| 693 | −} | |
| 694 | − | |
| 695 | − | |
| 696 | −/* Get the processor and platform information logged by SAL with respect to the machine | |
| 697 | − * state at the time of the MCAs, INITs, CMCs, or CPEs. | |
| 698 | − */ | |
| 699 | −static inline u64 | |
| 700 | −ia64_sal_get_state_info (u64 sal_info_type, u64 *sal_info) | |
| 701 | −{ | |
| 702 | − struct ia64_sal_retval isrv; | |
| 703 | − SAL_CALL_REENTRANT(isrv, SAL_GET_STATE_INFO, sal_info_type, 0, | |
| 704 | − sal_info, 0, 0, 0, 0); | |
| 705 | − if (isrv.status) | |
| 706 | − return 0; | |
| 707 | − | |
| 708 | − return isrv.v0; | |
| 709 | −} | |
| 710 | − | |
| 711 | −/* | |
| 712 | − * Get the maximum size of the information logged by SAL with respect to the machine state | |
| 713 | − * at the time of MCAs, INITs, CMCs, or CPEs. | |
| 714 | − */ | |
| 715 | −static inline u64 | |
| 716 | −ia64_sal_get_state_info_size (u64 sal_info_type) | |
| 717 | −{ | |
| 718 | − struct ia64_sal_retval isrv; | |
| 719 | − SAL_CALL_REENTRANT(isrv, SAL_GET_STATE_INFO_SIZE, sal_info_type, 0, | |
| 720 | − 0, 0, 0, 0, 0); | |
| 721 | − if (isrv.status) | |
| 722 | − return 0; | |
| 723 | − return isrv.v0; | |
| 724 | −} | |
| 725 | − | |
| 726 | −/* | |
| 727 | − * Causes the processor to go into a spin loop within SAL where SAL awaits a wakeup from | |
| 728 | − * the monarch processor. Must not lock, because it will not return on any cpu until the | |
| 729 | − * monarch processor sends a wake up. | |
| 730 | − */ | |
| 731 | −static inline s64 | |
| 732 | −ia64_sal_mc_rendez (void) | |
| 733 | −{ | |
| 734 | − struct ia64_sal_retval isrv; | |
| 735 | − SAL_CALL_NOLOCK(isrv, SAL_MC_RENDEZ, 0, 0, 0, 0, 0, 0, 0); | |
| 736 | − return isrv.status; | |
| 737 | −} | |
| 738 | − | |
| 739 | −/* | |
| 740 | − * Allow the OS to specify the interrupt number to be used by SAL to interrupt OS during | |
| 741 | − * the machine check rendezvous sequence as well as the mechanism to wake up the | |
| 742 | − * non-monarch processor at the end of machine check processing. | |
| 743 | − * Returns the complete ia64_sal_retval because some calls return more than just a status | |
| 744 | − * value. | |
| 745 | − */ | |
| 746 | −static inline struct ia64_sal_retval | |
| 747 | −ia64_sal_mc_set_params (u64 param_type, u64 i_or_m, u64 i_or_m_val, u64 timeout, u64 rz_always) | |
| 748 | −{ | |
| 749 | − struct ia64_sal_retval isrv; | |
| 750 | − SAL_CALL(isrv, SAL_MC_SET_PARAMS, param_type, i_or_m, i_or_m_val, | |
| 751 | − timeout, rz_always, 0, 0); | |
| 752 | − return isrv; | |
| 753 | −} | |
| 754 | − | |
| 755 | −/* Read from PCI configuration space */ | |
| 756 | −static inline s64 | |
| 757 | −ia64_sal_pci_config_read (u64 pci_config_addr, int type, u64 size, u64 *value) | |
| 758 | −{ | |
| 759 | − struct ia64_sal_retval isrv; | |
| 760 | − SAL_CALL(isrv, SAL_PCI_CONFIG_READ, pci_config_addr, size, type, 0, 0, 0, 0); | |
| 761 | − if (value) | |
| 762 | − *value = isrv.v0; | |
| 763 | − return isrv.status; | |
| 764 | −} | |
| 765 | − | |
| 766 | −/* Write to PCI configuration space */ | |
| 767 | −static inline s64 | |
| 768 | −ia64_sal_pci_config_write (u64 pci_config_addr, int type, u64 size, u64 value) | |
| 769 | −{ | |
| 770 | − struct ia64_sal_retval isrv; | |
| 771 | − SAL_CALL(isrv, SAL_PCI_CONFIG_WRITE, pci_config_addr, size, value, | |
| 772 | − type, 0, 0, 0); | |
| 773 | − return isrv.status; | |
| 774 | −} | |
| 775 | − | |
| 776 | −/* | |
| 777 | − * Register physical addresses of locations needed by SAL when SAL procedures are invoked | |
| 778 | − * in virtual mode. | |
| 779 | − */ | |
| 780 | −static inline s64 | |
| 781 | −ia64_sal_register_physical_addr (u64 phys_entry, u64 phys_addr) | |
| 782 | −{ | |
| 783 | − struct ia64_sal_retval isrv; | |
| 784 | − SAL_CALL(isrv, SAL_REGISTER_PHYSICAL_ADDR, phys_entry, phys_addr, | |
| 785 | − 0, 0, 0, 0, 0); | |
| 786 | − return isrv.status; | |
| 787 | −} | |
| 788 | − | |
| 789 | −/* | |
| 790 | − * Register software dependent code locations within SAL. These locations are handlers or | |
| 791 | − * entry points where SAL will pass control for the specified event. These event handlers | |
| 792 | − * are for the bott rendezvous, MCAs and INIT scenarios. | |
| 793 | − */ | |
| 794 | −static inline s64 | |
| 795 | −ia64_sal_set_vectors (u64 vector_type, | |
| 796 | − u64 handler_addr1, u64 gp1, u64 handler_len1, | |
| 797 | − u64 handler_addr2, u64 gp2, u64 handler_len2) | |
| 798 | −{ | |
| 799 | − struct ia64_sal_retval isrv; | |
| 800 | − SAL_CALL(isrv, SAL_SET_VECTORS, vector_type, | |
| 801 | − handler_addr1, gp1, handler_len1, | |
| 802 | − handler_addr2, gp2, handler_len2); | |
| 803 | − | |
| 804 | − return isrv.status; | |
| 805 | −} | |
| 806 | − | |
| 807 | −/* Update the contents of PAL block in the non-volatile storage device */ | |
| 808 | −static inline s64 | |
| 809 | −ia64_sal_update_pal (u64 param_buf, u64 scratch_buf, u64 scratch_buf_size, | |
| 810 | − u64 *error_code, u64 *scratch_buf_size_needed) | |
| 811 | −{ | |
| 812 | − struct ia64_sal_retval isrv; | |
| 813 | − SAL_CALL(isrv, SAL_UPDATE_PAL, param_buf, scratch_buf, scratch_buf_size, | |
| 814 | − 0, 0, 0, 0); | |
| 815 | − if (error_code) | |
| 816 | − *error_code = isrv.v0; | |
| 817 | − if (scratch_buf_size_needed) | |
| 818 | − *scratch_buf_size_needed = isrv.v1; | |
| 819 | − return isrv.status; | |
| 820 | −} | |
| 821 | − | |
| 822 | −/* Get physical processor die mapping in the platform. */ | |
| 823 | −static inline s64 | |
| 824 | −ia64_sal_physical_id_info(u16 *splid) | |
| 825 | −{ | |
| 826 | − struct ia64_sal_retval isrv; | |
| 827 | − | |
| 828 | − if (sal_revision < SAL_VERSION_CODE(3,2)) | |
| 829 | − return -1; | |
| 830 | − | |
| 831 | − SAL_CALL(isrv, SAL_PHYSICAL_ID_INFO, 0, 0, 0, 0, 0, 0, 0); | |
| 832 | − if (splid) | |
| 833 | − *splid = isrv.v0; | |
| 834 | − return isrv.status; | |
| 835 | −} | |
| 836 | − | |
| 837 | −extern unsigned long sal_platform_features; | |
| 838 | − | |
| 839 | −extern int (*salinfo_platform_oemdata)(const u8 *, u8 **, u64 *); | |
| 840 | − | |
| 841 | −struct sal_ret_values { | |
| 842 | − long r8; long r9; long r10; long r11; | |
| 843 | −}; | |
| 844 | − | |
| 845 | −#define IA64_SAL_OEMFUNC_MIN 0x02000000 | |
| 846 | −#define IA64_SAL_OEMFUNC_MAX 0x03ffffff | |
| 847 | − | |
| 848 | −extern int ia64_sal_oemcall(struct ia64_sal_retval *, u64, u64, u64, u64, u64, | |
| 849 | − u64, u64, u64); | |
| 850 | −extern int ia64_sal_oemcall_nolock(struct ia64_sal_retval *, u64, u64, u64, | |
| 851 | − u64, u64, u64, u64, u64); | |
| 852 | −extern int ia64_sal_oemcall_reentrant(struct ia64_sal_retval *, u64, u64, u64, | |
| 853 | − u64, u64, u64, u64, u64); | |
| 854 | −extern long | |
| 855 | −ia64_sal_freq_base (unsigned long which, unsigned long *ticks_per_second, | |
| 856 | − unsigned long *drift_info); | |
| 857 | −#ifdef CONFIG_HOTPLUG_CPU | |
| 858 | −/* | |
| 859 | − * System Abstraction Layer Specification | |
| 860 | − * Section 3.2.5.1: OS_BOOT_RENDEZ to SAL return State. | |
| 861 | − * Note: region regs are stored first in head.S _start. Hence they must | |
| 862 | − * stay up front. | |
| 863 | − */ | |
| 864 | −struct sal_to_os_boot { | |
| 865 | − u64 rr[8]; /* Region Registers */ | |
| 866 | − u64 br[6]; /* br0: | |
| 867 | − * return addr into SAL boot rendez routine */ | |
| 868 | − u64 gr1; /* SAL:GP */ | |
| 869 | − u64 gr12; /* SAL:SP */ | |
| 870 | − u64 gr13; /* SAL: Task Pointer */ | |
| 871 | − u64 fpsr; | |
| 872 | − u64 pfs; | |
| 873 | − u64 rnat; | |
| 874 | − u64 unat; | |
| 875 | − u64 bspstore; | |
| 876 | − u64 dcr; /* Default Control Register */ | |
| 877 | − u64 iva; | |
| 878 | − u64 pta; | |
| 879 | − u64 itv; | |
| 880 | − u64 pmv; | |
| 881 | − u64 cmcv; | |
| 882 | − u64 lrr[2]; | |
| 883 | − u64 gr[4]; | |
| 884 | − u64 pr; /* Predicate registers */ | |
| 885 | − u64 lc; /* Loop Count */ | |
| 886 | − struct ia64_fpreg fp[20]; | |
| 887 | −}; | |
| 888 | − | |
| 889 | −/* | |
| 890 | − * Global array allocated for NR_CPUS at boot time | |
| 891 | − */ | |
| 892 | −extern struct sal_to_os_boot sal_boot_rendez_state[NR_CPUS]; | |
| 893 | − | |
| 894 | −extern void ia64_jump_to_sal(struct sal_to_os_boot *); | |
| 895 | −#endif | |
| 896 | − | |
| 897 | −extern void ia64_sal_handler_init(void *entry_point, void *gpval); | |
| 898 | − | |
| 899 | −#define PALO_MAX_TLB_PURGES 0xFFFF | |
| 900 | −#define PALO_SIG "PALO" | |
| 901 | − | |
| 902 | −struct palo_table { | |
| 903 | − u8 signature[4]; /* Should be "PALO" */ | |
| 904 | − u32 length; | |
| 905 | − u8 minor_revision; | |
| 906 | − u8 major_revision; | |
| 907 | − u8 checksum; | |
| 908 | − u8 reserved1[5]; | |
| 909 | − u16 max_tlb_purges; | |
| 910 | − u8 reserved2[6]; | |
| 911 | −}; | |
| 912 | − | |
| 913 | −#define NPTCG_FROM_PAL 0 | |
| 914 | −#define NPTCG_FROM_PALO 1 | |
| 915 | −#define NPTCG_FROM_KERNEL_PARAMETER 2 | |
| 916 | − | |
| 917 | −#endif /* __ASSEMBLY__ */ | |
| 918 | − | |
| 919 | −#endif /* _ASM_IA64_SAL_H */ | |
| @@ -1,33 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_SECTIONS_H | |
| 3 | −#define _ASM_IA64_SECTIONS_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Copyright (C) 1998-2003 Hewlett-Packard Co | |
| 7 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 8 | − */ | |
| 9 | − | |
| 10 | −#include <linux/elf.h> | |
| 11 | −#include <linux/uaccess.h> | |
| 12 | − | |
| 13 | −typedef struct fdesc func_desc_t; | |
| 14 | − | |
| 15 | −#include <asm-generic/sections.h> | |
| 16 | − | |
| 17 | −extern char __phys_per_cpu_start[]; | |
| 18 | −#ifdef CONFIG_SMP | |
| 19 | −extern char __cpu0_per_cpu[]; | |
| 20 | −#endif | |
| 21 | −extern char __start___vtop_patchlist[], __end___vtop_patchlist[]; | |
| 22 | −extern char __start___rse_patchlist[], __end___rse_patchlist[]; | |
| 23 | −extern char __start___mckinley_e9_bundles[], __end___mckinley_e9_bundles[]; | |
| 24 | −extern char __start___phys_stack_reg_patchlist[], __end___phys_stack_reg_patchlist[]; | |
| 25 | −extern char __start_gate_section[]; | |
| 26 | −extern char __start_gate_mckinley_e9_patchlist[], __end_gate_mckinley_e9_patchlist[]; | |
| 27 | −extern char __start_gate_vtop_patchlist[], __end_gate_vtop_patchlist[]; | |
| 28 | −extern char __start_gate_fsyscall_patchlist[], __end_gate_fsyscall_patchlist[]; | |
| 29 | −extern char __start_gate_brl_fsys_bubble_down_patchlist[], __end_gate_brl_fsys_bubble_down_patchlist[]; | |
| 30 | −extern char __start_unwind[], __end_unwind[]; | |
| 31 | −extern char __start_ivt_text[], __end_ivt_text[]; | |
| 32 | − | |
| 33 | −#endif /* _ASM_IA64_SECTIONS_H */ | |
| @@ -1,17 +0,0 @@ | ||
| 1 | −/* | |
| 2 | − * Derived from the i386 version. | |
| 3 | − */ | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * This assumes you have a 1.8432 MHz clock for your UART. | |
| 7 | − * | |
| 8 | − * It'd be nice if someone built a serial card with a 24.576 MHz | |
| 9 | − * clock, since the 16550A is capable of handling a top speed of 1.5 | |
| 10 | − * megabits/second; but this requires the faster clock. | |
| 11 | − */ | |
| 12 | −#define BASE_BAUD ( 1843200 / 16 ) | |
| 13 | − | |
| 14 | −/* | |
| 15 | − * All legacy serial ports should be enumerated via ACPI namespace, so | |
| 16 | − * we need not list them here. | |
| 17 | − */ | |
| @@ -1,13 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_SHMPARAM_H | |
| 3 | −#define _ASM_IA64_SHMPARAM_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * SHMLBA controls minimum alignment at which shared memory segments | |
| 7 | − * get attached. The IA-64 architecture says that there may be a | |
| 8 | − * performance degradation when there are virtual aliases within 1MB. | |
| 9 | − * To reduce the chance of this, we set SHMLBA to 1MB. --davidm 00/12/20 | |
| 10 | − */ | |
| 11 | −#define SHMLBA (1024*1024) | |
| 12 | − | |
| 13 | −#endif /* _ASM_IA64_SHMPARAM_H */ | |
| @@ -1,33 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −/* | |
| 3 | − * Modified 1998-2001, 2003 | |
| 4 | − * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co | |
| 5 | − * | |
| 6 | − * Unfortunately, this file is being included by bits/signal.h in | |
| 7 | − * glibc-2.x. Hence the #ifdef __KERNEL__ ugliness. | |
| 8 | − */ | |
| 9 | −#ifndef _ASM_IA64_SIGNAL_H | |
| 10 | −#define _ASM_IA64_SIGNAL_H | |
| 11 | − | |
| 12 | −#include <uapi/asm/signal.h> | |
| 13 | − | |
| 14 | − | |
| 15 | −#define _NSIG 64 | |
| 16 | −#define _NSIG_BPW 64 | |
| 17 | −#define _NSIG_WORDS (_NSIG / _NSIG_BPW) | |
| 18 | − | |
| 19 | −# ifndef __ASSEMBLY__ | |
| 20 | − | |
| 21 | −/* Most things should be clean enough to redefine this at will, if care | |
| 22 | − is taken to make libc match. */ | |
| 23 | − | |
| 24 | −typedef unsigned long old_sigset_t; | |
| 25 | − | |
| 26 | −typedef struct { | |
| 27 | − unsigned long sig[_NSIG_WORDS]; | |
| 28 | −} sigset_t; | |
| 29 | − | |
| 30 | −# include <asm/sigcontext.h> | |
| 31 | − | |
| 32 | −# endif /* !__ASSEMBLY__ */ | |
| 33 | −#endif /* _ASM_IA64_SIGNAL_H */ | |
| @@ -1,103 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −/* | |
| 3 | − * SMP Support | |
| 4 | − * | |
| 5 | − * Copyright (C) 1999 VA Linux Systems | |
| 6 | − * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> | |
| 7 | − * (c) Copyright 2001-2003, 2005 Hewlett-Packard Development Company, L.P. | |
| 8 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 9 | − * Bjorn Helgaas <bjorn.helgaas@hp.com> | |
| 10 | − */ | |
| 11 | −#ifndef _ASM_IA64_SMP_H | |
| 12 | −#define _ASM_IA64_SMP_H | |
| 13 | − | |
| 14 | −#include <linux/init.h> | |
| 15 | −#include <linux/threads.h> | |
| 16 | −#include <linux/kernel.h> | |
| 17 | −#include <linux/cpumask.h> | |
| 18 | −#include <linux/bitops.h> | |
| 19 | −#include <linux/irqreturn.h> | |
| 20 | − | |
| 21 | −#include <asm/param.h> | |
| 22 | −#include <asm/processor.h> | |
| 23 | −#include <asm/ptrace.h> | |
| 24 | − | |
| 25 | −static inline unsigned int | |
| 26 | −ia64_get_lid (void) | |
| 27 | −{ | |
| 28 | − union { | |
| 29 | − struct { | |
| 30 | − unsigned long reserved : 16; | |
| 31 | − unsigned long eid : 8; | |
| 32 | − unsigned long id : 8; | |
| 33 | − unsigned long ignored : 32; | |
| 34 | − } f; | |
| 35 | − unsigned long bits; | |
| 36 | − } lid; | |
| 37 | − | |
| 38 | − lid.bits = ia64_getreg(_IA64_REG_CR_LID); | |
| 39 | − return lid.f.id << 8 | lid.f.eid; | |
| 40 | −} | |
| 41 | − | |
| 42 | −#define hard_smp_processor_id() ia64_get_lid() | |
| 43 | − | |
| 44 | −#ifdef CONFIG_SMP | |
| 45 | − | |
| 46 | −#define raw_smp_processor_id() (current_thread_info()->cpu) | |
| 47 | − | |
| 48 | −extern struct smp_boot_data { | |
| 49 | − int cpu_count; | |
| 50 | − int cpu_phys_id[NR_CPUS]; | |
| 51 | −} smp_boot_data __initdata; | |
| 52 | − | |
| 53 | −extern char no_int_routing; | |
| 54 | − | |
| 55 | −extern cpumask_t cpu_core_map[NR_CPUS]; | |
| 56 | −DECLARE_PER_CPU_SHARED_ALIGNED(cpumask_t, cpu_sibling_map); | |
| 57 | −extern int smp_num_siblings; | |
| 58 | −extern void __iomem *ipi_base_addr; | |
| 59 | − | |
| 60 | −extern volatile int ia64_cpu_to_sapicid[]; | |
| 61 | −#define cpu_physical_id(i) ia64_cpu_to_sapicid[i] | |
| 62 | − | |
| 63 | −extern unsigned long ap_wakeup_vector; | |
| 64 | − | |
| 65 | −/* | |
| 66 | − * Function to map hard smp processor id to logical id. Slow, so don't use this in | |
| 67 | − * performance-critical code. | |
| 68 | − */ | |
| 69 | −static inline int | |
| 70 | −cpu_logical_id (int cpuid) | |
| 71 | −{ | |
| 72 | − int i; | |
| 73 | − | |
| 74 | − for (i = 0; i < NR_CPUS; ++i) | |
| 75 | − if (cpu_physical_id(i) == cpuid) | |
| 76 | − break; | |
| 77 | − return i; | |
| 78 | −} | |
| 79 | − | |
| 80 | −/* Upping and downing of CPUs */ | |
| 81 | −extern int __cpu_disable (void); | |
| 82 | −extern void __cpu_die (unsigned int cpu); | |
| 83 | −extern void cpu_die (void) __attribute__ ((noreturn)); | |
| 84 | −extern void __init smp_build_cpu_map(void); | |
| 85 | − | |
| 86 | −extern void __init init_smp_config (void); | |
| 87 | −extern void smp_do_timer (struct pt_regs *regs); | |
| 88 | − | |
| 89 | −extern irqreturn_t handle_IPI(int irq, void *dev_id); | |
| 90 | −extern void smp_send_reschedule (int cpu); | |
| 91 | −extern void identify_siblings (struct cpuinfo_ia64 *); | |
| 92 | −extern int is_multithreading_enabled(void); | |
| 93 | − | |
| 94 | −extern void arch_send_call_function_single_ipi(int cpu); | |
| 95 | −extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); | |
| 96 | − | |
| 97 | −#else /* CONFIG_SMP */ | |
| 98 | − | |
| 99 | −#define cpu_logical_id(i) 0 | |
| 100 | −#define cpu_physical_id(i) ia64_get_lid() | |
| 101 | − | |
| 102 | −#endif /* CONFIG_SMP */ | |
| 103 | −#endif /* _ASM_IA64_SMP_H */ | |
| @@ -1,15 +0,0 @@ | ||
| 1 | −/* | |
| 2 | − * This file is subject to the terms and conditions of the GNU General Public | |
| 3 | − * License. See the file "COPYING" in the main directory of this archive | |
| 4 | − * for more details. | |
| 5 | − * | |
| 6 | − * Copyright (C) 1992 - 1997, 2000-2006 Silicon Graphics, Inc. All rights reserved. | |
| 7 | − */ | |
| 8 | − | |
| 9 | −#ifndef _ASM_IA64_SN_INTR_H | |
| 10 | −#define _ASM_IA64_SN_INTR_H | |
| 11 | − | |
| 12 | −#define SGI_XPC_ACTIVATE 0x30 | |
| 13 | −#define SGI_XPC_NOTIFY 0xe7 | |
| 14 | − | |
| 15 | −#endif /* _ASM_IA64_SN_INTR_H */ | |
| @@ -1,124 +0,0 @@ | ||
| 1 | −#ifndef _ASM_IA64_SN_SN_SAL_H | |
| 2 | −#define _ASM_IA64_SN_SN_SAL_H | |
| 3 | − | |
| 4 | −/* | |
| 5 | − * System Abstraction Layer definitions for IA64 | |
| 6 | − * | |
| 7 | − * This file is subject to the terms and conditions of the GNU General Public | |
| 8 | − * License. See the file "COPYING" in the main directory of this archive | |
| 9 | − * for more details. | |
| 10 | − * | |
| 11 | − * Copyright (c) 2000-2006 Silicon Graphics, Inc. All rights reserved. | |
| 12 | − */ | |
| 13 | − | |
| 14 | −#include <linux/types.h> | |
| 15 | −#include <asm/sal.h> | |
| 16 | − | |
| 17 | −// SGI Specific Calls | |
| 18 | −#define SN_SAL_GET_PARTITION_ADDR 0x02000009 | |
| 19 | −#define SN_SAL_MEMPROTECT 0x0200003e | |
| 20 | − | |
| 21 | −#define SN_SAL_WATCHLIST_ALLOC 0x02000070 | |
| 22 | −#define SN_SAL_WATCHLIST_FREE 0x02000071 | |
| 23 | − | |
| 24 | −/* | |
| 25 | − * SAL Error Codes | |
| 26 | − */ | |
| 27 | −#define SALRET_MORE_PASSES 1 | |
| 28 | −#define SALRET_OK 0 | |
| 29 | −#define SALRET_NOT_IMPLEMENTED (-1) | |
| 30 | −#define SALRET_INVALID_ARG (-2) | |
| 31 | −#define SALRET_ERROR (-3) | |
| 32 | − | |
| 33 | −/* | |
| 34 | − * Returns the physical address of the partition's reserved page through | |
| 35 | − * an iterative number of calls. | |
| 36 | − * | |
| 37 | − * On first call, 'cookie' and 'len' should be set to 0, and 'addr' | |
| 38 | − * set to the nasid of the partition whose reserved page's address is | |
| 39 | − * being sought. | |
| 40 | − * On subsequent calls, pass the values, that were passed back on the | |
| 41 | − * previous call. | |
| 42 | − * | |
| 43 | − * While the return status equals SALRET_MORE_PASSES, keep calling | |
| 44 | − * this function after first copying 'len' bytes starting at 'addr' | |
| 45 | − * into 'buf'. Once the return status equals SALRET_OK, 'addr' will | |
| 46 | − * be the physical address of the partition's reserved page. If the | |
| 47 | − * return status equals neither of these, an error as occurred. | |
| 48 | − */ | |
| 49 | −static inline s64 | |
| 50 | −sn_partition_reserved_page_pa(u64 buf, u64 *cookie, u64 *addr, u64 *len) | |
| 51 | −{ | |
| 52 | − struct ia64_sal_retval rv; | |
| 53 | − ia64_sal_oemcall_reentrant(&rv, SN_SAL_GET_PARTITION_ADDR, *cookie, | |
| 54 | − *addr, buf, *len, 0, 0, 0); | |
| 55 | − *cookie = rv.v0; | |
| 56 | − *addr = rv.v1; | |
| 57 | − *len = rv.v2; | |
| 58 | − return rv.status; | |
| 59 | −} | |
| 60 | − | |
| 61 | −/* | |
| 62 | − * Change memory access protections for a physical address range. | |
| 63 | − * nasid_array is not used on Altix, but may be in future architectures. | |
| 64 | − * Available memory protection access classes are defined after the function. | |
| 65 | − */ | |
| 66 | −static inline int | |
| 67 | −sn_change_memprotect(u64 paddr, u64 len, u64 perms, u64 *nasid_array) | |
| 68 | −{ | |
| 69 | − struct ia64_sal_retval ret_stuff; | |
| 70 | − | |
| 71 | − ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_MEMPROTECT, paddr, len, | |
| 72 | − (u64)nasid_array, perms, 0, 0, 0); | |
| 73 | − return ret_stuff.status; | |
| 74 | −} | |
| 75 | −#define SN_MEMPROT_ACCESS_CLASS_0 0x14a080 | |
| 76 | −#define SN_MEMPROT_ACCESS_CLASS_1 0x2520c2 | |
| 77 | −#define SN_MEMPROT_ACCESS_CLASS_2 0x14a1ca | |
| 78 | −#define SN_MEMPROT_ACCESS_CLASS_3 0x14a290 | |
| 79 | −#define SN_MEMPROT_ACCESS_CLASS_6 0x084080 | |
| 80 | −#define SN_MEMPROT_ACCESS_CLASS_7 0x021080 | |
| 81 | − | |
| 82 | −union sn_watchlist_u { | |
| 83 | − u64 val; | |
| 84 | − struct { | |
| 85 | − u64 blade : 16, | |
| 86 | − size : 32, | |
| 87 | − filler : 16; | |
| 88 | − }; | |
| 89 | −}; | |
| 90 | − | |
| 91 | −static inline int | |
| 92 | −sn_mq_watchlist_alloc(int blade, void *mq, unsigned int mq_size, | |
| 93 | − unsigned long *intr_mmr_offset) | |
| 94 | −{ | |
| 95 | − struct ia64_sal_retval rv; | |
| 96 | − unsigned long addr; | |
| 97 | − union sn_watchlist_u size_blade; | |
| 98 | − int watchlist; | |
| 99 | − | |
| 100 | − addr = (unsigned long)mq; | |
| 101 | − size_blade.size = mq_size; | |
| 102 | − size_blade.blade = blade; | |
| 103 | − | |
| 104 | − /* | |
| 105 | − * bios returns watchlist number or negative error number. | |
| 106 | − */ | |
| 107 | − ia64_sal_oemcall_nolock(&rv, SN_SAL_WATCHLIST_ALLOC, addr, | |
| 108 | − size_blade.val, (u64)intr_mmr_offset, | |
| 109 | − (u64)&watchlist, 0, 0, 0); | |
| 110 | − if (rv.status < 0) | |
| 111 | − return rv.status; | |
| 112 | − | |
| 113 | − return watchlist; | |
| 114 | −} | |
| 115 | − | |
| 116 | −static inline int | |
| 117 | −sn_mq_watchlist_free(int blade, int watchlist_num) | |
| 118 | −{ | |
| 119 | − struct ia64_sal_retval rv; | |
| 120 | − ia64_sal_oemcall_nolock(&rv, SN_SAL_WATCHLIST_FREE, blade, | |
| 121 | − watchlist_num, 0, 0, 0, 0, 0); | |
| 122 | − return rv.status; | |
| 123 | −} | |
| 124 | −#endif /* _ASM_IA64_SN_SN_SAL_H */ | |
| @@ -1,28 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_SPARSEMEM_H | |
| 3 | −#define _ASM_IA64_SPARSEMEM_H | |
| 4 | − | |
| 5 | −#ifdef CONFIG_SPARSEMEM | |
| 6 | −#include <asm/page.h> | |
| 7 | −/* | |
| 8 | − * SECTION_SIZE_BITS 2^N: how big each section will be | |
| 9 | − * MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space | |
| 10 | − */ | |
| 11 | − | |
| 12 | −#define SECTION_SIZE_BITS (30) | |
| 13 | −#define MAX_PHYSMEM_BITS (50) | |
| 14 | −#ifdef CONFIG_ARCH_FORCE_MAX_ORDER | |
| 15 | −#if (CONFIG_ARCH_FORCE_MAX_ORDER + PAGE_SHIFT > SECTION_SIZE_BITS) | |
| 16 | −#undef SECTION_SIZE_BITS | |
| 17 | −#define SECTION_SIZE_BITS (CONFIG_ARCH_FORCE_MAX_ORDER + PAGE_SHIFT) | |
| 18 | −#endif | |
| 19 | −#endif | |
| 20 | − | |
| 21 | −#endif /* CONFIG_SPARSEMEM */ | |
| 22 | − | |
| 23 | −#ifdef CONFIG_MEMORY_HOTPLUG | |
| 24 | −int memory_add_physaddr_to_nid(u64 addr); | |
| 25 | −#define memory_add_physaddr_to_nid memory_add_physaddr_to_nid | |
| 26 | −#endif | |
| 27 | − | |
| 28 | −#endif /* _ASM_IA64_SPARSEMEM_H */ | |
| @@ -1,265 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_SPINLOCK_H | |
| 3 | −#define _ASM_IA64_SPINLOCK_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Copyright (C) 1998-2003 Hewlett-Packard Co | |
| 7 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 8 | − * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> | |
| 9 | − * | |
| 10 | − * This file is used for SMP configurations only. | |
| 11 | − */ | |
| 12 | − | |
| 13 | −#include <linux/compiler.h> | |
| 14 | −#include <linux/kernel.h> | |
| 15 | −#include <linux/bitops.h> | |
| 16 | − | |
| 17 | −#include <linux/atomic.h> | |
| 18 | −#include <asm/intrinsics.h> | |
| 19 | −#include <asm/barrier.h> | |
| 20 | −#include <asm/processor.h> | |
| 21 | − | |
| 22 | −#define arch_spin_lock_init(x) ((x)->lock = 0) | |
| 23 | − | |
| 24 | −/* | |
| 25 | − * Ticket locks are conceptually two parts, one indicating the current head of | |
| 26 | − * the queue, and the other indicating the current tail. The lock is acquired | |
| 27 | − * by atomically noting the tail and incrementing it by one (thus adding | |
| 28 | − * ourself to the queue and noting our position), then waiting until the head | |
| 29 | − * becomes equal to the initial value of the tail. | |
| 30 | − * The pad bits in the middle are used to prevent the next_ticket number | |
| 31 | − * overflowing into the now_serving number. | |
| 32 | − * | |
| 33 | − * 31 17 16 15 14 0 | |
| 34 | − * +----------------------------------------------------+ | |
| 35 | − * | now_serving | padding | next_ticket | | |
| 36 | − * +----------------------------------------------------+ | |
| 37 | − */ | |
| 38 | − | |
| 39 | −#define TICKET_SHIFT 17 | |
| 40 | −#define TICKET_BITS 15 | |
| 41 | −#define TICKET_MASK ((1 << TICKET_BITS) - 1) | |
| 42 | − | |
| 43 | −static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock) | |
| 44 | −{ | |
| 45 | − int *p = (int *)&lock->lock, ticket, serve; | |
| 46 | − | |
| 47 | − ticket = ia64_fetchadd(1, p, acq); | |
| 48 | − | |
| 49 | − if (!(((ticket >> TICKET_SHIFT) ^ ticket) & TICKET_MASK)) | |
| 50 | − return; | |
| 51 | − | |
| 52 | − ia64_invala(); | |
| 53 | − | |
| 54 | − for (;;) { | |
| 55 | − asm volatile ("ld4.c.nc %0=[%1]" : "=r"(serve) : "r"(p) : "memory"); | |
| 56 | − | |
| 57 | − if (!(((serve >> TICKET_SHIFT) ^ ticket) & TICKET_MASK)) | |
| 58 | − return; | |
| 59 | − cpu_relax(); | |
| 60 | − } | |
| 61 | −} | |
| 62 | − | |
| 63 | −static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock) | |
| 64 | −{ | |
| 65 | − int tmp = READ_ONCE(lock->lock); | |
| 66 | − | |
| 67 | − if (!(((tmp >> TICKET_SHIFT) ^ tmp) & TICKET_MASK)) | |
| 68 | − return ia64_cmpxchg(acq, &lock->lock, tmp, tmp + 1, sizeof (tmp)) == tmp; | |
| 69 | − return 0; | |
| 70 | −} | |
| 71 | − | |
| 72 | −static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock) | |
| 73 | −{ | |
| 74 | − unsigned short *p = (unsigned short *)&lock->lock + 1, tmp; | |
| 75 | − | |
| 76 | − /* This could be optimised with ARCH_HAS_MMIOWB */ | |
| 77 | − mmiowb(); | |
| 78 | − asm volatile ("ld2.bias %0=[%1]" : "=r"(tmp) : "r"(p)); | |
| 79 | − WRITE_ONCE(*p, (tmp + 2) & ~1); | |
| 80 | −} | |
| 81 | − | |
| 82 | −static inline int __ticket_spin_is_locked(arch_spinlock_t *lock) | |
| 83 | −{ | |
| 84 | − long tmp = READ_ONCE(lock->lock); | |
| 85 | − | |
| 86 | − return !!(((tmp >> TICKET_SHIFT) ^ tmp) & TICKET_MASK); | |
| 87 | −} | |
| 88 | − | |
| 89 | −static inline int __ticket_spin_is_contended(arch_spinlock_t *lock) | |
| 90 | −{ | |
| 91 | − long tmp = READ_ONCE(lock->lock); | |
| 92 | − | |
| 93 | − return ((tmp - (tmp >> TICKET_SHIFT)) & TICKET_MASK) > 1; | |
| 94 | −} | |
| 95 | − | |
| 96 | −static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock) | |
| 97 | −{ | |
| 98 | − return !(((lock.lock >> TICKET_SHIFT) ^ lock.lock) & TICKET_MASK); | |
| 99 | −} | |
| 100 | − | |
| 101 | −static inline int arch_spin_is_locked(arch_spinlock_t *lock) | |
| 102 | −{ | |
| 103 | − return __ticket_spin_is_locked(lock); | |
| 104 | −} | |
| 105 | − | |
| 106 | −static inline int arch_spin_is_contended(arch_spinlock_t *lock) | |
| 107 | −{ | |
| 108 | − return __ticket_spin_is_contended(lock); | |
| 109 | −} | |
| 110 | −#define arch_spin_is_contended arch_spin_is_contended | |
| 111 | − | |
| 112 | −static __always_inline void arch_spin_lock(arch_spinlock_t *lock) | |
| 113 | −{ | |
| 114 | − __ticket_spin_lock(lock); | |
| 115 | −} | |
| 116 | − | |
| 117 | −static __always_inline int arch_spin_trylock(arch_spinlock_t *lock) | |
| 118 | −{ | |
| 119 | − return __ticket_spin_trylock(lock); | |
| 120 | −} | |
| 121 | − | |
| 122 | −static __always_inline void arch_spin_unlock(arch_spinlock_t *lock) | |
| 123 | −{ | |
| 124 | − __ticket_spin_unlock(lock); | |
| 125 | −} | |
| 126 | − | |
| 127 | −#ifdef ASM_SUPPORTED | |
| 128 | − | |
| 129 | −static __always_inline void | |
| 130 | −arch_read_lock(arch_rwlock_t *lock) | |
| 131 | −{ | |
| 132 | − unsigned long flags = 0; | |
| 133 | − | |
| 134 | − __asm__ __volatile__ ( | |
| 135 | − "tbit.nz p6, p0 = %1,%2\n" | |
| 136 | − "br.few 3f\n" | |
| 137 | − "1:\n" | |
| 138 | − "fetchadd4.rel r2 = [%0], -1;;\n" | |
| 139 | − "(p6) ssm psr.i\n" | |
| 140 | − "2:\n" | |
| 141 | − "hint @pause\n" | |
| 142 | − "ld4 r2 = [%0];;\n" | |
| 143 | − "cmp4.lt p7,p0 = r2, r0\n" | |
| 144 | − "(p7) br.cond.spnt.few 2b\n" | |
| 145 | − "(p6) rsm psr.i\n" | |
| 146 | − ";;\n" | |
| 147 | − "3:\n" | |
| 148 | − "fetchadd4.acq r2 = [%0], 1;;\n" | |
| 149 | − "cmp4.lt p7,p0 = r2, r0\n" | |
| 150 | − "(p7) br.cond.spnt.few 1b\n" | |
| 151 | − : : "r"(lock), "r"(flags), "i"(IA64_PSR_I_BIT) | |
| 152 | − : "p6", "p7", "r2", "memory"); | |
| 153 | −} | |
| 154 | − | |
| 155 | −#else /* !ASM_SUPPORTED */ | |
| 156 | − | |
| 157 | −#define arch_read_lock(rw) \ | |
| 158 | −do { \ | |
| 159 | − arch_rwlock_t *__read_lock_ptr = (rw); \ | |
| 160 | − \ | |
| 161 | − while (unlikely(ia64_fetchadd(1, (int *) __read_lock_ptr, acq) < 0)) { \ | |
| 162 | − ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \ | |
| 163 | − while (*(volatile int *)__read_lock_ptr < 0) \ | |
| 164 | − cpu_relax(); \ | |
| 165 | − } \ | |
| 166 | −} while (0) | |
| 167 | − | |
| 168 | −#endif /* !ASM_SUPPORTED */ | |
| 169 | − | |
| 170 | −#define arch_read_unlock(rw) \ | |
| 171 | −do { \ | |
| 172 | − arch_rwlock_t *__read_lock_ptr = (rw); \ | |
| 173 | − ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \ | |
| 174 | −} while (0) | |
| 175 | − | |
| 176 | −#ifdef ASM_SUPPORTED | |
| 177 | − | |
| 178 | −static __always_inline void | |
| 179 | −arch_write_lock(arch_rwlock_t *lock) | |
| 180 | −{ | |
| 181 | − unsigned long flags = 0; | |
| 182 | − | |
| 183 | − __asm__ __volatile__ ( | |
| 184 | − "tbit.nz p6, p0 = %1, %2\n" | |
| 185 | − "mov ar.ccv = r0\n" | |
| 186 | − "dep r29 = -1, r0, 31, 1\n" | |
| 187 | − "br.few 3f;;\n" | |
| 188 | − "1:\n" | |
| 189 | − "(p6) ssm psr.i\n" | |
| 190 | − "2:\n" | |
| 191 | − "hint @pause\n" | |
| 192 | − "ld4 r2 = [%0];;\n" | |
| 193 | − "cmp4.eq p0,p7 = r0, r2\n" | |
| 194 | − "(p7) br.cond.spnt.few 2b\n" | |
| 195 | − "(p6) rsm psr.i\n" | |
| 196 | − ";;\n" | |
| 197 | − "3:\n" | |
| 198 | − "cmpxchg4.acq r2 = [%0], r29, ar.ccv;;\n" | |
| 199 | − "cmp4.eq p0,p7 = r0, r2\n" | |
| 200 | − "(p7) br.cond.spnt.few 1b;;\n" | |
| 201 | − : : "r"(lock), "r"(flags), "i"(IA64_PSR_I_BIT) | |
| 202 | − : "ar.ccv", "p6", "p7", "r2", "r29", "memory"); | |
| 203 | −} | |
| 204 | − | |
| 205 | −#define arch_write_trylock(rw) \ | |
| 206 | −({ \ | |
| 207 | − register long result; \ | |
| 208 | − \ | |
| 209 | − __asm__ __volatile__ ( \ | |
| 210 | − "mov ar.ccv = r0\n" \ | |
| 211 | − "dep r29 = -1, r0, 31, 1;;\n" \ | |
| 212 | − "cmpxchg4.acq %0 = [%1], r29, ar.ccv\n" \ | |
| 213 | − : "=r"(result) : "r"(rw) : "ar.ccv", "r29", "memory"); \ | |
| 214 | − (result == 0); \ | |
| 215 | −}) | |
| 216 | − | |
| 217 | −static inline void arch_write_unlock(arch_rwlock_t *x) | |
| 218 | −{ | |
| 219 | − u8 *y = (u8 *)x; | |
| 220 | − barrier(); | |
| 221 | − asm volatile ("st1.rel.nta [%0] = r0\n\t" :: "r"(y+3) : "memory" ); | |
| 222 | −} | |
| 223 | − | |
| 224 | −#else /* !ASM_SUPPORTED */ | |
| 225 | − | |
| 226 | −#define arch_write_lock(l) \ | |
| 227 | −({ \ | |
| 228 | − __u64 ia64_val, ia64_set_val = ia64_dep_mi(-1, 0, 31, 1); \ | |
| 229 | − __u32 *ia64_write_lock_ptr = (__u32 *) (l); \ | |
| 230 | − do { \ | |
| 231 | − while (*ia64_write_lock_ptr) \ | |
| 232 | − ia64_barrier(); \ | |
| 233 | − ia64_val = ia64_cmpxchg4_acq(ia64_write_lock_ptr, ia64_set_val, 0); \ | |
| 234 | − } while (ia64_val); \ | |
| 235 | −}) | |
| 236 | − | |
| 237 | −#define arch_write_trylock(rw) \ | |
| 238 | −({ \ | |
| 239 | − __u64 ia64_val; \ | |
| 240 | − __u64 ia64_set_val = ia64_dep_mi(-1, 0, 31,1); \ | |
| 241 | − ia64_val = ia64_cmpxchg4_acq((__u32 *)(rw), ia64_set_val, 0); \ | |
| 242 | − (ia64_val == 0); \ | |
| 243 | −}) | |
| 244 | − | |
| 245 | −static inline void arch_write_unlock(arch_rwlock_t *x) | |
| 246 | −{ | |
| 247 | − barrier(); | |
| 248 | − x->write_lock = 0; | |
| 249 | −} | |
| 250 | − | |
| 251 | −#endif /* !ASM_SUPPORTED */ | |
| 252 | − | |
| 253 | −static inline int arch_read_trylock(arch_rwlock_t *x) | |
| 254 | −{ | |
| 255 | − union { | |
| 256 | − arch_rwlock_t lock; | |
| 257 | − __u32 word; | |
| 258 | − } old, new; | |
| 259 | − old.lock = new.lock = *x; | |
| 260 | − old.lock.write_lock = new.lock.write_lock = 0; | |
| 261 | − ++new.lock.read_counter; | |
| 262 | − return (u32)ia64_cmpxchg4_acq((__u32 *)(x), new.word, old.word) == old.word; | |
| 263 | −} | |
| 264 | − | |
| 265 | −#endif /* _ASM_IA64_SPINLOCK_H */ | |
| @@ -1,22 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_SPINLOCK_TYPES_H | |
| 3 | −#define _ASM_IA64_SPINLOCK_TYPES_H | |
| 4 | − | |
| 5 | −#ifndef __LINUX_SPINLOCK_TYPES_RAW_H | |
| 6 | −# error "please don't include this file directly" | |
| 7 | −#endif | |
| 8 | − | |
| 9 | −typedef struct { | |
| 10 | − volatile unsigned int lock; | |
| 11 | −} arch_spinlock_t; | |
| 12 | − | |
| 13 | −#define __ARCH_SPIN_LOCK_UNLOCKED { 0 } | |
| 14 | − | |
| 15 | −typedef struct { | |
| 16 | − volatile unsigned int read_counter : 31; | |
| 17 | − volatile unsigned int write_lock : 1; | |
| 18 | −} arch_rwlock_t; | |
| 19 | − | |
| 20 | −#define __ARCH_RW_LOCK_UNLOCKED { 0, 0 } | |
| 21 | − | |
| 22 | −#endif | |
| @@ -1,22 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_STRING_H | |
| 3 | −#define _ASM_IA64_STRING_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Here is where we want to put optimized versions of the string | |
| 7 | − * routines. | |
| 8 | − * | |
| 9 | − * Copyright (C) 1998-2000, 2002 Hewlett-Packard Co | |
| 10 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 11 | − */ | |
| 12 | − | |
| 13 | − | |
| 14 | −#define __HAVE_ARCH_STRLEN 1 /* see arch/ia64/lib/strlen.S */ | |
| 15 | −#define __HAVE_ARCH_MEMSET 1 /* see arch/ia64/lib/memset.S */ | |
| 16 | −#define __HAVE_ARCH_MEMCPY 1 /* see arch/ia64/lib/memcpy.S */ | |
| 17 | − | |
| 18 | −extern __kernel_size_t strlen (const char *); | |
| 19 | −extern void *memcpy (void *, const void *, __kernel_size_t); | |
| 20 | −extern void *memset (void *, int, __kernel_size_t); | |
| 21 | − | |
| 22 | −#endif /* _ASM_IA64_STRING_H */ | |
| @@ -1,71 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −/* | |
| 3 | − * Low-level task switching. This is based on information published in | |
| 4 | − * the Processor Abstraction Layer and the System Abstraction Layer | |
| 5 | − * manual. | |
| 6 | − * | |
| 7 | − * Copyright (C) 1998-2003 Hewlett-Packard Co | |
| 8 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 9 | − * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> | |
| 10 | − * Copyright (C) 1999 Don Dugger <don.dugger@intel.com> | |
| 11 | − */ | |
| 12 | −#ifndef _ASM_IA64_SWITCH_TO_H | |
| 13 | −#define _ASM_IA64_SWITCH_TO_H | |
| 14 | − | |
| 15 | −#include <linux/percpu.h> | |
| 16 | − | |
| 17 | −struct task_struct; | |
| 18 | − | |
| 19 | −/* | |
| 20 | − * Context switch from one thread to another. If the two threads have | |
| 21 | − * different address spaces, schedule() has already taken care of | |
| 22 | − * switching to the new address space by calling switch_mm(). | |
| 23 | − * | |
| 24 | − * Disabling access to the fph partition and the debug-register | |
| 25 | − * context switch MUST be done before calling ia64_switch_to() since a | |
| 26 | − * newly created thread returns directly to | |
| 27 | − * ia64_ret_from_syscall_clear_r8. | |
| 28 | − */ | |
| 29 | −extern struct task_struct *ia64_switch_to (void *next_task); | |
| 30 | − | |
| 31 | −extern void ia64_save_extra (struct task_struct *task); | |
| 32 | −extern void ia64_load_extra (struct task_struct *task); | |
| 33 | − | |
| 34 | −#define IA64_HAS_EXTRA_STATE(t) \ | |
| 35 | − ((t)->thread.flags & (IA64_THREAD_DBG_VALID|IA64_THREAD_PM_VALID)) | |
| 36 | − | |
| 37 | −#define __switch_to(prev,next,last) do { \ | |
| 38 | − if (IA64_HAS_EXTRA_STATE(prev)) \ | |
| 39 | − ia64_save_extra(prev); \ | |
| 40 | − if (IA64_HAS_EXTRA_STATE(next)) \ | |
| 41 | − ia64_load_extra(next); \ | |
| 42 | − ia64_psr(task_pt_regs(next))->dfh = !ia64_is_local_fpu_owner(next); \ | |
| 43 | − (last) = ia64_switch_to((next)); \ | |
| 44 | −} while (0) | |
| 45 | − | |
| 46 | −#ifdef CONFIG_SMP | |
| 47 | −/* | |
| 48 | − * In the SMP case, we save the fph state when context-switching away from a thread that | |
| 49 | − * modified fph. This way, when the thread gets scheduled on another CPU, the CPU can | |
| 50 | − * pick up the state from task->thread.fph, avoiding the complication of having to fetch | |
| 51 | − * the latest fph state from another CPU. In other words: eager save, lazy restore. | |
| 52 | − */ | |
| 53 | −# define switch_to(prev,next,last) do { \ | |
| 54 | − if (ia64_psr(task_pt_regs(prev))->mfh && ia64_is_local_fpu_owner(prev)) { \ | |
| 55 | − ia64_psr(task_pt_regs(prev))->mfh = 0; \ | |
| 56 | − (prev)->thread.flags |= IA64_THREAD_FPH_VALID; \ | |
| 57 | − __ia64_save_fpu((prev)->thread.fph); \ | |
| 58 | − } \ | |
| 59 | − __switch_to(prev, next, last); \ | |
| 60 | − /* "next" in old context is "current" in new context */ \ | |
| 61 | − if (unlikely((current->thread.flags & IA64_THREAD_MIGRATION) && \ | |
| 62 | − (task_cpu(current) != \ | |
| 63 | − task_thread_info(current)->last_cpu))) { \ | |
| 64 | − task_thread_info(current)->last_cpu = task_cpu(current); \ | |
| 65 | − } \ | |
| 66 | −} while (0) | |
| 67 | −#else | |
| 68 | −# define switch_to(prev,next,last) __switch_to(prev, next, last) | |
| 69 | −#endif | |
| 70 | − | |
| 71 | −#endif /* _ASM_IA64_SWITCH_TO_H */ | |
| @@ -1,65 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0-only */ | |
| 2 | −/* | |
| 3 | − * Access to user system call parameters and results | |
| 4 | − * | |
| 5 | − * Copyright (C) 2008 Intel Corp. Shaohua Li <shaohua.li@intel.com> | |
| 6 | − * | |
| 7 | − * See asm-generic/syscall.h for descriptions of what we must do here. | |
| 8 | − */ | |
| 9 | − | |
| 10 | −#ifndef _ASM_SYSCALL_H | |
| 11 | −#define _ASM_SYSCALL_H 1 | |
| 12 | − | |
| 13 | −#include <uapi/linux/audit.h> | |
| 14 | −#include <linux/sched.h> | |
| 15 | −#include <linux/err.h> | |
| 16 | − | |
| 17 | −static inline long syscall_get_nr(struct task_struct *task, | |
| 18 | − struct pt_regs *regs) | |
| 19 | −{ | |
| 20 | − if ((long)regs->cr_ifs < 0) /* Not a syscall */ | |
| 21 | − return -1; | |
| 22 | − | |
| 23 | − return regs->r15; | |
| 24 | −} | |
| 25 | − | |
| 26 | −static inline void syscall_rollback(struct task_struct *task, | |
| 27 | − struct pt_regs *regs) | |
| 28 | −{ | |
| 29 | − /* do nothing */ | |
| 30 | −} | |
| 31 | − | |
| 32 | −static inline long syscall_get_error(struct task_struct *task, | |
| 33 | − struct pt_regs *regs) | |
| 34 | −{ | |
| 35 | − return regs->r10 == -1 ? -regs->r8:0; | |
| 36 | −} | |
| 37 | − | |
| 38 | −static inline long syscall_get_return_value(struct task_struct *task, | |
| 39 | − struct pt_regs *regs) | |
| 40 | −{ | |
| 41 | − return regs->r8; | |
| 42 | −} | |
| 43 | − | |
| 44 | −static inline void syscall_set_return_value(struct task_struct *task, | |
| 45 | − struct pt_regs *regs, | |
| 46 | − int error, long val) | |
| 47 | −{ | |
| 48 | − if (error) { | |
| 49 | − /* error < 0, but ia64 uses > 0 return value */ | |
| 50 | − regs->r8 = -error; | |
| 51 | − regs->r10 = -1; | |
| 52 | − } else { | |
| 53 | − regs->r8 = val; | |
| 54 | − regs->r10 = 0; | |
| 55 | − } | |
| 56 | −} | |
| 57 | − | |
| 58 | −extern void syscall_get_arguments(struct task_struct *task, | |
| 59 | − struct pt_regs *regs, unsigned long *args); | |
| 60 | − | |
| 61 | −static inline int syscall_get_arch(struct task_struct *task) | |
| 62 | −{ | |
| 63 | − return AUDIT_ARCH_IA64; | |
| 64 | −} | |
| 65 | −#endif /* _ASM_SYSCALL_H */ | |
| @@ -1,131 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −/* | |
| 3 | − * Copyright (C) 2002-2003 Hewlett-Packard Co | |
| 4 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 5 | − */ | |
| 6 | −#ifndef _ASM_IA64_THREAD_INFO_H | |
| 7 | −#define _ASM_IA64_THREAD_INFO_H | |
| 8 | − | |
| 9 | −#ifndef ASM_OFFSETS_C | |
| 10 | −#include <asm/asm-offsets.h> | |
| 11 | −#endif | |
| 12 | −#include <asm/processor.h> | |
| 13 | −#include <asm/ptrace.h> | |
| 14 | − | |
| 15 | −#define THREAD_SIZE KERNEL_STACK_SIZE | |
| 16 | − | |
| 17 | −#ifndef __ASSEMBLY__ | |
| 18 | − | |
| 19 | −/* | |
| 20 | − * On IA-64, we want to keep the task structure and kernel stack together, so they can be | |
| 21 | − * mapped by a single TLB entry and so they can be addressed by the "current" pointer | |
| 22 | − * without having to do pointer masking. | |
| 23 | − */ | |
| 24 | −struct thread_info { | |
| 25 | − struct task_struct *task; /* XXX not really needed, except for dup_task_struct() */ | |
| 26 | − __u32 flags; /* thread_info flags (see TIF_*) */ | |
| 27 | − __u32 cpu; /* current CPU */ | |
| 28 | − __u32 last_cpu; /* Last CPU thread ran on */ | |
| 29 | − __u32 status; /* Thread synchronous flags */ | |
| 30 | − int preempt_count; /* 0=premptable, <0=BUG; will also serve as bh-counter */ | |
| 31 | −#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE | |
| 32 | − __u64 utime; | |
| 33 | − __u64 stime; | |
| 34 | − __u64 gtime; | |
| 35 | − __u64 hardirq_time; | |
| 36 | − __u64 softirq_time; | |
| 37 | − __u64 idle_time; | |
| 38 | − __u64 ac_stamp; | |
| 39 | − __u64 ac_leave; | |
| 40 | − __u64 ac_stime; | |
| 41 | − __u64 ac_utime; | |
| 42 | −#endif | |
| 43 | −}; | |
| 44 | − | |
| 45 | −#define INIT_THREAD_INFO(tsk) \ | |
| 46 | −{ \ | |
| 47 | − .task = &tsk, \ | |
| 48 | − .flags = 0, \ | |
| 49 | − .cpu = 0, \ | |
| 50 | − .preempt_count = INIT_PREEMPT_COUNT, \ | |
| 51 | −} | |
| 52 | − | |
| 53 | −#ifndef ASM_OFFSETS_C | |
| 54 | −/* how to get the thread information struct from C */ | |
| 55 | −#define current_thread_info() ((struct thread_info *) ((char *) current + IA64_TASK_SIZE)) | |
| 56 | −#define arch_alloc_thread_stack_node(tsk, node) \ | |
| 57 | − ((unsigned long *) ((char *) (tsk) + IA64_TASK_SIZE)) | |
| 58 | −#define task_thread_info(tsk) ((struct thread_info *) ((char *) (tsk) + IA64_TASK_SIZE)) | |
| 59 | −#else | |
| 60 | −#define current_thread_info() ((struct thread_info *) 0) | |
| 61 | −#define arch_alloc_thread_stack_node(tsk, node) ((unsigned long *) 0) | |
| 62 | −#define task_thread_info(tsk) ((struct thread_info *) 0) | |
| 63 | −#endif | |
| 64 | −#define arch_free_thread_stack(tsk) /* nothing */ | |
| 65 | −#define task_stack_page(tsk) ((void *)(tsk)) | |
| 66 | − | |
| 67 | −#define __HAVE_THREAD_FUNCTIONS | |
| 68 | −#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE | |
| 69 | −#define setup_thread_stack(p, org) \ | |
| 70 | − *task_thread_info(p) = *task_thread_info(org); \ | |
| 71 | − task_thread_info(p)->ac_stime = 0; \ | |
| 72 | − task_thread_info(p)->ac_utime = 0; \ | |
| 73 | − task_thread_info(p)->task = (p); | |
| 74 | −#else | |
| 75 | −#define setup_thread_stack(p, org) \ | |
| 76 | − *task_thread_info(p) = *task_thread_info(org); \ | |
| 77 | − task_thread_info(p)->task = (p); | |
| 78 | −#endif | |
| 79 | −#define end_of_stack(p) (unsigned long *)((void *)(p) + IA64_RBS_OFFSET) | |
| 80 | − | |
| 81 | −#define alloc_task_struct_node(node) \ | |
| 82 | −({ \ | |
| 83 | − struct page *page = alloc_pages_node(node, GFP_KERNEL | __GFP_COMP, \ | |
| 84 | − KERNEL_STACK_SIZE_ORDER); \ | |
| 85 | − struct task_struct *ret = page ? page_address(page) : NULL; \ | |
| 86 | − \ | |
| 87 | − ret; \ | |
| 88 | −}) | |
| 89 | −#define free_task_struct(tsk) free_pages((unsigned long) (tsk), KERNEL_STACK_SIZE_ORDER) | |
| 90 | − | |
| 91 | −#endif /* !__ASSEMBLY */ | |
| 92 | − | |
| 93 | −/* | |
| 94 | − * thread information flags | |
| 95 | − * - these are process state flags that various assembly files may need to access | |
| 96 | − * - pending work-to-be-done flags are in least-significant 16 bits, other flags | |
| 97 | − * in top 16 bits | |
| 98 | − */ | |
| 99 | −#define TIF_SIGPENDING 0 /* signal pending */ | |
| 100 | −#define TIF_NEED_RESCHED 1 /* rescheduling necessary */ | |
| 101 | −#define TIF_SYSCALL_TRACE 2 /* syscall trace active */ | |
| 102 | −#define TIF_SYSCALL_AUDIT 3 /* syscall auditing active */ | |
| 103 | −#define TIF_SINGLESTEP 4 /* restore singlestep on return to user mode */ | |
| 104 | −#define TIF_NOTIFY_SIGNAL 5 /* signal notification exist */ | |
| 105 | −#define TIF_NOTIFY_RESUME 6 /* resumption notification requested */ | |
| 106 | −#define TIF_MEMDIE 17 /* is terminating due to OOM killer */ | |
| 107 | −#define TIF_MCA_INIT 18 /* this task is processing MCA or INIT */ | |
| 108 | −#define TIF_DB_DISABLED 19 /* debug trap disabled for fsyscall */ | |
| 109 | −#define TIF_RESTORE_RSE 21 /* user RBS is newer than kernel RBS */ | |
| 110 | −#define TIF_POLLING_NRFLAG 22 /* idle is polling for TIF_NEED_RESCHED */ | |
| 111 | − | |
| 112 | −#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) | |
| 113 | −#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) | |
| 114 | −#define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP) | |
| 115 | −#define _TIF_SYSCALL_TRACEAUDIT (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SINGLESTEP) | |
| 116 | −#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) | |
| 117 | −#define _TIF_NOTIFY_SIGNAL (1 << TIF_NOTIFY_SIGNAL) | |
| 118 | −#define _TIF_SIGPENDING (1 << TIF_SIGPENDING) | |
| 119 | −#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) | |
| 120 | −#define _TIF_MCA_INIT (1 << TIF_MCA_INIT) | |
| 121 | −#define _TIF_DB_DISABLED (1 << TIF_DB_DISABLED) | |
| 122 | −#define _TIF_RESTORE_RSE (1 << TIF_RESTORE_RSE) | |
| 123 | −#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) | |
| 124 | − | |
| 125 | −/* "work to do on user-return" bits */ | |
| 126 | −#define TIF_ALLWORK_MASK (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME|_TIF_SYSCALL_AUDIT|\ | |
| 127 | − _TIF_NEED_RESCHED|_TIF_SYSCALL_TRACE|_TIF_NOTIFY_SIGNAL) | |
| 128 | −/* like TIF_ALLWORK_BITS but sans TIF_SYSCALL_TRACE or TIF_SYSCALL_AUDIT */ | |
| 129 | −#define TIF_WORK_MASK (TIF_ALLWORK_MASK&~(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)) | |
| 130 | − | |
| 131 | −#endif /* _ASM_IA64_THREAD_INFO_H */ | |
| @@ -1,47 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_TIMEX_H | |
| 3 | −#define _ASM_IA64_TIMEX_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co | |
| 7 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 8 | − */ | |
| 9 | −/* | |
| 10 | − * 2001/01/18 davidm Removed CLOCK_TICK_RATE. It makes no sense on IA-64. | |
| 11 | − * Also removed cacheflush_time as it's entirely unused. | |
| 12 | − */ | |
| 13 | − | |
| 14 | −#include <asm/intrinsics.h> | |
| 15 | −#include <asm/processor.h> | |
| 16 | − | |
| 17 | −typedef unsigned long cycles_t; | |
| 18 | − | |
| 19 | −extern void (*ia64_udelay)(unsigned long usecs); | |
| 20 | − | |
| 21 | −/* | |
| 22 | − * For performance reasons, we don't want to define CLOCK_TICK_TRATE as | |
| 23 | − * local_cpu_data->itc_rate. Fortunately, we don't have to, either: according to George | |
| 24 | − * Anzinger, 1/CLOCK_TICK_RATE is taken as the resolution of the timer clock. The time | |
| 25 | − * calculation assumes that you will use enough of these so that your tick size <= 1/HZ. | |
| 26 | − * If the calculation shows that your CLOCK_TICK_RATE can not supply exactly 1/HZ ticks, | |
| 27 | − * the actual value is calculated and used to update the wall clock each jiffie. Setting | |
| 28 | − * the CLOCK_TICK_RATE to x*HZ insures that the calculation will find no errors. Hence we | |
| 29 | − * pick a multiple of HZ which gives us a (totally virtual) CLOCK_TICK_RATE of about | |
| 30 | − * 100MHz. | |
| 31 | − */ | |
| 32 | −#define CLOCK_TICK_RATE (HZ * 100000UL) | |
| 33 | − | |
| 34 | −static inline cycles_t | |
| 35 | −get_cycles (void) | |
| 36 | −{ | |
| 37 | − cycles_t ret; | |
| 38 | − | |
| 39 | − ret = ia64_getreg(_IA64_REG_AR_ITC); | |
| 40 | − return ret; | |
| 41 | −} | |
| 42 | −#define get_cycles get_cycles | |
| 43 | − | |
| 44 | −extern void ia64_cpu_local_tick (void); | |
| 45 | −extern unsigned long long ia64_native_sched_clock (void); | |
| 46 | − | |
| 47 | −#endif /* _ASM_IA64_TIMEX_H */ | |
| @@ -1,50 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_TLB_H | |
| 3 | −#define _ASM_IA64_TLB_H | |
| 4 | −/* | |
| 5 | − * Based on <asm-generic/tlb.h>. | |
| 6 | − * | |
| 7 | − * Copyright (C) 2002-2003 Hewlett-Packard Co | |
| 8 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 9 | − */ | |
| 10 | −/* | |
| 11 | − * Removing a translation from a page table (including TLB-shootdown) is a four-step | |
| 12 | − * procedure: | |
| 13 | − * | |
| 14 | − * (1) Flush (virtual) caches --- ensures virtual memory is coherent with kernel memory | |
| 15 | − * (this is a no-op on ia64). | |
| 16 | − * (2) Clear the relevant portions of the page-table | |
| 17 | − * (3) Flush the TLBs --- ensures that stale content is gone from CPU TLBs | |
| 18 | − * (4) Release the pages that were freed up in step (2). | |
| 19 | − * | |
| 20 | − * Note that the ordering of these steps is crucial to avoid races on MP machines. | |
| 21 | − * | |
| 22 | − * The Linux kernel defines several platform-specific hooks for TLB-shootdown. When | |
| 23 | − * unmapping a portion of the virtual address space, these hooks are called according to | |
| 24 | − * the following template: | |
| 25 | − * | |
| 26 | − * tlb <- tlb_gather_mmu(mm); // start unmap for address space MM | |
| 27 | − * { | |
| 28 | − * for each vma that needs a shootdown do { | |
| 29 | − * tlb_start_vma(tlb, vma); | |
| 30 | − * for each page-table-entry PTE that needs to be removed do { | |
| 31 | − * tlb_remove_tlb_entry(tlb, pte, address); | |
| 32 | − * if (pte refers to a normal page) { | |
| 33 | − * tlb_remove_page(tlb, page); | |
| 34 | − * } | |
| 35 | − * } | |
| 36 | − * tlb_end_vma(tlb, vma); | |
| 37 | − * } | |
| 38 | − * } | |
| 39 | − * tlb_finish_mmu(tlb); // finish unmap for address space MM | |
| 40 | − */ | |
| 41 | −#include <linux/mm.h> | |
| 42 | −#include <linux/pagemap.h> | |
| 43 | −#include <linux/swap.h> | |
| 44 | − | |
| 45 | −#include <asm/processor.h> | |
| 46 | −#include <asm/tlbflush.h> | |
| 47 | − | |
| 48 | −#include <asm-generic/tlb.h> | |
| 49 | − | |
| 50 | −#endif /* _ASM_IA64_TLB_H */ | |
| @@ -1,128 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_TLBFLUSH_H | |
| 3 | −#define _ASM_IA64_TLBFLUSH_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Copyright (C) 2002 Hewlett-Packard Co | |
| 7 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 8 | − */ | |
| 9 | − | |
| 10 | − | |
| 11 | −#include <linux/mm.h> | |
| 12 | − | |
| 13 | −#include <asm/intrinsics.h> | |
| 14 | −#include <asm/mmu_context.h> | |
| 15 | −#include <asm/page.h> | |
| 16 | − | |
| 17 | −struct ia64_tr_entry { | |
| 18 | − u64 ifa; | |
| 19 | − u64 itir; | |
| 20 | − u64 pte; | |
| 21 | − u64 rr; | |
| 22 | −}; /*Record for tr entry!*/ | |
| 23 | − | |
| 24 | −extern int ia64_itr_entry(u64 target_mask, u64 va, u64 pte, u64 log_size); | |
| 25 | −extern void ia64_ptr_entry(u64 target_mask, int slot); | |
| 26 | −extern struct ia64_tr_entry *ia64_idtrs[NR_CPUS]; | |
| 27 | − | |
| 28 | −/* | |
| 29 | − region register macros | |
| 30 | −*/ | |
| 31 | −#define RR_TO_VE(val) (((val) >> 0) & 0x0000000000000001) | |
| 32 | −#define RR_VE(val) (((val) & 0x0000000000000001) << 0) | |
| 33 | −#define RR_VE_MASK 0x0000000000000001L | |
| 34 | −#define RR_VE_SHIFT 0 | |
| 35 | −#define RR_TO_PS(val) (((val) >> 2) & 0x000000000000003f) | |
| 36 | −#define RR_PS(val) (((val) & 0x000000000000003f) << 2) | |
| 37 | −#define RR_PS_MASK 0x00000000000000fcL | |
| 38 | −#define RR_PS_SHIFT 2 | |
| 39 | −#define RR_RID_MASK 0x00000000ffffff00L | |
| 40 | −#define RR_TO_RID(val) ((val >> 8) & 0xffffff) | |
| 41 | − | |
| 42 | −/* | |
| 43 | − * Now for some TLB flushing routines. This is the kind of stuff that | |
| 44 | − * can be very expensive, so try to avoid them whenever possible. | |
| 45 | − */ | |
| 46 | −extern void setup_ptcg_sem(int max_purges, int from_palo); | |
| 47 | − | |
| 48 | −/* | |
| 49 | − * Flush everything (kernel mapping may also have changed due to | |
| 50 | − * vmalloc/vfree). | |
| 51 | − */ | |
| 52 | −extern void local_flush_tlb_all (void); | |
| 53 | − | |
| 54 | −#ifdef CONFIG_SMP | |
| 55 | − extern void smp_flush_tlb_all (void); | |
| 56 | − extern void smp_flush_tlb_mm (struct mm_struct *mm); | |
| 57 | − extern void smp_flush_tlb_cpumask (cpumask_t xcpumask); | |
| 58 | −# define flush_tlb_all() smp_flush_tlb_all() | |
| 59 | −#else | |
| 60 | −# define flush_tlb_all() local_flush_tlb_all() | |
| 61 | −# define smp_flush_tlb_cpumask(m) local_flush_tlb_all() | |
| 62 | −#endif | |
| 63 | − | |
| 64 | −static inline void | |
| 65 | −local_finish_flush_tlb_mm (struct mm_struct *mm) | |
| 66 | −{ | |
| 67 | − if (mm == current->active_mm) | |
| 68 | − activate_context(mm); | |
| 69 | −} | |
| 70 | − | |
| 71 | −/* | |
| 72 | − * Flush a specified user mapping. This is called, e.g., as a result of fork() and | |
| 73 | − * exit(). fork() ends up here because the copy-on-write mechanism needs to write-protect | |
| 74 | − * the PTEs of the parent task. | |
| 75 | − */ | |
| 76 | −static inline void | |
| 77 | −flush_tlb_mm (struct mm_struct *mm) | |
| 78 | −{ | |
| 79 | − if (!mm) | |
| 80 | − return; | |
| 81 | − | |
| 82 | − set_bit(mm->context, ia64_ctx.flushmap); | |
| 83 | − mm->context = 0; | |
| 84 | − | |
| 85 | − if (atomic_read(&mm->mm_users) == 0) | |
| 86 | − return; /* happens as a result of exit_mmap() */ | |
| 87 | − | |
| 88 | −#ifdef CONFIG_SMP | |
| 89 | − smp_flush_tlb_mm(mm); | |
| 90 | −#else | |
| 91 | − local_finish_flush_tlb_mm(mm); | |
| 92 | −#endif | |
| 93 | −} | |
| 94 | − | |
| 95 | −extern void flush_tlb_range (struct vm_area_struct *vma, unsigned long start, unsigned long end); | |
| 96 | − | |
| 97 | −/* | |
| 98 | − * Page-granular tlb flush. | |
| 99 | − */ | |
| 100 | −static inline void | |
| 101 | −flush_tlb_page (struct vm_area_struct *vma, unsigned long addr) | |
| 102 | −{ | |
| 103 | −#ifdef CONFIG_SMP | |
| 104 | − flush_tlb_range(vma, (addr & PAGE_MASK), (addr & PAGE_MASK) + PAGE_SIZE); | |
| 105 | −#else | |
| 106 | − if (vma->vm_mm == current->active_mm) | |
| 107 | − ia64_ptcl(addr, (PAGE_SHIFT << 2)); | |
| 108 | − else | |
| 109 | − vma->vm_mm->context = 0; | |
| 110 | −#endif | |
| 111 | −} | |
| 112 | − | |
| 113 | −/* | |
| 114 | − * Flush the local TLB. Invoked from another cpu using an IPI. | |
| 115 | − */ | |
| 116 | −#ifdef CONFIG_SMP | |
| 117 | −void smp_local_flush_tlb(void); | |
| 118 | −#else | |
| 119 | −#define smp_local_flush_tlb() | |
| 120 | −#endif | |
| 121 | − | |
| 122 | −static inline void flush_tlb_kernel_range(unsigned long start, | |
| 123 | − unsigned long end) | |
| 124 | −{ | |
| 125 | − flush_tlb_all(); /* XXX fix me */ | |
| 126 | −} | |
| 127 | − | |
| 128 | −#endif /* _ASM_IA64_TLBFLUSH_H */ | |
| @@ -1,56 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0-or-later */ | |
| 2 | −/* | |
| 3 | − * Copyright (C) 2002, Erich Focht, NEC | |
| 4 | − * | |
| 5 | − * All rights reserved. | |
| 6 | − */ | |
| 7 | −#ifndef _ASM_IA64_TOPOLOGY_H | |
| 8 | −#define _ASM_IA64_TOPOLOGY_H | |
| 9 | − | |
| 10 | −#include <asm/acpi.h> | |
| 11 | −#include <asm/numa.h> | |
| 12 | −#include <asm/smp.h> | |
| 13 | − | |
| 14 | −#ifdef CONFIG_NUMA | |
| 15 | − | |
| 16 | −/* Nodes w/o CPUs are preferred for memory allocations, see build_zonelists */ | |
| 17 | −#define PENALTY_FOR_NODE_WITH_CPUS 255 | |
| 18 | − | |
| 19 | −/* | |
| 20 | − * Nodes within this distance are eligible for reclaim by zone_reclaim() when | |
| 21 | − * zone_reclaim_mode is enabled. | |
| 22 | − */ | |
| 23 | −#define RECLAIM_DISTANCE 15 | |
| 24 | − | |
| 25 | −/* | |
| 26 | − * Returns a bitmask of CPUs on Node 'node'. | |
| 27 | − */ | |
| 28 | −#define cpumask_of_node(node) ((node) == -1 ? \ | |
| 29 | − cpu_all_mask : \ | |
| 30 | − &node_to_cpu_mask[node]) | |
| 31 | − | |
| 32 | −/* | |
| 33 | − * Determines the node for a given pci bus | |
| 34 | − */ | |
| 35 | −#define pcibus_to_node(bus) PCI_CONTROLLER(bus)->node | |
| 36 | − | |
| 37 | −void build_cpu_to_node_map(void); | |
| 38 | − | |
| 39 | −#endif /* CONFIG_NUMA */ | |
| 40 | − | |
| 41 | −#ifdef CONFIG_SMP | |
| 42 | −#define topology_physical_package_id(cpu) (cpu_data(cpu)->socket_id) | |
| 43 | −#define topology_core_id(cpu) (cpu_data(cpu)->core_id) | |
| 44 | −#define topology_core_cpumask(cpu) (&cpu_core_map[cpu]) | |
| 45 | −#define topology_sibling_cpumask(cpu) (&per_cpu(cpu_sibling_map, cpu)) | |
| 46 | −#endif | |
| 47 | − | |
| 48 | −extern void arch_fix_phys_package_id(int num, u32 slot); | |
| 49 | − | |
| 50 | −#define cpumask_of_pcibus(bus) (pcibus_to_node(bus) == -1 ? \ | |
| 51 | − cpu_all_mask : \ | |
| 52 | − cpumask_of_node(pcibus_to_node(bus))) | |
| 53 | − | |
| 54 | −#include <asm-generic/topology.h> | |
| 55 | − | |
| 56 | −#endif /* _ASM_IA64_TOPOLOGY_H */ | |
| @@ -1,32 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −/* | |
| 3 | − * This file is never included by application software unless explicitly | |
| 4 | − * requested (e.g., via linux/types.h) in which case the application is | |
| 5 | − * Linux specific so (user-) name space pollution is not a major issue. | |
| 6 | − * However, for interoperability, libraries still need to be careful to | |
| 7 | − * avoid naming clashes. | |
| 8 | − * | |
| 9 | − * Based on <asm-alpha/types.h>. | |
| 10 | − * | |
| 11 | − * Modified 1998-2000, 2002 | |
| 12 | − * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co | |
| 13 | − */ | |
| 14 | −#ifndef _ASM_IA64_TYPES_H | |
| 15 | −#define _ASM_IA64_TYPES_H | |
| 16 | − | |
| 17 | −#include <asm-generic/int-ll64.h> | |
| 18 | −#include <uapi/asm/types.h> | |
| 19 | − | |
| 20 | −#ifdef __ASSEMBLY__ | |
| 21 | −#else | |
| 22 | −/* | |
| 23 | − * These aren't exported outside the kernel to avoid name space clashes | |
| 24 | − */ | |
| 25 | − | |
| 26 | −struct fnptr { | |
| 27 | − unsigned long ip; | |
| 28 | − unsigned long gp; | |
| 29 | −}; | |
| 30 | − | |
| 31 | −#endif /* !__ASSEMBLY__ */ | |
| 32 | −#endif /* _ASM_IA64_TYPES_H */ | |
| @@ -1,265 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_UACCESS_H | |
| 3 | −#define _ASM_IA64_UACCESS_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * This file defines various macros to transfer memory areas across | |
| 7 | − * the user/kernel boundary. This needs to be done carefully because | |
| 8 | − * this code is executed in kernel mode and uses user-specified | |
| 9 | − * addresses. Thus, we need to be careful not to let the user to | |
| 10 | − * trick us into accessing kernel memory that would normally be | |
| 11 | − * inaccessible. This code is also fairly performance sensitive, | |
| 12 | − * so we want to spend as little time doing safety checks as | |
| 13 | − * possible. | |
| 14 | − * | |
| 15 | − * To make matters a bit more interesting, these macros sometimes also | |
| 16 | − * called from within the kernel itself, in which case the address | |
| 17 | − * validity check must be skipped. The get_fs() macro tells us what | |
| 18 | − * to do: if get_fs()==USER_DS, checking is performed, if | |
| 19 | − * get_fs()==KERNEL_DS, checking is bypassed. | |
| 20 | − * | |
| 21 | − * Note that even if the memory area specified by the user is in a | |
| 22 | − * valid address range, it is still possible that we'll get a page | |
| 23 | − * fault while accessing it. This is handled by filling out an | |
| 24 | − * exception handler fixup entry for each instruction that has the | |
| 25 | − * potential to fault. When such a fault occurs, the page fault | |
| 26 | − * handler checks to see whether the faulting instruction has a fixup | |
| 27 | − * associated and, if so, sets r8 to -EFAULT and clears r9 to 0 and | |
| 28 | − * then resumes execution at the continuation point. | |
| 29 | − * | |
| 30 | − * Based on <asm-alpha/uaccess.h>. | |
| 31 | − * | |
| 32 | − * Copyright (C) 1998, 1999, 2001-2004 Hewlett-Packard Co | |
| 33 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 34 | − */ | |
| 35 | − | |
| 36 | −#include <linux/compiler.h> | |
| 37 | −#include <linux/page-flags.h> | |
| 38 | − | |
| 39 | −#include <asm/intrinsics.h> | |
| 40 | −#include <linux/pgtable.h> | |
| 41 | −#include <asm/io.h> | |
| 42 | −#include <asm/extable.h> | |
| 43 | − | |
| 44 | −/* | |
| 45 | − * When accessing user memory, we need to make sure the entire area really is | |
| 46 | − * in user-level space. We also need to make sure that the address doesn't | |
| 47 | − * point inside the virtually mapped linear page table. | |
| 48 | − */ | |
| 49 | −static inline int __access_ok(const void __user *p, unsigned long size) | |
| 50 | −{ | |
| 51 | − unsigned long limit = TASK_SIZE; | |
| 52 | − unsigned long addr = (unsigned long)p; | |
| 53 | − | |
| 54 | − return likely((size <= limit) && (addr <= (limit - size)) && | |
| 55 | − likely(REGION_OFFSET(addr) < RGN_MAP_LIMIT)); | |
| 56 | −} | |
| 57 | −#define __access_ok __access_ok | |
| 58 | −#include <asm-generic/access_ok.h> | |
| 59 | − | |
| 60 | −/* | |
| 61 | − * These are the main single-value transfer routines. They automatically | |
| 62 | − * use the right size if we just have the right pointer type. | |
| 63 | − * | |
| 64 | − * Careful to not | |
| 65 | − * (a) re-use the arguments for side effects (sizeof/typeof is ok) | |
| 66 | − * (b) require any knowledge of processes at this stage | |
| 67 | − */ | |
| 68 | −#define put_user(x, ptr) __put_user_check((__typeof__(*(ptr))) (x), (ptr), sizeof(*(ptr))) | |
| 69 | −#define get_user(x, ptr) __get_user_check((x), (ptr), sizeof(*(ptr))) | |
| 70 | − | |
| 71 | −/* | |
| 72 | − * The "__xxx" versions do not do address space checking, useful when | |
| 73 | − * doing multiple accesses to the same area (the programmer has to do the | |
| 74 | − * checks by hand with "access_ok()") | |
| 75 | − */ | |
| 76 | −#define __put_user(x, ptr) __put_user_nocheck((__typeof__(*(ptr))) (x), (ptr), sizeof(*(ptr))) | |
| 77 | −#define __get_user(x, ptr) __get_user_nocheck((x), (ptr), sizeof(*(ptr))) | |
| 78 | − | |
| 79 | −#ifdef ASM_SUPPORTED | |
| 80 | − struct __large_struct { unsigned long buf[100]; }; | |
| 81 | −# define __m(x) (*(struct __large_struct __user *)(x)) | |
| 82 | − | |
| 83 | −/* We need to declare the __ex_table section before we can use it in .xdata. */ | |
| 84 | −asm (".section \"__ex_table\", \"a\"\n\t.previous"); | |
| 85 | − | |
| 86 | −# define __get_user_size(val, addr, n, err) \ | |
| 87 | −do { \ | |
| 88 | − register long __gu_r8 asm ("r8") = 0; \ | |
| 89 | − register long __gu_r9 asm ("r9"); \ | |
| 90 | − asm ("\n[1:]\tld"#n" %0=%2%P2\t// %0 and %1 get overwritten by exception handler\n" \ | |
| 91 | − "\t.xdata4 \"__ex_table\", 1b-., 1f-.+4\n" \ | |
| 92 | − "[1:]" \ | |
| 93 | − : "=r"(__gu_r9), "=r"(__gu_r8) : "m"(__m(addr)), "1"(__gu_r8)); \ | |
| 94 | − (err) = __gu_r8; \ | |
| 95 | − (val) = __gu_r9; \ | |
| 96 | −} while (0) | |
| 97 | − | |
| 98 | −/* | |
| 99 | − * The "__put_user_size()" macro tells gcc it reads from memory instead of writing it. This | |
| 100 | − * is because they do not write to any memory gcc knows about, so there are no aliasing | |
| 101 | − * issues. | |
| 102 | − */ | |
| 103 | −# define __put_user_size(val, addr, n, err) \ | |
| 104 | −do { \ | |
| 105 | − register long __pu_r8 asm ("r8") = 0; \ | |
| 106 | − asm volatile ("\n[1:]\tst"#n" %1=%r2%P1\t// %0 gets overwritten by exception handler\n" \ | |
| 107 | − "\t.xdata4 \"__ex_table\", 1b-., 1f-.\n" \ | |
| 108 | − "[1:]" \ | |
| 109 | − : "=r"(__pu_r8) : "m"(__m(addr)), "rO"(val), "0"(__pu_r8)); \ | |
| 110 | − (err) = __pu_r8; \ | |
| 111 | −} while (0) | |
| 112 | − | |
| 113 | −#else /* !ASM_SUPPORTED */ | |
| 114 | −# define RELOC_TYPE 2 /* ip-rel */ | |
| 115 | −# define __get_user_size(val, addr, n, err) \ | |
| 116 | −do { \ | |
| 117 | − __ld_user("__ex_table", (unsigned long) addr, n, RELOC_TYPE); \ | |
| 118 | − (err) = ia64_getreg(_IA64_REG_R8); \ | |
| 119 | − (val) = ia64_getreg(_IA64_REG_R9); \ | |
| 120 | −} while (0) | |
| 121 | −# define __put_user_size(val, addr, n, err) \ | |
| 122 | −do { \ | |
| 123 | − __st_user("__ex_table", (unsigned long) addr, n, RELOC_TYPE, \ | |
| 124 | − (__force unsigned long) (val)); \ | |
| 125 | − (err) = ia64_getreg(_IA64_REG_R8); \ | |
| 126 | −} while (0) | |
| 127 | −#endif /* !ASM_SUPPORTED */ | |
| 128 | − | |
| 129 | −extern void __get_user_unknown (void); | |
| 130 | − | |
| 131 | −/* | |
| 132 | − * Evaluating arguments X, PTR, SIZE, and SEGMENT may involve subroutine-calls, which | |
| 133 | − * could clobber r8 and r9 (among others). Thus, be careful not to evaluate it while | |
| 134 | − * using r8/r9. | |
| 135 | − */ | |
| 136 | −#define __do_get_user(check, x, ptr, size) \ | |
| 137 | −({ \ | |
| 138 | − const __typeof__(*(ptr)) __user *__gu_ptr = (ptr); \ | |
| 139 | − __typeof__ (size) __gu_size = (size); \ | |
| 140 | − long __gu_err = -EFAULT; \ | |
| 141 | − unsigned long __gu_val = 0; \ | |
| 142 | − if (!check || __access_ok(__gu_ptr, size)) \ | |
| 143 | − switch (__gu_size) { \ | |
| 144 | − case 1: __get_user_size(__gu_val, __gu_ptr, 1, __gu_err); break; \ | |
| 145 | − case 2: __get_user_size(__gu_val, __gu_ptr, 2, __gu_err); break; \ | |
| 146 | − case 4: __get_user_size(__gu_val, __gu_ptr, 4, __gu_err); break; \ | |
| 147 | − case 8: __get_user_size(__gu_val, __gu_ptr, 8, __gu_err); break; \ | |
| 148 | − default: __get_user_unknown(); break; \ | |
| 149 | − } \ | |
| 150 | − (x) = (__force __typeof__(*(__gu_ptr))) __gu_val; \ | |
| 151 | − __gu_err; \ | |
| 152 | −}) | |
| 153 | − | |
| 154 | −#define __get_user_nocheck(x, ptr, size) __do_get_user(0, x, ptr, size) | |
| 155 | −#define __get_user_check(x, ptr, size) __do_get_user(1, x, ptr, size) | |
| 156 | − | |
| 157 | −extern void __put_user_unknown (void); | |
| 158 | − | |
| 159 | −/* | |
| 160 | − * Evaluating arguments X, PTR, SIZE, and SEGMENT may involve subroutine-calls, which | |
| 161 | − * could clobber r8 (among others). Thus, be careful not to evaluate them while using r8. | |
| 162 | − */ | |
| 163 | −#define __do_put_user(check, x, ptr, size) \ | |
| 164 | −({ \ | |
| 165 | − __typeof__ (x) __pu_x = (x); \ | |
| 166 | − __typeof__ (*(ptr)) __user *__pu_ptr = (ptr); \ | |
| 167 | − __typeof__ (size) __pu_size = (size); \ | |
| 168 | − long __pu_err = -EFAULT; \ | |
| 169 | − \ | |
| 170 | − if (!check || __access_ok(__pu_ptr, __pu_size)) \ | |
| 171 | − switch (__pu_size) { \ | |
| 172 | − case 1: __put_user_size(__pu_x, __pu_ptr, 1, __pu_err); break; \ | |
| 173 | − case 2: __put_user_size(__pu_x, __pu_ptr, 2, __pu_err); break; \ | |
| 174 | − case 4: __put_user_size(__pu_x, __pu_ptr, 4, __pu_err); break; \ | |
| 175 | − case 8: __put_user_size(__pu_x, __pu_ptr, 8, __pu_err); break; \ | |
| 176 | − default: __put_user_unknown(); break; \ | |
| 177 | − } \ | |
| 178 | − __pu_err; \ | |
| 179 | −}) | |
| 180 | − | |
| 181 | −#define __put_user_nocheck(x, ptr, size) __do_put_user(0, x, ptr, size) | |
| 182 | −#define __put_user_check(x, ptr, size) __do_put_user(1, x, ptr, size) | |
| 183 | − | |
| 184 | −/* | |
| 185 | − * Complex access routines | |
| 186 | − */ | |
| 187 | −extern unsigned long __must_check __copy_user (void __user *to, const void __user *from, | |
| 188 | − unsigned long count); | |
| 189 | − | |
| 190 | −static inline unsigned long | |
| 191 | −raw_copy_to_user(void __user *to, const void *from, unsigned long count) | |
| 192 | −{ | |
| 193 | − return __copy_user(to, (__force void __user *) from, count); | |
| 194 | −} | |
| 195 | − | |
| 196 | −static inline unsigned long | |
| 197 | −raw_copy_from_user(void *to, const void __user *from, unsigned long count) | |
| 198 | −{ | |
| 199 | − return __copy_user((__force void __user *) to, from, count); | |
| 200 | −} | |
| 201 | − | |
| 202 | −#define INLINE_COPY_FROM_USER | |
| 203 | −#define INLINE_COPY_TO_USER | |
| 204 | − | |
| 205 | −extern unsigned long __do_clear_user (void __user *, unsigned long); | |
| 206 | − | |
| 207 | −#define __clear_user(to, n) __do_clear_user(to, n) | |
| 208 | − | |
| 209 | −#define clear_user(to, n) \ | |
| 210 | −({ \ | |
| 211 | − unsigned long __cu_len = (n); \ | |
| 212 | − if (__access_ok(to, __cu_len)) \ | |
| 213 | − __cu_len = __do_clear_user(to, __cu_len); \ | |
| 214 | − __cu_len; \ | |
| 215 | −}) | |
| 216 | − | |
| 217 | − | |
| 218 | −/* | |
| 219 | − * Returns: -EFAULT if exception before terminator, N if the entire buffer filled, else | |
| 220 | − * strlen. | |
| 221 | − */ | |
| 222 | −extern long __must_check __strncpy_from_user (char *to, const char __user *from, long to_len); | |
| 223 | − | |
| 224 | −#define strncpy_from_user(to, from, n) \ | |
| 225 | −({ \ | |
| 226 | − const char __user * __sfu_from = (from); \ | |
| 227 | − long __sfu_ret = -EFAULT; \ | |
| 228 | − if (__access_ok(__sfu_from, 0)) \ | |
| 229 | − __sfu_ret = __strncpy_from_user((to), __sfu_from, (n)); \ | |
| 230 | − __sfu_ret; \ | |
| 231 | −}) | |
| 232 | − | |
| 233 | −/* | |
| 234 | − * Returns: 0 if exception before NUL or reaching the supplied limit | |
| 235 | − * (N), a value greater than N if the limit would be exceeded, else | |
| 236 | − * strlen. | |
| 237 | − */ | |
| 238 | −extern unsigned long __strnlen_user (const char __user *, long); | |
| 239 | − | |
| 240 | −#define strnlen_user(str, len) \ | |
| 241 | −({ \ | |
| 242 | − const char __user *__su_str = (str); \ | |
| 243 | − unsigned long __su_ret = 0; \ | |
| 244 | − if (__access_ok(__su_str, 0)) \ | |
| 245 | − __su_ret = __strnlen_user(__su_str, len); \ | |
| 246 | − __su_ret; \ | |
| 247 | −}) | |
| 248 | − | |
| 249 | −#define ARCH_HAS_TRANSLATE_MEM_PTR 1 | |
| 250 | −static __inline__ void * | |
| 251 | −xlate_dev_mem_ptr(phys_addr_t p) | |
| 252 | −{ | |
| 253 | − struct page *page; | |
| 254 | − void *ptr; | |
| 255 | − | |
| 256 | − page = pfn_to_page(p >> PAGE_SHIFT); | |
| 257 | − if (PageUncached(page)) | |
| 258 | − ptr = (void *)p + __IA64_UNCACHED_OFFSET; | |
| 259 | − else | |
| 260 | − ptr = __va(p); | |
| 261 | − | |
| 262 | − return ptr; | |
| 263 | −} | |
| 264 | − | |
| 265 | −#endif /* _ASM_IA64_UACCESS_H */ | |
| @@ -1,9 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0-only */ | |
| 2 | −/* | |
| 3 | − * Copyright (C) 2001-2008 Silicon Graphics, Inc. All rights reserved. | |
| 4 | − * | |
| 5 | − * Prototypes for the uncached page allocator | |
| 6 | − */ | |
| 7 | − | |
| 8 | −extern unsigned long uncached_alloc_page(int starting_nid, int n_pages); | |
| 9 | −extern void uncached_free_page(unsigned long uc_addr, int n_pages); | |
| @@ -1,38 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −/* | |
| 3 | − * IA-64 Linux syscall numbers and inline-functions. | |
| 4 | − * | |
| 5 | − * Copyright (C) 1998-2005 Hewlett-Packard Co | |
| 6 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 7 | − */ | |
| 8 | −#ifndef _ASM_IA64_UNISTD_H | |
| 9 | −#define _ASM_IA64_UNISTD_H | |
| 10 | − | |
| 11 | −#include <uapi/asm/unistd.h> | |
| 12 | − | |
| 13 | −#define NR_syscalls __NR_syscalls /* length of syscall table */ | |
| 14 | − | |
| 15 | −#define __ARCH_WANT_NEW_STAT | |
| 16 | −#define __ARCH_WANT_SYS_UTIME | |
| 17 | − | |
| 18 | −#if !defined(__ASSEMBLY__) && !defined(ASSEMBLER) | |
| 19 | − | |
| 20 | −#include <linux/types.h> | |
| 21 | −#include <linux/linkage.h> | |
| 22 | −#include <linux/compiler.h> | |
| 23 | − | |
| 24 | −extern long __ia64_syscall (long a0, long a1, long a2, long a3, long a4, long nr); | |
| 25 | − | |
| 26 | −asmlinkage unsigned long sys_mmap( | |
| 27 | − unsigned long addr, unsigned long len, | |
| 28 | − int prot, int flags, | |
| 29 | − int fd, long off); | |
| 30 | −asmlinkage unsigned long sys_mmap2( | |
| 31 | − unsigned long addr, unsigned long len, | |
| 32 | − int prot, int flags, | |
| 33 | − int fd, long pgoff); | |
| 34 | −struct pt_regs; | |
| 35 | −asmlinkage long sys_ia64_pipe(void); | |
| 36 | − | |
| 37 | −#endif /* !__ASSEMBLY__ */ | |
| 38 | −#endif /* _ASM_IA64_UNISTD_H */ | |
| @@ -1,234 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_UNWIND_H | |
| 3 | −#define _ASM_IA64_UNWIND_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Copyright (C) 1999-2000, 2003 Hewlett-Packard Co | |
| 7 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 8 | − * | |
| 9 | − * A simple API for unwinding kernel stacks. This is used for | |
| 10 | − * debugging and error reporting purposes. The kernel doesn't need | |
| 11 | − * full-blown stack unwinding with all the bells and whitles, so there | |
| 12 | − * is not much point in implementing the full IA-64 unwind API (though | |
| 13 | − * it would of course be possible to implement the kernel API on top | |
| 14 | − * of it). | |
| 15 | − */ | |
| 16 | − | |
| 17 | −struct task_struct; /* forward declaration */ | |
| 18 | −struct switch_stack; /* forward declaration */ | |
| 19 | − | |
| 20 | −enum unw_application_register { | |
| 21 | − UNW_AR_BSP, | |
| 22 | − UNW_AR_BSPSTORE, | |
| 23 | − UNW_AR_PFS, | |
| 24 | − UNW_AR_RNAT, | |
| 25 | − UNW_AR_UNAT, | |
| 26 | − UNW_AR_LC, | |
| 27 | − UNW_AR_EC, | |
| 28 | − UNW_AR_FPSR, | |
| 29 | − UNW_AR_RSC, | |
| 30 | − UNW_AR_CCV, | |
| 31 | − UNW_AR_CSD, | |
| 32 | − UNW_AR_SSD | |
| 33 | −}; | |
| 34 | − | |
| 35 | −/* | |
| 36 | − * The following declarations are private to the unwind | |
| 37 | − * implementation: | |
| 38 | − */ | |
| 39 | − | |
| 40 | −struct unw_stack { | |
| 41 | − unsigned long limit; | |
| 42 | − unsigned long top; | |
| 43 | −}; | |
| 44 | − | |
| 45 | −#define UNW_FLAG_INTERRUPT_FRAME (1UL << 0) | |
| 46 | − | |
| 47 | −/* | |
| 48 | − * No user of this module should every access this structure directly | |
| 49 | − * as it is subject to change. It is declared here solely so we can | |
| 50 | − * use automatic variables. | |
| 51 | − */ | |
| 52 | −struct unw_frame_info { | |
| 53 | − struct unw_stack regstk; | |
| 54 | − struct unw_stack memstk; | |
| 55 | − unsigned int flags; | |
| 56 | − short hint; | |
| 57 | − short prev_script; | |
| 58 | − | |
| 59 | − /* current frame info: */ | |
| 60 | − unsigned long bsp; /* backing store pointer value */ | |
| 61 | − unsigned long sp; /* stack pointer value */ | |
| 62 | − unsigned long psp; /* previous sp value */ | |
| 63 | − unsigned long ip; /* instruction pointer value */ | |
| 64 | − unsigned long pr; /* current predicate values */ | |
| 65 | − unsigned long *cfm_loc; /* cfm save location (or NULL) */ | |
| 66 | − unsigned long pt; /* struct pt_regs location */ | |
| 67 | − | |
| 68 | − struct task_struct *task; | |
| 69 | − struct switch_stack *sw; | |
| 70 | − | |
| 71 | − /* preserved state: */ | |
| 72 | − unsigned long *bsp_loc; /* previous bsp save location */ | |
| 73 | − unsigned long *bspstore_loc; | |
| 74 | − unsigned long *pfs_loc; | |
| 75 | − unsigned long *rnat_loc; | |
| 76 | − unsigned long *rp_loc; | |
| 77 | − unsigned long *pri_unat_loc; | |
| 78 | − unsigned long *unat_loc; | |
| 79 | − unsigned long *pr_loc; | |
| 80 | − unsigned long *lc_loc; | |
| 81 | − unsigned long *fpsr_loc; | |
| 82 | − struct unw_ireg { | |
| 83 | − unsigned long *loc; | |
| 84 | − struct unw_ireg_nat { | |
| 85 | − unsigned long type : 3; /* enum unw_nat_type */ | |
| 86 | − signed long off : 61; /* NaT word is at loc+nat.off */ | |
| 87 | − } nat; | |
| 88 | − } r4, r5, r6, r7; | |
| 89 | − unsigned long *b1_loc, *b2_loc, *b3_loc, *b4_loc, *b5_loc; | |
| 90 | − struct ia64_fpreg *f2_loc, *f3_loc, *f4_loc, *f5_loc, *fr_loc[16]; | |
| 91 | −}; | |
| 92 | − | |
| 93 | −/* | |
| 94 | − * The official API follows below: | |
| 95 | − */ | |
| 96 | − | |
| 97 | −struct unw_table_entry { | |
| 98 | − u64 start_offset; | |
| 99 | − u64 end_offset; | |
| 100 | − u64 info_offset; | |
| 101 | −}; | |
| 102 | − | |
| 103 | −/* | |
| 104 | − * Initialize unwind support. | |
| 105 | − */ | |
| 106 | −extern void unw_init (void); | |
| 107 | − | |
| 108 | −extern void *unw_add_unwind_table (const char *name, unsigned long segment_base, unsigned long gp, | |
| 109 | − const void *table_start, const void *table_end); | |
| 110 | − | |
| 111 | −extern void unw_remove_unwind_table (void *handle); | |
| 112 | − | |
| 113 | −/* | |
| 114 | − * Prepare to unwind blocked task t. | |
| 115 | − */ | |
| 116 | −extern void unw_init_from_blocked_task (struct unw_frame_info *info, struct task_struct *t); | |
| 117 | − | |
| 118 | −extern void unw_init_frame_info (struct unw_frame_info *info, struct task_struct *t, | |
| 119 | − struct switch_stack *sw); | |
| 120 | − | |
| 121 | −/* | |
| 122 | − * Prepare to unwind the currently running thread. | |
| 123 | − */ | |
| 124 | −extern void unw_init_running (void (*callback)(struct unw_frame_info *info, void *arg), void *arg); | |
| 125 | − | |
| 126 | −/* | |
| 127 | − * Unwind to previous to frame. Returns 0 if successful, negative | |
| 128 | − * number in case of an error. | |
| 129 | − */ | |
| 130 | −extern int unw_unwind (struct unw_frame_info *info); | |
| 131 | − | |
| 132 | −/* | |
| 133 | − * Unwind until the return pointer is in user-land (or until an error | |
| 134 | − * occurs). Returns 0 if successful, negative number in case of | |
| 135 | − * error. | |
| 136 | − */ | |
| 137 | −extern int unw_unwind_to_user (struct unw_frame_info *info); | |
| 138 | − | |
| 139 | −#define unw_is_intr_frame(info) (((info)->flags & UNW_FLAG_INTERRUPT_FRAME) != 0) | |
| 140 | − | |
| 141 | −static inline int | |
| 142 | −unw_get_ip (struct unw_frame_info *info, unsigned long *valp) | |
| 143 | −{ | |
| 144 | − *valp = (info)->ip; | |
| 145 | − return 0; | |
| 146 | −} | |
| 147 | − | |
| 148 | −static inline int | |
| 149 | −unw_get_sp (struct unw_frame_info *info, unsigned long *valp) | |
| 150 | −{ | |
| 151 | − *valp = (info)->sp; | |
| 152 | − return 0; | |
| 153 | −} | |
| 154 | − | |
| 155 | −static inline int | |
| 156 | −unw_get_psp (struct unw_frame_info *info, unsigned long *valp) | |
| 157 | −{ | |
| 158 | − *valp = (info)->psp; | |
| 159 | − return 0; | |
| 160 | −} | |
| 161 | − | |
| 162 | −static inline int | |
| 163 | −unw_get_bsp (struct unw_frame_info *info, unsigned long *valp) | |
| 164 | −{ | |
| 165 | − *valp = (info)->bsp; | |
| 166 | − return 0; | |
| 167 | −} | |
| 168 | − | |
| 169 | −static inline int | |
| 170 | −unw_get_cfm (struct unw_frame_info *info, unsigned long *valp) | |
| 171 | −{ | |
| 172 | − *valp = *(info)->cfm_loc; | |
| 173 | − return 0; | |
| 174 | −} | |
| 175 | − | |
| 176 | −static inline int | |
| 177 | −unw_set_cfm (struct unw_frame_info *info, unsigned long val) | |
| 178 | −{ | |
| 179 | − *(info)->cfm_loc = val; | |
| 180 | − return 0; | |
| 181 | −} | |
| 182 | − | |
| 183 | −static inline int | |
| 184 | −unw_get_rp (struct unw_frame_info *info, unsigned long *val) | |
| 185 | −{ | |
| 186 | − if (!info->rp_loc) | |
| 187 | − return -1; | |
| 188 | − *val = *info->rp_loc; | |
| 189 | − return 0; | |
| 190 | −} | |
| 191 | − | |
| 192 | −extern int unw_access_gr (struct unw_frame_info *, int, unsigned long *, char *, int); | |
| 193 | −extern int unw_access_br (struct unw_frame_info *, int, unsigned long *, int); | |
| 194 | −extern int unw_access_fr (struct unw_frame_info *, int, struct ia64_fpreg *, int); | |
| 195 | −extern int unw_access_ar (struct unw_frame_info *, int, unsigned long *, int); | |
| 196 | −extern int unw_access_pr (struct unw_frame_info *, unsigned long *, int); | |
| 197 | − | |
| 198 | −static inline int | |
| 199 | −unw_set_gr (struct unw_frame_info *i, int n, unsigned long v, char nat) | |
| 200 | −{ | |
| 201 | − return unw_access_gr(i, n, &v, &nat, 1); | |
| 202 | −} | |
| 203 | − | |
| 204 | −static inline int | |
| 205 | −unw_set_br (struct unw_frame_info *i, int n, unsigned long v) | |
| 206 | −{ | |
| 207 | − return unw_access_br(i, n, &v, 1); | |
| 208 | −} | |
| 209 | − | |
| 210 | −static inline int | |
| 211 | −unw_set_fr (struct unw_frame_info *i, int n, struct ia64_fpreg v) | |
| 212 | −{ | |
| 213 | − return unw_access_fr(i, n, &v, 1); | |
| 214 | −} | |
| 215 | − | |
| 216 | −static inline int | |
| 217 | −unw_set_ar (struct unw_frame_info *i, int n, unsigned long v) | |
| 218 | −{ | |
| 219 | − return unw_access_ar(i, n, &v, 1); | |
| 220 | −} | |
| 221 | − | |
| 222 | −static inline int | |
| 223 | −unw_set_pr (struct unw_frame_info *i, unsigned long v) | |
| 224 | −{ | |
| 225 | − return unw_access_pr(i, &v, 1); | |
| 226 | −} | |
| 227 | − | |
| 228 | −#define unw_get_gr(i,n,v,nat) unw_access_gr(i,n,v,nat,0) | |
| 229 | −#define unw_get_br(i,n,v) unw_access_br(i,n,v,0) | |
| 230 | −#define unw_get_fr(i,n,v) unw_access_fr(i,n,v,0) | |
| 231 | −#define unw_get_ar(i,n,v) unw_access_ar(i,n,v,0) | |
| 232 | −#define unw_get_pr(i,v) unw_access_pr(i,v,0) | |
| 233 | − | |
| 234 | −#endif /* _ASM_UNWIND_H */ | |
| @@ -1,53 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_USER_H | |
| 3 | −#define _ASM_IA64_USER_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Core file format: The core file is written in such a way that gdb | |
| 7 | − * can understand it and provide useful information to the user (under | |
| 8 | − * linux we use the `trad-core' bfd). The file contents are as | |
| 9 | − * follows: | |
| 10 | − * | |
| 11 | − * upage: 1 page consisting of a user struct that tells gdb | |
| 12 | − * what is present in the file. Directly after this is a | |
| 13 | − * copy of the task_struct, which is currently not used by gdb, | |
| 14 | − * but it may come in handy at some point. All of the registers | |
| 15 | − * are stored as part of the upage. The upage should always be | |
| 16 | − * only one page long. | |
| 17 | − * data: The data segment follows next. We use current->end_text to | |
| 18 | − * current->brk to pick up all of the user variables, plus any memory | |
| 19 | − * that may have been sbrk'ed. No attempt is made to determine if a | |
| 20 | − * page is demand-zero or if a page is totally unused, we just cover | |
| 21 | − * the entire range. All of the addresses are rounded in such a way | |
| 22 | − * that an integral number of pages is written. | |
| 23 | − * stack: We need the stack information in order to get a meaningful | |
| 24 | − * backtrace. We need to write the data from usp to | |
| 25 | − * current->start_stack, so we round each of these in order to be able | |
| 26 | − * to write an integer number of pages. | |
| 27 | − * | |
| 28 | − * Modified 1998, 1999, 2001 | |
| 29 | − * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co | |
| 30 | − */ | |
| 31 | − | |
| 32 | −#include <linux/ptrace.h> | |
| 33 | −#include <linux/types.h> | |
| 34 | − | |
| 35 | −#include <asm/page.h> | |
| 36 | − | |
| 37 | −#define EF_SIZE 3072 /* XXX fix me */ | |
| 38 | − | |
| 39 | −struct user { | |
| 40 | − unsigned long regs[EF_SIZE/8+32]; /* integer and fp regs */ | |
| 41 | − size_t u_tsize; /* text size (pages) */ | |
| 42 | − size_t u_dsize; /* data size (pages) */ | |
| 43 | − size_t u_ssize; /* stack size (pages) */ | |
| 44 | − unsigned long start_code; /* text starting address */ | |
| 45 | − unsigned long start_data; /* data starting address */ | |
| 46 | − unsigned long start_stack; /* stack starting address */ | |
| 47 | − long int signal; /* signal causing core dump */ | |
| 48 | − unsigned long u_ar0; /* help gdb find registers */ | |
| 49 | − unsigned long magic; /* identifies a core file */ | |
| 50 | − char u_comm[32]; /* user command name */ | |
| 51 | −}; | |
| 52 | − | |
| 53 | −#endif /* _ASM_IA64_USER_H */ | |
| @@ -1,12 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_USTACK_H | |
| 3 | −#define _ASM_IA64_USTACK_H | |
| 4 | − | |
| 5 | −#include <asm/page.h> | |
| 6 | −#include <uapi/asm/ustack.h> | |
| 7 | − | |
| 8 | −/* The absolute hard limit for stack size is 1/2 of the mappable space in the region */ | |
| 9 | −#define MAX_USER_STACK_SIZE (RGN_MAP_LIMIT/2) | |
| 10 | −#define STACK_TOP (0x6000000000000000UL + RGN_MAP_LIMIT) | |
| 11 | −#define STACK_TOP_MAX STACK_TOP | |
| 12 | −#endif /* _ASM_IA64_USTACK_H */ | |
| @@ -1,30 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_UV_UV_H | |
| 3 | −#define _ASM_IA64_UV_UV_H | |
| 4 | − | |
| 5 | −#ifdef CONFIG_IA64_SGI_UV | |
| 6 | −extern bool ia64_is_uv; | |
| 7 | − | |
| 8 | −static inline int is_uv_system(void) | |
| 9 | −{ | |
| 10 | − return ia64_is_uv; | |
| 11 | −} | |
| 12 | − | |
| 13 | −void __init uv_probe_system_type(void); | |
| 14 | −void __init uv_setup(char **cmdline_p); | |
| 15 | −#else /* CONFIG_IA64_SGI_UV */ | |
| 16 | −static inline int is_uv_system(void) | |
| 17 | −{ | |
| 18 | − return false; | |
| 19 | −} | |
| 20 | − | |
| 21 | −static inline void __init uv_probe_system_type(void) | |
| 22 | −{ | |
| 23 | −} | |
| 24 | − | |
| 25 | −static inline void __init uv_setup(char **cmdline_p) | |
| 26 | −{ | |
| 27 | −} | |
| 28 | −#endif /* CONFIG_IA64_SGI_UV */ | |
| 29 | − | |
| 30 | −#endif /* _ASM_IA64_UV_UV_H */ | |
| @@ -1,315 +0,0 @@ | ||
| 1 | −/* | |
| 2 | − * This file is subject to the terms and conditions of the GNU General Public | |
| 3 | − * License. See the file "COPYING" in the main directory of this archive | |
| 4 | − * for more details. | |
| 5 | − * | |
| 6 | − * SGI UV architectural definitions | |
| 7 | − * | |
| 8 | − * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved. | |
| 9 | − */ | |
| 10 | − | |
| 11 | −#ifndef __ASM_IA64_UV_HUB_H__ | |
| 12 | −#define __ASM_IA64_UV_HUB_H__ | |
| 13 | − | |
| 14 | −#include <linux/numa.h> | |
| 15 | −#include <linux/percpu.h> | |
| 16 | −#include <asm/types.h> | |
| 17 | −#include <asm/percpu.h> | |
| 18 | − | |
| 19 | − | |
| 20 | −/* | |
| 21 | − * Addressing Terminology | |
| 22 | − * | |
| 23 | − * M - The low M bits of a physical address represent the offset | |
| 24 | − * into the blade local memory. RAM memory on a blade is physically | |
| 25 | − * contiguous (although various IO spaces may punch holes in | |
| 26 | − * it).. | |
| 27 | − * | |
| 28 | − * N - Number of bits in the node portion of a socket physical | |
| 29 | − * address. | |
| 30 | − * | |
| 31 | − * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of | |
| 32 | − * routers always have low bit of 1, C/MBricks have low bit | |
| 33 | − * equal to 0. Most addressing macros that target UV hub chips | |
| 34 | − * right shift the NASID by 1 to exclude the always-zero bit. | |
| 35 | − * NASIDs contain up to 15 bits. | |
| 36 | − * | |
| 37 | − * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead | |
| 38 | − * of nasids. | |
| 39 | − * | |
| 40 | − * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant | |
| 41 | − * of the nasid for socket usage. | |
| 42 | − * | |
| 43 | − * | |
| 44 | − * NumaLink Global Physical Address Format: | |
| 45 | − * +--------------------------------+---------------------+ | |
| 46 | − * |00..000| GNODE | NodeOffset | | |
| 47 | − * +--------------------------------+---------------------+ | |
| 48 | − * |<-------53 - M bits --->|<--------M bits -----> | |
| 49 | − * | |
| 50 | − * M - number of node offset bits (35 .. 40) | |
| 51 | − * | |
| 52 | − * | |
| 53 | − * Memory/UV-HUB Processor Socket Address Format: | |
| 54 | − * +----------------+---------------+---------------------+ | |
| 55 | − * |00..000000000000| PNODE | NodeOffset | | |
| 56 | − * +----------------+---------------+---------------------+ | |
| 57 | − * <--- N bits --->|<--------M bits -----> | |
| 58 | − * | |
| 59 | − * M - number of node offset bits (35 .. 40) | |
| 60 | − * N - number of PNODE bits (0 .. 10) | |
| 61 | − * | |
| 62 | − * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). | |
| 63 | − * The actual values are configuration dependent and are set at | |
| 64 | − * boot time. M & N values are set by the hardware/BIOS at boot. | |
| 65 | − */ | |
| 66 | − | |
| 67 | − | |
| 68 | −/* | |
| 69 | − * Maximum number of bricks in all partitions and in all coherency domains. | |
| 70 | − * This is the total number of bricks accessible in the numalink fabric. It | |
| 71 | − * includes all C & M bricks. Routers are NOT included. | |
| 72 | − * | |
| 73 | − * This value is also the value of the maximum number of non-router NASIDs | |
| 74 | − * in the numalink fabric. | |
| 75 | − * | |
| 76 | − * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. | |
| 77 | − */ | |
| 78 | −#define UV_MAX_NUMALINK_BLADES 16384 | |
| 79 | − | |
| 80 | −/* | |
| 81 | − * Maximum number of C/Mbricks within a software SSI (hardware may support | |
| 82 | − * more). | |
| 83 | − */ | |
| 84 | −#define UV_MAX_SSI_BLADES 1 | |
| 85 | − | |
| 86 | −/* | |
| 87 | − * The largest possible NASID of a C or M brick (+ 2) | |
| 88 | − */ | |
| 89 | −#define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2) | |
| 90 | − | |
| 91 | −/* | |
| 92 | − * The following defines attributes of the HUB chip. These attributes are | |
| 93 | − * frequently referenced and are kept in the per-cpu data areas of each cpu. | |
| 94 | − * They are kept together in a struct to minimize cache misses. | |
| 95 | − */ | |
| 96 | −struct uv_hub_info_s { | |
| 97 | − unsigned long global_mmr_base; | |
| 98 | − unsigned long gpa_mask; | |
| 99 | − unsigned long gnode_upper; | |
| 100 | − unsigned long lowmem_remap_top; | |
| 101 | − unsigned long lowmem_remap_base; | |
| 102 | − unsigned short pnode; | |
| 103 | − unsigned short pnode_mask; | |
| 104 | − unsigned short coherency_domain_number; | |
| 105 | − unsigned short numa_blade_id; | |
| 106 | − unsigned char blade_processor_id; | |
| 107 | − unsigned char m_val; | |
| 108 | − unsigned char n_val; | |
| 109 | −}; | |
| 110 | −DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); | |
| 111 | −#define uv_hub_info this_cpu_ptr(&__uv_hub_info) | |
| 112 | −#define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu)) | |
| 113 | − | |
| 114 | −/* | |
| 115 | − * Local & Global MMR space macros. | |
| 116 | − * Note: macros are intended to be used ONLY by inline functions | |
| 117 | − * in this file - not by other kernel code. | |
| 118 | − * n - NASID (full 15-bit global nasid) | |
| 119 | − * g - GNODE (full 15-bit global nasid, right shifted 1) | |
| 120 | − * p - PNODE (local part of nsids, right shifted 1) | |
| 121 | − */ | |
| 122 | −#define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask) | |
| 123 | −#define UV_PNODE_TO_NASID(p) (((p) << 1) | uv_hub_info->gnode_upper) | |
| 124 | − | |
| 125 | −#define UV_LOCAL_MMR_BASE 0xf4000000UL | |
| 126 | −#define UV_GLOBAL_MMR32_BASE 0xf8000000UL | |
| 127 | −#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) | |
| 128 | − | |
| 129 | −#define UV_GLOBAL_MMR32_PNODE_SHIFT 15 | |
| 130 | −#define UV_GLOBAL_MMR64_PNODE_SHIFT 26 | |
| 131 | − | |
| 132 | −#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) | |
| 133 | − | |
| 134 | −#define UV_GLOBAL_MMR64_PNODE_BITS(p) \ | |
| 135 | − ((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT) | |
| 136 | − | |
| 137 | −/* | |
| 138 | − * Macros for converting between kernel virtual addresses, socket local physical | |
| 139 | − * addresses, and UV global physical addresses. | |
| 140 | − * Note: use the standard __pa() & __va() macros for converting | |
| 141 | − * between socket virtual and socket physical addresses. | |
| 142 | − */ | |
| 143 | − | |
| 144 | −/* socket phys RAM --> UV global physical address */ | |
| 145 | −static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) | |
| 146 | −{ | |
| 147 | − if (paddr < uv_hub_info->lowmem_remap_top) | |
| 148 | − paddr += uv_hub_info->lowmem_remap_base; | |
| 149 | − return paddr | uv_hub_info->gnode_upper; | |
| 150 | −} | |
| 151 | − | |
| 152 | − | |
| 153 | −/* socket virtual --> UV global physical address */ | |
| 154 | −static inline unsigned long uv_gpa(void *v) | |
| 155 | −{ | |
| 156 | − return __pa(v) | uv_hub_info->gnode_upper; | |
| 157 | −} | |
| 158 | − | |
| 159 | −/* socket virtual --> UV global physical address */ | |
| 160 | −static inline void *uv_vgpa(void *v) | |
| 161 | −{ | |
| 162 | − return (void *)uv_gpa(v); | |
| 163 | −} | |
| 164 | − | |
| 165 | −/* UV global physical address --> socket virtual */ | |
| 166 | −static inline void *uv_va(unsigned long gpa) | |
| 167 | −{ | |
| 168 | − return __va(gpa & uv_hub_info->gpa_mask); | |
| 169 | −} | |
| 170 | − | |
| 171 | −/* pnode, offset --> socket virtual */ | |
| 172 | −static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) | |
| 173 | −{ | |
| 174 | − return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); | |
| 175 | −} | |
| 176 | − | |
| 177 | − | |
| 178 | −/* | |
| 179 | − * Access global MMRs using the low memory MMR32 space. This region supports | |
| 180 | − * faster MMR access but not all MMRs are accessible in this space. | |
| 181 | − */ | |
| 182 | −static inline unsigned long *uv_global_mmr32_address(int pnode, | |
| 183 | − unsigned long offset) | |
| 184 | −{ | |
| 185 | − return __va(UV_GLOBAL_MMR32_BASE | | |
| 186 | − UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); | |
| 187 | −} | |
| 188 | − | |
| 189 | −static inline void uv_write_global_mmr32(int pnode, unsigned long offset, | |
| 190 | − unsigned long val) | |
| 191 | −{ | |
| 192 | − *uv_global_mmr32_address(pnode, offset) = val; | |
| 193 | −} | |
| 194 | − | |
| 195 | −static inline unsigned long uv_read_global_mmr32(int pnode, | |
| 196 | − unsigned long offset) | |
| 197 | −{ | |
| 198 | − return *uv_global_mmr32_address(pnode, offset); | |
| 199 | −} | |
| 200 | − | |
| 201 | −/* | |
| 202 | − * Access Global MMR space using the MMR space located at the top of physical | |
| 203 | − * memory. | |
| 204 | − */ | |
| 205 | −static inline unsigned long *uv_global_mmr64_address(int pnode, | |
| 206 | − unsigned long offset) | |
| 207 | −{ | |
| 208 | − return __va(UV_GLOBAL_MMR64_BASE | | |
| 209 | − UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); | |
| 210 | −} | |
| 211 | − | |
| 212 | −static inline void uv_write_global_mmr64(int pnode, unsigned long offset, | |
| 213 | − unsigned long val) | |
| 214 | −{ | |
| 215 | − *uv_global_mmr64_address(pnode, offset) = val; | |
| 216 | −} | |
| 217 | − | |
| 218 | −static inline unsigned long uv_read_global_mmr64(int pnode, | |
| 219 | − unsigned long offset) | |
| 220 | −{ | |
| 221 | − return *uv_global_mmr64_address(pnode, offset); | |
| 222 | −} | |
| 223 | − | |
| 224 | −/* | |
| 225 | − * Access hub local MMRs. Faster than using global space but only local MMRs | |
| 226 | − * are accessible. | |
| 227 | − */ | |
| 228 | −static inline unsigned long *uv_local_mmr_address(unsigned long offset) | |
| 229 | −{ | |
| 230 | − return __va(UV_LOCAL_MMR_BASE | offset); | |
| 231 | −} | |
| 232 | − | |
| 233 | −static inline unsigned long uv_read_local_mmr(unsigned long offset) | |
| 234 | −{ | |
| 235 | − return *uv_local_mmr_address(offset); | |
| 236 | −} | |
| 237 | − | |
| 238 | −static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) | |
| 239 | −{ | |
| 240 | − *uv_local_mmr_address(offset) = val; | |
| 241 | −} | |
| 242 | − | |
| 243 | −/* | |
| 244 | − * Structures and definitions for converting between cpu, node, pnode, and blade | |
| 245 | − * numbers. | |
| 246 | − */ | |
| 247 | − | |
| 248 | −/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ | |
| 249 | −static inline int uv_blade_processor_id(void) | |
| 250 | −{ | |
| 251 | − return smp_processor_id(); | |
| 252 | −} | |
| 253 | − | |
| 254 | −/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ | |
| 255 | −static inline int uv_numa_blade_id(void) | |
| 256 | −{ | |
| 257 | − return 0; | |
| 258 | −} | |
| 259 | − | |
| 260 | −/* Convert a cpu number to the UV blade number */ | |
| 261 | −static inline int uv_cpu_to_blade_id(int cpu) | |
| 262 | −{ | |
| 263 | − return 0; | |
| 264 | −} | |
| 265 | − | |
| 266 | −/* Convert linux node number to the UV blade number */ | |
| 267 | −static inline int uv_node_to_blade_id(int nid) | |
| 268 | −{ | |
| 269 | − return 0; | |
| 270 | −} | |
| 271 | − | |
| 272 | −/* Convert a blade id to the PNODE of the blade */ | |
| 273 | −static inline int uv_blade_to_pnode(int bid) | |
| 274 | −{ | |
| 275 | − return 0; | |
| 276 | −} | |
| 277 | − | |
| 278 | −/* Determine the number of possible cpus on a blade */ | |
| 279 | −static inline int uv_blade_nr_possible_cpus(int bid) | |
| 280 | −{ | |
| 281 | − return num_possible_cpus(); | |
| 282 | −} | |
| 283 | − | |
| 284 | −/* Determine the number of online cpus on a blade */ | |
| 285 | −static inline int uv_blade_nr_online_cpus(int bid) | |
| 286 | −{ | |
| 287 | − return num_online_cpus(); | |
| 288 | −} | |
| 289 | − | |
| 290 | −/* Convert a cpu id to the PNODE of the blade containing the cpu */ | |
| 291 | −static inline int uv_cpu_to_pnode(int cpu) | |
| 292 | −{ | |
| 293 | − return 0; | |
| 294 | −} | |
| 295 | − | |
| 296 | −/* Convert a linux node number to the PNODE of the blade */ | |
| 297 | −static inline int uv_node_to_pnode(int nid) | |
| 298 | −{ | |
| 299 | − return 0; | |
| 300 | −} | |
| 301 | − | |
| 302 | −/* Maximum possible number of blades */ | |
| 303 | −static inline int uv_num_possible_blades(void) | |
| 304 | −{ | |
| 305 | − return 1; | |
| 306 | −} | |
| 307 | − | |
| 308 | −static inline void uv_hub_send_ipi(int pnode, int apicid, int vector) | |
| 309 | −{ | |
| 310 | − /* not currently needed on ia64 */ | |
| 311 | −} | |
| 312 | − | |
| 313 | − | |
| 314 | −#endif /* __ASM_IA64_UV_HUB__ */ | |
| 315 | − | |
| @@ -1,825 +0,0 @@ | ||
| 1 | −/* | |
| 2 | − * This file is subject to the terms and conditions of the GNU General Public | |
| 3 | − * License. See the file "COPYING" in the main directory of this archive | |
| 4 | − * for more details. | |
| 5 | − * | |
| 6 | − * SGI UV MMR definitions | |
| 7 | − * | |
| 8 | − * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved. | |
| 9 | − */ | |
| 10 | − | |
| 11 | −#ifndef _ASM_IA64_UV_UV_MMRS_H | |
| 12 | −#define _ASM_IA64_UV_UV_MMRS_H | |
| 13 | − | |
| 14 | −#define UV_MMR_ENABLE (1UL << 63) | |
| 15 | − | |
| 16 | −/* ========================================================================= */ | |
| 17 | −/* UVH_BAU_DATA_CONFIG */ | |
| 18 | −/* ========================================================================= */ | |
| 19 | −#define UVH_BAU_DATA_CONFIG 0x61680UL | |
| 20 | −#define UVH_BAU_DATA_CONFIG_32 0x0438 | |
| 21 | − | |
| 22 | −#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0 | |
| 23 | −#define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL | |
| 24 | −#define UVH_BAU_DATA_CONFIG_DM_SHFT 8 | |
| 25 | −#define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL | |
| 26 | −#define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11 | |
| 27 | −#define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL | |
| 28 | −#define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12 | |
| 29 | −#define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL | |
| 30 | −#define UVH_BAU_DATA_CONFIG_P_SHFT 13 | |
| 31 | −#define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL | |
| 32 | −#define UVH_BAU_DATA_CONFIG_T_SHFT 15 | |
| 33 | −#define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL | |
| 34 | −#define UVH_BAU_DATA_CONFIG_M_SHFT 16 | |
| 35 | −#define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL | |
| 36 | −#define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32 | |
| 37 | −#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | |
| 38 | − | |
| 39 | −union uvh_bau_data_config_u { | |
| 40 | − unsigned long v; | |
| 41 | − struct uvh_bau_data_config_s { | |
| 42 | − unsigned long vector_ : 8; /* RW */ | |
| 43 | − unsigned long dm : 3; /* RW */ | |
| 44 | − unsigned long destmode : 1; /* RW */ | |
| 45 | − unsigned long status : 1; /* RO */ | |
| 46 | − unsigned long p : 1; /* RO */ | |
| 47 | − unsigned long rsvd_14 : 1; /* */ | |
| 48 | − unsigned long t : 1; /* RO */ | |
| 49 | − unsigned long m : 1; /* RW */ | |
| 50 | − unsigned long rsvd_17_31: 15; /* */ | |
| 51 | − unsigned long apic_id : 32; /* RW */ | |
| 52 | − } s; | |
| 53 | −}; | |
| 54 | − | |
| 55 | −/* ========================================================================= */ | |
| 56 | −/* UVH_EVENT_OCCURRED0 */ | |
| 57 | −/* ========================================================================= */ | |
| 58 | −#define UVH_EVENT_OCCURRED0 0x70000UL | |
| 59 | −#define UVH_EVENT_OCCURRED0_32 0x005e8 | |
| 60 | − | |
| 61 | −#define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0 | |
| 62 | −#define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL | |
| 63 | −#define UVH_EVENT_OCCURRED0_GR0_HCERR_SHFT 1 | |
| 64 | −#define UVH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL | |
| 65 | −#define UVH_EVENT_OCCURRED0_GR1_HCERR_SHFT 2 | |
| 66 | −#define UVH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL | |
| 67 | −#define UVH_EVENT_OCCURRED0_LH_HCERR_SHFT 3 | |
| 68 | −#define UVH_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL | |
| 69 | −#define UVH_EVENT_OCCURRED0_RH_HCERR_SHFT 4 | |
| 70 | −#define UVH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL | |
| 71 | −#define UVH_EVENT_OCCURRED0_XN_HCERR_SHFT 5 | |
| 72 | −#define UVH_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL | |
| 73 | −#define UVH_EVENT_OCCURRED0_SI_HCERR_SHFT 6 | |
| 74 | −#define UVH_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL | |
| 75 | −#define UVH_EVENT_OCCURRED0_LB_AOERR0_SHFT 7 | |
| 76 | −#define UVH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL | |
| 77 | −#define UVH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8 | |
| 78 | −#define UVH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL | |
| 79 | −#define UVH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9 | |
| 80 | −#define UVH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL | |
| 81 | −#define UVH_EVENT_OCCURRED0_LH_AOERR0_SHFT 10 | |
| 82 | −#define UVH_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL | |
| 83 | −#define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 | |
| 84 | −#define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL | |
| 85 | −#define UVH_EVENT_OCCURRED0_XN_AOERR0_SHFT 12 | |
| 86 | −#define UVH_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL | |
| 87 | −#define UVH_EVENT_OCCURRED0_SI_AOERR0_SHFT 13 | |
| 88 | −#define UVH_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL | |
| 89 | −#define UVH_EVENT_OCCURRED0_LB_AOERR1_SHFT 14 | |
| 90 | −#define UVH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL | |
| 91 | −#define UVH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15 | |
| 92 | −#define UVH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL | |
| 93 | −#define UVH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16 | |
| 94 | −#define UVH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL | |
| 95 | −#define UVH_EVENT_OCCURRED0_LH_AOERR1_SHFT 17 | |
| 96 | −#define UVH_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL | |
| 97 | −#define UVH_EVENT_OCCURRED0_RH_AOERR1_SHFT 18 | |
| 98 | −#define UVH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL | |
| 99 | −#define UVH_EVENT_OCCURRED0_XN_AOERR1_SHFT 19 | |
| 100 | −#define UVH_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL | |
| 101 | −#define UVH_EVENT_OCCURRED0_SI_AOERR1_SHFT 20 | |
| 102 | −#define UVH_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL | |
| 103 | −#define UVH_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21 | |
| 104 | −#define UVH_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL | |
| 105 | −#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22 | |
| 106 | −#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL | |
| 107 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23 | |
| 108 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL | |
| 109 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24 | |
| 110 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL | |
| 111 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25 | |
| 112 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL | |
| 113 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26 | |
| 114 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL | |
| 115 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27 | |
| 116 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL | |
| 117 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28 | |
| 118 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL | |
| 119 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29 | |
| 120 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL | |
| 121 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30 | |
| 122 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL | |
| 123 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31 | |
| 124 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL | |
| 125 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32 | |
| 126 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL | |
| 127 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33 | |
| 128 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL | |
| 129 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34 | |
| 130 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL | |
| 131 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35 | |
| 132 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL | |
| 133 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36 | |
| 134 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL | |
| 135 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37 | |
| 136 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL | |
| 137 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38 | |
| 138 | −#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL | |
| 139 | −#define UVH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39 | |
| 140 | −#define UVH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL | |
| 141 | −#define UVH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40 | |
| 142 | −#define UVH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL | |
| 143 | −#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41 | |
| 144 | −#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL | |
| 145 | −#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42 | |
| 146 | −#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL | |
| 147 | −#define UVH_EVENT_OCCURRED0_LTC_INT_SHFT 43 | |
| 148 | −#define UVH_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL | |
| 149 | −#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44 | |
| 150 | −#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL | |
| 151 | −#define UVH_EVENT_OCCURRED0_IPI_INT_SHFT 45 | |
| 152 | −#define UVH_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL | |
| 153 | −#define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46 | |
| 154 | −#define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL | |
| 155 | −#define UVH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47 | |
| 156 | −#define UVH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL | |
| 157 | −#define UVH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48 | |
| 158 | −#define UVH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL | |
| 159 | −#define UVH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49 | |
| 160 | −#define UVH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL | |
| 161 | −#define UVH_EVENT_OCCURRED0_PROFILE_INT_SHFT 50 | |
| 162 | −#define UVH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL | |
| 163 | −#define UVH_EVENT_OCCURRED0_RTC0_SHFT 51 | |
| 164 | −#define UVH_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL | |
| 165 | −#define UVH_EVENT_OCCURRED0_RTC1_SHFT 52 | |
| 166 | −#define UVH_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL | |
| 167 | −#define UVH_EVENT_OCCURRED0_RTC2_SHFT 53 | |
| 168 | −#define UVH_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL | |
| 169 | −#define UVH_EVENT_OCCURRED0_RTC3_SHFT 54 | |
| 170 | −#define UVH_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL | |
| 171 | −#define UVH_EVENT_OCCURRED0_BAU_DATA_SHFT 55 | |
| 172 | −#define UVH_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL | |
| 173 | −#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56 | |
| 174 | −#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL | |
| 175 | −union uvh_event_occurred0_u { | |
| 176 | − unsigned long v; | |
| 177 | − struct uvh_event_occurred0_s { | |
| 178 | − unsigned long lb_hcerr : 1; /* RW, W1C */ | |
| 179 | − unsigned long gr0_hcerr : 1; /* RW, W1C */ | |
| 180 | − unsigned long gr1_hcerr : 1; /* RW, W1C */ | |
| 181 | − unsigned long lh_hcerr : 1; /* RW, W1C */ | |
| 182 | − unsigned long rh_hcerr : 1; /* RW, W1C */ | |
| 183 | − unsigned long xn_hcerr : 1; /* RW, W1C */ | |
| 184 | − unsigned long si_hcerr : 1; /* RW, W1C */ | |
| 185 | − unsigned long lb_aoerr0 : 1; /* RW, W1C */ | |
| 186 | − unsigned long gr0_aoerr0 : 1; /* RW, W1C */ | |
| 187 | − unsigned long gr1_aoerr0 : 1; /* RW, W1C */ | |
| 188 | − unsigned long lh_aoerr0 : 1; /* RW, W1C */ | |
| 189 | − unsigned long rh_aoerr0 : 1; /* RW, W1C */ | |
| 190 | − unsigned long xn_aoerr0 : 1; /* RW, W1C */ | |
| 191 | − unsigned long si_aoerr0 : 1; /* RW, W1C */ | |
| 192 | − unsigned long lb_aoerr1 : 1; /* RW, W1C */ | |
| 193 | − unsigned long gr0_aoerr1 : 1; /* RW, W1C */ | |
| 194 | − unsigned long gr1_aoerr1 : 1; /* RW, W1C */ | |
| 195 | − unsigned long lh_aoerr1 : 1; /* RW, W1C */ | |
| 196 | − unsigned long rh_aoerr1 : 1; /* RW, W1C */ | |
| 197 | − unsigned long xn_aoerr1 : 1; /* RW, W1C */ | |
| 198 | − unsigned long si_aoerr1 : 1; /* RW, W1C */ | |
| 199 | − unsigned long rh_vpi_int : 1; /* RW, W1C */ | |
| 200 | − unsigned long system_shutdown_int : 1; /* RW, W1C */ | |
| 201 | − unsigned long lb_irq_int_0 : 1; /* RW, W1C */ | |
| 202 | − unsigned long lb_irq_int_1 : 1; /* RW, W1C */ | |
| 203 | − unsigned long lb_irq_int_2 : 1; /* RW, W1C */ | |
| 204 | − unsigned long lb_irq_int_3 : 1; /* RW, W1C */ | |
| 205 | − unsigned long lb_irq_int_4 : 1; /* RW, W1C */ | |
| 206 | − unsigned long lb_irq_int_5 : 1; /* RW, W1C */ | |
| 207 | − unsigned long lb_irq_int_6 : 1; /* RW, W1C */ | |
| 208 | − unsigned long lb_irq_int_7 : 1; /* RW, W1C */ | |
| 209 | − unsigned long lb_irq_int_8 : 1; /* RW, W1C */ | |
| 210 | − unsigned long lb_irq_int_9 : 1; /* RW, W1C */ | |
| 211 | − unsigned long lb_irq_int_10 : 1; /* RW, W1C */ | |
| 212 | − unsigned long lb_irq_int_11 : 1; /* RW, W1C */ | |
| 213 | − unsigned long lb_irq_int_12 : 1; /* RW, W1C */ | |
| 214 | − unsigned long lb_irq_int_13 : 1; /* RW, W1C */ | |
| 215 | − unsigned long lb_irq_int_14 : 1; /* RW, W1C */ | |
| 216 | − unsigned long lb_irq_int_15 : 1; /* RW, W1C */ | |
| 217 | − unsigned long l1_nmi_int : 1; /* RW, W1C */ | |
| 218 | − unsigned long stop_clock : 1; /* RW, W1C */ | |
| 219 | − unsigned long asic_to_l1 : 1; /* RW, W1C */ | |
| 220 | − unsigned long l1_to_asic : 1; /* RW, W1C */ | |
| 221 | − unsigned long ltc_int : 1; /* RW, W1C */ | |
| 222 | − unsigned long la_seq_trigger : 1; /* RW, W1C */ | |
| 223 | − unsigned long ipi_int : 1; /* RW, W1C */ | |
| 224 | − unsigned long extio_int0 : 1; /* RW, W1C */ | |
| 225 | − unsigned long extio_int1 : 1; /* RW, W1C */ | |
| 226 | − unsigned long extio_int2 : 1; /* RW, W1C */ | |
| 227 | − unsigned long extio_int3 : 1; /* RW, W1C */ | |
| 228 | − unsigned long profile_int : 1; /* RW, W1C */ | |
| 229 | − unsigned long rtc0 : 1; /* RW, W1C */ | |
| 230 | − unsigned long rtc1 : 1; /* RW, W1C */ | |
| 231 | − unsigned long rtc2 : 1; /* RW, W1C */ | |
| 232 | − unsigned long rtc3 : 1; /* RW, W1C */ | |
| 233 | − unsigned long bau_data : 1; /* RW, W1C */ | |
| 234 | − unsigned long power_management_req : 1; /* RW, W1C */ | |
| 235 | − unsigned long rsvd_57_63 : 7; /* */ | |
| 236 | − } s; | |
| 237 | −}; | |
| 238 | − | |
| 239 | −/* ========================================================================= */ | |
| 240 | −/* UVH_EVENT_OCCURRED0_ALIAS */ | |
| 241 | −/* ========================================================================= */ | |
| 242 | −#define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL | |
| 243 | −#define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0 | |
| 244 | − | |
| 245 | −/* ========================================================================= */ | |
| 246 | −/* UVH_GR0_TLB_INT0_CONFIG */ | |
| 247 | −/* ========================================================================= */ | |
| 248 | −#define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL | |
| 249 | − | |
| 250 | −#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0 | |
| 251 | −#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL | |
| 252 | −#define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8 | |
| 253 | −#define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL | |
| 254 | −#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11 | |
| 255 | −#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL | |
| 256 | −#define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12 | |
| 257 | −#define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL | |
| 258 | −#define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13 | |
| 259 | −#define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL | |
| 260 | −#define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15 | |
| 261 | −#define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL | |
| 262 | −#define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16 | |
| 263 | −#define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL | |
| 264 | −#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32 | |
| 265 | −#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | |
| 266 | − | |
| 267 | −union uvh_gr0_tlb_int0_config_u { | |
| 268 | − unsigned long v; | |
| 269 | − struct uvh_gr0_tlb_int0_config_s { | |
| 270 | − unsigned long vector_ : 8; /* RW */ | |
| 271 | − unsigned long dm : 3; /* RW */ | |
| 272 | − unsigned long destmode : 1; /* RW */ | |
| 273 | − unsigned long status : 1; /* RO */ | |
| 274 | − unsigned long p : 1; /* RO */ | |
| 275 | − unsigned long rsvd_14 : 1; /* */ | |
| 276 | − unsigned long t : 1; /* RO */ | |
| 277 | − unsigned long m : 1; /* RW */ | |
| 278 | − unsigned long rsvd_17_31: 15; /* */ | |
| 279 | − unsigned long apic_id : 32; /* RW */ | |
| 280 | − } s; | |
| 281 | −}; | |
| 282 | − | |
| 283 | −/* ========================================================================= */ | |
| 284 | −/* UVH_GR0_TLB_INT1_CONFIG */ | |
| 285 | −/* ========================================================================= */ | |
| 286 | −#define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL | |
| 287 | − | |
| 288 | −#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0 | |
| 289 | −#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL | |
| 290 | −#define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8 | |
| 291 | −#define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL | |
| 292 | −#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11 | |
| 293 | −#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL | |
| 294 | −#define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12 | |
| 295 | −#define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL | |
| 296 | −#define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13 | |
| 297 | −#define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL | |
| 298 | −#define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15 | |
| 299 | −#define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL | |
| 300 | −#define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16 | |
| 301 | −#define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL | |
| 302 | −#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32 | |
| 303 | −#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | |
| 304 | − | |
| 305 | −union uvh_gr0_tlb_int1_config_u { | |
| 306 | − unsigned long v; | |
| 307 | − struct uvh_gr0_tlb_int1_config_s { | |
| 308 | − unsigned long vector_ : 8; /* RW */ | |
| 309 | − unsigned long dm : 3; /* RW */ | |
| 310 | − unsigned long destmode : 1; /* RW */ | |
| 311 | − unsigned long status : 1; /* RO */ | |
| 312 | − unsigned long p : 1; /* RO */ | |
| 313 | − unsigned long rsvd_14 : 1; /* */ | |
| 314 | − unsigned long t : 1; /* RO */ | |
| 315 | − unsigned long m : 1; /* RW */ | |
| 316 | − unsigned long rsvd_17_31: 15; /* */ | |
| 317 | − unsigned long apic_id : 32; /* RW */ | |
| 318 | − } s; | |
| 319 | −}; | |
| 320 | − | |
| 321 | −/* ========================================================================= */ | |
| 322 | −/* UVH_GR1_TLB_INT0_CONFIG */ | |
| 323 | −/* ========================================================================= */ | |
| 324 | −#define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL | |
| 325 | − | |
| 326 | −#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0 | |
| 327 | −#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL | |
| 328 | −#define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8 | |
| 329 | −#define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL | |
| 330 | −#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11 | |
| 331 | −#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL | |
| 332 | −#define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12 | |
| 333 | −#define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL | |
| 334 | −#define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13 | |
| 335 | −#define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL | |
| 336 | −#define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15 | |
| 337 | −#define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL | |
| 338 | −#define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16 | |
| 339 | −#define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL | |
| 340 | −#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32 | |
| 341 | −#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | |
| 342 | − | |
| 343 | −union uvh_gr1_tlb_int0_config_u { | |
| 344 | − unsigned long v; | |
| 345 | − struct uvh_gr1_tlb_int0_config_s { | |
| 346 | − unsigned long vector_ : 8; /* RW */ | |
| 347 | − unsigned long dm : 3; /* RW */ | |
| 348 | − unsigned long destmode : 1; /* RW */ | |
| 349 | − unsigned long status : 1; /* RO */ | |
| 350 | − unsigned long p : 1; /* RO */ | |
| 351 | − unsigned long rsvd_14 : 1; /* */ | |
| 352 | − unsigned long t : 1; /* RO */ | |
| 353 | − unsigned long m : 1; /* RW */ | |
| 354 | − unsigned long rsvd_17_31: 15; /* */ | |
| 355 | − unsigned long apic_id : 32; /* RW */ | |
| 356 | − } s; | |
| 357 | −}; | |
| 358 | − | |
| 359 | −/* ========================================================================= */ | |
| 360 | −/* UVH_GR1_TLB_INT1_CONFIG */ | |
| 361 | −/* ========================================================================= */ | |
| 362 | −#define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL | |
| 363 | − | |
| 364 | −#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0 | |
| 365 | −#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL | |
| 366 | −#define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8 | |
| 367 | −#define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL | |
| 368 | −#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11 | |
| 369 | −#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL | |
| 370 | −#define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12 | |
| 371 | −#define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL | |
| 372 | −#define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13 | |
| 373 | −#define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL | |
| 374 | −#define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15 | |
| 375 | −#define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL | |
| 376 | −#define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16 | |
| 377 | −#define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL | |
| 378 | −#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32 | |
| 379 | −#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | |
| 380 | − | |
| 381 | −union uvh_gr1_tlb_int1_config_u { | |
| 382 | − unsigned long v; | |
| 383 | − struct uvh_gr1_tlb_int1_config_s { | |
| 384 | − unsigned long vector_ : 8; /* RW */ | |
| 385 | − unsigned long dm : 3; /* RW */ | |
| 386 | − unsigned long destmode : 1; /* RW */ | |
| 387 | − unsigned long status : 1; /* RO */ | |
| 388 | − unsigned long p : 1; /* RO */ | |
| 389 | − unsigned long rsvd_14 : 1; /* */ | |
| 390 | − unsigned long t : 1; /* RO */ | |
| 391 | − unsigned long m : 1; /* RW */ | |
| 392 | − unsigned long rsvd_17_31: 15; /* */ | |
| 393 | − unsigned long apic_id : 32; /* RW */ | |
| 394 | − } s; | |
| 395 | −}; | |
| 396 | − | |
| 397 | −/* ========================================================================= */ | |
| 398 | −/* UVH_INT_CMPB */ | |
| 399 | −/* ========================================================================= */ | |
| 400 | −#define UVH_INT_CMPB 0x22080UL | |
| 401 | − | |
| 402 | −#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 | |
| 403 | −#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL | |
| 404 | − | |
| 405 | −union uvh_int_cmpb_u { | |
| 406 | − unsigned long v; | |
| 407 | − struct uvh_int_cmpb_s { | |
| 408 | − unsigned long real_time_cmpb : 56; /* RW */ | |
| 409 | − unsigned long rsvd_56_63 : 8; /* */ | |
| 410 | − } s; | |
| 411 | −}; | |
| 412 | − | |
| 413 | −/* ========================================================================= */ | |
| 414 | −/* UVH_INT_CMPC */ | |
| 415 | −/* ========================================================================= */ | |
| 416 | −#define UVH_INT_CMPC 0x22100UL | |
| 417 | − | |
| 418 | −#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0 | |
| 419 | −#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL | |
| 420 | − | |
| 421 | −union uvh_int_cmpc_u { | |
| 422 | − unsigned long v; | |
| 423 | − struct uvh_int_cmpc_s { | |
| 424 | − unsigned long real_time_cmpc : 56; /* RW */ | |
| 425 | − unsigned long rsvd_56_63 : 8; /* */ | |
| 426 | − } s; | |
| 427 | −}; | |
| 428 | − | |
| 429 | −/* ========================================================================= */ | |
| 430 | −/* UVH_INT_CMPD */ | |
| 431 | −/* ========================================================================= */ | |
| 432 | −#define UVH_INT_CMPD 0x22180UL | |
| 433 | − | |
| 434 | −#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 | |
| 435 | −#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL | |
| 436 | − | |
| 437 | −union uvh_int_cmpd_u { | |
| 438 | − unsigned long v; | |
| 439 | − struct uvh_int_cmpd_s { | |
| 440 | − unsigned long real_time_cmpd : 56; /* RW */ | |
| 441 | − unsigned long rsvd_56_63 : 8; /* */ | |
| 442 | − } s; | |
| 443 | −}; | |
| 444 | − | |
| 445 | −/* ========================================================================= */ | |
| 446 | −/* UVH_NODE_ID */ | |
| 447 | −/* ========================================================================= */ | |
| 448 | −#define UVH_NODE_ID 0x0UL | |
| 449 | − | |
| 450 | −#define UVH_NODE_ID_FORCE1_SHFT 0 | |
| 451 | −#define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL | |
| 452 | −#define UVH_NODE_ID_MANUFACTURER_SHFT 1 | |
| 453 | −#define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL | |
| 454 | −#define UVH_NODE_ID_PART_NUMBER_SHFT 12 | |
| 455 | −#define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL | |
| 456 | −#define UVH_NODE_ID_REVISION_SHFT 28 | |
| 457 | −#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL | |
| 458 | −#define UVH_NODE_ID_NODE_ID_SHFT 32 | |
| 459 | −#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL | |
| 460 | −#define UVH_NODE_ID_NODES_PER_BIT_SHFT 48 | |
| 461 | −#define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL | |
| 462 | −#define UVH_NODE_ID_NI_PORT_SHFT 56 | |
| 463 | −#define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL | |
| 464 | − | |
| 465 | −union uvh_node_id_u { | |
| 466 | − unsigned long v; | |
| 467 | − struct uvh_node_id_s { | |
| 468 | − unsigned long force1 : 1; /* RO */ | |
| 469 | − unsigned long manufacturer : 11; /* RO */ | |
| 470 | − unsigned long part_number : 16; /* RO */ | |
| 471 | − unsigned long revision : 4; /* RO */ | |
| 472 | − unsigned long node_id : 15; /* RW */ | |
| 473 | − unsigned long rsvd_47 : 1; /* */ | |
| 474 | − unsigned long nodes_per_bit : 7; /* RW */ | |
| 475 | − unsigned long rsvd_55 : 1; /* */ | |
| 476 | − unsigned long ni_port : 4; /* RO */ | |
| 477 | − unsigned long rsvd_60_63 : 4; /* */ | |
| 478 | − } s; | |
| 479 | −}; | |
| 480 | − | |
| 481 | −/* ========================================================================= */ | |
| 482 | −/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */ | |
| 483 | −/* ========================================================================= */ | |
| 484 | −#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL | |
| 485 | − | |
| 486 | −#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 | |
| 487 | −#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL | |
| 488 | − | |
| 489 | −union uvh_rh_gam_alias210_redirect_config_0_mmr_u { | |
| 490 | − unsigned long v; | |
| 491 | − struct uvh_rh_gam_alias210_redirect_config_0_mmr_s { | |
| 492 | − unsigned long rsvd_0_23 : 24; /* */ | |
| 493 | − unsigned long dest_base : 22; /* RW */ | |
| 494 | − unsigned long rsvd_46_63: 18; /* */ | |
| 495 | − } s; | |
| 496 | −}; | |
| 497 | − | |
| 498 | −/* ========================================================================= */ | |
| 499 | −/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */ | |
| 500 | −/* ========================================================================= */ | |
| 501 | −#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL | |
| 502 | − | |
| 503 | −#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 | |
| 504 | −#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL | |
| 505 | − | |
| 506 | −union uvh_rh_gam_alias210_redirect_config_1_mmr_u { | |
| 507 | − unsigned long v; | |
| 508 | − struct uvh_rh_gam_alias210_redirect_config_1_mmr_s { | |
| 509 | − unsigned long rsvd_0_23 : 24; /* */ | |
| 510 | − unsigned long dest_base : 22; /* RW */ | |
| 511 | − unsigned long rsvd_46_63: 18; /* */ | |
| 512 | − } s; | |
| 513 | −}; | |
| 514 | − | |
| 515 | −/* ========================================================================= */ | |
| 516 | −/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */ | |
| 517 | −/* ========================================================================= */ | |
| 518 | −#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL | |
| 519 | − | |
| 520 | −#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 | |
| 521 | −#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL | |
| 522 | − | |
| 523 | −union uvh_rh_gam_alias210_redirect_config_2_mmr_u { | |
| 524 | − unsigned long v; | |
| 525 | − struct uvh_rh_gam_alias210_redirect_config_2_mmr_s { | |
| 526 | − unsigned long rsvd_0_23 : 24; /* */ | |
| 527 | − unsigned long dest_base : 22; /* RW */ | |
| 528 | − unsigned long rsvd_46_63: 18; /* */ | |
| 529 | − } s; | |
| 530 | −}; | |
| 531 | − | |
| 532 | −/* ========================================================================= */ | |
| 533 | −/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */ | |
| 534 | −/* ========================================================================= */ | |
| 535 | −#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL | |
| 536 | − | |
| 537 | −#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 | |
| 538 | −#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL | |
| 539 | −#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48 | |
| 540 | −#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL | |
| 541 | −#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 | |
| 542 | −#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL | |
| 543 | −#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 | |
| 544 | −#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL | |
| 545 | − | |
| 546 | −union uvh_rh_gam_gru_overlay_config_mmr_u { | |
| 547 | − unsigned long v; | |
| 548 | − struct uvh_rh_gam_gru_overlay_config_mmr_s { | |
| 549 | − unsigned long rsvd_0_27: 28; /* */ | |
| 550 | − unsigned long base : 18; /* RW */ | |
| 551 | − unsigned long rsvd_46_47: 2; /* */ | |
| 552 | − unsigned long gr4 : 1; /* RW */ | |
| 553 | − unsigned long rsvd_49_51: 3; /* */ | |
| 554 | − unsigned long n_gru : 4; /* RW */ | |
| 555 | − unsigned long rsvd_56_62: 7; /* */ | |
| 556 | − unsigned long enable : 1; /* RW */ | |
| 557 | − } s; | |
| 558 | −}; | |
| 559 | − | |
| 560 | −/* ========================================================================= */ | |
| 561 | −/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */ | |
| 562 | −/* ========================================================================= */ | |
| 563 | −#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL | |
| 564 | − | |
| 565 | −#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 | |
| 566 | −#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL | |
| 567 | −#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46 | |
| 568 | −#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL | |
| 569 | −#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 | |
| 570 | −#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL | |
| 571 | − | |
| 572 | −union uvh_rh_gam_mmr_overlay_config_mmr_u { | |
| 573 | − unsigned long v; | |
| 574 | − struct uvh_rh_gam_mmr_overlay_config_mmr_s { | |
| 575 | − unsigned long rsvd_0_25: 26; /* */ | |
| 576 | − unsigned long base : 20; /* RW */ | |
| 577 | − unsigned long dual_hub : 1; /* RW */ | |
| 578 | − unsigned long rsvd_47_62: 16; /* */ | |
| 579 | − unsigned long enable : 1; /* RW */ | |
| 580 | − } s; | |
| 581 | −}; | |
| 582 | − | |
| 583 | −/* ========================================================================= */ | |
| 584 | −/* UVH_RTC */ | |
| 585 | −/* ========================================================================= */ | |
| 586 | −#define UVH_RTC 0x340000UL | |
| 587 | − | |
| 588 | −#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0 | |
| 589 | −#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL | |
| 590 | − | |
| 591 | −union uvh_rtc_u { | |
| 592 | − unsigned long v; | |
| 593 | − struct uvh_rtc_s { | |
| 594 | − unsigned long real_time_clock : 56; /* RW */ | |
| 595 | − unsigned long rsvd_56_63 : 8; /* */ | |
| 596 | − } s; | |
| 597 | −}; | |
| 598 | − | |
| 599 | −/* ========================================================================= */ | |
| 600 | −/* UVH_RTC1_INT_CONFIG */ | |
| 601 | −/* ========================================================================= */ | |
| 602 | −#define UVH_RTC1_INT_CONFIG 0x615c0UL | |
| 603 | − | |
| 604 | −#define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0 | |
| 605 | −#define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL | |
| 606 | −#define UVH_RTC1_INT_CONFIG_DM_SHFT 8 | |
| 607 | −#define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL | |
| 608 | −#define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11 | |
| 609 | −#define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL | |
| 610 | −#define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12 | |
| 611 | −#define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL | |
| 612 | −#define UVH_RTC1_INT_CONFIG_P_SHFT 13 | |
| 613 | −#define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL | |
| 614 | −#define UVH_RTC1_INT_CONFIG_T_SHFT 15 | |
| 615 | −#define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL | |
| 616 | −#define UVH_RTC1_INT_CONFIG_M_SHFT 16 | |
| 617 | −#define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL | |
| 618 | −#define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32 | |
| 619 | −#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | |
| 620 | − | |
| 621 | −union uvh_rtc1_int_config_u { | |
| 622 | − unsigned long v; | |
| 623 | − struct uvh_rtc1_int_config_s { | |
| 624 | − unsigned long vector_ : 8; /* RW */ | |
| 625 | − unsigned long dm : 3; /* RW */ | |
| 626 | − unsigned long destmode : 1; /* RW */ | |
| 627 | − unsigned long status : 1; /* RO */ | |
| 628 | − unsigned long p : 1; /* RO */ | |
| 629 | − unsigned long rsvd_14 : 1; /* */ | |
| 630 | − unsigned long t : 1; /* RO */ | |
| 631 | − unsigned long m : 1; /* RW */ | |
| 632 | − unsigned long rsvd_17_31: 15; /* */ | |
| 633 | − unsigned long apic_id : 32; /* RW */ | |
| 634 | − } s; | |
| 635 | −}; | |
| 636 | − | |
| 637 | −/* ========================================================================= */ | |
| 638 | −/* UVH_RTC2_INT_CONFIG */ | |
| 639 | −/* ========================================================================= */ | |
| 640 | −#define UVH_RTC2_INT_CONFIG 0x61600UL | |
| 641 | − | |
| 642 | −#define UVH_RTC2_INT_CONFIG_VECTOR_SHFT 0 | |
| 643 | −#define UVH_RTC2_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL | |
| 644 | −#define UVH_RTC2_INT_CONFIG_DM_SHFT 8 | |
| 645 | −#define UVH_RTC2_INT_CONFIG_DM_MASK 0x0000000000000700UL | |
| 646 | −#define UVH_RTC2_INT_CONFIG_DESTMODE_SHFT 11 | |
| 647 | −#define UVH_RTC2_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL | |
| 648 | −#define UVH_RTC2_INT_CONFIG_STATUS_SHFT 12 | |
| 649 | −#define UVH_RTC2_INT_CONFIG_STATUS_MASK 0x0000000000001000UL | |
| 650 | −#define UVH_RTC2_INT_CONFIG_P_SHFT 13 | |
| 651 | −#define UVH_RTC2_INT_CONFIG_P_MASK 0x0000000000002000UL | |
| 652 | −#define UVH_RTC2_INT_CONFIG_T_SHFT 15 | |
| 653 | −#define UVH_RTC2_INT_CONFIG_T_MASK 0x0000000000008000UL | |
| 654 | −#define UVH_RTC2_INT_CONFIG_M_SHFT 16 | |
| 655 | −#define UVH_RTC2_INT_CONFIG_M_MASK 0x0000000000010000UL | |
| 656 | −#define UVH_RTC2_INT_CONFIG_APIC_ID_SHFT 32 | |
| 657 | −#define UVH_RTC2_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | |
| 658 | − | |
| 659 | −union uvh_rtc2_int_config_u { | |
| 660 | − unsigned long v; | |
| 661 | − struct uvh_rtc2_int_config_s { | |
| 662 | − unsigned long vector_ : 8; /* RW */ | |
| 663 | − unsigned long dm : 3; /* RW */ | |
| 664 | − unsigned long destmode : 1; /* RW */ | |
| 665 | − unsigned long status : 1; /* RO */ | |
| 666 | − unsigned long p : 1; /* RO */ | |
| 667 | − unsigned long rsvd_14 : 1; /* */ | |
| 668 | − unsigned long t : 1; /* RO */ | |
| 669 | − unsigned long m : 1; /* RW */ | |
| 670 | − unsigned long rsvd_17_31: 15; /* */ | |
| 671 | − unsigned long apic_id : 32; /* RW */ | |
| 672 | − } s; | |
| 673 | −}; | |
| 674 | − | |
| 675 | −/* ========================================================================= */ | |
| 676 | −/* UVH_RTC3_INT_CONFIG */ | |
| 677 | −/* ========================================================================= */ | |
| 678 | −#define UVH_RTC3_INT_CONFIG 0x61640UL | |
| 679 | − | |
| 680 | −#define UVH_RTC3_INT_CONFIG_VECTOR_SHFT 0 | |
| 681 | −#define UVH_RTC3_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL | |
| 682 | −#define UVH_RTC3_INT_CONFIG_DM_SHFT 8 | |
| 683 | −#define UVH_RTC3_INT_CONFIG_DM_MASK 0x0000000000000700UL | |
| 684 | −#define UVH_RTC3_INT_CONFIG_DESTMODE_SHFT 11 | |
| 685 | −#define UVH_RTC3_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL | |
| 686 | −#define UVH_RTC3_INT_CONFIG_STATUS_SHFT 12 | |
| 687 | −#define UVH_RTC3_INT_CONFIG_STATUS_MASK 0x0000000000001000UL | |
| 688 | −#define UVH_RTC3_INT_CONFIG_P_SHFT 13 | |
| 689 | −#define UVH_RTC3_INT_CONFIG_P_MASK 0x0000000000002000UL | |
| 690 | −#define UVH_RTC3_INT_CONFIG_T_SHFT 15 | |
| 691 | −#define UVH_RTC3_INT_CONFIG_T_MASK 0x0000000000008000UL | |
| 692 | −#define UVH_RTC3_INT_CONFIG_M_SHFT 16 | |
| 693 | −#define UVH_RTC3_INT_CONFIG_M_MASK 0x0000000000010000UL | |
| 694 | −#define UVH_RTC3_INT_CONFIG_APIC_ID_SHFT 32 | |
| 695 | −#define UVH_RTC3_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | |
| 696 | − | |
| 697 | −union uvh_rtc3_int_config_u { | |
| 698 | − unsigned long v; | |
| 699 | − struct uvh_rtc3_int_config_s { | |
| 700 | − unsigned long vector_ : 8; /* RW */ | |
| 701 | − unsigned long dm : 3; /* RW */ | |
| 702 | − unsigned long destmode : 1; /* RW */ | |
| 703 | − unsigned long status : 1; /* RO */ | |
| 704 | − unsigned long p : 1; /* RO */ | |
| 705 | − unsigned long rsvd_14 : 1; /* */ | |
| 706 | − unsigned long t : 1; /* RO */ | |
| 707 | − unsigned long m : 1; /* RW */ | |
| 708 | − unsigned long rsvd_17_31: 15; /* */ | |
| 709 | − unsigned long apic_id : 32; /* RW */ | |
| 710 | − } s; | |
| 711 | −}; | |
| 712 | − | |
| 713 | −/* ========================================================================= */ | |
| 714 | −/* UVH_RTC_INC_RATIO */ | |
| 715 | −/* ========================================================================= */ | |
| 716 | −#define UVH_RTC_INC_RATIO 0x350000UL | |
| 717 | − | |
| 718 | −#define UVH_RTC_INC_RATIO_FRACTION_SHFT 0 | |
| 719 | −#define UVH_RTC_INC_RATIO_FRACTION_MASK 0x00000000000fffffUL | |
| 720 | −#define UVH_RTC_INC_RATIO_RATIO_SHFT 20 | |
| 721 | −#define UVH_RTC_INC_RATIO_RATIO_MASK 0x0000000000700000UL | |
| 722 | − | |
| 723 | −union uvh_rtc_inc_ratio_u { | |
| 724 | − unsigned long v; | |
| 725 | − struct uvh_rtc_inc_ratio_s { | |
| 726 | − unsigned long fraction : 20; /* RW */ | |
| 727 | − unsigned long ratio : 3; /* RW */ | |
| 728 | − unsigned long rsvd_23_63: 41; /* */ | |
| 729 | − } s; | |
| 730 | −}; | |
| 731 | − | |
| 732 | −/* ========================================================================= */ | |
| 733 | −/* UVH_SI_ADDR_MAP_CONFIG */ | |
| 734 | −/* ========================================================================= */ | |
| 735 | −#define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL | |
| 736 | − | |
| 737 | −#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0 | |
| 738 | −#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL | |
| 739 | −#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8 | |
| 740 | −#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL | |
| 741 | − | |
| 742 | −union uvh_si_addr_map_config_u { | |
| 743 | − unsigned long v; | |
| 744 | − struct uvh_si_addr_map_config_s { | |
| 745 | − unsigned long m_skt : 6; /* RW */ | |
| 746 | − unsigned long rsvd_6_7: 2; /* */ | |
| 747 | − unsigned long n_skt : 4; /* RW */ | |
| 748 | − unsigned long rsvd_12_63: 52; /* */ | |
| 749 | − } s; | |
| 750 | −}; | |
| 751 | − | |
| 752 | −/* ========================================================================= */ | |
| 753 | −/* UVH_SI_ALIAS0_OVERLAY_CONFIG */ | |
| 754 | −/* ========================================================================= */ | |
| 755 | −#define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL | |
| 756 | − | |
| 757 | −#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24 | |
| 758 | −#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL | |
| 759 | −#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48 | |
| 760 | −#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL | |
| 761 | −#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63 | |
| 762 | −#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL | |
| 763 | − | |
| 764 | −union uvh_si_alias0_overlay_config_u { | |
| 765 | − unsigned long v; | |
| 766 | − struct uvh_si_alias0_overlay_config_s { | |
| 767 | − unsigned long rsvd_0_23: 24; /* */ | |
| 768 | − unsigned long base : 8; /* RW */ | |
| 769 | − unsigned long rsvd_32_47: 16; /* */ | |
| 770 | − unsigned long m_alias : 5; /* RW */ | |
| 771 | − unsigned long rsvd_53_62: 10; /* */ | |
| 772 | − unsigned long enable : 1; /* RW */ | |
| 773 | − } s; | |
| 774 | −}; | |
| 775 | − | |
| 776 | −/* ========================================================================= */ | |
| 777 | −/* UVH_SI_ALIAS1_OVERLAY_CONFIG */ | |
| 778 | −/* ========================================================================= */ | |
| 779 | −#define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL | |
| 780 | − | |
| 781 | −#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24 | |
| 782 | −#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL | |
| 783 | −#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48 | |
| 784 | −#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL | |
| 785 | −#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63 | |
| 786 | −#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL | |
| 787 | − | |
| 788 | −union uvh_si_alias1_overlay_config_u { | |
| 789 | − unsigned long v; | |
| 790 | − struct uvh_si_alias1_overlay_config_s { | |
| 791 | − unsigned long rsvd_0_23: 24; /* */ | |
| 792 | − unsigned long base : 8; /* RW */ | |
| 793 | − unsigned long rsvd_32_47: 16; /* */ | |
| 794 | − unsigned long m_alias : 5; /* RW */ | |
| 795 | − unsigned long rsvd_53_62: 10; /* */ | |
| 796 | − unsigned long enable : 1; /* RW */ | |
| 797 | − } s; | |
| 798 | −}; | |
| 799 | − | |
| 800 | −/* ========================================================================= */ | |
| 801 | −/* UVH_SI_ALIAS2_OVERLAY_CONFIG */ | |
| 802 | −/* ========================================================================= */ | |
| 803 | −#define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL | |
| 804 | − | |
| 805 | −#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24 | |
| 806 | −#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL | |
| 807 | −#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48 | |
| 808 | −#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL | |
| 809 | −#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63 | |
| 810 | −#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL | |
| 811 | − | |
| 812 | −union uvh_si_alias2_overlay_config_u { | |
| 813 | − unsigned long v; | |
| 814 | − struct uvh_si_alias2_overlay_config_s { | |
| 815 | − unsigned long rsvd_0_23: 24; /* */ | |
| 816 | − unsigned long base : 8; /* RW */ | |
| 817 | − unsigned long rsvd_32_47: 16; /* */ | |
| 818 | − unsigned long m_alias : 5; /* RW */ | |
| 819 | − unsigned long rsvd_53_62: 10; /* */ | |
| 820 | − unsigned long enable : 1; /* RW */ | |
| 821 | − } s; | |
| 822 | −}; | |
| 823 | − | |
| 824 | − | |
| 825 | −#endif /* _ASM_IA64_UV_UV_MMRS_H */ | |
| @@ -1,15 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −/* | |
| 3 | − * Copyright (C) 2003 Hewlett-Packard Co | |
| 4 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 5 | − */ | |
| 6 | − | |
| 7 | −#ifndef _ASM_VERMAGIC_H | |
| 8 | −#define _ASM_VERMAGIC_H | |
| 9 | − | |
| 10 | −#include <linux/stringify.h> | |
| 11 | − | |
| 12 | −#define MODULE_ARCH_VERMAGIC "ia64" \ | |
| 13 | − "gcc-" __stringify(__GNUC__) "." __stringify(__GNUC_MINOR__) | |
| 14 | − | |
| 15 | −#endif /* _ASM_VERMAGIC_H */ | |
| @@ -1,26 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −/* | |
| 3 | − * Access to VGA videoram | |
| 4 | − * | |
| 5 | − * (c) 1998 Martin Mares <mj@ucw.cz> | |
| 6 | − * (c) 1999 Asit Mallick <asit.k.mallick@intel.com> | |
| 7 | − * (c) 1999 Don Dugger <don.dugger@intel.com> | |
| 8 | − */ | |
| 9 | − | |
| 10 | −#ifndef __ASM_IA64_VGA_H_ | |
| 11 | −#define __ASM_IA64_VGA_H_ | |
| 12 | − | |
| 13 | −/* | |
| 14 | − * On the PC, we can just recalculate addresses and then access the | |
| 15 | − * videoram directly without any black magic. | |
| 16 | − */ | |
| 17 | − | |
| 18 | −extern unsigned long vga_console_iobase; | |
| 19 | −extern unsigned long vga_console_membase; | |
| 20 | − | |
| 21 | −#define VGA_MAP_MEM(x,s) ((unsigned long) ioremap(vga_console_membase + (x), s)) | |
| 22 | − | |
| 23 | −#define vga_readb(x) (*(x)) | |
| 24 | −#define vga_writeb(x,y) (*(y) = (x)) | |
| 25 | − | |
| 26 | −#endif /* __ASM_IA64_VGA_H_ */ | |
| @@ -1,4 +0,0 @@ | ||
| 1 | −#ifndef _ASM_IA64_VMALLOC_H | |
| 2 | −#define _ASM_IA64_VMALLOC_H | |
| 3 | − | |
| 4 | −#endif /* _ASM_IA64_VMALLOC_H */ | |
| @@ -1,30 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0-or-later */ | |
| 2 | −/* | |
| 3 | − * Optimized RAID-5 checksumming functions for IA-64. | |
| 4 | − */ | |
| 5 | − | |
| 6 | − | |
| 7 | −extern void xor_ia64_2(unsigned long bytes, unsigned long * __restrict p1, | |
| 8 | − const unsigned long * __restrict p2); | |
| 9 | −extern void xor_ia64_3(unsigned long bytes, unsigned long * __restrict p1, | |
| 10 | − const unsigned long * __restrict p2, | |
| 11 | − const unsigned long * __restrict p3); | |
| 12 | −extern void xor_ia64_4(unsigned long bytes, unsigned long * __restrict p1, | |
| 13 | − const unsigned long * __restrict p2, | |
| 14 | − const unsigned long * __restrict p3, | |
| 15 | − const unsigned long * __restrict p4); | |
| 16 | −extern void xor_ia64_5(unsigned long bytes, unsigned long * __restrict p1, | |
| 17 | − const unsigned long * __restrict p2, | |
| 18 | − const unsigned long * __restrict p3, | |
| 19 | − const unsigned long * __restrict p4, | |
| 20 | − const unsigned long * __restrict p5); | |
| 21 | − | |
| 22 | −static struct xor_block_template xor_block_ia64 = { | |
| 23 | − .name = "ia64", | |
| 24 | − .do_2 = xor_ia64_2, | |
| 25 | − .do_3 = xor_ia64_3, | |
| 26 | − .do_4 = xor_ia64_4, | |
| 27 | − .do_5 = xor_ia64_5, | |
| 28 | −}; | |
| 29 | − | |
| 30 | −#define XOR_TRY_TEMPLATES xor_speed(&xor_block_ia64) | |
| @@ -1,46 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | −#ifndef _ASM_IA64_XTP_H | |
| 3 | −#define _ASM_IA64_XTP_H | |
| 4 | − | |
| 5 | −#include <asm/io.h> | |
| 6 | − | |
| 7 | −#ifdef CONFIG_SMP | |
| 8 | − | |
| 9 | −#define XTP_OFFSET 0x1e0008 | |
| 10 | − | |
| 11 | −#define SMP_IRQ_REDIRECTION (1 << 0) | |
| 12 | −#define SMP_IPI_REDIRECTION (1 << 1) | |
| 13 | − | |
| 14 | −extern unsigned char smp_int_redirect; | |
| 15 | − | |
| 16 | −/* | |
| 17 | − * XTP control functions: | |
| 18 | − * min_xtp : route all interrupts to this CPU | |
| 19 | − * normal_xtp: nominal XTP value | |
| 20 | − * max_xtp : never deliver interrupts to this CPU. | |
| 21 | − */ | |
| 22 | − | |
| 23 | −static inline void | |
| 24 | −min_xtp (void) | |
| 25 | −{ | |
| 26 | − if (smp_int_redirect & SMP_IRQ_REDIRECTION) | |
| 27 | − writeb(0x00, ipi_base_addr + XTP_OFFSET); /* XTP to min */ | |
| 28 | −} | |
| 29 | − | |
| 30 | −static inline void | |
| 31 | −normal_xtp (void) | |
| 32 | −{ | |
| 33 | − if (smp_int_redirect & SMP_IRQ_REDIRECTION) | |
| 34 | − writeb(0x08, ipi_base_addr + XTP_OFFSET); /* XTP normal */ | |
| 35 | −} | |
| 36 | − | |
| 37 | −static inline void | |
| 38 | −max_xtp (void) | |
| 39 | −{ | |
| 40 | − if (smp_int_redirect & SMP_IRQ_REDIRECTION) | |
| 41 | − writeb(0x0f, ipi_base_addr + XTP_OFFSET); /* Set XTP to max */ | |
| 42 | −} | |
| 43 | − | |
| 44 | −#endif /* CONFIG_SMP */ | |
| 45 | − | |
| 46 | −#endif /* _ASM_IA64_XTP_Hy */ | |
| @@ -1,2 +0,0 @@ | ||
| 1 | −# SPDX-License-Identifier: GPL-2.0 | |
| 2 | −generated-y += unistd_64.h | |
| @@ -1,14 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ | |
| 2 | −#ifndef _ASM_IA64_AUXVEC_H | |
| 3 | −#define _ASM_IA64_AUXVEC_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Architecture-neutral AT_ values are in the range 0-17. Leave some room for more of | |
| 7 | − * them, start the architecture-specific ones at 32. | |
| 8 | − */ | |
| 9 | −#define AT_SYSINFO 32 | |
| 10 | −#define AT_SYSINFO_EHDR 33 | |
| 11 | − | |
| 12 | −#define AT_VECTOR_SIZE_ARCH 2 /* entries in ARCH_DLINFO */ | |
| 13 | − | |
| 14 | −#endif /* _ASM_IA64_AUXVEC_H */ | |
| @@ -1,9 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ | |
| 2 | −#ifndef __ASM_IA64_BITSPERLONG_H | |
| 3 | −#define __ASM_IA64_BITSPERLONG_H | |
| 4 | − | |
| 5 | −#define __BITS_PER_LONG 64 | |
| 6 | − | |
| 7 | −#include <asm-generic/bitsperlong.h> | |
| 8 | − | |
| 9 | −#endif /* __ASM_IA64_BITSPERLONG_H */ | |
| @@ -1,23 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ | |
| 2 | −#ifndef _ASM_IA64_BREAK_H | |
| 3 | −#define _ASM_IA64_BREAK_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * IA-64 Linux break numbers. | |
| 7 | − * | |
| 8 | − * Copyright (C) 1999 Hewlett-Packard Co | |
| 9 | − * Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com> | |
| 10 | − */ | |
| 11 | − | |
| 12 | −/* | |
| 13 | − * OS-specific debug break numbers: | |
| 14 | − */ | |
| 15 | −#define __IA64_BREAK_KDB 0x80100 | |
| 16 | −#define __IA64_BREAK_KPROBE 0x81000 /* .. 0x81fff */ | |
| 17 | − | |
| 18 | −/* | |
| 19 | − * OS-specific break numbers: | |
| 20 | − */ | |
| 21 | −#define __IA64_BREAK_SYSCALL 0x100000 | |
| 22 | − | |
| 23 | −#endif /* _ASM_IA64_BREAK_H */ | |
| @@ -1,7 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ | |
| 2 | −#ifndef _ASM_IA64_BYTEORDER_H | |
| 3 | −#define _ASM_IA64_BYTEORDER_H | |
| 4 | − | |
| 5 | −#include <linux/byteorder/little_endian.h> | |
| 6 | − | |
| 7 | −#endif /* _ASM_IA64_BYTEORDER_H */ | |
| @@ -1,138 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ | |
| 2 | −#ifndef _UAPI_ASM_IA64_CMPXCHG_H | |
| 3 | −#define _UAPI_ASM_IA64_CMPXCHG_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Compare/Exchange, forked from asm/intrinsics.h | |
| 7 | − * which was: | |
| 8 | − * | |
| 9 | − * Copyright (C) 2002-2003 Hewlett-Packard Co | |
| 10 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 11 | − */ | |
| 12 | − | |
| 13 | −#ifndef __ASSEMBLY__ | |
| 14 | − | |
| 15 | −#include <linux/types.h> | |
| 16 | −/* include compiler specific intrinsics */ | |
| 17 | −#include <asm/ia64regs.h> | |
| 18 | −#include <asm/gcc_intrin.h> | |
| 19 | − | |
| 20 | −/* | |
| 21 | − * This function doesn't exist, so you'll get a linker error if | |
| 22 | − * something tries to do an invalid xchg(). | |
| 23 | − */ | |
| 24 | −extern void ia64_xchg_called_with_bad_pointer(void); | |
| 25 | − | |
| 26 | −#define __arch_xchg(x, ptr, size) \ | |
| 27 | −({ \ | |
| 28 | − unsigned long __xchg_result; \ | |
| 29 | − \ | |
| 30 | − switch (size) { \ | |
| 31 | − case 1: \ | |
| 32 | − __xchg_result = ia64_xchg1((__u8 __force *)ptr, x); \ | |
| 33 | − break; \ | |
| 34 | − \ | |
| 35 | − case 2: \ | |
| 36 | − __xchg_result = ia64_xchg2((__u16 __force *)ptr, x); \ | |
| 37 | − break; \ | |
| 38 | − \ | |
| 39 | − case 4: \ | |
| 40 | − __xchg_result = ia64_xchg4((__u32 __force *)ptr, x); \ | |
| 41 | − break; \ | |
| 42 | − \ | |
| 43 | − case 8: \ | |
| 44 | − __xchg_result = ia64_xchg8((__u64 __force *)ptr, x); \ | |
| 45 | − break; \ | |
| 46 | − default: \ | |
| 47 | − ia64_xchg_called_with_bad_pointer(); \ | |
| 48 | − } \ | |
| 49 | − (__typeof__ (*(ptr)) __force) __xchg_result; \ | |
| 50 | −}) | |
| 51 | − | |
| 52 | −#ifndef __KERNEL__ | |
| 53 | −#define xchg(ptr, x) \ | |
| 54 | −({(__typeof__(*(ptr))) __arch_xchg((unsigned long) (x), (ptr), sizeof(*(ptr)));}) | |
| 55 | −#endif | |
| 56 | − | |
| 57 | −/* | |
| 58 | − * Atomic compare and exchange. Compare OLD with MEM, if identical, | |
| 59 | − * store NEW in MEM. Return the initial value in MEM. Success is | |
| 60 | − * indicated by comparing RETURN with OLD. | |
| 61 | − */ | |
| 62 | − | |
| 63 | −/* | |
| 64 | − * This function doesn't exist, so you'll get a linker error | |
| 65 | − * if something tries to do an invalid cmpxchg(). | |
| 66 | − */ | |
| 67 | −extern long ia64_cmpxchg_called_with_bad_pointer(void); | |
| 68 | − | |
| 69 | −#define ia64_cmpxchg(sem, ptr, old, new, size) \ | |
| 70 | −({ \ | |
| 71 | − __u64 _o_, _r_; \ | |
| 72 | − \ | |
| 73 | − switch (size) { \ | |
| 74 | − case 1: \ | |
| 75 | − _o_ = (__u8) (long __force) (old); \ | |
| 76 | − break; \ | |
| 77 | − case 2: \ | |
| 78 | − _o_ = (__u16) (long __force) (old); \ | |
| 79 | − break; \ | |
| 80 | − case 4: \ | |
| 81 | − _o_ = (__u32) (long __force) (old); \ | |
| 82 | − break; \ | |
| 83 | − case 8: \ | |
| 84 | − _o_ = (__u64) (long __force) (old); \ | |
| 85 | − break; \ | |
| 86 | − default: \ | |
| 87 | − break; \ | |
| 88 | − } \ | |
| 89 | − switch (size) { \ | |
| 90 | − case 1: \ | |
| 91 | − _r_ = ia64_cmpxchg1_##sem((__u8 __force *) ptr, new, _o_); \ | |
| 92 | − break; \ | |
| 93 | − \ | |
| 94 | − case 2: \ | |
| 95 | − _r_ = ia64_cmpxchg2_##sem((__u16 __force *) ptr, new, _o_); \ | |
| 96 | − break; \ | |
| 97 | − \ | |
| 98 | − case 4: \ | |
| 99 | − _r_ = ia64_cmpxchg4_##sem((__u32 __force *) ptr, new, _o_); \ | |
| 100 | − break; \ | |
| 101 | − \ | |
| 102 | − case 8: \ | |
| 103 | − _r_ = ia64_cmpxchg8_##sem((__u64 __force *) ptr, new, _o_); \ | |
| 104 | − break; \ | |
| 105 | − \ | |
| 106 | − default: \ | |
| 107 | − _r_ = ia64_cmpxchg_called_with_bad_pointer(); \ | |
| 108 | − break; \ | |
| 109 | − } \ | |
| 110 | − (__typeof__(old) __force) _r_; \ | |
| 111 | −}) | |
| 112 | − | |
| 113 | −#define cmpxchg_acq(ptr, o, n) \ | |
| 114 | − ia64_cmpxchg(acq, (ptr), (o), (n), sizeof(*(ptr))) | |
| 115 | −#define cmpxchg_rel(ptr, o, n) \ | |
| 116 | − ia64_cmpxchg(rel, (ptr), (o), (n), sizeof(*(ptr))) | |
| 117 | − | |
| 118 | −/* | |
| 119 | − * Worse still - early processor implementations actually just ignored | |
| 120 | − * the acquire/release and did a full fence all the time. Unfortunately | |
| 121 | − * this meant a lot of badly written code that used .acq when they really | |
| 122 | − * wanted .rel became legacy out in the wild - so when we made a cpu | |
| 123 | − * that strictly did the .acq or .rel ... all that code started breaking - so | |
| 124 | − * we had to back-pedal and keep the "legacy" behavior of a full fence :-( | |
| 125 | − */ | |
| 126 | − | |
| 127 | −#ifndef __KERNEL__ | |
| 128 | −/* for compatibility with other platforms: */ | |
| 129 | −#define cmpxchg(ptr, o, n) cmpxchg_acq((ptr), (o), (n)) | |
| 130 | −#define cmpxchg64(ptr, o, n) cmpxchg_acq((ptr), (o), (n)) | |
| 131 | − | |
| 132 | −#define cmpxchg_local cmpxchg | |
| 133 | −#define cmpxchg64_local cmpxchg64 | |
| 134 | −#endif | |
| 135 | − | |
| 136 | −#endif /* !__ASSEMBLY__ */ | |
| 137 | − | |
| 138 | −#endif /* _UAPI_ASM_IA64_CMPXCHG_H */ | |
| @@ -1,15 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ | |
| 2 | −#ifndef _ASM_IA64_FCNTL_H | |
| 3 | −#define _ASM_IA64_FCNTL_H | |
| 4 | −/* | |
| 5 | − * Modified 1998-2000 | |
| 6 | − * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co. | |
| 7 | − */ | |
| 8 | − | |
| 9 | −#define force_o_largefile() \ | |
| 10 | − (personality(current->personality) != PER_LINUX32) | |
| 11 | − | |
| 12 | −#include <linux/personality.h> | |
| 13 | −#include <asm-generic/fcntl.h> | |
| 14 | − | |
| 15 | −#endif /* _ASM_IA64_FCNTL_H */ | |
| @@ -1,67 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ | |
| 2 | −#ifndef _ASM_IA64_FPU_H | |
| 3 | −#define _ASM_IA64_FPU_H | |
| 4 | − | |
| 5 | −/* | |
| 6 | − * Copyright (C) 1998, 1999, 2002, 2003 Hewlett-Packard Co | |
| 7 | − * David Mosberger-Tang <davidm@hpl.hp.com> | |
| 8 | − */ | |
| 9 | − | |
| 10 | −#include <linux/types.h> | |
| 11 | − | |
| 12 | −/* floating point status register: */ | |
| 13 | −#define FPSR_TRAP_VD (1 << 0) /* invalid op trap disabled */ | |
| 14 | −#define FPSR_TRAP_DD (1 << 1) /* denormal trap disabled */ | |
| 15 | −#define FPSR_TRAP_ZD (1 << 2) /* zero-divide trap disabled */ | |
| 16 | −#define FPSR_TRAP_OD (1 << 3) /* overflow trap disabled */ | |
| 17 | −#define FPSR_TRAP_UD (1 << 4) /* underflow trap disabled */ | |
| 18 | −#define FPSR_TRAP_ID (1 << 5) /* inexact trap disabled */ | |
| 19 | −#define FPSR_S0(x) ((x) << 6) | |
| 20 | −#define FPSR_S1(x) ((x) << 19) | |
| 21 | −#define FPSR_S2(x) (__IA64_UL(x) << 32) | |
| 22 | −#define FPSR_S3(x) (__IA64_UL(x) << 45) | |
| 23 | − | |
| 24 | −/* floating-point status field controls: */ | |
| 25 | −#define FPSF_FTZ (1 << 0) /* flush-to-zero */ | |
| 26 | −#define FPSF_WRE (1 << 1) /* widest-range exponent */ | |
| 27 | −#define FPSF_PC(x) (((x) & 0x3) << 2) /* precision control */ | |
| 28 | −#define FPSF_RC(x) (((x) & 0x3) << 4) /* rounding control */ | |
| 29 | −#define FPSF_TD (1 << 6) /* trap disabled */ | |
| 30 | − | |
| 31 | −/* floating-point status field flags: */ | |
| 32 | −#define FPSF_V (1 << 7) /* invalid operation flag */ | |
| 33 | −#define FPSF_D (1 << 8) /* denormal/unnormal operand flag */ | |
| 34 | −#define FPSF_Z (1 << 9) /* zero divide (IEEE) flag */ | |
| 35 | −#define FPSF_O (1 << 10) /* overflow (IEEE) flag */ | |
| 36 | −#define FPSF_U (1 << 11) /* underflow (IEEE) flag */ | |
| 37 | −#define FPSF_I (1 << 12) /* inexact (IEEE) flag) */ | |
| 38 | − | |
| 39 | −/* floating-point rounding control: */ | |
| 40 | −#define FPRC_NEAREST 0x0 | |
| 41 | −#define FPRC_NEGINF 0x1 | |
| 42 | −#define FPRC_POSINF 0x2 | |
| 43 | −#define FPRC_TRUNC 0x3 | |
| 44 | − | |
| 45 | −#define FPSF_DEFAULT (FPSF_PC (0x3) | FPSF_RC (FPRC_NEAREST)) | |
| 46 | − | |
| 47 | −/* This default value is the same as HP-UX uses. Don't change it | |
| 48 | − without a very good reason. */ | |
| 49 | −#define FPSR_DEFAULT (FPSR_TRAP_VD | FPSR_TRAP_DD | FPSR_TRAP_ZD \ | |
| 50 | − | FPSR_TRAP_OD | FPSR_TRAP_UD | FPSR_TRAP_ID \ | |
| 51 | − | FPSR_S0 (FPSF_DEFAULT) \ | |
| 52 | − | FPSR_S1 (FPSF_DEFAULT | FPSF_TD | FPSF_WRE) \ | |
| 53 | − | FPSR_S2 (FPSF_DEFAULT | FPSF_TD) \ | |
| 54 | − | FPSR_S3 (FPSF_DEFAULT | FPSF_TD)) | |
| 55 | − | |
| 56 | −# ifndef __ASSEMBLY__ | |
| 57 | − | |
| 58 | −struct ia64_fpreg { | |
| 59 | − union { | |
| 60 | − unsigned long bits[2]; | |
| 61 | − long double __dummy; /* force 16-byte alignment */ | |
| 62 | − } u; | |
| 63 | −}; | |
| 64 | − | |
| 65 | −# endif /* __ASSEMBLY__ */ | |
| 66 | − | |
| 67 | −#endif /* _ASM_IA64_FPU_H */ | |
| @@ -1,619 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ | |
| 2 | −/* | |
| 3 | − * | |
| 4 | − * Copyright (C) 2002,2003 Jun Nakajima <jun.nakajima@intel.com> | |
| 5 | − * Copyright (C) 2002,2003 Suresh Siddha <suresh.b.siddha@intel.com> | |
| 6 | − */ | |
| 7 | −#ifndef _UAPI_ASM_IA64_GCC_INTRIN_H | |
| 8 | −#define _UAPI_ASM_IA64_GCC_INTRIN_H | |
| 9 | − | |
| 10 | −#include <linux/types.h> | |
| 11 | −#include <linux/compiler.h> | |
| 12 | − | |
| 13 | −/* define this macro to get some asm stmts included in 'c' files */ | |
| 14 | −#define ASM_SUPPORTED | |
| 15 | − | |
| 16 | −/* Optimization barrier */ | |
| 17 | −/* The "volatile" is due to gcc bugs */ | |
| 18 | −#define ia64_barrier() asm volatile ("":::"memory") | |
| 19 | − | |
| 20 | −#define ia64_stop() asm volatile (";;"::) | |
| 21 | − | |
| 22 | −#define ia64_invala_gr(regnum) asm volatile ("invala.e r%0" :: "i"(regnum)) | |
| 23 | − | |
| 24 | −#define ia64_invala_fr(regnum) asm volatile ("invala.e f%0" :: "i"(regnum)) | |
| 25 | − | |
| 26 | −#define ia64_flushrs() asm volatile ("flushrs;;":::"memory") | |
| 27 | − | |
| 28 | −#define ia64_loadrs() asm volatile ("loadrs;;":::"memory") | |
| 29 | − | |
| 30 | −extern void ia64_bad_param_for_setreg (void); | |
| 31 | −extern void ia64_bad_param_for_getreg (void); | |
| 32 | − | |
| 33 | − | |
| 34 | −#define ia64_setreg(regnum, val) \ | |
| 35 | −({ \ | |
| 36 | − switch (regnum) { \ | |
| 37 | − case _IA64_REG_PSR_L: \ | |
| 38 | − asm volatile ("mov psr.l=%0" :: "r"(val) : "memory"); \ | |
| 39 | − break; \ | |
| 40 | − case _IA64_REG_AR_KR0 ... _IA64_REG_AR_EC: \ | |
| 41 | − asm volatile ("mov ar%0=%1" :: \ | |
| 42 | − "i" (regnum - _IA64_REG_AR_KR0), \ | |
| 43 | − "r"(val): "memory"); \ | |
| 44 | − break; \ | |
| 45 | − case _IA64_REG_CR_DCR ... _IA64_REG_CR_LRR1: \ | |
| 46 | − asm volatile ("mov cr%0=%1" :: \ | |
| 47 | − "i" (regnum - _IA64_REG_CR_DCR), \ | |
| 48 | − "r"(val): "memory" ); \ | |
| 49 | − break; \ | |
| 50 | − case _IA64_REG_SP: \ | |
| 51 | − asm volatile ("mov r12=%0" :: \ | |
| 52 | − "r"(val): "memory"); \ | |
| 53 | − break; \ | |
| 54 | − case _IA64_REG_GP: \ | |
| 55 | − asm volatile ("mov gp=%0" :: "r"(val) : "memory"); \ | |
| 56 | − break; \ | |
| 57 | − default: \ | |
| 58 | − ia64_bad_param_for_setreg(); \ | |
| 59 | − break; \ | |
| 60 | − } \ | |
| 61 | −}) | |
| 62 | − | |
| 63 | −#define ia64_getreg(regnum) \ | |
| 64 | −({ \ | |
| 65 | − __u64 ia64_intri_res; \ | |
| 66 | − \ | |
| 67 | − switch (regnum) { \ | |
| 68 | − case _IA64_REG_GP: \ | |
| 69 | − asm volatile ("mov %0=gp" : "=r"(ia64_intri_res)); \ | |
| 70 | − break; \ | |
| 71 | − case _IA64_REG_IP: \ | |
| 72 | − asm volatile ("mov %0=ip" : "=r"(ia64_intri_res)); \ | |
| 73 | − break; \ | |
| 74 | − case _IA64_REG_PSR: \ | |
| 75 | − asm volatile ("mov %0=psr" : "=r"(ia64_intri_res)); \ | |
| 76 | − break; \ | |
| 77 | − case _IA64_REG_TP: /* for current() */ \ | |
| 78 | − ia64_intri_res = ia64_r13; \ | |
| 79 | − break; \ | |
| 80 | − case _IA64_REG_AR_KR0 ... _IA64_REG_AR_EC: \ | |
| 81 | − asm volatile ("mov %0=ar%1" : "=r" (ia64_intri_res) \ | |
| 82 | − : "i"(regnum - _IA64_REG_AR_KR0)); \ | |
| 83 | − break; \ | |
| 84 | − case _IA64_REG_CR_DCR ... _IA64_REG_CR_LRR1: \ | |
| 85 | − asm volatile ("mov %0=cr%1" : "=r" (ia64_intri_res) \ | |
| 86 | − : "i" (regnum - _IA64_REG_CR_DCR)); \ | |
| 87 | − break; \ | |
| 88 | − case _IA64_REG_SP: \ | |
| 89 | − asm volatile ("mov %0=sp" : "=r" (ia64_intri_res)); \ | |
| 90 | − break; \ | |
| 91 | − default: \ | |
| 92 | − ia64_bad_param_for_getreg(); \ | |
| 93 | − break; \ | |
| 94 | − } \ | |
| 95 | − ia64_intri_res; \ | |
| 96 | −}) | |
| 97 | − | |
| 98 | −#define ia64_hint_pause 0 | |
| 99 | − | |
| 100 | −#define ia64_hint(mode) \ | |
| 101 | −({ \ | |
| 102 | − switch (mode) { \ | |
| 103 | − case ia64_hint_pause: \ | |
| 104 | − asm volatile ("hint @pause" ::: "memory"); \ | |
| 105 | − break; \ | |
| 106 | − } \ | |
| 107 | −}) | |
| 108 | − | |
| 109 | − | |
| 110 | −/* Integer values for mux1 instruction */ | |
| 111 | −#define ia64_mux1_brcst 0 | |
| 112 | −#define ia64_mux1_mix 8 | |
| 113 | −#define ia64_mux1_shuf 9 | |
| 114 | −#define ia64_mux1_alt 10 | |
| 115 | −#define ia64_mux1_rev 11 | |
| 116 | − | |
| 117 | −#define ia64_mux1(x, mode) \ | |
| 118 | −({ \ | |
| 119 | − __u64 ia64_intri_res; \ | |
| 120 | − \ | |
| 121 | − switch (mode) { \ | |
| 122 | − case ia64_mux1_brcst: \ | |
| 123 | − asm ("mux1 %0=%1,@brcst" : "=r" (ia64_intri_res) : "r" (x)); \ | |
| 124 | − break; \ | |
| 125 | − case ia64_mux1_mix: \ | |
| 126 | − asm ("mux1 %0=%1,@mix" : "=r" (ia64_intri_res) : "r" (x)); \ | |
| 127 | − break; \ | |
| 128 | − case ia64_mux1_shuf: \ | |
| 129 | − asm ("mux1 %0=%1,@shuf" : "=r" (ia64_intri_res) : "r" (x)); \ | |
| 130 | − break; \ | |
| 131 | − case ia64_mux1_alt: \ | |
| 132 | − asm ("mux1 %0=%1,@alt" : "=r" (ia64_intri_res) : "r" (x)); \ | |
| 133 | − break; \ | |
| 134 | − case ia64_mux1_rev: \ | |
| 135 | − asm ("mux1 %0=%1,@rev" : "=r" (ia64_intri_res) : "r" (x)); \ | |
| 136 | − break; \ | |
| 137 | − } \ | |
| 138 | − ia64_intri_res; \ | |
| 139 | −}) | |
| 140 | − | |
| 141 | −#if __GNUC__ >= 4 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4) | |
| 142 | −# define ia64_popcnt(x) __builtin_popcountl(x) | |
| 143 | −#else | |
| 144 | −# define ia64_popcnt(x) \ | |
| 145 | − ({ \ | |
| 146 | − __u64 ia64_intri_res; \ | |
| 147 | − asm ("popcnt %0=%1" : "=r" (ia64_intri_res) : "r" (x)); \ | |
| 148 | − \ | |
| 149 | − ia64_intri_res; \ | |
| 150 | − }) | |
| 151 | −#endif | |
| 152 | − | |
| 153 | −#define ia64_getf_exp(x) \ | |
| 154 | −({ \ | |
| 155 | − long ia64_intri_res; \ | |
| 156 | − \ | |
| 157 | − asm ("getf.exp %0=%1" : "=r"(ia64_intri_res) : "f"(x)); \ | |
| 158 | − \ | |
| 159 | − ia64_intri_res; \ | |
| 160 | −}) | |
| 161 | − | |
| 162 | −#define ia64_shrp(a, b, count) \ | |
| 163 | −({ \ | |
| 164 | − __u64 ia64_intri_res; \ | |
| 165 | − asm ("shrp %0=%1,%2,%3" : "=r"(ia64_intri_res) : "r"(a), "r"(b), "i"(count)); \ | |
| 166 | − ia64_intri_res; \ | |
| 167 | −}) | |
| 168 | − | |
| 169 | −#define ia64_ldfs(regnum, x) \ | |
| 170 | −({ \ | |
| 171 | − register double __f__ asm ("f"#regnum); \ | |
| 172 | − asm volatile ("ldfs %0=[%1]" :"=f"(__f__): "r"(x)); \ | |
| 173 | −}) | |
| 174 | − | |
| 175 | −#define ia64_ldfd(regnum, x) \ | |
| 176 | −({ \ | |
| 177 | − register double __f__ asm ("f"#regnum); \ | |
| 178 | − asm volatile ("ldfd %0=[%1]" :"=f"(__f__): "r"(x)); \ | |
| 179 | −}) | |
| 180 | − | |
| 181 | −#define ia64_ldfe(regnum, x) \ | |
| 182 | −({ \ | |
| 183 | − register double __f__ asm ("f"#regnum); \ | |
| 184 | − asm volatile ("ldfe %0=[%1]" :"=f"(__f__): "r"(x)); \ | |
| 185 | −}) | |
| 186 | − | |
| 187 | −#define ia64_ldf8(regnum, x) \ | |
| 188 | −({ \ | |
| 189 | − register double __f__ asm ("f"#regnum); \ | |
| 190 | − asm volatile ("ldf8 %0=[%1]" :"=f"(__f__): "r"(x)); \ | |
| 191 | −}) | |
| 192 | − | |
| 193 | −#define ia64_ldf_fill(regnum, x) \ | |
| 194 | −({ \ | |
| 195 | − register double __f__ asm ("f"#regnum); \ | |
| 196 | − asm volatile ("ldf.fill %0=[%1]" :"=f"(__f__): "r"(x)); \ | |
| 197 | −}) | |
| 198 | − | |
| 199 | −#define ia64_st4_rel_nta(m, val) \ | |
| 200 | −({ \ | |
| 201 | − asm volatile ("st4.rel.nta [%0] = %1\n\t" :: "r"(m), "r"(val)); \ | |
| 202 | −}) | |
| 203 | − | |
| 204 | −#define ia64_stfs(x, regnum) \ | |
| 205 | −({ \ | |
| 206 | − register double __f__ asm ("f"#regnum); \ | |
| 207 | − asm volatile ("stfs [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \ | |
| 208 | −}) | |
| 209 | − | |
| 210 | −#define ia64_stfd(x, regnum) \ | |
| 211 | −({ \ | |
| 212 | − register double __f__ asm ("f"#regnum); \ | |
| 213 | − asm volatile ("stfd [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \ | |
| 214 | −}) | |
| 215 | − | |
| 216 | −#define ia64_stfe(x, regnum) \ | |
| 217 | −({ \ | |
| 218 | − register double __f__ asm ("f"#regnum); \ | |
| 219 | − asm volatile ("stfe [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \ | |
| 220 | −}) | |
| 221 | − | |
| 222 | −#define ia64_stf8(x, regnum) \ | |
| 223 | −({ \ | |
| 224 | − register double __f__ asm ("f"#regnum); \ | |
| 225 | − asm volatile ("stf8 [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \ | |
| 226 | −}) | |
| 227 | − | |
| 228 | −#define ia64_stf_spill(x, regnum) \ | |
| 229 | −({ \ | |
| 230 | − register double __f__ asm ("f"#regnum); \ | |
| 231 | − asm volatile ("stf.spill [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \ | |
| 232 | −}) | |
| 233 | − | |
| 234 | −#define ia64_fetchadd4_acq(p, inc) \ | |
| 235 | −({ \ | |
| 236 | − \ | |
| 237 | − __u64 ia64_intri_res; \ | |
| 238 | − asm volatile ("fetchadd4.acq %0=[%1],%2" \ | |
| 239 | − : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \ | |
| 240 | − : "memory"); \ | |
| 241 | − \ | |
| 242 | − ia64_intri_res; \ | |
| 243 | −}) | |
| 244 | − | |
| 245 | −#define ia64_fetchadd4_rel(p, inc) \ | |
| 246 | −({ \ | |
| 247 | − __u64 ia64_intri_res; \ | |
| 248 | − asm volatile ("fetchadd4.rel %0=[%1],%2" \ | |
| 249 | − : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \ | |
| 250 | − : "memory"); \ | |
| 251 | − \ | |
| 252 | − ia64_intri_res; \ | |
| 253 | −}) | |
| 254 | − | |
| 255 | −#define ia64_fetchadd8_acq(p, inc) \ | |
| 256 | −({ \ | |
| 257 | − \ | |
| 258 | − __u64 ia64_intri_res; \ | |
| 259 | − asm volatile ("fetchadd8.acq %0=[%1],%2" \ | |
| 260 | − : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \ | |
| 261 | − : "memory"); \ | |
| 262 | − \ | |
| 263 | − ia64_intri_res; \ | |
| 264 | −}) | |
| 265 | − | |
| 266 | −#define ia64_fetchadd8_rel(p, inc) \ | |
| 267 | −({ \ | |
| 268 | − __u64 ia64_intri_res; \ | |
| 269 | − asm volatile ("fetchadd8.rel %0=[%1],%2" \ | |
| 270 | − : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \ | |
| 271 | − : "memory"); \ | |
| 272 | − \ | |
| 273 | − ia64_intri_res; \ | |
| 274 | −}) | |
| 275 | − | |
| 276 | −#define ia64_xchg1(ptr,x) \ | |
| 277 | −({ \ | |
| 278 | − __u64 ia64_intri_res; \ | |
| 279 | − asm volatile ("xchg1 %0=[%1],%2" \ | |
| 280 | − : "=r" (ia64_intri_res) : "r" (ptr), "r" (x) : "memory"); \ | |
| 281 | − ia64_intri_res; \ | |
| 282 | −}) | |
| 283 | − | |
| 284 | −#define ia64_xchg2(ptr,x) \ | |
| 285 | −({ \ | |
| 286 | − __u64 ia64_intri_res; \ | |
| 287 | − asm volatile ("xchg2 %0=[%1],%2" : "=r" (ia64_intri_res) \ | |
| 288 | − : "r" (ptr), "r" (x) : "memory"); \ | |
| 289 | − ia64_intri_res; \ | |
| 290 | −}) | |
| 291 | − | |
| 292 | −#define ia64_xchg4(ptr,x) \ | |
| 293 | −({ \ | |
| 294 | − __u64 ia64_intri_res; \ | |
| 295 | − asm volatile ("xchg4 %0=[%1],%2" : "=r" (ia64_intri_res) \ | |
| 296 | − : "r" (ptr), "r" (x) : "memory"); \ | |
| 297 | − ia64_intri_res; \ | |
| 298 | −}) | |
| 299 | − | |
| 300 | −#define ia64_xchg8(ptr,x) \ | |
| 301 | −({ \ | |
| 302 | − __u64 ia64_intri_res; \ | |
| 303 | − asm volatile ("xchg8 %0=[%1],%2" : "=r" (ia64_intri_res) \ | |
| 304 | − : "r" (ptr), "r" (x) : "memory"); \ | |
| 305 | − ia64_intri_res; \ | |
| 306 | −}) | |
| 307 | − | |
| 308 | −#define ia64_cmpxchg1_acq(ptr, new, old) \ | |
| 309 | −({ \ | |
| 310 | − __u64 ia64_intri_res; \ | |
| 311 | − asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ | |
| 312 | − asm volatile ("cmpxchg1.acq %0=[%1],%2,ar.ccv": \ | |
| 313 | − "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ | |
| 314 | − ia64_intri_res; \ | |
| 315 | −}) | |
| 316 | − | |
| 317 | −#define ia64_cmpxchg1_rel(ptr, new, old) \ | |
| 318 | −({ \ | |
| 319 | − __u64 ia64_intri_res; \ | |
| 320 | − asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ | |
| 321 | − asm volatile ("cmpxchg1.rel %0=[%1],%2,ar.ccv": \ | |
| 322 | − "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ | |
| 323 | − ia64_intri_res; \ | |
| 324 | −}) | |
| 325 | − | |
| 326 | −#define ia64_cmpxchg2_acq(ptr, new, old) \ | |
| 327 | −({ \ | |
| 328 | − __u64 ia64_intri_res; \ | |
| 329 | − asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ | |
| 330 | − asm volatile ("cmpxchg2.acq %0=[%1],%2,ar.ccv": \ | |
| 331 | − "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ | |
| 332 | − ia64_intri_res; \ | |
| 333 | −}) | |
| 334 | − | |
| 335 | −#define ia64_cmpxchg2_rel(ptr, new, old) \ | |
| 336 | −({ \ | |
| 337 | − __u64 ia64_intri_res; \ | |
| 338 | − asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ | |
| 339 | − \ | |
| 340 | − asm volatile ("cmpxchg2.rel %0=[%1],%2,ar.ccv": \ | |
| 341 | − "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ | |
| 342 | − ia64_intri_res; \ | |
| 343 | −}) | |
| 344 | − | |
| 345 | −#define ia64_cmpxchg4_acq(ptr, new, old) \ | |
| 346 | −({ \ | |
| 347 | − __u64 ia64_intri_res; \ | |
| 348 | − asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ | |
| 349 | − asm volatile ("cmpxchg4.acq %0=[%1],%2,ar.ccv": \ | |
| 350 | − "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ | |
| 351 | − ia64_intri_res; \ | |
| 352 | −}) | |
| 353 | − | |
| 354 | −#define ia64_cmpxchg4_rel(ptr, new, old) \ | |
| 355 | −({ \ | |
| 356 | − __u64 ia64_intri_res; \ | |
| 357 | − asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ | |
| 358 | − asm volatile ("cmpxchg4.rel %0=[%1],%2,ar.ccv": \ | |
| 359 | − "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ | |
| 360 | − ia64_intri_res; \ | |
| 361 | −}) | |
| 362 | − | |
| 363 | −#define ia64_cmpxchg8_acq(ptr, new, old) \ | |
| 364 | −({ \ | |
| 365 | − __u64 ia64_intri_res; \ | |
| 366 | − asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ | |
| 367 | − asm volatile ("cmpxchg8.acq %0=[%1],%2,ar.ccv": \ | |
| 368 | − "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ | |
| 369 | − ia64_intri_res; \ | |
| 370 | −}) | |
| 371 | − | |
| 372 | −#define ia64_cmpxchg8_rel(ptr, new, old) \ | |
| 373 | −({ \ | |
| 374 | − __u64 ia64_intri_res; \ | |
| 375 | − asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ | |
| 376 | − \ | |
| 377 | − asm volatile ("cmpxchg8.rel %0=[%1],%2,ar.ccv": \ | |
| 378 | − "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ | |
| 379 | − ia64_intri_res; \ | |
| 380 | −}) | |
| 381 | − | |
| 382 | −#define ia64_mf() asm volatile ("mf" ::: "memory") | |
| 383 | −#define ia64_mfa() asm volatile ("mf.a" ::: "memory") | |
| 384 | − | |
| 385 | −#define ia64_invala() asm volatile ("invala" ::: "memory") | |
| 386 | − | |
| 387 | −#define ia64_thash(addr) \ | |
| 388 | −({ \ | |
| 389 | − unsigned long ia64_intri_res; \ | |
| 390 | − asm volatile ("thash %0=%1" : "=r"(ia64_intri_res) : "r" (addr)); \ | |
| 391 | − ia64_intri_res; \ | |
| 392 | −}) | |
| 393 | − | |
| 394 | −#define ia64_srlz_i() asm volatile (";; srlz.i ;;" ::: "memory") | |
| 395 | −#define ia64_srlz_d() asm volatile (";; srlz.d" ::: "memory"); | |
| 396 | − | |
| 397 | −#ifdef HAVE_SERIALIZE_DIRECTIVE | |
| 398 | −# define ia64_dv_serialize_data() asm volatile (".serialize.data"); | |
| 399 | −# define ia64_dv_serialize_instruction() asm volatile (".serialize.instruction"); | |
| 400 | −#else | |
| 401 | −# define ia64_dv_serialize_data() | |
| 402 | −# define ia64_dv_serialize_instruction() | |
| 403 | −#endif | |
| 404 | − | |
| 405 | −#define ia64_nop(x) asm volatile ("nop %0"::"i"(x)); | |
| 406 | − | |
| 407 | −#define ia64_itci(addr) asm volatile ("itc.i %0;;" :: "r"(addr) : "memory") | |
| 408 | − | |
| 409 | −#define ia64_itcd(addr) asm volatile ("itc.d %0;;" :: "r"(addr) : "memory") | |
| 410 | − | |
| 411 | − | |
| 412 | −#define ia64_itri(trnum, addr) asm volatile ("itr.i itr[%0]=%1" \ | |
| 413 | − :: "r"(trnum), "r"(addr) : "memory") | |
| 414 | − | |
| 415 | −#define ia64_itrd(trnum, addr) asm volatile ("itr.d dtr[%0]=%1" \ | |
| 416 | − :: "r"(trnum), "r"(addr) : "memory") | |
| 417 | − | |
| 418 | −#define ia64_tpa(addr) \ | |
| 419 | −({ \ | |
| 420 | − unsigned long ia64_pa; \ | |
| 421 | − asm volatile ("tpa %0 = %1" : "=r"(ia64_pa) : "r"(addr) : "memory"); \ | |
| 422 | − ia64_pa; \ | |
| 423 | −}) | |
| 424 | − | |
| 425 | −#define __ia64_set_dbr(index, val) \ | |
| 426 | − asm volatile ("mov dbr[%0]=%1" :: "r"(index), "r"(val) : "memory") | |
| 427 | − | |
| 428 | −#define ia64_set_ibr(index, val) \ | |
| 429 | − asm volatile ("mov ibr[%0]=%1" :: "r"(index), "r"(val) : "memory") | |
| 430 | − | |
| 431 | −#define ia64_set_pkr(index, val) \ | |
| 432 | − asm volatile ("mov pkr[%0]=%1" :: "r"(index), "r"(val) : "memory") | |
| 433 | − | |
| 434 | −#define ia64_set_pmc(index, val) \ | |
| 435 | − asm volatile ("mov pmc[%0]=%1" :: "r"(index), "r"(val) : "memory") | |
| 436 | − | |
| 437 | −#define ia64_set_pmd(index, val) \ | |
| 438 | − asm volatile ("mov pmd[%0]=%1" :: "r"(index), "r"(val) : "memory") | |
| 439 | − | |
| 440 | −#define ia64_set_rr(index, val) \ | |
| 441 | − asm volatile ("mov rr[%0]=%1" :: "r"(index), "r"(val) : "memory"); | |
| 442 | − | |
| 443 | −#define ia64_get_cpuid(index) \ | |
| 444 | −({ \ | |
| 445 | − unsigned long ia64_intri_res; \ | |
| 446 | − asm volatile ("mov %0=cpuid[%r1]" : "=r"(ia64_intri_res) : "rO"(index)); \ | |
| 447 | − ia64_intri_res; \ | |
| 448 | −}) | |
| 449 | − | |
| 450 | −#define __ia64_get_dbr(index) \ | |
| 451 | −({ \ | |
| 452 | − unsigned long ia64_intri_res; \ | |
| 453 | − asm volatile ("mov %0=dbr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ | |
| 454 | − ia64_intri_res; \ | |
| 455 | −}) | |
| 456 | − | |
| 457 | −#define ia64_get_ibr(index) \ | |
| 458 | −({ \ | |
| 459 | − unsigned long ia64_intri_res; \ | |
| 460 | − asm volatile ("mov %0=ibr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ | |
| 461 | − ia64_intri_res; \ | |
| 462 | −}) | |
| 463 | − | |
| 464 | −#define ia64_get_pkr(index) \ | |
| 465 | −({ \ | |
| 466 | − unsigned long ia64_intri_res; \ | |
| 467 | − asm volatile ("mov %0=pkr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ | |
| 468 | − ia64_intri_res; \ | |
| 469 | −}) | |
| 470 | − | |
| 471 | −#define ia64_get_pmc(index) \ | |
| 472 | −({ \ | |
| 473 | − unsigned long ia64_intri_res; \ | |
| 474 | − asm volatile ("mov %0=pmc[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ | |
| 475 | − ia64_intri_res; \ | |
| 476 | −}) | |
| 477 | − | |
| 478 | − | |
| 479 | −#define ia64_get_pmd(index) \ | |
| 480 | −({ \ | |
| 481 | − unsigned long ia64_intri_res; \ | |
| 482 | − asm volatile ("mov %0=pmd[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ | |
| 483 | − ia64_intri_res; \ | |
| 484 | −}) | |
| 485 | − | |
| 486 | −#define ia64_get_rr(index) \ | |
| 487 | −({ \ | |
| 488 | − unsigned long ia64_intri_res; \ | |
| 489 | − asm volatile ("mov %0=rr[%1]" : "=r"(ia64_intri_res) : "r" (index)); \ | |
| 490 | − ia64_intri_res; \ | |
| 491 | −}) | |
| 492 | − | |
| 493 | −#define ia64_fc(addr) asm volatile ("fc %0" :: "r"(addr) : "memory") | |
| 494 | − | |
| 495 | − | |
| 496 | −#define ia64_sync_i() asm volatile (";; sync.i" ::: "memory") | |
| 497 | − | |
| 498 | −#define ia64_ssm(mask) asm volatile ("ssm %0":: "i"((mask)) : "memory") | |
| 499 | −#define ia64_rsm(mask) asm volatile ("rsm %0":: "i"((mask)) : "memory") | |
| 500 | −#define ia64_sum(mask) asm volatile ("sum %0":: "i"((mask)) : "memory") | |
| 501 | −#define ia64_rum(mask) asm volatile ("rum %0":: "i"((mask)) : "memory") | |
| 502 | − | |
| 503 | −#define ia64_ptce(addr) asm volatile ("ptc.e %0" :: "r"(addr)) | |
| 504 | − | |
| 505 | −#define ia64_ptcga(addr, size) \ | |
| 506 | −do { \ | |
| 507 | − asm volatile ("ptc.ga %0,%1" :: "r"(addr), "r"(size) : "memory"); \ | |
| 508 | − ia64_dv_serialize_data(); \ | |
| 509 | −} while (0) | |
| 510 | − | |
| 511 | −#define ia64_ptcl(addr, size) \ | |
| 512 | −do { \ | |
| 513 | − asm volatile ("ptc.l %0,%1" :: "r"(addr), "r"(size) : "memory"); \ | |
| 514 | − ia64_dv_serialize_data(); \ | |
| 515 | −} while (0) | |
| 516 | − | |
| 517 | −#define ia64_ptri(addr, size) \ | |
| 518 | − asm volatile ("ptr.i %0,%1" :: "r"(addr), "r"(size) : "memory") | |
| 519 | − | |
| 520 | −#define ia64_ptrd(addr, size) \ | |
| 521 | − asm volatile ("ptr.d %0,%1" :: "r"(addr), "r"(size) : "memory") | |
| 522 | − | |
| 523 | −#define ia64_ttag(addr) \ | |
| 524 | −({ \ | |
| 525 | − __u64 ia64_intri_res; \ | |
| 526 | − asm volatile ("ttag %0=%1" : "=r"(ia64_intri_res) : "r" (addr)); \ | |
| 527 | − ia64_intri_res; \ | |
| 528 | −}) | |
| 529 | − | |
| 530 | − | |
| 531 | −/* Values for lfhint in ia64_lfetch and ia64_lfetch_fault */ | |
| 532 | − | |
| 533 | −#define ia64_lfhint_none 0 | |
| 534 | −#define ia64_lfhint_nt1 1 | |
| 535 | −#define ia64_lfhint_nt2 2 | |
| 536 | −#define ia64_lfhint_nta 3 | |
| 537 | − | |
| 538 | −#define ia64_lfetch(lfhint, y) \ | |
| 539 | −({ \ | |
| 540 | − switch (lfhint) { \ | |
| 541 | − case ia64_lfhint_none: \ | |
| 542 | − asm volatile ("lfetch [%0]" : : "r"(y)); \ | |
| 543 | − break; \ | |
| 544 | − case ia64_lfhint_nt1: \ | |
| 545 | − asm volatile ("lfetch.nt1 [%0]" : : "r"(y)); \ | |
| 546 | − break; \ | |
| 547 | − case ia64_lfhint_nt2: \ | |
| 548 | − asm volatile ("lfetch.nt2 [%0]" : : "r"(y)); \ | |
| 549 | − break; \ | |
| 550 | − case ia64_lfhint_nta: \ | |
| 551 | − asm volatile ("lfetch.nta [%0]" : : "r"(y)); \ | |
| 552 | − break; \ | |
| 553 | − } \ | |
| 554 | −}) | |
| 555 | − | |
| 556 | −#define ia64_lfetch_excl(lfhint, y) \ | |
| 557 | −({ \ | |
| 558 | − switch (lfhint) { \ | |
| 559 | − case ia64_lfhint_none: \ | |
| 560 | − asm volatile ("lfetch.excl [%0]" :: "r"(y)); \ | |
| 561 | − break; \ | |
| 562 | − case ia64_lfhint_nt1: \ | |
| 563 | − asm volatile ("lfetch.excl.nt1 [%0]" :: "r"(y)); \ | |
| 564 | − break; \ | |
| 565 | − case ia64_lfhint_nt2: \ | |
| 566 | − asm volatile ("lfetch.excl.nt2 [%0]" :: "r"(y)); \ | |
| 567 | − break; \ | |
| 568 | − case ia64_lfhint_nta: \ | |
| 569 | − asm volatile ("lfetch.excl.nta [%0]" :: "r"(y)); \ | |
| 570 | − break; \ | |
| 571 | − } \ | |
| 572 | −}) | |
| 573 | − | |
| 574 | −#define ia64_lfetch_fault(lfhint, y) \ | |
| 575 | −({ \ | |
| 576 | − switch (lfhint) { \ | |
| 577 | − case ia64_lfhint_none: \ | |
| 578 | − asm volatile ("lfetch.fault [%0]" : : "r"(y)); \ | |
| 579 | − break; \ | |
| 580 | − case ia64_lfhint_nt1: \ | |
| 581 | − asm volatile ("lfetch.fault.nt1 [%0]" : : "r"(y)); \ | |
| 582 | − break; \ | |
| 583 | − case ia64_lfhint_nt2: \ | |
| 584 | − asm volatile ("lfetch.fault.nt2 [%0]" : : "r"(y)); \ | |
| 585 | − break; \ | |
| 586 | − case ia64_lfhint_nta: \ | |
| 587 | − asm volatile ("lfetch.fault.nta [%0]" : : "r"(y)); \ | |
| 588 | − break; \ | |
| 589 | − } \ | |
| 590 | −}) | |
| 591 | − | |
| 592 | −#define ia64_lfetch_fault_excl(lfhint, y) \ | |
| 593 | −({ \ | |
| 594 | − switch (lfhint) { \ | |
| 595 | − case ia64_lfhint_none: \ | |
| 596 | − asm volatile ("lfetch.fault.excl [%0]" :: "r"(y)); \ | |
| 597 | − break; \ | |
| 598 | − case ia64_lfhint_nt1: \ | |
| 599 | − asm volatile ("lfetch.fault.excl.nt1 [%0]" :: "r"(y)); \ | |
| 600 | − break; \ | |
| 601 | − case ia64_lfhint_nt2: \ | |
| 602 | − asm volatile ("lfetch.fault.excl.nt2 [%0]" :: "r"(y)); \ | |
| 603 | − break; \ | |
| 604 | − case ia64_lfhint_nta: \ | |
| 605 | − asm volatile ("lfetch.fault.excl.nta [%0]" :: "r"(y)); \ | |
| 606 | − break; \ | |
| 607 | − } \ | |
| 608 | −}) | |
| 609 | − | |
| 610 | −#define ia64_intrin_local_irq_restore(x) \ | |
| 611 | −do { \ | |
| 612 | − asm volatile (";; cmp.ne p6,p7=%0,r0;;" \ | |
| 613 | − "(p6) ssm psr.i;" \ | |
| 614 | − "(p7) rsm psr.i;;" \ | |
| 615 | − "(p6) srlz.d" \ | |
| 616 | − :: "r"((x)) : "p6", "p7", "memory"); \ | |
| 617 | −} while (0) | |
| 618 | − | |
| 619 | −#endif /* _UAPI_ASM_IA64_GCC_INTRIN_H */ | |
| @@ -1,101 +0,0 @@ | ||
| 1 | −/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ | |
| 2 | −/* | |
| 3 | − * Copyright (C) 2002,2003 Intel Corp. | |
| 4 | − * Jun Nakajima <jun.nakajima@intel.com> | |
| 5 | − * Suresh Siddha <suresh.b.siddha@intel.com> | |
| 6 | − */ | |
| 7 | − | |
| 8 | −#ifndef _ASM_IA64_IA64REGS_H | |
| 9 | −#define _ASM_IA64_IA64REGS_H | |
| 10 | − | |
| 11 | −/* | |
| 12 | − * Register Names for getreg() and setreg(). | |
| 13 | − * | |
| 14 | − * The "magic" numbers happen to match the values used by the Intel compiler's | |
| 15 | − * getreg()/setreg() intrinsics. | |
| 16 | − */ | |
| 17 | − | |
| 18 | −/* Special Registers */ | |
| 19 | − | |
| 20 | −#define _IA64_REG_IP 1016 /* getreg only */ | |
| 21 | −#define _IA64_REG_PSR 1019 | |
| 22 | −#define _IA64_REG_PSR_L 1019 | |
| 23 | − | |
| 24 | −/* General Integer Registers */ | |
| 25 | − | |
| 26 | −#define _IA64_REG_GP 1025 /* R1 */ | |
| 27 | −#define _IA64_REG_R8 1032 /* R8 */ | |
| 28 | −#define _IA64_REG_R9 1033 /* R9 */ | |
| 29 | −#define _IA64_REG_SP 1036 /* R12 */ | |
| 30 | −#define _IA64_REG_TP 1037 /* R13 */ | |
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This diff is large: its 156 lines aren’t shown here.
This diff is large: its 9 lines aren’t shown here.
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