Pull i2c fix from Wolfram Sang: "I2C has a revert to fix a regression" * 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: Revert "i2c: designware: detect when dynamic tar update is possible"
Unified · Split
| @@ -475,30 +475,28 @@ static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) · 474 unmodified lines | ||
| 475 | 475 | static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) |
| 476 | 476 | { |
| 477 | 477 | struct i2c_msg *msgs = dev->msgs; |
| 478 | − u32 ic_tar = 0; | |
| 478 | + u32 ic_con, ic_tar = 0; | |
| 479 | 479 | |
| 480 | 480 | /* Disable the adapter */ |
| 481 | 481 | __i2c_dw_enable_and_wait(dev, false); |
| 482 | 482 | |
| 483 | 483 | /* if the slave address is ten bit address, enable 10BITADDR */ |
| 484 | − if (dev->dynamic_tar_update_enabled) { | |
| 484 | + ic_con = dw_readl(dev, DW_IC_CON); | |
| 485 | + if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) { | |
| 486 | + ic_con |= DW_IC_CON_10BITADDR_MASTER; | |
| 485 | 487 | /* |
| 486 | 488 | * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing |
| 487 | − * mode has to be enabled via bit 12 of IC_TAR register, | |
| 488 | − * otherwise bit 4 of IC_CON is used. | |
| 489 | + * mode has to be enabled via bit 12 of IC_TAR register. | |
| 490 | + * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be | |
| 491 | + * detected from registers. | |
| 489 | 492 | */ |
| 490 | − if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) | |
| 491 | − ic_tar = DW_IC_TAR_10BITADDR_MASTER; | |
| 493 | + ic_tar = DW_IC_TAR_10BITADDR_MASTER; | |
| 492 | 494 | } else { |
| 493 | − u32 ic_con = dw_readl(dev, DW_IC_CON); | |
| 494 | − | |
| 495 | − if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) | |
| 496 | − ic_con |= DW_IC_CON_10BITADDR_MASTER; | |
| 497 | − else | |
| 498 | − ic_con &= ~DW_IC_CON_10BITADDR_MASTER; | |
| 499 | − dw_writel(dev, ic_con, DW_IC_CON); | |
| 495 | + ic_con &= ~DW_IC_CON_10BITADDR_MASTER; | |
| 500 | 496 | } |
| 501 | 497 | |
| 498 | + dw_writel(dev, ic_con, DW_IC_CON); | |
| 499 | + | |
| 502 | 500 | /* |
| 503 | 501 | * Set the slave (target) address and enable 10-bit addressing mode |
| 504 | 502 | * if applicable. |
| @@ -963,7 +961,6 @@ int i2c_dw_probe(struct dw_i2c_dev *dev) · 458 unmodified lines | ||
| 963 | 961 | { |
| 964 | 962 | struct i2c_adapter *adap = &dev->adapter; |
| 965 | 963 | int r; |
| 966 | − u32 reg; | |
| 967 | 964 | |
| 968 | 965 | init_completion(&dev->cmd_complete); |
| 969 | 966 | |
| @@ -971,26 +968,6 @@ int i2c_dw_probe(struct dw_i2c_dev *dev) · 1 unmodified line | ||
| 971 | 968 | if (r) |
| 972 | 969 | return r; |
| 973 | 970 | |
| 974 | − r = i2c_dw_acquire_lock(dev); | |
| 975 | − if (r) | |
| 976 | − return r; | |
| 977 | − | |
| 978 | − /* | |
| 979 | − * Test if dynamic TAR update is enabled in this controller by writing | |
| 980 | − * to IC_10BITADDR_MASTER field in IC_CON: when it is enabled this | |
| 981 | − * field is read-only so it should not succeed | |
| 982 | − */ | |
| 983 | − reg = dw_readl(dev, DW_IC_CON); | |
| 984 | − dw_writel(dev, reg ^ DW_IC_CON_10BITADDR_MASTER, DW_IC_CON); | |
| 985 | − | |
| 986 | − if ((dw_readl(dev, DW_IC_CON) & DW_IC_CON_10BITADDR_MASTER) == | |
| 987 | − (reg & DW_IC_CON_10BITADDR_MASTER)) { | |
| 988 | − dev->dynamic_tar_update_enabled = true; | |
| 989 | − dev_dbg(dev->dev, "Dynamic TAR update enabled"); | |
| 990 | − } | |
| 991 | − | |
| 992 | − i2c_dw_release_lock(dev); | |
| 993 | − | |
| 994 | 971 | snprintf(adap->name, sizeof(adap->name), |
| 995 | 972 | "Synopsys DesignWare I2C adapter"); |
| 996 | 973 | adap->retries = 3; |
| @@ -125,7 +125,6 @@ struct dw_i2c_dev { · 124 unmodified lines | ||
| 125 | 125 | int (*acquire_lock)(struct dw_i2c_dev *dev); |
| 126 | 126 | void (*release_lock)(struct dw_i2c_dev *dev); |
| 127 | 127 | bool pm_runtime_disabled; |
| 128 | − bool dynamic_tar_update_enabled; | |
| 129 | 128 | }; |
| 130 | 129 | |
| 131 | 130 | #define ACCESS_SWAP 0x00000001 |