Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s features as defined in PCIe spec r4.0, sec 7.7.4 for Data Link Feature and sec 7.7.5 for Physical Layer 16.0 GT/s.
Showing the changes to include/uapi/linux (1 of 1 file). Show all
Unified · Split
| @@ -713,7 +713,9 @@ · 712 unmodified lines | ||
| 713 | 713 | #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ |
| 714 | 714 | #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ |
| 715 | 715 | #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ |
| 716 | −#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM | |
| 716 | +#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ | |
| 717 | +#define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ | |
| 718 | +#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT | |
| 717 | 719 | |
| 718 | 720 | #define PCI_EXT_CAP_DSN_SIZEOF 12 |
| 719 | 721 | #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 |
| @@ -1053,4 +1055,14 @@ · 333 unmodified lines | ||
| 1053 | 1055 | #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ |
| 1054 | 1056 | #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ |
| 1055 | 1057 | |
| 1058 | +/* Data Link Feature */ | |
| 1059 | +#define PCI_DLF_CAP 0x04 /* Capabilities Register */ | |
| 1060 | +#define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */ | |
| 1061 | + | |
| 1062 | +/* Physical Layer 16.0 GT/s */ | |
| 1063 | +#define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ | |
| 1064 | +#define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK 0x0000000F | |
| 1065 | +#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0 | |
| 1066 | +#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4 | |
| 1067 | + | |
| 1056 | 1068 | #endif /* LINUX_PCI_REGS_H */ |