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Merge tag 'perf_urgent_for_v6.9_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 perf fixes from Borislav Petkov: - Define the correct set of default hw events on AMD Zen4 - Use the correct stalled cycles PMCs on AMD Zen2 and newer - Fix detection of the LBR freeze feature on AMD * tag 'perf_urgent_for_v6.9_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf/x86/amd/core: Define a proper ref-cycles event for Zen 4 and later perf/x86/amd/core: Update and fix stalled-cycles-* events for Zen 2 and later perf/x86/amd/lbr: Use freeze based on availability x86/cpufeatures: Add new word for scattered features

Linus Torvalds committed 2 years ago

Commit 448f8282 parents 8d338df 68cdf1e7 files · +62 −16Browse files

Unified · Split

7 files
  1. arch/x86/events/amd/core.c +34 −5
  2. arch/x86/events/amd/lbr.c +10 −6
  3. arch/x86/include/asm/cpufeature.h +4 −2
  4. arch/x86/include/asm/cpufeatures.h +9 −1
  5. arch/x86/include/asm/disabled-features.h +2 −1
  6. arch/x86/include/asm/required-features.h +2 −1
  7. arch/x86/kernel/cpu/scattered.c +1 −0
arch/x86/events/amd/core.c+34−5
@@ -250,7 +250,7 @@ static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] = · 249 unmodified lines
250250 /*
251251 * AMD Performance Monitor Family 17h and later:
252252 */
253−static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] =
253+static const u64 amd_zen1_perfmon_event_map[PERF_COUNT_HW_MAX] =
254254 {
255255 [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
256256 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
@@ -262,10 +262,39 @@ static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] = · 5 unmodified lines
262262 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x0187,
263263 };
264264
265+static const u64 amd_zen2_perfmon_event_map[PERF_COUNT_HW_MAX] =
266+{
267+ [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
268+ [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
269+ [PERF_COUNT_HW_CACHE_REFERENCES] = 0xff60,
270+ [PERF_COUNT_HW_CACHE_MISSES] = 0x0964,
271+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2,
272+ [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3,
273+ [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a9,
274+};
275+
276+static const u64 amd_zen4_perfmon_event_map[PERF_COUNT_HW_MAX] =
277+{
278+ [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
279+ [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
280+ [PERF_COUNT_HW_CACHE_REFERENCES] = 0xff60,
281+ [PERF_COUNT_HW_CACHE_MISSES] = 0x0964,
282+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2,
283+ [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3,
284+ [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a9,
285+ [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x100000120,
286+};
287+
265288 static u64 amd_pmu_event_map(int hw_event)
266289 {
267− if (boot_cpu_data.x86 >= 0x17)
268− return amd_f17h_perfmon_event_map[hw_event];
290+ if (cpu_feature_enabled(X86_FEATURE_ZEN4) || boot_cpu_data.x86 >= 0x1a)
291+ return amd_zen4_perfmon_event_map[hw_event];
292+
293+ if (cpu_feature_enabled(X86_FEATURE_ZEN2) || boot_cpu_data.x86 >= 0x19)
294+ return amd_zen2_perfmon_event_map[hw_event];
295+
296+ if (cpu_feature_enabled(X86_FEATURE_ZEN1))
297+ return amd_zen1_perfmon_event_map[hw_event];
269298
270299 return amd_perfmon_event_map[hw_event];
271300 }
@@ -904,8 +933,8 @@ static int amd_pmu_v2_handle_irq(struct pt_regs *regs) · 632 unmodified lines
904933 if (!status)
905934 goto done;
906935
907− /* Read branch records before unfreezing */
908− if (status & GLOBAL_STATUS_LBRS_FROZEN) {
936+ /* Read branch records */
937+ if (x86_pmu.lbr_nr) {
909938 amd_pmu_lbr_read();
910939 status &= ~GLOBAL_STATUS_LBRS_FROZEN;
911940 }
arch/x86/events/amd/lbr.c+10−6
@@ -402,10 +402,12 @@ void amd_pmu_lbr_enable_all(void) · 401 unmodified lines
402402 wrmsrl(MSR_AMD64_LBR_SELECT, lbr_select);
403403 }
404404
405− rdmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl);
406− rdmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg);
405+ if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) {
406+ rdmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl);
407+ wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
408+ }
407409
408− wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
410+ rdmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg);
409411 wrmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg | DBG_EXTN_CFG_LBRV2EN);
410412 }
411413
@@ -418,10 +420,12 @@ void amd_pmu_lbr_disable_all(void) · 6 unmodified lines
418420 return;
419421
420422 rdmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg);
421− rdmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl);
422−
423423 wrmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg & ~DBG_EXTN_CFG_LBRV2EN);
424− wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
424+
425+ if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) {
426+ rdmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl);
427+ wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
428+ }
425429 }
426430
427431 __init int amd_pmu_lbr_init(void)
arch/x86/include/asm/cpufeature.h+4−2
@@ -91,8 +91,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; · 90 unmodified lines
9191 CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) || \
9292 CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 19, feature_bit) || \
9393 CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 20, feature_bit) || \
94+ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 21, feature_bit) || \
9495 REQUIRED_MASK_CHECK || \
95− BUILD_BUG_ON_ZERO(NCAPINTS != 21))
96+ BUILD_BUG_ON_ZERO(NCAPINTS != 22))
9697
9798 #define DISABLED_MASK_BIT_SET(feature_bit) \
9899 ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 0, feature_bit) || \
@@ -116,8 +117,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; · 17 unmodified lines
116117 CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) || \
117118 CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 19, feature_bit) || \
118119 CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 20, feature_bit) || \
120+ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 21, feature_bit) || \
119121 DISABLED_MASK_CHECK || \
120− BUILD_BUG_ON_ZERO(NCAPINTS != 21))
122+ BUILD_BUG_ON_ZERO(NCAPINTS != 22))
121123
122124 #define cpu_has(c, bit) \
123125 (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
arch/x86/include/asm/cpufeatures.h+9−1
@@ -13,7 +13,7 @@ · 12 unmodified lines
1313 /*
1414 * Defines x86 CPU feature bits
1515 */
16−#define NCAPINTS 21 /* N 32-bit words worth of info */
16+#define NCAPINTS 22 /* N 32-bit words worth of info */
1717 #define NBUGINTS 2 /* N 32-bit bug flags */
1818
1919 /*
@@ -459,6 +459,14 @@ · 439 unmodified lines
459459 #define X86_FEATURE_IBPB_BRTYPE (20*32+28) /* "" MSR_PRED_CMD[IBPB] flushes all branch type predictions */
460460 #define X86_FEATURE_SRSO_NO (20*32+29) /* "" CPU is not affected by SRSO */
461461
462+/*
463+ * Extended auxiliary flags: Linux defined - for features scattered in various
464+ * CPUID levels like 0x80000022, etc.
465+ *
466+ * Reuse free bits when adding new feature flags!
467+ */
468+#define X86_FEATURE_AMD_LBR_PMC_FREEZE (21*32+ 0) /* AMD LBR and PMC Freeze */
469+
462470 /*
463471 * BUG word(s)
464472 */
arch/x86/include/asm/disabled-features.h+2−1
@@ -155,6 +155,7 @@ · 154 unmodified lines
155155 #define DISABLED_MASK18 (DISABLE_IBT)
156156 #define DISABLED_MASK19 (DISABLE_SEV_SNP)
157157 #define DISABLED_MASK20 0
158−#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 21)
158+#define DISABLED_MASK21 0
159+#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 22)
159160
160161 #endif /* _ASM_X86_DISABLED_FEATURES_H */
arch/x86/include/asm/required-features.h+2−1
@@ -99,6 +99,7 @@ · 98 unmodified lines
9999 #define REQUIRED_MASK18 0
100100 #define REQUIRED_MASK19 0
101101 #define REQUIRED_MASK20 0
102−#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 21)
102+#define REQUIRED_MASK21 0
103+#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 22)
103104
104105 #endif /* _ASM_X86_REQUIRED_FEATURES_H */
arch/x86/kernel/cpu/scattered.c+1−0
@@ -49,6 +49,7 @@ static const struct cpuid_bit cpuid_bits[] = { · 48 unmodified lines
4949 { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 },
5050 { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 },
5151 { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 },
52+ { X86_FEATURE_AMD_LBR_PMC_FREEZE, CPUID_EAX, 2, 0x80000022, 0 },
5253 { 0, 0, 0, 0, 0 }
5354 };
5455