Pull staging and IIO updates from Greg KH: "Here is the "big" staging and IIO driver update for 4.15-rc1. Lots and lots of little changes, almost all minor code cleanups as the Outreachy application process happened during this development cycle. Also happened was a lot of IIO driver activity, and the typec USB code moving out of staging to drivers/usb (same commits are in the USB tree on a persistent branch to not cause merge issues.) Overall, it's a wash, I think we added a few hundred more lines than removed, but really only a few thousand were modified at all. All of these have been in linux-next for a while. There might be a merge issue with Al's vfs tree in the pi433 driver (take his changes, they are always better), and the media tree with some of the odd atomisp cleanups (take the media tree's version)" * tag 'staging-4.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (507 commits) staging: lustre: add SPDX identifiers to all lustre files staging: greybus: Remove redundant license text staging: greybus: add SPDX identifiers to all greybus driver files staging: ccree: simplify ioread/iowrite staging: ccree: simplify registers access staging: ccree: simplify error handling logic staging: ccree: remove dead code staging: ccree: handle limiting of DMA masks staging: ccree: copy IV to DMAable memory staging: fbtft: remove redundant initialization of buf staging: sm750fb: Fix parameter mistake in poke32 staging: wilc1000: Fix bssid buffer offset in Txq staging: fbtft: fb_ssd1331: fix mirrored display staging: android: Fix checkpatch.pl error staging: greybus: loopback: convert loopback to use generic async operations staging: greybus: operation: add private data with get/set accessors staging: greybus: loopback: Fix iteration count on async path staging: greybus: loopback: Hold per-connection mutex across operations staging: greybus/loopback: use ktime_get() for time intervals staging: fsl-dpaa2/eth: Extra headroom in RX buffers ...
Unified · Split
| @@ -522,6 +522,7 @@ Description: · 521 unmodified lines | |||
| 522 | Specifies the output powerdown mode. | 522 | Specifies the output powerdown mode. |
| 523 | DAC output stage is disconnected from the amplifier and | 523 | DAC output stage is disconnected from the amplifier and |
| 524 | 1kohm_to_gnd: connected to ground via an 1kOhm resistor, | 524 | 1kohm_to_gnd: connected to ground via an 1kOhm resistor, |
| 525 | 2.5kohm_to_gnd: connected to ground via a 2.5kOhm resistor, | ||
| 525 | 6kohm_to_gnd: connected to ground via a 6kOhm resistor, | 526 | 6kohm_to_gnd: connected to ground via a 6kOhm resistor, |
| 526 | 20kohm_to_gnd: connected to ground via a 20kOhm resistor, | 527 | 20kohm_to_gnd: connected to ground via a 20kOhm resistor, |
| 527 | 90kohm_to_gnd: connected to ground via a 90kOhm resistor, | 528 | 90kohm_to_gnd: connected to ground via a 90kOhm resistor, |
| @@ -1242,9 +1243,9 @@ What: /sys/.../iio:deviceX/in_distance_raw · 714 unmodified lines | |||
| 1242 | KernelVersion: 4.0 | 1243 | KernelVersion: 4.0 |
| 1243 | Contact: linux-iio@vger.kernel.org | 1244 | Contact: linux-iio@vger.kernel.org |
| 1244 | Description: | 1245 | Description: |
| 1245 | This attribute is used to read the distance covered by the user | 1246 | This attribute is used to read the measured distance to an object |
| 1246 | since the last reboot while activated. Units after application | 1247 | or the distance covered by the user since the last reboot while |
| 1247 | of scale are meters. | 1248 | activated. Units after application of scale are meters. |
| 1248 | 1249 | ||
| 1249 | What: /sys/bus/iio/devices/iio:deviceX/store_eeprom | 1250 | What: /sys/bus/iio/devices/iio:deviceX/store_eeprom |
| 1250 | KernelVersion: 3.4.0 | 1251 | KernelVersion: 3.4.0 |
| @@ -16,3 +16,13 @@ Description: · 15 unmodified lines | |||
| 16 | the motion sensor is placed. For example, in a laptop a motion | 16 | the motion sensor is placed. For example, in a laptop a motion |
| 17 | sensor can be located on the base or on the lid. Current valid | 17 | sensor can be located on the base or on the lid. Current valid |
| 18 | values are 'base' and 'lid'. | 18 | values are 'base' and 'lid'. |
| 19 | |||
| 20 | What: /sys/bus/iio/devices/iio:deviceX/id | ||
| 21 | Date: Septembre 2017 | ||
| 22 | KernelVersion: 4.14 | ||
| 23 | Contact: linux-iio@vger.kernel.org | ||
| 24 | Description: | ||
| 25 | This attribute is exposed by the CrOS EC legacy accelerometer | ||
| 26 | driver and represents the sensor ID as exposed by the EC. This | ||
| 27 | ID is used by the Android sensor service hardware abstraction | ||
| 28 | layer (sensor HAL) through the Android container on ChromeOS. | ||
| @@ -29,15 +29,29 @@ Required properties: · 28 unmodified lines | |||
| 29 | "microchip,mcp3204" | 29 | "microchip,mcp3204" |
| 30 | "microchip,mcp3208" | 30 | "microchip,mcp3208" |
| 31 | "microchip,mcp3301" | 31 | "microchip,mcp3301" |
| 32 | "microchip,mcp3550-50" | ||
| 33 | "microchip,mcp3550-60" | ||
| 34 | "microchip,mcp3551" | ||
| 35 | "microchip,mcp3553" | ||
| 32 | 36 | ||
| 33 | NOTE: The use of the compatibles with no vendor prefix | 37 | NOTE: The use of the compatibles with no vendor prefix |
| 34 | is deprecated and only listed because old DT use them. | 38 | is deprecated and only listed because old DT use them. |
| 35 | 39 | ||
| 40 | - spi-cpha, spi-cpol (boolean): | ||
| 41 | Either SPI mode (0,0) or (1,1) must be used, so specify | ||
| 42 | none or both of spi-cpha, spi-cpol. The MCP3550/1/3 | ||
| 43 | is more efficient in mode (1,1) as only 3 instead of | ||
| 44 | 4 bytes need to be read from the ADC, but not all SPI | ||
| 45 | masters support it. | ||
| 46 | |||
| 47 | - vref-supply: Phandle to the external reference voltage supply. | ||
| 48 | |||
| 36 | Examples: | 49 | Examples: |
| 37 | spi_controller { | 50 | spi_controller { |
| 38 | mcp3x0x@0 { | 51 | mcp3x0x@0 { |
| 39 | compatible = "mcp3002"; | 52 | compatible = "mcp3002"; |
| 40 | reg = <0>; | 53 | reg = <0>; |
| 41 | spi-max-frequency = <1000000>; | 54 | spi-max-frequency = <1000000>; |
| 55 | vref-supply = <&vref_reg>; | ||
| 42 | }; | 56 | }; |
| 43 | }; | 57 | }; |
| @@ -12,6 +12,7 @@ for the Thermal Controller which holds a phandle to the AUXADC. · 11 unmodified lines | |||
| 12 | Required properties: | 12 | Required properties: |
| 13 | - compatible: Should be one of: | 13 | - compatible: Should be one of: |
| 14 | - "mediatek,mt2701-auxadc": For MT2701 family of SoCs | 14 | - "mediatek,mt2701-auxadc": For MT2701 family of SoCs |
| 15 | - "mediatek,mt2712-auxadc": For MT2712 family of SoCs | ||
| 15 | - "mediatek,mt7622-auxadc": For MT7622 family of SoCs | 16 | - "mediatek,mt7622-auxadc": For MT7622 family of SoCs |
| 16 | - "mediatek,mt8173-auxadc": For MT8173 family of SoCs | 17 | - "mediatek,mt8173-auxadc": For MT8173 family of SoCs |
| 17 | - reg: Address range of the AUXADC unit. | 18 | - reg: Address range of the AUXADC unit. |
| @@ -0,0 +1,20 @@ | |||
| 1 | Maxim Integrated DS4422/DS4424 7-bit Sink/Source Current DAC Device Driver | ||
| 2 | |||
| 3 | Datasheet publicly available at: | ||
| 4 | https://datasheets.maximintegrated.com/en/ds/DS4422-DS4424.pdf | ||
| 5 | |||
| 6 | Required properties: | ||
| 7 | - compatible: Should be one of | ||
| 8 | maxim,ds4422 | ||
| 9 | maxim,ds4424 | ||
| 10 | - reg: Should contain the DAC I2C address | ||
| 11 | |||
| 12 | Optional properties: | ||
| 13 | - vcc-supply: Power supply is optional. If not defined, driver will ignore it. | ||
| 14 | |||
| 15 | Example: | ||
| 16 | ds4224@10 { | ||
| 17 | compatible = "maxim,ds4424"; | ||
| 18 | reg = <0x10>; /* When A0, A1 pins are ground */ | ||
| 19 | vcc-supply = <&vcc_3v3>; | ||
| 20 | }; | ||
| @@ -0,0 +1,34 @@ | |||
| 1 | Texas Instruments 8/10/12-bit 2/4-channel DAC driver | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible: Must be one of: | ||
| 5 | "ti,dac082s085" | ||
| 6 | "ti,dac102s085" | ||
| 7 | "ti,dac122s085" | ||
| 8 | "ti,dac084s085" | ||
| 9 | "ti,dac104s085" | ||
| 10 | "ti,dac124s085" | ||
| 11 | - reg: Chip select number. | ||
| 12 | - spi-cpha, spi-cpol: SPI mode (0,1) or (1,0) must be used, so specify | ||
| 13 | either spi-cpha or spi-cpol (but not both). | ||
| 14 | - vref-supply: Phandle to the external reference voltage supply. | ||
| 15 | |||
| 16 | For other required and optional properties of SPI slave nodes please refer to | ||
| 17 | ../../spi/spi-bus.txt. | ||
| 18 | |||
| 19 | Example: | ||
| 20 | vref_2v5_reg: regulator-vref { | ||
| 21 | compatible = "regulator-fixed"; | ||
| 22 | regulator-name = "2v5"; | ||
| 23 | regulator-min-microvolt = <2500000>; | ||
| 24 | regulator-max-microvolt = <2500000>; | ||
| 25 | regulator-always-on; | ||
| 26 | }; | ||
| 27 | |||
| 28 | dac@0 { | ||
| 29 | compatible = "ti,dac082s085"; | ||
| 30 | reg = <0>; | ||
| 31 | spi-max-frequency = <40000000>; | ||
| 32 | spi-cpol; | ||
| 33 | vref-supply = <&vref_2v5_reg>; | ||
| 34 | }; | ||
| @@ -20,9 +20,9 @@ Optional properties: · 19 unmodified lines | |||
| 20 | 20 | ||
| 21 | Example: | 21 | Example: |
| 22 | 22 | ||
| 23 | max30100@057 { | 23 | max30100@57 { |
| 24 | compatible = "maxim,max30100"; | 24 | compatible = "maxim,max30100"; |
| 25 | reg = <57>; | 25 | reg = <0x57>; |
| 26 | maxim,led-current-microamp = <24000 50000>; | 26 | maxim,led-current-microamp = <24000 50000>; |
| 27 | interrupt-parent = <&gpio1>; | 27 | interrupt-parent = <&gpio1>; |
| 28 | interrupts = <16 2>; | 28 | interrupts = <16 2>; |
| @@ -20,7 +20,7 @@ Optional properties: · 19 unmodified lines | |||
| 20 | 20 | ||
| 21 | Example: | 21 | Example: |
| 22 | 22 | ||
| 23 | max30100@57 { | 23 | max30102@57 { |
| 24 | compatible = "maxim,max30102"; | 24 | compatible = "maxim,max30102"; |
| 25 | reg = <0x57>; | 25 | reg = <0x57>; |
| 26 | maxim,red-led-current-microamp = <7000>; | 26 | maxim,red-led-current-microamp = <7000>; |
| @@ -46,6 +46,8 @@ Accelerometers: · 45 unmodified lines | |||
| 46 | - st,h3lis331dl-accel | 46 | - st,h3lis331dl-accel |
| 47 | - st,lng2dm-accel | 47 | - st,lng2dm-accel |
| 48 | - st,lis3l02dq | 48 | - st,lis3l02dq |
| 49 | - st,lis2dw12 | ||
| 50 | - st,lis3dhh | ||
| 49 | 51 | ||
| 50 | Gyroscopes: | 52 | Gyroscopes: |
| 51 | - st,l3g4200d-gyro | 53 | - st,l3g4200d-gyro |
| @@ -71,3 +73,5 @@ Pressure sensors: · 19 unmodified lines | |||
| 71 | - st,lps25h-press | 73 | - st,lps25h-press |
| 72 | - st,lps331ap-press | 74 | - st,lps331ap-press |
| 73 | - st,lps22hb-press | 75 | - st,lps22hb-press |
| 76 | - st,lps33hw | ||
| 77 | - st,lps35hw | ||
| @@ -219,7 +219,8 @@ CONFIG_AD525X_DPOT_I2C=m · 218 unmodified lines | |||
| 219 | CONFIG_ICS932S401=m | 219 | CONFIG_ICS932S401=m |
| 220 | CONFIG_APDS9802ALS=m | 220 | CONFIG_APDS9802ALS=m |
| 221 | CONFIG_ISL29003=m | 221 | CONFIG_ISL29003=m |
| 222 | CONFIG_TI_DAC7512=m | 222 | CONFIG_IIO=m |
| 223 | CONFIG_AD5446=m | ||
| 223 | CONFIG_EEPROM_AT24=m | 224 | CONFIG_EEPROM_AT24=m |
| 224 | CONFIG_SENSORS_LIS3_SPI=m | 225 | CONFIG_SENSORS_LIS3_SPI=m |
| 225 | CONFIG_IDE=m | 226 | CONFIG_IDE=m |
| @@ -37,7 +37,8 @@ CONFIG_MTD_NAND_PXA3xx=y · 36 unmodified lines | |||
| 37 | CONFIG_MTD_UBI=y | 37 | CONFIG_MTD_UBI=y |
| 38 | CONFIG_BLK_DEV_LOOP=y | 38 | CONFIG_BLK_DEV_LOOP=y |
| 39 | CONFIG_ISL29003=y | 39 | CONFIG_ISL29003=y |
| 40 | CONFIG_TI_DAC7512=y | 40 | CONFIG_IIO=y |
| 41 | CONFIG_AD5446=y | ||
| 41 | CONFIG_SCSI=y | 42 | CONFIG_SCSI=y |
| 42 | CONFIG_BLK_DEV_SD=y | 43 | CONFIG_BLK_DEV_SD=y |
| 43 | CONFIG_CHR_DEV_SG=y | 44 | CONFIG_CHR_DEV_SG=y |
| @@ -148,6 +148,17 @@ config HID_SENSOR_ACCEL_3D · 147 unmodified lines | |||
| 148 | To compile this driver as a module, choose M here: the | 148 | To compile this driver as a module, choose M here: the |
| 149 | module will be called hid-sensor-accel-3d. | 149 | module will be called hid-sensor-accel-3d. |
| 150 | 150 | ||
| 151 | config IIO_CROS_EC_ACCEL_LEGACY | ||
| 152 | tristate "ChromeOS EC Legacy Accelerometer Sensor" | ||
| 153 | select IIO_BUFFER | ||
| 154 | select IIO_TRIGGERED_BUFFER | ||
| 155 | select CROS_EC_LPC_REGISTER_DEVICE | ||
| 156 | help | ||
| 157 | Say yes here to get support for accelerometers on Chromebook using | ||
| 158 | legacy EC firmware. | ||
| 159 | Sensor data is retrieved through IO memory. | ||
| 160 | Newer devices should use IIO_CROS_EC_SENSORS. | ||
| 161 | |||
| 151 | config IIO_ST_ACCEL_3AXIS | 162 | config IIO_ST_ACCEL_3AXIS |
| 152 | tristate "STMicroelectronics accelerometers 3-Axis Driver" | 163 | tristate "STMicroelectronics accelerometers 3-Axis Driver" |
| 153 | depends on (I2C || SPI_MASTER) && SYSFS | 164 | depends on (I2C || SPI_MASTER) && SYSFS |
| @@ -219,8 +230,8 @@ config KXCJK1013 · 65 unmodified lines | |||
| 219 | select IIO_TRIGGERED_BUFFER | 230 | select IIO_TRIGGERED_BUFFER |
| 220 | help | 231 | help |
| 221 | Say Y here if you want to build a driver for the Kionix KXCJK-1013 | 232 | Say Y here if you want to build a driver for the Kionix KXCJK-1013 |
| 222 | triaxial acceleration sensor. This driver also supports KXCJ9-1008 | 233 | triaxial acceleration sensor. This driver also supports KXCJ9-1008, |
| 223 | and KXTJ2-1009. | 234 | KXTJ2-1009 and KXTF9. |
| 224 | 235 | ||
| 225 | To compile this driver as a module, choose M here: the module will | 236 | To compile this driver as a module, choose M here: the module will |
| 226 | be called kxcjk-1013. | 237 | be called kxcjk-1013. |
| @@ -44,6 +44,8 @@ obj-$(CONFIG_SCA3000) += sca3000.o · 43 unmodified lines | |||
| 44 | obj-$(CONFIG_STK8312) += stk8312.o | 44 | obj-$(CONFIG_STK8312) += stk8312.o |
| 45 | obj-$(CONFIG_STK8BA50) += stk8ba50.o | 45 | obj-$(CONFIG_STK8BA50) += stk8ba50.o |
| 46 | 46 | ||
| 47 | obj-$(CONFIG_IIO_CROS_EC_ACCEL_LEGACY) += cros_ec_accel_legacy.o | ||
| 48 | |||
| 47 | obj-$(CONFIG_IIO_SSP_SENSORS_COMMONS) += ssp_accel_sensor.o | 49 | obj-$(CONFIG_IIO_SSP_SENSORS_COMMONS) += ssp_accel_sensor.o |
| 48 | 50 | ||
| 49 | obj-$(CONFIG_IIO_ST_ACCEL_3AXIS) += st_accel.o | 51 | obj-$(CONFIG_IIO_ST_ACCEL_3AXIS) += st_accel.o |
| @@ -95,7 +95,6 @@ static int adxl345_read_raw(struct iio_dev *indio_dev, · 94 unmodified lines | |||
| 95 | } | 95 | } |
| 96 | 96 | ||
| 97 | static const struct iio_info adxl345_info = { | 97 | static const struct iio_info adxl345_info = { |
| 98 | .driver_module = THIS_MODULE, | ||
| 99 | .read_raw = adxl345_read_raw, | 98 | .read_raw = adxl345_read_raw, |
| 100 | }; | 99 | }; |
| 101 | 100 | ||
| @@ -536,7 +536,6 @@ static const struct iio_info bma180_info = { · 535 unmodified lines | |||
| 536 | .attrs = &bma180_attrs_group, | 536 | .attrs = &bma180_attrs_group, |
| 537 | .read_raw = bma180_read_raw, | 537 | .read_raw = bma180_read_raw, |
| 538 | .write_raw = bma180_write_raw, | 538 | .write_raw = bma180_write_raw, |
| 539 | .driver_module = THIS_MODULE, | ||
| 540 | }; | 539 | }; |
| 541 | 540 | ||
| 542 | static const char * const bma180_power_modes[] = { "low_noise", "low_power" }; | 541 | static const char * const bma180_power_modes[] = { "low_noise", "low_power" }; |
| @@ -700,7 +699,6 @@ static int bma180_trig_try_reen(struct iio_trigger *trig) · 157 unmodified lines | |||
| 700 | static const struct iio_trigger_ops bma180_trigger_ops = { | 699 | static const struct iio_trigger_ops bma180_trigger_ops = { |
| 701 | .set_trigger_state = bma180_data_rdy_trigger_set_state, | 700 | .set_trigger_state = bma180_data_rdy_trigger_set_state, |
| 702 | .try_reenable = bma180_trig_try_reen, | 701 | .try_reenable = bma180_trig_try_reen, |
| 703 | .owner = THIS_MODULE, | ||
| 704 | }; | 702 | }; |
| 705 | 703 | ||
| 706 | static int bma180_probe(struct i2c_client *client, | 704 | static int bma180_probe(struct i2c_client *client, |
| @@ -186,7 +186,6 @@ static int bma220_write_raw(struct iio_dev *indio_dev, · 185 unmodified lines | |||
| 186 | } | 186 | } |
| 187 | 187 | ||
| 188 | static const struct iio_info bma220_info = { | 188 | static const struct iio_info bma220_info = { |
| 189 | .driver_module = THIS_MODULE, | ||
| 190 | .read_raw = bma220_read_raw, | 189 | .read_raw = bma220_read_raw, |
| 191 | .write_raw = bma220_write_raw, | 190 | .write_raw = bma220_write_raw, |
| 192 | .attrs = &bma220_attribute_group, | 191 | .attrs = &bma220_attribute_group, |
| @@ -1094,7 +1094,6 @@ static const struct iio_info bmc150_accel_info = { · 1093 unmodified lines | |||
| 1094 | .write_event_value = bmc150_accel_write_event, | 1094 | .write_event_value = bmc150_accel_write_event, |
| 1095 | .write_event_config = bmc150_accel_write_event_config, | 1095 | .write_event_config = bmc150_accel_write_event_config, |
| 1096 | .read_event_config = bmc150_accel_read_event_config, | 1096 | .read_event_config = bmc150_accel_read_event_config, |
| 1097 | .driver_module = THIS_MODULE, | ||
| 1098 | }; | 1097 | }; |
| 1099 | 1098 | ||
| 1100 | static const struct iio_info bmc150_accel_info_fifo = { | 1099 | static const struct iio_info bmc150_accel_info_fifo = { |
| @@ -1108,7 +1107,6 @@ static const struct iio_info bmc150_accel_info_fifo = { · 7 unmodified lines | |||
| 1108 | .validate_trigger = bmc150_accel_validate_trigger, | 1107 | .validate_trigger = bmc150_accel_validate_trigger, |
| 1109 | .hwfifo_set_watermark = bmc150_accel_set_watermark, | 1108 | .hwfifo_set_watermark = bmc150_accel_set_watermark, |
| 1110 | .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush, | 1109 | .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush, |
| 1111 | .driver_module = THIS_MODULE, | ||
| 1112 | }; | 1110 | }; |
| 1113 | 1111 | ||
| 1114 | static const unsigned long bmc150_accel_scan_masks[] = { | 1112 | static const unsigned long bmc150_accel_scan_masks[] = { |
| @@ -1200,7 +1198,6 @@ static int bmc150_accel_trigger_set_state(struct iio_trigger *trig, · 85 unmodified lines | |||
| 1200 | static const struct iio_trigger_ops bmc150_accel_trigger_ops = { | 1198 | static const struct iio_trigger_ops bmc150_accel_trigger_ops = { |
| 1201 | .set_trigger_state = bmc150_accel_trigger_set_state, | 1199 | .set_trigger_state = bmc150_accel_trigger_set_state, |
| 1202 | .try_reenable = bmc150_accel_trig_try_reen, | 1200 | .try_reenable = bmc150_accel_trig_try_reen, |
| 1203 | .owner = THIS_MODULE, | ||
| 1204 | }; | 1201 | }; |
| 1205 | 1202 | ||
| 1206 | static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev) | 1203 | static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev) |
| @@ -0,0 +1,423 @@ | |||
| 1 | /* | ||
| 2 | * Driver for older Chrome OS EC accelerometer | ||
| 3 | * | ||
| 4 | * Copyright 2017 Google, Inc | ||
| 5 | * | ||
| 6 | * This software is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2, as published by the Free Software Foundation, and | ||
| 8 | * may be copied, distributed, and modified under those terms. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * This driver uses the memory mapper cros-ec interface to communicate | ||
| 16 | * with the Chrome OS EC about accelerometer data. | ||
| 17 | * Accelerometer access is presented through iio sysfs. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #include <linux/delay.h> | ||
| 21 | #include <linux/device.h> | ||
| 22 | #include <linux/iio/buffer.h> | ||
| 23 | #include <linux/iio/iio.h> | ||
| 24 | #include <linux/iio/kfifo_buf.h> | ||
| 25 | #include <linux/iio/trigger_consumer.h> | ||
| 26 | #include <linux/iio/triggered_buffer.h> | ||
| 27 | #include <linux/kernel.h> | ||
| 28 | #include <linux/mfd/cros_ec.h> | ||
| 29 | #include <linux/mfd/cros_ec_commands.h> | ||
| 30 | #include <linux/module.h> | ||
| 31 | #include <linux/slab.h> | ||
| 32 | #include <linux/sysfs.h> | ||
| 33 | #include <linux/platform_device.h> | ||
| 34 | |||
| 35 | #define DRV_NAME "cros-ec-accel-legacy" | ||
| 36 | |||
| 37 | /* | ||
| 38 | * Sensor scale hard coded at 10 bits per g, computed as: | ||
| 39 | * g / (2^10 - 1) = 0.009586168; with g = 9.80665 m.s^-2 | ||
| 40 | */ | ||
| 41 | #define ACCEL_LEGACY_NSCALE 9586168 | ||
| 42 | |||
| 43 | /* Indices for EC sensor values. */ | ||
| 44 | enum { | ||
| 45 | X, | ||
| 46 | Y, | ||
| 47 | Z, | ||
| 48 | MAX_AXIS, | ||
| 49 | }; | ||
| 50 | |||
| 51 | /* State data for cros_ec_accel_legacy iio driver. */ | ||
| 52 | struct cros_ec_accel_legacy_state { | ||
| 53 | struct cros_ec_device *ec; | ||
| 54 | |||
| 55 | /* | ||
| 56 | * Array holding data from a single capture. 2 bytes per channel | ||
| 57 | * for the 3 channels plus the timestamp which is always last and | ||
| 58 | * 8-bytes aligned. | ||
| 59 | */ | ||
| 60 | s16 capture_data[8]; | ||
| 61 | s8 sign[MAX_AXIS]; | ||
| 62 | u8 sensor_num; | ||
| 63 | }; | ||
| 64 | |||
| 65 | static int ec_cmd_read_u8(struct cros_ec_device *ec, unsigned int offset, | ||
| 66 | u8 *dest) | ||
| 67 | { | ||
| 68 | return ec->cmd_readmem(ec, offset, 1, dest); | ||
| 69 | } | ||
| 70 | |||
| 71 | static int ec_cmd_read_u16(struct cros_ec_device *ec, unsigned int offset, | ||
| 72 | u16 *dest) | ||
| 73 | { | ||
| 74 | __le16 tmp; | ||
| 75 | int ret = ec->cmd_readmem(ec, offset, 2, &tmp); | ||
| 76 | |||
| 77 | *dest = le16_to_cpu(tmp); | ||
| 78 | |||
| 79 | return ret; | ||
| 80 | } | ||
| 81 | |||
| 82 | /** | ||
| 83 | * read_ec_until_not_busy() - Read from EC status byte until it reads not busy. | ||
| 84 | * @st: Pointer to state information for device. | ||
| 85 | * | ||
| 86 | * This function reads EC status until its busy bit gets cleared. It does not | ||
| 87 | * wait indefinitely and returns -EIO if the EC status is still busy after a | ||
| 88 | * few hundreds milliseconds. | ||
| 89 | * | ||
| 90 | * Return: 8-bit status if ok, -EIO on error | ||
| 91 | */ | ||
| 92 | static int read_ec_until_not_busy(struct cros_ec_accel_legacy_state *st) | ||
| 93 | { | ||
| 94 | struct cros_ec_device *ec = st->ec; | ||
| 95 | u8 status; | ||
| 96 | int attempts = 0; | ||
| 97 | |||
| 98 | ec_cmd_read_u8(ec, EC_MEMMAP_ACC_STATUS, &status); | ||
| 99 | while (status & EC_MEMMAP_ACC_STATUS_BUSY_BIT) { | ||
| 100 | /* Give up after enough attempts, return error. */ | ||
| 101 | if (attempts++ >= 50) | ||
| 102 | return -EIO; | ||
| 103 | |||
| 104 | /* Small delay every so often. */ | ||
| 105 | if (attempts % 5 == 0) | ||
| 106 | msleep(25); | ||
| 107 | |||
| 108 | ec_cmd_read_u8(ec, EC_MEMMAP_ACC_STATUS, &status); | ||
| 109 | } | ||
| 110 | |||
| 111 | return status; | ||
| 112 | } | ||
| 113 | |||
| 114 | /** | ||
| 115 | * read_ec_accel_data_unsafe() - Read acceleration data from EC shared memory. | ||
| 116 | * @st: Pointer to state information for device. | ||
| 117 | * @scan_mask: Bitmap of the sensor indices to scan. | ||
| 118 | * @data: Location to store data. | ||
| 119 | * | ||
| 120 | * This is the unsafe function for reading the EC data. It does not guarantee | ||
| 121 | * that the EC will not modify the data as it is being read in. | ||
| 122 | */ | ||
| 123 | static void read_ec_accel_data_unsafe(struct cros_ec_accel_legacy_state *st, | ||
| 124 | unsigned long scan_mask, s16 *data) | ||
| 125 | { | ||
| 126 | int i = 0; | ||
| 127 | int num_enabled = bitmap_weight(&scan_mask, MAX_AXIS); | ||
| 128 | |||
| 129 | /* Read all sensors enabled in scan_mask. Each value is 2 bytes. */ | ||
| 130 | while (num_enabled--) { | ||
| 131 | i = find_next_bit(&scan_mask, MAX_AXIS, i); | ||
| 132 | ec_cmd_read_u16(st->ec, | ||
| 133 | EC_MEMMAP_ACC_DATA + | ||
| 134 | sizeof(s16) * | ||
| 135 | (1 + i + st->sensor_num * MAX_AXIS), | ||
| 136 | data); | ||
| 137 | *data *= st->sign[i]; | ||
| 138 | i++; | ||
| 139 | data++; | ||
| 140 | } | ||
| 141 | } | ||
| 142 | |||
| 143 | /** | ||
| 144 | * read_ec_accel_data() - Read acceleration data from EC shared memory. | ||
| 145 | * @st: Pointer to state information for device. | ||
| 146 | * @scan_mask: Bitmap of the sensor indices to scan. | ||
| 147 | * @data: Location to store data. | ||
| 148 | * | ||
| 149 | * This is the safe function for reading the EC data. It guarantees that | ||
| 150 | * the data sampled was not modified by the EC while being read. | ||
| 151 | * | ||
| 152 | * Return: 0 if ok, -ve on error | ||
| 153 | */ | ||
| 154 | static int read_ec_accel_data(struct cros_ec_accel_legacy_state *st, | ||
| 155 | unsigned long scan_mask, s16 *data) | ||
| 156 | { | ||
| 157 | u8 samp_id = 0xff; | ||
| 158 | u8 status = 0; | ||
| 159 | int ret; | ||
| 160 | int attempts = 0; | ||
| 161 | |||
| 162 | /* | ||
| 163 | * Continually read all data from EC until the status byte after | ||
| 164 | * all reads reflects that the EC is not busy and the sample id | ||
| 165 | * matches the sample id from before all reads. This guarantees | ||
| 166 | * that data read in was not modified by the EC while reading. | ||
| 167 | */ | ||
| 168 | while ((status & (EC_MEMMAP_ACC_STATUS_BUSY_BIT | | ||
| 169 | EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK)) != samp_id) { | ||
| 170 | /* If we have tried to read too many times, return error. */ | ||
| 171 | if (attempts++ >= 5) | ||
| 172 | return -EIO; | ||
| 173 | |||
| 174 | /* Read status byte until EC is not busy. */ | ||
| 175 | ret = read_ec_until_not_busy(st); | ||
| 176 | if (ret < 0) | ||
| 177 | return ret; | ||
| 178 | status = ret; | ||
| 179 | |||
| 180 | /* | ||
| 181 | * Store the current sample id so that we can compare to the | ||
| 182 | * sample id after reading the data. | ||
| 183 | */ | ||
| 184 | samp_id = status & EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK; | ||
| 185 | |||
| 186 | /* Read all EC data, format it, and store it into data. */ | ||
| 187 | read_ec_accel_data_unsafe(st, scan_mask, data); | ||
| 188 | |||
| 189 | /* Read status byte. */ | ||
| 190 | ec_cmd_read_u8(st->ec, EC_MEMMAP_ACC_STATUS, &status); | ||
| 191 | } | ||
| 192 | |||
| 193 | return 0; | ||
| 194 | } | ||
| 195 | |||
| 196 | static int cros_ec_accel_legacy_read(struct iio_dev *indio_dev, | ||
| 197 | struct iio_chan_spec const *chan, | ||
| 198 | int *val, int *val2, long mask) | ||
| 199 | { | ||
| 200 | struct cros_ec_accel_legacy_state *st = iio_priv(indio_dev); | ||
| 201 | s16 data = 0; | ||
| 202 | int ret = IIO_VAL_INT; | ||
| 203 | |||
| 204 | switch (mask) { | ||
| 205 | case IIO_CHAN_INFO_RAW: | ||
| 206 | ret = read_ec_accel_data(st, (1 << chan->scan_index), &data); | ||
| 207 | if (ret) | ||
| 208 | return ret; | ||
| 209 | *val = data; | ||
| 210 | return IIO_VAL_INT; | ||
| 211 | case IIO_CHAN_INFO_SCALE: | ||
| 212 | *val = 0; | ||
| 213 | *val2 = ACCEL_LEGACY_NSCALE; | ||
| 214 | return IIO_VAL_INT_PLUS_NANO; | ||
| 215 | case IIO_CHAN_INFO_CALIBBIAS: | ||
| 216 | /* Calibration not supported. */ | ||
| 217 | *val = 0; | ||
| 218 | return IIO_VAL_INT; | ||
| 219 | default: | ||
| 220 | return -EINVAL; | ||
| 221 | } | ||
| 222 | } | ||
| 223 | |||
| 224 | static int cros_ec_accel_legacy_write(struct iio_dev *indio_dev, | ||
| 225 | struct iio_chan_spec const *chan, | ||
| 226 | int val, int val2, long mask) | ||
| 227 | { | ||
| 228 | /* | ||
| 229 | * Do nothing but don't return an error code to allow calibration | ||
| 230 | * script to work. | ||
| 231 | */ | ||
| 232 | if (mask == IIO_CHAN_INFO_CALIBBIAS) | ||
| 233 | return 0; | ||
| 234 | |||
| 235 | return -EINVAL; | ||
| 236 | } | ||
| 237 | |||
| 238 | static const struct iio_info cros_ec_accel_legacy_info = { | ||
| 239 | .read_raw = &cros_ec_accel_legacy_read, | ||
| 240 | .write_raw = &cros_ec_accel_legacy_write, | ||
| 241 | }; | ||
| 242 | |||
| 243 | /** | ||
| 244 | * cros_ec_accel_legacy_capture() - The trigger handler function | ||
| 245 | * @irq: The interrupt number. | ||
| 246 | * @p: Private data - always a pointer to the poll func. | ||
| 247 | * | ||
| 248 | * On a trigger event occurring, if the pollfunc is attached then this | ||
| 249 | * handler is called as a threaded interrupt (and hence may sleep). It | ||
| 250 | * is responsible for grabbing data from the device and pushing it into | ||
| 251 | * the associated buffer. | ||
| 252 | * | ||
| 253 | * Return: IRQ_HANDLED | ||
| 254 | */ | ||
| 255 | static irqreturn_t cros_ec_accel_legacy_capture(int irq, void *p) | ||
| 256 | { | ||
| 257 | struct iio_poll_func *pf = p; | ||
| 258 | struct iio_dev *indio_dev = pf->indio_dev; | ||
| 259 | struct cros_ec_accel_legacy_state *st = iio_priv(indio_dev); | ||
| 260 | |||
| 261 | /* Clear capture data. */ | ||
| 262 | memset(st->capture_data, 0, sizeof(st->capture_data)); | ||
| 263 | |||
| 264 | /* | ||
| 265 | * Read data based on which channels are enabled in scan mask. Note | ||
| 266 | * that on a capture we are always reading the calibrated data. | ||
| 267 | */ | ||
| 268 | read_ec_accel_data(st, *indio_dev->active_scan_mask, st->capture_data); | ||
| 269 | |||
| 270 | iio_push_to_buffers_with_timestamp(indio_dev, (void *)st->capture_data, | ||
| 271 | iio_get_time_ns(indio_dev)); | ||
| 272 | |||
| 273 | /* | ||
| 274 | * Tell the core we are done with this trigger and ready for the | ||
| 275 | * next one. | ||
| 276 | */ | ||
| 277 | iio_trigger_notify_done(indio_dev->trig); | ||
| 278 | |||
| 279 | return IRQ_HANDLED; | ||
| 280 | } | ||
| 281 | |||
| 282 | static char *cros_ec_accel_legacy_loc_strings[] = { | ||
| 283 | [MOTIONSENSE_LOC_BASE] = "base", | ||
| 284 | [MOTIONSENSE_LOC_LID] = "lid", | ||
| 285 | [MOTIONSENSE_LOC_MAX] = "unknown", | ||
| 286 | }; | ||
| 287 | |||
| 288 | static ssize_t cros_ec_accel_legacy_loc(struct iio_dev *indio_dev, | ||
| 289 | uintptr_t private, | ||
| 290 | const struct iio_chan_spec *chan, | ||
| 291 | char *buf) | ||
| 292 | { | ||
| 293 | struct cros_ec_accel_legacy_state *st = iio_priv(indio_dev); | ||
| 294 | |||
| 295 | return sprintf(buf, "%s\n", | ||
| 296 | cros_ec_accel_legacy_loc_strings[st->sensor_num + | ||
| 297 | MOTIONSENSE_LOC_BASE]); | ||
| 298 | } | ||
| 299 | |||
| 300 | static ssize_t cros_ec_accel_legacy_id(struct iio_dev *indio_dev, | ||
| 301 | uintptr_t private, | ||
| 302 | const struct iio_chan_spec *chan, | ||
| 303 | char *buf) | ||
| 304 | { | ||
| 305 | struct cros_ec_accel_legacy_state *st = iio_priv(indio_dev); | ||
| 306 | |||
| 307 | return sprintf(buf, "%d\n", st->sensor_num); | ||
| 308 | } | ||
| 309 | |||
| 310 | static const struct iio_chan_spec_ext_info cros_ec_accel_legacy_ext_info[] = { | ||
| 311 | { | ||
| 312 | .name = "id", | ||
| 313 | .shared = IIO_SHARED_BY_ALL, | ||
| 314 | .read = cros_ec_accel_legacy_id, | ||
| 315 | }, | ||
| 316 | { | ||
| 317 | .name = "location", | ||
| 318 | .shared = IIO_SHARED_BY_ALL, | ||
| 319 | .read = cros_ec_accel_legacy_loc, | ||
| 320 | }, | ||
| 321 | { } | ||
| 322 | }; | ||
| 323 | |||
| 324 | #define CROS_EC_ACCEL_LEGACY_CHAN(_axis) \ | ||
| 325 | { \ | ||
| 326 | .type = IIO_ACCEL, \ | ||
| 327 | .channel2 = IIO_MOD_X + (_axis), \ | ||
| 328 | .modified = 1, \ | ||
| 329 | .info_mask_separate = \ | ||
| 330 | BIT(IIO_CHAN_INFO_RAW) | \ | ||
| 331 | BIT(IIO_CHAN_INFO_SCALE) | \ | ||
| 332 | BIT(IIO_CHAN_INFO_CALIBBIAS), \ | ||
| 333 | .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE), \ | ||
| 334 | .ext_info = cros_ec_accel_legacy_ext_info, \ | ||
| 335 | .scan_type = { \ | ||
| 336 | .sign = 's', \ | ||
| 337 | .realbits = 16, \ | ||
| 338 | .storagebits = 16, \ | ||
| 339 | }, \ | ||
| 340 | } \ | ||
| 341 | |||
| 342 | static struct iio_chan_spec ec_accel_channels[] = { | ||
| 343 | CROS_EC_ACCEL_LEGACY_CHAN(X), | ||
| 344 | CROS_EC_ACCEL_LEGACY_CHAN(Y), | ||
| 345 | CROS_EC_ACCEL_LEGACY_CHAN(Z), | ||
| 346 | IIO_CHAN_SOFT_TIMESTAMP(MAX_AXIS) | ||
| 347 | }; | ||
| 348 | |||
| 349 | static int cros_ec_accel_legacy_probe(struct platform_device *pdev) | ||
| 350 | { | ||
| 351 | struct device *dev = &pdev->dev; | ||
| 352 | struct cros_ec_dev *ec = dev_get_drvdata(dev->parent); | ||
| 353 | struct cros_ec_sensor_platform *sensor_platform = dev_get_platdata(dev); | ||
| 354 | struct iio_dev *indio_dev; | ||
| 355 | struct cros_ec_accel_legacy_state *state; | ||
| 356 | int ret, i; | ||
| 357 | |||
| 358 | if (!ec || !ec->ec_dev) { | ||
| 359 | dev_warn(&pdev->dev, "No EC device found.\n"); | ||
| 360 | return -EINVAL; | ||
| 361 | } | ||
| 362 | |||
| 363 | if (!ec->ec_dev->cmd_readmem) { | ||
| 364 | dev_warn(&pdev->dev, "EC does not support direct reads.\n"); | ||
| 365 | return -EINVAL; | ||
| 366 | } | ||
| 367 | |||
| 368 | indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*state)); | ||
| 369 | if (!indio_dev) | ||
| 370 | return -ENOMEM; | ||
| 371 | |||
| 372 | platform_set_drvdata(pdev, indio_dev); | ||
| 373 | state = iio_priv(indio_dev); | ||
| 374 | state->ec = ec->ec_dev; | ||
| 375 | state->sensor_num = sensor_platform->sensor_num; | ||
| 376 | |||
| 377 | indio_dev->dev.parent = dev; | ||
| 378 | indio_dev->name = pdev->name; | ||
| 379 | indio_dev->channels = ec_accel_channels; | ||
| 380 | /* | ||
| 381 | * Present the channel using HTML5 standard: | ||
| 382 | * need to invert X and Y and invert some lid axis. | ||
| 383 | */ | ||
| 384 | for (i = X ; i < MAX_AXIS; i++) { | ||
| 385 | switch (i) { | ||
| 386 | case X: | ||
| 387 | ec_accel_channels[X].scan_index = Y; | ||
| 388 | case Y: | ||
| 389 | ec_accel_channels[Y].scan_index = X; | ||
| 390 | case Z: | ||
| 391 | ec_accel_channels[Z].scan_index = Z; | ||
| 392 | } | ||
| 393 | if (state->sensor_num == MOTIONSENSE_LOC_LID && i != Y) | ||
| 394 | state->sign[i] = -1; | ||
| 395 | else | ||
| 396 | state->sign[i] = 1; | ||
| 397 | } | ||
| 398 | indio_dev->num_channels = ARRAY_SIZE(ec_accel_channels); | ||
| 399 | indio_dev->dev.parent = &pdev->dev; | ||
| 400 | indio_dev->info = &cros_ec_accel_legacy_info; | ||
| 401 | indio_dev->modes = INDIO_DIRECT_MODE; | ||
| 402 | |||
| 403 | ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, | ||
| 404 | cros_ec_accel_legacy_capture, | ||
| 405 | NULL); | ||
| 406 | if (ret) | ||
| 407 | return ret; | ||
| 408 | |||
| 409 | return devm_iio_device_register(dev, indio_dev); | ||
| 410 | } | ||
| 411 | |||
| 412 | static struct platform_driver cros_ec_accel_platform_driver = { | ||
| 413 | .driver = { | ||
| 414 | .name = DRV_NAME, | ||
| 415 | }, | ||
| 416 | .probe = cros_ec_accel_legacy_probe, | ||
| 417 | }; | ||
| 418 | module_platform_driver(cros_ec_accel_platform_driver); | ||
| 419 | |||
| 420 | MODULE_DESCRIPTION("ChromeOS EC legacy accelerometer driver"); | ||
| 421 | MODULE_AUTHOR("Gwendal Grignou <gwendal@chromium.org>"); | ||
| 422 | MODULE_LICENSE("GPL"); | ||
| 423 | MODULE_ALIAS("platform:" DRV_NAME); | ||
| @@ -88,7 +88,6 @@ static int da280_read_raw(struct iio_dev *indio_dev, · 87 unmodified lines | |||
| 88 | } | 88 | } |
| 89 | 89 | ||
| 90 | static const struct iio_info da280_info = { | 90 | static const struct iio_info da280_info = { |
| 91 | .driver_module = THIS_MODULE, | ||
| 92 | .read_raw = da280_read_raw, | 91 | .read_raw = da280_read_raw, |
| 93 | }; | 92 | }; |
| 94 | 93 | ||
| @@ -212,7 +212,6 @@ static int da311_read_raw(struct iio_dev *indio_dev, · 211 unmodified lines | |||
| 212 | } | 212 | } |
| 213 | 213 | ||
| 214 | static const struct iio_info da311_info = { | 214 | static const struct iio_info da311_info = { |
| 215 | .driver_module = THIS_MODULE, | ||
| 216 | .read_raw = da311_read_raw, | 215 | .read_raw = da311_read_raw, |
| 217 | }; | 216 | }; |
| 218 | 217 | ||
| @@ -124,7 +124,6 @@ static int dmard06_read_raw(struct iio_dev *indio_dev, · 123 unmodified lines | |||
| 124 | } | 124 | } |
| 125 | 125 | ||
| 126 | static const struct iio_info dmard06_info = { | 126 | static const struct iio_info dmard06_info = { |
| 127 | .driver_module = THIS_MODULE, | ||
| 128 | .read_raw = dmard06_read_raw, | 127 | .read_raw = dmard06_read_raw, |
| 129 | }; | 128 | }; |
| 130 | 129 | ||
| @@ -93,7 +93,6 @@ static int dmard09_read_raw(struct iio_dev *indio_dev, · 92 unmodified lines | |||
| 93 | } | 93 | } |
| 94 | 94 | ||
| 95 | static const struct iio_info dmard09_info = { | 95 | static const struct iio_info dmard09_info = { |
| 96 | .driver_module = THIS_MODULE, | ||
| 97 | .read_raw = dmard09_read_raw, | 96 | .read_raw = dmard09_read_raw, |
| 98 | }; | 97 | }; |
| 99 | 98 | ||
| @@ -170,7 +170,6 @@ static int dmard10_read_raw(struct iio_dev *indio_dev, · 169 unmodified lines | |||
| 170 | } | 170 | } |
| 171 | 171 | ||
| 172 | static const struct iio_info dmard10_info = { | 172 | static const struct iio_info dmard10_info = { |
| 173 | .driver_module = THIS_MODULE, | ||
| 174 | .read_raw = dmard10_read_raw, | 173 | .read_raw = dmard10_read_raw, |
| 175 | }; | 174 | }; |
| 176 | 175 | ||
| @@ -225,7 +225,6 @@ static int accel_3d_write_raw(struct iio_dev *indio_dev, · 224 unmodified lines | |||
| 225 | } | 225 | } |
| 226 | 226 | ||
| 227 | static const struct iio_info accel_3d_info = { | 227 | static const struct iio_info accel_3d_info = { |
| 228 | .driver_module = THIS_MODULE, | ||
| 229 | .read_raw = &accel_3d_read_raw, | 228 | .read_raw = &accel_3d_read_raw, |
| 230 | .write_raw = &accel_3d_write_raw, | 229 | .write_raw = &accel_3d_write_raw, |
| 231 | }; | 230 | }; |
| @@ -34,6 +34,13 @@ · 33 unmodified lines | |||
| 34 | #define KXCJK1013_DRV_NAME "kxcjk1013" | 34 | #define KXCJK1013_DRV_NAME "kxcjk1013" |
| 35 | #define KXCJK1013_IRQ_NAME "kxcjk1013_event" | 35 | #define KXCJK1013_IRQ_NAME "kxcjk1013_event" |
| 36 | 36 | ||
| 37 | #define KXTF9_REG_HP_XOUT_L 0x00 | ||
| 38 | #define KXTF9_REG_HP_XOUT_H 0x01 | ||
| 39 | #define KXTF9_REG_HP_YOUT_L 0x02 | ||
| 40 | #define KXTF9_REG_HP_YOUT_H 0x03 | ||
| 41 | #define KXTF9_REG_HP_ZOUT_L 0x04 | ||
| 42 | #define KXTF9_REG_HP_ZOUT_H 0x05 | ||
| 43 | |||
| 37 | #define KXCJK1013_REG_XOUT_L 0x06 | 44 | #define KXCJK1013_REG_XOUT_L 0x06 |
| 38 | /* | 45 | /* |
| 39 | * From low byte X axis register, all the other addresses of Y and Z can be | 46 | * From low byte X axis register, all the other addresses of Y and Z can be |
| @@ -48,17 +55,33 @@ · 8 unmodified lines | |||
| 48 | 55 | ||
| 49 | #define KXCJK1013_REG_DCST_RESP 0x0C | 56 | #define KXCJK1013_REG_DCST_RESP 0x0C |
| 50 | #define KXCJK1013_REG_WHO_AM_I 0x0F | 57 | #define KXCJK1013_REG_WHO_AM_I 0x0F |
| 51 | #define KXCJK1013_REG_INT_SRC1 0x16 | 58 | #define KXTF9_REG_TILT_POS_CUR 0x10 |
| 59 | #define KXTF9_REG_TILT_POS_PREV 0x11 | ||
| 60 | #define KXTF9_REG_INT_SRC1 0x15 | ||
| 61 | #define KXCJK1013_REG_INT_SRC1 0x16 /* compatible, but called INT_SRC2 in KXTF9 ds */ | ||
| 52 | #define KXCJK1013_REG_INT_SRC2 0x17 | 62 | #define KXCJK1013_REG_INT_SRC2 0x17 |
| 53 | #define KXCJK1013_REG_STATUS_REG 0x18 | 63 | #define KXCJK1013_REG_STATUS_REG 0x18 |
| 54 | #define KXCJK1013_REG_INT_REL 0x1A | 64 | #define KXCJK1013_REG_INT_REL 0x1A |
| 55 | #define KXCJK1013_REG_CTRL1 0x1B | 65 | #define KXCJK1013_REG_CTRL1 0x1B |
| 56 | #define KXCJK1013_REG_CTRL2 0x1D | 66 | #define KXTF9_REG_CTRL2 0x1C |
| 67 | #define KXCJK1013_REG_CTRL2 0x1D /* mostly compatible, CTRL_REG3 in KTXF9 ds */ | ||
| 57 | #define KXCJK1013_REG_INT_CTRL1 0x1E | 68 | #define KXCJK1013_REG_INT_CTRL1 0x1E |
| 58 | #define KXCJK1013_REG_INT_CTRL2 0x1F | 69 | #define KXCJK1013_REG_INT_CTRL2 0x1F |
| 70 | #define KXTF9_REG_INT_CTRL3 0x20 | ||
| 59 | #define KXCJK1013_REG_DATA_CTRL 0x21 | 71 | #define KXCJK1013_REG_DATA_CTRL 0x21 |
| 72 | #define KXTF9_REG_TILT_TIMER 0x28 | ||
| 60 | #define KXCJK1013_REG_WAKE_TIMER 0x29 | 73 | #define KXCJK1013_REG_WAKE_TIMER 0x29 |
| 74 | #define KXTF9_REG_TDT_TIMER 0x2B | ||
| 75 | #define KXTF9_REG_TDT_THRESH_H 0x2C | ||
| 76 | #define KXTF9_REG_TDT_THRESH_L 0x2D | ||
| 77 | #define KXTF9_REG_TDT_TAP_TIMER 0x2E | ||
| 78 | #define KXTF9_REG_TDT_TOTAL_TIMER 0x2F | ||
| 79 | #define KXTF9_REG_TDT_LATENCY_TIMER 0x30 | ||
| 80 | #define KXTF9_REG_TDT_WINDOW_TIMER 0x31 | ||
| 61 | #define KXCJK1013_REG_SELF_TEST 0x3A | 81 | #define KXCJK1013_REG_SELF_TEST 0x3A |
| 82 | #define KXTF9_REG_WAKE_THRESH 0x5A | ||
| 83 | #define KXTF9_REG_TILT_ANGLE 0x5C | ||
| 84 | #define KXTF9_REG_HYST_SET 0x5F | ||
| 62 | #define KXCJK1013_REG_WAKE_THRES 0x6A | 85 | #define KXCJK1013_REG_WAKE_THRES 0x6A |
| 63 | 86 | ||
| 64 | #define KXCJK1013_REG_CTRL1_BIT_PC1 BIT(7) | 87 | #define KXCJK1013_REG_CTRL1_BIT_PC1 BIT(7) |
| @@ -67,14 +90,33 @@ · 2 unmodified lines | |||
| 67 | #define KXCJK1013_REG_CTRL1_BIT_GSEL1 BIT(4) | 90 | #define KXCJK1013_REG_CTRL1_BIT_GSEL1 BIT(4) |
| 68 | #define KXCJK1013_REG_CTRL1_BIT_GSEL0 BIT(3) | 91 | #define KXCJK1013_REG_CTRL1_BIT_GSEL0 BIT(3) |
| 69 | #define KXCJK1013_REG_CTRL1_BIT_WUFE BIT(1) | 92 | #define KXCJK1013_REG_CTRL1_BIT_WUFE BIT(1) |
| 70 | #define KXCJK1013_REG_INT_REG1_BIT_IEA BIT(4) | 93 | |
| 71 | #define KXCJK1013_REG_INT_REG1_BIT_IEN BIT(5) | 94 | #define KXCJK1013_REG_INT_CTRL1_BIT_IEU BIT(2) /* KXTF9 */ |
| 95 | #define KXCJK1013_REG_INT_CTRL1_BIT_IEL BIT(3) | ||
| 96 | #define KXCJK1013_REG_INT_CTRL1_BIT_IEA BIT(4) | ||
| 97 | #define KXCJK1013_REG_INT_CTRL1_BIT_IEN BIT(5) | ||
| 98 | |||
| 99 | #define KXTF9_REG_TILT_BIT_LEFT_EDGE BIT(5) | ||
| 100 | #define KXTF9_REG_TILT_BIT_RIGHT_EDGE BIT(4) | ||
| 101 | #define KXTF9_REG_TILT_BIT_LOWER_EDGE BIT(3) | ||
| 102 | #define KXTF9_REG_TILT_BIT_UPPER_EDGE BIT(2) | ||
| 103 | #define KXTF9_REG_TILT_BIT_FACE_DOWN BIT(1) | ||
| 104 | #define KXTF9_REG_TILT_BIT_FACE_UP BIT(0) | ||
| 72 | 105 | ||
| 73 | #define KXCJK1013_DATA_MASK_12_BIT 0x0FFF | 106 | #define KXCJK1013_DATA_MASK_12_BIT 0x0FFF |
| 74 | #define KXCJK1013_MAX_STARTUP_TIME_US 100000 | 107 | #define KXCJK1013_MAX_STARTUP_TIME_US 100000 |
| 75 | 108 | ||
| 76 | #define KXCJK1013_SLEEP_DELAY_MS 2000 | 109 | #define KXCJK1013_SLEEP_DELAY_MS 2000 |
| 77 | 110 | ||
| 111 | #define KXCJK1013_REG_INT_SRC1_BIT_TPS BIT(0) /* KXTF9 */ | ||
| 112 | #define KXCJK1013_REG_INT_SRC1_BIT_WUFS BIT(1) | ||
| 113 | #define KXCJK1013_REG_INT_SRC1_MASK_TDTS (BIT(2) | BIT(3)) /* KXTF9 */ | ||
| 114 | #define KXCJK1013_REG_INT_SRC1_TAP_NONE 0 | ||
| 115 | #define KXCJK1013_REG_INT_SRC1_TAP_SINGLE BIT(2) | ||
| 116 | #define KXCJK1013_REG_INT_SRC1_TAP_DOUBLE BIT(3) | ||
| 117 | #define KXCJK1013_REG_INT_SRC1_BIT_DRDY BIT(4) | ||
| 118 | |||
| 119 | /* KXCJK: INT_SOURCE2: motion detect, KXTF9: INT_SRC_REG1: tap detect */ | ||
| 78 | #define KXCJK1013_REG_INT_SRC2_BIT_ZP BIT(0) | 120 | #define KXCJK1013_REG_INT_SRC2_BIT_ZP BIT(0) |
| 79 | #define KXCJK1013_REG_INT_SRC2_BIT_ZN BIT(1) | 121 | #define KXCJK1013_REG_INT_SRC2_BIT_ZN BIT(1) |
| 80 | #define KXCJK1013_REG_INT_SRC2_BIT_YP BIT(2) | 122 | #define KXCJK1013_REG_INT_SRC2_BIT_YP BIT(2) |
| @@ -88,6 +130,7 @@ enum kx_chipset { · 7 unmodified lines | |||
| 88 | KXCJK1013, | 130 | KXCJK1013, |
| 89 | KXCJ91008, | 131 | KXCJ91008, |
| 90 | KXTJ21009, | 132 | KXTJ21009, |
| 133 | KXTF9, | ||
| 91 | KX_MAX_CHIPS /* this must be last */ | 134 | KX_MAX_CHIPS /* this must be last */ |
| 92 | }; | 135 | }; |
| 93 | 136 | ||
| @@ -128,15 +171,42 @@ enum kxcjk1013_range { · 34 unmodified lines | |||
| 128 | KXCJK1013_RANGE_8G, | 171 | KXCJK1013_RANGE_8G, |
| 129 | }; | 172 | }; |
| 130 | 173 | ||
| 131 | static const struct { | 174 | struct kx_odr_map { |
| 132 | int val; | 175 | int val; |
| 133 | int val2; | 176 | int val2; |
| 134 | int odr_bits; | 177 | int odr_bits; |
| 135 | } samp_freq_table[] = { {0, 781000, 0x08}, {1, 563000, 0x09}, | 178 | int wuf_bits; |
| 136 | {3, 125000, 0x0A}, {6, 250000, 0x0B}, {12, 500000, 0}, | 179 | }; |
| 137 | {25, 0, 0x01}, {50, 0, 0x02}, {100, 0, 0x03}, | 180 | |
| 138 | {200, 0, 0x04}, {400, 0, 0x05}, {800, 0, 0x06}, | 181 | static const struct kx_odr_map samp_freq_table[] = { |
| 139 | {1600, 0, 0x07} }; | 182 | { 0, 781000, 0x08, 0x00 }, |
| 183 | { 1, 563000, 0x09, 0x01 }, | ||
| 184 | { 3, 125000, 0x0A, 0x02 }, | ||
| 185 | { 6, 250000, 0x0B, 0x03 }, | ||
| 186 | { 12, 500000, 0x00, 0x04 }, | ||
| 187 | { 25, 0, 0x01, 0x05 }, | ||
| 188 | { 50, 0, 0x02, 0x06 }, | ||
| 189 | { 100, 0, 0x03, 0x06 }, | ||
| 190 | { 200, 0, 0x04, 0x06 }, | ||
| 191 | { 400, 0, 0x05, 0x06 }, | ||
| 192 | { 800, 0, 0x06, 0x06 }, | ||
| 193 | { 1600, 0, 0x07, 0x06 }, | ||
| 194 | }; | ||
| 195 | |||
| 196 | static const char *const kxcjk1013_samp_freq_avail = | ||
| 197 | "0.781000 1.563000 3.125000 6.250000 12.500000 25 50 100 200 400 800 1600"; | ||
| 198 | |||
| 199 | static const struct kx_odr_map kxtf9_samp_freq_table[] = { | ||
| 200 | { 25, 0, 0x01, 0x00 }, | ||
| 201 | { 50, 0, 0x02, 0x01 }, | ||
| 202 | { 100, 0, 0x03, 0x01 }, | ||
| 203 | { 200, 0, 0x04, 0x01 }, | ||
| 204 | { 400, 0, 0x05, 0x01 }, | ||
| 205 | { 800, 0, 0x06, 0x01 }, | ||
| 206 | }; | ||
| 207 | |||
| 208 | static const char *const kxtf9_samp_freq_avail = | ||
| 209 | "25 50 100 200 400 800"; | ||
| 140 | 210 | ||
| 141 | /* Refer to section 4 of the specification */ | 211 | /* Refer to section 4 of the specification */ |
| 142 | static const struct { | 212 | static const struct { |
| @@ -188,6 +258,15 @@ static const struct { · 45 unmodified lines | |||
| 188 | {0x06, 3000}, | 258 | {0x06, 3000}, |
| 189 | {0x07, 2000}, | 259 | {0x07, 2000}, |
| 190 | }, | 260 | }, |
| 261 | /* KXTF9 */ | ||
| 262 | { | ||
| 263 | {0x01, 81000}, | ||
| 264 | {0x02, 41000}, | ||
| 265 | {0x03, 21000}, | ||
| 266 | {0x04, 11000}, | ||
| 267 | {0x05, 5100}, | ||
| 268 | {0x06, 2700}, | ||
| 269 | }, | ||
| 191 | }; | 270 | }; |
| 192 | 271 | ||
| 193 | static const struct { | 272 | static const struct { |
| @@ -198,23 +277,6 @@ static const struct { · 4 unmodified lines | |||
| 198 | {19163, 1, 0}, | 277 | {19163, 1, 0}, |
| 199 | {38326, 0, 1} }; | 278 | {38326, 0, 1} }; |
| 200 | 279 | ||
| 201 | static const struct { | ||
| 202 | int val; | ||
| 203 | int val2; | ||
| 204 | int odr_bits; | ||
| 205 | } wake_odr_data_rate_table[] = { {0, 781000, 0x00}, | ||
| 206 | {1, 563000, 0x01}, | ||
| 207 | {3, 125000, 0x02}, | ||
| 208 | {6, 250000, 0x03}, | ||
| 209 | {12, 500000, 0x04}, | ||
| 210 | {25, 0, 0x05}, | ||
| 211 | {50, 0, 0x06}, | ||
| 212 | {100, 0, 0x06}, | ||
| 213 | {200, 0, 0x06}, | ||
| 214 | {400, 0, 0x06}, | ||
| 215 | {800, 0, 0x06}, | ||
| 216 | {1600, 0, 0x06} }; | ||
| 217 | |||
| 218 | static int kxcjk1013_set_mode(struct kxcjk1013_data *data, | 280 | static int kxcjk1013_set_mode(struct kxcjk1013_data *data, |
| 219 | enum kxcjk1013_mode mode) | 281 | enum kxcjk1013_mode mode) |
| 220 | { | 282 | { |
| @@ -341,9 +403,9 @@ static int kxcjk1013_chip_init(struct kxcjk1013_data *data) · 120 unmodified lines | |||
| 341 | } | 403 | } |
| 342 | 404 | ||
| 343 | if (data->active_high_intr) | 405 | if (data->active_high_intr) |
| 344 | ret |= KXCJK1013_REG_INT_REG1_BIT_IEA; | 406 | ret |= KXCJK1013_REG_INT_CTRL1_BIT_IEA; |
| 345 | else | 407 | else |
| 346 | ret &= ~KXCJK1013_REG_INT_REG1_BIT_IEA; | 408 | ret &= ~KXCJK1013_REG_INT_CTRL1_BIT_IEA; |
| 347 | 409 | ||
| 348 | ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1, | 410 | ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1, |
| 349 | ret); | 411 | ret); |
| @@ -401,7 +463,7 @@ static int kxcjk1013_set_power_state(struct kxcjk1013_data *data, bool on) · 51 unmodified lines | |||
| 401 | 463 | ||
| 402 | static int kxcjk1013_chip_update_thresholds(struct kxcjk1013_data *data) | 464 | static int kxcjk1013_chip_update_thresholds(struct kxcjk1013_data *data) |
| 403 | { | 465 | { |
| 404 | int ret; | 466 | int waketh_reg, ret; |
| 405 | 467 | ||
| 406 | ret = i2c_smbus_write_byte_data(data->client, | 468 | ret = i2c_smbus_write_byte_data(data->client, |
| 407 | KXCJK1013_REG_WAKE_TIMER, | 469 | KXCJK1013_REG_WAKE_TIMER, |
| @@ -412,8 +474,9 @@ static int kxcjk1013_chip_update_thresholds(struct kxcjk1013_data *data) · 4 unmodified lines | |||
| 412 | return ret; | 474 | return ret; |
| 413 | } | 475 | } |
| 414 | 476 | ||
| 415 | ret = i2c_smbus_write_byte_data(data->client, | 477 | waketh_reg = data->chipset == KXTF9 ? |
| 416 | KXCJK1013_REG_WAKE_THRES, | 478 | KXTF9_REG_WAKE_THRESH : KXCJK1013_REG_WAKE_THRES; |
| 479 | ret = i2c_smbus_write_byte_data(data->client, waketh_reg, | ||
| 417 | data->wake_thres); | 480 | data->wake_thres); |
| 418 | if (ret < 0) { | 481 | if (ret < 0) { |
| 419 | dev_err(&data->client->dev, "Error writing reg_wake_thres\n"); | 482 | dev_err(&data->client->dev, "Error writing reg_wake_thres\n"); |
| @@ -449,9 +512,9 @@ static int kxcjk1013_setup_any_motion_interrupt(struct kxcjk1013_data *data, · 29 unmodified lines | |||
| 449 | } | 512 | } |
| 450 | 513 | ||
| 451 | if (status) | 514 | if (status) |
| 452 | ret |= KXCJK1013_REG_INT_REG1_BIT_IEN; | 515 | ret |= KXCJK1013_REG_INT_CTRL1_BIT_IEN; |
| 453 | else | 516 | else |
| 454 | ret &= ~KXCJK1013_REG_INT_REG1_BIT_IEN; | 517 | ret &= ~KXCJK1013_REG_INT_CTRL1_BIT_IEN; |
| 455 | 518 | ||
| 456 | ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1, | 519 | ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1, |
| 457 | ret); | 520 | ret); |
| @@ -509,9 +572,9 @@ static int kxcjk1013_setup_new_data_interrupt(struct kxcjk1013_data *data, · 51 unmodified lines | |||
| 509 | } | 572 | } |
| 510 | 573 | ||
| 511 | if (status) | 574 | if (status) |
| 512 | ret |= KXCJK1013_REG_INT_REG1_BIT_IEN; | 575 | ret |= KXCJK1013_REG_INT_CTRL1_BIT_IEN; |
| 513 | else | 576 | else |
| 514 | ret &= ~KXCJK1013_REG_INT_REG1_BIT_IEN; | 577 | ret &= ~KXCJK1013_REG_INT_CTRL1_BIT_IEN; |
| 515 | 578 | ||
| 516 | ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1, | 579 | ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1, |
| 517 | ret); | 580 | ret); |
| @@ -547,28 +610,30 @@ static int kxcjk1013_setup_new_data_interrupt(struct kxcjk1013_data *data, · 29 unmodified lines | |||
| 547 | return 0; | 610 | return 0; |
| 548 | } | 611 | } |
| 549 | 612 | ||
| 550 | static int kxcjk1013_convert_freq_to_bit(int val, int val2) | 613 | static const struct kx_odr_map *kxcjk1013_find_odr_value( |
| 614 | const struct kx_odr_map *map, size_t map_size, int val, int val2) | ||
| 551 | { | 615 | { |
| 552 | int i; | 616 | int i; |
| 553 | 617 | ||
| 554 | for (i = 0; i < ARRAY_SIZE(samp_freq_table); ++i) { | 618 | for (i = 0; i < map_size; ++i) { |
| 555 | if (samp_freq_table[i].val == val && | 619 | if (map[i].val == val && map[i].val2 == val2) |
| 556 | samp_freq_table[i].val2 == val2) { | 620 | return &map[i]; |
| 557 | return samp_freq_table[i].odr_bits; | ||
| 558 | } | ||
| 559 | } | 621 | } |
| 560 | 622 | ||
| 561 | return -EINVAL; | 623 | return ERR_PTR(-EINVAL); |
| 562 | } | 624 | } |
| 563 | 625 | ||
| 564 | static int kxcjk1013_convert_wake_odr_to_bit(int val, int val2) | 626 | static int kxcjk1013_convert_odr_value(const struct kx_odr_map *map, |
| 627 | size_t map_size, int odr_bits, | ||
| 628 | int *val, int *val2) | ||
| 565 | { | 629 | { |
| 566 | int i; | 630 | int i; |
| 567 | 631 | ||
| 568 | for (i = 0; i < ARRAY_SIZE(wake_odr_data_rate_table); ++i) { | 632 | for (i = 0; i < map_size; ++i) { |
| 569 | if (wake_odr_data_rate_table[i].val == val && | 633 | if (map[i].odr_bits == odr_bits) { |
| 570 | wake_odr_data_rate_table[i].val2 == val2) { | 634 | *val = map[i].val; |
| 571 | return wake_odr_data_rate_table[i].odr_bits; | 635 | *val2 = map[i].val2; |
| 636 | return IIO_VAL_INT_PLUS_MICRO; | ||
| 572 | } | 637 | } |
| 573 | } | 638 | } |
| 574 | 639 | ||
| @@ -578,16 +643,24 @@ static int kxcjk1013_convert_wake_odr_to_bit(int val, int val2) · 3 unmodified lines | |||
| 578 | static int kxcjk1013_set_odr(struct kxcjk1013_data *data, int val, int val2) | 643 | static int kxcjk1013_set_odr(struct kxcjk1013_data *data, int val, int val2) |
| 579 | { | 644 | { |
| 580 | int ret; | 645 | int ret; |
| 581 | int odr_bits; | ||
| 582 | enum kxcjk1013_mode store_mode; | 646 | enum kxcjk1013_mode store_mode; |
| 647 | const struct kx_odr_map *odr_setting; | ||
| 583 | 648 | ||
| 584 | ret = kxcjk1013_get_mode(data, &store_mode); | 649 | ret = kxcjk1013_get_mode(data, &store_mode); |
| 585 | if (ret < 0) | 650 | if (ret < 0) |
| 586 | return ret; | 651 | return ret; |
| 587 | 652 | ||
| 588 | odr_bits = kxcjk1013_convert_freq_to_bit(val, val2); | 653 | if (data->chipset == KXTF9) |
| 589 | if (odr_bits < 0) | 654 | odr_setting = kxcjk1013_find_odr_value(kxtf9_samp_freq_table, |
| 590 | return odr_bits; | 655 | ARRAY_SIZE(kxtf9_samp_freq_table), |
| 656 | val, val2); | ||
| 657 | else | ||
| 658 | odr_setting = kxcjk1013_find_odr_value(samp_freq_table, | ||
| 659 | ARRAY_SIZE(samp_freq_table), | ||
| 660 | val, val2); | ||
| 661 | |||
| 662 | if (IS_ERR(odr_setting)) | ||
| 663 | return PTR_ERR(odr_setting); | ||
| 591 | 664 | ||
| 592 | /* To change ODR, the chip must be set to STANDBY as per spec */ | 665 | /* To change ODR, the chip must be set to STANDBY as per spec */ |
| 593 | ret = kxcjk1013_set_mode(data, STANDBY); | 666 | ret = kxcjk1013_set_mode(data, STANDBY); |
| @@ -595,20 +668,16 @@ static int kxcjk1013_set_odr(struct kxcjk1013_data *data, int val, int val2) · 1 unmodified line | |||
| 595 | return ret; | 668 | return ret; |
| 596 | 669 | ||
| 597 | ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_DATA_CTRL, | 670 | ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_DATA_CTRL, |
| 598 | odr_bits); | 671 | odr_setting->odr_bits); |
| 599 | if (ret < 0) { | 672 | if (ret < 0) { |
| 600 | dev_err(&data->client->dev, "Error writing data_ctrl\n"); | 673 | dev_err(&data->client->dev, "Error writing data_ctrl\n"); |
| 601 | return ret; | 674 | return ret; |
| 602 | } | 675 | } |
| 603 | 676 | ||
| 604 | data->odr_bits = odr_bits; | 677 | data->odr_bits = odr_setting->odr_bits; |
| 605 | |||
| 606 | odr_bits = kxcjk1013_convert_wake_odr_to_bit(val, val2); | ||
| 607 | if (odr_bits < 0) | ||
| 608 | return odr_bits; | ||
| 609 | 678 | ||
| 610 | ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_CTRL2, | 679 | ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_CTRL2, |
| 611 | odr_bits); | 680 | odr_setting->wuf_bits); |
| 612 | if (ret < 0) { | 681 | if (ret < 0) { |
| 613 | dev_err(&data->client->dev, "Error writing reg_ctrl2\n"); | 682 | dev_err(&data->client->dev, "Error writing reg_ctrl2\n"); |
| 614 | return ret; | 683 | return ret; |
| @@ -625,17 +694,14 @@ static int kxcjk1013_set_odr(struct kxcjk1013_data *data, int val, int val2) · 10 unmodified lines | |||
| 625 | 694 | ||
| 626 | static int kxcjk1013_get_odr(struct kxcjk1013_data *data, int *val, int *val2) | 695 | static int kxcjk1013_get_odr(struct kxcjk1013_data *data, int *val, int *val2) |
| 627 | { | 696 | { |
| 628 | int i; | 697 | if (data->chipset == KXTF9) |
| 629 | 698 | return kxcjk1013_convert_odr_value(kxtf9_samp_freq_table, | |
| 630 | for (i = 0; i < ARRAY_SIZE(samp_freq_table); ++i) { | 699 | ARRAY_SIZE(kxtf9_samp_freq_table), |
| 631 | if (samp_freq_table[i].odr_bits == data->odr_bits) { | 700 | data->odr_bits, val, val2); |
| 632 | *val = samp_freq_table[i].val; | 701 | else |
| 633 | *val2 = samp_freq_table[i].val2; | 702 | return kxcjk1013_convert_odr_value(samp_freq_table, |
| 634 | return IIO_VAL_INT_PLUS_MICRO; | 703 | ARRAY_SIZE(samp_freq_table), |
| 635 | } | 704 | data->odr_bits, val, val2); |
| 636 | } | ||
| 637 | |||
| 638 | return -EINVAL; | ||
| 639 | } | 705 | } |
| 640 | 706 | ||
| 641 | static int kxcjk1013_get_acc_reg(struct kxcjk1013_data *data, int axis) | 707 | static int kxcjk1013_get_acc_reg(struct kxcjk1013_data *data, int axis) |
| @@ -886,13 +952,29 @@ static int kxcjk1013_buffer_postdisable(struct iio_dev *indio_dev) · 244 unmodified lines | |||
| 886 | return kxcjk1013_set_power_state(data, false); | 952 | return kxcjk1013_set_power_state(data, false); |
| 887 | } | 953 | } |
| 888 | 954 | ||
| 889 | static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( | 955 | static ssize_t kxcjk1013_get_samp_freq_avail(struct device *dev, |
| 890 | "0.781000 1.563000 3.125000 6.250000 12.500000 25 50 100 200 400 800 1600"); | 956 | struct device_attribute *attr, |
| 957 | char *buf) | ||
| 958 | { | ||
| 959 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); | ||
| 960 | struct kxcjk1013_data *data = iio_priv(indio_dev); | ||
| 961 | const char *str; | ||
| 962 | |||
| 963 | if (data->chipset == KXTF9) | ||
| 964 | str = kxtf9_samp_freq_avail; | ||
| 965 | else | ||
| 966 | str = kxcjk1013_samp_freq_avail; | ||
| 967 | |||
| 968 | return sprintf(buf, "%s\n", str); | ||
| 969 | } | ||
| 970 | |||
| 971 | static IIO_DEVICE_ATTR(in_accel_sampling_frequency_available, S_IRUGO, | ||
| 972 | kxcjk1013_get_samp_freq_avail, NULL, 0); | ||
| 891 | 973 | ||
| 892 | static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019163 0.038326"); | 974 | static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019163 0.038326"); |
| 893 | 975 | ||
| 894 | static struct attribute *kxcjk1013_attributes[] = { | 976 | static struct attribute *kxcjk1013_attributes[] = { |
| 895 | &iio_const_attr_sampling_frequency_available.dev_attr.attr, | 977 | &iio_dev_attr_in_accel_sampling_frequency_available.dev_attr.attr, |
| 896 | &iio_const_attr_in_accel_scale_available.dev_attr.attr, | 978 | &iio_const_attr_in_accel_scale_available.dev_attr.attr, |
| 897 | NULL, | 979 | NULL, |
| 898 | }; | 980 | }; |
| @@ -950,7 +1032,6 @@ static const struct iio_info kxcjk1013_info = { · 51 unmodified lines | |||
| 950 | .write_event_value = kxcjk1013_write_event, | 1032 | .write_event_value = kxcjk1013_write_event, |
| 951 | .write_event_config = kxcjk1013_write_event_config, | 1033 | .write_event_config = kxcjk1013_write_event_config, |
| 952 | .read_event_config = kxcjk1013_read_event_config, | 1034 | .read_event_config = kxcjk1013_read_event_config, |
| 953 | .driver_module = THIS_MODULE, | ||
| 954 | }; | 1035 | }; |
| 955 | 1036 | ||
| 956 | static const unsigned long kxcjk1013_scan_masks[] = {0x7, 0}; | 1037 | static const unsigned long kxcjk1013_scan_masks[] = {0x7, 0}; |
| @@ -1036,9 +1117,74 @@ static int kxcjk1013_data_rdy_trigger_set_state(struct iio_trigger *trig, · 79 unmodified lines | |||
| 1036 | static const struct iio_trigger_ops kxcjk1013_trigger_ops = { | 1117 | static const struct iio_trigger_ops kxcjk1013_trigger_ops = { |
| 1037 | .set_trigger_state = kxcjk1013_data_rdy_trigger_set_state, | 1118 | .set_trigger_state = kxcjk1013_data_rdy_trigger_set_state, |
| 1038 | .try_reenable = kxcjk1013_trig_try_reen, | 1119 | .try_reenable = kxcjk1013_trig_try_reen, |
| 1039 | .owner = THIS_MODULE, | ||
| 1040 | }; | 1120 | }; |
| 1041 | 1121 | ||
| 1122 | static void kxcjk1013_report_motion_event(struct iio_dev *indio_dev) | ||
| 1123 | { | ||
| 1124 | struct kxcjk1013_data *data = iio_priv(indio_dev); | ||
| 1125 | |||
| 1126 | int ret = i2c_smbus_read_byte_data(data->client, | ||
| 1127 | KXCJK1013_REG_INT_SRC2); | ||
| 1128 | if (ret < 0) { | ||
| 1129 | dev_err(&data->client->dev, "Error reading reg_int_src2\n"); | ||
| 1130 | return; | ||
| 1131 | } | ||
| 1132 | |||
| 1133 | if (ret & KXCJK1013_REG_INT_SRC2_BIT_XN) | ||
| 1134 | iio_push_event(indio_dev, | ||
| 1135 | IIO_MOD_EVENT_CODE(IIO_ACCEL, | ||
| 1136 | 0, | ||
| 1137 | IIO_MOD_X, | ||
| 1138 | IIO_EV_TYPE_THRESH, | ||
| 1139 | IIO_EV_DIR_FALLING), | ||
| 1140 | data->timestamp); | ||
| 1141 | |||
| 1142 | if (ret & KXCJK1013_REG_INT_SRC2_BIT_XP) | ||
| 1143 | iio_push_event(indio_dev, | ||
| 1144 | IIO_MOD_EVENT_CODE(IIO_ACCEL, | ||
| 1145 | 0, | ||
| 1146 | IIO_MOD_X, | ||
| 1147 | IIO_EV_TYPE_THRESH, | ||
| 1148 | IIO_EV_DIR_RISING), | ||
| 1149 | data->timestamp); | ||
| 1150 | |||
| 1151 | if (ret & KXCJK1013_REG_INT_SRC2_BIT_YN) | ||
| 1152 | iio_push_event(indio_dev, | ||
| 1153 | IIO_MOD_EVENT_CODE(IIO_ACCEL, | ||
| 1154 | 0, | ||
| 1155 | IIO_MOD_Y, | ||
| 1156 | IIO_EV_TYPE_THRESH, | ||
| 1157 | IIO_EV_DIR_FALLING), | ||
| 1158 | data->timestamp); | ||
| 1159 | |||
| 1160 | if (ret & KXCJK1013_REG_INT_SRC2_BIT_YP) | ||
| 1161 | iio_push_event(indio_dev, | ||
| 1162 | IIO_MOD_EVENT_CODE(IIO_ACCEL, | ||
| 1163 | 0, | ||
| 1164 | IIO_MOD_Y, | ||
| 1165 | IIO_EV_TYPE_THRESH, | ||
| 1166 | IIO_EV_DIR_RISING), | ||
| 1167 | data->timestamp); | ||
| 1168 | |||
| 1169 | if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZN) | ||
| 1170 | iio_push_event(indio_dev, | ||
| 1171 | IIO_MOD_EVENT_CODE(IIO_ACCEL, | ||
| 1172 | 0, | ||
| 1173 | IIO_MOD_Z, | ||
| 1174 | IIO_EV_TYPE_THRESH, | ||
| 1175 | IIO_EV_DIR_FALLING), | ||
| 1176 | data->timestamp); | ||
| 1177 | |||
| 1178 | if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZP) | ||
| 1179 | iio_push_event(indio_dev, | ||
| 1180 | IIO_MOD_EVENT_CODE(IIO_ACCEL, | ||
| 1181 | 0, | ||
| 1182 | IIO_MOD_Z, | ||
| 1183 | IIO_EV_TYPE_THRESH, | ||
| 1184 | IIO_EV_DIR_RISING), | ||
| 1185 | data->timestamp); | ||
| 1186 | } | ||
| 1187 | |||
| 1042 | static irqreturn_t kxcjk1013_event_handler(int irq, void *private) | 1188 | static irqreturn_t kxcjk1013_event_handler(int irq, void *private) |
| 1043 | { | 1189 | { |
| 1044 | struct iio_dev *indio_dev = private; | 1190 | struct iio_dev *indio_dev = private; |
| @@ -1051,66 +1197,17 @@ static irqreturn_t kxcjk1013_event_handler(int irq, void *private) · 6 unmodified lines | |||
| 1051 | goto ack_intr; | 1197 | goto ack_intr; |
| 1052 | } | 1198 | } |
| 1053 | 1199 | ||
| 1054 | if (ret & 0x02) { | 1200 | if (ret & KXCJK1013_REG_INT_SRC1_BIT_WUFS) { |
| 1055 | ret = i2c_smbus_read_byte_data(data->client, | 1201 | if (data->chipset == KXTF9) |
| 1056 | KXCJK1013_REG_INT_SRC2); | ||
| 1057 | if (ret < 0) { | ||
| 1058 | dev_err(&data->client->dev, | ||
| 1059 | "Error reading reg_int_src2\n"); | ||
| 1060 | goto ack_intr; | ||
| 1061 | } | ||
| 1062 | |||
| 1063 | if (ret & KXCJK1013_REG_INT_SRC2_BIT_XN) | ||
| 1064 | iio_push_event(indio_dev, | ||
| 1065 | IIO_MOD_EVENT_CODE(IIO_ACCEL, | ||
| 1066 | 0, | ||
| 1067 | IIO_MOD_X, | ||
| 1068 | IIO_EV_TYPE_THRESH, | ||
| 1069 | IIO_EV_DIR_FALLING), | ||
| 1070 | data->timestamp); | ||
| 1071 | if (ret & KXCJK1013_REG_INT_SRC2_BIT_XP) | ||
| 1072 | iio_push_event(indio_dev, | ||
| 1073 | IIO_MOD_EVENT_CODE(IIO_ACCEL, | ||
| 1074 | 0, | ||
| 1075 | IIO_MOD_X, | ||
| 1076 | IIO_EV_TYPE_THRESH, | ||
| 1077 | IIO_EV_DIR_RISING), | ||
| 1078 | data->timestamp); | ||
| 1079 | |||
| 1080 | |||
| 1081 | if (ret & KXCJK1013_REG_INT_SRC2_BIT_YN) | ||
| 1082 | iio_push_event(indio_dev, | ||
| 1083 | IIO_MOD_EVENT_CODE(IIO_ACCEL, | ||
| 1084 | 0, | ||
| 1085 | IIO_MOD_Y, | ||
| 1086 | IIO_EV_TYPE_THRESH, | ||
| 1087 | IIO_EV_DIR_FALLING), | ||
| 1088 | data->timestamp); | ||
| 1089 | if (ret & KXCJK1013_REG_INT_SRC2_BIT_YP) | ||
| 1090 | iio_push_event(indio_dev, | ||
| 1091 | IIO_MOD_EVENT_CODE(IIO_ACCEL, | ||
| 1092 | 0, | ||
| 1093 | IIO_MOD_Y, | ||
| 1094 | IIO_EV_TYPE_THRESH, | ||
| 1095 | IIO_EV_DIR_RISING), | ||
| 1096 | data->timestamp); | ||
| 1097 | |||
| 1098 | if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZN) | ||
| 1099 | iio_push_event(indio_dev, | ||
| 1100 | IIO_MOD_EVENT_CODE(IIO_ACCEL, | ||
| 1101 | 0, | ||
| 1102 | IIO_MOD_Z, | ||
| 1103 | IIO_EV_TYPE_THRESH, | ||
| 1104 | IIO_EV_DIR_FALLING), | ||
| 1105 | data->timestamp); | ||
| 1106 | if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZP) | ||
| 1107 | iio_push_event(indio_dev, | 1202 | iio_push_event(indio_dev, |
| 1108 | IIO_MOD_EVENT_CODE(IIO_ACCEL, | 1203 | IIO_MOD_EVENT_CODE(IIO_ACCEL, |
| 1109 | 0, | 1204 | 0, |
| 1110 | IIO_MOD_Z, | 1205 | IIO_MOD_X_AND_Y_AND_Z, |
| 1111 | IIO_EV_TYPE_THRESH, | 1206 | IIO_EV_TYPE_THRESH, |
| 1112 | IIO_EV_DIR_RISING), | 1207 | IIO_EV_DIR_RISING), |
| 1113 | data->timestamp); | 1208 | data->timestamp); |
| 1209 | else | ||
| 1210 | kxcjk1013_report_motion_event(indio_dev); | ||
| 1114 | } | 1211 | } |
| 1115 | 1212 | ||
| 1116 | ack_intr: | 1213 | ack_intr: |
| @@ -1403,6 +1500,7 @@ static const struct i2c_device_id kxcjk1013_id[] = { · 286 unmodified lines | |||
| 1403 | {"kxcjk1013", KXCJK1013}, | 1500 | {"kxcjk1013", KXCJK1013}, |
| 1404 | {"kxcj91008", KXCJ91008}, | 1501 | {"kxcj91008", KXCJ91008}, |
| 1405 | {"kxtj21009", KXTJ21009}, | 1502 | {"kxtj21009", KXTJ21009}, |
| 1503 | {"kxtf9", KXTF9}, | ||
| 1406 | {"SMO8500", KXCJ91008}, | 1504 | {"SMO8500", KXCJ91008}, |
| 1407 | {} | 1505 | {} |
| 1408 | }; | 1506 | }; |
| @@ -390,7 +390,6 @@ static const struct iio_info kxsd9_info = { · 389 unmodified lines | |||
| 390 | .read_raw = &kxsd9_read_raw, | 390 | .read_raw = &kxsd9_read_raw, |
| 391 | .write_raw = &kxsd9_write_raw, | 391 | .write_raw = &kxsd9_write_raw, |
| 392 | .attrs = &kxsd9_attribute_group, | 392 | .attrs = &kxsd9_attribute_group, |
| 393 | .driver_module = THIS_MODULE, | ||
| 394 | }; | 393 | }; |
| 395 | 394 | ||
| 396 | /* Four channels apart from timestamp, scan mask = 0x0f */ | 395 | /* Four channels apart from timestamp, scan mask = 0x0f */ |
| @@ -107,7 +107,6 @@ static int mc3230_read_raw(struct iio_dev *indio_dev, · 106 unmodified lines | |||
| 107 | } | 107 | } |
| 108 | 108 | ||
| 109 | static const struct iio_info mc3230_info = { | 109 | static const struct iio_info mc3230_info = { |
| 110 | .driver_module = THIS_MODULE, | ||
| 111 | .read_raw = mc3230_read_raw, | 110 | .read_raw = mc3230_read_raw, |
| 112 | }; | 111 | }; |
| 113 | 112 | ||
| @@ -199,7 +199,6 @@ static const struct iio_info mma7455_info = { · 198 unmodified lines | |||
| 199 | .attrs = &mma7455_group, | 199 | .attrs = &mma7455_group, |
| 200 | .read_raw = mma7455_read_raw, | 200 | .read_raw = mma7455_read_raw, |
| 201 | .write_raw = mma7455_write_raw, | 201 | .write_raw = mma7455_write_raw, |
| 202 | .driver_module = THIS_MODULE, | ||
| 203 | }; | 202 | }; |
| 204 | 203 | ||
| 205 | #define MMA7455_CHANNEL(axis, idx) { \ | 204 | #define MMA7455_CHANNEL(axis, idx) { \ |
| @@ -168,7 +168,6 @@ static int mma7660_read_raw(struct iio_dev *indio_dev, · 167 unmodified lines | |||
| 168 | } | 168 | } |
| 169 | 169 | ||
| 170 | static const struct iio_info mma7660_info = { | 170 | static const struct iio_info mma7660_info = { |
| 171 | .driver_module = THIS_MODULE, | ||
| 172 | .read_raw = mma7660_read_raw, | 171 | .read_raw = mma7660_read_raw, |
| 173 | .attrs = &mma7660_attribute_group, | 172 | .attrs = &mma7660_attribute_group, |
| 174 | }; | 173 | }; |
| @@ -59,7 +59,9 @@ · 58 unmodified lines | |||
| 59 | #define MMA8452_FF_MT_THS 0x17 | 59 | #define MMA8452_FF_MT_THS 0x17 |
| 60 | #define MMA8452_FF_MT_THS_MASK 0x7f | 60 | #define MMA8452_FF_MT_THS_MASK 0x7f |
| 61 | #define MMA8452_FF_MT_COUNT 0x18 | 61 | #define MMA8452_FF_MT_COUNT 0x18 |
| 62 | #define MMA8452_FF_MT_CHAN_SHIFT 3 | ||
| 62 | #define MMA8452_TRANSIENT_CFG 0x1d | 63 | #define MMA8452_TRANSIENT_CFG 0x1d |
| 64 | #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1) | ||
| 63 | #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0) | 65 | #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0) |
| 64 | #define MMA8452_TRANSIENT_CFG_ELE BIT(4) | 66 | #define MMA8452_TRANSIENT_CFG_ELE BIT(4) |
| 65 | #define MMA8452_TRANSIENT_SRC 0x1e | 67 | #define MMA8452_TRANSIENT_SRC 0x1e |
| @@ -69,6 +71,7 @@ · 3 unmodified lines | |||
| 69 | #define MMA8452_TRANSIENT_THS 0x1f | 71 | #define MMA8452_TRANSIENT_THS 0x1f |
| 70 | #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0) | 72 | #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0) |
| 71 | #define MMA8452_TRANSIENT_COUNT 0x20 | 73 | #define MMA8452_TRANSIENT_COUNT 0x20 |
| 74 | #define MMA8452_TRANSIENT_CHAN_SHIFT 1 | ||
| 72 | #define MMA8452_CTRL_REG1 0x2a | 75 | #define MMA8452_CTRL_REG1 0x2a |
| 73 | #define MMA8452_CTRL_ACTIVE BIT(0) | 76 | #define MMA8452_CTRL_ACTIVE BIT(0) |
| 74 | #define MMA8452_CTRL_DR_MASK GENMASK(5, 3) | 77 | #define MMA8452_CTRL_DR_MASK GENMASK(5, 3) |
| @@ -107,6 +110,51 @@ struct mma8452_data { · 32 unmodified lines | |||
| 107 | const struct mma_chip_info *chip_info; | 110 | const struct mma_chip_info *chip_info; |
| 108 | }; | 111 | }; |
| 109 | 112 | ||
| 113 | /** | ||
| 114 | * struct mma8452_event_regs - chip specific data related to events | ||
| 115 | * @ev_cfg: event config register address | ||
| 116 | * @ev_cfg_ele: latch bit in event config register | ||
| 117 | * @ev_cfg_chan_shift: number of the bit to enable events in X | ||
| 118 | * direction; in event config register | ||
| 119 | * @ev_src: event source register address | ||
| 120 | * @ev_ths: event threshold register address | ||
| 121 | * @ev_ths_mask: mask for the threshold value | ||
| 122 | * @ev_count: event count (period) register address | ||
| 123 | * | ||
| 124 | * Since not all chips supported by the driver support comparing high pass | ||
| 125 | * filtered data for events (interrupts), different interrupt sources are | ||
| 126 | * used for different chips and the relevant registers are included here. | ||
| 127 | */ | ||
| 128 | struct mma8452_event_regs { | ||
| 129 | u8 ev_cfg; | ||
| 130 | u8 ev_cfg_ele; | ||
| 131 | u8 ev_cfg_chan_shift; | ||
| 132 | u8 ev_src; | ||
| 133 | u8 ev_ths; | ||
| 134 | u8 ev_ths_mask; | ||
| 135 | u8 ev_count; | ||
| 136 | }; | ||
| 137 | |||
| 138 | static const struct mma8452_event_regs ev_regs_accel_falling = { | ||
| 139 | .ev_cfg = MMA8452_FF_MT_CFG, | ||
| 140 | .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE, | ||
| 141 | .ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT, | ||
| 142 | .ev_src = MMA8452_FF_MT_SRC, | ||
| 143 | .ev_ths = MMA8452_FF_MT_THS, | ||
| 144 | .ev_ths_mask = MMA8452_FF_MT_THS_MASK, | ||
| 145 | .ev_count = MMA8452_FF_MT_COUNT | ||
| 146 | }; | ||
| 147 | |||
| 148 | static const struct mma8452_event_regs ev_regs_accel_rising = { | ||
| 149 | .ev_cfg = MMA8452_TRANSIENT_CFG, | ||
| 150 | .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE, | ||
| 151 | .ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT, | ||
| 152 | .ev_src = MMA8452_TRANSIENT_SRC, | ||
| 153 | .ev_ths = MMA8452_TRANSIENT_THS, | ||
| 154 | .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK, | ||
| 155 | .ev_count = MMA8452_TRANSIENT_COUNT, | ||
| 156 | }; | ||
| 157 | |||
| 110 | /** | 158 | /** |
| 111 | * struct mma_chip_info - chip specific data | 159 | * struct mma_chip_info - chip specific data |
| 112 | * @chip_id: WHO_AM_I register's value | 160 | * @chip_id: WHO_AM_I register's value |
| @@ -116,40 +164,16 @@ struct mma8452_data { · 3 unmodified lines | |||
| 116 | * @mma_scales: scale factors for converting register values | 164 | * @mma_scales: scale factors for converting register values |
| 117 | * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers | 165 | * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers |
| 118 | * per mode: m/s^2 and micro m/s^2 | 166 | * per mode: m/s^2 and micro m/s^2 |
| 119 | * @ev_cfg: event config register address | 167 | * @all_events: all events supported by this chip |
| 120 | * @ev_cfg_ele: latch bit in event config register | 168 | * @enabled_events: event flags enabled and handled by this driver |
| 121 | * @ev_cfg_chan_shift: number of the bit to enable events in X | ||
| 122 | * direction; in event config register | ||
| 123 | * @ev_src: event source register address | ||
| 124 | * @ev_src_xe: bit in event source register that indicates | ||
| 125 | * an event in X direction | ||
| 126 | * @ev_src_ye: bit in event source register that indicates | ||
| 127 | * an event in Y direction | ||
| 128 | * @ev_src_ze: bit in event source register that indicates | ||
| 129 | * an event in Z direction | ||
| 130 | * @ev_ths: event threshold register address | ||
| 131 | * @ev_ths_mask: mask for the threshold value | ||
| 132 | * @ev_count: event count (period) register address | ||
| 133 | * | ||
| 134 | * Since not all chips supported by the driver support comparing high pass | ||
| 135 | * filtered data for events (interrupts), different interrupt sources are | ||
| 136 | * used for different chips and the relevant registers are included here. | ||
| 137 | */ | 169 | */ |
| 138 | struct mma_chip_info { | 170 | struct mma_chip_info { |
| 139 | u8 chip_id; | 171 | u8 chip_id; |
| 140 | const struct iio_chan_spec *channels; | 172 | const struct iio_chan_spec *channels; |
| 141 | int num_channels; | 173 | int num_channels; |
| 142 | const int mma_scales[3][2]; | 174 | const int mma_scales[3][2]; |
| 143 | u8 ev_cfg; | 175 | int all_events; |
| 144 | u8 ev_cfg_ele; | 176 | int enabled_events; |
| 145 | u8 ev_cfg_chan_shift; | ||
| 146 | u8 ev_src; | ||
| 147 | u8 ev_src_xe; | ||
| 148 | u8 ev_src_ye; | ||
| 149 | u8 ev_src_ze; | ||
| 150 | u8 ev_ths; | ||
| 151 | u8 ev_ths_mask; | ||
| 152 | u8 ev_count; | ||
| 153 | }; | 177 | }; |
| 154 | 178 | ||
| 155 | enum { | 179 | enum { |
| @@ -394,11 +418,11 @@ static ssize_t mma8452_show_os_ratio_avail(struct device *dev, · 238 unmodified lines | |||
| 394 | } | 418 | } |
| 395 | 419 | ||
| 396 | static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail); | 420 | static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail); |
| 397 | static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO, | 421 | static IIO_DEVICE_ATTR(in_accel_scale_available, 0444, |
| 398 | mma8452_show_scale_avail, NULL, 0); | 422 | mma8452_show_scale_avail, NULL, 0); |
| 399 | static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available, | 423 | static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available, |
| 400 | S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0); | 424 | 0444, mma8452_show_hp_cutoff_avail, NULL, 0); |
| 401 | static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, S_IRUGO, | 425 | static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, 0444, |
| 402 | mma8452_show_os_ratio_avail, NULL, 0); | 426 | mma8452_show_os_ratio_avail, NULL, 0); |
| 403 | 427 | ||
| 404 | static int mma8452_get_samp_freq_index(struct mma8452_data *data, | 428 | static int mma8452_get_samp_freq_index(struct mma8452_data *data, |
| @@ -602,9 +626,8 @@ static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode) · 197 unmodified lines | |||
| 602 | static int mma8452_freefall_mode_enabled(struct mma8452_data *data) | 626 | static int mma8452_freefall_mode_enabled(struct mma8452_data *data) |
| 603 | { | 627 | { |
| 604 | int val; | 628 | int val; |
| 605 | const struct mma_chip_info *chip = data->chip_info; | ||
| 606 | 629 | ||
| 607 | val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg); | 630 | val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG); |
| 608 | if (val < 0) | 631 | if (val < 0) |
| 609 | return val; | 632 | return val; |
| 610 | 633 | ||
| @@ -614,29 +637,28 @@ static int mma8452_freefall_mode_enabled(struct mma8452_data *data) · 3 unmodified lines | |||
| 614 | static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state) | 637 | static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state) |
| 615 | { | 638 | { |
| 616 | int val; | 639 | int val; |
| 617 | const struct mma_chip_info *chip = data->chip_info; | ||
| 618 | 640 | ||
| 619 | if ((state && mma8452_freefall_mode_enabled(data)) || | 641 | if ((state && mma8452_freefall_mode_enabled(data)) || |
| 620 | (!state && !(mma8452_freefall_mode_enabled(data)))) | 642 | (!state && !(mma8452_freefall_mode_enabled(data)))) |
| 621 | return 0; | 643 | return 0; |
| 622 | 644 | ||
| 623 | val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg); | 645 | val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG); |
| 624 | if (val < 0) | 646 | if (val < 0) |
| 625 | return val; | 647 | return val; |
| 626 | 648 | ||
| 627 | if (state) { | 649 | if (state) { |
| 628 | val |= BIT(idx_x + chip->ev_cfg_chan_shift); | 650 | val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); |
| 629 | val |= BIT(idx_y + chip->ev_cfg_chan_shift); | 651 | val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); |
| 630 | val |= BIT(idx_z + chip->ev_cfg_chan_shift); | 652 | val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); |
| 631 | val &= ~MMA8452_FF_MT_CFG_OAE; | 653 | val &= ~MMA8452_FF_MT_CFG_OAE; |
| 632 | } else { | 654 | } else { |
| 633 | val &= ~BIT(idx_x + chip->ev_cfg_chan_shift); | 655 | val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); |
| 634 | val &= ~BIT(idx_y + chip->ev_cfg_chan_shift); | 656 | val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); |
| 635 | val &= ~BIT(idx_z + chip->ev_cfg_chan_shift); | 657 | val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); |
| 636 | val |= MMA8452_FF_MT_CFG_OAE; | 658 | val |= MMA8452_FF_MT_CFG_OAE; |
| 637 | } | 659 | } |
| 638 | 660 | ||
| 639 | return mma8452_change_config(data, chip->ev_cfg, val); | 661 | return mma8452_change_config(data, MMA8452_FF_MT_CFG, val); |
| 640 | } | 662 | } |
| 641 | 663 | ||
| 642 | static int mma8452_set_hp_filter_frequency(struct mma8452_data *data, | 664 | static int mma8452_set_hp_filter_frequency(struct mma8452_data *data, |
| @@ -740,7 +762,37 @@ static int mma8452_write_raw(struct iio_dev *indio_dev, · 97 unmodified lines | |||
| 740 | return ret; | 762 | return ret; |
| 741 | } | 763 | } |
| 742 | 764 | ||
| 743 | static int mma8452_read_thresh(struct iio_dev *indio_dev, | 765 | static int mma8452_get_event_regs(struct mma8452_data *data, |
| 766 | const struct iio_chan_spec *chan, enum iio_event_direction dir, | ||
| 767 | const struct mma8452_event_regs **ev_reg) | ||
| 768 | { | ||
| 769 | if (!chan) | ||
| 770 | return -EINVAL; | ||
| 771 | |||
| 772 | switch (chan->type) { | ||
| 773 | case IIO_ACCEL: | ||
| 774 | switch (dir) { | ||
| 775 | case IIO_EV_DIR_RISING: | ||
| 776 | if ((data->chip_info->all_events | ||
| 777 | & MMA8452_INT_TRANS) && | ||
| 778 | (data->chip_info->enabled_events | ||
| 779 | & MMA8452_INT_TRANS)) | ||
| 780 | *ev_reg = &ev_regs_accel_rising; | ||
| 781 | else | ||
| 782 | *ev_reg = &ev_regs_accel_falling; | ||
| 783 | return 0; | ||
| 784 | case IIO_EV_DIR_FALLING: | ||
| 785 | *ev_reg = &ev_regs_accel_falling; | ||
| 786 | return 0; | ||
| 787 | default: | ||
| 788 | return -EINVAL; | ||
| 789 | } | ||
| 790 | default: | ||
| 791 | return -EINVAL; | ||
| 792 | } | ||
| 793 | } | ||
| 794 | |||
| 795 | static int mma8452_read_event_value(struct iio_dev *indio_dev, | ||
| 744 | const struct iio_chan_spec *chan, | 796 | const struct iio_chan_spec *chan, |
| 745 | enum iio_event_type type, | 797 | enum iio_event_type type, |
| 746 | enum iio_event_direction dir, | 798 | enum iio_event_direction dir, |
| @@ -749,21 +801,24 @@ static int mma8452_read_thresh(struct iio_dev *indio_dev, · 2 unmodified lines | |||
| 749 | { | 801 | { |
| 750 | struct mma8452_data *data = iio_priv(indio_dev); | 802 | struct mma8452_data *data = iio_priv(indio_dev); |
| 751 | int ret, us, power_mode; | 803 | int ret, us, power_mode; |
| 804 | const struct mma8452_event_regs *ev_regs; | ||
| 805 | |||
| 806 | ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); | ||
| 807 | if (ret) | ||
| 808 | return ret; | ||
| 752 | 809 | ||
| 753 | switch (info) { | 810 | switch (info) { |
| 754 | case IIO_EV_INFO_VALUE: | 811 | case IIO_EV_INFO_VALUE: |
| 755 | ret = i2c_smbus_read_byte_data(data->client, | 812 | ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_ths); |
| 756 | data->chip_info->ev_ths); | ||
| 757 | if (ret < 0) | 813 | if (ret < 0) |
| 758 | return ret; | 814 | return ret; |
| 759 | 815 | ||
| 760 | *val = ret & data->chip_info->ev_ths_mask; | 816 | *val = ret & ev_regs->ev_ths_mask; |
| 761 | 817 | ||
| 762 | return IIO_VAL_INT; | 818 | return IIO_VAL_INT; |
| 763 | 819 | ||
| 764 | case IIO_EV_INFO_PERIOD: | 820 | case IIO_EV_INFO_PERIOD: |
| 765 | ret = i2c_smbus_read_byte_data(data->client, | 821 | ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_count); |
| 766 | data->chip_info->ev_count); | ||
| 767 | if (ret < 0) | 822 | if (ret < 0) |
| 768 | return ret; | 823 | return ret; |
| 769 | 824 | ||
| @@ -800,7 +855,7 @@ static int mma8452_read_thresh(struct iio_dev *indio_dev, · 30 unmodified lines | |||
| 800 | } | 855 | } |
| 801 | } | 856 | } |
| 802 | 857 | ||
| 803 | static int mma8452_write_thresh(struct iio_dev *indio_dev, | 858 | static int mma8452_write_event_value(struct iio_dev *indio_dev, |
| 804 | const struct iio_chan_spec *chan, | 859 | const struct iio_chan_spec *chan, |
| 805 | enum iio_event_type type, | 860 | enum iio_event_type type, |
| 806 | enum iio_event_direction dir, | 861 | enum iio_event_direction dir, |
| @@ -809,14 +864,18 @@ static int mma8452_write_thresh(struct iio_dev *indio_dev, · 2 unmodified lines | |||
| 809 | { | 864 | { |
| 810 | struct mma8452_data *data = iio_priv(indio_dev); | 865 | struct mma8452_data *data = iio_priv(indio_dev); |
| 811 | int ret, reg, steps; | 866 | int ret, reg, steps; |
| 867 | const struct mma8452_event_regs *ev_regs; | ||
| 868 | |||
| 869 | ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); | ||
| 870 | if (ret) | ||
| 871 | return ret; | ||
| 812 | 872 | ||
| 813 | switch (info) { | 873 | switch (info) { |
| 814 | case IIO_EV_INFO_VALUE: | 874 | case IIO_EV_INFO_VALUE: |
| 815 | if (val < 0 || val > MMA8452_TRANSIENT_THS_MASK) | 875 | if (val < 0 || val > ev_regs->ev_ths_mask) |
| 816 | return -EINVAL; | 876 | return -EINVAL; |
| 817 | 877 | ||
| 818 | return mma8452_change_config(data, data->chip_info->ev_ths, | 878 | return mma8452_change_config(data, ev_regs->ev_ths, val); |
| 819 | val); | ||
| 820 | 879 | ||
| 821 | case IIO_EV_INFO_PERIOD: | 880 | case IIO_EV_INFO_PERIOD: |
| 822 | ret = mma8452_get_power_mode(data); | 881 | ret = mma8452_get_power_mode(data); |
| @@ -830,8 +889,7 @@ static int mma8452_write_thresh(struct iio_dev *indio_dev, · 7 unmodified lines | |||
| 830 | if (steps < 0 || steps > 0xff) | 889 | if (steps < 0 || steps > 0xff) |
| 831 | return -EINVAL; | 890 | return -EINVAL; |
| 832 | 891 | ||
| 833 | return mma8452_change_config(data, data->chip_info->ev_count, | 892 | return mma8452_change_config(data, ev_regs->ev_count, steps); |
| 834 | steps); | ||
| 835 | 893 | ||
| 836 | case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: | 894 | case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: |
| 837 | reg = i2c_smbus_read_byte_data(data->client, | 895 | reg = i2c_smbus_read_byte_data(data->client, |
| @@ -861,23 +919,24 @@ static int mma8452_read_event_config(struct iio_dev *indio_dev, · 23 unmodified lines | |||
| 861 | enum iio_event_direction dir) | 919 | enum iio_event_direction dir) |
| 862 | { | 920 | { |
| 863 | struct mma8452_data *data = iio_priv(indio_dev); | 921 | struct mma8452_data *data = iio_priv(indio_dev); |
| 864 | const struct mma_chip_info *chip = data->chip_info; | ||
| 865 | int ret; | 922 | int ret; |
| 923 | const struct mma8452_event_regs *ev_regs; | ||
| 924 | |||
| 925 | ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); | ||
| 926 | if (ret) | ||
| 927 | return ret; | ||
| 866 | 928 | ||
| 867 | switch (dir) { | 929 | switch (dir) { |
| 868 | case IIO_EV_DIR_FALLING: | 930 | case IIO_EV_DIR_FALLING: |
| 869 | return mma8452_freefall_mode_enabled(data); | 931 | return mma8452_freefall_mode_enabled(data); |
| 870 | case IIO_EV_DIR_RISING: | 932 | case IIO_EV_DIR_RISING: |
| 871 | if (mma8452_freefall_mode_enabled(data)) | ||
| 872 | return 0; | ||
| 873 | |||
| 874 | ret = i2c_smbus_read_byte_data(data->client, | 933 | ret = i2c_smbus_read_byte_data(data->client, |
| 875 | data->chip_info->ev_cfg); | 934 | ev_regs->ev_cfg); |
| 876 | if (ret < 0) | 935 | if (ret < 0) |
| 877 | return ret; | 936 | return ret; |
| 878 | 937 | ||
| 879 | return !!(ret & BIT(chan->scan_index + | 938 | return !!(ret & BIT(chan->scan_index + |
| 880 | chip->ev_cfg_chan_shift)); | 939 | ev_regs->ev_cfg_chan_shift)); |
| 881 | default: | 940 | default: |
| 882 | return -EINVAL; | 941 | return -EINVAL; |
| 883 | } | 942 | } |
| @@ -890,8 +949,12 @@ static int mma8452_write_event_config(struct iio_dev *indio_dev, · 6 unmodified lines | |||
| 890 | int state) | 949 | int state) |
| 891 | { | 950 | { |
| 892 | struct mma8452_data *data = iio_priv(indio_dev); | 951 | struct mma8452_data *data = iio_priv(indio_dev); |
| 893 | const struct mma_chip_info *chip = data->chip_info; | ||
| 894 | int val, ret; | 952 | int val, ret; |
| 953 | const struct mma8452_event_regs *ev_regs; | ||
| 954 | |||
| 955 | ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); | ||
| 956 | if (ret) | ||
| 957 | return ret; | ||
| 895 | 958 | ||
| 896 | ret = mma8452_set_runtime_pm_state(data->client, state); | 959 | ret = mma8452_set_runtime_pm_state(data->client, state); |
| 897 | if (ret) | 960 | if (ret) |
| @@ -901,28 +964,30 @@ static int mma8452_write_event_config(struct iio_dev *indio_dev, · 3 unmodified lines | |||
| 901 | case IIO_EV_DIR_FALLING: | 964 | case IIO_EV_DIR_FALLING: |
| 902 | return mma8452_set_freefall_mode(data, state); | 965 | return mma8452_set_freefall_mode(data, state); |
| 903 | case IIO_EV_DIR_RISING: | 966 | case IIO_EV_DIR_RISING: |
| 904 | val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg); | 967 | val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg); |
| 905 | if (val < 0) | 968 | if (val < 0) |
| 906 | return val; | 969 | return val; |
| 907 | 970 | ||
| 908 | if (state) { | 971 | if (state) { |
| 909 | if (mma8452_freefall_mode_enabled(data)) { | 972 | if (mma8452_freefall_mode_enabled(data)) { |
| 910 | val &= ~BIT(idx_x + chip->ev_cfg_chan_shift); | 973 | val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift); |
| 911 | val &= ~BIT(idx_y + chip->ev_cfg_chan_shift); | 974 | val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift); |
| 912 | val &= ~BIT(idx_z + chip->ev_cfg_chan_shift); | 975 | val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift); |
| 913 | val |= MMA8452_FF_MT_CFG_OAE; | 976 | val |= MMA8452_FF_MT_CFG_OAE; |
| 914 | } | 977 | } |
| 915 | val |= BIT(chan->scan_index + chip->ev_cfg_chan_shift); | 978 | val |= BIT(chan->scan_index + |
| 979 | ev_regs->ev_cfg_chan_shift); | ||
| 916 | } else { | 980 | } else { |
| 917 | if (mma8452_freefall_mode_enabled(data)) | 981 | if (mma8452_freefall_mode_enabled(data)) |
| 918 | return 0; | 982 | return 0; |
| 919 | 983 | ||
| 920 | val &= ~BIT(chan->scan_index + chip->ev_cfg_chan_shift); | 984 | val &= ~BIT(chan->scan_index + |
| 985 | ev_regs->ev_cfg_chan_shift); | ||
| 921 | } | 986 | } |
| 922 | 987 | ||
| 923 | val |= chip->ev_cfg_ele; | 988 | val |= ev_regs->ev_cfg_ele; |
| 924 | 989 | ||
| 925 | return mma8452_change_config(data, chip->ev_cfg, val); | 990 | return mma8452_change_config(data, ev_regs->ev_cfg, val); |
| 926 | default: | 991 | default: |
| 927 | return -EINVAL; | 992 | return -EINVAL; |
| 928 | } | 993 | } |
| @@ -934,35 +999,25 @@ static void mma8452_transient_interrupt(struct iio_dev *indio_dev) · 5 unmodified lines | |||
| 934 | s64 ts = iio_get_time_ns(indio_dev); | 999 | s64 ts = iio_get_time_ns(indio_dev); |
| 935 | int src; | 1000 | int src; |
| 936 | 1001 | ||
| 937 | src = i2c_smbus_read_byte_data(data->client, data->chip_info->ev_src); | 1002 | src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC); |
| 938 | if (src < 0) | 1003 | if (src < 0) |
| 939 | return; | 1004 | return; |
| 940 | 1005 | ||
| 941 | if (mma8452_freefall_mode_enabled(data)) { | 1006 | if (src & MMA8452_TRANSIENT_SRC_XTRANSE) |
| 942 | iio_push_event(indio_dev, | ||
| 943 | IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, | ||
| 944 | IIO_MOD_X_AND_Y_AND_Z, | ||
| 945 | IIO_EV_TYPE_MAG, | ||
| 946 | IIO_EV_DIR_FALLING), | ||
| 947 | ts); | ||
| 948 | return; | ||
| 949 | } | ||
| 950 | |||
| 951 | if (src & data->chip_info->ev_src_xe) | ||
| 952 | iio_push_event(indio_dev, | 1007 | iio_push_event(indio_dev, |
| 953 | IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, | 1008 | IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, |
| 954 | IIO_EV_TYPE_MAG, | 1009 | IIO_EV_TYPE_MAG, |
| 955 | IIO_EV_DIR_RISING), | 1010 | IIO_EV_DIR_RISING), |
| 956 | ts); | 1011 | ts); |
| 957 | 1012 | ||
| 958 | if (src & data->chip_info->ev_src_ye) | 1013 | if (src & MMA8452_TRANSIENT_SRC_YTRANSE) |
| 959 | iio_push_event(indio_dev, | 1014 | iio_push_event(indio_dev, |
| 960 | IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y, | 1015 | IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y, |
| 961 | IIO_EV_TYPE_MAG, | 1016 | IIO_EV_TYPE_MAG, |
| 962 | IIO_EV_DIR_RISING), | 1017 | IIO_EV_DIR_RISING), |
| 963 | ts); | 1018 | ts); |
| 964 | 1019 | ||
| 965 | if (src & data->chip_info->ev_src_ze) | 1020 | if (src & MMA8452_TRANSIENT_SRC_ZTRANSE) |
| 966 | iio_push_event(indio_dev, | 1021 | iio_push_event(indio_dev, |
| 967 | IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z, | 1022 | IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z, |
| 968 | IIO_EV_TYPE_MAG, | 1023 | IIO_EV_TYPE_MAG, |
| @@ -974,7 +1029,6 @@ static irqreturn_t mma8452_interrupt(int irq, void *p) · 5 unmodified lines | |||
| 974 | { | 1029 | { |
| 975 | struct iio_dev *indio_dev = p; | 1030 | struct iio_dev *indio_dev = p; |
| 976 | struct mma8452_data *data = iio_priv(indio_dev); | 1031 | struct mma8452_data *data = iio_priv(indio_dev); |
| 977 | const struct mma_chip_info *chip = data->chip_info; | ||
| 978 | int ret = IRQ_NONE; | 1032 | int ret = IRQ_NONE; |
| 979 | int src; | 1033 | int src; |
| 980 | 1034 | ||
| @@ -982,15 +1036,29 @@ static irqreturn_t mma8452_interrupt(int irq, void *p) · 1 unmodified line | |||
| 982 | if (src < 0) | 1036 | if (src < 0) |
| 983 | return IRQ_NONE; | 1037 | return IRQ_NONE; |
| 984 | 1038 | ||
| 1039 | if (!(src & data->chip_info->enabled_events)) | ||
| 1040 | return IRQ_NONE; | ||
| 1041 | |||
| 985 | if (src & MMA8452_INT_DRDY) { | 1042 | if (src & MMA8452_INT_DRDY) { |
| 986 | iio_trigger_poll_chained(indio_dev->trig); | 1043 | iio_trigger_poll_chained(indio_dev->trig); |
| 987 | ret = IRQ_HANDLED; | 1044 | ret = IRQ_HANDLED; |
| 988 | } | 1045 | } |
| 989 | 1046 | ||
| 990 | if ((src & MMA8452_INT_TRANS && | 1047 | if (src & MMA8452_INT_FF_MT) { |
| 991 | chip->ev_src == MMA8452_TRANSIENT_SRC) || | 1048 | if (mma8452_freefall_mode_enabled(data)) { |
| 992 | (src & MMA8452_INT_FF_MT && | 1049 | s64 ts = iio_get_time_ns(indio_dev); |
| 993 | chip->ev_src == MMA8452_FF_MT_SRC)) { | 1050 | |
| 1051 | iio_push_event(indio_dev, | ||
| 1052 | IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, | ||
| 1053 | IIO_MOD_X_AND_Y_AND_Z, | ||
| 1054 | IIO_EV_TYPE_MAG, | ||
| 1055 | IIO_EV_DIR_FALLING), | ||
| 1056 | ts); | ||
| 1057 | } | ||
| 1058 | ret = IRQ_HANDLED; | ||
| 1059 | } | ||
| 1060 | |||
| 1061 | if (src & MMA8452_INT_TRANS) { | ||
| 994 | mma8452_transient_interrupt(indio_dev); | 1062 | mma8452_transient_interrupt(indio_dev); |
| 995 | ret = IRQ_HANDLED; | 1063 | ret = IRQ_HANDLED; |
| 996 | } | 1064 | } |
| @@ -1020,8 +1088,8 @@ done: · 23 unmodified lines | |||
| 1020 | } | 1088 | } |
| 1021 | 1089 | ||
| 1022 | static int mma8452_reg_access_dbg(struct iio_dev *indio_dev, | 1090 | static int mma8452_reg_access_dbg(struct iio_dev *indio_dev, |
| 1023 | unsigned reg, unsigned writeval, | 1091 | unsigned int reg, unsigned int writeval, |
| 1024 | unsigned *readval) | 1092 | unsigned int *readval) |
| 1025 | { | 1093 | { |
| 1026 | int ret; | 1094 | int ret; |
| 1027 | struct mma8452_data *data = iio_priv(indio_dev); | 1095 | struct mma8452_data *data = iio_priv(indio_dev); |
| @@ -1222,96 +1290,87 @@ static const struct mma_chip_info mma_chip_info_table[] = { · 194 unmodified lines | |||
| 1222 | * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665 | 1290 | * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665 |
| 1223 | */ | 1291 | */ |
| 1224 | .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, | 1292 | .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, |
| 1225 | .ev_cfg = MMA8452_TRANSIENT_CFG, | 1293 | /* |
| 1226 | .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE, | 1294 | * Although we enable the interrupt sources once and for |
| 1227 | .ev_cfg_chan_shift = 1, | 1295 | * all here the event detection itself is not enabled until |
| 1228 | .ev_src = MMA8452_TRANSIENT_SRC, | 1296 | * userspace asks for it by mma8452_write_event_config() |
| 1229 | .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE, | 1297 | */ |
| 1230 | .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE, | 1298 | .all_events = MMA8452_INT_DRDY | |
| 1231 | .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE, | 1299 | MMA8452_INT_TRANS | |
| 1232 | .ev_ths = MMA8452_TRANSIENT_THS, | 1300 | MMA8452_INT_FF_MT, |
| 1233 | .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK, | 1301 | .enabled_events = MMA8452_INT_TRANS | |
| 1234 | .ev_count = MMA8452_TRANSIENT_COUNT, | 1302 | MMA8452_INT_FF_MT, |
| 1235 | }, | 1303 | }, |
| 1236 | [mma8452] = { | 1304 | [mma8452] = { |
| 1237 | .chip_id = MMA8452_DEVICE_ID, | 1305 | .chip_id = MMA8452_DEVICE_ID, |
| 1238 | .channels = mma8452_channels, | 1306 | .channels = mma8452_channels, |
| 1239 | .num_channels = ARRAY_SIZE(mma8452_channels), | 1307 | .num_channels = ARRAY_SIZE(mma8452_channels), |
| 1240 | .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, | 1308 | .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, |
| 1241 | .ev_cfg = MMA8452_TRANSIENT_CFG, | 1309 | /* |
| 1242 | .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE, | 1310 | * Although we enable the interrupt sources once and for |
| 1243 | .ev_cfg_chan_shift = 1, | 1311 | * all here the event detection itself is not enabled until |
| 1244 | .ev_src = MMA8452_TRANSIENT_SRC, | 1312 | * userspace asks for it by mma8452_write_event_config() |
| 1245 | .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE, | 1313 | */ |
| 1246 | .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE, | 1314 | .all_events = MMA8452_INT_DRDY | |
| 1247 | .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE, | 1315 | MMA8452_INT_TRANS | |
| 1248 | .ev_ths = MMA8452_TRANSIENT_THS, | 1316 | MMA8452_INT_FF_MT, |
| 1249 | .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK, | 1317 | .enabled_events = MMA8452_INT_TRANS | |
| 1250 | .ev_count = MMA8452_TRANSIENT_COUNT, | 1318 | MMA8452_INT_FF_MT, |
| 1251 | }, | 1319 | }, |
| 1252 | [mma8453] = { | 1320 | [mma8453] = { |
| 1253 | .chip_id = MMA8453_DEVICE_ID, | 1321 | .chip_id = MMA8453_DEVICE_ID, |
| 1254 | .channels = mma8453_channels, | 1322 | .channels = mma8453_channels, |
| 1255 | .num_channels = ARRAY_SIZE(mma8453_channels), | 1323 | .num_channels = ARRAY_SIZE(mma8453_channels), |
| 1256 | .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, | 1324 | .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, |
| 1257 | .ev_cfg = MMA8452_TRANSIENT_CFG, | 1325 | /* |
| 1258 | .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE, | 1326 | * Although we enable the interrupt sources once and for |
| 1259 | .ev_cfg_chan_shift = 1, | 1327 | * all here the event detection itself is not enabled until |
| 1260 | .ev_src = MMA8452_TRANSIENT_SRC, | 1328 | * userspace asks for it by mma8452_write_event_config() |
| 1261 | .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE, | 1329 | */ |
| 1262 | .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE, | 1330 | .all_events = MMA8452_INT_DRDY | |
| 1263 | .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE, | 1331 | MMA8452_INT_TRANS | |
| 1264 | .ev_ths = MMA8452_TRANSIENT_THS, | 1332 | MMA8452_INT_FF_MT, |
| 1265 | .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK, | 1333 | .enabled_events = MMA8452_INT_TRANS | |
| 1266 | .ev_count = MMA8452_TRANSIENT_COUNT, | 1334 | MMA8452_INT_FF_MT, |
| 1267 | }, | 1335 | }, |
| 1268 | [mma8652] = { | 1336 | [mma8652] = { |
| 1269 | .chip_id = MMA8652_DEVICE_ID, | 1337 | .chip_id = MMA8652_DEVICE_ID, |
| 1270 | .channels = mma8652_channels, | 1338 | .channels = mma8652_channels, |
| 1271 | .num_channels = ARRAY_SIZE(mma8652_channels), | 1339 | .num_channels = ARRAY_SIZE(mma8652_channels), |
| 1272 | .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, | 1340 | .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, |
| 1273 | .ev_cfg = MMA8452_FF_MT_CFG, | 1341 | .all_events = MMA8452_INT_DRDY | |
| 1274 | .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE, | 1342 | MMA8452_INT_FF_MT, |
| 1275 | .ev_cfg_chan_shift = 3, | 1343 | .enabled_events = MMA8452_INT_FF_MT, |
| 1276 | .ev_src = MMA8452_FF_MT_SRC, | ||
| 1277 | .ev_src_xe = MMA8452_FF_MT_SRC_XHE, | ||
| 1278 | .ev_src_ye = MMA8452_FF_MT_SRC_YHE, | ||
| 1279 | .ev_src_ze = MMA8452_FF_MT_SRC_ZHE, | ||
| 1280 | .ev_ths = MMA8452_FF_MT_THS, | ||
| 1281 | .ev_ths_mask = MMA8452_FF_MT_THS_MASK, | ||
| 1282 | .ev_count = MMA8452_FF_MT_COUNT, | ||
| 1283 | }, | 1344 | }, |
| 1284 | [mma8653] = { | 1345 | [mma8653] = { |
| 1285 | .chip_id = MMA8653_DEVICE_ID, | 1346 | .chip_id = MMA8653_DEVICE_ID, |
| 1286 | .channels = mma8653_channels, | 1347 | .channels = mma8653_channels, |
| 1287 | .num_channels = ARRAY_SIZE(mma8653_channels), | 1348 | .num_channels = ARRAY_SIZE(mma8653_channels), |
| 1288 | .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, | 1349 | .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, |
| 1289 | .ev_cfg = MMA8452_FF_MT_CFG, | 1350 | /* |
| 1290 | .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE, | 1351 | * Although we enable the interrupt sources once and for |
| 1291 | .ev_cfg_chan_shift = 3, | 1352 | * all here the event detection itself is not enabled until |
| 1292 | .ev_src = MMA8452_FF_MT_SRC, | 1353 | * userspace asks for it by mma8452_write_event_config() |
| 1293 | .ev_src_xe = MMA8452_FF_MT_SRC_XHE, | 1354 | */ |
| 1294 | .ev_src_ye = MMA8452_FF_MT_SRC_YHE, | 1355 | .all_events = MMA8452_INT_DRDY | |
| 1295 | .ev_src_ze = MMA8452_FF_MT_SRC_ZHE, | 1356 | MMA8452_INT_FF_MT, |
| 1296 | .ev_ths = MMA8452_FF_MT_THS, | 1357 | .enabled_events = MMA8452_INT_FF_MT, |
| 1297 | .ev_ths_mask = MMA8452_FF_MT_THS_MASK, | ||
| 1298 | .ev_count = MMA8452_FF_MT_COUNT, | ||
| 1299 | }, | 1358 | }, |
| 1300 | [fxls8471] = { | 1359 | [fxls8471] = { |
| 1301 | .chip_id = FXLS8471_DEVICE_ID, | 1360 | .chip_id = FXLS8471_DEVICE_ID, |
| 1302 | .channels = mma8451_channels, | 1361 | .channels = mma8451_channels, |
| 1303 | .num_channels = ARRAY_SIZE(mma8451_channels), | 1362 | .num_channels = ARRAY_SIZE(mma8451_channels), |
| 1304 | .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, | 1363 | .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, |
| 1305 | .ev_cfg = MMA8452_TRANSIENT_CFG, | 1364 | /* |
| 1306 | .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE, | 1365 | * Although we enable the interrupt sources once and for |
| 1307 | .ev_cfg_chan_shift = 1, | 1366 | * all here the event detection itself is not enabled until |
| 1308 | .ev_src = MMA8452_TRANSIENT_SRC, | 1367 | * userspace asks for it by mma8452_write_event_config() |
| 1309 | .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE, | 1368 | */ |
| 1310 | .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE, | 1369 | .all_events = MMA8452_INT_DRDY | |
| 1311 | .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE, | 1370 | MMA8452_INT_TRANS | |
| 1312 | .ev_ths = MMA8452_TRANSIENT_THS, | 1371 | MMA8452_INT_FF_MT, |
| 1313 | .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK, | 1372 | .enabled_events = MMA8452_INT_TRANS | |
| 1314 | .ev_count = MMA8452_TRANSIENT_COUNT, | 1373 | MMA8452_INT_FF_MT, |
| 1315 | }, | 1374 | }, |
| 1316 | }; | 1375 | }; |
| 1317 | 1376 | ||
| @@ -1332,12 +1391,11 @@ static const struct iio_info mma8452_info = { · 14 unmodified lines | |||
| 1332 | .read_raw = &mma8452_read_raw, | 1391 | .read_raw = &mma8452_read_raw, |
| 1333 | .write_raw = &mma8452_write_raw, | 1392 | .write_raw = &mma8452_write_raw, |
| 1334 | .event_attrs = &mma8452_event_attribute_group, | 1393 | .event_attrs = &mma8452_event_attribute_group, |
| 1335 | .read_event_value = &mma8452_read_thresh, | 1394 | .read_event_value = &mma8452_read_event_value, |
| 1336 | .write_event_value = &mma8452_write_thresh, | 1395 | .write_event_value = &mma8452_write_event_value, |
| 1337 | .read_event_config = &mma8452_read_event_config, | 1396 | .read_event_config = &mma8452_read_event_config, |
| 1338 | .write_event_config = &mma8452_write_event_config, | 1397 | .write_event_config = &mma8452_write_event_config, |
| 1339 | .debugfs_reg_access = &mma8452_reg_access_dbg, | 1398 | .debugfs_reg_access = &mma8452_reg_access_dbg, |
| 1340 | .driver_module = THIS_MODULE, | ||
| 1341 | }; | 1399 | }; |
| 1342 | 1400 | ||
| 1343 | static const unsigned long mma8452_scan_masks[] = {0x7, 0}; | 1401 | static const unsigned long mma8452_scan_masks[] = {0x7, 0}; |
| @@ -1368,7 +1426,6 @@ static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig, · 24 unmodified lines | |||
| 1368 | static const struct iio_trigger_ops mma8452_trigger_ops = { | 1426 | static const struct iio_trigger_ops mma8452_trigger_ops = { |
| 1369 | .set_trigger_state = mma8452_data_rdy_trigger_set_state, | 1427 | .set_trigger_state = mma8452_data_rdy_trigger_set_state, |
| 1370 | .validate_device = iio_trigger_validate_own_device, | 1428 | .validate_device = iio_trigger_validate_own_device, |
| 1371 | .owner = THIS_MODULE, | ||
| 1372 | }; | 1429 | }; |
| 1373 | 1430 | ||
| 1374 | static int mma8452_trigger_setup(struct iio_dev *indio_dev) | 1431 | static int mma8452_trigger_setup(struct iio_dev *indio_dev) |
| @@ -1509,16 +1566,6 @@ static int mma8452_probe(struct i2c_client *client, · 134 unmodified lines | |||
| 1509 | return ret; | 1566 | return ret; |
| 1510 | 1567 | ||
| 1511 | if (client->irq) { | 1568 | if (client->irq) { |
| 1512 | /* | ||
| 1513 | * Although we enable the interrupt sources once and for | ||
| 1514 | * all here the event detection itself is not enabled until | ||
| 1515 | * userspace asks for it by mma8452_write_event_config() | ||
| 1516 | */ | ||
| 1517 | int supported_interrupts = MMA8452_INT_DRDY | | ||
| 1518 | MMA8452_INT_TRANS | | ||
| 1519 | MMA8452_INT_FF_MT; | ||
| 1520 | int enabled_interrupts = MMA8452_INT_TRANS | | ||
| 1521 | MMA8452_INT_FF_MT; | ||
| 1522 | int irq2; | 1569 | int irq2; |
| 1523 | 1570 | ||
| 1524 | irq2 = of_irq_get_byname(client->dev.of_node, "INT2"); | 1571 | irq2 = of_irq_get_byname(client->dev.of_node, "INT2"); |
| @@ -1527,8 +1574,8 @@ static int mma8452_probe(struct i2c_client *client, · 2 unmodified lines | |||
| 1527 | dev_dbg(&client->dev, "using interrupt line INT2\n"); | 1574 | dev_dbg(&client->dev, "using interrupt line INT2\n"); |
| 1528 | } else { | 1575 | } else { |
| 1529 | ret = i2c_smbus_write_byte_data(client, | 1576 | ret = i2c_smbus_write_byte_data(client, |
| 1530 | MMA8452_CTRL_REG5, | 1577 | MMA8452_CTRL_REG5, |
| 1531 | supported_interrupts); | 1578 | data->chip_info->all_events); |
| 1532 | if (ret < 0) | 1579 | if (ret < 0) |
| 1533 | return ret; | 1580 | return ret; |
| 1534 | 1581 | ||
| @@ -1536,8 +1583,8 @@ static int mma8452_probe(struct i2c_client *client, · 1 unmodified line | |||
| 1536 | } | 1583 | } |
| 1537 | 1584 | ||
| 1538 | ret = i2c_smbus_write_byte_data(client, | 1585 | ret = i2c_smbus_write_byte_data(client, |
| 1539 | MMA8452_CTRL_REG4, | 1586 | MMA8452_CTRL_REG4, |
| 1540 | enabled_interrupts); | 1587 | data->chip_info->enabled_events); |
| 1541 | if (ret < 0) | 1588 | if (ret < 0) |
| 1542 | return ret; | 1589 | return ret; |
| 1543 | 1590 | ||
| @@ -332,7 +332,6 @@ static const struct iio_chan_spec mma9551_channels[] = { · 331 unmodified lines | |||
| 332 | }; | 332 | }; |
| 333 | 333 | ||
| 334 | static const struct iio_info mma9551_info = { | 334 | static const struct iio_info mma9551_info = { |
| 335 | .driver_module = THIS_MODULE, | ||
| 336 | .read_raw = mma9551_read_raw, | 335 | .read_raw = mma9551_read_raw, |
| 337 | .read_event_config = mma9551_read_event_config, | 336 | .read_event_config = mma9551_read_event_config, |
| 338 | .write_event_config = mma9551_write_event_config, | 337 | .write_event_config = mma9551_write_event_config, |
| @@ -987,7 +987,6 @@ static const struct iio_chan_spec mma9553_channels[] = { · 986 unmodified lines | |||
| 987 | }; | 987 | }; |
| 988 | 988 | ||
| 989 | static const struct iio_info mma9553_info = { | 989 | static const struct iio_info mma9553_info = { |
| 990 | .driver_module = THIS_MODULE, | ||
| 991 | .read_raw = mma9553_read_raw, | 990 | .read_raw = mma9553_read_raw, |
| 992 | .write_raw = mma9553_write_raw, | 991 | .write_raw = mma9553_write_raw, |
| 993 | .read_event_config = mma9553_read_event_config, | 992 | .read_event_config = mma9553_read_event_config, |
| @@ -264,7 +264,6 @@ static int mxc4005_write_raw(struct iio_dev *indio_dev, · 263 unmodified lines | |||
| 264 | } | 264 | } |
| 265 | 265 | ||
| 266 | static const struct iio_info mxc4005_info = { | 266 | static const struct iio_info mxc4005_info = { |
| 267 | .driver_module = THIS_MODULE, | ||
| 268 | .read_raw = mxc4005_read_raw, | 267 | .read_raw = mxc4005_read_raw, |
| 269 | .write_raw = mxc4005_write_raw, | 268 | .write_raw = mxc4005_write_raw, |
| 270 | .attrs = &mxc4005_attrs_group, | 269 | .attrs = &mxc4005_attrs_group, |
| @@ -376,7 +375,6 @@ static int mxc4005_trigger_try_reen(struct iio_trigger *trig) · 105 unmodified lines | |||
| 376 | static const struct iio_trigger_ops mxc4005_trigger_ops = { | 375 | static const struct iio_trigger_ops mxc4005_trigger_ops = { |
| 377 | .set_trigger_state = mxc4005_set_trigger_state, | 376 | .set_trigger_state = mxc4005_set_trigger_state, |
| 378 | .try_reenable = mxc4005_trigger_try_reen, | 377 | .try_reenable = mxc4005_trigger_try_reen, |
| 379 | .owner = THIS_MODULE, | ||
| 380 | }; | 378 | }; |
| 381 | 379 | ||
| 382 | static int mxc4005_chip_init(struct mxc4005_data *data) | 380 | static int mxc4005_chip_init(struct mxc4005_data *data) |
| @@ -78,7 +78,6 @@ static int mxc6255_read_raw(struct iio_dev *indio_dev, · 77 unmodified lines | |||
| 78 | } | 78 | } |
| 79 | 79 | ||
| 80 | static const struct iio_info mxc6255_info = { | 80 | static const struct iio_info mxc6255_info = { |
| 81 | .driver_module = THIS_MODULE, | ||
| 82 | .read_raw = mxc6255_read_raw, | 81 | .read_raw = mxc6255_read_raw, |
| 83 | }; | 82 | }; |
| 84 | 83 | ||
| @@ -1454,7 +1454,6 @@ static const struct iio_info sca3000_info = { · 1453 unmodified lines | |||
| 1454 | .write_event_value = &sca3000_write_event_value, | 1454 | .write_event_value = &sca3000_write_event_value, |
| 1455 | .read_event_config = &sca3000_read_event_config, | 1455 | .read_event_config = &sca3000_read_event_config, |
| 1456 | .write_event_config = &sca3000_write_event_config, | 1456 | .write_event_config = &sca3000_write_event_config, |
| 1457 | .driver_module = THIS_MODULE, | ||
| 1458 | }; | 1457 | }; |
| 1459 | 1458 | ||
| 1460 | static int sca3000_probe(struct spi_device *spi) | 1459 | static int sca3000_probe(struct spi_device *spi) |
| @@ -32,6 +32,8 @@ enum st_accel_type { · 31 unmodified lines | |||
| 32 | H3LIS331DL, | 32 | H3LIS331DL, |
| 33 | LIS331DL, | 33 | LIS331DL, |
| 34 | LIS3LV02DL, | 34 | LIS3LV02DL, |
| 35 | LIS2DW12, | ||
| 36 | LIS3DHH, | ||
| 35 | ST_ACCEL_MAX, | 37 | ST_ACCEL_MAX, |
| 36 | }; | 38 | }; |
| 37 | 39 | ||
| @@ -52,6 +54,8 @@ enum st_accel_type { · 14 unmodified lines | |||
| 52 | #define LIS2DH12_ACCEL_DEV_NAME "lis2dh12_accel" | 54 | #define LIS2DH12_ACCEL_DEV_NAME "lis2dh12_accel" |
| 53 | #define LIS3L02DQ_ACCEL_DEV_NAME "lis3l02dq" | 55 | #define LIS3L02DQ_ACCEL_DEV_NAME "lis3l02dq" |
| 54 | #define LNG2DM_ACCEL_DEV_NAME "lng2dm" | 56 | #define LNG2DM_ACCEL_DEV_NAME "lng2dm" |
| 57 | #define LIS2DW12_ACCEL_DEV_NAME "lis2dw12" | ||
| 58 | #define LIS3DHH_ACCEL_DEV_NAME "lis3dhh" | ||
| 55 | 59 | ||
| 56 | /** | 60 | /** |
| 57 | * struct st_sensors_platform_data - default accel platform data | 61 | * struct st_sensors_platform_data - default accel platform data |
| @@ -159,12 +159,16 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = { · 158 unmodified lines | |||
| 159 | .mask = 0x80, | 159 | .mask = 0x80, |
| 160 | }, | 160 | }, |
| 161 | .drdy_irq = { | 161 | .drdy_irq = { |
| 162 | .addr = 0x22, | 162 | .int1 = { |
| 163 | .mask_int1 = 0x10, | 163 | .addr = 0x22, |
| 164 | .mask_int2 = 0x00, | 164 | .mask = 0x10, |
| 165 | }, | ||
| 165 | .addr_ihl = 0x25, | 166 | .addr_ihl = 0x25, |
| 166 | .mask_ihl = 0x02, | 167 | .mask_ihl = 0x02, |
| 167 | .addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR, | 168 | .stat_drdy = { |
| 169 | .addr = ST_SENSORS_DEFAULT_STAT_ADDR, | ||
| 170 | .mask = 0x07, | ||
| 171 | }, | ||
| 168 | }, | 172 | }, |
| 169 | .sim = { | 173 | .sim = { |
| 170 | .addr = 0x23, | 174 | .addr = 0x23, |
| @@ -229,14 +233,24 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = { · 58 unmodified lines | |||
| 229 | .mask = 0x80, | 233 | .mask = 0x80, |
| 230 | }, | 234 | }, |
| 231 | .drdy_irq = { | 235 | .drdy_irq = { |
| 232 | .addr = 0x22, | 236 | .int1 = { |
| 233 | .mask_int1 = 0x02, | 237 | .addr = 0x22, |
| 234 | .mask_int2 = 0x10, | 238 | .mask = 0x02, |
| 239 | .addr_od = 0x22, | ||
| 240 | .mask_od = 0x40, | ||
| 241 | }, | ||
| 242 | .int2 = { | ||
| 243 | .addr = 0x22, | ||
| 244 | .mask = 0x10, | ||
| 245 | .addr_od = 0x22, | ||
| 246 | .mask_od = 0x40, | ||
| 247 | }, | ||
| 235 | .addr_ihl = 0x22, | 248 | .addr_ihl = 0x22, |
| 236 | .mask_ihl = 0x80, | 249 | .mask_ihl = 0x80, |
| 237 | .addr_od = 0x22, | 250 | .stat_drdy = { |
| 238 | .mask_od = 0x40, | 251 | .addr = ST_SENSORS_DEFAULT_STAT_ADDR, |
| 239 | .addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR, | 252 | .mask = 0x07, |
| 253 | }, | ||
| 240 | }, | 254 | }, |
| 241 | .sim = { | 255 | .sim = { |
| 242 | .addr = 0x23, | 256 | .addr = 0x23, |
| @@ -313,12 +327,16 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = { · 70 unmodified lines | |||
| 313 | .mask = 0x08, | 327 | .mask = 0x08, |
| 314 | }, | 328 | }, |
| 315 | .drdy_irq = { | 329 | .drdy_irq = { |
| 316 | .addr = 0x23, | 330 | .int1 = { |
| 317 | .mask_int1 = 0x80, | 331 | .addr = 0x23, |
| 318 | .mask_int2 = 0x00, | 332 | .mask = 0x80, |
| 333 | }, | ||
| 319 | .addr_ihl = 0x23, | 334 | .addr_ihl = 0x23, |
| 320 | .mask_ihl = 0x40, | 335 | .mask_ihl = 0x40, |
| 321 | .addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR, | 336 | .stat_drdy = { |
| 337 | .addr = ST_SENSORS_DEFAULT_STAT_ADDR, | ||
| 338 | .mask = 0x07, | ||
| 339 | }, | ||
| 322 | .ig1 = { | 340 | .ig1 = { |
| 323 | .en_addr = 0x23, | 341 | .en_addr = 0x23, |
| 324 | .en_mask = 0x08, | 342 | .en_mask = 0x08, |
| @@ -387,9 +405,14 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = { · 62 unmodified lines | |||
| 387 | .mask = 0x01, | 405 | .mask = 0x01, |
| 388 | }, | 406 | }, |
| 389 | .drdy_irq = { | 407 | .drdy_irq = { |
| 390 | .addr = 0x21, | 408 | .int1 = { |
| 391 | .mask_int1 = 0x04, | 409 | .addr = 0x21, |
| 392 | .addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR, | 410 | .mask = 0x04, |
| 411 | }, | ||
| 412 | .stat_drdy = { | ||
| 413 | .addr = ST_SENSORS_DEFAULT_STAT_ADDR, | ||
| 414 | .mask = 0x07, | ||
| 415 | }, | ||
| 393 | }, | 416 | }, |
| 394 | .sim = { | 417 | .sim = { |
| 395 | .addr = 0x21, | 418 | .addr = 0x21, |
| @@ -444,14 +467,24 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = { · 48 unmodified lines | |||
| 444 | }, | 467 | }, |
| 445 | }, | 468 | }, |
| 446 | .drdy_irq = { | 469 | .drdy_irq = { |
| 447 | .addr = 0x22, | 470 | .int1 = { |
| 448 | .mask_int1 = 0x04, | 471 | .addr = 0x22, |
| 449 | .mask_int2 = 0x20, | 472 | .mask = 0x04, |
| 473 | .addr_od = 0x22, | ||
| 474 | .mask_od = 0x40, | ||
| 475 | }, | ||
| 476 | .int2 = { | ||
| 477 | .addr = 0x22, | ||
| 478 | .mask = 0x20, | ||
| 479 | .addr_od = 0x22, | ||
| 480 | .mask_od = 0x40, | ||
| 481 | }, | ||
| 450 | .addr_ihl = 0x22, | 482 | .addr_ihl = 0x22, |
| 451 | .mask_ihl = 0x80, | 483 | .mask_ihl = 0x80, |
| 452 | .addr_od = 0x22, | 484 | .stat_drdy = { |
| 453 | .mask_od = 0x40, | 485 | .addr = ST_SENSORS_DEFAULT_STAT_ADDR, |
| 454 | .addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR, | 486 | .mask = 0x07, |
| 487 | }, | ||
| 455 | }, | 488 | }, |
| 456 | .sim = { | 489 | .sim = { |
| 457 | .addr = 0x21, | 490 | .addr = 0x21, |
| @@ -513,9 +546,14 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = { · 55 unmodified lines | |||
| 513 | .mask = 0x80, | 546 | .mask = 0x80, |
| 514 | }, | 547 | }, |
| 515 | .drdy_irq = { | 548 | .drdy_irq = { |
| 516 | .addr = 0x22, | 549 | .int1 = { |
| 517 | .mask_int1 = 0x02, | 550 | .addr = 0x22, |
| 518 | .mask_int2 = 0x10, | 551 | .mask = 0x02, |
| 552 | }, | ||
| 553 | .int2 = { | ||
| 554 | .addr = 0x22, | ||
| 555 | .mask = 0x10, | ||
| 556 | }, | ||
| 519 | .addr_ihl = 0x22, | 557 | .addr_ihl = 0x22, |
| 520 | .mask_ihl = 0x80, | 558 | .mask_ihl = 0x80, |
| 521 | }, | 559 | }, |
| @@ -567,9 +605,14 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = { · 45 unmodified lines | |||
| 567 | .bdu = { | 605 | .bdu = { |
| 568 | }, | 606 | }, |
| 569 | .drdy_irq = { | 607 | .drdy_irq = { |
| 570 | .addr = 0x21, | 608 | .int1 = { |
| 571 | .mask_int1 = 0x04, | 609 | .addr = 0x21, |
| 572 | .addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR, | 610 | .mask = 0x04, |
| 611 | }, | ||
| 612 | .stat_drdy = { | ||
| 613 | .addr = ST_SENSORS_DEFAULT_STAT_ADDR, | ||
| 614 | .mask = 0x07, | ||
| 615 | }, | ||
| 573 | }, | 616 | }, |
| 574 | .sim = { | 617 | .sim = { |
| 575 | .addr = 0x21, | 618 | .addr = 0x21, |
| @@ -635,12 +678,16 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = { · 59 unmodified lines | |||
| 635 | }, | 678 | }, |
| 636 | }, | 679 | }, |
| 637 | .drdy_irq = { | 680 | .drdy_irq = { |
| 638 | .addr = 0x22, | 681 | .int1 = { |
| 639 | .mask_int1 = 0x10, | 682 | .addr = 0x22, |
| 640 | .mask_int2 = 0x00, | 683 | .mask = 0x10, |
| 684 | }, | ||
| 641 | .addr_ihl = 0x25, | 685 | .addr_ihl = 0x25, |
| 642 | .mask_ihl = 0x02, | 686 | .mask_ihl = 0x02, |
| 643 | .addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR, | 687 | .stat_drdy = { |
| 688 | .addr = ST_SENSORS_DEFAULT_STAT_ADDR, | ||
| 689 | .mask = 0x07, | ||
| 690 | }, | ||
| 644 | }, | 691 | }, |
| 645 | .sim = { | 692 | .sim = { |
| 646 | .addr = 0x23, | 693 | .addr = 0x23, |
| @@ -649,6 +696,139 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = { · 2 unmodified lines | |||
| 649 | .multi_read_bit = true, | 696 | .multi_read_bit = true, |
| 650 | .bootime = 2, | 697 | .bootime = 2, |
| 651 | }, | 698 | }, |
| 699 | { | ||
| 700 | .wai = 0x44, | ||
| 701 | .wai_addr = ST_SENSORS_DEFAULT_WAI_ADDRESS, | ||
| 702 | .sensors_supported = { | ||
| 703 | [0] = LIS2DW12_ACCEL_DEV_NAME, | ||
| 704 | }, | ||
| 705 | .ch = (struct iio_chan_spec *)st_accel_12bit_channels, | ||
| 706 | .odr = { | ||
| 707 | .addr = 0x20, | ||
| 708 | .mask = 0xf0, | ||
| 709 | .odr_avl = { | ||
| 710 | { .hz = 1, .value = 0x01, }, | ||
| 711 | { .hz = 12, .value = 0x02, }, | ||
| 712 | { .hz = 25, .value = 0x03, }, | ||
| 713 | { .hz = 50, .value = 0x04, }, | ||
| 714 | { .hz = 100, .value = 0x05, }, | ||
| 715 | { .hz = 200, .value = 0x06, }, | ||
| 716 | }, | ||
| 717 | }, | ||
| 718 | .pw = { | ||
| 719 | .addr = 0x20, | ||
| 720 | .mask = 0xf0, | ||
| 721 | .value_off = ST_SENSORS_DEFAULT_POWER_OFF_VALUE, | ||
| 722 | }, | ||
| 723 | .fs = { | ||
| 724 | .addr = 0x25, | ||
| 725 | .mask = 0x30, | ||
| 726 | .fs_avl = { | ||
| 727 | [0] = { | ||
| 728 | .num = ST_ACCEL_FS_AVL_2G, | ||
| 729 | .value = 0x00, | ||
| 730 | .gain = IIO_G_TO_M_S_2(976), | ||
| 731 | }, | ||
| 732 | [1] = { | ||
| 733 | .num = ST_ACCEL_FS_AVL_4G, | ||
| 734 | .value = 0x01, | ||
| 735 | .gain = IIO_G_TO_M_S_2(1952), | ||
| 736 | }, | ||
| 737 | [2] = { | ||
| 738 | .num = ST_ACCEL_FS_AVL_8G, | ||
| 739 | .value = 0x02, | ||
| 740 | .gain = IIO_G_TO_M_S_2(3904), | ||
| 741 | }, | ||
| 742 | [3] = { | ||
| 743 | .num = ST_ACCEL_FS_AVL_16G, | ||
| 744 | .value = 0x03, | ||
| 745 | .gain = IIO_G_TO_M_S_2(7808), | ||
| 746 | }, | ||
| 747 | }, | ||
| 748 | }, | ||
| 749 | .bdu = { | ||
| 750 | .addr = 0x21, | ||
| 751 | .mask = 0x08, | ||
| 752 | }, | ||
| 753 | .drdy_irq = { | ||
| 754 | .int1 = { | ||
| 755 | .addr = 0x23, | ||
| 756 | .mask = 0x01, | ||
| 757 | .addr_od = 0x22, | ||
| 758 | .mask_od = 0x20, | ||
| 759 | }, | ||
| 760 | .int2 = { | ||
| 761 | .addr = 0x24, | ||
| 762 | .mask = 0x01, | ||
| 763 | .addr_od = 0x22, | ||
| 764 | .mask_od = 0x20, | ||
| 765 | }, | ||
| 766 | .addr_ihl = 0x22, | ||
| 767 | .mask_ihl = 0x08, | ||
| 768 | .stat_drdy = { | ||
| 769 | .addr = ST_SENSORS_DEFAULT_STAT_ADDR, | ||
| 770 | .mask = 0x01, | ||
| 771 | }, | ||
| 772 | }, | ||
| 773 | .sim = { | ||
| 774 | .addr = 0x21, | ||
| 775 | .value = BIT(0), | ||
| 776 | }, | ||
| 777 | .multi_read_bit = false, | ||
| 778 | .bootime = 2, | ||
| 779 | }, | ||
| 780 | { | ||
| 781 | .wai = 0x11, | ||
| 782 | .wai_addr = ST_SENSORS_DEFAULT_WAI_ADDRESS, | ||
| 783 | .sensors_supported = { | ||
| 784 | [0] = LIS3DHH_ACCEL_DEV_NAME, | ||
| 785 | }, | ||
| 786 | .ch = (struct iio_chan_spec *)st_accel_16bit_channels, | ||
| 787 | .odr = { | ||
| 788 | /* just ODR = 1100Hz available */ | ||
| 789 | .odr_avl = { | ||
| 790 | { .hz = 1100, .value = 0x00, }, | ||
| 791 | }, | ||
| 792 | }, | ||
| 793 | .pw = { | ||
| 794 | .addr = 0x20, | ||
| 795 | .mask = 0x80, | ||
| 796 | .value_on = ST_SENSORS_DEFAULT_POWER_ON_VALUE, | ||
| 797 | .value_off = ST_SENSORS_DEFAULT_POWER_OFF_VALUE, | ||
| 798 | }, | ||
| 799 | .fs = { | ||
| 800 | .fs_avl = { | ||
| 801 | [0] = { | ||
| 802 | .num = ST_ACCEL_FS_AVL_2G, | ||
| 803 | .gain = IIO_G_TO_M_S_2(76), | ||
| 804 | }, | ||
| 805 | }, | ||
| 806 | }, | ||
| 807 | .bdu = { | ||
| 808 | .addr = 0x20, | ||
| 809 | .mask = 0x01, | ||
| 810 | }, | ||
| 811 | .drdy_irq = { | ||
| 812 | .int1 = { | ||
| 813 | .addr = 0x21, | ||
| 814 | .mask = 0x80, | ||
| 815 | .addr_od = 0x23, | ||
| 816 | .mask_od = 0x04, | ||
| 817 | }, | ||
| 818 | .int2 = { | ||
| 819 | .addr = 0x22, | ||
| 820 | .mask = 0x80, | ||
| 821 | .addr_od = 0x23, | ||
| 822 | .mask_od = 0x08, | ||
| 823 | }, | ||
| 824 | .stat_drdy = { | ||
| 825 | .addr = ST_SENSORS_DEFAULT_STAT_ADDR, | ||
| 826 | .mask = 0x07, | ||
| 827 | }, | ||
| 828 | }, | ||
| 829 | .multi_read_bit = false, | ||
| 830 | .bootime = 2, | ||
| 831 | }, | ||
| 652 | }; | 832 | }; |
| 653 | 833 | ||
| 654 | static int st_accel_read_raw(struct iio_dev *indio_dev, | 834 | static int st_accel_read_raw(struct iio_dev *indio_dev, |
| @@ -721,7 +901,6 @@ static const struct attribute_group st_accel_attribute_group = { · 66 unmodified lines | |||
| 721 | }; | 901 | }; |
| 722 | 902 | ||
| 723 | static const struct iio_info accel_info = { | 903 | static const struct iio_info accel_info = { |
| 724 | .driver_module = THIS_MODULE, | ||
| 725 | .attrs = &st_accel_attribute_group, | 904 | .attrs = &st_accel_attribute_group, |
| 726 | .read_raw = &st_accel_read_raw, | 905 | .read_raw = &st_accel_read_raw, |
| 727 | .write_raw = &st_accel_write_raw, | 906 | .write_raw = &st_accel_write_raw, |
| @@ -730,7 +909,6 @@ static const struct iio_info accel_info = { · 2 unmodified lines | |||
| 730 | 909 | ||
| 731 | #ifdef CONFIG_IIO_TRIGGER | 910 | #ifdef CONFIG_IIO_TRIGGER |
| 732 | static const struct iio_trigger_ops st_accel_trigger_ops = { | 911 | static const struct iio_trigger_ops st_accel_trigger_ops = { |
| 733 | .owner = THIS_MODULE, | ||
| 734 | .set_trigger_state = ST_ACCEL_TRIGGER_SET_STATE, | 912 | .set_trigger_state = ST_ACCEL_TRIGGER_SET_STATE, |
| 735 | .validate_device = st_sensors_validate_device, | 913 | .validate_device = st_sensors_validate_device, |
| 736 | }; | 914 | }; |
| @@ -94,6 +94,10 @@ static const struct of_device_id st_accel_of_match[] = { · 93 unmodified lines | |||
| 94 | .compatible = "st,lng2dm-accel", | 94 | .compatible = "st,lng2dm-accel", |
| 95 | .data = LNG2DM_ACCEL_DEV_NAME, | 95 | .data = LNG2DM_ACCEL_DEV_NAME, |
| 96 | }, | 96 | }, |
| 97 | { | ||
| 98 | .compatible = "st,lis2dw12", | ||
| 99 | .data = LIS2DW12_ACCEL_DEV_NAME, | ||
| 100 | }, | ||
| 97 | {}, | 101 | {}, |
| 98 | }; | 102 | }; |
| 99 | MODULE_DEVICE_TABLE(of, st_accel_of_match); | 103 | MODULE_DEVICE_TABLE(of, st_accel_of_match); |
| @@ -129,6 +133,7 @@ static const struct i2c_device_id st_accel_id_table[] = { · 29 unmodified lines | |||
| 129 | { H3LIS331DL_ACCEL_DEV_NAME, H3LIS331DL }, | 133 | { H3LIS331DL_ACCEL_DEV_NAME, H3LIS331DL }, |
| 130 | { LIS331DL_ACCEL_DEV_NAME, LIS331DL }, | 134 | { LIS331DL_ACCEL_DEV_NAME, LIS331DL }, |
| 131 | { LIS3LV02DL_ACCEL_DEV_NAME, LIS3LV02DL }, | 135 | { LIS3LV02DL_ACCEL_DEV_NAME, LIS3LV02DL }, |
| 136 | { LIS2DW12_ACCEL_DEV_NAME, LIS2DW12 }, | ||
| 132 | {}, | 137 | {}, |
| 133 | }; | 138 | }; |
| 134 | MODULE_DEVICE_TABLE(i2c, st_accel_id_table); | 139 | MODULE_DEVICE_TABLE(i2c, st_accel_id_table); |
| @@ -82,6 +82,14 @@ static const struct of_device_id st_accel_of_match[] = { · 81 unmodified lines | |||
| 82 | .compatible = "st,lis331dl-accel", | 82 | .compatible = "st,lis331dl-accel", |
| 83 | .data = LIS331DL_ACCEL_DEV_NAME, | 83 | .data = LIS331DL_ACCEL_DEV_NAME, |
| 84 | }, | 84 | }, |
| 85 | { | ||
| 86 | .compatible = "st,lis2dw12", | ||
| 87 | .data = LIS2DW12_ACCEL_DEV_NAME, | ||
| 88 | }, | ||
| 89 | { | ||
| 90 | .compatible = "st,lis3dhh", | ||
| 91 | .data = LIS3DHH_ACCEL_DEV_NAME, | ||
| 92 | }, | ||
| 85 | {} | 93 | {} |
| 86 | }; | 94 | }; |
| 87 | MODULE_DEVICE_TABLE(of, st_accel_of_match); | 95 | MODULE_DEVICE_TABLE(of, st_accel_of_match); |
| @@ -133,6 +141,8 @@ static const struct spi_device_id st_accel_id_table[] = { · 45 unmodified lines | |||
| 133 | { H3LIS331DL_ACCEL_DEV_NAME }, | 141 | { H3LIS331DL_ACCEL_DEV_NAME }, |
| 134 | { LIS331DL_ACCEL_DEV_NAME }, | 142 | { LIS331DL_ACCEL_DEV_NAME }, |
| 135 | { LIS3LV02DL_ACCEL_DEV_NAME }, | 143 | { LIS3LV02DL_ACCEL_DEV_NAME }, |
| 144 | { LIS2DW12_ACCEL_DEV_NAME }, | ||
| 145 | { LIS3DHH_ACCEL_DEV_NAME }, | ||
| 136 | {}, | 146 | {}, |
| 137 | }; | 147 | }; |
| 138 | MODULE_DEVICE_TABLE(spi, st_accel_id_table); | 148 | MODULE_DEVICE_TABLE(spi, st_accel_id_table); |
| @@ -237,7 +237,6 @@ static int stk8312_data_rdy_trigger_set_state(struct iio_trigger *trig, · 236 unmodified lines | |||
| 237 | 237 | ||
| 238 | static const struct iio_trigger_ops stk8312_trigger_ops = { | 238 | static const struct iio_trigger_ops stk8312_trigger_ops = { |
| 239 | .set_trigger_state = stk8312_data_rdy_trigger_set_state, | 239 | .set_trigger_state = stk8312_data_rdy_trigger_set_state, |
| 240 | .owner = THIS_MODULE, | ||
| 241 | }; | 240 | }; |
| 242 | 241 | ||
| 243 | static int stk8312_set_sample_rate(struct stk8312_data *data, u8 rate) | 242 | static int stk8312_set_sample_rate(struct stk8312_data *data, u8 rate) |
| @@ -421,7 +420,6 @@ static int stk8312_write_raw(struct iio_dev *indio_dev, · 177 unmodified lines | |||
| 421 | } | 420 | } |
| 422 | 421 | ||
| 423 | static const struct iio_info stk8312_info = { | 422 | static const struct iio_info stk8312_info = { |
| 424 | .driver_module = THIS_MODULE, | ||
| 425 | .read_raw = stk8312_read_raw, | 423 | .read_raw = stk8312_read_raw, |
| 426 | .write_raw = stk8312_write_raw, | 424 | .write_raw = stk8312_write_raw, |
| 427 | .attrs = &stk8312_attribute_group, | 425 | .attrs = &stk8312_attribute_group, |
| @@ -179,7 +179,6 @@ static int stk8ba50_data_rdy_trigger_set_state(struct iio_trigger *trig, · 178 unmodified lines | |||
| 179 | 179 | ||
| 180 | static const struct iio_trigger_ops stk8ba50_trigger_ops = { | 180 | static const struct iio_trigger_ops stk8ba50_trigger_ops = { |
| 181 | .set_trigger_state = stk8ba50_data_rdy_trigger_set_state, | 181 | .set_trigger_state = stk8ba50_data_rdy_trigger_set_state, |
| 182 | .owner = THIS_MODULE, | ||
| 183 | }; | 182 | }; |
| 184 | 183 | ||
| 185 | static int stk8ba50_set_power(struct stk8ba50_data *data, bool mode) | 184 | static int stk8ba50_set_power(struct stk8ba50_data *data, bool mode) |
| @@ -307,7 +306,6 @@ static int stk8ba50_write_raw(struct iio_dev *indio_dev, · 121 unmodified lines | |||
| 307 | } | 306 | } |
| 308 | 307 | ||
| 309 | static const struct iio_info stk8ba50_info = { | 308 | static const struct iio_info stk8ba50_info = { |
| 310 | .driver_module = THIS_MODULE, | ||
| 311 | .read_raw = stk8ba50_read_raw, | 309 | .read_raw = stk8ba50_read_raw, |
| 312 | .write_raw = stk8ba50_write_raw, | 310 | .write_raw = stk8ba50_write_raw, |
| 313 | .attrs = &stk8ba50_attribute_group, | 311 | .attrs = &stk8ba50_attribute_group, |
| @@ -477,12 +477,13 @@ config MAX9611 · 476 unmodified lines | |||
| 477 | called max9611. | 477 | called max9611. |
| 478 | 478 | ||
| 479 | config MCP320X | 479 | config MCP320X |
| 480 | tristate "Microchip Technology MCP3x01/02/04/08" | 480 | tristate "Microchip Technology MCP3x01/02/04/08 and MCP3550/1/3" |
| 481 | depends on SPI | 481 | depends on SPI |
| 482 | help | 482 | help |
| 483 | Say yes here to build support for Microchip Technology's | 483 | Say yes here to build support for Microchip Technology's |
| 484 | MCP3001, MCP3002, MCP3004, MCP3008, MCP3201, MCP3202, MCP3204, | 484 | MCP3001, MCP3002, MCP3004, MCP3008, MCP3201, MCP3202, MCP3204, |
| 485 | MCP3208 or MCP3301 analog to digital converter. | 485 | MCP3208, MCP3301, MCP3550, MCP3551 and MCP3553 analog to digital |
| 486 | converters. | ||
| 486 | 487 | ||
| 487 | This driver can also be built as a module. If so, the module will be | 488 | This driver can also be built as a module. If so, the module will be |
| 488 | called mcp320x. | 489 | called mcp320x. |
| @@ -595,7 +596,7 @@ config QCOM_SPMI_VADC · 106 unmodified lines | |||
| 595 | 596 | ||
| 596 | config RCAR_GYRO_ADC | 597 | config RCAR_GYRO_ADC |
| 597 | tristate "Renesas R-Car GyroADC driver" | 598 | tristate "Renesas R-Car GyroADC driver" |
| 598 | depends on ARCH_RCAR_GEN2 || (ARM && COMPILE_TEST) | 599 | depends on ARCH_RCAR_GEN2 || COMPILE_TEST |
| 599 | help | 600 | help |
| 600 | Say yes here to build support for the GyroADC found in Renesas | 601 | Say yes here to build support for the GyroADC found in Renesas |
| 601 | R-Car Gen2 SoCs. This block is a simple SPI offload engine for | 602 | R-Car Gen2 SoCs. This block is a simple SPI offload engine for |
| @@ -280,7 +280,6 @@ static AD7266_DECLARE_DIFF_CHANNELS_FIXED(u, 'u'); · 279 unmodified lines | |||
| 280 | static const struct iio_info ad7266_info = { | 280 | static const struct iio_info ad7266_info = { |
| 281 | .read_raw = &ad7266_read_raw, | 281 | .read_raw = &ad7266_read_raw, |
| 282 | .update_scan_mode = &ad7266_update_scan_mode, | 282 | .update_scan_mode = &ad7266_update_scan_mode, |
| 283 | .driver_module = THIS_MODULE, | ||
| 284 | }; | 283 | }; |
| 285 | 284 | ||
| 286 | static const unsigned long ad7266_available_scan_masks[] = { | 285 | static const unsigned long ad7266_available_scan_masks[] = { |
| @@ -461,7 +461,6 @@ static const struct iio_info ad7291_info = { · 460 unmodified lines | |||
| 461 | .write_event_config = &ad7291_write_event_config, | 461 | .write_event_config = &ad7291_write_event_config, |
| 462 | .read_event_value = &ad7291_read_event_value, | 462 | .read_event_value = &ad7291_read_event_value, |
| 463 | .write_event_value = &ad7291_write_event_value, | 463 | .write_event_value = &ad7291_write_event_value, |
| 464 | .driver_module = THIS_MODULE, | ||
| 465 | }; | 464 | }; |
| 466 | 465 | ||
| 467 | static int ad7291_probe(struct i2c_client *client, | 466 | static int ad7291_probe(struct i2c_client *client, |
| @@ -280,7 +280,6 @@ static int ad7298_read_raw(struct iio_dev *indio_dev, · 279 unmodified lines | |||
| 280 | static const struct iio_info ad7298_info = { | 280 | static const struct iio_info ad7298_info = { |
| 281 | .read_raw = &ad7298_read_raw, | 281 | .read_raw = &ad7298_read_raw, |
| 282 | .update_scan_mode = ad7298_update_scan_mode, | 282 | .update_scan_mode = ad7298_update_scan_mode, |
| 283 | .driver_module = THIS_MODULE, | ||
| 284 | }; | 283 | }; |
| 285 | 284 | ||
| 286 | static int ad7298_probe(struct spi_device *spi) | 285 | static int ad7298_probe(struct spi_device *spi) |
| @@ -195,7 +195,6 @@ static const struct ad7476_chip_info ad7476_chip_info_tbl[] = { · 194 unmodified lines | |||
| 195 | }; | 195 | }; |
| 196 | 196 | ||
| 197 | static const struct iio_info ad7476_info = { | 197 | static const struct iio_info ad7476_info = { |
| 198 | .driver_module = THIS_MODULE, | ||
| 199 | .read_raw = &ad7476_read_raw, | 198 | .read_raw = &ad7476_read_raw, |
| 200 | }; | 199 | }; |
| 201 | 200 | ||
| @@ -185,7 +185,6 @@ static const struct iio_buffer_setup_ops ad7766_buffer_setup_ops = { · 184 unmodified lines | |||
| 185 | }; | 185 | }; |
| 186 | 186 | ||
| 187 | static const struct iio_info ad7766_info = { | 187 | static const struct iio_info ad7766_info = { |
| 188 | .driver_module = THIS_MODULE, | ||
| 189 | .read_raw = &ad7766_read_raw, | 188 | .read_raw = &ad7766_read_raw, |
| 190 | }; | 189 | }; |
| 191 | 190 | ||
| @@ -208,7 +207,6 @@ static int ad7766_set_trigger_state(struct iio_trigger *trig, bool enable) · 16 unmodified lines | |||
| 208 | } | 207 | } |
| 209 | 208 | ||
| 210 | static const struct iio_trigger_ops ad7766_trigger_ops = { | 209 | static const struct iio_trigger_ops ad7766_trigger_ops = { |
| 211 | .owner = THIS_MODULE, | ||
| 212 | .set_trigger_state = ad7766_set_trigger_state, | 210 | .set_trigger_state = ad7766_set_trigger_state, |
| 213 | .validate_device = iio_trigger_validate_own_device, | 211 | .validate_device = iio_trigger_validate_own_device, |
| 214 | }; | 212 | }; |
| @@ -308,13 +308,11 @@ static const struct iio_info ad7791_info = { · 307 unmodified lines | |||
| 308 | .read_raw = &ad7791_read_raw, | 308 | .read_raw = &ad7791_read_raw, |
| 309 | .attrs = &ad7791_attribute_group, | 309 | .attrs = &ad7791_attribute_group, |
| 310 | .validate_trigger = ad_sd_validate_trigger, | 310 | .validate_trigger = ad_sd_validate_trigger, |
| 311 | .driver_module = THIS_MODULE, | ||
| 312 | }; | 311 | }; |
| 313 | 312 | ||
| 314 | static const struct iio_info ad7791_no_filter_info = { | 313 | static const struct iio_info ad7791_no_filter_info = { |
| 315 | .read_raw = &ad7791_read_raw, | 314 | .read_raw = &ad7791_read_raw, |
| 316 | .validate_trigger = ad_sd_validate_trigger, | 315 | .validate_trigger = ad_sd_validate_trigger, |
| 317 | .driver_module = THIS_MODULE, | ||
| 318 | }; | 316 | }; |
| 319 | 317 | ||
| 320 | static int ad7791_setup(struct ad7791_state *st, | 318 | static int ad7791_setup(struct ad7791_state *st, |
| @@ -563,7 +563,6 @@ static const struct iio_info ad7793_info = { · 562 unmodified lines | |||
| 563 | .write_raw_get_fmt = &ad7793_write_raw_get_fmt, | 563 | .write_raw_get_fmt = &ad7793_write_raw_get_fmt, |
| 564 | .attrs = &ad7793_attribute_group, | 564 | .attrs = &ad7793_attribute_group, |
| 565 | .validate_trigger = ad_sd_validate_trigger, | 565 | .validate_trigger = ad_sd_validate_trigger, |
| 566 | .driver_module = THIS_MODULE, | ||
| 567 | }; | 566 | }; |
| 568 | 567 | ||
| 569 | static const struct iio_info ad7797_info = { | 568 | static const struct iio_info ad7797_info = { |
| @@ -572,7 +571,6 @@ static const struct iio_info ad7797_info = { · 2 unmodified lines | |||
| 572 | .write_raw_get_fmt = &ad7793_write_raw_get_fmt, | 571 | .write_raw_get_fmt = &ad7793_write_raw_get_fmt, |
| 573 | .attrs = &ad7793_attribute_group, | 572 | .attrs = &ad7793_attribute_group, |
| 574 | .validate_trigger = ad_sd_validate_trigger, | 573 | .validate_trigger = ad_sd_validate_trigger, |
| 575 | .driver_module = THIS_MODULE, | ||
| 576 | }; | 574 | }; |
| 577 | 575 | ||
| 578 | #define DECLARE_AD7793_CHANNELS(_name, _b, _sb, _s) \ | 576 | #define DECLARE_AD7793_CHANNELS(_name, _b, _sb, _s) \ |
| @@ -229,7 +229,6 @@ static const struct ad7887_chip_info ad7887_chip_info_tbl[] = { · 228 unmodified lines | |||
| 229 | 229 | ||
| 230 | static const struct iio_info ad7887_info = { | 230 | static const struct iio_info ad7887_info = { |
| 231 | .read_raw = &ad7887_read_raw, | 231 | .read_raw = &ad7887_read_raw, |
| 232 | .driver_module = THIS_MODULE, | ||
| 233 | }; | 232 | }; |
| 234 | 233 | ||
| 235 | static int ad7887_probe(struct spi_device *spi) | 234 | static int ad7887_probe(struct spi_device *spi) |
| @@ -262,7 +262,6 @@ static int ad7923_read_raw(struct iio_dev *indio_dev, · 261 unmodified lines | |||
| 262 | static const struct iio_info ad7923_info = { | 262 | static const struct iio_info ad7923_info = { |
| 263 | .read_raw = &ad7923_read_raw, | 263 | .read_raw = &ad7923_read_raw, |
| 264 | .update_scan_mode = ad7923_update_scan_mode, | 264 | .update_scan_mode = ad7923_update_scan_mode, |
| 265 | .driver_module = THIS_MODULE, | ||
| 266 | }; | 265 | }; |
| 267 | 266 | ||
| 268 | static int ad7923_probe(struct spi_device *spi) | 267 | static int ad7923_probe(struct spi_device *spi) |
| @@ -526,13 +526,11 @@ static const struct attribute_group ad799x_event_attrs_group = { · 525 unmodified lines | |||
| 526 | 526 | ||
| 527 | static const struct iio_info ad7991_info = { | 527 | static const struct iio_info ad7991_info = { |
| 528 | .read_raw = &ad799x_read_raw, | 528 | .read_raw = &ad799x_read_raw, |
| 529 | .driver_module = THIS_MODULE, | ||
| 530 | .update_scan_mode = ad799x_update_scan_mode, | 529 | .update_scan_mode = ad799x_update_scan_mode, |
| 531 | }; | 530 | }; |
| 532 | 531 | ||
| 533 | static const struct iio_info ad7993_4_7_8_noirq_info = { | 532 | static const struct iio_info ad7993_4_7_8_noirq_info = { |
| 534 | .read_raw = &ad799x_read_raw, | 533 | .read_raw = &ad799x_read_raw, |
| 535 | .driver_module = THIS_MODULE, | ||
| 536 | .update_scan_mode = ad799x_update_scan_mode, | 534 | .update_scan_mode = ad799x_update_scan_mode, |
| 537 | }; | 535 | }; |
| 538 | 536 | ||
| @@ -543,7 +541,6 @@ static const struct iio_info ad7993_4_7_8_irq_info = { · 4 unmodified lines | |||
| 543 | .write_event_config = &ad799x_write_event_config, | 541 | .write_event_config = &ad799x_write_event_config, |
| 544 | .read_event_value = &ad799x_read_event_value, | 542 | .read_event_value = &ad799x_read_event_value, |
| 545 | .write_event_value = &ad799x_write_event_value, | 543 | .write_event_value = &ad799x_write_event_value, |
| 546 | .driver_module = THIS_MODULE, | ||
| 547 | .update_scan_mode = ad799x_update_scan_mode, | 544 | .update_scan_mode = ad799x_update_scan_mode, |
| 548 | }; | 545 | }; |
| 549 | 546 | ||
| @@ -463,7 +463,6 @@ int ad_sd_validate_trigger(struct iio_dev *indio_dev, struct iio_trigger *trig) · 462 unmodified lines | |||
| 463 | EXPORT_SYMBOL_GPL(ad_sd_validate_trigger); | 463 | EXPORT_SYMBOL_GPL(ad_sd_validate_trigger); |
| 464 | 464 | ||
| 465 | static const struct iio_trigger_ops ad_sd_trigger_ops = { | 465 | static const struct iio_trigger_ops ad_sd_trigger_ops = { |
| 466 | .owner = THIS_MODULE, | ||
| 467 | }; | 466 | }; |
| 468 | 467 | ||
| 469 | static int ad_sd_probe_trigger(struct iio_dev *indio_dev) | 468 | static int ad_sd_probe_trigger(struct iio_dev *indio_dev) |
| @@ -165,7 +165,6 @@ static int aspeed_adc_reg_access(struct iio_dev *indio_dev, · 164 unmodified lines | |||
| 165 | } | 165 | } |
| 166 | 166 | ||
| 167 | static const struct iio_info aspeed_adc_iio_info = { | 167 | static const struct iio_info aspeed_adc_iio_info = { |
| 168 | .driver_module = THIS_MODULE, | ||
| 169 | .read_raw = aspeed_adc_read_raw, | 168 | .read_raw = aspeed_adc_read_raw, |
| 170 | .write_raw = aspeed_adc_write_raw, | 169 | .write_raw = aspeed_adc_write_raw, |
| 171 | .debugfs_reg_access = aspeed_adc_reg_access, | 170 | .debugfs_reg_access = aspeed_adc_reg_access, |
| @@ -348,7 +348,6 @@ static int at91_adc_reenable_trigger(struct iio_trigger *trig) · 347 unmodified lines | |||
| 348 | } | 348 | } |
| 349 | 349 | ||
| 350 | static const struct iio_trigger_ops at91_adc_trigger_ops = { | 350 | static const struct iio_trigger_ops at91_adc_trigger_ops = { |
| 351 | .owner = THIS_MODULE, | ||
| 352 | .set_trigger_state = &at91_adc_configure_trigger, | 351 | .set_trigger_state = &at91_adc_configure_trigger, |
| 353 | .try_reenable = &at91_adc_reenable_trigger, | 352 | .try_reenable = &at91_adc_reenable_trigger, |
| 354 | }; | 353 | }; |
| @@ -584,7 +583,6 @@ static int at91_adc_write_raw(struct iio_dev *indio_dev, · 229 unmodified lines | |||
| 584 | static const struct iio_info at91_adc_info = { | 583 | static const struct iio_info at91_adc_info = { |
| 585 | .read_raw = &at91_adc_read_raw, | 584 | .read_raw = &at91_adc_read_raw, |
| 586 | .write_raw = &at91_adc_write_raw, | 585 | .write_raw = &at91_adc_write_raw, |
| 587 | .driver_module = THIS_MODULE, | ||
| 588 | }; | 586 | }; |
| 589 | 587 | ||
| 590 | static void at91_adc_hw_init(struct at91_adc_state *st) | 588 | static void at91_adc_hw_init(struct at91_adc_state *st) |
| @@ -594,7 +594,6 @@ static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) · 593 unmodified lines | |||
| 594 | } | 594 | } |
| 595 | 595 | ||
| 596 | static const struct iio_trigger_ops at91_adc_trigger_ops = { | 596 | static const struct iio_trigger_ops at91_adc_trigger_ops = { |
| 597 | .owner = THIS_MODULE, | ||
| 598 | .set_trigger_state = &at91_adc_configure_trigger, | 597 | .set_trigger_state = &at91_adc_configure_trigger, |
| 599 | }; | 598 | }; |
| 600 | 599 | ||
| @@ -976,7 +975,6 @@ static int at91_adc_probe_pdata(struct at91_adc_state *st, · 375 unmodified lines | |||
| 976 | } | 975 | } |
| 977 | 976 | ||
| 978 | static const struct iio_info at91_adc_info = { | 977 | static const struct iio_info at91_adc_info = { |
| 979 | .driver_module = THIS_MODULE, | ||
| 980 | .read_raw = &at91_adc_read_raw, | 978 | .read_raw = &at91_adc_read_raw, |
| 981 | }; | 979 | }; |
| 982 | 980 | ||
| @@ -464,12 +464,10 @@ static int axp20x_write_raw(struct iio_dev *indio_dev, · 463 unmodified lines | |||
| 464 | static const struct iio_info axp20x_adc_iio_info = { | 464 | static const struct iio_info axp20x_adc_iio_info = { |
| 465 | .read_raw = axp20x_read_raw, | 465 | .read_raw = axp20x_read_raw, |
| 466 | .write_raw = axp20x_write_raw, | 466 | .write_raw = axp20x_write_raw, |
| 467 | .driver_module = THIS_MODULE, | ||
| 468 | }; | 467 | }; |
| 469 | 468 | ||
| 470 | static const struct iio_info axp22x_adc_iio_info = { | 469 | static const struct iio_info axp22x_adc_iio_info = { |
| 471 | .read_raw = axp22x_read_raw, | 470 | .read_raw = axp22x_read_raw, |
| 472 | .driver_module = THIS_MODULE, | ||
| 473 | }; | 471 | }; |
| 474 | 472 | ||
| 475 | static int axp20x_adc_rate(int rate) | 473 | static int axp20x_adc_rate(int rate) |
| @@ -183,7 +183,6 @@ static int axp288_adc_set_state(struct regmap *regmap) · 182 unmodified lines | |||
| 183 | 183 | ||
| 184 | static const struct iio_info axp288_adc_iio_info = { | 184 | static const struct iio_info axp288_adc_iio_info = { |
| 185 | .read_raw = &axp288_adc_read_raw, | 185 | .read_raw = &axp288_adc_read_raw, |
| 186 | .driver_module = THIS_MODULE, | ||
| 187 | }; | 186 | }; |
| 188 | 187 | ||
| 189 | static int axp288_adc_probe(struct platform_device *pdev) | 188 | static int axp288_adc_probe(struct platform_device *pdev) |
| @@ -492,7 +492,6 @@ static int iproc_adc_read_raw(struct iio_dev *indio_dev, · 491 unmodified lines | |||
| 492 | 492 | ||
| 493 | static const struct iio_info iproc_adc_iio_info = { | 493 | static const struct iio_info iproc_adc_iio_info = { |
| 494 | .read_raw = &iproc_adc_read_raw, | 494 | .read_raw = &iproc_adc_read_raw, |
| 495 | .driver_module = THIS_MODULE, | ||
| 496 | }; | 495 | }; |
| 497 | 496 | ||
| 498 | #define IPROC_ADC_CHANNEL(_index, _id) { \ | 497 | #define IPROC_ADC_CHANNEL(_index, _id) { \ |
| @@ -277,7 +277,6 @@ static irqreturn_t berlin2_adc_tsen_irq(int irq, void *private) · 276 unmodified lines | |||
| 277 | } | 277 | } |
| 278 | 278 | ||
| 279 | static const struct iio_info berlin2_adc_info = { | 279 | static const struct iio_info berlin2_adc_info = { |
| 280 | .driver_module = THIS_MODULE, | ||
| 281 | .read_raw = berlin2_adc_read_raw, | 280 | .read_raw = berlin2_adc_read_raw, |
| 282 | }; | 281 | }; |
| 283 | 282 | ||
| @@ -262,7 +262,6 @@ static int cc10001_update_scan_mode(struct iio_dev *indio_dev, · 261 unmodified lines | |||
| 262 | } | 262 | } |
| 263 | 263 | ||
| 264 | static const struct iio_info cc10001_adc_info = { | 264 | static const struct iio_info cc10001_adc_info = { |
| 265 | .driver_module = THIS_MODULE, | ||
| 266 | .read_raw = &cc10001_adc_read_raw, | 265 | .read_raw = &cc10001_adc_read_raw, |
| 267 | .update_scan_mode = &cc10001_update_scan_mode, | 266 | .update_scan_mode = &cc10001_update_scan_mode, |
| 268 | }; | 267 | }; |
| @@ -932,7 +932,6 @@ err_unlock: · 931 unmodified lines | |||
| 932 | 932 | ||
| 933 | static const struct iio_info cpcap_adc_info = { | 933 | static const struct iio_info cpcap_adc_info = { |
| 934 | .read_raw = &cpcap_adc_read, | 934 | .read_raw = &cpcap_adc_read, |
| 935 | .driver_module = THIS_MODULE, | ||
| 936 | }; | 935 | }; |
| 937 | 936 | ||
| 938 | /* | 937 | /* |
| @@ -249,7 +249,6 @@ static int da9150_gpadc_read_raw(struct iio_dev *indio_dev, · 248 unmodified lines | |||
| 249 | 249 | ||
| 250 | static const struct iio_info da9150_gpadc_info = { | 250 | static const struct iio_info da9150_gpadc_info = { |
| 251 | .read_raw = &da9150_gpadc_read_raw, | 251 | .read_raw = &da9150_gpadc_read_raw, |
| 252 | .driver_module = THIS_MODULE, | ||
| 253 | }; | 252 | }; |
| 254 | 253 | ||
| 255 | #define DA9150_GPADC_CHANNEL(_id, _hw_id, _type, chan_info, \ | 254 | #define DA9150_GPADC_CHANNEL(_id, _hw_id, _type, chan_info, \ |
| @@ -479,7 +479,6 @@ static const struct iio_info dln2_adc_info = { · 478 unmodified lines | |||
| 479 | .read_raw = dln2_adc_read_raw, | 479 | .read_raw = dln2_adc_read_raw, |
| 480 | .write_raw = dln2_adc_write_raw, | 480 | .write_raw = dln2_adc_write_raw, |
| 481 | .update_scan_mode = dln2_update_scan_mode, | 481 | .update_scan_mode = dln2_update_scan_mode, |
| 482 | .driver_module = THIS_MODULE, | ||
| 483 | }; | 482 | }; |
| 484 | 483 | ||
| 485 | static irqreturn_t dln2_adc_trigger_h(int irq, void *p) | 484 | static irqreturn_t dln2_adc_trigger_h(int irq, void *p) |
| @@ -604,10 +603,6 @@ static void dln2_adc_event(struct platform_device *pdev, u16 echo, · 118 unmodified lines | |||
| 604 | iio_trigger_poll(dln2->trig); | 603 | iio_trigger_poll(dln2->trig); |
| 605 | } | 604 | } |
| 606 | 605 | ||
| 607 | static const struct iio_trigger_ops dln2_adc_trigger_ops = { | ||
| 608 | .owner = THIS_MODULE, | ||
| 609 | }; | ||
| 610 | |||
| 611 | static int dln2_adc_probe(struct platform_device *pdev) | 606 | static int dln2_adc_probe(struct platform_device *pdev) |
| 612 | { | 607 | { |
| 613 | struct device *dev = &pdev->dev; | 608 | struct device *dev = &pdev->dev; |
| @@ -665,7 +660,6 @@ static int dln2_adc_probe(struct platform_device *pdev) · 51 unmodified lines | |||
| 665 | dev_err(dev, "failed to allocate trigger\n"); | 660 | dev_err(dev, "failed to allocate trigger\n"); |
| 666 | return -ENOMEM; | 661 | return -ENOMEM; |
| 667 | } | 662 | } |
| 668 | dln2->trig->ops = &dln2_adc_trigger_ops; | ||
| 669 | iio_trigger_set_drvdata(dln2->trig, dln2); | 663 | iio_trigger_set_drvdata(dln2->trig, dln2); |
| 670 | devm_iio_trigger_register(dev, dln2->trig); | 664 | devm_iio_trigger_register(dev, dln2->trig); |
| 671 | iio_trigger_set_immutable(indio_dev, dln2->trig); | 665 | iio_trigger_set_immutable(indio_dev, dln2->trig); |
| @@ -322,7 +322,6 @@ static const struct iio_chan_spec envelope_detector_iio_channel = { · 321 unmodified lines | |||
| 322 | 322 | ||
| 323 | static const struct iio_info envelope_detector_info = { | 323 | static const struct iio_info envelope_detector_info = { |
| 324 | .read_raw = &envelope_detector_read_raw, | 324 | .read_raw = &envelope_detector_read_raw, |
| 325 | .driver_module = THIS_MODULE, | ||
| 326 | }; | 325 | }; |
| 327 | 326 | ||
| 328 | static int envelope_detector_probe(struct platform_device *pdev) | 327 | static int envelope_detector_probe(struct platform_device *pdev) |
| @@ -150,7 +150,6 @@ static int ep93xx_read_raw(struct iio_dev *iiodev, · 149 unmodified lines | |||
| 150 | } | 150 | } |
| 151 | 151 | ||
| 152 | static const struct iio_info ep93xx_adc_info = { | 152 | static const struct iio_info ep93xx_adc_info = { |
| 153 | .driver_module = THIS_MODULE, | ||
| 154 | .read_raw = ep93xx_read_raw, | 153 | .read_raw = ep93xx_read_raw, |
| 155 | }; | 154 | }; |
| 156 | 155 | ||
| @@ -657,7 +657,6 @@ static int exynos_adc_reg_access(struct iio_dev *indio_dev, · 656 unmodified lines | |||
| 657 | static const struct iio_info exynos_adc_iio_info = { | 657 | static const struct iio_info exynos_adc_iio_info = { |
| 658 | .read_raw = &exynos_read_raw, | 658 | .read_raw = &exynos_read_raw, |
| 659 | .debugfs_reg_access = &exynos_adc_reg_access, | 659 | .debugfs_reg_access = &exynos_adc_reg_access, |
| 660 | .driver_module = THIS_MODULE, | ||
| 661 | }; | 660 | }; |
| 662 | 661 | ||
| 663 | #define ADC_CHANNEL(_index, _id) { \ | 662 | #define ADC_CHANNEL(_index, _id) { \ |
| @@ -408,7 +408,6 @@ static const struct iio_chan_spec hi8435_channels[] = { · 407 unmodified lines | |||
| 408 | }; | 408 | }; |
| 409 | 409 | ||
| 410 | static const struct iio_info hi8435_info = { | 410 | static const struct iio_info hi8435_info = { |
| 411 | .driver_module = THIS_MODULE, | ||
| 412 | .read_raw = hi8435_read_raw, | 411 | .read_raw = hi8435_read_raw, |
| 413 | .read_event_config = hi8435_read_event_config, | 412 | .read_event_config = hi8435_read_event_config, |
| 414 | .write_event_config = hi8435_write_event_config, | 413 | .write_event_config = hi8435_write_event_config, |
| @@ -374,7 +374,6 @@ static const struct attribute_group hx711_attribute_group = { · 373 unmodified lines | |||
| 374 | }; | 374 | }; |
| 375 | 375 | ||
| 376 | static const struct iio_info hx711_iio_info = { | 376 | static const struct iio_info hx711_iio_info = { |
| 377 | .driver_module = THIS_MODULE, | ||
| 378 | .read_raw = hx711_read_raw, | 377 | .read_raw = hx711_read_raw, |
| 379 | .write_raw = hx711_write_raw, | 378 | .write_raw = hx711_write_raw, |
| 380 | .write_raw_get_fmt = hx711_write_raw_get_fmt, | 379 | .write_raw_get_fmt = hx711_write_raw_get_fmt, |
| @@ -412,7 +412,6 @@ static int imx7d_adc_reg_access(struct iio_dev *indio_dev, · 411 unmodified lines | |||
| 412 | } | 412 | } |
| 413 | 413 | ||
| 414 | static const struct iio_info imx7d_adc_iio_info = { | 414 | static const struct iio_info imx7d_adc_iio_info = { |
| 415 | .driver_module = THIS_MODULE, | ||
| 416 | .read_raw = &imx7d_adc_read_raw, | 415 | .read_raw = &imx7d_adc_read_raw, |
| 417 | .debugfs_reg_access = &imx7d_adc_reg_access, | 416 | .debugfs_reg_access = &imx7d_adc_reg_access, |
| 418 | }; | 417 | }; |
| @@ -123,7 +123,7 @@ struct ina2xx_chip_info { · 122 unmodified lines | |||
| 123 | struct task_struct *task; | 123 | struct task_struct *task; |
| 124 | const struct ina2xx_config *config; | 124 | const struct ina2xx_config *config; |
| 125 | struct mutex state_lock; | 125 | struct mutex state_lock; |
| 126 | unsigned int shunt_resistor; | 126 | unsigned int shunt_resistor_uohm; |
| 127 | int avg; | 127 | int avg; |
| 128 | int int_time_vbus; /* Bus voltage integration time uS */ | 128 | int int_time_vbus; /* Bus voltage integration time uS */ |
| 129 | int int_time_vshunt; /* Shunt voltage integration time uS */ | 129 | int int_time_vshunt; /* Shunt voltage integration time uS */ |
| @@ -436,7 +436,7 @@ static ssize_t ina2xx_allow_async_readout_store(struct device *dev, · 306 unmodified lines | |||
| 436 | /* | 436 | /* |
| 437 | * Set current LSB to 1mA, shunt is in uOhms | 437 | * Set current LSB to 1mA, shunt is in uOhms |
| 438 | * (equation 13 in datasheet). We hardcode a Current_LSB | 438 | * (equation 13 in datasheet). We hardcode a Current_LSB |
| 439 | * of 1.0 x10-6. The only remaining parameter is RShunt. | 439 | * of 1.0 x10-3. The only remaining parameter is RShunt. |
| 440 | * There is no need to expose the CALIBRATION register | 440 | * There is no need to expose the CALIBRATION register |
| 441 | * to the user for now. But we need to reset this register | 441 | * to the user for now. But we need to reset this register |
| 442 | * if the user updates RShunt after driver init, e.g upon | 442 | * if the user updates RShunt after driver init, e.g upon |
| @@ -445,7 +445,7 @@ static ssize_t ina2xx_allow_async_readout_store(struct device *dev, · 2 unmodified lines | |||
| 445 | static int ina2xx_set_calibration(struct ina2xx_chip_info *chip) | 445 | static int ina2xx_set_calibration(struct ina2xx_chip_info *chip) |
| 446 | { | 446 | { |
| 447 | u16 regval = DIV_ROUND_CLOSEST(chip->config->calibration_factor, | 447 | u16 regval = DIV_ROUND_CLOSEST(chip->config->calibration_factor, |
| 448 | chip->shunt_resistor); | 448 | chip->shunt_resistor_uohm); |
| 449 | 449 | ||
| 450 | return regmap_write(chip->regmap, INA2XX_CALIBRATION, regval); | 450 | return regmap_write(chip->regmap, INA2XX_CALIBRATION, regval); |
| 451 | } | 451 | } |
| @@ -455,7 +455,7 @@ static int set_shunt_resistor(struct ina2xx_chip_info *chip, unsigned int val) · 3 unmodified lines | |||
| 455 | if (val <= 0 || val > chip->config->calibration_factor) | 455 | if (val <= 0 || val > chip->config->calibration_factor) |
| 456 | return -EINVAL; | 456 | return -EINVAL; |
| 457 | 457 | ||
| 458 | chip->shunt_resistor = val; | 458 | chip->shunt_resistor_uohm = val; |
| 459 | 459 | ||
| 460 | return 0; | 460 | return 0; |
| 461 | } | 461 | } |
| @@ -465,8 +465,9 @@ static ssize_t ina2xx_shunt_resistor_show(struct device *dev, · 3 unmodified lines | |||
| 465 | char *buf) | 465 | char *buf) |
| 466 | { | 466 | { |
| 467 | struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev)); | 467 | struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev)); |
| 468 | int vals[2] = { chip->shunt_resistor_uohm, 1000000 }; | ||
| 468 | 469 | ||
| 469 | return sprintf(buf, "%d\n", chip->shunt_resistor); | 470 | return iio_format_value(buf, IIO_VAL_FRACTIONAL, 1, vals); |
| 470 | } | 471 | } |
| 471 | 472 | ||
| 472 | static ssize_t ina2xx_shunt_resistor_store(struct device *dev, | 473 | static ssize_t ina2xx_shunt_resistor_store(struct device *dev, |
| @@ -474,14 +475,13 @@ static ssize_t ina2xx_shunt_resistor_store(struct device *dev, · 1 unmodified line | |||
| 474 | const char *buf, size_t len) | 475 | const char *buf, size_t len) |
| 475 | { | 476 | { |
| 476 | struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev)); | 477 | struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev)); |
| 477 | unsigned long val; | 478 | int val, val_fract, ret; |
| 478 | int ret; | ||
| 479 | 479 | ||
| 480 | ret = kstrtoul((const char *) buf, 10, &val); | 480 | ret = iio_str_to_fixpoint(buf, 100000, &val, &val_fract); |
| 481 | if (ret) | 481 | if (ret) |
| 482 | return ret; | 482 | return ret; |
| 483 | 483 | ||
| 484 | ret = set_shunt_resistor(chip, val); | 484 | ret = set_shunt_resistor(chip, val * 1000000 + val_fract); |
| 485 | if (ret) | 485 | if (ret) |
| 486 | return ret; | 486 | return ret; |
| 487 | 487 | ||
| @@ -778,7 +778,6 @@ static const struct attribute_group ina226_attribute_group = { · 290 unmodified lines | |||
| 778 | }; | 778 | }; |
| 779 | 779 | ||
| 780 | static const struct iio_info ina219_info = { | 780 | static const struct iio_info ina219_info = { |
| 781 | .driver_module = THIS_MODULE, | ||
| 782 | .attrs = &ina219_attribute_group, | 781 | .attrs = &ina219_attribute_group, |
| 783 | .read_raw = ina2xx_read_raw, | 782 | .read_raw = ina2xx_read_raw, |
| 784 | .write_raw = ina2xx_write_raw, | 783 | .write_raw = ina2xx_write_raw, |
| @@ -786,7 +785,6 @@ static const struct iio_info ina219_info = { · 1 unmodified line | |||
| 786 | }; | 785 | }; |
| 787 | 786 | ||
| 788 | static const struct iio_info ina226_info = { | 787 | static const struct iio_info ina226_info = { |
| 789 | .driver_module = THIS_MODULE, | ||
| 790 | .attrs = &ina226_attribute_group, | 788 | .attrs = &ina226_attribute_group, |
| 791 | .read_raw = ina2xx_read_raw, | 789 | .read_raw = ina2xx_read_raw, |
| 792 | .write_raw = ina2xx_write_raw, | 790 | .write_raw = ina2xx_write_raw, |
| @@ -125,7 +125,6 @@ static int lp8788_adc_read_raw(struct iio_dev *indio_dev, · 124 unmodified lines | |||
| 125 | 125 | ||
| 126 | static const struct iio_info lp8788_adc_info = { | 126 | static const struct iio_info lp8788_adc_info = { |
| 127 | .read_raw = &lp8788_adc_read_raw, | 127 | .read_raw = &lp8788_adc_read_raw, |
| 128 | .driver_module = THIS_MODULE, | ||
| 129 | }; | 128 | }; |
| 130 | 129 | ||
| 131 | #define LP8788_CHAN(_id, _type) { \ | 130 | #define LP8788_CHAN(_id, _type) { \ |
| @@ -116,7 +116,6 @@ static int lpc18xx_adc_read_raw(struct iio_dev *indio_dev, · 115 unmodified lines | |||
| 116 | 116 | ||
| 117 | static const struct iio_info lpc18xx_adc_info = { | 117 | static const struct iio_info lpc18xx_adc_info = { |
| 118 | .read_raw = lpc18xx_adc_read_raw, | 118 | .read_raw = lpc18xx_adc_read_raw, |
| 119 | .driver_module = THIS_MODULE, | ||
| 120 | }; | 119 | }; |
| 121 | 120 | ||
| 122 | static int lpc18xx_adc_probe(struct platform_device *pdev) | 121 | static int lpc18xx_adc_probe(struct platform_device *pdev) |
| @@ -104,7 +104,6 @@ static int lpc32xx_read_raw(struct iio_dev *indio_dev, · 103 unmodified lines | |||
| 104 | 104 | ||
| 105 | static const struct iio_info lpc32xx_adc_iio_info = { | 105 | static const struct iio_info lpc32xx_adc_iio_info = { |
| 106 | .read_raw = &lpc32xx_read_raw, | 106 | .read_raw = &lpc32xx_read_raw, |
| 107 | .driver_module = THIS_MODULE, | ||
| 108 | }; | 107 | }; |
| 109 | 108 | ||
| 110 | #define LPC32XX_ADC_CHANNEL(_index) { \ | 109 | #define LPC32XX_ADC_CHANNEL(_index) { \ |
| @@ -98,7 +98,6 @@ static const struct iio_chan_spec ltc2473_channel[] = { · 97 unmodified lines | |||
| 98 | 98 | ||
| 99 | static const struct iio_info ltc2471_info = { | 99 | static const struct iio_info ltc2471_info = { |
| 100 | .read_raw = ltc2471_read_raw, | 100 | .read_raw = ltc2471_read_raw, |
| 101 | .driver_module = THIS_MODULE, | ||
| 102 | }; | 101 | }; |
| 103 | 102 | ||
| 104 | static int ltc2471_i2c_probe(struct i2c_client *client, | 103 | static int ltc2471_i2c_probe(struct i2c_client *client, |
| @@ -90,7 +90,6 @@ static const struct iio_chan_spec ltc2485_channel[] = { · 89 unmodified lines | |||
| 90 | 90 | ||
| 91 | static const struct iio_info ltc2485_info = { | 91 | static const struct iio_info ltc2485_info = { |
| 92 | .read_raw = ltc2485_read_raw, | 92 | .read_raw = ltc2485_read_raw, |
| 93 | .driver_module = THIS_MODULE, | ||
| 94 | }; | 93 | }; |
| 95 | 94 | ||
| 96 | static int ltc2485_probe(struct i2c_client *client, | 95 | static int ltc2485_probe(struct i2c_client *client, |
| @@ -186,7 +186,6 @@ static const struct iio_chan_spec ltc2497_channel[] = { · 185 unmodified lines | |||
| 186 | 186 | ||
| 187 | static const struct iio_info ltc2497_info = { | 187 | static const struct iio_info ltc2497_info = { |
| 188 | .read_raw = ltc2497_read_raw, | 188 | .read_raw = ltc2497_read_raw, |
| 189 | .driver_module = THIS_MODULE, | ||
| 190 | }; | 189 | }; |
| 191 | 190 | ||
| 192 | static int ltc2497_probe(struct i2c_client *client, | 191 | static int ltc2497_probe(struct i2c_client *client, |
| @@ -381,13 +381,11 @@ static irqreturn_t max1027_trigger_handler(int irq, void *private) · 380 unmodified lines | |||
| 381 | } | 381 | } |
| 382 | 382 | ||
| 383 | static const struct iio_trigger_ops max1027_trigger_ops = { | 383 | static const struct iio_trigger_ops max1027_trigger_ops = { |
| 384 | .owner = THIS_MODULE, | ||
| 385 | .validate_device = &iio_trigger_validate_own_device, | 384 | .validate_device = &iio_trigger_validate_own_device, |
| 386 | .set_trigger_state = &max1027_set_trigger_state, | 385 | .set_trigger_state = &max1027_set_trigger_state, |
| 387 | }; | 386 | }; |
| 388 | 387 | ||
| 389 | static const struct iio_info max1027_info = { | 388 | static const struct iio_info max1027_info = { |
| 390 | .driver_module = THIS_MODULE, | ||
| 391 | .read_raw = &max1027_read_raw, | 389 | .read_raw = &max1027_read_raw, |
| 392 | .validate_trigger = &max1027_validate_trigger, | 390 | .validate_trigger = &max1027_validate_trigger, |
| 393 | .debugfs_reg_access = &max1027_debugfs_reg_access, | 391 | .debugfs_reg_access = &max1027_debugfs_reg_access, |
| @@ -100,7 +100,6 @@ static int max11100_read_raw(struct iio_dev *indio_dev, · 99 unmodified lines | |||
| 100 | } | 100 | } |
| 101 | 101 | ||
| 102 | static const struct iio_info max11100_info = { | 102 | static const struct iio_info max11100_info = { |
| 103 | .driver_module = THIS_MODULE, | ||
| 104 | .read_raw = max11100_read_raw, | 103 | .read_raw = max11100_read_raw, |
| 105 | }; | 104 | }; |
| 106 | 105 | ||
| @@ -155,7 +155,6 @@ static int max1118_read_raw(struct iio_dev *indio_dev, · 154 unmodified lines | |||
| 155 | 155 | ||
| 156 | static const struct iio_info max1118_info = { | 156 | static const struct iio_info max1118_info = { |
| 157 | .read_raw = max1118_read_raw, | 157 | .read_raw = max1118_read_raw, |
| 158 | .driver_module = THIS_MODULE, | ||
| 159 | }; | 158 | }; |
| 160 | 159 | ||
| 161 | static irqreturn_t max1118_trigger_handler(int irq, void *p) | 160 | static irqreturn_t max1118_trigger_handler(int irq, void *p) |
| @@ -1029,7 +1029,6 @@ static int max1363_update_scan_mode(struct iio_dev *indio_dev, · 1028 unmodified lines | |||
| 1029 | 1029 | ||
| 1030 | static const struct iio_info max1238_info = { | 1030 | static const struct iio_info max1238_info = { |
| 1031 | .read_raw = &max1363_read_raw, | 1031 | .read_raw = &max1363_read_raw, |
| 1032 | .driver_module = THIS_MODULE, | ||
| 1033 | .update_scan_mode = &max1363_update_scan_mode, | 1032 | .update_scan_mode = &max1363_update_scan_mode, |
| 1034 | }; | 1033 | }; |
| 1035 | 1034 | ||
| @@ -1040,7 +1039,6 @@ static const struct iio_info max1363_info = { · 4 unmodified lines | |||
| 1040 | .write_event_config = &max1363_write_event_config, | 1039 | .write_event_config = &max1363_write_event_config, |
| 1041 | .read_raw = &max1363_read_raw, | 1040 | .read_raw = &max1363_read_raw, |
| 1042 | .update_scan_mode = &max1363_update_scan_mode, | 1041 | .update_scan_mode = &max1363_update_scan_mode, |
| 1043 | .driver_module = THIS_MODULE, | ||
| 1044 | .event_attrs = &max1363_event_attribute_group, | 1042 | .event_attrs = &max1363_event_attribute_group, |
| 1045 | }; | 1043 | }; |
| 1046 | 1044 | ||
| @@ -460,7 +460,6 @@ static const struct attribute_group max9611_attribute_group = { · 459 unmodified lines | |||
| 460 | }; | 460 | }; |
| 461 | 461 | ||
| 462 | static const struct iio_info indio_info = { | 462 | static const struct iio_info indio_info = { |
| 463 | .driver_module = THIS_MODULE, | ||
| 464 | .read_raw = max9611_read_raw, | 463 | .read_raw = max9611_read_raw, |
| 465 | .attrs = &max9611_attribute_group, | 464 | .attrs = &max9611_attribute_group, |
| 466 | }; | 465 | }; |
| @@ -573,7 +572,6 @@ static int max9611_probe(struct i2c_client *client, · 106 unmodified lines | |||
| 573 | static struct i2c_driver max9611_driver = { | 572 | static struct i2c_driver max9611_driver = { |
| 574 | .driver = { | 573 | .driver = { |
| 575 | .name = DRIVER_NAME, | 574 | .name = DRIVER_NAME, |
| 576 | .owner = THIS_MODULE, | ||
| 577 | .of_match_table = max9611_of_table, | 575 | .of_match_table = max9611_of_table, |
| 578 | }, | 576 | }, |
| 579 | .probe = max9611_probe, | 577 | .probe = max9611_probe, |
| @@ -19,6 +19,11 @@ · 18 unmodified lines | |||
| 19 | * ------------ | 19 | * ------------ |
| 20 | * 13 bit converter | 20 | * 13 bit converter |
| 21 | * MCP3301 | 21 | * MCP3301 |
| 22 | * ------------ | ||
| 23 | * 22 bit converter | ||
| 24 | * MCP3550 | ||
| 25 | * MCP3551 | ||
| 26 | * MCP3553 | ||
| 22 | * | 27 | * |
| 23 | * Datasheet can be found here: | 28 | * Datasheet can be found here: |
| 24 | * http://ww1.microchip.com/downloads/en/DeviceDoc/21293C.pdf mcp3001 | 29 | * http://ww1.microchip.com/downloads/en/DeviceDoc/21293C.pdf mcp3001 |
| @@ -28,6 +33,7 @@ · 3 unmodified lines | |||
| 28 | * http://ww1.microchip.com/downloads/en/DeviceDoc/21034D.pdf mcp3202 | 33 | * http://ww1.microchip.com/downloads/en/DeviceDoc/21034D.pdf mcp3202 |
| 29 | * http://ww1.microchip.com/downloads/en/DeviceDoc/21298c.pdf mcp3204/08 | 34 | * http://ww1.microchip.com/downloads/en/DeviceDoc/21298c.pdf mcp3204/08 |
| 30 | * http://ww1.microchip.com/downloads/en/DeviceDoc/21700E.pdf mcp3301 | 35 | * http://ww1.microchip.com/downloads/en/DeviceDoc/21700E.pdf mcp3301 |
| 36 | * http://ww1.microchip.com/downloads/en/DeviceDoc/21950D.pdf mcp3550/1/3 | ||
| 31 | * | 37 | * |
| 32 | * This program is free software; you can redistribute it and/or modify | 38 | * This program is free software; you can redistribute it and/or modify |
| 33 | * it under the terms of the GNU General Public License version 2 as | 39 | * it under the terms of the GNU General Public License version 2 as |
| @@ -51,25 +57,45 @@ enum { · 17 unmodified lines | |||
| 51 | mcp3204, | 57 | mcp3204, |
| 52 | mcp3208, | 58 | mcp3208, |
| 53 | mcp3301, | 59 | mcp3301, |
| 60 | mcp3550_50, | ||
| 61 | mcp3550_60, | ||
| 62 | mcp3551, | ||
| 63 | mcp3553, | ||
| 54 | }; | 64 | }; |
| 55 | 65 | ||
| 56 | struct mcp320x_chip_info { | 66 | struct mcp320x_chip_info { |
| 57 | const struct iio_chan_spec *channels; | 67 | const struct iio_chan_spec *channels; |
| 58 | unsigned int num_channels; | 68 | unsigned int num_channels; |
| 59 | unsigned int resolution; | 69 | unsigned int resolution; |
| 70 | unsigned int conv_time; /* usec */ | ||
| 60 | }; | 71 | }; |
| 61 | 72 | ||
| 73 | /** | ||
| 74 | * struct mcp320x - Microchip SPI ADC instance | ||
| 75 | * @spi: SPI slave (parent of the IIO device) | ||
| 76 | * @msg: SPI message to select a channel and receive a value from the ADC | ||
| 77 | * @transfer: SPI transfers used by @msg | ||
| 78 | * @start_conv_msg: SPI message to start a conversion by briefly asserting CS | ||
| 79 | * @start_conv_transfer: SPI transfer used by @start_conv_msg | ||
| 80 | * @reg: regulator generating Vref | ||
| 81 | * @lock: protects read sequences | ||
| 82 | * @chip_info: ADC properties | ||
| 83 | * @tx_buf: buffer for @transfer[0] (not used on single-channel converters) | ||
| 84 | * @rx_buf: buffer for @transfer[1] | ||
| 85 | */ | ||
| 62 | struct mcp320x { | 86 | struct mcp320x { |
| 63 | struct spi_device *spi; | 87 | struct spi_device *spi; |
| 64 | struct spi_message msg; | 88 | struct spi_message msg; |
| 65 | struct spi_transfer transfer[2]; | 89 | struct spi_transfer transfer[2]; |
| 90 | struct spi_message start_conv_msg; | ||
| 91 | struct spi_transfer start_conv_transfer; | ||
| 66 | 92 | ||
| 67 | struct regulator *reg; | 93 | struct regulator *reg; |
| 68 | struct mutex lock; | 94 | struct mutex lock; |
| 69 | const struct mcp320x_chip_info *chip_info; | 95 | const struct mcp320x_chip_info *chip_info; |
| 70 | 96 | ||
| 71 | u8 tx_buf ____cacheline_aligned; | 97 | u8 tx_buf ____cacheline_aligned; |
| 72 | u8 rx_buf[2]; | 98 | u8 rx_buf[4]; |
| 73 | }; | 99 | }; |
| 74 | 100 | ||
| 75 | static int mcp320x_channel_to_tx_data(int device_index, | 101 | static int mcp320x_channel_to_tx_data(int device_index, |
| @@ -78,10 +104,6 @@ static int mcp320x_channel_to_tx_data(int device_index, · 2 unmodified lines | |||
| 78 | int start_bit = 1; | 104 | int start_bit = 1; |
| 79 | 105 | ||
| 80 | switch (device_index) { | 106 | switch (device_index) { |
| 81 | case mcp3001: | ||
| 82 | case mcp3201: | ||
| 83 | case mcp3301: | ||
| 84 | return 0; | ||
| 85 | case mcp3002: | 107 | case mcp3002: |
| 86 | case mcp3202: | 108 | case mcp3202: |
| 87 | return ((start_bit << 4) | (!differential << 3) | | 109 | return ((start_bit << 4) | (!differential << 3) | |
| @@ -102,21 +124,24 @@ static int mcp320x_adc_conversion(struct mcp320x *adc, u8 channel, · 14 unmodified lines | |||
| 102 | { | 124 | { |
| 103 | int ret; | 125 | int ret; |
| 104 | 126 | ||
| 105 | adc->rx_buf[0] = 0; | 127 | if (adc->chip_info->conv_time) { |
| 106 | adc->rx_buf[1] = 0; | 128 | ret = spi_sync(adc->spi, &adc->start_conv_msg); |
| 107 | adc->tx_buf = mcp320x_channel_to_tx_data(device_index, | ||
| 108 | channel, differential); | ||
| 109 | |||
| 110 | if (device_index != mcp3001 && device_index != mcp3201 && device_index != mcp3301) { | ||
| 111 | ret = spi_sync(adc->spi, &adc->msg); | ||
| 112 | if (ret < 0) | ||
| 113 | return ret; | ||
| 114 | } else { | ||
| 115 | ret = spi_read(adc->spi, &adc->rx_buf, sizeof(adc->rx_buf)); | ||
| 116 | if (ret < 0) | 129 | if (ret < 0) |
| 117 | return ret; | 130 | return ret; |
| 131 | |||
| 132 | usleep_range(adc->chip_info->conv_time, | ||
| 133 | adc->chip_info->conv_time + 100); | ||
| 118 | } | 134 | } |
| 119 | 135 | ||
| 136 | memset(&adc->rx_buf, 0, sizeof(adc->rx_buf)); | ||
| 137 | if (adc->chip_info->num_channels > 1) | ||
| 138 | adc->tx_buf = mcp320x_channel_to_tx_data(device_index, channel, | ||
| 139 | differential); | ||
| 140 | |||
| 141 | ret = spi_sync(adc->spi, &adc->msg); | ||
| 142 | if (ret < 0) | ||
| 143 | return ret; | ||
| 144 | |||
| 120 | switch (device_index) { | 145 | switch (device_index) { |
| 121 | case mcp3001: | 146 | case mcp3001: |
| 122 | *val = (adc->rx_buf[0] << 5 | adc->rx_buf[1] >> 3); | 147 | *val = (adc->rx_buf[0] << 5 | adc->rx_buf[1] >> 3); |
| @@ -138,6 +163,31 @@ static int mcp320x_adc_conversion(struct mcp320x *adc, u8 channel, · 15 unmodified lines | |||
| 138 | *val = sign_extend32((adc->rx_buf[0] & 0x1f) << 8 | 163 | *val = sign_extend32((adc->rx_buf[0] & 0x1f) << 8 |
| 139 | | adc->rx_buf[1], 12); | 164 | | adc->rx_buf[1], 12); |
| 140 | return 0; | 165 | return 0; |
| 166 | case mcp3550_50: | ||
| 167 | case mcp3550_60: | ||
| 168 | case mcp3551: | ||
| 169 | case mcp3553: { | ||
| 170 | u32 raw = be32_to_cpup((u32 *)adc->rx_buf); | ||
| 171 | |||
| 172 | if (!(adc->spi->mode & SPI_CPOL)) | ||
| 173 | raw <<= 1; /* strip Data Ready bit in SPI mode 0,0 */ | ||
| 174 | |||
| 175 | /* | ||
| 176 | * If the input is within -vref and vref, bit 21 is the sign. | ||
| 177 | * Up to 12% overrange or underrange are allowed, in which case | ||
| 178 | * bit 23 is the sign and bit 0 to 21 is the value. | ||
| 179 | */ | ||
| 180 | raw >>= 8; | ||
| 181 | if (raw & BIT(22) && raw & BIT(23)) | ||
| 182 | return -EIO; /* cannot have overrange AND underrange */ | ||
| 183 | else if (raw & BIT(22)) | ||
| 184 | raw &= ~BIT(22); /* overrange */ | ||
| 185 | else if (raw & BIT(23) || raw & BIT(21)) | ||
| 186 | raw |= GENMASK(31, 22); /* underrange or negative */ | ||
| 187 | |||
| 188 | *val = (s32)raw; | ||
| 189 | return 0; | ||
| 190 | } | ||
| 141 | default: | 191 | default: |
| 142 | return -EINVAL; | 192 | return -EINVAL; |
| 143 | } | 193 | } |
| @@ -248,7 +298,6 @@ static const struct iio_chan_spec mcp3208_channels[] = { · 104 unmodified lines | |||
| 248 | 298 | ||
| 249 | static const struct iio_info mcp320x_info = { | 299 | static const struct iio_info mcp320x_info = { |
| 250 | .read_raw = mcp320x_read_raw, | 300 | .read_raw = mcp320x_read_raw, |
| 251 | .driver_module = THIS_MODULE, | ||
| 252 | }; | 301 | }; |
| 253 | 302 | ||
| 254 | static const struct mcp320x_chip_info mcp320x_chip_infos[] = { | 303 | static const struct mcp320x_chip_info mcp320x_chip_infos[] = { |
| @@ -297,6 +346,31 @@ static const struct mcp320x_chip_info mcp320x_chip_infos[] = { · 42 unmodified lines | |||
| 297 | .num_channels = ARRAY_SIZE(mcp3201_channels), | 346 | .num_channels = ARRAY_SIZE(mcp3201_channels), |
| 298 | .resolution = 13 | 347 | .resolution = 13 |
| 299 | }, | 348 | }, |
| 349 | [mcp3550_50] = { | ||
| 350 | .channels = mcp3201_channels, | ||
| 351 | .num_channels = ARRAY_SIZE(mcp3201_channels), | ||
| 352 | .resolution = 21, | ||
| 353 | /* 2% max deviation + 144 clock periods to exit shutdown */ | ||
| 354 | .conv_time = 80000 * 1.02 + 144000 / 102.4, | ||
| 355 | }, | ||
| 356 | [mcp3550_60] = { | ||
| 357 | .channels = mcp3201_channels, | ||
| 358 | .num_channels = ARRAY_SIZE(mcp3201_channels), | ||
| 359 | .resolution = 21, | ||
| 360 | .conv_time = 66670 * 1.02 + 144000 / 122.88, | ||
| 361 | }, | ||
| 362 | [mcp3551] = { | ||
| 363 | .channels = mcp3201_channels, | ||
| 364 | .num_channels = ARRAY_SIZE(mcp3201_channels), | ||
| 365 | .resolution = 21, | ||
| 366 | .conv_time = 73100 * 1.02 + 144000 / 112.64, | ||
| 367 | }, | ||
| 368 | [mcp3553] = { | ||
| 369 | .channels = mcp3201_channels, | ||
| 370 | .num_channels = ARRAY_SIZE(mcp3201_channels), | ||
| 371 | .resolution = 21, | ||
| 372 | .conv_time = 16670 * 1.02 + 144000 / 122.88, | ||
| 373 | }, | ||
| 300 | }; | 374 | }; |
| 301 | 375 | ||
| 302 | static int mcp320x_probe(struct spi_device *spi) | 376 | static int mcp320x_probe(struct spi_device *spi) |
| @@ -304,7 +378,7 @@ static int mcp320x_probe(struct spi_device *spi) · 1 unmodified line | |||
| 304 | struct iio_dev *indio_dev; | 378 | struct iio_dev *indio_dev; |
| 305 | struct mcp320x *adc; | 379 | struct mcp320x *adc; |
| 306 | const struct mcp320x_chip_info *chip_info; | 380 | const struct mcp320x_chip_info *chip_info; |
| 307 | int ret; | 381 | int ret, device_index; |
| 308 | 382 | ||
| 309 | indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc)); | 383 | indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc)); |
| 310 | if (!indio_dev) | 384 | if (!indio_dev) |
| @@ -320,7 +394,8 @@ static int mcp320x_probe(struct spi_device *spi) · 9 unmodified lines | |||
| 320 | indio_dev->info = &mcp320x_info; | 394 | indio_dev->info = &mcp320x_info; |
| 321 | spi_set_drvdata(spi, indio_dev); | 395 | spi_set_drvdata(spi, indio_dev); |
| 322 | 396 | ||
| 323 | chip_info = &mcp320x_chip_infos[spi_get_device_id(spi)->driver_data]; | 397 | device_index = spi_get_device_id(spi)->driver_data; |
| 398 | chip_info = &mcp320x_chip_infos[device_index]; | ||
| 324 | indio_dev->channels = chip_info->channels; | 399 | indio_dev->channels = chip_info->channels; |
| 325 | indio_dev->num_channels = chip_info->num_channels; | 400 | indio_dev->num_channels = chip_info->num_channels; |
| 326 | 401 | ||
| @@ -329,10 +404,41 @@ static int mcp320x_probe(struct spi_device *spi) · 2 unmodified lines | |||
| 329 | adc->transfer[0].tx_buf = &adc->tx_buf; | 404 | adc->transfer[0].tx_buf = &adc->tx_buf; |
| 330 | adc->transfer[0].len = sizeof(adc->tx_buf); | 405 | adc->transfer[0].len = sizeof(adc->tx_buf); |
| 331 | adc->transfer[1].rx_buf = adc->rx_buf; | 406 | adc->transfer[1].rx_buf = adc->rx_buf; |
| 332 | adc->transfer[1].len = sizeof(adc->rx_buf); | 407 | adc->transfer[1].len = DIV_ROUND_UP(chip_info->resolution, 8); |
| 408 | |||
| 409 | if (chip_info->num_channels == 1) | ||
| 410 | /* single-channel converters are rx only (no MOSI pin) */ | ||
| 411 | spi_message_init_with_transfers(&adc->msg, | ||
| 412 | &adc->transfer[1], 1); | ||
| 413 | else | ||
| 414 | spi_message_init_with_transfers(&adc->msg, adc->transfer, | ||
| 415 | ARRAY_SIZE(adc->transfer)); | ||
| 333 | 416 | ||
| 334 | spi_message_init_with_transfers(&adc->msg, adc->transfer, | 417 | switch (device_index) { |
| 335 | ARRAY_SIZE(adc->transfer)); | 418 | case mcp3550_50: |
| 419 | case mcp3550_60: | ||
| 420 | case mcp3551: | ||
| 421 | case mcp3553: | ||
| 422 | /* rx len increases from 24 to 25 bit in SPI mode 0,0 */ | ||
| 423 | if (!(spi->mode & SPI_CPOL)) | ||
| 424 | adc->transfer[1].len++; | ||
| 425 | |||
| 426 | /* conversions are started by asserting CS pin for 8 usec */ | ||
| 427 | adc->start_conv_transfer.delay_usecs = 8; | ||
| 428 | spi_message_init_with_transfers(&adc->start_conv_msg, | ||
| 429 | &adc->start_conv_transfer, 1); | ||
| 430 | |||
| 431 | /* | ||
| 432 | * If CS was previously kept low (continuous conversion mode) | ||
| 433 | * and then changed to high, the chip is in shutdown. | ||
| 434 | * Sometimes it fails to wake from shutdown and clocks out | ||
| 435 | * only 0xffffff. The magic sequence of performing two | ||
| 436 | * conversions without delay between them resets the chip | ||
| 437 | * and ensures all subsequent conversions succeed. | ||
| 438 | */ | ||
| 439 | mcp320x_adc_conversion(adc, 0, 1, device_index, &ret); | ||
| 440 | mcp320x_adc_conversion(adc, 0, 1, device_index, &ret); | ||
| 441 | } | ||
| 336 | 442 | ||
| 337 | adc->reg = devm_regulator_get(&spi->dev, "vref"); | 443 | adc->reg = devm_regulator_get(&spi->dev, "vref"); |
| 338 | if (IS_ERR(adc->reg)) | 444 | if (IS_ERR(adc->reg)) |
| @@ -370,62 +476,29 @@ static int mcp320x_remove(struct spi_device *spi) · 31 unmodified lines | |||
| 370 | #if defined(CONFIG_OF) | 476 | #if defined(CONFIG_OF) |
| 371 | static const struct of_device_id mcp320x_dt_ids[] = { | 477 | static const struct of_device_id mcp320x_dt_ids[] = { |
| 372 | /* NOTE: The use of compatibles with no vendor prefix is deprecated. */ | 478 | /* NOTE: The use of compatibles with no vendor prefix is deprecated. */ |
| 373 | { | 479 | { .compatible = "mcp3001" }, |
| 374 | .compatible = "mcp3001", | 480 | { .compatible = "mcp3002" }, |
| 375 | .data = &mcp320x_chip_infos[mcp3001], | 481 | { .compatible = "mcp3004" }, |
| 376 | }, { | 482 | { .compatible = "mcp3008" }, |
| 377 | .compatible = "mcp3002", | 483 | { .compatible = "mcp3201" }, |
| 378 | .data = &mcp320x_chip_infos[mcp3002], | 484 | { .compatible = "mcp3202" }, |
| 379 | }, { | 485 | { .compatible = "mcp3204" }, |
| 380 | .compatible = "mcp3004", | 486 | { .compatible = "mcp3208" }, |
| 381 | .data = &mcp320x_chip_infos[mcp3004], | 487 | { .compatible = "mcp3301" }, |
| 382 | }, { | 488 | { .compatible = "microchip,mcp3001" }, |
| 383 | .compatible = "mcp3008", | 489 | { .compatible = "microchip,mcp3002" }, |
| 384 | .data = &mcp320x_chip_infos[mcp3008], | 490 | { .compatible = "microchip,mcp3004" }, |
| 385 | }, { | 491 | { .compatible = "microchip,mcp3008" }, |
| 386 | .compatible = "mcp3201", | 492 | { .compatible = "microchip,mcp3201" }, |
| 387 | .data = &mcp320x_chip_infos[mcp3201], | 493 | { .compatible = "microchip,mcp3202" }, |
| 388 | }, { | 494 | { .compatible = "microchip,mcp3204" }, |
| 389 | .compatible = "mcp3202", | 495 | { .compatible = "microchip,mcp3208" }, |
| 390 | .data = &mcp320x_chip_infos[mcp3202], | 496 | { .compatible = "microchip,mcp3301" }, |
| 391 | }, { | 497 | { .compatible = "microchip,mcp3550-50" }, |
| 392 | .compatible = "mcp3204", | 498 | { .compatible = "microchip,mcp3550-60" }, |
| 393 | .data = &mcp320x_chip_infos[mcp3204], | 499 | { .compatible = "microchip,mcp3551" }, |
| 394 | }, { | 500 | { .compatible = "microchip,mcp3553" }, |
| 395 | .compatible = "mcp3208", | 501 | { } |
| 396 | .data = &mcp320x_chip_infos[mcp3208], | ||
| 397 | }, { | ||
| 398 | .compatible = "mcp3301", | ||
| 399 | .data = &mcp320x_chip_infos[mcp3301], | ||
| 400 | }, { | ||
| 401 | .compatible = "microchip,mcp3001", | ||
| 402 | .data = &mcp320x_chip_infos[mcp3001], | ||
| 403 | }, { | ||
| 404 | .compatible = "microchip,mcp3002", | ||
| 405 | .data = &mcp320x_chip_infos[mcp3002], | ||
| 406 | }, { | ||
| 407 | .compatible = "microchip,mcp3004", | ||
| 408 | .data = &mcp320x_chip_infos[mcp3004], | ||
| 409 | }, { | ||
| 410 | .compatible = "microchip,mcp3008", | ||
| 411 | .data = &mcp320x_chip_infos[mcp3008], | ||
| 412 | }, { | ||
| 413 | .compatible = "microchip,mcp3201", | ||
| 414 | .data = &mcp320x_chip_infos[mcp3201], | ||
| 415 | }, { | ||
| 416 | .compatible = "microchip,mcp3202", | ||
| 417 | .data = &mcp320x_chip_infos[mcp3202], | ||
| 418 | }, { | ||
| 419 | .compatible = "microchip,mcp3204", | ||
| 420 | .data = &mcp320x_chip_infos[mcp3204], | ||
| 421 | }, { | ||
| 422 | .compatible = "microchip,mcp3208", | ||
| 423 | .data = &mcp320x_chip_infos[mcp3208], | ||
| 424 | }, { | ||
| 425 | .compatible = "microchip,mcp3301", | ||
| 426 | .data = &mcp320x_chip_infos[mcp3301], | ||
| 427 | }, { | ||
| 428 | } | ||
| 429 | }; | 502 | }; |
| 430 | MODULE_DEVICE_TABLE(of, mcp320x_dt_ids); | 503 | MODULE_DEVICE_TABLE(of, mcp320x_dt_ids); |
| 431 | #endif | 504 | #endif |
| @@ -440,6 +513,10 @@ static const struct spi_device_id mcp320x_id[] = { · 8 unmodified lines | |||
| 440 | { "mcp3204", mcp3204 }, | 513 | { "mcp3204", mcp3204 }, |
| 441 | { "mcp3208", mcp3208 }, | 514 | { "mcp3208", mcp3208 }, |
| 442 | { "mcp3301", mcp3301 }, | 515 | { "mcp3301", mcp3301 }, |
| 516 | { "mcp3550-50", mcp3550_50 }, | ||
| 517 | { "mcp3550-60", mcp3550_60 }, | ||
| 518 | { "mcp3551", mcp3551 }, | ||
| 519 | { "mcp3553", mcp3553 }, | ||
| 443 | { } | 520 | { } |
| 444 | }; | 521 | }; |
| 445 | MODULE_DEVICE_TABLE(spi, mcp320x_id); | 522 | MODULE_DEVICE_TABLE(spi, mcp320x_id); |
| @@ -456,5 +533,5 @@ static struct spi_driver mcp320x_driver = { · 10 unmodified lines | |||
| 456 | module_spi_driver(mcp320x_driver); | 533 | module_spi_driver(mcp320x_driver); |
| 457 | 534 | ||
| 458 | MODULE_AUTHOR("Oskar Andero <oskar.andero@gmail.com>"); | 535 | MODULE_AUTHOR("Oskar Andero <oskar.andero@gmail.com>"); |
| 459 | MODULE_DESCRIPTION("Microchip Technology MCP3x01/02/04/08"); | 536 | MODULE_DESCRIPTION("Microchip Technology MCP3x01/02/04/08 and MCP3550/1/3"); |
| 460 | MODULE_LICENSE("GPL v2"); | 537 | MODULE_LICENSE("GPL v2"); |
| @@ -327,7 +327,6 @@ static const struct iio_info mcp3422_info = { · 326 unmodified lines | |||
| 327 | .write_raw = mcp3422_write_raw, | 327 | .write_raw = mcp3422_write_raw, |
| 328 | .write_raw_get_fmt = mcp3422_write_raw_get_fmt, | 328 | .write_raw_get_fmt = mcp3422_write_raw_get_fmt, |
| 329 | .attrs = &mcp3422_attribute_group, | 329 | .attrs = &mcp3422_attribute_group, |
| 330 | .driver_module = THIS_MODULE, | ||
| 331 | }; | 330 | }; |
| 332 | 331 | ||
| 333 | static int mcp3422_probe(struct i2c_client *client, | 332 | static int mcp3422_probe(struct i2c_client *client, |
| @@ -80,7 +80,6 @@ static int z188_iio_read_raw(struct iio_dev *iio_dev, · 79 unmodified lines | |||
| 80 | 80 | ||
| 81 | static const struct iio_info z188_adc_info = { | 81 | static const struct iio_info z188_adc_info = { |
| 82 | .read_raw = &z188_iio_read_raw, | 82 | .read_raw = &z188_iio_read_raw, |
| 83 | .driver_module = THIS_MODULE, | ||
| 84 | }; | 83 | }; |
| 85 | 84 | ||
| 86 | static void men_z188_config_channels(void __iomem *addr) | 85 | static void men_z188_config_channels(void __iomem *addr) |
| @@ -840,7 +840,6 @@ out: · 839 unmodified lines | |||
| 840 | 840 | ||
| 841 | static const struct iio_info meson_sar_adc_iio_info = { | 841 | static const struct iio_info meson_sar_adc_iio_info = { |
| 842 | .read_raw = meson_sar_adc_iio_info_read_raw, | 842 | .read_raw = meson_sar_adc_iio_info_read_raw, |
| 843 | .driver_module = THIS_MODULE, | ||
| 844 | }; | 843 | }; |
| 845 | 844 | ||
| 846 | static const struct meson_sar_adc_data meson_sar_adc_meson8_data = { | 845 | static const struct meson_sar_adc_data meson_sar_adc_meson8_data = { |
| @@ -180,7 +180,6 @@ static int mt6577_auxadc_read_raw(struct iio_dev *indio_dev, · 179 unmodified lines | |||
| 180 | } | 180 | } |
| 181 | 181 | ||
| 182 | static const struct iio_info mt6577_auxadc_info = { | 182 | static const struct iio_info mt6577_auxadc_info = { |
| 183 | .driver_module = THIS_MODULE, | ||
| 184 | .read_raw = &mt6577_auxadc_read_raw, | 183 | .read_raw = &mt6577_auxadc_read_raw, |
| 185 | }; | 184 | }; |
| 186 | 185 | ||
| @@ -306,6 +305,7 @@ static SIMPLE_DEV_PM_OPS(mt6577_auxadc_pm_ops, · 119 unmodified lines | |||
| 306 | 305 | ||
| 307 | static const struct of_device_id mt6577_auxadc_of_match[] = { | 306 | static const struct of_device_id mt6577_auxadc_of_match[] = { |
| 308 | { .compatible = "mediatek,mt2701-auxadc", }, | 307 | { .compatible = "mediatek,mt2701-auxadc", }, |
| 308 | { .compatible = "mediatek,mt2712-auxadc", }, | ||
| 309 | { .compatible = "mediatek,mt7622-auxadc", }, | 309 | { .compatible = "mediatek,mt7622-auxadc", }, |
| 310 | { .compatible = "mediatek,mt8173-auxadc", }, | 310 | { .compatible = "mediatek,mt8173-auxadc", }, |
| 311 | { } | 311 | { } |
| @@ -382,7 +382,6 @@ static const struct attribute_group mxs_lradc_adc_attribute_group = { · 381 unmodified lines | |||
| 382 | }; | 382 | }; |
| 383 | 383 | ||
| 384 | static const struct iio_info mxs_lradc_adc_iio_info = { | 384 | static const struct iio_info mxs_lradc_adc_iio_info = { |
| 385 | .driver_module = THIS_MODULE, | ||
| 386 | .read_raw = mxs_lradc_adc_read_raw, | 385 | .read_raw = mxs_lradc_adc_read_raw, |
| 387 | .write_raw = mxs_lradc_adc_write_raw, | 386 | .write_raw = mxs_lradc_adc_write_raw, |
| 388 | .write_raw_get_fmt = mxs_lradc_adc_write_raw_get_fmt, | 387 | .write_raw_get_fmt = mxs_lradc_adc_write_raw_get_fmt, |
| @@ -455,7 +454,6 @@ static int mxs_lradc_adc_configure_trigger(struct iio_trigger *trig, bool state) · 66 unmodified lines | |||
| 455 | } | 454 | } |
| 456 | 455 | ||
| 457 | static const struct iio_trigger_ops mxs_lradc_adc_trigger_ops = { | 456 | static const struct iio_trigger_ops mxs_lradc_adc_trigger_ops = { |
| 458 | .owner = THIS_MODULE, | ||
| 459 | .set_trigger_state = &mxs_lradc_adc_configure_trigger, | 457 | .set_trigger_state = &mxs_lradc_adc_configure_trigger, |
| 460 | }; | 458 | }; |
| 461 | 459 | ||
| @@ -402,7 +402,6 @@ static int nau7802_write_raw_get_fmt(struct iio_dev *indio_dev, · 401 unmodified lines | |||
| 402 | } | 402 | } |
| 403 | 403 | ||
| 404 | static const struct iio_info nau7802_info = { | 404 | static const struct iio_info nau7802_info = { |
| 405 | .driver_module = THIS_MODULE, | ||
| 406 | .read_raw = &nau7802_read_raw, | 405 | .read_raw = &nau7802_read_raw, |
| 407 | .write_raw = &nau7802_write_raw, | 406 | .write_raw = &nau7802_write_raw, |
| 408 | .write_raw_get_fmt = nau7802_write_raw_get_fmt, | 407 | .write_raw_get_fmt = nau7802_write_raw_get_fmt, |
| @@ -430,7 +430,6 @@ out: · 429 unmodified lines | |||
| 430 | 430 | ||
| 431 | static const struct iio_info palmas_gpadc_iio_info = { | 431 | static const struct iio_info palmas_gpadc_iio_info = { |
| 432 | .read_raw = palmas_gpadc_read_raw, | 432 | .read_raw = palmas_gpadc_read_raw, |
| 433 | .driver_module = THIS_MODULE, | ||
| 434 | }; | 433 | }; |
| 435 | 434 | ||
| 436 | #define PALMAS_ADC_CHAN_IIO(chan, _type, chan_info) \ | 435 | #define PALMAS_ADC_CHAN_IIO(chan, _type, chan_info) \ |
| @@ -728,7 +728,6 @@ static int pm8xxx_of_xlate(struct iio_dev *indio_dev, · 727 unmodified lines | |||
| 728 | } | 728 | } |
| 729 | 729 | ||
| 730 | static const struct iio_info pm8xxx_xoadc_info = { | 730 | static const struct iio_info pm8xxx_xoadc_info = { |
| 731 | .driver_module = THIS_MODULE, | ||
| 732 | .of_xlate = pm8xxx_of_xlate, | 731 | .of_xlate = pm8xxx_of_xlate, |
| 733 | .read_raw = pm8xxx_read_raw, | 732 | .read_raw = pm8xxx_read_raw, |
| 734 | }; | 733 | }; |
| @@ -356,7 +356,6 @@ static int iadc_read_raw(struct iio_dev *indio_dev, · 355 unmodified lines | |||
| 356 | 356 | ||
| 357 | static const struct iio_info iadc_info = { | 357 | static const struct iio_info iadc_info = { |
| 358 | .read_raw = iadc_read_raw, | 358 | .read_raw = iadc_read_raw, |
| 359 | .driver_module = THIS_MODULE, | ||
| 360 | }; | 359 | }; |
| 361 | 360 | ||
| 362 | static irqreturn_t iadc_isr(int irq, void *dev_id) | 361 | static irqreturn_t iadc_isr(int irq, void *dev_id) |
| @@ -506,7 +506,6 @@ static int vadc_of_xlate(struct iio_dev *indio_dev, · 505 unmodified lines | |||
| 506 | static const struct iio_info vadc_info = { | 506 | static const struct iio_info vadc_info = { |
| 507 | .read_raw = vadc_read_raw, | 507 | .read_raw = vadc_read_raw, |
| 508 | .of_xlate = vadc_of_xlate, | 508 | .of_xlate = vadc_of_xlate, |
| 509 | .driver_module = THIS_MODULE, | ||
| 510 | }; | 509 | }; |
| 511 | 510 | ||
| 512 | struct vadc_channels { | 511 | struct vadc_channels { |
| @@ -277,7 +277,6 @@ static int rcar_gyroadc_reg_access(struct iio_dev *indio_dev, · 276 unmodified lines | |||
| 277 | } | 277 | } |
| 278 | 278 | ||
| 279 | static const struct iio_info rcar_gyroadc_iio_info = { | 279 | static const struct iio_info rcar_gyroadc_iio_info = { |
| 280 | .driver_module = THIS_MODULE, | ||
| 281 | .read_raw = rcar_gyroadc_read_raw, | 280 | .read_raw = rcar_gyroadc_read_raw, |
| 282 | .debugfs_reg_access = rcar_gyroadc_reg_access, | 281 | .debugfs_reg_access = rcar_gyroadc_reg_access, |
| 283 | }; | 282 | }; |
| @@ -349,7 +348,7 @@ static int rcar_gyroadc_parse_subdevs(struct iio_dev *indio_dev) · 65 unmodified lines | |||
| 349 | continue; | 348 | continue; |
| 350 | } | 349 | } |
| 351 | 350 | ||
| 352 | childmode = (unsigned int)of_id->data; | 351 | childmode = (uintptr_t)of_id->data; |
| 353 | switch (childmode) { | 352 | switch (childmode) { |
| 354 | case RCAR_GYROADC_MODE_SELECT_1_MB88101A: | 353 | case RCAR_GYROADC_MODE_SELECT_1_MB88101A: |
| 355 | sample_width = 12; | 354 | sample_width = 12; |
| @@ -488,8 +487,6 @@ err: · 132 unmodified lines | |||
| 488 | 487 | ||
| 489 | static int rcar_gyroadc_probe(struct platform_device *pdev) | 488 | static int rcar_gyroadc_probe(struct platform_device *pdev) |
| 490 | { | 489 | { |
| 491 | const struct of_device_id *of_id = | ||
| 492 | of_match_device(rcar_gyroadc_match, &pdev->dev); | ||
| 493 | struct device *dev = &pdev->dev; | 490 | struct device *dev = &pdev->dev; |
| 494 | struct rcar_gyroadc *priv; | 491 | struct rcar_gyroadc *priv; |
| 495 | struct iio_dev *indio_dev; | 492 | struct iio_dev *indio_dev; |
| @@ -526,7 +523,8 @@ static int rcar_gyroadc_probe(struct platform_device *pdev) · 30 unmodified lines | |||
| 526 | if (ret) | 523 | if (ret) |
| 527 | return ret; | 524 | return ret; |
| 528 | 525 | ||
| 529 | priv->model = (enum rcar_gyroadc_model)of_id->data; | 526 | priv->model = (enum rcar_gyroadc_model) |
| 527 | of_device_get_match_data(&pdev->dev); | ||
| 530 | 528 | ||
| 531 | platform_set_drvdata(pdev, indio_dev); | 529 | platform_set_drvdata(pdev, indio_dev); |
| 532 | 530 | ||
| @@ -125,7 +125,6 @@ static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id) · 124 unmodified lines | |||
| 125 | 125 | ||
| 126 | static const struct iio_info rockchip_saradc_iio_info = { | 126 | static const struct iio_info rockchip_saradc_iio_info = { |
| 127 | .read_raw = rockchip_saradc_read_raw, | 127 | .read_raw = rockchip_saradc_read_raw, |
| 128 | .driver_module = THIS_MODULE, | ||
| 129 | }; | 128 | }; |
| 130 | 129 | ||
| 131 | #define ADC_CHANNEL(_index, _id) { \ | 130 | #define ADC_CHANNEL(_index, _id) { \ |
| @@ -254,7 +254,6 @@ static int spear_adc_configure(struct spear_adc_state *st) · 253 unmodified lines | |||
| 254 | static const struct iio_info spear_adc_info = { | 254 | static const struct iio_info spear_adc_info = { |
| 255 | .read_raw = &spear_adc_read_raw, | 255 | .read_raw = &spear_adc_read_raw, |
| 256 | .write_raw = &spear_adc_write_raw, | 256 | .write_raw = &spear_adc_write_raw, |
| 257 | .driver_module = THIS_MODULE, | ||
| 258 | }; | 257 | }; |
| 259 | 258 | ||
| 260 | static int spear_adc_probe(struct platform_device *pdev) | 259 | static int spear_adc_probe(struct platform_device *pdev) |
| @@ -139,6 +139,11 @@ static int stm32f4_adc_clk_sel(struct platform_device *pdev, · 138 unmodified lines | |||
| 139 | } | 139 | } |
| 140 | 140 | ||
| 141 | rate = clk_get_rate(priv->aclk); | 141 | rate = clk_get_rate(priv->aclk); |
| 142 | if (!rate) { | ||
| 143 | dev_err(&pdev->dev, "Invalid clock rate: 0\n"); | ||
| 144 | return -EINVAL; | ||
| 145 | } | ||
| 146 | |||
| 142 | for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) { | 147 | for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) { |
| 143 | if ((rate / stm32f4_pclk_div[i]) <= STM32F4_ADC_MAX_CLK_RATE) | 148 | if ((rate / stm32f4_pclk_div[i]) <= STM32F4_ADC_MAX_CLK_RATE) |
| 144 | break; | 149 | break; |
| @@ -216,6 +221,10 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev, · 71 unmodified lines | |||
| 216 | * From spec: PLL output musn't exceed max rate | 221 | * From spec: PLL output musn't exceed max rate |
| 217 | */ | 222 | */ |
| 218 | rate = clk_get_rate(priv->aclk); | 223 | rate = clk_get_rate(priv->aclk); |
| 224 | if (!rate) { | ||
| 225 | dev_err(&pdev->dev, "Invalid adc clock rate: 0\n"); | ||
| 226 | return -EINVAL; | ||
| 227 | } | ||
| 219 | 228 | ||
| 220 | for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { | 229 | for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { |
| 221 | ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; | 230 | ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; |
| @@ -232,6 +241,10 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev, · 10 unmodified lines | |||
| 232 | 241 | ||
| 233 | /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */ | 242 | /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */ |
| 234 | rate = clk_get_rate(priv->bclk); | 243 | rate = clk_get_rate(priv->bclk); |
| 244 | if (!rate) { | ||
| 245 | dev_err(&pdev->dev, "Invalid bus clock rate: 0\n"); | ||
| 246 | return -EINVAL; | ||
| 247 | } | ||
| 235 | 248 | ||
| 236 | for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { | 249 | for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { |
| 237 | ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; | 250 | ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; |
| @@ -531,6 +531,7 @@ static struct stm32_adc_trig_info stm32h7_adc_trigs[] = { · 530 unmodified lines | |||
| 531 | { TIM2_TRGO, STM32_EXT11 }, | 531 | { TIM2_TRGO, STM32_EXT11 }, |
| 532 | { TIM4_TRGO, STM32_EXT12 }, | 532 | { TIM4_TRGO, STM32_EXT12 }, |
| 533 | { TIM6_TRGO, STM32_EXT13 }, | 533 | { TIM6_TRGO, STM32_EXT13 }, |
| 534 | { TIM15_TRGO, STM32_EXT14 }, | ||
| 534 | { TIM3_CH4, STM32_EXT15 }, | 535 | { TIM3_CH4, STM32_EXT15 }, |
| 535 | { LPTIM1_OUT, STM32_EXT18 }, | 536 | { LPTIM1_OUT, STM32_EXT18 }, |
| 536 | { LPTIM2_OUT, STM32_EXT19 }, | 537 | { LPTIM2_OUT, STM32_EXT19 }, |
| @@ -1385,7 +1386,6 @@ static const struct iio_info stm32_adc_iio_info = { · 848 unmodified lines | |||
| 1385 | .update_scan_mode = stm32_adc_update_scan_mode, | 1386 | .update_scan_mode = stm32_adc_update_scan_mode, |
| 1386 | .debugfs_reg_access = stm32_adc_debugfs_reg_access, | 1387 | .debugfs_reg_access = stm32_adc_debugfs_reg_access, |
| 1387 | .of_xlate = stm32_adc_of_xlate, | 1388 | .of_xlate = stm32_adc_of_xlate, |
| 1388 | .driver_module = THIS_MODULE, | ||
| 1389 | }; | 1389 | }; |
| 1390 | 1390 | ||
| 1391 | static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc) | 1391 | static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc) |
| @@ -172,7 +172,6 @@ static int stx104_write_raw(struct iio_dev *indio_dev, · 171 unmodified lines | |||
| 172 | } | 172 | } |
| 173 | 173 | ||
| 174 | static const struct iio_info stx104_info = { | 174 | static const struct iio_info stx104_info = { |
| 175 | .driver_module = THIS_MODULE, | ||
| 176 | .read_raw = stx104_read_raw, | 175 | .read_raw = stx104_read_raw, |
| 177 | .write_raw = stx104_write_raw | 176 | .write_raw = stx104_write_raw |
| 178 | }; | 177 | }; |
| @@ -352,7 +352,6 @@ static int sun4i_gpadc_read_raw(struct iio_dev *indio_dev, · 351 unmodified lines | |||
| 352 | 352 | ||
| 353 | static const struct iio_info sun4i_gpadc_iio_info = { | 353 | static const struct iio_info sun4i_gpadc_iio_info = { |
| 354 | .read_raw = sun4i_gpadc_read_raw, | 354 | .read_raw = sun4i_gpadc_read_raw, |
| 355 | .driver_module = THIS_MODULE, | ||
| 356 | }; | 355 | }; |
| 357 | 356 | ||
| 358 | static irqreturn_t sun4i_gpadc_temp_data_irq_handler(int irq, void *dev_id) | 357 | static irqreturn_t sun4i_gpadc_temp_data_irq_handler(int irq, void *dev_id) |
| @@ -502,17 +501,15 @@ static int sun4i_gpadc_probe_dt(struct platform_device *pdev, · 143 unmodified lines | |||
| 502 | struct iio_dev *indio_dev) | 501 | struct iio_dev *indio_dev) |
| 503 | { | 502 | { |
| 504 | struct sun4i_gpadc_iio *info = iio_priv(indio_dev); | 503 | struct sun4i_gpadc_iio *info = iio_priv(indio_dev); |
| 505 | const struct of_device_id *of_dev; | ||
| 506 | struct resource *mem; | 504 | struct resource *mem; |
| 507 | void __iomem *base; | 505 | void __iomem *base; |
| 508 | int ret; | 506 | int ret; |
| 509 | 507 | ||
| 510 | of_dev = of_match_device(sun4i_gpadc_of_id, &pdev->dev); | 508 | info->data = of_device_get_match_data(&pdev->dev); |
| 511 | if (!of_dev) | 509 | if (!info->data) |
| 512 | return -ENODEV; | 510 | return -ENODEV; |
| 513 | 511 | ||
| 514 | info->no_irq = true; | 512 | info->no_irq = true; |
| 515 | info->data = (struct gpadc_data *)of_dev->data; | ||
| 516 | indio_dev->num_channels = ARRAY_SIZE(sun8i_a33_gpadc_channels); | 513 | indio_dev->num_channels = ARRAY_SIZE(sun8i_a33_gpadc_channels); |
| 517 | indio_dev->channels = sun8i_a33_gpadc_channels; | 514 | indio_dev->channels = sun8i_a33_gpadc_channels; |
| 518 | 515 | ||
| @@ -529,17 +526,10 @@ static int sun4i_gpadc_probe_dt(struct platform_device *pdev, · 10 unmodified lines | |||
| 529 | return ret; | 526 | return ret; |
| 530 | } | 527 | } |
| 531 | 528 | ||
| 532 | if (!IS_ENABLED(CONFIG_THERMAL_OF)) | 529 | if (IS_ENABLED(CONFIG_THERMAL_OF)) |
| 533 | return 0; | 530 | info->sensor_device = &pdev->dev; |
| 534 | 531 | ||
| 535 | info->sensor_device = &pdev->dev; | 532 | return 0; |
| 536 | info->tzd = thermal_zone_of_sensor_register(info->sensor_device, 0, | ||
| 537 | info, &sun4i_ts_tz_ops); | ||
| 538 | if (IS_ERR(info->tzd)) | ||
| 539 | dev_err(&pdev->dev, "could not register thermal sensor: %ld\n", | ||
| 540 | PTR_ERR(info->tzd)); | ||
| 541 | |||
| 542 | return PTR_ERR_OR_ZERO(info->tzd); | ||
| 543 | } | 533 | } |
| 544 | 534 | ||
| 545 | static int sun4i_gpadc_probe_mfd(struct platform_device *pdev, | 535 | static int sun4i_gpadc_probe_mfd(struct platform_device *pdev, |
| @@ -586,15 +576,6 @@ static int sun4i_gpadc_probe_mfd(struct platform_device *pdev, · 40 unmodified lines | |||
| 586 | * return the temperature. | 576 | * return the temperature. |
| 587 | */ | 577 | */ |
| 588 | info->sensor_device = pdev->dev.parent; | 578 | info->sensor_device = pdev->dev.parent; |
| 589 | info->tzd = thermal_zone_of_sensor_register(info->sensor_device, | ||
| 590 | 0, info, | ||
| 591 | &sun4i_ts_tz_ops); | ||
| 592 | if (IS_ERR(info->tzd)) { | ||
| 593 | dev_err(&pdev->dev, | ||
| 594 | "could not register thermal sensor: %ld\n", | ||
| 595 | PTR_ERR(info->tzd)); | ||
| 596 | return PTR_ERR(info->tzd); | ||
| 597 | } | ||
| 598 | } else { | 579 | } else { |
| 599 | indio_dev->num_channels = | 580 | indio_dev->num_channels = |
| 600 | ARRAY_SIZE(sun4i_gpadc_channels_no_temp); | 581 | ARRAY_SIZE(sun4i_gpadc_channels_no_temp); |
| @@ -664,6 +645,22 @@ static int sun4i_gpadc_probe(struct platform_device *pdev) · 63 unmodified lines | |||
| 664 | pm_runtime_set_suspended(&pdev->dev); | 645 | pm_runtime_set_suspended(&pdev->dev); |
| 665 | pm_runtime_enable(&pdev->dev); | 646 | pm_runtime_enable(&pdev->dev); |
| 666 | 647 | ||
| 648 | if (IS_ENABLED(CONFIG_THERMAL_OF)) { | ||
| 649 | info->tzd = thermal_zone_of_sensor_register(info->sensor_device, | ||
| 650 | 0, info, | ||
| 651 | &sun4i_ts_tz_ops); | ||
| 652 | /* | ||
| 653 | * Do not fail driver probing when failing to register in | ||
| 654 | * thermal because no thermal DT node is found. | ||
| 655 | */ | ||
| 656 | if (IS_ERR(info->tzd) && PTR_ERR(info->tzd) != -ENODEV) { | ||
| 657 | dev_err(&pdev->dev, | ||
| 658 | "could not register thermal sensor: %ld\n", | ||
| 659 | PTR_ERR(info->tzd)); | ||
| 660 | return PTR_ERR(info->tzd); | ||
| 661 | } | ||
| 662 | } | ||
| 663 | |||
| 667 | ret = devm_iio_device_register(&pdev->dev, indio_dev); | 664 | ret = devm_iio_device_register(&pdev->dev, indio_dev); |
| 668 | if (ret < 0) { | 665 | if (ret < 0) { |
| 669 | dev_err(&pdev->dev, "could not register the device\n"); | 666 | dev_err(&pdev->dev, "could not register the device\n"); |
| @@ -124,7 +124,6 @@ static struct adcxx1c_model adcxx1c_models[] = { · 123 unmodified lines | |||
| 124 | 124 | ||
| 125 | static const struct iio_info adc081c_info = { | 125 | static const struct iio_info adc081c_info = { |
| 126 | .read_raw = adc081c_read_raw, | 126 | .read_raw = adc081c_read_raw, |
| 127 | .driver_module = THIS_MODULE, | ||
| 128 | }; | 127 | }; |
| 129 | 128 | ||
| 130 | static irqreturn_t adc081c_trigger_handler(int irq, void *p) | 129 | static irqreturn_t adc081c_trigger_handler(int irq, void *p) |
| @@ -195,7 +195,6 @@ static int adc0832_read_raw(struct iio_dev *iio, · 194 unmodified lines | |||
| 195 | 195 | ||
| 196 | static const struct iio_info adc0832_info = { | 196 | static const struct iio_info adc0832_info = { |
| 197 | .read_raw = adc0832_read_raw, | 197 | .read_raw = adc0832_read_raw, |
| 198 | .driver_module = THIS_MODULE, | ||
| 199 | }; | 198 | }; |
| 200 | 199 | ||
| 201 | static irqreturn_t adc0832_trigger_handler(int irq, void *p) | 200 | static irqreturn_t adc0832_trigger_handler(int irq, void *p) |
| @@ -186,7 +186,6 @@ static int adc084s021_buffer_postdisable(struct iio_dev *indio_dev) · 185 unmodified lines | |||
| 186 | 186 | ||
| 187 | static const struct iio_info adc084s021_info = { | 187 | static const struct iio_info adc084s021_info = { |
| 188 | .read_raw = adc084s021_read_raw, | 188 | .read_raw = adc084s021_read_raw, |
| 189 | .driver_module = THIS_MODULE, | ||
| 190 | }; | 189 | }; |
| 191 | 190 | ||
| 192 | static const struct iio_buffer_setup_ops adc084s021_buffer_setup_ops = { | 191 | static const struct iio_buffer_setup_ops adc084s021_buffer_setup_ops = { |
| @@ -220,7 +220,6 @@ static int adc108s102_read_raw(struct iio_dev *indio_dev, · 219 unmodified lines | |||
| 220 | static const struct iio_info adc108s102_info = { | 220 | static const struct iio_info adc108s102_info = { |
| 221 | .read_raw = &adc108s102_read_raw, | 221 | .read_raw = &adc108s102_read_raw, |
| 222 | .update_scan_mode = &adc108s102_update_scan_mode, | 222 | .update_scan_mode = &adc108s102_update_scan_mode, |
| 223 | .driver_module = THIS_MODULE, | ||
| 224 | }; | 223 | }; |
| 225 | 224 | ||
| 226 | static int adc108s102_probe(struct spi_device *spi) | 225 | static int adc108s102_probe(struct spi_device *spi) |
| @@ -164,7 +164,7 @@ static int __adc12138_start_conv(struct adc12138 *adc, · 163 unmodified lines | |||
| 164 | void *data, int len) | 164 | void *data, int len) |
| 165 | 165 | ||
| 166 | { | 166 | { |
| 167 | const u8 ch_to_mux[] = { 0, 4, 1, 5, 2, 6, 3, 7 }; | 167 | static const u8 ch_to_mux[] = { 0, 4, 1, 5, 2, 6, 3, 7 }; |
| 168 | u8 mode = (ch_to_mux[channel->channel] << 4) | | 168 | u8 mode = (ch_to_mux[channel->channel] << 4) | |
| 169 | (channel->differential ? 0 : 0x80); | 169 | (channel->differential ? 0 : 0x80); |
| 170 | 170 | ||
| @@ -277,7 +277,6 @@ static int adc12138_read_raw(struct iio_dev *iio, · 106 unmodified lines | |||
| 277 | 277 | ||
| 278 | static const struct iio_info adc12138_info = { | 278 | static const struct iio_info adc12138_info = { |
| 279 | .read_raw = adc12138_read_raw, | 279 | .read_raw = adc12138_read_raw, |
| 280 | .driver_module = THIS_MODULE, | ||
| 281 | }; | 280 | }; |
| 282 | 281 | ||
| 283 | static int adc12138_init(struct adc12138 *adc) | 282 | static int adc12138_init(struct adc12138 *adc) |
| @@ -130,7 +130,6 @@ static const struct adc128_configuration adc128_config[] = { · 129 unmodified lines | |||
| 130 | 130 | ||
| 131 | static const struct iio_info adc128_info = { | 131 | static const struct iio_info adc128_info = { |
| 132 | .read_raw = adc128_read_raw, | 132 | .read_raw = adc128_read_raw, |
| 133 | .driver_module = THIS_MODULE, | ||
| 134 | }; | 133 | }; |
| 135 | 134 | ||
| 136 | static int adc128_probe(struct spi_device *spi) | 135 | static int adc128_probe(struct spi_device *spi) |
| @@ -173,7 +173,6 @@ static int ti_adc_read_raw(struct iio_dev *indio_dev, · 172 unmodified lines | |||
| 173 | } | 173 | } |
| 174 | 174 | ||
| 175 | static const struct iio_info ti_adc_info = { | 175 | static const struct iio_info ti_adc_info = { |
| 176 | .driver_module = THIS_MODULE, | ||
| 177 | .read_raw = ti_adc_read_raw, | 176 | .read_raw = ti_adc_read_raw, |
| 178 | }; | 177 | }; |
| 179 | 178 | ||
| @@ -332,7 +332,7 @@ static int ads1015_set_power_state(struct ads1015_data *data, bool on) · 331 unmodified lines | |||
| 332 | static | 332 | static |
| 333 | int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val) | 333 | int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val) |
| 334 | { | 334 | { |
| 335 | int ret, pga, dr, conv_time; | 335 | int ret, pga, dr, dr_old, conv_time; |
| 336 | unsigned int old, mask, cfg; | 336 | unsigned int old, mask, cfg; |
| 337 | 337 | ||
| 338 | if (chan < 0 || chan >= ADS1015_CHANNELS) | 338 | if (chan < 0 || chan >= ADS1015_CHANNELS) |
| @@ -358,17 +358,17 @@ int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val) · 19 unmodified lines | |||
| 358 | } | 358 | } |
| 359 | 359 | ||
| 360 | cfg = (old & ~mask) | (cfg & mask); | 360 | cfg = (old & ~mask) | (cfg & mask); |
| 361 | 361 | if (old != cfg) { | |
| 362 | ret = regmap_write(data->regmap, ADS1015_CFG_REG, cfg); | 362 | ret = regmap_write(data->regmap, ADS1015_CFG_REG, cfg); |
| 363 | if (ret) | 363 | if (ret) |
| 364 | return ret; | 364 | return ret; |
| 365 | 365 | data->conv_invalid = true; | |
| 366 | if (old != cfg || data->conv_invalid) { | 366 | } |
| 367 | int dr_old = (old & ADS1015_CFG_DR_MASK) >> | 367 | if (data->conv_invalid) { |
| 368 | ADS1015_CFG_DR_SHIFT; | 368 | dr_old = (old & ADS1015_CFG_DR_MASK) >> ADS1015_CFG_DR_SHIFT; |
| 369 | |||
| 370 | conv_time = DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr_old]); | 369 | conv_time = DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr_old]); |
| 371 | conv_time += DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr]); | 370 | conv_time += DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr]); |
| 371 | conv_time += conv_time / 10; /* 10% internal clock inaccuracy */ | ||
| 372 | usleep_range(conv_time, conv_time + 1); | 372 | usleep_range(conv_time, conv_time + 1); |
| 373 | data->conv_invalid = false; | 373 | data->conv_invalid = false; |
| 374 | } | 374 | } |
| @@ -821,7 +821,6 @@ static const struct attribute_group ads1115_attribute_group = { · 446 unmodified lines | |||
| 821 | }; | 821 | }; |
| 822 | 822 | ||
| 823 | static const struct iio_info ads1015_info = { | 823 | static const struct iio_info ads1015_info = { |
| 824 | .driver_module = THIS_MODULE, | ||
| 825 | .read_raw = ads1015_read_raw, | 824 | .read_raw = ads1015_read_raw, |
| 826 | .write_raw = ads1015_write_raw, | 825 | .write_raw = ads1015_write_raw, |
| 827 | .read_event_value = ads1015_read_event, | 826 | .read_event_value = ads1015_read_event, |
| @@ -832,7 +831,6 @@ static const struct iio_info ads1015_info = { · 4 unmodified lines | |||
| 832 | }; | 831 | }; |
| 833 | 832 | ||
| 834 | static const struct iio_info ads1115_info = { | 833 | static const struct iio_info ads1115_info = { |
| 835 | .driver_module = THIS_MODULE, | ||
| 836 | .read_raw = ads1015_read_raw, | 834 | .read_raw = ads1015_read_raw, |
| 837 | .write_raw = ads1015_write_raw, | 835 | .write_raw = ads1015_write_raw, |
| 838 | .read_event_value = ads1015_read_event, | 836 | .read_event_value = ads1015_read_event, |
| @@ -372,7 +372,6 @@ static int ti_ads7950_read_raw(struct iio_dev *indio_dev, · 371 unmodified lines | |||
| 372 | static const struct iio_info ti_ads7950_info = { | 372 | static const struct iio_info ti_ads7950_info = { |
| 373 | .read_raw = &ti_ads7950_read_raw, | 373 | .read_raw = &ti_ads7950_read_raw, |
| 374 | .update_scan_mode = ti_ads7950_update_scan_mode, | 374 | .update_scan_mode = ti_ads7950_update_scan_mode, |
| 375 | .driver_module = THIS_MODULE, | ||
| 376 | }; | 375 | }; |
| 377 | 376 | ||
| 378 | static int ti_ads7950_probe(struct spi_device *spi) | 377 | static int ti_ads7950_probe(struct spi_device *spi) |
| @@ -369,7 +369,6 @@ static const struct iio_info ads8688_info = { · 368 unmodified lines | |||
| 369 | .write_raw = &ads8688_write_raw, | 369 | .write_raw = &ads8688_write_raw, |
| 370 | .write_raw_get_fmt = &ads8688_write_raw_get_fmt, | 370 | .write_raw_get_fmt = &ads8688_write_raw_get_fmt, |
| 371 | .attrs = &ads8688_attribute_group, | 371 | .attrs = &ads8688_attribute_group, |
| 372 | .driver_module = THIS_MODULE, | ||
| 373 | }; | 372 | }; |
| 374 | 373 | ||
| 375 | static const struct ads8688_chip_info ads8688_chip_info_tbl[] = { | 374 | static const struct ads8688_chip_info ads8688_chip_info_tbl[] = { |
| @@ -474,7 +473,6 @@ MODULE_DEVICE_TABLE(of, ads8688_of_match); · 98 unmodified lines | |||
| 474 | static struct spi_driver ads8688_driver = { | 473 | static struct spi_driver ads8688_driver = { |
| 475 | .driver = { | 474 | .driver = { |
| 476 | .name = "ads8688", | 475 | .name = "ads8688", |
| 477 | .owner = THIS_MODULE, | ||
| 478 | }, | 476 | }, |
| 479 | .probe = ads8688_probe, | 477 | .probe = ads8688_probe, |
| 480 | .remove = ads8688_remove, | 478 | .remove = ads8688_remove, |
| @@ -157,7 +157,6 @@ static int tlc4541_read_raw(struct iio_dev *indio_dev, · 156 unmodified lines | |||
| 157 | 157 | ||
| 158 | static const struct iio_info tlc4541_info = { | 158 | static const struct iio_info tlc4541_info = { |
| 159 | .read_raw = &tlc4541_read_raw, | 159 | .read_raw = &tlc4541_read_raw, |
| 160 | .driver_module = THIS_MODULE, | ||
| 161 | }; | 160 | }; |
| 162 | 161 | ||
| 163 | static int tlc4541_probe(struct spi_device *spi) | 162 | static int tlc4541_probe(struct spi_device *spi) |
| @@ -533,7 +533,6 @@ err_unlock: · 532 unmodified lines | |||
| 533 | 533 | ||
| 534 | static const struct iio_info tiadc_info = { | 534 | static const struct iio_info tiadc_info = { |
| 535 | .read_raw = &tiadc_read_raw, | 535 | .read_raw = &tiadc_read_raw, |
| 536 | .driver_module = THIS_MODULE, | ||
| 537 | }; | 536 | }; |
| 538 | 537 | ||
| 539 | static int tiadc_request_dma(struct platform_device *pdev, | 538 | static int tiadc_request_dma(struct platform_device *pdev, |
| @@ -212,7 +212,6 @@ static int twl4030_madc_read(struct iio_dev *iio_dev, · 211 unmodified lines | |||
| 212 | 212 | ||
| 213 | static const struct iio_info twl4030_madc_iio_info = { | 213 | static const struct iio_info twl4030_madc_iio_info = { |
| 214 | .read_raw = &twl4030_madc_read, | 214 | .read_raw = &twl4030_madc_read, |
| 215 | .driver_module = THIS_MODULE, | ||
| 216 | }; | 215 | }; |
| 217 | 216 | ||
| 218 | #define TWL4030_ADC_CHANNEL(_channel, _type, _name) { \ | 217 | #define TWL4030_ADC_CHANNEL(_channel, _type, _name) { \ |
| @@ -843,7 +843,6 @@ static const struct iio_chan_spec twl6032_gpadc_iio_channels[] = { · 842 unmodified lines | |||
| 843 | 843 | ||
| 844 | static const struct iio_info twl6030_gpadc_iio_info = { | 844 | static const struct iio_info twl6030_gpadc_iio_info = { |
| 845 | .read_raw = &twl6030_gpadc_read_raw, | 845 | .read_raw = &twl6030_gpadc_read_raw, |
| 846 | .driver_module = THIS_MODULE, | ||
| 847 | }; | 846 | }; |
| 848 | 847 | ||
| 849 | static const struct twl6030_gpadc_platform_data twl6030_pdata = { | 848 | static const struct twl6030_gpadc_platform_data twl6030_pdata = { |
| @@ -799,7 +799,6 @@ static int vf610_adc_reg_access(struct iio_dev *indio_dev, · 798 unmodified lines | |||
| 799 | } | 799 | } |
| 800 | 800 | ||
| 801 | static const struct iio_info vf610_adc_iio_info = { | 801 | static const struct iio_info vf610_adc_iio_info = { |
| 802 | .driver_module = THIS_MODULE, | ||
| 803 | .read_raw = &vf610_read_raw, | 802 | .read_raw = &vf610_read_raw, |
| 804 | .write_raw = &vf610_write_raw, | 803 | .write_raw = &vf610_write_raw, |
| 805 | .debugfs_reg_access = &vf610_adc_reg_access, | 804 | .debugfs_reg_access = &vf610_adc_reg_access, |
| @@ -107,7 +107,6 @@ error: · 106 unmodified lines | |||
| 107 | 107 | ||
| 108 | static const struct iio_info vprbrd_adc_iio_info = { | 108 | static const struct iio_info vprbrd_adc_iio_info = { |
| 109 | .read_raw = &vprbrd_iio_read_raw, | 109 | .read_raw = &vprbrd_iio_read_raw, |
| 110 | .driver_module = THIS_MODULE, | ||
| 111 | }; | 110 | }; |
| 112 | 111 | ||
| 113 | static int vprbrd_adc_probe(struct platform_device *pdev) | 112 | static int vprbrd_adc_probe(struct platform_device *pdev) |
| @@ -675,7 +675,6 @@ err_out: · 674 unmodified lines | |||
| 675 | } | 675 | } |
| 676 | 676 | ||
| 677 | static const struct iio_trigger_ops xadc_trigger_ops = { | 677 | static const struct iio_trigger_ops xadc_trigger_ops = { |
| 678 | .owner = THIS_MODULE, | ||
| 679 | .set_trigger_state = &xadc_trigger_set_state, | 678 | .set_trigger_state = &xadc_trigger_set_state, |
| 680 | }; | 679 | }; |
| 681 | 680 | ||
| @@ -1028,7 +1027,6 @@ static const struct iio_info xadc_info = { · 346 unmodified lines | |||
| 1028 | .read_event_value = &xadc_read_event_value, | 1027 | .read_event_value = &xadc_read_event_value, |
| 1029 | .write_event_value = &xadc_write_event_value, | 1028 | .write_event_value = &xadc_write_event_value, |
| 1030 | .update_scan_mode = &xadc_update_scan_mode, | 1029 | .update_scan_mode = &xadc_update_scan_mode, |
| 1031 | .driver_module = THIS_MODULE, | ||
| 1032 | }; | 1030 | }; |
| 1033 | 1031 | ||
| 1034 | static const struct of_device_id xadc_of_match_table[] = { | 1032 | static const struct of_device_id xadc_of_match_table[] = { |
| @@ -117,7 +117,6 @@ static int ad8366_write_raw(struct iio_dev *indio_dev, · 116 unmodified lines | |||
| 117 | static const struct iio_info ad8366_info = { | 117 | static const struct iio_info ad8366_info = { |
| 118 | .read_raw = &ad8366_read_raw, | 118 | .read_raw = &ad8366_read_raw, |
| 119 | .write_raw = &ad8366_write_raw, | 119 | .write_raw = &ad8366_write_raw, |
| 120 | .driver_module = THIS_MODULE, | ||
| 121 | }; | 120 | }; |
| 122 | 121 | ||
| 123 | #define AD8366_CHAN(_channel) { \ | 122 | #define AD8366_CHAN(_channel) { \ |
| @@ -141,7 +141,6 @@ err_out: · 140 unmodified lines | |||
| 141 | 141 | ||
| 142 | static const struct iio_info ams_iaqcore_info = { | 142 | static const struct iio_info ams_iaqcore_info = { |
| 143 | .read_raw = ams_iaqcore_read_raw, | 143 | .read_raw = ams_iaqcore_read_raw, |
| 144 | .driver_module = THIS_MODULE, | ||
| 145 | }; | 144 | }; |
| 146 | 145 | ||
| 147 | static int ams_iaqcore_probe(struct i2c_client *client, | 146 | static int ams_iaqcore_probe(struct i2c_client *client, |
| @@ -344,7 +344,6 @@ static int atlas_buffer_predisable(struct iio_dev *indio_dev) · 343 unmodified lines | |||
| 344 | } | 344 | } |
| 345 | 345 | ||
| 346 | static const struct iio_trigger_ops atlas_interrupt_trigger_ops = { | 346 | static const struct iio_trigger_ops atlas_interrupt_trigger_ops = { |
| 347 | .owner = THIS_MODULE, | ||
| 348 | }; | 347 | }; |
| 349 | 348 | ||
| 350 | static const struct iio_buffer_setup_ops atlas_buffer_setup_ops = { | 349 | static const struct iio_buffer_setup_ops atlas_buffer_setup_ops = { |
| @@ -499,7 +498,6 @@ static int atlas_write_raw(struct iio_dev *indio_dev, · 148 unmodified lines | |||
| 499 | } | 498 | } |
| 500 | 499 | ||
| 501 | static const struct iio_info atlas_info = { | 500 | static const struct iio_info atlas_info = { |
| 502 | .driver_module = THIS_MODULE, | ||
| 503 | .read_raw = atlas_read_raw, | 501 | .read_raw = atlas_read_raw, |
| 504 | .write_raw = atlas_write_raw, | 502 | .write_raw = atlas_write_raw, |
| 505 | }; | 503 | }; |
| @@ -22,6 +22,7 @@ · 21 unmodified lines | |||
| 22 | #include <linux/i2c.h> | 22 | #include <linux/i2c.h> |
| 23 | #include <linux/iio/iio.h> | 23 | #include <linux/iio/iio.h> |
| 24 | #include <linux/iio/buffer.h> | 24 | #include <linux/iio/buffer.h> |
| 25 | #include <linux/iio/trigger.h> | ||
| 25 | #include <linux/iio/triggered_buffer.h> | 26 | #include <linux/iio/triggered_buffer.h> |
| 26 | #include <linux/iio/trigger_consumer.h> | 27 | #include <linux/iio/trigger_consumer.h> |
| 27 | #include <linux/module.h> | 28 | #include <linux/module.h> |
| @@ -59,6 +60,8 @@ · 31 unmodified lines | |||
| 59 | #define CCS811_MODE_IAQ_60SEC 0x30 | 60 | #define CCS811_MODE_IAQ_60SEC 0x30 |
| 60 | #define CCS811_MODE_RAW_DATA 0x40 | 61 | #define CCS811_MODE_RAW_DATA 0x40 |
| 61 | 62 | ||
| 63 | #define CCS811_MEAS_MODE_INTERRUPT BIT(3) | ||
| 64 | |||
| 62 | #define CCS811_VOLTAGE_MASK 0x3FF | 65 | #define CCS811_VOLTAGE_MASK 0x3FF |
| 63 | 66 | ||
| 64 | struct ccs811_reading { | 67 | struct ccs811_reading { |
| @@ -73,6 +76,8 @@ struct ccs811_data { · 8 unmodified lines | |||
| 73 | struct i2c_client *client; | 76 | struct i2c_client *client; |
| 74 | struct mutex lock; /* Protect readings */ | 77 | struct mutex lock; /* Protect readings */ |
| 75 | struct ccs811_reading buffer; | 78 | struct ccs811_reading buffer; |
| 79 | struct iio_trigger *drdy_trig; | ||
| 80 | bool drdy_trig_on; | ||
| 76 | }; | 81 | }; |
| 77 | 82 | ||
| 78 | static const struct iio_chan_spec ccs811_channels[] = { | 83 | static const struct iio_chan_spec ccs811_channels[] = { |
| @@ -193,10 +198,14 @@ static int ccs811_read_raw(struct iio_dev *indio_dev, · 114 unmodified lines | |||
| 193 | 198 | ||
| 194 | switch (mask) { | 199 | switch (mask) { |
| 195 | case IIO_CHAN_INFO_RAW: | 200 | case IIO_CHAN_INFO_RAW: |
| 201 | ret = iio_device_claim_direct_mode(indio_dev); | ||
| 202 | if (ret) | ||
| 203 | return ret; | ||
| 196 | mutex_lock(&data->lock); | 204 | mutex_lock(&data->lock); |
| 197 | ret = ccs811_get_measurement(data); | 205 | ret = ccs811_get_measurement(data); |
| 198 | if (ret < 0) { | 206 | if (ret < 0) { |
| 199 | mutex_unlock(&data->lock); | 207 | mutex_unlock(&data->lock); |
| 208 | iio_device_release_direct_mode(indio_dev); | ||
| 200 | return ret; | 209 | return ret; |
| 201 | } | 210 | } |
| 202 | 211 | ||
| @@ -228,6 +237,7 @@ static int ccs811_read_raw(struct iio_dev *indio_dev, · 25 unmodified lines | |||
| 228 | ret = -EINVAL; | 237 | ret = -EINVAL; |
| 229 | } | 238 | } |
| 230 | mutex_unlock(&data->lock); | 239 | mutex_unlock(&data->lock); |
| 240 | iio_device_release_direct_mode(indio_dev); | ||
| 231 | 241 | ||
| 232 | return ret; | 242 | return ret; |
| 233 | 243 | ||
| @@ -270,7 +280,31 @@ static int ccs811_read_raw(struct iio_dev *indio_dev, · 36 unmodified lines | |||
| 270 | 280 | ||
| 271 | static const struct iio_info ccs811_info = { | 281 | static const struct iio_info ccs811_info = { |
| 272 | .read_raw = ccs811_read_raw, | 282 | .read_raw = ccs811_read_raw, |
| 273 | .driver_module = THIS_MODULE, | 283 | }; |
| 284 | |||
| 285 | static int ccs811_set_trigger_state(struct iio_trigger *trig, | ||
| 286 | bool state) | ||
| 287 | { | ||
| 288 | struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); | ||
| 289 | struct ccs811_data *data = iio_priv(indio_dev); | ||
| 290 | int ret; | ||
| 291 | |||
| 292 | ret = i2c_smbus_read_byte_data(data->client, CCS811_MEAS_MODE); | ||
| 293 | if (ret < 0) | ||
| 294 | return ret; | ||
| 295 | |||
| 296 | if (state) | ||
| 297 | ret |= CCS811_MEAS_MODE_INTERRUPT; | ||
| 298 | else | ||
| 299 | ret &= ~CCS811_MEAS_MODE_INTERRUPT; | ||
| 300 | |||
| 301 | data->drdy_trig_on = state; | ||
| 302 | |||
| 303 | return i2c_smbus_write_byte_data(data->client, CCS811_MEAS_MODE, ret); | ||
| 304 | } | ||
| 305 | |||
| 306 | static const struct iio_trigger_ops ccs811_trigger_ops = { | ||
| 307 | .set_trigger_state = ccs811_set_trigger_state, | ||
| 274 | }; | 308 | }; |
| 275 | 309 | ||
| 276 | static irqreturn_t ccs811_trigger_handler(int irq, void *p) | 310 | static irqreturn_t ccs811_trigger_handler(int irq, void *p) |
| @@ -298,6 +332,17 @@ err: · 21 unmodified lines | |||
| 298 | return IRQ_HANDLED; | 332 | return IRQ_HANDLED; |
| 299 | } | 333 | } |
| 300 | 334 | ||
| 335 | static irqreturn_t ccs811_data_rdy_trigger_poll(int irq, void *private) | ||
| 336 | { | ||
| 337 | struct iio_dev *indio_dev = private; | ||
| 338 | struct ccs811_data *data = iio_priv(indio_dev); | ||
| 339 | |||
| 340 | if (data->drdy_trig_on) | ||
| 341 | iio_trigger_poll(data->drdy_trig); | ||
| 342 | |||
| 343 | return IRQ_HANDLED; | ||
| 344 | } | ||
| 345 | |||
| 301 | static int ccs811_probe(struct i2c_client *client, | 346 | static int ccs811_probe(struct i2c_client *client, |
| 302 | const struct i2c_device_id *id) | 347 | const struct i2c_device_id *id) |
| 303 | { | 348 | { |
| @@ -346,16 +391,48 @@ static int ccs811_probe(struct i2c_client *client, · 42 unmodified lines | |||
| 346 | indio_dev->dev.parent = &client->dev; | 391 | indio_dev->dev.parent = &client->dev; |
| 347 | indio_dev->name = id->name; | 392 | indio_dev->name = id->name; |
| 348 | indio_dev->info = &ccs811_info; | 393 | indio_dev->info = &ccs811_info; |
| 394 | indio_dev->modes = INDIO_DIRECT_MODE; | ||
| 349 | 395 | ||
| 350 | indio_dev->channels = ccs811_channels; | 396 | indio_dev->channels = ccs811_channels; |
| 351 | indio_dev->num_channels = ARRAY_SIZE(ccs811_channels); | 397 | indio_dev->num_channels = ARRAY_SIZE(ccs811_channels); |
| 352 | 398 | ||
| 399 | if (client->irq > 0) { | ||
| 400 | ret = devm_request_threaded_irq(&client->dev, client->irq, | ||
| 401 | ccs811_data_rdy_trigger_poll, | ||
| 402 | NULL, | ||
| 403 | IRQF_TRIGGER_FALLING | | ||
| 404 | IRQF_ONESHOT, | ||
| 405 | "ccs811_irq", indio_dev); | ||
| 406 | if (ret) { | ||
| 407 | dev_err(&client->dev, "irq request error %d\n", -ret); | ||
| 408 | goto err_poweroff; | ||
| 409 | } | ||
| 410 | |||
| 411 | data->drdy_trig = devm_iio_trigger_alloc(&client->dev, | ||
| 412 | "%s-dev%d", | ||
| 413 | indio_dev->name, | ||
| 414 | indio_dev->id); | ||
| 415 | if (!data->drdy_trig) { | ||
| 416 | ret = -ENOMEM; | ||
| 417 | goto err_poweroff; | ||
| 418 | } | ||
| 419 | |||
| 420 | data->drdy_trig->dev.parent = &client->dev; | ||
| 421 | data->drdy_trig->ops = &ccs811_trigger_ops; | ||
| 422 | iio_trigger_set_drvdata(data->drdy_trig, indio_dev); | ||
| 423 | indio_dev->trig = data->drdy_trig; | ||
| 424 | iio_trigger_get(indio_dev->trig); | ||
| 425 | ret = iio_trigger_register(data->drdy_trig); | ||
| 426 | if (ret) | ||
| 427 | goto err_poweroff; | ||
| 428 | } | ||
| 429 | |||
| 353 | ret = iio_triggered_buffer_setup(indio_dev, NULL, | 430 | ret = iio_triggered_buffer_setup(indio_dev, NULL, |
| 354 | ccs811_trigger_handler, NULL); | 431 | ccs811_trigger_handler, NULL); |
| 355 | 432 | ||
| 356 | if (ret < 0) { | 433 | if (ret < 0) { |
| 357 | dev_err(&client->dev, "triggered buffer setup failed\n"); | 434 | dev_err(&client->dev, "triggered buffer setup failed\n"); |
| 358 | goto err_poweroff; | 435 | goto err_trigger_unregister; |
| 359 | } | 436 | } |
| 360 | 437 | ||
| 361 | ret = iio_device_register(indio_dev); | 438 | ret = iio_device_register(indio_dev); |
| @@ -367,6 +444,9 @@ static int ccs811_probe(struct i2c_client *client, · 5 unmodified lines | |||
| 367 | 444 | ||
| 368 | err_buffer_cleanup: | 445 | err_buffer_cleanup: |
| 369 | iio_triggered_buffer_cleanup(indio_dev); | 446 | iio_triggered_buffer_cleanup(indio_dev); |
| 447 | err_trigger_unregister: | ||
| 448 | if (data->drdy_trig) | ||
| 449 | iio_trigger_unregister(data->drdy_trig); | ||
| 370 | err_poweroff: | 450 | err_poweroff: |
| 371 | i2c_smbus_write_byte_data(client, CCS811_MEAS_MODE, CCS811_MODE_IDLE); | 451 | i2c_smbus_write_byte_data(client, CCS811_MEAS_MODE, CCS811_MODE_IDLE); |
| 372 | 452 | ||
| @@ -376,9 +456,12 @@ err_poweroff: · 3 unmodified lines | |||
| 376 | static int ccs811_remove(struct i2c_client *client) | 456 | static int ccs811_remove(struct i2c_client *client) |
| 377 | { | 457 | { |
| 378 | struct iio_dev *indio_dev = i2c_get_clientdata(client); | 458 | struct iio_dev *indio_dev = i2c_get_clientdata(client); |
| 459 | struct ccs811_data *data = iio_priv(indio_dev); | ||
| 379 | 460 | ||
| 380 | iio_device_unregister(indio_dev); | 461 | iio_device_unregister(indio_dev); |
| 381 | iio_triggered_buffer_cleanup(indio_dev); | 462 | iio_triggered_buffer_cleanup(indio_dev); |
| 463 | if (data->drdy_trig) | ||
| 464 | iio_trigger_unregister(data->drdy_trig); | ||
| 382 | 465 | ||
| 383 | return i2c_smbus_write_byte_data(client, CCS811_MEAS_MODE, | 466 | return i2c_smbus_write_byte_data(client, CCS811_MEAS_MODE, |
| 384 | CCS811_MODE_IDLE); | 467 | CCS811_MODE_IDLE); |
| @@ -326,7 +326,6 @@ static int vz89x_read_raw(struct iio_dev *indio_dev, · 325 unmodified lines | |||
| 326 | static const struct iio_info vz89x_info = { | 326 | static const struct iio_info vz89x_info = { |
| 327 | .attrs = &vz89x_attrs_group, | 327 | .attrs = &vz89x_attrs_group, |
| 328 | .read_raw = vz89x_read_raw, | 328 | .read_raw = vz89x_read_raw, |
| 329 | .driver_module = THIS_MODULE, | ||
| 330 | }; | 329 | }; |
| 331 | 330 | ||
| 332 | static const struct vz89x_chip_data vz89x_chips[] = { | 331 | static const struct vz89x_chip_data vz89x_chips[] = { |
| @@ -185,7 +185,6 @@ static int cros_ec_sensors_write(struct iio_dev *indio_dev, · 184 unmodified lines | |||
| 185 | static const struct iio_info ec_sensors_info = { | 185 | static const struct iio_info ec_sensors_info = { |
| 186 | .read_raw = &cros_ec_sensors_read, | 186 | .read_raw = &cros_ec_sensors_read, |
| 187 | .write_raw = &cros_ec_sensors_write, | 187 | .write_raw = &cros_ec_sensors_write, |
| 188 | .driver_module = THIS_MODULE, | ||
| 189 | }; | 188 | }; |
| 190 | 189 | ||
| 191 | static int cros_ec_sensors_probe(struct platform_device *pdev) | 190 | static int cros_ec_sensors_probe(struct platform_device *pdev) |
| @@ -179,6 +179,10 @@ int hid_sensor_power_state(struct hid_sensor_common *st, bool state) · 178 unmodified lines | |||
| 179 | int ret; | 179 | int ret; |
| 180 | 180 | ||
| 181 | atomic_set(&st->user_requested_state, state); | 181 | atomic_set(&st->user_requested_state, state); |
| 182 | |||
| 183 | if (atomic_add_unless(&st->runtime_pm_enable, 1, 1)) | ||
| 184 | pm_runtime_enable(&st->pdev->dev); | ||
| 185 | |||
| 182 | if (state) | 186 | if (state) |
| 183 | ret = pm_runtime_get_sync(&st->pdev->dev); | 187 | ret = pm_runtime_get_sync(&st->pdev->dev); |
| 184 | else { | 188 | else { |
| @@ -221,7 +225,8 @@ static void hid_sensor_set_power_work(struct work_struct *work) · 36 unmodified lines | |||
| 221 | if (attrb->latency_ms > 0) | 225 | if (attrb->latency_ms > 0) |
| 222 | hid_sensor_set_report_latency(attrb, attrb->latency_ms); | 226 | hid_sensor_set_report_latency(attrb, attrb->latency_ms); |
| 223 | 227 | ||
| 224 | _hid_sensor_power_state(attrb, true); | 228 | if (atomic_read(&attrb->user_requested_state)) |
| 229 | _hid_sensor_power_state(attrb, true); | ||
| 225 | } | 230 | } |
| 226 | 231 | ||
| 227 | static int hid_sensor_data_rdy_trigger_set_state(struct iio_trigger *trig, | 232 | static int hid_sensor_data_rdy_trigger_set_state(struct iio_trigger *trig, |
| @@ -232,7 +237,9 @@ static int hid_sensor_data_rdy_trigger_set_state(struct iio_trigger *trig, · 4 unmodified lines | |||
| 232 | 237 | ||
| 233 | void hid_sensor_remove_trigger(struct hid_sensor_common *attrb) | 238 | void hid_sensor_remove_trigger(struct hid_sensor_common *attrb) |
| 234 | { | 239 | { |
| 235 | pm_runtime_disable(&attrb->pdev->dev); | 240 | if (atomic_read(&attrb->runtime_pm_enable)) |
| 241 | pm_runtime_disable(&attrb->pdev->dev); | ||
| 242 | |||
| 236 | pm_runtime_set_suspended(&attrb->pdev->dev); | 243 | pm_runtime_set_suspended(&attrb->pdev->dev); |
| 237 | pm_runtime_put_noidle(&attrb->pdev->dev); | 244 | pm_runtime_put_noidle(&attrb->pdev->dev); |
| 238 | 245 | ||
| @@ -243,7 +250,6 @@ void hid_sensor_remove_trigger(struct hid_sensor_common *attrb) · 4 unmodified lines | |||
| 243 | EXPORT_SYMBOL(hid_sensor_remove_trigger); | 250 | EXPORT_SYMBOL(hid_sensor_remove_trigger); |
| 244 | 251 | ||
| 245 | static const struct iio_trigger_ops hid_sensor_trigger_ops = { | 252 | static const struct iio_trigger_ops hid_sensor_trigger_ops = { |
| 246 | .owner = THIS_MODULE, | ||
| 247 | .set_trigger_state = &hid_sensor_data_rdy_trigger_set_state, | 253 | .set_trigger_state = &hid_sensor_data_rdy_trigger_set_state, |
| 248 | }; | 254 | }; |
| 249 | 255 | ||
| @@ -283,7 +289,6 @@ int hid_sensor_setup_trigger(struct iio_dev *indio_dev, const char *name, · 33 unmodified lines | |||
| 283 | INIT_WORK(&attrb->work, hid_sensor_set_power_work); | 289 | INIT_WORK(&attrb->work, hid_sensor_set_power_work); |
| 284 | 290 | ||
| 285 | pm_suspend_ignore_children(&attrb->pdev->dev, true); | 291 | pm_suspend_ignore_children(&attrb->pdev->dev, true); |
| 286 | pm_runtime_enable(&attrb->pdev->dev); | ||
| 287 | /* Default to 3 seconds, but can be changed from sysfs */ | 292 | /* Default to 3 seconds, but can be changed from sysfs */ |
| 288 | pm_runtime_set_autosuspend_delay(&attrb->pdev->dev, | 293 | pm_runtime_set_autosuspend_delay(&attrb->pdev->dev, |
| 289 | 3000); | 294 | 3000); |
| @@ -93,6 +93,9 @@ int st_sensors_set_odr(struct iio_dev *indio_dev, unsigned int odr) · 92 unmodified lines | |||
| 93 | struct st_sensor_odr_avl odr_out = {0, 0}; | 93 | struct st_sensor_odr_avl odr_out = {0, 0}; |
| 94 | struct st_sensor_data *sdata = iio_priv(indio_dev); | 94 | struct st_sensor_data *sdata = iio_priv(indio_dev); |
| 95 | 95 | ||
| 96 | if (!sdata->sensor_settings->odr.addr) | ||
| 97 | return 0; | ||
| 98 | |||
| 96 | err = st_sensors_match_odr(sdata->sensor_settings, odr, &odr_out); | 99 | err = st_sensors_match_odr(sdata->sensor_settings, odr, &odr_out); |
| 97 | if (err < 0) | 100 | if (err < 0) |
| 98 | goto st_sensors_match_odr_error; | 101 | goto st_sensors_match_odr_error; |
| @@ -221,11 +224,14 @@ EXPORT_SYMBOL(st_sensors_set_enable); · 122 unmodified lines | |||
| 221 | int st_sensors_set_axis_enable(struct iio_dev *indio_dev, u8 axis_enable) | 224 | int st_sensors_set_axis_enable(struct iio_dev *indio_dev, u8 axis_enable) |
| 222 | { | 225 | { |
| 223 | struct st_sensor_data *sdata = iio_priv(indio_dev); | 226 | struct st_sensor_data *sdata = iio_priv(indio_dev); |
| 227 | int err = 0; | ||
| 224 | 228 | ||
| 225 | return st_sensors_write_data_with_mask(indio_dev, | 229 | if (sdata->sensor_settings->enable_axis.addr) |
| 230 | err = st_sensors_write_data_with_mask(indio_dev, | ||
| 226 | sdata->sensor_settings->enable_axis.addr, | 231 | sdata->sensor_settings->enable_axis.addr, |
| 227 | sdata->sensor_settings->enable_axis.mask, | 232 | sdata->sensor_settings->enable_axis.mask, |
| 228 | axis_enable); | 233 | axis_enable); |
| 234 | return err; | ||
| 229 | } | 235 | } |
| 230 | EXPORT_SYMBOL(st_sensors_set_axis_enable); | 236 | EXPORT_SYMBOL(st_sensors_set_axis_enable); |
| 231 | 237 | ||
| @@ -283,7 +289,8 @@ static int st_sensors_set_drdy_int_pin(struct iio_dev *indio_dev, · 51 unmodified lines | |||
| 283 | struct st_sensor_data *sdata = iio_priv(indio_dev); | 289 | struct st_sensor_data *sdata = iio_priv(indio_dev); |
| 284 | 290 | ||
| 285 | /* Sensor does not support interrupts */ | 291 | /* Sensor does not support interrupts */ |
| 286 | if (sdata->sensor_settings->drdy_irq.addr == 0) { | 292 | if (!sdata->sensor_settings->drdy_irq.int1.addr && |
| 293 | !sdata->sensor_settings->drdy_irq.int2.addr) { | ||
| 287 | if (pdata->drdy_int_pin) | 294 | if (pdata->drdy_int_pin) |
| 288 | dev_info(&indio_dev->dev, | 295 | dev_info(&indio_dev->dev, |
| 289 | "DRDY on pin INT%d specified, but sensor " | 296 | "DRDY on pin INT%d specified, but sensor " |
| @@ -294,7 +301,7 @@ static int st_sensors_set_drdy_int_pin(struct iio_dev *indio_dev, · 4 unmodified lines | |||
| 294 | 301 | ||
| 295 | switch (pdata->drdy_int_pin) { | 302 | switch (pdata->drdy_int_pin) { |
| 296 | case 1: | 303 | case 1: |
| 297 | if (sdata->sensor_settings->drdy_irq.mask_int1 == 0) { | 304 | if (!sdata->sensor_settings->drdy_irq.int1.mask) { |
| 298 | dev_err(&indio_dev->dev, | 305 | dev_err(&indio_dev->dev, |
| 299 | "DRDY on INT1 not available.\n"); | 306 | "DRDY on INT1 not available.\n"); |
| 300 | return -EINVAL; | 307 | return -EINVAL; |
| @@ -302,7 +309,7 @@ static int st_sensors_set_drdy_int_pin(struct iio_dev *indio_dev, · 1 unmodified line | |||
| 302 | sdata->drdy_int_pin = 1; | 309 | sdata->drdy_int_pin = 1; |
| 303 | break; | 310 | break; |
| 304 | case 2: | 311 | case 2: |
| 305 | if (sdata->sensor_settings->drdy_irq.mask_int2 == 0) { | 312 | if (!sdata->sensor_settings->drdy_irq.int2.mask) { |
| 306 | dev_err(&indio_dev->dev, | 313 | dev_err(&indio_dev->dev, |
| 307 | "DRDY on INT2 not available.\n"); | 314 | "DRDY on INT2 not available.\n"); |
| 308 | return -EINVAL; | 315 | return -EINVAL; |
| @@ -315,7 +322,8 @@ static int st_sensors_set_drdy_int_pin(struct iio_dev *indio_dev, · 6 unmodified lines | |||
| 315 | } | 322 | } |
| 316 | 323 | ||
| 317 | if (pdata->open_drain) { | 324 | if (pdata->open_drain) { |
| 318 | if (!sdata->sensor_settings->drdy_irq.addr_od) | 325 | if (!sdata->sensor_settings->drdy_irq.int1.addr_od && |
| 326 | !sdata->sensor_settings->drdy_irq.int2.addr_od) | ||
| 319 | dev_err(&indio_dev->dev, | 327 | dev_err(&indio_dev->dev, |
| 320 | "open drain requested but unsupported.\n"); | 328 | "open drain requested but unsupported.\n"); |
| 321 | else | 329 | else |
| @@ -442,11 +450,21 @@ int st_sensors_init_sensor(struct iio_dev *indio_dev, · 120 unmodified lines | |||
| 442 | } | 450 | } |
| 443 | 451 | ||
| 444 | if (sdata->int_pin_open_drain) { | 452 | if (sdata->int_pin_open_drain) { |
| 453 | u8 addr, mask; | ||
| 454 | |||
| 455 | if (sdata->drdy_int_pin == 1) { | ||
| 456 | addr = sdata->sensor_settings->drdy_irq.int1.addr_od; | ||
| 457 | mask = sdata->sensor_settings->drdy_irq.int1.mask_od; | ||
| 458 | } else { | ||
| 459 | addr = sdata->sensor_settings->drdy_irq.int2.addr_od; | ||
| 460 | mask = sdata->sensor_settings->drdy_irq.int2.mask_od; | ||
| 461 | } | ||
| 462 | |||
| 445 | dev_info(&indio_dev->dev, | 463 | dev_info(&indio_dev->dev, |
| 446 | "set interrupt line to open drain mode\n"); | 464 | "set interrupt line to open drain mode on pin %d\n", |
| 447 | err = st_sensors_write_data_with_mask(indio_dev, | 465 | sdata->drdy_int_pin); |
| 448 | sdata->sensor_settings->drdy_irq.addr_od, | 466 | err = st_sensors_write_data_with_mask(indio_dev, addr, |
| 449 | sdata->sensor_settings->drdy_irq.mask_od, 1); | 467 | mask, 1); |
| 450 | if (err < 0) | 468 | if (err < 0) |
| 451 | return err; | 469 | return err; |
| 452 | } | 470 | } |
| @@ -460,17 +478,18 @@ EXPORT_SYMBOL(st_sensors_init_sensor); · 7 unmodified lines | |||
| 460 | int st_sensors_set_dataready_irq(struct iio_dev *indio_dev, bool enable) | 478 | int st_sensors_set_dataready_irq(struct iio_dev *indio_dev, bool enable) |
| 461 | { | 479 | { |
| 462 | int err; | 480 | int err; |
| 463 | u8 drdy_mask; | 481 | u8 drdy_addr, drdy_mask; |
| 464 | struct st_sensor_data *sdata = iio_priv(indio_dev); | 482 | struct st_sensor_data *sdata = iio_priv(indio_dev); |
| 465 | 483 | ||
| 466 | if (!sdata->sensor_settings->drdy_irq.addr) { | 484 | if (!sdata->sensor_settings->drdy_irq.int1.addr && |
| 485 | !sdata->sensor_settings->drdy_irq.int2.addr) { | ||
| 467 | /* | 486 | /* |
| 468 | * there are some devices (e.g. LIS3MDL) where drdy line is | 487 | * there are some devices (e.g. LIS3MDL) where drdy line is |
| 469 | * routed to a given pin and it is not possible to select a | 488 | * routed to a given pin and it is not possible to select a |
| 470 | * different one. Take into account irq status register | 489 | * different one. Take into account irq status register |
| 471 | * to understand if irq trigger can be properly supported | 490 | * to understand if irq trigger can be properly supported |
| 472 | */ | 491 | */ |
| 473 | if (sdata->sensor_settings->drdy_irq.addr_stat_drdy) | 492 | if (sdata->sensor_settings->drdy_irq.stat_drdy.addr) |
| 474 | sdata->hw_irq_trigger = enable; | 493 | sdata->hw_irq_trigger = enable; |
| 475 | return 0; | 494 | return 0; |
| 476 | } | 495 | } |
| @@ -485,18 +504,20 @@ int st_sensors_set_dataready_irq(struct iio_dev *indio_dev, bool enable) · 8 unmodified lines | |||
| 485 | goto st_accel_set_dataready_irq_error; | 504 | goto st_accel_set_dataready_irq_error; |
| 486 | } | 505 | } |
| 487 | 506 | ||
| 488 | if (sdata->drdy_int_pin == 1) | 507 | if (sdata->drdy_int_pin == 1) { |
| 489 | drdy_mask = sdata->sensor_settings->drdy_irq.mask_int1; | 508 | drdy_addr = sdata->sensor_settings->drdy_irq.int1.addr; |
| 490 | else | 509 | drdy_mask = sdata->sensor_settings->drdy_irq.int1.mask; |
| 491 | drdy_mask = sdata->sensor_settings->drdy_irq.mask_int2; | 510 | } else { |
| 511 | drdy_addr = sdata->sensor_settings->drdy_irq.int2.addr; | ||
| 512 | drdy_mask = sdata->sensor_settings->drdy_irq.int2.mask; | ||
| 513 | } | ||
| 492 | 514 | ||
| 493 | /* Flag to the poll function that the hardware trigger is in use */ | 515 | /* Flag to the poll function that the hardware trigger is in use */ |
| 494 | sdata->hw_irq_trigger = enable; | 516 | sdata->hw_irq_trigger = enable; |
| 495 | 517 | ||
| 496 | /* Enable/Disable the interrupt generator for data ready. */ | 518 | /* Enable/Disable the interrupt generator for data ready. */ |
| 497 | err = st_sensors_write_data_with_mask(indio_dev, | 519 | err = st_sensors_write_data_with_mask(indio_dev, drdy_addr, |
| 498 | sdata->sensor_settings->drdy_irq.addr, | 520 | drdy_mask, (int)enable); |
| 499 | drdy_mask, (int)enable); | ||
| 500 | 521 | ||
| 501 | st_accel_set_dataready_irq_error: | 522 | st_accel_set_dataready_irq_error: |
| 502 | return err; | 523 | return err; |
| @@ -31,7 +31,7 @@ static int st_sensors_new_samples_available(struct iio_dev *indio_dev, · 30 unmodified lines | |||
| 31 | int ret; | 31 | int ret; |
| 32 | 32 | ||
| 33 | /* How would I know if I can't check it? */ | 33 | /* How would I know if I can't check it? */ |
| 34 | if (!sdata->sensor_settings->drdy_irq.addr_stat_drdy) | 34 | if (!sdata->sensor_settings->drdy_irq.stat_drdy.addr) |
| 35 | return -EINVAL; | 35 | return -EINVAL; |
| 36 | 36 | ||
| 37 | /* No scan mask, no interrupt */ | 37 | /* No scan mask, no interrupt */ |
| @@ -39,23 +39,15 @@ static int st_sensors_new_samples_available(struct iio_dev *indio_dev, · 1 unmodified line | |||
| 39 | return 0; | 39 | return 0; |
| 40 | 40 | ||
| 41 | ret = sdata->tf->read_byte(&sdata->tb, sdata->dev, | 41 | ret = sdata->tf->read_byte(&sdata->tb, sdata->dev, |
| 42 | sdata->sensor_settings->drdy_irq.addr_stat_drdy, | 42 | sdata->sensor_settings->drdy_irq.stat_drdy.addr, |
| 43 | &status); | 43 | &status); |
| 44 | if (ret < 0) { | 44 | if (ret < 0) { |
| 45 | dev_err(sdata->dev, | 45 | dev_err(sdata->dev, |
| 46 | "error checking samples available\n"); | 46 | "error checking samples available\n"); |
| 47 | return ret; | 47 | return ret; |
| 48 | } | 48 | } |
| 49 | /* | ||
| 50 | * the lower bits of .active_scan_mask[0] is directly mapped | ||
| 51 | * to the channels on the sensor: either bit 0 for | ||
| 52 | * one-dimensional sensors, or e.g. x,y,z for accelerometers, | ||
| 53 | * gyroscopes or magnetometers. No sensor use more than 3 | ||
| 54 | * channels, so cut the other status bits here. | ||
| 55 | */ | ||
| 56 | status &= 0x07; | ||
| 57 | 49 | ||
| 58 | if (status & (u8)indio_dev->active_scan_mask[0]) | 50 | if (status & sdata->sensor_settings->drdy_irq.stat_drdy.mask) |
| 59 | return 1; | 51 | return 1; |
| 60 | 52 | ||
| 61 | return 0; | 53 | return 0; |
| @@ -212,7 +204,7 @@ int st_sensors_allocate_trigger(struct iio_dev *indio_dev, · 150 unmodified lines | |||
| 212 | * it was "our" interrupt. | 204 | * it was "our" interrupt. |
| 213 | */ | 205 | */ |
| 214 | if (sdata->int_pin_open_drain && | 206 | if (sdata->int_pin_open_drain && |
| 215 | sdata->sensor_settings->drdy_irq.addr_stat_drdy) | 207 | sdata->sensor_settings->drdy_irq.stat_drdy.addr) |
| 216 | irq_trig |= IRQF_SHARED; | 208 | irq_trig |= IRQF_SHARED; |
| 217 | 209 | ||
| 218 | err = request_threaded_irq(sdata->get_irq_data_ready(indio_dev), | 210 | err = request_threaded_irq(sdata->get_irq_data_ready(indio_dev), |
| @@ -185,7 +185,6 @@ static int quad8_write_raw(struct iio_dev *indio_dev, · 184 unmodified lines | |||
| 185 | } | 185 | } |
| 186 | 186 | ||
| 187 | static const struct iio_info quad8_info = { | 187 | static const struct iio_info quad8_info = { |
| 188 | .driver_module = THIS_MODULE, | ||
| 189 | .read_raw = quad8_read_raw, | 188 | .read_raw = quad8_read_raw, |
| 190 | .write_raw = quad8_write_raw | 189 | .write_raw = quad8_write_raw |
| 191 | }; | 190 | }; |
| @@ -178,7 +178,6 @@ static int stm32_lptim_read_raw(struct iio_dev *indio_dev, · 177 unmodified lines | |||
| 178 | static const struct iio_info stm32_lptim_cnt_iio_info = { | 178 | static const struct iio_info stm32_lptim_cnt_iio_info = { |
| 179 | .read_raw = stm32_lptim_read_raw, | 179 | .read_raw = stm32_lptim_read_raw, |
| 180 | .write_raw = stm32_lptim_write_raw, | 180 | .write_raw = stm32_lptim_write_raw, |
| 181 | .driver_module = THIS_MODULE, | ||
| 182 | }; | 181 | }; |
| 183 | 182 | ||
| 184 | static const char *const stm32_lptim_quadrature_modes[] = { | 183 | static const char *const stm32_lptim_quadrature_modes[] = { |
| @@ -60,7 +60,8 @@ config AD5446 · 59 unmodified lines | |||
| 60 | Say yes here to build support for Analog Devices AD5300, AD5301, AD5310, | 60 | Say yes here to build support for Analog Devices AD5300, AD5301, AD5310, |
| 61 | AD5311, AD5320, AD5321, AD5444, AD5446, AD5450, AD5451, AD5452, AD5453, | 61 | AD5311, AD5320, AD5321, AD5444, AD5446, AD5450, AD5451, AD5452, AD5453, |
| 62 | AD5512A, AD5541A, AD5542A, AD5543, AD5553, AD5601, AD5602, AD5611, AD5612, | 62 | AD5512A, AD5541A, AD5542A, AD5543, AD5553, AD5601, AD5602, AD5611, AD5612, |
| 63 | AD5620, AD5621, AD5622, AD5640, AD5641, AD5660, AD5662 DACs. | 63 | AD5620, AD5621, AD5622, AD5640, AD5641, AD5660, AD5662 DACs |
| 64 | as well as Texas Instruments DAC081S101, DAC101S101, DAC121S101. | ||
| 64 | 65 | ||
| 65 | To compile this driver as a module, choose M here: the | 66 | To compile this driver as a module, choose M here: the |
| 66 | module will be called ad5446. | 67 | module will be called ad5446. |
| @@ -221,6 +222,15 @@ config DPOT_DAC · 154 unmodified lines | |||
| 221 | To compile this driver as a module, choose M here: the module will be | 222 | To compile this driver as a module, choose M here: the module will be |
| 222 | called dpot-dac. | 223 | called dpot-dac. |
| 223 | 224 | ||
| 225 | config DS4424 | ||
| 226 | tristate "Maxim Integrated DS4422/DS4424 DAC driver" | ||
| 227 | depends on I2C | ||
| 228 | help | ||
| 229 | If you say yes here you get support for Maxim chips DS4422, DS4424. | ||
| 230 | |||
| 231 | This driver can also be built as a module. If so, the module | ||
| 232 | will be called ds4424. | ||
| 233 | |||
| 224 | config LPC18XX_DAC | 234 | config LPC18XX_DAC |
| 225 | tristate "NXP LPC18xx DAC driver" | 235 | tristate "NXP LPC18xx DAC driver" |
| 226 | depends on ARCH_LPC18XX || COMPILE_TEST | 236 | depends on ARCH_LPC18XX || COMPILE_TEST |
| @@ -300,6 +310,16 @@ config STM32_DAC · 73 unmodified lines | |||
| 300 | config STM32_DAC_CORE | 310 | config STM32_DAC_CORE |
| 301 | tristate | 311 | tristate |
| 302 | 312 | ||
| 313 | config TI_DAC082S085 | ||
| 314 | tristate "Texas Instruments 8/10/12-bit 2/4-channel DAC driver" | ||
| 315 | depends on SPI_MASTER | ||
| 316 | help | ||
| 317 | Driver for the Texas Instruments (formerly National Semiconductor) | ||
| 318 | DAC082S085, DAC102S085, DAC122S085, DAC084S085, DAC104S085 and | ||
| 319 | DAC124S085. | ||
| 320 | |||
| 321 | If compiled as a module, it will be called ti-dac082s085. | ||
| 322 | |||
| 303 | config VF610_DAC | 323 | config VF610_DAC |
| 304 | tristate "Vybrid vf610 DAC driver" | 324 | tristate "Vybrid vf610 DAC driver" |
| 305 | depends on OF | 325 | depends on OF |
| @@ -24,6 +24,7 @@ obj-$(CONFIG_AD7303) += ad7303.o · 23 unmodified lines | |||
| 24 | obj-$(CONFIG_AD8801) += ad8801.o | 24 | obj-$(CONFIG_AD8801) += ad8801.o |
| 25 | obj-$(CONFIG_CIO_DAC) += cio-dac.o | 25 | obj-$(CONFIG_CIO_DAC) += cio-dac.o |
| 26 | obj-$(CONFIG_DPOT_DAC) += dpot-dac.o | 26 | obj-$(CONFIG_DPOT_DAC) += dpot-dac.o |
| 27 | obj-$(CONFIG_DS4424) += ds4424.o | ||
| 27 | obj-$(CONFIG_LPC18XX_DAC) += lpc18xx_dac.o | 28 | obj-$(CONFIG_LPC18XX_DAC) += lpc18xx_dac.o |
| 28 | obj-$(CONFIG_LTC2632) += ltc2632.o | 29 | obj-$(CONFIG_LTC2632) += ltc2632.o |
| 29 | obj-$(CONFIG_M62332) += m62332.o | 30 | obj-$(CONFIG_M62332) += m62332.o |
| @@ -33,4 +34,5 @@ obj-$(CONFIG_MCP4725) += mcp4725.o · 3 unmodified lines | |||
| 33 | obj-$(CONFIG_MCP4922) += mcp4922.o | 34 | obj-$(CONFIG_MCP4922) += mcp4922.o |
| 34 | obj-$(CONFIG_STM32_DAC_CORE) += stm32-dac-core.o | 35 | obj-$(CONFIG_STM32_DAC_CORE) += stm32-dac-core.o |
| 35 | obj-$(CONFIG_STM32_DAC) += stm32-dac.o | 36 | obj-$(CONFIG_STM32_DAC) += stm32-dac.o |
| 37 | obj-$(CONFIG_TI_DAC082S085) += ti-dac082s085.o | ||
| 36 | obj-$(CONFIG_VF610_DAC) += vf610_dac.o | 38 | obj-$(CONFIG_VF610_DAC) += vf610_dac.o |
| @@ -366,7 +366,6 @@ static int ad5064_write_raw(struct iio_dev *indio_dev, · 365 unmodified lines | |||
| 366 | static const struct iio_info ad5064_info = { | 366 | static const struct iio_info ad5064_info = { |
| 367 | .read_raw = ad5064_read_raw, | 367 | .read_raw = ad5064_read_raw, |
| 368 | .write_raw = ad5064_write_raw, | 368 | .write_raw = ad5064_write_raw, |
| 369 | .driver_module = THIS_MODULE, | ||
| 370 | }; | 369 | }; |
| 371 | 370 | ||
| 372 | static const struct iio_chan_spec_ext_info ad5064_ext_info[] = { | 371 | static const struct iio_chan_spec_ext_info ad5064_ext_info[] = { |
| @@ -425,7 +425,6 @@ static const struct iio_info ad5360_info = { · 424 unmodified lines | |||
| 425 | .read_raw = ad5360_read_raw, | 425 | .read_raw = ad5360_read_raw, |
| 426 | .write_raw = ad5360_write_raw, | 426 | .write_raw = ad5360_write_raw, |
| 427 | .attrs = &ad5360_attribute_group, | 427 | .attrs = &ad5360_attribute_group, |
| 428 | .driver_module = THIS_MODULE, | ||
| 429 | }; | 428 | }; |
| 430 | 429 | ||
| 431 | static const char * const ad5360_vref_name[] = { | 430 | static const char * const ad5360_vref_name[] = { |
| @@ -237,7 +237,6 @@ static int ad5380_read_raw(struct iio_dev *indio_dev, · 236 unmodified lines | |||
| 237 | static const struct iio_info ad5380_info = { | 237 | static const struct iio_info ad5380_info = { |
| 238 | .read_raw = ad5380_read_raw, | 238 | .read_raw = ad5380_read_raw, |
| 239 | .write_raw = ad5380_write_raw, | 239 | .write_raw = ad5380_write_raw, |
| 240 | .driver_module = THIS_MODULE, | ||
| 241 | }; | 240 | }; |
| 242 | 241 | ||
| 243 | static struct iio_chan_spec_ext_info ad5380_ext_info[] = { | 242 | static struct iio_chan_spec_ext_info ad5380_ext_info[] = { |
| @@ -465,7 +465,6 @@ static const struct iio_info ad5421_info = { · 464 unmodified lines | |||
| 465 | .read_event_config = ad5421_read_event_config, | 465 | .read_event_config = ad5421_read_event_config, |
| 466 | .write_event_config = ad5421_write_event_config, | 466 | .write_event_config = ad5421_write_event_config, |
| 467 | .read_event_value = ad5421_read_event_value, | 467 | .read_event_value = ad5421_read_event_value, |
| 468 | .driver_module = THIS_MODULE, | ||
| 469 | }; | 468 | }; |
| 470 | 469 | ||
| 471 | static int ad5421_probe(struct spi_device *spi) | 470 | static int ad5421_probe(struct spi_device *spi) |
| @@ -212,7 +212,6 @@ static int ad5446_write_raw(struct iio_dev *indio_dev, · 211 unmodified lines | |||
| 212 | static const struct iio_info ad5446_info = { | 212 | static const struct iio_info ad5446_info = { |
| 213 | .read_raw = ad5446_read_raw, | 213 | .read_raw = ad5446_read_raw, |
| 214 | .write_raw = ad5446_write_raw, | 214 | .write_raw = ad5446_write_raw, |
| 215 | .driver_module = THIS_MODULE, | ||
| 216 | }; | 215 | }; |
| 217 | 216 | ||
| 218 | static int ad5446_probe(struct device *dev, const char *name, | 217 | static int ad5446_probe(struct device *dev, const char *name, |
| @@ -461,10 +460,22 @@ static const struct spi_device_id ad5446_spi_ids[] = { · 242 unmodified lines | |||
| 461 | {"ad5660-2500", ID_AD5660_2500}, | 460 | {"ad5660-2500", ID_AD5660_2500}, |
| 462 | {"ad5660-1250", ID_AD5660_1250}, | 461 | {"ad5660-1250", ID_AD5660_1250}, |
| 463 | {"ad5662", ID_AD5662}, | 462 | {"ad5662", ID_AD5662}, |
| 463 | {"dac081s101", ID_AD5300}, /* compatible Texas Instruments chips */ | ||
| 464 | {"dac101s101", ID_AD5310}, | ||
| 465 | {"dac121s101", ID_AD5320}, | ||
| 466 | {"dac7512", ID_AD5320}, | ||
| 464 | {} | 467 | {} |
| 465 | }; | 468 | }; |
| 466 | MODULE_DEVICE_TABLE(spi, ad5446_spi_ids); | 469 | MODULE_DEVICE_TABLE(spi, ad5446_spi_ids); |
| 467 | 470 | ||
| 471 | #ifdef CONFIG_OF | ||
| 472 | static const struct of_device_id ad5446_of_ids[] = { | ||
| 473 | { .compatible = "ti,dac7512" }, | ||
| 474 | { } | ||
| 475 | }; | ||
| 476 | MODULE_DEVICE_TABLE(of, ad5446_of_ids); | ||
| 477 | #endif | ||
| 478 | |||
| 468 | static int ad5446_spi_probe(struct spi_device *spi) | 479 | static int ad5446_spi_probe(struct spi_device *spi) |
| 469 | { | 480 | { |
| 470 | const struct spi_device_id *id = spi_get_device_id(spi); | 481 | const struct spi_device_id *id = spi_get_device_id(spi); |
| @@ -481,6 +492,7 @@ static int ad5446_spi_remove(struct spi_device *spi) · 10 unmodified lines | |||
| 481 | static struct spi_driver ad5446_spi_driver = { | 492 | static struct spi_driver ad5446_spi_driver = { |
| 482 | .driver = { | 493 | .driver = { |
| 483 | .name = "ad5446", | 494 | .name = "ad5446", |
| 495 | .of_match_table = of_match_ptr(ad5446_of_ids), | ||
| 484 | }, | 496 | }, |
| 485 | .probe = ad5446_spi_probe, | 497 | .probe = ad5446_spi_probe, |
| 486 | .remove = ad5446_spi_remove, | 498 | .remove = ad5446_spi_remove, |
| @@ -193,7 +193,6 @@ static int ad5449_write_raw(struct iio_dev *indio_dev, · 192 unmodified lines | |||
| 193 | static const struct iio_info ad5449_info = { | 193 | static const struct iio_info ad5449_info = { |
| 194 | .read_raw = ad5449_read_raw, | 194 | .read_raw = ad5449_read_raw, |
| 195 | .write_raw = ad5449_write_raw, | 195 | .write_raw = ad5449_write_raw, |
| 196 | .driver_module = THIS_MODULE, | ||
| 197 | }; | 196 | }; |
| 198 | 197 | ||
| 199 | #define AD5449_CHANNEL(chan, bits) { \ | 198 | #define AD5449_CHANNEL(chan, bits) { \ |
| @@ -232,7 +232,6 @@ static const struct iio_info ad5504_info = { · 231 unmodified lines | |||
| 232 | .write_raw = ad5504_write_raw, | 232 | .write_raw = ad5504_write_raw, |
| 233 | .read_raw = ad5504_read_raw, | 233 | .read_raw = ad5504_read_raw, |
| 234 | .event_attrs = &ad5504_ev_attribute_group, | 234 | .event_attrs = &ad5504_ev_attribute_group, |
| 235 | .driver_module = THIS_MODULE, | ||
| 236 | }; | 235 | }; |
| 237 | 236 | ||
| 238 | static const struct iio_chan_spec_ext_info ad5504_ext_info[] = { | 237 | static const struct iio_chan_spec_ext_info ad5504_ext_info[] = { |
| @@ -474,7 +474,6 @@ static const struct iio_info ad5592r_info = { · 473 unmodified lines | |||
| 474 | .read_raw = ad5592r_read_raw, | 474 | .read_raw = ad5592r_read_raw, |
| 475 | .write_raw = ad5592r_write_raw, | 475 | .write_raw = ad5592r_write_raw, |
| 476 | .write_raw_get_fmt = ad5592r_write_raw_get_fmt, | 476 | .write_raw_get_fmt = ad5592r_write_raw_get_fmt, |
| 477 | .driver_module = THIS_MODULE, | ||
| 478 | }; | 477 | }; |
| 479 | 478 | ||
| 480 | static ssize_t ad5592r_show_scale_available(struct iio_dev *iio_dev, | 479 | static ssize_t ad5592r_show_scale_available(struct iio_dev *iio_dev, |
| @@ -149,7 +149,6 @@ static ssize_t ad5624r_write_dac_powerdown(struct iio_dev *indio_dev, · 148 unmodified lines | |||
| 149 | static const struct iio_info ad5624r_info = { | 149 | static const struct iio_info ad5624r_info = { |
| 150 | .write_raw = ad5624r_write_raw, | 150 | .write_raw = ad5624r_write_raw, |
| 151 | .read_raw = ad5624r_read_raw, | 151 | .read_raw = ad5624r_read_raw, |
| 152 | .driver_module = THIS_MODULE, | ||
| 153 | }; | 152 | }; |
| 154 | 153 | ||
| 155 | static const struct iio_chan_spec_ext_info ad5624r_ext_info[] = { | 154 | static const struct iio_chan_spec_ext_info ad5624r_ext_info[] = { |
| @@ -252,7 +252,6 @@ static int ad5686_write_raw(struct iio_dev *indio_dev, · 251 unmodified lines | |||
| 252 | static const struct iio_info ad5686_info = { | 252 | static const struct iio_info ad5686_info = { |
| 253 | .read_raw = ad5686_read_raw, | 253 | .read_raw = ad5686_read_raw, |
| 254 | .write_raw = ad5686_write_raw, | 254 | .write_raw = ad5686_write_raw, |
| 255 | .driver_module = THIS_MODULE, | ||
| 256 | }; | 255 | }; |
| 257 | 256 | ||
| 258 | static const struct iio_chan_spec_ext_info ad5686_ext_info[] = { | 257 | static const struct iio_chan_spec_ext_info ad5686_ext_info[] = { |
| @@ -417,7 +417,6 @@ static ssize_t ad5755_write_powerdown(struct iio_dev *indio_dev, uintptr_t priv, · 416 unmodified lines | |||
| 417 | static const struct iio_info ad5755_info = { | 417 | static const struct iio_info ad5755_info = { |
| 418 | .read_raw = ad5755_read_raw, | 418 | .read_raw = ad5755_read_raw, |
| 419 | .write_raw = ad5755_write_raw, | 419 | .write_raw = ad5755_write_raw, |
| 420 | .driver_module = THIS_MODULE, | ||
| 421 | }; | 420 | }; |
| 422 | 421 | ||
| 423 | static const struct iio_chan_spec_ext_info ad5755_ext_info[] = { | 422 | static const struct iio_chan_spec_ext_info ad5755_ext_info[] = { |
| @@ -251,7 +251,6 @@ static int ad5761_write_raw(struct iio_dev *indio_dev, · 250 unmodified lines | |||
| 251 | static const struct iio_info ad5761_info = { | 251 | static const struct iio_info ad5761_info = { |
| 252 | .read_raw = &ad5761_read_raw, | 252 | .read_raw = &ad5761_read_raw, |
| 253 | .write_raw = &ad5761_write_raw, | 253 | .write_raw = &ad5761_write_raw, |
| 254 | .driver_module = THIS_MODULE, | ||
| 255 | }; | 254 | }; |
| 256 | 255 | ||
| 257 | #define AD5761_CHAN(_bits) { \ | 256 | #define AD5761_CHAN(_bits) { \ |
| @@ -268,7 +268,6 @@ static int ad5764_read_raw(struct iio_dev *indio_dev, · 267 unmodified lines | |||
| 268 | static const struct iio_info ad5764_info = { | 268 | static const struct iio_info ad5764_info = { |
| 269 | .read_raw = ad5764_read_raw, | 269 | .read_raw = ad5764_read_raw, |
| 270 | .write_raw = ad5764_write_raw, | 270 | .write_raw = ad5764_write_raw, |
| 271 | .driver_module = THIS_MODULE, | ||
| 272 | }; | 271 | }; |
| 273 | 272 | ||
| 274 | static int ad5764_probe(struct spi_device *spi) | 273 | static int ad5764_probe(struct spi_device *spi) |
| @@ -340,7 +340,6 @@ static int ad5791_write_raw(struct iio_dev *indio_dev, · 339 unmodified lines | |||
| 340 | static const struct iio_info ad5791_info = { | 340 | static const struct iio_info ad5791_info = { |
| 341 | .read_raw = &ad5791_read_raw, | 341 | .read_raw = &ad5791_read_raw, |
| 342 | .write_raw = &ad5791_write_raw, | 342 | .write_raw = &ad5791_write_raw, |
| 343 | .driver_module = THIS_MODULE, | ||
| 344 | }; | 343 | }; |
| 345 | 344 | ||
| 346 | static int ad5791_probe(struct spi_device *spi) | 345 | static int ad5791_probe(struct spi_device *spi) |
| @@ -161,7 +161,6 @@ static int ad7303_write_raw(struct iio_dev *indio_dev, · 160 unmodified lines | |||
| 161 | static const struct iio_info ad7303_info = { | 161 | static const struct iio_info ad7303_info = { |
| 162 | .read_raw = ad7303_read_raw, | 162 | .read_raw = ad7303_read_raw, |
| 163 | .write_raw = ad7303_write_raw, | 163 | .write_raw = ad7303_write_raw, |
| 164 | .driver_module = THIS_MODULE, | ||
| 165 | }; | 164 | }; |
| 166 | 165 | ||
| 167 | static const struct iio_chan_spec_ext_info ad7303_ext_info[] = { | 166 | static const struct iio_chan_spec_ext_info ad7303_ext_info[] = { |
| @@ -92,7 +92,6 @@ static int ad8801_read_raw(struct iio_dev *indio_dev, · 91 unmodified lines | |||
| 92 | static const struct iio_info ad8801_info = { | 92 | static const struct iio_info ad8801_info = { |
| 93 | .read_raw = ad8801_read_raw, | 93 | .read_raw = ad8801_read_raw, |
| 94 | .write_raw = ad8801_write_raw, | 94 | .write_raw = ad8801_write_raw, |
| 95 | .driver_module = THIS_MODULE, | ||
| 96 | }; | 95 | }; |
| 97 | 96 | ||
| 98 | #define AD8801_CHANNEL(chan) { \ | 97 | #define AD8801_CHANNEL(chan) { \ |
| @@ -85,7 +85,6 @@ static int cio_dac_write_raw(struct iio_dev *indio_dev, · 84 unmodified lines | |||
| 85 | } | 85 | } |
| 86 | 86 | ||
| 87 | static const struct iio_info cio_dac_info = { | 87 | static const struct iio_info cio_dac_info = { |
| 88 | .driver_module = THIS_MODULE, | ||
| 89 | .read_raw = cio_dac_read_raw, | 88 | .read_raw = cio_dac_read_raw, |
| 90 | .write_raw = cio_dac_write_raw | 89 | .write_raw = cio_dac_write_raw |
| 91 | }; | 90 | }; |
| @@ -128,7 +128,6 @@ static const struct iio_info dpot_dac_info = { · 127 unmodified lines | |||
| 128 | .read_raw = dpot_dac_read_raw, | 128 | .read_raw = dpot_dac_read_raw, |
| 129 | .read_avail = dpot_dac_read_avail, | 129 | .read_avail = dpot_dac_read_avail, |
| 130 | .write_raw = dpot_dac_write_raw, | 130 | .write_raw = dpot_dac_write_raw, |
| 131 | .driver_module = THIS_MODULE, | ||
| 132 | }; | 131 | }; |
| 133 | 132 | ||
| 134 | static int dpot_dac_channel_max_ohms(struct iio_dev *indio_dev) | 133 | static int dpot_dac_channel_max_ohms(struct iio_dev *indio_dev) |
| @@ -0,0 +1,341 @@ | |||
| 1 | /* | ||
| 2 | * Maxim Integrated | ||
| 3 | * 7-bit, Multi-Channel Sink/Source Current DAC Driver | ||
| 4 | * Copyright (C) 2017 Maxim Integrated | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/i2c.h> | ||
| 14 | #include <linux/regulator/consumer.h> | ||
| 15 | #include <linux/err.h> | ||
| 16 | #include <linux/delay.h> | ||
| 17 | #include <linux/iio/iio.h> | ||
| 18 | #include <linux/iio/driver.h> | ||
| 19 | #include <linux/iio/machine.h> | ||
| 20 | #include <linux/iio/consumer.h> | ||
| 21 | |||
| 22 | #define DS4422_MAX_DAC_CHANNELS 2 | ||
| 23 | #define DS4424_MAX_DAC_CHANNELS 4 | ||
| 24 | |||
| 25 | #define DS4424_DAC_ADDR(chan) ((chan) + 0xf8) | ||
| 26 | #define DS4424_SOURCE_I 1 | ||
| 27 | #define DS4424_SINK_I 0 | ||
| 28 | |||
| 29 | #define DS4424_CHANNEL(chan) { \ | ||
| 30 | .type = IIO_CURRENT, \ | ||
| 31 | .indexed = 1, \ | ||
| 32 | .output = 1, \ | ||
| 33 | .channel = chan, \ | ||
| 34 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ | ||
| 35 | } | ||
| 36 | |||
| 37 | /* | ||
| 38 | * DS4424 DAC control register 8 bits | ||
| 39 | * [7] 0: to sink; 1: to source | ||
| 40 | * [6:0] steps to sink/source | ||
| 41 | * bit[7] looks like a sign bit, but the value of the register is | ||
| 42 | * not a two's complement code considering the bit[6:0] is a absolute | ||
| 43 | * distance from the zero point. | ||
| 44 | */ | ||
| 45 | union ds4424_raw_data { | ||
| 46 | struct { | ||
| 47 | u8 dx:7; | ||
| 48 | u8 source_bit:1; | ||
| 49 | }; | ||
| 50 | u8 bits; | ||
| 51 | }; | ||
| 52 | |||
| 53 | enum ds4424_device_ids { | ||
| 54 | ID_DS4422, | ||
| 55 | ID_DS4424, | ||
| 56 | }; | ||
| 57 | |||
| 58 | struct ds4424_data { | ||
| 59 | struct i2c_client *client; | ||
| 60 | struct mutex lock; | ||
| 61 | uint8_t save[DS4424_MAX_DAC_CHANNELS]; | ||
| 62 | struct regulator *vcc_reg; | ||
| 63 | uint8_t raw[DS4424_MAX_DAC_CHANNELS]; | ||
| 64 | }; | ||
| 65 | |||
| 66 | static const struct iio_chan_spec ds4424_channels[] = { | ||
| 67 | DS4424_CHANNEL(0), | ||
| 68 | DS4424_CHANNEL(1), | ||
| 69 | DS4424_CHANNEL(2), | ||
| 70 | DS4424_CHANNEL(3), | ||
| 71 | }; | ||
| 72 | |||
| 73 | static int ds4424_get_value(struct iio_dev *indio_dev, | ||
| 74 | int *val, int channel) | ||
| 75 | { | ||
| 76 | struct ds4424_data *data = iio_priv(indio_dev); | ||
| 77 | int ret; | ||
| 78 | |||
| 79 | mutex_lock(&data->lock); | ||
| 80 | ret = i2c_smbus_read_byte_data(data->client, DS4424_DAC_ADDR(channel)); | ||
| 81 | if (ret < 0) | ||
| 82 | goto fail; | ||
| 83 | |||
| 84 | *val = ret; | ||
| 85 | |||
| 86 | fail: | ||
| 87 | mutex_unlock(&data->lock); | ||
| 88 | return ret; | ||
| 89 | } | ||
| 90 | |||
| 91 | static int ds4424_set_value(struct iio_dev *indio_dev, | ||
| 92 | int val, struct iio_chan_spec const *chan) | ||
| 93 | { | ||
| 94 | struct ds4424_data *data = iio_priv(indio_dev); | ||
| 95 | int ret; | ||
| 96 | |||
| 97 | mutex_lock(&data->lock); | ||
| 98 | ret = i2c_smbus_write_byte_data(data->client, | ||
| 99 | DS4424_DAC_ADDR(chan->channel), val); | ||
| 100 | if (ret < 0) | ||
| 101 | goto fail; | ||
| 102 | |||
| 103 | data->raw[chan->channel] = val; | ||
| 104 | |||
| 105 | fail: | ||
| 106 | mutex_unlock(&data->lock); | ||
| 107 | return ret; | ||
| 108 | } | ||
| 109 | |||
| 110 | static int ds4424_read_raw(struct iio_dev *indio_dev, | ||
| 111 | struct iio_chan_spec const *chan, | ||
| 112 | int *val, int *val2, long mask) | ||
| 113 | { | ||
| 114 | union ds4424_raw_data raw; | ||
| 115 | int ret; | ||
| 116 | |||
| 117 | switch (mask) { | ||
| 118 | case IIO_CHAN_INFO_RAW: | ||
| 119 | ret = ds4424_get_value(indio_dev, val, chan->channel); | ||
| 120 | if (ret < 0) { | ||
| 121 | pr_err("%s : ds4424_get_value returned %d\n", | ||
| 122 | __func__, ret); | ||
| 123 | return ret; | ||
| 124 | } | ||
| 125 | raw.bits = *val; | ||
| 126 | *val = raw.dx; | ||
| 127 | if (raw.source_bit == DS4424_SINK_I) | ||
| 128 | *val = -*val; | ||
| 129 | return IIO_VAL_INT; | ||
| 130 | |||
| 131 | default: | ||
| 132 | return -EINVAL; | ||
| 133 | } | ||
| 134 | } | ||
| 135 | |||
| 136 | static int ds4424_write_raw(struct iio_dev *indio_dev, | ||
| 137 | struct iio_chan_spec const *chan, | ||
| 138 | int val, int val2, long mask) | ||
| 139 | { | ||
| 140 | union ds4424_raw_data raw; | ||
| 141 | |||
| 142 | if (val2 != 0) | ||
| 143 | return -EINVAL; | ||
| 144 | |||
| 145 | switch (mask) { | ||
| 146 | case IIO_CHAN_INFO_RAW: | ||
| 147 | if (val < S8_MIN || val > S8_MAX) | ||
| 148 | return -EINVAL; | ||
| 149 | |||
| 150 | if (val > 0) { | ||
| 151 | raw.source_bit = DS4424_SOURCE_I; | ||
| 152 | raw.dx = val; | ||
| 153 | } else { | ||
| 154 | raw.source_bit = DS4424_SINK_I; | ||
| 155 | raw.dx = -val; | ||
| 156 | } | ||
| 157 | |||
| 158 | return ds4424_set_value(indio_dev, raw.bits, chan); | ||
| 159 | |||
| 160 | default: | ||
| 161 | return -EINVAL; | ||
| 162 | } | ||
| 163 | } | ||
| 164 | |||
| 165 | static int ds4424_verify_chip(struct iio_dev *indio_dev) | ||
| 166 | { | ||
| 167 | int ret, val; | ||
| 168 | |||
| 169 | ret = ds4424_get_value(indio_dev, &val, DS4424_DAC_ADDR(0)); | ||
| 170 | if (ret < 0) | ||
| 171 | dev_err(&indio_dev->dev, | ||
| 172 | "%s failed. ret: %d\n", __func__, ret); | ||
| 173 | |||
| 174 | return ret; | ||
| 175 | } | ||
| 176 | |||
| 177 | static int __maybe_unused ds4424_suspend(struct device *dev) | ||
| 178 | { | ||
| 179 | struct i2c_client *client = to_i2c_client(dev); | ||
| 180 | struct iio_dev *indio_dev = i2c_get_clientdata(client); | ||
| 181 | struct ds4424_data *data = iio_priv(indio_dev); | ||
| 182 | int ret = 0; | ||
| 183 | int i; | ||
| 184 | |||
| 185 | for (i = 0; i < indio_dev->num_channels; i++) { | ||
| 186 | data->save[i] = data->raw[i]; | ||
| 187 | ret = ds4424_set_value(indio_dev, 0, | ||
| 188 | &indio_dev->channels[i]); | ||
| 189 | if (ret < 0) | ||
| 190 | return ret; | ||
| 191 | } | ||
| 192 | return ret; | ||
| 193 | } | ||
| 194 | |||
| 195 | static int __maybe_unused ds4424_resume(struct device *dev) | ||
| 196 | { | ||
| 197 | struct i2c_client *client = to_i2c_client(dev); | ||
| 198 | struct iio_dev *indio_dev = i2c_get_clientdata(client); | ||
| 199 | struct ds4424_data *data = iio_priv(indio_dev); | ||
| 200 | int ret = 0; | ||
| 201 | int i; | ||
| 202 | |||
| 203 | for (i = 0; i < indio_dev->num_channels; i++) { | ||
| 204 | ret = ds4424_set_value(indio_dev, data->save[i], | ||
| 205 | &indio_dev->channels[i]); | ||
| 206 | if (ret < 0) | ||
| 207 | return ret; | ||
| 208 | } | ||
| 209 | return ret; | ||
| 210 | } | ||
| 211 | |||
| 212 | static SIMPLE_DEV_PM_OPS(ds4424_pm_ops, ds4424_suspend, ds4424_resume); | ||
| 213 | |||
| 214 | static const struct iio_info ds4424_info = { | ||
| 215 | .read_raw = ds4424_read_raw, | ||
| 216 | .write_raw = ds4424_write_raw, | ||
| 217 | }; | ||
| 218 | |||
| 219 | static int ds4424_probe(struct i2c_client *client, | ||
| 220 | const struct i2c_device_id *id) | ||
| 221 | { | ||
| 222 | struct ds4424_data *data; | ||
| 223 | struct iio_dev *indio_dev; | ||
| 224 | int ret; | ||
| 225 | |||
| 226 | indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); | ||
| 227 | if (!indio_dev) { | ||
| 228 | dev_err(&client->dev, "iio dev alloc failed.\n"); | ||
| 229 | return -ENOMEM; | ||
| 230 | } | ||
| 231 | |||
| 232 | data = iio_priv(indio_dev); | ||
| 233 | i2c_set_clientdata(client, indio_dev); | ||
| 234 | data->client = client; | ||
| 235 | indio_dev->name = id->name; | ||
| 236 | indio_dev->dev.of_node = client->dev.of_node; | ||
| 237 | indio_dev->dev.parent = &client->dev; | ||
| 238 | |||
| 239 | if (!client->dev.of_node) { | ||
| 240 | dev_err(&client->dev, | ||
| 241 | "Not found DT.\n"); | ||
| 242 | return -ENODEV; | ||
| 243 | } | ||
| 244 | |||
| 245 | data->vcc_reg = devm_regulator_get(&client->dev, "vcc"); | ||
| 246 | if (IS_ERR(data->vcc_reg)) { | ||
| 247 | dev_err(&client->dev, | ||
| 248 | "Failed to get vcc-supply regulator. err: %ld\n", | ||
| 249 | PTR_ERR(data->vcc_reg)); | ||
| 250 | return PTR_ERR(data->vcc_reg); | ||
| 251 | } | ||
| 252 | |||
| 253 | mutex_init(&data->lock); | ||
| 254 | ret = regulator_enable(data->vcc_reg); | ||
| 255 | if (ret < 0) { | ||
| 256 | dev_err(&client->dev, | ||
| 257 | "Unable to enable the regulator.\n"); | ||
| 258 | return ret; | ||
| 259 | } | ||
| 260 | |||
| 261 | usleep_range(1000, 1200); | ||
| 262 | ret = ds4424_verify_chip(indio_dev); | ||
| 263 | if (ret < 0) | ||
| 264 | goto fail; | ||
| 265 | |||
| 266 | switch (id->driver_data) { | ||
| 267 | case ID_DS4422: | ||
| 268 | indio_dev->num_channels = DS4422_MAX_DAC_CHANNELS; | ||
| 269 | break; | ||
| 270 | case ID_DS4424: | ||
| 271 | indio_dev->num_channels = DS4424_MAX_DAC_CHANNELS; | ||
| 272 | break; | ||
| 273 | default: | ||
| 274 | dev_err(&client->dev, | ||
| 275 | "ds4424: Invalid chip id.\n"); | ||
| 276 | ret = -ENXIO; | ||
| 277 | goto fail; | ||
| 278 | } | ||
| 279 | |||
| 280 | indio_dev->channels = ds4424_channels; | ||
| 281 | indio_dev->modes = INDIO_DIRECT_MODE; | ||
| 282 | indio_dev->info = &ds4424_info; | ||
| 283 | |||
| 284 | ret = iio_device_register(indio_dev); | ||
| 285 | if (ret < 0) { | ||
| 286 | dev_err(&client->dev, | ||
| 287 | "iio_device_register failed. ret: %d\n", ret); | ||
| 288 | goto fail; | ||
| 289 | } | ||
| 290 | |||
| 291 | return ret; | ||
| 292 | |||
| 293 | fail: | ||
| 294 | regulator_disable(data->vcc_reg); | ||
| 295 | return ret; | ||
| 296 | } | ||
| 297 | |||
| 298 | static int ds4424_remove(struct i2c_client *client) | ||
| 299 | { | ||
| 300 | struct iio_dev *indio_dev = i2c_get_clientdata(client); | ||
| 301 | struct ds4424_data *data = iio_priv(indio_dev); | ||
| 302 | |||
| 303 | iio_device_unregister(indio_dev); | ||
| 304 | regulator_disable(data->vcc_reg); | ||
| 305 | |||
| 306 | return 0; | ||
| 307 | } | ||
| 308 | |||
| 309 | static const struct i2c_device_id ds4424_id[] = { | ||
| 310 | { "ds4422", ID_DS4422 }, | ||
| 311 | { "ds4424", ID_DS4424 }, | ||
| 312 | { } | ||
| 313 | }; | ||
| 314 | |||
| 315 | MODULE_DEVICE_TABLE(i2c, ds4424_id); | ||
| 316 | |||
| 317 | static const struct of_device_id ds4424_of_match[] = { | ||
| 318 | { .compatible = "maxim,ds4422" }, | ||
| 319 | { .compatible = "maxim,ds4424" }, | ||
| 320 | { }, | ||
| 321 | }; | ||
| 322 | |||
| 323 | MODULE_DEVICE_TABLE(of, ds4424_of_match); | ||
| 324 | |||
| 325 | static struct i2c_driver ds4424_driver = { | ||
| 326 | .driver = { | ||
| 327 | .name = "ds4424", | ||
| 328 | .of_match_table = ds4424_of_match, | ||
| 329 | .pm = &ds4424_pm_ops, | ||
| 330 | }, | ||
| 331 | .probe = ds4424_probe, | ||
| 332 | .remove = ds4424_remove, | ||
| 333 | .id_table = ds4424_id, | ||
| 334 | }; | ||
| 335 | module_i2c_driver(ds4424_driver); | ||
| 336 | |||
| 337 | MODULE_DESCRIPTION("Maxim DS4424 DAC Driver"); | ||
| 338 | MODULE_AUTHOR("Ismail H. Kose <ismail.kose@maximintegrated.com>"); | ||
| 339 | MODULE_AUTHOR("Vishal Sood <vishal.sood@maximintegrated.com>"); | ||
| 340 | MODULE_AUTHOR("David Jung <david.jung@maximintegrated.com>"); | ||
| 341 | MODULE_LICENSE("GPL v2"); | ||
| @@ -103,7 +103,6 @@ static int lpc18xx_dac_write_raw(struct iio_dev *indio_dev, · 102 unmodified lines | |||
| 103 | static const struct iio_info lpc18xx_dac_info = { | 103 | static const struct iio_info lpc18xx_dac_info = { |
| 104 | .read_raw = lpc18xx_dac_read_raw, | 104 | .read_raw = lpc18xx_dac_read_raw, |
| 105 | .write_raw = lpc18xx_dac_write_raw, | 105 | .write_raw = lpc18xx_dac_write_raw, |
| 106 | .driver_module = THIS_MODULE, | ||
| 107 | }; | 106 | }; |
| 108 | 107 | ||
| 109 | static int lpc18xx_dac_probe(struct platform_device *pdev) | 108 | static int lpc18xx_dac_probe(struct platform_device *pdev) |
| @@ -159,7 +159,6 @@ static ssize_t ltc2632_write_dac_powerdown(struct iio_dev *indio_dev, · 158 unmodified lines | |||
| 159 | static const struct iio_info ltc2632_info = { | 159 | static const struct iio_info ltc2632_info = { |
| 160 | .write_raw = ltc2632_write_raw, | 160 | .write_raw = ltc2632_write_raw, |
| 161 | .read_raw = ltc2632_read_raw, | 161 | .read_raw = ltc2632_read_raw, |
| 162 | .driver_module = THIS_MODULE, | ||
| 163 | }; | 162 | }; |
| 164 | 163 | ||
| 165 | static const struct iio_chan_spec_ext_info ltc2632_ext_info[] = { | 164 | static const struct iio_chan_spec_ext_info ltc2632_ext_info[] = { |
| @@ -174,7 +174,6 @@ static SIMPLE_DEV_PM_OPS(m62332_pm_ops, m62332_suspend, m62332_resume); · 173 unmodified lines | |||
| 174 | static const struct iio_info m62332_info = { | 174 | static const struct iio_info m62332_info = { |
| 175 | .read_raw = m62332_read_raw, | 175 | .read_raw = m62332_read_raw, |
| 176 | .write_raw = m62332_write_raw, | 176 | .write_raw = m62332_write_raw, |
| 177 | .driver_module = THIS_MODULE, | ||
| 178 | }; | 177 | }; |
| 179 | 178 | ||
| 180 | #define M62332_CHANNEL(chan) { \ | 179 | #define M62332_CHANNEL(chan) { \ |
| @@ -137,7 +137,6 @@ static SIMPLE_DEV_PM_OPS(max517_pm_ops, max517_suspend, max517_resume); · 136 unmodified lines | |||
| 137 | static const struct iio_info max517_info = { | 137 | static const struct iio_info max517_info = { |
| 138 | .read_raw = max517_read_raw, | 138 | .read_raw = max517_read_raw, |
| 139 | .write_raw = max517_write_raw, | 139 | .write_raw = max517_write_raw, |
| 140 | .driver_module = THIS_MODULE, | ||
| 141 | }; | 140 | }; |
| 142 | 141 | ||
| 143 | #define MAX517_CHANNEL(chan) { \ | 142 | #define MAX517_CHANNEL(chan) { \ |
| @@ -300,7 +300,6 @@ static SIMPLE_DEV_PM_OPS(max5821_pm_ops, max5821_suspend, max5821_resume); · 299 unmodified lines | |||
| 300 | static const struct iio_info max5821_info = { | 300 | static const struct iio_info max5821_info = { |
| 301 | .read_raw = max5821_read_raw, | 301 | .read_raw = max5821_read_raw, |
| 302 | .write_raw = max5821_write_raw, | 302 | .write_raw = max5821_write_raw, |
| 303 | .driver_module = THIS_MODULE, | ||
| 304 | }; | 303 | }; |
| 305 | 304 | ||
| 306 | static int max5821_probe(struct i2c_client *client, | 305 | static int max5821_probe(struct i2c_client *client, |
| @@ -363,7 +363,6 @@ static const struct iio_info mcp4725_info = { · 362 unmodified lines | |||
| 363 | .read_raw = mcp4725_read_raw, | 363 | .read_raw = mcp4725_read_raw, |
| 364 | .write_raw = mcp4725_write_raw, | 364 | .write_raw = mcp4725_write_raw, |
| 365 | .attrs = &mcp4725_attribute_group, | 365 | .attrs = &mcp4725_attribute_group, |
| 366 | .driver_module = THIS_MODULE, | ||
| 367 | }; | 366 | }; |
| 368 | 367 | ||
| 369 | #ifdef CONFIG_OF | 368 | #ifdef CONFIG_OF |
| @@ -119,7 +119,6 @@ static const struct iio_chan_spec mcp4922_channels[3][MCP4922_NUM_CHANNELS] = { · 118 unmodified lines | |||
| 119 | static const struct iio_info mcp4922_info = { | 119 | static const struct iio_info mcp4922_info = { |
| 120 | .read_raw = &mcp4922_read_raw, | 120 | .read_raw = &mcp4922_read_raw, |
| 121 | .write_raw = &mcp4922_write_raw, | 121 | .write_raw = &mcp4922_write_raw, |
| 122 | .driver_module = THIS_MODULE, | ||
| 123 | }; | 122 | }; |
| 124 | 123 | ||
| 125 | static int mcp4922_probe(struct spi_device *spi) | 124 | static int mcp4922_probe(struct spi_device *spi) |
| @@ -156,7 +156,6 @@ static const struct iio_info stm32_dac_iio_info = { · 155 unmodified lines | |||
| 156 | .read_raw = stm32_dac_read_raw, | 156 | .read_raw = stm32_dac_read_raw, |
| 157 | .write_raw = stm32_dac_write_raw, | 157 | .write_raw = stm32_dac_write_raw, |
| 158 | .debugfs_reg_access = stm32_dac_debugfs_reg_access, | 158 | .debugfs_reg_access = stm32_dac_debugfs_reg_access, |
| 159 | .driver_module = THIS_MODULE, | ||
| 160 | }; | 159 | }; |
| 161 | 160 | ||
| 162 | static const char * const stm32_dac_powerdown_modes[] = { | 161 | static const char * const stm32_dac_powerdown_modes[] = { |
| @@ -0,0 +1,368 @@ | |||
| 1 | /* | ||
| 2 | * ti-dac082s085.c - Texas Instruments 8/10/12-bit 2/4-channel DAC driver | ||
| 3 | * | ||
| 4 | * Copyright (C) 2017 KUNBUS GmbH | ||
| 5 | * | ||
| 6 | * http://www.ti.com/lit/ds/symlink/dac082s085.pdf | ||
| 7 | * http://www.ti.com/lit/ds/symlink/dac102s085.pdf | ||
| 8 | * http://www.ti.com/lit/ds/symlink/dac122s085.pdf | ||
| 9 | * http://www.ti.com/lit/ds/symlink/dac084s085.pdf | ||
| 10 | * http://www.ti.com/lit/ds/symlink/dac104s085.pdf | ||
| 11 | * http://www.ti.com/lit/ds/symlink/dac124s085.pdf | ||
| 12 | * | ||
| 13 | * This program is free software; you can redistribute it and/or modify | ||
| 14 | * it under the terms of the GNU General Public License (version 2) as | ||
| 15 | * published by the Free Software Foundation. | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include <linux/iio/iio.h> | ||
| 19 | #include <linux/module.h> | ||
| 20 | #include <linux/regulator/consumer.h> | ||
| 21 | #include <linux/spi/spi.h> | ||
| 22 | |||
| 23 | enum { dual_8bit, dual_10bit, dual_12bit, quad_8bit, quad_10bit, quad_12bit }; | ||
| 24 | |||
| 25 | struct ti_dac_spec { | ||
| 26 | u8 num_channels; | ||
| 27 | u8 resolution; | ||
| 28 | }; | ||
| 29 | |||
| 30 | static const struct ti_dac_spec ti_dac_spec[] = { | ||
| 31 | [dual_8bit] = { .num_channels = 2, .resolution = 8 }, | ||
| 32 | [dual_10bit] = { .num_channels = 2, .resolution = 10 }, | ||
| 33 | [dual_12bit] = { .num_channels = 2, .resolution = 12 }, | ||
| 34 | [quad_8bit] = { .num_channels = 4, .resolution = 8 }, | ||
| 35 | [quad_10bit] = { .num_channels = 4, .resolution = 10 }, | ||
| 36 | [quad_12bit] = { .num_channels = 4, .resolution = 12 }, | ||
| 37 | }; | ||
| 38 | |||
| 39 | /** | ||
| 40 | * struct ti_dac_chip - TI DAC chip | ||
| 41 | * @lock: protects write sequences | ||
| 42 | * @vref: regulator generating Vref | ||
| 43 | * @mesg: SPI message to perform a write | ||
| 44 | * @xfer: SPI transfer used by @mesg | ||
| 45 | * @val: cached value of each output | ||
| 46 | * @powerdown: whether the chip is powered down | ||
| 47 | * @powerdown_mode: selected by the user | ||
| 48 | * @resolution: resolution of the chip | ||
| 49 | * @buf: buffer for @xfer | ||
| 50 | */ | ||
| 51 | struct ti_dac_chip { | ||
| 52 | struct mutex lock; | ||
| 53 | struct regulator *vref; | ||
| 54 | struct spi_message mesg; | ||
| 55 | struct spi_transfer xfer; | ||
| 56 | u16 val[4]; | ||
| 57 | bool powerdown; | ||
| 58 | u8 powerdown_mode; | ||
| 59 | u8 resolution; | ||
| 60 | u8 buf[2] ____cacheline_aligned; | ||
| 61 | }; | ||
| 62 | |||
| 63 | #define WRITE_NOT_UPDATE(chan) (0x00 | (chan) << 6) | ||
| 64 | #define WRITE_AND_UPDATE(chan) (0x10 | (chan) << 6) | ||
| 65 | #define WRITE_ALL_UPDATE 0x20 | ||
| 66 | #define POWERDOWN(mode) (0x30 | ((mode) + 1) << 6) | ||
| 67 | |||
| 68 | static int ti_dac_cmd(struct ti_dac_chip *ti_dac, u8 cmd, u16 val) | ||
| 69 | { | ||
| 70 | u8 shift = 12 - ti_dac->resolution; | ||
| 71 | |||
| 72 | ti_dac->buf[0] = cmd | (val >> (8 - shift)); | ||
| 73 | ti_dac->buf[1] = (val << shift) & 0xff; | ||
| 74 | return spi_sync(ti_dac->mesg.spi, &ti_dac->mesg); | ||
| 75 | } | ||
| 76 | |||
| 77 | static const char * const ti_dac_powerdown_modes[] = { | ||
| 78 | "2.5kohm_to_gnd", "100kohm_to_gnd", "three_state", | ||
| 79 | }; | ||
| 80 | |||
| 81 | static int ti_dac_get_powerdown_mode(struct iio_dev *indio_dev, | ||
| 82 | const struct iio_chan_spec *chan) | ||
| 83 | { | ||
| 84 | struct ti_dac_chip *ti_dac = iio_priv(indio_dev); | ||
| 85 | |||
| 86 | return ti_dac->powerdown_mode; | ||
| 87 | } | ||
| 88 | |||
| 89 | static int ti_dac_set_powerdown_mode(struct iio_dev *indio_dev, | ||
| 90 | const struct iio_chan_spec *chan, | ||
| 91 | unsigned int mode) | ||
| 92 | { | ||
| 93 | struct ti_dac_chip *ti_dac = iio_priv(indio_dev); | ||
| 94 | int ret = 0; | ||
| 95 | |||
| 96 | if (ti_dac->powerdown_mode == mode) | ||
| 97 | return 0; | ||
| 98 | |||
| 99 | mutex_lock(&ti_dac->lock); | ||
| 100 | if (ti_dac->powerdown) { | ||
| 101 | ret = ti_dac_cmd(ti_dac, POWERDOWN(mode), 0); | ||
| 102 | if (ret) | ||
| 103 | goto out; | ||
| 104 | } | ||
| 105 | ti_dac->powerdown_mode = mode; | ||
| 106 | |||
| 107 | out: | ||
| 108 | mutex_unlock(&ti_dac->lock); | ||
| 109 | return ret; | ||
| 110 | } | ||
| 111 | |||
| 112 | static const struct iio_enum ti_dac_powerdown_mode = { | ||
| 113 | .items = ti_dac_powerdown_modes, | ||
| 114 | .num_items = ARRAY_SIZE(ti_dac_powerdown_modes), | ||
| 115 | .get = ti_dac_get_powerdown_mode, | ||
| 116 | .set = ti_dac_set_powerdown_mode, | ||
| 117 | }; | ||
| 118 | |||
| 119 | static ssize_t ti_dac_read_powerdown(struct iio_dev *indio_dev, | ||
| 120 | uintptr_t private, | ||
| 121 | const struct iio_chan_spec *chan, | ||
| 122 | char *buf) | ||
| 123 | { | ||
| 124 | struct ti_dac_chip *ti_dac = iio_priv(indio_dev); | ||
| 125 | |||
| 126 | return sprintf(buf, "%d\n", ti_dac->powerdown); | ||
| 127 | } | ||
| 128 | |||
| 129 | static ssize_t ti_dac_write_powerdown(struct iio_dev *indio_dev, | ||
| 130 | uintptr_t private, | ||
| 131 | const struct iio_chan_spec *chan, | ||
| 132 | const char *buf, size_t len) | ||
| 133 | { | ||
| 134 | struct ti_dac_chip *ti_dac = iio_priv(indio_dev); | ||
| 135 | bool powerdown; | ||
| 136 | int ret; | ||
| 137 | |||
| 138 | ret = strtobool(buf, &powerdown); | ||
| 139 | if (ret) | ||
| 140 | return ret; | ||
| 141 | |||
| 142 | if (ti_dac->powerdown == powerdown) | ||
| 143 | return len; | ||
| 144 | |||
| 145 | mutex_lock(&ti_dac->lock); | ||
| 146 | if (powerdown) | ||
| 147 | ret = ti_dac_cmd(ti_dac, POWERDOWN(ti_dac->powerdown_mode), 0); | ||
| 148 | else | ||
| 149 | ret = ti_dac_cmd(ti_dac, WRITE_AND_UPDATE(0), ti_dac->val[0]); | ||
| 150 | if (!ret) | ||
| 151 | ti_dac->powerdown = powerdown; | ||
| 152 | mutex_unlock(&ti_dac->lock); | ||
| 153 | |||
| 154 | return ret ? ret : len; | ||
| 155 | } | ||
| 156 | |||
| 157 | static const struct iio_chan_spec_ext_info ti_dac_ext_info[] = { | ||
| 158 | { | ||
| 159 | .name = "powerdown", | ||
| 160 | .read = ti_dac_read_powerdown, | ||
| 161 | .write = ti_dac_write_powerdown, | ||
| 162 | .shared = IIO_SHARED_BY_TYPE, | ||
| 163 | }, | ||
| 164 | IIO_ENUM("powerdown_mode", IIO_SHARED_BY_TYPE, &ti_dac_powerdown_mode), | ||
| 165 | IIO_ENUM_AVAILABLE("powerdown_mode", &ti_dac_powerdown_mode), | ||
| 166 | { }, | ||
| 167 | }; | ||
| 168 | |||
| 169 | #define TI_DAC_CHANNEL(chan) { \ | ||
| 170 | .type = IIO_VOLTAGE, \ | ||
| 171 | .channel = (chan), \ | ||
| 172 | .address = (chan), \ | ||
| 173 | .indexed = true, \ | ||
| 174 | .output = true, \ | ||
| 175 | .datasheet_name = (const char[]){ 'A' + (chan), 0 }, \ | ||
| 176 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ | ||
| 177 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ | ||
| 178 | .ext_info = ti_dac_ext_info, \ | ||
| 179 | } | ||
| 180 | |||
| 181 | static const struct iio_chan_spec ti_dac_channels[] = { | ||
| 182 | TI_DAC_CHANNEL(0), | ||
| 183 | TI_DAC_CHANNEL(1), | ||
| 184 | TI_DAC_CHANNEL(2), | ||
| 185 | TI_DAC_CHANNEL(3), | ||
| 186 | }; | ||
| 187 | |||
| 188 | static int ti_dac_read_raw(struct iio_dev *indio_dev, | ||
| 189 | struct iio_chan_spec const *chan, | ||
| 190 | int *val, int *val2, long mask) | ||
| 191 | { | ||
| 192 | struct ti_dac_chip *ti_dac = iio_priv(indio_dev); | ||
| 193 | int ret; | ||
| 194 | |||
| 195 | switch (mask) { | ||
| 196 | case IIO_CHAN_INFO_RAW: | ||
| 197 | *val = ti_dac->val[chan->channel]; | ||
| 198 | ret = IIO_VAL_INT; | ||
| 199 | break; | ||
| 200 | |||
| 201 | case IIO_CHAN_INFO_SCALE: | ||
| 202 | ret = regulator_get_voltage(ti_dac->vref); | ||
| 203 | if (ret < 0) | ||
| 204 | return ret; | ||
| 205 | |||
| 206 | *val = ret / 1000; | ||
| 207 | *val2 = ti_dac->resolution; | ||
| 208 | ret = IIO_VAL_FRACTIONAL_LOG2; | ||
| 209 | break; | ||
| 210 | |||
| 211 | default: | ||
| 212 | ret = -EINVAL; | ||
| 213 | } | ||
| 214 | |||
| 215 | return ret; | ||
| 216 | } | ||
| 217 | |||
| 218 | static int ti_dac_write_raw(struct iio_dev *indio_dev, | ||
| 219 | struct iio_chan_spec const *chan, | ||
| 220 | int val, int val2, long mask) | ||
| 221 | { | ||
| 222 | struct ti_dac_chip *ti_dac = iio_priv(indio_dev); | ||
| 223 | int ret; | ||
| 224 | |||
| 225 | switch (mask) { | ||
| 226 | case IIO_CHAN_INFO_RAW: | ||
| 227 | if (ti_dac->val[chan->channel] == val) | ||
| 228 | return 0; | ||
| 229 | |||
| 230 | if (val >= (1 << ti_dac->resolution) || val < 0) | ||
| 231 | return -EINVAL; | ||
| 232 | |||
| 233 | if (ti_dac->powerdown) | ||
| 234 | return -EBUSY; | ||
| 235 | |||
| 236 | mutex_lock(&ti_dac->lock); | ||
| 237 | ret = ti_dac_cmd(ti_dac, WRITE_AND_UPDATE(chan->channel), val); | ||
| 238 | if (!ret) | ||
| 239 | ti_dac->val[chan->channel] = val; | ||
| 240 | mutex_unlock(&ti_dac->lock); | ||
| 241 | break; | ||
| 242 | |||
| 243 | default: | ||
| 244 | ret = -EINVAL; | ||
| 245 | } | ||
| 246 | |||
| 247 | return ret; | ||
| 248 | } | ||
| 249 | |||
| 250 | static int ti_dac_write_raw_get_fmt(struct iio_dev *indio_dev, | ||
| 251 | struct iio_chan_spec const *chan, long mask) | ||
| 252 | { | ||
| 253 | return IIO_VAL_INT; | ||
| 254 | } | ||
| 255 | |||
| 256 | static const struct iio_info ti_dac_info = { | ||
| 257 | .read_raw = ti_dac_read_raw, | ||
| 258 | .write_raw = ti_dac_write_raw, | ||
| 259 | .write_raw_get_fmt = ti_dac_write_raw_get_fmt, | ||
| 260 | }; | ||
| 261 | |||
| 262 | static int ti_dac_probe(struct spi_device *spi) | ||
| 263 | { | ||
| 264 | struct device *dev = &spi->dev; | ||
| 265 | const struct ti_dac_spec *spec; | ||
| 266 | struct ti_dac_chip *ti_dac; | ||
| 267 | struct iio_dev *indio_dev; | ||
| 268 | int ret; | ||
| 269 | |||
| 270 | indio_dev = devm_iio_device_alloc(dev, sizeof(*ti_dac)); | ||
| 271 | if (!indio_dev) | ||
| 272 | return -ENOMEM; | ||
| 273 | |||
| 274 | indio_dev->dev.parent = dev; | ||
| 275 | indio_dev->info = &ti_dac_info; | ||
| 276 | indio_dev->name = spi->modalias; | ||
| 277 | indio_dev->modes = INDIO_DIRECT_MODE; | ||
| 278 | indio_dev->channels = ti_dac_channels; | ||
| 279 | spi_set_drvdata(spi, indio_dev); | ||
| 280 | |||
| 281 | ti_dac = iio_priv(indio_dev); | ||
| 282 | ti_dac->xfer.tx_buf = &ti_dac->buf; | ||
| 283 | ti_dac->xfer.len = sizeof(ti_dac->buf); | ||
| 284 | spi_message_init_with_transfers(&ti_dac->mesg, &ti_dac->xfer, 1); | ||
| 285 | ti_dac->mesg.spi = spi; | ||
| 286 | |||
| 287 | spec = &ti_dac_spec[spi_get_device_id(spi)->driver_data]; | ||
| 288 | indio_dev->num_channels = spec->num_channels; | ||
| 289 | ti_dac->resolution = spec->resolution; | ||
| 290 | |||
| 291 | ti_dac->vref = devm_regulator_get(dev, "vref"); | ||
| 292 | if (IS_ERR(ti_dac->vref)) | ||
| 293 | return PTR_ERR(ti_dac->vref); | ||
| 294 | |||
| 295 | ret = regulator_enable(ti_dac->vref); | ||
| 296 | if (ret < 0) | ||
| 297 | return ret; | ||
| 298 | |||
| 299 | mutex_init(&ti_dac->lock); | ||
| 300 | |||
| 301 | ret = ti_dac_cmd(ti_dac, WRITE_ALL_UPDATE, 0); | ||
| 302 | if (ret) { | ||
| 303 | dev_err(dev, "failed to initialize outputs to 0\n"); | ||
| 304 | goto err; | ||
| 305 | } | ||
| 306 | |||
| 307 | ret = iio_device_register(indio_dev); | ||
| 308 | if (ret) | ||
| 309 | goto err; | ||
| 310 | |||
| 311 | return 0; | ||
| 312 | |||
| 313 | err: | ||
| 314 | mutex_destroy(&ti_dac->lock); | ||
| 315 | regulator_disable(ti_dac->vref); | ||
| 316 | return ret; | ||
| 317 | } | ||
| 318 | |||
| 319 | static int ti_dac_remove(struct spi_device *spi) | ||
| 320 | { | ||
| 321 | struct iio_dev *indio_dev = spi_get_drvdata(spi); | ||
| 322 | struct ti_dac_chip *ti_dac = iio_priv(indio_dev); | ||
| 323 | |||
| 324 | iio_device_unregister(indio_dev); | ||
| 325 | mutex_destroy(&ti_dac->lock); | ||
| 326 | regulator_disable(ti_dac->vref); | ||
| 327 | |||
| 328 | return 0; | ||
| 329 | } | ||
| 330 | |||
| 331 | #ifdef CONFIG_OF | ||
| 332 | static const struct of_device_id ti_dac_of_id[] = { | ||
| 333 | { .compatible = "ti,dac082s085" }, | ||
| 334 | { .compatible = "ti,dac102s085" }, | ||
| 335 | { .compatible = "ti,dac122s085" }, | ||
| 336 | { .compatible = "ti,dac084s085" }, | ||
| 337 | { .compatible = "ti,dac104s085" }, | ||
| 338 | { .compatible = "ti,dac124s085" }, | ||
| 339 | { } | ||
| 340 | }; | ||
| 341 | MODULE_DEVICE_TABLE(of, ti_dac_of_id); | ||
| 342 | #endif | ||
| 343 | |||
| 344 | static const struct spi_device_id ti_dac_spi_id[] = { | ||
| 345 | { "dac082s085", dual_8bit }, | ||
| 346 | { "dac102s085", dual_10bit }, | ||
| 347 | { "dac122s085", dual_12bit }, | ||
| 348 | { "dac084s085", quad_8bit }, | ||
| 349 | { "dac104s085", quad_10bit }, | ||
| 350 | { "dac124s085", quad_12bit }, | ||
| 351 | { } | ||
| 352 | }; | ||
| 353 | MODULE_DEVICE_TABLE(spi, ti_dac_spi_id); | ||
| 354 | |||
| 355 | static struct spi_driver ti_dac_driver = { | ||
| 356 | .driver = { | ||
| 357 | .name = "ti-dac082s085", | ||
| 358 | .of_match_table = of_match_ptr(ti_dac_of_id), | ||
| 359 | }, | ||
| 360 | .probe = ti_dac_probe, | ||
| 361 | .remove = ti_dac_remove, | ||
| 362 | .id_table = ti_dac_spi_id, | ||
| 363 | }; | ||
| 364 | module_spi_driver(ti_dac_driver); | ||
| 365 | |||
| 366 | MODULE_AUTHOR("Lukas Wunner <lukas@wunner.de>"); | ||
| 367 | MODULE_DESCRIPTION("Texas Instruments 8/10/12-bit 2/4-channel DAC driver"); | ||
| 368 | MODULE_LICENSE("GPL v2"); | ||
| @@ -167,7 +167,6 @@ static int vf610_write_raw(struct iio_dev *indio_dev, · 166 unmodified lines | |||
| 167 | } | 167 | } |
| 168 | 168 | ||
| 169 | static const struct iio_info vf610_dac_iio_info = { | 169 | static const struct iio_info vf610_dac_iio_info = { |
| 170 | .driver_module = THIS_MODULE, | ||
| 171 | .read_raw = &vf610_read_raw, | 170 | .read_raw = &vf610_read_raw, |
| 172 | .write_raw = &vf610_write_raw, | 171 | .write_raw = &vf610_write_raw, |
| 173 | }; | 172 | }; |
| @@ -5,7 +5,7 @@ menu "IIO dummy driver" · 4 unmodified lines | |||
| 5 | depends on IIO | 5 | depends on IIO |
| 6 | 6 | ||
| 7 | config IIO_DUMMY_EVGEN | 7 | config IIO_DUMMY_EVGEN |
| 8 | select IRQ_WORK | 8 | select IRQ_SIM |
| 9 | tristate | 9 | tristate |
| 10 | 10 | ||
| 11 | config IIO_SIMPLE_DUMMY | 11 | config IIO_SIMPLE_DUMMY |
| @@ -24,97 +24,46 @@ · 23 unmodified lines | |||
| 24 | #include "iio_dummy_evgen.h" | 24 | #include "iio_dummy_evgen.h" |
| 25 | #include <linux/iio/iio.h> | 25 | #include <linux/iio/iio.h> |
| 26 | #include <linux/iio/sysfs.h> | 26 | #include <linux/iio/sysfs.h> |
| 27 | #include <linux/irq_work.h> | 27 | #include <linux/irq_sim.h> |
| 28 | 28 | ||
| 29 | /* Fiddly bit of faking and irq without hardware */ | 29 | /* Fiddly bit of faking and irq without hardware */ |
| 30 | #define IIO_EVENTGEN_NO 10 | 30 | #define IIO_EVENTGEN_NO 10 |
| 31 | 31 | ||
| 32 | /** | 32 | /** |
| 33 | * struct iio_dummy_handle_irq - helper struct to simulate interrupt generation | ||
| 34 | * @work: irq_work used to run handlers from hardirq context | ||
| 35 | * @irq: fake irq line number to trigger an interrupt | ||
| 36 | */ | ||
| 37 | struct iio_dummy_handle_irq { | ||
| 38 | struct irq_work work; | ||
| 39 | int irq; | ||
| 40 | }; | ||
| 41 | |||
| 42 | /** | ||
| 43 | * struct iio_dummy_evgen - evgen state | ||
| 44 | * @chip: irq chip we are faking | ||
| 45 | * @base: base of irq range | ||
| 46 | * @enabled: mask of which irqs are enabled | ||
| 47 | * @inuse: mask of which irqs are connected | ||
| 48 | * @regs: irq regs we are faking | 33 | * @regs: irq regs we are faking |
| 49 | * @lock: protect the evgen state | 34 | * @lock: protect the evgen state |
| 50 | * @handler: helper for a 'hardware-like' interrupt simulation | 35 | * @inuse: mask of which irqs are connected |
| 36 | * @irq_sim: interrupt simulator | ||
| 37 | * @base: base of irq range | ||
| 51 | */ | 38 | */ |
| 52 | struct iio_dummy_eventgen { | 39 | struct iio_dummy_eventgen { |
| 53 | struct irq_chip chip; | ||
| 54 | int base; | ||
| 55 | bool enabled[IIO_EVENTGEN_NO]; | ||
| 56 | bool inuse[IIO_EVENTGEN_NO]; | ||
| 57 | struct iio_dummy_regs regs[IIO_EVENTGEN_NO]; | 40 | struct iio_dummy_regs regs[IIO_EVENTGEN_NO]; |
| 58 | struct mutex lock; | 41 | struct mutex lock; |
| 59 | struct iio_dummy_handle_irq handler; | 42 | bool inuse[IIO_EVENTGEN_NO]; |
| 43 | struct irq_sim irq_sim; | ||
| 44 | int base; | ||
| 60 | }; | 45 | }; |
| 61 | 46 | ||
| 62 | /* We can only ever have one instance of this 'device' */ | 47 | /* We can only ever have one instance of this 'device' */ |
| 63 | static struct iio_dummy_eventgen *iio_evgen; | 48 | static struct iio_dummy_eventgen *iio_evgen; |
| 64 | static const char *iio_evgen_name = "iio_dummy_evgen"; | ||
| 65 | |||
| 66 | static void iio_dummy_event_irqmask(struct irq_data *d) | ||
| 67 | { | ||
| 68 | struct irq_chip *chip = irq_data_get_irq_chip(d); | ||
| 69 | struct iio_dummy_eventgen *evgen = | ||
| 70 | container_of(chip, struct iio_dummy_eventgen, chip); | ||
| 71 | |||
| 72 | evgen->enabled[d->irq - evgen->base] = false; | ||
| 73 | } | ||
| 74 | |||
| 75 | static void iio_dummy_event_irqunmask(struct irq_data *d) | ||
| 76 | { | ||
| 77 | struct irq_chip *chip = irq_data_get_irq_chip(d); | ||
| 78 | struct iio_dummy_eventgen *evgen = | ||
| 79 | container_of(chip, struct iio_dummy_eventgen, chip); | ||
| 80 | |||
| 81 | evgen->enabled[d->irq - evgen->base] = true; | ||
| 82 | } | ||
| 83 | |||
| 84 | static void iio_dummy_work_handler(struct irq_work *work) | ||
| 85 | { | ||
| 86 | struct iio_dummy_handle_irq *irq_handler; | ||
| 87 | |||
| 88 | irq_handler = container_of(work, struct iio_dummy_handle_irq, work); | ||
| 89 | handle_simple_irq(irq_to_desc(irq_handler->irq)); | ||
| 90 | } | ||
| 91 | 49 | ||
| 92 | static int iio_dummy_evgen_create(void) | 50 | static int iio_dummy_evgen_create(void) |
| 93 | { | 51 | { |
| 94 | int ret, i; | 52 | int ret; |
| 95 | 53 | ||
| 96 | iio_evgen = kzalloc(sizeof(*iio_evgen), GFP_KERNEL); | 54 | iio_evgen = kzalloc(sizeof(*iio_evgen), GFP_KERNEL); |
| 97 | if (!iio_evgen) | 55 | if (!iio_evgen) |
| 98 | return -ENOMEM; | 56 | return -ENOMEM; |
| 99 | 57 | ||
| 100 | iio_evgen->base = irq_alloc_descs(-1, 0, IIO_EVENTGEN_NO, 0); | 58 | ret = irq_sim_init(&iio_evgen->irq_sim, IIO_EVENTGEN_NO); |
| 101 | if (iio_evgen->base < 0) { | 59 | if (ret) { |
| 102 | ret = iio_evgen->base; | ||
| 103 | kfree(iio_evgen); | 60 | kfree(iio_evgen); |
| 104 | return ret; | 61 | return ret; |
| 105 | } | 62 | } |
| 106 | iio_evgen->chip.name = iio_evgen_name; | 63 | |
| 107 | iio_evgen->chip.irq_mask = &iio_dummy_event_irqmask; | 64 | iio_evgen->base = irq_sim_irqnum(&iio_evgen->irq_sim, 0); |
| 108 | iio_evgen->chip.irq_unmask = &iio_dummy_event_irqunmask; | ||
| 109 | for (i = 0; i < IIO_EVENTGEN_NO; i++) { | ||
| 110 | irq_set_chip(iio_evgen->base + i, &iio_evgen->chip); | ||
| 111 | irq_set_handler(iio_evgen->base + i, &handle_simple_irq); | ||
| 112 | irq_modify_status(iio_evgen->base + i, | ||
| 113 | IRQ_NOREQUEST | IRQ_NOAUTOEN, | ||
| 114 | IRQ_NOPROBE); | ||
| 115 | } | ||
| 116 | init_irq_work(&iio_evgen->handler.work, iio_dummy_work_handler); | ||
| 117 | mutex_init(&iio_evgen->lock); | 65 | mutex_init(&iio_evgen->lock); |
| 66 | |||
| 118 | return 0; | 67 | return 0; |
| 119 | } | 68 | } |
| 120 | 69 | ||
| @@ -132,15 +81,17 @@ int iio_dummy_evgen_get_irq(void) · 11 unmodified lines | |||
| 132 | return -ENODEV; | 81 | return -ENODEV; |
| 133 | 82 | ||
| 134 | mutex_lock(&iio_evgen->lock); | 83 | mutex_lock(&iio_evgen->lock); |
| 135 | for (i = 0; i < IIO_EVENTGEN_NO; i++) | 84 | for (i = 0; i < IIO_EVENTGEN_NO; i++) { |
| 136 | if (!iio_evgen->inuse[i]) { | 85 | if (!iio_evgen->inuse[i]) { |
| 137 | ret = iio_evgen->base + i; | 86 | ret = irq_sim_irqnum(&iio_evgen->irq_sim, i); |
| 138 | iio_evgen->inuse[i] = true; | 87 | iio_evgen->inuse[i] = true; |
| 139 | break; | 88 | break; |
| 140 | } | 89 | } |
| 90 | } | ||
| 141 | mutex_unlock(&iio_evgen->lock); | 91 | mutex_unlock(&iio_evgen->lock); |
| 142 | if (i == IIO_EVENTGEN_NO) | 92 | if (i == IIO_EVENTGEN_NO) |
| 143 | return -ENOMEM; | 93 | return -ENOMEM; |
| 94 | |||
| 144 | return ret; | 95 | return ret; |
| 145 | } | 96 | } |
| 146 | EXPORT_SYMBOL_GPL(iio_dummy_evgen_get_irq); | 97 | EXPORT_SYMBOL_GPL(iio_dummy_evgen_get_irq); |
| @@ -167,7 +118,7 @@ EXPORT_SYMBOL_GPL(iio_dummy_evgen_get_regs); · 20 unmodified lines | |||
| 167 | 118 | ||
| 168 | static void iio_dummy_evgen_free(void) | 119 | static void iio_dummy_evgen_free(void) |
| 169 | { | 120 | { |
| 170 | irq_free_descs(iio_evgen->base, IIO_EVENTGEN_NO); | 121 | irq_sim_fini(&iio_evgen->irq_sim); |
| 171 | kfree(iio_evgen); | 122 | kfree(iio_evgen); |
| 172 | } | 123 | } |
| 173 | 124 | ||
| @@ -192,9 +143,7 @@ static ssize_t iio_evgen_poke(struct device *dev, · 18 unmodified lines | |||
| 192 | iio_evgen->regs[this_attr->address].reg_id = this_attr->address; | 143 | iio_evgen->regs[this_attr->address].reg_id = this_attr->address; |
| 193 | iio_evgen->regs[this_attr->address].reg_data = event; | 144 | iio_evgen->regs[this_attr->address].reg_data = event; |
| 194 | 145 | ||
| 195 | iio_evgen->handler.irq = iio_evgen->base + this_attr->address; | 146 | irq_sim_fire(&iio_evgen->irq_sim, this_attr->address); |
| 196 | if (iio_evgen->enabled[this_attr->address]) | ||
| 197 | irq_work_queue(&iio_evgen->handler.work); | ||
| 198 | 147 | ||
| 199 | return len; | 148 | return len; |
| 200 | } | 149 | } |
| @@ -519,7 +519,6 @@ static int iio_dummy_write_raw(struct iio_dev *indio_dev, · 518 unmodified lines | |||
| 519 | * Device type specific information. | 519 | * Device type specific information. |
| 520 | */ | 520 | */ |
| 521 | static const struct iio_info iio_dummy_info = { | 521 | static const struct iio_info iio_dummy_info = { |
| 522 | .driver_module = THIS_MODULE, | ||
| 523 | .read_raw = &iio_dummy_read_raw, | 522 | .read_raw = &iio_dummy_read_raw, |
| 524 | .write_raw = &iio_dummy_write_raw, | 523 | .write_raw = &iio_dummy_write_raw, |
| 525 | #ifdef CONFIG_IIO_SIMPLE_DUMMY_EVENTS | 524 | #ifdef CONFIG_IIO_SIMPLE_DUMMY_EVENTS |
| @@ -738,7 +738,6 @@ static const struct iio_info ad9523_info = { · 737 unmodified lines | |||
| 738 | .write_raw = &ad9523_write_raw, | 738 | .write_raw = &ad9523_write_raw, |
| 739 | .debugfs_reg_access = &ad9523_reg_access, | 739 | .debugfs_reg_access = &ad9523_reg_access, |
| 740 | .attrs = &ad9523_attribute_group, | 740 | .attrs = &ad9523_attribute_group, |
| 741 | .driver_module = THIS_MODULE, | ||
| 742 | }; | 741 | }; |
| 743 | 742 | ||
| 744 | static int ad9523_setup(struct iio_dev *indio_dev) | 743 | static int ad9523_setup(struct iio_dev *indio_dev) |
| @@ -374,7 +374,6 @@ static const struct iio_chan_spec adf4350_chan = { · 373 unmodified lines | |||
| 374 | 374 | ||
| 375 | static const struct iio_info adf4350_info = { | 375 | static const struct iio_info adf4350_info = { |
| 376 | .debugfs_reg_access = &adf4350_reg_access, | 376 | .debugfs_reg_access = &adf4350_reg_access, |
| 377 | .driver_module = THIS_MODULE, | ||
| 378 | }; | 377 | }; |
| 379 | 378 | ||
| 380 | #ifdef CONFIG_OF | 379 | #ifdef CONFIG_OF |
| @@ -163,7 +163,6 @@ static const struct iio_chan_spec adis16080_channels[] = { · 162 unmodified lines | |||
| 163 | 163 | ||
| 164 | static const struct iio_info adis16080_info = { | 164 | static const struct iio_info adis16080_info = { |
| 165 | .read_raw = &adis16080_read_raw, | 165 | .read_raw = &adis16080_read_raw, |
| 166 | .driver_module = THIS_MODULE, | ||
| 167 | }; | 166 | }; |
| 168 | 167 | ||
| 169 | enum { | 168 | enum { |
| @@ -137,7 +137,6 @@ static const struct iio_chan_spec adis16130_channels[] = { · 136 unmodified lines | |||
| 137 | 137 | ||
| 138 | static const struct iio_info adis16130_info = { | 138 | static const struct iio_info adis16130_info = { |
| 139 | .read_raw = &adis16130_read_raw, | 139 | .read_raw = &adis16130_read_raw, |
| 140 | .driver_module = THIS_MODULE, | ||
| 141 | }; | 140 | }; |
| 142 | 141 | ||
| 143 | static int adis16130_probe(struct spi_device *spi) | 142 | static int adis16130_probe(struct spi_device *spi) |
| @@ -398,7 +398,6 @@ static const struct attribute_group adis16136_attribute_group = { · 397 unmodified lines | |||
| 398 | }; | 398 | }; |
| 399 | 399 | ||
| 400 | static const struct iio_info adis16136_info = { | 400 | static const struct iio_info adis16136_info = { |
| 401 | .driver_module = THIS_MODULE, | ||
| 402 | .attrs = &adis16136_attribute_group, | 401 | .attrs = &adis16136_attribute_group, |
| 403 | .read_raw = &adis16136_read_raw, | 402 | .read_raw = &adis16136_read_raw, |
| 404 | .write_raw = &adis16136_write_raw, | 403 | .write_raw = &adis16136_write_raw, |
| @@ -321,7 +321,6 @@ static const struct iio_info adis16260_info = { · 320 unmodified lines | |||
| 321 | .read_raw = &adis16260_read_raw, | 321 | .read_raw = &adis16260_read_raw, |
| 322 | .write_raw = &adis16260_write_raw, | 322 | .write_raw = &adis16260_write_raw, |
| 323 | .update_scan_mode = adis_update_scan_mode, | 323 | .update_scan_mode = adis_update_scan_mode, |
| 324 | .driver_module = THIS_MODULE, | ||
| 325 | }; | 324 | }; |
| 326 | 325 | ||
| 327 | static const char * const adis1620_status_error_msgs[] = { | 326 | static const char * const adis1620_status_error_msgs[] = { |
| @@ -405,7 +405,6 @@ static const struct iio_chan_spec adxrs450_channels[2][2] = { · 404 unmodified lines | |||
| 405 | }; | 405 | }; |
| 406 | 406 | ||
| 407 | static const struct iio_info adxrs450_info = { | 407 | static const struct iio_info adxrs450_info = { |
| 408 | .driver_module = THIS_MODULE, | ||
| 409 | .read_raw = &adxrs450_read_raw, | 408 | .read_raw = &adxrs450_read_raw, |
| 410 | .write_raw = &adxrs450_write_raw, | 409 | .write_raw = &adxrs450_write_raw, |
| 411 | }; | 410 | }; |
| @@ -858,7 +858,6 @@ static const struct iio_info bmg160_info = { · 857 unmodified lines | |||
| 858 | .write_event_value = bmg160_write_event, | 858 | .write_event_value = bmg160_write_event, |
| 859 | .write_event_config = bmg160_write_event_config, | 859 | .write_event_config = bmg160_write_event_config, |
| 860 | .read_event_config = bmg160_read_event_config, | 860 | .read_event_config = bmg160_read_event_config, |
| 861 | .driver_module = THIS_MODULE, | ||
| 862 | }; | 861 | }; |
| 863 | 862 | ||
| 864 | static const unsigned long bmg160_accel_scan_masks[] = { | 863 | static const unsigned long bmg160_accel_scan_masks[] = { |
| @@ -956,7 +955,6 @@ static int bmg160_data_rdy_trigger_set_state(struct iio_trigger *trig, · 91 unmodified lines | |||
| 956 | static const struct iio_trigger_ops bmg160_trigger_ops = { | 955 | static const struct iio_trigger_ops bmg160_trigger_ops = { |
| 957 | .set_trigger_state = bmg160_data_rdy_trigger_set_state, | 956 | .set_trigger_state = bmg160_data_rdy_trigger_set_state, |
| 958 | .try_reenable = bmg160_trig_try_reen, | 957 | .try_reenable = bmg160_trig_try_reen, |
| 959 | .owner = THIS_MODULE, | ||
| 960 | }; | 958 | }; |
| 961 | 959 | ||
| 962 | static irqreturn_t bmg160_event_handler(int irq, void *private) | 960 | static irqreturn_t bmg160_event_handler(int irq, void *private) |
| @@ -186,7 +186,6 @@ static int gyro_3d_write_raw(struct iio_dev *indio_dev, · 185 unmodified lines | |||
| 186 | } | 186 | } |
| 187 | 187 | ||
| 188 | static const struct iio_info gyro_3d_info = { | 188 | static const struct iio_info gyro_3d_info = { |
| 189 | .driver_module = THIS_MODULE, | ||
| 190 | .read_raw = &gyro_3d_read_raw, | 189 | .read_raw = &gyro_3d_read_raw, |
| 191 | .write_raw = &gyro_3d_write_raw, | 190 | .write_raw = &gyro_3d_write_raw, |
| 192 | }; | 191 | }; |
| @@ -101,7 +101,6 @@ error_ret: · 100 unmodified lines | |||
| 101 | } | 101 | } |
| 102 | 102 | ||
| 103 | static const struct iio_trigger_ops itg3200_trigger_ops = { | 103 | static const struct iio_trigger_ops itg3200_trigger_ops = { |
| 104 | .owner = THIS_MODULE, | ||
| 105 | .set_trigger_state = &itg3200_data_rdy_trigger_set_state, | 104 | .set_trigger_state = &itg3200_data_rdy_trigger_set_state, |
| 106 | }; | 105 | }; |
| 107 | 106 | ||
| @@ -278,7 +278,6 @@ static const struct iio_chan_spec itg3200_channels[] = { · 277 unmodified lines | |||
| 278 | static const struct iio_info itg3200_info = { | 278 | static const struct iio_info itg3200_info = { |
| 279 | .read_raw = &itg3200_read_raw, | 279 | .read_raw = &itg3200_read_raw, |
| 280 | .write_raw = &itg3200_write_raw, | 280 | .write_raw = &itg3200_write_raw, |
| 281 | .driver_module = THIS_MODULE, | ||
| 282 | }; | 281 | }; |
| 283 | 282 | ||
| 284 | static const unsigned long itg3200_available_scan_masks[] = { 0xffffffff, 0x0 }; | 283 | static const unsigned long itg3200_available_scan_masks[] = { 0xffffffff, 0x0 }; |
| @@ -742,7 +742,6 @@ static const struct attribute_group mpu3050_attribute_group = { · 741 unmodified lines | |||
| 742 | }; | 742 | }; |
| 743 | 743 | ||
| 744 | static const struct iio_info mpu3050_info = { | 744 | static const struct iio_info mpu3050_info = { |
| 745 | .driver_module = THIS_MODULE, | ||
| 746 | .read_raw = mpu3050_read_raw, | 745 | .read_raw = mpu3050_read_raw, |
| 747 | .write_raw = mpu3050_write_raw, | 746 | .write_raw = mpu3050_write_raw, |
| 748 | .attrs = &mpu3050_attribute_group, | 747 | .attrs = &mpu3050_attribute_group, |
| @@ -1032,7 +1031,6 @@ static int mpu3050_drdy_trigger_set_state(struct iio_trigger *trig, · 283 unmodified lines | |||
| 1032 | } | 1031 | } |
| 1033 | 1032 | ||
| 1034 | static const struct iio_trigger_ops mpu3050_trigger_ops = { | 1033 | static const struct iio_trigger_ops mpu3050_trigger_ops = { |
| 1035 | .owner = THIS_MODULE, | ||
| 1036 | .set_trigger_state = mpu3050_drdy_trigger_set_state, | 1034 | .set_trigger_state = mpu3050_drdy_trigger_set_state, |
| 1037 | }; | 1035 | }; |
| 1038 | 1036 | ||
| @@ -111,14 +111,23 @@ static const struct st_sensor_settings st_gyro_sensors_settings[] = { · 110 unmodified lines | |||
| 111 | .mask = 0x80, | 111 | .mask = 0x80, |
| 112 | }, | 112 | }, |
| 113 | .drdy_irq = { | 113 | .drdy_irq = { |
| 114 | .addr = 0x22, | 114 | .int2 = { |
| 115 | .mask_int2 = 0x08, | 115 | .addr = 0x22, |
| 116 | .mask = 0x08, | ||
| 117 | }, | ||
| 116 | /* | 118 | /* |
| 117 | * The sensor has IHL (active low) and open | 119 | * The sensor has IHL (active low) and open |
| 118 | * drain settings, but only for INT1 and not | 120 | * drain settings, but only for INT1 and not |
| 119 | * for the DRDY line on INT2. | 121 | * for the DRDY line on INT2. |
| 120 | */ | 122 | */ |
| 121 | .addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR, | 123 | .stat_drdy = { |
| 124 | .addr = ST_SENSORS_DEFAULT_STAT_ADDR, | ||
| 125 | .mask = 0x07, | ||
| 126 | }, | ||
| 127 | }, | ||
| 128 | .sim = { | ||
| 129 | .addr = 0x23, | ||
| 130 | .value = BIT(0), | ||
| 122 | }, | 131 | }, |
| 123 | .multi_read_bit = true, | 132 | .multi_read_bit = true, |
| 124 | .bootime = 2, | 133 | .bootime = 2, |
| @@ -181,14 +190,23 @@ static const struct st_sensor_settings st_gyro_sensors_settings[] = { · 56 unmodified lines | |||
| 181 | .mask = 0x80, | 190 | .mask = 0x80, |
| 182 | }, | 191 | }, |
| 183 | .drdy_irq = { | 192 | .drdy_irq = { |
| 184 | .addr = 0x22, | 193 | .int2 = { |
| 185 | .mask_int2 = 0x08, | 194 | .addr = 0x22, |
| 195 | .mask = 0x08, | ||
| 196 | }, | ||
| 186 | /* | 197 | /* |
| 187 | * The sensor has IHL (active low) and open | 198 | * The sensor has IHL (active low) and open |
| 188 | * drain settings, but only for INT1 and not | 199 | * drain settings, but only for INT1 and not |
| 189 | * for the DRDY line on INT2. | 200 | * for the DRDY line on INT2. |
| 190 | */ | 201 | */ |
| 191 | .addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR, | 202 | .stat_drdy = { |
| 203 | .addr = ST_SENSORS_DEFAULT_STAT_ADDR, | ||
| 204 | .mask = 0x07, | ||
| 205 | }, | ||
| 206 | }, | ||
| 207 | .sim = { | ||
| 208 | .addr = 0x23, | ||
| 209 | .value = BIT(0), | ||
| 192 | }, | 210 | }, |
| 193 | .multi_read_bit = true, | 211 | .multi_read_bit = true, |
| 194 | .bootime = 2, | 212 | .bootime = 2, |
| @@ -246,14 +264,23 @@ static const struct st_sensor_settings st_gyro_sensors_settings[] = { · 51 unmodified lines | |||
| 246 | .mask = 0x80, | 264 | .mask = 0x80, |
| 247 | }, | 265 | }, |
| 248 | .drdy_irq = { | 266 | .drdy_irq = { |
| 249 | .addr = 0x22, | 267 | .int2 = { |
| 250 | .mask_int2 = 0x08, | 268 | .addr = 0x22, |
| 269 | .mask = 0x08, | ||
| 270 | }, | ||
| 251 | /* | 271 | /* |
| 252 | * The sensor has IHL (active low) and open | 272 | * The sensor has IHL (active low) and open |
| 253 | * drain settings, but only for INT1 and not | 273 | * drain settings, but only for INT1 and not |
| 254 | * for the DRDY line on INT2. | 274 | * for the DRDY line on INT2. |
| 255 | */ | 275 | */ |
| 256 | .addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR, | 276 | .stat_drdy = { |
| 277 | .addr = ST_SENSORS_DEFAULT_STAT_ADDR, | ||
| 278 | .mask = 0x07, | ||
| 279 | }, | ||
| 280 | }, | ||
| 281 | .sim = { | ||
| 282 | .addr = 0x23, | ||
| 283 | .value = BIT(0), | ||
| 257 | }, | 284 | }, |
| 258 | .multi_read_bit = true, | 285 | .multi_read_bit = true, |
| 259 | .bootime = 2, | 286 | .bootime = 2, |
| @@ -326,7 +353,6 @@ static const struct attribute_group st_gyro_attribute_group = { · 66 unmodified lines | |||
| 326 | }; | 353 | }; |
| 327 | 354 | ||
| 328 | static const struct iio_info gyro_info = { | 355 | static const struct iio_info gyro_info = { |
| 329 | .driver_module = THIS_MODULE, | ||
| 330 | .attrs = &st_gyro_attribute_group, | 356 | .attrs = &st_gyro_attribute_group, |
| 331 | .read_raw = &st_gyro_read_raw, | 357 | .read_raw = &st_gyro_read_raw, |
| 332 | .write_raw = &st_gyro_write_raw, | 358 | .write_raw = &st_gyro_write_raw, |
| @@ -335,7 +361,6 @@ static const struct iio_info gyro_info = { · 2 unmodified lines | |||
| 335 | 361 | ||
| 336 | #ifdef CONFIG_IIO_TRIGGER | 362 | #ifdef CONFIG_IIO_TRIGGER |
| 337 | static const struct iio_trigger_ops st_gyro_trigger_ops = { | 363 | static const struct iio_trigger_ops st_gyro_trigger_ops = { |
| 338 | .owner = THIS_MODULE, | ||
| 339 | .set_trigger_state = ST_GYRO_TRIGGER_SET_STATE, | 364 | .set_trigger_state = ST_GYRO_TRIGGER_SET_STATE, |
| 340 | .validate_device = st_sensors_validate_device, | 365 | .validate_device = st_sensors_validate_device, |
| 341 | }; | 366 | }; |
| @@ -309,7 +309,6 @@ static const struct iio_info afe4403_iio_info = { · 308 unmodified lines | |||
| 309 | .attrs = &afe440x_attribute_group, | 309 | .attrs = &afe440x_attribute_group, |
| 310 | .read_raw = afe4403_read_raw, | 310 | .read_raw = afe4403_read_raw, |
| 311 | .write_raw = afe4403_write_raw, | 311 | .write_raw = afe4403_write_raw, |
| 312 | .driver_module = THIS_MODULE, | ||
| 313 | }; | 312 | }; |
| 314 | 313 | ||
| 315 | static irqreturn_t afe4403_trigger_handler(int irq, void *private) | 314 | static irqreturn_t afe4403_trigger_handler(int irq, void *private) |
| @@ -354,7 +353,6 @@ err: · 38 unmodified lines | |||
| 354 | } | 353 | } |
| 355 | 354 | ||
| 356 | static const struct iio_trigger_ops afe4403_trigger_ops = { | 355 | static const struct iio_trigger_ops afe4403_trigger_ops = { |
| 357 | .owner = THIS_MODULE, | ||
| 358 | }; | 356 | }; |
| 359 | 357 | ||
| 360 | #define AFE4403_TIMING_PAIRS \ | 358 | #define AFE4403_TIMING_PAIRS \ |
| @@ -328,7 +328,6 @@ static const struct iio_info afe4404_iio_info = { · 327 unmodified lines | |||
| 328 | .attrs = &afe440x_attribute_group, | 328 | .attrs = &afe440x_attribute_group, |
| 329 | .read_raw = afe4404_read_raw, | 329 | .read_raw = afe4404_read_raw, |
| 330 | .write_raw = afe4404_write_raw, | 330 | .write_raw = afe4404_write_raw, |
| 331 | .driver_module = THIS_MODULE, | ||
| 332 | }; | 331 | }; |
| 333 | 332 | ||
| 334 | static irqreturn_t afe4404_trigger_handler(int irq, void *private) | 333 | static irqreturn_t afe4404_trigger_handler(int irq, void *private) |
| @@ -355,7 +354,6 @@ err: · 20 unmodified lines | |||
| 355 | } | 354 | } |
| 356 | 355 | ||
| 357 | static const struct iio_trigger_ops afe4404_trigger_ops = { | 356 | static const struct iio_trigger_ops afe4404_trigger_ops = { |
| 358 | .owner = THIS_MODULE, | ||
| 359 | }; | 357 | }; |
| 360 | 358 | ||
| 361 | /* Default timings from data-sheet */ | 359 | /* Default timings from data-sheet */ |
| @@ -420,7 +420,6 @@ static int max30100_read_raw(struct iio_dev *indio_dev, · 419 unmodified lines | |||
| 420 | } | 420 | } |
| 421 | 421 | ||
| 422 | static const struct iio_info max30100_info = { | 422 | static const struct iio_info max30100_info = { |
| 423 | .driver_module = THIS_MODULE, | ||
| 424 | .read_raw = max30100_read_raw, | 423 | .read_raw = max30100_read_raw, |
| 425 | }; | 424 | }; |
| 426 | 425 | ||
| @@ -381,7 +381,6 @@ static int max30102_read_raw(struct iio_dev *indio_dev, · 380 unmodified lines | |||
| 381 | } | 381 | } |
| 382 | 382 | ||
| 383 | static const struct iio_info max30102_info = { | 383 | static const struct iio_info max30102_info = { |
| 384 | .driver_module = THIS_MODULE, | ||
| 385 | .read_raw = max30102_read_raw, | 384 | .read_raw = max30102_read_raw, |
| 386 | }; | 385 | }; |
| 387 | 386 | ||
| @@ -215,7 +215,6 @@ static int am2315_read_raw(struct iio_dev *indio_dev, · 214 unmodified lines | |||
| 215 | } | 215 | } |
| 216 | 216 | ||
| 217 | static const struct iio_info am2315_info = { | 217 | static const struct iio_info am2315_info = { |
| 218 | .driver_module = THIS_MODULE, | ||
| 219 | .read_raw = am2315_read_raw, | 218 | .read_raw = am2315_read_raw, |
| 220 | }; | 219 | }; |
| 221 | 220 | ||
| @@ -284,7 +284,6 @@ err: · 283 unmodified lines | |||
| 284 | } | 284 | } |
| 285 | 285 | ||
| 286 | static const struct iio_info dht11_iio_info = { | 286 | static const struct iio_info dht11_iio_info = { |
| 287 | .driver_module = THIS_MODULE, | ||
| 288 | .read_raw = dht11_read_raw, | 287 | .read_raw = dht11_read_raw, |
| 289 | }; | 288 | }; |
| 290 | 289 | ||
| @@ -357,7 +357,6 @@ static const struct iio_info hdc100x_info = { · 356 unmodified lines | |||
| 357 | .read_raw = hdc100x_read_raw, | 357 | .read_raw = hdc100x_read_raw, |
| 358 | .write_raw = hdc100x_write_raw, | 358 | .write_raw = hdc100x_write_raw, |
| 359 | .attrs = &hdc100x_attribute_group, | 359 | .attrs = &hdc100x_attribute_group, |
| 360 | .driver_module = THIS_MODULE, | ||
| 361 | }; | 360 | }; |
| 362 | 361 | ||
| 363 | static int hdc100x_probe(struct i2c_client *client, | 362 | static int hdc100x_probe(struct i2c_client *client, |
| @@ -125,7 +125,6 @@ static int humidity_write_raw(struct iio_dev *indio_dev, · 124 unmodified lines | |||
| 125 | } | 125 | } |
| 126 | 126 | ||
| 127 | static const struct iio_info humidity_info = { | 127 | static const struct iio_info humidity_info = { |
| 128 | .driver_module = THIS_MODULE, | ||
| 129 | .read_raw = &humidity_read_raw, | 128 | .read_raw = &humidity_read_raw, |
| 130 | .write_raw = &humidity_write_raw, | 129 | .write_raw = &humidity_write_raw, |
| 131 | }; | 130 | }; |
| @@ -47,7 +47,6 @@ static int hts221_trig_set_state(struct iio_trigger *trig, bool state) · 46 unmodified lines | |||
| 47 | } | 47 | } |
| 48 | 48 | ||
| 49 | static const struct iio_trigger_ops hts221_trigger_ops = { | 49 | static const struct iio_trigger_ops hts221_trigger_ops = { |
| 50 | .owner = THIS_MODULE, | ||
| 51 | .set_trigger_state = hts221_trig_set_state, | 50 | .set_trigger_state = hts221_trig_set_state, |
| 52 | }; | 51 | }; |
| 53 | 52 | ||
| @@ -573,7 +573,6 @@ static const struct attribute_group hts221_attribute_group = { · 572 unmodified lines | |||
| 573 | }; | 573 | }; |
| 574 | 574 | ||
| 575 | static const struct iio_info hts221_info = { | 575 | static const struct iio_info hts221_info = { |
| 576 | .driver_module = THIS_MODULE, | ||
| 577 | .attrs = &hts221_attribute_group, | 576 | .attrs = &hts221_attribute_group, |
| 578 | .read_raw = hts221_read_raw, | 577 | .read_raw = hts221_read_raw, |
| 579 | .write_raw = hts221_write_raw, | 578 | .write_raw = hts221_write_raw, |
| @@ -175,7 +175,6 @@ static const struct iio_info htu21_info = { · 174 unmodified lines | |||
| 175 | .read_raw = htu21_read_raw, | 175 | .read_raw = htu21_read_raw, |
| 176 | .write_raw = htu21_write_raw, | 176 | .write_raw = htu21_write_raw, |
| 177 | .attrs = &htu21_attribute_group, | 177 | .attrs = &htu21_attribute_group, |
| 178 | .driver_module = THIS_MODULE, | ||
| 179 | }; | 178 | }; |
| 180 | 179 | ||
| 181 | static int htu21_probe(struct i2c_client *client, | 180 | static int htu21_probe(struct i2c_client *client, |
| @@ -124,7 +124,6 @@ static const struct iio_chan_spec si7005_channels[] = { · 123 unmodified lines | |||
| 124 | 124 | ||
| 125 | static const struct iio_info si7005_info = { | 125 | static const struct iio_info si7005_info = { |
| 126 | .read_raw = si7005_read_raw, | 126 | .read_raw = si7005_read_raw, |
| 127 | .driver_module = THIS_MODULE, | ||
| 128 | }; | 127 | }; |
| 129 | 128 | ||
| 130 | static int si7005_probe(struct i2c_client *client, | 129 | static int si7005_probe(struct i2c_client *client, |
| @@ -108,7 +108,6 @@ static const struct iio_chan_spec si7020_channels[] = { · 107 unmodified lines | |||
| 108 | 108 | ||
| 109 | static const struct iio_info si7020_info = { | 109 | static const struct iio_info si7020_info = { |
| 110 | .read_raw = si7020_read_raw, | 110 | .read_raw = si7020_read_raw, |
| 111 | .driver_module = THIS_MODULE, | ||
| 112 | }; | 111 | }; |
| 113 | 112 | ||
| 114 | static int si7020_probe(struct i2c_client *client, | 113 | static int si7020_probe(struct i2c_client *client, |
| @@ -833,7 +833,6 @@ static struct adis16400_chip_info adis16400_chips[] = { · 832 unmodified lines | |||
| 833 | }; | 833 | }; |
| 834 | 834 | ||
| 835 | static const struct iio_info adis16400_info = { | 835 | static const struct iio_info adis16400_info = { |
| 836 | .driver_module = THIS_MODULE, | ||
| 837 | .read_raw = &adis16400_read_raw, | 836 | .read_raw = &adis16400_read_raw, |
| 838 | .write_raw = &adis16400_write_raw, | 837 | .write_raw = &adis16400_write_raw, |
| 839 | .update_scan_mode = adis16400_update_scan_mode, | 838 | .update_scan_mode = adis16400_update_scan_mode, |
| @@ -720,7 +720,6 @@ static const struct iio_info adis16480_info = { · 719 unmodified lines | |||
| 720 | .read_raw = &adis16480_read_raw, | 720 | .read_raw = &adis16480_read_raw, |
| 721 | .write_raw = &adis16480_write_raw, | 721 | .write_raw = &adis16480_write_raw, |
| 722 | .update_scan_mode = adis_update_scan_mode, | 722 | .update_scan_mode = adis_update_scan_mode, |
| 723 | .driver_module = THIS_MODULE, | ||
| 724 | }; | 723 | }; |
| 725 | 724 | ||
| 726 | static int adis16480_stop_device(struct iio_dev *indio_dev) | 725 | static int adis16480_stop_device(struct iio_dev *indio_dev) |
| @@ -25,7 +25,6 @@ static int adis_data_rdy_trigger_set_state(struct iio_trigger *trig, · 24 unmodified lines | |||
| 25 | } | 25 | } |
| 26 | 26 | ||
| 27 | static const struct iio_trigger_ops adis_trigger_ops = { | 27 | static const struct iio_trigger_ops adis_trigger_ops = { |
| 28 | .owner = THIS_MODULE, | ||
| 29 | .set_trigger_state = &adis_data_rdy_trigger_set_state, | 28 | .set_trigger_state = &adis_data_rdy_trigger_set_state, |
| 30 | }; | 29 | }; |
| 31 | 30 | ||
| @@ -482,7 +482,6 @@ static const struct attribute_group bmi160_attrs_group = { · 481 unmodified lines | |||
| 482 | }; | 482 | }; |
| 483 | 483 | ||
| 484 | static const struct iio_info bmi160_info = { | 484 | static const struct iio_info bmi160_info = { |
| 485 | .driver_module = THIS_MODULE, | ||
| 486 | .read_raw = bmi160_read_raw, | 485 | .read_raw = bmi160_read_raw, |
| 487 | .write_raw = bmi160_write_raw, | 486 | .write_raw = bmi160_write_raw, |
| 488 | .attrs = &bmi160_attrs_group, | 487 | .attrs = &bmi160_attrs_group, |
| @@ -542,7 +542,9 @@ static int inv_mpu6050_write_raw(struct iio_dev *indio_dev, · 541 unmodified lines | |||
| 542 | break; | 542 | break; |
| 543 | default: | 543 | default: |
| 544 | result = -EINVAL; | 544 | result = -EINVAL; |
| 545 | break; | ||
| 545 | } | 546 | } |
| 547 | break; | ||
| 546 | default: | 548 | default: |
| 547 | result = -EINVAL; | 549 | result = -EINVAL; |
| 548 | break; | 550 | break; |
| @@ -570,10 +572,12 @@ error_write_raw_unlock: · 21 unmodified lines | |||
| 570 | */ | 572 | */ |
| 571 | static int inv_mpu6050_set_lpf(struct inv_mpu6050_state *st, int rate) | 573 | static int inv_mpu6050_set_lpf(struct inv_mpu6050_state *st, int rate) |
| 572 | { | 574 | { |
| 573 | const int hz[] = {188, 98, 42, 20, 10, 5}; | 575 | static const int hz[] = {188, 98, 42, 20, 10, 5}; |
| 574 | const int d[] = {INV_MPU6050_FILTER_188HZ, INV_MPU6050_FILTER_98HZ, | 576 | static const int d[] = { |
| 575 | INV_MPU6050_FILTER_42HZ, INV_MPU6050_FILTER_20HZ, | 577 | INV_MPU6050_FILTER_188HZ, INV_MPU6050_FILTER_98HZ, |
| 576 | INV_MPU6050_FILTER_10HZ, INV_MPU6050_FILTER_5HZ}; | 578 | INV_MPU6050_FILTER_42HZ, INV_MPU6050_FILTER_20HZ, |
| 579 | INV_MPU6050_FILTER_10HZ, INV_MPU6050_FILTER_5HZ | ||
| 580 | }; | ||
| 577 | int i, h, result; | 581 | int i, h, result; |
| 578 | u8 data; | 582 | u8 data; |
| 579 | 583 | ||
| @@ -795,7 +799,6 @@ static const struct attribute_group inv_attribute_group = { · 215 unmodified lines | |||
| 795 | }; | 799 | }; |
| 796 | 800 | ||
| 797 | static const struct iio_info mpu_info = { | 801 | static const struct iio_info mpu_info = { |
| 798 | .driver_module = THIS_MODULE, | ||
| 799 | .read_raw = &inv_mpu6050_read_raw, | 802 | .read_raw = &inv_mpu6050_read_raw, |
| 800 | .write_raw = &inv_mpu6050_write_raw, | 803 | .write_raw = &inv_mpu6050_write_raw, |
| 801 | .write_raw_get_fmt = &inv_write_raw_get_fmt, | 804 | .write_raw_get_fmt = &inv_write_raw_get_fmt, |
| @@ -114,7 +114,6 @@ static int inv_mpu_data_rdy_trigger_set_state(struct iio_trigger *trig, · 113 unmodified lines | |||
| 114 | } | 114 | } |
| 115 | 115 | ||
| 116 | static const struct iio_trigger_ops inv_mpu_trigger_ops = { | 116 | static const struct iio_trigger_ops inv_mpu_trigger_ops = { |
| 117 | .owner = THIS_MODULE, | ||
| 118 | .set_trigger_state = &inv_mpu_data_rdy_trigger_set_state, | 117 | .set_trigger_state = &inv_mpu_data_rdy_trigger_set_state, |
| 119 | }; | 118 | }; |
| 120 | 119 | ||
| @@ -1003,7 +1003,6 @@ static int kmx61_mag_validate_trigger(struct iio_dev *indio_dev, · 1002 unmodified lines | |||
| 1003 | } | 1003 | } |
| 1004 | 1004 | ||
| 1005 | static const struct iio_info kmx61_acc_info = { | 1005 | static const struct iio_info kmx61_acc_info = { |
| 1006 | .driver_module = THIS_MODULE, | ||
| 1007 | .read_raw = kmx61_read_raw, | 1006 | .read_raw = kmx61_read_raw, |
| 1008 | .write_raw = kmx61_write_raw, | 1007 | .write_raw = kmx61_write_raw, |
| 1009 | .attrs = &kmx61_acc_attribute_group, | 1008 | .attrs = &kmx61_acc_attribute_group, |
| @@ -1015,7 +1014,6 @@ static const struct iio_info kmx61_acc_info = { · 5 unmodified lines | |||
| 1015 | }; | 1014 | }; |
| 1016 | 1015 | ||
| 1017 | static const struct iio_info kmx61_mag_info = { | 1016 | static const struct iio_info kmx61_mag_info = { |
| 1018 | .driver_module = THIS_MODULE, | ||
| 1019 | .read_raw = kmx61_read_raw, | 1017 | .read_raw = kmx61_read_raw, |
| 1020 | .write_raw = kmx61_write_raw, | 1018 | .write_raw = kmx61_write_raw, |
| 1021 | .attrs = &kmx61_mag_attribute_group, | 1019 | .attrs = &kmx61_mag_attribute_group, |
| @@ -1087,7 +1085,6 @@ static int kmx61_trig_try_reenable(struct iio_trigger *trig) · 65 unmodified lines | |||
| 1087 | static const struct iio_trigger_ops kmx61_trigger_ops = { | 1085 | static const struct iio_trigger_ops kmx61_trigger_ops = { |
| 1088 | .set_trigger_state = kmx61_data_rdy_trigger_set_state, | 1086 | .set_trigger_state = kmx61_data_rdy_trigger_set_state, |
| 1089 | .try_reenable = kmx61_trig_try_reenable, | 1087 | .try_reenable = kmx61_trig_try_reenable, |
| 1090 | .owner = THIS_MODULE, | ||
| 1091 | }; | 1088 | }; |
| 1092 | 1089 | ||
| 1093 | static irqreturn_t kmx61_event_handler(int irq, void *private) | 1090 | static irqreturn_t kmx61_event_handler(int irq, void *private) |
| @@ -29,8 +29,6 @@ enum st_lsm6dsx_hw_id { · 28 unmodified lines | |||
| 29 | 29 | ||
| 30 | #define ST_LSM6DSX_CHAN_SIZE 2 | 30 | #define ST_LSM6DSX_CHAN_SIZE 2 |
| 31 | #define ST_LSM6DSX_SAMPLE_SIZE 6 | 31 | #define ST_LSM6DSX_SAMPLE_SIZE 6 |
| 32 | #define ST_LSM6DSX_SAMPLE_DEPTH (ST_LSM6DSX_SAMPLE_SIZE / \ | ||
| 33 | ST_LSM6DSX_CHAN_SIZE) | ||
| 34 | 32 | ||
| 35 | #if defined(CONFIG_SPI_MASTER) | 33 | #if defined(CONFIG_SPI_MASTER) |
| 36 | #define ST_LSM6DSX_RX_MAX_LENGTH 256 | 34 | #define ST_LSM6DSX_RX_MAX_LENGTH 256 |
| @@ -52,10 +50,38 @@ struct st_lsm6dsx_reg { · 15 unmodified lines | |||
| 52 | u8 mask; | 50 | u8 mask; |
| 53 | }; | 51 | }; |
| 54 | 52 | ||
| 53 | /** | ||
| 54 | * struct st_lsm6dsx_fifo_ops - ST IMU FIFO settings | ||
| 55 | * @fifo_th: FIFO threshold register info (addr + mask). | ||
| 56 | * @fifo_diff: FIFO diff status register info (addr + mask). | ||
| 57 | * @th_wl: FIFO threshold word length. | ||
| 58 | */ | ||
| 59 | struct st_lsm6dsx_fifo_ops { | ||
| 60 | struct { | ||
| 61 | u8 addr; | ||
| 62 | u16 mask; | ||
| 63 | } fifo_th; | ||
| 64 | struct { | ||
| 65 | u8 addr; | ||
| 66 | u16 mask; | ||
| 67 | } fifo_diff; | ||
| 68 | u8 th_wl; | ||
| 69 | }; | ||
| 70 | |||
| 71 | /** | ||
| 72 | * struct st_lsm6dsx_settings - ST IMU sensor settings | ||
| 73 | * @wai: Sensor WhoAmI default value. | ||
| 74 | * @max_fifo_size: Sensor max fifo length in FIFO words. | ||
| 75 | * @id: List of hw id supported by the driver configuration. | ||
| 76 | * @decimator: List of decimator register info (addr + mask). | ||
| 77 | * @fifo_ops: Sensor hw FIFO parameters. | ||
| 78 | */ | ||
| 55 | struct st_lsm6dsx_settings { | 79 | struct st_lsm6dsx_settings { |
| 56 | u8 wai; | 80 | u8 wai; |
| 57 | u16 max_fifo_size; | 81 | u16 max_fifo_size; |
| 58 | enum st_lsm6dsx_hw_id id[ST_LSM6DSX_MAX_ID]; | 82 | enum st_lsm6dsx_hw_id id[ST_LSM6DSX_MAX_ID]; |
| 83 | struct st_lsm6dsx_reg decimator[ST_LSM6DSX_MAX_ID]; | ||
| 84 | struct st_lsm6dsx_fifo_ops fifo_ops; | ||
| 59 | }; | 85 | }; |
| 60 | 86 | ||
| 61 | enum st_lsm6dsx_sensor_id { | 87 | enum st_lsm6dsx_sensor_id { |
| @@ -79,7 +105,6 @@ enum st_lsm6dsx_fifo_mode { · 17 unmodified lines | |||
| 79 | * @watermark: Sensor watermark level. | 105 | * @watermark: Sensor watermark level. |
| 80 | * @sip: Number of samples in a given pattern. | 106 | * @sip: Number of samples in a given pattern. |
| 81 | * @decimator: FIFO decimation factor. | 107 | * @decimator: FIFO decimation factor. |
| 82 | * @decimator_mask: Sensor mask for decimation register. | ||
| 83 | * @delta_ts: Delta time between two consecutive interrupts. | 108 | * @delta_ts: Delta time between two consecutive interrupts. |
| 84 | * @ts: Latest timestamp from the interrupt handler. | 109 | * @ts: Latest timestamp from the interrupt handler. |
| 85 | */ | 110 | */ |
| @@ -94,7 +119,6 @@ struct st_lsm6dsx_sensor { · 8 unmodified lines | |||
| 94 | u16 watermark; | 119 | u16 watermark; |
| 95 | u8 sip; | 120 | u8 sip; |
| 96 | u8 decimator; | 121 | u8 decimator; |
| 97 | u8 decimator_mask; | ||
| 98 | 122 | ||
| 99 | s64 delta_ts; | 123 | s64 delta_ts; |
| 100 | s64 ts; | 124 | s64 ts; |
| @@ -35,10 +35,6 @@ · 34 unmodified lines | |||
| 35 | 35 | ||
| 36 | #include "st_lsm6dsx.h" | 36 | #include "st_lsm6dsx.h" |
| 37 | 37 | ||
| 38 | #define ST_LSM6DSX_REG_FIFO_THL_ADDR 0x06 | ||
| 39 | #define ST_LSM6DSX_REG_FIFO_THH_ADDR 0x07 | ||
| 40 | #define ST_LSM6DSX_FIFO_TH_MASK GENMASK(11, 0) | ||
| 41 | #define ST_LSM6DSX_REG_FIFO_DEC_GXL_ADDR 0x08 | ||
| 42 | #define ST_LSM6DSX_REG_HLACTIVE_ADDR 0x12 | 38 | #define ST_LSM6DSX_REG_HLACTIVE_ADDR 0x12 |
| 43 | #define ST_LSM6DSX_REG_HLACTIVE_MASK BIT(5) | 39 | #define ST_LSM6DSX_REG_HLACTIVE_MASK BIT(5) |
| 44 | #define ST_LSM6DSX_REG_PP_OD_ADDR 0x12 | 40 | #define ST_LSM6DSX_REG_PP_OD_ADDR 0x12 |
| @@ -46,8 +42,6 @@ · 1 unmodified line | |||
| 46 | #define ST_LSM6DSX_REG_FIFO_MODE_ADDR 0x0a | 42 | #define ST_LSM6DSX_REG_FIFO_MODE_ADDR 0x0a |
| 47 | #define ST_LSM6DSX_FIFO_MODE_MASK GENMASK(2, 0) | 43 | #define ST_LSM6DSX_FIFO_MODE_MASK GENMASK(2, 0) |
| 48 | #define ST_LSM6DSX_FIFO_ODR_MASK GENMASK(6, 3) | 44 | #define ST_LSM6DSX_FIFO_ODR_MASK GENMASK(6, 3) |
| 49 | #define ST_LSM6DSX_REG_FIFO_DIFFL_ADDR 0x3a | ||
| 50 | #define ST_LSM6DSX_FIFO_DIFF_MASK GENMASK(11, 0) | ||
| 51 | #define ST_LSM6DSX_FIFO_EMPTY_MASK BIT(12) | 45 | #define ST_LSM6DSX_FIFO_EMPTY_MASK BIT(12) |
| 52 | #define ST_LSM6DSX_REG_FIFO_OUTL_ADDR 0x3e | 46 | #define ST_LSM6DSX_REG_FIFO_OUTL_ADDR 0x3e |
| 53 | 47 | ||
| @@ -110,8 +104,9 @@ static int st_lsm6dsx_update_decimators(struct st_lsm6dsx_hw *hw) · 56 unmodified lines | |||
| 110 | st_lsm6dsx_get_max_min_odr(hw, &max_odr, &min_odr); | 104 | st_lsm6dsx_get_max_min_odr(hw, &max_odr, &min_odr); |
| 111 | 105 | ||
| 112 | for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) { | 106 | for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) { |
| 113 | sensor = iio_priv(hw->iio_devs[i]); | 107 | const struct st_lsm6dsx_reg *dec_reg; |
| 114 | 108 | ||
| 109 | sensor = iio_priv(hw->iio_devs[i]); | ||
| 115 | /* update fifo decimators and sample in pattern */ | 110 | /* update fifo decimators and sample in pattern */ |
| 116 | if (hw->enable_mask & BIT(sensor->id)) { | 111 | if (hw->enable_mask & BIT(sensor->id)) { |
| 117 | sensor->sip = sensor->odr / min_odr; | 112 | sensor->sip = sensor->odr / min_odr; |
| @@ -123,12 +118,13 @@ static int st_lsm6dsx_update_decimators(struct st_lsm6dsx_hw *hw) · 5 unmodified lines | |||
| 123 | data = 0; | 118 | data = 0; |
| 124 | } | 119 | } |
| 125 | 120 | ||
| 126 | err = st_lsm6dsx_write_with_mask(hw, | 121 | dec_reg = &hw->settings->decimator[sensor->id]; |
| 127 | ST_LSM6DSX_REG_FIFO_DEC_GXL_ADDR, | 122 | if (dec_reg->addr) { |
| 128 | sensor->decimator_mask, data); | 123 | err = st_lsm6dsx_write_with_mask(hw, dec_reg->addr, |
| 129 | if (err < 0) | 124 | dec_reg->mask, data); |
| 130 | return err; | 125 | if (err < 0) |
| 131 | 126 | return err; | |
| 127 | } | ||
| 132 | sip += sensor->sip; | 128 | sip += sensor->sip; |
| 133 | } | 129 | } |
| 134 | hw->sip = sip; | 130 | hw->sip = sip; |
| @@ -139,23 +135,10 @@ static int st_lsm6dsx_update_decimators(struct st_lsm6dsx_hw *hw) · 4 unmodified lines | |||
| 139 | int st_lsm6dsx_set_fifo_mode(struct st_lsm6dsx_hw *hw, | 135 | int st_lsm6dsx_set_fifo_mode(struct st_lsm6dsx_hw *hw, |
| 140 | enum st_lsm6dsx_fifo_mode fifo_mode) | 136 | enum st_lsm6dsx_fifo_mode fifo_mode) |
| 141 | { | 137 | { |
| 142 | u8 data; | ||
| 143 | int err; | 138 | int err; |
| 144 | 139 | ||
| 145 | switch (fifo_mode) { | 140 | err = st_lsm6dsx_write_with_mask(hw, ST_LSM6DSX_REG_FIFO_MODE_ADDR, |
| 146 | case ST_LSM6DSX_FIFO_BYPASS: | 141 | ST_LSM6DSX_FIFO_MODE_MASK, fifo_mode); |
| 147 | data = fifo_mode; | ||
| 148 | break; | ||
| 149 | case ST_LSM6DSX_FIFO_CONT: | ||
| 150 | data = (ST_LSM6DSX_MAX_FIFO_ODR_VAL << | ||
| 151 | __ffs(ST_LSM6DSX_FIFO_ODR_MASK)) | fifo_mode; | ||
| 152 | break; | ||
| 153 | default: | ||
| 154 | return -EINVAL; | ||
| 155 | } | ||
| 156 | |||
| 157 | err = hw->tf->write(hw->dev, ST_LSM6DSX_REG_FIFO_MODE_ADDR, | ||
| 158 | sizeof(data), &data); | ||
| 159 | if (err < 0) | 142 | if (err < 0) |
| 160 | return err; | 143 | return err; |
| 161 | 144 | ||
| @@ -164,9 +147,20 @@ int st_lsm6dsx_set_fifo_mode(struct st_lsm6dsx_hw *hw, · 2 unmodified lines | |||
| 164 | return 0; | 147 | return 0; |
| 165 | } | 148 | } |
| 166 | 149 | ||
| 150 | static int st_lsm6dsx_set_fifo_odr(struct st_lsm6dsx_sensor *sensor, | ||
| 151 | bool enable) | ||
| 152 | { | ||
| 153 | struct st_lsm6dsx_hw *hw = sensor->hw; | ||
| 154 | u8 data; | ||
| 155 | |||
| 156 | data = hw->enable_mask ? ST_LSM6DSX_MAX_FIFO_ODR_VAL : 0; | ||
| 157 | return st_lsm6dsx_write_with_mask(hw, ST_LSM6DSX_REG_FIFO_MODE_ADDR, | ||
| 158 | ST_LSM6DSX_FIFO_ODR_MASK, data); | ||
| 159 | } | ||
| 160 | |||
| 167 | int st_lsm6dsx_update_watermark(struct st_lsm6dsx_sensor *sensor, u16 watermark) | 161 | int st_lsm6dsx_update_watermark(struct st_lsm6dsx_sensor *sensor, u16 watermark) |
| 168 | { | 162 | { |
| 169 | u16 fifo_watermark = ~0, cur_watermark, sip = 0; | 163 | u16 fifo_watermark = ~0, cur_watermark, sip = 0, fifo_th_mask; |
| 170 | struct st_lsm6dsx_hw *hw = sensor->hw; | 164 | struct st_lsm6dsx_hw *hw = sensor->hw; |
| 171 | struct st_lsm6dsx_sensor *cur_sensor; | 165 | struct st_lsm6dsx_sensor *cur_sensor; |
| 172 | __le16 wdata; | 166 | __le16 wdata; |
| @@ -191,20 +185,21 @@ int st_lsm6dsx_update_watermark(struct st_lsm6dsx_sensor *sensor, u16 watermark) · 18 unmodified lines | |||
| 191 | 185 | ||
| 192 | fifo_watermark = max_t(u16, fifo_watermark, sip); | 186 | fifo_watermark = max_t(u16, fifo_watermark, sip); |
| 193 | fifo_watermark = (fifo_watermark / sip) * sip; | 187 | fifo_watermark = (fifo_watermark / sip) * sip; |
| 194 | fifo_watermark = fifo_watermark * ST_LSM6DSX_SAMPLE_DEPTH; | 188 | fifo_watermark = fifo_watermark * hw->settings->fifo_ops.th_wl; |
| 195 | 189 | ||
| 196 | mutex_lock(&hw->lock); | 190 | mutex_lock(&hw->lock); |
| 197 | 191 | ||
| 198 | err = hw->tf->read(hw->dev, ST_LSM6DSX_REG_FIFO_THH_ADDR, | 192 | err = hw->tf->read(hw->dev, hw->settings->fifo_ops.fifo_th.addr + 1, |
| 199 | sizeof(data), &data); | 193 | sizeof(data), &data); |
| 200 | if (err < 0) | 194 | if (err < 0) |
| 201 | goto out; | 195 | goto out; |
| 202 | 196 | ||
| 203 | fifo_watermark = ((data << 8) & ~ST_LSM6DSX_FIFO_TH_MASK) | | 197 | fifo_th_mask = hw->settings->fifo_ops.fifo_th.mask; |
| 204 | (fifo_watermark & ST_LSM6DSX_FIFO_TH_MASK); | 198 | fifo_watermark = ((data << 8) & ~fifo_th_mask) | |
| 199 | (fifo_watermark & fifo_th_mask); | ||
| 205 | 200 | ||
| 206 | wdata = cpu_to_le16(fifo_watermark); | 201 | wdata = cpu_to_le16(fifo_watermark); |
| 207 | err = hw->tf->write(hw->dev, ST_LSM6DSX_REG_FIFO_THL_ADDR, | 202 | err = hw->tf->write(hw->dev, hw->settings->fifo_ops.fifo_th.addr, |
| 208 | sizeof(wdata), (u8 *)&wdata); | 203 | sizeof(wdata), (u8 *)&wdata); |
| 209 | out: | 204 | out: |
| 210 | mutex_unlock(&hw->lock); | 205 | mutex_unlock(&hw->lock); |
| @@ -223,6 +218,7 @@ out: · 12 unmodified lines | |||
| 223 | static int st_lsm6dsx_read_fifo(struct st_lsm6dsx_hw *hw) | 218 | static int st_lsm6dsx_read_fifo(struct st_lsm6dsx_hw *hw) |
| 224 | { | 219 | { |
| 225 | u16 fifo_len, pattern_len = hw->sip * ST_LSM6DSX_SAMPLE_SIZE; | 220 | u16 fifo_len, pattern_len = hw->sip * ST_LSM6DSX_SAMPLE_SIZE; |
| 221 | u16 fifo_diff_mask = hw->settings->fifo_ops.fifo_diff.mask; | ||
| 226 | int err, acc_sip, gyro_sip, read_len, samples, offset; | 222 | int err, acc_sip, gyro_sip, read_len, samples, offset; |
| 227 | struct st_lsm6dsx_sensor *acc_sensor, *gyro_sensor; | 223 | struct st_lsm6dsx_sensor *acc_sensor, *gyro_sensor; |
| 228 | s64 acc_ts, acc_delta_ts, gyro_ts, gyro_delta_ts; | 224 | s64 acc_ts, acc_delta_ts, gyro_ts, gyro_delta_ts; |
| @@ -230,7 +226,7 @@ static int st_lsm6dsx_read_fifo(struct st_lsm6dsx_hw *hw) · 1 unmodified line | |||
| 230 | u8 buff[pattern_len]; | 226 | u8 buff[pattern_len]; |
| 231 | __le16 fifo_status; | 227 | __le16 fifo_status; |
| 232 | 228 | ||
| 233 | err = hw->tf->read(hw->dev, ST_LSM6DSX_REG_FIFO_DIFFL_ADDR, | 229 | err = hw->tf->read(hw->dev, hw->settings->fifo_ops.fifo_diff.addr, |
| 234 | sizeof(fifo_status), (u8 *)&fifo_status); | 230 | sizeof(fifo_status), (u8 *)&fifo_status); |
| 235 | if (err < 0) | 231 | if (err < 0) |
| 236 | return err; | 232 | return err; |
| @@ -238,7 +234,7 @@ static int st_lsm6dsx_read_fifo(struct st_lsm6dsx_hw *hw) · 1 unmodified line | |||
| 238 | if (fifo_status & cpu_to_le16(ST_LSM6DSX_FIFO_EMPTY_MASK)) | 234 | if (fifo_status & cpu_to_le16(ST_LSM6DSX_FIFO_EMPTY_MASK)) |
| 239 | return 0; | 235 | return 0; |
| 240 | 236 | ||
| 241 | fifo_len = (le16_to_cpu(fifo_status) & ST_LSM6DSX_FIFO_DIFF_MASK) * | 237 | fifo_len = (le16_to_cpu(fifo_status) & fifo_diff_mask) * |
| 242 | ST_LSM6DSX_CHAN_SIZE; | 238 | ST_LSM6DSX_CHAN_SIZE; |
| 243 | samples = fifo_len / ST_LSM6DSX_SAMPLE_SIZE; | 239 | samples = fifo_len / ST_LSM6DSX_SAMPLE_SIZE; |
| 244 | fifo_len = (fifo_len / pattern_len) * pattern_len; | 240 | fifo_len = (fifo_len / pattern_len) * pattern_len; |
| @@ -345,6 +341,10 @@ static int st_lsm6dsx_update_fifo(struct iio_dev *iio_dev, bool enable) · 100 unmodified lines | |||
| 345 | return err; | 341 | return err; |
| 346 | } | 342 | } |
| 347 | 343 | ||
| 344 | err = st_lsm6dsx_set_fifo_odr(sensor, enable); | ||
| 345 | if (err < 0) | ||
| 346 | return err; | ||
| 347 | |||
| 348 | err = st_lsm6dsx_update_decimators(hw); | 348 | err = st_lsm6dsx_update_decimators(hw); |
| 349 | if (err < 0) | 349 | if (err < 0) |
| 350 | return err; | 350 | return err; |
| @@ -42,8 +42,6 @@ · 41 unmodified lines | |||
| 42 | 42 | ||
| 43 | #include "st_lsm6dsx.h" | 43 | #include "st_lsm6dsx.h" |
| 44 | 44 | ||
| 45 | #define ST_LSM6DSX_REG_ACC_DEC_MASK GENMASK(2, 0) | ||
| 46 | #define ST_LSM6DSX_REG_GYRO_DEC_MASK GENMASK(5, 3) | ||
| 47 | #define ST_LSM6DSX_REG_INT1_ADDR 0x0d | 45 | #define ST_LSM6DSX_REG_INT1_ADDR 0x0d |
| 48 | #define ST_LSM6DSX_REG_INT2_ADDR 0x0e | 46 | #define ST_LSM6DSX_REG_INT2_ADDR 0x0e |
| 49 | #define ST_LSM6DSX_REG_FIFO_FTH_IRQ_MASK BIT(3) | 47 | #define ST_LSM6DSX_REG_FIFO_FTH_IRQ_MASK BIT(3) |
| @@ -54,10 +52,6 @@ · 4 unmodified lines | |||
| 54 | #define ST_LSM6DSX_REG_BDU_MASK BIT(6) | 52 | #define ST_LSM6DSX_REG_BDU_MASK BIT(6) |
| 55 | #define ST_LSM6DSX_REG_INT2_ON_INT1_ADDR 0x13 | 53 | #define ST_LSM6DSX_REG_INT2_ON_INT1_ADDR 0x13 |
| 56 | #define ST_LSM6DSX_REG_INT2_ON_INT1_MASK BIT(5) | 54 | #define ST_LSM6DSX_REG_INT2_ON_INT1_MASK BIT(5) |
| 57 | #define ST_LSM6DSX_REG_ROUNDING_ADDR 0x16 | ||
| 58 | #define ST_LSM6DSX_REG_ROUNDING_MASK BIT(2) | ||
| 59 | #define ST_LSM6DSX_REG_LIR_ADDR 0x58 | ||
| 60 | #define ST_LSM6DSX_REG_LIR_MASK BIT(0) | ||
| 61 | 55 | ||
| 62 | #define ST_LSM6DSX_REG_ACC_ODR_ADDR 0x10 | 56 | #define ST_LSM6DSX_REG_ACC_ODR_ADDR 0x10 |
| 63 | #define ST_LSM6DSX_REG_ACC_ODR_MASK GENMASK(7, 4) | 57 | #define ST_LSM6DSX_REG_ACC_ODR_MASK GENMASK(7, 4) |
| @@ -160,25 +154,88 @@ static const struct st_lsm6dsx_fs_table_entry st_lsm6dsx_fs_table[] = { · 96 unmodified lines | |||
| 160 | static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = { | 154 | static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = { |
| 161 | { | 155 | { |
| 162 | .wai = 0x69, | 156 | .wai = 0x69, |
| 163 | .max_fifo_size = 8192, | 157 | .max_fifo_size = 1365, |
| 164 | .id = { | 158 | .id = { |
| 165 | [0] = ST_LSM6DS3_ID, | 159 | [0] = ST_LSM6DS3_ID, |
| 166 | }, | 160 | }, |
| 161 | .decimator = { | ||
| 162 | [ST_LSM6DSX_ID_ACC] = { | ||
| 163 | .addr = 0x08, | ||
| 164 | .mask = GENMASK(2, 0), | ||
| 165 | }, | ||
| 166 | [ST_LSM6DSX_ID_GYRO] = { | ||
| 167 | .addr = 0x08, | ||
| 168 | .mask = GENMASK(5, 3), | ||
| 169 | }, | ||
| 170 | }, | ||
| 171 | .fifo_ops = { | ||
| 172 | .fifo_th = { | ||
| 173 | .addr = 0x06, | ||
| 174 | .mask = GENMASK(11, 0), | ||
| 175 | }, | ||
| 176 | .fifo_diff = { | ||
| 177 | .addr = 0x3a, | ||
| 178 | .mask = GENMASK(11, 0), | ||
| 179 | }, | ||
| 180 | .th_wl = 3, /* 1LSB = 2B */ | ||
| 181 | }, | ||
| 167 | }, | 182 | }, |
| 168 | { | 183 | { |
| 169 | .wai = 0x69, | 184 | .wai = 0x69, |
| 170 | .max_fifo_size = 4096, | 185 | .max_fifo_size = 682, |
| 171 | .id = { | 186 | .id = { |
| 172 | [0] = ST_LSM6DS3H_ID, | 187 | [0] = ST_LSM6DS3H_ID, |
| 173 | }, | 188 | }, |
| 189 | .decimator = { | ||
| 190 | [ST_LSM6DSX_ID_ACC] = { | ||
| 191 | .addr = 0x08, | ||
| 192 | .mask = GENMASK(2, 0), | ||
| 193 | }, | ||
| 194 | [ST_LSM6DSX_ID_GYRO] = { | ||
| 195 | .addr = 0x08, | ||
| 196 | .mask = GENMASK(5, 3), | ||
| 197 | }, | ||
| 198 | }, | ||
| 199 | .fifo_ops = { | ||
| 200 | .fifo_th = { | ||
| 201 | .addr = 0x06, | ||
| 202 | .mask = GENMASK(11, 0), | ||
| 203 | }, | ||
| 204 | .fifo_diff = { | ||
| 205 | .addr = 0x3a, | ||
| 206 | .mask = GENMASK(11, 0), | ||
| 207 | }, | ||
| 208 | .th_wl = 3, /* 1LSB = 2B */ | ||
| 209 | }, | ||
| 174 | }, | 210 | }, |
| 175 | { | 211 | { |
| 176 | .wai = 0x6a, | 212 | .wai = 0x6a, |
| 177 | .max_fifo_size = 4096, | 213 | .max_fifo_size = 682, |
| 178 | .id = { | 214 | .id = { |
| 179 | [0] = ST_LSM6DSL_ID, | 215 | [0] = ST_LSM6DSL_ID, |
| 180 | [1] = ST_LSM6DSM_ID, | 216 | [1] = ST_LSM6DSM_ID, |
| 181 | }, | 217 | }, |
| 218 | .decimator = { | ||
| 219 | [ST_LSM6DSX_ID_ACC] = { | ||
| 220 | .addr = 0x08, | ||
| 221 | .mask = GENMASK(2, 0), | ||
| 222 | }, | ||
| 223 | [ST_LSM6DSX_ID_GYRO] = { | ||
| 224 | .addr = 0x08, | ||
| 225 | .mask = GENMASK(5, 3), | ||
| 226 | }, | ||
| 227 | }, | ||
| 228 | .fifo_ops = { | ||
| 229 | .fifo_th = { | ||
| 230 | .addr = 0x06, | ||
| 231 | .mask = GENMASK(11, 0), | ||
| 232 | }, | ||
| 233 | .fifo_diff = { | ||
| 234 | .addr = 0x3a, | ||
| 235 | .mask = GENMASK(11, 0), | ||
| 236 | }, | ||
| 237 | .th_wl = 3, /* 1LSB = 2B */ | ||
| 238 | }, | ||
| 182 | }, | 239 | }, |
| 183 | }; | 240 | }; |
| 184 | 241 | ||
| @@ -322,7 +379,6 @@ static int st_lsm6dsx_check_odr(struct st_lsm6dsx_sensor *sensor, u16 odr, · 137 unmodified lines | |||
| 322 | return -EINVAL; | 379 | return -EINVAL; |
| 323 | 380 | ||
| 324 | *val = st_lsm6dsx_odr_table[sensor->id].odr_avl[i].val; | 381 | *val = st_lsm6dsx_odr_table[sensor->id].odr_avl[i].val; |
| 325 | sensor->odr = odr; | ||
| 326 | 382 | ||
| 327 | return 0; | 383 | return 0; |
| 328 | } | 384 | } |
| @@ -449,6 +505,8 @@ static int st_lsm6dsx_write_raw(struct iio_dev *iio_dev, · 120 unmodified lines | |||
| 449 | u8 data; | 505 | u8 data; |
| 450 | 506 | ||
| 451 | err = st_lsm6dsx_check_odr(sensor, val, &data); | 507 | err = st_lsm6dsx_check_odr(sensor, val, &data); |
| 508 | if (!err) | ||
| 509 | sensor->odr = val; | ||
| 452 | break; | 510 | break; |
| 453 | } | 511 | } |
| 454 | default: | 512 | default: |
| @@ -465,10 +523,9 @@ static int st_lsm6dsx_set_watermark(struct iio_dev *iio_dev, unsigned int val) · 10 unmodified lines | |||
| 465 | { | 523 | { |
| 466 | struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); | 524 | struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); |
| 467 | struct st_lsm6dsx_hw *hw = sensor->hw; | 525 | struct st_lsm6dsx_hw *hw = sensor->hw; |
| 468 | int err, max_fifo_len; | 526 | int err; |
| 469 | 527 | ||
| 470 | max_fifo_len = hw->settings->max_fifo_size / ST_LSM6DSX_SAMPLE_SIZE; | 528 | if (val < 1 || val > hw->settings->max_fifo_size) |
| 471 | if (val < 1 || val > max_fifo_len) | ||
| 472 | return -EINVAL; | 529 | return -EINVAL; |
| 473 | 530 | ||
| 474 | err = st_lsm6dsx_update_watermark(sensor, val); | 531 | err = st_lsm6dsx_update_watermark(sensor, val); |
| @@ -530,7 +587,6 @@ static const struct attribute_group st_lsm6dsx_acc_attribute_group = { · 55 unmodified lines | |||
| 530 | }; | 587 | }; |
| 531 | 588 | ||
| 532 | static const struct iio_info st_lsm6dsx_acc_info = { | 589 | static const struct iio_info st_lsm6dsx_acc_info = { |
| 533 | .driver_module = THIS_MODULE, | ||
| 534 | .attrs = &st_lsm6dsx_acc_attribute_group, | 590 | .attrs = &st_lsm6dsx_acc_attribute_group, |
| 535 | .read_raw = st_lsm6dsx_read_raw, | 591 | .read_raw = st_lsm6dsx_read_raw, |
| 536 | .write_raw = st_lsm6dsx_write_raw, | 592 | .write_raw = st_lsm6dsx_write_raw, |
| @@ -548,7 +604,6 @@ static const struct attribute_group st_lsm6dsx_gyro_attribute_group = { · 11 unmodified lines | |||
| 548 | }; | 604 | }; |
| 549 | 605 | ||
| 550 | static const struct iio_info st_lsm6dsx_gyro_info = { | 606 | static const struct iio_info st_lsm6dsx_gyro_info = { |
| 551 | .driver_module = THIS_MODULE, | ||
| 552 | .attrs = &st_lsm6dsx_gyro_attribute_group, | 607 | .attrs = &st_lsm6dsx_gyro_attribute_group, |
| 553 | .read_raw = st_lsm6dsx_read_raw, | 608 | .read_raw = st_lsm6dsx_read_raw, |
| 554 | .write_raw = st_lsm6dsx_write_raw, | 609 | .write_raw = st_lsm6dsx_write_raw, |
| @@ -608,23 +663,12 @@ static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw) · 53 unmodified lines | |||
| 608 | 663 | ||
| 609 | msleep(200); | 664 | msleep(200); |
| 610 | 665 | ||
| 611 | /* latch interrupts */ | ||
| 612 | err = st_lsm6dsx_write_with_mask(hw, ST_LSM6DSX_REG_LIR_ADDR, | ||
| 613 | ST_LSM6DSX_REG_LIR_MASK, 1); | ||
| 614 | if (err < 0) | ||
| 615 | return err; | ||
| 616 | |||
| 617 | /* enable Block Data Update */ | 666 | /* enable Block Data Update */ |
| 618 | err = st_lsm6dsx_write_with_mask(hw, ST_LSM6DSX_REG_BDU_ADDR, | 667 | err = st_lsm6dsx_write_with_mask(hw, ST_LSM6DSX_REG_BDU_ADDR, |
| 619 | ST_LSM6DSX_REG_BDU_MASK, 1); | 668 | ST_LSM6DSX_REG_BDU_MASK, 1); |
| 620 | if (err < 0) | 669 | if (err < 0) |
| 621 | return err; | 670 | return err; |
| 622 | 671 | ||
| 623 | err = st_lsm6dsx_write_with_mask(hw, ST_LSM6DSX_REG_ROUNDING_ADDR, | ||
| 624 | ST_LSM6DSX_REG_ROUNDING_MASK, 1); | ||
| 625 | if (err < 0) | ||
| 626 | return err; | ||
| 627 | |||
| 628 | /* enable FIFO watermak interrupt */ | 672 | /* enable FIFO watermak interrupt */ |
| 629 | err = st_lsm6dsx_get_drdy_reg(hw, &drdy_int_reg); | 673 | err = st_lsm6dsx_get_drdy_reg(hw, &drdy_int_reg); |
| 630 | if (err < 0) | 674 | if (err < 0) |
| @@ -662,7 +706,6 @@ static struct iio_dev *st_lsm6dsx_alloc_iiodev(struct st_lsm6dsx_hw *hw, · 31 unmodified lines | |||
| 662 | iio_dev->num_channels = ARRAY_SIZE(st_lsm6dsx_acc_channels); | 706 | iio_dev->num_channels = ARRAY_SIZE(st_lsm6dsx_acc_channels); |
| 663 | iio_dev->info = &st_lsm6dsx_acc_info; | 707 | iio_dev->info = &st_lsm6dsx_acc_info; |
| 664 | 708 | ||
| 665 | sensor->decimator_mask = ST_LSM6DSX_REG_ACC_DEC_MASK; | ||
| 666 | scnprintf(sensor->name, sizeof(sensor->name), "%s_accel", | 709 | scnprintf(sensor->name, sizeof(sensor->name), "%s_accel", |
| 667 | name); | 710 | name); |
| 668 | break; | 711 | break; |
| @@ -671,7 +714,6 @@ static struct iio_dev *st_lsm6dsx_alloc_iiodev(struct st_lsm6dsx_hw *hw, · 2 unmodified lines | |||
| 671 | iio_dev->num_channels = ARRAY_SIZE(st_lsm6dsx_gyro_channels); | 714 | iio_dev->num_channels = ARRAY_SIZE(st_lsm6dsx_gyro_channels); |
| 672 | iio_dev->info = &st_lsm6dsx_gyro_info; | 715 | iio_dev->info = &st_lsm6dsx_gyro_info; |
| 673 | 716 | ||
| 674 | sensor->decimator_mask = ST_LSM6DSX_REG_GYRO_DEC_MASK; | ||
| 675 | scnprintf(sensor->name, sizeof(sensor->name), "%s_gyro", | 717 | scnprintf(sensor->name, sizeof(sensor->name), "%s_gyro", |
| 676 | name); | 718 | name); |
| 677 | break; | 719 | break; |
| @@ -1662,14 +1662,11 @@ static int iio_check_unique_scan_index(struct iio_dev *indio_dev) · 1661 unmodified lines | |||
| 1662 | 1662 | ||
| 1663 | static const struct iio_buffer_setup_ops noop_ring_setup_ops; | 1663 | static const struct iio_buffer_setup_ops noop_ring_setup_ops; |
| 1664 | 1664 | ||
| 1665 | /** | 1665 | int __iio_device_register(struct iio_dev *indio_dev, struct module *this_mod) |
| 1666 | * iio_device_register() - register a device with the IIO subsystem | ||
| 1667 | * @indio_dev: Device structure filled by the device driver | ||
| 1668 | **/ | ||
| 1669 | int iio_device_register(struct iio_dev *indio_dev) | ||
| 1670 | { | 1666 | { |
| 1671 | int ret; | 1667 | int ret; |
| 1672 | 1668 | ||
| 1669 | indio_dev->driver_module = this_mod; | ||
| 1673 | /* If the calling driver did not initialize of_node, do it here */ | 1670 | /* If the calling driver did not initialize of_node, do it here */ |
| 1674 | if (!indio_dev->dev.of_node && indio_dev->dev.parent) | 1671 | if (!indio_dev->dev.of_node && indio_dev->dev.parent) |
| 1675 | indio_dev->dev.of_node = indio_dev->dev.parent->of_node; | 1672 | indio_dev->dev.of_node = indio_dev->dev.parent->of_node; |
| @@ -1715,7 +1712,8 @@ int iio_device_register(struct iio_dev *indio_dev) · 39 unmodified lines | |||
| 1715 | indio_dev->setup_ops = &noop_ring_setup_ops; | 1712 | indio_dev->setup_ops = &noop_ring_setup_ops; |
| 1716 | 1713 | ||
| 1717 | cdev_init(&indio_dev->chrdev, &iio_buffer_fileops); | 1714 | cdev_init(&indio_dev->chrdev, &iio_buffer_fileops); |
| 1718 | indio_dev->chrdev.owner = indio_dev->info->driver_module; | 1715 | |
| 1716 | indio_dev->chrdev.owner = this_mod; | ||
| 1719 | 1717 | ||
| 1720 | ret = cdev_device_add(&indio_dev->chrdev, &indio_dev->dev); | 1718 | ret = cdev_device_add(&indio_dev->chrdev, &indio_dev->dev); |
| 1721 | if (ret < 0) | 1719 | if (ret < 0) |
| @@ -1733,7 +1731,7 @@ error_unreg_debugfs: · 11 unmodified lines | |||
| 1733 | iio_device_unregister_debugfs(indio_dev); | 1731 | iio_device_unregister_debugfs(indio_dev); |
| 1734 | return ret; | 1732 | return ret; |
| 1735 | } | 1733 | } |
| 1736 | EXPORT_SYMBOL(iio_device_register); | 1734 | EXPORT_SYMBOL(__iio_device_register); |
| 1737 | 1735 | ||
| 1738 | /** | 1736 | /** |
| 1739 | * iio_device_unregister() - unregister a device from the IIO subsystem | 1737 | * iio_device_unregister() - unregister a device from the IIO subsystem |
| @@ -1765,23 +1763,8 @@ static void devm_iio_device_unreg(struct device *dev, void *res) · 25 unmodified lines | |||
| 1765 | iio_device_unregister(*(struct iio_dev **)res); | 1763 | iio_device_unregister(*(struct iio_dev **)res); |
| 1766 | } | 1764 | } |
| 1767 | 1765 | ||
| 1768 | /** | 1766 | int __devm_iio_device_register(struct device *dev, struct iio_dev *indio_dev, |
| 1769 | * devm_iio_device_register - Resource-managed iio_device_register() | 1767 | struct module *this_mod) |
| 1770 | * @dev: Device to allocate iio_dev for | ||
| 1771 | * @indio_dev: Device structure filled by the device driver | ||
| 1772 | * | ||
| 1773 | * Managed iio_device_register. The IIO device registered with this | ||
| 1774 | * function is automatically unregistered on driver detach. This function | ||
| 1775 | * calls iio_device_register() internally. Refer to that function for more | ||
| 1776 | * information. | ||
| 1777 | * | ||
| 1778 | * If an iio_dev registered with this function needs to be unregistered | ||
| 1779 | * separately, devm_iio_device_unregister() must be used. | ||
| 1780 | * | ||
| 1781 | * RETURNS: | ||
| 1782 | * 0 on success, negative error number on failure. | ||
| 1783 | */ | ||
| 1784 | int devm_iio_device_register(struct device *dev, struct iio_dev *indio_dev) | ||
| 1785 | { | 1768 | { |
| 1786 | struct iio_dev **ptr; | 1769 | struct iio_dev **ptr; |
| 1787 | int ret; | 1770 | int ret; |
| @@ -1791,7 +1774,7 @@ int devm_iio_device_register(struct device *dev, struct iio_dev *indio_dev) · 3 unmodified lines | |||
| 1791 | return -ENOMEM; | 1774 | return -ENOMEM; |
| 1792 | 1775 | ||
| 1793 | *ptr = indio_dev; | 1776 | *ptr = indio_dev; |
| 1794 | ret = iio_device_register(indio_dev); | 1777 | ret = __iio_device_register(indio_dev, this_mod); |
| 1795 | if (!ret) | 1778 | if (!ret) |
| 1796 | devres_add(dev, ptr); | 1779 | devres_add(dev, ptr); |
| 1797 | else | 1780 | else |
| @@ -1799,7 +1782,7 @@ int devm_iio_device_register(struct device *dev, struct iio_dev *indio_dev) · 1 unmodified line | |||
| 1799 | 1782 | ||
| 1800 | return ret; | 1783 | return ret; |
| 1801 | } | 1784 | } |
| 1802 | EXPORT_SYMBOL_GPL(devm_iio_device_register); | 1785 | EXPORT_SYMBOL_GPL(__devm_iio_device_register); |
| 1803 | 1786 | ||
| 1804 | /** | 1787 | /** |
| 1805 | * devm_iio_device_unregister - Resource-managed iio_device_unregister() | 1788 | * devm_iio_device_unregister - Resource-managed iio_device_unregister() |
| @@ -66,13 +66,12 @@ ATTRIBUTE_GROUPS(iio_trig_dev); · 65 unmodified lines | |||
| 66 | 66 | ||
| 67 | static struct iio_trigger *__iio_trigger_find_by_name(const char *name); | 67 | static struct iio_trigger *__iio_trigger_find_by_name(const char *name); |
| 68 | 68 | ||
| 69 | int iio_trigger_register(struct iio_trigger *trig_info) | 69 | int __iio_trigger_register(struct iio_trigger *trig_info, |
| 70 | struct module *this_mod) | ||
| 70 | { | 71 | { |
| 71 | int ret; | 72 | int ret; |
| 72 | 73 | ||
| 73 | /* trig_info->ops is required for the module member */ | 74 | trig_info->owner = this_mod; |
| 74 | if (!trig_info->ops) | ||
| 75 | return -EINVAL; | ||
| 76 | 75 | ||
| 77 | trig_info->id = ida_simple_get(&iio_trigger_ida, 0, 0, GFP_KERNEL); | 76 | trig_info->id = ida_simple_get(&iio_trigger_ida, 0, 0, GFP_KERNEL); |
| 78 | if (trig_info->id < 0) | 77 | if (trig_info->id < 0) |
| @@ -105,7 +104,7 @@ error_unregister_id: · 26 unmodified lines | |||
| 105 | ida_simple_remove(&iio_trigger_ida, trig_info->id); | 104 | ida_simple_remove(&iio_trigger_ida, trig_info->id); |
| 106 | return ret; | 105 | return ret; |
| 107 | } | 106 | } |
| 108 | EXPORT_SYMBOL(iio_trigger_register); | 107 | EXPORT_SYMBOL(__iio_trigger_register); |
| 109 | 108 | ||
| 110 | void iio_trigger_unregister(struct iio_trigger *trig_info) | 109 | void iio_trigger_unregister(struct iio_trigger *trig_info) |
| 111 | { | 110 | { |
| @@ -206,7 +205,8 @@ EXPORT_SYMBOL(iio_trigger_poll_chained); · 94 unmodified lines | |||
| 206 | 205 | ||
| 207 | void iio_trigger_notify_done(struct iio_trigger *trig) | 206 | void iio_trigger_notify_done(struct iio_trigger *trig) |
| 208 | { | 207 | { |
| 209 | if (atomic_dec_and_test(&trig->use_count) && trig->ops->try_reenable) | 208 | if (atomic_dec_and_test(&trig->use_count) && trig->ops && |
| 209 | trig->ops->try_reenable) | ||
| 210 | if (trig->ops->try_reenable(trig)) | 210 | if (trig->ops->try_reenable(trig)) |
| 211 | /* Missed an interrupt so launch new poll now */ | 211 | /* Missed an interrupt so launch new poll now */ |
| 212 | iio_trigger_poll(trig); | 212 | iio_trigger_poll(trig); |
| @@ -250,7 +250,7 @@ static int iio_trigger_attach_poll_func(struct iio_trigger *trig, · 37 unmodified lines | |||
| 250 | = bitmap_empty(trig->pool, CONFIG_IIO_CONSUMERS_PER_TRIGGER); | 250 | = bitmap_empty(trig->pool, CONFIG_IIO_CONSUMERS_PER_TRIGGER); |
| 251 | 251 | ||
| 252 | /* Prevent the module from being removed whilst attached to a trigger */ | 252 | /* Prevent the module from being removed whilst attached to a trigger */ |
| 253 | __module_get(pf->indio_dev->info->driver_module); | 253 | __module_get(pf->indio_dev->driver_module); |
| 254 | 254 | ||
| 255 | /* Get irq number */ | 255 | /* Get irq number */ |
| 256 | pf->irq = iio_trigger_get_irq(trig); | 256 | pf->irq = iio_trigger_get_irq(trig); |
| @@ -265,7 +265,7 @@ static int iio_trigger_attach_poll_func(struct iio_trigger *trig, · 8 unmodified lines | |||
| 265 | goto out_put_irq; | 265 | goto out_put_irq; |
| 266 | 266 | ||
| 267 | /* Enable trigger in driver */ | 267 | /* Enable trigger in driver */ |
| 268 | if (trig->ops->set_trigger_state && notinuse) { | 268 | if (trig->ops && trig->ops->set_trigger_state && notinuse) { |
| 269 | ret = trig->ops->set_trigger_state(trig, true); | 269 | ret = trig->ops->set_trigger_state(trig, true); |
| 270 | if (ret < 0) | 270 | if (ret < 0) |
| 271 | goto out_free_irq; | 271 | goto out_free_irq; |
| @@ -286,7 +286,7 @@ out_free_irq: · 14 unmodified lines | |||
| 286 | out_put_irq: | 286 | out_put_irq: |
| 287 | iio_trigger_put_irq(trig, pf->irq); | 287 | iio_trigger_put_irq(trig, pf->irq); |
| 288 | out_put_module: | 288 | out_put_module: |
| 289 | module_put(pf->indio_dev->info->driver_module); | 289 | module_put(pf->indio_dev->driver_module); |
| 290 | return ret; | 290 | return ret; |
| 291 | } | 291 | } |
| 292 | 292 | ||
| @@ -298,7 +298,7 @@ static int iio_trigger_detach_poll_func(struct iio_trigger *trig, · 5 unmodified lines | |||
| 298 | = (bitmap_weight(trig->pool, | 298 | = (bitmap_weight(trig->pool, |
| 299 | CONFIG_IIO_CONSUMERS_PER_TRIGGER) | 299 | CONFIG_IIO_CONSUMERS_PER_TRIGGER) |
| 300 | == 1); | 300 | == 1); |
| 301 | if (trig->ops->set_trigger_state && no_other_users) { | 301 | if (trig->ops && trig->ops->set_trigger_state && no_other_users) { |
| 302 | ret = trig->ops->set_trigger_state(trig, false); | 302 | ret = trig->ops->set_trigger_state(trig, false); |
| 303 | if (ret) | 303 | if (ret) |
| 304 | return ret; | 304 | return ret; |
| @@ -307,7 +307,7 @@ static int iio_trigger_detach_poll_func(struct iio_trigger *trig, · 2 unmodified lines | |||
| 307 | trig->attached_own_device = false; | 307 | trig->attached_own_device = false; |
| 308 | iio_trigger_put_irq(trig, pf->irq); | 308 | iio_trigger_put_irq(trig, pf->irq); |
| 309 | free_irq(pf->irq, pf); | 309 | free_irq(pf->irq, pf); |
| 310 | module_put(pf->indio_dev->info->driver_module); | 310 | module_put(pf->indio_dev->driver_module); |
| 311 | 311 | ||
| 312 | return ret; | 312 | return ret; |
| 313 | } | 313 | } |
| @@ -428,7 +428,7 @@ static ssize_t iio_trigger_write_current(struct device *dev, · 114 unmodified lines | |||
| 428 | goto out_trigger_put; | 428 | goto out_trigger_put; |
| 429 | } | 429 | } |
| 430 | 430 | ||
| 431 | if (trig && trig->ops->validate_device) { | 431 | if (trig && trig->ops && trig->ops->validate_device) { |
| 432 | ret = trig->ops->validate_device(trig, indio_dev); | 432 | ret = trig->ops->validate_device(trig, indio_dev); |
| 433 | if (ret) | 433 | if (ret) |
| 434 | goto out_trigger_put; | 434 | goto out_trigger_put; |
| @@ -663,9 +663,10 @@ static void devm_iio_trigger_unreg(struct device *dev, void *res) · 228 unmodified lines | |||
| 663 | } | 663 | } |
| 664 | 664 | ||
| 665 | /** | 665 | /** |
| 666 | * devm_iio_trigger_register - Resource-managed iio_trigger_register() | 666 | * __devm_iio_trigger_register - Resource-managed iio_trigger_register() |
| 667 | * @dev: device this trigger was allocated for | 667 | * @dev: device this trigger was allocated for |
| 668 | * @trig_info: trigger to register | 668 | * @trig_info: trigger to register |
| 669 | * @this_mod: module registering the trigger | ||
| 669 | * | 670 | * |
| 670 | * Managed iio_trigger_register(). The IIO trigger registered with this | 671 | * Managed iio_trigger_register(). The IIO trigger registered with this |
| 671 | * function is automatically unregistered on driver detach. This function | 672 | * function is automatically unregistered on driver detach. This function |
| @@ -678,7 +679,9 @@ static void devm_iio_trigger_unreg(struct device *dev, void *res) · 6 unmodified lines | |||
| 678 | * RETURNS: | 679 | * RETURNS: |
| 679 | * 0 on success, negative error number on failure. | 680 | * 0 on success, negative error number on failure. |
| 680 | */ | 681 | */ |
| 681 | int devm_iio_trigger_register(struct device *dev, struct iio_trigger *trig_info) | 682 | int __devm_iio_trigger_register(struct device *dev, |
| 683 | struct iio_trigger *trig_info, | ||
| 684 | struct module *this_mod) | ||
| 682 | { | 685 | { |
| 683 | struct iio_trigger **ptr; | 686 | struct iio_trigger **ptr; |
| 684 | int ret; | 687 | int ret; |
| @@ -688,7 +691,7 @@ int devm_iio_trigger_register(struct device *dev, struct iio_trigger *trig_info) · 3 unmodified lines | |||
| 688 | return -ENOMEM; | 691 | return -ENOMEM; |
| 689 | 692 | ||
| 690 | *ptr = trig_info; | 693 | *ptr = trig_info; |
| 691 | ret = iio_trigger_register(trig_info); | 694 | ret = __iio_trigger_register(trig_info, this_mod); |
| 692 | if (!ret) | 695 | if (!ret) |
| 693 | devres_add(dev, ptr); | 696 | devres_add(dev, ptr); |
| 694 | else | 697 | else |
| @@ -696,7 +699,7 @@ int devm_iio_trigger_register(struct device *dev, struct iio_trigger *trig_info) · 1 unmodified line | |||
| 696 | 699 | ||
| 697 | return ret; | 700 | return ret; |
| 698 | } | 701 | } |
| 699 | EXPORT_SYMBOL_GPL(devm_iio_trigger_register); | 702 | EXPORT_SYMBOL_GPL(__devm_iio_trigger_register); |
| 700 | 703 | ||
| 701 | /** | 704 | /** |
| 702 | * devm_iio_trigger_unregister - Resource-managed iio_trigger_unregister() | 705 | * devm_iio_trigger_unregister - Resource-managed iio_trigger_unregister() |
| @@ -171,7 +171,6 @@ static int acpi_als_read_raw(struct iio_dev *indio_dev, · 170 unmodified lines | |||
| 171 | } | 171 | } |
| 172 | 172 | ||
| 173 | static const struct iio_info acpi_als_info = { | 173 | static const struct iio_info acpi_als_info = { |
| 174 | .driver_module = THIS_MODULE, | ||
| 175 | .read_raw = acpi_als_read_raw, | 174 | .read_raw = acpi_als_read_raw, |
| 176 | }; | 175 | }; |
| 177 | 176 | ||
| @@ -245,7 +245,6 @@ static const struct iio_info adjd_s311_info = { · 244 unmodified lines | |||
| 245 | .read_raw = adjd_s311_read_raw, | 245 | .read_raw = adjd_s311_read_raw, |
| 246 | .write_raw = adjd_s311_write_raw, | 246 | .write_raw = adjd_s311_write_raw, |
| 247 | .update_scan_mode = adjd_s311_update_scan_mode, | 247 | .update_scan_mode = adjd_s311_update_scan_mode, |
| 248 | .driver_module = THIS_MODULE, | ||
| 249 | }; | 248 | }; |
| 250 | 249 | ||
| 251 | static int adjd_s311_probe(struct i2c_client *client, | 250 | static int adjd_s311_probe(struct i2c_client *client, |
| @@ -168,7 +168,6 @@ static int al3320a_write_raw(struct iio_dev *indio_dev, · 167 unmodified lines | |||
| 168 | } | 168 | } |
| 169 | 169 | ||
| 170 | static const struct iio_info al3320a_info = { | 170 | static const struct iio_info al3320a_info = { |
| 171 | .driver_module = THIS_MODULE, | ||
| 172 | .read_raw = al3320a_read_raw, | 171 | .read_raw = al3320a_read_raw, |
| 173 | .write_raw = al3320a_write_raw, | 172 | .write_raw = al3320a_write_raw, |
| 174 | .attrs = &al3320a_attribute_group, | 173 | .attrs = &al3320a_attribute_group, |
| @@ -337,12 +337,10 @@ static int apds9300_write_interrupt_config(struct iio_dev *indio_dev, · 336 unmodified lines | |||
| 337 | } | 337 | } |
| 338 | 338 | ||
| 339 | static const struct iio_info apds9300_info_no_irq = { | 339 | static const struct iio_info apds9300_info_no_irq = { |
| 340 | .driver_module = THIS_MODULE, | ||
| 341 | .read_raw = apds9300_read_raw, | 340 | .read_raw = apds9300_read_raw, |
| 342 | }; | 341 | }; |
| 343 | 342 | ||
| 344 | static const struct iio_info apds9300_info = { | 343 | static const struct iio_info apds9300_info = { |
| 345 | .driver_module = THIS_MODULE, | ||
| 346 | .read_raw = apds9300_read_raw, | 344 | .read_raw = apds9300_read_raw, |
| 347 | .read_event_value = apds9300_read_thresh, | 345 | .read_event_value = apds9300_read_thresh, |
| 348 | .write_event_value = apds9300_write_thresh, | 346 | .write_event_value = apds9300_write_thresh, |
| @@ -744,7 +744,6 @@ static int apds9960_write_event_config(struct iio_dev *indio_dev, · 743 unmodified lines | |||
| 744 | } | 744 | } |
| 745 | 745 | ||
| 746 | static const struct iio_info apds9960_info = { | 746 | static const struct iio_info apds9960_info = { |
| 747 | .driver_module = THIS_MODULE, | ||
| 748 | .attrs = &apds9960_attribute_group, | 747 | .attrs = &apds9960_attribute_group, |
| 749 | .read_raw = apds9960_read_raw, | 748 | .read_raw = apds9960_read_raw, |
| 750 | .write_raw = apds9960_write_raw, | 749 | .write_raw = apds9960_write_raw, |
| @@ -217,7 +217,6 @@ static const struct attribute_group bh1750_attribute_group = { · 216 unmodified lines | |||
| 217 | }; | 217 | }; |
| 218 | 218 | ||
| 219 | static const struct iio_info bh1750_info = { | 219 | static const struct iio_info bh1750_info = { |
| 220 | .driver_module = THIS_MODULE, | ||
| 221 | .attrs = &bh1750_attribute_group, | 220 | .attrs = &bh1750_attribute_group, |
| 222 | .read_raw = bh1750_read_raw, | 221 | .read_raw = bh1750_read_raw, |
| 223 | .write_raw = bh1750_write_raw, | 222 | .write_raw = bh1750_write_raw, |
| @@ -128,7 +128,6 @@ static int bh1780_read_raw(struct iio_dev *indio_dev, · 127 unmodified lines | |||
| 128 | } | 128 | } |
| 129 | 129 | ||
| 130 | static const struct iio_info bh1780_info = { | 130 | static const struct iio_info bh1780_info = { |
| 131 | .driver_module = THIS_MODULE, | ||
| 132 | .read_raw = bh1780_read_raw, | 131 | .read_raw = bh1780_read_raw, |
| 133 | .debugfs_reg_access = bh1780_debugfs_reg_access, | 132 | .debugfs_reg_access = bh1780_debugfs_reg_access, |
| 134 | }; | 133 | }; |
| @@ -292,7 +292,6 @@ static const struct attribute_group cm32181_attribute_group = { · 291 unmodified lines | |||
| 292 | }; | 292 | }; |
| 293 | 293 | ||
| 294 | static const struct iio_info cm32181_info = { | 294 | static const struct iio_info cm32181_info = { |
| 295 | .driver_module = THIS_MODULE, | ||
| 296 | .read_raw = &cm32181_read_raw, | 295 | .read_raw = &cm32181_read_raw, |
| 297 | .write_raw = &cm32181_write_raw, | 296 | .write_raw = &cm32181_write_raw, |
| 298 | .attrs = &cm32181_attribute_group, | 297 | .attrs = &cm32181_attribute_group, |
| @@ -322,7 +322,6 @@ static const struct attribute_group cm3232_attribute_group = { · 321 unmodified lines | |||
| 322 | }; | 322 | }; |
| 323 | 323 | ||
| 324 | static const struct iio_info cm3232_info = { | 324 | static const struct iio_info cm3232_info = { |
| 325 | .driver_module = THIS_MODULE, | ||
| 326 | .read_raw = &cm3232_read_raw, | 325 | .read_raw = &cm3232_read_raw, |
| 327 | .write_raw = &cm3232_write_raw, | 326 | .write_raw = &cm3232_write_raw, |
| 328 | .attrs = &cm3232_attribute_group, | 327 | .attrs = &cm3232_attribute_group, |
| @@ -211,7 +211,6 @@ static int cm3323_write_raw(struct iio_dev *indio_dev, · 210 unmodified lines | |||
| 211 | } | 211 | } |
| 212 | 212 | ||
| 213 | static const struct iio_info cm3323_info = { | 213 | static const struct iio_info cm3323_info = { |
| 214 | .driver_module = THIS_MODULE, | ||
| 215 | .read_raw = cm3323_read_raw, | 214 | .read_raw = cm3323_read_raw, |
| 216 | .write_raw = cm3323_write_raw, | 215 | .write_raw = cm3323_write_raw, |
| 217 | .attrs = &cm3323_attribute_group, | 216 | .attrs = &cm3323_attribute_group, |
| @@ -126,7 +126,6 @@ static int cm3605_read_raw(struct iio_dev *indio_dev, · 125 unmodified lines | |||
| 126 | } | 126 | } |
| 127 | 127 | ||
| 128 | static const struct iio_info cm3605_info = { | 128 | static const struct iio_info cm3605_info = { |
| 129 | .driver_module = THIS_MODULE, | ||
| 130 | .read_raw = cm3605_read_raw, | 129 | .read_raw = cm3605_read_raw, |
| 131 | }; | 130 | }; |
| 132 | 131 | ||
| @@ -612,7 +612,6 @@ static const struct attribute_group cm36651_attribute_group = { · 611 unmodified lines | |||
| 612 | }; | 612 | }; |
| 613 | 613 | ||
| 614 | static const struct iio_info cm36651_info = { | 614 | static const struct iio_info cm36651_info = { |
| 615 | .driver_module = THIS_MODULE, | ||
| 616 | .read_raw = &cm36651_read_raw, | 615 | .read_raw = &cm36651_read_raw, |
| 617 | .write_raw = &cm36651_write_raw, | 616 | .write_raw = &cm36651_write_raw, |
| 618 | .read_event_value = &cm36651_read_prox_thresh, | 617 | .read_event_value = &cm36651_read_prox_thresh, |
| @@ -175,7 +175,6 @@ static int cros_ec_light_prox_write(struct iio_dev *indio_dev, · 174 unmodified lines | |||
| 175 | static const struct iio_info cros_ec_light_prox_info = { | 175 | static const struct iio_info cros_ec_light_prox_info = { |
| 176 | .read_raw = &cros_ec_light_prox_read, | 176 | .read_raw = &cros_ec_light_prox_read, |
| 177 | .write_raw = &cros_ec_light_prox_write, | 177 | .write_raw = &cros_ec_light_prox_write, |
| 178 | .driver_module = THIS_MODULE, | ||
| 179 | }; | 178 | }; |
| 180 | 179 | ||
| 181 | static int cros_ec_light_prox_probe(struct platform_device *pdev) | 180 | static int cros_ec_light_prox_probe(struct platform_device *pdev) |
| @@ -1384,7 +1384,6 @@ static const struct iio_info gp2ap020a00f_info = { · 1383 unmodified lines | |||
| 1384 | .read_event_config = &gp2ap020a00f_read_event_config, | 1384 | .read_event_config = &gp2ap020a00f_read_event_config, |
| 1385 | .write_event_value = &gp2ap020a00f_write_event_val, | 1385 | .write_event_value = &gp2ap020a00f_write_event_val, |
| 1386 | .write_event_config = &gp2ap020a00f_write_event_config, | 1386 | .write_event_config = &gp2ap020a00f_write_event_config, |
| 1387 | .driver_module = THIS_MODULE, | ||
| 1388 | }; | 1387 | }; |
| 1389 | 1388 | ||
| 1390 | static int gp2ap020a00f_buffer_postenable(struct iio_dev *indio_dev) | 1389 | static int gp2ap020a00f_buffer_postenable(struct iio_dev *indio_dev) |
| @@ -1481,7 +1480,6 @@ static const struct iio_buffer_setup_ops gp2ap020a00f_buffer_setup_ops = { · 90 unmodified lines | |||
| 1481 | }; | 1480 | }; |
| 1482 | 1481 | ||
| 1483 | static const struct iio_trigger_ops gp2ap020a00f_trigger_ops = { | 1482 | static const struct iio_trigger_ops gp2ap020a00f_trigger_ops = { |
| 1484 | .owner = THIS_MODULE, | ||
| 1485 | }; | 1483 | }; |
| 1486 | 1484 | ||
| 1487 | static int gp2ap020a00f_probe(struct i2c_client *client, | 1485 | static int gp2ap020a00f_probe(struct i2c_client *client, |
| @@ -177,7 +177,6 @@ static int als_write_raw(struct iio_dev *indio_dev, · 176 unmodified lines | |||
| 177 | } | 177 | } |
| 178 | 178 | ||
| 179 | static const struct iio_info als_info = { | 179 | static const struct iio_info als_info = { |
| 180 | .driver_module = THIS_MODULE, | ||
| 181 | .read_raw = &als_read_raw, | 180 | .read_raw = &als_read_raw, |
| 182 | .write_raw = &als_write_raw, | 181 | .write_raw = &als_write_raw, |
| 183 | }; | 182 | }; |
| @@ -156,7 +156,6 @@ static int prox_write_raw(struct iio_dev *indio_dev, · 155 unmodified lines | |||
| 156 | } | 156 | } |
| 157 | 157 | ||
| 158 | static const struct iio_info prox_info = { | 158 | static const struct iio_info prox_info = { |
| 159 | .driver_module = THIS_MODULE, | ||
| 160 | .read_raw = &prox_read_raw, | 159 | .read_raw = &prox_read_raw, |
| 161 | .write_raw = &prox_write_raw, | 160 | .write_raw = &prox_write_raw, |
| 162 | }; | 161 | }; |
| @@ -624,14 +624,12 @@ static int isl29018_chip_init(struct isl29018_chip *chip) · 623 unmodified lines | |||
| 624 | 624 | ||
| 625 | static const struct iio_info isl29018_info = { | 625 | static const struct iio_info isl29018_info = { |
| 626 | .attrs = &isl29018_group, | 626 | .attrs = &isl29018_group, |
| 627 | .driver_module = THIS_MODULE, | ||
| 628 | .read_raw = isl29018_read_raw, | 627 | .read_raw = isl29018_read_raw, |
| 629 | .write_raw = isl29018_write_raw, | 628 | .write_raw = isl29018_write_raw, |
| 630 | }; | 629 | }; |
| 631 | 630 | ||
| 632 | static const struct iio_info isl29023_info = { | 631 | static const struct iio_info isl29023_info = { |
| 633 | .attrs = &isl29023_group, | 632 | .attrs = &isl29023_group, |
| 634 | .driver_module = THIS_MODULE, | ||
| 635 | .read_raw = isl29018_read_raw, | 633 | .read_raw = isl29018_read_raw, |
| 636 | .write_raw = isl29018_write_raw, | 634 | .write_raw = isl29018_write_raw, |
| 637 | }; | 635 | }; |
| @@ -536,7 +536,6 @@ static const struct iio_chan_spec isl29028_channels[] = { · 535 unmodified lines | |||
| 536 | 536 | ||
| 537 | static const struct iio_info isl29028_info = { | 537 | static const struct iio_info isl29028_info = { |
| 538 | .attrs = &isl29108_group, | 538 | .attrs = &isl29108_group, |
| 539 | .driver_module = THIS_MODULE, | ||
| 540 | .read_raw = isl29028_read_raw, | 539 | .read_raw = isl29028_read_raw, |
| 541 | .write_raw = isl29028_write_raw, | 540 | .write_raw = isl29028_write_raw, |
| 542 | }; | 541 | }; |
| @@ -214,7 +214,6 @@ static const struct iio_info isl29125_info = { · 213 unmodified lines | |||
| 214 | .read_raw = isl29125_read_raw, | 214 | .read_raw = isl29125_read_raw, |
| 215 | .write_raw = isl29125_write_raw, | 215 | .write_raw = isl29125_write_raw, |
| 216 | .attrs = &isl29125_attribute_group, | 216 | .attrs = &isl29125_attribute_group, |
| 217 | .driver_module = THIS_MODULE, | ||
| 218 | }; | 217 | }; |
| 219 | 218 | ||
| 220 | static int isl29125_buffer_preenable(struct iio_dev *indio_dev) | 219 | static int isl29125_buffer_preenable(struct iio_dev *indio_dev) |
| @@ -271,7 +271,6 @@ static const struct iio_chan_spec jsa1212_channels[] = { · 270 unmodified lines | |||
| 271 | }; | 271 | }; |
| 272 | 272 | ||
| 273 | static const struct iio_info jsa1212_info = { | 273 | static const struct iio_info jsa1212_info = { |
| 274 | .driver_module = THIS_MODULE, | ||
| 275 | .read_raw = &jsa1212_read_raw, | 274 | .read_raw = &jsa1212_read_raw, |
| 276 | }; | 275 | }; |
| 277 | 276 | ||
| @@ -827,7 +827,6 @@ static int lm3533_als_disable(struct lm3533_als *als) · 826 unmodified lines | |||
| 827 | static const struct iio_info lm3533_als_info = { | 827 | static const struct iio_info lm3533_als_info = { |
| 828 | .attrs = &lm3533_als_attribute_group, | 828 | .attrs = &lm3533_als_attribute_group, |
| 829 | .event_attrs = &lm3533_als_event_attribute_group, | 829 | .event_attrs = &lm3533_als_event_attribute_group, |
| 830 | .driver_module = THIS_MODULE, | ||
| 831 | .read_raw = &lm3533_als_read_raw, | 830 | .read_raw = &lm3533_als_read_raw, |
| 832 | }; | 831 | }; |
| 833 | 832 | ||
| @@ -1158,7 +1158,6 @@ static const struct iio_info ltr501_info_no_irq = { · 1157 unmodified lines | |||
| 1158 | .read_raw = ltr501_read_raw, | 1158 | .read_raw = ltr501_read_raw, |
| 1159 | .write_raw = ltr501_write_raw, | 1159 | .write_raw = ltr501_write_raw, |
| 1160 | .attrs = <r501_attribute_group, | 1160 | .attrs = <r501_attribute_group, |
| 1161 | .driver_module = THIS_MODULE, | ||
| 1162 | }; | 1161 | }; |
| 1163 | 1162 | ||
| 1164 | static const struct iio_info ltr501_info = { | 1163 | static const struct iio_info ltr501_info = { |
| @@ -1169,14 +1168,12 @@ static const struct iio_info ltr501_info = { · 4 unmodified lines | |||
| 1169 | .write_event_value = <r501_write_event, | 1168 | .write_event_value = <r501_write_event, |
| 1170 | .read_event_config = <r501_read_event_config, | 1169 | .read_event_config = <r501_read_event_config, |
| 1171 | .write_event_config = <r501_write_event_config, | 1170 | .write_event_config = <r501_write_event_config, |
| 1172 | .driver_module = THIS_MODULE, | ||
| 1173 | }; | 1171 | }; |
| 1174 | 1172 | ||
| 1175 | static const struct iio_info ltr301_info_no_irq = { | 1173 | static const struct iio_info ltr301_info_no_irq = { |
| 1176 | .read_raw = ltr501_read_raw, | 1174 | .read_raw = ltr501_read_raw, |
| 1177 | .write_raw = ltr501_write_raw, | 1175 | .write_raw = ltr501_write_raw, |
| 1178 | .attrs = <r301_attribute_group, | 1176 | .attrs = <r301_attribute_group, |
| 1179 | .driver_module = THIS_MODULE, | ||
| 1180 | }; | 1177 | }; |
| 1181 | 1178 | ||
| 1182 | static const struct iio_info ltr301_info = { | 1179 | static const struct iio_info ltr301_info = { |
| @@ -1187,7 +1184,6 @@ static const struct iio_info ltr301_info = { · 4 unmodified lines | |||
| 1187 | .write_event_value = <r501_write_event, | 1184 | .write_event_value = <r501_write_event, |
| 1188 | .read_event_config = <r501_read_event_config, | 1185 | .read_event_config = <r501_read_event_config, |
| 1189 | .write_event_config = <r501_write_event_config, | 1186 | .write_event_config = <r501_write_event_config, |
| 1190 | .driver_module = THIS_MODULE, | ||
| 1191 | }; | 1187 | }; |
| 1192 | 1188 | ||
| 1193 | static struct ltr501_chip_info ltr501_chip_info_tbl[] = { | 1189 | static struct ltr501_chip_info ltr501_chip_info_tbl[] = { |
| @@ -402,7 +402,6 @@ static const struct attribute_group max44000_attribute_group = { · 401 unmodified lines | |||
| 402 | }; | 402 | }; |
| 403 | 403 | ||
| 404 | static const struct iio_info max44000_info = { | 404 | static const struct iio_info max44000_info = { |
| 405 | .driver_module = THIS_MODULE, | ||
| 406 | .read_raw = max44000_read_raw, | 405 | .read_raw = max44000_read_raw, |
| 407 | .write_raw = max44000_write_raw, | 406 | .write_raw = max44000_write_raw, |
| 408 | .write_raw_get_fmt = max44000_write_raw_get_fmt, | 407 | .write_raw_get_fmt = max44000_write_raw_get_fmt, |
| @@ -585,7 +585,6 @@ err: · 584 unmodified lines | |||
| 585 | } | 585 | } |
| 586 | 586 | ||
| 587 | static const struct iio_info opt3001_info = { | 587 | static const struct iio_info opt3001_info = { |
| 588 | .driver_module = THIS_MODULE, | ||
| 589 | .attrs = &opt3001_attribute_group, | 588 | .attrs = &opt3001_attribute_group, |
| 590 | .read_raw = opt3001_read_raw, | 589 | .read_raw = opt3001_read_raw, |
| 591 | .write_raw = opt3001_write_raw, | 590 | .write_raw = opt3001_write_raw, |
| @@ -306,7 +306,6 @@ static int pa12203001_write_raw(struct iio_dev *indio_dev, · 305 unmodified lines | |||
| 306 | } | 306 | } |
| 307 | 307 | ||
| 308 | static const struct iio_info pa12203001_info = { | 308 | static const struct iio_info pa12203001_info = { |
| 309 | .driver_module = THIS_MODULE, | ||
| 310 | .read_raw = pa12203001_read_raw, | 309 | .read_raw = pa12203001_read_raw, |
| 311 | .write_raw = pa12203001_write_raw, | 310 | .write_raw = pa12203001_write_raw, |
| 312 | .attrs = &pa12203001_attr_group, | 311 | .attrs = &pa12203001_attr_group, |
| @@ -538,7 +538,6 @@ static int rpr0521_pxs_drdy_set_state(struct iio_trigger *trigger, · 537 unmodified lines | |||
| 538 | 538 | ||
| 539 | static const struct iio_trigger_ops rpr0521_trigger_ops = { | 539 | static const struct iio_trigger_ops rpr0521_trigger_ops = { |
| 540 | .set_trigger_state = rpr0521_pxs_drdy_set_state, | 540 | .set_trigger_state = rpr0521_pxs_drdy_set_state, |
| 541 | .owner = THIS_MODULE, | ||
| 542 | }; | 541 | }; |
| 543 | 542 | ||
| 544 | 543 | ||
| @@ -830,7 +829,6 @@ static int rpr0521_write_raw(struct iio_dev *indio_dev, · 285 unmodified lines | |||
| 830 | } | 829 | } |
| 831 | 830 | ||
| 832 | static const struct iio_info rpr0521_info = { | 831 | static const struct iio_info rpr0521_info = { |
| 833 | .driver_module = THIS_MODULE, | ||
| 834 | .read_raw = rpr0521_read_raw, | 832 | .read_raw = rpr0521_read_raw, |
| 835 | .write_raw = rpr0521_write_raw, | 833 | .write_raw = rpr0521_write_raw, |
| 836 | .attrs = &rpr0521_attribute_group, | 834 | .attrs = &rpr0521_attribute_group, |
| @@ -989,14 +989,12 @@ static const struct attribute_group si114x_attribute_group = { · 988 unmodified lines | |||
| 989 | static const struct iio_info si1132_info = { | 989 | static const struct iio_info si1132_info = { |
| 990 | .read_raw = si1145_read_raw, | 990 | .read_raw = si1145_read_raw, |
| 991 | .write_raw = si1145_write_raw, | 991 | .write_raw = si1145_write_raw, |
| 992 | .driver_module = THIS_MODULE, | ||
| 993 | .attrs = &si1132_attribute_group, | 992 | .attrs = &si1132_attribute_group, |
| 994 | }; | 993 | }; |
| 995 | 994 | ||
| 996 | static const struct iio_info si114x_info = { | 995 | static const struct iio_info si114x_info = { |
| 997 | .read_raw = si1145_read_raw, | 996 | .read_raw = si1145_read_raw, |
| 998 | .write_raw = si1145_write_raw, | 997 | .write_raw = si1145_write_raw, |
| 999 | .driver_module = THIS_MODULE, | ||
| 1000 | .attrs = &si114x_attribute_group, | 998 | .attrs = &si114x_attribute_group, |
| 1001 | }; | 999 | }; |
| 1002 | 1000 | ||
| @@ -1237,7 +1235,6 @@ disable: · 234 unmodified lines | |||
| 1237 | } | 1235 | } |
| 1238 | 1236 | ||
| 1239 | static const struct iio_trigger_ops si1145_trigger_ops = { | 1237 | static const struct iio_trigger_ops si1145_trigger_ops = { |
| 1240 | .owner = THIS_MODULE, | ||
| 1241 | .set_trigger_state = si1145_trigger_set_state, | 1238 | .set_trigger_state = si1145_trigger_set_state, |
| 1242 | }; | 1239 | }; |
| 1243 | 1240 | ||
| @@ -409,7 +409,6 @@ static int stk3310_write_raw(struct iio_dev *indio_dev, · 408 unmodified lines | |||
| 409 | } | 409 | } |
| 410 | 410 | ||
| 411 | static const struct iio_info stk3310_info = { | 411 | static const struct iio_info stk3310_info = { |
| 412 | .driver_module = THIS_MODULE, | ||
| 413 | .read_raw = stk3310_read_raw, | 412 | .read_raw = stk3310_read_raw, |
| 414 | .write_raw = stk3310_write_raw, | 413 | .write_raw = stk3310_write_raw, |
| 415 | .attrs = &stk3310_attribute_group, | 414 | .attrs = &stk3310_attribute_group, |
| @@ -241,7 +241,6 @@ static const struct iio_info tcs3414_info = { · 240 unmodified lines | |||
| 241 | .read_raw = tcs3414_read_raw, | 241 | .read_raw = tcs3414_read_raw, |
| 242 | .write_raw = tcs3414_write_raw, | 242 | .write_raw = tcs3414_write_raw, |
| 243 | .attrs = &tcs3414_attribute_group, | 243 | .attrs = &tcs3414_attribute_group, |
| 244 | .driver_module = THIS_MODULE, | ||
| 245 | }; | 244 | }; |
| 246 | 245 | ||
| 247 | static int tcs3414_buffer_preenable(struct iio_dev *indio_dev) | 246 | static int tcs3414_buffer_preenable(struct iio_dev *indio_dev) |
| @@ -13,7 +13,7 @@ · 12 unmodified lines | |||
| 13 | * | 13 | * |
| 14 | * Datasheet: http://ams.com/eng/content/download/319364/1117183/file/TCS3472_Datasheet_EN_v2.pdf | 14 | * Datasheet: http://ams.com/eng/content/download/319364/1117183/file/TCS3472_Datasheet_EN_v2.pdf |
| 15 | * | 15 | * |
| 16 | * TODO: interrupt support, thresholds, wait time | 16 | * TODO: wait time |
| 17 | */ | 17 | */ |
| 18 | 18 | ||
| 19 | #include <linux/module.h> | 19 | #include <linux/module.h> |
| @@ -23,6 +23,7 @@ · 3 unmodified lines | |||
| 23 | 23 | ||
| 24 | #include <linux/iio/iio.h> | 24 | #include <linux/iio/iio.h> |
| 25 | #include <linux/iio/sysfs.h> | 25 | #include <linux/iio/sysfs.h> |
| 26 | #include <linux/iio/events.h> | ||
| 26 | #include <linux/iio/trigger_consumer.h> | 27 | #include <linux/iio/trigger_consumer.h> |
| 27 | #include <linux/iio/buffer.h> | 28 | #include <linux/iio/buffer.h> |
| 28 | #include <linux/iio/triggered_buffer.h> | 29 | #include <linux/iio/triggered_buffer.h> |
| @@ -31,12 +32,15 @@ · 2 unmodified lines | |||
| 31 | 32 | ||
| 32 | #define TCS3472_COMMAND BIT(7) | 33 | #define TCS3472_COMMAND BIT(7) |
| 33 | #define TCS3472_AUTO_INCR BIT(5) | 34 | #define TCS3472_AUTO_INCR BIT(5) |
| 35 | #define TCS3472_SPECIAL_FUNC (BIT(5) | BIT(6)) | ||
| 36 | |||
| 37 | #define TCS3472_INTR_CLEAR (TCS3472_COMMAND | TCS3472_SPECIAL_FUNC | 0x06) | ||
| 34 | 38 | ||
| 35 | #define TCS3472_ENABLE (TCS3472_COMMAND | 0x00) | 39 | #define TCS3472_ENABLE (TCS3472_COMMAND | 0x00) |
| 36 | #define TCS3472_ATIME (TCS3472_COMMAND | 0x01) | 40 | #define TCS3472_ATIME (TCS3472_COMMAND | 0x01) |
| 37 | #define TCS3472_WTIME (TCS3472_COMMAND | 0x03) | 41 | #define TCS3472_WTIME (TCS3472_COMMAND | 0x03) |
| 38 | #define TCS3472_AILT (TCS3472_COMMAND | 0x04) | 42 | #define TCS3472_AILT (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x04) |
| 39 | #define TCS3472_AIHT (TCS3472_COMMAND | 0x06) | 43 | #define TCS3472_AIHT (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x06) |
| 40 | #define TCS3472_PERS (TCS3472_COMMAND | 0x0c) | 44 | #define TCS3472_PERS (TCS3472_COMMAND | 0x0c) |
| 41 | #define TCS3472_CONFIG (TCS3472_COMMAND | 0x0d) | 45 | #define TCS3472_CONFIG (TCS3472_COMMAND | 0x0d) |
| 42 | #define TCS3472_CONTROL (TCS3472_COMMAND | 0x0f) | 46 | #define TCS3472_CONTROL (TCS3472_COMMAND | 0x0f) |
| @@ -47,19 +51,42 @@ · 4 unmodified lines | |||
| 47 | #define TCS3472_GDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x18) | 51 | #define TCS3472_GDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x18) |
| 48 | #define TCS3472_BDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x1a) | 52 | #define TCS3472_BDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x1a) |
| 49 | 53 | ||
| 54 | #define TCS3472_STATUS_AINT BIT(4) | ||
| 50 | #define TCS3472_STATUS_AVALID BIT(0) | 55 | #define TCS3472_STATUS_AVALID BIT(0) |
| 56 | #define TCS3472_ENABLE_AIEN BIT(4) | ||
| 51 | #define TCS3472_ENABLE_AEN BIT(1) | 57 | #define TCS3472_ENABLE_AEN BIT(1) |
| 52 | #define TCS3472_ENABLE_PON BIT(0) | 58 | #define TCS3472_ENABLE_PON BIT(0) |
| 53 | #define TCS3472_CONTROL_AGAIN_MASK (BIT(0) | BIT(1)) | 59 | #define TCS3472_CONTROL_AGAIN_MASK (BIT(0) | BIT(1)) |
| 54 | 60 | ||
| 55 | struct tcs3472_data { | 61 | struct tcs3472_data { |
| 56 | struct i2c_client *client; | 62 | struct i2c_client *client; |
| 63 | struct mutex lock; | ||
| 64 | u16 low_thresh; | ||
| 65 | u16 high_thresh; | ||
| 57 | u8 enable; | 66 | u8 enable; |
| 58 | u8 control; | 67 | u8 control; |
| 59 | u8 atime; | 68 | u8 atime; |
| 69 | u8 apers; | ||
| 60 | u16 buffer[8]; /* 4 16-bit channels + 64-bit timestamp */ | 70 | u16 buffer[8]; /* 4 16-bit channels + 64-bit timestamp */ |
| 61 | }; | 71 | }; |
| 62 | 72 | ||
| 73 | static const struct iio_event_spec tcs3472_events[] = { | ||
| 74 | { | ||
| 75 | .type = IIO_EV_TYPE_THRESH, | ||
| 76 | .dir = IIO_EV_DIR_RISING, | ||
| 77 | .mask_separate = BIT(IIO_EV_INFO_VALUE), | ||
| 78 | }, { | ||
| 79 | .type = IIO_EV_TYPE_THRESH, | ||
| 80 | .dir = IIO_EV_DIR_FALLING, | ||
| 81 | .mask_separate = BIT(IIO_EV_INFO_VALUE), | ||
| 82 | }, { | ||
| 83 | .type = IIO_EV_TYPE_THRESH, | ||
| 84 | .dir = IIO_EV_DIR_EITHER, | ||
| 85 | .mask_separate = BIT(IIO_EV_INFO_ENABLE) | | ||
| 86 | BIT(IIO_EV_INFO_PERIOD), | ||
| 87 | }, | ||
| 88 | }; | ||
| 89 | |||
| 63 | #define TCS3472_CHANNEL(_color, _si, _addr) { \ | 90 | #define TCS3472_CHANNEL(_color, _si, _addr) { \ |
| 64 | .type = IIO_INTENSITY, \ | 91 | .type = IIO_INTENSITY, \ |
| 65 | .modified = 1, \ | 92 | .modified = 1, \ |
| @@ -75,6 +102,8 @@ struct tcs3472_data { · 9 unmodified lines | |||
| 75 | .storagebits = 16, \ | 102 | .storagebits = 16, \ |
| 76 | .endianness = IIO_CPU, \ | 103 | .endianness = IIO_CPU, \ |
| 77 | }, \ | 104 | }, \ |
| 105 | .event_spec = _si ? NULL : tcs3472_events, \ | ||
| 106 | .num_event_specs = _si ? 0 : ARRAY_SIZE(tcs3472_events), \ | ||
| 78 | } | 107 | } |
| 79 | 108 | ||
| 80 | static const int tcs3472_agains[] = { 1, 4, 16, 60 }; | 109 | static const int tcs3472_agains[] = { 1, 4, 16, 60 }; |
| @@ -182,6 +211,166 @@ static int tcs3472_write_raw(struct iio_dev *indio_dev, · 101 unmodified lines | |||
| 182 | return -EINVAL; | 211 | return -EINVAL; |
| 183 | } | 212 | } |
| 184 | 213 | ||
| 214 | /* | ||
| 215 | * Translation from APERS field value to the number of consecutive out-of-range | ||
| 216 | * clear channel values before an interrupt is generated | ||
| 217 | */ | ||
| 218 | static const int tcs3472_intr_pers[] = { | ||
| 219 | 0, 1, 2, 3, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60 | ||
| 220 | }; | ||
| 221 | |||
| 222 | static int tcs3472_read_event(struct iio_dev *indio_dev, | ||
| 223 | const struct iio_chan_spec *chan, enum iio_event_type type, | ||
| 224 | enum iio_event_direction dir, enum iio_event_info info, int *val, | ||
| 225 | int *val2) | ||
| 226 | { | ||
| 227 | struct tcs3472_data *data = iio_priv(indio_dev); | ||
| 228 | int ret; | ||
| 229 | unsigned int period; | ||
| 230 | |||
| 231 | mutex_lock(&data->lock); | ||
| 232 | |||
| 233 | switch (info) { | ||
| 234 | case IIO_EV_INFO_VALUE: | ||
| 235 | *val = (dir == IIO_EV_DIR_RISING) ? | ||
| 236 | data->high_thresh : data->low_thresh; | ||
| 237 | ret = IIO_VAL_INT; | ||
| 238 | break; | ||
| 239 | case IIO_EV_INFO_PERIOD: | ||
| 240 | period = (256 - data->atime) * 2400 * | ||
| 241 | tcs3472_intr_pers[data->apers]; | ||
| 242 | *val = period / USEC_PER_SEC; | ||
| 243 | *val2 = period % USEC_PER_SEC; | ||
| 244 | ret = IIO_VAL_INT_PLUS_MICRO; | ||
| 245 | break; | ||
| 246 | default: | ||
| 247 | ret = -EINVAL; | ||
| 248 | break; | ||
| 249 | } | ||
| 250 | |||
| 251 | mutex_unlock(&data->lock); | ||
| 252 | |||
| 253 | return ret; | ||
| 254 | } | ||
| 255 | |||
| 256 | static int tcs3472_write_event(struct iio_dev *indio_dev, | ||
| 257 | const struct iio_chan_spec *chan, enum iio_event_type type, | ||
| 258 | enum iio_event_direction dir, enum iio_event_info info, int val, | ||
| 259 | int val2) | ||
| 260 | { | ||
| 261 | struct tcs3472_data *data = iio_priv(indio_dev); | ||
| 262 | int ret; | ||
| 263 | u8 command; | ||
| 264 | int period; | ||
| 265 | int i; | ||
| 266 | |||
| 267 | mutex_lock(&data->lock); | ||
| 268 | switch (info) { | ||
| 269 | case IIO_EV_INFO_VALUE: | ||
| 270 | switch (dir) { | ||
| 271 | case IIO_EV_DIR_RISING: | ||
| 272 | command = TCS3472_AIHT; | ||
| 273 | break; | ||
| 274 | case IIO_EV_DIR_FALLING: | ||
| 275 | command = TCS3472_AILT; | ||
| 276 | break; | ||
| 277 | default: | ||
| 278 | ret = -EINVAL; | ||
| 279 | goto error; | ||
| 280 | } | ||
| 281 | ret = i2c_smbus_write_word_data(data->client, command, val); | ||
| 282 | if (ret) | ||
| 283 | goto error; | ||
| 284 | |||
| 285 | if (dir == IIO_EV_DIR_RISING) | ||
| 286 | data->high_thresh = val; | ||
| 287 | else | ||
| 288 | data->low_thresh = val; | ||
| 289 | break; | ||
| 290 | case IIO_EV_INFO_PERIOD: | ||
| 291 | period = val * USEC_PER_SEC + val2; | ||
| 292 | for (i = 1; i < ARRAY_SIZE(tcs3472_intr_pers) - 1; i++) { | ||
| 293 | if (period <= (256 - data->atime) * 2400 * | ||
| 294 | tcs3472_intr_pers[i]) | ||
| 295 | break; | ||
| 296 | } | ||
| 297 | ret = i2c_smbus_write_byte_data(data->client, TCS3472_PERS, i); | ||
| 298 | if (ret) | ||
| 299 | goto error; | ||
| 300 | |||
| 301 | data->apers = i; | ||
| 302 | break; | ||
| 303 | default: | ||
| 304 | ret = -EINVAL; | ||
| 305 | break; | ||
| 306 | } | ||
| 307 | error: | ||
| 308 | mutex_unlock(&data->lock); | ||
| 309 | |||
| 310 | return ret; | ||
| 311 | } | ||
| 312 | |||
| 313 | static int tcs3472_read_event_config(struct iio_dev *indio_dev, | ||
| 314 | const struct iio_chan_spec *chan, enum iio_event_type type, | ||
| 315 | enum iio_event_direction dir) | ||
| 316 | { | ||
| 317 | struct tcs3472_data *data = iio_priv(indio_dev); | ||
| 318 | int ret; | ||
| 319 | |||
| 320 | mutex_lock(&data->lock); | ||
| 321 | ret = !!(data->enable & TCS3472_ENABLE_AIEN); | ||
| 322 | mutex_unlock(&data->lock); | ||
| 323 | |||
| 324 | return ret; | ||
| 325 | } | ||
| 326 | |||
| 327 | static int tcs3472_write_event_config(struct iio_dev *indio_dev, | ||
| 328 | const struct iio_chan_spec *chan, enum iio_event_type type, | ||
| 329 | enum iio_event_direction dir, int state) | ||
| 330 | { | ||
| 331 | struct tcs3472_data *data = iio_priv(indio_dev); | ||
| 332 | int ret = 0; | ||
| 333 | u8 enable_old; | ||
| 334 | |||
| 335 | mutex_lock(&data->lock); | ||
| 336 | |||
| 337 | enable_old = data->enable; | ||
| 338 | |||
| 339 | if (state) | ||
| 340 | data->enable |= TCS3472_ENABLE_AIEN; | ||
| 341 | else | ||
| 342 | data->enable &= ~TCS3472_ENABLE_AIEN; | ||
| 343 | |||
| 344 | if (enable_old != data->enable) { | ||
| 345 | ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE, | ||
| 346 | data->enable); | ||
| 347 | if (ret) | ||
| 348 | data->enable = enable_old; | ||
| 349 | } | ||
| 350 | mutex_unlock(&data->lock); | ||
| 351 | |||
| 352 | return ret; | ||
| 353 | } | ||
| 354 | |||
| 355 | static irqreturn_t tcs3472_event_handler(int irq, void *priv) | ||
| 356 | { | ||
| 357 | struct iio_dev *indio_dev = priv; | ||
| 358 | struct tcs3472_data *data = iio_priv(indio_dev); | ||
| 359 | int ret; | ||
| 360 | |||
| 361 | ret = i2c_smbus_read_byte_data(data->client, TCS3472_STATUS); | ||
| 362 | if (ret >= 0 && (ret & TCS3472_STATUS_AINT)) { | ||
| 363 | iio_push_event(indio_dev, IIO_UNMOD_EVENT_CODE(IIO_INTENSITY, 0, | ||
| 364 | IIO_EV_TYPE_THRESH, | ||
| 365 | IIO_EV_DIR_EITHER), | ||
| 366 | iio_get_time_ns(indio_dev)); | ||
| 367 | |||
| 368 | i2c_smbus_read_byte_data(data->client, TCS3472_INTR_CLEAR); | ||
| 369 | } | ||
| 370 | |||
| 371 | return IRQ_HANDLED; | ||
| 372 | } | ||
| 373 | |||
| 185 | static irqreturn_t tcs3472_trigger_handler(int irq, void *p) | 374 | static irqreturn_t tcs3472_trigger_handler(int irq, void *p) |
| 186 | { | 375 | { |
| 187 | struct iio_poll_func *pf = p; | 376 | struct iio_poll_func *pf = p; |
| @@ -245,8 +434,11 @@ static const struct attribute_group tcs3472_attribute_group = { · 57 unmodified lines | |||
| 245 | static const struct iio_info tcs3472_info = { | 434 | static const struct iio_info tcs3472_info = { |
| 246 | .read_raw = tcs3472_read_raw, | 435 | .read_raw = tcs3472_read_raw, |
| 247 | .write_raw = tcs3472_write_raw, | 436 | .write_raw = tcs3472_write_raw, |
| 437 | .read_event_value = tcs3472_read_event, | ||
| 438 | .write_event_value = tcs3472_write_event, | ||
| 439 | .read_event_config = tcs3472_read_event_config, | ||
| 440 | .write_event_config = tcs3472_write_event_config, | ||
| 248 | .attrs = &tcs3472_attribute_group, | 441 | .attrs = &tcs3472_attribute_group, |
| 249 | .driver_module = THIS_MODULE, | ||
| 250 | }; | 442 | }; |
| 251 | 443 | ||
| 252 | static int tcs3472_probe(struct i2c_client *client, | 444 | static int tcs3472_probe(struct i2c_client *client, |
| @@ -263,6 +455,7 @@ static int tcs3472_probe(struct i2c_client *client, · 10 unmodified lines | |||
| 263 | data = iio_priv(indio_dev); | 455 | data = iio_priv(indio_dev); |
| 264 | i2c_set_clientdata(client, indio_dev); | 456 | i2c_set_clientdata(client, indio_dev); |
| 265 | data->client = client; | 457 | data->client = client; |
| 458 | mutex_init(&data->lock); | ||
| 266 | 459 | ||
| 267 | indio_dev->dev.parent = &client->dev; | 460 | indio_dev->dev.parent = &client->dev; |
| 268 | indio_dev->info = &tcs3472_info; | 461 | indio_dev->info = &tcs3472_info; |
| @@ -292,12 +485,29 @@ static int tcs3472_probe(struct i2c_client *client, · 23 unmodified lines | |||
| 292 | return ret; | 485 | return ret; |
| 293 | data->atime = ret; | 486 | data->atime = ret; |
| 294 | 487 | ||
| 488 | ret = i2c_smbus_read_word_data(data->client, TCS3472_AILT); | ||
| 489 | if (ret < 0) | ||
| 490 | return ret; | ||
| 491 | data->low_thresh = ret; | ||
| 492 | |||
| 493 | ret = i2c_smbus_read_word_data(data->client, TCS3472_AIHT); | ||
| 494 | if (ret < 0) | ||
| 495 | return ret; | ||
| 496 | data->high_thresh = ret; | ||
| 497 | |||
| 498 | data->apers = 1; | ||
| 499 | ret = i2c_smbus_write_byte_data(data->client, TCS3472_PERS, | ||
| 500 | data->apers); | ||
| 501 | if (ret < 0) | ||
| 502 | return ret; | ||
| 503 | |||
| 295 | ret = i2c_smbus_read_byte_data(data->client, TCS3472_ENABLE); | 504 | ret = i2c_smbus_read_byte_data(data->client, TCS3472_ENABLE); |
| 296 | if (ret < 0) | 505 | if (ret < 0) |
| 297 | return ret; | 506 | return ret; |
| 298 | 507 | ||
| 299 | /* enable device */ | 508 | /* enable device */ |
| 300 | data->enable = ret | TCS3472_ENABLE_PON | TCS3472_ENABLE_AEN; | 509 | data->enable = ret | TCS3472_ENABLE_PON | TCS3472_ENABLE_AEN; |
| 510 | data->enable &= ~TCS3472_ENABLE_AIEN; | ||
| 301 | ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE, | 511 | ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE, |
| 302 | data->enable); | 512 | data->enable); |
| 303 | if (ret < 0) | 513 | if (ret < 0) |
| @@ -308,12 +518,24 @@ static int tcs3472_probe(struct i2c_client *client, · 4 unmodified lines | |||
| 308 | if (ret < 0) | 518 | if (ret < 0) |
| 309 | return ret; | 519 | return ret; |
| 310 | 520 | ||
| 521 | if (client->irq) { | ||
| 522 | ret = request_threaded_irq(client->irq, NULL, | ||
| 523 | tcs3472_event_handler, | ||
| 524 | IRQF_TRIGGER_FALLING | IRQF_SHARED | | ||
| 525 | IRQF_ONESHOT, | ||
| 526 | client->name, indio_dev); | ||
| 527 | if (ret) | ||
| 528 | goto buffer_cleanup; | ||
| 529 | } | ||
| 530 | |||
| 311 | ret = iio_device_register(indio_dev); | 531 | ret = iio_device_register(indio_dev); |
| 312 | if (ret < 0) | 532 | if (ret < 0) |
| 313 | goto buffer_cleanup; | 533 | goto free_irq; |
| 314 | 534 | ||
| 315 | return 0; | 535 | return 0; |
| 316 | 536 | ||
| 537 | free_irq: | ||
| 538 | free_irq(client->irq, indio_dev); | ||
| 317 | buffer_cleanup: | 539 | buffer_cleanup: |
| 318 | iio_triggered_buffer_cleanup(indio_dev); | 540 | iio_triggered_buffer_cleanup(indio_dev); |
| 319 | return ret; | 541 | return ret; |
| @@ -321,8 +543,19 @@ buffer_cleanup: · 1 unmodified line | |||
| 321 | 543 | ||
| 322 | static int tcs3472_powerdown(struct tcs3472_data *data) | 544 | static int tcs3472_powerdown(struct tcs3472_data *data) |
| 323 | { | 545 | { |
| 324 | return i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE, | 546 | int ret; |
| 325 | data->enable & ~(TCS3472_ENABLE_AEN | TCS3472_ENABLE_PON)); | 547 | u8 enable_mask = TCS3472_ENABLE_AEN | TCS3472_ENABLE_PON; |
| 548 | |||
| 549 | mutex_lock(&data->lock); | ||
| 550 | |||
| 551 | ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE, | ||
| 552 | data->enable & ~enable_mask); | ||
| 553 | if (!ret) | ||
| 554 | data->enable &= ~enable_mask; | ||
| 555 | |||
| 556 | mutex_unlock(&data->lock); | ||
| 557 | |||
| 558 | return ret; | ||
| 326 | } | 559 | } |
| 327 | 560 | ||
| 328 | static int tcs3472_remove(struct i2c_client *client) | 561 | static int tcs3472_remove(struct i2c_client *client) |
| @@ -330,6 +563,7 @@ static int tcs3472_remove(struct i2c_client *client) · 1 unmodified line | |||
| 330 | struct iio_dev *indio_dev = i2c_get_clientdata(client); | 563 | struct iio_dev *indio_dev = i2c_get_clientdata(client); |
| 331 | 564 | ||
| 332 | iio_device_unregister(indio_dev); | 565 | iio_device_unregister(indio_dev); |
| 566 | free_irq(client->irq, indio_dev); | ||
| 333 | iio_triggered_buffer_cleanup(indio_dev); | 567 | iio_triggered_buffer_cleanup(indio_dev); |
| 334 | tcs3472_powerdown(iio_priv(indio_dev)); | 568 | tcs3472_powerdown(iio_priv(indio_dev)); |
| 335 | 569 | ||
| @@ -348,8 +582,19 @@ static int tcs3472_resume(struct device *dev) · 12 unmodified lines | |||
| 348 | { | 582 | { |
| 349 | struct tcs3472_data *data = iio_priv(i2c_get_clientdata( | 583 | struct tcs3472_data *data = iio_priv(i2c_get_clientdata( |
| 350 | to_i2c_client(dev))); | 584 | to_i2c_client(dev))); |
| 351 | return i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE, | 585 | int ret; |
| 352 | data->enable | (TCS3472_ENABLE_AEN | TCS3472_ENABLE_PON)); | 586 | u8 enable_mask = TCS3472_ENABLE_AEN | TCS3472_ENABLE_PON; |
| 587 | |||
| 588 | mutex_lock(&data->lock); | ||
| 589 | |||
| 590 | ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE, | ||
| 591 | data->enable | enable_mask); | ||
| 592 | if (!ret) | ||
| 593 | data->enable |= enable_mask; | ||
| 594 | |||
| 595 | mutex_unlock(&data->lock); | ||
| 596 | |||
| 597 | return ret; | ||
| 353 | } | 598 | } |
| 354 | #endif | 599 | #endif |
| 355 | 600 | ||
| @@ -697,13 +697,11 @@ static int tsl2563_read_interrupt_config(struct iio_dev *indio_dev, · 696 unmodified lines | |||
| 697 | } | 697 | } |
| 698 | 698 | ||
| 699 | static const struct iio_info tsl2563_info_no_irq = { | 699 | static const struct iio_info tsl2563_info_no_irq = { |
| 700 | .driver_module = THIS_MODULE, | ||
| 701 | .read_raw = &tsl2563_read_raw, | 700 | .read_raw = &tsl2563_read_raw, |
| 702 | .write_raw = &tsl2563_write_raw, | 701 | .write_raw = &tsl2563_write_raw, |
| 703 | }; | 702 | }; |
| 704 | 703 | ||
| 705 | static const struct iio_info tsl2563_info = { | 704 | static const struct iio_info tsl2563_info = { |
| 706 | .driver_module = THIS_MODULE, | ||
| 707 | .read_raw = &tsl2563_read_raw, | 705 | .read_raw = &tsl2563_read_raw, |
| 708 | .write_raw = &tsl2563_write_raw, | 706 | .write_raw = &tsl2563_write_raw, |
| 709 | .read_event_value = &tsl2563_read_thresh, | 707 | .read_event_value = &tsl2563_read_thresh, |
| @@ -804,7 +804,6 @@ static int tsl2583_write_raw(struct iio_dev *indio_dev, · 803 unmodified lines | |||
| 804 | 804 | ||
| 805 | static const struct iio_info tsl2583_info = { | 805 | static const struct iio_info tsl2583_info = { |
| 806 | .attrs = &tsl2583_attribute_group, | 806 | .attrs = &tsl2583_attribute_group, |
| 807 | .driver_module = THIS_MODULE, | ||
| 808 | .read_raw = tsl2583_read_raw, | 807 | .read_raw = tsl2583_read_raw, |
| 809 | .write_raw = tsl2583_write_raw, | 808 | .write_raw = tsl2583_write_raw, |
| 810 | }; | 809 | }; |
| @@ -144,7 +144,6 @@ static const struct iio_info tsl4531_info = { · 143 unmodified lines | |||
| 144 | .read_raw = tsl4531_read_raw, | 144 | .read_raw = tsl4531_read_raw, |
| 145 | .write_raw = tsl4531_write_raw, | 145 | .write_raw = tsl4531_write_raw, |
| 146 | .attrs = &tsl4531_attribute_group, | 146 | .attrs = &tsl4531_attribute_group, |
| 147 | .driver_module = THIS_MODULE, | ||
| 148 | }; | 147 | }; |
| 149 | 148 | ||
| 150 | static int tsl4531_check_id(struct i2c_client *client) | 149 | static int tsl4531_check_id(struct i2c_client *client) |
| @@ -714,7 +714,6 @@ err: · 713 unmodified lines | |||
| 714 | } | 714 | } |
| 715 | 715 | ||
| 716 | static const struct iio_info us5182d_info = { | 716 | static const struct iio_info us5182d_info = { |
| 717 | .driver_module = THIS_MODULE, | ||
| 718 | .read_raw = us5182d_read_raw, | 717 | .read_raw = us5182d_read_raw, |
| 719 | .write_raw = us5182d_write_raw, | 718 | .write_raw = us5182d_write_raw, |
| 720 | .attrs = &us5182d_attr_group, | 719 | .attrs = &us5182d_attr_group, |
| @@ -155,7 +155,6 @@ static int vcnl4000_read_raw(struct iio_dev *indio_dev, · 154 unmodified lines | |||
| 155 | 155 | ||
| 156 | static const struct iio_info vcnl4000_info = { | 156 | static const struct iio_info vcnl4000_info = { |
| 157 | .read_raw = vcnl4000_read_raw, | 157 | .read_raw = vcnl4000_read_raw, |
| 158 | .driver_module = THIS_MODULE, | ||
| 159 | }; | 158 | }; |
| 160 | 159 | ||
| 161 | static int vcnl4000_probe(struct i2c_client *client, | 160 | static int vcnl4000_probe(struct i2c_client *client, |
| @@ -136,7 +136,6 @@ static int veml6070_read_raw(struct iio_dev *indio_dev, · 135 unmodified lines | |||
| 136 | 136 | ||
| 137 | static const struct iio_info veml6070_info = { | 137 | static const struct iio_info veml6070_info = { |
| 138 | .read_raw = veml6070_read_raw, | 138 | .read_raw = veml6070_read_raw, |
| 139 | .driver_module = THIS_MODULE, | ||
| 140 | }; | 139 | }; |
| 141 | 140 | ||
| 142 | static int veml6070_probe(struct i2c_client *client, | 141 | static int veml6070_probe(struct i2c_client *client, |
| @@ -24,6 +24,7 @@ · 23 unmodified lines | |||
| 24 | #include <linux/err.h> | 24 | #include <linux/err.h> |
| 25 | #include <linux/of.h> | 25 | #include <linux/of.h> |
| 26 | #include <linux/delay.h> | 26 | #include <linux/delay.h> |
| 27 | #include <linux/util_macros.h> | ||
| 27 | 28 | ||
| 28 | #include <linux/iio/iio.h> | 29 | #include <linux/iio/iio.h> |
| 29 | #include <linux/iio/sysfs.h> | 30 | #include <linux/iio/sysfs.h> |
| @@ -86,6 +87,8 @@ · 56 unmodified lines | |||
| 86 | struct vl6180_data { | 87 | struct vl6180_data { |
| 87 | struct i2c_client *client; | 88 | struct i2c_client *client; |
| 88 | struct mutex lock; | 89 | struct mutex lock; |
| 90 | unsigned int als_gain_milli; | ||
| 91 | unsigned int als_it_ms; | ||
| 89 | }; | 92 | }; |
| 90 | 93 | ||
| 91 | enum { VL6180_ALS, VL6180_RANGE, VL6180_PROX }; | 94 | enum { VL6180_ALS, VL6180_RANGE, VL6180_PROX }; |
| @@ -275,19 +278,17 @@ static const struct iio_chan_spec vl6180_channels[] = { · 183 unmodified lines | |||
| 275 | }; | 278 | }; |
| 276 | 279 | ||
| 277 | /* | 280 | /* |
| 278 | * Columns 3 & 4 represent the same value in decimal and hex notations. | 281 | * Available Ambient Light Sensor gain settings, 1/1000th, and |
| 279 | * Kept in order to avoid the datatype conversion while reading the | 282 | * corresponding setting for the VL6180_ALS_GAIN register |
| 280 | * hardware_gain. | ||
| 281 | */ | 283 | */ |
| 282 | static const int vl6180_als_gain[8][4] = { | 284 | static const int vl6180_als_gain_tab[8] = { |
| 283 | { 1, 0, 70, VL6180_ALS_GAIN_1 }, | 285 | 1000, 1250, 1670, 2500, 5000, 10000, 20000, 40000 |
| 284 | { 1, 250000, 69, VL6180_ALS_GAIN_1_25 }, | 286 | }; |
| 285 | { 1, 670000, 68, VL6180_ALS_GAIN_1_67 }, | 287 | static const u8 vl6180_als_gain_tab_bits[8] = { |
| 286 | { 2, 500000, 67, VL6180_ALS_GAIN_2_5 }, | 288 | VL6180_ALS_GAIN_1, VL6180_ALS_GAIN_1_25, |
| 287 | { 5, 0, 66, VL6180_ALS_GAIN_5 }, | 289 | VL6180_ALS_GAIN_1_67, VL6180_ALS_GAIN_2_5, |
| 288 | { 10, 0, 65, VL6180_ALS_GAIN_10 }, | 290 | VL6180_ALS_GAIN_5, VL6180_ALS_GAIN_10, |
| 289 | { 20, 0, 64, VL6180_ALS_GAIN_20 }, | 291 | VL6180_ALS_GAIN_20, VL6180_ALS_GAIN_40 |
| 290 | { 40, 0, 71, VL6180_ALS_GAIN_40 } | ||
| 291 | }; | 292 | }; |
| 292 | 293 | ||
| 293 | static int vl6180_read_raw(struct iio_dev *indio_dev, | 294 | static int vl6180_read_raw(struct iio_dev *indio_dev, |
| @@ -295,7 +296,7 @@ static int vl6180_read_raw(struct iio_dev *indio_dev, · 1 unmodified line | |||
| 295 | int *val, int *val2, long mask) | 296 | int *val, int *val2, long mask) |
| 296 | { | 297 | { |
| 297 | struct vl6180_data *data = iio_priv(indio_dev); | 298 | struct vl6180_data *data = iio_priv(indio_dev); |
| 298 | int ret, i; | 299 | int ret; |
| 299 | 300 | ||
| 300 | switch (mask) { | 301 | switch (mask) { |
| 301 | case IIO_CHAN_INFO_RAW: | 302 | case IIO_CHAN_INFO_RAW: |
| @@ -306,19 +307,20 @@ static int vl6180_read_raw(struct iio_dev *indio_dev, · 4 unmodified lines | |||
| 306 | 307 | ||
| 307 | return IIO_VAL_INT; | 308 | return IIO_VAL_INT; |
| 308 | case IIO_CHAN_INFO_INT_TIME: | 309 | case IIO_CHAN_INFO_INT_TIME: |
| 309 | ret = vl6180_read_word(data->client, VL6180_ALS_IT); | 310 | *val = data->als_it_ms; |
| 310 | if (ret < 0) | 311 | *val2 = 1000; |
| 311 | return ret; | 312 | |
| 312 | *val = 0; /* 1 count = 1ms (0 = 1ms) */ | 313 | return IIO_VAL_FRACTIONAL; |
| 313 | *val2 = (ret + 1) * 1000; /* convert to seconds */ | ||
| 314 | 314 | ||
| 315 | return IIO_VAL_INT_PLUS_MICRO; | ||
| 316 | case IIO_CHAN_INFO_SCALE: | 315 | case IIO_CHAN_INFO_SCALE: |
| 317 | switch (chan->type) { | 316 | switch (chan->type) { |
| 318 | case IIO_LIGHT: | 317 | case IIO_LIGHT: |
| 319 | *val = 0; /* one ALS count is 0.32 Lux */ | 318 | /* one ALS count is 0.32 Lux @ gain 1, IT 100 ms */ |
| 320 | *val2 = 320000; | 319 | *val = 32000; /* 0.32 * 1000 * 100 */ |
| 321 | break; | 320 | *val2 = data->als_gain_milli * data->als_it_ms; |
| 321 | |||
| 322 | return IIO_VAL_FRACTIONAL; | ||
| 323 | |||
| 322 | case IIO_DISTANCE: | 324 | case IIO_DISTANCE: |
| 323 | *val = 0; /* sensor reports mm, scale to meter */ | 325 | *val = 0; /* sensor reports mm, scale to meter */ |
| 324 | *val2 = 1000; | 326 | *val2 = 1000; |
| @@ -329,17 +331,11 @@ static int vl6180_read_raw(struct iio_dev *indio_dev, · 4 unmodified lines | |||
| 329 | 331 | ||
| 330 | return IIO_VAL_INT_PLUS_MICRO; | 332 | return IIO_VAL_INT_PLUS_MICRO; |
| 331 | case IIO_CHAN_INFO_HARDWAREGAIN: | 333 | case IIO_CHAN_INFO_HARDWAREGAIN: |
| 332 | ret = vl6180_read_byte(data->client, VL6180_ALS_GAIN); | 334 | *val = data->als_gain_milli; |
| 333 | if (ret < 0) | 335 | *val2 = 1000; |
| 334 | return -EINVAL; | 336 | |
| 335 | for (i = 0; i < ARRAY_SIZE(vl6180_als_gain); i++) { | 337 | return IIO_VAL_FRACTIONAL; |
| 336 | if (ret == vl6180_als_gain[i][2]) { | ||
| 337 | *val = vl6180_als_gain[i][0]; | ||
| 338 | *val2 = vl6180_als_gain[i][1]; | ||
| 339 | } | ||
| 340 | } | ||
| 341 | 338 | ||
| 342 | return IIO_VAL_INT_PLUS_MICRO; | ||
| 343 | default: | 339 | default: |
| 344 | return -EINVAL; | 340 | return -EINVAL; |
| 345 | } | 341 | } |
| @@ -365,37 +361,53 @@ static int vl6180_hold(struct vl6180_data *data, bool hold) · 19 unmodified lines | |||
| 365 | 361 | ||
| 366 | static int vl6180_set_als_gain(struct vl6180_data *data, int val, int val2) | 362 | static int vl6180_set_als_gain(struct vl6180_data *data, int val, int val2) |
| 367 | { | 363 | { |
| 368 | int i, ret; | 364 | int i, ret, gain; |
| 369 | |||
| 370 | for (i = 0; i < ARRAY_SIZE(vl6180_als_gain); i++) { | ||
| 371 | if (val == vl6180_als_gain[i][0] && | ||
| 372 | val2 == vl6180_als_gain[i][1]) { | ||
| 373 | mutex_lock(&data->lock); | ||
| 374 | ret = vl6180_hold(data, true); | ||
| 375 | if (ret < 0) | ||
| 376 | goto fail; | ||
| 377 | ret = vl6180_write_byte(data->client, VL6180_ALS_GAIN, | ||
| 378 | vl6180_als_gain[i][3]); | ||
| 379 | fail: | ||
| 380 | vl6180_hold(data, false); | ||
| 381 | mutex_unlock(&data->lock); | ||
| 382 | return ret; | ||
| 383 | } | ||
| 384 | } | ||
| 385 | 365 | ||
| 386 | return -EINVAL; | 366 | if (val < 1 || val > 40) |
| 367 | return -EINVAL; | ||
| 368 | |||
| 369 | gain = (val * 1000000 + val2) / 1000; | ||
| 370 | if (gain < 1 || gain > 40000) | ||
| 371 | return -EINVAL; | ||
| 372 | |||
| 373 | i = find_closest(gain, vl6180_als_gain_tab, | ||
| 374 | ARRAY_SIZE(vl6180_als_gain_tab)); | ||
| 375 | |||
| 376 | mutex_lock(&data->lock); | ||
| 377 | ret = vl6180_hold(data, true); | ||
| 378 | if (ret < 0) | ||
| 379 | goto fail; | ||
| 380 | |||
| 381 | ret = vl6180_write_byte(data->client, VL6180_ALS_GAIN, | ||
| 382 | vl6180_als_gain_tab_bits[i]); | ||
| 383 | |||
| 384 | if (ret >= 0) | ||
| 385 | data->als_gain_milli = vl6180_als_gain_tab[i]; | ||
| 386 | |||
| 387 | fail: | ||
| 388 | vl6180_hold(data, false); | ||
| 389 | mutex_unlock(&data->lock); | ||
| 390 | return ret; | ||
| 387 | } | 391 | } |
| 388 | 392 | ||
| 389 | static int vl6180_set_it(struct vl6180_data *data, int val2) | 393 | static int vl6180_set_it(struct vl6180_data *data, int val, int val2) |
| 390 | { | 394 | { |
| 391 | int ret; | 395 | int ret, it_ms; |
| 396 | |||
| 397 | it_ms = (val2 + 500) / 1000; /* round to ms */ | ||
| 398 | if (val != 0 || it_ms < 1 || it_ms > 512) | ||
| 399 | return -EINVAL; | ||
| 392 | 400 | ||
| 393 | mutex_lock(&data->lock); | 401 | mutex_lock(&data->lock); |
| 394 | ret = vl6180_hold(data, true); | 402 | ret = vl6180_hold(data, true); |
| 395 | if (ret < 0) | 403 | if (ret < 0) |
| 396 | goto fail; | 404 | goto fail; |
| 397 | ret = vl6180_write_word(data->client, VL6180_ALS_IT, | 405 | |
| 398 | (val2 - 500) / 1000); /* write value in ms */ | 406 | ret = vl6180_write_word(data->client, VL6180_ALS_IT, it_ms - 1); |
| 407 | |||
| 408 | if (ret >= 0) | ||
| 409 | data->als_it_ms = it_ms; | ||
| 410 | |||
| 399 | fail: | 411 | fail: |
| 400 | vl6180_hold(data, false); | 412 | vl6180_hold(data, false); |
| 401 | mutex_unlock(&data->lock); | 413 | mutex_unlock(&data->lock); |
| @@ -411,10 +423,8 @@ static int vl6180_write_raw(struct iio_dev *indio_dev, · 9 unmodified lines | |||
| 411 | 423 | ||
| 412 | switch (mask) { | 424 | switch (mask) { |
| 413 | case IIO_CHAN_INFO_INT_TIME: | 425 | case IIO_CHAN_INFO_INT_TIME: |
| 414 | if (val != 0 || val2 < 500 || val2 >= 512500) | 426 | return vl6180_set_it(data, val, val2); |
| 415 | return -EINVAL; | ||
| 416 | 427 | ||
| 417 | return vl6180_set_it(data, val2); | ||
| 418 | case IIO_CHAN_INFO_HARDWAREGAIN: | 428 | case IIO_CHAN_INFO_HARDWAREGAIN: |
| 419 | if (chan->type != IIO_LIGHT) | 429 | if (chan->type != IIO_LIGHT) |
| 420 | return -EINVAL; | 430 | return -EINVAL; |
| @@ -429,7 +439,6 @@ static const struct iio_info vl6180_info = { · 8 unmodified lines | |||
| 429 | .read_raw = vl6180_read_raw, | 439 | .read_raw = vl6180_read_raw, |
| 430 | .write_raw = vl6180_write_raw, | 440 | .write_raw = vl6180_write_raw, |
| 431 | .attrs = &vl6180_attribute_group, | 441 | .attrs = &vl6180_attribute_group, |
| 432 | .driver_module = THIS_MODULE, | ||
| 433 | }; | 442 | }; |
| 434 | 443 | ||
| 435 | static int vl6180_init(struct vl6180_data *data) | 444 | static int vl6180_init(struct vl6180_data *data) |
| @@ -468,11 +477,13 @@ static int vl6180_init(struct vl6180_data *data) · 32 unmodified lines | |||
| 468 | return ret; | 477 | return ret; |
| 469 | 478 | ||
| 470 | /* ALS integration time: 100ms */ | 479 | /* ALS integration time: 100ms */ |
| 480 | data->als_it_ms = 100; | ||
| 471 | ret = vl6180_write_word(client, VL6180_ALS_IT, VL6180_ALS_IT_100); | 481 | ret = vl6180_write_word(client, VL6180_ALS_IT, VL6180_ALS_IT_100); |
| 472 | if (ret < 0) | 482 | if (ret < 0) |
| 473 | return ret; | 483 | return ret; |
| 474 | 484 | ||
| 475 | /* ALS gain: 1 */ | 485 | /* ALS gain: 1 */ |
| 486 | data->als_gain_milli = 1000; | ||
| 476 | ret = vl6180_write_byte(client, VL6180_ALS_GAIN, VL6180_ALS_GAIN_1); | 487 | ret = vl6180_write_byte(client, VL6180_ALS_GAIN, VL6180_ALS_GAIN_1); |
| 477 | if (ret < 0) | 488 | if (ret < 0) |
| 478 | return ret; | 489 | return ret; |
| @@ -658,7 +658,6 @@ static const unsigned long ak8974_scan_masks[] = { 0x7, 0 }; · 657 unmodified lines | |||
| 658 | 658 | ||
| 659 | static const struct iio_info ak8974_info = { | 659 | static const struct iio_info ak8974_info = { |
| 660 | .read_raw = &ak8974_read_raw, | 660 | .read_raw = &ak8974_read_raw, |
| 661 | .driver_module = THIS_MODULE, | ||
| 662 | }; | 661 | }; |
| 663 | 662 | ||
| 664 | static bool ak8974_writeable_reg(struct device *dev, unsigned int reg) | 663 | static bool ak8974_writeable_reg(struct device *dev, unsigned int reg) |
| @@ -781,7 +781,6 @@ static const unsigned long ak8975_scan_masks[] = { 0x7, 0 }; · 780 unmodified lines | |||
| 781 | 781 | ||
| 782 | static const struct iio_info ak8975_info = { | 782 | static const struct iio_info ak8975_info = { |
| 783 | .read_raw = &ak8975_read_raw, | 783 | .read_raw = &ak8975_read_raw, |
| 784 | .driver_module = THIS_MODULE, | ||
| 785 | }; | 784 | }; |
| 786 | 785 | ||
| 787 | #ifdef CONFIG_ACPI | 786 | #ifdef CONFIG_ACPI |
| @@ -651,7 +651,6 @@ static const struct iio_info bmc150_magn_info = { · 650 unmodified lines | |||
| 651 | .attrs = &bmc150_magn_attrs_group, | 651 | .attrs = &bmc150_magn_attrs_group, |
| 652 | .read_raw = bmc150_magn_read_raw, | 652 | .read_raw = bmc150_magn_read_raw, |
| 653 | .write_raw = bmc150_magn_write_raw, | 653 | .write_raw = bmc150_magn_write_raw, |
| 654 | .driver_module = THIS_MODULE, | ||
| 655 | }; | 654 | }; |
| 656 | 655 | ||
| 657 | static const unsigned long bmc150_magn_scan_masks[] = { | 656 | static const unsigned long bmc150_magn_scan_masks[] = { |
| @@ -811,7 +810,6 @@ err_unlock: · 153 unmodified lines | |||
| 811 | static const struct iio_trigger_ops bmc150_magn_trigger_ops = { | 810 | static const struct iio_trigger_ops bmc150_magn_trigger_ops = { |
| 812 | .set_trigger_state = bmc150_magn_data_rdy_trigger_set_state, | 811 | .set_trigger_state = bmc150_magn_data_rdy_trigger_set_state, |
| 813 | .try_reenable = bmc150_magn_trig_try_reen, | 812 | .try_reenable = bmc150_magn_trig_try_reen, |
| 814 | .owner = THIS_MODULE, | ||
| 815 | }; | 813 | }; |
| 816 | 814 | ||
| 817 | static int bmc150_magn_buffer_preenable(struct iio_dev *indio_dev) | 815 | static int bmc150_magn_buffer_preenable(struct iio_dev *indio_dev) |
| @@ -282,7 +282,6 @@ static int magn_3d_write_raw(struct iio_dev *indio_dev, · 281 unmodified lines | |||
| 282 | } | 282 | } |
| 283 | 283 | ||
| 284 | static const struct iio_info magn_3d_info = { | 284 | static const struct iio_info magn_3d_info = { |
| 285 | .driver_module = THIS_MODULE, | ||
| 286 | .read_raw = &magn_3d_read_raw, | 285 | .read_raw = &magn_3d_read_raw, |
| 287 | .write_raw = &magn_3d_write_raw, | 286 | .write_raw = &magn_3d_write_raw, |
| 288 | }; | 287 | }; |
| @@ -597,7 +597,6 @@ static const struct iio_info hmc5843_info = { · 596 unmodified lines | |||
| 597 | .read_raw = &hmc5843_read_raw, | 597 | .read_raw = &hmc5843_read_raw, |
| 598 | .write_raw = &hmc5843_write_raw, | 598 | .write_raw = &hmc5843_write_raw, |
| 599 | .write_raw_get_fmt = &hmc5843_write_raw_get_fmt, | 599 | .write_raw_get_fmt = &hmc5843_write_raw_get_fmt, |
| 600 | .driver_module = THIS_MODULE, | ||
| 601 | }; | 600 | }; |
| 602 | 601 | ||
| 603 | static const unsigned long hmc5843_scan_masks[] = {0x7, 0}; | 602 | static const unsigned long hmc5843_scan_masks[] = {0x7, 0}; |
| @@ -333,7 +333,6 @@ static const struct iio_info mag3110_info = { · 332 unmodified lines | |||
| 333 | .attrs = &mag3110_group, | 333 | .attrs = &mag3110_group, |
| 334 | .read_raw = &mag3110_read_raw, | 334 | .read_raw = &mag3110_read_raw, |
| 335 | .write_raw = &mag3110_write_raw, | 335 | .write_raw = &mag3110_write_raw, |
| 336 | .driver_module = THIS_MODULE, | ||
| 337 | }; | 336 | }; |
| 338 | 337 | ||
| 339 | static const unsigned long mag3110_scan_masks[] = {0x7, 0xf, 0}; | 338 | static const unsigned long mag3110_scan_masks[] = {0x7, 0xf, 0}; |
| @@ -418,7 +418,6 @@ static int mmc35240_write_raw(struct iio_dev *indio_dev, · 417 unmodified lines | |||
| 418 | } | 418 | } |
| 419 | 419 | ||
| 420 | static const struct iio_info mmc35240_info = { | 420 | static const struct iio_info mmc35240_info = { |
| 421 | .driver_module = THIS_MODULE, | ||
| 422 | .read_raw = mmc35240_read_raw, | 421 | .read_raw = mmc35240_read_raw, |
| 423 | .write_raw = mmc35240_write_raw, | 422 | .write_raw = mmc35240_write_raw, |
| 424 | .attrs = &mmc35240_attribute_group, | 423 | .attrs = &mmc35240_attribute_group, |
| @@ -317,7 +317,14 @@ static const struct st_sensor_settings st_magn_sensors_settings[] = { · 316 unmodified lines | |||
| 317 | }, | 317 | }, |
| 318 | .drdy_irq = { | 318 | .drdy_irq = { |
| 319 | /* drdy line is routed drdy pin */ | 319 | /* drdy line is routed drdy pin */ |
| 320 | .addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR, | 320 | .stat_drdy = { |
| 321 | .addr = ST_SENSORS_DEFAULT_STAT_ADDR, | ||
| 322 | .mask = 0x07, | ||
| 323 | }, | ||
| 324 | }, | ||
| 325 | .sim = { | ||
| 326 | .addr = 0x22, | ||
| 327 | .value = BIT(2), | ||
| 321 | }, | 328 | }, |
| 322 | .multi_read_bit = true, | 329 | .multi_read_bit = true, |
| 323 | .bootime = 2, | 330 | .bootime = 2, |
| @@ -359,9 +366,14 @@ static const struct st_sensor_settings st_magn_sensors_settings[] = { · 35 unmodified lines | |||
| 359 | .mask = 0x10, | 366 | .mask = 0x10, |
| 360 | }, | 367 | }, |
| 361 | .drdy_irq = { | 368 | .drdy_irq = { |
| 362 | .addr = 0x62, | 369 | .int1 = { |
| 363 | .mask_int1 = 0x01, | 370 | .addr = 0x62, |
| 364 | .addr_stat_drdy = 0x67, | 371 | .mask = 0x01, |
| 372 | }, | ||
| 373 | .stat_drdy = { | ||
| 374 | .addr = 0x67, | ||
| 375 | .mask = 0x07, | ||
| 376 | }, | ||
| 365 | }, | 377 | }, |
| 366 | .multi_read_bit = false, | 378 | .multi_read_bit = false, |
| 367 | .bootime = 2, | 379 | .bootime = 2, |
| @@ -438,7 +450,6 @@ static const struct attribute_group st_magn_attribute_group = { · 70 unmodified lines | |||
| 438 | }; | 450 | }; |
| 439 | 451 | ||
| 440 | static const struct iio_info magn_info = { | 452 | static const struct iio_info magn_info = { |
| 441 | .driver_module = THIS_MODULE, | ||
| 442 | .attrs = &st_magn_attribute_group, | 453 | .attrs = &st_magn_attribute_group, |
| 443 | .read_raw = &st_magn_read_raw, | 454 | .read_raw = &st_magn_read_raw, |
| 444 | .write_raw = &st_magn_write_raw, | 455 | .write_raw = &st_magn_write_raw, |
| @@ -447,7 +458,6 @@ static const struct iio_info magn_info = { · 2 unmodified lines | |||
| 447 | 458 | ||
| 448 | #ifdef CONFIG_IIO_TRIGGER | 459 | #ifdef CONFIG_IIO_TRIGGER |
| 449 | static const struct iio_trigger_ops st_magn_trigger_ops = { | 460 | static const struct iio_trigger_ops st_magn_trigger_ops = { |
| 450 | .owner = THIS_MODULE, | ||
| 451 | .set_trigger_state = ST_MAGN_TRIGGER_SET_STATE, | 461 | .set_trigger_state = ST_MAGN_TRIGGER_SET_STATE, |
| 452 | .validate_device = st_sensors_validate_device, | 462 | .validate_device = st_sensors_validate_device, |
| 453 | }; | 463 | }; |
| @@ -173,7 +173,6 @@ static const struct iio_info mux_info = { · 172 unmodified lines | |||
| 173 | .read_raw = mux_read_raw, | 173 | .read_raw = mux_read_raw, |
| 174 | .read_avail = mux_read_avail, | 174 | .read_avail = mux_read_avail, |
| 175 | .write_raw = mux_write_raw, | 175 | .write_raw = mux_write_raw, |
| 176 | .driver_module = THIS_MODULE, | ||
| 177 | }; | 176 | }; |
| 178 | 177 | ||
| 179 | static ssize_t mux_read_ext_info(struct iio_dev *indio_dev, uintptr_t private, | 178 | static ssize_t mux_read_ext_info(struct iio_dev *indio_dev, uintptr_t private, |
| @@ -285,6 +284,9 @@ static int mux_configure_channel(struct device *dev, struct mux *mux, · 105 unmodified lines | |||
| 285 | child->ext_info_cache = devm_kzalloc(dev, | 284 | child->ext_info_cache = devm_kzalloc(dev, |
| 286 | sizeof(*child->ext_info_cache) * | 285 | sizeof(*child->ext_info_cache) * |
| 287 | num_ext_info, GFP_KERNEL); | 286 | num_ext_info, GFP_KERNEL); |
| 287 | if (!child->ext_info_cache) | ||
| 288 | return -ENOMEM; | ||
| 289 | |||
| 288 | for (i = 0; i < num_ext_info; ++i) { | 290 | for (i = 0; i < num_ext_info; ++i) { |
| 289 | child->ext_info_cache[i].size = -1; | 291 | child->ext_info_cache[i].size = -1; |
| 290 | 292 | ||
| @@ -309,6 +311,9 @@ static int mux_configure_channel(struct device *dev, struct mux *mux, · 18 unmodified lines | |||
| 309 | 311 | ||
| 310 | child->ext_info_cache[i].data = devm_kmemdup(dev, page, ret + 1, | 312 | child->ext_info_cache[i].data = devm_kmemdup(dev, page, ret + 1, |
| 311 | GFP_KERNEL); | 313 | GFP_KERNEL); |
| 314 | if (!child->ext_info_cache[i].data) | ||
| 315 | return -ENOMEM; | ||
| 316 | |||
| 312 | child->ext_info_cache[i].data[ret] = 0; | 317 | child->ext_info_cache[i].data[ret] = 0; |
| 313 | child->ext_info_cache[i].size = ret; | 318 | child->ext_info_cache[i].size = ret; |
| 314 | } | 319 | } |
| @@ -186,7 +186,6 @@ static int incl_3d_write_raw(struct iio_dev *indio_dev, · 185 unmodified lines | |||
| 186 | } | 186 | } |
| 187 | 187 | ||
| 188 | static const struct iio_info incl_3d_info = { | 188 | static const struct iio_info incl_3d_info = { |
| 189 | .driver_module = THIS_MODULE, | ||
| 190 | .read_raw = &incl_3d_read_raw, | 189 | .read_raw = &incl_3d_read_raw, |
| 191 | .write_raw = &incl_3d_write_raw, | 190 | .write_raw = &incl_3d_write_raw, |
| 192 | }; | 191 | }; |
| @@ -138,7 +138,6 @@ static int dev_rot_write_raw(struct iio_dev *indio_dev, · 137 unmodified lines | |||
| 138 | } | 138 | } |
| 139 | 139 | ||
| 140 | static const struct iio_info dev_rot_info = { | 140 | static const struct iio_info dev_rot_info = { |
| 141 | .driver_module = THIS_MODULE, | ||
| 142 | .read_raw_multi = &dev_rot_read_raw, | 141 | .read_raw_multi = &dev_rot_read_raw, |
| 143 | .write_raw = &dev_rot_write_raw, | 142 | .write_raw = &dev_rot_write_raw, |
| 144 | }; | 143 | }; |
| @@ -110,7 +110,6 @@ static int ds1803_write_raw(struct iio_dev *indio_dev, · 109 unmodified lines | |||
| 110 | static const struct iio_info ds1803_info = { | 110 | static const struct iio_info ds1803_info = { |
| 111 | .read_raw = ds1803_read_raw, | 111 | .read_raw = ds1803_read_raw, |
| 112 | .write_raw = ds1803_write_raw, | 112 | .write_raw = ds1803_write_raw, |
| 113 | .driver_module = THIS_MODULE, | ||
| 114 | }; | 113 | }; |
| 115 | 114 | ||
| 116 | static int ds1803_probe(struct i2c_client *client, | 115 | static int ds1803_probe(struct i2c_client *client, |
| @@ -119,7 +119,6 @@ static int max5481_write_raw(struct iio_dev *indio_dev, · 118 unmodified lines | |||
| 119 | static const struct iio_info max5481_info = { | 119 | static const struct iio_info max5481_info = { |
| 120 | .read_raw = max5481_read_raw, | 120 | .read_raw = max5481_read_raw, |
| 121 | .write_raw = max5481_write_raw, | 121 | .write_raw = max5481_write_raw, |
| 122 | .driver_module = THIS_MODULE, | ||
| 123 | }; | 122 | }; |
| 124 | 123 | ||
| 125 | #if defined(CONFIG_OF) | 124 | #if defined(CONFIG_OF) |
| @@ -207,7 +206,6 @@ MODULE_DEVICE_TABLE(acpi, max5481_acpi_match); · 81 unmodified lines | |||
| 207 | static struct spi_driver max5481_driver = { | 206 | static struct spi_driver max5481_driver = { |
| 208 | .driver = { | 207 | .driver = { |
| 209 | .name = "max5481", | 208 | .name = "max5481", |
| 210 | .owner = THIS_MODULE, | ||
| 211 | .of_match_table = of_match_ptr(max5481_match), | 209 | .of_match_table = of_match_ptr(max5481_match), |
| 212 | .acpi_match_table = ACPI_PTR(max5481_acpi_match), | 210 | .acpi_match_table = ACPI_PTR(max5481_acpi_match), |
| 213 | }, | 211 | }, |
| @@ -83,7 +83,6 @@ static int max5487_write_raw(struct iio_dev *indio_dev, · 82 unmodified lines | |||
| 83 | static const struct iio_info max5487_info = { | 83 | static const struct iio_info max5487_info = { |
| 84 | .read_raw = max5487_read_raw, | 84 | .read_raw = max5487_read_raw, |
| 85 | .write_raw = max5487_write_raw, | 85 | .write_raw = max5487_write_raw, |
| 86 | .driver_module = THIS_MODULE, | ||
| 87 | }; | 86 | }; |
| 88 | 87 | ||
| 89 | static int max5487_spi_probe(struct spi_device *spi) | 88 | static int max5487_spi_probe(struct spi_device *spi) |
| @@ -147,7 +146,6 @@ MODULE_DEVICE_TABLE(acpi, max5487_acpi_match); · 57 unmodified lines | |||
| 147 | static struct spi_driver max5487_driver = { | 146 | static struct spi_driver max5487_driver = { |
| 148 | .driver = { | 147 | .driver = { |
| 149 | .name = "max5487", | 148 | .name = "max5487", |
| 150 | .owner = THIS_MODULE, | ||
| 151 | .acpi_match_table = ACPI_PTR(max5487_acpi_match), | 149 | .acpi_match_table = ACPI_PTR(max5487_acpi_match), |
| 152 | }, | 150 | }, |
| 153 | .id_table = max5487_id, | 151 | .id_table = max5487_id, |
| @@ -237,7 +237,6 @@ static int mcp4131_write_raw(struct iio_dev *indio_dev, · 236 unmodified lines | |||
| 237 | static const struct iio_info mcp4131_info = { | 237 | static const struct iio_info mcp4131_info = { |
| 238 | .read_raw = mcp4131_read_raw, | 238 | .read_raw = mcp4131_read_raw, |
| 239 | .write_raw = mcp4131_write_raw, | 239 | .write_raw = mcp4131_write_raw, |
| 240 | .driver_module = THIS_MODULE, | ||
| 241 | }; | 240 | }; |
| 242 | 241 | ||
| 243 | static int mcp4131_probe(struct spi_device *spi) | 242 | static int mcp4131_probe(struct spi_device *spi) |
| @@ -207,7 +207,6 @@ static const struct iio_info mcp4531_info = { · 206 unmodified lines | |||
| 207 | .read_raw = mcp4531_read_raw, | 207 | .read_raw = mcp4531_read_raw, |
| 208 | .read_avail = mcp4531_read_avail, | 208 | .read_avail = mcp4531_read_avail, |
| 209 | .write_raw = mcp4531_write_raw, | 209 | .write_raw = mcp4531_write_raw, |
| 210 | .driver_module = THIS_MODULE, | ||
| 211 | }; | 210 | }; |
| 212 | 211 | ||
| 213 | #ifdef CONFIG_OF | 212 | #ifdef CONFIG_OF |
| @@ -106,7 +106,6 @@ static int tpl0102_write_raw(struct iio_dev *indio_dev, · 105 unmodified lines | |||
| 106 | static const struct iio_info tpl0102_info = { | 106 | static const struct iio_info tpl0102_info = { |
| 107 | .read_raw = tpl0102_read_raw, | 107 | .read_raw = tpl0102_read_raw, |
| 108 | .write_raw = tpl0102_write_raw, | 108 | .write_raw = tpl0102_write_raw, |
| 109 | .driver_module = THIS_MODULE, | ||
| 110 | }; | 109 | }; |
| 111 | 110 | ||
| 112 | static int tpl0102_probe(struct i2c_client *client, | 111 | static int tpl0102_probe(struct i2c_client *client, |
| @@ -207,7 +207,6 @@ static int lmp91000_read_raw(struct iio_dev *indio_dev, · 206 unmodified lines | |||
| 207 | } | 207 | } |
| 208 | 208 | ||
| 209 | static const struct iio_info lmp91000_info = { | 209 | static const struct iio_info lmp91000_info = { |
| 210 | .driver_module = THIS_MODULE, | ||
| 211 | .read_raw = lmp91000_read_raw, | 210 | .read_raw = lmp91000_read_raw, |
| 212 | }; | 211 | }; |
| 213 | 212 | ||
| @@ -283,7 +282,6 @@ static int lmp91000_buffer_cb(const void *val, void *private) · 69 unmodified lines | |||
| 283 | } | 282 | } |
| 284 | 283 | ||
| 285 | static const struct iio_trigger_ops lmp91000_trigger_ops = { | 284 | static const struct iio_trigger_ops lmp91000_trigger_ops = { |
| 286 | .owner = THIS_MODULE, | ||
| 287 | }; | 285 | }; |
| 288 | 286 | ||
| 289 | 287 | ||
| @@ -168,7 +168,6 @@ static int abp060mg_read_raw(struct iio_dev *indio_dev, · 167 unmodified lines | |||
| 168 | } | 168 | } |
| 169 | 169 | ||
| 170 | static const struct iio_info abp060mg_info = { | 170 | static const struct iio_info abp060mg_info = { |
| 171 | .driver_module = THIS_MODULE, | ||
| 172 | .read_raw = abp060mg_read_raw, | 171 | .read_raw = abp060mg_read_raw, |
| 173 | }; | 172 | }; |
| 174 | 173 | ||
| @@ -561,7 +561,6 @@ static const struct attribute_group bmp280_attrs_group = { · 560 unmodified lines | |||
| 561 | }; | 561 | }; |
| 562 | 562 | ||
| 563 | static const struct iio_info bmp280_info = { | 563 | static const struct iio_info bmp280_info = { |
| 564 | .driver_module = THIS_MODULE, | ||
| 565 | .read_raw = &bmp280_read_raw, | 564 | .read_raw = &bmp280_read_raw, |
| 566 | .write_raw = &bmp280_write_raw, | 565 | .write_raw = &bmp280_write_raw, |
| 567 | .attrs = &bmp280_attrs_group, | 566 | .attrs = &bmp280_attrs_group, |
| @@ -120,14 +120,12 @@ static int cros_ec_baro_write(struct iio_dev *indio_dev, · 119 unmodified lines | |||
| 120 | static const struct iio_info cros_ec_baro_info = { | 120 | static const struct iio_info cros_ec_baro_info = { |
| 121 | .read_raw = &cros_ec_baro_read, | 121 | .read_raw = &cros_ec_baro_read, |
| 122 | .write_raw = &cros_ec_baro_write, | 122 | .write_raw = &cros_ec_baro_write, |
| 123 | .driver_module = THIS_MODULE, | ||
| 124 | }; | 123 | }; |
| 125 | 124 | ||
| 126 | static int cros_ec_baro_probe(struct platform_device *pdev) | 125 | static int cros_ec_baro_probe(struct platform_device *pdev) |
| 127 | { | 126 | { |
| 128 | struct device *dev = &pdev->dev; | 127 | struct device *dev = &pdev->dev; |
| 129 | struct cros_ec_dev *ec_dev = dev_get_drvdata(dev->parent); | 128 | struct cros_ec_dev *ec_dev = dev_get_drvdata(dev->parent); |
| 130 | struct cros_ec_device *ec_device; | ||
| 131 | struct iio_dev *indio_dev; | 129 | struct iio_dev *indio_dev; |
| 132 | struct cros_ec_baro_state *state; | 130 | struct cros_ec_baro_state *state; |
| 133 | struct iio_chan_spec *channel; | 131 | struct iio_chan_spec *channel; |
| @@ -137,7 +135,6 @@ static int cros_ec_baro_probe(struct platform_device *pdev) · 3 unmodified lines | |||
| 137 | dev_warn(dev, "No CROS EC device found.\n"); | 135 | dev_warn(dev, "No CROS EC device found.\n"); |
| 138 | return -EINVAL; | 136 | return -EINVAL; |
| 139 | } | 137 | } |
| 140 | ec_device = ec_dev->ec_dev; | ||
| 141 | 138 | ||
| 142 | indio_dev = devm_iio_device_alloc(dev, sizeof(*state)); | 139 | indio_dev = devm_iio_device_alloc(dev, sizeof(*state)); |
| 143 | if (!indio_dev) | 140 | if (!indio_dev) |
| @@ -160,7 +160,6 @@ static int press_write_raw(struct iio_dev *indio_dev, · 159 unmodified lines | |||
| 160 | } | 160 | } |
| 161 | 161 | ||
| 162 | static const struct iio_info press_info = { | 162 | static const struct iio_info press_info = { |
| 163 | .driver_module = THIS_MODULE, | ||
| 164 | .read_raw = &press_read_raw, | 163 | .read_raw = &press_read_raw, |
| 165 | .write_raw = &press_write_raw, | 164 | .write_raw = &press_write_raw, |
| 166 | }; | 165 | }; |
| @@ -208,7 +208,6 @@ static int hp03_read_raw(struct iio_dev *indio_dev, · 207 unmodified lines | |||
| 208 | } | 208 | } |
| 209 | 209 | ||
| 210 | static const struct iio_info hp03_info = { | 210 | static const struct iio_info hp03_info = { |
| 211 | .driver_module = THIS_MODULE, | ||
| 212 | .read_raw = &hp03_read_raw, | 211 | .read_raw = &hp03_read_raw, |
| 213 | }; | 212 | }; |
| 214 | 213 | ||
| @@ -351,7 +351,6 @@ static const struct iio_info hp206c_info = { · 350 unmodified lines | |||
| 351 | .attrs = &hp206c_attribute_group, | 351 | .attrs = &hp206c_attribute_group, |
| 352 | .read_raw = hp206c_read_raw, | 352 | .read_raw = hp206c_read_raw, |
| 353 | .write_raw = hp206c_write_raw, | 353 | .write_raw = hp206c_write_raw, |
| 354 | .driver_module = THIS_MODULE, | ||
| 355 | }; | 354 | }; |
| 356 | 355 | ||
| 357 | static int hp206c_probe(struct i2c_client *client, | 356 | static int hp206c_probe(struct i2c_client *client, |
| @@ -144,7 +144,6 @@ static const struct iio_chan_spec mpl115_channels[] = { · 143 unmodified lines | |||
| 144 | 144 | ||
| 145 | static const struct iio_info mpl115_info = { | 145 | static const struct iio_info mpl115_info = { |
| 146 | .read_raw = &mpl115_read_raw, | 146 | .read_raw = &mpl115_read_raw, |
| 147 | .driver_module = THIS_MODULE, | ||
| 148 | }; | 147 | }; |
| 149 | 148 | ||
| 150 | int mpl115_probe(struct device *dev, const char *name, | 149 | int mpl115_probe(struct device *dev, const char *name, |
| @@ -218,7 +218,6 @@ static const struct iio_chan_spec mpl3115_channels[] = { · 217 unmodified lines | |||
| 218 | 218 | ||
| 219 | static const struct iio_info mpl3115_info = { | 219 | static const struct iio_info mpl3115_info = { |
| 220 | .read_raw = &mpl3115_read_raw, | 220 | .read_raw = &mpl3115_read_raw, |
| 221 | .driver_module = THIS_MODULE, | ||
| 222 | }; | 221 | }; |
| 223 | 222 | ||
| 224 | static int mpl3115_probe(struct i2c_client *client, | 223 | static int mpl3115_probe(struct i2c_client *client, |
| @@ -384,7 +384,6 @@ static const struct iio_info ms5611_info = { · 383 unmodified lines | |||
| 384 | .read_raw = &ms5611_read_raw, | 384 | .read_raw = &ms5611_read_raw, |
| 385 | .write_raw = &ms5611_write_raw, | 385 | .write_raw = &ms5611_write_raw, |
| 386 | .attrs = &ms5611_attribute_group, | 386 | .attrs = &ms5611_attribute_group, |
| 387 | .driver_module = THIS_MODULE, | ||
| 388 | }; | 387 | }; |
| 389 | 388 | ||
| 390 | static int ms5611_init(struct iio_dev *indio_dev) | 389 | static int ms5611_init(struct iio_dev *indio_dev) |
| @@ -124,7 +124,6 @@ static const struct iio_info ms5637_info = { · 123 unmodified lines | |||
| 124 | .read_raw = ms5637_read_raw, | 124 | .read_raw = ms5637_read_raw, |
| 125 | .write_raw = ms5637_write_raw, | 125 | .write_raw = ms5637_write_raw, |
| 126 | .attrs = &ms5637_attribute_group, | 126 | .attrs = &ms5637_attribute_group, |
| 127 | .driver_module = THIS_MODULE, | ||
| 128 | }; | 127 | }; |
| 129 | 128 | ||
| 130 | static int ms5637_probe(struct i2c_client *client, | 129 | static int ms5637_probe(struct i2c_client *client, |
| @@ -19,6 +19,8 @@ enum st_press_type { · 18 unmodified lines | |||
| 19 | LPS25H, | 19 | LPS25H, |
| 20 | LPS331AP, | 20 | LPS331AP, |
| 21 | LPS22HB, | 21 | LPS22HB, |
| 22 | LPS33HW, | ||
| 23 | LPS35HW, | ||
| 22 | ST_PRESS_MAX, | 24 | ST_PRESS_MAX, |
| 23 | }; | 25 | }; |
| 24 | 26 | ||
| @@ -26,6 +28,8 @@ enum st_press_type { · 1 unmodified line | |||
| 26 | #define LPS25H_PRESS_DEV_NAME "lps25h" | 28 | #define LPS25H_PRESS_DEV_NAME "lps25h" |
| 27 | #define LPS331AP_PRESS_DEV_NAME "lps331ap" | 29 | #define LPS331AP_PRESS_DEV_NAME "lps331ap" |
| 28 | #define LPS22HB_PRESS_DEV_NAME "lps22hb" | 30 | #define LPS22HB_PRESS_DEV_NAME "lps22hb" |
| 31 | #define LPS33HW_PRESS_DEV_NAME "lps33hw" | ||
| 32 | #define LPS35HW_PRESS_DEV_NAME "lps35hw" | ||
| 29 | 33 | ||
| 30 | /** | 34 | /** |
| 31 | * struct st_sensors_platform_data - default press platform data | 35 | * struct st_sensors_platform_data - default press platform data |
| @@ -280,14 +280,28 @@ static const struct st_sensor_settings st_press_sensors_settings[] = { · 279 unmodified lines | |||
| 280 | .mask = 0x04, | 280 | .mask = 0x04, |
| 281 | }, | 281 | }, |
| 282 | .drdy_irq = { | 282 | .drdy_irq = { |
| 283 | .addr = 0x22, | 283 | .int1 = { |
| 284 | .mask_int1 = 0x04, | 284 | .addr = 0x22, |
| 285 | .mask_int2 = 0x20, | 285 | .mask = 0x04, |
| 286 | .addr_od = 0x22, | ||
| 287 | .mask_od = 0x40, | ||
| 288 | }, | ||
| 289 | .int2 = { | ||
| 290 | .addr = 0x22, | ||
| 291 | .mask = 0x20, | ||
| 292 | .addr_od = 0x22, | ||
| 293 | .mask_od = 0x40, | ||
| 294 | }, | ||
| 286 | .addr_ihl = 0x22, | 295 | .addr_ihl = 0x22, |
| 287 | .mask_ihl = 0x80, | 296 | .mask_ihl = 0x80, |
| 288 | .addr_od = 0x22, | 297 | .stat_drdy = { |
| 289 | .mask_od = 0x40, | 298 | .addr = ST_SENSORS_DEFAULT_STAT_ADDR, |
| 290 | .addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR, | 299 | .mask = 0x03, |
| 300 | }, | ||
| 301 | }, | ||
| 302 | .sim = { | ||
| 303 | .addr = 0x20, | ||
| 304 | .value = BIT(0), | ||
| 291 | }, | 305 | }, |
| 292 | .multi_read_bit = true, | 306 | .multi_read_bit = true, |
| 293 | .bootime = 2, | 307 | .bootime = 2, |
| @@ -335,8 +349,9 @@ static const struct st_sensor_settings st_press_sensors_settings[] = { · 41 unmodified lines | |||
| 335 | .addr = 0x20, | 349 | .addr = 0x20, |
| 336 | .mask = 0x04, | 350 | .mask = 0x04, |
| 337 | }, | 351 | }, |
| 338 | .drdy_irq = { | 352 | .sim = { |
| 339 | .addr = 0, | 353 | .addr = 0x20, |
| 354 | .value = BIT(0), | ||
| 340 | }, | 355 | }, |
| 341 | .multi_read_bit = true, | 356 | .multi_read_bit = true, |
| 342 | .bootime = 2, | 357 | .bootime = 2, |
| @@ -388,14 +403,22 @@ static const struct st_sensor_settings st_press_sensors_settings[] = { · 45 unmodified lines | |||
| 388 | .mask = 0x04, | 403 | .mask = 0x04, |
| 389 | }, | 404 | }, |
| 390 | .drdy_irq = { | 405 | .drdy_irq = { |
| 391 | .addr = 0x23, | 406 | .int1 = { |
| 392 | .mask_int1 = 0x01, | 407 | .addr = 0x23, |
| 393 | .mask_int2 = 0x00, | 408 | .mask = 0x01, |
| 409 | .addr_od = 0x22, | ||
| 410 | .mask_od = 0x40, | ||
| 411 | }, | ||
| 394 | .addr_ihl = 0x22, | 412 | .addr_ihl = 0x22, |
| 395 | .mask_ihl = 0x80, | 413 | .mask_ihl = 0x80, |
| 396 | .addr_od = 0x22, | 414 | .stat_drdy = { |
| 397 | .mask_od = 0x40, | 415 | .addr = ST_SENSORS_DEFAULT_STAT_ADDR, |
| 398 | .addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR, | 416 | .mask = 0x03, |
| 417 | }, | ||
| 418 | }, | ||
| 419 | .sim = { | ||
| 420 | .addr = 0x20, | ||
| 421 | .value = BIT(0), | ||
| 399 | }, | 422 | }, |
| 400 | .multi_read_bit = true, | 423 | .multi_read_bit = true, |
| 401 | .bootime = 2, | 424 | .bootime = 2, |
| @@ -410,6 +433,8 @@ static const struct st_sensor_settings st_press_sensors_settings[] = { · 8 unmodified lines | |||
| 410 | .wai_addr = ST_SENSORS_DEFAULT_WAI_ADDRESS, | 433 | .wai_addr = ST_SENSORS_DEFAULT_WAI_ADDRESS, |
| 411 | .sensors_supported = { | 434 | .sensors_supported = { |
| 412 | [0] = LPS22HB_PRESS_DEV_NAME, | 435 | [0] = LPS22HB_PRESS_DEV_NAME, |
| 436 | [1] = LPS33HW_PRESS_DEV_NAME, | ||
| 437 | [2] = LPS35HW_PRESS_DEV_NAME, | ||
| 413 | }, | 438 | }, |
| 414 | .ch = (struct iio_chan_spec *)st_press_lps22hb_channels, | 439 | .ch = (struct iio_chan_spec *)st_press_lps22hb_channels, |
| 415 | .num_ch = ARRAY_SIZE(st_press_lps22hb_channels), | 440 | .num_ch = ARRAY_SIZE(st_press_lps22hb_channels), |
| @@ -447,14 +472,22 @@ static const struct st_sensor_settings st_press_sensors_settings[] = { · 31 unmodified lines | |||
| 447 | .mask = 0x02, | 472 | .mask = 0x02, |
| 448 | }, | 473 | }, |
| 449 | .drdy_irq = { | 474 | .drdy_irq = { |
| 450 | .addr = 0x12, | 475 | .int1 = { |
| 451 | .mask_int1 = 0x04, | 476 | .addr = 0x12, |
| 452 | .mask_int2 = 0x00, | 477 | .mask = 0x04, |
| 478 | .addr_od = 0x12, | ||
| 479 | .mask_od = 0x40, | ||
| 480 | }, | ||
| 453 | .addr_ihl = 0x12, | 481 | .addr_ihl = 0x12, |
| 454 | .mask_ihl = 0x80, | 482 | .mask_ihl = 0x80, |
| 455 | .addr_od = 0x12, | 483 | .stat_drdy = { |
| 456 | .mask_od = 0x40, | 484 | .addr = ST_SENSORS_DEFAULT_STAT_ADDR, |
| 457 | .addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR, | 485 | .mask = 0x03, |
| 486 | }, | ||
| 487 | }, | ||
| 488 | .sim = { | ||
| 489 | .addr = 0x10, | ||
| 490 | .value = BIT(0), | ||
| 458 | }, | 491 | }, |
| 459 | .multi_read_bit = false, | 492 | .multi_read_bit = false, |
| 460 | .bootime = 2, | 493 | .bootime = 2, |
| @@ -547,7 +580,6 @@ static const struct attribute_group st_press_attribute_group = { · 86 unmodified lines | |||
| 547 | }; | 580 | }; |
| 548 | 581 | ||
| 549 | static const struct iio_info press_info = { | 582 | static const struct iio_info press_info = { |
| 550 | .driver_module = THIS_MODULE, | ||
| 551 | .attrs = &st_press_attribute_group, | 583 | .attrs = &st_press_attribute_group, |
| 552 | .read_raw = &st_press_read_raw, | 584 | .read_raw = &st_press_read_raw, |
| 553 | .write_raw = &st_press_write_raw, | 585 | .write_raw = &st_press_write_raw, |
| @@ -556,7 +588,6 @@ static const struct iio_info press_info = { · 2 unmodified lines | |||
| 556 | 588 | ||
| 557 | #ifdef CONFIG_IIO_TRIGGER | 589 | #ifdef CONFIG_IIO_TRIGGER |
| 558 | static const struct iio_trigger_ops st_press_trigger_ops = { | 590 | static const struct iio_trigger_ops st_press_trigger_ops = { |
| 559 | .owner = THIS_MODULE, | ||
| 560 | .set_trigger_state = ST_PRESS_TRIGGER_SET_STATE, | 591 | .set_trigger_state = ST_PRESS_TRIGGER_SET_STATE, |
| 561 | .validate_device = st_sensors_validate_device, | 592 | .validate_device = st_sensors_validate_device, |
| 562 | }; | 593 | }; |
| @@ -605,7 +636,8 @@ int st_press_common_probe(struct iio_dev *indio_dev) · 42 unmodified lines | |||
| 605 | press_data->odr = press_data->sensor_settings->odr.odr_avl[0].hz; | 636 | press_data->odr = press_data->sensor_settings->odr.odr_avl[0].hz; |
| 606 | 637 | ||
| 607 | /* Some devices don't support a data ready pin. */ | 638 | /* Some devices don't support a data ready pin. */ |
| 608 | if (!pdata && press_data->sensor_settings->drdy_irq.addr) | 639 | if (!pdata && (press_data->sensor_settings->drdy_irq.int1.addr || |
| 640 | press_data->sensor_settings->drdy_irq.int2.addr)) | ||
| 609 | pdata = (struct st_sensors_platform_data *)&default_press_pdata; | 641 | pdata = (struct st_sensors_platform_data *)&default_press_pdata; |
| 610 | 642 | ||
| 611 | err = st_sensors_init_sensor(indio_dev, press_data->dev->platform_data); | 643 | err = st_sensors_init_sensor(indio_dev, press_data->dev->platform_data); |
| @@ -37,6 +37,14 @@ static const struct of_device_id st_press_of_match[] = { · 36 unmodified lines | |||
| 37 | .compatible = "st,lps22hb-press", | 37 | .compatible = "st,lps22hb-press", |
| 38 | .data = LPS22HB_PRESS_DEV_NAME, | 38 | .data = LPS22HB_PRESS_DEV_NAME, |
| 39 | }, | 39 | }, |
| 40 | { | ||
| 41 | .compatible = "st,lps33hw", | ||
| 42 | .data = LPS33HW_PRESS_DEV_NAME, | ||
| 43 | }, | ||
| 44 | { | ||
| 45 | .compatible = "st,lps35hw", | ||
| 46 | .data = LPS35HW_PRESS_DEV_NAME, | ||
| 47 | }, | ||
| 40 | {}, | 48 | {}, |
| 41 | }; | 49 | }; |
| 42 | MODULE_DEVICE_TABLE(of, st_press_of_match); | 50 | MODULE_DEVICE_TABLE(of, st_press_of_match); |
| @@ -59,6 +67,8 @@ static const struct i2c_device_id st_press_id_table[] = { · 16 unmodified lines | |||
| 59 | { LPS25H_PRESS_DEV_NAME, LPS25H }, | 67 | { LPS25H_PRESS_DEV_NAME, LPS25H }, |
| 60 | { LPS331AP_PRESS_DEV_NAME, LPS331AP }, | 68 | { LPS331AP_PRESS_DEV_NAME, LPS331AP }, |
| 61 | { LPS22HB_PRESS_DEV_NAME, LPS22HB }, | 69 | { LPS22HB_PRESS_DEV_NAME, LPS22HB }, |
| 70 | { LPS33HW_PRESS_DEV_NAME, LPS33HW }, | ||
| 71 | { LPS35HW_PRESS_DEV_NAME, LPS35HW }, | ||
| 62 | {}, | 72 | {}, |
| 63 | }; | 73 | }; |
| 64 | MODULE_DEVICE_TABLE(i2c, st_press_id_table); | 74 | MODULE_DEVICE_TABLE(i2c, st_press_id_table); |
| @@ -41,6 +41,14 @@ static const struct of_device_id st_press_of_match[] = { · 40 unmodified lines | |||
| 41 | .compatible = "st,lps22hb-press", | 41 | .compatible = "st,lps22hb-press", |
| 42 | .data = LPS22HB_PRESS_DEV_NAME, | 42 | .data = LPS22HB_PRESS_DEV_NAME, |
| 43 | }, | 43 | }, |
| 44 | { | ||
| 45 | .compatible = "st,lps33hw", | ||
| 46 | .data = LPS33HW_PRESS_DEV_NAME, | ||
| 47 | }, | ||
| 48 | { | ||
| 49 | .compatible = "st,lps35hw", | ||
| 50 | .data = LPS35HW_PRESS_DEV_NAME, | ||
| 51 | }, | ||
| 44 | {}, | 52 | {}, |
| 45 | }; | 53 | }; |
| 46 | MODULE_DEVICE_TABLE(of, st_press_of_match); | 54 | MODULE_DEVICE_TABLE(of, st_press_of_match); |
| @@ -83,6 +91,8 @@ static const struct spi_device_id st_press_id_table[] = { · 36 unmodified lines | |||
| 83 | { LPS25H_PRESS_DEV_NAME }, | 91 | { LPS25H_PRESS_DEV_NAME }, |
| 84 | { LPS331AP_PRESS_DEV_NAME }, | 92 | { LPS331AP_PRESS_DEV_NAME }, |
| 85 | { LPS22HB_PRESS_DEV_NAME }, | 93 | { LPS22HB_PRESS_DEV_NAME }, |
| 94 | { LPS33HW_PRESS_DEV_NAME }, | ||
| 95 | { LPS35HW_PRESS_DEV_NAME }, | ||
| 86 | {}, | 96 | {}, |
| 87 | }; | 97 | }; |
| 88 | MODULE_DEVICE_TABLE(spi, st_press_id_table); | 98 | MODULE_DEVICE_TABLE(spi, st_press_id_table); |
| @@ -209,7 +209,6 @@ static const struct iio_info t5403_info = { · 208 unmodified lines | |||
| 209 | .read_raw = &t5403_read_raw, | 209 | .read_raw = &t5403_read_raw, |
| 210 | .write_raw = &t5403_write_raw, | 210 | .write_raw = &t5403_write_raw, |
| 211 | .attrs = &t5403_attribute_group, | 211 | .attrs = &t5403_attribute_group, |
| 212 | .driver_module = THIS_MODULE, | ||
| 213 | }; | 212 | }; |
| 214 | 213 | ||
| 215 | static int t5403_probe(struct i2c_client *client, | 214 | static int t5403_probe(struct i2c_client *client, |
| @@ -1390,7 +1390,6 @@ static int zpa2326_set_trigger_state(struct iio_trigger *trig, bool state) · 1389 unmodified lines | |||
| 1390 | } | 1390 | } |
| 1391 | 1391 | ||
| 1392 | static const struct iio_trigger_ops zpa2326_trigger_ops = { | 1392 | static const struct iio_trigger_ops zpa2326_trigger_ops = { |
| 1393 | .owner = THIS_MODULE, | ||
| 1394 | .set_trigger_state = zpa2326_set_trigger_state, | 1393 | .set_trigger_state = zpa2326_set_trigger_state, |
| 1395 | }; | 1394 | }; |
| 1396 | 1395 | ||
| @@ -1590,7 +1589,6 @@ static const struct iio_chan_spec zpa2326_channels[] = { · 193 unmodified lines | |||
| 1590 | }; | 1589 | }; |
| 1591 | 1590 | ||
| 1592 | static const struct iio_info zpa2326_info = { | 1591 | static const struct iio_info zpa2326_info = { |
| 1593 | .driver_module = THIS_MODULE, | ||
| 1594 | .attrs = &zpa2326_attribute_group, | 1592 | .attrs = &zpa2326_attribute_group, |
| 1595 | .read_raw = zpa2326_read_raw, | 1593 | .read_raw = zpa2326_read_raw, |
| 1596 | .write_raw = zpa2326_write_raw, | 1594 | .write_raw = zpa2326_write_raw, |
| @@ -32,6 +32,16 @@ config LIDAR_LITE_V2 · 31 unmodified lines | |||
| 32 | To compile this driver as a module, choose M here: the | 32 | To compile this driver as a module, choose M here: the |
| 33 | module will be called pulsedlight-lite-v2 | 33 | module will be called pulsedlight-lite-v2 |
| 34 | 34 | ||
| 35 | config RFD77402 | ||
| 36 | tristate "RFD77402 ToF sensor" | ||
| 37 | depends on I2C | ||
| 38 | help | ||
| 39 | Say Y to build a driver for the RFD77420 Time-of-Flight (distance) | ||
| 40 | sensor module with I2C interface. | ||
| 41 | |||
| 42 | To compile this driver as a module, choose M here: the | ||
| 43 | module will be called rfd77402. | ||
| 44 | |||
| 35 | config SRF04 | 45 | config SRF04 |
| 36 | tristate "Devantech SRF04 ultrasonic ranger sensor" | 46 | tristate "Devantech SRF04 ultrasonic ranger sensor" |
| 37 | depends on GPIOLIB | 47 | depends on GPIOLIB |
| @@ -6,6 +6,7 @@ · 5 unmodified lines | |||
| 6 | # When adding new entries keep the list in alphabetical order | 6 | # When adding new entries keep the list in alphabetical order |
| 7 | obj-$(CONFIG_AS3935) += as3935.o | 7 | obj-$(CONFIG_AS3935) += as3935.o |
| 8 | obj-$(CONFIG_LIDAR_LITE_V2) += pulsedlight-lidar-lite-v2.o | 8 | obj-$(CONFIG_LIDAR_LITE_V2) += pulsedlight-lidar-lite-v2.o |
| 9 | obj-$(CONFIG_RFD77402) += rfd77402.o | ||
| 9 | obj-$(CONFIG_SRF04) += srf04.o | 10 | obj-$(CONFIG_SRF04) += srf04.o |
| 10 | obj-$(CONFIG_SRF08) += srf08.o | 11 | obj-$(CONFIG_SRF08) += srf08.o |
| 11 | obj-$(CONFIG_SX9500) += sx9500.o | 12 | obj-$(CONFIG_SX9500) += sx9500.o |
| @@ -221,7 +221,6 @@ static int as3935_read_raw(struct iio_dev *indio_dev, · 220 unmodified lines | |||
| 221 | } | 221 | } |
| 222 | 222 | ||
| 223 | static const struct iio_info as3935_info = { | 223 | static const struct iio_info as3935_info = { |
| 224 | .driver_module = THIS_MODULE, | ||
| 225 | .attrs = &as3935_attribute_group, | 224 | .attrs = &as3935_attribute_group, |
| 226 | .read_raw = &as3935_read_raw, | 225 | .read_raw = &as3935_read_raw, |
| 227 | }; | 226 | }; |
| @@ -247,7 +246,6 @@ err_read: · 19 unmodified lines | |||
| 247 | } | 246 | } |
| 248 | 247 | ||
| 249 | static const struct iio_trigger_ops iio_interrupt_trigger_ops = { | 248 | static const struct iio_trigger_ops iio_interrupt_trigger_ops = { |
| 250 | .owner = THIS_MODULE, | ||
| 251 | }; | 249 | }; |
| 252 | 250 | ||
| 253 | static void as3935_event_work(struct work_struct *work) | 251 | static void as3935_event_work(struct work_struct *work) |
| @@ -249,7 +249,6 @@ static irqreturn_t lidar_trigger_handler(int irq, void *private) · 248 unmodified lines | |||
| 249 | } | 249 | } |
| 250 | 250 | ||
| 251 | static const struct iio_info lidar_info = { | 251 | static const struct iio_info lidar_info = { |
| 252 | .driver_module = THIS_MODULE, | ||
| 253 | .read_raw = lidar_read_raw, | 252 | .read_raw = lidar_read_raw, |
| 254 | }; | 253 | }; |
| 255 | 254 | ||
| @@ -0,0 +1,352 @@ | |||
| 1 | /* | ||
| 2 | * rfd77402.c - Support for RF Digital RFD77402 Time-of-Flight (distance) sensor | ||
| 3 | * | ||
| 4 | * Copyright 2017 Peter Meerwald-Stadler <pmeerw@pmeerw.net> | ||
| 5 | * | ||
| 6 | * This file is subject to the terms and conditions of version 2 of | ||
| 7 | * the GNU General Public License. See the file COPYING in the main | ||
| 8 | * directory of this archive for more details. | ||
| 9 | * | ||
| 10 | * 7-bit I2C slave address 0x4c | ||
| 11 | * | ||
| 12 | * TODO: interrupt | ||
| 13 | * https://media.digikey.com/pdf/Data%20Sheets/RF%20Digital%20PDFs/RFD77402.pdf | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/module.h> | ||
| 17 | #include <linux/i2c.h> | ||
| 18 | #include <linux/delay.h> | ||
| 19 | |||
| 20 | #include <linux/iio/iio.h> | ||
| 21 | |||
| 22 | #define RFD77402_DRV_NAME "rfd77402" | ||
| 23 | |||
| 24 | #define RFD77402_ICSR 0x00 /* Interrupt Control Status Register */ | ||
| 25 | #define RFD77402_ICSR_INT_MODE BIT(2) | ||
| 26 | #define RFD77402_ICSR_INT_POL BIT(3) | ||
| 27 | #define RFD77402_ICSR_RESULT BIT(4) | ||
| 28 | #define RFD77402_ICSR_M2H_MSG BIT(5) | ||
| 29 | #define RFD77402_ICSR_H2M_MSG BIT(6) | ||
| 30 | #define RFD77402_ICSR_RESET BIT(7) | ||
| 31 | |||
| 32 | #define RFD77402_CMD_R 0x04 | ||
| 33 | #define RFD77402_CMD_SINGLE 0x01 | ||
| 34 | #define RFD77402_CMD_STANDBY 0x10 | ||
| 35 | #define RFD77402_CMD_MCPU_OFF 0x11 | ||
| 36 | #define RFD77402_CMD_MCPU_ON 0x12 | ||
| 37 | #define RFD77402_CMD_RESET BIT(6) | ||
| 38 | #define RFD77402_CMD_VALID BIT(7) | ||
| 39 | |||
| 40 | #define RFD77402_STATUS_R 0x06 | ||
| 41 | #define RFD77402_STATUS_PM_MASK GENMASK(4, 0) | ||
| 42 | #define RFD77402_STATUS_STANDBY 0x00 | ||
| 43 | #define RFD77402_STATUS_MCPU_OFF 0x10 | ||
| 44 | #define RFD77402_STATUS_MCPU_ON 0x18 | ||
| 45 | |||
| 46 | #define RFD77402_RESULT_R 0x08 | ||
| 47 | #define RFD77402_RESULT_DIST_MASK GENMASK(12, 2) | ||
| 48 | #define RFD77402_RESULT_ERR_MASK GENMASK(14, 13) | ||
| 49 | #define RFD77402_RESULT_VALID BIT(15) | ||
| 50 | |||
| 51 | #define RFD77402_PMU_CFG 0x14 | ||
| 52 | #define RFD77402_PMU_MCPU_INIT BIT(9) | ||
| 53 | |||
| 54 | #define RFD77402_I2C_INIT_CFG 0x1c | ||
| 55 | #define RFD77402_I2C_ADDR_INCR BIT(0) | ||
| 56 | #define RFD77402_I2C_DATA_INCR BIT(2) | ||
| 57 | #define RFD77402_I2C_HOST_DEBUG BIT(5) | ||
| 58 | #define RFD77402_I2C_MCPU_DEBUG BIT(6) | ||
| 59 | |||
| 60 | #define RFD77402_CMD_CFGR_A 0x0c | ||
| 61 | #define RFD77402_CMD_CFGR_B 0x0e | ||
| 62 | #define RFD77402_HFCFG_0 0x20 | ||
| 63 | #define RFD77402_HFCFG_1 0x22 | ||
| 64 | #define RFD77402_HFCFG_2 0x24 | ||
| 65 | #define RFD77402_HFCFG_3 0x26 | ||
| 66 | |||
| 67 | #define RFD77402_MOD_CHIP_ID 0x28 | ||
| 68 | |||
| 69 | /* magic configuration values from datasheet */ | ||
| 70 | static const struct { | ||
| 71 | u8 reg; | ||
| 72 | u16 val; | ||
| 73 | } rf77402_tof_config[] = { | ||
| 74 | {RFD77402_CMD_CFGR_A, 0xe100}, | ||
| 75 | {RFD77402_CMD_CFGR_B, 0x10ff}, | ||
| 76 | {RFD77402_HFCFG_0, 0x07d0}, | ||
| 77 | {RFD77402_HFCFG_1, 0x5008}, | ||
| 78 | {RFD77402_HFCFG_2, 0xa041}, | ||
| 79 | {RFD77402_HFCFG_3, 0x45d4}, | ||
| 80 | }; | ||
| 81 | |||
| 82 | struct rfd77402_data { | ||
| 83 | struct i2c_client *client; | ||
| 84 | /* Serialize reads from the sensor */ | ||
| 85 | struct mutex lock; | ||
| 86 | }; | ||
| 87 | |||
| 88 | static const struct iio_chan_spec rfd77402_channels[] = { | ||
| 89 | { | ||
| 90 | .type = IIO_DISTANCE, | ||
| 91 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | | ||
| 92 | BIT(IIO_CHAN_INFO_SCALE), | ||
| 93 | }, | ||
| 94 | }; | ||
| 95 | |||
| 96 | static int rfd77402_set_state(struct rfd77402_data *data, u8 state, u16 check) | ||
| 97 | { | ||
| 98 | int ret; | ||
| 99 | |||
| 100 | ret = i2c_smbus_write_byte_data(data->client, RFD77402_CMD_R, | ||
| 101 | state | RFD77402_CMD_VALID); | ||
| 102 | if (ret < 0) | ||
| 103 | return ret; | ||
| 104 | |||
| 105 | usleep_range(10000, 20000); | ||
| 106 | |||
| 107 | ret = i2c_smbus_read_word_data(data->client, RFD77402_STATUS_R); | ||
| 108 | if (ret < 0) | ||
| 109 | return ret; | ||
| 110 | if ((ret & RFD77402_STATUS_PM_MASK) != check) | ||
| 111 | return -ENODEV; | ||
| 112 | |||
| 113 | return 0; | ||
| 114 | } | ||
| 115 | |||
| 116 | static int rfd77402_measure(struct rfd77402_data *data) | ||
| 117 | { | ||
| 118 | int ret; | ||
| 119 | int tries = 10; | ||
| 120 | |||
| 121 | ret = rfd77402_set_state(data, RFD77402_CMD_MCPU_ON, | ||
| 122 | RFD77402_STATUS_MCPU_ON); | ||
| 123 | if (ret < 0) | ||
| 124 | return ret; | ||
| 125 | |||
| 126 | ret = i2c_smbus_write_byte_data(data->client, RFD77402_CMD_R, | ||
| 127 | RFD77402_CMD_SINGLE | | ||
| 128 | RFD77402_CMD_VALID); | ||
| 129 | if (ret < 0) | ||
| 130 | goto err; | ||
| 131 | |||
| 132 | while (tries-- > 0) { | ||
| 133 | ret = i2c_smbus_read_byte_data(data->client, RFD77402_ICSR); | ||
| 134 | if (ret < 0) | ||
| 135 | goto err; | ||
| 136 | if (ret & RFD77402_ICSR_RESULT) | ||
| 137 | break; | ||
| 138 | msleep(20); | ||
| 139 | } | ||
| 140 | |||
| 141 | if (tries < 0) { | ||
| 142 | ret = -ETIMEDOUT; | ||
| 143 | goto err; | ||
| 144 | } | ||
| 145 | |||
| 146 | ret = i2c_smbus_read_word_data(data->client, RFD77402_RESULT_R); | ||
| 147 | if (ret < 0) | ||
| 148 | goto err; | ||
| 149 | |||
| 150 | if ((ret & RFD77402_RESULT_ERR_MASK) || | ||
| 151 | !(ret & RFD77402_RESULT_VALID)) { | ||
| 152 | ret = -EIO; | ||
| 153 | goto err; | ||
| 154 | } | ||
| 155 | |||
| 156 | return (ret & RFD77402_RESULT_DIST_MASK) >> 2; | ||
| 157 | |||
| 158 | err: | ||
| 159 | rfd77402_set_state(data, RFD77402_CMD_MCPU_OFF, | ||
| 160 | RFD77402_STATUS_MCPU_OFF); | ||
| 161 | return ret; | ||
| 162 | } | ||
| 163 | |||
| 164 | static int rfd77402_read_raw(struct iio_dev *indio_dev, | ||
| 165 | struct iio_chan_spec const *chan, | ||
| 166 | int *val, int *val2, long mask) | ||
| 167 | { | ||
| 168 | struct rfd77402_data *data = iio_priv(indio_dev); | ||
| 169 | int ret; | ||
| 170 | |||
| 171 | switch (mask) { | ||
| 172 | case IIO_CHAN_INFO_RAW: | ||
| 173 | mutex_lock(&data->lock); | ||
| 174 | ret = rfd77402_measure(data); | ||
| 175 | mutex_unlock(&data->lock); | ||
| 176 | if (ret < 0) | ||
| 177 | return ret; | ||
| 178 | *val = ret; | ||
| 179 | return IIO_VAL_INT; | ||
| 180 | case IIO_CHAN_INFO_SCALE: | ||
| 181 | /* 1 LSB is 1 mm */ | ||
| 182 | *val = 0; | ||
| 183 | *val2 = 1000; | ||
| 184 | return IIO_VAL_INT_PLUS_MICRO; | ||
| 185 | default: | ||
| 186 | return -EINVAL; | ||
| 187 | } | ||
| 188 | } | ||
| 189 | |||
| 190 | static const struct iio_info rfd77402_info = { | ||
| 191 | .read_raw = rfd77402_read_raw, | ||
| 192 | }; | ||
| 193 | |||
| 194 | static int rfd77402_init(struct rfd77402_data *data) | ||
| 195 | { | ||
| 196 | int ret, i; | ||
| 197 | |||
| 198 | ret = rfd77402_set_state(data, RFD77402_CMD_STANDBY, | ||
| 199 | RFD77402_STATUS_STANDBY); | ||
| 200 | if (ret < 0) | ||
| 201 | return ret; | ||
| 202 | |||
| 203 | /* configure INT pad as push-pull, active low */ | ||
| 204 | ret = i2c_smbus_write_byte_data(data->client, RFD77402_ICSR, | ||
| 205 | RFD77402_ICSR_INT_MODE); | ||
| 206 | if (ret < 0) | ||
| 207 | return ret; | ||
| 208 | |||
| 209 | /* I2C configuration */ | ||
| 210 | ret = i2c_smbus_write_word_data(data->client, RFD77402_I2C_INIT_CFG, | ||
| 211 | RFD77402_I2C_ADDR_INCR | | ||
| 212 | RFD77402_I2C_DATA_INCR | | ||
| 213 | RFD77402_I2C_HOST_DEBUG | | ||
| 214 | RFD77402_I2C_MCPU_DEBUG); | ||
| 215 | if (ret < 0) | ||
| 216 | return ret; | ||
| 217 | |||
| 218 | /* set initialization */ | ||
| 219 | ret = i2c_smbus_write_word_data(data->client, RFD77402_PMU_CFG, 0x0500); | ||
| 220 | if (ret < 0) | ||
| 221 | return ret; | ||
| 222 | |||
| 223 | ret = rfd77402_set_state(data, RFD77402_CMD_MCPU_OFF, | ||
| 224 | RFD77402_STATUS_MCPU_OFF); | ||
| 225 | if (ret < 0) | ||
| 226 | return ret; | ||
| 227 | |||
| 228 | /* set initialization */ | ||
| 229 | ret = i2c_smbus_write_word_data(data->client, RFD77402_PMU_CFG, 0x0600); | ||
| 230 | if (ret < 0) | ||
| 231 | return ret; | ||
| 232 | |||
| 233 | ret = rfd77402_set_state(data, RFD77402_CMD_MCPU_ON, | ||
| 234 | RFD77402_STATUS_MCPU_ON); | ||
| 235 | if (ret < 0) | ||
| 236 | return ret; | ||
| 237 | |||
| 238 | for (i = 0; i < ARRAY_SIZE(rf77402_tof_config); i++) { | ||
| 239 | ret = i2c_smbus_write_word_data(data->client, | ||
| 240 | rf77402_tof_config[i].reg, | ||
| 241 | rf77402_tof_config[i].val); | ||
| 242 | if (ret < 0) | ||
| 243 | return ret; | ||
| 244 | } | ||
| 245 | |||
| 246 | ret = rfd77402_set_state(data, RFD77402_CMD_STANDBY, | ||
| 247 | RFD77402_STATUS_STANDBY); | ||
| 248 | |||
| 249 | return ret; | ||
| 250 | } | ||
| 251 | |||
| 252 | static int rfd77402_powerdown(struct rfd77402_data *data) | ||
| 253 | { | ||
| 254 | return rfd77402_set_state(data, RFD77402_CMD_STANDBY, | ||
| 255 | RFD77402_STATUS_STANDBY); | ||
| 256 | } | ||
| 257 | |||
| 258 | static int rfd77402_probe(struct i2c_client *client, | ||
| 259 | const struct i2c_device_id *id) | ||
| 260 | { | ||
| 261 | struct rfd77402_data *data; | ||
| 262 | struct iio_dev *indio_dev; | ||
| 263 | int ret; | ||
| 264 | |||
| 265 | ret = i2c_smbus_read_word_data(client, RFD77402_MOD_CHIP_ID); | ||
| 266 | if (ret < 0) | ||
| 267 | return ret; | ||
| 268 | if (ret != 0xad01 && ret != 0xad02) /* known chip ids */ | ||
| 269 | return -ENODEV; | ||
| 270 | |||
| 271 | indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); | ||
| 272 | if (!indio_dev) | ||
| 273 | return -ENOMEM; | ||
| 274 | |||
| 275 | data = iio_priv(indio_dev); | ||
| 276 | i2c_set_clientdata(client, indio_dev); | ||
| 277 | data->client = client; | ||
| 278 | mutex_init(&data->lock); | ||
| 279 | |||
| 280 | indio_dev->dev.parent = &client->dev; | ||
| 281 | indio_dev->info = &rfd77402_info; | ||
| 282 | indio_dev->channels = rfd77402_channels; | ||
| 283 | indio_dev->num_channels = ARRAY_SIZE(rfd77402_channels); | ||
| 284 | indio_dev->name = RFD77402_DRV_NAME; | ||
| 285 | indio_dev->modes = INDIO_DIRECT_MODE; | ||
| 286 | |||
| 287 | ret = rfd77402_init(data); | ||
| 288 | if (ret < 0) | ||
| 289 | return ret; | ||
| 290 | |||
| 291 | ret = iio_device_register(indio_dev); | ||
| 292 | if (ret) | ||
| 293 | goto err_powerdown; | ||
| 294 | |||
| 295 | return 0; | ||
| 296 | |||
| 297 | err_powerdown: | ||
| 298 | rfd77402_powerdown(data); | ||
| 299 | return ret; | ||
| 300 | } | ||
| 301 | |||
| 302 | static int rfd77402_remove(struct i2c_client *client) | ||
| 303 | { | ||
| 304 | struct iio_dev *indio_dev = i2c_get_clientdata(client); | ||
| 305 | |||
| 306 | iio_device_unregister(indio_dev); | ||
| 307 | rfd77402_powerdown(iio_priv(indio_dev)); | ||
| 308 | |||
| 309 | return 0; | ||
| 310 | } | ||
| 311 | |||
| 312 | #ifdef CONFIG_PM_SLEEP | ||
| 313 | static int rfd77402_suspend(struct device *dev) | ||
| 314 | { | ||
| 315 | struct rfd77402_data *data = iio_priv(i2c_get_clientdata( | ||
| 316 | to_i2c_client(dev))); | ||
| 317 | |||
| 318 | return rfd77402_powerdown(data); | ||
| 319 | } | ||
| 320 | |||
| 321 | static int rfd77402_resume(struct device *dev) | ||
| 322 | { | ||
| 323 | struct rfd77402_data *data = iio_priv(i2c_get_clientdata( | ||
| 324 | to_i2c_client(dev))); | ||
| 325 | |||
| 326 | return rfd77402_init(data); | ||
| 327 | } | ||
| 328 | #endif | ||
| 329 | |||
| 330 | static SIMPLE_DEV_PM_OPS(rfd77402_pm_ops, rfd77402_suspend, rfd77402_resume); | ||
| 331 | |||
| 332 | static const struct i2c_device_id rfd77402_id[] = { | ||
| 333 | { "rfd77402", 0}, | ||
| 334 | { } | ||
| 335 | }; | ||
| 336 | MODULE_DEVICE_TABLE(i2c, rfd77402_id); | ||
| 337 | |||
| 338 | static struct i2c_driver rfd77402_driver = { | ||
| 339 | .driver = { | ||
| 340 | .name = RFD77402_DRV_NAME, | ||
| 341 | .pm = &rfd77402_pm_ops, | ||
| 342 | }, | ||
| 343 | .probe = rfd77402_probe, | ||
| 344 | .remove = rfd77402_remove, | ||
| 345 | .id_table = rfd77402_id, | ||
| 346 | }; | ||
| 347 | |||
| 348 | module_i2c_driver(rfd77402_driver); | ||
| 349 | |||
| 350 | MODULE_AUTHOR("Peter Meerwald-Stadler <pmeerw@pmeerw.net>"); | ||
| 351 | MODULE_DESCRIPTION("RFD77402 Time-of-Flight sensor driver"); | ||
| 352 | MODULE_LICENSE("GPL"); | ||
| @@ -203,7 +203,6 @@ static int srf04_read_raw(struct iio_dev *indio_dev, · 202 unmodified lines | |||
| 203 | } | 203 | } |
| 204 | 204 | ||
| 205 | static const struct iio_info srf04_iio_info = { | 205 | static const struct iio_info srf04_iio_info = { |
| 206 | .driver_module = THIS_MODULE, | ||
| 207 | .read_raw = srf04_read_raw, | 206 | .read_raw = srf04_read_raw, |
| 208 | }; | 207 | }; |
| 209 | 208 | ||
| @@ -436,7 +436,6 @@ static const struct iio_chan_spec srf08_channels[] = { · 435 unmodified lines | |||
| 436 | static const struct iio_info srf08_info = { | 436 | static const struct iio_info srf08_info = { |
| 437 | .read_raw = srf08_read_raw, | 437 | .read_raw = srf08_read_raw, |
| 438 | .attrs = &srf08_attribute_group, | 438 | .attrs = &srf08_attribute_group, |
| 439 | .driver_module = THIS_MODULE, | ||
| 440 | }; | 439 | }; |
| 441 | 440 | ||
| 442 | /* | 441 | /* |
| @@ -445,7 +444,6 @@ static const struct iio_info srf08_info = { · 2 unmodified lines | |||
| 445 | */ | 444 | */ |
| 446 | static const struct iio_info srf02_info = { | 445 | static const struct iio_info srf02_info = { |
| 447 | .read_raw = srf08_read_raw, | 446 | .read_raw = srf08_read_raw, |
| 448 | .driver_module = THIS_MODULE, | ||
| 449 | }; | 447 | }; |
| 450 | 448 | ||
| 451 | static int srf08_probe(struct i2c_client *client, | 449 | static int srf08_probe(struct i2c_client *client, |
| @@ -615,7 +615,6 @@ static const struct attribute_group sx9500_attribute_group = { · 614 unmodified lines | |||
| 615 | }; | 615 | }; |
| 616 | 616 | ||
| 617 | static const struct iio_info sx9500_info = { | 617 | static const struct iio_info sx9500_info = { |
| 618 | .driver_module = THIS_MODULE, | ||
| 619 | .attrs = &sx9500_attribute_group, | 618 | .attrs = &sx9500_attribute_group, |
| 620 | .read_raw = &sx9500_read_raw, | 619 | .read_raw = &sx9500_read_raw, |
| 621 | .write_raw = &sx9500_write_raw, | 620 | .write_raw = &sx9500_write_raw, |
| @@ -650,7 +649,6 @@ out: · 28 unmodified lines | |||
| 650 | 649 | ||
| 651 | static const struct iio_trigger_ops sx9500_trigger_ops = { | 650 | static const struct iio_trigger_ops sx9500_trigger_ops = { |
| 652 | .set_trigger_state = sx9500_set_trigger_state, | 651 | .set_trigger_state = sx9500_set_trigger_state, |
| 653 | .owner = THIS_MODULE, | ||
| 654 | }; | 652 | }; |
| 655 | 653 | ||
| 656 | static irqreturn_t sx9500_trigger_handler(int irq, void *private) | 654 | static irqreturn_t sx9500_trigger_handler(int irq, void *private) |
| @@ -123,7 +123,6 @@ static int temperature_write_raw(struct iio_dev *indio_dev, · 122 unmodified lines | |||
| 123 | } | 123 | } |
| 124 | 124 | ||
| 125 | static const struct iio_info temperature_info = { | 125 | static const struct iio_info temperature_info = { |
| 126 | .driver_module = THIS_MODULE, | ||
| 127 | .read_raw = &temperature_read_raw, | 126 | .read_raw = &temperature_read_raw, |
| 128 | .write_raw = &temperature_write_raw, | 127 | .write_raw = &temperature_write_raw, |
| 129 | }; | 128 | }; |
| @@ -208,7 +208,6 @@ static int maxim_thermocouple_read_raw(struct iio_dev *indio_dev, · 207 unmodified lines | |||
| 208 | } | 208 | } |
| 209 | 209 | ||
| 210 | static const struct iio_info maxim_thermocouple_info = { | 210 | static const struct iio_info maxim_thermocouple_info = { |
| 211 | .driver_module = THIS_MODULE, | ||
| 212 | .read_raw = maxim_thermocouple_read_raw, | 211 | .read_raw = maxim_thermocouple_read_raw, |
| 213 | }; | 212 | }; |
| 214 | 213 | ||
| @@ -400,7 +400,6 @@ static const struct iio_info mlx90614_info = { · 399 unmodified lines | |||
| 400 | .write_raw = mlx90614_write_raw, | 400 | .write_raw = mlx90614_write_raw, |
| 401 | .write_raw_get_fmt = mlx90614_write_raw_get_fmt, | 401 | .write_raw_get_fmt = mlx90614_write_raw_get_fmt, |
| 402 | .attrs = &mlx90614_attr_group, | 402 | .attrs = &mlx90614_attr_group, |
| 403 | .driver_module = THIS_MODULE, | ||
| 404 | }; | 403 | }; |
| 405 | 404 | ||
| 406 | #ifdef CONFIG_PM | 405 | #ifdef CONFIG_PM |
| @@ -179,7 +179,6 @@ static const struct iio_info tmp006_info = { · 178 unmodified lines | |||
| 179 | .read_raw = tmp006_read_raw, | 179 | .read_raw = tmp006_read_raw, |
| 180 | .write_raw = tmp006_write_raw, | 180 | .write_raw = tmp006_write_raw, |
| 181 | .attrs = &tmp006_attribute_group, | 181 | .attrs = &tmp006_attribute_group, |
| 182 | .driver_module = THIS_MODULE, | ||
| 183 | }; | 182 | }; |
| 184 | 183 | ||
| 185 | static bool tmp006_check_identification(struct i2c_client *client) | 184 | static bool tmp006_check_identification(struct i2c_client *client) |
| @@ -426,7 +426,6 @@ static const struct iio_info tmp007_info = { · 425 unmodified lines | |||
| 426 | .read_event_value = tmp007_read_thresh, | 426 | .read_event_value = tmp007_read_thresh, |
| 427 | .write_event_value = tmp007_write_thresh, | 427 | .write_event_value = tmp007_write_thresh, |
| 428 | .attrs = &tmp007_attribute_group, | 428 | .attrs = &tmp007_attribute_group, |
| 429 | .driver_module = THIS_MODULE, | ||
| 430 | }; | 429 | }; |
| 431 | 430 | ||
| 432 | static bool tmp007_identify(struct i2c_client *client) | 431 | static bool tmp007_identify(struct i2c_client *client) |
| @@ -111,7 +111,6 @@ static const struct iio_chan_spec tsys01_channels[] = { · 110 unmodified lines | |||
| 111 | 111 | ||
| 112 | static const struct iio_info tsys01_info = { | 112 | static const struct iio_info tsys01_info = { |
| 113 | .read_raw = tsys01_read_raw, | 113 | .read_raw = tsys01_read_raw, |
| 114 | .driver_module = THIS_MODULE, | ||
| 115 | }; | 114 | }; |
| 116 | 115 | ||
| 117 | static bool tsys01_crc_valid(u16 *n_prom) | 116 | static bool tsys01_crc_valid(u16 *n_prom) |
| @@ -120,7 +120,6 @@ static const struct iio_info tsys02d_info = { · 119 unmodified lines | |||
| 120 | .read_raw = tsys02d_read_raw, | 120 | .read_raw = tsys02d_read_raw, |
| 121 | .write_raw = tsys02d_write_raw, | 121 | .write_raw = tsys02d_write_raw, |
| 122 | .attrs = &tsys02d_attribute_group, | 122 | .attrs = &tsys02d_attribute_group, |
| 123 | .driver_module = THIS_MODULE, | ||
| 124 | }; | 123 | }; |
| 125 | 124 | ||
| 126 | static int tsys02d_probe(struct i2c_client *client, | 125 | static int tsys02d_probe(struct i2c_client *client, |
| @@ -114,7 +114,6 @@ static int iio_trig_hrtimer_set_state(struct iio_trigger *trig, bool state) · 113 unmodified lines | |||
| 114 | } | 114 | } |
| 115 | 115 | ||
| 116 | static const struct iio_trigger_ops iio_hrtimer_trigger_ops = { | 116 | static const struct iio_trigger_ops iio_hrtimer_trigger_ops = { |
| 117 | .owner = THIS_MODULE, | ||
| 118 | .set_trigger_state = iio_trig_hrtimer_set_state, | 117 | .set_trigger_state = iio_trig_hrtimer_set_state, |
| 119 | }; | 118 | }; |
| 120 | 119 | ||
| @@ -29,7 +29,6 @@ static irqreturn_t iio_interrupt_trigger_poll(int irq, void *private) · 28 unmodified lines | |||
| 29 | } | 29 | } |
| 30 | 30 | ||
| 31 | static const struct iio_trigger_ops iio_interrupt_trigger_ops = { | 31 | static const struct iio_trigger_ops iio_interrupt_trigger_ops = { |
| 32 | .owner = THIS_MODULE, | ||
| 33 | }; | 32 | }; |
| 34 | 33 | ||
| 35 | static int iio_interrupt_trigger_probe(struct platform_device *pdev) | 34 | static int iio_interrupt_trigger_probe(struct platform_device *pdev) |
| @@ -74,7 +74,6 @@ static int iio_loop_trigger_set_state(struct iio_trigger *trig, bool state) · 73 unmodified lines | |||
| 74 | 74 | ||
| 75 | static const struct iio_trigger_ops iio_loop_trigger_ops = { | 75 | static const struct iio_trigger_ops iio_loop_trigger_ops = { |
| 76 | .set_trigger_state = iio_loop_trigger_set_state, | 76 | .set_trigger_state = iio_loop_trigger_set_state, |
| 77 | .owner = THIS_MODULE, | ||
| 78 | }; | 77 | }; |
| 79 | 78 | ||
| 80 | static struct iio_sw_trigger *iio_trig_loop_probe(const char *name) | 79 | static struct iio_sw_trigger *iio_trig_loop_probe(const char *name) |
| @@ -127,7 +127,6 @@ static const struct attribute_group *iio_sysfs_trigger_attr_groups[] = { · 126 unmodified lines | |||
| 127 | }; | 127 | }; |
| 128 | 128 | ||
| 129 | static const struct iio_trigger_ops iio_sysfs_trigger_ops = { | 129 | static const struct iio_trigger_ops iio_sysfs_trigger_ops = { |
| 130 | .owner = THIS_MODULE, | ||
| 131 | }; | 130 | }; |
| 132 | 131 | ||
| 133 | static int iio_sysfs_trigger_probe(int id) | 132 | static int iio_sysfs_trigger_probe(int id) |
| @@ -37,7 +37,6 @@ static int stm32_lptim_validate_device(struct iio_trigger *trig, · 36 unmodified lines | |||
| 37 | } | 37 | } |
| 38 | 38 | ||
| 39 | static const struct iio_trigger_ops stm32_lptim_trigger_ops = { | 39 | static const struct iio_trigger_ops stm32_lptim_trigger_ops = { |
| 40 | .owner = THIS_MODULE, | ||
| 41 | .validate_device = stm32_lptim_validate_device, | 40 | .validate_device = stm32_lptim_validate_device, |
| 42 | }; | 41 | }; |
| 43 | 42 | ||
| @@ -355,7 +355,6 @@ static const struct attribute_group *stm32_trigger_attr_groups[] = { · 354 unmodified lines | |||
| 355 | }; | 355 | }; |
| 356 | 356 | ||
| 357 | static const struct iio_trigger_ops timer_trigger_ops = { | 357 | static const struct iio_trigger_ops timer_trigger_ops = { |
| 358 | .owner = THIS_MODULE, | ||
| 359 | }; | 358 | }; |
| 360 | 359 | ||
| 361 | static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv) | 360 | static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv) |
| @@ -493,7 +492,6 @@ static int stm32_counter_validate_trigger(struct iio_dev *indio_dev, · 131 unmodified lines | |||
| 493 | } | 492 | } |
| 494 | 493 | ||
| 495 | static const struct iio_info stm32_trigger_info = { | 494 | static const struct iio_info stm32_trigger_info = { |
| 496 | .driver_module = THIS_MODULE, | ||
| 497 | .validate_trigger = stm32_counter_validate_trigger, | 495 | .validate_trigger = stm32_counter_validate_trigger, |
| 498 | .read_raw = stm32_counter_read_raw, | 496 | .read_raw = stm32_counter_read_raw, |
| 499 | .write_raw = stm32_counter_write_raw | 497 | .write_raw = stm32_counter_write_raw |
| @@ -104,7 +104,6 @@ static int tsc2007_read_raw(struct iio_dev *indio_dev, · 103 unmodified lines | |||
| 104 | 104 | ||
| 105 | static const struct iio_info tsc2007_iio_info = { | 105 | static const struct iio_info tsc2007_iio_info = { |
| 106 | .read_raw = tsc2007_read_raw, | 106 | .read_raw = tsc2007_read_raw, |
| 107 | .driver_module = THIS_MODULE, | ||
| 108 | }; | 107 | }; |
| 109 | 108 | ||
| 110 | int tsc2007_iio_configure(struct tsc2007 *ts) | 109 | int tsc2007_iio_configure(struct tsc2007 *ts) |
| @@ -393,16 +393,6 @@ config SPEAR13XX_PCIE_GADGET · 392 unmodified lines | |||
| 393 | entry will be created for that controller. User can use these | 393 | entry will be created for that controller. User can use these |
| 394 | sysfs node to configure PCIe EP as per his requirements. | 394 | sysfs node to configure PCIe EP as per his requirements. |
| 395 | 395 | ||
| 396 | config TI_DAC7512 | ||
| 397 | tristate "Texas Instruments DAC7512" | ||
| 398 | depends on SPI && SYSFS | ||
| 399 | help | ||
| 400 | If you say yes here you get support for the Texas Instruments | ||
| 401 | DAC7512 16-bit digital-to-analog converter. | ||
| 402 | |||
| 403 | This driver can also be built as a module. If so, the module | ||
| 404 | will be called ti_dac7512. | ||
| 405 | |||
| 406 | config VMWARE_BALLOON | 396 | config VMWARE_BALLOON |
| 407 | tristate "VMware Balloon Driver" | 397 | tristate "VMware Balloon Driver" |
| 408 | depends on VMWARE_VMCI && X86 && HYPERVISOR_GUEST | 398 | depends on VMWARE_VMCI && X86 && HYPERVISOR_GUEST |
| @@ -31,7 +31,6 @@ obj-$(CONFIG_ISL29003) += isl29003.o · 30 unmodified lines | |||
| 31 | obj-$(CONFIG_ISL29020) += isl29020.o | 31 | obj-$(CONFIG_ISL29020) += isl29020.o |
| 32 | obj-$(CONFIG_SENSORS_TSL2550) += tsl2550.o | 32 | obj-$(CONFIG_SENSORS_TSL2550) += tsl2550.o |
| 33 | obj-$(CONFIG_DS1682) += ds1682.o | 33 | obj-$(CONFIG_DS1682) += ds1682.o |
| 34 | obj-$(CONFIG_TI_DAC7512) += ti_dac7512.o | ||
| 35 | obj-$(CONFIG_C2PORT) += c2port/ | 34 | obj-$(CONFIG_C2PORT) += c2port/ |
| 36 | obj-$(CONFIG_HMC6352) += hmc6352.o | 35 | obj-$(CONFIG_HMC6352) += hmc6352.o |
| 37 | obj-y += eeprom/ | 36 | obj-y += eeprom/ |
| @@ -1,103 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * dac7512.c - Linux kernel module for | ||
| 3 | * Texas Instruments DAC7512 | ||
| 4 | * | ||
| 5 | * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 20 | */ | ||
| 21 | |||
| 22 | #include <linux/module.h> | ||
| 23 | #include <linux/spi/spi.h> | ||
| 24 | #include <linux/of.h> | ||
| 25 | |||
| 26 | static ssize_t dac7512_store_val(struct device *dev, | ||
| 27 | struct device_attribute *attr, | ||
| 28 | const char *buf, size_t count) | ||
| 29 | { | ||
| 30 | struct spi_device *spi = to_spi_device(dev); | ||
| 31 | unsigned char tmp[2]; | ||
| 32 | unsigned long val; | ||
| 33 | int ret; | ||
| 34 | |||
| 35 | ret = kstrtoul(buf, 10, &val); | ||
| 36 | if (ret) | ||
| 37 | return ret; | ||
| 38 | |||
| 39 | tmp[0] = val >> 8; | ||
| 40 | tmp[1] = val & 0xff; | ||
| 41 | spi_write(spi, tmp, sizeof(tmp)); | ||
| 42 | return count; | ||
| 43 | } | ||
| 44 | |||
| 45 | static DEVICE_ATTR(value, S_IWUSR, NULL, dac7512_store_val); | ||
| 46 | |||
| 47 | static struct attribute *dac7512_attributes[] = { | ||
| 48 | &dev_attr_value.attr, | ||
| 49 | NULL | ||
| 50 | }; | ||
| 51 | |||
| 52 | static const struct attribute_group dac7512_attr_group = { | ||
| 53 | .attrs = dac7512_attributes, | ||
| 54 | }; | ||
| 55 | |||
| 56 | static int dac7512_probe(struct spi_device *spi) | ||
| 57 | { | ||
| 58 | int ret; | ||
| 59 | |||
| 60 | spi->bits_per_word = 8; | ||
| 61 | spi->mode = SPI_MODE_0; | ||
| 62 | ret = spi_setup(spi); | ||
| 63 | if (ret < 0) | ||
| 64 | return ret; | ||
| 65 | |||
| 66 | return sysfs_create_group(&spi->dev.kobj, &dac7512_attr_group); | ||
| 67 | } | ||
| 68 | |||
| 69 | static int dac7512_remove(struct spi_device *spi) | ||
| 70 | { | ||
| 71 | sysfs_remove_group(&spi->dev.kobj, &dac7512_attr_group); | ||
| 72 | return 0; | ||
| 73 | } | ||
| 74 | |||
| 75 | static const struct spi_device_id dac7512_id_table[] = { | ||
| 76 | { "dac7512", 0 }, | ||
| 77 | { } | ||
| 78 | }; | ||
| 79 | MODULE_DEVICE_TABLE(spi, dac7512_id_table); | ||
| 80 | |||
| 81 | #ifdef CONFIG_OF | ||
| 82 | static const struct of_device_id dac7512_of_match[] = { | ||
| 83 | { .compatible = "ti,dac7512", }, | ||
| 84 | { } | ||
| 85 | }; | ||
| 86 | MODULE_DEVICE_TABLE(of, dac7512_of_match); | ||
| 87 | #endif | ||
| 88 | |||
| 89 | static struct spi_driver dac7512_driver = { | ||
| 90 | .driver = { | ||
| 91 | .name = "dac7512", | ||
| 92 | .of_match_table = of_match_ptr(dac7512_of_match), | ||
| 93 | }, | ||
| 94 | .probe = dac7512_probe, | ||
| 95 | .remove = dac7512_remove, | ||
| 96 | .id_table = dac7512_id_table, | ||
| 97 | }; | ||
| 98 | |||
| 99 | module_spi_driver(dac7512_driver); | ||
| 100 | |||
| 101 | MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>"); | ||
| 102 | MODULE_DESCRIPTION("DAC7512 16-bit DAC"); | ||
| 103 | MODULE_LICENSE("GPL v2"); | ||
| @@ -2510,7 +2510,6 @@ static const struct iio_chan_spec toshiba_iio_accel_channels[] = { · 2509 unmodified lines | |||
| 2510 | }; | 2510 | }; |
| 2511 | 2511 | ||
| 2512 | static const struct iio_info toshiba_iio_accel_info = { | 2512 | static const struct iio_info toshiba_iio_accel_info = { |
| 2513 | .driver_module = THIS_MODULE, | ||
| 2514 | .read_raw = &toshiba_iio_accel_read_raw, | 2513 | .read_raw = &toshiba_iio_accel_read_raw, |
| 2515 | }; | 2514 | }; |
| 2516 | 2515 | ||
| @@ -1,5 +1,4 @@ | |||
| 1 | TODO: | 1 | TODO: |
| 2 | - checkpatch.pl cleanups | ||
| 3 | - sparse fixes | 2 | - sparse fixes |
| 4 | - rename files to be not so "generic" | 3 | - rename files to be not so "generic" |
| 5 | - add proper arch dependencies as needed | 4 | - add proper arch dependencies as needed |
| @@ -27,19 +27,18 @@ union ion_ioctl_arg { · 26 unmodified lines | |||
| 27 | 27 | ||
| 28 | static int validate_ioctl_arg(unsigned int cmd, union ion_ioctl_arg *arg) | 28 | static int validate_ioctl_arg(unsigned int cmd, union ion_ioctl_arg *arg) |
| 29 | { | 29 | { |
| 30 | int ret = 0; | ||
| 31 | |||
| 32 | switch (cmd) { | 30 | switch (cmd) { |
| 33 | case ION_IOC_HEAP_QUERY: | 31 | case ION_IOC_HEAP_QUERY: |
| 34 | ret = arg->query.reserved0 != 0; | 32 | if (arg->query.reserved0 || |
| 35 | ret |= arg->query.reserved1 != 0; | 33 | arg->query.reserved1 || |
| 36 | ret |= arg->query.reserved2 != 0; | 34 | arg->query.reserved2) |
| 35 | return -EINVAL; | ||
| 37 | break; | 36 | break; |
| 38 | default: | 37 | default: |
| 39 | break; | 38 | break; |
| 40 | } | 39 | } |
| 41 | 40 | ||
| 42 | return ret ? -EINVAL : 0; | 41 | return 0; |
| 43 | } | 42 | } |
| 44 | 43 | ||
| 45 | /* fix up the cases where the ioctl direction bits are incorrect */ | 44 | /* fix up the cases where the ioctl direction bits are incorrect */ |
| @@ -81,7 +81,6 @@ static struct ion_buffer *ion_buffer_create(struct ion_heap *heap, · 80 unmodified lines | |||
| 81 | unsigned long flags) | 81 | unsigned long flags) |
| 82 | { | 82 | { |
| 83 | struct ion_buffer *buffer; | 83 | struct ion_buffer *buffer; |
| 84 | struct sg_table *table; | ||
| 85 | int ret; | 84 | int ret; |
| 86 | 85 | ||
| 87 | buffer = kzalloc(sizeof(*buffer), GFP_KERNEL); | 86 | buffer = kzalloc(sizeof(*buffer), GFP_KERNEL); |
| @@ -109,7 +108,6 @@ static struct ion_buffer *ion_buffer_create(struct ion_heap *heap, · 21 unmodified lines | |||
| 109 | goto err1; | 108 | goto err1; |
| 110 | } | 109 | } |
| 111 | 110 | ||
| 112 | table = buffer->sg_table; | ||
| 113 | buffer->dev = dev; | 111 | buffer->dev = dev; |
| 114 | buffer->size = len; | 112 | buffer->size = len; |
| 115 | 113 | ||
| @@ -86,6 +86,7 @@ struct ion_buffer { · 85 unmodified lines | |||
| 86 | struct sg_table *sg_table; | 86 | struct sg_table *sg_table; |
| 87 | struct list_head attachments; | 87 | struct list_head attachments; |
| 88 | }; | 88 | }; |
| 89 | |||
| 89 | void ion_buffer_destroy(struct ion_buffer *buffer); | 90 | void ion_buffer_destroy(struct ion_buffer *buffer); |
| 90 | 91 | ||
| 91 | /** | 92 | /** |
| @@ -299,7 +300,6 @@ size_t ion_heap_freelist_shrink(struct ion_heap *heap, · 207 unmodified lines | |||
| 299 | */ | 300 | */ |
| 300 | size_t ion_heap_freelist_size(struct ion_heap *heap); | 301 | size_t ion_heap_freelist_size(struct ion_heap *heap); |
| 301 | 302 | ||
| 302 | |||
| 303 | /** | 303 | /** |
| 304 | * functions for creating and destroying a heap pool -- allows you | 304 | * functions for creating and destroying a heap pool -- allows you |
| 305 | * to keep a pool of pre allocated memory to use from your heap. Keeping | 305 | * to keep a pool of pre allocated memory to use from your heap. Keeping |
| @@ -1,33 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2012-2017 ARM Limited or its affiliates. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | ||
| 15 | */ | ||
| 16 | |||
| 17 | /* pseudo cc_hal.h for cc7x_perf_test_driver (to be able to include code from | ||
| 18 | * CC drivers). | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __CC_HAL_H__ | ||
| 22 | #define __CC_HAL_H__ | ||
| 23 | |||
| 24 | #include <linux/io.h> | ||
| 25 | |||
| 26 | #define READ_REGISTER(_addr) ioread32((_addr)) | ||
| 27 | #define WRITE_REGISTER(_addr, _data) iowrite32((_data), (_addr)) | ||
| 28 | |||
| 29 | #define CC_HAL_WRITE_REGISTER(offset, val) \ | ||
| 30 | WRITE_REGISTER(cc_base + (offset), val) | ||
| 31 | #define CC_HAL_READ_REGISTER(offset) READ_REGISTER(cc_base + (offset)) | ||
| 32 | |||
| 33 | #endif | ||
| @@ -59,7 +59,7 @@ static inline void cc_lli_set_addr(u32 *lli_p, dma_addr_t addr) · 58 unmodified lines | |||
| 59 | lli_p[LLI_WORD0_OFFSET] = (addr & U32_MAX); | 59 | lli_p[LLI_WORD0_OFFSET] = (addr & U32_MAX); |
| 60 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | 60 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
| 61 | lli_p[LLI_WORD1_OFFSET] &= ~LLI_HADDR_MASK; | 61 | lli_p[LLI_WORD1_OFFSET] &= ~LLI_HADDR_MASK; |
| 62 | lli_p[LLI_WORD1_OFFSET] |= FIELD_PREP(LLI_HADDR_MASK, (addr >> 16)); | 62 | lli_p[LLI_WORD1_OFFSET] |= FIELD_PREP(LLI_HADDR_MASK, (addr >> 32)); |
| 63 | #endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */ | 63 | #endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */ |
| 64 | } | 64 | } |
| 65 | 65 | ||
| @@ -1,42 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2012-2017 ARM Limited or its affiliates. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | ||
| 15 | */ | ||
| 16 | |||
| 17 | /*! | ||
| 18 | * @file | ||
| 19 | * @brief This file contains macro definitions for accessing ARM TrustZone | ||
| 20 | * CryptoCell register space. | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef _CC_REGS_H_ | ||
| 24 | #define _CC_REGS_H_ | ||
| 25 | |||
| 26 | #include <linux/bitfield.h> | ||
| 27 | |||
| 28 | #define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP) | ||
| 29 | #define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \ | ||
| 30 | DX_AXIM_MON_COMP_VALUE_BIT_SHIFT, \ | ||
| 31 | DX_AXIM_MON_COMP_VALUE_BIT_SHIFT) | ||
| 32 | |||
| 33 | #define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP) | ||
| 34 | #define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \ | ||
| 35 | DX_AXIM_MON_COMP_VALUE_BIT_SHIFT, \ | ||
| 36 | DX_AXIM_MON_COMP_VALUE_BIT_SHIFT) | ||
| 37 | |||
| 38 | /* Register Offset macro */ | ||
| 39 | #define CC_REG_OFFSET(unit_name, reg_name) \ | ||
| 40 | (DX_BASE_ ## unit_name + DX_ ## reg_name ## _REG_OFFSET) | ||
| 41 | |||
| 42 | #endif /*_CC_REGS_H_*/ | ||
| @@ -1,25 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2012-2017 ARM Limited or its affiliates. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef __DX_REG_BASE_HOST_H__ | ||
| 18 | #define __DX_REG_BASE_HOST_H__ | ||
| 19 | |||
| 20 | #define DX_BASE_CC 0x80000000 | ||
| 21 | #define DX_BASE_HOST_RGF 0x0UL | ||
| 22 | #define DX_BASE_CRY_KERNEL 0x0UL | ||
| 23 | #define DX_BASE_ROM 0x40000000 | ||
| 24 | |||
| 25 | #endif /*__DX_REG_BASE_HOST_H__*/ | ||
| @@ -92,18 +92,17 @@ static inline bool valid_assoclen(struct aead_request *req) · 91 unmodified lines | |||
| 92 | 92 | ||
| 93 | static void ssi_aead_exit(struct crypto_aead *tfm) | 93 | static void ssi_aead_exit(struct crypto_aead *tfm) |
| 94 | { | 94 | { |
| 95 | struct device *dev = NULL; | ||
| 96 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); | 95 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); |
| 96 | struct device *dev = drvdata_to_dev(ctx->drvdata); | ||
| 97 | 97 | ||
| 98 | SSI_LOG_DEBUG("Clearing context @%p for %s\n", | 98 | dev_dbg(dev, "Clearing context @%p for %s\n", crypto_aead_ctx(tfm), |
| 99 | crypto_aead_ctx(tfm), crypto_tfm_alg_name(&tfm->base)); | 99 | crypto_tfm_alg_name(&tfm->base)); |
| 100 | 100 | ||
| 101 | dev = &ctx->drvdata->plat_dev->dev; | ||
| 102 | /* Unmap enckey buffer */ | 101 | /* Unmap enckey buffer */ |
| 103 | if (ctx->enckey) { | 102 | if (ctx->enckey) { |
| 104 | dma_free_coherent(dev, AES_MAX_KEY_SIZE, ctx->enckey, ctx->enckey_dma_addr); | 103 | dma_free_coherent(dev, AES_MAX_KEY_SIZE, ctx->enckey, ctx->enckey_dma_addr); |
| 105 | SSI_LOG_DEBUG("Freed enckey DMA buffer enckey_dma_addr=%pad\n", | 104 | dev_dbg(dev, "Freed enckey DMA buffer enckey_dma_addr=%pad\n", |
| 106 | ctx->enckey_dma_addr); | 105 | &ctx->enckey_dma_addr); |
| 107 | ctx->enckey_dma_addr = 0; | 106 | ctx->enckey_dma_addr = 0; |
| 108 | ctx->enckey = NULL; | 107 | ctx->enckey = NULL; |
| 109 | } | 108 | } |
| @@ -116,8 +115,8 @@ static void ssi_aead_exit(struct crypto_aead *tfm) · 6 unmodified lines | |||
| 116 | xcbc->xcbc_keys, | 115 | xcbc->xcbc_keys, |
| 117 | xcbc->xcbc_keys_dma_addr); | 116 | xcbc->xcbc_keys_dma_addr); |
| 118 | } | 117 | } |
| 119 | SSI_LOG_DEBUG("Freed xcbc_keys DMA buffer xcbc_keys_dma_addr=%pad\n", | 118 | dev_dbg(dev, "Freed xcbc_keys DMA buffer xcbc_keys_dma_addr=%pad\n", |
| 120 | xcbc->xcbc_keys_dma_addr); | 119 | &xcbc->xcbc_keys_dma_addr); |
| 121 | xcbc->xcbc_keys_dma_addr = 0; | 120 | xcbc->xcbc_keys_dma_addr = 0; |
| 122 | xcbc->xcbc_keys = NULL; | 121 | xcbc->xcbc_keys = NULL; |
| 123 | } else if (ctx->auth_mode != DRV_HASH_NULL) { /* HMAC auth. */ | 122 | } else if (ctx->auth_mode != DRV_HASH_NULL) { /* HMAC auth. */ |
| @@ -127,8 +126,8 @@ static void ssi_aead_exit(struct crypto_aead *tfm) · 3 unmodified lines | |||
| 127 | dma_free_coherent(dev, 2 * MAX_HMAC_DIGEST_SIZE, | 126 | dma_free_coherent(dev, 2 * MAX_HMAC_DIGEST_SIZE, |
| 128 | hmac->ipad_opad, | 127 | hmac->ipad_opad, |
| 129 | hmac->ipad_opad_dma_addr); | 128 | hmac->ipad_opad_dma_addr); |
| 130 | SSI_LOG_DEBUG("Freed ipad_opad DMA buffer ipad_opad_dma_addr=%pad\n", | 129 | dev_dbg(dev, "Freed ipad_opad DMA buffer ipad_opad_dma_addr=%pad\n", |
| 131 | hmac->ipad_opad_dma_addr); | 130 | &hmac->ipad_opad_dma_addr); |
| 132 | hmac->ipad_opad_dma_addr = 0; | 131 | hmac->ipad_opad_dma_addr = 0; |
| 133 | hmac->ipad_opad = NULL; | 132 | hmac->ipad_opad = NULL; |
| 134 | } | 133 | } |
| @@ -136,8 +135,8 @@ static void ssi_aead_exit(struct crypto_aead *tfm) · 1 unmodified line | |||
| 136 | dma_free_coherent(dev, MAX_HMAC_BLOCK_SIZE, | 135 | dma_free_coherent(dev, MAX_HMAC_BLOCK_SIZE, |
| 137 | hmac->padded_authkey, | 136 | hmac->padded_authkey, |
| 138 | hmac->padded_authkey_dma_addr); | 137 | hmac->padded_authkey_dma_addr); |
| 139 | SSI_LOG_DEBUG("Freed padded_authkey DMA buffer padded_authkey_dma_addr=%pad\n", | 138 | dev_dbg(dev, "Freed padded_authkey DMA buffer padded_authkey_dma_addr=%pad\n", |
| 140 | hmac->padded_authkey_dma_addr); | 139 | &hmac->padded_authkey_dma_addr); |
| 141 | hmac->padded_authkey_dma_addr = 0; | 140 | hmac->padded_authkey_dma_addr = 0; |
| 142 | hmac->padded_authkey = NULL; | 141 | hmac->padded_authkey = NULL; |
| 143 | } | 142 | } |
| @@ -146,29 +145,31 @@ static void ssi_aead_exit(struct crypto_aead *tfm) · 2 unmodified lines | |||
| 146 | 145 | ||
| 147 | static int ssi_aead_init(struct crypto_aead *tfm) | 146 | static int ssi_aead_init(struct crypto_aead *tfm) |
| 148 | { | 147 | { |
| 149 | struct device *dev; | ||
| 150 | struct aead_alg *alg = crypto_aead_alg(tfm); | 148 | struct aead_alg *alg = crypto_aead_alg(tfm); |
| 151 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); | 149 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); |
| 152 | struct ssi_crypto_alg *ssi_alg = | 150 | struct ssi_crypto_alg *ssi_alg = |
| 153 | container_of(alg, struct ssi_crypto_alg, aead_alg); | 151 | container_of(alg, struct ssi_crypto_alg, aead_alg); |
| 154 | SSI_LOG_DEBUG("Initializing context @%p for %s\n", ctx, crypto_tfm_alg_name(&tfm->base)); | 152 | struct device *dev = drvdata_to_dev(ssi_alg->drvdata); |
| 153 | |||
| 154 | dev_dbg(dev, "Initializing context @%p for %s\n", ctx, | ||
| 155 | crypto_tfm_alg_name(&tfm->base)); | ||
| 155 | 156 | ||
| 156 | /* Initialize modes in instance */ | 157 | /* Initialize modes in instance */ |
| 157 | ctx->cipher_mode = ssi_alg->cipher_mode; | 158 | ctx->cipher_mode = ssi_alg->cipher_mode; |
| 158 | ctx->flow_mode = ssi_alg->flow_mode; | 159 | ctx->flow_mode = ssi_alg->flow_mode; |
| 159 | ctx->auth_mode = ssi_alg->auth_mode; | 160 | ctx->auth_mode = ssi_alg->auth_mode; |
| 160 | ctx->drvdata = ssi_alg->drvdata; | 161 | ctx->drvdata = ssi_alg->drvdata; |
| 161 | dev = &ctx->drvdata->plat_dev->dev; | ||
| 162 | crypto_aead_set_reqsize(tfm, sizeof(struct aead_req_ctx)); | 162 | crypto_aead_set_reqsize(tfm, sizeof(struct aead_req_ctx)); |
| 163 | 163 | ||
| 164 | /* Allocate key buffer, cache line aligned */ | 164 | /* Allocate key buffer, cache line aligned */ |
| 165 | ctx->enckey = dma_alloc_coherent(dev, AES_MAX_KEY_SIZE, | 165 | ctx->enckey = dma_alloc_coherent(dev, AES_MAX_KEY_SIZE, |
| 166 | &ctx->enckey_dma_addr, GFP_KERNEL); | 166 | &ctx->enckey_dma_addr, GFP_KERNEL); |
| 167 | if (!ctx->enckey) { | 167 | if (!ctx->enckey) { |
| 168 | SSI_LOG_ERR("Failed allocating key buffer\n"); | 168 | dev_err(dev, "Failed allocating key buffer\n"); |
| 169 | goto init_failed; | 169 | goto init_failed; |
| 170 | } | 170 | } |
| 171 | SSI_LOG_DEBUG("Allocated enckey buffer in context ctx->enckey=@%p\n", ctx->enckey); | 171 | dev_dbg(dev, "Allocated enckey buffer in context ctx->enckey=@%p\n", |
| 172 | ctx->enckey); | ||
| 172 | 173 | ||
| 173 | /* Set default authlen value */ | 174 | /* Set default authlen value */ |
| 174 | 175 | ||
| @@ -182,7 +183,7 @@ static int ssi_aead_init(struct crypto_aead *tfm) · 7 unmodified lines | |||
| 182 | &xcbc->xcbc_keys_dma_addr, | 183 | &xcbc->xcbc_keys_dma_addr, |
| 183 | GFP_KERNEL); | 184 | GFP_KERNEL); |
| 184 | if (!xcbc->xcbc_keys) { | 185 | if (!xcbc->xcbc_keys) { |
| 185 | SSI_LOG_ERR("Failed allocating buffer for XCBC keys\n"); | 186 | dev_err(dev, "Failed allocating buffer for XCBC keys\n"); |
| 186 | goto init_failed; | 187 | goto init_failed; |
| 187 | } | 188 | } |
| 188 | } else if (ctx->auth_mode != DRV_HASH_NULL) { /* HMAC authentication */ | 189 | } else if (ctx->auth_mode != DRV_HASH_NULL) { /* HMAC authentication */ |
| @@ -196,12 +197,12 @@ static int ssi_aead_init(struct crypto_aead *tfm) · 7 unmodified lines | |||
| 196 | GFP_KERNEL); | 197 | GFP_KERNEL); |
| 197 | 198 | ||
| 198 | if (!hmac->ipad_opad) { | 199 | if (!hmac->ipad_opad) { |
| 199 | SSI_LOG_ERR("Failed allocating IPAD/OPAD buffer\n"); | 200 | dev_err(dev, "Failed allocating IPAD/OPAD buffer\n"); |
| 200 | goto init_failed; | 201 | goto init_failed; |
| 201 | } | 202 | } |
| 202 | 203 | ||
| 203 | SSI_LOG_DEBUG("Allocated authkey buffer in context ctx->authkey=@%p\n", | 204 | dev_dbg(dev, "Allocated authkey buffer in context ctx->authkey=@%p\n", |
| 204 | hmac->ipad_opad); | 205 | hmac->ipad_opad); |
| 205 | 206 | ||
| 206 | hmac->padded_authkey = dma_alloc_coherent(dev, | 207 | hmac->padded_authkey = dma_alloc_coherent(dev, |
| 207 | MAX_HMAC_BLOCK_SIZE, | 208 | MAX_HMAC_BLOCK_SIZE, |
| @@ -209,7 +210,7 @@ static int ssi_aead_init(struct crypto_aead *tfm) · 1 unmodified line | |||
| 209 | GFP_KERNEL); | 210 | GFP_KERNEL); |
| 210 | 211 | ||
| 211 | if (!hmac->padded_authkey) { | 212 | if (!hmac->padded_authkey) { |
| 212 | SSI_LOG_ERR("failed to allocate padded_authkey\n"); | 213 | dev_err(dev, "failed to allocate padded_authkey\n"); |
| 213 | goto init_failed; | 214 | goto init_failed; |
| 214 | } | 215 | } |
| 215 | } else { | 216 | } else { |
| @@ -240,8 +241,7 @@ static void ssi_aead_complete(struct device *dev, void *ssi_req, void __iomem *c · 24 unmodified lines | |||
| 240 | if (areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) { | 241 | if (areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) { |
| 241 | if (memcmp(areq_ctx->mac_buf, areq_ctx->icv_virt_addr, | 242 | if (memcmp(areq_ctx->mac_buf, areq_ctx->icv_virt_addr, |
| 242 | ctx->authsize) != 0) { | 243 | ctx->authsize) != 0) { |
| 243 | SSI_LOG_DEBUG("Payload authentication failure, " | 244 | dev_dbg(dev, "Payload authentication failure, (auth-size=%d, cipher=%d)\n", |
| 244 | "(auth-size=%d, cipher=%d).\n", | ||
| 245 | ctx->authsize, ctx->cipher_mode); | 245 | ctx->authsize, ctx->cipher_mode); |
| 246 | /* In case of payload authentication failure, MUST NOT | 246 | /* In case of payload authentication failure, MUST NOT |
| 247 | * revealed the decrypted message --> zero its memory. | 247 | * revealed the decrypted message --> zero its memory. |
| @@ -252,8 +252,11 @@ static void ssi_aead_complete(struct device *dev, void *ssi_req, void __iomem *c · 4 unmodified lines | |||
| 252 | } else { /*ENCRYPT*/ | 252 | } else { /*ENCRYPT*/ |
| 253 | if (unlikely(areq_ctx->is_icv_fragmented)) | 253 | if (unlikely(areq_ctx->is_icv_fragmented)) |
| 254 | ssi_buffer_mgr_copy_scatterlist_portion( | 254 | ssi_buffer_mgr_copy_scatterlist_portion( |
| 255 | areq_ctx->mac_buf, areq_ctx->dst_sgl, areq->cryptlen + areq_ctx->dst_offset, | 255 | dev, areq_ctx->mac_buf, areq_ctx->dst_sgl, |
| 256 | areq->cryptlen + areq_ctx->dst_offset + ctx->authsize, SSI_SG_FROM_BUF); | 256 | areq->cryptlen + areq_ctx->dst_offset, |
| 257 | (areq->cryptlen + areq_ctx->dst_offset + | ||
| 258 | ctx->authsize), | ||
| 259 | SSI_SG_FROM_BUF); | ||
| 257 | 260 | ||
| 258 | /* If an IV was generated, copy it back to the user provided buffer. */ | 261 | /* If an IV was generated, copy it back to the user provided buffer. */ |
| 259 | if (areq_ctx->backup_giv) { | 262 | if (areq_ctx->backup_giv) { |
| @@ -377,8 +380,10 @@ static int hmac_setkey(struct cc_hw_desc *desc, struct ssi_aead_ctx *ctx) · 117 unmodified lines | |||
| 377 | 380 | ||
| 378 | static int validate_keys_sizes(struct ssi_aead_ctx *ctx) | 381 | static int validate_keys_sizes(struct ssi_aead_ctx *ctx) |
| 379 | { | 382 | { |
| 380 | SSI_LOG_DEBUG("enc_keylen=%u authkeylen=%u\n", | 383 | struct device *dev = drvdata_to_dev(ctx->drvdata); |
| 381 | ctx->enc_keylen, ctx->auth_keylen); | 384 | |
| 385 | dev_dbg(dev, "enc_keylen=%u authkeylen=%u\n", | ||
| 386 | ctx->enc_keylen, ctx->auth_keylen); | ||
| 382 | 387 | ||
| 383 | switch (ctx->auth_mode) { | 388 | switch (ctx->auth_mode) { |
| 384 | case DRV_HASH_SHA1: | 389 | case DRV_HASH_SHA1: |
| @@ -395,22 +400,22 @@ static int validate_keys_sizes(struct ssi_aead_ctx *ctx) · 10 unmodified lines | |||
| 395 | return -EINVAL; | 400 | return -EINVAL; |
| 396 | break; | 401 | break; |
| 397 | default: | 402 | default: |
| 398 | SSI_LOG_ERR("Invalid auth_mode=%d\n", ctx->auth_mode); | 403 | dev_err(dev, "Invalid auth_mode=%d\n", ctx->auth_mode); |
| 399 | return -EINVAL; | 404 | return -EINVAL; |
| 400 | } | 405 | } |
| 401 | /* Check cipher key size */ | 406 | /* Check cipher key size */ |
| 402 | if (unlikely(ctx->flow_mode == S_DIN_to_DES)) { | 407 | if (unlikely(ctx->flow_mode == S_DIN_to_DES)) { |
| 403 | if (ctx->enc_keylen != DES3_EDE_KEY_SIZE) { | 408 | if (ctx->enc_keylen != DES3_EDE_KEY_SIZE) { |
| 404 | SSI_LOG_ERR("Invalid cipher(3DES) key size: %u\n", | 409 | dev_err(dev, "Invalid cipher(3DES) key size: %u\n", |
| 405 | ctx->enc_keylen); | 410 | ctx->enc_keylen); |
| 406 | return -EINVAL; | 411 | return -EINVAL; |
| 407 | } | 412 | } |
| 408 | } else { /* Default assumed to be AES ciphers */ | 413 | } else { /* Default assumed to be AES ciphers */ |
| 409 | if ((ctx->enc_keylen != AES_KEYSIZE_128) && | 414 | if ((ctx->enc_keylen != AES_KEYSIZE_128) && |
| 410 | (ctx->enc_keylen != AES_KEYSIZE_192) && | 415 | (ctx->enc_keylen != AES_KEYSIZE_192) && |
| 411 | (ctx->enc_keylen != AES_KEYSIZE_256)) { | 416 | (ctx->enc_keylen != AES_KEYSIZE_256)) { |
| 412 | SSI_LOG_ERR("Invalid cipher(AES) key size: %u\n", | 417 | dev_err(dev, "Invalid cipher(AES) key size: %u\n", |
| 413 | ctx->enc_keylen); | 418 | ctx->enc_keylen); |
| 414 | return -EINVAL; | 419 | return -EINVAL; |
| 415 | } | 420 | } |
| 416 | } | 421 | } |
| @@ -426,7 +431,7 @@ ssi_get_plain_hmac_key(struct crypto_aead *tfm, const u8 *key, unsigned int keyl · 9 unmodified lines | |||
| 426 | { | 431 | { |
| 427 | dma_addr_t key_dma_addr = 0; | 432 | dma_addr_t key_dma_addr = 0; |
| 428 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); | 433 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); |
| 429 | struct device *dev = &ctx->drvdata->plat_dev->dev; | 434 | struct device *dev = drvdata_to_dev(ctx->drvdata); |
| 430 | u32 larval_addr = ssi_ahash_get_larval_digest_sram_addr( | 435 | u32 larval_addr = ssi_ahash_get_larval_digest_sram_addr( |
| 431 | ctx->drvdata, ctx->auth_mode); | 436 | ctx->drvdata, ctx->auth_mode); |
| 432 | struct ssi_crypto_req ssi_req = {}; | 437 | struct ssi_crypto_req ssi_req = {}; |
| @@ -455,8 +460,8 @@ ssi_get_plain_hmac_key(struct crypto_aead *tfm, const u8 *key, unsigned int keyl · 22 unmodified lines | |||
| 455 | if (likely(keylen != 0)) { | 460 | if (likely(keylen != 0)) { |
| 456 | key_dma_addr = dma_map_single(dev, (void *)key, keylen, DMA_TO_DEVICE); | 461 | key_dma_addr = dma_map_single(dev, (void *)key, keylen, DMA_TO_DEVICE); |
| 457 | if (unlikely(dma_mapping_error(dev, key_dma_addr))) { | 462 | if (unlikely(dma_mapping_error(dev, key_dma_addr))) { |
| 458 | SSI_LOG_ERR("Mapping key va=0x%p len=%u for" | 463 | dev_err(dev, "Mapping key va=0x%p len=%u for DMA failed\n", |
| 459 | " DMA failed\n", key, keylen); | 464 | key, keylen); |
| 460 | return -ENOMEM; | 465 | return -ENOMEM; |
| 461 | } | 466 | } |
| 462 | if (keylen > blocksize) { | 467 | if (keylen > blocksize) { |
| @@ -534,7 +539,7 @@ ssi_get_plain_hmac_key(struct crypto_aead *tfm, const u8 *key, unsigned int keyl · 71 unmodified lines | |||
| 534 | 539 | ||
| 535 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0); | 540 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0); |
| 536 | if (unlikely(rc != 0)) | 541 | if (unlikely(rc != 0)) |
| 537 | SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc); | 542 | dev_err(dev, "send_request() failed (rc=%d)\n", rc); |
| 538 | 543 | ||
| 539 | if (likely(key_dma_addr != 0)) | 544 | if (likely(key_dma_addr != 0)) |
| 540 | dma_unmap_single(dev, key_dma_addr, keylen, DMA_TO_DEVICE); | 545 | dma_unmap_single(dev, key_dma_addr, keylen, DMA_TO_DEVICE); |
| @@ -551,10 +556,10 @@ ssi_aead_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) · 10 unmodified lines | |||
| 551 | struct crypto_authenc_key_param *param; | 556 | struct crypto_authenc_key_param *param; |
| 552 | struct cc_hw_desc desc[MAX_AEAD_SETKEY_SEQ]; | 557 | struct cc_hw_desc desc[MAX_AEAD_SETKEY_SEQ]; |
| 553 | int seq_len = 0, rc = -EINVAL; | 558 | int seq_len = 0, rc = -EINVAL; |
| 559 | struct device *dev = drvdata_to_dev(ctx->drvdata); | ||
| 554 | 560 | ||
| 555 | SSI_LOG_DEBUG("Setting key in context @%p for %s. key=%p keylen=%u\n", | 561 | dev_dbg(dev, "Setting key in context @%p for %s. key=%p keylen=%u\n", |
| 556 | ctx, crypto_tfm_alg_name(crypto_aead_tfm(tfm)), | 562 | ctx, crypto_tfm_alg_name(crypto_aead_tfm(tfm)), key, keylen); |
| 557 | key, keylen); | ||
| 558 | 563 | ||
| 559 | /* STAT_PHASE_0: Init and sanity checks */ | 564 | /* STAT_PHASE_0: Init and sanity checks */ |
| 560 | 565 | ||
| @@ -622,7 +627,7 @@ ssi_aead_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) · 61 unmodified lines | |||
| 622 | case DRV_HASH_NULL: /* non-authenc modes, e.g., CCM */ | 627 | case DRV_HASH_NULL: /* non-authenc modes, e.g., CCM */ |
| 623 | break; /* No auth. key setup */ | 628 | break; /* No auth. key setup */ |
| 624 | default: | 629 | default: |
| 625 | SSI_LOG_ERR("Unsupported authenc (%d)\n", ctx->auth_mode); | 630 | dev_err(dev, "Unsupported authenc (%d)\n", ctx->auth_mode); |
| 626 | rc = -ENOTSUPP; | 631 | rc = -ENOTSUPP; |
| 627 | goto badkey; | 632 | goto badkey; |
| 628 | } | 633 | } |
| @@ -632,7 +637,7 @@ ssi_aead_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) · 3 unmodified lines | |||
| 632 | if (seq_len > 0) { /* For CCM there is no sequence to setup the key */ | 637 | if (seq_len > 0) { /* For CCM there is no sequence to setup the key */ |
| 633 | rc = send_request(ctx->drvdata, &ssi_req, desc, seq_len, 0); | 638 | rc = send_request(ctx->drvdata, &ssi_req, desc, seq_len, 0); |
| 634 | if (unlikely(rc != 0)) { | 639 | if (unlikely(rc != 0)) { |
| 635 | SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc); | 640 | dev_err(dev, "send_request() failed (rc=%d)\n", rc); |
| 636 | goto setkey_error; | 641 | goto setkey_error; |
| 637 | } | 642 | } |
| 638 | } | 643 | } |
| @@ -651,7 +656,6 @@ setkey_error: · 12 unmodified lines | |||
| 651 | static int ssi_rfc4309_ccm_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) | 656 | static int ssi_rfc4309_ccm_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) |
| 652 | { | 657 | { |
| 653 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); | 658 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); |
| 654 | int rc = 0; | ||
| 655 | 659 | ||
| 656 | if (keylen < 3) | 660 | if (keylen < 3) |
| 657 | return -EINVAL; | 661 | return -EINVAL; |
| @@ -659,9 +663,7 @@ static int ssi_rfc4309_ccm_setkey(struct crypto_aead *tfm, const u8 *key, unsign · 1 unmodified line | |||
| 659 | keylen -= 3; | 663 | keylen -= 3; |
| 660 | memcpy(ctx->ctr_nonce, key + keylen, 3); | 664 | memcpy(ctx->ctr_nonce, key + keylen, 3); |
| 661 | 665 | ||
| 662 | rc = ssi_aead_setkey(tfm, key, keylen); | 666 | return ssi_aead_setkey(tfm, key, keylen); |
| 663 | |||
| 664 | return rc; | ||
| 665 | } | 667 | } |
| 666 | #endif /*SSI_CC_HAS_AES_CCM*/ | 668 | #endif /*SSI_CC_HAS_AES_CCM*/ |
| 667 | 669 | ||
| @@ -670,6 +672,7 @@ static int ssi_aead_setauthsize( · 2 unmodified lines | |||
| 670 | unsigned int authsize) | 672 | unsigned int authsize) |
| 671 | { | 673 | { |
| 672 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(authenc); | 674 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(authenc); |
| 675 | struct device *dev = drvdata_to_dev(ctx->drvdata); | ||
| 673 | 676 | ||
| 674 | /* Unsupported auth. sizes */ | 677 | /* Unsupported auth. sizes */ |
| 675 | if ((authsize == 0) || | 678 | if ((authsize == 0) || |
| @@ -678,7 +681,7 @@ static int ssi_aead_setauthsize( · 2 unmodified lines | |||
| 678 | } | 681 | } |
| 679 | 682 | ||
| 680 | ctx->authsize = authsize; | 683 | ctx->authsize = authsize; |
| 681 | SSI_LOG_DEBUG("authlen=%d\n", ctx->authsize); | 684 | dev_dbg(dev, "authlen=%d\n", ctx->authsize); |
| 682 | 685 | ||
| 683 | return 0; | 686 | return 0; |
| 684 | } | 687 | } |
| @@ -731,10 +734,11 @@ ssi_aead_create_assoc_desc( · 46 unmodified lines | |||
| 731 | struct aead_req_ctx *areq_ctx = aead_request_ctx(areq); | 734 | struct aead_req_ctx *areq_ctx = aead_request_ctx(areq); |
| 732 | enum ssi_req_dma_buf_type assoc_dma_type = areq_ctx->assoc_buff_type; | 735 | enum ssi_req_dma_buf_type assoc_dma_type = areq_ctx->assoc_buff_type; |
| 733 | unsigned int idx = *seq_size; | 736 | unsigned int idx = *seq_size; |
| 737 | struct device *dev = drvdata_to_dev(ctx->drvdata); | ||
| 734 | 738 | ||
| 735 | switch (assoc_dma_type) { | 739 | switch (assoc_dma_type) { |
| 736 | case SSI_DMA_BUF_DLLI: | 740 | case SSI_DMA_BUF_DLLI: |
| 737 | SSI_LOG_DEBUG("ASSOC buffer type DLLI\n"); | 741 | dev_dbg(dev, "ASSOC buffer type DLLI\n"); |
| 738 | hw_desc_init(&desc[idx]); | 742 | hw_desc_init(&desc[idx]); |
| 739 | set_din_type(&desc[idx], DMA_DLLI, sg_dma_address(areq->src), | 743 | set_din_type(&desc[idx], DMA_DLLI, sg_dma_address(areq->src), |
| 740 | areq->assoclen, NS_BIT); set_flow_mode(&desc[idx], | 744 | areq->assoclen, NS_BIT); set_flow_mode(&desc[idx], |
| @@ -744,7 +748,7 @@ ssi_aead_create_assoc_desc( · 3 unmodified lines | |||
| 744 | set_din_not_last_indication(&desc[idx]); | 748 | set_din_not_last_indication(&desc[idx]); |
| 745 | break; | 749 | break; |
| 746 | case SSI_DMA_BUF_MLLI: | 750 | case SSI_DMA_BUF_MLLI: |
| 747 | SSI_LOG_DEBUG("ASSOC buffer type MLLI\n"); | 751 | dev_dbg(dev, "ASSOC buffer type MLLI\n"); |
| 748 | hw_desc_init(&desc[idx]); | 752 | hw_desc_init(&desc[idx]); |
| 749 | set_din_type(&desc[idx], DMA_MLLI, areq_ctx->assoc.sram_addr, | 753 | set_din_type(&desc[idx], DMA_MLLI, areq_ctx->assoc.sram_addr, |
| 750 | areq_ctx->assoc.mlli_nents, NS_BIT); | 754 | areq_ctx->assoc.mlli_nents, NS_BIT); |
| @@ -755,7 +759,7 @@ ssi_aead_create_assoc_desc( · 4 unmodified lines | |||
| 755 | break; | 759 | break; |
| 756 | case SSI_DMA_BUF_NULL: | 760 | case SSI_DMA_BUF_NULL: |
| 757 | default: | 761 | default: |
| 758 | SSI_LOG_ERR("Invalid ASSOC buffer type\n"); | 762 | dev_err(dev, "Invalid ASSOC buffer type\n"); |
| 759 | } | 763 | } |
| 760 | 764 | ||
| 761 | *seq_size = (++idx); | 765 | *seq_size = (++idx); |
| @@ -772,6 +776,9 @@ ssi_aead_process_authenc_data_desc( · 10 unmodified lines | |||
| 772 | struct aead_req_ctx *areq_ctx = aead_request_ctx(areq); | 776 | struct aead_req_ctx *areq_ctx = aead_request_ctx(areq); |
| 773 | enum ssi_req_dma_buf_type data_dma_type = areq_ctx->data_buff_type; | 777 | enum ssi_req_dma_buf_type data_dma_type = areq_ctx->data_buff_type; |
| 774 | unsigned int idx = *seq_size; | 778 | unsigned int idx = *seq_size; |
| 779 | struct crypto_aead *tfm = crypto_aead_reqtfm(areq); | ||
| 780 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); | ||
| 781 | struct device *dev = drvdata_to_dev(ctx->drvdata); | ||
| 775 | 782 | ||
| 776 | switch (data_dma_type) { | 783 | switch (data_dma_type) { |
| 777 | case SSI_DMA_BUF_DLLI: | 784 | case SSI_DMA_BUF_DLLI: |
| @@ -783,7 +790,7 @@ ssi_aead_process_authenc_data_desc( · 5 unmodified lines | |||
| 783 | unsigned int offset = | 790 | unsigned int offset = |
| 784 | (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ? | 791 | (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ? |
| 785 | areq_ctx->dst_offset : areq_ctx->src_offset; | 792 | areq_ctx->dst_offset : areq_ctx->src_offset; |
| 786 | SSI_LOG_DEBUG("AUTHENC: SRC/DST buffer type DLLI\n"); | 793 | dev_dbg(dev, "AUTHENC: SRC/DST buffer type DLLI\n"); |
| 787 | hw_desc_init(&desc[idx]); | 794 | hw_desc_init(&desc[idx]); |
| 788 | set_din_type(&desc[idx], DMA_DLLI, | 795 | set_din_type(&desc[idx], DMA_DLLI, |
| 789 | (sg_dma_address(cipher) + offset), | 796 | (sg_dma_address(cipher) + offset), |
| @@ -810,7 +817,7 @@ ssi_aead_process_authenc_data_desc( · 20 unmodified lines | |||
| 810 | } | 817 | } |
| 811 | } | 818 | } |
| 812 | 819 | ||
| 813 | SSI_LOG_DEBUG("AUTHENC: SRC/DST buffer type MLLI\n"); | 820 | dev_dbg(dev, "AUTHENC: SRC/DST buffer type MLLI\n"); |
| 814 | hw_desc_init(&desc[idx]); | 821 | hw_desc_init(&desc[idx]); |
| 815 | set_din_type(&desc[idx], DMA_MLLI, mlli_addr, mlli_nents, | 822 | set_din_type(&desc[idx], DMA_MLLI, mlli_addr, mlli_nents, |
| 816 | NS_BIT); | 823 | NS_BIT); |
| @@ -819,7 +826,7 @@ ssi_aead_process_authenc_data_desc( · 2 unmodified lines | |||
| 819 | } | 826 | } |
| 820 | case SSI_DMA_BUF_NULL: | 827 | case SSI_DMA_BUF_NULL: |
| 821 | default: | 828 | default: |
| 822 | SSI_LOG_ERR("AUTHENC: Invalid SRC/DST buffer type\n"); | 829 | dev_err(dev, "AUTHENC: Invalid SRC/DST buffer type\n"); |
| 823 | } | 830 | } |
| 824 | 831 | ||
| 825 | *seq_size = (++idx); | 832 | *seq_size = (++idx); |
| @@ -835,13 +842,16 @@ ssi_aead_process_cipher_data_desc( · 9 unmodified lines | |||
| 835 | unsigned int idx = *seq_size; | 842 | unsigned int idx = *seq_size; |
| 836 | struct aead_req_ctx *areq_ctx = aead_request_ctx(areq); | 843 | struct aead_req_ctx *areq_ctx = aead_request_ctx(areq); |
| 837 | enum ssi_req_dma_buf_type data_dma_type = areq_ctx->data_buff_type; | 844 | enum ssi_req_dma_buf_type data_dma_type = areq_ctx->data_buff_type; |
| 845 | struct crypto_aead *tfm = crypto_aead_reqtfm(areq); | ||
| 846 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); | ||
| 847 | struct device *dev = drvdata_to_dev(ctx->drvdata); | ||
| 838 | 848 | ||
| 839 | if (areq_ctx->cryptlen == 0) | 849 | if (areq_ctx->cryptlen == 0) |
| 840 | return; /*null processing*/ | 850 | return; /*null processing*/ |
| 841 | 851 | ||
| 842 | switch (data_dma_type) { | 852 | switch (data_dma_type) { |
| 843 | case SSI_DMA_BUF_DLLI: | 853 | case SSI_DMA_BUF_DLLI: |
| 844 | SSI_LOG_DEBUG("CIPHER: SRC/DST buffer type DLLI\n"); | 854 | dev_dbg(dev, "CIPHER: SRC/DST buffer type DLLI\n"); |
| 845 | hw_desc_init(&desc[idx]); | 855 | hw_desc_init(&desc[idx]); |
| 846 | set_din_type(&desc[idx], DMA_DLLI, | 856 | set_din_type(&desc[idx], DMA_DLLI, |
| 847 | (sg_dma_address(areq_ctx->src_sgl) + | 857 | (sg_dma_address(areq_ctx->src_sgl) + |
| @@ -853,7 +863,7 @@ ssi_aead_process_cipher_data_desc( · 5 unmodified lines | |||
| 853 | set_flow_mode(&desc[idx], flow_mode); | 863 | set_flow_mode(&desc[idx], flow_mode); |
| 854 | break; | 864 | break; |
| 855 | case SSI_DMA_BUF_MLLI: | 865 | case SSI_DMA_BUF_MLLI: |
| 856 | SSI_LOG_DEBUG("CIPHER: SRC/DST buffer type MLLI\n"); | 866 | dev_dbg(dev, "CIPHER: SRC/DST buffer type MLLI\n"); |
| 857 | hw_desc_init(&desc[idx]); | 867 | hw_desc_init(&desc[idx]); |
| 858 | set_din_type(&desc[idx], DMA_MLLI, areq_ctx->src.sram_addr, | 868 | set_din_type(&desc[idx], DMA_MLLI, areq_ctx->src.sram_addr, |
| 859 | areq_ctx->src.mlli_nents, NS_BIT); | 869 | areq_ctx->src.mlli_nents, NS_BIT); |
| @@ -863,7 +873,7 @@ ssi_aead_process_cipher_data_desc( · 3 unmodified lines | |||
| 863 | break; | 873 | break; |
| 864 | case SSI_DMA_BUF_NULL: | 874 | case SSI_DMA_BUF_NULL: |
| 865 | default: | 875 | default: |
| 866 | SSI_LOG_ERR("CIPHER: Invalid SRC/DST buffer type\n"); | 876 | dev_err(dev, "CIPHER: Invalid SRC/DST buffer type\n"); |
| 867 | } | 877 | } |
| 868 | 878 | ||
| 869 | *seq_size = (++idx); | 879 | *seq_size = (++idx); |
| @@ -1178,14 +1188,15 @@ static inline void ssi_aead_load_mlli_to_sram( · 308 unmodified lines | |||
| 1178 | struct aead_req_ctx *req_ctx = aead_request_ctx(req); | 1188 | struct aead_req_ctx *req_ctx = aead_request_ctx(req); |
| 1179 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); | 1189 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); |
| 1180 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); | 1190 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); |
| 1191 | struct device *dev = drvdata_to_dev(ctx->drvdata); | ||
| 1181 | 1192 | ||
| 1182 | if (unlikely( | 1193 | if (unlikely( |
| 1183 | (req_ctx->assoc_buff_type == SSI_DMA_BUF_MLLI) || | 1194 | (req_ctx->assoc_buff_type == SSI_DMA_BUF_MLLI) || |
| 1184 | (req_ctx->data_buff_type == SSI_DMA_BUF_MLLI) || | 1195 | (req_ctx->data_buff_type == SSI_DMA_BUF_MLLI) || |
| 1185 | !req_ctx->is_single_pass)) { | 1196 | !req_ctx->is_single_pass)) { |
| 1186 | SSI_LOG_DEBUG("Copy-to-sram: mlli_dma=%08x, mlli_size=%u\n", | 1197 | dev_dbg(dev, "Copy-to-sram: mlli_dma=%08x, mlli_size=%u\n", |
| 1187 | (unsigned int)ctx->drvdata->mlli_sram_addr, | 1198 | (unsigned int)ctx->drvdata->mlli_sram_addr, |
| 1188 | req_ctx->mlli_params.mlli_len); | 1199 | req_ctx->mlli_params.mlli_len); |
| 1189 | /* Copy MLLI table host-to-sram */ | 1200 | /* Copy MLLI table host-to-sram */ |
| 1190 | hw_desc_init(&desc[*seq_size]); | 1201 | hw_desc_init(&desc[*seq_size]); |
| 1191 | set_din_type(&desc[*seq_size], DMA_DLLI, | 1202 | set_din_type(&desc[*seq_size], DMA_DLLI, |
| @@ -1333,6 +1344,7 @@ static int validate_data_size(struct ssi_aead_ctx *ctx, · 141 unmodified lines | |||
| 1333 | struct aead_request *req) | 1344 | struct aead_request *req) |
| 1334 | { | 1345 | { |
| 1335 | struct aead_req_ctx *areq_ctx = aead_request_ctx(req); | 1346 | struct aead_req_ctx *areq_ctx = aead_request_ctx(req); |
| 1347 | struct device *dev = drvdata_to_dev(ctx->drvdata); | ||
| 1336 | unsigned int assoclen = req->assoclen; | 1348 | unsigned int assoclen = req->assoclen; |
| 1337 | unsigned int cipherlen = (direct == DRV_CRYPTO_DIRECTION_DECRYPT) ? | 1349 | unsigned int cipherlen = (direct == DRV_CRYPTO_DIRECTION_DECRYPT) ? |
| 1338 | (req->cryptlen - ctx->authsize) : req->cryptlen; | 1350 | (req->cryptlen - ctx->authsize) : req->cryptlen; |
| @@ -1371,7 +1383,7 @@ static int validate_data_size(struct ssi_aead_ctx *ctx, · 32 unmodified lines | |||
| 1371 | areq_ctx->is_single_pass = false; | 1383 | areq_ctx->is_single_pass = false; |
| 1372 | break; | 1384 | break; |
| 1373 | default: | 1385 | default: |
| 1374 | SSI_LOG_ERR("Unexpected flow mode (%d)\n", ctx->flow_mode); | 1386 | dev_err(dev, "Unexpected flow mode (%d)\n", ctx->flow_mode); |
| 1375 | goto data_size_err; | 1387 | goto data_size_err; |
| 1376 | } | 1388 | } |
| 1377 | 1389 | ||
| @@ -1554,6 +1566,7 @@ static int config_ccm_adata(struct aead_request *req) · 176 unmodified lines | |||
| 1554 | { | 1566 | { |
| 1555 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); | 1567 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); |
| 1556 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); | 1568 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); |
| 1569 | struct device *dev = drvdata_to_dev(ctx->drvdata); | ||
| 1557 | struct aead_req_ctx *req_ctx = aead_request_ctx(req); | 1570 | struct aead_req_ctx *req_ctx = aead_request_ctx(req); |
| 1558 | //unsigned int size_of_a = 0, rem_a_size = 0; | 1571 | //unsigned int size_of_a = 0, rem_a_size = 0; |
| 1559 | unsigned int lp = req->iv[0]; | 1572 | unsigned int lp = req->iv[0]; |
| @@ -1575,7 +1588,7 @@ static int config_ccm_adata(struct aead_request *req) · 15 unmodified lines | |||
| 1575 | /* taken from crypto/ccm.c */ | 1588 | /* taken from crypto/ccm.c */ |
| 1576 | /* 2 <= L <= 8, so 1 <= L' <= 7. */ | 1589 | /* 2 <= L <= 8, so 1 <= L' <= 7. */ |
| 1577 | if (l < 2 || l > 8) { | 1590 | if (l < 2 || l > 8) { |
| 1578 | SSI_LOG_ERR("illegal iv value %X\n", req->iv[0]); | 1591 | dev_err(dev, "illegal iv value %X\n", req->iv[0]); |
| 1579 | return -EINVAL; | 1592 | return -EINVAL; |
| 1580 | } | 1593 | } |
| 1581 | memcpy(b0, req->iv, AES_BLOCK_SIZE); | 1594 | memcpy(b0, req->iv, AES_BLOCK_SIZE); |
| @@ -1588,8 +1601,10 @@ static int config_ccm_adata(struct aead_request *req) · 6 unmodified lines | |||
| 1588 | *b0 |= 64; /* Enable bit 6 if Adata exists. */ | 1601 | *b0 |= 64; /* Enable bit 6 if Adata exists. */ |
| 1589 | 1602 | ||
| 1590 | rc = set_msg_len(b0 + 16 - l, cryptlen, l); /* Write L'. */ | 1603 | rc = set_msg_len(b0 + 16 - l, cryptlen, l); /* Write L'. */ |
| 1591 | if (rc != 0) | 1604 | if (rc != 0) { |
| 1605 | dev_err(dev, "message len overflow detected"); | ||
| 1592 | return rc; | 1606 | return rc; |
| 1607 | } | ||
| 1593 | /* END of "taken from crypto/ccm.c" */ | 1608 | /* END of "taken from crypto/ccm.c" */ |
| 1594 | 1609 | ||
| 1595 | /* l(a) - size of associated data. */ | 1610 | /* l(a) - size of associated data. */ |
| @@ -1812,7 +1827,6 @@ static inline int ssi_aead_gcm( · 216 unmodified lines | |||
| 1812 | unsigned int *seq_size) | 1827 | unsigned int *seq_size) |
| 1813 | { | 1828 | { |
| 1814 | struct aead_req_ctx *req_ctx = aead_request_ctx(req); | 1829 | struct aead_req_ctx *req_ctx = aead_request_ctx(req); |
| 1815 | unsigned int idx = *seq_size; | ||
| 1816 | unsigned int cipher_flow_mode; | 1830 | unsigned int cipher_flow_mode; |
| 1817 | 1831 | ||
| 1818 | if (req_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) { | 1832 | if (req_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) { |
| @@ -1829,7 +1843,6 @@ static inline int ssi_aead_gcm( · 10 unmodified lines | |||
| 1829 | ssi_aead_create_assoc_desc(req, DIN_HASH, desc, seq_size); | 1843 | ssi_aead_create_assoc_desc(req, DIN_HASH, desc, seq_size); |
| 1830 | ssi_aead_gcm_setup_gctr_desc(req, desc, seq_size); | 1844 | ssi_aead_gcm_setup_gctr_desc(req, desc, seq_size); |
| 1831 | ssi_aead_process_gcm_result_desc(req, desc, seq_size); | 1845 | ssi_aead_process_gcm_result_desc(req, desc, seq_size); |
| 1832 | idx = *seq_size; | ||
| 1833 | return 0; | 1846 | return 0; |
| 1834 | } | 1847 | } |
| 1835 | 1848 | ||
| @@ -1844,7 +1857,6 @@ static inline int ssi_aead_gcm( · 8 unmodified lines | |||
| 1844 | ssi_aead_process_cipher_data_desc(req, cipher_flow_mode, desc, seq_size); | 1857 | ssi_aead_process_cipher_data_desc(req, cipher_flow_mode, desc, seq_size); |
| 1845 | ssi_aead_process_gcm_result_desc(req, desc, seq_size); | 1858 | ssi_aead_process_gcm_result_desc(req, desc, seq_size); |
| 1846 | 1859 | ||
| 1847 | idx = *seq_size; | ||
| 1848 | return 0; | 1860 | return 0; |
| 1849 | } | 1861 | } |
| 1850 | 1862 | ||
| @@ -1861,13 +1873,13 @@ static inline void ssi_aead_dump_gcm( · 10 unmodified lines | |||
| 1861 | return; | 1873 | return; |
| 1862 | 1874 | ||
| 1863 | if (title) { | 1875 | if (title) { |
| 1864 | SSI_LOG_DEBUG("----------------------------------------------------------------------------------"); | 1876 | dev_dbg(dev, "----------------------------------------------------------------------------------"); |
| 1865 | SSI_LOG_DEBUG("%s\n", title); | 1877 | dev_dbg(dev, "%s\n", title); |
| 1866 | } | 1878 | } |
| 1867 | 1879 | ||
| 1868 | SSI_LOG_DEBUG("cipher_mode %d, authsize %d, enc_keylen %d, assoclen %d, cryptlen %d\n", | 1880 | dev_dbg(dev, "cipher_mode %d, authsize %d, enc_keylen %d, assoclen %d, cryptlen %d\n", |
| 1869 | ctx->cipher_mode, ctx->authsize, ctx->enc_keylen, | 1881 | ctx->cipher_mode, ctx->authsize, ctx->enc_keylen, |
| 1870 | req->assoclen, req_ctx->cryptlen); | 1882 | req->assoclen, req_ctx->cryptlen); |
| 1871 | 1883 | ||
| 1872 | if (ctx->enckey) | 1884 | if (ctx->enckey) |
| 1873 | dump_byte_array("mac key", ctx->enckey, 16); | 1885 | dump_byte_array("mac key", ctx->enckey, 16); |
| @@ -1897,6 +1909,7 @@ static int config_gcm_context(struct aead_request *req) · 23 unmodified lines | |||
| 1897 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); | 1909 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); |
| 1898 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); | 1910 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); |
| 1899 | struct aead_req_ctx *req_ctx = aead_request_ctx(req); | 1911 | struct aead_req_ctx *req_ctx = aead_request_ctx(req); |
| 1912 | struct device *dev = drvdata_to_dev(ctx->drvdata); | ||
| 1900 | 1913 | ||
| 1901 | unsigned int cryptlen = (req_ctx->gen_ctx.op_type == | 1914 | unsigned int cryptlen = (req_ctx->gen_ctx.op_type == |
| 1902 | DRV_CRYPTO_DIRECTION_ENCRYPT) ? | 1915 | DRV_CRYPTO_DIRECTION_ENCRYPT) ? |
| @@ -1904,7 +1917,8 @@ static int config_gcm_context(struct aead_request *req) · 1 unmodified line | |||
| 1904 | (req->cryptlen - ctx->authsize); | 1917 | (req->cryptlen - ctx->authsize); |
| 1905 | __be32 counter = cpu_to_be32(2); | 1918 | __be32 counter = cpu_to_be32(2); |
| 1906 | 1919 | ||
| 1907 | SSI_LOG_DEBUG("%s() cryptlen = %d, req->assoclen = %d ctx->authsize = %d\n", __func__, cryptlen, req->assoclen, ctx->authsize); | 1920 | dev_dbg(dev, "%s() cryptlen = %d, req->assoclen = %d ctx->authsize = %d\n", |
| 1921 | __func__, cryptlen, req->assoclen, ctx->authsize); | ||
| 1908 | 1922 | ||
| 1909 | memset(req_ctx->hkey, 0, AES_BLOCK_SIZE); | 1923 | memset(req_ctx->hkey, 0, AES_BLOCK_SIZE); |
| 1910 | 1924 | ||
| @@ -1958,20 +1972,20 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction · 47 unmodified lines | |||
| 1958 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); | 1972 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); |
| 1959 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); | 1973 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); |
| 1960 | struct aead_req_ctx *areq_ctx = aead_request_ctx(req); | 1974 | struct aead_req_ctx *areq_ctx = aead_request_ctx(req); |
| 1961 | struct device *dev = &ctx->drvdata->plat_dev->dev; | 1975 | struct device *dev = drvdata_to_dev(ctx->drvdata); |
| 1962 | struct ssi_crypto_req ssi_req = {}; | 1976 | struct ssi_crypto_req ssi_req = {}; |
| 1963 | 1977 | ||
| 1964 | SSI_LOG_DEBUG("%s context=%p req=%p iv=%p src=%p src_ofs=%d dst=%p dst_ofs=%d cryptolen=%d\n", | 1978 | dev_dbg(dev, "%s context=%p req=%p iv=%p src=%p src_ofs=%d dst=%p dst_ofs=%d cryptolen=%d\n", |
| 1965 | ((direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ? "Encrypt" : "Decrypt"), | 1979 | ((direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ? "Enc" : "Dec"), |
| 1966 | ctx, req, req->iv, sg_virt(req->src), req->src->offset, | 1980 | ctx, req, req->iv, sg_virt(req->src), req->src->offset, |
| 1967 | sg_virt(req->dst), req->dst->offset, req->cryptlen); | 1981 | sg_virt(req->dst), req->dst->offset, req->cryptlen); |
| 1968 | 1982 | ||
| 1969 | /* STAT_PHASE_0: Init and sanity checks */ | 1983 | /* STAT_PHASE_0: Init and sanity checks */ |
| 1970 | 1984 | ||
| 1971 | /* Check data length according to mode */ | 1985 | /* Check data length according to mode */ |
| 1972 | if (unlikely(validate_data_size(ctx, direct, req) != 0)) { | 1986 | if (unlikely(validate_data_size(ctx, direct, req) != 0)) { |
| 1973 | SSI_LOG_ERR("Unsupported crypt/assoc len %d/%d.\n", | 1987 | dev_err(dev, "Unsupported crypt/assoc len %d/%d.\n", |
| 1974 | req->cryptlen, req->assoclen); | 1988 | req->cryptlen, req->assoclen); |
| 1975 | crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_BLOCK_LEN); | 1989 | crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_BLOCK_LEN); |
| 1976 | return -EINVAL; | 1990 | return -EINVAL; |
| 1977 | } | 1991 | } |
| @@ -2017,7 +2031,8 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction · 39 unmodified lines | |||
| 2017 | if (ctx->cipher_mode == DRV_CIPHER_CCM) { | 2031 | if (ctx->cipher_mode == DRV_CIPHER_CCM) { |
| 2018 | rc = config_ccm_adata(req); | 2032 | rc = config_ccm_adata(req); |
| 2019 | if (unlikely(rc != 0)) { | 2033 | if (unlikely(rc != 0)) { |
| 2020 | SSI_LOG_ERR("config_ccm_adata() returned with a failure %d!", rc); | 2034 | dev_dbg(dev, "config_ccm_adata() returned with a failure %d!", |
| 2035 | rc); | ||
| 2021 | goto exit; | 2036 | goto exit; |
| 2022 | } | 2037 | } |
| 2023 | } else { | 2038 | } else { |
| @@ -2031,7 +2046,8 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction · 7 unmodified lines | |||
| 2031 | if (ctx->cipher_mode == DRV_CIPHER_GCTR) { | 2046 | if (ctx->cipher_mode == DRV_CIPHER_GCTR) { |
| 2032 | rc = config_gcm_context(req); | 2047 | rc = config_gcm_context(req); |
| 2033 | if (unlikely(rc != 0)) { | 2048 | if (unlikely(rc != 0)) { |
| 2034 | SSI_LOG_ERR("config_gcm_context() returned with a failure %d!", rc); | 2049 | dev_dbg(dev, "config_gcm_context() returned with a failure %d!", |
| 2050 | rc); | ||
| 2035 | goto exit; | 2051 | goto exit; |
| 2036 | } | 2052 | } |
| 2037 | } | 2053 | } |
| @@ -2039,7 +2055,7 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction · 1 unmodified line | |||
| 2039 | 2055 | ||
| 2040 | rc = ssi_buffer_mgr_map_aead_request(ctx->drvdata, req); | 2056 | rc = ssi_buffer_mgr_map_aead_request(ctx->drvdata, req); |
| 2041 | if (unlikely(rc != 0)) { | 2057 | if (unlikely(rc != 0)) { |
| 2042 | SSI_LOG_ERR("map_request() failed\n"); | 2058 | dev_err(dev, "map_request() failed\n"); |
| 2043 | goto exit; | 2059 | goto exit; |
| 2044 | } | 2060 | } |
| 2045 | 2061 | ||
| @@ -2095,7 +2111,7 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction · 49 unmodified lines | |||
| 2095 | break; | 2111 | break; |
| 2096 | #endif | 2112 | #endif |
| 2097 | default: | 2113 | default: |
| 2098 | SSI_LOG_ERR("Unsupported authenc (%d)\n", ctx->auth_mode); | 2114 | dev_err(dev, "Unsupported authenc (%d)\n", ctx->auth_mode); |
| 2099 | ssi_buffer_mgr_unmap_aead_request(dev, req); | 2115 | ssi_buffer_mgr_unmap_aead_request(dev, req); |
| 2100 | rc = -ENOTSUPP; | 2116 | rc = -ENOTSUPP; |
| 2101 | goto exit; | 2117 | goto exit; |
| @@ -2106,7 +2122,7 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction · 4 unmodified lines | |||
| 2106 | rc = send_request(ctx->drvdata, &ssi_req, desc, seq_len, 1); | 2122 | rc = send_request(ctx->drvdata, &ssi_req, desc, seq_len, 1); |
| 2107 | 2123 | ||
| 2108 | if (unlikely(rc != -EINPROGRESS)) { | 2124 | if (unlikely(rc != -EINPROGRESS)) { |
| 2109 | SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc); | 2125 | dev_err(dev, "send_request() failed (rc=%d)\n", rc); |
| 2110 | ssi_buffer_mgr_unmap_aead_request(dev, req); | 2126 | ssi_buffer_mgr_unmap_aead_request(dev, req); |
| 2111 | } | 2127 | } |
| 2112 | 2128 | ||
| @@ -2139,10 +2155,13 @@ static int ssi_rfc4309_ccm_encrypt(struct aead_request *req) · 26 unmodified lines | |||
| 2139 | /* Very similar to ssi_aead_encrypt() above. */ | 2155 | /* Very similar to ssi_aead_encrypt() above. */ |
| 2140 | 2156 | ||
| 2141 | struct aead_req_ctx *areq_ctx = aead_request_ctx(req); | 2157 | struct aead_req_ctx *areq_ctx = aead_request_ctx(req); |
| 2158 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); | ||
| 2159 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); | ||
| 2160 | struct device *dev = drvdata_to_dev(ctx->drvdata); | ||
| 2142 | int rc = -EINVAL; | 2161 | int rc = -EINVAL; |
| 2143 | 2162 | ||
| 2144 | if (!valid_assoclen(req)) { | 2163 | if (!valid_assoclen(req)) { |
| 2145 | SSI_LOG_ERR("invalid Assoclen:%u\n", req->assoclen); | 2164 | dev_err(dev, "invalid Assoclen:%u\n", req->assoclen); |
| 2146 | goto out; | 2165 | goto out; |
| 2147 | } | 2166 | } |
| 2148 | 2167 | ||
| @@ -2183,13 +2202,14 @@ static int ssi_aead_decrypt(struct aead_request *req) · 34 unmodified lines | |||
| 2183 | #if SSI_CC_HAS_AES_CCM | 2202 | #if SSI_CC_HAS_AES_CCM |
| 2184 | static int ssi_rfc4309_ccm_decrypt(struct aead_request *req) | 2203 | static int ssi_rfc4309_ccm_decrypt(struct aead_request *req) |
| 2185 | { | 2204 | { |
| 2186 | /* Very similar to ssi_aead_decrypt() above. */ | 2205 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); |
| 2187 | 2206 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); | |
| 2207 | struct device *dev = drvdata_to_dev(ctx->drvdata); | ||
| 2188 | struct aead_req_ctx *areq_ctx = aead_request_ctx(req); | 2208 | struct aead_req_ctx *areq_ctx = aead_request_ctx(req); |
| 2189 | int rc = -EINVAL; | 2209 | int rc = -EINVAL; |
| 2190 | 2210 | ||
| 2191 | if (!valid_assoclen(req)) { | 2211 | if (!valid_assoclen(req)) { |
| 2192 | SSI_LOG_ERR("invalid Assoclen:%u\n", req->assoclen); | 2212 | dev_err(dev, "invalid Assoclen:%u\n", req->assoclen); |
| 2193 | goto out; | 2213 | goto out; |
| 2194 | } | 2214 | } |
| 2195 | 2215 | ||
| @@ -2214,9 +2234,9 @@ out: · 18 unmodified lines | |||
| 2214 | static int ssi_rfc4106_gcm_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) | 2234 | static int ssi_rfc4106_gcm_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) |
| 2215 | { | 2235 | { |
| 2216 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); | 2236 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); |
| 2217 | int rc = 0; | 2237 | struct device *dev = drvdata_to_dev(ctx->drvdata); |
| 2218 | 2238 | ||
| 2219 | SSI_LOG_DEBUG("%s() keylen %d, key %p\n", __func__, keylen, key); | 2239 | dev_dbg(dev, "%s() keylen %d, key %p\n", __func__, keylen, key); |
| 2220 | 2240 | ||
| 2221 | if (keylen < 4) | 2241 | if (keylen < 4) |
| 2222 | return -EINVAL; | 2242 | return -EINVAL; |
| @@ -2224,17 +2244,15 @@ static int ssi_rfc4106_gcm_setkey(struct crypto_aead *tfm, const u8 *key, unsign · 1 unmodified line | |||
| 2224 | keylen -= 4; | 2244 | keylen -= 4; |
| 2225 | memcpy(ctx->ctr_nonce, key + keylen, 4); | 2245 | memcpy(ctx->ctr_nonce, key + keylen, 4); |
| 2226 | 2246 | ||
| 2227 | rc = ssi_aead_setkey(tfm, key, keylen); | 2247 | return ssi_aead_setkey(tfm, key, keylen); |
| 2228 | |||
| 2229 | return rc; | ||
| 2230 | } | 2248 | } |
| 2231 | 2249 | ||
| 2232 | static int ssi_rfc4543_gcm_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) | 2250 | static int ssi_rfc4543_gcm_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) |
| 2233 | { | 2251 | { |
| 2234 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); | 2252 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); |
| 2235 | int rc = 0; | 2253 | struct device *dev = drvdata_to_dev(ctx->drvdata); |
| 2236 | 2254 | ||
| 2237 | SSI_LOG_DEBUG("%s() keylen %d, key %p\n", __func__, keylen, key); | 2255 | dev_dbg(dev, "%s() keylen %d, key %p\n", __func__, keylen, key); |
| 2238 | 2256 | ||
| 2239 | if (keylen < 4) | 2257 | if (keylen < 4) |
| 2240 | return -EINVAL; | 2258 | return -EINVAL; |
| @@ -2242,9 +2260,7 @@ static int ssi_rfc4543_gcm_setkey(struct crypto_aead *tfm, const u8 *key, unsign · 1 unmodified line | |||
| 2242 | keylen -= 4; | 2260 | keylen -= 4; |
| 2243 | memcpy(ctx->ctr_nonce, key + keylen, 4); | 2261 | memcpy(ctx->ctr_nonce, key + keylen, 4); |
| 2244 | 2262 | ||
| 2245 | rc = ssi_aead_setkey(tfm, key, keylen); | 2263 | return ssi_aead_setkey(tfm, key, keylen); |
| 2246 | |||
| 2247 | return rc; | ||
| 2248 | } | 2264 | } |
| 2249 | 2265 | ||
| 2250 | static int ssi_gcm_setauthsize(struct crypto_aead *authenc, | 2266 | static int ssi_gcm_setauthsize(struct crypto_aead *authenc, |
| @@ -2269,7 +2285,10 @@ static int ssi_gcm_setauthsize(struct crypto_aead *authenc, · 18 unmodified lines | |||
| 2269 | static int ssi_rfc4106_gcm_setauthsize(struct crypto_aead *authenc, | 2285 | static int ssi_rfc4106_gcm_setauthsize(struct crypto_aead *authenc, |
| 2270 | unsigned int authsize) | 2286 | unsigned int authsize) |
| 2271 | { | 2287 | { |
| 2272 | SSI_LOG_DEBUG("authsize %d\n", authsize); | 2288 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(authenc); |
| 2289 | struct device *dev = drvdata_to_dev(ctx->drvdata); | ||
| 2290 | |||
| 2291 | dev_dbg(dev, "authsize %d\n", authsize); | ||
| 2273 | 2292 | ||
| 2274 | switch (authsize) { | 2293 | switch (authsize) { |
| 2275 | case 8: | 2294 | case 8: |
| @@ -2286,7 +2305,10 @@ static int ssi_rfc4106_gcm_setauthsize(struct crypto_aead *authenc, · 10 unmodified lines | |||
| 2286 | static int ssi_rfc4543_gcm_setauthsize(struct crypto_aead *authenc, | 2305 | static int ssi_rfc4543_gcm_setauthsize(struct crypto_aead *authenc, |
| 2287 | unsigned int authsize) | 2306 | unsigned int authsize) |
| 2288 | { | 2307 | { |
| 2289 | SSI_LOG_DEBUG("authsize %d\n", authsize); | 2308 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(authenc); |
| 2309 | struct device *dev = drvdata_to_dev(ctx->drvdata); | ||
| 2310 | |||
| 2311 | dev_dbg(dev, "authsize %d\n", authsize); | ||
| 2290 | 2312 | ||
| 2291 | if (authsize != 16) | 2313 | if (authsize != 16) |
| 2292 | return -EINVAL; | 2314 | return -EINVAL; |
| @@ -2298,11 +2320,14 @@ static int ssi_rfc4106_gcm_encrypt(struct aead_request *req) · 5 unmodified lines | |||
| 2298 | { | 2320 | { |
| 2299 | /* Very similar to ssi_aead_encrypt() above. */ | 2321 | /* Very similar to ssi_aead_encrypt() above. */ |
| 2300 | 2322 | ||
| 2323 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); | ||
| 2324 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); | ||
| 2325 | struct device *dev = drvdata_to_dev(ctx->drvdata); | ||
| 2301 | struct aead_req_ctx *areq_ctx = aead_request_ctx(req); | 2326 | struct aead_req_ctx *areq_ctx = aead_request_ctx(req); |
| 2302 | int rc = -EINVAL; | 2327 | int rc = -EINVAL; |
| 2303 | 2328 | ||
| 2304 | if (!valid_assoclen(req)) { | 2329 | if (!valid_assoclen(req)) { |
| 2305 | SSI_LOG_ERR("invalid Assoclen:%u\n", req->assoclen); | 2330 | dev_err(dev, "invalid Assoclen:%u\n", req->assoclen); |
| 2306 | goto out; | 2331 | goto out; |
| 2307 | } | 2332 | } |
| 2308 | 2333 | ||
| @@ -2350,11 +2375,14 @@ static int ssi_rfc4106_gcm_decrypt(struct aead_request *req) · 41 unmodified lines | |||
| 2350 | { | 2375 | { |
| 2351 | /* Very similar to ssi_aead_decrypt() above. */ | 2376 | /* Very similar to ssi_aead_decrypt() above. */ |
| 2352 | 2377 | ||
| 2378 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); | ||
| 2379 | struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); | ||
| 2380 | struct device *dev = drvdata_to_dev(ctx->drvdata); | ||
| 2353 | struct aead_req_ctx *areq_ctx = aead_request_ctx(req); | 2381 | struct aead_req_ctx *areq_ctx = aead_request_ctx(req); |
| 2354 | int rc = -EINVAL; | 2382 | int rc = -EINVAL; |
| 2355 | 2383 | ||
| 2356 | if (!valid_assoclen(req)) { | 2384 | if (!valid_assoclen(req)) { |
| 2357 | SSI_LOG_ERR("invalid Assoclen:%u\n", req->assoclen); | 2385 | dev_err(dev, "invalid Assoclen:%u\n", req->assoclen); |
| 2358 | goto out; | 2386 | goto out; |
| 2359 | } | 2387 | } |
| 2360 | 2388 | ||
| @@ -2654,16 +2682,17 @@ static struct ssi_alg_template aead_algs[] = { · 293 unmodified lines | |||
| 2654 | #endif /*SSI_CC_HAS_AES_GCM*/ | 2682 | #endif /*SSI_CC_HAS_AES_GCM*/ |
| 2655 | }; | 2683 | }; |
| 2656 | 2684 | ||
| 2657 | static struct ssi_crypto_alg *ssi_aead_create_alg(struct ssi_alg_template *template) | 2685 | static struct ssi_crypto_alg *ssi_aead_create_alg( |
| 2686 | struct ssi_alg_template *template, | ||
| 2687 | struct device *dev) | ||
| 2658 | { | 2688 | { |
| 2659 | struct ssi_crypto_alg *t_alg; | 2689 | struct ssi_crypto_alg *t_alg; |
| 2660 | struct aead_alg *alg; | 2690 | struct aead_alg *alg; |
| 2661 | 2691 | ||
| 2662 | t_alg = kzalloc(sizeof(*t_alg), GFP_KERNEL); | 2692 | t_alg = kzalloc(sizeof(*t_alg), GFP_KERNEL); |
| 2663 | if (!t_alg) { | 2693 | if (!t_alg) |
| 2664 | SSI_LOG_ERR("failed to allocate t_alg\n"); | ||
| 2665 | return ERR_PTR(-ENOMEM); | 2694 | return ERR_PTR(-ENOMEM); |
| 2666 | } | 2695 | |
| 2667 | alg = &template->template_aead; | 2696 | alg = &template->template_aead; |
| 2668 | 2697 | ||
| 2669 | snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", template->name); | 2698 | snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", template->name); |
| @@ -2713,6 +2742,7 @@ int ssi_aead_alloc(struct ssi_drvdata *drvdata) · 43 unmodified lines | |||
| 2713 | struct ssi_crypto_alg *t_alg; | 2742 | struct ssi_crypto_alg *t_alg; |
| 2714 | int rc = -ENOMEM; | 2743 | int rc = -ENOMEM; |
| 2715 | int alg; | 2744 | int alg; |
| 2745 | struct device *dev = drvdata_to_dev(drvdata); | ||
| 2716 | 2746 | ||
| 2717 | aead_handle = kmalloc(sizeof(*aead_handle), GFP_KERNEL); | 2747 | aead_handle = kmalloc(sizeof(*aead_handle), GFP_KERNEL); |
| 2718 | if (!aead_handle) { | 2748 | if (!aead_handle) { |
| @@ -2720,36 +2750,36 @@ int ssi_aead_alloc(struct ssi_drvdata *drvdata) · 1 unmodified line | |||
| 2720 | goto fail0; | 2750 | goto fail0; |
| 2721 | } | 2751 | } |
| 2722 | 2752 | ||
| 2753 | INIT_LIST_HEAD(&aead_handle->aead_list); | ||
| 2723 | drvdata->aead_handle = aead_handle; | 2754 | drvdata->aead_handle = aead_handle; |
| 2724 | 2755 | ||
| 2725 | aead_handle->sram_workspace_addr = ssi_sram_mgr_alloc( | 2756 | aead_handle->sram_workspace_addr = ssi_sram_mgr_alloc( |
| 2726 | drvdata, MAX_HMAC_DIGEST_SIZE); | 2757 | drvdata, MAX_HMAC_DIGEST_SIZE); |
| 2727 | if (aead_handle->sram_workspace_addr == NULL_SRAM_ADDR) { | 2758 | if (aead_handle->sram_workspace_addr == NULL_SRAM_ADDR) { |
| 2728 | SSI_LOG_ERR("SRAM pool exhausted\n"); | 2759 | dev_err(dev, "SRAM pool exhausted\n"); |
| 2729 | rc = -ENOMEM; | 2760 | rc = -ENOMEM; |
| 2730 | goto fail1; | 2761 | goto fail1; |
| 2731 | } | 2762 | } |
| 2732 | 2763 | ||
| 2733 | INIT_LIST_HEAD(&aead_handle->aead_list); | ||
| 2734 | |||
| 2735 | /* Linux crypto */ | 2764 | /* Linux crypto */ |
| 2736 | for (alg = 0; alg < ARRAY_SIZE(aead_algs); alg++) { | 2765 | for (alg = 0; alg < ARRAY_SIZE(aead_algs); alg++) { |
| 2737 | t_alg = ssi_aead_create_alg(&aead_algs[alg]); | 2766 | t_alg = ssi_aead_create_alg(&aead_algs[alg], dev); |
| 2738 | if (IS_ERR(t_alg)) { | 2767 | if (IS_ERR(t_alg)) { |
| 2739 | rc = PTR_ERR(t_alg); | 2768 | rc = PTR_ERR(t_alg); |
| 2740 | SSI_LOG_ERR("%s alg allocation failed\n", | 2769 | dev_err(dev, "%s alg allocation failed\n", |
| 2741 | aead_algs[alg].driver_name); | 2770 | aead_algs[alg].driver_name); |
| 2742 | goto fail1; | 2771 | goto fail1; |
| 2743 | } | 2772 | } |
| 2744 | t_alg->drvdata = drvdata; | 2773 | t_alg->drvdata = drvdata; |
| 2745 | rc = crypto_register_aead(&t_alg->aead_alg); | 2774 | rc = crypto_register_aead(&t_alg->aead_alg); |
| 2746 | if (unlikely(rc != 0)) { | 2775 | if (unlikely(rc != 0)) { |
| 2747 | SSI_LOG_ERR("%s alg registration failed\n", | 2776 | dev_err(dev, "%s alg registration failed\n", |
| 2748 | t_alg->aead_alg.base.cra_driver_name); | 2777 | t_alg->aead_alg.base.cra_driver_name); |
| 2749 | goto fail2; | 2778 | goto fail2; |
| 2750 | } else { | 2779 | } else { |
| 2751 | list_add_tail(&t_alg->entry, &aead_handle->aead_list); | 2780 | list_add_tail(&t_alg->entry, &aead_handle->aead_list); |
| 2752 | SSI_LOG_DEBUG("Registered %s\n", t_alg->aead_alg.base.cra_driver_name); | 2781 | dev_dbg(dev, "Registered %s\n", |
| 2782 | t_alg->aead_alg.base.cra_driver_name); | ||
| 2753 | } | 2783 | } |
| 2754 | } | 2784 | } |
| 2755 | 2785 | ||
| @@ -33,14 +33,10 @@ · 32 unmodified lines | |||
| 33 | #include "ssi_hash.h" | 33 | #include "ssi_hash.h" |
| 34 | #include "ssi_aead.h" | 34 | #include "ssi_aead.h" |
| 35 | 35 | ||
| 36 | #ifdef CC_DEBUG | ||
| 37 | #define GET_DMA_BUFFER_TYPE(buff_type) ( \ | 36 | #define GET_DMA_BUFFER_TYPE(buff_type) ( \ |
| 38 | ((buff_type) == SSI_DMA_BUF_NULL) ? "BUF_NULL" : \ | 37 | ((buff_type) == SSI_DMA_BUF_NULL) ? "BUF_NULL" : \ |
| 39 | ((buff_type) == SSI_DMA_BUF_DLLI) ? "BUF_DLLI" : \ | 38 | ((buff_type) == SSI_DMA_BUF_DLLI) ? "BUF_DLLI" : \ |
| 40 | ((buff_type) == SSI_DMA_BUF_MLLI) ? "BUF_MLLI" : "BUF_INVALID") | 39 | ((buff_type) == SSI_DMA_BUF_MLLI) ? "BUF_MLLI" : "BUF_INVALID") |
| 41 | #else | ||
| 42 | #define GET_DMA_BUFFER_TYPE(buff_type) | ||
| 43 | #endif | ||
| 44 | 40 | ||
| 45 | enum dma_buffer_type { | 41 | enum dma_buffer_type { |
| 46 | DMA_NULL_TYPE = -1, | 42 | DMA_NULL_TYPE = -1, |
| @@ -76,16 +72,12 @@ struct buffer_array { · 29 unmodified lines | |||
| 76 | * @lbytes: [OUT] Returns the amount of bytes at the last entry | 72 | * @lbytes: [OUT] Returns the amount of bytes at the last entry |
| 77 | */ | 73 | */ |
| 78 | static unsigned int ssi_buffer_mgr_get_sgl_nents( | 74 | static unsigned int ssi_buffer_mgr_get_sgl_nents( |
| 79 | struct scatterlist *sg_list, unsigned int nbytes, u32 *lbytes, bool *is_chained) | 75 | struct device *dev, struct scatterlist *sg_list, |
| 76 | unsigned int nbytes, u32 *lbytes, bool *is_chained) | ||
| 80 | { | 77 | { |
| 81 | unsigned int nents = 0; | 78 | unsigned int nents = 0; |
| 82 | 79 | ||
| 83 | while (nbytes != 0) { | 80 | while (nbytes != 0) { |
| 84 | if (sg_is_chain(sg_list)) { | ||
| 85 | SSI_LOG_ERR("Unexpected chained entry " | ||
| 86 | "in sg (entry =0x%X)\n", nents); | ||
| 87 | BUG(); | ||
| 88 | } | ||
| 89 | if (sg_list->length != 0) { | 81 | if (sg_list->length != 0) { |
| 90 | nents++; | 82 | nents++; |
| 91 | /* get the number of bytes in the last entry */ | 83 | /* get the number of bytes in the last entry */ |
| @@ -98,7 +90,7 @@ static unsigned int ssi_buffer_mgr_get_sgl_nents( · 6 unmodified lines | |||
| 98 | *is_chained = true; | 90 | *is_chained = true; |
| 99 | } | 91 | } |
| 100 | } | 92 | } |
| 101 | SSI_LOG_DEBUG("nents %d last bytes %d\n", nents, *lbytes); | 93 | dev_dbg(dev, "nents %d last bytes %d\n", nents, *lbytes); |
| 102 | return nents; | 94 | return nents; |
| 103 | } | 95 | } |
| 104 | 96 | ||
| @@ -134,20 +126,20 @@ void ssi_buffer_mgr_zero_sgl(struct scatterlist *sgl, u32 data_len) · 29 unmodified lines | |||
| 134 | * @direct: | 126 | * @direct: |
| 135 | */ | 127 | */ |
| 136 | void ssi_buffer_mgr_copy_scatterlist_portion( | 128 | void ssi_buffer_mgr_copy_scatterlist_portion( |
| 137 | u8 *dest, struct scatterlist *sg, | 129 | struct device *dev, u8 *dest, |
| 138 | u32 to_skip, u32 end, | 130 | struct scatterlist *sg, u32 to_skip, |
| 139 | enum ssi_sg_cpy_direct direct) | 131 | u32 end, enum ssi_sg_cpy_direct direct) |
| 140 | { | 132 | { |
| 141 | u32 nents, lbytes; | 133 | u32 nents, lbytes; |
| 142 | 134 | ||
| 143 | nents = ssi_buffer_mgr_get_sgl_nents(sg, end, &lbytes, NULL); | 135 | nents = ssi_buffer_mgr_get_sgl_nents(dev, sg, end, &lbytes, NULL); |
| 144 | sg_copy_buffer(sg, nents, (void *)dest, (end - to_skip + 1), to_skip, | 136 | sg_copy_buffer(sg, nents, (void *)dest, (end - to_skip + 1), to_skip, |
| 145 | (direct == SSI_SG_TO_BUF)); | 137 | (direct == SSI_SG_TO_BUF)); |
| 146 | } | 138 | } |
| 147 | 139 | ||
| 148 | static inline int ssi_buffer_mgr_render_buff_to_mlli( | 140 | static inline int ssi_buffer_mgr_render_buff_to_mlli( |
| 149 | dma_addr_t buff_dma, u32 buff_size, u32 *curr_nents, | 141 | struct device *dev, dma_addr_t buff_dma, u32 buff_size, |
| 150 | u32 **mlli_entry_pp) | 142 | u32 *curr_nents, u32 **mlli_entry_pp) |
| 151 | { | 143 | { |
| 152 | u32 *mlli_entry_p = *mlli_entry_pp; | 144 | u32 *mlli_entry_p = *mlli_entry_pp; |
| 153 | u32 new_nents; | 145 | u32 new_nents; |
| @@ -161,9 +153,9 @@ static inline int ssi_buffer_mgr_render_buff_to_mlli( · 7 unmodified lines | |||
| 161 | while (buff_size > CC_MAX_MLLI_ENTRY_SIZE) { | 153 | while (buff_size > CC_MAX_MLLI_ENTRY_SIZE) { |
| 162 | cc_lli_set_addr(mlli_entry_p, buff_dma); | 154 | cc_lli_set_addr(mlli_entry_p, buff_dma); |
| 163 | cc_lli_set_size(mlli_entry_p, CC_MAX_MLLI_ENTRY_SIZE); | 155 | cc_lli_set_size(mlli_entry_p, CC_MAX_MLLI_ENTRY_SIZE); |
| 164 | SSI_LOG_DEBUG("entry[%d]: single_buff=0x%08X size=%08X\n", *curr_nents, | 156 | dev_dbg(dev, "entry[%d]: single_buff=0x%08X size=%08X\n", |
| 165 | mlli_entry_p[LLI_WORD0_OFFSET], | 157 | *curr_nents, mlli_entry_p[LLI_WORD0_OFFSET], |
| 166 | mlli_entry_p[LLI_WORD1_OFFSET]); | 158 | mlli_entry_p[LLI_WORD1_OFFSET]); |
| 167 | buff_dma += CC_MAX_MLLI_ENTRY_SIZE; | 159 | buff_dma += CC_MAX_MLLI_ENTRY_SIZE; |
| 168 | buff_size -= CC_MAX_MLLI_ENTRY_SIZE; | 160 | buff_size -= CC_MAX_MLLI_ENTRY_SIZE; |
| 169 | mlli_entry_p = mlli_entry_p + 2; | 161 | mlli_entry_p = mlli_entry_p + 2; |
| @@ -172,9 +164,9 @@ static inline int ssi_buffer_mgr_render_buff_to_mlli( · 2 unmodified lines | |||
| 172 | /*Last entry */ | 164 | /*Last entry */ |
| 173 | cc_lli_set_addr(mlli_entry_p, buff_dma); | 165 | cc_lli_set_addr(mlli_entry_p, buff_dma); |
| 174 | cc_lli_set_size(mlli_entry_p, buff_size); | 166 | cc_lli_set_size(mlli_entry_p, buff_size); |
| 175 | SSI_LOG_DEBUG("entry[%d]: single_buff=0x%08X size=%08X\n", *curr_nents, | 167 | dev_dbg(dev, "entry[%d]: single_buff=0x%08X size=%08X\n", |
| 176 | mlli_entry_p[LLI_WORD0_OFFSET], | 168 | *curr_nents, mlli_entry_p[LLI_WORD0_OFFSET], |
| 177 | mlli_entry_p[LLI_WORD1_OFFSET]); | 169 | mlli_entry_p[LLI_WORD1_OFFSET]); |
| 178 | mlli_entry_p = mlli_entry_p + 2; | 170 | mlli_entry_p = mlli_entry_p + 2; |
| 179 | *mlli_entry_pp = mlli_entry_p; | 171 | *mlli_entry_pp = mlli_entry_p; |
| 180 | (*curr_nents)++; | 172 | (*curr_nents)++; |
| @@ -182,8 +174,9 @@ static inline int ssi_buffer_mgr_render_buff_to_mlli( · 1 unmodified line | |||
| 182 | } | 174 | } |
| 183 | 175 | ||
| 184 | static inline int ssi_buffer_mgr_render_scatterlist_to_mlli( | 176 | static inline int ssi_buffer_mgr_render_scatterlist_to_mlli( |
| 185 | struct scatterlist *sgl, u32 sgl_data_len, u32 sgl_offset, | 177 | struct device *dev, struct scatterlist *sgl, |
| 186 | u32 *curr_nents, u32 **mlli_entry_pp) | 178 | u32 sgl_data_len, u32 sgl_offset, u32 *curr_nents, |
| 179 | u32 **mlli_entry_pp) | ||
| 187 | { | 180 | { |
| 188 | struct scatterlist *curr_sgl = sgl; | 181 | struct scatterlist *curr_sgl = sgl; |
| 189 | u32 *mlli_entry_p = *mlli_entry_pp; | 182 | u32 *mlli_entry_p = *mlli_entry_pp; |
| @@ -197,8 +190,8 @@ static inline int ssi_buffer_mgr_render_scatterlist_to_mlli( · 7 unmodified lines | |||
| 197 | sgl_data_len; | 190 | sgl_data_len; |
| 198 | sgl_data_len -= entry_data_len; | 191 | sgl_data_len -= entry_data_len; |
| 199 | rc = ssi_buffer_mgr_render_buff_to_mlli( | 192 | rc = ssi_buffer_mgr_render_buff_to_mlli( |
| 200 | sg_dma_address(curr_sgl) + sgl_offset, entry_data_len, | 193 | dev, sg_dma_address(curr_sgl) + sgl_offset, |
| 201 | curr_nents, &mlli_entry_p); | 194 | entry_data_len, curr_nents, &mlli_entry_p); |
| 202 | if (rc != 0) | 195 | if (rc != 0) |
| 203 | return rc; | 196 | return rc; |
| 204 | 197 | ||
| @@ -217,14 +210,14 @@ static int ssi_buffer_mgr_generate_mlli( · 12 unmodified lines | |||
| 217 | u32 total_nents = 0, prev_total_nents = 0; | 210 | u32 total_nents = 0, prev_total_nents = 0; |
| 218 | int rc = 0, i; | 211 | int rc = 0, i; |
| 219 | 212 | ||
| 220 | SSI_LOG_DEBUG("NUM of SG's = %d\n", sg_data->num_of_buffers); | 213 | dev_dbg(dev, "NUM of SG's = %d\n", sg_data->num_of_buffers); |
| 221 | 214 | ||
| 222 | /* Allocate memory from the pointed pool */ | 215 | /* Allocate memory from the pointed pool */ |
| 223 | mlli_params->mlli_virt_addr = dma_pool_alloc( | 216 | mlli_params->mlli_virt_addr = dma_pool_alloc( |
| 224 | mlli_params->curr_pool, GFP_KERNEL, | 217 | mlli_params->curr_pool, GFP_KERNEL, |
| 225 | &mlli_params->mlli_dma_addr); | 218 | &mlli_params->mlli_dma_addr); |
| 226 | if (unlikely(!mlli_params->mlli_virt_addr)) { | 219 | if (unlikely(!mlli_params->mlli_virt_addr)) { |
| 227 | SSI_LOG_ERR("dma_pool_alloc() failed\n"); | 220 | dev_err(dev, "dma_pool_alloc() failed\n"); |
| 228 | rc = -ENOMEM; | 221 | rc = -ENOMEM; |
| 229 | goto build_mlli_exit; | 222 | goto build_mlli_exit; |
| 230 | } | 223 | } |
| @@ -234,12 +227,12 @@ static int ssi_buffer_mgr_generate_mlli( · 3 unmodified lines | |||
| 234 | for (i = 0; i < sg_data->num_of_buffers; i++) { | 227 | for (i = 0; i < sg_data->num_of_buffers; i++) { |
| 235 | if (sg_data->type[i] == DMA_SGL_TYPE) | 228 | if (sg_data->type[i] == DMA_SGL_TYPE) |
| 236 | rc = ssi_buffer_mgr_render_scatterlist_to_mlli( | 229 | rc = ssi_buffer_mgr_render_scatterlist_to_mlli( |
| 237 | sg_data->entry[i].sgl, | 230 | dev, sg_data->entry[i].sgl, |
| 238 | sg_data->total_data_len[i], sg_data->offset[i], &total_nents, | 231 | sg_data->total_data_len[i], sg_data->offset[i], |
| 239 | &mlli_p); | 232 | &total_nents, &mlli_p); |
| 240 | else /*DMA_BUFF_TYPE*/ | 233 | else /*DMA_BUFF_TYPE*/ |
| 241 | rc = ssi_buffer_mgr_render_buff_to_mlli( | 234 | rc = ssi_buffer_mgr_render_buff_to_mlli( |
| 242 | sg_data->entry[i].buffer_dma, | 235 | dev, sg_data->entry[i].buffer_dma, |
| 243 | sg_data->total_data_len[i], &total_nents, | 236 | sg_data->total_data_len[i], &total_nents, |
| 244 | &mlli_p); | 237 | &mlli_p); |
| 245 | if (rc != 0) | 238 | if (rc != 0) |
| @@ -259,26 +252,23 @@ static int ssi_buffer_mgr_generate_mlli( · 13 unmodified lines | |||
| 259 | /* Set MLLI size for the bypass operation */ | 252 | /* Set MLLI size for the bypass operation */ |
| 260 | mlli_params->mlli_len = (total_nents * LLI_ENTRY_BYTE_SIZE); | 253 | mlli_params->mlli_len = (total_nents * LLI_ENTRY_BYTE_SIZE); |
| 261 | 254 | ||
| 262 | SSI_LOG_DEBUG("MLLI params: " | 255 | dev_dbg(dev, "MLLI params: virt_addr=%pK dma_addr=%pad mlli_len=0x%X\n", |
| 263 | "virt_addr=%pK dma_addr=%pad mlli_len=0x%X\n", | 256 | mlli_params->mlli_virt_addr, &mlli_params->mlli_dma_addr, |
| 264 | mlli_params->mlli_virt_addr, | 257 | mlli_params->mlli_len); |
| 265 | mlli_params->mlli_dma_addr, | ||
| 266 | mlli_params->mlli_len); | ||
| 267 | 258 | ||
| 268 | build_mlli_exit: | 259 | build_mlli_exit: |
| 269 | return rc; | 260 | return rc; |
| 270 | } | 261 | } |
| 271 | 262 | ||
| 272 | static inline void ssi_buffer_mgr_add_buffer_entry( | 263 | static inline void ssi_buffer_mgr_add_buffer_entry( |
| 273 | struct buffer_array *sgl_data, | 264 | struct device *dev, struct buffer_array *sgl_data, |
| 274 | dma_addr_t buffer_dma, unsigned int buffer_len, | 265 | dma_addr_t buffer_dma, unsigned int buffer_len, |
| 275 | bool is_last_entry, u32 *mlli_nents) | 266 | bool is_last_entry, u32 *mlli_nents) |
| 276 | { | 267 | { |
| 277 | unsigned int index = sgl_data->num_of_buffers; | 268 | unsigned int index = sgl_data->num_of_buffers; |
| 278 | 269 | ||
| 279 | SSI_LOG_DEBUG("index=%u single_buff=%pad " | 270 | dev_dbg(dev, "index=%u single_buff=%pad buffer_len=0x%08X is_last=%d\n", |
| 280 | "buffer_len=0x%08X is_last=%d\n", | 271 | index, &buffer_dma, buffer_len, is_last_entry); |
| 281 | index, buffer_dma, buffer_len, is_last_entry); | ||
| 282 | sgl_data->nents[index] = 1; | 272 | sgl_data->nents[index] = 1; |
| 283 | sgl_data->entry[index].buffer_dma = buffer_dma; | 273 | sgl_data->entry[index].buffer_dma = buffer_dma; |
| 284 | sgl_data->offset[index] = 0; | 274 | sgl_data->offset[index] = 0; |
| @@ -292,6 +282,7 @@ static inline void ssi_buffer_mgr_add_buffer_entry( · 7 unmodified lines | |||
| 292 | } | 282 | } |
| 293 | 283 | ||
| 294 | static inline void ssi_buffer_mgr_add_scatterlist_entry( | 284 | static inline void ssi_buffer_mgr_add_scatterlist_entry( |
| 285 | struct device *dev, | ||
| 295 | struct buffer_array *sgl_data, | 286 | struct buffer_array *sgl_data, |
| 296 | unsigned int nents, | 287 | unsigned int nents, |
| 297 | struct scatterlist *sgl, | 288 | struct scatterlist *sgl, |
| @@ -302,8 +293,8 @@ static inline void ssi_buffer_mgr_add_scatterlist_entry( · 4 unmodified lines | |||
| 302 | { | 293 | { |
| 303 | unsigned int index = sgl_data->num_of_buffers; | 294 | unsigned int index = sgl_data->num_of_buffers; |
| 304 | 295 | ||
| 305 | SSI_LOG_DEBUG("index=%u nents=%u sgl=%pK data_len=0x%08X is_last=%d\n", | 296 | dev_dbg(dev, "index=%u nents=%u sgl=%pK data_len=0x%08X is_last=%d\n", |
| 306 | index, nents, sgl, data_len, is_last_table); | 297 | index, nents, sgl, data_len, is_last_table); |
| 307 | sgl_data->nents[index] = nents; | 298 | sgl_data->nents[index] = nents; |
| 308 | sgl_data->entry[index].sgl = sgl; | 299 | sgl_data->entry[index].sgl = sgl; |
| 309 | sgl_data->offset[index] = data_offset; | 300 | sgl_data->offset[index] = data_offset; |
| @@ -327,7 +318,7 @@ ssi_buffer_mgr_dma_map_sg(struct device *dev, struct scatterlist *sg, u32 nents, · 17 unmodified lines | |||
| 327 | if (!l_sg) | 318 | if (!l_sg) |
| 328 | break; | 319 | break; |
| 329 | if (unlikely(dma_map_sg(dev, l_sg, 1, direction) != 1)) { | 320 | if (unlikely(dma_map_sg(dev, l_sg, 1, direction) != 1)) { |
| 330 | SSI_LOG_ERR("dma_map_page() sg buffer failed\n"); | 321 | dev_err(dev, "dma_map_page() sg buffer failed\n"); |
| 331 | goto err; | 322 | goto err; |
| 332 | } | 323 | } |
| 333 | l_sg = sg_next(l_sg); | 324 | l_sg = sg_next(l_sg); |
| @@ -356,26 +347,22 @@ static int ssi_buffer_mgr_map_scatterlist( · 22 unmodified lines | |||
| 356 | if (sg_is_last(sg)) { | 347 | if (sg_is_last(sg)) { |
| 357 | /* One entry only case -set to DLLI */ | 348 | /* One entry only case -set to DLLI */ |
| 358 | if (unlikely(dma_map_sg(dev, sg, 1, direction) != 1)) { | 349 | if (unlikely(dma_map_sg(dev, sg, 1, direction) != 1)) { |
| 359 | SSI_LOG_ERR("dma_map_sg() single buffer failed\n"); | 350 | dev_err(dev, "dma_map_sg() single buffer failed\n"); |
| 360 | return -ENOMEM; | 351 | return -ENOMEM; |
| 361 | } | 352 | } |
| 362 | SSI_LOG_DEBUG("Mapped sg: dma_address=%pad " | 353 | dev_dbg(dev, "Mapped sg: dma_address=%pad page=%p addr=%pK offset=%u length=%u\n", |
| 363 | "page=%p addr=%pK offset=%u " | 354 | &sg_dma_address(sg), sg_page(sg), sg_virt(sg), |
| 364 | "length=%u\n", | 355 | sg->offset, sg->length); |
| 365 | sg_dma_address(sg), | ||
| 366 | sg_page(sg), | ||
| 367 | sg_virt(sg), | ||
| 368 | sg->offset, sg->length); | ||
| 369 | *lbytes = nbytes; | 356 | *lbytes = nbytes; |
| 370 | *nents = 1; | 357 | *nents = 1; |
| 371 | *mapped_nents = 1; | 358 | *mapped_nents = 1; |
| 372 | } else { /*sg_is_last*/ | 359 | } else { /*sg_is_last*/ |
| 373 | *nents = ssi_buffer_mgr_get_sgl_nents(sg, nbytes, lbytes, | 360 | *nents = ssi_buffer_mgr_get_sgl_nents(dev, sg, nbytes, lbytes, |
| 374 | &is_chained); | 361 | &is_chained); |
| 375 | if (*nents > max_sg_nents) { | 362 | if (*nents > max_sg_nents) { |
| 376 | *nents = 0; | 363 | *nents = 0; |
| 377 | SSI_LOG_ERR("Too many fragments. current %d max %d\n", | 364 | dev_err(dev, "Too many fragments. current %d max %d\n", |
| 378 | *nents, max_sg_nents); | 365 | *nents, max_sg_nents); |
| 379 | return -ENOMEM; | 366 | return -ENOMEM; |
| 380 | } | 367 | } |
| 381 | if (!is_chained) { | 368 | if (!is_chained) { |
| @@ -385,7 +372,7 @@ static int ssi_buffer_mgr_map_scatterlist( · 3 unmodified lines | |||
| 385 | *mapped_nents = dma_map_sg(dev, sg, *nents, direction); | 372 | *mapped_nents = dma_map_sg(dev, sg, *nents, direction); |
| 386 | if (unlikely(*mapped_nents == 0)) { | 373 | if (unlikely(*mapped_nents == 0)) { |
| 387 | *nents = 0; | 374 | *nents = 0; |
| 388 | SSI_LOG_ERR("dma_map_sg() sg buffer failed\n"); | 375 | dev_err(dev, "dma_map_sg() sg buffer failed\n"); |
| 389 | return -ENOMEM; | 376 | return -ENOMEM; |
| 390 | } | 377 | } |
| 391 | } else { | 378 | } else { |
| @@ -398,7 +385,7 @@ static int ssi_buffer_mgr_map_scatterlist( · 6 unmodified lines | |||
| 398 | direction); | 385 | direction); |
| 399 | if (unlikely(*mapped_nents != *nents)) { | 386 | if (unlikely(*mapped_nents != *nents)) { |
| 400 | *nents = *mapped_nents; | 387 | *nents = *mapped_nents; |
| 401 | SSI_LOG_ERR("dma_map_sg() sg buffer failed\n"); | 388 | dev_err(dev, "dma_map_sg() sg buffer failed\n"); |
| 402 | return -ENOMEM; | 389 | return -ENOMEM; |
| 403 | } | 390 | } |
| 404 | } | 391 | } |
| @@ -414,26 +401,22 @@ ssi_aead_handle_config_buf(struct device *dev, · 9 unmodified lines | |||
| 414 | struct buffer_array *sg_data, | 401 | struct buffer_array *sg_data, |
| 415 | unsigned int assoclen) | 402 | unsigned int assoclen) |
| 416 | { | 403 | { |
| 417 | SSI_LOG_DEBUG(" handle additional data config set to DLLI\n"); | 404 | dev_dbg(dev, " handle additional data config set to DLLI\n"); |
| 418 | /* create sg for the current buffer */ | 405 | /* create sg for the current buffer */ |
| 419 | sg_init_one(&areq_ctx->ccm_adata_sg, config_data, AES_BLOCK_SIZE + areq_ctx->ccm_hdr_size); | 406 | sg_init_one(&areq_ctx->ccm_adata_sg, config_data, AES_BLOCK_SIZE + areq_ctx->ccm_hdr_size); |
| 420 | if (unlikely(dma_map_sg(dev, &areq_ctx->ccm_adata_sg, 1, | 407 | if (unlikely(dma_map_sg(dev, &areq_ctx->ccm_adata_sg, 1, |
| 421 | DMA_TO_DEVICE) != 1)) { | 408 | DMA_TO_DEVICE) != 1)) { |
| 422 | SSI_LOG_ERR("dma_map_sg() " | 409 | dev_err(dev, "dma_map_sg() config buffer failed\n"); |
| 423 | "config buffer failed\n"); | 410 | return -ENOMEM; |
| 424 | return -ENOMEM; | ||
| 425 | } | 411 | } |
| 426 | SSI_LOG_DEBUG("Mapped curr_buff: dma_address=%pad " | 412 | dev_dbg(dev, "Mapped curr_buff: dma_address=%pad page=%p addr=%pK offset=%u length=%u\n", |
| 427 | "page=%p addr=%pK " | 413 | &sg_dma_address(&areq_ctx->ccm_adata_sg), |
| 428 | "offset=%u length=%u\n", | 414 | sg_page(&areq_ctx->ccm_adata_sg), |
| 429 | sg_dma_address(&areq_ctx->ccm_adata_sg), | 415 | sg_virt(&areq_ctx->ccm_adata_sg), |
| 430 | sg_page(&areq_ctx->ccm_adata_sg), | 416 | areq_ctx->ccm_adata_sg.offset, areq_ctx->ccm_adata_sg.length); |
| 431 | sg_virt(&areq_ctx->ccm_adata_sg), | ||
| 432 | areq_ctx->ccm_adata_sg.offset, | ||
| 433 | areq_ctx->ccm_adata_sg.length); | ||
| 434 | /* prepare for case of MLLI */ | 417 | /* prepare for case of MLLI */ |
| 435 | if (assoclen > 0) { | 418 | if (assoclen > 0) { |
| 436 | ssi_buffer_mgr_add_scatterlist_entry(sg_data, 1, | 419 | ssi_buffer_mgr_add_scatterlist_entry(dev, sg_data, 1, |
| 437 | &areq_ctx->ccm_adata_sg, | 420 | &areq_ctx->ccm_adata_sg, |
| 438 | (AES_BLOCK_SIZE + areq_ctx->ccm_hdr_size), | 421 | (AES_BLOCK_SIZE + areq_ctx->ccm_hdr_size), |
| 439 | 0, false, NULL); | 422 | 0, false, NULL); |
| @@ -447,28 +430,23 @@ static inline int ssi_ahash_handle_curr_buf(struct device *dev, · 7 unmodified lines | |||
| 447 | u32 curr_buff_cnt, | 430 | u32 curr_buff_cnt, |
| 448 | struct buffer_array *sg_data) | 431 | struct buffer_array *sg_data) |
| 449 | { | 432 | { |
| 450 | SSI_LOG_DEBUG(" handle curr buff %x set to DLLI\n", curr_buff_cnt); | 433 | dev_dbg(dev, " handle curr buff %x set to DLLI\n", curr_buff_cnt); |
| 451 | /* create sg for the current buffer */ | 434 | /* create sg for the current buffer */ |
| 452 | sg_init_one(areq_ctx->buff_sg, curr_buff, curr_buff_cnt); | 435 | sg_init_one(areq_ctx->buff_sg, curr_buff, curr_buff_cnt); |
| 453 | if (unlikely(dma_map_sg(dev, areq_ctx->buff_sg, 1, | 436 | if (unlikely(dma_map_sg(dev, areq_ctx->buff_sg, 1, |
| 454 | DMA_TO_DEVICE) != 1)) { | 437 | DMA_TO_DEVICE) != 1)) { |
| 455 | SSI_LOG_ERR("dma_map_sg() " | 438 | dev_err(dev, "dma_map_sg() src buffer failed\n"); |
| 456 | "src buffer failed\n"); | 439 | return -ENOMEM; |
| 457 | return -ENOMEM; | ||
| 458 | } | 440 | } |
| 459 | SSI_LOG_DEBUG("Mapped curr_buff: dma_address=%pad " | 441 | dev_dbg(dev, "Mapped curr_buff: dma_address=%pad page=%p addr=%pK offset=%u length=%u\n", |
| 460 | "page=%p addr=%pK " | 442 | &sg_dma_address(areq_ctx->buff_sg), sg_page(areq_ctx->buff_sg), |
| 461 | "offset=%u length=%u\n", | 443 | sg_virt(areq_ctx->buff_sg), areq_ctx->buff_sg->offset, |
| 462 | sg_dma_address(areq_ctx->buff_sg), | 444 | areq_ctx->buff_sg->length); |
| 463 | sg_page(areq_ctx->buff_sg), | ||
| 464 | sg_virt(areq_ctx->buff_sg), | ||
| 465 | areq_ctx->buff_sg->offset, | ||
| 466 | areq_ctx->buff_sg->length); | ||
| 467 | areq_ctx->data_dma_buf_type = SSI_DMA_BUF_DLLI; | 445 | areq_ctx->data_dma_buf_type = SSI_DMA_BUF_DLLI; |
| 468 | areq_ctx->curr_sg = areq_ctx->buff_sg; | 446 | areq_ctx->curr_sg = areq_ctx->buff_sg; |
| 469 | areq_ctx->in_nents = 0; | 447 | areq_ctx->in_nents = 0; |
| 470 | /* prepare for case of MLLI */ | 448 | /* prepare for case of MLLI */ |
| 471 | ssi_buffer_mgr_add_scatterlist_entry(sg_data, 1, areq_ctx->buff_sg, | 449 | ssi_buffer_mgr_add_scatterlist_entry(dev, sg_data, 1, areq_ctx->buff_sg, |
| 472 | curr_buff_cnt, 0, false, NULL); | 450 | curr_buff_cnt, 0, false, NULL); |
| 473 | return 0; | 451 | return 0; |
| 474 | } | 452 | } |
| @@ -483,9 +461,8 @@ void ssi_buffer_mgr_unmap_blkcipher_request( · 8 unmodified lines | |||
| 483 | struct blkcipher_req_ctx *req_ctx = (struct blkcipher_req_ctx *)ctx; | 461 | struct blkcipher_req_ctx *req_ctx = (struct blkcipher_req_ctx *)ctx; |
| 484 | 462 | ||
| 485 | if (likely(req_ctx->gen_ctx.iv_dma_addr != 0)) { | 463 | if (likely(req_ctx->gen_ctx.iv_dma_addr != 0)) { |
| 486 | SSI_LOG_DEBUG("Unmapped iv: iv_dma_addr=%pad iv_size=%u\n", | 464 | dev_dbg(dev, "Unmapped iv: iv_dma_addr=%pad iv_size=%u\n", |
| 487 | req_ctx->gen_ctx.iv_dma_addr, | 465 | &req_ctx->gen_ctx.iv_dma_addr, ivsize); |
| 488 | ivsize); | ||
| 489 | dma_unmap_single(dev, req_ctx->gen_ctx.iv_dma_addr, | 466 | dma_unmap_single(dev, req_ctx->gen_ctx.iv_dma_addr, |
| 490 | ivsize, | 467 | ivsize, |
| 491 | req_ctx->is_giv ? DMA_BIDIRECTIONAL : | 468 | req_ctx->is_giv ? DMA_BIDIRECTIONAL : |
| @@ -499,11 +476,11 @@ void ssi_buffer_mgr_unmap_blkcipher_request( · 7 unmodified lines | |||
| 499 | } | 476 | } |
| 500 | 477 | ||
| 501 | dma_unmap_sg(dev, src, req_ctx->in_nents, DMA_BIDIRECTIONAL); | 478 | dma_unmap_sg(dev, src, req_ctx->in_nents, DMA_BIDIRECTIONAL); |
| 502 | SSI_LOG_DEBUG("Unmapped req->src=%pK\n", sg_virt(src)); | 479 | dev_dbg(dev, "Unmapped req->src=%pK\n", sg_virt(src)); |
| 503 | 480 | ||
| 504 | if (src != dst) { | 481 | if (src != dst) { |
| 505 | dma_unmap_sg(dev, dst, req_ctx->out_nents, DMA_BIDIRECTIONAL); | 482 | dma_unmap_sg(dev, dst, req_ctx->out_nents, DMA_BIDIRECTIONAL); |
| 506 | SSI_LOG_DEBUG("Unmapped req->dst=%pK\n", sg_virt(dst)); | 483 | dev_dbg(dev, "Unmapped req->dst=%pK\n", sg_virt(dst)); |
| 507 | } | 484 | } |
| 508 | } | 485 | } |
| 509 | 486 | ||
| @@ -519,7 +496,7 @@ int ssi_buffer_mgr_map_blkcipher_request( · 9 unmodified lines | |||
| 519 | struct blkcipher_req_ctx *req_ctx = (struct blkcipher_req_ctx *)ctx; | 496 | struct blkcipher_req_ctx *req_ctx = (struct blkcipher_req_ctx *)ctx; |
| 520 | struct mlli_params *mlli_params = &req_ctx->mlli_params; | 497 | struct mlli_params *mlli_params = &req_ctx->mlli_params; |
| 521 | struct buff_mgr_handle *buff_mgr = drvdata->buff_mgr_handle; | 498 | struct buff_mgr_handle *buff_mgr = drvdata->buff_mgr_handle; |
| 522 | struct device *dev = &drvdata->plat_dev->dev; | 499 | struct device *dev = drvdata_to_dev(drvdata); |
| 523 | struct buffer_array sg_data; | 500 | struct buffer_array sg_data; |
| 524 | u32 dummy = 0; | 501 | u32 dummy = 0; |
| 525 | int rc = 0; | 502 | int rc = 0; |
| @@ -539,13 +516,12 @@ int ssi_buffer_mgr_map_blkcipher_request( · 13 unmodified lines | |||
| 539 | DMA_TO_DEVICE); | 516 | DMA_TO_DEVICE); |
| 540 | if (unlikely(dma_mapping_error(dev, | 517 | if (unlikely(dma_mapping_error(dev, |
| 541 | req_ctx->gen_ctx.iv_dma_addr))) { | 518 | req_ctx->gen_ctx.iv_dma_addr))) { |
| 542 | SSI_LOG_ERR("Mapping iv %u B at va=%pK " | 519 | dev_err(dev, "Mapping iv %u B at va=%pK for DMA failed\n", |
| 543 | "for DMA failed\n", ivsize, info); | 520 | ivsize, info); |
| 544 | return -ENOMEM; | 521 | return -ENOMEM; |
| 545 | } | 522 | } |
| 546 | SSI_LOG_DEBUG("Mapped iv %u B at va=%pK to dma=%pad\n", | 523 | dev_dbg(dev, "Mapped iv %u B at va=%pK to dma=%pad\n", |
| 547 | ivsize, info, | 524 | ivsize, info, &req_ctx->gen_ctx.iv_dma_addr); |
| 548 | req_ctx->gen_ctx.iv_dma_addr); | ||
| 549 | } else { | 525 | } else { |
| 550 | req_ctx->gen_ctx.iv_dma_addr = 0; | 526 | req_ctx->gen_ctx.iv_dma_addr = 0; |
| 551 | } | 527 | } |
| @@ -567,7 +543,7 @@ int ssi_buffer_mgr_map_blkcipher_request( · 15 unmodified lines | |||
| 567 | /* Handle inplace operation */ | 543 | /* Handle inplace operation */ |
| 568 | if (unlikely(req_ctx->dma_buf_type == SSI_DMA_BUF_MLLI)) { | 544 | if (unlikely(req_ctx->dma_buf_type == SSI_DMA_BUF_MLLI)) { |
| 569 | req_ctx->out_nents = 0; | 545 | req_ctx->out_nents = 0; |
| 570 | ssi_buffer_mgr_add_scatterlist_entry(&sg_data, | 546 | ssi_buffer_mgr_add_scatterlist_entry(dev, &sg_data, |
| 571 | req_ctx->in_nents, | 547 | req_ctx->in_nents, |
| 572 | src, nbytes, 0, | 548 | src, nbytes, 0, |
| 573 | true, | 549 | true, |
| @@ -587,12 +563,12 @@ int ssi_buffer_mgr_map_blkcipher_request( · 13 unmodified lines | |||
| 587 | req_ctx->dma_buf_type = SSI_DMA_BUF_MLLI; | 563 | req_ctx->dma_buf_type = SSI_DMA_BUF_MLLI; |
| 588 | 564 | ||
| 589 | if (unlikely((req_ctx->dma_buf_type == SSI_DMA_BUF_MLLI))) { | 565 | if (unlikely((req_ctx->dma_buf_type == SSI_DMA_BUF_MLLI))) { |
| 590 | ssi_buffer_mgr_add_scatterlist_entry(&sg_data, | 566 | ssi_buffer_mgr_add_scatterlist_entry(dev, &sg_data, |
| 591 | req_ctx->in_nents, | 567 | req_ctx->in_nents, |
| 592 | src, nbytes, 0, | 568 | src, nbytes, 0, |
| 593 | true, | 569 | true, |
| 594 | &req_ctx->in_mlli_nents); | 570 | &req_ctx->in_mlli_nents); |
| 595 | ssi_buffer_mgr_add_scatterlist_entry(&sg_data, | 571 | ssi_buffer_mgr_add_scatterlist_entry(dev, &sg_data, |
| 596 | req_ctx->out_nents, | 572 | req_ctx->out_nents, |
| 597 | dst, nbytes, 0, | 573 | dst, nbytes, 0, |
| 598 | true, | 574 | true, |
| @@ -607,8 +583,8 @@ int ssi_buffer_mgr_map_blkcipher_request( · 8 unmodified lines | |||
| 607 | goto ablkcipher_exit; | 583 | goto ablkcipher_exit; |
| 608 | } | 584 | } |
| 609 | 585 | ||
| 610 | SSI_LOG_DEBUG("areq_ctx->dma_buf_type = %s\n", | 586 | dev_dbg(dev, "areq_ctx->dma_buf_type = %s\n", |
| 611 | GET_DMA_BUFFER_TYPE(req_ctx->dma_buf_type)); | 587 | GET_DMA_BUFFER_TYPE(req_ctx->dma_buf_type)); |
| 612 | 588 | ||
| 613 | return 0; | 589 | return 0; |
| 614 | 590 | ||
| @@ -674,30 +650,34 @@ void ssi_buffer_mgr_unmap_aead_request( · 59 unmodified lines | |||
| 674 | *allocated and should be released | 650 | *allocated and should be released |
| 675 | */ | 651 | */ |
| 676 | if (areq_ctx->mlli_params.curr_pool) { | 652 | if (areq_ctx->mlli_params.curr_pool) { |
| 677 | SSI_LOG_DEBUG("free MLLI buffer: dma=%pad virt=%pK\n", | 653 | dev_dbg(dev, "free MLLI buffer: dma=%pad virt=%pK\n", |
| 678 | areq_ctx->mlli_params.mlli_dma_addr, | 654 | &areq_ctx->mlli_params.mlli_dma_addr, |
| 679 | areq_ctx->mlli_params.mlli_virt_addr); | 655 | areq_ctx->mlli_params.mlli_virt_addr); |
| 680 | dma_pool_free(areq_ctx->mlli_params.curr_pool, | 656 | dma_pool_free(areq_ctx->mlli_params.curr_pool, |
| 681 | areq_ctx->mlli_params.mlli_virt_addr, | 657 | areq_ctx->mlli_params.mlli_virt_addr, |
| 682 | areq_ctx->mlli_params.mlli_dma_addr); | 658 | areq_ctx->mlli_params.mlli_dma_addr); |
| 683 | } | 659 | } |
| 684 | 660 | ||
| 685 | SSI_LOG_DEBUG("Unmapping src sgl: req->src=%pK areq_ctx->src.nents=%u areq_ctx->assoc.nents=%u assoclen:%u cryptlen=%u\n", sg_virt(req->src), areq_ctx->src.nents, areq_ctx->assoc.nents, req->assoclen, req->cryptlen); | 661 | dev_dbg(dev, "Unmapping src sgl: req->src=%pK areq_ctx->src.nents=%u areq_ctx->assoc.nents=%u assoclen:%u cryptlen=%u\n", |
| 662 | sg_virt(req->src), areq_ctx->src.nents, areq_ctx->assoc.nents, | ||
| 663 | req->assoclen, req->cryptlen); | ||
| 686 | size_to_unmap = req->assoclen + req->cryptlen; | 664 | size_to_unmap = req->assoclen + req->cryptlen; |
| 687 | if (areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_ENCRYPT) | 665 | if (areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_ENCRYPT) |
| 688 | size_to_unmap += areq_ctx->req_authsize; | 666 | size_to_unmap += areq_ctx->req_authsize; |
| 689 | if (areq_ctx->is_gcm4543) | 667 | if (areq_ctx->is_gcm4543) |
| 690 | size_to_unmap += crypto_aead_ivsize(tfm); | 668 | size_to_unmap += crypto_aead_ivsize(tfm); |
| 691 | 669 | ||
| 692 | dma_unmap_sg(dev, req->src, ssi_buffer_mgr_get_sgl_nents(req->src, size_to_unmap, &dummy, &chained), DMA_BIDIRECTIONAL); | 670 | dma_unmap_sg(dev, req->src, |
| 671 | ssi_buffer_mgr_get_sgl_nents(dev, req->src, size_to_unmap, | ||
| 672 | &dummy, &chained), | ||
| 673 | DMA_BIDIRECTIONAL); | ||
| 693 | if (unlikely(req->src != req->dst)) { | 674 | if (unlikely(req->src != req->dst)) { |
| 694 | SSI_LOG_DEBUG("Unmapping dst sgl: req->dst=%pK\n", | 675 | dev_dbg(dev, "Unmapping dst sgl: req->dst=%pK\n", |
| 695 | sg_virt(req->dst)); | 676 | sg_virt(req->dst)); |
| 696 | dma_unmap_sg(dev, req->dst, | 677 | dma_unmap_sg(dev, req->dst, |
| 697 | ssi_buffer_mgr_get_sgl_nents(req->dst, | 678 | ssi_buffer_mgr_get_sgl_nents(dev, req->dst, |
| 698 | size_to_unmap, | 679 | size_to_unmap, |
| 699 | &dummy, | 680 | &dummy, &chained), |
| 700 | &chained), | ||
| 701 | DMA_BIDIRECTIONAL); | 681 | DMA_BIDIRECTIONAL); |
| 702 | } | 682 | } |
| 703 | if (drvdata->coherent && | 683 | if (drvdata->coherent && |
| @@ -712,13 +692,14 @@ void ssi_buffer_mgr_unmap_aead_request( · 8 unmodified lines | |||
| 712 | * data memory overriding that caused by cache coherence problem. | 692 | * data memory overriding that caused by cache coherence problem. |
| 713 | */ | 693 | */ |
| 714 | ssi_buffer_mgr_copy_scatterlist_portion( | 694 | ssi_buffer_mgr_copy_scatterlist_portion( |
| 715 | areq_ctx->backup_mac, req->src, | 695 | dev, areq_ctx->backup_mac, req->src, |
| 716 | size_to_skip + req->cryptlen - areq_ctx->req_authsize, | 696 | size_to_skip + req->cryptlen - areq_ctx->req_authsize, |
| 717 | size_to_skip + req->cryptlen, SSI_SG_FROM_BUF); | 697 | size_to_skip + req->cryptlen, SSI_SG_FROM_BUF); |
| 718 | } | 698 | } |
| 719 | } | 699 | } |
| 720 | 700 | ||
| 721 | static inline int ssi_buffer_mgr_get_aead_icv_nents( | 701 | static inline int ssi_buffer_mgr_get_aead_icv_nents( |
| 702 | struct device *dev, | ||
| 722 | struct scatterlist *sgl, | 703 | struct scatterlist *sgl, |
| 723 | unsigned int sgl_nents, | 704 | unsigned int sgl_nents, |
| 724 | unsigned int authsize, | 705 | unsigned int authsize, |
| @@ -757,12 +738,12 @@ static inline int ssi_buffer_mgr_get_aead_icv_nents( · 32 unmodified lines | |||
| 757 | nents = 2; | 738 | nents = 2; |
| 758 | *is_icv_fragmented = true; | 739 | *is_icv_fragmented = true; |
| 759 | } else { | 740 | } else { |
| 760 | SSI_LOG_ERR("Unsupported num. of ICV fragments (> %d)\n", | 741 | dev_err(dev, "Unsupported num. of ICV fragments (> %d)\n", |
| 761 | MAX_ICV_NENTS_SUPPORTED); | 742 | MAX_ICV_NENTS_SUPPORTED); |
| 762 | nents = -1; /*unsupported*/ | 743 | nents = -1; /*unsupported*/ |
| 763 | } | 744 | } |
| 764 | SSI_LOG_DEBUG("is_frag=%s icv_nents=%u\n", | 745 | dev_dbg(dev, "is_frag=%s icv_nents=%u\n", |
| 765 | (*is_icv_fragmented ? "true" : "false"), nents); | 746 | (*is_icv_fragmented ? "true" : "false"), nents); |
| 766 | 747 | ||
| 767 | return nents; | 748 | return nents; |
| 768 | } | 749 | } |
| @@ -775,7 +756,7 @@ static inline int ssi_buffer_mgr_aead_chain_iv( · 6 unmodified lines | |||
| 775 | { | 756 | { |
| 776 | struct aead_req_ctx *areq_ctx = aead_request_ctx(req); | 757 | struct aead_req_ctx *areq_ctx = aead_request_ctx(req); |
| 777 | unsigned int hw_iv_size = areq_ctx->hw_iv_size; | 758 | unsigned int hw_iv_size = areq_ctx->hw_iv_size; |
| 778 | struct device *dev = &drvdata->plat_dev->dev; | 759 | struct device *dev = drvdata_to_dev(drvdata); |
| 779 | int rc = 0; | 760 | int rc = 0; |
| 780 | 761 | ||
| 781 | if (unlikely(!req->iv)) { | 762 | if (unlikely(!req->iv)) { |
| @@ -786,22 +767,22 @@ static inline int ssi_buffer_mgr_aead_chain_iv( · 4 unmodified lines | |||
| 786 | areq_ctx->gen_ctx.iv_dma_addr = dma_map_single(dev, req->iv, hw_iv_size, | 767 | areq_ctx->gen_ctx.iv_dma_addr = dma_map_single(dev, req->iv, hw_iv_size, |
| 787 | DMA_BIDIRECTIONAL); | 768 | DMA_BIDIRECTIONAL); |
| 788 | if (unlikely(dma_mapping_error(dev, areq_ctx->gen_ctx.iv_dma_addr))) { | 769 | if (unlikely(dma_mapping_error(dev, areq_ctx->gen_ctx.iv_dma_addr))) { |
| 789 | SSI_LOG_ERR("Mapping iv %u B at va=%pK for DMA failed\n", | 770 | dev_err(dev, "Mapping iv %u B at va=%pK for DMA failed\n", |
| 790 | hw_iv_size, req->iv); | 771 | hw_iv_size, req->iv); |
| 791 | rc = -ENOMEM; | 772 | rc = -ENOMEM; |
| 792 | goto chain_iv_exit; | 773 | goto chain_iv_exit; |
| 793 | } | 774 | } |
| 794 | 775 | ||
| 795 | SSI_LOG_DEBUG("Mapped iv %u B at va=%pK to dma=%pad\n", | 776 | dev_dbg(dev, "Mapped iv %u B at va=%pK to dma=%pad\n", |
| 796 | hw_iv_size, req->iv, | 777 | hw_iv_size, req->iv, &areq_ctx->gen_ctx.iv_dma_addr); |
| 797 | areq_ctx->gen_ctx.iv_dma_addr); | ||
| 798 | if (do_chain && areq_ctx->plaintext_authenticate_only) { // TODO: what about CTR?? ask Ron | 778 | if (do_chain && areq_ctx->plaintext_authenticate_only) { // TODO: what about CTR?? ask Ron |
| 799 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); | 779 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); |
| 800 | unsigned int iv_size_to_authenc = crypto_aead_ivsize(tfm); | 780 | unsigned int iv_size_to_authenc = crypto_aead_ivsize(tfm); |
| 801 | unsigned int iv_ofs = GCM_BLOCK_RFC4_IV_OFFSET; | 781 | unsigned int iv_ofs = GCM_BLOCK_RFC4_IV_OFFSET; |
| 802 | /* Chain to given list */ | 782 | /* Chain to given list */ |
| 803 | ssi_buffer_mgr_add_buffer_entry( | 783 | ssi_buffer_mgr_add_buffer_entry( |
| 804 | sg_data, areq_ctx->gen_ctx.iv_dma_addr + iv_ofs, | 784 | dev, sg_data, |
| 785 | areq_ctx->gen_ctx.iv_dma_addr + iv_ofs, | ||
| 805 | iv_size_to_authenc, is_last, | 786 | iv_size_to_authenc, is_last, |
| 806 | &areq_ctx->assoc.mlli_nents); | 787 | &areq_ctx->assoc.mlli_nents); |
| 807 | areq_ctx->assoc_buff_type = SSI_DMA_BUF_MLLI; | 788 | areq_ctx->assoc_buff_type = SSI_DMA_BUF_MLLI; |
| @@ -824,6 +805,7 @@ static inline int ssi_buffer_mgr_aead_chain_assoc( · 16 unmodified lines | |||
| 824 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); | 805 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); |
| 825 | unsigned int sg_index = 0; | 806 | unsigned int sg_index = 0; |
| 826 | u32 size_of_assoc = req->assoclen; | 807 | u32 size_of_assoc = req->assoclen; |
| 808 | struct device *dev = drvdata_to_dev(drvdata); | ||
| 827 | 809 | ||
| 828 | if (areq_ctx->is_gcm4543) | 810 | if (areq_ctx->is_gcm4543) |
| 829 | size_of_assoc += crypto_aead_ivsize(tfm); | 811 | size_of_assoc += crypto_aead_ivsize(tfm); |
| @@ -837,9 +819,9 @@ static inline int ssi_buffer_mgr_aead_chain_assoc( · 7 unmodified lines | |||
| 837 | areq_ctx->assoc_buff_type = SSI_DMA_BUF_NULL; | 819 | areq_ctx->assoc_buff_type = SSI_DMA_BUF_NULL; |
| 838 | areq_ctx->assoc.nents = 0; | 820 | areq_ctx->assoc.nents = 0; |
| 839 | areq_ctx->assoc.mlli_nents = 0; | 821 | areq_ctx->assoc.mlli_nents = 0; |
| 840 | SSI_LOG_DEBUG("Chain assoc of length 0: buff_type=%s nents=%u\n", | 822 | dev_dbg(dev, "Chain assoc of length 0: buff_type=%s nents=%u\n", |
| 841 | GET_DMA_BUFFER_TYPE(areq_ctx->assoc_buff_type), | 823 | GET_DMA_BUFFER_TYPE(areq_ctx->assoc_buff_type), |
| 842 | areq_ctx->assoc.nents); | 824 | areq_ctx->assoc.nents); |
| 843 | goto chain_assoc_exit; | 825 | goto chain_assoc_exit; |
| 844 | } | 826 | } |
| 845 | 827 | ||
| @@ -853,16 +835,16 @@ static inline int ssi_buffer_mgr_aead_chain_assoc( · 7 unmodified lines | |||
| 853 | current_sg = sg_next(current_sg); | 835 | current_sg = sg_next(current_sg); |
| 854 | //if have reached the end of the sgl, then this is unexpected | 836 | //if have reached the end of the sgl, then this is unexpected |
| 855 | if (!current_sg) { | 837 | if (!current_sg) { |
| 856 | SSI_LOG_ERR("reached end of sg list. unexpected\n"); | 838 | dev_err(dev, "reached end of sg list. unexpected\n"); |
| 857 | BUG(); | 839 | return -EINVAL; |
| 858 | } | 840 | } |
| 859 | sg_index += current_sg->length; | 841 | sg_index += current_sg->length; |
| 860 | mapped_nents++; | 842 | mapped_nents++; |
| 861 | } | 843 | } |
| 862 | } | 844 | } |
| 863 | if (unlikely(mapped_nents > LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES)) { | 845 | if (unlikely(mapped_nents > LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES)) { |
| 864 | SSI_LOG_ERR("Too many fragments. current %d max %d\n", | 846 | dev_err(dev, "Too many fragments. current %d max %d\n", |
| 865 | mapped_nents, LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES); | 847 | mapped_nents, LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES); |
| 866 | return -ENOMEM; | 848 | return -ENOMEM; |
| 867 | } | 849 | } |
| 868 | areq_ctx->assoc.nents = mapped_nents; | 850 | areq_ctx->assoc.nents = mapped_nents; |
| @@ -873,9 +855,9 @@ static inline int ssi_buffer_mgr_aead_chain_assoc( · 4 unmodified lines | |||
| 873 | if (areq_ctx->ccm_hdr_size != ccm_header_size_null) { | 855 | if (areq_ctx->ccm_hdr_size != ccm_header_size_null) { |
| 874 | if (unlikely((mapped_nents + 1) > | 856 | if (unlikely((mapped_nents + 1) > |
| 875 | LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES)) { | 857 | LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES)) { |
| 876 | SSI_LOG_ERR("CCM case.Too many fragments. Current %d max %d\n", | 858 | dev_err(dev, "CCM case.Too many fragments. Current %d max %d\n", |
| 877 | (areq_ctx->assoc.nents + 1), | 859 | (areq_ctx->assoc.nents + 1), |
| 878 | LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES); | 860 | LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES); |
| 879 | rc = -ENOMEM; | 861 | rc = -ENOMEM; |
| 880 | goto chain_assoc_exit; | 862 | goto chain_assoc_exit; |
| 881 | } | 863 | } |
| @@ -889,11 +871,11 @@ static inline int ssi_buffer_mgr_aead_chain_assoc( · 7 unmodified lines | |||
| 889 | 871 | ||
| 890 | if (unlikely((do_chain) || | 872 | if (unlikely((do_chain) || |
| 891 | (areq_ctx->assoc_buff_type == SSI_DMA_BUF_MLLI))) { | 873 | (areq_ctx->assoc_buff_type == SSI_DMA_BUF_MLLI))) { |
| 892 | SSI_LOG_DEBUG("Chain assoc: buff_type=%s nents=%u\n", | 874 | dev_dbg(dev, "Chain assoc: buff_type=%s nents=%u\n", |
| 893 | GET_DMA_BUFFER_TYPE(areq_ctx->assoc_buff_type), | 875 | GET_DMA_BUFFER_TYPE(areq_ctx->assoc_buff_type), |
| 894 | areq_ctx->assoc.nents); | 876 | areq_ctx->assoc.nents); |
| 895 | ssi_buffer_mgr_add_scatterlist_entry( | 877 | ssi_buffer_mgr_add_scatterlist_entry( |
| 896 | sg_data, areq_ctx->assoc.nents, | 878 | dev, sg_data, areq_ctx->assoc.nents, |
| 897 | req->src, req->assoclen, 0, is_last, | 879 | req->src, req->assoclen, 0, is_last, |
| 898 | &areq_ctx->assoc.mlli_nents); | 880 | &areq_ctx->assoc.mlli_nents); |
| 899 | areq_ctx->assoc_buff_type = SSI_DMA_BUF_MLLI; | 881 | areq_ctx->assoc_buff_type = SSI_DMA_BUF_MLLI; |
| @@ -951,10 +933,11 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli( · 51 unmodified lines | |||
| 951 | unsigned int authsize = areq_ctx->req_authsize; | 933 | unsigned int authsize = areq_ctx->req_authsize; |
| 952 | int rc = 0, icv_nents; | 934 | int rc = 0, icv_nents; |
| 953 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); | 935 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); |
| 936 | struct device *dev = drvdata_to_dev(drvdata); | ||
| 954 | 937 | ||
| 955 | if (likely(req->src == req->dst)) { | 938 | if (likely(req->src == req->dst)) { |
| 956 | /*INPLACE*/ | 939 | /*INPLACE*/ |
| 957 | ssi_buffer_mgr_add_scatterlist_entry(sg_data, | 940 | ssi_buffer_mgr_add_scatterlist_entry(dev, sg_data, |
| 958 | areq_ctx->src.nents, | 941 | areq_ctx->src.nents, |
| 959 | areq_ctx->src_sgl, | 942 | areq_ctx->src_sgl, |
| 960 | areq_ctx->cryptlen, | 943 | areq_ctx->cryptlen, |
| @@ -962,7 +945,8 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli( · 1 unmodified line | |||
| 962 | is_last_table, | 945 | is_last_table, |
| 963 | &areq_ctx->src.mlli_nents); | 946 | &areq_ctx->src.mlli_nents); |
| 964 | 947 | ||
| 965 | icv_nents = ssi_buffer_mgr_get_aead_icv_nents(areq_ctx->src_sgl, | 948 | icv_nents = ssi_buffer_mgr_get_aead_icv_nents(dev, |
| 949 | areq_ctx->src_sgl, | ||
| 966 | areq_ctx->src.nents, | 950 | areq_ctx->src.nents, |
| 967 | authsize, | 951 | authsize, |
| 968 | *src_last_bytes, | 952 | *src_last_bytes, |
| @@ -990,7 +974,8 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli( · 21 unmodified lines | |||
| 990 | skip += crypto_aead_ivsize(tfm); | 974 | skip += crypto_aead_ivsize(tfm); |
| 991 | 975 | ||
| 992 | ssi_buffer_mgr_copy_scatterlist_portion( | 976 | ssi_buffer_mgr_copy_scatterlist_portion( |
| 993 | areq_ctx->backup_mac, req->src, | 977 | dev, areq_ctx->backup_mac, |
| 978 | req->src, | ||
| 994 | (skip + req->cryptlen - | 979 | (skip + req->cryptlen - |
| 995 | areq_ctx->req_authsize), | 980 | areq_ctx->req_authsize), |
| 996 | skip + req->cryptlen, | 981 | skip + req->cryptlen, |
| @@ -1013,14 +998,14 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli( · 16 unmodified lines | |||
| 1013 | 998 | ||
| 1014 | } else if (direct == DRV_CRYPTO_DIRECTION_DECRYPT) { | 999 | } else if (direct == DRV_CRYPTO_DIRECTION_DECRYPT) { |
| 1015 | /*NON-INPLACE and DECRYPT*/ | 1000 | /*NON-INPLACE and DECRYPT*/ |
| 1016 | ssi_buffer_mgr_add_scatterlist_entry(sg_data, | 1001 | ssi_buffer_mgr_add_scatterlist_entry(dev, sg_data, |
| 1017 | areq_ctx->src.nents, | 1002 | areq_ctx->src.nents, |
| 1018 | areq_ctx->src_sgl, | 1003 | areq_ctx->src_sgl, |
| 1019 | areq_ctx->cryptlen, | 1004 | areq_ctx->cryptlen, |
| 1020 | areq_ctx->src_offset, | 1005 | areq_ctx->src_offset, |
| 1021 | is_last_table, | 1006 | is_last_table, |
| 1022 | &areq_ctx->src.mlli_nents); | 1007 | &areq_ctx->src.mlli_nents); |
| 1023 | ssi_buffer_mgr_add_scatterlist_entry(sg_data, | 1008 | ssi_buffer_mgr_add_scatterlist_entry(dev, sg_data, |
| 1024 | areq_ctx->dst.nents, | 1009 | areq_ctx->dst.nents, |
| 1025 | areq_ctx->dst_sgl, | 1010 | areq_ctx->dst_sgl, |
| 1026 | areq_ctx->cryptlen, | 1011 | areq_ctx->cryptlen, |
| @@ -1028,7 +1013,8 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli( · 1 unmodified line | |||
| 1028 | is_last_table, | 1013 | is_last_table, |
| 1029 | &areq_ctx->dst.mlli_nents); | 1014 | &areq_ctx->dst.mlli_nents); |
| 1030 | 1015 | ||
| 1031 | icv_nents = ssi_buffer_mgr_get_aead_icv_nents(areq_ctx->src_sgl, | 1016 | icv_nents = ssi_buffer_mgr_get_aead_icv_nents(dev, |
| 1017 | areq_ctx->src_sgl, | ||
| 1032 | areq_ctx->src.nents, | 1018 | areq_ctx->src.nents, |
| 1033 | authsize, | 1019 | authsize, |
| 1034 | *src_last_bytes, | 1020 | *src_last_bytes, |
| @@ -1043,15 +1029,15 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli( · 8 unmodified lines | |||
| 1043 | * verification is made by CPU compare in order to simplify | 1029 | * verification is made by CPU compare in order to simplify |
| 1044 | * MAC verification upon request completion | 1030 | * MAC verification upon request completion |
| 1045 | */ | 1031 | */ |
| 1046 | u32 size_to_skip = req->assoclen; | 1032 | u32 size_to_skip = req->assoclen; |
| 1047 | 1033 | ||
| 1048 | if (areq_ctx->is_gcm4543) | 1034 | if (areq_ctx->is_gcm4543) |
| 1049 | size_to_skip += crypto_aead_ivsize(tfm); | 1035 | size_to_skip += crypto_aead_ivsize(tfm); |
| 1050 | 1036 | ||
| 1051 | ssi_buffer_mgr_copy_scatterlist_portion( | 1037 | ssi_buffer_mgr_copy_scatterlist_portion( |
| 1052 | areq_ctx->backup_mac, req->src, | 1038 | dev, areq_ctx->backup_mac, req->src, |
| 1053 | size_to_skip + req->cryptlen - areq_ctx->req_authsize, | 1039 | size_to_skip + req->cryptlen - areq_ctx->req_authsize, |
| 1054 | size_to_skip + req->cryptlen, SSI_SG_TO_BUF); | 1040 | size_to_skip + req->cryptlen, SSI_SG_TO_BUF); |
| 1055 | areq_ctx->icv_virt_addr = areq_ctx->backup_mac; | 1041 | areq_ctx->icv_virt_addr = areq_ctx->backup_mac; |
| 1056 | } else { /* Contig. ICV */ | 1042 | } else { /* Contig. ICV */ |
| 1057 | /*Should hanlde if the sg is not contig.*/ | 1043 | /*Should hanlde if the sg is not contig.*/ |
| @@ -1065,14 +1051,14 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli( · 7 unmodified lines | |||
| 1065 | 1051 | ||
| 1066 | } else { | 1052 | } else { |
| 1067 | /*NON-INPLACE and ENCRYPT*/ | 1053 | /*NON-INPLACE and ENCRYPT*/ |
| 1068 | ssi_buffer_mgr_add_scatterlist_entry(sg_data, | 1054 | ssi_buffer_mgr_add_scatterlist_entry(dev, sg_data, |
| 1069 | areq_ctx->dst.nents, | 1055 | areq_ctx->dst.nents, |
| 1070 | areq_ctx->dst_sgl, | 1056 | areq_ctx->dst_sgl, |
| 1071 | areq_ctx->cryptlen, | 1057 | areq_ctx->cryptlen, |
| 1072 | areq_ctx->dst_offset, | 1058 | areq_ctx->dst_offset, |
| 1073 | is_last_table, | 1059 | is_last_table, |
| 1074 | &areq_ctx->dst.mlli_nents); | 1060 | &areq_ctx->dst.mlli_nents); |
| 1075 | ssi_buffer_mgr_add_scatterlist_entry(sg_data, | 1061 | ssi_buffer_mgr_add_scatterlist_entry(dev, sg_data, |
| 1076 | areq_ctx->src.nents, | 1062 | areq_ctx->src.nents, |
| 1077 | areq_ctx->src_sgl, | 1063 | areq_ctx->src_sgl, |
| 1078 | areq_ctx->cryptlen, | 1064 | areq_ctx->cryptlen, |
| @@ -1080,7 +1066,8 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli( · 1 unmodified line | |||
| 1080 | is_last_table, | 1066 | is_last_table, |
| 1081 | &areq_ctx->src.mlli_nents); | 1067 | &areq_ctx->src.mlli_nents); |
| 1082 | 1068 | ||
| 1083 | icv_nents = ssi_buffer_mgr_get_aead_icv_nents(areq_ctx->dst_sgl, | 1069 | icv_nents = ssi_buffer_mgr_get_aead_icv_nents(dev, |
| 1070 | areq_ctx->dst_sgl, | ||
| 1084 | areq_ctx->dst.nents, | 1071 | areq_ctx->dst.nents, |
| 1085 | authsize, | 1072 | authsize, |
| 1086 | *dst_last_bytes, | 1073 | *dst_last_bytes, |
| @@ -1115,7 +1102,7 @@ static inline int ssi_buffer_mgr_aead_chain_data( · 28 unmodified lines | |||
| 1115 | bool is_last_table, bool do_chain) | 1102 | bool is_last_table, bool do_chain) |
| 1116 | { | 1103 | { |
| 1117 | struct aead_req_ctx *areq_ctx = aead_request_ctx(req); | 1104 | struct aead_req_ctx *areq_ctx = aead_request_ctx(req); |
| 1118 | struct device *dev = &drvdata->plat_dev->dev; | 1105 | struct device *dev = drvdata_to_dev(drvdata); |
| 1119 | enum drv_crypto_direction direct = areq_ctx->gen_ctx.op_type; | 1106 | enum drv_crypto_direction direct = areq_ctx->gen_ctx.op_type; |
| 1120 | unsigned int authsize = areq_ctx->req_authsize; | 1107 | unsigned int authsize = areq_ctx->req_authsize; |
| 1121 | int src_last_bytes = 0, dst_last_bytes = 0; | 1108 | int src_last_bytes = 0, dst_last_bytes = 0; |
| @@ -1134,10 +1121,9 @@ static inline int ssi_buffer_mgr_aead_chain_data( · 12 unmodified lines | |||
| 1134 | 1121 | ||
| 1135 | offset = size_to_skip; | 1122 | offset = size_to_skip; |
| 1136 | 1123 | ||
| 1137 | if (!sg_data) { | 1124 | if (!sg_data) |
| 1138 | rc = -EINVAL; | 1125 | return -EINVAL; |
| 1139 | goto chain_data_exit; | 1126 | |
| 1140 | } | ||
| 1141 | areq_ctx->src_sgl = req->src; | 1127 | areq_ctx->src_sgl = req->src; |
| 1142 | areq_ctx->dst_sgl = req->dst; | 1128 | areq_ctx->dst_sgl = req->dst; |
| 1143 | 1129 | ||
| @@ -1145,7 +1131,10 @@ static inline int ssi_buffer_mgr_aead_chain_data( · 1 unmodified line | |||
| 1145 | size_for_map += crypto_aead_ivsize(tfm); | 1131 | size_for_map += crypto_aead_ivsize(tfm); |
| 1146 | 1132 | ||
| 1147 | size_for_map += (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ? authsize : 0; | 1133 | size_for_map += (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ? authsize : 0; |
| 1148 | src_mapped_nents = ssi_buffer_mgr_get_sgl_nents(req->src, size_for_map, &src_last_bytes, &chained); | 1134 | src_mapped_nents = ssi_buffer_mgr_get_sgl_nents(dev, req->src, |
| 1135 | size_for_map, | ||
| 1136 | &src_last_bytes, | ||
| 1137 | &chained); | ||
| 1149 | sg_index = areq_ctx->src_sgl->length; | 1138 | sg_index = areq_ctx->src_sgl->length; |
| 1150 | //check where the data starts | 1139 | //check where the data starts |
| 1151 | while (sg_index <= size_to_skip) { | 1140 | while (sg_index <= size_to_skip) { |
| @@ -1153,15 +1142,15 @@ static inline int ssi_buffer_mgr_aead_chain_data( · 1 unmodified line | |||
| 1153 | areq_ctx->src_sgl = sg_next(areq_ctx->src_sgl); | 1142 | areq_ctx->src_sgl = sg_next(areq_ctx->src_sgl); |
| 1154 | //if have reached the end of the sgl, then this is unexpected | 1143 | //if have reached the end of the sgl, then this is unexpected |
| 1155 | if (!areq_ctx->src_sgl) { | 1144 | if (!areq_ctx->src_sgl) { |
| 1156 | SSI_LOG_ERR("reached end of sg list. unexpected\n"); | 1145 | dev_err(dev, "reached end of sg list. unexpected\n"); |
| 1157 | BUG(); | 1146 | return -EINVAL; |
| 1158 | } | 1147 | } |
| 1159 | sg_index += areq_ctx->src_sgl->length; | 1148 | sg_index += areq_ctx->src_sgl->length; |
| 1160 | src_mapped_nents--; | 1149 | src_mapped_nents--; |
| 1161 | } | 1150 | } |
| 1162 | if (unlikely(src_mapped_nents > LLI_MAX_NUM_OF_DATA_ENTRIES)) { | 1151 | if (unlikely(src_mapped_nents > LLI_MAX_NUM_OF_DATA_ENTRIES)) { |
| 1163 | SSI_LOG_ERR("Too many fragments. current %d max %d\n", | 1152 | dev_err(dev, "Too many fragments. current %d max %d\n", |
| 1164 | src_mapped_nents, LLI_MAX_NUM_OF_DATA_ENTRIES); | 1153 | src_mapped_nents, LLI_MAX_NUM_OF_DATA_ENTRIES); |
| 1165 | return -ENOMEM; | 1154 | return -ENOMEM; |
| 1166 | } | 1155 | } |
| 1167 | 1156 | ||
| @@ -1187,7 +1176,10 @@ static inline int ssi_buffer_mgr_aead_chain_data( · 19 unmodified lines | |||
| 1187 | } | 1176 | } |
| 1188 | } | 1177 | } |
| 1189 | 1178 | ||
| 1190 | dst_mapped_nents = ssi_buffer_mgr_get_sgl_nents(req->dst, size_for_map, &dst_last_bytes, &chained); | 1179 | dst_mapped_nents = ssi_buffer_mgr_get_sgl_nents(dev, req->dst, |
| 1180 | size_for_map, | ||
| 1181 | &dst_last_bytes, | ||
| 1182 | &chained); | ||
| 1191 | sg_index = areq_ctx->dst_sgl->length; | 1183 | sg_index = areq_ctx->dst_sgl->length; |
| 1192 | offset = size_to_skip; | 1184 | offset = size_to_skip; |
| 1193 | 1185 | ||
| @@ -1197,15 +1189,15 @@ static inline int ssi_buffer_mgr_aead_chain_data( · 3 unmodified lines | |||
| 1197 | areq_ctx->dst_sgl = sg_next(areq_ctx->dst_sgl); | 1189 | areq_ctx->dst_sgl = sg_next(areq_ctx->dst_sgl); |
| 1198 | //if have reached the end of the sgl, then this is unexpected | 1190 | //if have reached the end of the sgl, then this is unexpected |
| 1199 | if (!areq_ctx->dst_sgl) { | 1191 | if (!areq_ctx->dst_sgl) { |
| 1200 | SSI_LOG_ERR("reached end of sg list. unexpected\n"); | 1192 | dev_err(dev, "reached end of sg list. unexpected\n"); |
| 1201 | BUG(); | 1193 | return -EINVAL; |
| 1202 | } | 1194 | } |
| 1203 | sg_index += areq_ctx->dst_sgl->length; | 1195 | sg_index += areq_ctx->dst_sgl->length; |
| 1204 | dst_mapped_nents--; | 1196 | dst_mapped_nents--; |
| 1205 | } | 1197 | } |
| 1206 | if (unlikely(dst_mapped_nents > LLI_MAX_NUM_OF_DATA_ENTRIES)) { | 1198 | if (unlikely(dst_mapped_nents > LLI_MAX_NUM_OF_DATA_ENTRIES)) { |
| 1207 | SSI_LOG_ERR("Too many fragments. current %d max %d\n", | 1199 | dev_err(dev, "Too many fragments. current %d max %d\n", |
| 1208 | dst_mapped_nents, LLI_MAX_NUM_OF_DATA_ENTRIES); | 1200 | dst_mapped_nents, LLI_MAX_NUM_OF_DATA_ENTRIES); |
| 1209 | return -ENOMEM; | 1201 | return -ENOMEM; |
| 1210 | } | 1202 | } |
| 1211 | areq_ctx->dst.nents = dst_mapped_nents; | 1203 | areq_ctx->dst.nents = dst_mapped_nents; |
| @@ -1285,7 +1277,7 @@ int ssi_buffer_mgr_map_aead_request( · 73 unmodified lines | |||
| 1285 | { | 1277 | { |
| 1286 | struct aead_req_ctx *areq_ctx = aead_request_ctx(req); | 1278 | struct aead_req_ctx *areq_ctx = aead_request_ctx(req); |
| 1287 | struct mlli_params *mlli_params = &areq_ctx->mlli_params; | 1279 | struct mlli_params *mlli_params = &areq_ctx->mlli_params; |
| 1288 | struct device *dev = &drvdata->plat_dev->dev; | 1280 | struct device *dev = drvdata_to_dev(drvdata); |
| 1289 | struct buffer_array sg_data; | 1281 | struct buffer_array sg_data; |
| 1290 | unsigned int authsize = areq_ctx->req_authsize; | 1282 | unsigned int authsize = areq_ctx->req_authsize; |
| 1291 | struct buff_mgr_handle *buff_mgr = drvdata->buff_mgr_handle; | 1283 | struct buff_mgr_handle *buff_mgr = drvdata->buff_mgr_handle; |
| @@ -1312,7 +1304,7 @@ int ssi_buffer_mgr_map_aead_request( · 20 unmodified lines | |||
| 1312 | * data memory overriding that caused by cache coherence problem. | 1304 | * data memory overriding that caused by cache coherence problem. |
| 1313 | */ | 1305 | */ |
| 1314 | ssi_buffer_mgr_copy_scatterlist_portion( | 1306 | ssi_buffer_mgr_copy_scatterlist_portion( |
| 1315 | areq_ctx->backup_mac, req->src, | 1307 | dev, areq_ctx->backup_mac, req->src, |
| 1316 | size_to_skip + req->cryptlen - areq_ctx->req_authsize, | 1308 | size_to_skip + req->cryptlen - areq_ctx->req_authsize, |
| 1317 | size_to_skip + req->cryptlen, SSI_SG_TO_BUF); | 1309 | size_to_skip + req->cryptlen, SSI_SG_TO_BUF); |
| 1318 | } | 1310 | } |
| @@ -1327,8 +1319,8 @@ int ssi_buffer_mgr_map_aead_request( · 8 unmodified lines | |||
| 1327 | MAX_MAC_SIZE, | 1319 | MAX_MAC_SIZE, |
| 1328 | DMA_BIDIRECTIONAL); | 1320 | DMA_BIDIRECTIONAL); |
| 1329 | if (unlikely(dma_mapping_error(dev, areq_ctx->mac_buf_dma_addr))) { | 1321 | if (unlikely(dma_mapping_error(dev, areq_ctx->mac_buf_dma_addr))) { |
| 1330 | SSI_LOG_ERR("Mapping mac_buf %u B at va=%pK for DMA failed\n", | 1322 | dev_err(dev, "Mapping mac_buf %u B at va=%pK for DMA failed\n", |
| 1331 | MAX_MAC_SIZE, areq_ctx->mac_buf); | 1323 | MAX_MAC_SIZE, areq_ctx->mac_buf); |
| 1332 | rc = -ENOMEM; | 1324 | rc = -ENOMEM; |
| 1333 | goto aead_map_failure; | 1325 | goto aead_map_failure; |
| 1334 | } | 1326 | } |
| @@ -1340,9 +1332,10 @@ int ssi_buffer_mgr_map_aead_request( · 5 unmodified lines | |||
| 1340 | DMA_TO_DEVICE); | 1332 | DMA_TO_DEVICE); |
| 1341 | 1333 | ||
| 1342 | if (unlikely(dma_mapping_error(dev, areq_ctx->ccm_iv0_dma_addr))) { | 1334 | if (unlikely(dma_mapping_error(dev, areq_ctx->ccm_iv0_dma_addr))) { |
| 1343 | SSI_LOG_ERR("Mapping mac_buf %u B at va=%pK " | 1335 | dev_err(dev, "Mapping mac_buf %u B at va=%pK for DMA failed\n", |
| 1344 | "for DMA failed\n", AES_BLOCK_SIZE, | 1336 | AES_BLOCK_SIZE, |
| 1345 | (areq_ctx->ccm_config + CCM_CTR_COUNT_0_OFFSET)); | 1337 | (areq_ctx->ccm_config + |
| 1338 | CCM_CTR_COUNT_0_OFFSET)); | ||
| 1346 | areq_ctx->ccm_iv0_dma_addr = 0; | 1339 | areq_ctx->ccm_iv0_dma_addr = 0; |
| 1347 | rc = -ENOMEM; | 1340 | rc = -ENOMEM; |
| 1348 | goto aead_map_failure; | 1341 | goto aead_map_failure; |
| @@ -1362,8 +1355,8 @@ int ssi_buffer_mgr_map_aead_request( · 13 unmodified lines | |||
| 1362 | AES_BLOCK_SIZE, | 1355 | AES_BLOCK_SIZE, |
| 1363 | DMA_BIDIRECTIONAL); | 1356 | DMA_BIDIRECTIONAL); |
| 1364 | if (unlikely(dma_mapping_error(dev, areq_ctx->hkey_dma_addr))) { | 1357 | if (unlikely(dma_mapping_error(dev, areq_ctx->hkey_dma_addr))) { |
| 1365 | SSI_LOG_ERR("Mapping hkey %u B at va=%pK for DMA failed\n", | 1358 | dev_err(dev, "Mapping hkey %u B at va=%pK for DMA failed\n", |
| 1366 | AES_BLOCK_SIZE, areq_ctx->hkey); | 1359 | AES_BLOCK_SIZE, areq_ctx->hkey); |
| 1367 | rc = -ENOMEM; | 1360 | rc = -ENOMEM; |
| 1368 | goto aead_map_failure; | 1361 | goto aead_map_failure; |
| 1369 | } | 1362 | } |
| @@ -1373,8 +1366,8 @@ int ssi_buffer_mgr_map_aead_request( · 3 unmodified lines | |||
| 1373 | AES_BLOCK_SIZE, | 1366 | AES_BLOCK_SIZE, |
| 1374 | DMA_TO_DEVICE); | 1367 | DMA_TO_DEVICE); |
| 1375 | if (unlikely(dma_mapping_error(dev, areq_ctx->gcm_block_len_dma_addr))) { | 1368 | if (unlikely(dma_mapping_error(dev, areq_ctx->gcm_block_len_dma_addr))) { |
| 1376 | SSI_LOG_ERR("Mapping gcm_len_block %u B at va=%pK for DMA failed\n", | 1369 | dev_err(dev, "Mapping gcm_len_block %u B at va=%pK for DMA failed\n", |
| 1377 | AES_BLOCK_SIZE, &areq_ctx->gcm_len_block); | 1370 | AES_BLOCK_SIZE, &areq_ctx->gcm_len_block); |
| 1378 | rc = -ENOMEM; | 1371 | rc = -ENOMEM; |
| 1379 | goto aead_map_failure; | 1372 | goto aead_map_failure; |
| 1380 | } | 1373 | } |
| @@ -1385,9 +1378,8 @@ int ssi_buffer_mgr_map_aead_request( · 4 unmodified lines | |||
| 1385 | DMA_TO_DEVICE); | 1378 | DMA_TO_DEVICE); |
| 1386 | 1379 | ||
| 1387 | if (unlikely(dma_mapping_error(dev, areq_ctx->gcm_iv_inc1_dma_addr))) { | 1380 | if (unlikely(dma_mapping_error(dev, areq_ctx->gcm_iv_inc1_dma_addr))) { |
| 1388 | SSI_LOG_ERR("Mapping gcm_iv_inc1 %u B at va=%pK " | 1381 | dev_err(dev, "Mapping gcm_iv_inc1 %u B at va=%pK for DMA failed\n", |
| 1389 | "for DMA failed\n", AES_BLOCK_SIZE, | 1382 | AES_BLOCK_SIZE, (areq_ctx->gcm_iv_inc1)); |
| 1390 | (areq_ctx->gcm_iv_inc1)); | ||
| 1391 | areq_ctx->gcm_iv_inc1_dma_addr = 0; | 1383 | areq_ctx->gcm_iv_inc1_dma_addr = 0; |
| 1392 | rc = -ENOMEM; | 1384 | rc = -ENOMEM; |
| 1393 | goto aead_map_failure; | 1385 | goto aead_map_failure; |
| @@ -1399,9 +1391,8 @@ int ssi_buffer_mgr_map_aead_request( · 5 unmodified lines | |||
| 1399 | DMA_TO_DEVICE); | 1391 | DMA_TO_DEVICE); |
| 1400 | 1392 | ||
| 1401 | if (unlikely(dma_mapping_error(dev, areq_ctx->gcm_iv_inc2_dma_addr))) { | 1393 | if (unlikely(dma_mapping_error(dev, areq_ctx->gcm_iv_inc2_dma_addr))) { |
| 1402 | SSI_LOG_ERR("Mapping gcm_iv_inc2 %u B at va=%pK " | 1394 | dev_err(dev, "Mapping gcm_iv_inc2 %u B at va=%pK for DMA failed\n", |
| 1403 | "for DMA failed\n", AES_BLOCK_SIZE, | 1395 | AES_BLOCK_SIZE, (areq_ctx->gcm_iv_inc2)); |
| 1404 | (areq_ctx->gcm_iv_inc2)); | ||
| 1405 | areq_ctx->gcm_iv_inc2_dma_addr = 0; | 1396 | areq_ctx->gcm_iv_inc2_dma_addr = 0; |
| 1406 | rc = -ENOMEM; | 1397 | rc = -ENOMEM; |
| 1407 | goto aead_map_failure; | 1398 | goto aead_map_failure; |
| @@ -1481,9 +1472,10 @@ int ssi_buffer_mgr_map_aead_request( · 73 unmodified lines | |||
| 1481 | goto aead_map_failure; | 1472 | goto aead_map_failure; |
| 1482 | 1473 | ||
| 1483 | ssi_buffer_mgr_update_aead_mlli_nents(drvdata, req); | 1474 | ssi_buffer_mgr_update_aead_mlli_nents(drvdata, req); |
| 1484 | SSI_LOG_DEBUG("assoc params mn %d\n", areq_ctx->assoc.mlli_nents); | 1475 | dev_dbg(dev, "assoc params mn %d\n", |
| 1485 | SSI_LOG_DEBUG("src params mn %d\n", areq_ctx->src.mlli_nents); | 1476 | areq_ctx->assoc.mlli_nents); |
| 1486 | SSI_LOG_DEBUG("dst params mn %d\n", areq_ctx->dst.mlli_nents); | 1477 | dev_dbg(dev, "src params mn %d\n", areq_ctx->src.mlli_nents); |
| 1478 | dev_dbg(dev, "dst params mn %d\n", areq_ctx->dst.mlli_nents); | ||
| 1487 | } | 1479 | } |
| 1488 | return 0; | 1480 | return 0; |
| 1489 | 1481 | ||
| @@ -1496,7 +1488,7 @@ int ssi_buffer_mgr_map_hash_request_final( · 6 unmodified lines | |||
| 1496 | struct ssi_drvdata *drvdata, void *ctx, struct scatterlist *src, unsigned int nbytes, bool do_update) | 1488 | struct ssi_drvdata *drvdata, void *ctx, struct scatterlist *src, unsigned int nbytes, bool do_update) |
| 1497 | { | 1489 | { |
| 1498 | struct ahash_req_ctx *areq_ctx = (struct ahash_req_ctx *)ctx; | 1490 | struct ahash_req_ctx *areq_ctx = (struct ahash_req_ctx *)ctx; |
| 1499 | struct device *dev = &drvdata->plat_dev->dev; | 1491 | struct device *dev = drvdata_to_dev(drvdata); |
| 1500 | u8 *curr_buff = areq_ctx->buff_index ? areq_ctx->buff1 : | 1492 | u8 *curr_buff = areq_ctx->buff_index ? areq_ctx->buff1 : |
| 1501 | areq_ctx->buff0; | 1493 | areq_ctx->buff0; |
| 1502 | u32 *curr_buff_cnt = areq_ctx->buff_index ? &areq_ctx->buff1_cnt : | 1494 | u32 *curr_buff_cnt = areq_ctx->buff_index ? &areq_ctx->buff1_cnt : |
| @@ -1507,11 +1499,8 @@ int ssi_buffer_mgr_map_hash_request_final( · 4 unmodified lines | |||
| 1507 | u32 dummy = 0; | 1499 | u32 dummy = 0; |
| 1508 | u32 mapped_nents = 0; | 1500 | u32 mapped_nents = 0; |
| 1509 | 1501 | ||
| 1510 | SSI_LOG_DEBUG(" final params : curr_buff=%pK " | 1502 | dev_dbg(dev, "final params : curr_buff=%pK curr_buff_cnt=0x%X nbytes = 0x%X src=%pK curr_index=%u\n", |
| 1511 | "curr_buff_cnt=0x%X nbytes = 0x%X " | 1503 | curr_buff, *curr_buff_cnt, nbytes, src, areq_ctx->buff_index); |
| 1512 | "src=%pK curr_index=%u\n", | ||
| 1513 | curr_buff, *curr_buff_cnt, nbytes, | ||
| 1514 | src, areq_ctx->buff_index); | ||
| 1515 | /* Init the type of the dma buffer */ | 1504 | /* Init the type of the dma buffer */ |
| 1516 | areq_ctx->data_dma_buf_type = SSI_DMA_BUF_NULL; | 1505 | areq_ctx->data_dma_buf_type = SSI_DMA_BUF_NULL; |
| 1517 | mlli_params->curr_pool = NULL; | 1506 | mlli_params->curr_pool = NULL; |
| @@ -1557,7 +1546,7 @@ int ssi_buffer_mgr_map_hash_request_final( · 39 unmodified lines | |||
| 1557 | if (unlikely(areq_ctx->data_dma_buf_type == SSI_DMA_BUF_MLLI)) { | 1546 | if (unlikely(areq_ctx->data_dma_buf_type == SSI_DMA_BUF_MLLI)) { |
| 1558 | mlli_params->curr_pool = buff_mgr->mlli_buffs_pool; | 1547 | mlli_params->curr_pool = buff_mgr->mlli_buffs_pool; |
| 1559 | /* add the src data to the sg_data */ | 1548 | /* add the src data to the sg_data */ |
| 1560 | ssi_buffer_mgr_add_scatterlist_entry(&sg_data, | 1549 | ssi_buffer_mgr_add_scatterlist_entry(dev, &sg_data, |
| 1561 | areq_ctx->in_nents, | 1550 | areq_ctx->in_nents, |
| 1562 | src, nbytes, 0, true, | 1551 | src, nbytes, 0, true, |
| 1563 | &areq_ctx->mlli_nents); | 1552 | &areq_ctx->mlli_nents); |
| @@ -1568,8 +1557,8 @@ int ssi_buffer_mgr_map_hash_request_final( · 4 unmodified lines | |||
| 1568 | } | 1557 | } |
| 1569 | /* change the buffer index for the unmap function */ | 1558 | /* change the buffer index for the unmap function */ |
| 1570 | areq_ctx->buff_index = (areq_ctx->buff_index ^ 1); | 1559 | areq_ctx->buff_index = (areq_ctx->buff_index ^ 1); |
| 1571 | SSI_LOG_DEBUG("areq_ctx->data_dma_buf_type = %s\n", | 1560 | dev_dbg(dev, "areq_ctx->data_dma_buf_type = %s\n", |
| 1572 | GET_DMA_BUFFER_TYPE(areq_ctx->data_dma_buf_type)); | 1561 | GET_DMA_BUFFER_TYPE(areq_ctx->data_dma_buf_type)); |
| 1573 | return 0; | 1562 | return 0; |
| 1574 | 1563 | ||
| 1575 | fail_unmap_din: | 1564 | fail_unmap_din: |
| @@ -1586,7 +1575,7 @@ int ssi_buffer_mgr_map_hash_request_update( · 10 unmodified lines | |||
| 1586 | struct ssi_drvdata *drvdata, void *ctx, struct scatterlist *src, unsigned int nbytes, unsigned int block_size) | 1575 | struct ssi_drvdata *drvdata, void *ctx, struct scatterlist *src, unsigned int nbytes, unsigned int block_size) |
| 1587 | { | 1576 | { |
| 1588 | struct ahash_req_ctx *areq_ctx = (struct ahash_req_ctx *)ctx; | 1577 | struct ahash_req_ctx *areq_ctx = (struct ahash_req_ctx *)ctx; |
| 1589 | struct device *dev = &drvdata->plat_dev->dev; | 1578 | struct device *dev = drvdata_to_dev(drvdata); |
| 1590 | u8 *curr_buff = areq_ctx->buff_index ? areq_ctx->buff1 : | 1579 | u8 *curr_buff = areq_ctx->buff_index ? areq_ctx->buff1 : |
| 1591 | areq_ctx->buff0; | 1580 | areq_ctx->buff0; |
| 1592 | u32 *curr_buff_cnt = areq_ctx->buff_index ? &areq_ctx->buff1_cnt : | 1581 | u32 *curr_buff_cnt = areq_ctx->buff_index ? &areq_ctx->buff1_cnt : |
| @@ -1604,11 +1593,8 @@ int ssi_buffer_mgr_map_hash_request_update( · 11 unmodified lines | |||
| 1604 | u32 dummy = 0; | 1593 | u32 dummy = 0; |
| 1605 | u32 mapped_nents = 0; | 1594 | u32 mapped_nents = 0; |
| 1606 | 1595 | ||
| 1607 | SSI_LOG_DEBUG(" update params : curr_buff=%pK " | 1596 | dev_dbg(dev, " update params : curr_buff=%pK curr_buff_cnt=0x%X nbytes=0x%X src=%pK curr_index=%u\n", |
| 1608 | "curr_buff_cnt=0x%X nbytes=0x%X " | 1597 | curr_buff, *curr_buff_cnt, nbytes, src, areq_ctx->buff_index); |
| 1609 | "src=%pK curr_index=%u\n", | ||
| 1610 | curr_buff, *curr_buff_cnt, nbytes, | ||
| 1611 | src, areq_ctx->buff_index); | ||
| 1612 | /* Init the type of the dma buffer */ | 1598 | /* Init the type of the dma buffer */ |
| 1613 | areq_ctx->data_dma_buf_type = SSI_DMA_BUF_NULL; | 1599 | areq_ctx->data_dma_buf_type = SSI_DMA_BUF_NULL; |
| 1614 | mlli_params->curr_pool = NULL; | 1600 | mlli_params->curr_pool = NULL; |
| @@ -1617,14 +1603,11 @@ int ssi_buffer_mgr_map_hash_request_update( · 2 unmodified lines | |||
| 1617 | areq_ctx->in_nents = 0; | 1603 | areq_ctx->in_nents = 0; |
| 1618 | 1604 | ||
| 1619 | if (unlikely(total_in_len < block_size)) { | 1605 | if (unlikely(total_in_len < block_size)) { |
| 1620 | SSI_LOG_DEBUG(" less than one block: curr_buff=%pK " | 1606 | dev_dbg(dev, " less than one block: curr_buff=%pK *curr_buff_cnt=0x%X copy_to=%pK\n", |
| 1621 | "*curr_buff_cnt=0x%X copy_to=%pK\n", | 1607 | curr_buff, *curr_buff_cnt, &curr_buff[*curr_buff_cnt]); |
| 1622 | curr_buff, *curr_buff_cnt, | ||
| 1623 | &curr_buff[*curr_buff_cnt]); | ||
| 1624 | areq_ctx->in_nents = | 1608 | areq_ctx->in_nents = |
| 1625 | ssi_buffer_mgr_get_sgl_nents(src, | 1609 | ssi_buffer_mgr_get_sgl_nents(dev, src, nbytes, &dummy, |
| 1626 | nbytes, | 1610 | NULL); |
| 1627 | &dummy, NULL); | ||
| 1628 | sg_copy_to_buffer(src, areq_ctx->in_nents, | 1611 | sg_copy_to_buffer(src, areq_ctx->in_nents, |
| 1629 | &curr_buff[*curr_buff_cnt], nbytes); | 1612 | &curr_buff[*curr_buff_cnt], nbytes); |
| 1630 | *curr_buff_cnt += nbytes; | 1613 | *curr_buff_cnt += nbytes; |
| @@ -1636,17 +1619,15 @@ int ssi_buffer_mgr_map_hash_request_update( · 5 unmodified lines | |||
| 1636 | /* update data len */ | 1619 | /* update data len */ |
| 1637 | update_data_len = total_in_len - *next_buff_cnt; | 1620 | update_data_len = total_in_len - *next_buff_cnt; |
| 1638 | 1621 | ||
| 1639 | SSI_LOG_DEBUG(" temp length : *next_buff_cnt=0x%X " | 1622 | dev_dbg(dev, " temp length : *next_buff_cnt=0x%X update_data_len=0x%X\n", |
| 1640 | "update_data_len=0x%X\n", | ||
| 1641 | *next_buff_cnt, update_data_len); | 1623 | *next_buff_cnt, update_data_len); |
| 1642 | 1624 | ||
| 1643 | /* Copy the new residue to next buffer */ | 1625 | /* Copy the new residue to next buffer */ |
| 1644 | if (*next_buff_cnt != 0) { | 1626 | if (*next_buff_cnt != 0) { |
| 1645 | SSI_LOG_DEBUG(" handle residue: next buff %pK skip data %u" | 1627 | dev_dbg(dev, " handle residue: next buff %pK skip data %u residue %u\n", |
| 1646 | " residue %u\n", next_buff, | 1628 | next_buff, (update_data_len - *curr_buff_cnt), |
| 1647 | (update_data_len - *curr_buff_cnt), | 1629 | *next_buff_cnt); |
| 1648 | *next_buff_cnt); | 1630 | ssi_buffer_mgr_copy_scatterlist_portion(dev, next_buff, src, |
| 1649 | ssi_buffer_mgr_copy_scatterlist_portion(next_buff, src, | ||
| 1650 | (update_data_len - *curr_buff_cnt), | 1631 | (update_data_len - *curr_buff_cnt), |
| 1651 | nbytes, SSI_SG_TO_BUF); | 1632 | nbytes, SSI_SG_TO_BUF); |
| 1652 | /* change the buffer index for next operation */ | 1633 | /* change the buffer index for next operation */ |
| @@ -1688,7 +1669,7 @@ int ssi_buffer_mgr_map_hash_request_update( · 35 unmodified lines | |||
| 1688 | if (unlikely(areq_ctx->data_dma_buf_type == SSI_DMA_BUF_MLLI)) { | 1669 | if (unlikely(areq_ctx->data_dma_buf_type == SSI_DMA_BUF_MLLI)) { |
| 1689 | mlli_params->curr_pool = buff_mgr->mlli_buffs_pool; | 1670 | mlli_params->curr_pool = buff_mgr->mlli_buffs_pool; |
| 1690 | /* add the src data to the sg_data */ | 1671 | /* add the src data to the sg_data */ |
| 1691 | ssi_buffer_mgr_add_scatterlist_entry(&sg_data, | 1672 | ssi_buffer_mgr_add_scatterlist_entry(dev, &sg_data, |
| 1692 | areq_ctx->in_nents, | 1673 | areq_ctx->in_nents, |
| 1693 | src, | 1674 | src, |
| 1694 | (update_data_len - *curr_buff_cnt), | 1675 | (update_data_len - *curr_buff_cnt), |
| @@ -1725,29 +1706,26 @@ void ssi_buffer_mgr_unmap_hash_request( · 30 unmodified lines | |||
| 1725 | *allocated and should be released | 1706 | *allocated and should be released |
| 1726 | */ | 1707 | */ |
| 1727 | if (areq_ctx->mlli_params.curr_pool) { | 1708 | if (areq_ctx->mlli_params.curr_pool) { |
| 1728 | SSI_LOG_DEBUG("free MLLI buffer: dma=%pad virt=%pK\n", | 1709 | dev_dbg(dev, "free MLLI buffer: dma=%pad virt=%pK\n", |
| 1729 | areq_ctx->mlli_params.mlli_dma_addr, | 1710 | &areq_ctx->mlli_params.mlli_dma_addr, |
| 1730 | areq_ctx->mlli_params.mlli_virt_addr); | 1711 | areq_ctx->mlli_params.mlli_virt_addr); |
| 1731 | dma_pool_free(areq_ctx->mlli_params.curr_pool, | 1712 | dma_pool_free(areq_ctx->mlli_params.curr_pool, |
| 1732 | areq_ctx->mlli_params.mlli_virt_addr, | 1713 | areq_ctx->mlli_params.mlli_virt_addr, |
| 1733 | areq_ctx->mlli_params.mlli_dma_addr); | 1714 | areq_ctx->mlli_params.mlli_dma_addr); |
| 1734 | } | 1715 | } |
| 1735 | 1716 | ||
| 1736 | if ((src) && likely(areq_ctx->in_nents != 0)) { | 1717 | if ((src) && likely(areq_ctx->in_nents != 0)) { |
| 1737 | SSI_LOG_DEBUG("Unmapped sg src: virt=%pK dma=%pad len=0x%X\n", | 1718 | dev_dbg(dev, "Unmapped sg src: virt=%pK dma=%pad len=0x%X\n", |
| 1738 | sg_virt(src), | 1719 | sg_virt(src), &sg_dma_address(src), sg_dma_len(src)); |
| 1739 | sg_dma_address(src), | ||
| 1740 | sg_dma_len(src)); | ||
| 1741 | dma_unmap_sg(dev, src, | 1720 | dma_unmap_sg(dev, src, |
| 1742 | areq_ctx->in_nents, DMA_TO_DEVICE); | 1721 | areq_ctx->in_nents, DMA_TO_DEVICE); |
| 1743 | } | 1722 | } |
| 1744 | 1723 | ||
| 1745 | if (*prev_len != 0) { | 1724 | if (*prev_len != 0) { |
| 1746 | SSI_LOG_DEBUG("Unmapped buffer: areq_ctx->buff_sg=%pK" | 1725 | dev_dbg(dev, "Unmapped buffer: areq_ctx->buff_sg=%pK dma=%pad len 0x%X\n", |
| 1747 | " dma=%pad len 0x%X\n", | 1726 | sg_virt(areq_ctx->buff_sg), |
| 1748 | sg_virt(areq_ctx->buff_sg), | 1727 | &sg_dma_address(areq_ctx->buff_sg), |
| 1749 | sg_dma_address(areq_ctx->buff_sg), | 1728 | sg_dma_len(areq_ctx->buff_sg)); |
| 1750 | sg_dma_len(areq_ctx->buff_sg)); | ||
| 1751 | dma_unmap_sg(dev, areq_ctx->buff_sg, 1, DMA_TO_DEVICE); | 1729 | dma_unmap_sg(dev, areq_ctx->buff_sg, 1, DMA_TO_DEVICE); |
| 1752 | if (!do_revert) { | 1730 | if (!do_revert) { |
| 1753 | /* clean the previous data length for update operation */ | 1731 | /* clean the previous data length for update operation */ |
| @@ -1761,7 +1739,7 @@ void ssi_buffer_mgr_unmap_hash_request( · 7 unmodified lines | |||
| 1761 | int ssi_buffer_mgr_init(struct ssi_drvdata *drvdata) | 1739 | int ssi_buffer_mgr_init(struct ssi_drvdata *drvdata) |
| 1762 | { | 1740 | { |
| 1763 | struct buff_mgr_handle *buff_mgr_handle; | 1741 | struct buff_mgr_handle *buff_mgr_handle; |
| 1764 | struct device *dev = &drvdata->plat_dev->dev; | 1742 | struct device *dev = drvdata_to_dev(drvdata); |
| 1765 | 1743 | ||
| 1766 | buff_mgr_handle = kmalloc(sizeof(*buff_mgr_handle), GFP_KERNEL); | 1744 | buff_mgr_handle = kmalloc(sizeof(*buff_mgr_handle), GFP_KERNEL); |
| 1767 | if (!buff_mgr_handle) | 1745 | if (!buff_mgr_handle) |
| @@ -80,7 +80,10 @@ int ssi_buffer_mgr_map_hash_request_update(struct ssi_drvdata *drvdata, void *ct · 79 unmodified lines | |||
| 80 | 80 | ||
| 81 | void ssi_buffer_mgr_unmap_hash_request(struct device *dev, void *ctx, struct scatterlist *src, bool do_revert); | 81 | void ssi_buffer_mgr_unmap_hash_request(struct device *dev, void *ctx, struct scatterlist *src, bool do_revert); |
| 82 | 82 | ||
| 83 | void ssi_buffer_mgr_copy_scatterlist_portion(u8 *dest, struct scatterlist *sg, u32 to_skip, u32 end, enum ssi_sg_cpy_direct direct); | 83 | void ssi_buffer_mgr_copy_scatterlist_portion(struct device *dev, u8 *dest, |
| 84 | struct scatterlist *sg, | ||
| 85 | u32 to_skip, u32 end, | ||
| 86 | enum ssi_sg_cpy_direct direct); | ||
| 84 | 87 | ||
| 85 | void ssi_buffer_mgr_zero_sgl(struct scatterlist *sgl, u32 data_len); | 88 | void ssi_buffer_mgr_zero_sgl(struct scatterlist *sgl, u32 data_len); |
| 86 | 89 | ||
| @@ -181,45 +181,42 @@ static int ssi_blkcipher_init(struct crypto_tfm *tfm) · 180 unmodified lines | |||
| 181 | struct crypto_alg *alg = tfm->__crt_alg; | 181 | struct crypto_alg *alg = tfm->__crt_alg; |
| 182 | struct ssi_crypto_alg *ssi_alg = | 182 | struct ssi_crypto_alg *ssi_alg = |
| 183 | container_of(alg, struct ssi_crypto_alg, crypto_alg); | 183 | container_of(alg, struct ssi_crypto_alg, crypto_alg); |
| 184 | struct device *dev; | 184 | struct device *dev = drvdata_to_dev(ssi_alg->drvdata); |
| 185 | int rc = 0; | 185 | int rc = 0; |
| 186 | unsigned int max_key_buf_size = get_max_keysize(tfm); | 186 | unsigned int max_key_buf_size = get_max_keysize(tfm); |
| 187 | 187 | ||
| 188 | SSI_LOG_DEBUG("Initializing context @%p for %s\n", | 188 | dev_dbg(dev, "Initializing context @%p for %s\n", ctx_p, |
| 189 | ctx_p, crypto_tfm_alg_name(tfm)); | 189 | crypto_tfm_alg_name(tfm)); |
| 190 | 190 | ||
| 191 | ctx_p->cipher_mode = ssi_alg->cipher_mode; | 191 | ctx_p->cipher_mode = ssi_alg->cipher_mode; |
| 192 | ctx_p->flow_mode = ssi_alg->flow_mode; | 192 | ctx_p->flow_mode = ssi_alg->flow_mode; |
| 193 | ctx_p->drvdata = ssi_alg->drvdata; | 193 | ctx_p->drvdata = ssi_alg->drvdata; |
| 194 | dev = &ctx_p->drvdata->plat_dev->dev; | ||
| 195 | 194 | ||
| 196 | /* Allocate key buffer, cache line aligned */ | 195 | /* Allocate key buffer, cache line aligned */ |
| 197 | ctx_p->user.key = kmalloc(max_key_buf_size, GFP_KERNEL | GFP_DMA); | 196 | ctx_p->user.key = kmalloc(max_key_buf_size, GFP_KERNEL | GFP_DMA); |
| 198 | if (!ctx_p->user.key) { | 197 | if (!ctx_p->user.key) |
| 199 | SSI_LOG_ERR("Allocating key buffer in context failed\n"); | 198 | return -ENOMEM; |
| 200 | rc = -ENOMEM; | 199 | |
| 201 | } | 200 | dev_dbg(dev, "Allocated key buffer in context. key=@%p\n", |
| 202 | SSI_LOG_DEBUG("Allocated key buffer in context. key=@%p\n", | 201 | ctx_p->user.key); |
| 203 | ctx_p->user.key); | ||
| 204 | 202 | ||
| 205 | /* Map key buffer */ | 203 | /* Map key buffer */ |
| 206 | ctx_p->user.key_dma_addr = dma_map_single(dev, (void *)ctx_p->user.key, | 204 | ctx_p->user.key_dma_addr = dma_map_single(dev, (void *)ctx_p->user.key, |
| 207 | max_key_buf_size, | 205 | max_key_buf_size, |
| 208 | DMA_TO_DEVICE); | 206 | DMA_TO_DEVICE); |
| 209 | if (dma_mapping_error(dev, ctx_p->user.key_dma_addr)) { | 207 | if (dma_mapping_error(dev, ctx_p->user.key_dma_addr)) { |
| 210 | SSI_LOG_ERR("Mapping Key %u B at va=%pK for DMA failed\n", | 208 | dev_err(dev, "Mapping Key %u B at va=%pK for DMA failed\n", |
| 211 | max_key_buf_size, ctx_p->user.key); | 209 | max_key_buf_size, ctx_p->user.key); |
| 212 | return -ENOMEM; | 210 | return -ENOMEM; |
| 213 | } | 211 | } |
| 214 | SSI_LOG_DEBUG("Mapped key %u B at va=%pK to dma=%pad\n", | 212 | dev_dbg(dev, "Mapped key %u B at va=%pK to dma=%pad\n", |
| 215 | max_key_buf_size, ctx_p->user.key, | 213 | max_key_buf_size, ctx_p->user.key, &ctx_p->user.key_dma_addr); |
| 216 | ctx_p->user.key_dma_addr); | ||
| 217 | 214 | ||
| 218 | if (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) { | 215 | if (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) { |
| 219 | /* Alloc hash tfm for essiv */ | 216 | /* Alloc hash tfm for essiv */ |
| 220 | ctx_p->shash_tfm = crypto_alloc_shash("sha256-generic", 0, 0); | 217 | ctx_p->shash_tfm = crypto_alloc_shash("sha256-generic", 0, 0); |
| 221 | if (IS_ERR(ctx_p->shash_tfm)) { | 218 | if (IS_ERR(ctx_p->shash_tfm)) { |
| 222 | SSI_LOG_ERR("Error allocating hash tfm for ESSIV.\n"); | 219 | dev_err(dev, "Error allocating hash tfm for ESSIV.\n"); |
| 223 | return PTR_ERR(ctx_p->shash_tfm); | 220 | return PTR_ERR(ctx_p->shash_tfm); |
| 224 | } | 221 | } |
| 225 | } | 222 | } |
| @@ -230,11 +227,11 @@ static int ssi_blkcipher_init(struct crypto_tfm *tfm) · 4 unmodified lines | |||
| 230 | static void ssi_blkcipher_exit(struct crypto_tfm *tfm) | 227 | static void ssi_blkcipher_exit(struct crypto_tfm *tfm) |
| 231 | { | 228 | { |
| 232 | struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); | 229 | struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); |
| 233 | struct device *dev = &ctx_p->drvdata->plat_dev->dev; | 230 | struct device *dev = drvdata_to_dev(ctx_p->drvdata); |
| 234 | unsigned int max_key_buf_size = get_max_keysize(tfm); | 231 | unsigned int max_key_buf_size = get_max_keysize(tfm); |
| 235 | 232 | ||
| 236 | SSI_LOG_DEBUG("Clearing context @%p for %s\n", | 233 | dev_dbg(dev, "Clearing context @%p for %s\n", |
| 237 | crypto_tfm_ctx(tfm), crypto_tfm_alg_name(tfm)); | 234 | crypto_tfm_ctx(tfm), crypto_tfm_alg_name(tfm)); |
| 238 | 235 | ||
| 239 | if (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) { | 236 | if (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) { |
| 240 | /* Free hash tfm for essiv */ | 237 | /* Free hash tfm for essiv */ |
| @@ -245,12 +242,12 @@ static void ssi_blkcipher_exit(struct crypto_tfm *tfm) · 4 unmodified lines | |||
| 245 | /* Unmap key buffer */ | 242 | /* Unmap key buffer */ |
| 246 | dma_unmap_single(dev, ctx_p->user.key_dma_addr, max_key_buf_size, | 243 | dma_unmap_single(dev, ctx_p->user.key_dma_addr, max_key_buf_size, |
| 247 | DMA_TO_DEVICE); | 244 | DMA_TO_DEVICE); |
| 248 | SSI_LOG_DEBUG("Unmapped key buffer key_dma_addr=%pad\n", | 245 | dev_dbg(dev, "Unmapped key buffer key_dma_addr=%pad\n", |
| 249 | ctx_p->user.key_dma_addr); | 246 | &ctx_p->user.key_dma_addr); |
| 250 | 247 | ||
| 251 | /* Free key buffer in context */ | 248 | /* Free key buffer in context */ |
| 252 | kfree(ctx_p->user.key); | 249 | kfree(ctx_p->user.key); |
| 253 | SSI_LOG_DEBUG("Free key buffer in context. key=@%p\n", ctx_p->user.key); | 250 | dev_dbg(dev, "Free key buffer in context. key=@%p\n", ctx_p->user.key); |
| 254 | } | 251 | } |
| 255 | 252 | ||
| 256 | struct tdes_keys { | 253 | struct tdes_keys { |
| @@ -298,16 +295,14 @@ static int ssi_blkcipher_setkey(struct crypto_tfm *tfm, · 41 unmodified lines | |||
| 298 | unsigned int keylen) | 295 | unsigned int keylen) |
| 299 | { | 296 | { |
| 300 | struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); | 297 | struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); |
| 301 | struct device *dev = &ctx_p->drvdata->plat_dev->dev; | 298 | struct device *dev = drvdata_to_dev(ctx_p->drvdata); |
| 302 | u32 tmp[DES_EXPKEY_WORDS]; | 299 | u32 tmp[DES_EXPKEY_WORDS]; |
| 303 | unsigned int max_key_buf_size = get_max_keysize(tfm); | 300 | unsigned int max_key_buf_size = get_max_keysize(tfm); |
| 304 | 301 | ||
| 305 | SSI_LOG_DEBUG("Setting key in context @%p for %s. keylen=%u\n", | 302 | dev_dbg(dev, "Setting key in context @%p for %s. keylen=%u\n", |
| 306 | ctx_p, crypto_tfm_alg_name(tfm), keylen); | 303 | ctx_p, crypto_tfm_alg_name(tfm), keylen); |
| 307 | dump_byte_array("key", (u8 *)key, keylen); | 304 | dump_byte_array("key", (u8 *)key, keylen); |
| 308 | 305 | ||
| 309 | SSI_LOG_DEBUG("after FIPS check"); | ||
| 310 | |||
| 311 | /* STAT_PHASE_0: Init and sanity checks */ | 306 | /* STAT_PHASE_0: Init and sanity checks */ |
| 312 | 307 | ||
| 313 | #if SSI_CC_HAS_MULTI2 | 308 | #if SSI_CC_HAS_MULTI2 |
| @@ -317,7 +312,7 @@ static int ssi_blkcipher_setkey(struct crypto_tfm *tfm, · 3 unmodified lines | |||
| 317 | #endif /*SSI_CC_HAS_MULTI2*/ | 312 | #endif /*SSI_CC_HAS_MULTI2*/ |
| 318 | 313 | ||
| 319 | if (unlikely(validate_keys_sizes(ctx_p, keylen) != 0)) { | 314 | if (unlikely(validate_keys_sizes(ctx_p, keylen) != 0)) { |
| 320 | SSI_LOG_ERR("Unsupported key size %d.\n", keylen); | 315 | dev_err(dev, "Unsupported key size %d.\n", keylen); |
| 321 | crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); | 316 | crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); |
| 322 | return -EINVAL; | 317 | return -EINVAL; |
| 323 | } | 318 | } |
| @@ -327,13 +322,14 @@ static int ssi_blkcipher_setkey(struct crypto_tfm *tfm, · 3 unmodified lines | |||
| 327 | struct arm_hw_key_info *hki = (struct arm_hw_key_info *)key; | 322 | struct arm_hw_key_info *hki = (struct arm_hw_key_info *)key; |
| 328 | 323 | ||
| 329 | if (unlikely(ctx_p->flow_mode != S_DIN_to_AES)) { | 324 | if (unlikely(ctx_p->flow_mode != S_DIN_to_AES)) { |
| 330 | SSI_LOG_ERR("HW key not supported for non-AES flows\n"); | 325 | dev_err(dev, "HW key not supported for non-AES flows\n"); |
| 331 | return -EINVAL; | 326 | return -EINVAL; |
| 332 | } | 327 | } |
| 333 | 328 | ||
| 334 | ctx_p->hw.key1_slot = hw_key_to_cc_hw_key(hki->hw_key1); | 329 | ctx_p->hw.key1_slot = hw_key_to_cc_hw_key(hki->hw_key1); |
| 335 | if (unlikely(ctx_p->hw.key1_slot == END_OF_KEYS)) { | 330 | if (unlikely(ctx_p->hw.key1_slot == END_OF_KEYS)) { |
| 336 | SSI_LOG_ERR("Unsupported hw key1 number (%d)\n", hki->hw_key1); | 331 | dev_err(dev, "Unsupported hw key1 number (%d)\n", |
| 332 | hki->hw_key1); | ||
| 337 | return -EINVAL; | 333 | return -EINVAL; |
| 338 | } | 334 | } |
| 339 | 335 | ||
| @@ -341,18 +337,20 @@ static int ssi_blkcipher_setkey(struct crypto_tfm *tfm, · 1 unmodified line | |||
| 341 | (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) || | 337 | (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) || |
| 342 | (ctx_p->cipher_mode == DRV_CIPHER_BITLOCKER)) { | 338 | (ctx_p->cipher_mode == DRV_CIPHER_BITLOCKER)) { |
| 343 | if (unlikely(hki->hw_key1 == hki->hw_key2)) { | 339 | if (unlikely(hki->hw_key1 == hki->hw_key2)) { |
| 344 | SSI_LOG_ERR("Illegal hw key numbers (%d,%d)\n", hki->hw_key1, hki->hw_key2); | 340 | dev_err(dev, "Illegal hw key numbers (%d,%d)\n", |
| 341 | hki->hw_key1, hki->hw_key2); | ||
| 345 | return -EINVAL; | 342 | return -EINVAL; |
| 346 | } | 343 | } |
| 347 | ctx_p->hw.key2_slot = hw_key_to_cc_hw_key(hki->hw_key2); | 344 | ctx_p->hw.key2_slot = hw_key_to_cc_hw_key(hki->hw_key2); |
| 348 | if (unlikely(ctx_p->hw.key2_slot == END_OF_KEYS)) { | 345 | if (unlikely(ctx_p->hw.key2_slot == END_OF_KEYS)) { |
| 349 | SSI_LOG_ERR("Unsupported hw key2 number (%d)\n", hki->hw_key2); | 346 | dev_err(dev, "Unsupported hw key2 number (%d)\n", |
| 347 | hki->hw_key2); | ||
| 350 | return -EINVAL; | 348 | return -EINVAL; |
| 351 | } | 349 | } |
| 352 | } | 350 | } |
| 353 | 351 | ||
| 354 | ctx_p->keylen = keylen; | 352 | ctx_p->keylen = keylen; |
| 355 | SSI_LOG_DEBUG("ssi_is_hw_key ret 0"); | 353 | dev_dbg(dev, "ssi_is_hw_key ret 0"); |
| 356 | 354 | ||
| 357 | return 0; | 355 | return 0; |
| 358 | } | 356 | } |
| @@ -362,19 +360,19 @@ static int ssi_blkcipher_setkey(struct crypto_tfm *tfm, · 3 unmodified lines | |||
| 362 | if (unlikely(!des_ekey(tmp, key)) && | 360 | if (unlikely(!des_ekey(tmp, key)) && |
| 363 | (crypto_tfm_get_flags(tfm) & CRYPTO_TFM_REQ_WEAK_KEY)) { | 361 | (crypto_tfm_get_flags(tfm) & CRYPTO_TFM_REQ_WEAK_KEY)) { |
| 364 | tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY; | 362 | tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY; |
| 365 | SSI_LOG_DEBUG("weak DES key"); | 363 | dev_dbg(dev, "weak DES key"); |
| 366 | return -EINVAL; | 364 | return -EINVAL; |
| 367 | } | 365 | } |
| 368 | } | 366 | } |
| 369 | if ((ctx_p->cipher_mode == DRV_CIPHER_XTS) && | 367 | if ((ctx_p->cipher_mode == DRV_CIPHER_XTS) && |
| 370 | xts_check_key(tfm, key, keylen) != 0) { | 368 | xts_check_key(tfm, key, keylen) != 0) { |
| 371 | SSI_LOG_DEBUG("weak XTS key"); | 369 | dev_dbg(dev, "weak XTS key"); |
| 372 | return -EINVAL; | 370 | return -EINVAL; |
| 373 | } | 371 | } |
| 374 | if ((ctx_p->flow_mode == S_DIN_to_DES) && | 372 | if ((ctx_p->flow_mode == S_DIN_to_DES) && |
| 375 | (keylen == DES3_EDE_KEY_SIZE) && | 373 | (keylen == DES3_EDE_KEY_SIZE) && |
| 376 | ssi_verify_3des_keys(key, keylen) != 0) { | 374 | ssi_verify_3des_keys(key, keylen) != 0) { |
| 377 | SSI_LOG_DEBUG("weak 3DES key"); | 375 | dev_dbg(dev, "weak 3DES key"); |
| 378 | return -EINVAL; | 376 | return -EINVAL; |
| 379 | } | 377 | } |
| 380 | 378 | ||
| @@ -389,7 +387,7 @@ static int ssi_blkcipher_setkey(struct crypto_tfm *tfm, · 8 unmodified lines | |||
| 389 | if (ctx_p->key_round_number < CC_MULTI2_MIN_NUM_ROUNDS || | 387 | if (ctx_p->key_round_number < CC_MULTI2_MIN_NUM_ROUNDS || |
| 390 | ctx_p->key_round_number > CC_MULTI2_MAX_NUM_ROUNDS) { | 388 | ctx_p->key_round_number > CC_MULTI2_MAX_NUM_ROUNDS) { |
| 391 | crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); | 389 | crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); |
| 392 | SSI_LOG_DEBUG("SSI_CC_HAS_MULTI2 einval"); | 390 | dev_dbg(dev, "SSI_CC_HAS_MULTI2 einval"); |
| 393 | return -EINVAL; | 391 | return -EINVAL; |
| 394 | #endif /*SSI_CC_HAS_MULTI2*/ | 392 | #endif /*SSI_CC_HAS_MULTI2*/ |
| 395 | } else { | 393 | } else { |
| @@ -407,7 +405,7 @@ static int ssi_blkcipher_setkey(struct crypto_tfm *tfm, · 11 unmodified lines | |||
| 407 | 405 | ||
| 408 | err = crypto_shash_digest(desc, ctx_p->user.key, key_len, ctx_p->user.key + key_len); | 406 | err = crypto_shash_digest(desc, ctx_p->user.key, key_len, ctx_p->user.key + key_len); |
| 409 | if (err) { | 407 | if (err) { |
| 410 | SSI_LOG_ERR("Failed to hash ESSIV key.\n"); | 408 | dev_err(dev, "Failed to hash ESSIV key.\n"); |
| 411 | return err; | 409 | return err; |
| 412 | } | 410 | } |
| 413 | } | 411 | } |
| @@ -416,7 +414,7 @@ static int ssi_blkcipher_setkey(struct crypto_tfm *tfm, · 2 unmodified lines | |||
| 416 | max_key_buf_size, DMA_TO_DEVICE); | 414 | max_key_buf_size, DMA_TO_DEVICE); |
| 417 | ctx_p->keylen = keylen; | 415 | ctx_p->keylen = keylen; |
| 418 | 416 | ||
| 419 | SSI_LOG_DEBUG("return safely"); | 417 | dev_dbg(dev, "return safely"); |
| 420 | return 0; | 418 | return 0; |
| 421 | } | 419 | } |
| 422 | 420 | ||
| @@ -430,6 +428,7 @@ ssi_blkcipher_create_setup_desc( · 7 unmodified lines | |||
| 430 | unsigned int *seq_size) | 428 | unsigned int *seq_size) |
| 431 | { | 429 | { |
| 432 | struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); | 430 | struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); |
| 431 | struct device *dev = drvdata_to_dev(ctx_p->drvdata); | ||
| 433 | int cipher_mode = ctx_p->cipher_mode; | 432 | int cipher_mode = ctx_p->cipher_mode; |
| 434 | int flow_mode = ctx_p->flow_mode; | 433 | int flow_mode = ctx_p->flow_mode; |
| 435 | int direction = req_ctx->gen_ctx.op_type; | 434 | int direction = req_ctx->gen_ctx.op_type; |
| @@ -540,8 +539,7 @@ ssi_blkcipher_create_setup_desc( · 104 unmodified lines | |||
| 540 | (*seq_size)++; | 539 | (*seq_size)++; |
| 541 | break; | 540 | break; |
| 542 | default: | 541 | default: |
| 543 | SSI_LOG_ERR("Unsupported cipher mode (%d)\n", cipher_mode); | 542 | dev_err(dev, "Unsupported cipher mode (%d)\n", cipher_mode); |
| 544 | BUG(); | ||
| 545 | } | 543 | } |
| 546 | } | 544 | } |
| 547 | 545 | ||
| @@ -601,6 +599,7 @@ ssi_blkcipher_create_data_desc( · 53 unmodified lines | |||
| 601 | unsigned int *seq_size) | 599 | unsigned int *seq_size) |
| 602 | { | 600 | { |
| 603 | struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); | 601 | struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); |
| 602 | struct device *dev = drvdata_to_dev(ctx_p->drvdata); | ||
| 604 | unsigned int flow_mode = ctx_p->flow_mode; | 603 | unsigned int flow_mode = ctx_p->flow_mode; |
| 605 | 604 | ||
| 606 | switch (ctx_p->flow_mode) { | 605 | switch (ctx_p->flow_mode) { |
| @@ -616,15 +615,15 @@ ssi_blkcipher_create_data_desc( · 9 unmodified lines | |||
| 616 | break; | 615 | break; |
| 617 | #endif /*SSI_CC_HAS_MULTI2*/ | 616 | #endif /*SSI_CC_HAS_MULTI2*/ |
| 618 | default: | 617 | default: |
| 619 | SSI_LOG_ERR("invalid flow mode, flow_mode = %d\n", flow_mode); | 618 | dev_err(dev, "invalid flow mode, flow_mode = %d\n", flow_mode); |
| 620 | return; | 619 | return; |
| 621 | } | 620 | } |
| 622 | /* Process */ | 621 | /* Process */ |
| 623 | if (likely(req_ctx->dma_buf_type == SSI_DMA_BUF_DLLI)) { | 622 | if (likely(req_ctx->dma_buf_type == SSI_DMA_BUF_DLLI)) { |
| 624 | SSI_LOG_DEBUG(" data params addr %pad length 0x%X\n", | 623 | dev_dbg(dev, " data params addr %pad length 0x%X\n", |
| 625 | sg_dma_address(src), nbytes); | 624 | &sg_dma_address(src), nbytes); |
| 626 | SSI_LOG_DEBUG(" data params addr %pad length 0x%X\n", | 625 | dev_dbg(dev, " data params addr %pad length 0x%X\n", |
| 627 | sg_dma_address(dst), nbytes); | 626 | &sg_dma_address(dst), nbytes); |
| 628 | hw_desc_init(&desc[*seq_size]); | 627 | hw_desc_init(&desc[*seq_size]); |
| 629 | set_din_type(&desc[*seq_size], DMA_DLLI, sg_dma_address(src), | 628 | set_din_type(&desc[*seq_size], DMA_DLLI, sg_dma_address(src), |
| 630 | nbytes, NS_BIT); | 629 | nbytes, NS_BIT); |
| @@ -637,9 +636,8 @@ ssi_blkcipher_create_data_desc( · 6 unmodified lines | |||
| 637 | (*seq_size)++; | 636 | (*seq_size)++; |
| 638 | } else { | 637 | } else { |
| 639 | /* bypass */ | 638 | /* bypass */ |
| 640 | SSI_LOG_DEBUG(" bypass params addr %pad " | 639 | dev_dbg(dev, " bypass params addr %pad length 0x%X addr 0x%08X\n", |
| 641 | "length 0x%X addr 0x%08X\n", | 640 | &req_ctx->mlli_params.mlli_dma_addr, |
| 642 | req_ctx->mlli_params.mlli_dma_addr, | ||
| 643 | req_ctx->mlli_params.mlli_len, | 641 | req_ctx->mlli_params.mlli_len, |
| 644 | (unsigned int)ctx_p->drvdata->mlli_sram_addr); | 642 | (unsigned int)ctx_p->drvdata->mlli_sram_addr); |
| 645 | hw_desc_init(&desc[*seq_size]); | 643 | hw_desc_init(&desc[*seq_size]); |
| @@ -657,21 +655,18 @@ ssi_blkcipher_create_data_desc( · 11 unmodified lines | |||
| 657 | ctx_p->drvdata->mlli_sram_addr, | 655 | ctx_p->drvdata->mlli_sram_addr, |
| 658 | req_ctx->in_mlli_nents, NS_BIT); | 656 | req_ctx->in_mlli_nents, NS_BIT); |
| 659 | if (req_ctx->out_nents == 0) { | 657 | if (req_ctx->out_nents == 0) { |
| 660 | SSI_LOG_DEBUG(" din/dout params addr 0x%08X " | 658 | dev_dbg(dev, " din/dout params addr 0x%08X addr 0x%08X\n", |
| 661 | "addr 0x%08X\n", | 659 | (unsigned int)ctx_p->drvdata->mlli_sram_addr, |
| 662 | (unsigned int)ctx_p->drvdata->mlli_sram_addr, | 660 | (unsigned int)ctx_p->drvdata->mlli_sram_addr); |
| 663 | (unsigned int)ctx_p->drvdata->mlli_sram_addr); | ||
| 664 | set_dout_mlli(&desc[*seq_size], | 661 | set_dout_mlli(&desc[*seq_size], |
| 665 | ctx_p->drvdata->mlli_sram_addr, | 662 | ctx_p->drvdata->mlli_sram_addr, |
| 666 | req_ctx->in_mlli_nents, NS_BIT, | 663 | req_ctx->in_mlli_nents, NS_BIT, |
| 667 | (!areq ? 0 : 1)); | 664 | (!areq ? 0 : 1)); |
| 668 | } else { | 665 | } else { |
| 669 | SSI_LOG_DEBUG(" din/dout params " | 666 | dev_dbg(dev, " din/dout params addr 0x%08X addr 0x%08X\n", |
| 670 | "addr 0x%08X addr 0x%08X\n", | ||
| 671 | (unsigned int)ctx_p->drvdata->mlli_sram_addr, | 667 | (unsigned int)ctx_p->drvdata->mlli_sram_addr, |
| 672 | (unsigned int)ctx_p->drvdata->mlli_sram_addr + | 668 | (unsigned int)ctx_p->drvdata->mlli_sram_addr + |
| 673 | (u32)LLI_ENTRY_BYTE_SIZE * | 669 | (u32)LLI_ENTRY_BYTE_SIZE * req_ctx->in_nents); |
| 674 | req_ctx->in_nents); | ||
| 675 | set_dout_mlli(&desc[*seq_size], | 670 | set_dout_mlli(&desc[*seq_size], |
| 676 | (ctx_p->drvdata->mlli_sram_addr + | 671 | (ctx_p->drvdata->mlli_sram_addr + |
| 677 | (LLI_ENTRY_BYTE_SIZE * | 672 | (LLI_ENTRY_BYTE_SIZE * |
| @@ -697,16 +692,10 @@ static int ssi_blkcipher_complete(struct device *dev, · 19 unmodified lines | |||
| 697 | void __iomem *cc_base) | 692 | void __iomem *cc_base) |
| 698 | { | 693 | { |
| 699 | int completion_error = 0; | 694 | int completion_error = 0; |
| 700 | u32 inflight_counter; | ||
| 701 | struct ablkcipher_request *req = (struct ablkcipher_request *)areq; | 695 | struct ablkcipher_request *req = (struct ablkcipher_request *)areq; |
| 702 | 696 | ||
| 703 | ssi_buffer_mgr_unmap_blkcipher_request(dev, req_ctx, ivsize, src, dst); | 697 | ssi_buffer_mgr_unmap_blkcipher_request(dev, req_ctx, ivsize, src, dst); |
| 704 | 698 | kfree(req_ctx->iv); | |
| 705 | /*Set the inflight couter value to local variable*/ | ||
| 706 | inflight_counter = ctx_p->drvdata->inflight_counter; | ||
| 707 | /*Decrease the inflight counter*/ | ||
| 708 | if (ctx_p->flow_mode == BYPASS && ctx_p->drvdata->inflight_counter > 0) | ||
| 709 | ctx_p->drvdata->inflight_counter--; | ||
| 710 | 699 | ||
| 711 | if (areq) { | 700 | if (areq) { |
| 712 | /* | 701 | /* |
| @@ -742,20 +731,20 @@ static int ssi_blkcipher_process( · 29 unmodified lines | |||
| 742 | enum drv_crypto_direction direction) | 731 | enum drv_crypto_direction direction) |
| 743 | { | 732 | { |
| 744 | struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); | 733 | struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); |
| 745 | struct device *dev = &ctx_p->drvdata->plat_dev->dev; | 734 | struct device *dev = drvdata_to_dev(ctx_p->drvdata); |
| 746 | struct cc_hw_desc desc[MAX_ABLKCIPHER_SEQ_LEN]; | 735 | struct cc_hw_desc desc[MAX_ABLKCIPHER_SEQ_LEN]; |
| 747 | struct ssi_crypto_req ssi_req = {}; | 736 | struct ssi_crypto_req ssi_req = {}; |
| 748 | int rc, seq_len = 0, cts_restore_flag = 0; | 737 | int rc, seq_len = 0, cts_restore_flag = 0; |
| 749 | 738 | ||
| 750 | SSI_LOG_DEBUG("%s areq=%p info=%p nbytes=%d\n", | 739 | dev_dbg(dev, "%s areq=%p info=%p nbytes=%d\n", |
| 751 | ((direction == DRV_CRYPTO_DIRECTION_ENCRYPT) ? "Encrypt" : "Decrypt"), | 740 | ((direction == DRV_CRYPTO_DIRECTION_ENCRYPT) ? |
| 752 | areq, info, nbytes); | 741 | "Encrypt" : "Decrypt"), areq, info, nbytes); |
| 753 | 742 | ||
| 754 | /* STAT_PHASE_0: Init and sanity checks */ | 743 | /* STAT_PHASE_0: Init and sanity checks */ |
| 755 | 744 | ||
| 756 | /* TODO: check data length according to mode */ | 745 | /* TODO: check data length according to mode */ |
| 757 | if (unlikely(validate_data_size(ctx_p, nbytes))) { | 746 | if (unlikely(validate_data_size(ctx_p, nbytes))) { |
| 758 | SSI_LOG_ERR("Unsupported data size %d.\n", nbytes); | 747 | dev_err(dev, "Unsupported data size %d.\n", nbytes); |
| 759 | crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_BLOCK_LEN); | 748 | crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_BLOCK_LEN); |
| 760 | rc = -EINVAL; | 749 | rc = -EINVAL; |
| 761 | goto exit_process; | 750 | goto exit_process; |
| @@ -765,6 +754,17 @@ static int ssi_blkcipher_process( · 3 unmodified lines | |||
| 765 | rc = 0; | 754 | rc = 0; |
| 766 | goto exit_process; | 755 | goto exit_process; |
| 767 | } | 756 | } |
| 757 | |||
| 758 | /* The IV we are handed may be allocted from the stack so | ||
| 759 | * we must copy it to a DMAable buffer before use. | ||
| 760 | */ | ||
| 761 | req_ctx->iv = kmalloc(ivsize, GFP_KERNEL); | ||
| 762 | if (!req_ctx->iv) { | ||
| 763 | rc = -ENOMEM; | ||
| 764 | goto exit_process; | ||
| 765 | } | ||
| 766 | memcpy(req_ctx->iv, info, ivsize); | ||
| 767 | |||
| 768 | /*For CTS in case of data size aligned to 16 use CBC mode*/ | 768 | /*For CTS in case of data size aligned to 16 use CBC mode*/ |
| 769 | if (((nbytes % AES_BLOCK_SIZE) == 0) && (ctx_p->cipher_mode == DRV_CIPHER_CBC_CTS)) { | 769 | if (((nbytes % AES_BLOCK_SIZE) == 0) && (ctx_p->cipher_mode == DRV_CIPHER_CBC_CTS)) { |
| 770 | ctx_p->cipher_mode = DRV_CIPHER_CBC; | 770 | ctx_p->cipher_mode = DRV_CIPHER_CBC; |
| @@ -786,9 +786,11 @@ static int ssi_blkcipher_process( · 15 unmodified lines | |||
| 786 | 786 | ||
| 787 | /* STAT_PHASE_1: Map buffers */ | 787 | /* STAT_PHASE_1: Map buffers */ |
| 788 | 788 | ||
| 789 | rc = ssi_buffer_mgr_map_blkcipher_request(ctx_p->drvdata, req_ctx, ivsize, nbytes, info, src, dst); | 789 | rc = ssi_buffer_mgr_map_blkcipher_request(ctx_p->drvdata, req_ctx, |
| 790 | ivsize, nbytes, req_ctx->iv, | ||
| 791 | src, dst); | ||
| 790 | if (unlikely(rc != 0)) { | 792 | if (unlikely(rc != 0)) { |
| 791 | SSI_LOG_ERR("map_request() failed\n"); | 793 | dev_err(dev, "map_request() failed\n"); |
| 792 | goto exit_process; | 794 | goto exit_process; |
| 793 | } | 795 | } |
| 794 | 796 | ||
| @@ -838,8 +840,10 @@ exit_process: · 43 unmodified lines | |||
| 838 | if (cts_restore_flag != 0) | 840 | if (cts_restore_flag != 0) |
| 839 | ctx_p->cipher_mode = DRV_CIPHER_CBC_CTS; | 841 | ctx_p->cipher_mode = DRV_CIPHER_CBC_CTS; |
| 840 | 842 | ||
| 841 | if (rc != -EINPROGRESS) | 843 | if (rc != -EINPROGRESS) { |
| 842 | kfree(req_ctx->backup_info); | 844 | kfree(req_ctx->backup_info); |
| 845 | kfree(req_ctx->iv); | ||
| 846 | } | ||
| 843 | 847 | ||
| 844 | return rc; | 848 | return rc; |
| 845 | } | 849 | } |
| @@ -1245,16 +1249,15 @@ static struct ssi_alg_template blkcipher_algs[] = { · 399 unmodified lines | |||
| 1245 | }; | 1249 | }; |
| 1246 | 1250 | ||
| 1247 | static | 1251 | static |
| 1248 | struct ssi_crypto_alg *ssi_ablkcipher_create_alg(struct ssi_alg_template *template) | 1252 | struct ssi_crypto_alg *ssi_ablkcipher_create_alg(struct ssi_alg_template |
| 1253 | *template, struct device *dev) | ||
| 1249 | { | 1254 | { |
| 1250 | struct ssi_crypto_alg *t_alg; | 1255 | struct ssi_crypto_alg *t_alg; |
| 1251 | struct crypto_alg *alg; | 1256 | struct crypto_alg *alg; |
| 1252 | 1257 | ||
| 1253 | t_alg = kzalloc(sizeof(*t_alg), GFP_KERNEL); | 1258 | t_alg = kzalloc(sizeof(*t_alg), GFP_KERNEL); |
| 1254 | if (!t_alg) { | 1259 | if (!t_alg) |
| 1255 | SSI_LOG_ERR("failed to allocate t_alg\n"); | ||
| 1256 | return ERR_PTR(-ENOMEM); | 1260 | return ERR_PTR(-ENOMEM); |
| 1257 | } | ||
| 1258 | 1261 | ||
| 1259 | alg = &t_alg->crypto_alg; | 1262 | alg = &t_alg->crypto_alg; |
| 1260 | 1263 | ||
| @@ -1285,10 +1288,6 @@ int ssi_ablkcipher_free(struct ssi_drvdata *drvdata) · 24 unmodified lines | |||
| 1285 | struct ssi_crypto_alg *t_alg, *n; | 1288 | struct ssi_crypto_alg *t_alg, *n; |
| 1286 | struct ssi_blkcipher_handle *blkcipher_handle = | 1289 | struct ssi_blkcipher_handle *blkcipher_handle = |
| 1287 | drvdata->blkcipher_handle; | 1290 | drvdata->blkcipher_handle; |
| 1288 | struct device *dev; | ||
| 1289 | |||
| 1290 | dev = &drvdata->plat_dev->dev; | ||
| 1291 | |||
| 1292 | if (blkcipher_handle) { | 1291 | if (blkcipher_handle) { |
| 1293 | /* Remove registered algs */ | 1292 | /* Remove registered algs */ |
| 1294 | list_for_each_entry_safe(t_alg, n, | 1293 | list_for_each_entry_safe(t_alg, n, |
| @@ -1308,6 +1307,7 @@ int ssi_ablkcipher_alloc(struct ssi_drvdata *drvdata) · 13 unmodified lines | |||
| 1308 | { | 1307 | { |
| 1309 | struct ssi_blkcipher_handle *ablkcipher_handle; | 1308 | struct ssi_blkcipher_handle *ablkcipher_handle; |
| 1310 | struct ssi_crypto_alg *t_alg; | 1309 | struct ssi_crypto_alg *t_alg; |
| 1310 | struct device *dev = drvdata_to_dev(drvdata); | ||
| 1311 | int rc = -ENOMEM; | 1311 | int rc = -ENOMEM; |
| 1312 | int alg; | 1312 | int alg; |
| 1313 | 1313 | ||
| @@ -1315,37 +1315,38 @@ int ssi_ablkcipher_alloc(struct ssi_drvdata *drvdata) · 1 unmodified line | |||
| 1315 | if (!ablkcipher_handle) | 1315 | if (!ablkcipher_handle) |
| 1316 | return -ENOMEM; | 1316 | return -ENOMEM; |
| 1317 | 1317 | ||
| 1318 | drvdata->blkcipher_handle = ablkcipher_handle; | ||
| 1319 | |||
| 1320 | INIT_LIST_HEAD(&ablkcipher_handle->blkcipher_alg_list); | 1318 | INIT_LIST_HEAD(&ablkcipher_handle->blkcipher_alg_list); |
| 1319 | drvdata->blkcipher_handle = ablkcipher_handle; | ||
| 1321 | 1320 | ||
| 1322 | /* Linux crypto */ | 1321 | /* Linux crypto */ |
| 1323 | SSI_LOG_DEBUG("Number of algorithms = %zu\n", ARRAY_SIZE(blkcipher_algs)); | 1322 | dev_dbg(dev, "Number of algorithms = %zu\n", |
| 1323 | ARRAY_SIZE(blkcipher_algs)); | ||
| 1324 | for (alg = 0; alg < ARRAY_SIZE(blkcipher_algs); alg++) { | 1324 | for (alg = 0; alg < ARRAY_SIZE(blkcipher_algs); alg++) { |
| 1325 | SSI_LOG_DEBUG("creating %s\n", blkcipher_algs[alg].driver_name); | 1325 | dev_dbg(dev, "creating %s\n", blkcipher_algs[alg].driver_name); |
| 1326 | t_alg = ssi_ablkcipher_create_alg(&blkcipher_algs[alg]); | 1326 | t_alg = ssi_ablkcipher_create_alg(&blkcipher_algs[alg], dev); |
| 1327 | if (IS_ERR(t_alg)) { | 1327 | if (IS_ERR(t_alg)) { |
| 1328 | rc = PTR_ERR(t_alg); | 1328 | rc = PTR_ERR(t_alg); |
| 1329 | SSI_LOG_ERR("%s alg allocation failed\n", | 1329 | dev_err(dev, "%s alg allocation failed\n", |
| 1330 | blkcipher_algs[alg].driver_name); | 1330 | blkcipher_algs[alg].driver_name); |
| 1331 | goto fail0; | 1331 | goto fail0; |
| 1332 | } | 1332 | } |
| 1333 | t_alg->drvdata = drvdata; | 1333 | t_alg->drvdata = drvdata; |
| 1334 | 1334 | ||
| 1335 | SSI_LOG_DEBUG("registering %s\n", blkcipher_algs[alg].driver_name); | 1335 | dev_dbg(dev, "registering %s\n", |
| 1336 | blkcipher_algs[alg].driver_name); | ||
| 1336 | rc = crypto_register_alg(&t_alg->crypto_alg); | 1337 | rc = crypto_register_alg(&t_alg->crypto_alg); |
| 1337 | SSI_LOG_DEBUG("%s alg registration rc = %x\n", | 1338 | dev_dbg(dev, "%s alg registration rc = %x\n", |
| 1338 | t_alg->crypto_alg.cra_driver_name, rc); | 1339 | t_alg->crypto_alg.cra_driver_name, rc); |
| 1339 | if (unlikely(rc != 0)) { | 1340 | if (unlikely(rc != 0)) { |
| 1340 | SSI_LOG_ERR("%s alg registration failed\n", | 1341 | dev_err(dev, "%s alg registration failed\n", |
| 1341 | t_alg->crypto_alg.cra_driver_name); | 1342 | t_alg->crypto_alg.cra_driver_name); |
| 1342 | kfree(t_alg); | 1343 | kfree(t_alg); |
| 1343 | goto fail0; | 1344 | goto fail0; |
| 1344 | } else { | 1345 | } else { |
| 1345 | list_add_tail(&t_alg->entry, | 1346 | list_add_tail(&t_alg->entry, |
| 1346 | &ablkcipher_handle->blkcipher_alg_list); | 1347 | &ablkcipher_handle->blkcipher_alg_list); |
| 1347 | SSI_LOG_DEBUG("Registered %s\n", | 1348 | dev_dbg(dev, "Registered %s\n", |
| 1348 | t_alg->crypto_alg.cra_driver_name); | 1349 | t_alg->crypto_alg.cra_driver_name); |
| 1349 | } | 1350 | } |
| 1350 | } | 1351 | } |
| 1351 | return 0; | 1352 | return 0; |
| @@ -27,11 +27,11 @@ · 26 unmodified lines | |||
| 27 | #include "ssi_buffer_mgr.h" | 27 | #include "ssi_buffer_mgr.h" |
| 28 | 28 | ||
| 29 | /* Crypto cipher flags */ | 29 | /* Crypto cipher flags */ |
| 30 | #define CC_CRYPTO_CIPHER_KEY_KFDE0 (1 << 0) | 30 | #define CC_CRYPTO_CIPHER_KEY_KFDE0 BIT(0) |
| 31 | #define CC_CRYPTO_CIPHER_KEY_KFDE1 (1 << 1) | 31 | #define CC_CRYPTO_CIPHER_KEY_KFDE1 BIT(1) |
| 32 | #define CC_CRYPTO_CIPHER_KEY_KFDE2 (1 << 2) | 32 | #define CC_CRYPTO_CIPHER_KEY_KFDE2 BIT(2) |
| 33 | #define CC_CRYPTO_CIPHER_KEY_KFDE3 (1 << 3) | 33 | #define CC_CRYPTO_CIPHER_KEY_KFDE3 BIT(3) |
| 34 | #define CC_CRYPTO_CIPHER_DU_SIZE_512B (1 << 4) | 34 | #define CC_CRYPTO_CIPHER_DU_SIZE_512B BIT(4) |
| 35 | 35 | ||
| 36 | #define CC_CRYPTO_CIPHER_KEY_KFDE_MASK (CC_CRYPTO_CIPHER_KEY_KFDE0 | CC_CRYPTO_CIPHER_KEY_KFDE1 | CC_CRYPTO_CIPHER_KEY_KFDE2 | CC_CRYPTO_CIPHER_KEY_KFDE3) | 36 | #define CC_CRYPTO_CIPHER_KEY_KFDE_MASK (CC_CRYPTO_CIPHER_KEY_KFDE0 | CC_CRYPTO_CIPHER_KEY_KFDE1 | CC_CRYPTO_CIPHER_KEY_KFDE2 | CC_CRYPTO_CIPHER_KEY_KFDE3) |
| 37 | 37 | ||
| @@ -43,6 +43,7 @@ struct blkcipher_req_ctx { · 5 unmodified lines | |||
| 43 | u32 out_nents; | 43 | u32 out_nents; |
| 44 | u32 out_mlli_nents; | 44 | u32 out_mlli_nents; |
| 45 | u8 *backup_info; /*store iv for generated IV flow*/ | 45 | u8 *backup_info; /*store iv for generated IV flow*/ |
| 46 | u8 *iv; | ||
| 46 | bool is_giv; | 47 | bool is_giv; |
| 47 | struct mlli_params mlli_params; | 48 | struct mlli_params mlli_params; |
| 48 | }; | 49 | }; |
| @@ -75,7 +76,7 @@ struct arm_hw_key_info { · 26 unmodified lines | |||
| 75 | 76 | ||
| 76 | static inline bool ssi_is_hw_key(struct crypto_tfm *tfm) | 77 | static inline bool ssi_is_hw_key(struct crypto_tfm *tfm) |
| 77 | { | 78 | { |
| 78 | return 0; | 79 | return false; |
| 79 | } | 80 | } |
| 80 | 81 | ||
| 81 | #endif /* CRYPTO_TFM_REQ_HW_KEY */ | 82 | #endif /* CRYPTO_TFM_REQ_HW_KEY */ |
| @@ -74,70 +74,46 @@ · 73 unmodified lines | |||
| 74 | #include "ssi_fips.h" | 74 | #include "ssi_fips.h" |
| 75 | 75 | ||
| 76 | #ifdef DX_DUMP_BYTES | 76 | #ifdef DX_DUMP_BYTES |
| 77 | void dump_byte_array(const char *name, const u8 *the_array, unsigned long size) | 77 | void dump_byte_array(const char *name, const u8 *buf, size_t len) |
| 78 | { | 78 | { |
| 79 | int i, line_offset = 0, ret = 0; | 79 | char prefix[NAME_LEN]; |
| 80 | const u8 *cur_byte; | ||
| 81 | char line_buf[80]; | ||
| 82 | 80 | ||
| 83 | if (!the_array) { | 81 | if (!buf) |
| 84 | SSI_LOG_ERR("cannot dump array - NULL pointer\n"); | ||
| 85 | return; | 82 | return; |
| 86 | } | ||
| 87 | 83 | ||
| 88 | ret = snprintf(line_buf, sizeof(line_buf), "%s[%lu]: ", name, size); | 84 | snprintf(prefix, sizeof(prefix), "%s[%lu]: ", name, len); |
| 89 | if (ret < 0) { | ||
| 90 | SSI_LOG_ERR("snprintf returned %d . aborting buffer array dump\n", ret); | ||
| 91 | return; | ||
| 92 | } | ||
| 93 | line_offset = ret; | ||
| 94 | for (i = 0, cur_byte = the_array; | ||
| 95 | (i < size) && (line_offset < sizeof(line_buf)); i++, cur_byte++) { | ||
| 96 | ret = snprintf(line_buf + line_offset, | ||
| 97 | sizeof(line_buf) - line_offset, | ||
| 98 | "0x%02X ", *cur_byte); | ||
| 99 | if (ret < 0) { | ||
| 100 | SSI_LOG_ERR("snprintf returned %d . aborting buffer array dump\n", ret); | ||
| 101 | return; | ||
| 102 | } | ||
| 103 | line_offset += ret; | ||
| 104 | if (line_offset > 75) { /* Cut before line end */ | ||
| 105 | SSI_LOG_DEBUG("%s\n", line_buf); | ||
| 106 | line_offset = 0; | ||
| 107 | } | ||
| 108 | } | ||
| 109 | 85 | ||
| 110 | if (line_offset > 0) /* Dump remaining line */ | 86 | print_hex_dump(KERN_DEBUG, prefix, DUMP_PREFIX_ADDRESS, 16, 1, len, |
| 111 | SSI_LOG_DEBUG("%s\n", line_buf); | 87 | false); |
| 112 | } | 88 | } |
| 113 | #endif | 89 | #endif |
| 114 | 90 | ||
| 115 | static irqreturn_t cc_isr(int irq, void *dev_id) | 91 | static irqreturn_t cc_isr(int irq, void *dev_id) |
| 116 | { | 92 | { |
| 117 | struct ssi_drvdata *drvdata = (struct ssi_drvdata *)dev_id; | 93 | struct ssi_drvdata *drvdata = (struct ssi_drvdata *)dev_id; |
| 118 | void __iomem *cc_base = drvdata->cc_base; | 94 | struct device *dev = drvdata_to_dev(drvdata); |
| 119 | u32 irr; | 95 | u32 irr; |
| 120 | u32 imr; | 96 | u32 imr; |
| 121 | 97 | ||
| 122 | /* STAT_OP_TYPE_GENERIC STAT_PHASE_0: Interrupt */ | 98 | /* STAT_OP_TYPE_GENERIC STAT_PHASE_0: Interrupt */ |
| 123 | 99 | ||
| 124 | /* read the interrupt status */ | 100 | /* read the interrupt status */ |
| 125 | irr = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IRR)); | 101 | irr = cc_ioread(drvdata, CC_REG(HOST_IRR)); |
| 126 | SSI_LOG_DEBUG("Got IRR=0x%08X\n", irr); | 102 | dev_dbg(dev, "Got IRR=0x%08X\n", irr); |
| 127 | if (unlikely(irr == 0)) { /* Probably shared interrupt line */ | 103 | if (unlikely(irr == 0)) { /* Probably shared interrupt line */ |
| 128 | SSI_LOG_ERR("Got interrupt with empty IRR\n"); | 104 | dev_err(dev, "Got interrupt with empty IRR\n"); |
| 129 | return IRQ_NONE; | 105 | return IRQ_NONE; |
| 130 | } | 106 | } |
| 131 | imr = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR)); | 107 | imr = cc_ioread(drvdata, CC_REG(HOST_IMR)); |
| 132 | 108 | ||
| 133 | /* clear interrupt - must be before processing events */ | 109 | /* clear interrupt - must be before processing events */ |
| 134 | CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_ICR), irr); | 110 | cc_iowrite(drvdata, CC_REG(HOST_ICR), irr); |
| 135 | 111 | ||
| 136 | drvdata->irq = irr; | 112 | drvdata->irq = irr; |
| 137 | /* Completion interrupt - most probable */ | 113 | /* Completion interrupt - most probable */ |
| 138 | if (likely((irr & SSI_COMP_IRQ_MASK) != 0)) { | 114 | if (likely((irr & SSI_COMP_IRQ_MASK) != 0)) { |
| 139 | /* Mask AXI completion interrupt - will be unmasked in Deferred service handler */ | 115 | /* Mask AXI completion interrupt - will be unmasked in Deferred service handler */ |
| 140 | CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR), imr | SSI_COMP_IRQ_MASK); | 116 | cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | SSI_COMP_IRQ_MASK); |
| 141 | irr &= ~SSI_COMP_IRQ_MASK; | 117 | irr &= ~SSI_COMP_IRQ_MASK; |
| 142 | complete_request(drvdata); | 118 | complete_request(drvdata); |
| 143 | } | 119 | } |
| @@ -145,7 +121,7 @@ static irqreturn_t cc_isr(int irq, void *dev_id) · 1 unmodified line | |||
| 145 | /* TEE FIPS interrupt */ | 121 | /* TEE FIPS interrupt */ |
| 146 | if (likely((irr & SSI_GPR0_IRQ_MASK) != 0)) { | 122 | if (likely((irr & SSI_GPR0_IRQ_MASK) != 0)) { |
| 147 | /* Mask interrupt - will be unmasked in Deferred service handler */ | 123 | /* Mask interrupt - will be unmasked in Deferred service handler */ |
| 148 | CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR), imr | SSI_GPR0_IRQ_MASK); | 124 | cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | SSI_GPR0_IRQ_MASK); |
| 149 | irr &= ~SSI_GPR0_IRQ_MASK; | 125 | irr &= ~SSI_GPR0_IRQ_MASK; |
| 150 | fips_handler(drvdata); | 126 | fips_handler(drvdata); |
| 151 | } | 127 | } |
| @@ -155,14 +131,16 @@ static irqreturn_t cc_isr(int irq, void *dev_id) · 3 unmodified lines | |||
| 155 | u32 axi_err; | 131 | u32 axi_err; |
| 156 | 132 | ||
| 157 | /* Read the AXI error ID */ | 133 | /* Read the AXI error ID */ |
| 158 | axi_err = CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_ERR)); | 134 | axi_err = cc_ioread(drvdata, CC_REG(AXIM_MON_ERR)); |
| 159 | SSI_LOG_DEBUG("AXI completion error: axim_mon_err=0x%08X\n", axi_err); | 135 | dev_dbg(dev, "AXI completion error: axim_mon_err=0x%08X\n", |
| 136 | axi_err); | ||
| 160 | 137 | ||
| 161 | irr &= ~SSI_AXI_ERR_IRQ_MASK; | 138 | irr &= ~SSI_AXI_ERR_IRQ_MASK; |
| 162 | } | 139 | } |
| 163 | 140 | ||
| 164 | if (unlikely(irr != 0)) { | 141 | if (unlikely(irr != 0)) { |
| 165 | SSI_LOG_DEBUG("IRR includes unknown cause bits (0x%08X)\n", irr); | 142 | dev_dbg(dev, "IRR includes unknown cause bits (0x%08X)\n", |
| 143 | irr); | ||
| 166 | /* Just warning */ | 144 | /* Just warning */ |
| 167 | } | 145 | } |
| 168 | 146 | ||
| @@ -172,48 +150,48 @@ static irqreturn_t cc_isr(int irq, void *dev_id) · 3 unmodified lines | |||
| 172 | int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe) | 150 | int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe) |
| 173 | { | 151 | { |
| 174 | unsigned int val, cache_params; | 152 | unsigned int val, cache_params; |
| 175 | void __iomem *cc_base = drvdata->cc_base; | 153 | struct device *dev = drvdata_to_dev(drvdata); |
| 176 | 154 | ||
| 177 | /* Unmask all AXI interrupt sources AXI_CFG1 register */ | 155 | /* Unmask all AXI interrupt sources AXI_CFG1 register */ |
| 178 | val = CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CFG)); | 156 | val = cc_ioread(drvdata, CC_REG(AXIM_CFG)); |
| 179 | CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CFG), val & ~SSI_AXI_IRQ_MASK); | 157 | cc_iowrite(drvdata, CC_REG(AXIM_CFG), val & ~SSI_AXI_IRQ_MASK); |
| 180 | SSI_LOG_DEBUG("AXIM_CFG=0x%08X\n", CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CFG))); | 158 | dev_dbg(dev, "AXIM_CFG=0x%08X\n", |
| 159 | cc_ioread(drvdata, CC_REG(AXIM_CFG))); | ||
| 181 | 160 | ||
| 182 | /* Clear all pending interrupts */ | 161 | /* Clear all pending interrupts */ |
| 183 | val = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IRR)); | 162 | val = cc_ioread(drvdata, CC_REG(HOST_IRR)); |
| 184 | SSI_LOG_DEBUG("IRR=0x%08X\n", val); | 163 | dev_dbg(dev, "IRR=0x%08X\n", val); |
| 185 | CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_ICR), val); | 164 | cc_iowrite(drvdata, CC_REG(HOST_ICR), val); |
| 186 | 165 | ||
| 187 | /* Unmask relevant interrupt cause */ | 166 | /* Unmask relevant interrupt cause */ |
| 188 | val = (~(SSI_COMP_IRQ_MASK | SSI_AXI_ERR_IRQ_MASK | SSI_GPR0_IRQ_MASK)); | 167 | val = (unsigned int)(~(SSI_COMP_IRQ_MASK | SSI_AXI_ERR_IRQ_MASK | |
| 189 | CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR), val); | 168 | SSI_GPR0_IRQ_MASK)); |
| 169 | cc_iowrite(drvdata, CC_REG(HOST_IMR), val); | ||
| 190 | 170 | ||
| 191 | #ifdef DX_HOST_IRQ_TIMER_INIT_VAL_REG_OFFSET | 171 | #ifdef DX_HOST_IRQ_TIMER_INIT_VAL_REG_OFFSET |
| 192 | #ifdef DX_IRQ_DELAY | 172 | #ifdef DX_IRQ_DELAY |
| 193 | /* Set CC IRQ delay */ | 173 | /* Set CC IRQ delay */ |
| 194 | CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IRQ_TIMER_INIT_VAL), | 174 | cc_iowrite(drvdata, CC_REG(HOST_IRQ_TIMER_INIT_VAL), DX_IRQ_DELAY); |
| 195 | DX_IRQ_DELAY); | ||
| 196 | #endif | 175 | #endif |
| 197 | if (CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IRQ_TIMER_INIT_VAL)) > 0) { | 176 | if (cc_ioread(drvdata, CC_REG(HOST_IRQ_TIMER_INIT_VAL)) > 0) { |
| 198 | SSI_LOG_DEBUG("irq_delay=%d CC cycles\n", | 177 | dev_dbg(dev, "irq_delay=%d CC cycles\n", |
| 199 | CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IRQ_TIMER_INIT_VAL))); | 178 | cc_ioread(drvdata, CC_REG(HOST_IRQ_TIMER_INIT_VAL))); |
| 200 | } | 179 | } |
| 201 | #endif | 180 | #endif |
| 202 | 181 | ||
| 203 | cache_params = (drvdata->coherent ? CC_COHERENT_CACHE_PARAMS : 0x0); | 182 | cache_params = (drvdata->coherent ? CC_COHERENT_CACHE_PARAMS : 0x0); |
| 204 | 183 | ||
| 205 | val = CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CACHE_PARAMS)); | 184 | val = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS)); |
| 206 | 185 | ||
| 207 | if (is_probe) | 186 | if (is_probe) |
| 208 | SSI_LOG_INFO("Cache params previous: 0x%08X\n", val); | 187 | dev_info(dev, "Cache params previous: 0x%08X\n", val); |
| 209 | 188 | ||
| 210 | CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CACHE_PARAMS), | 189 | cc_iowrite(drvdata, CC_REG(AXIM_CACHE_PARAMS), cache_params); |
| 211 | cache_params); | 190 | val = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS)); |
| 212 | val = CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CACHE_PARAMS)); | ||
| 213 | 191 | ||
| 214 | if (is_probe) | 192 | if (is_probe) |
| 215 | SSI_LOG_INFO("Cache params current: 0x%08X (expect: 0x%08X)\n", | 193 | dev_info(dev, "Cache params current: 0x%08X (expect: 0x%08X)\n", |
| 216 | val, cache_params); | 194 | val, cache_params); |
| 217 | 195 | ||
| 218 | return 0; | 196 | return 0; |
| 219 | } | 197 | } |
| @@ -222,181 +200,172 @@ static int init_cc_resources(struct platform_device *plat_dev) · 2 unmodified lines | |||
| 222 | { | 200 | { |
| 223 | struct resource *req_mem_cc_regs = NULL; | 201 | struct resource *req_mem_cc_regs = NULL; |
| 224 | void __iomem *cc_base = NULL; | 202 | void __iomem *cc_base = NULL; |
| 225 | bool irq_registered = false; | 203 | struct ssi_drvdata *new_drvdata; |
| 226 | struct ssi_drvdata *new_drvdata = kzalloc(sizeof(*new_drvdata), | ||
| 227 | GFP_KERNEL); | ||
| 228 | struct device *dev = &plat_dev->dev; | 204 | struct device *dev = &plat_dev->dev; |
| 229 | struct device_node *np = dev->of_node; | 205 | struct device_node *np = dev->of_node; |
| 230 | u32 signature_val; | 206 | u32 signature_val; |
| 207 | dma_addr_t dma_mask; | ||
| 231 | int rc = 0; | 208 | int rc = 0; |
| 232 | 209 | ||
| 233 | if (unlikely(!new_drvdata)) { | 210 | new_drvdata = devm_kzalloc(dev, sizeof(*new_drvdata), GFP_KERNEL); |
| 234 | SSI_LOG_ERR("Failed to allocate drvdata"); | 211 | if (!new_drvdata) |
| 235 | rc = -ENOMEM; | 212 | return -ENOMEM; |
| 236 | goto init_cc_res_err; | 213 | |
| 237 | } | 214 | platform_set_drvdata(plat_dev, new_drvdata); |
| 215 | new_drvdata->plat_dev = plat_dev; | ||
| 238 | 216 | ||
| 239 | new_drvdata->clk = of_clk_get(np, 0); | 217 | new_drvdata->clk = of_clk_get(np, 0); |
| 240 | new_drvdata->coherent = of_dma_is_coherent(np); | 218 | new_drvdata->coherent = of_dma_is_coherent(np); |
| 241 | 219 | ||
| 242 | /*Initialize inflight counter used in dx_ablkcipher_secure_complete used for count of BYSPASS blocks operations*/ | ||
| 243 | new_drvdata->inflight_counter = 0; | ||
| 244 | |||
| 245 | dev_set_drvdata(&plat_dev->dev, new_drvdata); | ||
| 246 | /* Get device resources */ | 220 | /* Get device resources */ |
| 247 | /* First CC registers space */ | 221 | /* First CC registers space */ |
| 248 | new_drvdata->res_mem = platform_get_resource(plat_dev, IORESOURCE_MEM, 0); | 222 | req_mem_cc_regs = platform_get_resource(plat_dev, IORESOURCE_MEM, 0); |
| 249 | if (unlikely(!new_drvdata->res_mem)) { | ||
| 250 | SSI_LOG_ERR("Failed getting IO memory resource\n"); | ||
| 251 | rc = -ENODEV; | ||
| 252 | goto init_cc_res_err; | ||
| 253 | } | ||
| 254 | SSI_LOG_DEBUG("Got MEM resource (%s): start=%pad end=%pad\n", | ||
| 255 | new_drvdata->res_mem->name, | ||
| 256 | new_drvdata->res_mem->start, | ||
| 257 | new_drvdata->res_mem->end); | ||
| 258 | /* Map registers space */ | 223 | /* Map registers space */ |
| 259 | req_mem_cc_regs = request_mem_region(new_drvdata->res_mem->start, resource_size(new_drvdata->res_mem), "arm_cc7x_regs"); | 224 | new_drvdata->cc_base = devm_ioremap_resource(dev, req_mem_cc_regs); |
| 260 | if (unlikely(!req_mem_cc_regs)) { | 225 | if (IS_ERR(new_drvdata->cc_base)) { |
| 261 | SSI_LOG_ERR("Couldn't allocate registers memory region at " | 226 | dev_err(dev, "Failed to ioremap registers"); |
| 262 | "0x%08X\n", (unsigned int)new_drvdata->res_mem->start); | 227 | return PTR_ERR(new_drvdata->cc_base); |
| 263 | rc = -EBUSY; | ||
| 264 | goto init_cc_res_err; | ||
| 265 | } | 228 | } |
| 266 | cc_base = ioremap(new_drvdata->res_mem->start, resource_size(new_drvdata->res_mem)); | 229 | |
| 267 | if (unlikely(!cc_base)) { | 230 | dev_dbg(dev, "Got MEM resource (%s): %pR\n", req_mem_cc_regs->name, |
| 268 | SSI_LOG_ERR("ioremap[CC](0x%08X,0x%08X) failed\n", | 231 | req_mem_cc_regs); |
| 269 | (unsigned int)new_drvdata->res_mem->start, | 232 | dev_dbg(dev, "CC registers mapped from %pa to 0x%p\n", |
| 270 | (unsigned int)resource_size(new_drvdata->res_mem)); | 233 | &req_mem_cc_regs->start, new_drvdata->cc_base); |
| 271 | rc = -ENOMEM; | 234 | |
| 272 | goto init_cc_res_err; | 235 | cc_base = new_drvdata->cc_base; |
| 273 | } | ||
| 274 | SSI_LOG_DEBUG("CC registers mapped from %pa to 0x%p\n", &new_drvdata->res_mem->start, cc_base); | ||
| 275 | new_drvdata->cc_base = cc_base; | ||
| 276 | 236 | ||
| 277 | /* Then IRQ */ | 237 | /* Then IRQ */ |
| 278 | new_drvdata->res_irq = platform_get_resource(plat_dev, IORESOURCE_IRQ, 0); | 238 | new_drvdata->irq = platform_get_irq(plat_dev, 0); |
| 279 | if (unlikely(!new_drvdata->res_irq)) { | 239 | if (new_drvdata->irq < 0) { |
| 280 | SSI_LOG_ERR("Failed getting IRQ resource\n"); | 240 | dev_err(dev, "Failed getting IRQ resource\n"); |
| 281 | rc = -ENODEV; | 241 | return new_drvdata->irq; |
| 282 | goto init_cc_res_err; | ||
| 283 | } | ||
| 284 | rc = request_irq(new_drvdata->res_irq->start, cc_isr, | ||
| 285 | IRQF_SHARED, "arm_cc7x", new_drvdata); | ||
| 286 | if (unlikely(rc != 0)) { | ||
| 287 | SSI_LOG_ERR("Could not register to interrupt %llu\n", | ||
| 288 | (unsigned long long)new_drvdata->res_irq->start); | ||
| 289 | goto init_cc_res_err; | ||
| 290 | } | 242 | } |
| 291 | init_completion(&new_drvdata->icache_setup_completion); | ||
| 292 | 243 | ||
| 293 | irq_registered = true; | 244 | rc = devm_request_irq(dev, new_drvdata->irq, cc_isr, |
| 294 | SSI_LOG_DEBUG("Registered to IRQ (%s) %llu\n", | 245 | IRQF_SHARED, "arm_cc7x", new_drvdata); |
| 295 | new_drvdata->res_irq->name, | 246 | if (rc) { |
| 296 | (unsigned long long)new_drvdata->res_irq->start); | 247 | dev_err(dev, "Could not register to interrupt %d\n", |
| 248 | new_drvdata->irq); | ||
| 249 | return rc; | ||
| 250 | } | ||
| 251 | dev_dbg(dev, "Registered to IRQ: %d\n", new_drvdata->irq); | ||
| 297 | 252 | ||
| 298 | new_drvdata->plat_dev = plat_dev; | 253 | if (!plat_dev->dev.dma_mask) |
| 254 | plat_dev->dev.dma_mask = &plat_dev->dev.coherent_dma_mask; | ||
| 299 | 255 | ||
| 300 | rc = cc_clk_on(new_drvdata); | 256 | dma_mask = (dma_addr_t)(DMA_BIT_MASK(DMA_BIT_MASK_LEN)); |
| 301 | if (rc) | 257 | while (dma_mask > 0x7fffffffUL) { |
| 302 | goto init_cc_res_err; | 258 | if (dma_supported(&plat_dev->dev, dma_mask)) { |
| 259 | rc = dma_set_coherent_mask(&plat_dev->dev, dma_mask); | ||
| 260 | if (!rc) | ||
| 261 | break; | ||
| 262 | } | ||
| 263 | dma_mask >>= 1; | ||
| 264 | } | ||
| 303 | 265 | ||
| 304 | if (!new_drvdata->plat_dev->dev.dma_mask) | 266 | if (rc) { |
| 305 | new_drvdata->plat_dev->dev.dma_mask = &new_drvdata->plat_dev->dev.coherent_dma_mask; | 267 | dev_err(dev, "Failed in dma_set_mask, mask=%par\n", |
| 268 | &dma_mask); | ||
| 269 | return rc; | ||
| 270 | } | ||
| 306 | 271 | ||
| 307 | if (!new_drvdata->plat_dev->dev.coherent_dma_mask) | 272 | rc = cc_clk_on(new_drvdata); |
| 308 | new_drvdata->plat_dev->dev.coherent_dma_mask = DMA_BIT_MASK(DMA_BIT_MASK_LEN); | 273 | if (rc) { |
| 274 | dev_err(dev, "Failed to enable clock"); | ||
| 275 | return rc; | ||
| 276 | } | ||
| 309 | 277 | ||
| 310 | /* Verify correct mapping */ | 278 | /* Verify correct mapping */ |
| 311 | signature_val = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_SIGNATURE)); | 279 | signature_val = cc_ioread(new_drvdata, CC_REG(HOST_SIGNATURE)); |
| 312 | if (signature_val != DX_DEV_SIGNATURE) { | 280 | if (signature_val != DX_DEV_SIGNATURE) { |
| 313 | SSI_LOG_ERR("Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n", | 281 | dev_err(dev, "Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n", |
| 314 | signature_val, (u32)DX_DEV_SIGNATURE); | 282 | signature_val, (u32)DX_DEV_SIGNATURE); |
| 315 | rc = -EINVAL; | 283 | rc = -EINVAL; |
| 316 | goto init_cc_res_err; | 284 | goto post_clk_err; |
| 317 | } | 285 | } |
| 318 | SSI_LOG_DEBUG("CC SIGNATURE=0x%08X\n", signature_val); | 286 | dev_dbg(dev, "CC SIGNATURE=0x%08X\n", signature_val); |
| 319 | 287 | ||
| 320 | /* Display HW versions */ | 288 | /* Display HW versions */ |
| 321 | SSI_LOG(KERN_INFO, "ARM CryptoCell %s Driver: HW version 0x%08X, Driver version %s\n", SSI_DEV_NAME_STR, | 289 | dev_info(dev, "ARM CryptoCell %s Driver: HW version 0x%08X, Driver version %s\n", |
| 322 | CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_VERSION)), DRV_MODULE_VERSION); | 290 | SSI_DEV_NAME_STR, |
| 291 | cc_ioread(new_drvdata, CC_REG(HOST_VERSION)), | ||
| 292 | DRV_MODULE_VERSION); | ||
| 323 | 293 | ||
| 324 | rc = init_cc_regs(new_drvdata, true); | 294 | rc = init_cc_regs(new_drvdata, true); |
| 325 | if (unlikely(rc != 0)) { | 295 | if (unlikely(rc != 0)) { |
| 326 | SSI_LOG_ERR("init_cc_regs failed\n"); | 296 | dev_err(dev, "init_cc_regs failed\n"); |
| 327 | goto init_cc_res_err; | 297 | goto post_clk_err; |
| 328 | } | 298 | } |
| 329 | 299 | ||
| 330 | #ifdef ENABLE_CC_SYSFS | 300 | #ifdef ENABLE_CC_SYSFS |
| 331 | rc = ssi_sysfs_init(&plat_dev->dev.kobj, new_drvdata); | 301 | rc = ssi_sysfs_init(&dev->kobj, new_drvdata); |
| 332 | if (unlikely(rc != 0)) { | 302 | if (unlikely(rc != 0)) { |
| 333 | SSI_LOG_ERR("init_stat_db failed\n"); | 303 | dev_err(dev, "init_stat_db failed\n"); |
| 334 | goto init_cc_res_err; | 304 | goto post_regs_err; |
| 335 | } | 305 | } |
| 336 | #endif | 306 | #endif |
| 337 | 307 | ||
| 308 | rc = ssi_fips_init(new_drvdata); | ||
| 309 | if (unlikely(rc != 0)) { | ||
| 310 | dev_err(dev, "SSI_FIPS_INIT failed 0x%x\n", rc); | ||
| 311 | goto post_sysfs_err; | ||
| 312 | } | ||
| 338 | rc = ssi_sram_mgr_init(new_drvdata); | 313 | rc = ssi_sram_mgr_init(new_drvdata); |
| 339 | if (unlikely(rc != 0)) { | 314 | if (unlikely(rc != 0)) { |
| 340 | SSI_LOG_ERR("ssi_sram_mgr_init failed\n"); | 315 | dev_err(dev, "ssi_sram_mgr_init failed\n"); |
| 341 | goto init_cc_res_err; | 316 | goto post_fips_init_err; |
| 342 | } | 317 | } |
| 343 | 318 | ||
| 344 | new_drvdata->mlli_sram_addr = | 319 | new_drvdata->mlli_sram_addr = |
| 345 | ssi_sram_mgr_alloc(new_drvdata, MAX_MLLI_BUFF_SIZE); | 320 | ssi_sram_mgr_alloc(new_drvdata, MAX_MLLI_BUFF_SIZE); |
| 346 | if (unlikely(new_drvdata->mlli_sram_addr == NULL_SRAM_ADDR)) { | 321 | if (unlikely(new_drvdata->mlli_sram_addr == NULL_SRAM_ADDR)) { |
| 347 | SSI_LOG_ERR("Failed to alloc MLLI Sram buffer\n"); | 322 | dev_err(dev, "Failed to alloc MLLI Sram buffer\n"); |
| 348 | rc = -ENOMEM; | 323 | rc = -ENOMEM; |
| 349 | goto init_cc_res_err; | 324 | goto post_sram_mgr_err; |
| 350 | } | 325 | } |
| 351 | 326 | ||
| 352 | rc = request_mgr_init(new_drvdata); | 327 | rc = request_mgr_init(new_drvdata); |
| 353 | if (unlikely(rc != 0)) { | 328 | if (unlikely(rc != 0)) { |
| 354 | SSI_LOG_ERR("request_mgr_init failed\n"); | 329 | dev_err(dev, "request_mgr_init failed\n"); |
| 355 | goto init_cc_res_err; | 330 | goto post_sram_mgr_err; |
| 356 | } | 331 | } |
| 357 | 332 | ||
| 358 | rc = ssi_buffer_mgr_init(new_drvdata); | 333 | rc = ssi_buffer_mgr_init(new_drvdata); |
| 359 | if (unlikely(rc != 0)) { | 334 | if (unlikely(rc != 0)) { |
| 360 | SSI_LOG_ERR("buffer_mgr_init failed\n"); | 335 | dev_err(dev, "buffer_mgr_init failed\n"); |
| 361 | goto init_cc_res_err; | 336 | goto post_req_mgr_err; |
| 362 | } | 337 | } |
| 363 | 338 | ||
| 364 | rc = ssi_power_mgr_init(new_drvdata); | 339 | rc = ssi_power_mgr_init(new_drvdata); |
| 365 | if (unlikely(rc != 0)) { | 340 | if (unlikely(rc != 0)) { |
| 366 | SSI_LOG_ERR("ssi_power_mgr_init failed\n"); | 341 | dev_err(dev, "ssi_power_mgr_init failed\n"); |
| 367 | goto init_cc_res_err; | 342 | goto post_buf_mgr_err; |
| 368 | } | ||
| 369 | |||
| 370 | rc = ssi_fips_init(new_drvdata); | ||
| 371 | if (unlikely(rc != 0)) { | ||
| 372 | SSI_LOG_ERR("SSI_FIPS_INIT failed 0x%x\n", rc); | ||
| 373 | goto init_cc_res_err; | ||
| 374 | } | 343 | } |
| 375 | 344 | ||
| 376 | rc = ssi_ivgen_init(new_drvdata); | 345 | rc = ssi_ivgen_init(new_drvdata); |
| 377 | if (unlikely(rc != 0)) { | 346 | if (unlikely(rc != 0)) { |
| 378 | SSI_LOG_ERR("ssi_ivgen_init failed\n"); | 347 | dev_err(dev, "ssi_ivgen_init failed\n"); |
| 379 | goto init_cc_res_err; | 348 | goto post_power_mgr_err; |
| 380 | } | 349 | } |
| 381 | 350 | ||
| 382 | /* Allocate crypto algs */ | 351 | /* Allocate crypto algs */ |
| 383 | rc = ssi_ablkcipher_alloc(new_drvdata); | 352 | rc = ssi_ablkcipher_alloc(new_drvdata); |
| 384 | if (unlikely(rc != 0)) { | 353 | if (unlikely(rc != 0)) { |
| 385 | SSI_LOG_ERR("ssi_ablkcipher_alloc failed\n"); | 354 | dev_err(dev, "ssi_ablkcipher_alloc failed\n"); |
| 386 | goto init_cc_res_err; | 355 | goto post_ivgen_err; |
| 387 | } | 356 | } |
| 388 | 357 | ||
| 389 | /* hash must be allocated before aead since hash exports APIs */ | 358 | /* hash must be allocated before aead since hash exports APIs */ |
| 390 | rc = ssi_hash_alloc(new_drvdata); | 359 | rc = ssi_hash_alloc(new_drvdata); |
| 391 | if (unlikely(rc != 0)) { | 360 | if (unlikely(rc != 0)) { |
| 392 | SSI_LOG_ERR("ssi_hash_alloc failed\n"); | 361 | dev_err(dev, "ssi_hash_alloc failed\n"); |
| 393 | goto init_cc_res_err; | 362 | goto post_cipher_err; |
| 394 | } | 363 | } |
| 395 | 364 | ||
| 396 | rc = ssi_aead_alloc(new_drvdata); | 365 | rc = ssi_aead_alloc(new_drvdata); |
| 397 | if (unlikely(rc != 0)) { | 366 | if (unlikely(rc != 0)) { |
| 398 | SSI_LOG_ERR("ssi_aead_alloc failed\n"); | 367 | dev_err(dev, "ssi_aead_alloc failed\n"); |
| 399 | goto init_cc_res_err; | 368 | goto post_hash_err; |
| 400 | } | 369 | } |
| 401 | 370 | ||
| 402 | /* If we got here and FIPS mode is enabled | 371 | /* If we got here and FIPS mode is enabled |
| @@ -407,52 +376,43 @@ static int init_cc_resources(struct platform_device *plat_dev) · 4 unmodified lines | |||
| 407 | 376 | ||
| 408 | return 0; | 377 | return 0; |
| 409 | 378 | ||
| 410 | init_cc_res_err: | 379 | post_hash_err: |
| 411 | SSI_LOG_ERR("Freeing CC HW resources!\n"); | 380 | ssi_hash_free(new_drvdata); |
| 412 | 381 | post_cipher_err: | |
| 413 | if (new_drvdata) { | 382 | ssi_ablkcipher_free(new_drvdata); |
| 414 | ssi_aead_free(new_drvdata); | 383 | post_ivgen_err: |
| 415 | ssi_hash_free(new_drvdata); | 384 | ssi_ivgen_fini(new_drvdata); |
| 416 | ssi_ablkcipher_free(new_drvdata); | 385 | post_power_mgr_err: |
| 417 | ssi_ivgen_fini(new_drvdata); | 386 | ssi_power_mgr_fini(new_drvdata); |
| 418 | ssi_power_mgr_fini(new_drvdata); | 387 | post_buf_mgr_err: |
| 419 | ssi_buffer_mgr_fini(new_drvdata); | 388 | ssi_buffer_mgr_fini(new_drvdata); |
| 420 | request_mgr_fini(new_drvdata); | 389 | post_req_mgr_err: |
| 421 | ssi_sram_mgr_fini(new_drvdata); | 390 | request_mgr_fini(new_drvdata); |
| 422 | ssi_fips_fini(new_drvdata); | 391 | post_sram_mgr_err: |
| 392 | ssi_sram_mgr_fini(new_drvdata); | ||
| 393 | post_fips_init_err: | ||
| 394 | ssi_fips_fini(new_drvdata); | ||
| 395 | post_sysfs_err: | ||
| 423 | #ifdef ENABLE_CC_SYSFS | 396 | #ifdef ENABLE_CC_SYSFS |
| 424 | ssi_sysfs_fini(); | 397 | ssi_sysfs_fini(); |
| 425 | #endif | 398 | #endif |
| 426 | 399 | post_regs_err: | |
| 427 | if (req_mem_cc_regs) { | 400 | fini_cc_regs(new_drvdata); |
| 428 | if (irq_registered) { | 401 | post_clk_err: |
| 429 | free_irq(new_drvdata->res_irq->start, new_drvdata); | 402 | cc_clk_off(new_drvdata); |
| 430 | new_drvdata->res_irq = NULL; | ||
| 431 | iounmap(cc_base); | ||
| 432 | new_drvdata->cc_base = NULL; | ||
| 433 | } | ||
| 434 | release_mem_region(new_drvdata->res_mem->start, | ||
| 435 | resource_size(new_drvdata->res_mem)); | ||
| 436 | new_drvdata->res_mem = NULL; | ||
| 437 | } | ||
| 438 | kfree(new_drvdata); | ||
| 439 | dev_set_drvdata(&plat_dev->dev, NULL); | ||
| 440 | } | ||
| 441 | |||
| 442 | return rc; | 403 | return rc; |
| 443 | } | 404 | } |
| 444 | 405 | ||
| 445 | void fini_cc_regs(struct ssi_drvdata *drvdata) | 406 | void fini_cc_regs(struct ssi_drvdata *drvdata) |
| 446 | { | 407 | { |
| 447 | /* Mask all interrupts */ | 408 | /* Mask all interrupts */ |
| 448 | WRITE_REGISTER(drvdata->cc_base + | 409 | cc_iowrite(drvdata, CC_REG(HOST_IMR), 0xFFFFFFFF); |
| 449 | CC_REG_OFFSET(HOST_RGF, HOST_IMR), 0xFFFFFFFF); | ||
| 450 | } | 410 | } |
| 451 | 411 | ||
| 452 | static void cleanup_cc_resources(struct platform_device *plat_dev) | 412 | static void cleanup_cc_resources(struct platform_device *plat_dev) |
| 453 | { | 413 | { |
| 454 | struct ssi_drvdata *drvdata = | 414 | struct ssi_drvdata *drvdata = |
| 455 | (struct ssi_drvdata *)dev_get_drvdata(&plat_dev->dev); | 415 | (struct ssi_drvdata *)platform_get_drvdata(plat_dev); |
| 456 | 416 | ||
| 457 | ssi_aead_free(drvdata); | 417 | ssi_aead_free(drvdata); |
| 458 | ssi_hash_free(drvdata); | 418 | ssi_hash_free(drvdata); |
| @@ -466,22 +426,8 @@ static void cleanup_cc_resources(struct platform_device *plat_dev) · 7 unmodified lines | |||
| 466 | #ifdef ENABLE_CC_SYSFS | 426 | #ifdef ENABLE_CC_SYSFS |
| 467 | ssi_sysfs_fini(); | 427 | ssi_sysfs_fini(); |
| 468 | #endif | 428 | #endif |
| 469 | |||
| 470 | fini_cc_regs(drvdata); | 429 | fini_cc_regs(drvdata); |
| 471 | cc_clk_off(drvdata); | 430 | cc_clk_off(drvdata); |
| 472 | free_irq(drvdata->res_irq->start, drvdata); | ||
| 473 | drvdata->res_irq = NULL; | ||
| 474 | |||
| 475 | if (drvdata->cc_base) { | ||
| 476 | iounmap(drvdata->cc_base); | ||
| 477 | release_mem_region(drvdata->res_mem->start, | ||
| 478 | resource_size(drvdata->res_mem)); | ||
| 479 | drvdata->cc_base = NULL; | ||
| 480 | drvdata->res_mem = NULL; | ||
| 481 | } | ||
| 482 | |||
| 483 | kfree(drvdata); | ||
| 484 | dev_set_drvdata(&plat_dev->dev, NULL); | ||
| 485 | } | 431 | } |
| 486 | 432 | ||
| 487 | int cc_clk_on(struct ssi_drvdata *drvdata) | 433 | int cc_clk_on(struct ssi_drvdata *drvdata) |
| @@ -514,18 +460,19 @@ void cc_clk_off(struct ssi_drvdata *drvdata) · 26 unmodified lines | |||
| 514 | static int cc7x_probe(struct platform_device *plat_dev) | 460 | static int cc7x_probe(struct platform_device *plat_dev) |
| 515 | { | 461 | { |
| 516 | int rc; | 462 | int rc; |
| 463 | struct device *dev = &plat_dev->dev; | ||
| 517 | #if defined(CONFIG_ARM) && defined(CC_DEBUG) | 464 | #if defined(CONFIG_ARM) && defined(CC_DEBUG) |
| 518 | u32 ctr, cacheline_size; | 465 | u32 ctr, cacheline_size; |
| 519 | 466 | ||
| 520 | asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr)); | 467 | asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr)); |
| 521 | cacheline_size = 4 << ((ctr >> 16) & 0xf); | 468 | cacheline_size = 4 << ((ctr >> 16) & 0xf); |
| 522 | SSI_LOG_DEBUG("CP15(L1_CACHE_BYTES) = %u , Kconfig(L1_CACHE_BYTES) = %u\n", | 469 | dev_dbg(dev, "CP15(L1_CACHE_BYTES) = %u , Kconfig(L1_CACHE_BYTES) = %u\n", |
| 523 | cacheline_size, L1_CACHE_BYTES); | 470 | cacheline_size, L1_CACHE_BYTES); |
| 524 | 471 | ||
| 525 | asm volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (ctr)); | 472 | asm volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (ctr)); |
| 526 | SSI_LOG_DEBUG("Main ID register (MIDR): Implementer 0x%02X, Arch 0x%01X, Part 0x%03X, Rev r%dp%d\n", | 473 | dev_dbg(dev, "Main ID register (MIDR): Implementer 0x%02X, Arch 0x%01X, Part 0x%03X, Rev r%dp%d\n", |
| 527 | (ctr >> 24), (ctr >> 16) & 0xF, (ctr >> 4) & 0xFFF, | 474 | (ctr >> 24), (ctr >> 16) & 0xF, (ctr >> 4) & 0xFFF, |
| 528 | (ctr >> 20) & 0xF, ctr & 0xF); | 475 | (ctr >> 20) & 0xF, ctr & 0xF); |
| 529 | #endif | 476 | #endif |
| 530 | 477 | ||
| 531 | /* Map registers space */ | 478 | /* Map registers space */ |
| @@ -533,18 +480,20 @@ static int cc7x_probe(struct platform_device *plat_dev) · 1 unmodified line | |||
| 533 | if (rc != 0) | 480 | if (rc != 0) |
| 534 | return rc; | 481 | return rc; |
| 535 | 482 | ||
| 536 | SSI_LOG(KERN_INFO, "ARM cc7x_ree device initialized\n"); | 483 | dev_info(dev, "ARM ccree device initialized\n"); |
| 537 | 484 | ||
| 538 | return 0; | 485 | return 0; |
| 539 | } | 486 | } |
| 540 | 487 | ||
| 541 | static int cc7x_remove(struct platform_device *plat_dev) | 488 | static int cc7x_remove(struct platform_device *plat_dev) |
| 542 | { | 489 | { |
| 543 | SSI_LOG_DEBUG("Releasing cc7x resources...\n"); | 490 | struct device *dev = &plat_dev->dev; |
| 491 | |||
| 492 | dev_dbg(dev, "Releasing cc7x resources...\n"); | ||
| 544 | 493 | ||
| 545 | cleanup_cc_resources(plat_dev); | 494 | cleanup_cc_resources(plat_dev); |
| 546 | 495 | ||
| 547 | SSI_LOG(KERN_INFO, "ARM cc7x_ree device terminated\n"); | 496 | dev_info(dev, "ARM ccree device terminated\n"); |
| 548 | 497 | ||
| 549 | return 0; | 498 | return 0; |
| 550 | } | 499 | } |
| @@ -37,13 +37,11 @@ · 36 unmodified lines | |||
| 37 | #include <crypto/hash.h> | 37 | #include <crypto/hash.h> |
| 38 | #include <linux/version.h> | 38 | #include <linux/version.h> |
| 39 | #include <linux/clk.h> | 39 | #include <linux/clk.h> |
| 40 | #include <linux/platform_device.h> | ||
| 40 | 41 | ||
| 41 | /* Registers definitions from shared/hw/ree_include */ | 42 | /* Registers definitions from shared/hw/ree_include */ |
| 42 | #include "dx_reg_base_host.h" | ||
| 43 | #include "dx_host.h" | 43 | #include "dx_host.h" |
| 44 | #include "cc_regs.h" | ||
| 45 | #include "dx_reg_common.h" | 44 | #include "dx_reg_common.h" |
| 46 | #include "cc_hal.h" | ||
| 47 | #define CC_SUPPORT_SHA DX_DEV_SHA_MAX | 45 | #define CC_SUPPORT_SHA DX_DEV_SHA_MAX |
| 48 | #include "cc_crypto_ctx.h" | 46 | #include "cc_crypto_ctx.h" |
| 49 | #include "ssi_sysfs.h" | 47 | #include "ssi_sysfs.h" |
| @@ -68,12 +66,19 @@ · 18 unmodified lines | |||
| 68 | #define SSI_AXI_IRQ_MASK ((1 << DX_AXIM_CFG_BRESPMASK_BIT_SHIFT) | (1 << DX_AXIM_CFG_RRESPMASK_BIT_SHIFT) | \ | 66 | #define SSI_AXI_IRQ_MASK ((1 << DX_AXIM_CFG_BRESPMASK_BIT_SHIFT) | (1 << DX_AXIM_CFG_RRESPMASK_BIT_SHIFT) | \ |
| 69 | (1 << DX_AXIM_CFG_INFLTMASK_BIT_SHIFT) | (1 << DX_AXIM_CFG_COMPMASK_BIT_SHIFT)) | 67 | (1 << DX_AXIM_CFG_INFLTMASK_BIT_SHIFT) | (1 << DX_AXIM_CFG_COMPMASK_BIT_SHIFT)) |
| 70 | 68 | ||
| 71 | #define SSI_AXI_ERR_IRQ_MASK (1 << DX_HOST_IRR_AXI_ERR_INT_BIT_SHIFT) | 69 | #define SSI_AXI_ERR_IRQ_MASK BIT(DX_HOST_IRR_AXI_ERR_INT_BIT_SHIFT) |
| 72 | 70 | ||
| 73 | #define SSI_COMP_IRQ_MASK (1 << DX_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT) | 71 | #define SSI_COMP_IRQ_MASK BIT(DX_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT) |
| 72 | |||
| 73 | #define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \ | ||
| 74 | DX_AXIM_MON_COMP_VALUE_BIT_SHIFT, \ | ||
| 75 | DX_AXIM_MON_COMP_VALUE_BIT_SHIFT) | ||
| 76 | |||
| 77 | /* Register name mangling macro */ | ||
| 78 | #define CC_REG(reg_name) DX_ ## reg_name ## _REG_OFFSET | ||
| 74 | 79 | ||
| 75 | /* TEE FIPS status interrupt */ | 80 | /* TEE FIPS status interrupt */ |
| 76 | #define SSI_GPR0_IRQ_MASK (1 << DX_HOST_IRR_GPR0_BIT_SHIFT) | 81 | #define SSI_GPR0_IRQ_MASK BIT(DX_HOST_IRR_GPR0_BIT_SHIFT) |
| 77 | 82 | ||
| 78 | #define SSI_CRA_PRIO 3000 | 83 | #define SSI_CRA_PRIO 3000 |
| 79 | 84 | ||
| @@ -90,19 +95,6 @@ · 10 unmodified lines | |||
| 90 | * field in the HW descriptor. The DMA engine +8 that value. | 95 | * field in the HW descriptor. The DMA engine +8 that value. |
| 91 | */ | 96 | */ |
| 92 | 97 | ||
| 93 | /* Logging macros */ | ||
| 94 | #define SSI_LOG(level, format, ...) \ | ||
| 95 | printk(level "cc715ree::%s: " format, __func__, ##__VA_ARGS__) | ||
| 96 | #define SSI_LOG_ERR(format, ...) SSI_LOG(KERN_ERR, format, ##__VA_ARGS__) | ||
| 97 | #define SSI_LOG_WARNING(format, ...) SSI_LOG(KERN_WARNING, format, ##__VA_ARGS__) | ||
| 98 | #define SSI_LOG_NOTICE(format, ...) SSI_LOG(KERN_NOTICE, format, ##__VA_ARGS__) | ||
| 99 | #define SSI_LOG_INFO(format, ...) SSI_LOG(KERN_INFO, format, ##__VA_ARGS__) | ||
| 100 | #ifdef CC_DEBUG | ||
| 101 | #define SSI_LOG_DEBUG(format, ...) SSI_LOG(KERN_DEBUG, format, ##__VA_ARGS__) | ||
| 102 | #else /* Debug log messages are removed at compile time for non-DEBUG config. */ | ||
| 103 | #define SSI_LOG_DEBUG(format, ...) do {} while (0) | ||
| 104 | #endif | ||
| 105 | |||
| 106 | #define MIN(a, b) (((a) < (b)) ? (a) : (b)) | 98 | #define MIN(a, b) (((a) < (b)) ? (a) : (b)) |
| 107 | #define MAX(a, b) (((a) > (b)) ? (a) : (b)) | 99 | #define MAX(a, b) (((a) > (b)) ? (a) : (b)) |
| 108 | 100 | ||
| @@ -128,10 +120,8 @@ struct ssi_crypto_req { · 19 unmodified lines | |||
| 128 | * @fw_ver: SeP loaded firmware version | 120 | * @fw_ver: SeP loaded firmware version |
| 129 | */ | 121 | */ |
| 130 | struct ssi_drvdata { | 122 | struct ssi_drvdata { |
| 131 | struct resource *res_mem; | ||
| 132 | struct resource *res_irq; | ||
| 133 | void __iomem *cc_base; | 123 | void __iomem *cc_base; |
| 134 | unsigned int irq; | 124 | int irq; |
| 135 | u32 irq_mask; | 125 | u32 irq_mask; |
| 136 | u32 fw_ver; | 126 | u32 fw_ver; |
| 137 | /* Calibration time of start/stop | 127 | /* Calibration time of start/stop |
| @@ -140,7 +130,6 @@ struct ssi_drvdata { · 2 unmodified lines | |||
| 140 | u32 monitor_null_cycles; | 130 | u32 monitor_null_cycles; |
| 141 | struct platform_device *plat_dev; | 131 | struct platform_device *plat_dev; |
| 142 | ssi_sram_addr_t mlli_sram_addr; | 132 | ssi_sram_addr_t mlli_sram_addr; |
| 143 | struct completion icache_setup_completion; | ||
| 144 | void *buff_mgr_handle; | 133 | void *buff_mgr_handle; |
| 145 | void *hash_handle; | 134 | void *hash_handle; |
| 146 | void *aead_handle; | 135 | void *aead_handle; |
| @@ -149,7 +138,6 @@ struct ssi_drvdata { · 2 unmodified lines | |||
| 149 | void *fips_handle; | 138 | void *fips_handle; |
| 150 | void *ivgen_handle; | 139 | void *ivgen_handle; |
| 151 | void *sram_mgr_handle; | 140 | void *sram_mgr_handle; |
| 152 | u32 inflight_counter; | ||
| 153 | struct clk *clk; | 141 | struct clk *clk; |
| 154 | bool coherent; | 142 | bool coherent; |
| 155 | }; | 143 | }; |
| @@ -187,11 +175,16 @@ struct async_gen_req_ctx { · 31 unmodified lines | |||
| 187 | enum drv_crypto_direction op_type; | 175 | enum drv_crypto_direction op_type; |
| 188 | }; | 176 | }; |
| 189 | 177 | ||
| 178 | static inline struct device *drvdata_to_dev(struct ssi_drvdata *drvdata) | ||
| 179 | { | ||
| 180 | return &drvdata->plat_dev->dev; | ||
| 181 | } | ||
| 182 | |||
| 190 | #ifdef DX_DUMP_BYTES | 183 | #ifdef DX_DUMP_BYTES |
| 191 | void dump_byte_array(const char *name, const u8 *the_array, unsigned long size); | 184 | void dump_byte_array(const char *name, const u8 *the_array, unsigned long size); |
| 192 | #else | 185 | #else |
| 193 | #define dump_byte_array(name, array, size) do { \ | 186 | static inline void dump_byte_array(const char *name, const u8 *the_array, |
| 194 | } while (0); | 187 | unsigned long size) {}; |
| 195 | #endif | 188 | #endif |
| 196 | 189 | ||
| 197 | int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe); | 190 | int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe); |
| @@ -199,5 +192,15 @@ void fini_cc_regs(struct ssi_drvdata *drvdata); · 1 unmodified line | |||
| 199 | int cc_clk_on(struct ssi_drvdata *drvdata); | 192 | int cc_clk_on(struct ssi_drvdata *drvdata); |
| 200 | void cc_clk_off(struct ssi_drvdata *drvdata); | 193 | void cc_clk_off(struct ssi_drvdata *drvdata); |
| 201 | 194 | ||
| 195 | static inline void cc_iowrite(struct ssi_drvdata *drvdata, u32 reg, u32 val) | ||
| 196 | { | ||
| 197 | iowrite32(val, (drvdata->cc_base + reg)); | ||
| 198 | } | ||
| 199 | |||
| 200 | static inline u32 cc_ioread(struct ssi_drvdata *drvdata, u32 reg) | ||
| 201 | { | ||
| 202 | return ioread32(drvdata->cc_base + reg); | ||
| 203 | } | ||
| 204 | |||
| 202 | #endif /*__SSI_DRIVER_H__*/ | 205 | #endif /*__SSI_DRIVER_H__*/ |
| 203 | 206 | ||
| @@ -19,7 +19,6 @@ · 18 unmodified lines | |||
| 19 | 19 | ||
| 20 | #include "ssi_config.h" | 20 | #include "ssi_config.h" |
| 21 | #include "ssi_driver.h" | 21 | #include "ssi_driver.h" |
| 22 | #include "cc_hal.h" | ||
| 23 | #include "ssi_fips.h" | 22 | #include "ssi_fips.h" |
| 24 | 23 | ||
| 25 | static void fips_dsr(unsigned long devarg); | 24 | static void fips_dsr(unsigned long devarg); |
| @@ -34,9 +33,8 @@ struct ssi_fips_handle { · 8 unmodified lines | |||
| 34 | static bool cc_get_tee_fips_status(struct ssi_drvdata *drvdata) | 33 | static bool cc_get_tee_fips_status(struct ssi_drvdata *drvdata) |
| 35 | { | 34 | { |
| 36 | u32 reg; | 35 | u32 reg; |
| 37 | void __iomem *cc_base = drvdata->cc_base; | ||
| 38 | 36 | ||
| 39 | reg = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, GPR_HOST)); | 37 | reg = cc_ioread(drvdata, CC_REG(GPR_HOST)); |
| 40 | return (reg == (CC_FIPS_SYNC_TEE_STATUS | CC_FIPS_SYNC_MODULE_OK)); | 38 | return (reg == (CC_FIPS_SYNC_TEE_STATUS | CC_FIPS_SYNC_MODULE_OK)); |
| 41 | } | 39 | } |
| 42 | 40 | ||
| @@ -46,12 +44,11 @@ static bool cc_get_tee_fips_status(struct ssi_drvdata *drvdata) · 3 unmodified lines | |||
| 46 | */ | 44 | */ |
| 47 | void cc_set_ree_fips_status(struct ssi_drvdata *drvdata, bool status) | 45 | void cc_set_ree_fips_status(struct ssi_drvdata *drvdata, bool status) |
| 48 | { | 46 | { |
| 49 | void __iomem *cc_base = drvdata->cc_base; | ||
| 50 | int val = CC_FIPS_SYNC_REE_STATUS; | 47 | int val = CC_FIPS_SYNC_REE_STATUS; |
| 51 | 48 | ||
| 52 | val |= (status ? CC_FIPS_SYNC_MODULE_OK : CC_FIPS_SYNC_MODULE_ERROR); | 49 | val |= (status ? CC_FIPS_SYNC_MODULE_OK : CC_FIPS_SYNC_MODULE_ERROR); |
| 53 | 50 | ||
| 54 | CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_GPR0), val); | 51 | cc_iowrite(drvdata, CC_REG(HOST_GPR0), val); |
| 55 | } | 52 | } |
| 56 | 53 | ||
| 57 | void ssi_fips_fini(struct ssi_drvdata *drvdata) | 54 | void ssi_fips_fini(struct ssi_drvdata *drvdata) |
| @@ -76,41 +73,42 @@ void fips_handler(struct ssi_drvdata *drvdata) · 18 unmodified lines | |||
| 76 | tasklet_schedule(&fips_handle_ptr->tasklet); | 73 | tasklet_schedule(&fips_handle_ptr->tasklet); |
| 77 | } | 74 | } |
| 78 | 75 | ||
| 79 | static inline void tee_fips_error(void) | 76 | static inline void tee_fips_error(struct device *dev) |
| 80 | { | 77 | { |
| 81 | if (fips_enabled) | 78 | if (fips_enabled) |
| 82 | panic("ccree: TEE reported cryptographic error in fips mode!\n"); | 79 | panic("ccree: TEE reported cryptographic error in fips mode!\n"); |
| 83 | else | 80 | else |
| 84 | SSI_LOG_ERR("TEE reported error!\n"); | 81 | dev_err(dev, "TEE reported error!\n"); |
| 85 | } | 82 | } |
| 86 | 83 | ||
| 87 | /* Deferred service handler, run as interrupt-fired tasklet */ | 84 | /* Deferred service handler, run as interrupt-fired tasklet */ |
| 88 | static void fips_dsr(unsigned long devarg) | 85 | static void fips_dsr(unsigned long devarg) |
| 89 | { | 86 | { |
| 90 | struct ssi_drvdata *drvdata = (struct ssi_drvdata *)devarg; | 87 | struct ssi_drvdata *drvdata = (struct ssi_drvdata *)devarg; |
| 91 | void __iomem *cc_base = drvdata->cc_base; | 88 | struct device *dev = drvdata_to_dev(drvdata); |
| 92 | u32 irq, state, val; | 89 | u32 irq, state, val; |
| 93 | 90 | ||
| 94 | irq = (drvdata->irq & (SSI_GPR0_IRQ_MASK)); | 91 | irq = (drvdata->irq & (SSI_GPR0_IRQ_MASK)); |
| 95 | 92 | ||
| 96 | if (irq) { | 93 | if (irq) { |
| 97 | state = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, GPR_HOST)); | 94 | state = cc_ioread(drvdata, CC_REG(GPR_HOST)); |
| 98 | 95 | ||
| 99 | if (state != (CC_FIPS_SYNC_TEE_STATUS | CC_FIPS_SYNC_MODULE_OK)) | 96 | if (state != (CC_FIPS_SYNC_TEE_STATUS | CC_FIPS_SYNC_MODULE_OK)) |
| 100 | tee_fips_error(); | 97 | tee_fips_error(dev); |
| 101 | } | 98 | } |
| 102 | 99 | ||
| 103 | /* after verifing that there is nothing to do, | 100 | /* after verifing that there is nothing to do, |
| 104 | * unmask AXI completion interrupt. | 101 | * unmask AXI completion interrupt. |
| 105 | */ | 102 | */ |
| 106 | val = (CC_REG_OFFSET(HOST_RGF, HOST_IMR) & ~irq); | 103 | val = (CC_REG(HOST_IMR) & ~irq); |
| 107 | CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR), val); | 104 | cc_iowrite(drvdata, CC_REG(HOST_IMR), val); |
| 108 | } | 105 | } |
| 109 | 106 | ||
| 110 | /* The function called once at driver entry point .*/ | 107 | /* The function called once at driver entry point .*/ |
| 111 | int ssi_fips_init(struct ssi_drvdata *p_drvdata) | 108 | int ssi_fips_init(struct ssi_drvdata *p_drvdata) |
| 112 | { | 109 | { |
| 113 | struct ssi_fips_handle *fips_h; | 110 | struct ssi_fips_handle *fips_h; |
| 111 | struct device *dev = drvdata_to_dev(p_drvdata); | ||
| 114 | 112 | ||
| 115 | fips_h = kzalloc(sizeof(*fips_h), GFP_KERNEL); | 113 | fips_h = kzalloc(sizeof(*fips_h), GFP_KERNEL); |
| 116 | if (!fips_h) | 114 | if (!fips_h) |
| @@ -118,11 +116,11 @@ int ssi_fips_init(struct ssi_drvdata *p_drvdata) · 1 unmodified line | |||
| 118 | 116 | ||
| 119 | p_drvdata->fips_handle = fips_h; | 117 | p_drvdata->fips_handle = fips_h; |
| 120 | 118 | ||
| 121 | SSI_LOG_DEBUG("Initializing fips tasklet\n"); | 119 | dev_dbg(dev, "Initializing fips tasklet\n"); |
| 122 | tasklet_init(&fips_h->tasklet, fips_dsr, (unsigned long)p_drvdata); | 120 | tasklet_init(&fips_h->tasklet, fips_dsr, (unsigned long)p_drvdata); |
| 123 | 121 | ||
| 124 | if (!cc_get_tee_fips_status(p_drvdata)) | 122 | if (!cc_get_tee_fips_status(p_drvdata)) |
| 125 | tee_fips_error(); | 123 | tee_fips_error(dev); |
| 126 | 124 | ||
| 127 | return 0; | 125 | return 0; |
| 128 | } | 126 | } |
| @@ -40,8 +40,8 @@ static inline int ssi_fips_init(struct ssi_drvdata *p_drvdata) · 39 unmodified lines | |||
| 40 | } | 40 | } |
| 41 | 41 | ||
| 42 | static inline void ssi_fips_fini(struct ssi_drvdata *drvdata) {} | 42 | static inline void ssi_fips_fini(struct ssi_drvdata *drvdata) {} |
| 43 | void cc_set_ree_fips_status(struct ssi_drvdata *drvdata, bool ok) {} | 43 | static inline void cc_set_ree_fips_status(struct ssi_drvdata *drvdata, bool ok) {} |
| 44 | void fips_handler(struct ssi_drvdata *drvdata) {} | 44 | static inline void fips_handler(struct ssi_drvdata *drvdata) {} |
| 45 | 45 | ||
| 46 | #endif /* CONFIG_CRYPTO_FIPS */ | 46 | #endif /* CONFIG_CRYPTO_FIPS */ |
| 47 | 47 | ||
| @@ -134,14 +134,13 @@ static int ssi_hash_map_result(struct device *dev, · 133 unmodified lines | |||
| 134 | digestsize, | 134 | digestsize, |
| 135 | DMA_BIDIRECTIONAL); | 135 | DMA_BIDIRECTIONAL); |
| 136 | if (unlikely(dma_mapping_error(dev, state->digest_result_dma_addr))) { | 136 | if (unlikely(dma_mapping_error(dev, state->digest_result_dma_addr))) { |
| 137 | SSI_LOG_ERR("Mapping digest result buffer %u B for DMA failed\n", | 137 | dev_err(dev, "Mapping digest result buffer %u B for DMA failed\n", |
| 138 | digestsize); | 138 | digestsize); |
| 139 | return -ENOMEM; | 139 | return -ENOMEM; |
| 140 | } | 140 | } |
| 141 | SSI_LOG_DEBUG("Mapped digest result buffer %u B " | 141 | dev_dbg(dev, "Mapped digest result buffer %u B at va=%pK to dma=%pad\n", |
| 142 | "at va=%pK to dma=%pad\n", | ||
| 143 | digestsize, state->digest_result_buff, | 142 | digestsize, state->digest_result_buff, |
| 144 | state->digest_result_dma_addr); | 143 | &state->digest_result_dma_addr); |
| 145 | 144 | ||
| 146 | return 0; | 145 | return 0; |
| 147 | } | 146 | } |
| @@ -158,54 +157,50 @@ static int ssi_hash_map_request(struct device *dev, · 10 unmodified lines | |||
| 158 | int rc = -ENOMEM; | 157 | int rc = -ENOMEM; |
| 159 | 158 | ||
| 160 | state->buff0 = kzalloc(SSI_MAX_HASH_BLCK_SIZE, GFP_KERNEL | GFP_DMA); | 159 | state->buff0 = kzalloc(SSI_MAX_HASH_BLCK_SIZE, GFP_KERNEL | GFP_DMA); |
| 161 | if (!state->buff0) { | 160 | if (!state->buff0) |
| 162 | SSI_LOG_ERR("Allocating buff0 in context failed\n"); | ||
| 163 | goto fail0; | 161 | goto fail0; |
| 164 | } | 162 | |
| 165 | state->buff1 = kzalloc(SSI_MAX_HASH_BLCK_SIZE, GFP_KERNEL | GFP_DMA); | 163 | state->buff1 = kzalloc(SSI_MAX_HASH_BLCK_SIZE, GFP_KERNEL | GFP_DMA); |
| 166 | if (!state->buff1) { | 164 | if (!state->buff1) |
| 167 | SSI_LOG_ERR("Allocating buff1 in context failed\n"); | ||
| 168 | goto fail_buff0; | 165 | goto fail_buff0; |
| 169 | } | 166 | |
| 170 | state->digest_result_buff = kzalloc(SSI_MAX_HASH_DIGEST_SIZE, GFP_KERNEL | GFP_DMA); | 167 | state->digest_result_buff = kzalloc(SSI_MAX_HASH_DIGEST_SIZE, GFP_KERNEL | GFP_DMA); |
| 171 | if (!state->digest_result_buff) { | 168 | if (!state->digest_result_buff) |
| 172 | SSI_LOG_ERR("Allocating digest_result_buff in context failed\n"); | ||
| 173 | goto fail_buff1; | 169 | goto fail_buff1; |
| 174 | } | 170 | |
| 175 | state->digest_buff = kzalloc(ctx->inter_digestsize, GFP_KERNEL | GFP_DMA); | 171 | state->digest_buff = kzalloc(ctx->inter_digestsize, GFP_KERNEL | GFP_DMA); |
| 176 | if (!state->digest_buff) { | 172 | if (!state->digest_buff) |
| 177 | SSI_LOG_ERR("Allocating digest-buffer in context failed\n"); | ||
| 178 | goto fail_digest_result_buff; | 173 | goto fail_digest_result_buff; |
| 179 | } | ||
| 180 | 174 | ||
| 181 | SSI_LOG_DEBUG("Allocated digest-buffer in context ctx->digest_buff=@%p\n", state->digest_buff); | 175 | dev_dbg(dev, "Allocated digest-buffer in context ctx->digest_buff=@%p\n", |
| 176 | state->digest_buff); | ||
| 182 | if (ctx->hw_mode != DRV_CIPHER_XCBC_MAC) { | 177 | if (ctx->hw_mode != DRV_CIPHER_XCBC_MAC) { |
| 183 | state->digest_bytes_len = kzalloc(HASH_LEN_SIZE, GFP_KERNEL | GFP_DMA); | 178 | state->digest_bytes_len = kzalloc(HASH_LEN_SIZE, GFP_KERNEL | GFP_DMA); |
| 184 | if (!state->digest_bytes_len) { | 179 | if (!state->digest_bytes_len) |
| 185 | SSI_LOG_ERR("Allocating digest-bytes-len in context failed\n"); | ||
| 186 | goto fail1; | 180 | goto fail1; |
| 187 | } | 181 | |
| 188 | SSI_LOG_DEBUG("Allocated digest-bytes-len in context state->>digest_bytes_len=@%p\n", state->digest_bytes_len); | 182 | dev_dbg(dev, "Allocated digest-bytes-len in context state->>digest_bytes_len=@%p\n", |
| 183 | state->digest_bytes_len); | ||
| 189 | } else { | 184 | } else { |
| 190 | state->digest_bytes_len = NULL; | 185 | state->digest_bytes_len = NULL; |
| 191 | } | 186 | } |
| 192 | 187 | ||
| 193 | state->opad_digest_buff = kzalloc(ctx->inter_digestsize, GFP_KERNEL | GFP_DMA); | 188 | state->opad_digest_buff = kzalloc(ctx->inter_digestsize, GFP_KERNEL | GFP_DMA); |
| 194 | if (!state->opad_digest_buff) { | 189 | if (!state->opad_digest_buff) |
| 195 | SSI_LOG_ERR("Allocating opad-digest-buffer in context failed\n"); | ||
| 196 | goto fail2; | 190 | goto fail2; |
| 197 | } | 191 | |
| 198 | SSI_LOG_DEBUG("Allocated opad-digest-buffer in context state->digest_bytes_len=@%p\n", state->opad_digest_buff); | 192 | dev_dbg(dev, "Allocated opad-digest-buffer in context state->digest_bytes_len=@%p\n", |
| 193 | state->opad_digest_buff); | ||
| 199 | 194 | ||
| 200 | state->digest_buff_dma_addr = dma_map_single(dev, (void *)state->digest_buff, ctx->inter_digestsize, DMA_BIDIRECTIONAL); | 195 | state->digest_buff_dma_addr = dma_map_single(dev, (void *)state->digest_buff, ctx->inter_digestsize, DMA_BIDIRECTIONAL); |
| 201 | if (dma_mapping_error(dev, state->digest_buff_dma_addr)) { | 196 | if (dma_mapping_error(dev, state->digest_buff_dma_addr)) { |
| 202 | SSI_LOG_ERR("Mapping digest len %d B at va=%pK for DMA failed\n", | 197 | dev_err(dev, "Mapping digest len %d B at va=%pK for DMA failed\n", |
| 203 | ctx->inter_digestsize, state->digest_buff); | 198 | ctx->inter_digestsize, state->digest_buff); |
| 204 | goto fail3; | 199 | goto fail3; |
| 205 | } | 200 | } |
| 206 | SSI_LOG_DEBUG("Mapped digest %d B at va=%pK to dma=%pad\n", | 201 | dev_dbg(dev, "Mapped digest %d B at va=%pK to dma=%pad\n", |
| 207 | ctx->inter_digestsize, state->digest_buff, | 202 | ctx->inter_digestsize, state->digest_buff, |
| 208 | state->digest_buff_dma_addr); | 203 | &state->digest_buff_dma_addr); |
| 209 | 204 | ||
| 210 | if (is_hmac) { | 205 | if (is_hmac) { |
| 211 | dma_sync_single_for_cpu(dev, ctx->digest_buff_dma_addr, ctx->inter_digestsize, DMA_BIDIRECTIONAL); | 206 | dma_sync_single_for_cpu(dev, ctx->digest_buff_dma_addr, ctx->inter_digestsize, DMA_BIDIRECTIONAL); |
| @@ -240,7 +235,7 @@ static int ssi_hash_map_request(struct device *dev, · 28 unmodified lines | |||
| 240 | 235 | ||
| 241 | rc = send_request(ctx->drvdata, &ssi_req, &desc, 1, 0); | 236 | rc = send_request(ctx->drvdata, &ssi_req, &desc, 1, 0); |
| 242 | if (unlikely(rc != 0)) { | 237 | if (unlikely(rc != 0)) { |
| 243 | SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc); | 238 | dev_err(dev, "send_request() failed (rc=%d)\n", rc); |
| 244 | goto fail4; | 239 | goto fail4; |
| 245 | } | 240 | } |
| 246 | } | 241 | } |
| @@ -248,13 +243,13 @@ static int ssi_hash_map_request(struct device *dev, · 1 unmodified line | |||
| 248 | if (ctx->hw_mode != DRV_CIPHER_XCBC_MAC) { | 243 | if (ctx->hw_mode != DRV_CIPHER_XCBC_MAC) { |
| 249 | state->digest_bytes_len_dma_addr = dma_map_single(dev, (void *)state->digest_bytes_len, HASH_LEN_SIZE, DMA_BIDIRECTIONAL); | 244 | state->digest_bytes_len_dma_addr = dma_map_single(dev, (void *)state->digest_bytes_len, HASH_LEN_SIZE, DMA_BIDIRECTIONAL); |
| 250 | if (dma_mapping_error(dev, state->digest_bytes_len_dma_addr)) { | 245 | if (dma_mapping_error(dev, state->digest_bytes_len_dma_addr)) { |
| 251 | SSI_LOG_ERR("Mapping digest len %u B at va=%pK for DMA failed\n", | 246 | dev_err(dev, "Mapping digest len %u B at va=%pK for DMA failed\n", |
| 252 | HASH_LEN_SIZE, state->digest_bytes_len); | 247 | HASH_LEN_SIZE, state->digest_bytes_len); |
| 253 | goto fail4; | 248 | goto fail4; |
| 254 | } | 249 | } |
| 255 | SSI_LOG_DEBUG("Mapped digest len %u B at va=%pK to dma=%pad\n", | 250 | dev_dbg(dev, "Mapped digest len %u B at va=%pK to dma=%pad\n", |
| 256 | HASH_LEN_SIZE, state->digest_bytes_len, | 251 | HASH_LEN_SIZE, state->digest_bytes_len, |
| 257 | state->digest_bytes_len_dma_addr); | 252 | &state->digest_bytes_len_dma_addr); |
| 258 | } else { | 253 | } else { |
| 259 | state->digest_bytes_len_dma_addr = 0; | 254 | state->digest_bytes_len_dma_addr = 0; |
| 260 | } | 255 | } |
| @@ -262,14 +257,14 @@ static int ssi_hash_map_request(struct device *dev, · 1 unmodified line | |||
| 262 | if (is_hmac && ctx->hash_mode != DRV_HASH_NULL) { | 257 | if (is_hmac && ctx->hash_mode != DRV_HASH_NULL) { |
| 263 | state->opad_digest_dma_addr = dma_map_single(dev, (void *)state->opad_digest_buff, ctx->inter_digestsize, DMA_BIDIRECTIONAL); | 258 | state->opad_digest_dma_addr = dma_map_single(dev, (void *)state->opad_digest_buff, ctx->inter_digestsize, DMA_BIDIRECTIONAL); |
| 264 | if (dma_mapping_error(dev, state->opad_digest_dma_addr)) { | 259 | if (dma_mapping_error(dev, state->opad_digest_dma_addr)) { |
| 265 | SSI_LOG_ERR("Mapping opad digest %d B at va=%pK for DMA failed\n", | 260 | dev_err(dev, "Mapping opad digest %d B at va=%pK for DMA failed\n", |
| 266 | ctx->inter_digestsize, | 261 | ctx->inter_digestsize, |
| 267 | state->opad_digest_buff); | 262 | state->opad_digest_buff); |
| 268 | goto fail5; | 263 | goto fail5; |
| 269 | } | 264 | } |
| 270 | SSI_LOG_DEBUG("Mapped opad digest %d B at va=%pK to dma=%pad\n", | 265 | dev_dbg(dev, "Mapped opad digest %d B at va=%pK to dma=%pad\n", |
| 271 | ctx->inter_digestsize, state->opad_digest_buff, | 266 | ctx->inter_digestsize, state->opad_digest_buff, |
| 272 | state->opad_digest_dma_addr); | 267 | &state->opad_digest_dma_addr); |
| 273 | } else { | 268 | } else { |
| 274 | state->opad_digest_dma_addr = 0; | 269 | state->opad_digest_dma_addr = 0; |
| 275 | } | 270 | } |
| @@ -316,22 +311,22 @@ static void ssi_hash_unmap_request(struct device *dev, · 40 unmodified lines | |||
| 316 | if (state->digest_buff_dma_addr != 0) { | 311 | if (state->digest_buff_dma_addr != 0) { |
| 317 | dma_unmap_single(dev, state->digest_buff_dma_addr, | 312 | dma_unmap_single(dev, state->digest_buff_dma_addr, |
| 318 | ctx->inter_digestsize, DMA_BIDIRECTIONAL); | 313 | ctx->inter_digestsize, DMA_BIDIRECTIONAL); |
| 319 | SSI_LOG_DEBUG("Unmapped digest-buffer: digest_buff_dma_addr=%pad\n", | 314 | dev_dbg(dev, "Unmapped digest-buffer: digest_buff_dma_addr=%pad\n", |
| 320 | state->digest_buff_dma_addr); | 315 | &state->digest_buff_dma_addr); |
| 321 | state->digest_buff_dma_addr = 0; | 316 | state->digest_buff_dma_addr = 0; |
| 322 | } | 317 | } |
| 323 | if (state->digest_bytes_len_dma_addr != 0) { | 318 | if (state->digest_bytes_len_dma_addr != 0) { |
| 324 | dma_unmap_single(dev, state->digest_bytes_len_dma_addr, | 319 | dma_unmap_single(dev, state->digest_bytes_len_dma_addr, |
| 325 | HASH_LEN_SIZE, DMA_BIDIRECTIONAL); | 320 | HASH_LEN_SIZE, DMA_BIDIRECTIONAL); |
| 326 | SSI_LOG_DEBUG("Unmapped digest-bytes-len buffer: digest_bytes_len_dma_addr=%pad\n", | 321 | dev_dbg(dev, "Unmapped digest-bytes-len buffer: digest_bytes_len_dma_addr=%pad\n", |
| 327 | state->digest_bytes_len_dma_addr); | 322 | &state->digest_bytes_len_dma_addr); |
| 328 | state->digest_bytes_len_dma_addr = 0; | 323 | state->digest_bytes_len_dma_addr = 0; |
| 329 | } | 324 | } |
| 330 | if (state->opad_digest_dma_addr != 0) { | 325 | if (state->opad_digest_dma_addr != 0) { |
| 331 | dma_unmap_single(dev, state->opad_digest_dma_addr, | 326 | dma_unmap_single(dev, state->opad_digest_dma_addr, |
| 332 | ctx->inter_digestsize, DMA_BIDIRECTIONAL); | 327 | ctx->inter_digestsize, DMA_BIDIRECTIONAL); |
| 333 | SSI_LOG_DEBUG("Unmapped opad-digest: opad_digest_dma_addr=%pad\n", | 328 | dev_dbg(dev, "Unmapped opad-digest: opad_digest_dma_addr=%pad\n", |
| 334 | state->opad_digest_dma_addr); | 329 | &state->opad_digest_dma_addr); |
| 335 | state->opad_digest_dma_addr = 0; | 330 | state->opad_digest_dma_addr = 0; |
| 336 | } | 331 | } |
| 337 | 332 | ||
| @@ -352,11 +347,9 @@ static void ssi_hash_unmap_result(struct device *dev, · 14 unmodified lines | |||
| 352 | state->digest_result_dma_addr, | 347 | state->digest_result_dma_addr, |
| 353 | digestsize, | 348 | digestsize, |
| 354 | DMA_BIDIRECTIONAL); | 349 | DMA_BIDIRECTIONAL); |
| 355 | SSI_LOG_DEBUG("unmpa digest result buffer " | 350 | dev_dbg(dev, "unmpa digest result buffer va (%pK) pa (%pad) len %u\n", |
| 356 | "va (%pK) pa (%pad) len %u\n", | 351 | state->digest_result_buff, |
| 357 | state->digest_result_buff, | 352 | &state->digest_result_dma_addr, digestsize); |
| 358 | state->digest_result_dma_addr, | ||
| 359 | digestsize); | ||
| 360 | memcpy(result, | 353 | memcpy(result, |
| 361 | state->digest_result_buff, | 354 | state->digest_result_buff, |
| 362 | digestsize); | 355 | digestsize); |
| @@ -369,7 +362,7 @@ static void ssi_hash_update_complete(struct device *dev, void *ssi_req, void __i · 6 unmodified lines | |||
| 369 | struct ahash_request *req = (struct ahash_request *)ssi_req; | 362 | struct ahash_request *req = (struct ahash_request *)ssi_req; |
| 370 | struct ahash_req_ctx *state = ahash_request_ctx(req); | 363 | struct ahash_req_ctx *state = ahash_request_ctx(req); |
| 371 | 364 | ||
| 372 | SSI_LOG_DEBUG("req=%pK\n", req); | 365 | dev_dbg(dev, "req=%pK\n", req); |
| 373 | 366 | ||
| 374 | ssi_buffer_mgr_unmap_hash_request(dev, state, req->src, false); | 367 | ssi_buffer_mgr_unmap_hash_request(dev, state, req->src, false); |
| 375 | req->base.complete(&req->base, 0); | 368 | req->base.complete(&req->base, 0); |
| @@ -383,7 +376,7 @@ static void ssi_hash_digest_complete(struct device *dev, void *ssi_req, void __i · 7 unmodified lines | |||
| 383 | struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); | 376 | struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); |
| 384 | u32 digestsize = crypto_ahash_digestsize(tfm); | 377 | u32 digestsize = crypto_ahash_digestsize(tfm); |
| 385 | 378 | ||
| 386 | SSI_LOG_DEBUG("req=%pK\n", req); | 379 | dev_dbg(dev, "req=%pK\n", req); |
| 387 | 380 | ||
| 388 | ssi_buffer_mgr_unmap_hash_request(dev, state, req->src, false); | 381 | ssi_buffer_mgr_unmap_hash_request(dev, state, req->src, false); |
| 389 | ssi_hash_unmap_result(dev, state, digestsize, req->result); | 382 | ssi_hash_unmap_result(dev, state, digestsize, req->result); |
| @@ -399,7 +392,7 @@ static void ssi_hash_complete(struct device *dev, void *ssi_req, void __iomem *c · 9 unmodified lines | |||
| 399 | struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); | 392 | struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); |
| 400 | u32 digestsize = crypto_ahash_digestsize(tfm); | 393 | u32 digestsize = crypto_ahash_digestsize(tfm); |
| 401 | 394 | ||
| 402 | SSI_LOG_DEBUG("req=%pK\n", req); | 395 | dev_dbg(dev, "req=%pK\n", req); |
| 403 | 396 | ||
| 404 | ssi_buffer_mgr_unmap_hash_request(dev, state, req->src, false); | 397 | ssi_buffer_mgr_unmap_hash_request(dev, state, req->src, false); |
| 405 | ssi_hash_unmap_result(dev, state, digestsize, req->result); | 398 | ssi_hash_unmap_result(dev, state, digestsize, req->result); |
| @@ -414,7 +407,7 @@ static int ssi_hash_digest(struct ahash_req_ctx *state, · 8 unmodified lines | |||
| 414 | unsigned int nbytes, u8 *result, | 407 | unsigned int nbytes, u8 *result, |
| 415 | void *async_req) | 408 | void *async_req) |
| 416 | { | 409 | { |
| 417 | struct device *dev = &ctx->drvdata->plat_dev->dev; | 410 | struct device *dev = drvdata_to_dev(ctx->drvdata); |
| 418 | bool is_hmac = ctx->is_hmac; | 411 | bool is_hmac = ctx->is_hmac; |
| 419 | struct ssi_crypto_req ssi_req = {}; | 412 | struct ssi_crypto_req ssi_req = {}; |
| 420 | struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; | 413 | struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; |
| @@ -423,20 +416,21 @@ static int ssi_hash_digest(struct ahash_req_ctx *state, · 2 unmodified lines | |||
| 423 | int idx = 0; | 416 | int idx = 0; |
| 424 | int rc = 0; | 417 | int rc = 0; |
| 425 | 418 | ||
| 426 | SSI_LOG_DEBUG("===== %s-digest (%d) ====\n", is_hmac ? "hmac" : "hash", nbytes); | 419 | dev_dbg(dev, "===== %s-digest (%d) ====\n", is_hmac ? "hmac" : "hash", |
| 420 | nbytes); | ||
| 427 | 421 | ||
| 428 | if (unlikely(ssi_hash_map_request(dev, state, ctx) != 0)) { | 422 | if (unlikely(ssi_hash_map_request(dev, state, ctx) != 0)) { |
| 429 | SSI_LOG_ERR("map_ahash_source() failed\n"); | 423 | dev_err(dev, "map_ahash_source() failed\n"); |
| 430 | return -ENOMEM; | 424 | return -ENOMEM; |
| 431 | } | 425 | } |
| 432 | 426 | ||
| 433 | if (unlikely(ssi_hash_map_result(dev, state, digestsize) != 0)) { | 427 | if (unlikely(ssi_hash_map_result(dev, state, digestsize) != 0)) { |
| 434 | SSI_LOG_ERR("map_ahash_digest() failed\n"); | 428 | dev_err(dev, "map_ahash_digest() failed\n"); |
| 435 | return -ENOMEM; | 429 | return -ENOMEM; |
| 436 | } | 430 | } |
| 437 | 431 | ||
| 438 | if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, src, nbytes, 1) != 0)) { | 432 | if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, src, nbytes, 1) != 0)) { |
| 439 | SSI_LOG_ERR("map_ahash_request_final() failed\n"); | 433 | dev_err(dev, "map_ahash_request_final() failed\n"); |
| 440 | return -ENOMEM; | 434 | return -ENOMEM; |
| 441 | } | 435 | } |
| 442 | 436 | ||
| @@ -553,7 +547,7 @@ ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); · 110 unmodified lines | |||
| 553 | if (async_req) { | 547 | if (async_req) { |
| 554 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); | 548 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); |
| 555 | if (unlikely(rc != -EINPROGRESS)) { | 549 | if (unlikely(rc != -EINPROGRESS)) { |
| 556 | SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc); | 550 | dev_err(dev, "send_request() failed (rc=%d)\n", rc); |
| 557 | ssi_buffer_mgr_unmap_hash_request(dev, state, src, true); | 551 | ssi_buffer_mgr_unmap_hash_request(dev, state, src, true); |
| 558 | ssi_hash_unmap_result(dev, state, digestsize, result); | 552 | ssi_hash_unmap_result(dev, state, digestsize, result); |
| 559 | ssi_hash_unmap_request(dev, state, ctx); | 553 | ssi_hash_unmap_request(dev, state, ctx); |
| @@ -561,7 +555,7 @@ ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); · 1 unmodified line | |||
| 561 | } else { | 555 | } else { |
| 562 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0); | 556 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0); |
| 563 | if (rc != 0) { | 557 | if (rc != 0) { |
| 564 | SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc); | 558 | dev_err(dev, "send_request() failed (rc=%d)\n", rc); |
| 565 | ssi_buffer_mgr_unmap_hash_request(dev, state, src, true); | 559 | ssi_buffer_mgr_unmap_hash_request(dev, state, src, true); |
| 566 | } else { | 560 | } else { |
| 567 | ssi_buffer_mgr_unmap_hash_request(dev, state, src, false); | 561 | ssi_buffer_mgr_unmap_hash_request(dev, state, src, false); |
| @@ -579,14 +573,14 @@ static int ssi_hash_update(struct ahash_req_ctx *state, · 11 unmodified lines | |||
| 579 | unsigned int nbytes, | 573 | unsigned int nbytes, |
| 580 | void *async_req) | 574 | void *async_req) |
| 581 | { | 575 | { |
| 582 | struct device *dev = &ctx->drvdata->plat_dev->dev; | 576 | struct device *dev = drvdata_to_dev(ctx->drvdata); |
| 583 | struct ssi_crypto_req ssi_req = {}; | 577 | struct ssi_crypto_req ssi_req = {}; |
| 584 | struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; | 578 | struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; |
| 585 | u32 idx = 0; | 579 | u32 idx = 0; |
| 586 | int rc; | 580 | int rc; |
| 587 | 581 | ||
| 588 | SSI_LOG_DEBUG("===== %s-update (%d) ====\n", ctx->is_hmac ? | 582 | dev_dbg(dev, "===== %s-update (%d) ====\n", ctx->is_hmac ? |
| 589 | "hmac" : "hash", nbytes); | 583 | "hmac" : "hash", nbytes); |
| 590 | 584 | ||
| 591 | if (nbytes == 0) { | 585 | if (nbytes == 0) { |
| 592 | /* no real updates required */ | 586 | /* no real updates required */ |
| @@ -596,12 +590,12 @@ static int ssi_hash_update(struct ahash_req_ctx *state, · 3 unmodified lines | |||
| 596 | rc = ssi_buffer_mgr_map_hash_request_update(ctx->drvdata, state, src, nbytes, block_size); | 590 | rc = ssi_buffer_mgr_map_hash_request_update(ctx->drvdata, state, src, nbytes, block_size); |
| 597 | if (unlikely(rc)) { | 591 | if (unlikely(rc)) { |
| 598 | if (rc == 1) { | 592 | if (rc == 1) { |
| 599 | SSI_LOG_DEBUG(" data size not require HW update %x\n", | 593 | dev_dbg(dev, " data size not require HW update %x\n", |
| 600 | nbytes); | 594 | nbytes); |
| 601 | /* No hardware updates are required */ | 595 | /* No hardware updates are required */ |
| 602 | return 0; | 596 | return 0; |
| 603 | } | 597 | } |
| 604 | SSI_LOG_ERR("map_ahash_request_update() failed\n"); | 598 | dev_err(dev, "map_ahash_request_update() failed\n"); |
| 605 | return -ENOMEM; | 599 | return -ENOMEM; |
| 606 | } | 600 | } |
| 607 | 601 | ||
| @@ -653,13 +647,13 @@ static int ssi_hash_update(struct ahash_req_ctx *state, · 45 unmodified lines | |||
| 653 | if (async_req) { | 647 | if (async_req) { |
| 654 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); | 648 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); |
| 655 | if (unlikely(rc != -EINPROGRESS)) { | 649 | if (unlikely(rc != -EINPROGRESS)) { |
| 656 | SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc); | 650 | dev_err(dev, "send_request() failed (rc=%d)\n", rc); |
| 657 | ssi_buffer_mgr_unmap_hash_request(dev, state, src, true); | 651 | ssi_buffer_mgr_unmap_hash_request(dev, state, src, true); |
| 658 | } | 652 | } |
| 659 | } else { | 653 | } else { |
| 660 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0); | 654 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0); |
| 661 | if (rc != 0) { | 655 | if (rc != 0) { |
| 662 | SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc); | 656 | dev_err(dev, "send_request() failed (rc=%d)\n", rc); |
| 663 | ssi_buffer_mgr_unmap_hash_request(dev, state, src, true); | 657 | ssi_buffer_mgr_unmap_hash_request(dev, state, src, true); |
| 664 | } else { | 658 | } else { |
| 665 | ssi_buffer_mgr_unmap_hash_request(dev, state, src, false); | 659 | ssi_buffer_mgr_unmap_hash_request(dev, state, src, false); |
| @@ -676,21 +670,22 @@ static int ssi_hash_finup(struct ahash_req_ctx *state, · 10 unmodified lines | |||
| 676 | u8 *result, | 670 | u8 *result, |
| 677 | void *async_req) | 671 | void *async_req) |
| 678 | { | 672 | { |
| 679 | struct device *dev = &ctx->drvdata->plat_dev->dev; | 673 | struct device *dev = drvdata_to_dev(ctx->drvdata); |
| 680 | bool is_hmac = ctx->is_hmac; | 674 | bool is_hmac = ctx->is_hmac; |
| 681 | struct ssi_crypto_req ssi_req = {}; | 675 | struct ssi_crypto_req ssi_req = {}; |
| 682 | struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; | 676 | struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; |
| 683 | int idx = 0; | 677 | int idx = 0; |
| 684 | int rc; | 678 | int rc; |
| 685 | 679 | ||
| 686 | SSI_LOG_DEBUG("===== %s-finup (%d) ====\n", is_hmac ? "hmac" : "hash", nbytes); | 680 | dev_dbg(dev, "===== %s-finup (%d) ====\n", is_hmac ? "hmac" : "hash", |
| 681 | nbytes); | ||
| 687 | 682 | ||
| 688 | if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, src, nbytes, 1) != 0)) { | 683 | if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, src, nbytes, 1) != 0)) { |
| 689 | SSI_LOG_ERR("map_ahash_request_final() failed\n"); | 684 | dev_err(dev, "map_ahash_request_final() failed\n"); |
| 690 | return -ENOMEM; | 685 | return -ENOMEM; |
| 691 | } | 686 | } |
| 692 | if (unlikely(ssi_hash_map_result(dev, state, digestsize) != 0)) { | 687 | if (unlikely(ssi_hash_map_result(dev, state, digestsize) != 0)) { |
| 693 | SSI_LOG_ERR("map_ahash_digest() failed\n"); | 688 | dev_err(dev, "map_ahash_digest() failed\n"); |
| 694 | return -ENOMEM; | 689 | return -ENOMEM; |
| 695 | } | 690 | } |
| 696 | 691 | ||
| @@ -783,14 +778,14 @@ ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); · 86 unmodified lines | |||
| 783 | if (async_req) { | 778 | if (async_req) { |
| 784 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); | 779 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); |
| 785 | if (unlikely(rc != -EINPROGRESS)) { | 780 | if (unlikely(rc != -EINPROGRESS)) { |
| 786 | SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc); | 781 | dev_err(dev, "send_request() failed (rc=%d)\n", rc); |
| 787 | ssi_buffer_mgr_unmap_hash_request(dev, state, src, true); | 782 | ssi_buffer_mgr_unmap_hash_request(dev, state, src, true); |
| 788 | ssi_hash_unmap_result(dev, state, digestsize, result); | 783 | ssi_hash_unmap_result(dev, state, digestsize, result); |
| 789 | } | 784 | } |
| 790 | } else { | 785 | } else { |
| 791 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0); | 786 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0); |
| 792 | if (rc != 0) { | 787 | if (rc != 0) { |
| 793 | SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc); | 788 | dev_err(dev, "send_request() failed (rc=%d)\n", rc); |
| 794 | ssi_buffer_mgr_unmap_hash_request(dev, state, src, true); | 789 | ssi_buffer_mgr_unmap_hash_request(dev, state, src, true); |
| 795 | ssi_hash_unmap_result(dev, state, digestsize, result); | 790 | ssi_hash_unmap_result(dev, state, digestsize, result); |
| 796 | } else { | 791 | } else { |
| @@ -810,22 +805,23 @@ static int ssi_hash_final(struct ahash_req_ctx *state, · 13 unmodified lines | |||
| 810 | u8 *result, | 805 | u8 *result, |
| 811 | void *async_req) | 806 | void *async_req) |
| 812 | { | 807 | { |
| 813 | struct device *dev = &ctx->drvdata->plat_dev->dev; | 808 | struct device *dev = drvdata_to_dev(ctx->drvdata); |
| 814 | bool is_hmac = ctx->is_hmac; | 809 | bool is_hmac = ctx->is_hmac; |
| 815 | struct ssi_crypto_req ssi_req = {}; | 810 | struct ssi_crypto_req ssi_req = {}; |
| 816 | struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; | 811 | struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; |
| 817 | int idx = 0; | 812 | int idx = 0; |
| 818 | int rc; | 813 | int rc; |
| 819 | 814 | ||
| 820 | SSI_LOG_DEBUG("===== %s-final (%d) ====\n", is_hmac ? "hmac" : "hash", nbytes); | 815 | dev_dbg(dev, "===== %s-final (%d) ====\n", is_hmac ? "hmac" : "hash", |
| 816 | nbytes); | ||
| 821 | 817 | ||
| 822 | if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, src, nbytes, 0) != 0)) { | 818 | if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, src, nbytes, 0) != 0)) { |
| 823 | SSI_LOG_ERR("map_ahash_request_final() failed\n"); | 819 | dev_err(dev, "map_ahash_request_final() failed\n"); |
| 824 | return -ENOMEM; | 820 | return -ENOMEM; |
| 825 | } | 821 | } |
| 826 | 822 | ||
| 827 | if (unlikely(ssi_hash_map_result(dev, state, digestsize) != 0)) { | 823 | if (unlikely(ssi_hash_map_result(dev, state, digestsize) != 0)) { |
| 828 | SSI_LOG_ERR("map_ahash_digest() failed\n"); | 824 | dev_err(dev, "map_ahash_digest() failed\n"); |
| 829 | return -ENOMEM; | 825 | return -ENOMEM; |
| 830 | } | 826 | } |
| 831 | 827 | ||
| @@ -927,14 +923,14 @@ ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); · 95 unmodified lines | |||
| 927 | if (async_req) { | 923 | if (async_req) { |
| 928 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); | 924 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); |
| 929 | if (unlikely(rc != -EINPROGRESS)) { | 925 | if (unlikely(rc != -EINPROGRESS)) { |
| 930 | SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc); | 926 | dev_err(dev, "send_request() failed (rc=%d)\n", rc); |
| 931 | ssi_buffer_mgr_unmap_hash_request(dev, state, src, true); | 927 | ssi_buffer_mgr_unmap_hash_request(dev, state, src, true); |
| 932 | ssi_hash_unmap_result(dev, state, digestsize, result); | 928 | ssi_hash_unmap_result(dev, state, digestsize, result); |
| 933 | } | 929 | } |
| 934 | } else { | 930 | } else { |
| 935 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0); | 931 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0); |
| 936 | if (rc != 0) { | 932 | if (rc != 0) { |
| 937 | SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc); | 933 | dev_err(dev, "send_request() failed (rc=%d)\n", rc); |
| 938 | ssi_buffer_mgr_unmap_hash_request(dev, state, src, true); | 934 | ssi_buffer_mgr_unmap_hash_request(dev, state, src, true); |
| 939 | ssi_hash_unmap_result(dev, state, digestsize, result); | 935 | ssi_hash_unmap_result(dev, state, digestsize, result); |
| 940 | } else { | 936 | } else { |
| @@ -948,7 +944,7 @@ ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); · 7 unmodified lines | |||
| 948 | 944 | ||
| 949 | static int ssi_hash_init(struct ahash_req_ctx *state, struct ssi_hash_ctx *ctx) | 945 | static int ssi_hash_init(struct ahash_req_ctx *state, struct ssi_hash_ctx *ctx) |
| 950 | { | 946 | { |
| 951 | struct device *dev = &ctx->drvdata->plat_dev->dev; | 947 | struct device *dev = drvdata_to_dev(ctx->drvdata); |
| 952 | 948 | ||
| 953 | state->xcbc_count = 0; | 949 | state->xcbc_count = 0; |
| 954 | 950 | ||
| @@ -970,10 +966,12 @@ static int ssi_hash_setkey(void *hash, · 15 unmodified lines | |||
| 970 | int i, idx = 0, rc = 0; | 966 | int i, idx = 0, rc = 0; |
| 971 | struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; | 967 | struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; |
| 972 | ssi_sram_addr_t larval_addr; | 968 | ssi_sram_addr_t larval_addr; |
| 973 | 969 | struct device *dev; | |
| 974 | SSI_LOG_DEBUG("start keylen: %d", keylen); | ||
| 975 | 970 | ||
| 976 | ctx = crypto_ahash_ctx(((struct crypto_ahash *)hash)); | 971 | ctx = crypto_ahash_ctx(((struct crypto_ahash *)hash)); |
| 972 | dev = drvdata_to_dev(ctx->drvdata); | ||
| 973 | dev_dbg(dev, "start keylen: %d", keylen); | ||
| 974 | |||
| 977 | blocksize = crypto_tfm_alg_blocksize(&((struct crypto_ahash *)hash)->base); | 975 | blocksize = crypto_tfm_alg_blocksize(&((struct crypto_ahash *)hash)->base); |
| 978 | digestsize = crypto_ahash_digestsize(((struct crypto_ahash *)hash)); | 976 | digestsize = crypto_ahash_digestsize(((struct crypto_ahash *)hash)); |
| 979 | 977 | ||
| @@ -989,18 +987,16 @@ static int ssi_hash_setkey(void *hash, · 9 unmodified lines | |||
| 989 | 987 | ||
| 990 | if (keylen != 0) { | 988 | if (keylen != 0) { |
| 991 | ctx->key_params.key_dma_addr = dma_map_single( | 989 | ctx->key_params.key_dma_addr = dma_map_single( |
| 992 | &ctx->drvdata->plat_dev->dev, | 990 | dev, (void *)key, |
| 993 | (void *)key, | ||
| 994 | keylen, DMA_TO_DEVICE); | 991 | keylen, DMA_TO_DEVICE); |
| 995 | if (unlikely(dma_mapping_error(&ctx->drvdata->plat_dev->dev, | 992 | if (unlikely(dma_mapping_error(dev, |
| 996 | ctx->key_params.key_dma_addr))) { | 993 | ctx->key_params.key_dma_addr))) { |
| 997 | SSI_LOG_ERR("Mapping key va=0x%p len=%u for" | 994 | dev_err(dev, "Mapping key va=0x%p len=%u for DMA failed\n", |
| 998 | " DMA failed\n", key, keylen); | 995 | key, keylen); |
| 999 | return -ENOMEM; | 996 | return -ENOMEM; |
| 1000 | } | 997 | } |
| 1001 | SSI_LOG_DEBUG("mapping key-buffer: key_dma_addr=%pad " | 998 | dev_dbg(dev, "mapping key-buffer: key_dma_addr=%pad keylen=%u\n", |
| 1002 | "keylen=%u\n", ctx->key_params.key_dma_addr, | 999 | &ctx->key_params.key_dma_addr, ctx->key_params.keylen); |
| 1003 | ctx->key_params.keylen); | ||
| 1004 | 1000 | ||
| 1005 | if (keylen > blocksize) { | 1001 | if (keylen > blocksize) { |
| 1006 | /* Load hash initial state */ | 1002 | /* Load hash initial state */ |
| @@ -1079,7 +1075,7 @@ static int ssi_hash_setkey(void *hash, · 72 unmodified lines | |||
| 1079 | 1075 | ||
| 1080 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0); | 1076 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0); |
| 1081 | if (unlikely(rc != 0)) { | 1077 | if (unlikely(rc != 0)) { |
| 1082 | SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc); | 1078 | dev_err(dev, "send_request() failed (rc=%d)\n", rc); |
| 1083 | goto out; | 1079 | goto out; |
| 1084 | } | 1080 | } |
| 1085 | 1081 | ||
| @@ -1139,12 +1135,10 @@ out: · 53 unmodified lines | |||
| 1139 | crypto_ahash_set_flags((struct crypto_ahash *)hash, CRYPTO_TFM_RES_BAD_KEY_LEN); | 1135 | crypto_ahash_set_flags((struct crypto_ahash *)hash, CRYPTO_TFM_RES_BAD_KEY_LEN); |
| 1140 | 1136 | ||
| 1141 | if (ctx->key_params.key_dma_addr) { | 1137 | if (ctx->key_params.key_dma_addr) { |
| 1142 | dma_unmap_single(&ctx->drvdata->plat_dev->dev, | 1138 | dma_unmap_single(dev, ctx->key_params.key_dma_addr, |
| 1143 | ctx->key_params.key_dma_addr, | ||
| 1144 | ctx->key_params.keylen, DMA_TO_DEVICE); | 1139 | ctx->key_params.keylen, DMA_TO_DEVICE); |
| 1145 | SSI_LOG_DEBUG("Unmapped key-buffer: key_dma_addr=%pad keylen=%u\n", | 1140 | dev_dbg(dev, "Unmapped key-buffer: key_dma_addr=%pad keylen=%u\n", |
| 1146 | ctx->key_params.key_dma_addr, | 1141 | &ctx->key_params.key_dma_addr, ctx->key_params.keylen); |
| 1147 | ctx->key_params.keylen); | ||
| 1148 | } | 1142 | } |
| 1149 | return rc; | 1143 | return rc; |
| 1150 | } | 1144 | } |
| @@ -1154,10 +1148,11 @@ static int ssi_xcbc_setkey(struct crypto_ahash *ahash, · 3 unmodified lines | |||
| 1154 | { | 1148 | { |
| 1155 | struct ssi_crypto_req ssi_req = {}; | 1149 | struct ssi_crypto_req ssi_req = {}; |
| 1156 | struct ssi_hash_ctx *ctx = crypto_ahash_ctx(ahash); | 1150 | struct ssi_hash_ctx *ctx = crypto_ahash_ctx(ahash); |
| 1151 | struct device *dev = drvdata_to_dev(ctx->drvdata); | ||
| 1157 | int idx = 0, rc = 0; | 1152 | int idx = 0, rc = 0; |
| 1158 | struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; | 1153 | struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; |
| 1159 | 1154 | ||
| 1160 | SSI_LOG_DEBUG("===== setkey (%d) ====\n", keylen); | 1155 | dev_dbg(dev, "===== setkey (%d) ====\n", keylen); |
| 1161 | 1156 | ||
| 1162 | switch (keylen) { | 1157 | switch (keylen) { |
| 1163 | case AES_KEYSIZE_128: | 1158 | case AES_KEYSIZE_128: |
| @@ -1171,19 +1166,15 @@ static int ssi_xcbc_setkey(struct crypto_ahash *ahash, · 7 unmodified lines | |||
| 1171 | ctx->key_params.keylen = keylen; | 1166 | ctx->key_params.keylen = keylen; |
| 1172 | 1167 | ||
| 1173 | ctx->key_params.key_dma_addr = dma_map_single( | 1168 | ctx->key_params.key_dma_addr = dma_map_single( |
| 1174 | &ctx->drvdata->plat_dev->dev, | 1169 | dev, (void *)key, |
| 1175 | (void *)key, | ||
| 1176 | keylen, DMA_TO_DEVICE); | 1170 | keylen, DMA_TO_DEVICE); |
| 1177 | if (unlikely(dma_mapping_error(&ctx->drvdata->plat_dev->dev, | 1171 | if (unlikely(dma_mapping_error(dev, ctx->key_params.key_dma_addr))) { |
| 1178 | ctx->key_params.key_dma_addr))) { | 1172 | dev_err(dev, "Mapping key va=0x%p len=%u for DMA failed\n", |
| 1179 | SSI_LOG_ERR("Mapping key va=0x%p len=%u for" | 1173 | key, keylen); |
| 1180 | " DMA failed\n", key, keylen); | ||
| 1181 | return -ENOMEM; | 1174 | return -ENOMEM; |
| 1182 | } | 1175 | } |
| 1183 | SSI_LOG_DEBUG("mapping key-buffer: key_dma_addr=%pad " | 1176 | dev_dbg(dev, "mapping key-buffer: key_dma_addr=%pad keylen=%u\n", |
| 1184 | "keylen=%u\n", | 1177 | &ctx->key_params.key_dma_addr, ctx->key_params.keylen); |
| 1185 | ctx->key_params.key_dma_addr, | ||
| 1186 | ctx->key_params.keylen); | ||
| 1187 | 1178 | ||
| 1188 | ctx->is_hmac = true; | 1179 | ctx->is_hmac = true; |
| 1189 | /* 1. Load the AES key */ | 1180 | /* 1. Load the AES key */ |
| @@ -1226,12 +1217,10 @@ static int ssi_xcbc_setkey(struct crypto_ahash *ahash, · 36 unmodified lines | |||
| 1226 | if (rc != 0) | 1217 | if (rc != 0) |
| 1227 | crypto_ahash_set_flags(ahash, CRYPTO_TFM_RES_BAD_KEY_LEN); | 1218 | crypto_ahash_set_flags(ahash, CRYPTO_TFM_RES_BAD_KEY_LEN); |
| 1228 | 1219 | ||
| 1229 | dma_unmap_single(&ctx->drvdata->plat_dev->dev, | 1220 | dma_unmap_single(dev, ctx->key_params.key_dma_addr, |
| 1230 | ctx->key_params.key_dma_addr, | ||
| 1231 | ctx->key_params.keylen, DMA_TO_DEVICE); | 1221 | ctx->key_params.keylen, DMA_TO_DEVICE); |
| 1232 | SSI_LOG_DEBUG("Unmapped key-buffer: key_dma_addr=%pad keylen=%u\n", | 1222 | dev_dbg(dev, "Unmapped key-buffer: key_dma_addr=%pad keylen=%u\n", |
| 1233 | ctx->key_params.key_dma_addr, | 1223 | &ctx->key_params.key_dma_addr, ctx->key_params.keylen); |
| 1234 | ctx->key_params.keylen); | ||
| 1235 | 1224 | ||
| 1236 | return rc; | 1225 | return rc; |
| 1237 | } | 1226 | } |
| @@ -1241,8 +1230,9 @@ static int ssi_cmac_setkey(struct crypto_ahash *ahash, · 3 unmodified lines | |||
| 1241 | const u8 *key, unsigned int keylen) | 1230 | const u8 *key, unsigned int keylen) |
| 1242 | { | 1231 | { |
| 1243 | struct ssi_hash_ctx *ctx = crypto_ahash_ctx(ahash); | 1232 | struct ssi_hash_ctx *ctx = crypto_ahash_ctx(ahash); |
| 1233 | struct device *dev = drvdata_to_dev(ctx->drvdata); | ||
| 1244 | 1234 | ||
| 1245 | SSI_LOG_DEBUG("===== setkey (%d) ====\n", keylen); | 1235 | dev_dbg(dev, "===== setkey (%d) ====\n", keylen); |
| 1246 | 1236 | ||
| 1247 | ctx->is_hmac = true; | 1237 | ctx->is_hmac = true; |
| 1248 | 1238 | ||
| @@ -1259,16 +1249,14 @@ static int ssi_cmac_setkey(struct crypto_ahash *ahash, · 10 unmodified lines | |||
| 1259 | 1249 | ||
| 1260 | /* STAT_PHASE_1: Copy key to ctx */ | 1250 | /* STAT_PHASE_1: Copy key to ctx */ |
| 1261 | 1251 | ||
| 1262 | dma_sync_single_for_cpu(&ctx->drvdata->plat_dev->dev, | 1252 | dma_sync_single_for_cpu(dev, ctx->opad_tmp_keys_dma_addr, |
| 1263 | ctx->opad_tmp_keys_dma_addr, | ||
| 1264 | keylen, DMA_TO_DEVICE); | 1253 | keylen, DMA_TO_DEVICE); |
| 1265 | 1254 | ||
| 1266 | memcpy(ctx->opad_tmp_keys_buff, key, keylen); | 1255 | memcpy(ctx->opad_tmp_keys_buff, key, keylen); |
| 1267 | if (keylen == 24) | 1256 | if (keylen == 24) |
| 1268 | memset(ctx->opad_tmp_keys_buff + 24, 0, CC_AES_KEY_SIZE_MAX - 24); | 1257 | memset(ctx->opad_tmp_keys_buff + 24, 0, CC_AES_KEY_SIZE_MAX - 24); |
| 1269 | 1258 | ||
| 1270 | dma_sync_single_for_device(&ctx->drvdata->plat_dev->dev, | 1259 | dma_sync_single_for_device(dev, ctx->opad_tmp_keys_dma_addr, |
| 1271 | ctx->opad_tmp_keys_dma_addr, | ||
| 1272 | keylen, DMA_TO_DEVICE); | 1260 | keylen, DMA_TO_DEVICE); |
| 1273 | 1261 | ||
| 1274 | ctx->key_params.keylen = keylen; | 1262 | ctx->key_params.keylen = keylen; |
| @@ -1279,23 +1267,21 @@ static int ssi_cmac_setkey(struct crypto_ahash *ahash, · 4 unmodified lines | |||
| 1279 | 1267 | ||
| 1280 | static void ssi_hash_free_ctx(struct ssi_hash_ctx *ctx) | 1268 | static void ssi_hash_free_ctx(struct ssi_hash_ctx *ctx) |
| 1281 | { | 1269 | { |
| 1282 | struct device *dev = &ctx->drvdata->plat_dev->dev; | 1270 | struct device *dev = drvdata_to_dev(ctx->drvdata); |
| 1283 | 1271 | ||
| 1284 | if (ctx->digest_buff_dma_addr != 0) { | 1272 | if (ctx->digest_buff_dma_addr != 0) { |
| 1285 | dma_unmap_single(dev, ctx->digest_buff_dma_addr, | 1273 | dma_unmap_single(dev, ctx->digest_buff_dma_addr, |
| 1286 | sizeof(ctx->digest_buff), DMA_BIDIRECTIONAL); | 1274 | sizeof(ctx->digest_buff), DMA_BIDIRECTIONAL); |
| 1287 | SSI_LOG_DEBUG("Unmapped digest-buffer: " | 1275 | dev_dbg(dev, "Unmapped digest-buffer: digest_buff_dma_addr=%pad\n", |
| 1288 | "digest_buff_dma_addr=%pad\n", | 1276 | &ctx->digest_buff_dma_addr); |
| 1289 | ctx->digest_buff_dma_addr); | ||
| 1290 | ctx->digest_buff_dma_addr = 0; | 1277 | ctx->digest_buff_dma_addr = 0; |
| 1291 | } | 1278 | } |
| 1292 | if (ctx->opad_tmp_keys_dma_addr != 0) { | 1279 | if (ctx->opad_tmp_keys_dma_addr != 0) { |
| 1293 | dma_unmap_single(dev, ctx->opad_tmp_keys_dma_addr, | 1280 | dma_unmap_single(dev, ctx->opad_tmp_keys_dma_addr, |
| 1294 | sizeof(ctx->opad_tmp_keys_buff), | 1281 | sizeof(ctx->opad_tmp_keys_buff), |
| 1295 | DMA_BIDIRECTIONAL); | 1282 | DMA_BIDIRECTIONAL); |
| 1296 | SSI_LOG_DEBUG("Unmapped opad-digest: " | 1283 | dev_dbg(dev, "Unmapped opad-digest: opad_tmp_keys_dma_addr=%pad\n", |
| 1297 | "opad_tmp_keys_dma_addr=%pad\n", | 1284 | &ctx->opad_tmp_keys_dma_addr); |
| 1298 | ctx->opad_tmp_keys_dma_addr); | ||
| 1299 | ctx->opad_tmp_keys_dma_addr = 0; | 1285 | ctx->opad_tmp_keys_dma_addr = 0; |
| 1300 | } | 1286 | } |
| 1301 | 1287 | ||
| @@ -1304,30 +1290,30 @@ static void ssi_hash_free_ctx(struct ssi_hash_ctx *ctx) · 2 unmodified lines | |||
| 1304 | 1290 | ||
| 1305 | static int ssi_hash_alloc_ctx(struct ssi_hash_ctx *ctx) | 1291 | static int ssi_hash_alloc_ctx(struct ssi_hash_ctx *ctx) |
| 1306 | { | 1292 | { |
| 1307 | struct device *dev = &ctx->drvdata->plat_dev->dev; | 1293 | struct device *dev = drvdata_to_dev(ctx->drvdata); |
| 1308 | 1294 | ||
| 1309 | ctx->key_params.keylen = 0; | 1295 | ctx->key_params.keylen = 0; |
| 1310 | 1296 | ||
| 1311 | ctx->digest_buff_dma_addr = dma_map_single(dev, (void *)ctx->digest_buff, sizeof(ctx->digest_buff), DMA_BIDIRECTIONAL); | 1297 | ctx->digest_buff_dma_addr = dma_map_single(dev, (void *)ctx->digest_buff, sizeof(ctx->digest_buff), DMA_BIDIRECTIONAL); |
| 1312 | if (dma_mapping_error(dev, ctx->digest_buff_dma_addr)) { | 1298 | if (dma_mapping_error(dev, ctx->digest_buff_dma_addr)) { |
| 1313 | SSI_LOG_ERR("Mapping digest len %zu B at va=%pK for DMA failed\n", | 1299 | dev_err(dev, "Mapping digest len %zu B at va=%pK for DMA failed\n", |
| 1314 | sizeof(ctx->digest_buff), ctx->digest_buff); | 1300 | sizeof(ctx->digest_buff), ctx->digest_buff); |
| 1315 | goto fail; | 1301 | goto fail; |
| 1316 | } | 1302 | } |
| 1317 | SSI_LOG_DEBUG("Mapped digest %zu B at va=%pK to dma=%pad\n", | 1303 | dev_dbg(dev, "Mapped digest %zu B at va=%pK to dma=%pad\n", |
| 1318 | sizeof(ctx->digest_buff), ctx->digest_buff, | 1304 | sizeof(ctx->digest_buff), ctx->digest_buff, |
| 1319 | ctx->digest_buff_dma_addr); | 1305 | &ctx->digest_buff_dma_addr); |
| 1320 | 1306 | ||
| 1321 | ctx->opad_tmp_keys_dma_addr = dma_map_single(dev, (void *)ctx->opad_tmp_keys_buff, sizeof(ctx->opad_tmp_keys_buff), DMA_BIDIRECTIONAL); | 1307 | ctx->opad_tmp_keys_dma_addr = dma_map_single(dev, (void *)ctx->opad_tmp_keys_buff, sizeof(ctx->opad_tmp_keys_buff), DMA_BIDIRECTIONAL); |
| 1322 | if (dma_mapping_error(dev, ctx->opad_tmp_keys_dma_addr)) { | 1308 | if (dma_mapping_error(dev, ctx->opad_tmp_keys_dma_addr)) { |
| 1323 | SSI_LOG_ERR("Mapping opad digest %zu B at va=%pK for DMA failed\n", | 1309 | dev_err(dev, "Mapping opad digest %zu B at va=%pK for DMA failed\n", |
| 1324 | sizeof(ctx->opad_tmp_keys_buff), | 1310 | sizeof(ctx->opad_tmp_keys_buff), |
| 1325 | ctx->opad_tmp_keys_buff); | 1311 | ctx->opad_tmp_keys_buff); |
| 1326 | goto fail; | 1312 | goto fail; |
| 1327 | } | 1313 | } |
| 1328 | SSI_LOG_DEBUG("Mapped opad_tmp_keys %zu B at va=%pK to dma=%pad\n", | 1314 | dev_dbg(dev, "Mapped opad_tmp_keys %zu B at va=%pK to dma=%pad\n", |
| 1329 | sizeof(ctx->opad_tmp_keys_buff), ctx->opad_tmp_keys_buff, | 1315 | sizeof(ctx->opad_tmp_keys_buff), ctx->opad_tmp_keys_buff, |
| 1330 | ctx->opad_tmp_keys_dma_addr); | 1316 | &ctx->opad_tmp_keys_dma_addr); |
| 1331 | 1317 | ||
| 1332 | ctx->is_hmac = false; | 1318 | ctx->is_hmac = false; |
| 1333 | return 0; | 1319 | return 0; |
| @@ -1361,8 +1347,9 @@ static int ssi_ahash_cra_init(struct crypto_tfm *tfm) · 27 unmodified lines | |||
| 1361 | static void ssi_hash_cra_exit(struct crypto_tfm *tfm) | 1347 | static void ssi_hash_cra_exit(struct crypto_tfm *tfm) |
| 1362 | { | 1348 | { |
| 1363 | struct ssi_hash_ctx *ctx = crypto_tfm_ctx(tfm); | 1349 | struct ssi_hash_ctx *ctx = crypto_tfm_ctx(tfm); |
| 1350 | struct device *dev = drvdata_to_dev(ctx->drvdata); | ||
| 1364 | 1351 | ||
| 1365 | SSI_LOG_DEBUG("ssi_hash_cra_exit"); | 1352 | dev_dbg(dev, "ssi_hash_cra_exit"); |
| 1366 | ssi_hash_free_ctx(ctx); | 1353 | ssi_hash_free_ctx(ctx); |
| 1367 | } | 1354 | } |
| 1368 | 1355 | ||
| @@ -1371,7 +1358,7 @@ static int ssi_mac_update(struct ahash_request *req) · 2 unmodified lines | |||
| 1371 | struct ahash_req_ctx *state = ahash_request_ctx(req); | 1358 | struct ahash_req_ctx *state = ahash_request_ctx(req); |
| 1372 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); | 1359 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); |
| 1373 | struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); | 1360 | struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); |
| 1374 | struct device *dev = &ctx->drvdata->plat_dev->dev; | 1361 | struct device *dev = drvdata_to_dev(ctx->drvdata); |
| 1375 | unsigned int block_size = crypto_tfm_alg_blocksize(&tfm->base); | 1362 | unsigned int block_size = crypto_tfm_alg_blocksize(&tfm->base); |
| 1376 | struct ssi_crypto_req ssi_req = {}; | 1363 | struct ssi_crypto_req ssi_req = {}; |
| 1377 | struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; | 1364 | struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; |
| @@ -1388,12 +1375,12 @@ static int ssi_mac_update(struct ahash_request *req) · 10 unmodified lines | |||
| 1388 | rc = ssi_buffer_mgr_map_hash_request_update(ctx->drvdata, state, req->src, req->nbytes, block_size); | 1375 | rc = ssi_buffer_mgr_map_hash_request_update(ctx->drvdata, state, req->src, req->nbytes, block_size); |
| 1389 | if (unlikely(rc)) { | 1376 | if (unlikely(rc)) { |
| 1390 | if (rc == 1) { | 1377 | if (rc == 1) { |
| 1391 | SSI_LOG_DEBUG(" data size not require HW update %x\n", | 1378 | dev_dbg(dev, " data size not require HW update %x\n", |
| 1392 | req->nbytes); | 1379 | req->nbytes); |
| 1393 | /* No hardware updates are required */ | 1380 | /* No hardware updates are required */ |
| 1394 | return 0; | 1381 | return 0; |
| 1395 | } | 1382 | } |
| 1396 | SSI_LOG_ERR("map_ahash_request_update() failed\n"); | 1383 | dev_err(dev, "map_ahash_request_update() failed\n"); |
| 1397 | return -ENOMEM; | 1384 | return -ENOMEM; |
| 1398 | } | 1385 | } |
| 1399 | 1386 | ||
| @@ -1420,7 +1407,7 @@ static int ssi_mac_update(struct ahash_request *req) · 20 unmodified lines | |||
| 1420 | 1407 | ||
| 1421 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); | 1408 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); |
| 1422 | if (unlikely(rc != -EINPROGRESS)) { | 1409 | if (unlikely(rc != -EINPROGRESS)) { |
| 1423 | SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc); | 1410 | dev_err(dev, "send_request() failed (rc=%d)\n", rc); |
| 1424 | ssi_buffer_mgr_unmap_hash_request(dev, state, req->src, true); | 1411 | ssi_buffer_mgr_unmap_hash_request(dev, state, req->src, true); |
| 1425 | } | 1412 | } |
| 1426 | return rc; | 1413 | return rc; |
| @@ -1431,7 +1418,7 @@ static int ssi_mac_final(struct ahash_request *req) · 4 unmodified lines | |||
| 1431 | struct ahash_req_ctx *state = ahash_request_ctx(req); | 1418 | struct ahash_req_ctx *state = ahash_request_ctx(req); |
| 1432 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); | 1419 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); |
| 1433 | struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); | 1420 | struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); |
| 1434 | struct device *dev = &ctx->drvdata->plat_dev->dev; | 1421 | struct device *dev = drvdata_to_dev(ctx->drvdata); |
| 1435 | struct ssi_crypto_req ssi_req = {}; | 1422 | struct ssi_crypto_req ssi_req = {}; |
| 1436 | struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; | 1423 | struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; |
| 1437 | int idx = 0; | 1424 | int idx = 0; |
| @@ -1451,15 +1438,15 @@ static int ssi_mac_final(struct ahash_request *req) · 13 unmodified lines | |||
| 1451 | key_len = ctx->key_params.keylen; | 1438 | key_len = ctx->key_params.keylen; |
| 1452 | } | 1439 | } |
| 1453 | 1440 | ||
| 1454 | SSI_LOG_DEBUG("===== final xcbc reminder (%d) ====\n", rem_cnt); | 1441 | dev_dbg(dev, "===== final xcbc reminder (%d) ====\n", rem_cnt); |
| 1455 | 1442 | ||
| 1456 | if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, req->src, req->nbytes, 0) != 0)) { | 1443 | if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, req->src, req->nbytes, 0) != 0)) { |
| 1457 | SSI_LOG_ERR("map_ahash_request_final() failed\n"); | 1444 | dev_err(dev, "map_ahash_request_final() failed\n"); |
| 1458 | return -ENOMEM; | 1445 | return -ENOMEM; |
| 1459 | } | 1446 | } |
| 1460 | 1447 | ||
| 1461 | if (unlikely(ssi_hash_map_result(dev, state, digestsize) != 0)) { | 1448 | if (unlikely(ssi_hash_map_result(dev, state, digestsize) != 0)) { |
| 1462 | SSI_LOG_ERR("map_ahash_digest() failed\n"); | 1449 | dev_err(dev, "map_ahash_digest() failed\n"); |
| 1463 | return -ENOMEM; | 1450 | return -ENOMEM; |
| 1464 | } | 1451 | } |
| 1465 | 1452 | ||
| @@ -1530,7 +1517,7 @@ static int ssi_mac_final(struct ahash_request *req) · 64 unmodified lines | |||
| 1530 | 1517 | ||
| 1531 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); | 1518 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); |
| 1532 | if (unlikely(rc != -EINPROGRESS)) { | 1519 | if (unlikely(rc != -EINPROGRESS)) { |
| 1533 | SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc); | 1520 | dev_err(dev, "send_request() failed (rc=%d)\n", rc); |
| 1534 | ssi_buffer_mgr_unmap_hash_request(dev, state, req->src, true); | 1521 | ssi_buffer_mgr_unmap_hash_request(dev, state, req->src, true); |
| 1535 | ssi_hash_unmap_result(dev, state, digestsize, req->result); | 1522 | ssi_hash_unmap_result(dev, state, digestsize, req->result); |
| 1536 | } | 1523 | } |
| @@ -1542,7 +1529,7 @@ static int ssi_mac_finup(struct ahash_request *req) · 5 unmodified lines | |||
| 1542 | struct ahash_req_ctx *state = ahash_request_ctx(req); | 1529 | struct ahash_req_ctx *state = ahash_request_ctx(req); |
| 1543 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); | 1530 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); |
| 1544 | struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); | 1531 | struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); |
| 1545 | struct device *dev = &ctx->drvdata->plat_dev->dev; | 1532 | struct device *dev = drvdata_to_dev(ctx->drvdata); |
| 1546 | struct ssi_crypto_req ssi_req = {}; | 1533 | struct ssi_crypto_req ssi_req = {}; |
| 1547 | struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; | 1534 | struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; |
| 1548 | int idx = 0; | 1535 | int idx = 0; |
| @@ -1550,18 +1537,18 @@ static int ssi_mac_finup(struct ahash_request *req) · 1 unmodified line | |||
| 1550 | u32 key_len = 0; | 1537 | u32 key_len = 0; |
| 1551 | u32 digestsize = crypto_ahash_digestsize(tfm); | 1538 | u32 digestsize = crypto_ahash_digestsize(tfm); |
| 1552 | 1539 | ||
| 1553 | SSI_LOG_DEBUG("===== finup xcbc(%d) ====\n", req->nbytes); | 1540 | dev_dbg(dev, "===== finup xcbc(%d) ====\n", req->nbytes); |
| 1554 | if (state->xcbc_count > 0 && req->nbytes == 0) { | 1541 | if (state->xcbc_count > 0 && req->nbytes == 0) { |
| 1555 | SSI_LOG_DEBUG("No data to update. Call to fdx_mac_final\n"); | 1542 | dev_dbg(dev, "No data to update. Call to fdx_mac_final\n"); |
| 1556 | return ssi_mac_final(req); | 1543 | return ssi_mac_final(req); |
| 1557 | } | 1544 | } |
| 1558 | 1545 | ||
| 1559 | if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, req->src, req->nbytes, 1) != 0)) { | 1546 | if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, req->src, req->nbytes, 1) != 0)) { |
| 1560 | SSI_LOG_ERR("map_ahash_request_final() failed\n"); | 1547 | dev_err(dev, "map_ahash_request_final() failed\n"); |
| 1561 | return -ENOMEM; | 1548 | return -ENOMEM; |
| 1562 | } | 1549 | } |
| 1563 | if (unlikely(ssi_hash_map_result(dev, state, digestsize) != 0)) { | 1550 | if (unlikely(ssi_hash_map_result(dev, state, digestsize) != 0)) { |
| 1564 | SSI_LOG_ERR("map_ahash_digest() failed\n"); | 1551 | dev_err(dev, "map_ahash_digest() failed\n"); |
| 1565 | return -ENOMEM; | 1552 | return -ENOMEM; |
| 1566 | } | 1553 | } |
| 1567 | 1554 | ||
| @@ -1601,7 +1588,7 @@ static int ssi_mac_finup(struct ahash_request *req) · 33 unmodified lines | |||
| 1601 | 1588 | ||
| 1602 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); | 1589 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); |
| 1603 | if (unlikely(rc != -EINPROGRESS)) { | 1590 | if (unlikely(rc != -EINPROGRESS)) { |
| 1604 | SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc); | 1591 | dev_err(dev, "send_request() failed (rc=%d)\n", rc); |
| 1605 | ssi_buffer_mgr_unmap_hash_request(dev, state, req->src, true); | 1592 | ssi_buffer_mgr_unmap_hash_request(dev, state, req->src, true); |
| 1606 | ssi_hash_unmap_result(dev, state, digestsize, req->result); | 1593 | ssi_hash_unmap_result(dev, state, digestsize, req->result); |
| 1607 | } | 1594 | } |
| @@ -1613,7 +1600,7 @@ static int ssi_mac_digest(struct ahash_request *req) · 5 unmodified lines | |||
| 1613 | struct ahash_req_ctx *state = ahash_request_ctx(req); | 1600 | struct ahash_req_ctx *state = ahash_request_ctx(req); |
| 1614 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); | 1601 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); |
| 1615 | struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); | 1602 | struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); |
| 1616 | struct device *dev = &ctx->drvdata->plat_dev->dev; | 1603 | struct device *dev = drvdata_to_dev(ctx->drvdata); |
| 1617 | u32 digestsize = crypto_ahash_digestsize(tfm); | 1604 | u32 digestsize = crypto_ahash_digestsize(tfm); |
| 1618 | struct ssi_crypto_req ssi_req = {}; | 1605 | struct ssi_crypto_req ssi_req = {}; |
| 1619 | struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; | 1606 | struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; |
| @@ -1621,19 +1608,19 @@ static int ssi_mac_digest(struct ahash_request *req) · 1 unmodified line | |||
| 1621 | int idx = 0; | 1608 | int idx = 0; |
| 1622 | int rc; | 1609 | int rc; |
| 1623 | 1610 | ||
| 1624 | SSI_LOG_DEBUG("===== -digest mac (%d) ====\n", req->nbytes); | 1611 | dev_dbg(dev, "===== -digest mac (%d) ====\n", req->nbytes); |
| 1625 | 1612 | ||
| 1626 | if (unlikely(ssi_hash_map_request(dev, state, ctx) != 0)) { | 1613 | if (unlikely(ssi_hash_map_request(dev, state, ctx) != 0)) { |
| 1627 | SSI_LOG_ERR("map_ahash_source() failed\n"); | 1614 | dev_err(dev, "map_ahash_source() failed\n"); |
| 1628 | return -ENOMEM; | 1615 | return -ENOMEM; |
| 1629 | } | 1616 | } |
| 1630 | if (unlikely(ssi_hash_map_result(dev, state, digestsize) != 0)) { | 1617 | if (unlikely(ssi_hash_map_result(dev, state, digestsize) != 0)) { |
| 1631 | SSI_LOG_ERR("map_ahash_digest() failed\n"); | 1618 | dev_err(dev, "map_ahash_digest() failed\n"); |
| 1632 | return -ENOMEM; | 1619 | return -ENOMEM; |
| 1633 | } | 1620 | } |
| 1634 | 1621 | ||
| 1635 | if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, req->src, req->nbytes, 1) != 0)) { | 1622 | if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, req->src, req->nbytes, 1) != 0)) { |
| 1636 | SSI_LOG_ERR("map_ahash_request_final() failed\n"); | 1623 | dev_err(dev, "map_ahash_request_final() failed\n"); |
| 1637 | return -ENOMEM; | 1624 | return -ENOMEM; |
| 1638 | } | 1625 | } |
| 1639 | 1626 | ||
| @@ -1673,7 +1660,7 @@ static int ssi_mac_digest(struct ahash_request *req) · 33 unmodified lines | |||
| 1673 | 1660 | ||
| 1674 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); | 1661 | rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); |
| 1675 | if (unlikely(rc != -EINPROGRESS)) { | 1662 | if (unlikely(rc != -EINPROGRESS)) { |
| 1676 | SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc); | 1663 | dev_err(dev, "send_request() failed (rc=%d)\n", rc); |
| 1677 | ssi_buffer_mgr_unmap_hash_request(dev, state, req->src, true); | 1664 | ssi_buffer_mgr_unmap_hash_request(dev, state, req->src, true); |
| 1678 | ssi_hash_unmap_result(dev, state, digestsize, req->result); | 1665 | ssi_hash_unmap_result(dev, state, digestsize, req->result); |
| 1679 | ssi_hash_unmap_request(dev, state, ctx); | 1666 | ssi_hash_unmap_request(dev, state, ctx); |
| @@ -1727,8 +1714,9 @@ static int ssi_ahash_init(struct ahash_request *req) · 47 unmodified lines | |||
| 1727 | struct ahash_req_ctx *state = ahash_request_ctx(req); | 1714 | struct ahash_req_ctx *state = ahash_request_ctx(req); |
| 1728 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); | 1715 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); |
| 1729 | struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); | 1716 | struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); |
| 1717 | struct device *dev = drvdata_to_dev(ctx->drvdata); | ||
| 1730 | 1718 | ||
| 1731 | SSI_LOG_DEBUG("===== init (%d) ====\n", req->nbytes); | 1719 | dev_dbg(dev, "===== init (%d) ====\n", req->nbytes); |
| 1732 | 1720 | ||
| 1733 | return ssi_hash_init(state, ctx); | 1721 | return ssi_hash_init(state, ctx); |
| 1734 | } | 1722 | } |
| @@ -1737,7 +1725,7 @@ static int ssi_ahash_export(struct ahash_request *req, void *out) · 2 unmodified lines | |||
| 1737 | { | 1725 | { |
| 1738 | struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); | 1726 | struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); |
| 1739 | struct ssi_hash_ctx *ctx = crypto_ahash_ctx(ahash); | 1727 | struct ssi_hash_ctx *ctx = crypto_ahash_ctx(ahash); |
| 1740 | struct device *dev = &ctx->drvdata->plat_dev->dev; | 1728 | struct device *dev = drvdata_to_dev(ctx->drvdata); |
| 1741 | struct ahash_req_ctx *state = ahash_request_ctx(req); | 1729 | struct ahash_req_ctx *state = ahash_request_ctx(req); |
| 1742 | u8 *curr_buff = state->buff_index ? state->buff1 : state->buff0; | 1730 | u8 *curr_buff = state->buff_index ? state->buff1 : state->buff0; |
| 1743 | u32 curr_buff_cnt = state->buff_index ? state->buff1_cnt : | 1731 | u32 curr_buff_cnt = state->buff_index ? state->buff1_cnt : |
| @@ -1778,7 +1766,7 @@ static int ssi_ahash_import(struct ahash_request *req, const void *in) · 34 unmodified lines | |||
| 1778 | { | 1766 | { |
| 1779 | struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); | 1767 | struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); |
| 1780 | struct ssi_hash_ctx *ctx = crypto_ahash_ctx(ahash); | 1768 | struct ssi_hash_ctx *ctx = crypto_ahash_ctx(ahash); |
| 1781 | struct device *dev = &ctx->drvdata->plat_dev->dev; | 1769 | struct device *dev = drvdata_to_dev(ctx->drvdata); |
| 1782 | struct ahash_req_ctx *state = ahash_request_ctx(req); | 1770 | struct ahash_req_ctx *state = ahash_request_ctx(req); |
| 1783 | u32 tmp; | 1771 | u32 tmp; |
| 1784 | int rc; | 1772 | int rc; |
| @@ -2054,17 +2042,17 @@ static struct ssi_hash_template driver_hash[] = { · 269 unmodified lines | |||
| 2054 | }; | 2042 | }; |
| 2055 | 2043 | ||
| 2056 | static struct ssi_hash_alg * | 2044 | static struct ssi_hash_alg * |
| 2057 | ssi_hash_create_alg(struct ssi_hash_template *template, bool keyed) | 2045 | ssi_hash_create_alg(struct ssi_hash_template *template, struct device *dev, |
| 2046 | bool keyed) | ||
| 2058 | { | 2047 | { |
| 2059 | struct ssi_hash_alg *t_crypto_alg; | 2048 | struct ssi_hash_alg *t_crypto_alg; |
| 2060 | struct crypto_alg *alg; | 2049 | struct crypto_alg *alg; |
| 2061 | struct ahash_alg *halg; | 2050 | struct ahash_alg *halg; |
| 2062 | 2051 | ||
| 2063 | t_crypto_alg = kzalloc(sizeof(*t_crypto_alg), GFP_KERNEL); | 2052 | t_crypto_alg = kzalloc(sizeof(*t_crypto_alg), GFP_KERNEL); |
| 2064 | if (!t_crypto_alg) { | 2053 | if (!t_crypto_alg) |
| 2065 | SSI_LOG_ERR("failed to allocate t_crypto_alg\n"); | ||
| 2066 | return ERR_PTR(-ENOMEM); | 2054 | return ERR_PTR(-ENOMEM); |
| 2067 | } | 2055 | |
| 2068 | 2056 | ||
| 2069 | t_crypto_alg->ahash_alg = template->template_ahash; | 2057 | t_crypto_alg->ahash_alg = template->template_ahash; |
| 2070 | halg = &t_crypto_alg->ahash_alg; | 2058 | halg = &t_crypto_alg->ahash_alg; |
| @@ -2107,6 +2095,7 @@ int ssi_hash_init_sram_digest_consts(struct ssi_drvdata *drvdata) · 36 unmodified lines | |||
| 2107 | ssi_sram_addr_t sram_buff_ofs = hash_handle->digest_len_sram_addr; | 2095 | ssi_sram_addr_t sram_buff_ofs = hash_handle->digest_len_sram_addr; |
| 2108 | unsigned int larval_seq_len = 0; | 2096 | unsigned int larval_seq_len = 0; |
| 2109 | struct cc_hw_desc larval_seq[CC_DIGEST_SIZE_MAX / sizeof(u32)]; | 2097 | struct cc_hw_desc larval_seq[CC_DIGEST_SIZE_MAX / sizeof(u32)]; |
| 2098 | struct device *dev = drvdata_to_dev(drvdata); | ||
| 2110 | int rc = 0; | 2099 | int rc = 0; |
| 2111 | #if (DX_DEV_SHA_MAX > 256) | 2100 | #if (DX_DEV_SHA_MAX > 256) |
| 2112 | int i; | 2101 | int i; |
| @@ -2191,7 +2180,7 @@ int ssi_hash_init_sram_digest_consts(struct ssi_drvdata *drvdata) · 78 unmodified lines | |||
| 2191 | } | 2180 | } |
| 2192 | rc = send_request_init(drvdata, larval_seq, larval_seq_len); | 2181 | rc = send_request_init(drvdata, larval_seq, larval_seq_len); |
| 2193 | if (unlikely(rc != 0)) { | 2182 | if (unlikely(rc != 0)) { |
| 2194 | SSI_LOG_ERR("send_request() failed (rc = %d)\n", rc); | 2183 | dev_err(dev, "send_request() failed (rc = %d)\n", rc); |
| 2195 | goto init_digest_const_err; | 2184 | goto init_digest_const_err; |
| 2196 | } | 2185 | } |
| 2197 | larval_seq_len = 0; | 2186 | larval_seq_len = 0; |
| @@ -2209,7 +2198,7 @@ int ssi_hash_init_sram_digest_consts(struct ssi_drvdata *drvdata) · 11 unmodified lines | |||
| 2209 | } | 2198 | } |
| 2210 | rc = send_request_init(drvdata, larval_seq, larval_seq_len); | 2199 | rc = send_request_init(drvdata, larval_seq, larval_seq_len); |
| 2211 | if (unlikely(rc != 0)) { | 2200 | if (unlikely(rc != 0)) { |
| 2212 | SSI_LOG_ERR("send_request() failed (rc = %d)\n", rc); | 2201 | dev_err(dev, "send_request() failed (rc = %d)\n", rc); |
| 2213 | goto init_digest_const_err; | 2202 | goto init_digest_const_err; |
| 2214 | } | 2203 | } |
| 2215 | #endif | 2204 | #endif |
| @@ -2223,17 +2212,15 @@ int ssi_hash_alloc(struct ssi_drvdata *drvdata) · 7 unmodified lines | |||
| 2223 | struct ssi_hash_handle *hash_handle; | 2212 | struct ssi_hash_handle *hash_handle; |
| 2224 | ssi_sram_addr_t sram_buff; | 2213 | ssi_sram_addr_t sram_buff; |
| 2225 | u32 sram_size_to_alloc; | 2214 | u32 sram_size_to_alloc; |
| 2215 | struct device *dev = drvdata_to_dev(drvdata); | ||
| 2226 | int rc = 0; | 2216 | int rc = 0; |
| 2227 | int alg; | 2217 | int alg; |
| 2228 | 2218 | ||
| 2229 | hash_handle = kzalloc(sizeof(*hash_handle), GFP_KERNEL); | 2219 | hash_handle = kzalloc(sizeof(*hash_handle), GFP_KERNEL); |
| 2230 | if (!hash_handle) { | 2220 | if (!hash_handle) |
| 2231 | SSI_LOG_ERR("kzalloc failed to allocate %zu B\n", | 2221 | return -ENOMEM; |
| 2232 | sizeof(*hash_handle)); | ||
| 2233 | rc = -ENOMEM; | ||
| 2234 | goto fail; | ||
| 2235 | } | ||
| 2236 | 2222 | ||
| 2223 | INIT_LIST_HEAD(&hash_handle->hash_list); | ||
| 2237 | drvdata->hash_handle = hash_handle; | 2224 | drvdata->hash_handle = hash_handle; |
| 2238 | 2225 | ||
| 2239 | sram_size_to_alloc = sizeof(digest_len_init) + | 2226 | sram_size_to_alloc = sizeof(digest_len_init) + |
| @@ -2249,7 +2236,7 @@ int ssi_hash_alloc(struct ssi_drvdata *drvdata) · 9 unmodified lines | |||
| 2249 | 2236 | ||
| 2250 | sram_buff = ssi_sram_mgr_alloc(drvdata, sram_size_to_alloc); | 2237 | sram_buff = ssi_sram_mgr_alloc(drvdata, sram_size_to_alloc); |
| 2251 | if (sram_buff == NULL_SRAM_ADDR) { | 2238 | if (sram_buff == NULL_SRAM_ADDR) { |
| 2252 | SSI_LOG_ERR("SRAM pool exhausted\n"); | 2239 | dev_err(dev, "SRAM pool exhausted\n"); |
| 2253 | rc = -ENOMEM; | 2240 | rc = -ENOMEM; |
| 2254 | goto fail; | 2241 | goto fail; |
| 2255 | } | 2242 | } |
| @@ -2260,31 +2247,29 @@ int ssi_hash_alloc(struct ssi_drvdata *drvdata) · 4 unmodified lines | |||
| 2260 | /*must be set before the alg registration as it is being used there*/ | 2247 | /*must be set before the alg registration as it is being used there*/ |
| 2261 | rc = ssi_hash_init_sram_digest_consts(drvdata); | 2248 | rc = ssi_hash_init_sram_digest_consts(drvdata); |
| 2262 | if (unlikely(rc != 0)) { | 2249 | if (unlikely(rc != 0)) { |
| 2263 | SSI_LOG_ERR("Init digest CONST failed (rc=%d)\n", rc); | 2250 | dev_err(dev, "Init digest CONST failed (rc=%d)\n", rc); |
| 2264 | goto fail; | 2251 | goto fail; |
| 2265 | } | 2252 | } |
| 2266 | 2253 | ||
| 2267 | INIT_LIST_HEAD(&hash_handle->hash_list); | ||
| 2268 | |||
| 2269 | /* ahash registration */ | 2254 | /* ahash registration */ |
| 2270 | for (alg = 0; alg < ARRAY_SIZE(driver_hash); alg++) { | 2255 | for (alg = 0; alg < ARRAY_SIZE(driver_hash); alg++) { |
| 2271 | struct ssi_hash_alg *t_alg; | 2256 | struct ssi_hash_alg *t_alg; |
| 2272 | int hw_mode = driver_hash[alg].hw_mode; | 2257 | int hw_mode = driver_hash[alg].hw_mode; |
| 2273 | 2258 | ||
| 2274 | /* register hmac version */ | 2259 | /* register hmac version */ |
| 2275 | t_alg = ssi_hash_create_alg(&driver_hash[alg], true); | 2260 | t_alg = ssi_hash_create_alg(&driver_hash[alg], dev, true); |
| 2276 | if (IS_ERR(t_alg)) { | 2261 | if (IS_ERR(t_alg)) { |
| 2277 | rc = PTR_ERR(t_alg); | 2262 | rc = PTR_ERR(t_alg); |
| 2278 | SSI_LOG_ERR("%s alg allocation failed\n", | 2263 | dev_err(dev, "%s alg allocation failed\n", |
| 2279 | driver_hash[alg].driver_name); | 2264 | driver_hash[alg].driver_name); |
| 2280 | goto fail; | 2265 | goto fail; |
| 2281 | } | 2266 | } |
| 2282 | t_alg->drvdata = drvdata; | 2267 | t_alg->drvdata = drvdata; |
| 2283 | 2268 | ||
| 2284 | rc = crypto_register_ahash(&t_alg->ahash_alg); | 2269 | rc = crypto_register_ahash(&t_alg->ahash_alg); |
| 2285 | if (unlikely(rc)) { | 2270 | if (unlikely(rc)) { |
| 2286 | SSI_LOG_ERR("%s alg registration failed\n", | 2271 | dev_err(dev, "%s alg registration failed\n", |
| 2287 | driver_hash[alg].driver_name); | 2272 | driver_hash[alg].driver_name); |
| 2288 | kfree(t_alg); | 2273 | kfree(t_alg); |
| 2289 | goto fail; | 2274 | goto fail; |
| 2290 | } else { | 2275 | } else { |
| @@ -2297,19 +2282,19 @@ int ssi_hash_alloc(struct ssi_drvdata *drvdata) · 6 unmodified lines | |||
| 2297 | continue; | 2282 | continue; |
| 2298 | 2283 | ||
| 2299 | /* register hash version */ | 2284 | /* register hash version */ |
| 2300 | t_alg = ssi_hash_create_alg(&driver_hash[alg], false); | 2285 | t_alg = ssi_hash_create_alg(&driver_hash[alg], dev, false); |
| 2301 | if (IS_ERR(t_alg)) { | 2286 | if (IS_ERR(t_alg)) { |
| 2302 | rc = PTR_ERR(t_alg); | 2287 | rc = PTR_ERR(t_alg); |
| 2303 | SSI_LOG_ERR("%s alg allocation failed\n", | 2288 | dev_err(dev, "%s alg allocation failed\n", |
| 2304 | driver_hash[alg].driver_name); | 2289 | driver_hash[alg].driver_name); |
| 2305 | goto fail; | 2290 | goto fail; |
| 2306 | } | 2291 | } |
| 2307 | t_alg->drvdata = drvdata; | 2292 | t_alg->drvdata = drvdata; |
| 2308 | 2293 | ||
| 2309 | rc = crypto_register_ahash(&t_alg->ahash_alg); | 2294 | rc = crypto_register_ahash(&t_alg->ahash_alg); |
| 2310 | if (unlikely(rc)) { | 2295 | if (unlikely(rc)) { |
| 2311 | SSI_LOG_ERR("%s alg registration failed\n", | 2296 | dev_err(dev, "%s alg registration failed\n", |
| 2312 | driver_hash[alg].driver_name); | 2297 | driver_hash[alg].driver_name); |
| 2313 | kfree(t_alg); | 2298 | kfree(t_alg); |
| 2314 | goto fail; | 2299 | goto fail; |
| 2315 | } else { | 2300 | } else { |
| @@ -2443,6 +2428,7 @@ static void ssi_hash_create_data_desc(struct ahash_req_ctx *areq_ctx, · 127 unmodified lines | |||
| 2443 | unsigned int *seq_size) | 2428 | unsigned int *seq_size) |
| 2444 | { | 2429 | { |
| 2445 | unsigned int idx = *seq_size; | 2430 | unsigned int idx = *seq_size; |
| 2431 | struct device *dev = drvdata_to_dev(ctx->drvdata); | ||
| 2446 | 2432 | ||
| 2447 | if (likely(areq_ctx->data_dma_buf_type == SSI_DMA_BUF_DLLI)) { | 2433 | if (likely(areq_ctx->data_dma_buf_type == SSI_DMA_BUF_DLLI)) { |
| 2448 | hw_desc_init(&desc[idx]); | 2434 | hw_desc_init(&desc[idx]); |
| @@ -2453,7 +2439,7 @@ static void ssi_hash_create_data_desc(struct ahash_req_ctx *areq_ctx, · 4 unmodified lines | |||
| 2453 | idx++; | 2439 | idx++; |
| 2454 | } else { | 2440 | } else { |
| 2455 | if (areq_ctx->data_dma_buf_type == SSI_DMA_BUF_NULL) { | 2441 | if (areq_ctx->data_dma_buf_type == SSI_DMA_BUF_NULL) { |
| 2456 | SSI_LOG_DEBUG(" NULL mode\n"); | 2442 | dev_dbg(dev, " NULL mode\n"); |
| 2457 | /* nothing to build */ | 2443 | /* nothing to build */ |
| 2458 | return; | 2444 | return; |
| 2459 | } | 2445 | } |
| @@ -2493,6 +2479,7 @@ ssi_sram_addr_t ssi_ahash_get_larval_digest_sram_addr(void *drvdata, u32 mode) · 33 unmodified lines | |||
| 2493 | { | 2479 | { |
| 2494 | struct ssi_drvdata *_drvdata = (struct ssi_drvdata *)drvdata; | 2480 | struct ssi_drvdata *_drvdata = (struct ssi_drvdata *)drvdata; |
| 2495 | struct ssi_hash_handle *hash_handle = _drvdata->hash_handle; | 2481 | struct ssi_hash_handle *hash_handle = _drvdata->hash_handle; |
| 2482 | struct device *dev = drvdata_to_dev(_drvdata); | ||
| 2496 | 2483 | ||
| 2497 | switch (mode) { | 2484 | switch (mode) { |
| 2498 | case DRV_HASH_NULL: | 2485 | case DRV_HASH_NULL: |
| @@ -2527,7 +2514,7 @@ ssi_sram_addr_t ssi_ahash_get_larval_digest_sram_addr(void *drvdata, u32 mode) · 28 unmodified lines | |||
| 2527 | sizeof(sha384_init)); | 2514 | sizeof(sha384_init)); |
| 2528 | #endif | 2515 | #endif |
| 2529 | default: | 2516 | default: |
| 2530 | SSI_LOG_ERR("Invalid hash mode (%d)\n", mode); | 2517 | dev_err(dev, "Invalid hash mode (%d)\n", mode); |
| 2531 | } | 2518 | } |
| 2532 | 2519 | ||
| 2533 | /*This is valid wrong value to avoid kernel crash*/ | 2520 | /*This is valid wrong value to avoid kernel crash*/ |
| @@ -193,12 +193,9 @@ int ssi_ivgen_init(struct ssi_drvdata *drvdata) · 192 unmodified lines | |||
| 193 | /* Allocate "this" context */ | 193 | /* Allocate "this" context */ |
| 194 | drvdata->ivgen_handle = kzalloc(sizeof(*drvdata->ivgen_handle), | 194 | drvdata->ivgen_handle = kzalloc(sizeof(*drvdata->ivgen_handle), |
| 195 | GFP_KERNEL); | 195 | GFP_KERNEL); |
| 196 | if (!drvdata->ivgen_handle) { | 196 | if (!drvdata->ivgen_handle) |
| 197 | SSI_LOG_ERR("Not enough memory to allocate IVGEN context " | 197 | return -ENOMEM; |
| 198 | "(%zu B)\n", sizeof(*drvdata->ivgen_handle)); | 198 | |
| 199 | rc = -ENOMEM; | ||
| 200 | goto out; | ||
| 201 | } | ||
| 202 | ivgen_ctx = drvdata->ivgen_handle; | 199 | ivgen_ctx = drvdata->ivgen_handle; |
| 203 | 200 | ||
| 204 | /* Allocate pool's header for intial enc. key/IV */ | 201 | /* Allocate pool's header for intial enc. key/IV */ |
| @@ -206,15 +203,15 @@ int ssi_ivgen_init(struct ssi_drvdata *drvdata) · 1 unmodified line | |||
| 206 | &ivgen_ctx->pool_meta_dma, | 203 | &ivgen_ctx->pool_meta_dma, |
| 207 | GFP_KERNEL); | 204 | GFP_KERNEL); |
| 208 | if (!ivgen_ctx->pool_meta) { | 205 | if (!ivgen_ctx->pool_meta) { |
| 209 | SSI_LOG_ERR("Not enough memory to allocate DMA of pool_meta " | 206 | dev_err(device, "Not enough memory to allocate DMA of pool_meta (%u B)\n", |
| 210 | "(%u B)\n", SSI_IVPOOL_META_SIZE); | 207 | SSI_IVPOOL_META_SIZE); |
| 211 | rc = -ENOMEM; | 208 | rc = -ENOMEM; |
| 212 | goto out; | 209 | goto out; |
| 213 | } | 210 | } |
| 214 | /* Allocate IV pool in SRAM */ | 211 | /* Allocate IV pool in SRAM */ |
| 215 | ivgen_ctx->pool = ssi_sram_mgr_alloc(drvdata, SSI_IVPOOL_SIZE); | 212 | ivgen_ctx->pool = ssi_sram_mgr_alloc(drvdata, SSI_IVPOOL_SIZE); |
| 216 | if (ivgen_ctx->pool == NULL_SRAM_ADDR) { | 213 | if (ivgen_ctx->pool == NULL_SRAM_ADDR) { |
| 217 | SSI_LOG_ERR("SRAM pool exhausted\n"); | 214 | dev_err(device, "SRAM pool exhausted\n"); |
| 218 | rc = -ENOMEM; | 215 | rc = -ENOMEM; |
| 219 | goto out; | 216 | goto out; |
| 220 | } | 217 | } |
| @@ -248,6 +245,7 @@ int ssi_ivgen_getiv( · 27 unmodified lines | |||
| 248 | { | 245 | { |
| 249 | struct ssi_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle; | 246 | struct ssi_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle; |
| 250 | unsigned int idx = *iv_seq_len; | 247 | unsigned int idx = *iv_seq_len; |
| 248 | struct device *dev = drvdata_to_dev(drvdata); | ||
| 251 | unsigned int t; | 249 | unsigned int t; |
| 252 | 250 | ||
| 253 | if ((iv_out_size != CC_AES_IV_SIZE) && | 251 | if ((iv_out_size != CC_AES_IV_SIZE) && |
| @@ -291,7 +289,7 @@ int ssi_ivgen_getiv( · 37 unmodified lines | |||
| 291 | ivgen_ctx->next_iv_ofs += iv_out_size; | 289 | ivgen_ctx->next_iv_ofs += iv_out_size; |
| 292 | 290 | ||
| 293 | if ((SSI_IVPOOL_SIZE - ivgen_ctx->next_iv_ofs) < CC_AES_IV_SIZE) { | 291 | if ((SSI_IVPOOL_SIZE - ivgen_ctx->next_iv_ofs) < CC_AES_IV_SIZE) { |
| 294 | SSI_LOG_DEBUG("Pool exhausted, regenerating iv-pool\n"); | 292 | dev_dbg(dev, "Pool exhausted, regenerating iv-pool\n"); |
| 295 | /* pool is drained -regenerate it! */ | 293 | /* pool is drained -regenerate it! */ |
| 296 | return ssi_ivgen_generate_pool(ivgen_ctx, iv_seq, iv_seq_len); | 294 | return ssi_ivgen_generate_pool(ivgen_ctx, iv_seq, iv_seq_len); |
| 297 | } | 295 | } |
| @@ -40,11 +40,12 @@ int ssi_power_mgr_runtime_suspend(struct device *dev) · 39 unmodified lines | |||
| 40 | (struct ssi_drvdata *)dev_get_drvdata(dev); | 40 | (struct ssi_drvdata *)dev_get_drvdata(dev); |
| 41 | int rc; | 41 | int rc; |
| 42 | 42 | ||
| 43 | SSI_LOG_DEBUG("set HOST_POWER_DOWN_EN\n"); | 43 | dev_dbg(dev, "set HOST_POWER_DOWN_EN\n"); |
| 44 | WRITE_REGISTER(drvdata->cc_base + CC_REG_OFFSET(HOST_RGF, HOST_POWER_DOWN_EN), POWER_DOWN_ENABLE); | 44 | cc_iowrite(drvdata, CC_REG(HOST_POWER_DOWN_EN), POWER_DOWN_ENABLE); |
| 45 | rc = ssi_request_mgr_runtime_suspend_queue(drvdata); | 45 | rc = ssi_request_mgr_runtime_suspend_queue(drvdata); |
| 46 | if (rc != 0) { | 46 | if (rc != 0) { |
| 47 | SSI_LOG_ERR("ssi_request_mgr_runtime_suspend_queue (%x)\n", rc); | 47 | dev_err(dev, "ssi_request_mgr_runtime_suspend_queue (%x)\n", |
| 48 | rc); | ||
| 48 | return rc; | 49 | return rc; |
| 49 | } | 50 | } |
| 50 | fini_cc_regs(drvdata); | 51 | fini_cc_regs(drvdata); |
| @@ -58,24 +59,24 @@ int ssi_power_mgr_runtime_resume(struct device *dev) · 7 unmodified lines | |||
| 58 | struct ssi_drvdata *drvdata = | 59 | struct ssi_drvdata *drvdata = |
| 59 | (struct ssi_drvdata *)dev_get_drvdata(dev); | 60 | (struct ssi_drvdata *)dev_get_drvdata(dev); |
| 60 | 61 | ||
| 61 | SSI_LOG_DEBUG("unset HOST_POWER_DOWN_EN\n"); | 62 | dev_dbg(dev, "unset HOST_POWER_DOWN_EN\n"); |
| 62 | WRITE_REGISTER(drvdata->cc_base + CC_REG_OFFSET(HOST_RGF, HOST_POWER_DOWN_EN), POWER_DOWN_DISABLE); | 63 | cc_iowrite(drvdata, CC_REG(HOST_POWER_DOWN_EN), POWER_DOWN_DISABLE); |
| 63 | 64 | ||
| 64 | rc = cc_clk_on(drvdata); | 65 | rc = cc_clk_on(drvdata); |
| 65 | if (rc) { | 66 | if (rc) { |
| 66 | SSI_LOG_ERR("failed getting clock back on. We're toast.\n"); | 67 | dev_err(dev, "failed getting clock back on. We're toast.\n"); |
| 67 | return rc; | 68 | return rc; |
| 68 | } | 69 | } |
| 69 | 70 | ||
| 70 | rc = init_cc_regs(drvdata, false); | 71 | rc = init_cc_regs(drvdata, false); |
| 71 | if (rc != 0) { | 72 | if (rc != 0) { |
| 72 | SSI_LOG_ERR("init_cc_regs (%x)\n", rc); | 73 | dev_err(dev, "init_cc_regs (%x)\n", rc); |
| 73 | return rc; | 74 | return rc; |
| 74 | } | 75 | } |
| 75 | 76 | ||
| 76 | rc = ssi_request_mgr_runtime_resume_queue(drvdata); | 77 | rc = ssi_request_mgr_runtime_resume_queue(drvdata); |
| 77 | if (rc != 0) { | 78 | if (rc != 0) { |
| 78 | SSI_LOG_ERR("ssi_request_mgr_runtime_resume_queue (%x)\n", rc); | 79 | dev_err(dev, "ssi_request_mgr_runtime_resume_queue (%x)\n", rc); |
| 79 | return rc; | 80 | return rc; |
| 80 | } | 81 | } |
| 81 | 82 | ||
| @@ -109,7 +110,8 @@ int ssi_power_mgr_runtime_put_suspend(struct device *dev) · 27 unmodified lines | |||
| 109 | rc = pm_runtime_put_autosuspend(dev); | 110 | rc = pm_runtime_put_autosuspend(dev); |
| 110 | } else { | 111 | } else { |
| 111 | /* Something wrong happens*/ | 112 | /* Something wrong happens*/ |
| 112 | BUG(); | 113 | dev_err(dev, "request to suspend already suspended queue"); |
| 114 | rc = -EBUSY; | ||
| 113 | } | 115 | } |
| 114 | return rc; | 116 | return rc; |
| 115 | } | 117 | } |
| @@ -120,16 +122,17 @@ int ssi_power_mgr_init(struct ssi_drvdata *drvdata) · 4 unmodified lines | |||
| 120 | { | 122 | { |
| 121 | int rc = 0; | 123 | int rc = 0; |
| 122 | #if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) | 124 | #if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) |
| 123 | struct platform_device *plat_dev = drvdata->plat_dev; | 125 | struct device *dev = drvdata_to_dev(drvdata); |
| 126 | |||
| 124 | /* must be before the enabling to avoid resdundent suspending */ | 127 | /* must be before the enabling to avoid resdundent suspending */ |
| 125 | pm_runtime_set_autosuspend_delay(&plat_dev->dev, SSI_SUSPEND_TIMEOUT); | 128 | pm_runtime_set_autosuspend_delay(dev, SSI_SUSPEND_TIMEOUT); |
| 126 | pm_runtime_use_autosuspend(&plat_dev->dev); | 129 | pm_runtime_use_autosuspend(dev); |
| 127 | /* activate the PM module */ | 130 | /* activate the PM module */ |
| 128 | rc = pm_runtime_set_active(&plat_dev->dev); | 131 | rc = pm_runtime_set_active(dev); |
| 129 | if (rc != 0) | 132 | if (rc != 0) |
| 130 | return rc; | 133 | return rc; |
| 131 | /* enable the PM module*/ | 134 | /* enable the PM module*/ |
| 132 | pm_runtime_enable(&plat_dev->dev); | 135 | pm_runtime_enable(dev); |
| 133 | #endif | 136 | #endif |
| 134 | return rc; | 137 | return rc; |
| 135 | } | 138 | } |
| @@ -137,8 +140,6 @@ int ssi_power_mgr_init(struct ssi_drvdata *drvdata) · 1 unmodified line | |||
| 137 | void ssi_power_mgr_fini(struct ssi_drvdata *drvdata) | 140 | void ssi_power_mgr_fini(struct ssi_drvdata *drvdata) |
| 138 | { | 141 | { |
| 139 | #if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) | 142 | #if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) |
| 140 | struct platform_device *plat_dev = drvdata->plat_dev; | 143 | pm_runtime_disable(drvdata_to_dev(drvdata)); |
| 141 | |||
| 142 | pm_runtime_disable(&plat_dev->dev); | ||
| 143 | #endif | 144 | #endif |
| 144 | } | 145 | } |
| @@ -49,7 +49,6 @@ struct ssi_request_mgr_handle { · 48 unmodified lines | |||
| 49 | dma_addr_t dummy_comp_buff_dma; | 49 | dma_addr_t dummy_comp_buff_dma; |
| 50 | struct cc_hw_desc monitor_desc; | 50 | struct cc_hw_desc monitor_desc; |
| 51 | 51 | ||
| 52 | volatile unsigned long monitor_lock; | ||
| 53 | #ifdef COMP_IN_WQ | 52 | #ifdef COMP_IN_WQ |
| 54 | struct workqueue_struct *workq; | 53 | struct workqueue_struct *workq; |
| 55 | struct delayed_work compwork; | 54 | struct delayed_work compwork; |
| @@ -69,19 +68,19 @@ static void comp_work_handler(struct work_struct *work); · 13 unmodified lines | |||
| 69 | void request_mgr_fini(struct ssi_drvdata *drvdata) | 68 | void request_mgr_fini(struct ssi_drvdata *drvdata) |
| 70 | { | 69 | { |
| 71 | struct ssi_request_mgr_handle *req_mgr_h = drvdata->request_mgr_handle; | 70 | struct ssi_request_mgr_handle *req_mgr_h = drvdata->request_mgr_handle; |
| 71 | struct device *dev = drvdata_to_dev(drvdata); | ||
| 72 | 72 | ||
| 73 | if (!req_mgr_h) | 73 | if (!req_mgr_h) |
| 74 | return; /* Not allocated */ | 74 | return; /* Not allocated */ |
| 75 | 75 | ||
| 76 | if (req_mgr_h->dummy_comp_buff_dma != 0) { | 76 | if (req_mgr_h->dummy_comp_buff_dma != 0) { |
| 77 | dma_free_coherent(&drvdata->plat_dev->dev, | 77 | dma_free_coherent(dev, sizeof(u32), req_mgr_h->dummy_comp_buff, |
| 78 | sizeof(u32), req_mgr_h->dummy_comp_buff, | ||
| 79 | req_mgr_h->dummy_comp_buff_dma); | 78 | req_mgr_h->dummy_comp_buff_dma); |
| 80 | } | 79 | } |
| 81 | 80 | ||
| 82 | SSI_LOG_DEBUG("max_used_hw_slots=%d\n", (req_mgr_h->hw_queue_size - | 81 | dev_dbg(dev, "max_used_hw_slots=%d\n", (req_mgr_h->hw_queue_size - |
| 83 | req_mgr_h->min_free_hw_slots)); | 82 | req_mgr_h->min_free_hw_slots)); |
| 84 | SSI_LOG_DEBUG("max_used_sw_slots=%d\n", req_mgr_h->max_used_sw_slots); | 83 | dev_dbg(dev, "max_used_sw_slots=%d\n", req_mgr_h->max_used_sw_slots); |
| 85 | 84 | ||
| 86 | #ifdef COMP_IN_WQ | 85 | #ifdef COMP_IN_WQ |
| 87 | flush_workqueue(req_mgr_h->workq); | 86 | flush_workqueue(req_mgr_h->workq); |
| @@ -98,6 +97,7 @@ void request_mgr_fini(struct ssi_drvdata *drvdata) · 10 unmodified lines | |||
| 98 | int request_mgr_init(struct ssi_drvdata *drvdata) | 97 | int request_mgr_init(struct ssi_drvdata *drvdata) |
| 99 | { | 98 | { |
| 100 | struct ssi_request_mgr_handle *req_mgr_h; | 99 | struct ssi_request_mgr_handle *req_mgr_h; |
| 100 | struct device *dev = drvdata_to_dev(drvdata); | ||
| 101 | int rc = 0; | 101 | int rc = 0; |
| 102 | 102 | ||
| 103 | req_mgr_h = kzalloc(sizeof(*req_mgr_h), GFP_KERNEL); | 103 | req_mgr_h = kzalloc(sizeof(*req_mgr_h), GFP_KERNEL); |
| @@ -110,24 +110,24 @@ int request_mgr_init(struct ssi_drvdata *drvdata) · 6 unmodified lines | |||
| 110 | 110 | ||
| 111 | spin_lock_init(&req_mgr_h->hw_lock); | 111 | spin_lock_init(&req_mgr_h->hw_lock); |
| 112 | #ifdef COMP_IN_WQ | 112 | #ifdef COMP_IN_WQ |
| 113 | SSI_LOG_DEBUG("Initializing completion workqueue\n"); | 113 | dev_dbg(dev, "Initializing completion workqueue\n"); |
| 114 | req_mgr_h->workq = create_singlethread_workqueue("arm_cc7x_wq"); | 114 | req_mgr_h->workq = create_singlethread_workqueue("arm_cc7x_wq"); |
| 115 | if (unlikely(!req_mgr_h->workq)) { | 115 | if (unlikely(!req_mgr_h->workq)) { |
| 116 | SSI_LOG_ERR("Failed creating work queue\n"); | 116 | dev_err(dev, "Failed creating work queue\n"); |
| 117 | rc = -ENOMEM; | 117 | rc = -ENOMEM; |
| 118 | goto req_mgr_init_err; | 118 | goto req_mgr_init_err; |
| 119 | } | 119 | } |
| 120 | INIT_DELAYED_WORK(&req_mgr_h->compwork, comp_work_handler); | 120 | INIT_DELAYED_WORK(&req_mgr_h->compwork, comp_work_handler); |
| 121 | #else | 121 | #else |
| 122 | SSI_LOG_DEBUG("Initializing completion tasklet\n"); | 122 | dev_dbg(dev, "Initializing completion tasklet\n"); |
| 123 | tasklet_init(&req_mgr_h->comptask, comp_handler, (unsigned long)drvdata); | 123 | tasklet_init(&req_mgr_h->comptask, comp_handler, (unsigned long)drvdata); |
| 124 | #endif | 124 | #endif |
| 125 | req_mgr_h->hw_queue_size = READ_REGISTER(drvdata->cc_base + | 125 | req_mgr_h->hw_queue_size = cc_ioread(drvdata, |
| 126 | CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_SRAM_SIZE)); | 126 | CC_REG(DSCRPTR_QUEUE_SRAM_SIZE)); |
| 127 | SSI_LOG_DEBUG("hw_queue_size=0x%08X\n", req_mgr_h->hw_queue_size); | 127 | dev_dbg(dev, "hw_queue_size=0x%08X\n", req_mgr_h->hw_queue_size); |
| 128 | if (req_mgr_h->hw_queue_size < MIN_HW_QUEUE_SIZE) { | 128 | if (req_mgr_h->hw_queue_size < MIN_HW_QUEUE_SIZE) { |
| 129 | SSI_LOG_ERR("Invalid HW queue size = %u (Min. required is %u)\n", | 129 | dev_err(dev, "Invalid HW queue size = %u (Min. required is %u)\n", |
| 130 | req_mgr_h->hw_queue_size, MIN_HW_QUEUE_SIZE); | 130 | req_mgr_h->hw_queue_size, MIN_HW_QUEUE_SIZE); |
| 131 | rc = -ENOMEM; | 131 | rc = -ENOMEM; |
| 132 | goto req_mgr_init_err; | 132 | goto req_mgr_init_err; |
| 133 | } | 133 | } |
| @@ -135,13 +135,12 @@ int request_mgr_init(struct ssi_drvdata *drvdata) · 1 unmodified line | |||
| 135 | req_mgr_h->max_used_sw_slots = 0; | 135 | req_mgr_h->max_used_sw_slots = 0; |
| 136 | 136 | ||
| 137 | /* Allocate DMA word for "dummy" completion descriptor use */ | 137 | /* Allocate DMA word for "dummy" completion descriptor use */ |
| 138 | req_mgr_h->dummy_comp_buff = dma_alloc_coherent(&drvdata->plat_dev->dev, | 138 | req_mgr_h->dummy_comp_buff = dma_alloc_coherent(dev, sizeof(u32), |
| 139 | sizeof(u32), | ||
| 140 | &req_mgr_h->dummy_comp_buff_dma, | 139 | &req_mgr_h->dummy_comp_buff_dma, |
| 141 | GFP_KERNEL); | 140 | GFP_KERNEL); |
| 142 | if (!req_mgr_h->dummy_comp_buff) { | 141 | if (!req_mgr_h->dummy_comp_buff) { |
| 143 | SSI_LOG_ERR("Not enough memory to allocate DMA (%zu) dropped " | 142 | dev_err(dev, "Not enough memory to allocate DMA (%zu) dropped buffer\n", |
| 144 | "buffer\n", sizeof(u32)); | 143 | sizeof(u32)); |
| 145 | rc = -ENOMEM; | 144 | rc = -ENOMEM; |
| 146 | goto req_mgr_init_err; | 145 | goto req_mgr_init_err; |
| 147 | } | 146 | } |
| @@ -168,17 +167,17 @@ static inline void enqueue_seq( · 20 unmodified lines | |||
| 168 | int i; | 167 | int i; |
| 169 | 168 | ||
| 170 | for (i = 0; i < seq_len; i++) { | 169 | for (i = 0; i < seq_len; i++) { |
| 171 | writel_relaxed(seq[i].word[0], (volatile void __iomem *)(cc_base + CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0))); | 170 | writel_relaxed(seq[i].word[0], (volatile void __iomem *)(cc_base + CC_REG(DSCRPTR_QUEUE_WORD0))); |
| 172 | writel_relaxed(seq[i].word[1], (volatile void __iomem *)(cc_base + CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0))); | 171 | writel_relaxed(seq[i].word[1], (volatile void __iomem *)(cc_base + CC_REG(DSCRPTR_QUEUE_WORD0))); |
| 173 | writel_relaxed(seq[i].word[2], (volatile void __iomem *)(cc_base + CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0))); | 172 | writel_relaxed(seq[i].word[2], (volatile void __iomem *)(cc_base + CC_REG(DSCRPTR_QUEUE_WORD0))); |
| 174 | writel_relaxed(seq[i].word[3], (volatile void __iomem *)(cc_base + CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0))); | 173 | writel_relaxed(seq[i].word[3], (volatile void __iomem *)(cc_base + CC_REG(DSCRPTR_QUEUE_WORD0))); |
| 175 | writel_relaxed(seq[i].word[4], (volatile void __iomem *)(cc_base + CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0))); | 174 | writel_relaxed(seq[i].word[4], (volatile void __iomem *)(cc_base + CC_REG(DSCRPTR_QUEUE_WORD0))); |
| 176 | wmb(); | 175 | wmb(); |
| 177 | writel_relaxed(seq[i].word[5], (volatile void __iomem *)(cc_base + CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0))); | 176 | writel_relaxed(seq[i].word[5], (volatile void __iomem *)(cc_base + CC_REG(DSCRPTR_QUEUE_WORD0))); |
| 178 | #ifdef DX_DUMP_DESCS | 177 | #ifdef DX_DUMP_DESCS |
| 179 | SSI_LOG_DEBUG("desc[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", i, | 178 | dev_dbg(dev, "desc[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", |
| 180 | seq[i].word[0], seq[i].word[1], seq[i].word[2], | 179 | i, seq[i].word[0], seq[i].word[1], seq[i].word[2], |
| 181 | seq[i].word[3], seq[i].word[4], seq[i].word[5]); | 180 | seq[i].word[3], seq[i].word[4], seq[i].word[5]); |
| 182 | #endif | 181 | #endif |
| 183 | } | 182 | } |
| 184 | } | 183 | } |
| @@ -198,11 +197,12 @@ static void request_mgr_complete(struct device *dev, void *dx_compl_h, void __io · 13 unmodified lines | |||
| 198 | } | 197 | } |
| 199 | 198 | ||
| 200 | static inline int request_mgr_queues_status_check( | 199 | static inline int request_mgr_queues_status_check( |
| 200 | struct ssi_drvdata *drvdata, | ||
| 201 | struct ssi_request_mgr_handle *req_mgr_h, | 201 | struct ssi_request_mgr_handle *req_mgr_h, |
| 202 | void __iomem *cc_base, | ||
| 203 | unsigned int total_seq_len) | 202 | unsigned int total_seq_len) |
| 204 | { | 203 | { |
| 205 | unsigned long poll_queue; | 204 | unsigned long poll_queue; |
| 205 | struct device *dev = drvdata_to_dev(drvdata); | ||
| 206 | 206 | ||
| 207 | /* SW queue is checked only once as it will not | 207 | /* SW queue is checked only once as it will not |
| 208 | * be chaned during the poll becasue the spinlock_bh | 208 | * be chaned during the poll becasue the spinlock_bh |
| @@ -211,8 +211,8 @@ static inline int request_mgr_queues_status_check( · 2 unmodified lines | |||
| 211 | if (unlikely(((req_mgr_h->req_queue_head + 1) & | 211 | if (unlikely(((req_mgr_h->req_queue_head + 1) & |
| 212 | (MAX_REQUEST_QUEUE_SIZE - 1)) == | 212 | (MAX_REQUEST_QUEUE_SIZE - 1)) == |
| 213 | req_mgr_h->req_queue_tail)) { | 213 | req_mgr_h->req_queue_tail)) { |
| 214 | SSI_LOG_ERR("SW FIFO is full. req_queue_head=%d sw_fifo_len=%d\n", | 214 | dev_err(dev, "SW FIFO is full. req_queue_head=%d sw_fifo_len=%d\n", |
| 215 | req_mgr_h->req_queue_head, MAX_REQUEST_QUEUE_SIZE); | 215 | req_mgr_h->req_queue_head, MAX_REQUEST_QUEUE_SIZE); |
| 216 | return -EBUSY; | 216 | return -EBUSY; |
| 217 | } | 217 | } |
| 218 | 218 | ||
| @@ -222,8 +222,7 @@ static inline int request_mgr_queues_status_check( · 3 unmodified lines | |||
| 222 | /* Wait for space in HW queue. Poll constant num of iterations. */ | 222 | /* Wait for space in HW queue. Poll constant num of iterations. */ |
| 223 | for (poll_queue = 0; poll_queue < SSI_MAX_POLL_ITER ; poll_queue++) { | 223 | for (poll_queue = 0; poll_queue < SSI_MAX_POLL_ITER ; poll_queue++) { |
| 224 | req_mgr_h->q_free_slots = | 224 | req_mgr_h->q_free_slots = |
| 225 | CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, | 225 | cc_ioread(drvdata, CC_REG(DSCRPTR_QUEUE_CONTENT)); |
| 226 | DSCRPTR_QUEUE_CONTENT)); | ||
| 227 | if (unlikely(req_mgr_h->q_free_slots < | 226 | if (unlikely(req_mgr_h->q_free_slots < |
| 228 | req_mgr_h->min_free_hw_slots)) { | 227 | req_mgr_h->min_free_hw_slots)) { |
| 229 | req_mgr_h->min_free_hw_slots = req_mgr_h->q_free_slots; | 228 | req_mgr_h->min_free_hw_slots = req_mgr_h->q_free_slots; |
| @@ -234,16 +233,13 @@ static inline int request_mgr_queues_status_check( · 4 unmodified lines | |||
| 234 | return 0; | 233 | return 0; |
| 235 | } | 234 | } |
| 236 | 235 | ||
| 237 | SSI_LOG_DEBUG("HW FIFO is full. q_free_slots=%d total_seq_len=%d\n", | 236 | dev_dbg(dev, "HW FIFO is full. q_free_slots=%d total_seq_len=%d\n", |
| 238 | req_mgr_h->q_free_slots, total_seq_len); | 237 | req_mgr_h->q_free_slots, total_seq_len); |
| 239 | } | 238 | } |
| 240 | /* No room in the HW queue try again later */ | 239 | /* No room in the HW queue try again later */ |
| 241 | SSI_LOG_DEBUG("HW FIFO full, timeout. req_queue_head=%d " | 240 | dev_dbg(dev, "HW FIFO full, timeout. req_queue_head=%d sw_fifo_len=%d q_free_slots=%d total_seq_len=%d\n", |
| 242 | "sw_fifo_len=%d q_free_slots=%d total_seq_len=%d\n", | 241 | req_mgr_h->req_queue_head, MAX_REQUEST_QUEUE_SIZE, |
| 243 | req_mgr_h->req_queue_head, | 242 | req_mgr_h->q_free_slots, total_seq_len); |
| 244 | MAX_REQUEST_QUEUE_SIZE, | ||
| 245 | req_mgr_h->q_free_slots, | ||
| 246 | total_seq_len); | ||
| 247 | return -EAGAIN; | 243 | return -EAGAIN; |
| 248 | } | 244 | } |
| 249 | 245 | ||
| @@ -270,16 +266,17 @@ int send_request( · 20 unmodified lines | |||
| 270 | unsigned int iv_seq_len = 0; | 266 | unsigned int iv_seq_len = 0; |
| 271 | unsigned int total_seq_len = len; /*initial sequence length*/ | 267 | unsigned int total_seq_len = len; /*initial sequence length*/ |
| 272 | struct cc_hw_desc iv_seq[SSI_IVPOOL_SEQ_LEN]; | 268 | struct cc_hw_desc iv_seq[SSI_IVPOOL_SEQ_LEN]; |
| 269 | struct device *dev = drvdata_to_dev(drvdata); | ||
| 273 | int rc; | 270 | int rc; |
| 274 | unsigned int max_required_seq_len = (total_seq_len + | 271 | unsigned int max_required_seq_len = (total_seq_len + |
| 275 | ((ssi_req->ivgen_dma_addr_len == 0) ? 0 : | 272 | ((ssi_req->ivgen_dma_addr_len == 0) ? 0 : |
| 276 | SSI_IVPOOL_SEQ_LEN) + | 273 | SSI_IVPOOL_SEQ_LEN) + |
| 277 | ((is_dout == 0) ? 1 : 0)); | 274 | (!is_dout ? 1 : 0)); |
| 278 | 275 | ||
| 279 | #if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) | 276 | #if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) |
| 280 | rc = ssi_power_mgr_runtime_get(&drvdata->plat_dev->dev); | 277 | rc = ssi_power_mgr_runtime_get(dev); |
| 281 | if (rc != 0) { | 278 | if (rc != 0) { |
| 282 | SSI_LOG_ERR("ssi_power_mgr_runtime_get returned %x\n", rc); | 279 | dev_err(dev, "ssi_power_mgr_runtime_get returned %x\n", rc); |
| 283 | return rc; | 280 | return rc; |
| 284 | } | 281 | } |
| 285 | #endif | 282 | #endif |
| @@ -291,7 +288,7 @@ int send_request( · 5 unmodified lines | |||
| 291 | * in case iv gen add the max size and in case of no dout add 1 | 288 | * in case iv gen add the max size and in case of no dout add 1 |
| 292 | * for the internal completion descriptor | 289 | * for the internal completion descriptor |
| 293 | */ | 290 | */ |
| 294 | rc = request_mgr_queues_status_check(req_mgr_h, cc_base, | 291 | rc = request_mgr_queues_status_check(drvdata, req_mgr_h, |
| 295 | max_required_seq_len); | 292 | max_required_seq_len); |
| 296 | if (likely(rc == 0)) | 293 | if (likely(rc == 0)) |
| 297 | /* There is enough place in the queue */ | 294 | /* There is enough place in the queue */ |
| @@ -304,7 +301,7 @@ int send_request( · 6 unmodified lines | |||
| 304 | * (SW queue is full) | 301 | * (SW queue is full) |
| 305 | */ | 302 | */ |
| 306 | #if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) | 303 | #if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) |
| 307 | ssi_power_mgr_runtime_put_suspend(&drvdata->plat_dev->dev); | 304 | ssi_power_mgr_runtime_put_suspend(dev); |
| 308 | #endif | 305 | #endif |
| 309 | return rc; | 306 | return rc; |
| 310 | } | 307 | } |
| @@ -324,12 +321,12 @@ int send_request( · 13 unmodified lines | |||
| 324 | } | 321 | } |
| 325 | 322 | ||
| 326 | if (ssi_req->ivgen_dma_addr_len > 0) { | 323 | if (ssi_req->ivgen_dma_addr_len > 0) { |
| 327 | SSI_LOG_DEBUG("Acquire IV from pool into %d DMA addresses %pad, %pad, %pad, IV-size=%u\n", | 324 | dev_dbg(dev, "Acquire IV from pool into %d DMA addresses %pad, %pad, %pad, IV-size=%u\n", |
| 328 | ssi_req->ivgen_dma_addr_len, | 325 | ssi_req->ivgen_dma_addr_len, |
| 329 | ssi_req->ivgen_dma_addr[0], | 326 | &ssi_req->ivgen_dma_addr[0], |
| 330 | ssi_req->ivgen_dma_addr[1], | 327 | &ssi_req->ivgen_dma_addr[1], |
| 331 | ssi_req->ivgen_dma_addr[2], | 328 | &ssi_req->ivgen_dma_addr[2], |
| 332 | ssi_req->ivgen_size); | 329 | ssi_req->ivgen_size); |
| 333 | 330 | ||
| 334 | /* Acquire IV from pool */ | 331 | /* Acquire IV from pool */ |
| 335 | rc = ssi_ivgen_getiv(drvdata, ssi_req->ivgen_dma_addr, | 332 | rc = ssi_ivgen_getiv(drvdata, ssi_req->ivgen_dma_addr, |
| @@ -337,10 +334,10 @@ int send_request( · 1 unmodified line | |||
| 337 | ssi_req->ivgen_size, iv_seq, &iv_seq_len); | 334 | ssi_req->ivgen_size, iv_seq, &iv_seq_len); |
| 338 | 335 | ||
| 339 | if (unlikely(rc != 0)) { | 336 | if (unlikely(rc != 0)) { |
| 340 | SSI_LOG_ERR("Failed to generate IV (rc=%d)\n", rc); | 337 | dev_err(dev, "Failed to generate IV (rc=%d)\n", rc); |
| 341 | spin_unlock_bh(&req_mgr_h->hw_lock); | 338 | spin_unlock_bh(&req_mgr_h->hw_lock); |
| 342 | #if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) | 339 | #if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) |
| 343 | ssi_power_mgr_runtime_put_suspend(&drvdata->plat_dev->dev); | 340 | ssi_power_mgr_runtime_put_suspend(dev); |
| 344 | #endif | 341 | #endif |
| 345 | return rc; | 342 | return rc; |
| 346 | } | 343 | } |
| @@ -357,7 +354,7 @@ int send_request( · 10 unmodified lines | |||
| 357 | req_mgr_h->req_queue_head = (req_mgr_h->req_queue_head + 1) & (MAX_REQUEST_QUEUE_SIZE - 1); | 354 | req_mgr_h->req_queue_head = (req_mgr_h->req_queue_head + 1) & (MAX_REQUEST_QUEUE_SIZE - 1); |
| 358 | /* TODO: Use circ_buf.h ? */ | 355 | /* TODO: Use circ_buf.h ? */ |
| 359 | 356 | ||
| 360 | SSI_LOG_DEBUG("Enqueue request head=%u\n", req_mgr_h->req_queue_head); | 357 | dev_dbg(dev, "Enqueue request head=%u\n", req_mgr_h->req_queue_head); |
| 361 | 358 | ||
| 362 | #ifdef FLUSH_CACHE_ALL | 359 | #ifdef FLUSH_CACHE_ALL |
| 363 | flush_cache_all(); | 360 | flush_cache_all(); |
| @@ -369,11 +366,16 @@ int send_request( · 5 unmodified lines | |||
| 369 | enqueue_seq(cc_base, &req_mgr_h->compl_desc, (is_dout ? 0 : 1)); | 366 | enqueue_seq(cc_base, &req_mgr_h->compl_desc, (is_dout ? 0 : 1)); |
| 370 | 367 | ||
| 371 | if (unlikely(req_mgr_h->q_free_slots < total_seq_len)) { | 368 | if (unlikely(req_mgr_h->q_free_slots < total_seq_len)) { |
| 372 | /*This means that there was a problem with the resume*/ | 369 | /* This situation should never occur. Maybe indicating problem |
| 373 | BUG(); | 370 | * with resuming power. Set the free slot count to 0 and hope |
| 371 | * for the best. | ||
| 372 | */ | ||
| 373 | dev_err(dev, "HW free slot count mismatch."); | ||
| 374 | req_mgr_h->q_free_slots = 0; | ||
| 375 | } else { | ||
| 376 | /* Update the free slots in HW queue */ | ||
| 377 | req_mgr_h->q_free_slots -= total_seq_len; | ||
| 374 | } | 378 | } |
| 375 | /* Update the free slots in HW queue */ | ||
| 376 | req_mgr_h->q_free_slots -= total_seq_len; | ||
| 377 | 379 | ||
| 378 | spin_unlock_bh(&req_mgr_h->hw_lock); | 380 | spin_unlock_bh(&req_mgr_h->hw_lock); |
| 379 | 381 | ||
| @@ -383,10 +385,9 @@ int send_request( · 3 unmodified lines | |||
| 383 | */ | 385 | */ |
| 384 | wait_for_completion(&ssi_req->seq_compl); | 386 | wait_for_completion(&ssi_req->seq_compl); |
| 385 | return 0; | 387 | return 0; |
| 386 | } else { | ||
| 387 | /* Operation still in process */ | ||
| 388 | return -EINPROGRESS; | ||
| 389 | } | 388 | } |
| 389 | /* Operation still in process */ | ||
| 390 | return -EINPROGRESS; | ||
| 390 | } | 391 | } |
| 391 | 392 | ||
| 392 | /*! | 393 | /*! |
| @@ -409,7 +410,8 @@ int send_request_init( · 16 unmodified lines | |||
| 409 | int rc = 0; | 410 | int rc = 0; |
| 410 | 411 | ||
| 411 | /* Wait for space in HW and SW FIFO. Poll for as much as FIFO_TIMEOUT. */ | 412 | /* Wait for space in HW and SW FIFO. Poll for as much as FIFO_TIMEOUT. */ |
| 412 | rc = request_mgr_queues_status_check(req_mgr_h, cc_base, total_seq_len); | 413 | rc = request_mgr_queues_status_check(drvdata, req_mgr_h, |
| 414 | total_seq_len); | ||
| 413 | if (unlikely(rc != 0)) | 415 | if (unlikely(rc != 0)) |
| 414 | return rc; | 416 | return rc; |
| 415 | 417 | ||
| @@ -418,8 +420,8 @@ int send_request_init( · 2 unmodified lines | |||
| 418 | enqueue_seq(cc_base, desc, len); | 420 | enqueue_seq(cc_base, desc, len); |
| 419 | 421 | ||
| 420 | /* Update the free slots in HW queue */ | 422 | /* Update the free slots in HW queue */ |
| 421 | req_mgr_h->q_free_slots = CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, | 423 | req_mgr_h->q_free_slots = |
| 422 | DSCRPTR_QUEUE_CONTENT)); | 424 | cc_ioread(drvdata, CC_REG(DSCRPTR_QUEUE_CONTENT)); |
| 423 | 425 | ||
| 424 | return 0; | 426 | return 0; |
| 425 | } | 427 | } |
| @@ -448,7 +450,7 @@ static void comp_work_handler(struct work_struct *work) · 22 unmodified lines | |||
| 448 | static void proc_completions(struct ssi_drvdata *drvdata) | 450 | static void proc_completions(struct ssi_drvdata *drvdata) |
| 449 | { | 451 | { |
| 450 | struct ssi_crypto_req *ssi_req; | 452 | struct ssi_crypto_req *ssi_req; |
| 451 | struct platform_device *plat_dev = drvdata->plat_dev; | 453 | struct device *dev = drvdata_to_dev(drvdata); |
| 452 | struct ssi_request_mgr_handle *request_mgr_handle = | 454 | struct ssi_request_mgr_handle *request_mgr_handle = |
| 453 | drvdata->request_mgr_handle; | 455 | drvdata->request_mgr_handle; |
| 454 | #if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) | 456 | #if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) |
| @@ -460,8 +462,13 @@ static void proc_completions(struct ssi_drvdata *drvdata) · 5 unmodified lines | |||
| 460 | 462 | ||
| 461 | /* Dequeue request */ | 463 | /* Dequeue request */ |
| 462 | if (unlikely(request_mgr_handle->req_queue_head == request_mgr_handle->req_queue_tail)) { | 464 | if (unlikely(request_mgr_handle->req_queue_head == request_mgr_handle->req_queue_tail)) { |
| 463 | SSI_LOG_ERR("Request queue is empty req_queue_head==req_queue_tail==%u\n", request_mgr_handle->req_queue_head); | 465 | /* We are supposed to handle a completion but our |
| 464 | BUG(); | 466 | * queue is empty. This is not normal. Return and |
| 467 | * hope for the best. | ||
| 468 | */ | ||
| 469 | dev_err(dev, "Request queue is empty head == tail %u\n", | ||
| 470 | request_mgr_handle->req_queue_head); | ||
| 471 | break; | ||
| 465 | } | 472 | } |
| 466 | 473 | ||
| 467 | ssi_req = &request_mgr_handle->req_queue[request_mgr_handle->req_queue_tail]; | 474 | ssi_req = &request_mgr_handle->req_queue[request_mgr_handle->req_queue_tail]; |
| @@ -476,39 +483,40 @@ static void proc_completions(struct ssi_drvdata *drvdata) · 8 unmodified lines | |||
| 476 | u32 axi_err; | 483 | u32 axi_err; |
| 477 | int i; | 484 | int i; |
| 478 | 485 | ||
| 479 | SSI_LOG_INFO("Delay\n"); | 486 | dev_info(dev, "Delay\n"); |
| 480 | for (i = 0; i < 1000000; i++) | 487 | for (i = 0; i < 1000000; i++) |
| 481 | axi_err = READ_REGISTER(drvdata->cc_base + CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_ERR)); | 488 | axi_err = cc_ioread(drvdata, |
| 489 | CC_REG(AXIM_MON_ERR)); | ||
| 482 | } | 490 | } |
| 483 | #endif /* COMPLETION_DELAY */ | 491 | #endif /* COMPLETION_DELAY */ |
| 484 | 492 | ||
| 485 | if (likely(ssi_req->user_cb)) | 493 | if (likely(ssi_req->user_cb)) |
| 486 | ssi_req->user_cb(&plat_dev->dev, ssi_req->user_arg, drvdata->cc_base); | 494 | ssi_req->user_cb(dev, ssi_req->user_arg, |
| 495 | drvdata->cc_base); | ||
| 487 | request_mgr_handle->req_queue_tail = (request_mgr_handle->req_queue_tail + 1) & (MAX_REQUEST_QUEUE_SIZE - 1); | 496 | request_mgr_handle->req_queue_tail = (request_mgr_handle->req_queue_tail + 1) & (MAX_REQUEST_QUEUE_SIZE - 1); |
| 488 | SSI_LOG_DEBUG("Dequeue request tail=%u\n", request_mgr_handle->req_queue_tail); | 497 | dev_dbg(dev, "Dequeue request tail=%u\n", |
| 489 | SSI_LOG_DEBUG("Request completed. axi_completed=%d\n", request_mgr_handle->axi_completed); | 498 | request_mgr_handle->req_queue_tail); |
| 499 | dev_dbg(dev, "Request completed. axi_completed=%d\n", | ||
| 500 | request_mgr_handle->axi_completed); | ||
| 490 | #if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) | 501 | #if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) |
| 491 | rc = ssi_power_mgr_runtime_put_suspend(&plat_dev->dev); | 502 | rc = ssi_power_mgr_runtime_put_suspend(dev); |
| 492 | if (rc != 0) | 503 | if (rc != 0) |
| 493 | SSI_LOG_ERR("Failed to set runtime suspension %d\n", rc); | 504 | dev_err(dev, "Failed to set runtime suspension %d\n", |
| 505 | rc); | ||
| 494 | #endif | 506 | #endif |
| 495 | } | 507 | } |
| 496 | } | 508 | } |
| 497 | 509 | ||
| 498 | static inline u32 cc_axi_comp_count(void __iomem *cc_base) | 510 | static inline u32 cc_axi_comp_count(struct ssi_drvdata *drvdata) |
| 499 | { | 511 | { |
| 500 | /* The CC_HAL_READ_REGISTER macro implictly requires and uses | ||
| 501 | * a base MMIO register address variable named cc_base. | ||
| 502 | */ | ||
| 503 | return FIELD_GET(AXIM_MON_COMP_VALUE, | 512 | return FIELD_GET(AXIM_MON_COMP_VALUE, |
| 504 | CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET)); | 513 | cc_ioread(drvdata, CC_REG(AXIM_MON_COMP))); |
| 505 | } | 514 | } |
| 506 | 515 | ||
| 507 | /* Deferred service handler, run as interrupt-fired tasklet */ | 516 | /* Deferred service handler, run as interrupt-fired tasklet */ |
| 508 | static void comp_handler(unsigned long devarg) | 517 | static void comp_handler(unsigned long devarg) |
| 509 | { | 518 | { |
| 510 | struct ssi_drvdata *drvdata = (struct ssi_drvdata *)devarg; | 519 | struct ssi_drvdata *drvdata = (struct ssi_drvdata *)devarg; |
| 511 | void __iomem *cc_base = drvdata->cc_base; | ||
| 512 | struct ssi_request_mgr_handle *request_mgr_handle = | 520 | struct ssi_request_mgr_handle *request_mgr_handle = |
| 513 | drvdata->request_mgr_handle; | 521 | drvdata->request_mgr_handle; |
| 514 | 522 | ||
| @@ -517,12 +525,16 @@ static void comp_handler(unsigned long devarg) · 2 unmodified lines | |||
| 517 | irq = (drvdata->irq & SSI_COMP_IRQ_MASK); | 525 | irq = (drvdata->irq & SSI_COMP_IRQ_MASK); |
| 518 | 526 | ||
| 519 | if (irq & SSI_COMP_IRQ_MASK) { | 527 | if (irq & SSI_COMP_IRQ_MASK) { |
| 520 | /* To avoid the interrupt from firing as we unmask it, we clear it now */ | 528 | /* To avoid the interrupt from firing as we unmask it, |
| 521 | CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_ICR), SSI_COMP_IRQ_MASK); | 529 | * we clear it now |
| 530 | */ | ||
| 531 | cc_iowrite(drvdata, CC_REG(HOST_ICR), SSI_COMP_IRQ_MASK); | ||
| 522 | 532 | ||
| 523 | /* Avoid race with above clear: Test completion counter once more */ | 533 | /* Avoid race with above clear: Test completion counter |
| 534 | * once more | ||
| 535 | */ | ||
| 524 | request_mgr_handle->axi_completed += | 536 | request_mgr_handle->axi_completed += |
| 525 | cc_axi_comp_count(cc_base); | 537 | cc_axi_comp_count(drvdata); |
| 526 | 538 | ||
| 527 | while (request_mgr_handle->axi_completed) { | 539 | while (request_mgr_handle->axi_completed) { |
| 528 | do { | 540 | do { |
| @@ -531,20 +543,21 @@ static void comp_handler(unsigned long devarg) · 2 unmodified lines | |||
| 531 | * request_mgr_handle->axi_completed is 0. | 543 | * request_mgr_handle->axi_completed is 0. |
| 532 | */ | 544 | */ |
| 533 | request_mgr_handle->axi_completed = | 545 | request_mgr_handle->axi_completed = |
| 534 | cc_axi_comp_count(cc_base); | 546 | cc_axi_comp_count(drvdata); |
| 535 | } while (request_mgr_handle->axi_completed > 0); | 547 | } while (request_mgr_handle->axi_completed > 0); |
| 536 | 548 | ||
| 537 | /* To avoid the interrupt from firing as we unmask it, we clear it now */ | 549 | cc_iowrite(drvdata, CC_REG(HOST_ICR), |
| 538 | CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_ICR), SSI_COMP_IRQ_MASK); | 550 | SSI_COMP_IRQ_MASK); |
| 539 | 551 | ||
| 540 | /* Avoid race with above clear: Test completion counter once more */ | ||
| 541 | request_mgr_handle->axi_completed += | 552 | request_mgr_handle->axi_completed += |
| 542 | cc_axi_comp_count(cc_base); | 553 | cc_axi_comp_count(drvdata); |
| 543 | } | 554 | } |
| 544 | } | 555 | } |
| 545 | /* after verifing that there is nothing to do, Unmask AXI completion interrupt */ | 556 | /* after verifing that there is nothing to do, |
| 546 | CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR), | 557 | * unmask AXI completion interrupt |
| 547 | CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR)) & ~irq); | 558 | */ |
| 559 | cc_iowrite(drvdata, CC_REG(HOST_IMR), | ||
| 560 | cc_ioread(drvdata, CC_REG(HOST_IMR)) & ~irq); | ||
| 548 | } | 561 | } |
| 549 | 562 | ||
| 550 | /* | 563 | /* |
| @@ -50,28 +50,14 @@ void ssi_sram_mgr_fini(struct ssi_drvdata *drvdata) · 49 unmodified lines | |||
| 50 | */ | 50 | */ |
| 51 | int ssi_sram_mgr_init(struct ssi_drvdata *drvdata) | 51 | int ssi_sram_mgr_init(struct ssi_drvdata *drvdata) |
| 52 | { | 52 | { |
| 53 | struct ssi_sram_mgr_ctx *smgr_ctx; | ||
| 54 | int rc; | ||
| 55 | |||
| 56 | /* Allocate "this" context */ | 53 | /* Allocate "this" context */ |
| 57 | drvdata->sram_mgr_handle = kzalloc( | 54 | drvdata->sram_mgr_handle = kzalloc(sizeof(struct ssi_sram_mgr_ctx), |
| 58 | sizeof(struct ssi_sram_mgr_ctx), GFP_KERNEL); | 55 | GFP_KERNEL); |
| 59 | if (!drvdata->sram_mgr_handle) { | ||
| 60 | SSI_LOG_ERR("Not enough memory to allocate SRAM_MGR ctx (%zu)\n", | ||
| 61 | sizeof(struct ssi_sram_mgr_ctx)); | ||
| 62 | rc = -ENOMEM; | ||
| 63 | goto out; | ||
| 64 | } | ||
| 65 | smgr_ctx = drvdata->sram_mgr_handle; | ||
| 66 | 56 | ||
| 67 | /* Pool starts at start of SRAM */ | 57 | if (!drvdata->sram_mgr_handle) |
| 68 | smgr_ctx->sram_free_offset = 0; | 58 | return -ENOMEM; |
| 69 | 59 | ||
| 70 | return 0; | 60 | return 0; |
| 71 | |||
| 72 | out: | ||
| 73 | ssi_sram_mgr_fini(drvdata); | ||
| 74 | return rc; | ||
| 75 | } | 61 | } |
| 76 | 62 | ||
| 77 | /*! | 63 | /*! |
| @@ -86,22 +72,23 @@ out: · 8 unmodified lines | |||
| 86 | ssi_sram_addr_t ssi_sram_mgr_alloc(struct ssi_drvdata *drvdata, u32 size) | 72 | ssi_sram_addr_t ssi_sram_mgr_alloc(struct ssi_drvdata *drvdata, u32 size) |
| 87 | { | 73 | { |
| 88 | struct ssi_sram_mgr_ctx *smgr_ctx = drvdata->sram_mgr_handle; | 74 | struct ssi_sram_mgr_ctx *smgr_ctx = drvdata->sram_mgr_handle; |
| 75 | struct device *dev = drvdata_to_dev(drvdata); | ||
| 89 | ssi_sram_addr_t p; | 76 | ssi_sram_addr_t p; |
| 90 | 77 | ||
| 91 | if (unlikely((size & 0x3) != 0)) { | 78 | if (unlikely((size & 0x3) != 0)) { |
| 92 | SSI_LOG_ERR("Requested buffer size (%u) is not multiple of 4", | 79 | dev_err(dev, "Requested buffer size (%u) is not multiple of 4", |
| 93 | size); | 80 | size); |
| 94 | return NULL_SRAM_ADDR; | 81 | return NULL_SRAM_ADDR; |
| 95 | } | 82 | } |
| 96 | if (unlikely(size > (SSI_CC_SRAM_SIZE - smgr_ctx->sram_free_offset))) { | 83 | if (unlikely(size > (SSI_CC_SRAM_SIZE - smgr_ctx->sram_free_offset))) { |
| 97 | SSI_LOG_ERR("Not enough space to allocate %u B (at offset %llu)\n", | 84 | dev_err(dev, "Not enough space to allocate %u B (at offset %llu)\n", |
| 98 | size, smgr_ctx->sram_free_offset); | 85 | size, smgr_ctx->sram_free_offset); |
| 99 | return NULL_SRAM_ADDR; | 86 | return NULL_SRAM_ADDR; |
| 100 | } | 87 | } |
| 101 | 88 | ||
| 102 | p = smgr_ctx->sram_free_offset; | 89 | p = smgr_ctx->sram_free_offset; |
| 103 | smgr_ctx->sram_free_offset += size; | 90 | smgr_ctx->sram_free_offset += size; |
| 104 | SSI_LOG_DEBUG("Allocated %u B @ %u\n", size, (unsigned int)p); | 91 | dev_dbg(dev, "Allocated %u B @ %u\n", size, (unsigned int)p); |
| 105 | return p; | 92 | return p; |
| 106 | } | 93 | } |
| 107 | 94 | ||
| @@ -24,277 +24,22 @@ · 23 unmodified lines | |||
| 24 | 24 | ||
| 25 | static struct ssi_drvdata *sys_get_drvdata(void); | 25 | static struct ssi_drvdata *sys_get_drvdata(void); |
| 26 | 26 | ||
| 27 | #ifdef CC_CYCLE_COUNT | ||
| 28 | |||
| 29 | #include <asm/timex.h> | ||
| 30 | |||
| 31 | struct stat_item { | ||
| 32 | unsigned int min; | ||
| 33 | unsigned int max; | ||
| 34 | cycles_t sum; | ||
| 35 | unsigned int count; | ||
| 36 | }; | ||
| 37 | |||
| 38 | struct stat_name { | ||
| 39 | const char *op_type_name; | ||
| 40 | const char *stat_phase_name[MAX_STAT_PHASES]; | ||
| 41 | }; | ||
| 42 | |||
| 43 | static struct stat_name stat_name_db[MAX_STAT_OP_TYPES] = { | ||
| 44 | { | ||
| 45 | /* STAT_OP_TYPE_NULL */ | ||
| 46 | .op_type_name = "NULL", | ||
| 47 | .stat_phase_name = {NULL}, | ||
| 48 | }, | ||
| 49 | { | ||
| 50 | .op_type_name = "Encode", | ||
| 51 | .stat_phase_name[STAT_PHASE_0] = "Init and sanity checks", | ||
| 52 | .stat_phase_name[STAT_PHASE_1] = "Map buffers", | ||
| 53 | .stat_phase_name[STAT_PHASE_2] = "Create sequence", | ||
| 54 | .stat_phase_name[STAT_PHASE_3] = "Send Request", | ||
| 55 | .stat_phase_name[STAT_PHASE_4] = "HW-Q push", | ||
| 56 | .stat_phase_name[STAT_PHASE_5] = "Sequence completion", | ||
| 57 | .stat_phase_name[STAT_PHASE_6] = "HW cycles", | ||
| 58 | }, | ||
| 59 | { .op_type_name = "Decode", | ||
| 60 | .stat_phase_name[STAT_PHASE_0] = "Init and sanity checks", | ||
| 61 | .stat_phase_name[STAT_PHASE_1] = "Map buffers", | ||
| 62 | .stat_phase_name[STAT_PHASE_2] = "Create sequence", | ||
| 63 | .stat_phase_name[STAT_PHASE_3] = "Send Request", | ||
| 64 | .stat_phase_name[STAT_PHASE_4] = "HW-Q push", | ||
| 65 | .stat_phase_name[STAT_PHASE_5] = "Sequence completion", | ||
| 66 | .stat_phase_name[STAT_PHASE_6] = "HW cycles", | ||
| 67 | }, | ||
| 68 | { .op_type_name = "Setkey", | ||
| 69 | .stat_phase_name[STAT_PHASE_0] = "Init and sanity checks", | ||
| 70 | .stat_phase_name[STAT_PHASE_1] = "Copy key to ctx", | ||
| 71 | .stat_phase_name[STAT_PHASE_2] = "Create sequence", | ||
| 72 | .stat_phase_name[STAT_PHASE_3] = "Send Request", | ||
| 73 | .stat_phase_name[STAT_PHASE_4] = "HW-Q push", | ||
| 74 | .stat_phase_name[STAT_PHASE_5] = "Sequence completion", | ||
| 75 | .stat_phase_name[STAT_PHASE_6] = "HW cycles", | ||
| 76 | }, | ||
| 77 | { | ||
| 78 | .op_type_name = "Generic", | ||
| 79 | .stat_phase_name[STAT_PHASE_0] = "Interrupt", | ||
| 80 | .stat_phase_name[STAT_PHASE_1] = "ISR-to-Tasklet", | ||
| 81 | .stat_phase_name[STAT_PHASE_2] = "Tasklet start-to-end", | ||
| 82 | .stat_phase_name[STAT_PHASE_3] = "Tasklet:user_cb()", | ||
| 83 | .stat_phase_name[STAT_PHASE_4] = "Tasklet:dx_X_complete() - w/o X_complete()", | ||
| 84 | .stat_phase_name[STAT_PHASE_5] = "", | ||
| 85 | .stat_phase_name[STAT_PHASE_6] = "HW cycles", | ||
| 86 | } | ||
| 87 | }; | ||
| 88 | |||
| 89 | /* | ||
| 90 | * Structure used to create a directory | ||
| 91 | * and its attributes in sysfs. | ||
| 92 | */ | ||
| 93 | struct sys_dir { | ||
| 94 | struct kobject *sys_dir_kobj; | ||
| 95 | struct attribute_group sys_dir_attr_group; | ||
| 96 | struct attribute **sys_dir_attr_list; | ||
| 97 | u32 num_of_attrs; | ||
| 98 | struct ssi_drvdata *drvdata; /* Associated driver context */ | ||
| 99 | }; | ||
| 100 | |||
| 101 | /* top level directory structures */ | ||
| 102 | struct sys_dir sys_top_dir; | ||
| 103 | |||
| 104 | static DEFINE_SPINLOCK(stat_lock); | ||
| 105 | |||
| 106 | /* List of DBs */ | ||
| 107 | static struct stat_item stat_host_db[MAX_STAT_OP_TYPES][MAX_STAT_PHASES]; | ||
| 108 | static struct stat_item stat_cc_db[MAX_STAT_OP_TYPES][MAX_STAT_PHASES]; | ||
| 109 | |||
| 110 | static void init_db(struct stat_item item[MAX_STAT_OP_TYPES][MAX_STAT_PHASES]) | ||
| 111 | { | ||
| 112 | unsigned int i, j; | ||
| 113 | |||
| 114 | /* Clear db */ | ||
| 115 | for (i = 0; i < MAX_STAT_OP_TYPES; i++) { | ||
| 116 | for (j = 0; j < MAX_STAT_PHASES; j++) { | ||
| 117 | item[i][j].min = 0xFFFFFFFF; | ||
| 118 | item[i][j].max = 0; | ||
| 119 | item[i][j].sum = 0; | ||
| 120 | item[i][j].count = 0; | ||
| 121 | } | ||
| 122 | } | ||
| 123 | } | ||
| 124 | |||
| 125 | static void update_db(struct stat_item *item, unsigned int result) | ||
| 126 | { | ||
| 127 | item->count++; | ||
| 128 | item->sum += result; | ||
| 129 | if (result < item->min) | ||
| 130 | item->min = result; | ||
| 131 | if (result > item->max) | ||
| 132 | item->max = result; | ||
| 133 | } | ||
| 134 | |||
| 135 | static void display_db(struct stat_item item[MAX_STAT_OP_TYPES][MAX_STAT_PHASES]) | ||
| 136 | { | ||
| 137 | unsigned int i, j; | ||
| 138 | u64 avg; | ||
| 139 | |||
| 140 | for (i = STAT_OP_TYPE_ENCODE; i < MAX_STAT_OP_TYPES; i++) { | ||
| 141 | for (j = 0; j < MAX_STAT_PHASES; j++) { | ||
| 142 | if (item[i][j].count > 0) { | ||
| 143 | avg = (u64)item[i][j].sum; | ||
| 144 | do_div(avg, item[i][j].count); | ||
| 145 | SSI_LOG_ERR("%s, %s: min=%d avg=%d max=%d sum=%lld count=%d\n", | ||
| 146 | stat_name_db[i].op_type_name, | ||
| 147 | stat_name_db[i].stat_phase_name[j], | ||
| 148 | item[i][j].min, (int)avg, | ||
| 149 | item[i][j].max, | ||
| 150 | (long long)item[i][j].sum, | ||
| 151 | item[i][j].count); | ||
| 152 | } | ||
| 153 | } | ||
| 154 | } | ||
| 155 | } | ||
| 156 | |||
| 157 | /************************************** | ||
| 158 | * Attributes show functions section * | ||
| 159 | **************************************/ | ||
| 160 | |||
| 161 | static ssize_t ssi_sys_stats_host_db_clear(struct kobject *kobj, | ||
| 162 | struct kobj_attribute *attr, | ||
| 163 | const char *buf, size_t count) | ||
| 164 | { | ||
| 165 | init_db(stat_host_db); | ||
| 166 | return count; | ||
| 167 | } | ||
| 168 | |||
| 169 | static ssize_t ssi_sys_stats_cc_db_clear(struct kobject *kobj, | ||
| 170 | struct kobj_attribute *attr, | ||
| 171 | const char *buf, size_t count) | ||
| 172 | { | ||
| 173 | init_db(stat_cc_db); | ||
| 174 | return count; | ||
| 175 | } | ||
| 176 | |||
| 177 | static ssize_t ssi_sys_stat_host_db_show(struct kobject *kobj, | ||
| 178 | struct kobj_attribute *attr, char *buf) | ||
| 179 | { | ||
| 180 | int i, j; | ||
| 181 | char line[512]; | ||
| 182 | u32 min_cyc, max_cyc; | ||
| 183 | u64 avg; | ||
| 184 | ssize_t buf_len, tmp_len = 0; | ||
| 185 | |||
| 186 | buf_len = scnprintf(buf, PAGE_SIZE, | ||
| 187 | "phase\t\t\t\t\t\t\tmin[cy]\tavg[cy]\tmax[cy]\t#samples\n"); | ||
| 188 | if (buf_len < 0)/* scnprintf shouldn't return negative value according to its implementation*/ | ||
| 189 | return buf_len; | ||
| 190 | for (i = STAT_OP_TYPE_ENCODE; i < MAX_STAT_OP_TYPES; i++) { | ||
| 191 | for (j = 0; j < MAX_STAT_PHASES - 1; j++) { | ||
| 192 | if (stat_host_db[i][j].count > 0) { | ||
| 193 | avg = (u64)stat_host_db[i][j].sum; | ||
| 194 | do_div(avg, stat_host_db[i][j].count); | ||
| 195 | min_cyc = stat_host_db[i][j].min; | ||
| 196 | max_cyc = stat_host_db[i][j].max; | ||
| 197 | } else { | ||
| 198 | avg = min_cyc = max_cyc = 0; | ||
| 199 | } | ||
| 200 | tmp_len = scnprintf(line, 512, | ||
| 201 | "%s::%s\t\t\t\t\t%6u\t%6u\t%6u\t%7u\n", | ||
| 202 | stat_name_db[i].op_type_name, | ||
| 203 | stat_name_db[i].stat_phase_name[j], | ||
| 204 | min_cyc, (unsigned int)avg, max_cyc, | ||
| 205 | stat_host_db[i][j].count); | ||
| 206 | if (tmp_len < 0)/* scnprintf shouldn't return negative value according to its implementation*/ | ||
| 207 | return buf_len; | ||
| 208 | if (buf_len + tmp_len >= PAGE_SIZE) | ||
| 209 | return buf_len; | ||
| 210 | buf_len += tmp_len; | ||
| 211 | strncat(buf, line, 512); | ||
| 212 | } | ||
| 213 | } | ||
| 214 | return buf_len; | ||
| 215 | } | ||
| 216 | |||
| 217 | static ssize_t ssi_sys_stat_cc_db_show(struct kobject *kobj, | ||
| 218 | struct kobj_attribute *attr, char *buf) | ||
| 219 | { | ||
| 220 | int i; | ||
| 221 | char line[256]; | ||
| 222 | u32 min_cyc, max_cyc; | ||
| 223 | u64 avg; | ||
| 224 | ssize_t buf_len, tmp_len = 0; | ||
| 225 | |||
| 226 | buf_len = scnprintf(buf, PAGE_SIZE, | ||
| 227 | "phase\tmin[cy]\tavg[cy]\tmax[cy]\t#samples\n"); | ||
| 228 | if (buf_len < 0)/* scnprintf shouldn't return negative value according to its implementation*/ | ||
| 229 | return buf_len; | ||
| 230 | for (i = STAT_OP_TYPE_ENCODE; i < MAX_STAT_OP_TYPES; i++) { | ||
| 231 | if (stat_cc_db[i][STAT_PHASE_6].count > 0) { | ||
| 232 | avg = (u64)stat_cc_db[i][STAT_PHASE_6].sum; | ||
| 233 | do_div(avg, stat_cc_db[i][STAT_PHASE_6].count); | ||
| 234 | min_cyc = stat_cc_db[i][STAT_PHASE_6].min; | ||
| 235 | max_cyc = stat_cc_db[i][STAT_PHASE_6].max; | ||
| 236 | } else { | ||
| 237 | avg = min_cyc = max_cyc = 0; | ||
| 238 | } | ||
| 239 | tmp_len = scnprintf(line, 256, "%s\t%6u\t%6u\t%6u\t%7u\n", | ||
| 240 | stat_name_db[i].op_type_name, min_cyc, | ||
| 241 | (unsigned int)avg, max_cyc, | ||
| 242 | stat_cc_db[i][STAT_PHASE_6].count); | ||
| 243 | |||
| 244 | if (tmp_len < 0)/* scnprintf shouldn't return negative value according to its implementation*/ | ||
| 245 | return buf_len; | ||
| 246 | |||
| 247 | if (buf_len + tmp_len >= PAGE_SIZE) | ||
| 248 | return buf_len; | ||
| 249 | buf_len += tmp_len; | ||
| 250 | strncat(buf, line, 256); | ||
| 251 | } | ||
| 252 | return buf_len; | ||
| 253 | } | ||
| 254 | |||
| 255 | void update_host_stat(unsigned int op_type, unsigned int phase, cycles_t result) | ||
| 256 | { | ||
| 257 | unsigned long flags; | ||
| 258 | |||
| 259 | spin_lock_irqsave(&stat_lock, flags); | ||
| 260 | update_db(&stat_host_db[op_type][phase], (unsigned int)result); | ||
| 261 | spin_unlock_irqrestore(&stat_lock, flags); | ||
| 262 | } | ||
| 263 | |||
| 264 | void update_cc_stat( | ||
| 265 | unsigned int op_type, | ||
| 266 | unsigned int phase, | ||
| 267 | unsigned int elapsed_cycles) | ||
| 268 | { | ||
| 269 | update_db(&stat_cc_db[op_type][phase], elapsed_cycles); | ||
| 270 | } | ||
| 271 | |||
| 272 | void display_all_stat_db(void) | ||
| 273 | { | ||
| 274 | SSI_LOG_ERR("\n======= CYCLE COUNT STATS =======\n"); | ||
| 275 | display_db(stat_host_db); | ||
| 276 | SSI_LOG_ERR("\n======= CC HW CYCLE COUNT STATS =======\n"); | ||
| 277 | display_db(stat_cc_db); | ||
| 278 | } | ||
| 279 | #endif /*CC_CYCLE_COUNT*/ | ||
| 280 | |||
| 281 | static ssize_t ssi_sys_regdump_show(struct kobject *kobj, | 27 | static ssize_t ssi_sys_regdump_show(struct kobject *kobj, |
| 282 | struct kobj_attribute *attr, char *buf) | 28 | struct kobj_attribute *attr, char *buf) |
| 283 | { | 29 | { |
| 284 | struct ssi_drvdata *drvdata = sys_get_drvdata(); | 30 | struct ssi_drvdata *drvdata = sys_get_drvdata(); |
| 285 | u32 register_value; | 31 | u32 register_value; |
| 286 | void __iomem *cc_base = drvdata->cc_base; | ||
| 287 | int offset = 0; | 32 | int offset = 0; |
| 288 | 33 | ||
| 289 | register_value = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_SIGNATURE)); | 34 | register_value = cc_ioread(drvdata, CC_REG(HOST_SIGNATURE)); |
| 290 | offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s \t(0x%lX)\t 0x%08X\n", "HOST_SIGNATURE ", DX_HOST_SIGNATURE_REG_OFFSET, register_value); | 35 | offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s \t(0x%lX)\t 0x%08X\n", "HOST_SIGNATURE ", DX_HOST_SIGNATURE_REG_OFFSET, register_value); |
| 291 | register_value = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IRR)); | 36 | register_value = cc_ioread(drvdata, CC_REG(HOST_IRR)); |
| 292 | offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s \t(0x%lX)\t 0x%08X\n", "HOST_IRR ", DX_HOST_IRR_REG_OFFSET, register_value); | 37 | offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s \t(0x%lX)\t 0x%08X\n", "HOST_IRR ", DX_HOST_IRR_REG_OFFSET, register_value); |
| 293 | register_value = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_POWER_DOWN_EN)); | 38 | register_value = cc_ioread(drvdata, CC_REG(HOST_POWER_DOWN_EN)); |
| 294 | offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s \t(0x%lX)\t 0x%08X\n", "HOST_POWER_DOWN_EN ", DX_HOST_POWER_DOWN_EN_REG_OFFSET, register_value); | 39 | offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s \t(0x%lX)\t 0x%08X\n", "HOST_POWER_DOWN_EN ", DX_HOST_POWER_DOWN_EN_REG_OFFSET, register_value); |
| 295 | register_value = CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_ERR)); | 40 | register_value = cc_ioread(drvdata, CC_REG(AXIM_MON_ERR)); |
| 296 | offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s \t(0x%lX)\t 0x%08X\n", "AXIM_MON_ERR ", DX_AXIM_MON_ERR_REG_OFFSET, register_value); | 41 | offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s \t(0x%lX)\t 0x%08X\n", "AXIM_MON_ERR ", DX_AXIM_MON_ERR_REG_OFFSET, register_value); |
| 297 | register_value = CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_CONTENT)); | 42 | register_value = cc_ioread(drvdata, CC_REG(DSCRPTR_QUEUE_CONTENT)); |
| 298 | offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s \t(0x%lX)\t 0x%08X\n", "DSCRPTR_QUEUE_CONTENT", DX_DSCRPTR_QUEUE_CONTENT_REG_OFFSET, register_value); | 43 | offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s \t(0x%lX)\t 0x%08X\n", "DSCRPTR_QUEUE_CONTENT", DX_DSCRPTR_QUEUE_CONTENT_REG_OFFSET, register_value); |
| 299 | return offset; | 44 | return offset; |
| 300 | } | 45 | } |
| @@ -304,12 +49,6 @@ static ssize_t ssi_sys_help_show(struct kobject *kobj, · 3 unmodified lines | |||
| 304 | { | 49 | { |
| 305 | char *help_str[] = { | 50 | char *help_str[] = { |
| 306 | "cat reg_dump ", "Print several of CC register values", | 51 | "cat reg_dump ", "Print several of CC register values", |
| 307 | #if defined CC_CYCLE_COUNT | ||
| 308 | "cat stats_host ", "Print host statistics", | ||
| 309 | "echo <number> > stats_host", "Clear host statistics database", | ||
| 310 | "cat stats_cc ", "Print CC statistics", | ||
| 311 | "echo <number> > stats_cc ", "Clear CC statistics database", | ||
| 312 | #endif | ||
| 313 | }; | 52 | }; |
| 314 | int i = 0, offset = 0; | 53 | int i = 0, offset = 0; |
| 315 | 54 | ||
| @@ -376,7 +115,7 @@ static int sys_init_dir(struct sys_dir *sys_dir, struct ssi_drvdata *drvdata, · 60 unmodified lines | |||
| 376 | return -ENOMEM; | 115 | return -ENOMEM; |
| 377 | /* allocate memory for directory's attributes list */ | 116 | /* allocate memory for directory's attributes list */ |
| 378 | sys_dir->sys_dir_attr_list = | 117 | sys_dir->sys_dir_attr_list = |
| 379 | kzalloc(sizeof(struct attribute *) * (num_of_attrs + 1), | 118 | kcalloc(num_of_attrs + 1, sizeof(struct attribute *), |
| 380 | GFP_KERNEL); | 119 | GFP_KERNEL); |
| 381 | 120 | ||
| 382 | if (!(sys_dir->sys_dir_attr_list)) { | 121 | if (!(sys_dir->sys_dir_attr_list)) { |
| @@ -413,14 +152,9 @@ static void sys_free_dir(struct sys_dir *sys_dir) · 30 unmodified lines | |||
| 413 | int ssi_sysfs_init(struct kobject *sys_dev_obj, struct ssi_drvdata *drvdata) | 152 | int ssi_sysfs_init(struct kobject *sys_dev_obj, struct ssi_drvdata *drvdata) |
| 414 | { | 153 | { |
| 415 | int retval; | 154 | int retval; |
| 155 | struct device *dev = drvdata_to_dev(drvdata); | ||
| 416 | 156 | ||
| 417 | #if defined CC_CYCLE_COUNT | 157 | dev_info(dev, "setup sysfs under %s\n", sys_dev_obj->name); |
| 418 | /* Init. statistics */ | ||
| 419 | init_db(stat_host_db); | ||
| 420 | init_db(stat_cc_db); | ||
| 421 | #endif | ||
| 422 | |||
| 423 | SSI_LOG_ERR("setup sysfs under %s\n", sys_dev_obj->name); | ||
| 424 | 158 | ||
| 425 | /* Initialize top directory */ | 159 | /* Initialize top directory */ |
| 426 | retval = sys_init_dir(&sys_top_dir, drvdata, sys_dev_obj, "cc_info", | 160 | retval = sys_init_dir(&sys_top_dir, drvdata, sys_dev_obj, "cc_info", |
| @@ -785,8 +785,8 @@ config COMEDI_ADV_PCI_DIO · 784 unmodified lines | |||
| 785 | ---help--- | 785 | ---help--- |
| 786 | Enable support for Advantech PCI DIO cards | 786 | Enable support for Advantech PCI DIO cards |
| 787 | PCI-1730, PCI-1733, PCI-1734, PCI-1735U, PCI-1736UP, PCI-1739U, | 787 | PCI-1730, PCI-1733, PCI-1734, PCI-1735U, PCI-1736UP, PCI-1739U, |
| 788 | PCI-1750, PCI-1751, PCI-1752, PCI-1753/E, PCI-1754, PCI-1756 and | 788 | PCI-1750, PCI-1751, PCI-1752, PCI-1753/E, PCI-1754, PCI-1756, |
| 789 | PCI-1762 | 789 | PCI-1761 and PCI-1762 |
| 790 | 790 | ||
| 791 | To compile this driver as a module, choose M here: the module will be | 791 | To compile this driver as a module, choose M here: the module will be |
| 792 | called adv_pci_dio. | 792 | called adv_pci_dio. |
| @@ -12,9 +12,9 @@ · 11 unmodified lines | |||
| 12 | * Devices: [Advantech] PCI-1730 (adv_pci_dio), PCI-1733, | 12 | * Devices: [Advantech] PCI-1730 (adv_pci_dio), PCI-1733, |
| 13 | * PCI-1734, PCI-1735U, PCI-1736UP, PCI-1739U, PCI-1750, | 13 | * PCI-1734, PCI-1735U, PCI-1736UP, PCI-1739U, PCI-1750, |
| 14 | * PCI-1751, PCI-1752, PCI-1753, PCI-1753+PCI-1753E, | 14 | * PCI-1751, PCI-1752, PCI-1753, PCI-1753+PCI-1753E, |
| 15 | * PCI-1754, PCI-1756, PCI-1762 | 15 | * PCI-1754, PCI-1756, PCI-1761, PCI-1762 |
| 16 | * Author: Michal Dobes <dobes@tesnet.cz> | 16 | * Author: Michal Dobes <dobes@tesnet.cz> |
| 17 | * Updated: Mon, 09 Jan 2012 12:40:46 +0000 | 17 | * Updated: Fri, 25 Aug 2017 07:23:06 +0300 |
| 18 | * Status: untested | 18 | * Status: untested |
| 19 | * | 19 | * |
| 20 | * Configuration Options: not applicable, uses PCI auto config | 20 | * Configuration Options: not applicable, uses PCI auto config |
| @@ -50,6 +50,11 @@ · 29 unmodified lines | |||
| 50 | /* PCI-1752, PCI-1756 special registers */ | 50 | /* PCI-1752, PCI-1756 special registers */ |
| 51 | #define PCI1752_CFC_REG 0x12 /* R/W: channel freeze function */ | 51 | #define PCI1752_CFC_REG 0x12 /* R/W: channel freeze function */ |
| 52 | 52 | ||
| 53 | /* PCI-1761 interrupt control registers */ | ||
| 54 | #define PCI1761_INT_EN_REG 0x03 /* R/W: enable/disable interrupts */ | ||
| 55 | #define PCI1761_INT_RF_REG 0x04 /* R/W: falling/rising edge */ | ||
| 56 | #define PCI1761_INT_CLR_REG 0x05 /* R/W: clear interrupts */ | ||
| 57 | |||
| 53 | /* PCI-1762 interrupt control registers */ | 58 | /* PCI-1762 interrupt control registers */ |
| 54 | #define PCI1762_INT_REG 0x06 /* R/W: status/control */ | 59 | #define PCI1762_INT_REG 0x06 /* R/W: status/control */ |
| 55 | 60 | ||
| @@ -72,6 +77,7 @@ enum pci_dio_boardid { · 16 unmodified lines | |||
| 72 | TYPE_PCI1753E, | 77 | TYPE_PCI1753E, |
| 73 | TYPE_PCI1754, | 78 | TYPE_PCI1754, |
| 74 | TYPE_PCI1756, | 79 | TYPE_PCI1756, |
| 80 | TYPE_PCI1761, | ||
| 75 | TYPE_PCI1762 | 81 | TYPE_PCI1762 |
| 76 | }; | 82 | }; |
| 77 | 83 | ||
| @@ -181,6 +187,13 @@ static const struct dio_boardtype boardtypes[] = { · 103 unmodified lines | |||
| 181 | .id_reg = 0x10, | 187 | .id_reg = 0x10, |
| 182 | .is_16bit = 1, | 188 | .is_16bit = 1, |
| 183 | }, | 189 | }, |
| 190 | [TYPE_PCI1761] = { | ||
| 191 | .name = "pci1761", | ||
| 192 | .nsubdevs = 3, | ||
| 193 | .sdi[1] = { 8, 0x01 }, /* ISO DI 0-7 */ | ||
| 194 | .sdo[1] = { 8, 0x00 }, /* RELAY DO 0-7 */ | ||
| 195 | .id_reg = 0x02, | ||
| 196 | }, | ||
| 184 | [TYPE_PCI1762] = { | 197 | [TYPE_PCI1762] = { |
| 185 | .name = "pci1762", | 198 | .name = "pci1762", |
| 186 | .nsubdevs = 3, | 199 | .nsubdevs = 3, |
| @@ -309,6 +322,14 @@ static int pci_dio_reset(struct comedi_device *dev, unsigned long cardtype) · 122 unmodified lines | |||
| 309 | outw(0x08, dev->iobase + PCI1754_INT_REG(3)); | 322 | outw(0x08, dev->iobase + PCI1754_INT_REG(3)); |
| 310 | } | 323 | } |
| 311 | break; | 324 | break; |
| 325 | case TYPE_PCI1761: | ||
| 326 | /* disable interrupts */ | ||
| 327 | outb(0, dev->iobase + PCI1761_INT_EN_REG); | ||
| 328 | /* clear interrupts */ | ||
| 329 | outb(0xff, dev->iobase + PCI1761_INT_CLR_REG); | ||
| 330 | /* set rising edge trigger */ | ||
| 331 | outb(0, dev->iobase + PCI1761_INT_RF_REG); | ||
| 332 | break; | ||
| 312 | case TYPE_PCI1762: | 333 | case TYPE_PCI1762: |
| 313 | outw(0x0101, dev->iobase + PCI1762_INT_REG); | 334 | outw(0x0101, dev->iobase + PCI1762_INT_REG); |
| 314 | break; | 335 | break; |
| @@ -496,6 +517,7 @@ static const struct pci_device_id adv_pci_dio_pci_table[] = { · 181 unmodified lines | |||
| 496 | { PCI_VDEVICE(ADVANTECH, 0x1753), TYPE_PCI1753 }, | 517 | { PCI_VDEVICE(ADVANTECH, 0x1753), TYPE_PCI1753 }, |
| 497 | { PCI_VDEVICE(ADVANTECH, 0x1754), TYPE_PCI1754 }, | 518 | { PCI_VDEVICE(ADVANTECH, 0x1754), TYPE_PCI1754 }, |
| 498 | { PCI_VDEVICE(ADVANTECH, 0x1756), TYPE_PCI1756 }, | 519 | { PCI_VDEVICE(ADVANTECH, 0x1756), TYPE_PCI1756 }, |
| 520 | { PCI_VDEVICE(ADVANTECH, 0x1761), TYPE_PCI1761 }, | ||
| 499 | { PCI_VDEVICE(ADVANTECH, 0x1762), TYPE_PCI1762 }, | 521 | { PCI_VDEVICE(ADVANTECH, 0x1762), TYPE_PCI1762 }, |
| 500 | { 0 } | 522 | { 0 } |
| 501 | }; | 523 | }; |
| @@ -93,6 +93,7 @@ struct waveform_private { · 92 unmodified lines | |||
| 93 | unsigned int ai_scan_period; /* AI scan period in usec */ | 93 | unsigned int ai_scan_period; /* AI scan period in usec */ |
| 94 | unsigned int ai_convert_period; /* AI conversion period in usec */ | 94 | unsigned int ai_convert_period; /* AI conversion period in usec */ |
| 95 | struct timer_list ao_timer; /* timer for AO commands */ | 95 | struct timer_list ao_timer; /* timer for AO commands */ |
| 96 | struct comedi_device *dev; /* parent comedi device */ | ||
| 96 | u64 ao_last_scan_time; /* time of previous AO scan in usec */ | 97 | u64 ao_last_scan_time; /* time of previous AO scan in usec */ |
| 97 | unsigned int ao_scan_period; /* AO scan period in usec */ | 98 | unsigned int ao_scan_period; /* AO scan period in usec */ |
| 98 | unsigned short ao_loopbacks[N_CHANS]; | 99 | unsigned short ao_loopbacks[N_CHANS]; |
| @@ -201,10 +202,10 @@ static unsigned short fake_waveform(struct comedi_device *dev, · 102 unmodified lines | |||
| 201 | * It should run in the background; therefore it is scheduled by | 202 | * It should run in the background; therefore it is scheduled by |
| 202 | * a timer mechanism. | 203 | * a timer mechanism. |
| 203 | */ | 204 | */ |
| 204 | static void waveform_ai_timer(unsigned long arg) | 205 | static void waveform_ai_timer(struct timer_list *t) |
| 205 | { | 206 | { |
| 206 | struct comedi_device *dev = (struct comedi_device *)arg; | 207 | struct waveform_private *devpriv = from_timer(devpriv, t, ai_timer); |
| 207 | struct waveform_private *devpriv = dev->private; | 208 | struct comedi_device *dev = devpriv->dev; |
| 208 | struct comedi_subdevice *s = dev->read_subdev; | 209 | struct comedi_subdevice *s = dev->read_subdev; |
| 209 | struct comedi_async *async = s->async; | 210 | struct comedi_async *async = s->async; |
| 210 | struct comedi_cmd *cmd = &async->cmd; | 211 | struct comedi_cmd *cmd = &async->cmd; |
| @@ -438,10 +439,10 @@ static int waveform_ai_insn_read(struct comedi_device *dev, · 227 unmodified lines | |||
| 438 | * This is the background routine to handle AO commands, scheduled by | 439 | * This is the background routine to handle AO commands, scheduled by |
| 439 | * a timer mechanism. | 440 | * a timer mechanism. |
| 440 | */ | 441 | */ |
| 441 | static void waveform_ao_timer(unsigned long arg) | 442 | static void waveform_ao_timer(struct timer_list *t) |
| 442 | { | 443 | { |
| 443 | struct comedi_device *dev = (struct comedi_device *)arg; | 444 | struct waveform_private *devpriv = from_timer(devpriv, t, ao_timer); |
| 444 | struct waveform_private *devpriv = dev->private; | 445 | struct comedi_device *dev = devpriv->dev; |
| 445 | struct comedi_subdevice *s = dev->write_subdev; | 446 | struct comedi_subdevice *s = dev->write_subdev; |
| 446 | struct comedi_async *async = s->async; | 447 | struct comedi_async *async = s->async; |
| 447 | struct comedi_cmd *cmd = &async->cmd; | 448 | struct comedi_cmd *cmd = &async->cmd; |
| @@ -686,8 +687,9 @@ static int waveform_common_attach(struct comedi_device *dev, · 238 unmodified lines | |||
| 686 | for (i = 0; i < s->n_chan; i++) | 687 | for (i = 0; i < s->n_chan; i++) |
| 687 | devpriv->ao_loopbacks[i] = s->maxdata / 2; | 688 | devpriv->ao_loopbacks[i] = s->maxdata / 2; |
| 688 | 689 | ||
| 689 | setup_timer(&devpriv->ai_timer, waveform_ai_timer, (unsigned long)dev); | 690 | devpriv->dev = dev; |
| 690 | setup_timer(&devpriv->ao_timer, waveform_ao_timer, (unsigned long)dev); | 691 | timer_setup(&devpriv->ai_timer, waveform_ai_timer, 0); |
| 692 | timer_setup(&devpriv->ao_timer, waveform_ao_timer, 0); | ||
| 691 | 693 | ||
| 692 | dev_info(dev->class_dev, | 694 | dev_info(dev->class_dev, |
| 693 | "%s: %u microvolt, %u microsecond waveform attached\n", | 695 | "%s: %u microvolt, %u microsecond waveform attached\n", |
| @@ -440,6 +440,7 @@ static inline int timer_period(void) · 439 unmodified lines | |||
| 440 | 440 | ||
| 441 | struct das16_private_struct { | 441 | struct das16_private_struct { |
| 442 | struct comedi_isadma *dma; | 442 | struct comedi_isadma *dma; |
| 443 | struct comedi_device *dev; | ||
| 443 | unsigned int clockbase; | 444 | unsigned int clockbase; |
| 444 | unsigned int ctrl_reg; | 445 | unsigned int ctrl_reg; |
| 445 | unsigned int divisor1; | 446 | unsigned int divisor1; |
| @@ -525,10 +526,10 @@ static void das16_interrupt(struct comedi_device *dev) · 79 unmodified lines | |||
| 525 | comedi_handle_events(dev, s); | 526 | comedi_handle_events(dev, s); |
| 526 | } | 527 | } |
| 527 | 528 | ||
| 528 | static void das16_timer_interrupt(unsigned long arg) | 529 | static void das16_timer_interrupt(struct timer_list *t) |
| 529 | { | 530 | { |
| 530 | struct comedi_device *dev = (struct comedi_device *)arg; | 531 | struct das16_private_struct *devpriv = from_timer(devpriv, t, timer); |
| 531 | struct das16_private_struct *devpriv = dev->private; | 532 | struct comedi_device *dev = devpriv->dev; |
| 532 | unsigned long flags; | 533 | unsigned long flags; |
| 533 | 534 | ||
| 534 | das16_interrupt(dev); | 535 | das16_interrupt(dev); |
| @@ -934,6 +935,8 @@ static void das16_alloc_dma(struct comedi_device *dev, unsigned int dma_chan) · 399 unmodified lines | |||
| 934 | { | 935 | { |
| 935 | struct das16_private_struct *devpriv = dev->private; | 936 | struct das16_private_struct *devpriv = dev->private; |
| 936 | 937 | ||
| 938 | timer_setup(&devpriv->timer, das16_timer_interrupt, 0); | ||
| 939 | |||
| 937 | /* only DMA channels 3 and 1 are valid */ | 940 | /* only DMA channels 3 and 1 are valid */ |
| 938 | if (!(dma_chan == 1 || dma_chan == 3)) | 941 | if (!(dma_chan == 1 || dma_chan == 3)) |
| 939 | return; | 942 | return; |
| @@ -941,10 +944,6 @@ static void das16_alloc_dma(struct comedi_device *dev, unsigned int dma_chan) · 1 unmodified line | |||
| 941 | /* DMA uses two buffers */ | 944 | /* DMA uses two buffers */ |
| 942 | devpriv->dma = comedi_isadma_alloc(dev, 2, dma_chan, dma_chan, | 945 | devpriv->dma = comedi_isadma_alloc(dev, 2, dma_chan, dma_chan, |
| 943 | DAS16_DMA_SIZE, COMEDI_ISADMA_READ); | 946 | DAS16_DMA_SIZE, COMEDI_ISADMA_READ); |
| 944 | if (devpriv->dma) { | ||
| 945 | setup_timer(&devpriv->timer, das16_timer_interrupt, | ||
| 946 | (unsigned long)dev); | ||
| 947 | } | ||
| 948 | } | 947 | } |
| 949 | 948 | ||
| 950 | static void das16_free_dma(struct comedi_device *dev) | 949 | static void das16_free_dma(struct comedi_device *dev) |
| @@ -952,8 +951,7 @@ static void das16_free_dma(struct comedi_device *dev) · 1 unmodified line | |||
| 952 | struct das16_private_struct *devpriv = dev->private; | 951 | struct das16_private_struct *devpriv = dev->private; |
| 953 | 952 | ||
| 954 | if (devpriv) { | 953 | if (devpriv) { |
| 955 | if (devpriv->timer.data) | 954 | del_timer_sync(&devpriv->timer); |
| 956 | del_timer_sync(&devpriv->timer); | ||
| 957 | comedi_isadma_free(devpriv->dma); | 955 | comedi_isadma_free(devpriv->dma); |
| 958 | } | 956 | } |
| 959 | } | 957 | } |
| @@ -1046,6 +1044,7 @@ static int das16_attach(struct comedi_device *dev, struct comedi_devconfig *it) · 86 unmodified lines | |||
| 1046 | devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); | 1044 | devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); |
| 1047 | if (!devpriv) | 1045 | if (!devpriv) |
| 1048 | return -ENOMEM; | 1046 | return -ENOMEM; |
| 1047 | devpriv->dev = dev; | ||
| 1049 | 1048 | ||
| 1050 | if (board->size < 0x400) { | 1049 | if (board->size < 0x400) { |
| 1051 | ret = comedi_request_region(dev, it->options[0], board->size); | 1050 | ret = comedi_request_region(dev, it->options[0], board->size); |
| @@ -1062,6 +1062,8 @@ static void dt282x_alloc_dma(struct comedi_device *dev, · 1061 unmodified lines | |||
| 1062 | PAGE_SIZE, 0); | 1062 | PAGE_SIZE, 0); |
| 1063 | if (!devpriv->dma) | 1063 | if (!devpriv->dma) |
| 1064 | free_irq(irq_num, dev); | 1064 | free_irq(irq_num, dev); |
| 1065 | else | ||
| 1066 | dev->irq = irq_num; | ||
| 1065 | } | 1067 | } |
| 1066 | 1068 | ||
| 1067 | static void dt282x_free_dma(struct comedi_device *dev) | 1069 | static void dt282x_free_dma(struct comedi_device *dev) |
| @@ -96,6 +96,7 @@ struct jr3_pci_poll_delay { · 95 unmodified lines | |||
| 96 | 96 | ||
| 97 | struct jr3_pci_dev_private { | 97 | struct jr3_pci_dev_private { |
| 98 | struct timer_list timer; | 98 | struct timer_list timer; |
| 99 | struct comedi_device *dev; | ||
| 99 | }; | 100 | }; |
| 100 | 101 | ||
| 101 | union jr3_pci_single_range { | 102 | union jr3_pci_single_range { |
| @@ -585,10 +586,10 @@ jr3_pci_poll_subdevice(struct comedi_subdevice *s) · 483 unmodified lines | |||
| 585 | return result; | 586 | return result; |
| 586 | } | 587 | } |
| 587 | 588 | ||
| 588 | static void jr3_pci_poll_dev(unsigned long data) | 589 | static void jr3_pci_poll_dev(struct timer_list *t) |
| 589 | { | 590 | { |
| 590 | struct comedi_device *dev = (struct comedi_device *)data; | 591 | struct jr3_pci_dev_private *devpriv = from_timer(devpriv, t, timer); |
| 591 | struct jr3_pci_dev_private *devpriv = dev->private; | 592 | struct comedi_device *dev = devpriv->dev; |
| 592 | struct jr3_pci_subdev_private *spriv; | 593 | struct jr3_pci_subdev_private *spriv; |
| 593 | struct comedi_subdevice *s; | 594 | struct comedi_subdevice *s; |
| 594 | unsigned long flags; | 595 | unsigned long flags; |
| @@ -770,7 +771,8 @@ static int jr3_pci_auto_attach(struct comedi_device *dev, · 175 unmodified lines | |||
| 770 | spriv->next_time_min = jiffies + msecs_to_jiffies(500); | 771 | spriv->next_time_min = jiffies + msecs_to_jiffies(500); |
| 771 | } | 772 | } |
| 772 | 773 | ||
| 773 | setup_timer(&devpriv->timer, jr3_pci_poll_dev, (unsigned long)dev); | 774 | devpriv->dev = dev; |
| 775 | timer_setup(&devpriv->timer, jr3_pci_poll_dev, 0); | ||
| 774 | devpriv->timer.expires = jiffies + msecs_to_jiffies(1000); | 776 | devpriv->timer.expires = jiffies + msecs_to_jiffies(1000); |
| 775 | add_timer(&devpriv->timer); | 777 | add_timer(&devpriv->timer); |
| 776 | 778 | ||
| @@ -408,9 +408,8 @@ static int s526_gpct_winsn(struct comedi_device *dev, · 407 unmodified lines | |||
| 408 | */ | 408 | */ |
| 409 | if ((data[1] <= data[0]) || !data[0]) | 409 | if ((data[1] <= data[0]) || !data[0]) |
| 410 | return -EINVAL; | 410 | return -EINVAL; |
| 411 | 411 | /* to write the PULSE_WIDTH */ | |
| 412 | /* Fall thru to write the PULSE_WIDTH */ | 412 | /* fall through */ |
| 413 | |||
| 414 | case INSN_CONFIG_GPCT_QUADRATURE_ENCODER: | 413 | case INSN_CONFIG_GPCT_QUADRATURE_ENCODER: |
| 415 | case INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR: | 414 | case INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR: |
| 416 | s526_gpct_write(dev, chan, data[0]); | 415 | s526_gpct_write(dev, chan, data[0]); |
| @@ -291,7 +291,7 @@ static void dgnc_free_irq(struct dgnc_board *brd) · 290 unmodified lines | |||
| 291 | * waiter needs to be woken up, and (b) whether the poller needs to | 291 | * waiter needs to be woken up, and (b) whether the poller needs to |
| 292 | * be rescheduled. | 292 | * be rescheduled. |
| 293 | */ | 293 | */ |
| 294 | static void dgnc_poll_handler(ulong dummy) | 294 | static void dgnc_poll_handler(struct timer_list *unused) |
| 295 | { | 295 | { |
| 296 | struct dgnc_board *brd; | 296 | struct dgnc_board *brd; |
| 297 | unsigned long flags; | 297 | unsigned long flags; |
| @@ -323,7 +323,7 @@ static void dgnc_poll_handler(ulong dummy) · 25 unmodified lines | |||
| 323 | if ((ulong)new_time >= 2 * dgnc_poll_tick) | 323 | if ((ulong)new_time >= 2 * dgnc_poll_tick) |
| 324 | dgnc_poll_time = jiffies + dgnc_jiffies_from_ms(dgnc_poll_tick); | 324 | dgnc_poll_time = jiffies + dgnc_jiffies_from_ms(dgnc_poll_tick); |
| 325 | 325 | ||
| 326 | setup_timer(&dgnc_poll_timer, dgnc_poll_handler, 0); | 326 | timer_setup(&dgnc_poll_timer, dgnc_poll_handler, 0); |
| 327 | dgnc_poll_timer.expires = dgnc_poll_time; | 327 | dgnc_poll_timer.expires = dgnc_poll_time; |
| 328 | spin_unlock_irqrestore(&dgnc_poll_lock, flags); | 328 | spin_unlock_irqrestore(&dgnc_poll_lock, flags); |
| 329 | 329 | ||
| @@ -392,8 +392,6 @@ static int dgnc_start(void) · 62 unmodified lines | |||
| 392 | unsigned long flags; | 392 | unsigned long flags; |
| 393 | struct device *dev; | 393 | struct device *dev; |
| 394 | 394 | ||
| 395 | init_timer(&dgnc_poll_timer); | ||
| 396 | |||
| 397 | rc = register_chrdev(0, "dgnc", &dgnc_board_fops); | 395 | rc = register_chrdev(0, "dgnc", &dgnc_board_fops); |
| 398 | if (rc < 0) { | 396 | if (rc < 0) { |
| 399 | pr_err(DRVSTR ": Can't register dgnc driver device (%d)\n", rc); | 397 | pr_err(DRVSTR ": Can't register dgnc driver device (%d)\n", rc); |
| @@ -419,7 +417,7 @@ static int dgnc_start(void) · 19 unmodified lines | |||
| 419 | 417 | ||
| 420 | /* Start the poller */ | 418 | /* Start the poller */ |
| 421 | spin_lock_irqsave(&dgnc_poll_lock, flags); | 419 | spin_lock_irqsave(&dgnc_poll_lock, flags); |
| 422 | setup_timer(&dgnc_poll_timer, dgnc_poll_handler, 0); | 420 | timer_setup(&dgnc_poll_timer, dgnc_poll_handler, 0); |
| 423 | dgnc_poll_time = jiffies + dgnc_jiffies_from_ms(dgnc_poll_tick); | 421 | dgnc_poll_time = jiffies + dgnc_jiffies_from_ms(dgnc_poll_tick); |
| 424 | dgnc_poll_timer.expires = dgnc_poll_time; | 422 | dgnc_poll_timer.expires = dgnc_poll_time; |
| 425 | spin_unlock_irqrestore(&dgnc_poll_lock, flags); | 423 | spin_unlock_irqrestore(&dgnc_poll_lock, flags); |
| @@ -104,7 +104,6 @@ struct board_ops { · 103 unmodified lines | |||
| 104 | * struct dgnc_board - Per board information. | 104 | * struct dgnc_board - Per board information. |
| 105 | * @boardnum: Board number (0 - 32). | 105 | * @boardnum: Board number (0 - 32). |
| 106 | * | 106 | * |
| 107 | * @type: Type of board. | ||
| 108 | * @name: Product name. | 107 | * @name: Product name. |
| 109 | * @pdev: Pointer to the pci_dev structure. | 108 | * @pdev: Pointer to the pci_dev structure. |
| 110 | * @bd_flags: Board flags. | 109 | * @bd_flags: Board flags. |
| @@ -140,13 +139,9 @@ struct board_ops { · 29 unmodified lines | |||
| 140 | * @dpastatus: Board status as defined by DPA. | 139 | * @dpastatus: Board status as defined by DPA. |
| 141 | * @bd_dividend: Board/UART's specific dividend. | 140 | * @bd_dividend: Board/UART's specific dividend. |
| 142 | * @bd_ops: Pointer to board operations structure. | 141 | * @bd_ops: Pointer to board operations structure. |
| 143 | * @proc_entry_pointer: Proc/<board> entry | ||
| 144 | * @dgnc_board_table: Proc/<board> entry | ||
| 145 | */ | 142 | */ |
| 146 | struct dgnc_board { | 143 | struct dgnc_board { |
| 147 | int boardnum; | 144 | int boardnum; |
| 148 | |||
| 149 | int type; | ||
| 150 | char *name; | 145 | char *name; |
| 151 | struct pci_dev *pdev; | 146 | struct pci_dev *pdev; |
| 152 | unsigned long bd_flags; | 147 | unsigned long bd_flags; |
| @@ -200,10 +195,6 @@ struct dgnc_board { · 47 unmodified lines | |||
| 200 | uint bd_dividend; | 195 | uint bd_dividend; |
| 201 | 196 | ||
| 202 | struct board_ops *bd_ops; | 197 | struct board_ops *bd_ops; |
| 203 | |||
| 204 | struct proc_dir_entry *proc_entry_pointer; | ||
| 205 | struct dgnc_proc_entry *dgnc_board_table; | ||
| 206 | |||
| 207 | }; | 198 | }; |
| 208 | 199 | ||
| 209 | /* Unit flag definitions for un_flags. */ | 200 | /* Unit flag definitions for un_flags. */ |
| @@ -233,7 +224,6 @@ struct device; · 23 unmodified lines | |||
| 233 | */ | 224 | */ |
| 234 | struct un_t { | 225 | struct un_t { |
| 235 | struct channel_t *un_ch; | 226 | struct channel_t *un_ch; |
| 236 | ulong un_time; | ||
| 237 | uint un_type; | 227 | uint un_type; |
| 238 | uint un_open_count; | 228 | uint un_open_count; |
| 239 | struct tty_struct *un_tty; | 229 | struct tty_struct *un_tty; |
| @@ -321,8 +311,6 @@ struct un_t { · 81 unmodified lines | |||
| 321 | * @ch_err_overrun: Count of overruns on channel. | 311 | * @ch_err_overrun: Count of overruns on channel. |
| 322 | * @ch_xon_sends: Count of xons transmitted. | 312 | * @ch_xon_sends: Count of xons transmitted. |
| 323 | * @ch_xoff_sends: Count of xoffs transmitted. | 313 | * @ch_xoff_sends: Count of xoffs transmitted. |
| 324 | * @proc_entry_pointer: Proc/<board>/<channel> entry. | ||
| 325 | * @dgnc_channel_table: Proc/<board>/<channel> entry. | ||
| 326 | */ | 314 | */ |
| 327 | struct channel_t { | 315 | struct channel_t { |
| 328 | struct dgnc_board *ch_bd; | 316 | struct dgnc_board *ch_bd; |
| @@ -391,10 +379,6 @@ struct channel_t { · 62 unmodified lines | |||
| 391 | 379 | ||
| 392 | ulong ch_xon_sends; | 380 | ulong ch_xon_sends; |
| 393 | ulong ch_xoff_sends; | 381 | ulong ch_xoff_sends; |
| 394 | |||
| 395 | struct proc_dir_entry *proc_entry_pointer; | ||
| 396 | struct dgnc_proc_entry *dgnc_channel_table; | ||
| 397 | |||
| 398 | }; | 382 | }; |
| 399 | 383 | ||
| 400 | extern uint dgnc_major; /* Our driver/mgmt major */ | 384 | extern uint dgnc_major; /* Our driver/mgmt major */ |
| @@ -1182,7 +1182,6 @@ static int neo_drain(struct tty_struct *tty, uint seconds) · 1181 unmodified lines | |||
| 1182 | unsigned long flags; | 1182 | unsigned long flags; |
| 1183 | struct channel_t *ch; | 1183 | struct channel_t *ch; |
| 1184 | struct un_t *un; | 1184 | struct un_t *un; |
| 1185 | int rc = 0; | ||
| 1186 | 1185 | ||
| 1187 | if (!tty) | 1186 | if (!tty) |
| 1188 | return -ENXIO; | 1187 | return -ENXIO; |
| @@ -1199,12 +1198,10 @@ static int neo_drain(struct tty_struct *tty, uint seconds) · 10 unmodified lines | |||
| 1199 | un->un_flags |= UN_EMPTY; | 1198 | un->un_flags |= UN_EMPTY; |
| 1200 | spin_unlock_irqrestore(&ch->ch_lock, flags); | 1199 | spin_unlock_irqrestore(&ch->ch_lock, flags); |
| 1201 | 1200 | ||
| 1202 | rc = wait_event_interruptible_timeout(un->un_flags_wait, | 1201 | /* If returned value is non-zero, user ctrl-c'ed us */ |
| 1203 | ((un->un_flags & UN_EMPTY) == 0), | 1202 | return wait_event_interruptible_timeout(un->un_flags_wait, |
| 1204 | msecs_to_jiffies(seconds * 1000)); | 1203 | ((un->un_flags & UN_EMPTY) == 0), |
| 1205 | 1204 | msecs_to_jiffies(seconds * 1000)); | |
| 1206 | /* If ret is non-zero, user ctrl-c'ed us */ | ||
| 1207 | return rc; | ||
| 1208 | } | 1205 | } |
| 1209 | 1206 | ||
| 1210 | /* | 1207 | /* |
| @@ -253,7 +253,7 @@ static void write_reg8_bus8(struct fbtft_par *par, int len, ...) · 252 unmodified lines | |||
| 253 | static int write_vmem16_bus8(struct fbtft_par *par, size_t offset, size_t len) | 253 | static int write_vmem16_bus8(struct fbtft_par *par, size_t offset, size_t len) |
| 254 | { | 254 | { |
| 255 | u16 *vmem16; | 255 | u16 *vmem16; |
| 256 | __be16 *txbuf16 = par->txbuf.buf; | 256 | __be16 *txbuf16; |
| 257 | size_t remain; | 257 | size_t remain; |
| 258 | size_t to_copy; | 258 | size_t to_copy; |
| 259 | size_t tx_array_size; | 259 | size_t tx_array_size; |
| @@ -267,10 +267,10 @@ static int write_vmem16_bus8(struct fbtft_par *par, size_t offset, size_t len) · 7 unmodified lines | |||
| 267 | remain = len / 2; | 267 | remain = len / 2; |
| 268 | vmem16 = (u16 *)(par->info->screen_buffer + offset); | 268 | vmem16 = (u16 *)(par->info->screen_buffer + offset); |
| 269 | tx_array_size = par->txbuf.len / 2; | 269 | tx_array_size = par->txbuf.len / 2; |
| 270 | txbuf16 = par->txbuf.buf + 1; | 270 | txbuf16 = par->txbuf.buf + 1; |
| 271 | tx_array_size -= 2; | 271 | tx_array_size -= 2; |
| 272 | *(u8 *)(par->txbuf.buf) = 0x00; | 272 | *(u8 *)(par->txbuf.buf) = 0x00; |
| 273 | startbyte_size = 1; | 273 | startbyte_size = 1; |
| 274 | 274 | ||
| 275 | while (remain) { | 275 | while (remain) { |
| 276 | to_copy = min(tx_array_size, remain); | 276 | to_copy = min(tx_array_size, remain); |
| @@ -26,7 +26,13 @@ static int init_display(struct fbtft_par *par) · 25 unmodified lines | |||
| 26 | par->fbtftops.reset(par); | 26 | par->fbtftops.reset(par); |
| 27 | 27 | ||
| 28 | write_reg(par, 0xae); /* Display Off */ | 28 | write_reg(par, 0xae); /* Display Off */ |
| 29 | write_reg(par, 0xa0, 0x70 | (par->bgr << 2)); /* Set Colour Depth */ | 29 | |
| 30 | /* Set Column Address Mapping, COM Scan Direction and Colour Depth */ | ||
| 31 | if (par->info->var.rotate == 180) | ||
| 32 | write_reg(par, 0xa0, 0x60 | (par->bgr << 2)); | ||
| 33 | else | ||
| 34 | write_reg(par, 0xa0, 0x72 | (par->bgr << 2)); | ||
| 35 | |||
| 30 | write_reg(par, 0x72); /* RGB colour */ | 36 | write_reg(par, 0x72); /* RGB colour */ |
| 31 | write_reg(par, 0xa1, 0x00); /* Set Display Start Line */ | 37 | write_reg(par, 0xa1, 0x00); /* Set Display Start Line */ |
| 32 | write_reg(par, 0xa2, 0x00); /* Set Display Offset */ | 38 | write_reg(par, 0xa2, 0x00); /* Set Display Offset */ |
| @@ -225,7 +225,7 @@ static int write_vmem(struct fbtft_par *par, size_t offset, size_t len) · 224 unmodified lines | |||
| 225 | u8 *buf8 = par->txbuf.buf; | 225 | u8 *buf8 = par->txbuf.buf; |
| 226 | u16 *buf16 = par->txbuf.buf; | 226 | u16 *buf16 = par->txbuf.buf; |
| 227 | int line_length = par->info->fix.line_length; | 227 | int line_length = par->info->fix.line_length; |
| 228 | int y_start = (offset / line_length); | 228 | int y_start = offset / line_length; |
| 229 | int y_end = (offset + len - 1) / line_length; | 229 | int y_end = (offset + len - 1) / line_length; |
| 230 | int x, y, i; | 230 | int x, y, i; |
| 231 | int ret = 0; | 231 | int ret = 0; |
| @@ -127,7 +127,7 @@ static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye) · 126 unmodified lines | |||
| 127 | static int write_vmem(struct fbtft_par *par, size_t offset, size_t len) | 127 | static int write_vmem(struct fbtft_par *par, size_t offset, size_t len) |
| 128 | { | 128 | { |
| 129 | u16 *vmem16 = (u16 *)par->info->screen_buffer; | 129 | u16 *vmem16 = (u16 *)par->info->screen_buffer; |
| 130 | u8 *buf = par->txbuf.buf; | 130 | u8 *buf; |
| 131 | int x, y, i; | 131 | int x, y, i; |
| 132 | int ret = 0; | 132 | int ret = 0; |
| 133 | 133 | ||
| @@ -11,33 +11,33 @@ · 10 unmodified lines | |||
| 11 | * | 11 | * |
| 12 | *****************************************************************************/ | 12 | *****************************************************************************/ |
| 13 | 13 | ||
| 14 | #define define_fbtft_write_reg(func, type, modifier) \ | 14 | #define define_fbtft_write_reg(func, buffer_type, data_type, modifier) \ |
| 15 | void func(struct fbtft_par *par, int len, ...) \ | 15 | void func(struct fbtft_par *par, int len, ...) \ |
| 16 | { \ | 16 | { \ |
| 17 | va_list args; \ | 17 | va_list args; \ |
| 18 | int i, ret; \ | 18 | int i, ret; \ |
| 19 | int offset = 0; \ | 19 | int offset = 0; \ |
| 20 | type *buf = (type *)par->buf; \ | 20 | buffer_type *buf = (buffer_type *)par->buf; \ |
| 21 | \ | 21 | \ |
| 22 | if (unlikely(par->debug & DEBUG_WRITE_REGISTER)) { \ | 22 | if (unlikely(par->debug & DEBUG_WRITE_REGISTER)) { \ |
| 23 | va_start(args, len); \ | 23 | va_start(args, len); \ |
| 24 | for (i = 0; i < len; i++) { \ | 24 | for (i = 0; i < len; i++) { \ |
| 25 | buf[i] = (type)va_arg(args, unsigned int); \ | 25 | buf[i] = modifier((data_type)va_arg(args, unsigned int)); \ |
| 26 | } \ | 26 | } \ |
| 27 | va_end(args); \ | 27 | va_end(args); \ |
| 28 | fbtft_par_dbg_hex(DEBUG_WRITE_REGISTER, par, par->info->device, type, buf, len, "%s: ", __func__); \ | 28 | fbtft_par_dbg_hex(DEBUG_WRITE_REGISTER, par, par->info->device, buffer_type, buf, len, "%s: ", __func__); \ |
| 29 | } \ | 29 | } \ |
| 30 | \ | 30 | \ |
| 31 | va_start(args, len); \ | 31 | va_start(args, len); \ |
| 32 | \ | 32 | \ |
| 33 | if (par->startbyte) { \ | 33 | if (par->startbyte) { \ |
| 34 | *(u8 *)par->buf = par->startbyte; \ | 34 | *(u8 *)par->buf = par->startbyte; \ |
| 35 | buf = (type *)(par->buf + 1); \ | 35 | buf = (buffer_type *)(par->buf + 1); \ |
| 36 | offset = 1; \ | 36 | offset = 1; \ |
| 37 | } \ | 37 | } \ |
| 38 | \ | 38 | \ |
| 39 | *buf = modifier((type)va_arg(args, unsigned int)); \ | 39 | *buf = modifier((data_type)va_arg(args, unsigned int)); \ |
| 40 | ret = fbtft_write_buf_dc(par, par->buf, sizeof(type) + offset, 0); \ | 40 | ret = fbtft_write_buf_dc(par, par->buf, sizeof(data_type) + offset, 0); \ |
| 41 | if (ret < 0) \ | 41 | if (ret < 0) \ |
| 42 | goto out; \ | 42 | goto out; \ |
| 43 | len--; \ | 43 | len--; \ |
| @@ -48,18 +48,18 @@ void func(struct fbtft_par *par, int len, ...) \ · 4 unmodified lines | |||
| 48 | if (len) { \ | 48 | if (len) { \ |
| 49 | i = len; \ | 49 | i = len; \ |
| 50 | while (i--) \ | 50 | while (i--) \ |
| 51 | *buf++ = modifier((type)va_arg(args, unsigned int)); \ | 51 | *buf++ = modifier((data_type)va_arg(args, unsigned int)); \ |
| 52 | fbtft_write_buf_dc(par, par->buf, \ | 52 | fbtft_write_buf_dc(par, par->buf, \ |
| 53 | len * (sizeof(type) + offset), 1); \ | 53 | len * (sizeof(data_type) + offset), 1); \ |
| 54 | } \ | 54 | } \ |
| 55 | out: \ | 55 | out: \ |
| 56 | va_end(args); \ | 56 | va_end(args); \ |
| 57 | } \ | 57 | } \ |
| 58 | EXPORT_SYMBOL(func); | 58 | EXPORT_SYMBOL(func); |
| 59 | 59 | ||
| 60 | define_fbtft_write_reg(fbtft_write_reg8_bus8, u8, ) | 60 | define_fbtft_write_reg(fbtft_write_reg8_bus8, u8, u8, ) |
| 61 | define_fbtft_write_reg(fbtft_write_reg16_bus8, u16, cpu_to_be16) | 61 | define_fbtft_write_reg(fbtft_write_reg16_bus8, __be16, u16, cpu_to_be16) |
| 62 | define_fbtft_write_reg(fbtft_write_reg16_bus16, u16, ) | 62 | define_fbtft_write_reg(fbtft_write_reg16_bus16, u16, u16, ) |
| 63 | 63 | ||
| 64 | void fbtft_write_reg8_bus9(struct fbtft_par *par, int len, ...) | 64 | void fbtft_write_reg8_bus9(struct fbtft_par *par, int len, ...) |
| 65 | { | 65 | { |
| @@ -104,9 +104,11 @@ static void free_rx_fd(struct dpaa2_eth_priv *priv, · 103 unmodified lines | |||
| 104 | /* We don't support any other format */ | 104 | /* We don't support any other format */ |
| 105 | return; | 105 | return; |
| 106 | 106 | ||
| 107 | /* For S/G frames, we first need to free all SG entries */ | 107 | /* For S/G frames, we first need to free all SG entries |
| 108 | * except the first one, which was taken care of already | ||
| 109 | */ | ||
| 108 | sgt = vaddr + dpaa2_fd_get_offset(fd); | 110 | sgt = vaddr + dpaa2_fd_get_offset(fd); |
| 109 | for (i = 0; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) { | 111 | for (i = 1; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) { |
| 110 | addr = dpaa2_sg_get_addr(&sgt[i]); | 112 | addr = dpaa2_sg_get_addr(&sgt[i]); |
| 111 | sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr); | 113 | sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr); |
| 112 | dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE, | 114 | dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE, |
| @@ -131,16 +133,15 @@ static struct sk_buff *build_linear_skb(struct dpaa2_eth_priv *priv, · 18 unmodified lines | |||
| 131 | u16 fd_offset = dpaa2_fd_get_offset(fd); | 133 | u16 fd_offset = dpaa2_fd_get_offset(fd); |
| 132 | u32 fd_length = dpaa2_fd_get_len(fd); | 134 | u32 fd_length = dpaa2_fd_get_len(fd); |
| 133 | 135 | ||
| 134 | skb = build_skb(fd_vaddr, DPAA2_ETH_RX_BUF_SIZE + | 136 | ch->buf_count--; |
| 135 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info))); | 137 | |
| 138 | skb = build_skb(fd_vaddr, DPAA2_ETH_SKB_SIZE); | ||
| 136 | if (unlikely(!skb)) | 139 | if (unlikely(!skb)) |
| 137 | return NULL; | 140 | return NULL; |
| 138 | 141 | ||
| 139 | skb_reserve(skb, fd_offset); | 142 | skb_reserve(skb, fd_offset); |
| 140 | skb_put(skb, fd_length); | 143 | skb_put(skb, fd_length); |
| 141 | 144 | ||
| 142 | ch->buf_count--; | ||
| 143 | |||
| 144 | return skb; | 145 | return skb; |
| 145 | } | 146 | } |
| 146 | 147 | ||
| @@ -176,10 +177,21 @@ static struct sk_buff *build_frag_skb(struct dpaa2_eth_priv *priv, · 29 unmodified lines | |||
| 176 | 177 | ||
| 177 | if (i == 0) { | 178 | if (i == 0) { |
| 178 | /* We build the skb around the first data buffer */ | 179 | /* We build the skb around the first data buffer */ |
| 179 | skb = build_skb(sg_vaddr, DPAA2_ETH_RX_BUF_SIZE + | 180 | skb = build_skb(sg_vaddr, DPAA2_ETH_SKB_SIZE); |
| 180 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info))); | 181 | if (unlikely(!skb)) { |
| 181 | if (unlikely(!skb)) | 182 | /* Free the first SG entry now, since we already |
| 182 | return NULL; | 183 | * unmapped it and obtained the virtual address |
| 184 | */ | ||
| 185 | skb_free_frag(sg_vaddr); | ||
| 186 | |||
| 187 | /* We still need to subtract the buffers used | ||
| 188 | * by this FD from our software counter | ||
| 189 | */ | ||
| 190 | while (!dpaa2_sg_is_final(&sgt[i]) && | ||
| 191 | i < DPAA2_ETH_MAX_SG_ENTRIES) | ||
| 192 | i++; | ||
| 193 | break; | ||
| 194 | } | ||
| 183 | 195 | ||
| 184 | sg_offset = dpaa2_sg_get_offset(sge); | 196 | sg_offset = dpaa2_sg_get_offset(sge); |
| 185 | skb_reserve(skb, sg_offset); | 197 | skb_reserve(skb, sg_offset); |
| @@ -206,6 +218,8 @@ static struct sk_buff *build_frag_skb(struct dpaa2_eth_priv *priv, · 20 unmodified lines | |||
| 206 | break; | 218 | break; |
| 207 | } | 219 | } |
| 208 | 220 | ||
| 221 | WARN_ONCE(i == DPAA2_ETH_MAX_SG_ENTRIES, "Final bit not set in SGT"); | ||
| 222 | |||
| 209 | /* Count all data buffers + SG table buffer */ | 223 | /* Count all data buffers + SG table buffer */ |
| 210 | ch->buf_count -= i + 2; | 224 | ch->buf_count -= i + 2; |
| 211 | 225 | ||
| @@ -557,10 +571,10 @@ static netdev_tx_t dpaa2_eth_tx(struct sk_buff *skb, struct net_device *net_dev) · 345 unmodified lines | |||
| 557 | percpu_stats = this_cpu_ptr(priv->percpu_stats); | 571 | percpu_stats = this_cpu_ptr(priv->percpu_stats); |
| 558 | percpu_extras = this_cpu_ptr(priv->percpu_extras); | 572 | percpu_extras = this_cpu_ptr(priv->percpu_extras); |
| 559 | 573 | ||
| 560 | if (unlikely(skb_headroom(skb) < DPAA2_ETH_NEEDED_HEADROOM(priv))) { | 574 | if (unlikely(skb_headroom(skb) < dpaa2_eth_needed_headroom(priv))) { |
| 561 | struct sk_buff *ns; | 575 | struct sk_buff *ns; |
| 562 | 576 | ||
| 563 | ns = skb_realloc_headroom(skb, DPAA2_ETH_NEEDED_HEADROOM(priv)); | 577 | ns = skb_realloc_headroom(skb, dpaa2_eth_needed_headroom(priv)); |
| 564 | if (unlikely(!ns)) { | 578 | if (unlikely(!ns)) { |
| 565 | percpu_stats->tx_dropped++; | 579 | percpu_stats->tx_dropped++; |
| 566 | goto err_alloc_headroom; | 580 | goto err_alloc_headroom; |
| @@ -718,6 +732,23 @@ static int set_tx_csum(struct dpaa2_eth_priv *priv, bool enable) · 151 unmodified lines | |||
| 718 | return 0; | 732 | return 0; |
| 719 | } | 733 | } |
| 720 | 734 | ||
| 735 | /* Free buffers acquired from the buffer pool or which were meant to | ||
| 736 | * be released in the pool | ||
| 737 | */ | ||
| 738 | static void free_bufs(struct dpaa2_eth_priv *priv, u64 *buf_array, int count) | ||
| 739 | { | ||
| 740 | struct device *dev = priv->net_dev->dev.parent; | ||
| 741 | void *vaddr; | ||
| 742 | int i; | ||
| 743 | |||
| 744 | for (i = 0; i < count; i++) { | ||
| 745 | vaddr = dpaa2_iova_to_virt(priv->iommu_domain, buf_array[i]); | ||
| 746 | dma_unmap_single(dev, buf_array[i], DPAA2_ETH_RX_BUF_SIZE, | ||
| 747 | DMA_BIDIRECTIONAL); | ||
| 748 | skb_free_frag(vaddr); | ||
| 749 | } | ||
| 750 | } | ||
| 751 | |||
| 721 | /* Perform a single release command to add buffers | 752 | /* Perform a single release command to add buffers |
| 722 | * to the specified buffer pool | 753 | * to the specified buffer pool |
| 723 | */ | 754 | */ |
| @@ -727,17 +758,17 @@ static int add_bufs(struct dpaa2_eth_priv *priv, u16 bpid) · 3 unmodified lines | |||
| 727 | u64 buf_array[DPAA2_ETH_BUFS_PER_CMD]; | 758 | u64 buf_array[DPAA2_ETH_BUFS_PER_CMD]; |
| 728 | void *buf; | 759 | void *buf; |
| 729 | dma_addr_t addr; | 760 | dma_addr_t addr; |
| 730 | int i; | 761 | int i, err; |
| 731 | 762 | ||
| 732 | for (i = 0; i < DPAA2_ETH_BUFS_PER_CMD; i++) { | 763 | for (i = 0; i < DPAA2_ETH_BUFS_PER_CMD; i++) { |
| 733 | /* Allocate buffer visible to WRIOP + skb shared info + | 764 | /* Allocate buffer visible to WRIOP + skb shared info + |
| 734 | * alignment padding | 765 | * alignment padding |
| 735 | */ | 766 | */ |
| 736 | buf = napi_alloc_frag(DPAA2_ETH_BUF_RAW_SIZE); | 767 | buf = napi_alloc_frag(dpaa2_eth_buf_raw_size(priv)); |
| 737 | if (unlikely(!buf)) | 768 | if (unlikely(!buf)) |
| 738 | goto err_alloc; | 769 | goto err_alloc; |
| 739 | 770 | ||
| 740 | buf = PTR_ALIGN(buf, DPAA2_ETH_RX_BUF_ALIGN); | 771 | buf = PTR_ALIGN(buf, priv->rx_buf_align); |
| 741 | 772 | ||
| 742 | addr = dma_map_single(dev, buf, DPAA2_ETH_RX_BUF_SIZE, | 773 | addr = dma_map_single(dev, buf, DPAA2_ETH_RX_BUF_SIZE, |
| 743 | DMA_FROM_DEVICE); | 774 | DMA_FROM_DEVICE); |
| @@ -748,28 +779,33 @@ static int add_bufs(struct dpaa2_eth_priv *priv, u16 bpid) · 4 unmodified lines | |||
| 748 | 779 | ||
| 749 | /* tracing point */ | 780 | /* tracing point */ |
| 750 | trace_dpaa2_eth_buf_seed(priv->net_dev, | 781 | trace_dpaa2_eth_buf_seed(priv->net_dev, |
| 751 | buf, DPAA2_ETH_BUF_RAW_SIZE, | 782 | buf, dpaa2_eth_buf_raw_size(priv), |
| 752 | addr, DPAA2_ETH_RX_BUF_SIZE, | 783 | addr, DPAA2_ETH_RX_BUF_SIZE, |
| 753 | bpid); | 784 | bpid); |
| 754 | } | 785 | } |
| 755 | 786 | ||
| 756 | release_bufs: | 787 | release_bufs: |
| 757 | /* In case the portal is busy, retry until successful. | 788 | /* In case the portal is busy, retry until successful */ |
| 758 | * The buffer release function would only fail if the QBMan portal | 789 | while ((err = dpaa2_io_service_release(NULL, bpid, |
| 759 | * was busy, which implies portal contention (i.e. more CPUs than | 790 | buf_array, i)) == -EBUSY) |
| 760 | * portals, i.e. GPPs w/o affine DPIOs). For all practical purposes, | ||
| 761 | * there is little we can realistically do, short of giving up - | ||
| 762 | * in which case we'd risk depleting the buffer pool and never again | ||
| 763 | * receiving the Rx interrupt which would kick-start the refill logic. | ||
| 764 | * So just keep retrying, at the risk of being moved to ksoftirqd. | ||
| 765 | */ | ||
| 766 | while (dpaa2_io_service_release(NULL, bpid, buf_array, i)) | ||
| 767 | cpu_relax(); | 791 | cpu_relax(); |
| 792 | |||
| 793 | /* If release command failed, clean up and bail out; | ||
| 794 | * not much else we can do about it | ||
| 795 | */ | ||
| 796 | if (err) { | ||
| 797 | free_bufs(priv, buf_array, i); | ||
| 798 | return 0; | ||
| 799 | } | ||
| 800 | |||
| 768 | return i; | 801 | return i; |
| 769 | 802 | ||
| 770 | err_map: | 803 | err_map: |
| 771 | skb_free_frag(buf); | 804 | skb_free_frag(buf); |
| 772 | err_alloc: | 805 | err_alloc: |
| 806 | /* If we managed to allocate at least some buffers, | ||
| 807 | * release them to hardware | ||
| 808 | */ | ||
| 773 | if (i) | 809 | if (i) |
| 774 | goto release_bufs; | 810 | goto release_bufs; |
| 775 | 811 | ||
| @@ -811,10 +847,8 @@ static int seed_pool(struct dpaa2_eth_priv *priv, u16 bpid) · 35 unmodified lines | |||
| 811 | */ | 847 | */ |
| 812 | static void drain_bufs(struct dpaa2_eth_priv *priv, int count) | 848 | static void drain_bufs(struct dpaa2_eth_priv *priv, int count) |
| 813 | { | 849 | { |
| 814 | struct device *dev = priv->net_dev->dev.parent; | ||
| 815 | u64 buf_array[DPAA2_ETH_BUFS_PER_CMD]; | 850 | u64 buf_array[DPAA2_ETH_BUFS_PER_CMD]; |
| 816 | void *vaddr; | 851 | int ret; |
| 817 | int ret, i; | ||
| 818 | 852 | ||
| 819 | do { | 853 | do { |
| 820 | ret = dpaa2_io_service_acquire(NULL, priv->bpid, | 854 | ret = dpaa2_io_service_acquire(NULL, priv->bpid, |
| @@ -823,15 +857,7 @@ static void drain_bufs(struct dpaa2_eth_priv *priv, int count) · 2 unmodified lines | |||
| 823 | netdev_err(priv->net_dev, "dpaa2_io_service_acquire() failed\n"); | 857 | netdev_err(priv->net_dev, "dpaa2_io_service_acquire() failed\n"); |
| 824 | return; | 858 | return; |
| 825 | } | 859 | } |
| 826 | for (i = 0; i < ret; i++) { | 860 | free_bufs(priv, buf_array, ret); |
| 827 | /* Same logic as on regular Rx path */ | ||
| 828 | vaddr = dpaa2_iova_to_virt(priv->iommu_domain, | ||
| 829 | buf_array[i]); | ||
| 830 | dma_unmap_single(dev, buf_array[i], | ||
| 831 | DPAA2_ETH_RX_BUF_SIZE, | ||
| 832 | DMA_FROM_DEVICE); | ||
| 833 | skb_free_frag(vaddr); | ||
| 834 | } | ||
| 835 | } while (ret); | 861 | } while (ret); |
| 836 | } | 862 | } |
| 837 | 863 | ||
| @@ -927,13 +953,14 @@ static int dpaa2_eth_poll(struct napi_struct *napi, int budget) · 89 unmodified lines | |||
| 927 | break; | 953 | break; |
| 928 | } | 954 | } |
| 929 | 955 | ||
| 930 | if (cleaned < budget) { | 956 | if (cleaned < budget && napi_complete_done(napi, cleaned)) { |
| 931 | napi_complete_done(napi, cleaned); | ||
| 932 | /* Re-enable data available notifications */ | 957 | /* Re-enable data available notifications */ |
| 933 | do { | 958 | do { |
| 934 | err = dpaa2_io_service_rearm(NULL, &ch->nctx); | 959 | err = dpaa2_io_service_rearm(NULL, &ch->nctx); |
| 935 | cpu_relax(); | 960 | cpu_relax(); |
| 936 | } while (err == -EBUSY); | 961 | } while (err == -EBUSY); |
| 962 | WARN_ONCE(err, "CDAN notifications rearm failed on core %d", | ||
| 963 | ch->nctx.desired_cpu); | ||
| 937 | } | 964 | } |
| 938 | 965 | ||
| 939 | ch->stats.frames += cleaned; | 966 | ch->stats.frames += cleaned; |
| @@ -1415,34 +1442,32 @@ static struct fsl_mc_device *setup_dpcon(struct dpaa2_eth_priv *priv) · 475 unmodified lines | |||
| 1415 | err = dpcon_open(priv->mc_io, 0, dpcon->obj_desc.id, &dpcon->mc_handle); | 1442 | err = dpcon_open(priv->mc_io, 0, dpcon->obj_desc.id, &dpcon->mc_handle); |
| 1416 | if (err) { | 1443 | if (err) { |
| 1417 | dev_err(dev, "dpcon_open() failed\n"); | 1444 | dev_err(dev, "dpcon_open() failed\n"); |
| 1418 | goto err_open; | 1445 | goto free; |
| 1419 | } | 1446 | } |
| 1420 | 1447 | ||
| 1421 | err = dpcon_reset(priv->mc_io, 0, dpcon->mc_handle); | 1448 | err = dpcon_reset(priv->mc_io, 0, dpcon->mc_handle); |
| 1422 | if (err) { | 1449 | if (err) { |
| 1423 | dev_err(dev, "dpcon_reset() failed\n"); | 1450 | dev_err(dev, "dpcon_reset() failed\n"); |
| 1424 | goto err_reset; | 1451 | goto close; |
| 1425 | } | 1452 | } |
| 1426 | 1453 | ||
| 1427 | err = dpcon_get_attributes(priv->mc_io, 0, dpcon->mc_handle, &attrs); | 1454 | err = dpcon_get_attributes(priv->mc_io, 0, dpcon->mc_handle, &attrs); |
| 1428 | if (err) { | 1455 | if (err) { |
| 1429 | dev_err(dev, "dpcon_get_attributes() failed\n"); | 1456 | dev_err(dev, "dpcon_get_attributes() failed\n"); |
| 1430 | goto err_get_attr; | 1457 | goto close; |
| 1431 | } | 1458 | } |
| 1432 | 1459 | ||
| 1433 | err = dpcon_enable(priv->mc_io, 0, dpcon->mc_handle); | 1460 | err = dpcon_enable(priv->mc_io, 0, dpcon->mc_handle); |
| 1434 | if (err) { | 1461 | if (err) { |
| 1435 | dev_err(dev, "dpcon_enable() failed\n"); | 1462 | dev_err(dev, "dpcon_enable() failed\n"); |
| 1436 | goto err_enable; | 1463 | goto close; |
| 1437 | } | 1464 | } |
| 1438 | 1465 | ||
| 1439 | return dpcon; | 1466 | return dpcon; |
| 1440 | 1467 | ||
| 1441 | err_enable: | 1468 | close: |
| 1442 | err_get_attr: | ||
| 1443 | err_reset: | ||
| 1444 | dpcon_close(priv->mc_io, 0, dpcon->mc_handle); | 1469 | dpcon_close(priv->mc_io, 0, dpcon->mc_handle); |
| 1445 | err_open: | 1470 | free: |
| 1446 | fsl_mc_object_free(dpcon); | 1471 | fsl_mc_object_free(dpcon); |
| 1447 | 1472 | ||
| 1448 | return NULL; | 1473 | return NULL; |
| @@ -1749,66 +1774,32 @@ static void free_dpbp(struct dpaa2_eth_priv *priv) · 300 unmodified lines | |||
| 1749 | fsl_mc_object_free(priv->dpbp_dev); | 1774 | fsl_mc_object_free(priv->dpbp_dev); |
| 1750 | } | 1775 | } |
| 1751 | 1776 | ||
| 1752 | /* Configure the DPNI object this interface is associated with */ | 1777 | static int set_buffer_layout(struct dpaa2_eth_priv *priv) |
| 1753 | static int setup_dpni(struct fsl_mc_device *ls_dev) | ||
| 1754 | { | 1778 | { |
| 1755 | struct device *dev = &ls_dev->dev; | 1779 | struct device *dev = priv->net_dev->dev.parent; |
| 1756 | struct dpaa2_eth_priv *priv; | ||
| 1757 | struct net_device *net_dev; | ||
| 1758 | struct dpni_buffer_layout buf_layout = {0}; | 1780 | struct dpni_buffer_layout buf_layout = {0}; |
| 1759 | int err; | 1781 | int err; |
| 1760 | 1782 | ||
| 1761 | net_dev = dev_get_drvdata(dev); | 1783 | /* We need to check for WRIOP version 1.0.0, but depending on the MC |
| 1762 | priv = netdev_priv(net_dev); | 1784 | * version, this number is not always provided correctly on rev1. |
| 1763 | 1785 | * We need to check for both alternatives in this situation. | |
| 1764 | /* get a handle for the DPNI object */ | 1786 | */ |
| 1765 | err = dpni_open(priv->mc_io, 0, ls_dev->obj_desc.id, &priv->mc_token); | 1787 | if (priv->dpni_attrs.wriop_version == DPAA2_WRIOP_VERSION(0, 0, 0) || |
| 1766 | if (err) { | 1788 | priv->dpni_attrs.wriop_version == DPAA2_WRIOP_VERSION(1, 0, 0)) |
| 1767 | dev_err(dev, "dpni_open() failed\n"); | 1789 | priv->rx_buf_align = DPAA2_ETH_RX_BUF_ALIGN_REV1; |
| 1768 | goto err_open; | 1790 | else |
| 1769 | } | 1791 | priv->rx_buf_align = DPAA2_ETH_RX_BUF_ALIGN; |
| 1770 | |||
| 1771 | ls_dev->mc_io = priv->mc_io; | ||
| 1772 | ls_dev->mc_handle = priv->mc_token; | ||
| 1773 | |||
| 1774 | err = dpni_reset(priv->mc_io, 0, priv->mc_token); | ||
| 1775 | if (err) { | ||
| 1776 | dev_err(dev, "dpni_reset() failed\n"); | ||
| 1777 | goto err_reset; | ||
| 1778 | } | ||
| 1779 | |||
| 1780 | err = dpni_get_attributes(priv->mc_io, 0, priv->mc_token, | ||
| 1781 | &priv->dpni_attrs); | ||
| 1782 | if (err) { | ||
| 1783 | dev_err(dev, "dpni_get_attributes() failed (err=%d)\n", err); | ||
| 1784 | goto err_get_attr; | ||
| 1785 | } | ||
| 1786 | 1792 | ||
| 1787 | /* Configure buffer layouts */ | 1793 | /* tx buffer */ |
| 1788 | /* rx buffer */ | ||
| 1789 | buf_layout.pass_parser_result = true; | ||
| 1790 | buf_layout.pass_frame_status = true; | 1794 | buf_layout.pass_frame_status = true; |
| 1791 | buf_layout.private_data_size = DPAA2_ETH_SWA_SIZE; | 1795 | buf_layout.private_data_size = DPAA2_ETH_SWA_SIZE; |
| 1792 | buf_layout.data_align = DPAA2_ETH_RX_BUF_ALIGN; | ||
| 1793 | buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT | | ||
| 1794 | DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | | ||
| 1795 | DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE | | ||
| 1796 | DPNI_BUF_LAYOUT_OPT_DATA_ALIGN; | ||
| 1797 | err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token, | ||
| 1798 | DPNI_QUEUE_RX, &buf_layout); | ||
| 1799 | if (err) { | ||
| 1800 | dev_err(dev, "dpni_set_buffer_layout(RX) failed\n"); | ||
| 1801 | goto err_buf_layout; | ||
| 1802 | } | ||
| 1803 | |||
| 1804 | /* tx buffer */ | ||
| 1805 | buf_layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | | 1796 | buf_layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | |
| 1806 | DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE; | 1797 | DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE; |
| 1807 | err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token, | 1798 | err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token, |
| 1808 | DPNI_QUEUE_TX, &buf_layout); | 1799 | DPNI_QUEUE_TX, &buf_layout); |
| 1809 | if (err) { | 1800 | if (err) { |
| 1810 | dev_err(dev, "dpni_set_buffer_layout(TX) failed\n"); | 1801 | dev_err(dev, "dpni_set_buffer_layout(TX) failed\n"); |
| 1811 | goto err_buf_layout; | 1802 | return err; |
| 1812 | } | 1803 | } |
| 1813 | 1804 | ||
| 1814 | /* tx-confirm buffer */ | 1805 | /* tx-confirm buffer */ |
| @@ -1817,7 +1808,7 @@ static int setup_dpni(struct fsl_mc_device *ls_dev) · 2 unmodified lines | |||
| 1817 | DPNI_QUEUE_TX_CONFIRM, &buf_layout); | 1808 | DPNI_QUEUE_TX_CONFIRM, &buf_layout); |
| 1818 | if (err) { | 1809 | if (err) { |
| 1819 | dev_err(dev, "dpni_set_buffer_layout(TX_CONF) failed\n"); | 1810 | dev_err(dev, "dpni_set_buffer_layout(TX_CONF) failed\n"); |
| 1820 | goto err_buf_layout; | 1811 | return err; |
| 1821 | } | 1812 | } |
| 1822 | 1813 | ||
| 1823 | /* Now that we've set our tx buffer layout, retrieve the minimum | 1814 | /* Now that we've set our tx buffer layout, retrieve the minimum |
| @@ -1827,24 +1818,76 @@ static int setup_dpni(struct fsl_mc_device *ls_dev) · 3 unmodified lines | |||
| 1827 | &priv->tx_data_offset); | 1818 | &priv->tx_data_offset); |
| 1828 | if (err) { | 1819 | if (err) { |
| 1829 | dev_err(dev, "dpni_get_tx_data_offset() failed\n"); | 1820 | dev_err(dev, "dpni_get_tx_data_offset() failed\n"); |
| 1830 | goto err_data_offset; | 1821 | return err; |
| 1831 | } | 1822 | } |
| 1832 | 1823 | ||
| 1833 | if ((priv->tx_data_offset % 64) != 0) | 1824 | if ((priv->tx_data_offset % 64) != 0) |
| 1834 | dev_warn(dev, "Tx data offset (%d) not a multiple of 64B\n", | 1825 | dev_warn(dev, "Tx data offset (%d) not a multiple of 64B\n", |
| 1835 | priv->tx_data_offset); | 1826 | priv->tx_data_offset); |
| 1836 | 1827 | ||
| 1837 | /* Accommodate software annotation space (SWA) */ | 1828 | /* rx buffer */ |
| 1838 | priv->tx_data_offset += DPAA2_ETH_SWA_SIZE; | 1829 | buf_layout.pass_parser_result = true; |
| 1830 | buf_layout.data_align = priv->rx_buf_align; | ||
| 1831 | buf_layout.data_head_room = dpaa2_eth_rx_head_room(priv); | ||
| 1832 | buf_layout.private_data_size = 0; | ||
| 1833 | buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT | | ||
| 1834 | DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | | ||
| 1835 | DPNI_BUF_LAYOUT_OPT_DATA_ALIGN | | ||
| 1836 | DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM; | ||
| 1837 | err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token, | ||
| 1838 | DPNI_QUEUE_RX, &buf_layout); | ||
| 1839 | if (err) { | ||
| 1840 | dev_err(dev, "dpni_set_buffer_layout(RX) failed\n"); | ||
| 1841 | return err; | ||
| 1842 | } | ||
| 1839 | 1843 | ||
| 1840 | return 0; | 1844 | return 0; |
| 1845 | } | ||
| 1841 | 1846 | ||
| 1842 | err_data_offset: | 1847 | /* Configure the DPNI object this interface is associated with */ |
| 1843 | err_buf_layout: | 1848 | static int setup_dpni(struct fsl_mc_device *ls_dev) |
| 1844 | err_get_attr: | 1849 | { |
| 1845 | err_reset: | 1850 | struct device *dev = &ls_dev->dev; |
| 1851 | struct dpaa2_eth_priv *priv; | ||
| 1852 | struct net_device *net_dev; | ||
| 1853 | int err; | ||
| 1854 | |||
| 1855 | net_dev = dev_get_drvdata(dev); | ||
| 1856 | priv = netdev_priv(net_dev); | ||
| 1857 | |||
| 1858 | /* get a handle for the DPNI object */ | ||
| 1859 | err = dpni_open(priv->mc_io, 0, ls_dev->obj_desc.id, &priv->mc_token); | ||
| 1860 | if (err) { | ||
| 1861 | dev_err(dev, "dpni_open() failed\n"); | ||
| 1862 | return err; | ||
| 1863 | } | ||
| 1864 | |||
| 1865 | ls_dev->mc_io = priv->mc_io; | ||
| 1866 | ls_dev->mc_handle = priv->mc_token; | ||
| 1867 | |||
| 1868 | err = dpni_reset(priv->mc_io, 0, priv->mc_token); | ||
| 1869 | if (err) { | ||
| 1870 | dev_err(dev, "dpni_reset() failed\n"); | ||
| 1871 | goto close; | ||
| 1872 | } | ||
| 1873 | |||
| 1874 | err = dpni_get_attributes(priv->mc_io, 0, priv->mc_token, | ||
| 1875 | &priv->dpni_attrs); | ||
| 1876 | if (err) { | ||
| 1877 | dev_err(dev, "dpni_get_attributes() failed (err=%d)\n", err); | ||
| 1878 | goto close; | ||
| 1879 | } | ||
| 1880 | |||
| 1881 | err = set_buffer_layout(priv); | ||
| 1882 | if (err) | ||
| 1883 | goto close; | ||
| 1884 | |||
| 1885 | |||
| 1886 | return 0; | ||
| 1887 | |||
| 1888 | close: | ||
| 1846 | dpni_close(priv->mc_io, 0, priv->mc_token); | 1889 | dpni_close(priv->mc_io, 0, priv->mc_token); |
| 1847 | err_open: | 1890 | |
| 1848 | return err; | 1891 | return err; |
| 1849 | } | 1892 | } |
| 1850 | 1893 | ||
| @@ -2085,7 +2128,7 @@ static int bind_dpni(struct dpaa2_eth_priv *priv) · 234 unmodified lines | |||
| 2085 | */ | 2128 | */ |
| 2086 | err = dpaa2_eth_set_hash(net_dev, DPAA2_RXH_SUPPORTED); | 2129 | err = dpaa2_eth_set_hash(net_dev, DPAA2_RXH_SUPPORTED); |
| 2087 | if (err) | 2130 | if (err) |
| 2088 | netdev_err(net_dev, "Failed to configure hashing\n"); | 2131 | dev_err(dev, "Failed to configure hashing\n"); |
| 2089 | 2132 | ||
| 2090 | /* Configure handling of error frames */ | 2133 | /* Configure handling of error frames */ |
| 2091 | err_cfg.errors = DPAA2_FAS_RX_ERR_MASK; | 2134 | err_cfg.errors = DPAA2_FAS_RX_ERR_MASK; |
| @@ -2230,6 +2273,7 @@ static int netdev_init(struct net_device *net_dev) · 138 unmodified lines | |||
| 2230 | { | 2273 | { |
| 2231 | struct device *dev = net_dev->dev.parent; | 2274 | struct device *dev = net_dev->dev.parent; |
| 2232 | struct dpaa2_eth_priv *priv = netdev_priv(net_dev); | 2275 | struct dpaa2_eth_priv *priv = netdev_priv(net_dev); |
| 2276 | u16 rx_headroom, req_headroom; | ||
| 2233 | u8 bcast_addr[ETH_ALEN]; | 2277 | u8 bcast_addr[ETH_ALEN]; |
| 2234 | u8 num_queues; | 2278 | u8 num_queues; |
| 2235 | int err; | 2279 | int err; |
| @@ -2251,7 +2295,20 @@ static int netdev_init(struct net_device *net_dev) · 15 unmodified lines | |||
| 2251 | /* Reserve enough space to align buffer as per hardware requirement; | 2295 | /* Reserve enough space to align buffer as per hardware requirement; |
| 2252 | * NOTE: priv->tx_data_offset MUST be initialized at this point. | 2296 | * NOTE: priv->tx_data_offset MUST be initialized at this point. |
| 2253 | */ | 2297 | */ |
| 2254 | net_dev->needed_headroom = DPAA2_ETH_NEEDED_HEADROOM(priv); | 2298 | net_dev->needed_headroom = dpaa2_eth_needed_headroom(priv); |
| 2299 | |||
| 2300 | /* If headroom guaranteed by hardware in the Rx frame buffer is | ||
| 2301 | * smaller than the Tx headroom required by the stack, issue a | ||
| 2302 | * one time warning. This will most likely mean skbs forwarded to | ||
| 2303 | * another DPAA2 network interface will get reallocated, with a | ||
| 2304 | * significant performance impact. | ||
| 2305 | */ | ||
| 2306 | req_headroom = LL_RESERVED_SPACE(net_dev) - ETH_HLEN; | ||
| 2307 | rx_headroom = ALIGN(DPAA2_ETH_RX_HWA_SIZE + | ||
| 2308 | dpaa2_eth_rx_head_room(priv), priv->rx_buf_align); | ||
| 2309 | if (req_headroom > rx_headroom) | ||
| 2310 | dev_info_once(dev, "Required headroom (%d) greater than available (%d)\n", | ||
| 2311 | req_headroom, rx_headroom); | ||
| 2255 | 2312 | ||
| 2256 | /* Set MTU limits */ | 2313 | /* Set MTU limits */ |
| 2257 | net_dev->min_mtu = 68; | 2314 | net_dev->min_mtu = 68; |
| @@ -2303,7 +2360,7 @@ static irqreturn_t dpni_irq0_handler(int irq_num, void *arg) · 45 unmodified lines | |||
| 2303 | 2360 | ||
| 2304 | static irqreturn_t dpni_irq0_handler_thread(int irq_num, void *arg) | 2361 | static irqreturn_t dpni_irq0_handler_thread(int irq_num, void *arg) |
| 2305 | { | 2362 | { |
| 2306 | u32 status = 0, clear = 0; | 2363 | u32 status = ~0; |
| 2307 | struct device *dev = (struct device *)arg; | 2364 | struct device *dev = (struct device *)arg; |
| 2308 | struct fsl_mc_device *dpni_dev = to_fsl_mc_device(dev); | 2365 | struct fsl_mc_device *dpni_dev = to_fsl_mc_device(dev); |
| 2309 | struct net_device *net_dev = dev_get_drvdata(dev); | 2366 | struct net_device *net_dev = dev_get_drvdata(dev); |
| @@ -2313,18 +2370,12 @@ static irqreturn_t dpni_irq0_handler_thread(int irq_num, void *arg) · 3 unmodified lines | |||
| 2313 | DPNI_IRQ_INDEX, &status); | 2370 | DPNI_IRQ_INDEX, &status); |
| 2314 | if (unlikely(err)) { | 2371 | if (unlikely(err)) { |
| 2315 | netdev_err(net_dev, "Can't get irq status (err %d)\n", err); | 2372 | netdev_err(net_dev, "Can't get irq status (err %d)\n", err); |
| 2316 | clear = 0xffffffff; | 2373 | return IRQ_HANDLED; |
| 2317 | goto out; | ||
| 2318 | } | 2374 | } |
| 2319 | 2375 | ||
| 2320 | if (status & DPNI_IRQ_EVENT_LINK_CHANGED) { | 2376 | if (status & DPNI_IRQ_EVENT_LINK_CHANGED) |
| 2321 | clear |= DPNI_IRQ_EVENT_LINK_CHANGED; | ||
| 2322 | link_state_update(netdev_priv(net_dev)); | 2377 | link_state_update(netdev_priv(net_dev)); |
| 2323 | } | ||
| 2324 | 2378 | ||
| 2325 | out: | ||
| 2326 | dpni_clear_irq_status(dpni_dev->mc_io, 0, dpni_dev->mc_handle, | ||
| 2327 | DPNI_IRQ_INDEX, clear); | ||
| 2328 | return IRQ_HANDLED; | 2379 | return IRQ_HANDLED; |
| 2329 | } | 2380 | } |
| 2330 | 2381 | ||
| @@ -45,6 +45,8 @@ · 44 unmodified lines | |||
| 45 | 45 | ||
| 46 | #include "dpaa2-eth-trace.h" | 46 | #include "dpaa2-eth-trace.h" |
| 47 | 47 | ||
| 48 | #define DPAA2_WRIOP_VERSION(x, y, z) ((x) << 10 | (y) << 5 | (z) << 0) | ||
| 49 | |||
| 48 | #define DPAA2_ETH_STORE_SIZE 16 | 50 | #define DPAA2_ETH_STORE_SIZE 16 |
| 49 | 51 | ||
| 50 | /* Maximum number of scatter-gather entries in an ingress frame, | 52 | /* Maximum number of scatter-gather entries in an ingress frame, |
| @@ -80,23 +82,21 @@ · 29 unmodified lines | |||
| 80 | */ | 82 | */ |
| 81 | #define DPAA2_ETH_BUFS_PER_CMD 7 | 83 | #define DPAA2_ETH_BUFS_PER_CMD 7 |
| 82 | 84 | ||
| 83 | /* Hardware requires alignment for ingress/egress buffer addresses | 85 | /* Hardware requires alignment for ingress/egress buffer addresses */ |
| 84 | * and ingress buffer lengths. | ||
| 85 | */ | ||
| 86 | #define DPAA2_ETH_RX_BUF_SIZE 2048 | ||
| 87 | #define DPAA2_ETH_TX_BUF_ALIGN 64 | 86 | #define DPAA2_ETH_TX_BUF_ALIGN 64 |
| 88 | #define DPAA2_ETH_RX_BUF_ALIGN 256 | ||
| 89 | #define DPAA2_ETH_NEEDED_HEADROOM(p_priv) \ | ||
| 90 | ((p_priv)->tx_data_offset + DPAA2_ETH_TX_BUF_ALIGN) | ||
| 91 | 87 | ||
| 92 | /* Hardware only sees DPAA2_ETH_RX_BUF_SIZE, but we need to allocate ingress | 88 | #define DPAA2_ETH_RX_BUF_SIZE 2048 |
| 93 | * buffers large enough to allow building an skb around them and also account | 89 | #define DPAA2_ETH_SKB_SIZE \ |
| 94 | * for alignment restrictions | 90 | (DPAA2_ETH_RX_BUF_SIZE + SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) |
| 91 | |||
| 92 | /* Hardware annotation area in RX buffers */ | ||
| 93 | #define DPAA2_ETH_RX_HWA_SIZE 64 | ||
| 94 | |||
| 95 | /* Due to a limitation in WRIOP 1.0.0, the RX buffer data must be aligned | ||
| 96 | * to 256B. For newer revisions, the requirement is only for 64B alignment | ||
| 95 | */ | 97 | */ |
| 96 | #define DPAA2_ETH_BUF_RAW_SIZE \ | 98 | #define DPAA2_ETH_RX_BUF_ALIGN_REV1 256 |
| 97 | (DPAA2_ETH_RX_BUF_SIZE + \ | 99 | #define DPAA2_ETH_RX_BUF_ALIGN 64 |
| 98 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + \ | ||
| 99 | DPAA2_ETH_RX_BUF_ALIGN) | ||
| 100 | 100 | ||
| 101 | /* We are accommodating a skb backpointer and some S/G info | 101 | /* We are accommodating a skb backpointer and some S/G info |
| 102 | * in the frame's software annotation. The hardware | 102 | * in the frame's software annotation. The hardware |
| @@ -134,7 +134,7 @@ struct dpaa2_eth_swa { · 31 unmodified lines | |||
| 134 | DPAA2_FD_CTRL_FAERR) | 134 | DPAA2_FD_CTRL_FAERR) |
| 135 | 135 | ||
| 136 | /* Annotation bits in FD CTRL */ | 136 | /* Annotation bits in FD CTRL */ |
| 137 | #define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128 */ | 137 | #define DPAA2_FD_CTRL_ASAL 0x00010000 /* ASAL = 64 */ |
| 138 | #define DPAA2_FD_CTRL_PTA 0x00800000 | 138 | #define DPAA2_FD_CTRL_PTA 0x00800000 |
| 139 | #define DPAA2_FD_CTRL_PTV1 0x00400000 | 139 | #define DPAA2_FD_CTRL_PTV1 0x00400000 |
| 140 | 140 | ||
| @@ -318,6 +318,7 @@ struct dpaa2_eth_priv { · 177 unmodified lines | |||
| 318 | struct iommu_domain *iommu_domain; | 318 | struct iommu_domain *iommu_domain; |
| 319 | 319 | ||
| 320 | u16 tx_qdid; | 320 | u16 tx_qdid; |
| 321 | u16 rx_buf_align; | ||
| 321 | struct fsl_mc_io *mc_io; | 322 | struct fsl_mc_io *mc_io; |
| 322 | /* Cores which have an affine DPIO/DPCON. | 323 | /* Cores which have an affine DPIO/DPCON. |
| 323 | * This is the cpu set on which Rx and Tx conf frames are processed | 324 | * This is the cpu set on which Rx and Tx conf frames are processed |
| @@ -353,6 +354,29 @@ struct dpaa2_eth_priv { · 29 unmodified lines | |||
| 353 | extern const struct ethtool_ops dpaa2_ethtool_ops; | 354 | extern const struct ethtool_ops dpaa2_ethtool_ops; |
| 354 | extern const char dpaa2_eth_drv_version[]; | 355 | extern const char dpaa2_eth_drv_version[]; |
| 355 | 356 | ||
| 357 | /* Hardware only sees DPAA2_ETH_RX_BUF_SIZE, but the skb built around | ||
| 358 | * the buffer also needs space for its shared info struct, and we need | ||
| 359 | * to allocate enough to accommodate hardware alignment restrictions | ||
| 360 | */ | ||
| 361 | static inline unsigned int dpaa2_eth_buf_raw_size(struct dpaa2_eth_priv *priv) | ||
| 362 | { | ||
| 363 | return DPAA2_ETH_SKB_SIZE + priv->rx_buf_align; | ||
| 364 | } | ||
| 365 | |||
| 366 | static inline | ||
| 367 | unsigned int dpaa2_eth_needed_headroom(struct dpaa2_eth_priv *priv) | ||
| 368 | { | ||
| 369 | return priv->tx_data_offset + DPAA2_ETH_TX_BUF_ALIGN - HH_DATA_MOD; | ||
| 370 | } | ||
| 371 | |||
| 372 | /* Extra headroom space requested to hardware, in order to make sure there's | ||
| 373 | * no realloc'ing in forwarding scenarios | ||
| 374 | */ | ||
| 375 | static inline unsigned int dpaa2_eth_rx_head_room(struct dpaa2_eth_priv *priv) | ||
| 376 | { | ||
| 377 | return dpaa2_eth_needed_headroom(priv) - DPAA2_ETH_RX_HWA_SIZE; | ||
| 378 | } | ||
| 379 | |||
| 356 | static int dpaa2_eth_queue_count(struct dpaa2_eth_priv *priv) | 380 | static int dpaa2_eth_queue_count(struct dpaa2_eth_priv *priv) |
| 357 | { | 381 | { |
| 358 | return priv->dpni_attrs.num_queues; | 382 | return priv->dpni_attrs.num_queues; |
| @@ -76,10 +76,22 @@ static char dpaa2_ethtool_extras[][ETH_GSTRING_LEN] = { · 75 unmodified lines | |||
| 76 | static void dpaa2_eth_get_drvinfo(struct net_device *net_dev, | 76 | static void dpaa2_eth_get_drvinfo(struct net_device *net_dev, |
| 77 | struct ethtool_drvinfo *drvinfo) | 77 | struct ethtool_drvinfo *drvinfo) |
| 78 | { | 78 | { |
| 79 | struct dpaa2_eth_priv *priv = netdev_priv(net_dev); | ||
| 80 | u16 fw_major, fw_minor; | ||
| 81 | int err; | ||
| 82 | |||
| 79 | strlcpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver)); | 83 | strlcpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver)); |
| 80 | strlcpy(drvinfo->version, dpaa2_eth_drv_version, | 84 | strlcpy(drvinfo->version, dpaa2_eth_drv_version, |
| 81 | sizeof(drvinfo->version)); | 85 | sizeof(drvinfo->version)); |
| 82 | strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); | 86 | |
| 87 | err = dpni_get_api_version(priv->mc_io, 0, &fw_major, &fw_minor); | ||
| 88 | if (!err) | ||
| 89 | snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), | ||
| 90 | "%u.%u", fw_major, fw_minor); | ||
| 91 | else | ||
| 92 | strlcpy(drvinfo->fw_version, "N/A", | ||
| 93 | sizeof(drvinfo->fw_version)); | ||
| 94 | |||
| 83 | strlcpy(drvinfo->bus_info, dev_name(net_dev->dev.parent->parent), | 95 | strlcpy(drvinfo->bus_info, dev_name(net_dev->dev.parent->parent), |
| 84 | sizeof(drvinfo->bus_info)); | 96 | sizeof(drvinfo->bus_info)); |
| 85 | } | 97 | } |
| @@ -538,4 +538,9 @@ struct dpni_rsp_get_taildrop { · 537 unmodified lines | |||
| 538 | __le32 threshold; | 538 | __le32 threshold; |
| 539 | }; | 539 | }; |
| 540 | 540 | ||
| 541 | struct dpni_rsp_get_api_version { | ||
| 542 | u16 major; | ||
| 543 | u16 minor; | ||
| 544 | }; | ||
| 545 | |||
| 541 | #endif /* _FSL_DPNI_CMD_H */ | 546 | #endif /* _FSL_DPNI_CMD_H */ |
| @@ -1594,3 +1594,35 @@ int dpni_get_taildrop(struct fsl_mc_io *mc_io, · 1593 unmodified lines | |||
| 1594 | 1594 | ||
| 1595 | return 0; | 1595 | return 0; |
| 1596 | } | 1596 | } |
| 1597 | |||
| 1598 | /** | ||
| 1599 | * dpni_get_api_version() - Get Data Path Network Interface API version | ||
| 1600 | * @mc_io: Pointer to MC portal's I/O object | ||
| 1601 | * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' | ||
| 1602 | * @major_ver: Major version of data path network interface API | ||
| 1603 | * @minor_ver: Minor version of data path network interface API | ||
| 1604 | * | ||
| 1605 | * Return: '0' on Success; Error code otherwise. | ||
| 1606 | */ | ||
| 1607 | int dpni_get_api_version(struct fsl_mc_io *mc_io, | ||
| 1608 | u32 cmd_flags, | ||
| 1609 | u16 *major_ver, | ||
| 1610 | u16 *minor_ver) | ||
| 1611 | { | ||
| 1612 | struct dpni_rsp_get_api_version *rsp_params; | ||
| 1613 | struct mc_command cmd = { 0 }; | ||
| 1614 | int err; | ||
| 1615 | |||
| 1616 | cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_API_VERSION, | ||
| 1617 | cmd_flags, 0); | ||
| 1618 | |||
| 1619 | err = mc_send_command(mc_io, &cmd); | ||
| 1620 | if (err) | ||
| 1621 | return err; | ||
| 1622 | |||
| 1623 | rsp_params = (struct dpni_rsp_get_api_version *)cmd.params; | ||
| 1624 | *major_ver = le16_to_cpu(rsp_params->major); | ||
| 1625 | *minor_ver = le16_to_cpu(rsp_params->minor); | ||
| 1626 | |||
| 1627 | return 0; | ||
| 1628 | } | ||
| @@ -829,4 +829,9 @@ struct dpni_rule_cfg { · 828 unmodified lines | |||
| 829 | u8 key_size; | 829 | u8 key_size; |
| 830 | }; | 830 | }; |
| 831 | 831 | ||
| 832 | int dpni_get_api_version(struct fsl_mc_io *mc_io, | ||
| 833 | u32 cmd_flags, | ||
| 834 | u16 *major_ver, | ||
| 835 | u16 *minor_ver); | ||
| 836 | |||
| 832 | #endif /* __FSL_DPNI_H */ | 837 | #endif /* __FSL_DPNI_H */ |
| @@ -76,7 +76,7 @@ static inline struct dpaa2_io *service_select_by_cpu(struct dpaa2_io *d, · 75 unmodified lines | |||
| 76 | if (d) | 76 | if (d) |
| 77 | return d; | 77 | return d; |
| 78 | 78 | ||
| 79 | if (unlikely(cpu >= num_possible_cpus())) | 79 | if (cpu != DPAA2_IO_ANY_CPU && cpu >= num_possible_cpus()) |
| 80 | return NULL; | 80 | return NULL; |
| 81 | 81 | ||
| 82 | /* | 82 | /* |
| @@ -121,7 +121,7 @@ struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc) · 38 unmodified lines | |||
| 121 | return NULL; | 121 | return NULL; |
| 122 | 122 | ||
| 123 | /* check if CPU is out of range (-1 means any cpu) */ | 123 | /* check if CPU is out of range (-1 means any cpu) */ |
| 124 | if (desc->cpu >= num_possible_cpus()) { | 124 | if (desc->cpu != DPAA2_IO_ANY_CPU && desc->cpu >= num_possible_cpus()) { |
| 125 | kfree(obj); | 125 | kfree(obj); |
| 126 | return NULL; | 126 | return NULL; |
| 127 | } | 127 | } |
| @@ -137,7 +137,7 @@ static void fsl_mc_msi_update_chip_ops(struct msi_domain_info *info) · 136 unmodified lines | |||
| 137 | { | 137 | { |
| 138 | struct irq_chip *chip = info->chip; | 138 | struct irq_chip *chip = info->chip; |
| 139 | 139 | ||
| 140 | if (WARN_ON((!chip))) | 140 | if (WARN_ON(!chip)) |
| 141 | return; | 141 | return; |
| 142 | 142 | ||
| 143 | /* | 143 | /* |
| @@ -54,6 +54,8 @@ struct device; · 53 unmodified lines | |||
| 54 | * for dequeue. | 54 | * for dequeue. |
| 55 | */ | 55 | */ |
| 56 | 56 | ||
| 57 | #define DPAA2_IO_ANY_CPU -1 | ||
| 58 | |||
| 57 | /** | 59 | /** |
| 58 | * struct dpaa2_io_desc - The DPIO descriptor | 60 | * struct dpaa2_io_desc - The DPIO descriptor |
| 59 | * @receives_notifications: Use notificaton mode. Non-zero if the DPIO | 61 | * @receives_notifications: Use notificaton mode. Non-zero if the DPIO |
| @@ -91,8 +93,8 @@ irqreturn_t dpaa2_io_irq(struct dpaa2_io *obj); · 31 unmodified lines | |||
| 91 | * @cb: The callback to be invoked when the notification arrives | 93 | * @cb: The callback to be invoked when the notification arrives |
| 92 | * @is_cdan: Zero for FQDAN, non-zero for CDAN | 94 | * @is_cdan: Zero for FQDAN, non-zero for CDAN |
| 93 | * @id: FQID or channel ID, needed for rearm | 95 | * @id: FQID or channel ID, needed for rearm |
| 94 | * @desired_cpu: The cpu on which the notifications will show up. -1 means | 96 | * @desired_cpu: The cpu on which the notifications will show up. Use |
| 95 | * any CPU. | 97 | * DPAA2_IO_ANY_CPU if don't care |
| 96 | * @dpio_id: The dpio index | 98 | * @dpio_id: The dpio index |
| 97 | * @qman64: The 64-bit context value shows up in the FQDAN/CDAN. | 99 | * @qman64: The 64-bit context value shows up in the FQDAN/CDAN. |
| 98 | * @node: The list node | 100 | * @node: The list node |
| @@ -217,13 +217,6 @@ static void fwtty_log_tx_error(struct fwtty_port *port, int rcode) · 216 unmodified lines | |||
| 217 | } | 217 | } |
| 218 | } | 218 | } |
| 219 | 219 | ||
| 220 | static void fwtty_txn_constructor(void *this) | ||
| 221 | { | ||
| 222 | struct fwtty_transaction *txn = this; | ||
| 223 | |||
| 224 | init_timer(&txn->fw_txn.split_timeout_timer); | ||
| 225 | } | ||
| 226 | |||
| 227 | static void fwtty_common_callback(struct fw_card *card, int rcode, | 220 | static void fwtty_common_callback(struct fw_card *card, int rcode, |
| 228 | void *payload, size_t len, void *cb_data) | 221 | void *payload, size_t len, void *cb_data) |
| 229 | { | 222 | { |
| @@ -1806,9 +1799,9 @@ static void fwserial_release_port(struct fwtty_port *port, bool reset) · 1576 unmodified lines | |||
| 1806 | (*port->fwcon_ops->notify)(FWCON_NOTIFY_DETACH, port->con_data); | 1799 | (*port->fwcon_ops->notify)(FWCON_NOTIFY_DETACH, port->con_data); |
| 1807 | } | 1800 | } |
| 1808 | 1801 | ||
| 1809 | static void fwserial_plug_timeout(unsigned long data) | 1802 | static void fwserial_plug_timeout(struct timer_list *t) |
| 1810 | { | 1803 | { |
| 1811 | struct fwtty_peer *peer = (struct fwtty_peer *)data; | 1804 | struct fwtty_peer *peer = from_timer(peer, t, timer); |
| 1812 | struct fwtty_port *port; | 1805 | struct fwtty_port *port; |
| 1813 | 1806 | ||
| 1814 | spin_lock_bh(&peer->lock); | 1807 | spin_lock_bh(&peer->lock); |
| @@ -1860,7 +1853,6 @@ static int fwserial_connect_peer(struct fwtty_peer *peer) · 45 unmodified lines | |||
| 1860 | 1853 | ||
| 1861 | fill_plug_req(pkt, peer->port); | 1854 | fill_plug_req(pkt, peer->port); |
| 1862 | 1855 | ||
| 1863 | setup_timer(&peer->timer, fwserial_plug_timeout, (unsigned long)peer); | ||
| 1864 | mod_timer(&peer->timer, jiffies + VIRT_CABLE_PLUG_TIMEOUT); | 1856 | mod_timer(&peer->timer, jiffies + VIRT_CABLE_PLUG_TIMEOUT); |
| 1865 | spin_unlock_bh(&peer->lock); | 1857 | spin_unlock_bh(&peer->lock); |
| 1866 | 1858 | ||
| @@ -2098,7 +2090,7 @@ static int fwserial_add_peer(struct fw_serial *serial, struct fw_unit *unit) · 231 unmodified lines | |||
| 2098 | spin_lock_init(&peer->lock); | 2090 | spin_lock_init(&peer->lock); |
| 2099 | peer->port = NULL; | 2091 | peer->port = NULL; |
| 2100 | 2092 | ||
| 2101 | init_timer(&peer->timer); | 2093 | timer_setup(&peer->timer, fwserial_plug_timeout, 0); |
| 2102 | INIT_WORK(&peer->work, fwserial_peer_workfn); | 2094 | INIT_WORK(&peer->work, fwserial_peer_workfn); |
| 2103 | INIT_DELAYED_WORK(&peer->connect, fwserial_auto_connect); | 2095 | INIT_DELAYED_WORK(&peer->connect, fwserial_auto_connect); |
| 2104 | 2096 | ||
| @@ -2863,7 +2855,7 @@ static int __init fwserial_init(void) · 758 unmodified lines | |||
| 2863 | 2855 | ||
| 2864 | fwtty_txn_cache = kmem_cache_create("fwtty_txn_cache", | 2856 | fwtty_txn_cache = kmem_cache_create("fwtty_txn_cache", |
| 2865 | sizeof(struct fwtty_transaction), | 2857 | sizeof(struct fwtty_transaction), |
| 2866 | 0, 0, fwtty_txn_constructor); | 2858 | 0, 0, NULL); |
| 2867 | if (!fwtty_txn_cache) { | 2859 | if (!fwtty_txn_cache) { |
| 2868 | err = -ENOMEM; | 2860 | err = -ENOMEM; |
| 2869 | goto unregister_loop; | 2861 | goto unregister_loop; |
| @@ -26,6 +26,7 @@ · 25 unmodified lines | |||
| 26 | #include <linux/icmp.h> | 26 | #include <linux/icmp.h> |
| 27 | #include <linux/icmpv6.h> | 27 | #include <linux/icmpv6.h> |
| 28 | #include <linux/uaccess.h> | 28 | #include <linux/uaccess.h> |
| 29 | #include <linux/errno.h> | ||
| 29 | #include <net/ndisc.h> | 30 | #include <net/ndisc.h> |
| 30 | 31 | ||
| 31 | #include "gdm_lte.h" | 32 | #include "gdm_lte.h" |
| @@ -118,6 +119,10 @@ static int gdm_lte_emulate_arp(struct sk_buff *skb_in, u32 nic_type) · 86 unmodified lines | |||
| 118 | void *mac_header_data; | 119 | void *mac_header_data; |
| 119 | u32 mac_header_len; | 120 | u32 mac_header_len; |
| 120 | 121 | ||
| 122 | /* Check for skb->len, discard if empty */ | ||
| 123 | if (skb_in->len == 0) | ||
| 124 | return -ENODATA; | ||
| 125 | |||
| 121 | /* Format the mac header so that it can be put to skb */ | 126 | /* Format the mac header so that it can be put to skb */ |
| 122 | if (ntohs(((struct ethhdr *)skb_in->data)->h_proto) == ETH_P_8021Q) { | 127 | if (ntohs(((struct ethhdr *)skb_in->data)->h_proto) == ETH_P_8021Q) { |
| 123 | memcpy(&vlan_eth, skb_in->data, sizeof(struct vlan_ethhdr)); | 128 | memcpy(&vlan_eth, skb_in->data, sizeof(struct vlan_ethhdr)); |
| @@ -241,13 +246,13 @@ static int gdm_lte_emulate_ndp(struct sk_buff *skb_in, u32 nic_type) · 117 unmodified lines | |||
| 241 | if (ntohs(((struct ethhdr *)skb_in->data)->h_proto) == ETH_P_8021Q) { | 246 | if (ntohs(((struct ethhdr *)skb_in->data)->h_proto) == ETH_P_8021Q) { |
| 242 | memcpy(&vlan_eth, skb_in->data, sizeof(struct vlan_ethhdr)); | 247 | memcpy(&vlan_eth, skb_in->data, sizeof(struct vlan_ethhdr)); |
| 243 | if (ntohs(vlan_eth.h_vlan_encapsulated_proto) != ETH_P_IPV6) | 248 | if (ntohs(vlan_eth.h_vlan_encapsulated_proto) != ETH_P_IPV6) |
| 244 | return -1; | 249 | return -EPROTONOSUPPORT; |
| 245 | mac_header_data = &vlan_eth; | 250 | mac_header_data = &vlan_eth; |
| 246 | mac_header_len = VLAN_ETH_HLEN; | 251 | mac_header_len = VLAN_ETH_HLEN; |
| 247 | } else { | 252 | } else { |
| 248 | memcpy(ð, skb_in->data, sizeof(struct ethhdr)); | 253 | memcpy(ð, skb_in->data, sizeof(struct ethhdr)); |
| 249 | if (ntohs(eth.h_proto) != ETH_P_IPV6) | 254 | if (ntohs(eth.h_proto) != ETH_P_IPV6) |
| 250 | return -1; | 255 | return -EPROTONOSUPPORT; |
| 251 | mac_header_data = ð | 256 | mac_header_data = ð |
| 252 | mac_header_len = ETH_HLEN; | 257 | mac_header_len = ETH_HLEN; |
| 253 | } | 258 | } |
| @@ -255,13 +260,13 @@ static int gdm_lte_emulate_ndp(struct sk_buff *skb_in, u32 nic_type) · 1 unmodified line | |||
| 255 | /* Check if this is IPv6 ICMP packet */ | 260 | /* Check if this is IPv6 ICMP packet */ |
| 256 | ipv6_in = (struct ipv6hdr *)(skb_in->data + mac_header_len); | 261 | ipv6_in = (struct ipv6hdr *)(skb_in->data + mac_header_len); |
| 257 | if (ipv6_in->version != 6 || ipv6_in->nexthdr != IPPROTO_ICMPV6) | 262 | if (ipv6_in->version != 6 || ipv6_in->nexthdr != IPPROTO_ICMPV6) |
| 258 | return -1; | 263 | return -EPROTONOSUPPORT; |
| 259 | 264 | ||
| 260 | /* Check if this is NDP packet */ | 265 | /* Check if this is NDP packet */ |
| 261 | icmp6_in = (struct icmp6hdr *)(skb_in->data + mac_header_len + | 266 | icmp6_in = (struct icmp6hdr *)(skb_in->data + mac_header_len + |
| 262 | sizeof(struct ipv6hdr)); | 267 | sizeof(struct ipv6hdr)); |
| 263 | if (icmp6_in->icmp6_type == NDISC_ROUTER_SOLICITATION) { /* Check RS */ | 268 | if (icmp6_in->icmp6_type == NDISC_ROUTER_SOLICITATION) { /* Check RS */ |
| 264 | return -1; | 269 | return -EPROTONOSUPPORT; |
| 265 | } else if (icmp6_in->icmp6_type == NDISC_NEIGHBOUR_SOLICITATION) { | 270 | } else if (icmp6_in->icmp6_type == NDISC_NEIGHBOUR_SOLICITATION) { |
| 266 | /* Check NS */ | 271 | /* Check NS */ |
| 267 | u8 icmp_na[sizeof(struct icmp6hdr) + | 272 | u8 icmp_na[sizeof(struct icmp6hdr) + |
| @@ -305,7 +310,7 @@ static int gdm_lte_emulate_ndp(struct sk_buff *skb_in, u32 nic_type) · 37 unmodified lines | |||
| 305 | icmp6_out.icmp6_cksum = icmp6_checksum(&ipv6_out, | 310 | icmp6_out.icmp6_cksum = icmp6_checksum(&ipv6_out, |
| 306 | (u16 *)icmp_na, sizeof(icmp_na)); | 311 | (u16 *)icmp_na, sizeof(icmp_na)); |
| 307 | } else { | 312 | } else { |
| 308 | return -1; | 313 | return -EINVAL; |
| 309 | } | 314 | } |
| 310 | 315 | ||
| 311 | /* Fill the destination mac with source mac of the received packet */ | 316 | /* Fill the destination mac with source mac of the received packet */ |
| @@ -412,7 +417,7 @@ static int gdm_lte_tx(struct sk_buff *skb, struct net_device *dev) · 100 unmodified lines | |||
| 412 | nic_type = gdm_lte_tx_nic_type(dev, skb); | 417 | nic_type = gdm_lte_tx_nic_type(dev, skb); |
| 413 | if (nic_type == 0) { | 418 | if (nic_type == 0) { |
| 414 | netdev_err(dev, "tx - invalid nic_type\n"); | 419 | netdev_err(dev, "tx - invalid nic_type\n"); |
| 415 | return -1; | 420 | return -EMEDIUMTYPE; |
| 416 | } | 421 | } |
| 417 | 422 | ||
| 418 | if (nic_type & NIC_TYPE_ARP) { | 423 | if (nic_type & NIC_TYPE_ARP) { |
| @@ -539,7 +544,7 @@ int gdm_lte_event_init(void) · 120 unmodified lines | |||
| 539 | } | 544 | } |
| 540 | 545 | ||
| 541 | pr_err("event init failed\n"); | 546 | pr_err("event init failed\n"); |
| 542 | return -1; | 547 | return -ENODATA; |
| 543 | } | 548 | } |
| 544 | 549 | ||
| 545 | void gdm_lte_event_exit(void) | 550 | void gdm_lte_event_exit(void) |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) | ||
| 1 | /* | 2 | /* |
| 2 | * Sample code to test CAP protocol | 3 | * Sample code to test CAP protocol |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) | ||
| 1 | /* | 2 | /* |
| 2 | * Sample code to test firmware-management protocol | 3 | * Sample code to test firmware-management protocol |
| 3 | * | 4 | * |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Arche Platform driver to control APB. | 3 | * Arche Platform driver to control APB. |
| 3 | * | 4 | * |
| 4 | * Copyright 2014-2015 Google Inc. | 5 | * Copyright 2014-2015 Google Inc. |
| 5 | * Copyright 2014-2015 Linaro Ltd. | 6 | * Copyright 2014-2015 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/clk.h> | 9 | #include <linux/clk.h> |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Arche Platform driver to enable Unipro link. | 3 | * Arche Platform driver to enable Unipro link. |
| 3 | * | 4 | * |
| 4 | * Copyright 2014-2015 Google Inc. | 5 | * Copyright 2014-2015 Google Inc. |
| 5 | * Copyright 2014-2015 Linaro Ltd. | 6 | * Copyright 2014-2015 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/clk.h> | 9 | #include <linux/clk.h> |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Arche Platform driver to enable Unipro link. | 3 | * Arche Platform driver to enable Unipro link. |
| 3 | * | 4 | * |
| 4 | * Copyright 2015-2016 Google Inc. | 5 | * Copyright 2015-2016 Google Inc. |
| 5 | * Copyright 2015-2016 Linaro Ltd. | 6 | * Copyright 2015-2016 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #ifndef __ARCHE_PLATFORM_H | 9 | #ifndef __ARCHE_PLATFORM_H |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) | ||
| 1 | /* | 2 | /* |
| 2 | * This file is provided under a dual BSD/GPLv2 license. When using or | 3 | * This file is provided under a dual BSD/GPLv2 license. When using or |
| 3 | * redistributing this file, you may do so under either license. | 4 | * redistributing this file, you may do so under either license. |
| @@ -1,9 +1,8 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus Audio Device Class Protocol helpers | 3 | * Greybus Audio Device Class Protocol helpers |
| 3 | * | 4 | * |
| 4 | * Copyright 2015-2016 Google Inc. | 5 | * Copyright 2015-2016 Google Inc. |
| 5 | * | ||
| 6 | * Released under the GPLv2 only. | ||
| 7 | */ | 6 | */ |
| 8 | 7 | ||
| 9 | #include "greybus.h" | 8 | #include "greybus.h" |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: BSD-3-Clause | ||
| 1 | /** | 2 | /** |
| 2 | * Copyright (c) 2015-2016 Google Inc. | 3 | * Copyright (c) 2015-2016 Google Inc. |
| 3 | * All rights reserved. | 4 | * All rights reserved. |
| @@ -1,9 +1,8 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * APBridge ALSA SoC dummy codec driver | 3 | * APBridge ALSA SoC dummy codec driver |
| 3 | * Copyright 2016 Google Inc. | 4 | * Copyright 2016 Google Inc. |
| 4 | * Copyright 2016 Linaro Ltd. | 5 | * Copyright 2016 Linaro Ltd. |
| 5 | * | ||
| 6 | * Released under the GPLv2 only. | ||
| 7 | */ | 6 | */ |
| 8 | #include <linux/kernel.h> | 7 | #include <linux/kernel.h> |
| 9 | #include <linux/module.h> | 8 | #include <linux/module.h> |
| @@ -1,9 +1,8 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus audio driver | 3 | * Greybus audio driver |
| 3 | * Copyright 2015 Google Inc. | 4 | * Copyright 2015 Google Inc. |
| 4 | * Copyright 2015 Linaro Ltd. | 5 | * Copyright 2015 Linaro Ltd. |
| 5 | * | ||
| 6 | * Released under the GPLv2 only. | ||
| 7 | */ | 6 | */ |
| 8 | 7 | ||
| 9 | #ifndef __LINUX_GBAUDIO_CODEC_H | 8 | #ifndef __LINUX_GBAUDIO_CODEC_H |
| @@ -1,9 +1,8 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus Audio Device Class Protocol helpers | 3 | * Greybus Audio Device Class Protocol helpers |
| 3 | * | 4 | * |
| 4 | * Copyright 2015-2016 Google Inc. | 5 | * Copyright 2015-2016 Google Inc. |
| 5 | * | ||
| 6 | * Released under the GPLv2 only. | ||
| 7 | */ | 6 | */ |
| 8 | 7 | ||
| 9 | #include "greybus.h" | 8 | #include "greybus.h" |
| @@ -1,16 +1,15 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus operations | 3 | * Greybus operations |
| 3 | * | 4 | * |
| 4 | * Copyright 2015-2016 Google Inc. | 5 | * Copyright 2015-2016 Google Inc. |
| 5 | * | ||
| 6 | * Released under the GPLv2 only. | ||
| 7 | */ | 6 | */ |
| 8 | 7 | ||
| 9 | #include <linux/string.h> | 8 | #include <linux/string.h> |
| 10 | #include <linux/sysfs.h> | 9 | #include <linux/sysfs.h> |
| 11 | #include <linux/module.h> | 10 | #include <linux/module.h> |
| 12 | #include <linux/init.h> | 11 | #include <linux/init.h> |
| 13 | #include <linux/rwlock.h> | 12 | #include <linux/spinlock.h> |
| 14 | #include <linux/idr.h> | 13 | #include <linux/idr.h> |
| 15 | 14 | ||
| 16 | #include "audio_manager.h" | 15 | #include "audio_manager.h" |
| @@ -1,9 +1,8 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus operations | 3 | * Greybus operations |
| 3 | * | 4 | * |
| 4 | * Copyright 2015-2016 Google Inc. | 5 | * Copyright 2015-2016 Google Inc. |
| 5 | * | ||
| 6 | * Released under the GPLv2 only. | ||
| 7 | */ | 6 | */ |
| 8 | 7 | ||
| 9 | #ifndef _GB_AUDIO_MANAGER_H_ | 8 | #ifndef _GB_AUDIO_MANAGER_H_ |
| @@ -1,9 +1,8 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus operations | 3 | * Greybus operations |
| 3 | * | 4 | * |
| 4 | * Copyright 2015-2016 Google Inc. | 5 | * Copyright 2015-2016 Google Inc. |
| 5 | * | ||
| 6 | * Released under the GPLv2 only. | ||
| 7 | */ | 6 | */ |
| 8 | 7 | ||
| 9 | #include <linux/slab.h> | 8 | #include <linux/slab.h> |
| @@ -1,9 +1,8 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus operations | 3 | * Greybus operations |
| 3 | * | 4 | * |
| 4 | * Copyright 2015-2016 Google Inc. | 5 | * Copyright 2015-2016 Google Inc. |
| 5 | * | ||
| 6 | * Released under the GPLv2 only. | ||
| 7 | */ | 6 | */ |
| 8 | 7 | ||
| 9 | #ifndef _GB_AUDIO_MANAGER_PRIVATE_H_ | 8 | #ifndef _GB_AUDIO_MANAGER_PRIVATE_H_ |
| @@ -1,9 +1,8 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus operations | 3 | * Greybus operations |
| 3 | * | 4 | * |
| 4 | * Copyright 2015-2016 Google Inc. | 5 | * Copyright 2015-2016 Google Inc. |
| 5 | * | ||
| 6 | * Released under the GPLv2 only. | ||
| 7 | */ | 6 | */ |
| 8 | 7 | ||
| 9 | #include <linux/string.h> | 8 | #include <linux/string.h> |
| @@ -1,9 +1,8 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus audio driver | 3 | * Greybus audio driver |
| 3 | * Copyright 2015 Google Inc. | 4 | * Copyright 2015 Google Inc. |
| 4 | * Copyright 2015 Linaro Ltd. | 5 | * Copyright 2015 Linaro Ltd. |
| 5 | * | ||
| 6 | * Released under the GPLv2 only. | ||
| 7 | */ | 6 | */ |
| 8 | #include <linux/kernel.h> | 7 | #include <linux/kernel.h> |
| 9 | #include <linux/module.h> | 8 | #include <linux/module.h> |
| @@ -1,9 +1,8 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus audio driver | 3 | * Greybus audio driver |
| 3 | * Copyright 2015-2016 Google Inc. | 4 | * Copyright 2015-2016 Google Inc. |
| 4 | * Copyright 2015-2016 Linaro Ltd. | 5 | * Copyright 2015-2016 Linaro Ltd. |
| 5 | * | ||
| 6 | * Released under the GPLv2 only. | ||
| 7 | */ | 6 | */ |
| 8 | 7 | ||
| 9 | #include "audio_codec.h" | 8 | #include "audio_codec.h" |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus Component Authentication Protocol (CAP) Driver. | 3 | * Greybus Component Authentication Protocol (CAP) Driver. |
| 3 | * | 4 | * |
| 4 | * Copyright 2016 Google Inc. | 5 | * Copyright 2016 Google Inc. |
| 5 | * Copyright 2016 Linaro Ltd. | 6 | * Copyright 2016 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include "greybus.h" | 9 | #include "greybus.h" |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * BOOTROM Greybus driver. | 3 | * BOOTROM Greybus driver. |
| 3 | * | 4 | * |
| 4 | * Copyright 2016 Google Inc. | 5 | * Copyright 2016 Google Inc. |
| 5 | * Copyright 2016 Linaro Ltd. | 6 | * Copyright 2016 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/firmware.h> | 9 | #include <linux/firmware.h> |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus bundles | 3 | * Greybus bundles |
| 3 | * | 4 | * |
| 4 | * Copyright 2014-2015 Google Inc. | 5 | * Copyright 2014-2015 Google Inc. |
| 5 | * Copyright 2014-2015 Linaro Ltd. | 6 | * Copyright 2014-2015 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include "greybus.h" | 9 | #include "greybus.h" |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus bundles | 3 | * Greybus bundles |
| 3 | * | 4 | * |
| 4 | * Copyright 2014 Google Inc. | 5 | * Copyright 2014 Google Inc. |
| 5 | * Copyright 2014 Linaro Ltd. | 6 | * Copyright 2014 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #ifndef __BUNDLE_H | 9 | #ifndef __BUNDLE_H |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus Camera protocol driver. | 3 | * Greybus Camera protocol driver. |
| 3 | * | 4 | * |
| 4 | * Copyright 2015 Google Inc. | 5 | * Copyright 2015 Google Inc. |
| 5 | * Copyright 2015 Linaro Ltd. | 6 | * Copyright 2015 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/debugfs.h> | 9 | #include <linux/debugfs.h> |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus connections | 3 | * Greybus connections |
| 3 | * | 4 | * |
| 4 | * Copyright 2014 Google Inc. | 5 | * Copyright 2014 Google Inc. |
| 5 | * Copyright 2014 Linaro Ltd. | 6 | * Copyright 2014 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/workqueue.h> | 9 | #include <linux/workqueue.h> |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus connections | 3 | * Greybus connections |
| 3 | * | 4 | * |
| 4 | * Copyright 2014 Google Inc. | 5 | * Copyright 2014 Google Inc. |
| 5 | * Copyright 2014 Linaro Ltd. | 6 | * Copyright 2014 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #ifndef __CONNECTION_H | 9 | #ifndef __CONNECTION_H |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus CPort control protocol. | 3 | * Greybus CPort control protocol. |
| 3 | * | 4 | * |
| 4 | * Copyright 2015 Google Inc. | 5 | * Copyright 2015 Google Inc. |
| 5 | * Copyright 2015 Linaro Ltd. | 6 | * Copyright 2015 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/kernel.h> | 9 | #include <linux/kernel.h> |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus CPort control protocol | 3 | * Greybus CPort control protocol |
| 3 | * | 4 | * |
| 4 | * Copyright 2015 Google Inc. | 5 | * Copyright 2015 Google Inc. |
| 5 | * Copyright 2015 Linaro Ltd. | 6 | * Copyright 2015 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #ifndef __CONTROL_H | 9 | #ifndef __CONTROL_H |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus "Core" | 3 | * Greybus "Core" |
| 3 | * | 4 | * |
| 4 | * Copyright 2014-2015 Google Inc. | 5 | * Copyright 2014-2015 Google Inc. |
| 5 | * Copyright 2014-2015 Linaro Ltd. | 6 | * Copyright 2014-2015 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | 9 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus debugfs code | 3 | * Greybus debugfs code |
| 3 | * | 4 | * |
| 4 | * Copyright 2014 Google Inc. | 5 | * Copyright 2014 Google Inc. |
| 5 | * Copyright 2014 Linaro Ltd. | 6 | * Copyright 2014 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/debugfs.h> | 9 | #include <linux/debugfs.h> |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus "AP" USB driver for "ES2" controller chips | 3 | * Greybus "AP" USB driver for "ES2" controller chips |
| 3 | * | 4 | * |
| 4 | * Copyright 2014-2015 Google Inc. | 5 | * Copyright 2014-2015 Google Inc. |
| 5 | * Copyright 2014-2015 Linaro Ltd. | 6 | * Copyright 2014-2015 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | #include <linux/kthread.h> | 8 | #include <linux/kthread.h> |
| 10 | #include <linux/sizes.h> | 9 | #include <linux/sizes.h> |
| @@ -761,6 +760,7 @@ static int check_urb_status(struct urb *urb) · 750 unmodified lines | |||
| 761 | case -EOVERFLOW: | 760 | case -EOVERFLOW: |
| 762 | dev_err(dev, "%s: overflow actual length is %d\n", | 761 | dev_err(dev, "%s: overflow actual length is %d\n", |
| 763 | __func__, urb->actual_length); | 762 | __func__, urb->actual_length); |
| 763 | /* fall through */ | ||
| 764 | case -ECONNRESET: | 764 | case -ECONNRESET: |
| 765 | case -ENOENT: | 765 | case -ENOENT: |
| 766 | case -ESHUTDOWN: | 766 | case -ESHUTDOWN: |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus Firmware Management Header | 3 | * Greybus Firmware Management Header |
| 3 | * | 4 | * |
| 4 | * Copyright 2016 Google Inc. | 5 | * Copyright 2016 Google Inc. |
| 5 | * Copyright 2016 Linaro Ltd. | 6 | * Copyright 2016 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #ifndef __FIRMWARE_H | 9 | #ifndef __FIRMWARE_H |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus Firmware Core Bundle Driver. | 3 | * Greybus Firmware Core Bundle Driver. |
| 3 | * | 4 | * |
| 4 | * Copyright 2016 Google Inc. | 5 | * Copyright 2016 Google Inc. |
| 5 | * Copyright 2016 Linaro Ltd. | 6 | * Copyright 2016 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | 8 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 10 | 9 | ||
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus Firmware Download Protocol Driver. | 3 | * Greybus Firmware Download Protocol Driver. |
| 3 | * | 4 | * |
| 4 | * Copyright 2016 Google Inc. | 5 | * Copyright 2016 Google Inc. |
| 5 | * Copyright 2016 Linaro Ltd. | 6 | * Copyright 2016 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/firmware.h> | 9 | #include <linux/firmware.h> |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus Firmware Management Protocol Driver. | 3 | * Greybus Firmware Management Protocol Driver. |
| 3 | * | 4 | * |
| 4 | * Copyright 2016 Google Inc. | 5 | * Copyright 2016 Google Inc. |
| 5 | * Copyright 2016 Linaro Ltd. | 6 | * Copyright 2016 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/cdev.h> | 9 | #include <linux/cdev.h> |
| @@ -1,9 +1,8 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus Camera protocol driver. | 3 | * Greybus Camera protocol driver. |
| 3 | * | 4 | * |
| 4 | * Copyright 2015 Google Inc. | 5 | * Copyright 2015 Google Inc. |
| 5 | * | ||
| 6 | * Released under the GPLv2 only. | ||
| 7 | */ | 6 | */ |
| 8 | #ifndef __GB_CAMERA_H | 7 | #ifndef __GB_CAMERA_H |
| 9 | #define __GB_CAMERA_H | 8 | #define __GB_CAMERA_H |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus Bridged-Phy Bus driver | 3 | * Greybus Bridged-Phy Bus driver |
| 3 | * | 4 | * |
| 4 | * Copyright 2014 Google Inc. | 5 | * Copyright 2014 Google Inc. |
| 5 | * Copyright 2014 Linaro Ltd. | 6 | * Copyright 2014 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | 9 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| @@ -1,9 +1,8 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus Bridged-Phy Bus driver | 3 | * Greybus Bridged-Phy Bus driver |
| 3 | * | 4 | * |
| 4 | * Copyright 2016 Google Inc. | 5 | * Copyright 2016 Google Inc. |
| 5 | * | ||
| 6 | * Released under the GPLv2 only. | ||
| 7 | */ | 6 | */ |
| 8 | 7 | ||
| 9 | #ifndef __GBPHY_H | 8 | #ifndef __GBPHY_H |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPIO Greybus driver. | 3 | * GPIO Greybus driver. |
| 3 | * | 4 | * |
| 4 | * Copyright 2014 Google Inc. | 5 | * Copyright 2014 Google Inc. |
| 5 | * Copyright 2014 Linaro Ltd. | 6 | * Copyright 2014 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/kernel.h> | 9 | #include <linux/kernel.h> |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus driver and device API | 3 | * Greybus driver and device API |
| 3 | * | 4 | * |
| 4 | * Copyright 2014-2015 Google Inc. | 5 | * Copyright 2014-2015 Google Inc. |
| 5 | * Copyright 2014-2015 Linaro Ltd. | 6 | * Copyright 2014-2015 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #ifndef __LINUX_GREYBUS_H | 9 | #ifndef __LINUX_GREYBUS_H |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus Component Authentication User Header | 3 | * Greybus Component Authentication User Header |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus Firmware Management User Header | 3 | * Greybus Firmware Management User Header |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus manifest definition | 3 | * Greybus manifest definition |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) | ||
| 1 | /* | 2 | /* |
| 2 | * This file is provided under a dual BSD/GPLv2 license. When using or | 3 | * This file is provided under a dual BSD/GPLv2 license. When using or |
| 3 | * redistributing this file, you may do so under either license. | 4 | * redistributing this file, you may do so under either license. |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus driver and device API | 3 | * Greybus driver and device API |
| 3 | * | 4 | * |
| 4 | * Copyright 2015 Google Inc. | 5 | * Copyright 2015 Google Inc. |
| 5 | * Copyright 2015 Linaro Ltd. | 6 | * Copyright 2015 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | #undef TRACE_SYSTEM | 8 | #undef TRACE_SYSTEM |
| 10 | #define TRACE_SYSTEM greybus | 9 | #define TRACE_SYSTEM greybus |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus Host Device | 3 | * Greybus Host Device |
| 3 | * | 4 | * |
| 4 | * Copyright 2014-2015 Google Inc. | 5 | * Copyright 2014-2015 Google Inc. |
| 5 | * Copyright 2014-2015 Linaro Ltd. | 6 | * Copyright 2014-2015 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/kernel.h> | 9 | #include <linux/kernel.h> |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus Host Device | 3 | * Greybus Host Device |
| 3 | * | 4 | * |
| 4 | * Copyright 2014-2015 Google Inc. | 5 | * Copyright 2014-2015 Google Inc. |
| 5 | * Copyright 2014-2015 Linaro Ltd. | 6 | * Copyright 2014-2015 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #ifndef __HD_H | 9 | #ifndef __HD_H |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * HID class driver for the Greybus. | 3 | * HID class driver for the Greybus. |
| 3 | * | 4 | * |
| 4 | * Copyright 2014 Google Inc. | 5 | * Copyright 2014 Google Inc. |
| 5 | * Copyright 2014 Linaro Ltd. | 6 | * Copyright 2014 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/bitops.h> | 9 | #include <linux/bitops.h> |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * I2C bridge driver for the Greybus "generic" I2C module. | 3 | * I2C bridge driver for the Greybus "generic" I2C module. |
| 3 | * | 4 | * |
| 4 | * Copyright 2014 Google Inc. | 5 | * Copyright 2014 Google Inc. |
| 5 | * Copyright 2014 Linaro Ltd. | 6 | * Copyright 2014 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/kernel.h> | 9 | #include <linux/kernel.h> |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus interface code | 3 | * Greybus interface code |
| 3 | * | 4 | * |
| 4 | * Copyright 2014 Google Inc. | 5 | * Copyright 2014 Google Inc. |
| 5 | * Copyright 2014 Linaro Ltd. | 6 | * Copyright 2014 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/delay.h> | 9 | #include <linux/delay.h> |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus Interface Block code | 3 | * Greybus Interface Block code |
| 3 | * | 4 | * |
| 4 | * Copyright 2014 Google Inc. | 5 | * Copyright 2014 Google Inc. |
| 5 | * Copyright 2014 Linaro Ltd. | 6 | * Copyright 2014 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #ifndef __INTERFACE_H | 9 | #ifndef __INTERFACE_H |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus Lights protocol driver. | 3 | * Greybus Lights protocol driver. |
| 3 | * | 4 | * |
| 4 | * Copyright 2015 Google Inc. | 5 | * Copyright 2015 Google Inc. |
| 5 | * Copyright 2015 Linaro Ltd. | 6 | * Copyright 2015 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/kernel.h> | 9 | #include <linux/kernel.h> |
| @@ -925,6 +924,8 @@ static void __gb_lights_led_unregister(struct gb_channel *channel) · 914 unmodified lines | |||
| 925 | return; | 924 | return; |
| 926 | 925 | ||
| 927 | led_classdev_unregister(cdev); | 926 | led_classdev_unregister(cdev); |
| 927 | kfree(cdev->name); | ||
| 928 | cdev->name = NULL; | ||
| 928 | channel->led = NULL; | 929 | channel->led = NULL; |
| 929 | } | 930 | } |
| 930 | 931 | ||
| @@ -998,11 +999,7 @@ static int gb_lights_channel_config(struct gb_light *light, · 67 unmodified lines | |||
| 998 | 999 | ||
| 999 | light->has_flash = true; | 1000 | light->has_flash = true; |
| 1000 | 1001 | ||
| 1001 | ret = gb_lights_channel_flash_config(channel); | 1002 | return gb_lights_channel_flash_config(channel); |
| 1002 | if (ret < 0) | ||
| 1003 | return ret; | ||
| 1004 | |||
| 1005 | return ret; | ||
| 1006 | } | 1003 | } |
| 1007 | 1004 | ||
| 1008 | static int gb_lights_light_config(struct gb_lights *glights, u8 id) | 1005 | static int gb_lights_light_config(struct gb_lights *glights, u8 id) |
| @@ -1,9 +1,8 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus driver for the log protocol | 3 | * Greybus driver for the log protocol |
| 3 | * | 4 | * |
| 4 | * Copyright 2016 Google Inc. | 5 | * Copyright 2016 Google Inc. |
| 5 | * | ||
| 6 | * Released under the GPLv2 only. | ||
| 7 | */ | 6 | */ |
| 8 | #include <linux/kernel.h> | 7 | #include <linux/kernel.h> |
| 9 | #include <linux/module.h> | 8 | #include <linux/module.h> |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Loopback bridge driver for the Greybus loopback module. | 3 | * Loopback bridge driver for the Greybus loopback module. |
| 3 | * | 4 | * |
| 4 | * Copyright 2014 Google Inc. | 5 | * Copyright 2014 Google Inc. |
| 5 | * Copyright 2014 Linaro Ltd. | 6 | * Copyright 2014 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | 9 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| @@ -58,12 +57,7 @@ static struct gb_loopback_device gb_dev; · 47 unmodified lines | |||
| 58 | struct gb_loopback_async_operation { | 57 | struct gb_loopback_async_operation { |
| 59 | struct gb_loopback *gb; | 58 | struct gb_loopback *gb; |
| 60 | struct gb_operation *operation; | 59 | struct gb_operation *operation; |
| 61 | struct timeval ts; | 60 | ktime_t ts; |
| 62 | struct timer_list timer; | ||
| 63 | struct list_head entry; | ||
| 64 | struct work_struct work; | ||
| 65 | struct kref kref; | ||
| 66 | bool pending; | ||
| 67 | int (*completion)(struct gb_loopback_async_operation *op_async); | 61 | int (*completion)(struct gb_loopback_async_operation *op_async); |
| 68 | }; | 62 | }; |
| 69 | 63 | ||
| @@ -72,7 +66,6 @@ struct gb_loopback { · 2 unmodified lines | |||
| 72 | 66 | ||
| 73 | struct dentry *file; | 67 | struct dentry *file; |
| 74 | struct kfifo kfifo_lat; | 68 | struct kfifo kfifo_lat; |
| 75 | struct kfifo kfifo_ts; | ||
| 76 | struct mutex mutex; | 69 | struct mutex mutex; |
| 77 | struct task_struct *task; | 70 | struct task_struct *task; |
| 78 | struct list_head entry; | 71 | struct list_head entry; |
| @@ -82,7 +75,7 @@ struct gb_loopback { · 3 unmodified lines | |||
| 82 | atomic_t outstanding_operations; | 75 | atomic_t outstanding_operations; |
| 83 | 76 | ||
| 84 | /* Per connection stats */ | 77 | /* Per connection stats */ |
| 85 | struct timeval ts; | 78 | ktime_t ts; |
| 86 | struct gb_loopback_stats latency; | 79 | struct gb_loopback_stats latency; |
| 87 | struct gb_loopback_stats throughput; | 80 | struct gb_loopback_stats throughput; |
| 88 | struct gb_loopback_stats requests_per_second; | 81 | struct gb_loopback_stats requests_per_second; |
| @@ -262,7 +255,6 @@ static void gb_loopback_check_attr(struct gb_loopback *gb) · 173 unmodified lines | |||
| 262 | gb->iteration_max, kfifo_depth); | 255 | gb->iteration_max, kfifo_depth); |
| 263 | } | 256 | } |
| 264 | kfifo_reset_out(&gb->kfifo_lat); | 257 | kfifo_reset_out(&gb->kfifo_lat); |
| 265 | kfifo_reset_out(&gb->kfifo_ts); | ||
| 266 | 258 | ||
| 267 | switch (gb->type) { | 259 | switch (gb->type) { |
| 268 | case GB_LOOPBACK_TYPE_PING: | 260 | case GB_LOOPBACK_TYPE_PING: |
| @@ -377,21 +369,9 @@ static u64 __gb_loopback_calc_latency(u64 t1, u64 t2) · 108 unmodified lines | |||
| 377 | return NSEC_PER_DAY - t2 + t1; | 369 | return NSEC_PER_DAY - t2 + t1; |
| 378 | } | 370 | } |
| 379 | 371 | ||
| 380 | static u64 gb_loopback_calc_latency(struct timeval *ts, struct timeval *te) | 372 | static u64 gb_loopback_calc_latency(ktime_t ts, ktime_t te) |
| 381 | { | ||
| 382 | u64 t1, t2; | ||
| 383 | |||
| 384 | t1 = timeval_to_ns(ts); | ||
| 385 | t2 = timeval_to_ns(te); | ||
| 386 | |||
| 387 | return __gb_loopback_calc_latency(t1, t2); | ||
| 388 | } | ||
| 389 | |||
| 390 | static void gb_loopback_push_latency_ts(struct gb_loopback *gb, | ||
| 391 | struct timeval *ts, struct timeval *te) | ||
| 392 | { | 373 | { |
| 393 | kfifo_in(&gb->kfifo_ts, (unsigned char *)ts, sizeof(*ts)); | 374 | return __gb_loopback_calc_latency(ktime_to_ns(ts), ktime_to_ns(te)); |
| 394 | kfifo_in(&gb->kfifo_ts, (unsigned char *)te, sizeof(*te)); | ||
| 395 | } | 375 | } |
| 396 | 376 | ||
| 397 | static int gb_loopback_operation_sync(struct gb_loopback *gb, int type, | 377 | static int gb_loopback_operation_sync(struct gb_loopback *gb, int type, |
| @@ -399,10 +379,10 @@ static int gb_loopback_operation_sync(struct gb_loopback *gb, int type, · 1 unmodified line | |||
| 399 | void *response, int response_size) | 379 | void *response, int response_size) |
| 400 | { | 380 | { |
| 401 | struct gb_operation *operation; | 381 | struct gb_operation *operation; |
| 402 | struct timeval ts, te; | 382 | ktime_t ts, te; |
| 403 | int ret; | 383 | int ret; |
| 404 | 384 | ||
| 405 | do_gettimeofday(&ts); | 385 | ts = ktime_get(); |
| 406 | operation = gb_operation_create(gb->connection, type, request_size, | 386 | operation = gb_operation_create(gb->connection, type, request_size, |
| 407 | response_size, GFP_KERNEL); | 387 | response_size, GFP_KERNEL); |
| 408 | if (!operation) | 388 | if (!operation) |
| @@ -430,11 +410,10 @@ static int gb_loopback_operation_sync(struct gb_loopback *gb, int type, · 21 unmodified lines | |||
| 430 | } | 410 | } |
| 431 | } | 411 | } |
| 432 | 412 | ||
| 433 | do_gettimeofday(&te); | 413 | te = ktime_get(); |
| 434 | 414 | ||
| 435 | /* Calculate the total time the message took */ | 415 | /* Calculate the total time the message took */ |
| 436 | gb_loopback_push_latency_ts(gb, &ts, &te); | 416 | gb->elapsed_nsecs = gb_loopback_calc_latency(ts, te); |
| 437 | gb->elapsed_nsecs = gb_loopback_calc_latency(&ts, &te); | ||
| 438 | 417 | ||
| 439 | out_put_operation: | 418 | out_put_operation: |
| 440 | gb_operation_put(operation); | 419 | gb_operation_put(operation); |
| @@ -442,56 +421,6 @@ out_put_operation: · 1 unmodified line | |||
| 442 | return ret; | 421 | return ret; |
| 443 | } | 422 | } |
| 444 | 423 | ||
| 445 | static void __gb_loopback_async_operation_destroy(struct kref *kref) | ||
| 446 | { | ||
| 447 | struct gb_loopback_async_operation *op_async; | ||
| 448 | |||
| 449 | op_async = container_of(kref, struct gb_loopback_async_operation, kref); | ||
| 450 | |||
| 451 | list_del(&op_async->entry); | ||
| 452 | if (op_async->operation) | ||
| 453 | gb_operation_put(op_async->operation); | ||
| 454 | atomic_dec(&op_async->gb->outstanding_operations); | ||
| 455 | wake_up(&op_async->gb->wq_completion); | ||
| 456 | kfree(op_async); | ||
| 457 | } | ||
| 458 | |||
| 459 | static void gb_loopback_async_operation_get(struct gb_loopback_async_operation | ||
| 460 | *op_async) | ||
| 461 | { | ||
| 462 | kref_get(&op_async->kref); | ||
| 463 | } | ||
| 464 | |||
| 465 | static void gb_loopback_async_operation_put(struct gb_loopback_async_operation | ||
| 466 | *op_async) | ||
| 467 | { | ||
| 468 | unsigned long flags; | ||
| 469 | |||
| 470 | spin_lock_irqsave(&gb_dev.lock, flags); | ||
| 471 | kref_put(&op_async->kref, __gb_loopback_async_operation_destroy); | ||
| 472 | spin_unlock_irqrestore(&gb_dev.lock, flags); | ||
| 473 | } | ||
| 474 | |||
| 475 | static struct gb_loopback_async_operation * | ||
| 476 | gb_loopback_operation_find(u16 id) | ||
| 477 | { | ||
| 478 | struct gb_loopback_async_operation *op_async; | ||
| 479 | bool found = false; | ||
| 480 | unsigned long flags; | ||
| 481 | |||
| 482 | spin_lock_irqsave(&gb_dev.lock, flags); | ||
| 483 | list_for_each_entry(op_async, &gb_dev.list_op_async, entry) { | ||
| 484 | if (op_async->operation->id == id) { | ||
| 485 | gb_loopback_async_operation_get(op_async); | ||
| 486 | found = true; | ||
| 487 | break; | ||
| 488 | } | ||
| 489 | } | ||
| 490 | spin_unlock_irqrestore(&gb_dev.lock, flags); | ||
| 491 | |||
| 492 | return found ? op_async : NULL; | ||
| 493 | } | ||
| 494 | |||
| 495 | static void gb_loopback_async_wait_all(struct gb_loopback *gb) | 424 | static void gb_loopback_async_wait_all(struct gb_loopback *gb) |
| 496 | { | 425 | { |
| 497 | wait_event(gb->wq_completion, | 426 | wait_event(gb->wq_completion, |
| @@ -502,87 +431,42 @@ static void gb_loopback_async_operation_callback(struct gb_operation *operation) · 4 unmodified lines | |||
| 502 | { | 431 | { |
| 503 | struct gb_loopback_async_operation *op_async; | 432 | struct gb_loopback_async_operation *op_async; |
| 504 | struct gb_loopback *gb; | 433 | struct gb_loopback *gb; |
| 505 | struct timeval te; | 434 | ktime_t te; |
| 506 | bool err = false; | 435 | int result; |
| 507 | |||
| 508 | do_gettimeofday(&te); | ||
| 509 | op_async = gb_loopback_operation_find(operation->id); | ||
| 510 | if (!op_async) | ||
| 511 | return; | ||
| 512 | 436 | ||
| 437 | te = ktime_get(); | ||
| 438 | result = gb_operation_result(operation); | ||
| 439 | op_async = gb_operation_get_data(operation); | ||
| 513 | gb = op_async->gb; | 440 | gb = op_async->gb; |
| 441 | |||
| 514 | mutex_lock(&gb->mutex); | 442 | mutex_lock(&gb->mutex); |
| 515 | 443 | ||
| 516 | if (!op_async->pending || gb_operation_result(operation)) { | 444 | if (!result && op_async->completion) |
| 517 | err = true; | 445 | result = op_async->completion(op_async); |
| 446 | |||
| 447 | if (!result) { | ||
| 448 | gb->elapsed_nsecs = gb_loopback_calc_latency(op_async->ts, te); | ||
| 518 | } else { | 449 | } else { |
| 519 | if (op_async->completion) | 450 | gb->error++; |
| 520 | if (op_async->completion(op_async)) | 451 | if (result == -ETIMEDOUT) |
| 521 | err = true; | 452 | gb->requests_timedout++; |
| 522 | } | 453 | } |
| 523 | 454 | ||
| 524 | if (!err) { | 455 | gb->iteration_count++; |
| 525 | gb_loopback_push_latency_ts(gb, &op_async->ts, &te); | 456 | gb_loopback_calculate_stats(gb, result); |
| 526 | gb->elapsed_nsecs = gb_loopback_calc_latency(&op_async->ts, | ||
| 527 | &te); | ||
| 528 | } | ||
| 529 | 457 | ||
| 530 | if (op_async->pending) { | ||
| 531 | if (err) | ||
| 532 | gb->error++; | ||
| 533 | gb->iteration_count++; | ||
| 534 | op_async->pending = false; | ||
| 535 | del_timer_sync(&op_async->timer); | ||
| 536 | gb_loopback_async_operation_put(op_async); | ||
| 537 | gb_loopback_calculate_stats(gb, err); | ||
| 538 | } | ||
| 539 | mutex_unlock(&gb->mutex); | 458 | mutex_unlock(&gb->mutex); |
| 540 | 459 | ||
| 541 | dev_dbg(&gb->connection->bundle->dev, "complete operation %d\n", | 460 | dev_dbg(&gb->connection->bundle->dev, "complete operation %d\n", |
| 542 | operation->id); | 461 | operation->id); |
| 543 | 462 | ||
| 544 | gb_loopback_async_operation_put(op_async); | 463 | /* Wake up waiters */ |
| 545 | } | 464 | atomic_dec(&op_async->gb->outstanding_operations); |
| 546 | 465 | wake_up(&gb->wq_completion); | |
| 547 | static void gb_loopback_async_operation_work(struct work_struct *work) | ||
| 548 | { | ||
| 549 | struct gb_loopback *gb; | ||
| 550 | struct gb_operation *operation; | ||
| 551 | struct gb_loopback_async_operation *op_async; | ||
| 552 | |||
| 553 | op_async = container_of(work, struct gb_loopback_async_operation, work); | ||
| 554 | gb = op_async->gb; | ||
| 555 | operation = op_async->operation; | ||
| 556 | |||
| 557 | mutex_lock(&gb->mutex); | ||
| 558 | if (op_async->pending) { | ||
| 559 | gb->requests_timedout++; | ||
| 560 | gb->error++; | ||
| 561 | gb->iteration_count++; | ||
| 562 | op_async->pending = false; | ||
| 563 | gb_loopback_async_operation_put(op_async); | ||
| 564 | gb_loopback_calculate_stats(gb, true); | ||
| 565 | } | ||
| 566 | mutex_unlock(&gb->mutex); | ||
| 567 | |||
| 568 | dev_dbg(&gb->connection->bundle->dev, "timeout operation %d\n", | ||
| 569 | operation->id); | ||
| 570 | |||
| 571 | gb_operation_cancel(operation, -ETIMEDOUT); | ||
| 572 | gb_loopback_async_operation_put(op_async); | ||
| 573 | } | ||
| 574 | |||
| 575 | static void gb_loopback_async_operation_timeout(unsigned long data) | ||
| 576 | { | ||
| 577 | struct gb_loopback_async_operation *op_async; | ||
| 578 | u16 id = data; | ||
| 579 | 466 | ||
| 580 | op_async = gb_loopback_operation_find(id); | 467 | /* Release resources */ |
| 581 | if (!op_async) { | 468 | gb_operation_put(operation); |
| 582 | pr_err("operation %d not found - time out ?\n", id); | 469 | kfree(op_async); |
| 583 | return; | ||
| 584 | } | ||
| 585 | schedule_work(&op_async->work); | ||
| 586 | } | 470 | } |
| 587 | 471 | ||
| 588 | static int gb_loopback_async_operation(struct gb_loopback *gb, int type, | 472 | static int gb_loopback_async_operation(struct gb_loopback *gb, int type, |
| @@ -593,15 +477,11 @@ static int gb_loopback_async_operation(struct gb_loopback *gb, int type, · 4 unmodified lines | |||
| 593 | struct gb_loopback_async_operation *op_async; | 477 | struct gb_loopback_async_operation *op_async; |
| 594 | struct gb_operation *operation; | 478 | struct gb_operation *operation; |
| 595 | int ret; | 479 | int ret; |
| 596 | unsigned long flags; | ||
| 597 | 480 | ||
| 598 | op_async = kzalloc(sizeof(*op_async), GFP_KERNEL); | 481 | op_async = kzalloc(sizeof(*op_async), GFP_KERNEL); |
| 599 | if (!op_async) | 482 | if (!op_async) |
| 600 | return -ENOMEM; | 483 | return -ENOMEM; |
| 601 | 484 | ||
| 602 | INIT_WORK(&op_async->work, gb_loopback_async_operation_work); | ||
| 603 | kref_init(&op_async->kref); | ||
| 604 | |||
| 605 | operation = gb_operation_create(gb->connection, type, request_size, | 485 | operation = gb_operation_create(gb->connection, type, request_size, |
| 606 | response_size, GFP_KERNEL); | 486 | response_size, GFP_KERNEL); |
| 607 | if (!operation) { | 487 | if (!operation) { |
| @@ -612,35 +492,24 @@ static int gb_loopback_async_operation(struct gb_loopback *gb, int type, · 4 unmodified lines | |||
| 612 | if (request_size) | 492 | if (request_size) |
| 613 | memcpy(operation->request->payload, request, request_size); | 493 | memcpy(operation->request->payload, request, request_size); |
| 614 | 494 | ||
| 495 | gb_operation_set_data(operation, op_async); | ||
| 496 | |||
| 615 | op_async->gb = gb; | 497 | op_async->gb = gb; |
| 616 | op_async->operation = operation; | 498 | op_async->operation = operation; |
| 617 | op_async->completion = completion; | 499 | op_async->completion = completion; |
| 618 | 500 | ||
| 619 | spin_lock_irqsave(&gb_dev.lock, flags); | 501 | op_async->ts = ktime_get(); |
| 620 | list_add_tail(&op_async->entry, &gb_dev.list_op_async); | ||
| 621 | spin_unlock_irqrestore(&gb_dev.lock, flags); | ||
| 622 | 502 | ||
| 623 | do_gettimeofday(&op_async->ts); | ||
| 624 | op_async->pending = true; | ||
| 625 | atomic_inc(&gb->outstanding_operations); | 503 | atomic_inc(&gb->outstanding_operations); |
| 626 | mutex_lock(&gb->mutex); | ||
| 627 | ret = gb_operation_request_send(operation, | 504 | ret = gb_operation_request_send(operation, |
| 628 | gb_loopback_async_operation_callback, | 505 | gb_loopback_async_operation_callback, |
| 629 | 0, | 506 | jiffies_to_msecs(gb->jiffy_timeout), |
| 630 | GFP_KERNEL); | 507 | GFP_KERNEL); |
| 631 | if (ret) | 508 | if (ret) { |
| 632 | goto error; | 509 | atomic_dec(&gb->outstanding_operations); |
| 633 | 510 | gb_operation_put(operation); | |
| 634 | setup_timer(&op_async->timer, gb_loopback_async_operation_timeout, | 511 | kfree(op_async); |
| 635 | (unsigned long)operation->id); | 512 | } |
| 636 | op_async->timer.expires = jiffies + gb->jiffy_timeout; | ||
| 637 | add_timer(&op_async->timer); | ||
| 638 | |||
| 639 | goto done; | ||
| 640 | error: | ||
| 641 | gb_loopback_async_operation_put(op_async); | ||
| 642 | done: | ||
| 643 | mutex_unlock(&gb->mutex); | ||
| 644 | return ret; | 513 | return ret; |
| 645 | } | 514 | } |
| 646 | 515 | ||
| @@ -854,7 +723,7 @@ static void gb_loopback_reset_stats(struct gb_loopback *gb) · 207 unmodified lines | |||
| 854 | /* Should be initialized at least once per transaction set */ | 723 | /* Should be initialized at least once per transaction set */ |
| 855 | gb->apbridge_latency_ts = 0; | 724 | gb->apbridge_latency_ts = 0; |
| 856 | gb->gbphy_latency_ts = 0; | 725 | gb->gbphy_latency_ts = 0; |
| 857 | memset(&gb->ts, 0, sizeof(struct timeval)); | 726 | gb->ts = ktime_set(0, 0); |
| 858 | } | 727 | } |
| 859 | 728 | ||
| 860 | static void gb_loopback_update_stats(struct gb_loopback_stats *stats, u32 val) | 729 | static void gb_loopback_update_stats(struct gb_loopback_stats *stats, u32 val) |
| @@ -937,15 +806,15 @@ static void gb_loopback_calculate_stats(struct gb_loopback *gb, bool error) · 76 unmodified lines | |||
| 937 | { | 806 | { |
| 938 | u64 nlat; | 807 | u64 nlat; |
| 939 | u32 lat; | 808 | u32 lat; |
| 940 | struct timeval te; | 809 | ktime_t te; |
| 941 | 810 | ||
| 942 | if (!error) { | 811 | if (!error) { |
| 943 | gb->requests_completed++; | 812 | gb->requests_completed++; |
| 944 | gb_loopback_calculate_latency_stats(gb); | 813 | gb_loopback_calculate_latency_stats(gb); |
| 945 | } | 814 | } |
| 946 | 815 | ||
| 947 | do_gettimeofday(&te); | 816 | te = ktime_get(); |
| 948 | nlat = gb_loopback_calc_latency(&gb->ts, &te); | 817 | nlat = gb_loopback_calc_latency(gb->ts, te); |
| 949 | if (nlat >= NSEC_PER_SEC || gb->iteration_count == gb->iteration_max) { | 818 | if (nlat >= NSEC_PER_SEC || gb->iteration_count == gb->iteration_max) { |
| 950 | lat = gb_loopback_nsec_to_usec_latency(nlat); | 819 | lat = gb_loopback_nsec_to_usec_latency(nlat); |
| 951 | 820 | ||
| @@ -1029,9 +898,8 @@ static int gb_loopback_fn(void *data) · 77 unmodified lines | |||
| 1029 | size = gb->size; | 898 | size = gb->size; |
| 1030 | us_wait = gb->us_wait; | 899 | us_wait = gb->us_wait; |
| 1031 | type = gb->type; | 900 | type = gb->type; |
| 1032 | if (gb->ts.tv_usec == 0 && gb->ts.tv_sec == 0) | 901 | if (ktime_to_ns(gb->ts) == 0) |
| 1033 | do_gettimeofday(&gb->ts); | 902 | gb->ts = ktime_get(); |
| 1034 | mutex_unlock(&gb->mutex); | ||
| 1035 | 903 | ||
| 1036 | /* Else operations to perform */ | 904 | /* Else operations to perform */ |
| 1037 | if (gb->async) { | 905 | if (gb->async) { |
| @@ -1042,8 +910,10 @@ static int gb_loopback_fn(void *data) · 4 unmodified lines | |||
| 1042 | else if (type == GB_LOOPBACK_TYPE_SINK) | 910 | else if (type == GB_LOOPBACK_TYPE_SINK) |
| 1043 | error = gb_loopback_async_sink(gb, size); | 911 | error = gb_loopback_async_sink(gb, size); |
| 1044 | 912 | ||
| 1045 | if (error) | 913 | if (error) { |
| 1046 | gb->error++; | 914 | gb->error++; |
| 915 | gb->iteration_count++; | ||
| 916 | } | ||
| 1047 | } else { | 917 | } else { |
| 1048 | /* We are effectively single threaded here */ | 918 | /* We are effectively single threaded here */ |
| 1049 | if (type == GB_LOOPBACK_TYPE_PING) | 919 | if (type == GB_LOOPBACK_TYPE_PING) |
| @@ -1059,6 +929,7 @@ static int gb_loopback_fn(void *data) · 9 unmodified lines | |||
| 1059 | gb_loopback_calculate_stats(gb, !!error); | 929 | gb_loopback_calculate_stats(gb, !!error); |
| 1060 | } | 930 | } |
| 1061 | gb->send_count++; | 931 | gb->send_count++; |
| 932 | mutex_unlock(&gb->mutex); | ||
| 1062 | 933 | ||
| 1063 | if (us_wait) { | 934 | if (us_wait) { |
| 1064 | if (us_wait < 20000) | 935 | if (us_wait < 20000) |
| @@ -1241,18 +1112,12 @@ static int gb_loopback_probe(struct gb_bundle *bundle, · 176 unmodified lines | |||
| 1241 | retval = -ENOMEM; | 1112 | retval = -ENOMEM; |
| 1242 | goto out_conn; | 1113 | goto out_conn; |
| 1243 | } | 1114 | } |
| 1244 | if (kfifo_alloc(&gb->kfifo_ts, kfifo_depth * sizeof(struct timeval) * 2, | ||
| 1245 | GFP_KERNEL)) { | ||
| 1246 | retval = -ENOMEM; | ||
| 1247 | goto out_kfifo0; | ||
| 1248 | } | ||
| 1249 | |||
| 1250 | /* Fork worker thread */ | 1115 | /* Fork worker thread */ |
| 1251 | mutex_init(&gb->mutex); | 1116 | mutex_init(&gb->mutex); |
| 1252 | gb->task = kthread_run(gb_loopback_fn, gb, "gb_loopback"); | 1117 | gb->task = kthread_run(gb_loopback_fn, gb, "gb_loopback"); |
| 1253 | if (IS_ERR(gb->task)) { | 1118 | if (IS_ERR(gb->task)) { |
| 1254 | retval = PTR_ERR(gb->task); | 1119 | retval = PTR_ERR(gb->task); |
| 1255 | goto out_kfifo1; | 1120 | goto out_kfifo; |
| 1256 | } | 1121 | } |
| 1257 | 1122 | ||
| 1258 | spin_lock_irqsave(&gb_dev.lock, flags); | 1123 | spin_lock_irqsave(&gb_dev.lock, flags); |
| @@ -1266,9 +1131,7 @@ static int gb_loopback_probe(struct gb_bundle *bundle, · 7 unmodified lines | |||
| 1266 | 1131 | ||
| 1267 | return 0; | 1132 | return 0; |
| 1268 | 1133 | ||
| 1269 | out_kfifo1: | 1134 | out_kfifo: |
| 1270 | kfifo_free(&gb->kfifo_ts); | ||
| 1271 | out_kfifo0: | ||
| 1272 | kfifo_free(&gb->kfifo_lat); | 1135 | kfifo_free(&gb->kfifo_lat); |
| 1273 | out_conn: | 1136 | out_conn: |
| 1274 | device_unregister(dev); | 1137 | device_unregister(dev); |
| @@ -1302,7 +1165,6 @@ static void gb_loopback_disconnect(struct gb_bundle *bundle) · 27 unmodified lines | |||
| 1302 | kthread_stop(gb->task); | 1165 | kthread_stop(gb->task); |
| 1303 | 1166 | ||
| 1304 | kfifo_free(&gb->kfifo_lat); | 1167 | kfifo_free(&gb->kfifo_lat); |
| 1305 | kfifo_free(&gb->kfifo_ts); | ||
| 1306 | gb_connection_latency_tag_disable(gb->connection); | 1168 | gb_connection_latency_tag_disable(gb->connection); |
| 1307 | debugfs_remove(gb->file); | 1169 | debugfs_remove(gb->file); |
| 1308 | 1170 | ||
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus manifest parsing | 3 | * Greybus manifest parsing |
| 3 | * | 4 | * |
| 4 | * Copyright 2014-2015 Google Inc. | 5 | * Copyright 2014-2015 Google Inc. |
| 5 | * Copyright 2014-2015 Linaro Ltd. | 6 | * Copyright 2014-2015 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include "greybus.h" | 9 | #include "greybus.h" |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus manifest parsing | 3 | * Greybus manifest parsing |
| 3 | * | 4 | * |
| 4 | * Copyright 2014 Google Inc. | 5 | * Copyright 2014 Google Inc. |
| 5 | * Copyright 2014 Linaro Ltd. | 6 | * Copyright 2014 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #ifndef __MANIFEST_H | 9 | #ifndef __MANIFEST_H |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus Module code | 3 | * Greybus Module code |
| 3 | * | 4 | * |
| 4 | * Copyright 2016 Google Inc. | 5 | * Copyright 2016 Google Inc. |
| 5 | * Copyright 2016 Linaro Ltd. | 6 | * Copyright 2016 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include "greybus.h" | 9 | #include "greybus.h" |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus Module code | 3 | * Greybus Module code |
| 3 | * | 4 | * |
| 4 | * Copyright 2016 Google Inc. | 5 | * Copyright 2016 Google Inc. |
| 5 | * Copyright 2016 Linaro Ltd. | 6 | * Copyright 2016 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #ifndef __MODULE_H | 9 | #ifndef __MODULE_H |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus operations | 3 | * Greybus operations |
| 3 | * | 4 | * |
| 4 | * Copyright 2014-2015 Google Inc. | 5 | * Copyright 2014-2015 Google Inc. |
| 5 | * Copyright 2014-2015 Linaro Ltd. | 6 | * Copyright 2014-2015 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/kernel.h> | 9 | #include <linux/kernel.h> |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus operations | 3 | * Greybus operations |
| 3 | * | 4 | * |
| 4 | * Copyright 2014 Google Inc. | 5 | * Copyright 2014 Google Inc. |
| 5 | * Copyright 2014 Linaro Ltd. | 6 | * Copyright 2014 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #ifndef __OPERATION_H | 9 | #ifndef __OPERATION_H |
| @@ -105,6 +104,8 @@ struct gb_operation { · 94 unmodified lines | |||
| 105 | 104 | ||
| 106 | int active; | 105 | int active; |
| 107 | struct list_head links; /* connection->operations */ | 106 | struct list_head links; /* connection->operations */ |
| 107 | |||
| 108 | void *private; | ||
| 108 | }; | 109 | }; |
| 109 | 110 | ||
| 110 | static inline bool | 111 | static inline bool |
| @@ -206,6 +207,17 @@ static inline int gb_operation_unidirectional(struct gb_connection *connection, · 95 unmodified lines | |||
| 206 | request, request_size, GB_OPERATION_TIMEOUT_DEFAULT); | 207 | request, request_size, GB_OPERATION_TIMEOUT_DEFAULT); |
| 207 | } | 208 | } |
| 208 | 209 | ||
| 210 | static inline void *gb_operation_get_data(struct gb_operation *operation) | ||
| 211 | { | ||
| 212 | return operation->private; | ||
| 213 | } | ||
| 214 | |||
| 215 | static inline void gb_operation_set_data(struct gb_operation *operation, | ||
| 216 | void *data) | ||
| 217 | { | ||
| 218 | operation->private = data; | ||
| 219 | } | ||
| 220 | |||
| 209 | int gb_operation_init(void); | 221 | int gb_operation_init(void); |
| 210 | void gb_operation_exit(void); | 222 | void gb_operation_exit(void); |
| 211 | 223 | ||
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Power Supply driver for a Greybus module. | 3 | * Power Supply driver for a Greybus module. |
| 3 | * | 4 | * |
| 4 | * Copyright 2014-2015 Google Inc. | 5 | * Copyright 2014-2015 Google Inc. |
| 5 | * Copyright 2014-2015 Linaro Ltd. | 6 | * Copyright 2014-2015 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/kernel.h> | 9 | #include <linux/kernel.h> |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * PWM Greybus driver. | 3 | * PWM Greybus driver. |
| 3 | * | 4 | * |
| 4 | * Copyright 2014 Google Inc. | 5 | * Copyright 2014 Google Inc. |
| 5 | * Copyright 2014 Linaro Ltd. | 6 | * Copyright 2014 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/kernel.h> | 9 | #include <linux/kernel.h> |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus driver for the Raw protocol | 3 | * Greybus driver for the Raw protocol |
| 3 | * | 4 | * |
| 4 | * Copyright 2015 Google Inc. | 5 | * Copyright 2015 Google Inc. |
| 5 | * Copyright 2015 Linaro Ltd. | 6 | * Copyright 2015 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | #include <linux/kernel.h> | 8 | #include <linux/kernel.h> |
| 10 | #include <linux/module.h> | 9 | #include <linux/module.h> |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * SD/MMC Greybus driver. | 3 | * SD/MMC Greybus driver. |
| 3 | * | 4 | * |
| 4 | * Copyright 2014-2015 Google Inc. | 5 | * Copyright 2014-2015 Google Inc. |
| 5 | * Copyright 2014-2015 Linaro Ltd. | 6 | * Copyright 2014-2015 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/kernel.h> | 9 | #include <linux/kernel.h> |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * SPI bridge PHY driver. | 3 | * SPI bridge PHY driver. |
| 3 | * | 4 | * |
| 4 | * Copyright 2014-2016 Google Inc. | 5 | * Copyright 2014-2016 Google Inc. |
| 5 | * Copyright 2014-2016 Linaro Ltd. | 6 | * Copyright 2014-2016 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/module.h> | 9 | #include <linux/module.h> |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus SPI library | 3 | * Greybus SPI library |
| 3 | * | 4 | * |
| 4 | * Copyright 2014-2016 Google Inc. | 5 | * Copyright 2014-2016 Google Inc. |
| 5 | * Copyright 2014-2016 Linaro Ltd. | 6 | * Copyright 2014-2016 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/bitops.h> | 9 | #include <linux/bitops.h> |
| @@ -544,11 +543,14 @@ int gb_spilib_master_init(struct gb_connection *connection, struct device *dev, · 533 unmodified lines | |||
| 544 | 543 | ||
| 545 | return 0; | 544 | return 0; |
| 546 | 545 | ||
| 547 | exit_spi_unregister: | ||
| 548 | spi_unregister_master(master); | ||
| 549 | exit_spi_put: | 546 | exit_spi_put: |
| 550 | spi_master_put(master); | 547 | spi_master_put(master); |
| 551 | 548 | ||
| 549 | return ret; | ||
| 550 | |||
| 551 | exit_spi_unregister: | ||
| 552 | spi_unregister_master(master); | ||
| 553 | |||
| 552 | return ret; | 554 | return ret; |
| 553 | } | 555 | } |
| 554 | EXPORT_SYMBOL_GPL(gb_spilib_master_init); | 556 | EXPORT_SYMBOL_GPL(gb_spilib_master_init); |
| @@ -558,7 +560,6 @@ void gb_spilib_master_exit(struct gb_connection *connection) · 3 unmodified lines | |||
| 558 | struct spi_master *master = gb_connection_get_data(connection); | 560 | struct spi_master *master = gb_connection_get_data(connection); |
| 559 | 561 | ||
| 560 | spi_unregister_master(master); | 562 | spi_unregister_master(master); |
| 561 | spi_master_put(master); | ||
| 562 | } | 563 | } |
| 563 | EXPORT_SYMBOL_GPL(gb_spilib_master_exit); | 564 | EXPORT_SYMBOL_GPL(gb_spilib_master_exit); |
| 564 | 565 | ||
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus SPI library header | 3 | * Greybus SPI library header |
| 3 | * | 4 | * |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * SVC Greybus driver. | 3 | * SVC Greybus driver. |
| 3 | * | 4 | * |
| 4 | * Copyright 2015 Google Inc. | 5 | * Copyright 2015 Google Inc. |
| 5 | * Copyright 2015 Linaro Ltd. | 6 | * Copyright 2015 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/debugfs.h> | 9 | #include <linux/debugfs.h> |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus SVC code | 3 | * Greybus SVC code |
| 3 | * | 4 | * |
| 4 | * Copyright 2015 Google Inc. | 5 | * Copyright 2015 Google Inc. |
| 5 | * Copyright 2015 Linaro Ltd. | 6 | * Copyright 2015 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #ifndef __SVC_H | 9 | #ifndef __SVC_H |
| @@ -1,9 +1,8 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * SVC Greybus "watchdog" driver. | 3 | * SVC Greybus "watchdog" driver. |
| 3 | * | 4 | * |
| 4 | * Copyright 2016 Google Inc. | 5 | * Copyright 2016 Google Inc. |
| 5 | * | ||
| 6 | * Released under the GPLv2 only. | ||
| 7 | */ | 6 | */ |
| 8 | 7 | ||
| 9 | #include <linux/delay.h> | 8 | #include <linux/delay.h> |
| @@ -1,4 +1,5 @@ | |||
| 1 | #!/usr/bin/env python | 1 | #!/usr/bin/env python |
| 2 | # SPDX-License-Identifier: BSD-3-Clause | ||
| 2 | 3 | ||
| 3 | # Copyright (c) 2015 Google, Inc. | 4 | # Copyright (c) 2015 Google, Inc. |
| 4 | # Copyright (c) 2015 Linaro, Ltd. | 5 | # Copyright (c) 2015 Linaro, Ltd. |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: BSD-3-Clause | ||
| 1 | /* | 2 | /* |
| 2 | * Loopback test application | 3 | * Loopback test application |
| 3 | * | 4 | * |
| @@ -1,11 +1,10 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * UART driver for the Greybus "generic" UART module. | 3 | * UART driver for the Greybus "generic" UART module. |
| 3 | * | 4 | * |
| 4 | * Copyright 2014 Google Inc. | 5 | * Copyright 2014 Google Inc. |
| 5 | * Copyright 2014 Linaro Ltd. | 6 | * Copyright 2014 Linaro Ltd. |
| 6 | * | 7 | * |
| 7 | * Released under the GPLv2 only. | ||
| 8 | * | ||
| 9 | * Heavily based on drivers/usb/class/cdc-acm.c and | 8 | * Heavily based on drivers/usb/class/cdc-acm.c and |
| 10 | * drivers/usb/serial/usb-serial.c. | 9 | * drivers/usb/serial/usb-serial.c. |
| 11 | */ | 10 | */ |
| @@ -1,11 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * USB host driver for the Greybus "generic" USB module. | 3 | * USB host driver for the Greybus "generic" USB module. |
| 3 | * | 4 | * |
| 4 | * Copyright 2014 Google Inc. | 5 | * Copyright 2014 Google Inc. |
| 5 | * Copyright 2014 Linaro Ltd. | 6 | * Copyright 2014 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | * | ||
| 9 | */ | 7 | */ |
| 10 | #include <linux/kernel.h> | 8 | #include <linux/kernel.h> |
| 11 | #include <linux/module.h> | 9 | #include <linux/module.h> |
| @@ -1,10 +1,9 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Greybus Vibrator protocol driver. | 3 | * Greybus Vibrator protocol driver. |
| 3 | * | 4 | * |
| 4 | * Copyright 2014 Google Inc. | 5 | * Copyright 2014 Google Inc. |
| 5 | * Copyright 2014 Linaro Ltd. | 6 | * Copyright 2014 Linaro Ltd. |
| 6 | * | ||
| 7 | * Released under the GPLv2 only. | ||
| 8 | */ | 7 | */ |
| 9 | 8 | ||
| 10 | #include <linux/kernel.h> | 9 | #include <linux/kernel.h> |
| @@ -106,7 +106,7 @@ static int readmagic_bitstream(u8 *bitdata, int *offset) · 105 unmodified lines | |||
| 106 | read_bitstream(bitdata, buf, offset, 13); | 106 | read_bitstream(bitdata, buf, offset, 13); |
| 107 | r = memcmp(buf, bits_magic, 13); | 107 | r = memcmp(buf, bits_magic, 13); |
| 108 | if (r) { | 108 | if (r) { |
| 109 | pr_err("error: corrupted header"); | 109 | pr_err("error: corrupted header\n"); |
| 110 | return -EINVAL; | 110 | return -EINVAL; |
| 111 | } | 111 | } |
| 112 | pr_info("bitstream file magic number Ok\n"); | 112 | pr_info("bitstream file magic number Ok\n"); |
| @@ -26,9 +26,6 @@ Then fill in the following: · 25 unmodified lines | |||
| 26 | pointer to a structure with elements that tend to be fixed for | 26 | pointer to a structure with elements that tend to be fixed for |
| 27 | large sets of different parts supported by a given driver. | 27 | large sets of different parts supported by a given driver. |
| 28 | This contains: | 28 | This contains: |
| 29 | * info->driver_module: | ||
| 30 | Set to THIS_MODULE. Used to ensure correct ownership | ||
| 31 | of various resources allocate by the core. | ||
| 32 | * info->event_attrs: | 29 | * info->event_attrs: |
| 33 | Attributes used to enable / disable hardware events. | 30 | Attributes used to enable / disable hardware events. |
| 34 | * info->attrs: | 31 | * info->attrs: |
| @@ -10,10 +10,6 @@ struct iio_trig *trig = iio_trigger_alloc("<trigger format string>", ...); · 9 unmodified lines | |||
| 10 | allocates a trigger structure. The key elements to then fill in within | 10 | allocates a trigger structure. The key elements to then fill in within |
| 11 | a driver are: | 11 | a driver are: |
| 12 | 12 | ||
| 13 | trig->owner | ||
| 14 | Typically set to THIS_MODULE. Used to ensure correct | ||
| 15 | ownership of core allocated resources. | ||
| 16 | |||
| 17 | trig->set_trigger_state: | 13 | trig->set_trigger_state: |
| 18 | Function that enables / disables the underlying source of the trigger. | 14 | Function that enables / disables the underlying source of the trigger. |
| 19 | 15 | ||
| @@ -284,7 +284,6 @@ static const struct iio_info adis16201_info = { · 283 unmodified lines | |||
| 284 | .read_raw = adis16201_read_raw, | 284 | .read_raw = adis16201_read_raw, |
| 285 | .write_raw = adis16201_write_raw, | 285 | .write_raw = adis16201_write_raw, |
| 286 | .update_scan_mode = adis_update_scan_mode, | 286 | .update_scan_mode = adis_update_scan_mode, |
| 287 | .driver_module = THIS_MODULE, | ||
| 288 | }; | 287 | }; |
| 289 | 288 | ||
| 290 | static const char * const adis16201_status_error_msgs[] = { | 289 | static const char * const adis16201_status_error_msgs[] = { |
| @@ -232,7 +232,6 @@ static const struct iio_info adis16203_info = { · 231 unmodified lines | |||
| 232 | .read_raw = adis16203_read_raw, | 232 | .read_raw = adis16203_read_raw, |
| 233 | .write_raw = adis16203_write_raw, | 233 | .write_raw = adis16203_write_raw, |
| 234 | .update_scan_mode = adis_update_scan_mode, | 234 | .update_scan_mode = adis_update_scan_mode, |
| 235 | .driver_module = THIS_MODULE, | ||
| 236 | }; | 235 | }; |
| 237 | 236 | ||
| 238 | static const char * const adis16203_status_error_msgs[] = { | 237 | static const char * const adis16203_status_error_msgs[] = { |
| @@ -285,7 +285,6 @@ static const struct iio_info adis16209_info = { · 284 unmodified lines | |||
| 285 | .read_raw = adis16209_read_raw, | 285 | .read_raw = adis16209_read_raw, |
| 286 | .write_raw = adis16209_write_raw, | 286 | .write_raw = adis16209_write_raw, |
| 287 | .update_scan_mode = adis_update_scan_mode, | 287 | .update_scan_mode = adis_update_scan_mode, |
| 288 | .driver_module = THIS_MODULE, | ||
| 289 | }; | 288 | }; |
| 290 | 289 | ||
| 291 | static const char * const adis16209_status_error_msgs[] = { | 290 | static const char * const adis16209_status_error_msgs[] = { |
| @@ -361,7 +361,6 @@ static const struct iio_info adis16240_info = { · 360 unmodified lines | |||
| 361 | .read_raw = adis16240_read_raw, | 361 | .read_raw = adis16240_read_raw, |
| 362 | .write_raw = adis16240_write_raw, | 362 | .write_raw = adis16240_write_raw, |
| 363 | .update_scan_mode = adis_update_scan_mode, | 363 | .update_scan_mode = adis_update_scan_mode, |
| 364 | .driver_module = THIS_MODULE, | ||
| 365 | }; | 364 | }; |
| 366 | 365 | ||
| 367 | static const char * const adis16240_status_error_msgs[] = { | 366 | static const char * const adis16240_status_error_msgs[] = { |
| @@ -162,6 +162,7 @@ struct ad7192_state { · 161 unmodified lines | |||
| 162 | u32 scale_avail[8][2]; | 162 | u32 scale_avail[8][2]; |
| 163 | u8 gpocon; | 163 | u8 gpocon; |
| 164 | u8 devid; | 164 | u8 devid; |
| 165 | struct mutex lock; /* protect sensor state */ | ||
| 165 | 166 | ||
| 166 | struct ad_sigma_delta sd; | 167 | struct ad_sigma_delta sd; |
| 167 | }; | 168 | }; |
| @@ -461,10 +462,10 @@ static int ad7192_read_raw(struct iio_dev *indio_dev, · 293 unmodified lines | |||
| 461 | case IIO_CHAN_INFO_SCALE: | 462 | case IIO_CHAN_INFO_SCALE: |
| 462 | switch (chan->type) { | 463 | switch (chan->type) { |
| 463 | case IIO_VOLTAGE: | 464 | case IIO_VOLTAGE: |
| 464 | mutex_lock(&indio_dev->mlock); | 465 | mutex_lock(&st->lock); |
| 465 | *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0]; | 466 | *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0]; |
| 466 | *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1]; | 467 | *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1]; |
| 467 | mutex_unlock(&indio_dev->mlock); | 468 | mutex_unlock(&st->lock); |
| 468 | return IIO_VAL_INT_PLUS_NANO; | 469 | return IIO_VAL_INT_PLUS_NANO; |
| 469 | case IIO_TEMP: | 470 | case IIO_TEMP: |
| 470 | *val = 0; | 471 | *val = 0; |
| @@ -508,6 +509,7 @@ static int ad7192_write_raw(struct iio_dev *indio_dev, · 37 unmodified lines | |||
| 508 | switch (mask) { | 509 | switch (mask) { |
| 509 | case IIO_CHAN_INFO_SCALE: | 510 | case IIO_CHAN_INFO_SCALE: |
| 510 | ret = -EINVAL; | 511 | ret = -EINVAL; |
| 512 | mutex_lock(&st->lock); | ||
| 511 | for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) | 513 | for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) |
| 512 | if (val2 == st->scale_avail[i][1]) { | 514 | if (val2 == st->scale_avail[i][1]) { |
| 513 | ret = 0; | 515 | ret = 0; |
| @@ -521,6 +523,7 @@ static int ad7192_write_raw(struct iio_dev *indio_dev, · 7 unmodified lines | |||
| 521 | ad7192_calibrate_all(st); | 523 | ad7192_calibrate_all(st); |
| 522 | break; | 524 | break; |
| 523 | } | 525 | } |
| 526 | mutex_unlock(&st->lock); | ||
| 524 | break; | 527 | break; |
| 525 | case IIO_CHAN_INFO_SAMP_FREQ: | 528 | case IIO_CHAN_INFO_SAMP_FREQ: |
| 526 | if (!val) { | 529 | if (!val) { |
| @@ -567,7 +570,6 @@ static const struct iio_info ad7192_info = { · 40 unmodified lines | |||
| 567 | .write_raw_get_fmt = ad7192_write_raw_get_fmt, | 570 | .write_raw_get_fmt = ad7192_write_raw_get_fmt, |
| 568 | .attrs = &ad7192_attribute_group, | 571 | .attrs = &ad7192_attribute_group, |
| 569 | .validate_trigger = ad_sd_validate_trigger, | 572 | .validate_trigger = ad_sd_validate_trigger, |
| 570 | .driver_module = THIS_MODULE, | ||
| 571 | }; | 573 | }; |
| 572 | 574 | ||
| 573 | static const struct iio_info ad7195_info = { | 575 | static const struct iio_info ad7195_info = { |
| @@ -576,7 +578,6 @@ static const struct iio_info ad7195_info = { · 2 unmodified lines | |||
| 576 | .write_raw_get_fmt = ad7192_write_raw_get_fmt, | 578 | .write_raw_get_fmt = ad7192_write_raw_get_fmt, |
| 577 | .attrs = &ad7195_attribute_group, | 579 | .attrs = &ad7195_attribute_group, |
| 578 | .validate_trigger = ad_sd_validate_trigger, | 580 | .validate_trigger = ad_sd_validate_trigger, |
| 579 | .driver_module = THIS_MODULE, | ||
| 580 | }; | 581 | }; |
| 581 | 582 | ||
| 582 | static const struct iio_chan_spec ad7192_channels[] = { | 583 | static const struct iio_chan_spec ad7192_channels[] = { |
| @@ -632,6 +633,8 @@ static int ad7192_probe(struct spi_device *spi) · 49 unmodified lines | |||
| 632 | 633 | ||
| 633 | st = iio_priv(indio_dev); | 634 | st = iio_priv(indio_dev); |
| 634 | 635 | ||
| 636 | mutex_init(&st->lock); | ||
| 637 | |||
| 635 | st->avdd = devm_regulator_get(&spi->dev, "avdd"); | 638 | st->avdd = devm_regulator_get(&spi->dev, "avdd"); |
| 636 | if (IS_ERR(st->avdd)) | 639 | if (IS_ERR(st->avdd)) |
| 637 | return PTR_ERR(st->avdd); | 640 | return PTR_ERR(st->avdd); |
| @@ -828,7 +828,6 @@ static const struct iio_info ad7280_info = { · 827 unmodified lines | |||
| 828 | .read_raw = ad7280_read_raw, | 828 | .read_raw = ad7280_read_raw, |
| 829 | .event_attrs = &ad7280_event_attrs_group, | 829 | .event_attrs = &ad7280_event_attrs_group, |
| 830 | .attrs = &ad7280_attrs_group, | 830 | .attrs = &ad7280_attrs_group, |
| 831 | .driver_module = THIS_MODULE, | ||
| 832 | }; | 831 | }; |
| 833 | 832 | ||
| 834 | static const struct ad7280_platform_data ad7793_default_pdata = { | 833 | static const struct ad7280_platform_data ad7793_default_pdata = { |
| @@ -373,26 +373,22 @@ static irqreturn_t ad7606_interrupt(int irq, void *dev_id) · 372 unmodified lines | |||
| 373 | }; | 373 | }; |
| 374 | 374 | ||
| 375 | static const struct iio_info ad7606_info_no_os_or_range = { | 375 | static const struct iio_info ad7606_info_no_os_or_range = { |
| 376 | .driver_module = THIS_MODULE, | ||
| 377 | .read_raw = &ad7606_read_raw, | 376 | .read_raw = &ad7606_read_raw, |
| 378 | }; | 377 | }; |
| 379 | 378 | ||
| 380 | static const struct iio_info ad7606_info_os_and_range = { | 379 | static const struct iio_info ad7606_info_os_and_range = { |
| 381 | .driver_module = THIS_MODULE, | ||
| 382 | .read_raw = &ad7606_read_raw, | 380 | .read_raw = &ad7606_read_raw, |
| 383 | .write_raw = &ad7606_write_raw, | 381 | .write_raw = &ad7606_write_raw, |
| 384 | .attrs = &ad7606_attribute_group_os_and_range, | 382 | .attrs = &ad7606_attribute_group_os_and_range, |
| 385 | }; | 383 | }; |
| 386 | 384 | ||
| 387 | static const struct iio_info ad7606_info_os = { | 385 | static const struct iio_info ad7606_info_os = { |
| 388 | .driver_module = THIS_MODULE, | ||
| 389 | .read_raw = &ad7606_read_raw, | 386 | .read_raw = &ad7606_read_raw, |
| 390 | .write_raw = &ad7606_write_raw, | 387 | .write_raw = &ad7606_write_raw, |
| 391 | .attrs = &ad7606_attribute_group_os, | 388 | .attrs = &ad7606_attribute_group_os, |
| 392 | }; | 389 | }; |
| 393 | 390 | ||
| 394 | static const struct iio_info ad7606_info_range = { | 391 | static const struct iio_info ad7606_info_range = { |
| 395 | .driver_module = THIS_MODULE, | ||
| 396 | .read_raw = &ad7606_read_raw, | 392 | .read_raw = &ad7606_read_raw, |
| 397 | .write_raw = &ad7606_write_raw, | 393 | .write_raw = &ad7606_write_raw, |
| 398 | .attrs = &ad7606_attribute_group_range, | 394 | .attrs = &ad7606_attribute_group_range, |
| @@ -155,7 +155,6 @@ static const struct ad7780_chip_info ad7780_chip_info_tbl[] = { · 154 unmodified lines | |||
| 155 | 155 | ||
| 156 | static const struct iio_info ad7780_info = { | 156 | static const struct iio_info ad7780_info = { |
| 157 | .read_raw = ad7780_read_raw, | 157 | .read_raw = ad7780_read_raw, |
| 158 | .driver_module = THIS_MODULE, | ||
| 159 | }; | 158 | }; |
| 160 | 159 | ||
| 161 | static int ad7780_probe(struct spi_device *spi) | 160 | static int ad7780_probe(struct spi_device *spi) |
| @@ -335,7 +335,6 @@ static const struct attribute_group ad7816_event_attribute_group = { · 334 unmodified lines | |||
| 335 | static const struct iio_info ad7816_info = { | 335 | static const struct iio_info ad7816_info = { |
| 336 | .attrs = &ad7816_attribute_group, | 336 | .attrs = &ad7816_attribute_group, |
| 337 | .event_attrs = &ad7816_event_attribute_group, | 337 | .event_attrs = &ad7816_event_attribute_group, |
| 338 | .driver_module = THIS_MODULE, | ||
| 339 | }; | 338 | }; |
| 340 | 339 | ||
| 341 | /* | 340 | /* |
| @@ -2087,13 +2087,11 @@ EXPORT_SYMBOL_GPL(adt7316_pm_ops); · 2086 unmodified lines | |||
| 2087 | static const struct iio_info adt7316_info = { | 2087 | static const struct iio_info adt7316_info = { |
| 2088 | .attrs = &adt7316_attribute_group, | 2088 | .attrs = &adt7316_attribute_group, |
| 2089 | .event_attrs = &adt7316_event_attribute_group, | 2089 | .event_attrs = &adt7316_event_attribute_group, |
| 2090 | .driver_module = THIS_MODULE, | ||
| 2091 | }; | 2090 | }; |
| 2092 | 2091 | ||
| 2093 | static const struct iio_info adt7516_info = { | 2092 | static const struct iio_info adt7516_info = { |
| 2094 | .attrs = &adt7516_attribute_group, | 2093 | .attrs = &adt7516_attribute_group, |
| 2095 | .event_attrs = &adt7516_event_attribute_group, | 2094 | .event_attrs = &adt7516_event_attribute_group, |
| 2096 | .driver_module = THIS_MODULE, | ||
| 2097 | }; | 2095 | }; |
| 2098 | 2096 | ||
| 2099 | /* | 2097 | /* |
| @@ -569,7 +569,6 @@ static const struct attribute_group ad7150_event_attribute_group = { · 568 unmodified lines | |||
| 569 | 569 | ||
| 570 | static const struct iio_info ad7150_info = { | 570 | static const struct iio_info ad7150_info = { |
| 571 | .event_attrs = &ad7150_event_attribute_group, | 571 | .event_attrs = &ad7150_event_attribute_group, |
| 572 | .driver_module = THIS_MODULE, | ||
| 573 | .read_raw = &ad7150_read_raw, | 572 | .read_raw = &ad7150_read_raw, |
| 574 | .read_event_config = &ad7150_read_event_config, | 573 | .read_event_config = &ad7150_read_event_config, |
| 575 | .write_event_config = &ad7150_write_event_config, | 574 | .write_event_config = &ad7150_write_event_config, |
| @@ -441,7 +441,6 @@ static const struct iio_info ad7152_info = { · 440 unmodified lines | |||
| 441 | .read_raw = ad7152_read_raw, | 441 | .read_raw = ad7152_read_raw, |
| 442 | .write_raw = ad7152_write_raw, | 442 | .write_raw = ad7152_write_raw, |
| 443 | .write_raw_get_fmt = ad7152_write_raw_get_fmt, | 443 | .write_raw_get_fmt = ad7152_write_raw_get_fmt, |
| 444 | .driver_module = THIS_MODULE, | ||
| 445 | }; | 444 | }; |
| 446 | 445 | ||
| 447 | static const struct iio_chan_spec ad7152_channels[] = { | 446 | static const struct iio_chan_spec ad7152_channels[] = { |
| @@ -667,7 +667,6 @@ static const struct iio_info ad7746_info = { · 666 unmodified lines | |||
| 667 | .attrs = &ad7746_attribute_group, | 667 | .attrs = &ad7746_attribute_group, |
| 668 | .read_raw = ad7746_read_raw, | 668 | .read_raw = ad7746_read_raw, |
| 669 | .write_raw = ad7746_write_raw, | 669 | .write_raw = ad7746_write_raw, |
| 670 | .driver_module = THIS_MODULE, | ||
| 671 | }; | 670 | }; |
| 672 | 671 | ||
| 673 | /* | 672 | /* |
| @@ -290,7 +290,6 @@ static const struct attribute_group ad9832_attribute_group = { · 289 unmodified lines | |||
| 290 | 290 | ||
| 291 | static const struct iio_info ad9832_info = { | 291 | static const struct iio_info ad9832_info = { |
| 292 | .attrs = &ad9832_attribute_group, | 292 | .attrs = &ad9832_attribute_group, |
| 293 | .driver_module = THIS_MODULE, | ||
| 294 | }; | 293 | }; |
| 295 | 294 | ||
| 296 | static int ad9832_probe(struct spi_device *spi) | 295 | static int ad9832_probe(struct spi_device *spi) |
| @@ -381,12 +381,10 @@ static const struct attribute_group ad9833_attribute_group = { · 380 unmodified lines | |||
| 381 | 381 | ||
| 382 | static const struct iio_info ad9834_info = { | 382 | static const struct iio_info ad9834_info = { |
| 383 | .attrs = &ad9834_attribute_group, | 383 | .attrs = &ad9834_attribute_group, |
| 384 | .driver_module = THIS_MODULE, | ||
| 385 | }; | 384 | }; |
| 386 | 385 | ||
| 387 | static const struct iio_info ad9833_info = { | 386 | static const struct iio_info ad9833_info = { |
| 388 | .attrs = &ad9833_attribute_group, | 387 | .attrs = &ad9833_attribute_group, |
| 389 | .driver_module = THIS_MODULE, | ||
| 390 | }; | 388 | }; |
| 391 | 389 | ||
| 392 | static int ad9834_probe(struct spi_device *spi) | 390 | static int ad9834_probe(struct spi_device *spi) |
| @@ -103,7 +103,6 @@ static int adis16060_read_raw(struct iio_dev *indio_dev, · 102 unmodified lines | |||
| 103 | 103 | ||
| 104 | static const struct iio_info adis16060_info = { | 104 | static const struct iio_info adis16060_info = { |
| 105 | .read_raw = adis16060_read_raw, | 105 | .read_raw = adis16060_read_raw, |
| 106 | .driver_module = THIS_MODULE, | ||
| 107 | }; | 106 | }; |
| 108 | 107 | ||
| 109 | static const struct iio_chan_spec adis16060_channels[] = { | 108 | static const struct iio_chan_spec adis16060_channels[] = { |
| @@ -575,7 +575,6 @@ out: · 574 unmodified lines | |||
| 575 | static const struct iio_info ad5933_info = { | 575 | static const struct iio_info ad5933_info = { |
| 576 | .read_raw = ad5933_read_raw, | 576 | .read_raw = ad5933_read_raw, |
| 577 | .attrs = &ad5933_attribute_group, | 577 | .attrs = &ad5933_attribute_group, |
| 578 | .driver_module = THIS_MODULE, | ||
| 579 | }; | 578 | }; |
| 580 | 579 | ||
| 581 | static int ad5933_ring_preenable(struct iio_dev *indio_dev) | 580 | static int ad5933_ring_preenable(struct iio_dev *indio_dev) |
| @@ -15,112 +15,112 @@ · 14 unmodified lines | |||
| 15 | * more details. | 15 | * more details. |
| 16 | */ | 16 | */ |
| 17 | 17 | ||
| 18 | #include <linux/kernel.h> | ||
| 19 | #include <linux/i2c.h> | ||
| 20 | #include <linux/errno.h> | ||
| 21 | #include <linux/delay.h> | 18 | #include <linux/delay.h> |
| 22 | #include <linux/mutex.h> | 19 | #include <linux/errno.h> |
| 20 | #include <linux/i2c.h> | ||
| 23 | #include <linux/interrupt.h> | 21 | #include <linux/interrupt.h> |
| 24 | #include <linux/slab.h> | 22 | #include <linux/kernel.h> |
| 25 | #include <linux/module.h> | 23 | #include <linux/module.h> |
| 24 | #include <linux/mutex.h> | ||
| 25 | #include <linux/slab.h> | ||
| 26 | #include <linux/iio/events.h> | 26 | #include <linux/iio/events.h> |
| 27 | #include <linux/iio/iio.h> | 27 | #include <linux/iio/iio.h> |
| 28 | #include <linux/iio/sysfs.h> | 28 | #include <linux/iio/sysfs.h> |
| 29 | #include "tsl2x7x.h" | 29 | #include "tsl2x7x.h" |
| 30 | 30 | ||
| 31 | /* Cal defs*/ | 31 | /* Cal defs*/ |
| 32 | #define PROX_STAT_CAL 0 | 32 | #define PROX_STAT_CAL 0 |
| 33 | #define PROX_STAT_SAMP 1 | 33 | #define PROX_STAT_SAMP 1 |
| 34 | #define MAX_SAMPLES_CAL 200 | 34 | #define MAX_SAMPLES_CAL 200 |
| 35 | 35 | ||
| 36 | /* TSL2X7X Device ID */ | 36 | /* TSL2X7X Device ID */ |
| 37 | #define TRITON_ID 0x00 | 37 | #define TRITON_ID 0x00 |
| 38 | #define SWORDFISH_ID 0x30 | 38 | #define SWORDFISH_ID 0x30 |
| 39 | #define HALIBUT_ID 0x20 | 39 | #define HALIBUT_ID 0x20 |
| 40 | 40 | ||
| 41 | /* Lux calculation constants */ | 41 | /* Lux calculation constants */ |
| 42 | #define TSL2X7X_LUX_CALC_OVER_FLOW 65535 | 42 | #define TSL2X7X_LUX_CALC_OVER_FLOW 65535 |
| 43 | 43 | ||
| 44 | /* TAOS Register definitions - note: | 44 | /* TAOS Register definitions - note: |
| 45 | * depending on device, some of these register are not used and the | 45 | * depending on device, some of these register are not used and the |
| 46 | * register address is benign. | 46 | * register address is benign. |
| 47 | */ | 47 | */ |
| 48 | /* 2X7X register offsets */ | 48 | /* 2X7X register offsets */ |
| 49 | #define TSL2X7X_MAX_CONFIG_REG 16 | 49 | #define TSL2X7X_MAX_CONFIG_REG 16 |
| 50 | 50 | ||
| 51 | /* Device Registers and Masks */ | 51 | /* Device Registers and Masks */ |
| 52 | #define TSL2X7X_CNTRL 0x00 | 52 | #define TSL2X7X_CNTRL 0x00 |
| 53 | #define TSL2X7X_ALS_TIME 0X01 | 53 | #define TSL2X7X_ALS_TIME 0X01 |
| 54 | #define TSL2X7X_PRX_TIME 0x02 | 54 | #define TSL2X7X_PRX_TIME 0x02 |
| 55 | #define TSL2X7X_WAIT_TIME 0x03 | 55 | #define TSL2X7X_WAIT_TIME 0x03 |
| 56 | #define TSL2X7X_ALS_MINTHRESHLO 0X04 | 56 | #define TSL2X7X_ALS_MINTHRESHLO 0X04 |
| 57 | #define TSL2X7X_ALS_MINTHRESHHI 0X05 | 57 | #define TSL2X7X_ALS_MINTHRESHHI 0X05 |
| 58 | #define TSL2X7X_ALS_MAXTHRESHLO 0X06 | 58 | #define TSL2X7X_ALS_MAXTHRESHLO 0X06 |
| 59 | #define TSL2X7X_ALS_MAXTHRESHHI 0X07 | 59 | #define TSL2X7X_ALS_MAXTHRESHHI 0X07 |
| 60 | #define TSL2X7X_PRX_MINTHRESHLO 0X08 | 60 | #define TSL2X7X_PRX_MINTHRESHLO 0X08 |
| 61 | #define TSL2X7X_PRX_MINTHRESHHI 0X09 | 61 | #define TSL2X7X_PRX_MINTHRESHHI 0X09 |
| 62 | #define TSL2X7X_PRX_MAXTHRESHLO 0X0A | 62 | #define TSL2X7X_PRX_MAXTHRESHLO 0X0A |
| 63 | #define TSL2X7X_PRX_MAXTHRESHHI 0X0B | 63 | #define TSL2X7X_PRX_MAXTHRESHHI 0X0B |
| 64 | #define TSL2X7X_PERSISTENCE 0x0C | 64 | #define TSL2X7X_PERSISTENCE 0x0C |
| 65 | #define TSL2X7X_PRX_CONFIG 0x0D | 65 | #define TSL2X7X_PRX_CONFIG 0x0D |
| 66 | #define TSL2X7X_PRX_COUNT 0x0E | 66 | #define TSL2X7X_PRX_COUNT 0x0E |
| 67 | #define TSL2X7X_GAIN 0x0F | 67 | #define TSL2X7X_GAIN 0x0F |
| 68 | #define TSL2X7X_NOTUSED 0x10 | 68 | #define TSL2X7X_NOTUSED 0x10 |
| 69 | #define TSL2X7X_REVID 0x11 | 69 | #define TSL2X7X_REVID 0x11 |
| 70 | #define TSL2X7X_CHIPID 0x12 | 70 | #define TSL2X7X_CHIPID 0x12 |
| 71 | #define TSL2X7X_STATUS 0x13 | 71 | #define TSL2X7X_STATUS 0x13 |
| 72 | #define TSL2X7X_ALS_CHAN0LO 0x14 | 72 | #define TSL2X7X_ALS_CHAN0LO 0x14 |
| 73 | #define TSL2X7X_ALS_CHAN0HI 0x15 | 73 | #define TSL2X7X_ALS_CHAN0HI 0x15 |
| 74 | #define TSL2X7X_ALS_CHAN1LO 0x16 | 74 | #define TSL2X7X_ALS_CHAN1LO 0x16 |
| 75 | #define TSL2X7X_ALS_CHAN1HI 0x17 | 75 | #define TSL2X7X_ALS_CHAN1HI 0x17 |
| 76 | #define TSL2X7X_PRX_LO 0x18 | 76 | #define TSL2X7X_PRX_LO 0x18 |
| 77 | #define TSL2X7X_PRX_HI 0x19 | 77 | #define TSL2X7X_PRX_HI 0x19 |
| 78 | 78 | ||
| 79 | /* tsl2X7X cmd reg masks */ | 79 | /* tsl2X7X cmd reg masks */ |
| 80 | #define TSL2X7X_CMD_REG 0x80 | 80 | #define TSL2X7X_CMD_REG 0x80 |
| 81 | #define TSL2X7X_CMD_SPL_FN 0x60 | 81 | #define TSL2X7X_CMD_SPL_FN 0x60 |
| 82 | 82 | ||
| 83 | #define TSL2X7X_CMD_PROX_INT_CLR 0X05 | 83 | #define TSL2X7X_CMD_PROX_INT_CLR 0X05 |
| 84 | #define TSL2X7X_CMD_ALS_INT_CLR 0x06 | 84 | #define TSL2X7X_CMD_ALS_INT_CLR 0x06 |
| 85 | #define TSL2X7X_CMD_PROXALS_INT_CLR 0X07 | 85 | #define TSL2X7X_CMD_PROXALS_INT_CLR 0X07 |
| 86 | 86 | ||
| 87 | /* tsl2X7X cntrl reg masks */ | 87 | /* tsl2X7X cntrl reg masks */ |
| 88 | #define TSL2X7X_CNTL_ADC_ENBL 0x02 | 88 | #define TSL2X7X_CNTL_ADC_ENBL 0x02 |
| 89 | #define TSL2X7X_CNTL_PWR_ON 0x01 | 89 | #define TSL2X7X_CNTL_PWR_ON 0x01 |
| 90 | 90 | ||
| 91 | /* tsl2X7X status reg masks */ | 91 | /* tsl2X7X status reg masks */ |
| 92 | #define TSL2X7X_STA_ADC_VALID 0x01 | 92 | #define TSL2X7X_STA_ADC_VALID 0x01 |
| 93 | #define TSL2X7X_STA_PRX_VALID 0x02 | 93 | #define TSL2X7X_STA_PRX_VALID 0x02 |
| 94 | #define TSL2X7X_STA_ADC_PRX_VALID (TSL2X7X_STA_ADC_VALID |\ | 94 | #define TSL2X7X_STA_ADC_PRX_VALID (TSL2X7X_STA_ADC_VALID | \ |
| 95 | TSL2X7X_STA_PRX_VALID) | 95 | TSL2X7X_STA_PRX_VALID) |
| 96 | #define TSL2X7X_STA_ALS_INTR 0x10 | 96 | #define TSL2X7X_STA_ALS_INTR 0x10 |
| 97 | #define TSL2X7X_STA_PRX_INTR 0x20 | 97 | #define TSL2X7X_STA_PRX_INTR 0x20 |
| 98 | 98 | ||
| 99 | /* tsl2X7X cntrl reg masks */ | 99 | /* tsl2X7X cntrl reg masks */ |
| 100 | #define TSL2X7X_CNTL_REG_CLEAR 0x00 | 100 | #define TSL2X7X_CNTL_REG_CLEAR 0x00 |
| 101 | #define TSL2X7X_CNTL_PROX_INT_ENBL 0X20 | 101 | #define TSL2X7X_CNTL_PROX_INT_ENBL 0X20 |
| 102 | #define TSL2X7X_CNTL_ALS_INT_ENBL 0X10 | 102 | #define TSL2X7X_CNTL_ALS_INT_ENBL 0X10 |
| 103 | #define TSL2X7X_CNTL_WAIT_TMR_ENBL 0X08 | 103 | #define TSL2X7X_CNTL_WAIT_TMR_ENBL 0X08 |
| 104 | #define TSL2X7X_CNTL_PROX_DET_ENBL 0X04 | 104 | #define TSL2X7X_CNTL_PROX_DET_ENBL 0X04 |
| 105 | #define TSL2X7X_CNTL_PWRON 0x01 | 105 | #define TSL2X7X_CNTL_PWRON 0x01 |
| 106 | #define TSL2X7X_CNTL_ALSPON_ENBL 0x03 | 106 | #define TSL2X7X_CNTL_ALSPON_ENBL 0x03 |
| 107 | #define TSL2X7X_CNTL_INTALSPON_ENBL 0x13 | 107 | #define TSL2X7X_CNTL_INTALSPON_ENBL 0x13 |
| 108 | #define TSL2X7X_CNTL_PROXPON_ENBL 0x0F | 108 | #define TSL2X7X_CNTL_PROXPON_ENBL 0x0F |
| 109 | #define TSL2X7X_CNTL_INTPROXPON_ENBL 0x2F | 109 | #define TSL2X7X_CNTL_INTPROXPON_ENBL 0x2F |
| 110 | 110 | ||
| 111 | /*Prox diode to use */ | 111 | /*Prox diode to use */ |
| 112 | #define TSL2X7X_DIODE0 0x10 | 112 | #define TSL2X7X_DIODE0 0x10 |
| 113 | #define TSL2X7X_DIODE1 0x20 | 113 | #define TSL2X7X_DIODE1 0x20 |
| 114 | #define TSL2X7X_DIODE_BOTH 0x30 | 114 | #define TSL2X7X_DIODE_BOTH 0x30 |
| 115 | 115 | ||
| 116 | /* LED Power */ | 116 | /* LED Power */ |
| 117 | #define TSL2X7X_mA100 0x00 | 117 | #define TSL2X7X_100_mA 0x00 |
| 118 | #define TSL2X7X_mA50 0x40 | 118 | #define TSL2X7X_50_mA 0x40 |
| 119 | #define TSL2X7X_mA25 0x80 | 119 | #define TSL2X7X_25_mA 0x80 |
| 120 | #define TSL2X7X_mA13 0xD0 | 120 | #define TSL2X7X_13_mA 0xD0 |
| 121 | #define TSL2X7X_MAX_TIMER_CNT (0xFF) | 121 | #define TSL2X7X_MAX_TIMER_CNT 0xFF |
| 122 | 122 | ||
| 123 | #define TSL2X7X_MIN_ITIME 3 | 123 | #define TSL2X7X_MIN_ITIME 3 |
| 124 | 124 | ||
| 125 | /* TAOS txx2x7x Device family members */ | 125 | /* TAOS txx2x7x Device family members */ |
| 126 | enum { | 126 | enum { |
| @@ -142,11 +142,6 @@ enum { · 15 unmodified lines | |||
| 142 | TSL2X7X_CHIP_SUSPENDED = 2 | 142 | TSL2X7X_CHIP_SUSPENDED = 2 |
| 143 | }; | 143 | }; |
| 144 | 144 | ||
| 145 | struct tsl2x7x_parse_result { | ||
| 146 | int integer; | ||
| 147 | int fract; | ||
| 148 | }; | ||
| 149 | |||
| 150 | /* Per-device data */ | 145 | /* Per-device data */ |
| 151 | struct tsl2x7x_als_info { | 146 | struct tsl2x7x_als_info { |
| 152 | u16 als_ch0; | 147 | u16 als_ch0; |
| @@ -174,7 +169,7 @@ struct tsl2X7X_chip { · 21 unmodified lines | |||
| 174 | struct i2c_client *client; | 169 | struct i2c_client *client; |
| 175 | u16 prox_data; | 170 | u16 prox_data; |
| 176 | struct tsl2x7x_als_info als_cur_info; | 171 | struct tsl2x7x_als_info als_cur_info; |
| 177 | struct tsl2x7x_settings tsl2x7x_settings; | 172 | struct tsl2x7x_settings settings; |
| 178 | struct tsl2X7X_platform_data *pdata; | 173 | struct tsl2X7X_platform_data *pdata; |
| 179 | int als_time_scale; | 174 | int als_time_scale; |
| 180 | int als_saturation; | 175 | int als_saturation; |
| @@ -192,25 +187,25 @@ struct tsl2X7X_chip { · 11 unmodified lines | |||
| 192 | }; | 187 | }; |
| 193 | 188 | ||
| 194 | /* Different devices require different coefficents */ | 189 | /* Different devices require different coefficents */ |
| 195 | static const struct tsl2x7x_lux tsl2x71_lux_table[] = { | 190 | static const struct tsl2x7x_lux tsl2x71_lux_table[TSL2X7X_DEF_LUX_TABLE_SZ] = { |
| 196 | { 14461, 611, 1211 }, | 191 | { 14461, 611, 1211 }, |
| 197 | { 18540, 352, 623 }, | 192 | { 18540, 352, 623 }, |
| 198 | { 0, 0, 0 }, | 193 | { 0, 0, 0 }, |
| 199 | }; | 194 | }; |
| 200 | 195 | ||
| 201 | static const struct tsl2x7x_lux tmd2x71_lux_table[] = { | 196 | static const struct tsl2x7x_lux tmd2x71_lux_table[TSL2X7X_DEF_LUX_TABLE_SZ] = { |
| 202 | { 11635, 115, 256 }, | 197 | { 11635, 115, 256 }, |
| 203 | { 15536, 87, 179 }, | 198 | { 15536, 87, 179 }, |
| 204 | { 0, 0, 0 }, | 199 | { 0, 0, 0 }, |
| 205 | }; | 200 | }; |
| 206 | 201 | ||
| 207 | static const struct tsl2x7x_lux tsl2x72_lux_table[] = { | 202 | static const struct tsl2x7x_lux tsl2x72_lux_table[TSL2X7X_DEF_LUX_TABLE_SZ] = { |
| 208 | { 14013, 466, 917 }, | 203 | { 14013, 466, 917 }, |
| 209 | { 18222, 310, 552 }, | 204 | { 18222, 310, 552 }, |
| 210 | { 0, 0, 0 }, | 205 | { 0, 0, 0 }, |
| 211 | }; | 206 | }; |
| 212 | 207 | ||
| 213 | static const struct tsl2x7x_lux tmd2x72_lux_table[] = { | 208 | static const struct tsl2x7x_lux tmd2x72_lux_table[TSL2X7X_DEF_LUX_TABLE_SZ] = { |
| 214 | { 13218, 130, 262 }, | 209 | { 13218, 130, 262 }, |
| 215 | { 17592, 92, 169 }, | 210 | { 17592, 92, 169 }, |
| 216 | { 0, 0, 0 }, | 211 | { 0, 0, 0 }, |
| @@ -248,14 +243,14 @@ static const struct tsl2x7x_settings tsl2x7x_default_settings = { · 31 unmodified lines | |||
| 248 | .prox_pulse_count = 8 | 243 | .prox_pulse_count = 8 |
| 249 | }; | 244 | }; |
| 250 | 245 | ||
| 251 | static const s16 tsl2X7X_als_gainadj[] = { | 246 | static const s16 tsl2x7x_als_gain[] = { |
| 252 | 1, | 247 | 1, |
| 253 | 8, | 248 | 8, |
| 254 | 16, | 249 | 16, |
| 255 | 120 | 250 | 120 |
| 256 | }; | 251 | }; |
| 257 | 252 | ||
| 258 | static const s16 tsl2X7X_prx_gainadj[] = { | 253 | static const s16 tsl2x7x_prx_gain[] = { |
| 259 | 1, | 254 | 1, |
| 260 | 2, | 255 | 2, |
| 261 | 4, | 256 | 4, |
| @@ -353,9 +348,9 @@ static int tsl2x7x_get_lux(struct iio_dev *indio_dev) · 91 unmodified lines | |||
| 353 | 348 | ||
| 354 | /* clear any existing interrupt status */ | 349 | /* clear any existing interrupt status */ |
| 355 | ret = i2c_smbus_write_byte(chip->client, | 350 | ret = i2c_smbus_write_byte(chip->client, |
| 356 | (TSL2X7X_CMD_REG | | 351 | TSL2X7X_CMD_REG | |
| 357 | TSL2X7X_CMD_SPL_FN | | 352 | TSL2X7X_CMD_SPL_FN | |
| 358 | TSL2X7X_CMD_ALS_INT_CLR)); | 353 | TSL2X7X_CMD_ALS_INT_CLR); |
| 359 | if (ret < 0) { | 354 | if (ret < 0) { |
| 360 | dev_err(&chip->client->dev, | 355 | dev_err(&chip->client->dev, |
| 361 | "i2c_write_command failed - err = %d\n", ret); | 356 | "i2c_write_command failed - err = %d\n", ret); |
| @@ -369,7 +364,7 @@ static int tsl2x7x_get_lux(struct iio_dev *indio_dev) · 7 unmodified lines | |||
| 369 | chip->als_cur_info.als_ch0 = ch0; | 364 | chip->als_cur_info.als_ch0 = ch0; |
| 370 | chip->als_cur_info.als_ch1 = ch1; | 365 | chip->als_cur_info.als_ch1 = ch1; |
| 371 | 366 | ||
| 372 | if ((ch0 >= chip->als_saturation) || (ch1 >= chip->als_saturation)) { | 367 | if (ch0 >= chip->als_saturation || ch1 >= chip->als_saturation) { |
| 373 | lux = TSL2X7X_LUX_CALC_OVER_FLOW; | 368 | lux = TSL2X7X_LUX_CALC_OVER_FLOW; |
| 374 | goto return_max; | 369 | goto return_max; |
| 375 | } | 370 | } |
| @@ -389,11 +384,10 @@ static int tsl2x7x_get_lux(struct iio_dev *indio_dev) · 13 unmodified lines | |||
| 389 | if (p->ratio == 0) { | 384 | if (p->ratio == 0) { |
| 390 | lux = 0; | 385 | lux = 0; |
| 391 | } else { | 386 | } else { |
| 392 | ch0lux = DIV_ROUND_UP(ch0 * p->ch0, | 387 | lux = DIV_ROUND_UP(ch0 * p->ch0, |
| 393 | tsl2X7X_als_gainadj[chip->tsl2x7x_settings.als_gain]); | 388 | tsl2x7x_als_gain[chip->settings.als_gain]) - |
| 394 | ch1lux = DIV_ROUND_UP(ch1 * p->ch1, | 389 | DIV_ROUND_UP(ch1 * p->ch1, |
| 395 | tsl2X7X_als_gainadj[chip->tsl2x7x_settings.als_gain]); | 390 | tsl2x7x_als_gain[chip->settings.als_gain]); |
| 396 | lux = ch0lux - ch1lux; | ||
| 397 | } | 391 | } |
| 398 | 392 | ||
| 399 | /* note: lux is 31 bit max at this point */ | 393 | /* note: lux is 31 bit max at this point */ |
| @@ -419,7 +413,7 @@ static int tsl2x7x_get_lux(struct iio_dev *indio_dev) · 19 unmodified lines | |||
| 419 | */ | 413 | */ |
| 420 | 414 | ||
| 421 | lux64 = lux; | 415 | lux64 = lux; |
| 422 | lux64 = lux64 * chip->tsl2x7x_settings.als_gain_trim; | 416 | lux64 = lux64 * chip->settings.als_gain_trim; |
| 423 | lux64 >>= 8; | 417 | lux64 >>= 8; |
| 424 | lux = lux64; | 418 | lux = lux64; |
| 425 | lux = (lux + 500) / 1000; | 419 | lux = (lux + 500) / 1000; |
| @@ -472,7 +466,7 @@ static int tsl2x7x_get_prox(struct iio_dev *indio_dev) · 46 unmodified lines | |||
| 472 | case tmd2771: | 466 | case tmd2771: |
| 473 | if (!(ret & TSL2X7X_STA_ADC_VALID)) | 467 | if (!(ret & TSL2X7X_STA_ADC_VALID)) |
| 474 | goto prox_poll_err; | 468 | goto prox_poll_err; |
| 475 | break; | 469 | break; |
| 476 | case tsl2572: | 470 | case tsl2572: |
| 477 | case tsl2672: | 471 | case tsl2672: |
| 478 | case tmd2672: | 472 | case tmd2672: |
| @@ -480,7 +474,7 @@ static int tsl2x7x_get_prox(struct iio_dev *indio_dev) · 1 unmodified line | |||
| 480 | case tmd2772: | 474 | case tmd2772: |
| 481 | if (!(ret & TSL2X7X_STA_PRX_VALID)) | 475 | if (!(ret & TSL2X7X_STA_PRX_VALID)) |
| 482 | goto prox_poll_err; | 476 | goto prox_poll_err; |
| 483 | break; | 477 | break; |
| 484 | } | 478 | } |
| 485 | 479 | ||
| 486 | for (i = 0; i < 2; i++) { | 480 | for (i = 0; i < 2; i++) { |
| @@ -514,12 +508,10 @@ static void tsl2x7x_defaults(struct tsl2X7X_chip *chip) · 27 unmodified lines | |||
| 514 | { | 508 | { |
| 515 | /* If Operational settings defined elsewhere.. */ | 509 | /* If Operational settings defined elsewhere.. */ |
| 516 | if (chip->pdata && chip->pdata->platform_default_settings) | 510 | if (chip->pdata && chip->pdata->platform_default_settings) |
| 517 | memcpy(&chip->tsl2x7x_settings, | 511 | memcpy(&chip->settings, chip->pdata->platform_default_settings, |
| 518 | chip->pdata->platform_default_settings, | ||
| 519 | sizeof(tsl2x7x_default_settings)); | 512 | sizeof(tsl2x7x_default_settings)); |
| 520 | else | 513 | else |
| 521 | memcpy(&chip->tsl2x7x_settings, | 514 | memcpy(&chip->settings, &tsl2x7x_default_settings, |
| 522 | &tsl2x7x_default_settings, | ||
| 523 | sizeof(tsl2x7x_default_settings)); | 515 | sizeof(tsl2x7x_default_settings)); |
| 524 | 516 | ||
| 525 | /* Load up the proper lux table. */ | 517 | /* Load up the proper lux table. */ |
| @@ -529,8 +521,8 @@ static void tsl2x7x_defaults(struct tsl2X7X_chip *chip) · 3 unmodified lines | |||
| 529 | sizeof(chip->pdata->platform_lux_table)); | 521 | sizeof(chip->pdata->platform_lux_table)); |
| 530 | else | 522 | else |
| 531 | memcpy(chip->tsl2x7x_device_lux, | 523 | memcpy(chip->tsl2x7x_device_lux, |
| 532 | (struct tsl2x7x_lux *)tsl2x7x_default_lux_table_group[chip->id], | 524 | tsl2x7x_default_lux_table_group[chip->id], |
| 533 | MAX_DEFAULT_TABLE_BYTES); | 525 | TSL2X7X_DEFAULT_TABLE_BYTES); |
| 534 | } | 526 | } |
| 535 | 527 | ||
| 536 | /** | 528 | /** |
| @@ -542,9 +534,7 @@ static void tsl2x7x_defaults(struct tsl2X7X_chip *chip) · 5 unmodified lines | |||
| 542 | static int tsl2x7x_als_calibrate(struct iio_dev *indio_dev) | 534 | static int tsl2x7x_als_calibrate(struct iio_dev *indio_dev) |
| 543 | { | 535 | { |
| 544 | struct tsl2X7X_chip *chip = iio_priv(indio_dev); | 536 | struct tsl2X7X_chip *chip = iio_priv(indio_dev); |
| 545 | int gain_trim_val; | 537 | int ret, lux_val; |
| 546 | int ret; | ||
| 547 | int lux_val; | ||
| 548 | 538 | ||
| 549 | ret = i2c_smbus_read_byte_data(chip->client, | 539 | ret = i2c_smbus_read_byte_data(chip->client, |
| 550 | TSL2X7X_CMD_REG | TSL2X7X_CNTRL); | 540 | TSL2X7X_CMD_REG | TSL2X7X_CNTRL); |
| @@ -575,16 +565,16 @@ static int tsl2x7x_als_calibrate(struct iio_dev *indio_dev) · 24 unmodified lines | |||
| 575 | return lux_val; | 565 | return lux_val; |
| 576 | } | 566 | } |
| 577 | 567 | ||
| 578 | gain_trim_val = ((chip->tsl2x7x_settings.als_cal_target) | 568 | ret = (chip->settings.als_cal_target * chip->settings.als_gain_trim) / |
| 579 | * chip->tsl2x7x_settings.als_gain_trim) / lux_val; | 569 | lux_val; |
| 580 | if ((gain_trim_val < 250) || (gain_trim_val > 4000)) | 570 | if (ret < 250 || ret > 4000) |
| 581 | return -ERANGE; | 571 | return -ERANGE; |
| 582 | 572 | ||
| 583 | chip->tsl2x7x_settings.als_gain_trim = gain_trim_val; | 573 | chip->settings.als_gain_trim = ret; |
| 584 | dev_info(&chip->client->dev, | 574 | dev_info(&chip->client->dev, |
| 585 | "%s als_calibrate completed\n", chip->client->name); | 575 | "%s als_calibrate completed\n", chip->client->name); |
| 586 | 576 | ||
| 587 | return (int)gain_trim_val; | 577 | return ret; |
| 588 | } | 578 | } |
| 589 | 579 | ||
| 590 | static int tsl2x7x_chip_on(struct iio_dev *indio_dev) | 580 | static int tsl2x7x_chip_on(struct iio_dev *indio_dev) |
| @@ -602,34 +592,30 @@ static int tsl2x7x_chip_on(struct iio_dev *indio_dev) · 11 unmodified lines | |||
| 602 | chip->pdata->power_on(indio_dev); | 592 | chip->pdata->power_on(indio_dev); |
| 603 | 593 | ||
| 604 | /* Non calculated parameters */ | 594 | /* Non calculated parameters */ |
| 605 | chip->tsl2x7x_config[TSL2X7X_PRX_TIME] = | 595 | chip->tsl2x7x_config[TSL2X7X_PRX_TIME] = chip->settings.prx_time; |
| 606 | chip->tsl2x7x_settings.prx_time; | 596 | chip->tsl2x7x_config[TSL2X7X_WAIT_TIME] = chip->settings.wait_time; |
| 607 | chip->tsl2x7x_config[TSL2X7X_WAIT_TIME] = | 597 | chip->tsl2x7x_config[TSL2X7X_PRX_CONFIG] = chip->settings.prox_config; |
| 608 | chip->tsl2x7x_settings.wait_time; | ||
| 609 | chip->tsl2x7x_config[TSL2X7X_PRX_CONFIG] = | ||
| 610 | chip->tsl2x7x_settings.prox_config; | ||
| 611 | 598 | ||
| 612 | chip->tsl2x7x_config[TSL2X7X_ALS_MINTHRESHLO] = | 599 | chip->tsl2x7x_config[TSL2X7X_ALS_MINTHRESHLO] = |
| 613 | (chip->tsl2x7x_settings.als_thresh_low) & 0xFF; | 600 | (chip->settings.als_thresh_low) & 0xFF; |
| 614 | chip->tsl2x7x_config[TSL2X7X_ALS_MINTHRESHHI] = | 601 | chip->tsl2x7x_config[TSL2X7X_ALS_MINTHRESHHI] = |
| 615 | (chip->tsl2x7x_settings.als_thresh_low >> 8) & 0xFF; | 602 | (chip->settings.als_thresh_low >> 8) & 0xFF; |
| 616 | chip->tsl2x7x_config[TSL2X7X_ALS_MAXTHRESHLO] = | 603 | chip->tsl2x7x_config[TSL2X7X_ALS_MAXTHRESHLO] = |
| 617 | (chip->tsl2x7x_settings.als_thresh_high) & 0xFF; | 604 | (chip->settings.als_thresh_high) & 0xFF; |
| 618 | chip->tsl2x7x_config[TSL2X7X_ALS_MAXTHRESHHI] = | 605 | chip->tsl2x7x_config[TSL2X7X_ALS_MAXTHRESHHI] = |
| 619 | (chip->tsl2x7x_settings.als_thresh_high >> 8) & 0xFF; | 606 | (chip->settings.als_thresh_high >> 8) & 0xFF; |
| 620 | chip->tsl2x7x_config[TSL2X7X_PERSISTENCE] = | 607 | chip->tsl2x7x_config[TSL2X7X_PERSISTENCE] = chip->settings.persistence; |
| 621 | chip->tsl2x7x_settings.persistence; | ||
| 622 | 608 | ||
| 623 | chip->tsl2x7x_config[TSL2X7X_PRX_COUNT] = | 609 | chip->tsl2x7x_config[TSL2X7X_PRX_COUNT] = |
| 624 | chip->tsl2x7x_settings.prox_pulse_count; | 610 | chip->settings.prox_pulse_count; |
| 625 | chip->tsl2x7x_config[TSL2X7X_PRX_MINTHRESHLO] = | 611 | chip->tsl2x7x_config[TSL2X7X_PRX_MINTHRESHLO] = |
| 626 | (chip->tsl2x7x_settings.prox_thres_low) & 0xFF; | 612 | (chip->settings.prox_thres_low) & 0xFF; |
| 627 | chip->tsl2x7x_config[TSL2X7X_PRX_MINTHRESHHI] = | 613 | chip->tsl2x7x_config[TSL2X7X_PRX_MINTHRESHHI] = |
| 628 | (chip->tsl2x7x_settings.prox_thres_low >> 8) & 0xFF; | 614 | (chip->settings.prox_thres_low >> 8) & 0xFF; |
| 629 | chip->tsl2x7x_config[TSL2X7X_PRX_MAXTHRESHLO] = | 615 | chip->tsl2x7x_config[TSL2X7X_PRX_MAXTHRESHLO] = |
| 630 | (chip->tsl2x7x_settings.prox_thres_high) & 0xFF; | 616 | (chip->settings.prox_thres_high) & 0xFF; |
| 631 | chip->tsl2x7x_config[TSL2X7X_PRX_MAXTHRESHHI] = | 617 | chip->tsl2x7x_config[TSL2X7X_PRX_MAXTHRESHHI] = |
| 632 | (chip->tsl2x7x_settings.prox_thres_high >> 8) & 0xFF; | 618 | (chip->settings.prox_thres_high >> 8) & 0xFF; |
| 633 | 619 | ||
| 634 | /* and make sure we're not already on */ | 620 | /* and make sure we're not already on */ |
| 635 | if (chip->tsl2x7x_chip_status == TSL2X7X_CHIP_WORKING) { | 621 | if (chip->tsl2x7x_chip_status == TSL2X7X_CHIP_WORKING) { |
| @@ -639,7 +625,7 @@ static int tsl2x7x_chip_on(struct iio_dev *indio_dev) · 3 unmodified lines | |||
| 639 | } | 625 | } |
| 640 | 626 | ||
| 641 | /* determine als integration register */ | 627 | /* determine als integration register */ |
| 642 | als_count = (chip->tsl2x7x_settings.als_time * 100 + 135) / 270; | 628 | als_count = (chip->settings.als_time * 100 + 135) / 270; |
| 643 | if (!als_count) | 629 | if (!als_count) |
| 644 | als_count = 1; /* ensure at least one cycle */ | 630 | als_count = 1; /* ensure at least one cycle */ |
| 645 | 631 | ||
| @@ -649,9 +635,9 @@ static int tsl2x7x_chip_on(struct iio_dev *indio_dev) · 3 unmodified lines | |||
| 649 | 635 | ||
| 650 | /* Set the gain based on tsl2x7x_settings struct */ | 636 | /* Set the gain based on tsl2x7x_settings struct */ |
| 651 | chip->tsl2x7x_config[TSL2X7X_GAIN] = | 637 | chip->tsl2x7x_config[TSL2X7X_GAIN] = |
| 652 | chip->tsl2x7x_settings.als_gain | | 638 | chip->settings.als_gain | |
| 653 | (TSL2X7X_mA100 | TSL2X7X_DIODE1) | 639 | (TSL2X7X_100_mA | TSL2X7X_DIODE1) | |
| 654 | | ((chip->tsl2x7x_settings.prox_gain) << 2); | 640 | (chip->settings.prox_gain << 2); |
| 655 | 641 | ||
| 656 | /* set chip struct re scaling and saturation */ | 642 | /* set chip struct re scaling and saturation */ |
| 657 | chip->als_saturation = als_count * 922; /* 90% of full scale */ | 643 | chip->als_saturation = als_count * 922; /* 90% of full scale */ |
| @@ -706,18 +692,18 @@ static int tsl2x7x_chip_on(struct iio_dev *indio_dev) · 48 unmodified lines | |||
| 706 | 692 | ||
| 707 | chip->tsl2x7x_chip_status = TSL2X7X_CHIP_WORKING; | 693 | chip->tsl2x7x_chip_status = TSL2X7X_CHIP_WORKING; |
| 708 | 694 | ||
| 709 | if (chip->tsl2x7x_settings.interrupts_en != 0) { | 695 | if (chip->settings.interrupts_en != 0) { |
| 710 | dev_info(&chip->client->dev, "Setting Up Interrupt(s)\n"); | 696 | dev_info(&chip->client->dev, "Setting Up Interrupt(s)\n"); |
| 711 | 697 | ||
| 712 | reg_val = TSL2X7X_CNTL_PWR_ON | TSL2X7X_CNTL_ADC_ENBL; | 698 | reg_val = TSL2X7X_CNTL_PWR_ON | TSL2X7X_CNTL_ADC_ENBL; |
| 713 | if ((chip->tsl2x7x_settings.interrupts_en == 0x20) || | 699 | if (chip->settings.interrupts_en == 0x20 || |
| 714 | (chip->tsl2x7x_settings.interrupts_en == 0x30)) | 700 | chip->settings.interrupts_en == 0x30) |
| 715 | reg_val |= TSL2X7X_CNTL_PROX_DET_ENBL; | 701 | reg_val |= TSL2X7X_CNTL_PROX_DET_ENBL; |
| 716 | 702 | ||
| 717 | reg_val |= chip->tsl2x7x_settings.interrupts_en; | 703 | reg_val |= chip->settings.interrupts_en; |
| 718 | ret = i2c_smbus_write_byte_data(chip->client, | 704 | ret = i2c_smbus_write_byte_data(chip->client, |
| 719 | (TSL2X7X_CMD_REG | | 705 | TSL2X7X_CMD_REG | TSL2X7X_CNTRL, |
| 720 | TSL2X7X_CNTRL), reg_val); | 706 | reg_val); |
| 721 | if (ret < 0) | 707 | if (ret < 0) |
| 722 | dev_err(&chip->client->dev, | 708 | dev_err(&chip->client->dev, |
| 723 | "%s: failed in tsl2x7x_IOCTL_INT_SET.\n", | 709 | "%s: failed in tsl2x7x_IOCTL_INT_SET.\n", |
| @@ -766,8 +752,7 @@ static int tsl2x7x_chip_off(struct iio_dev *indio_dev) · 42 unmodified lines | |||
| 766 | * put device back into proper state, and unlock | 752 | * put device back into proper state, and unlock |
| 767 | * resource. | 753 | * resource. |
| 768 | */ | 754 | */ |
| 769 | static | 755 | static int tsl2x7x_invoke_change(struct iio_dev *indio_dev) |
| 770 | int tsl2x7x_invoke_change(struct iio_dev *indio_dev) | ||
| 771 | { | 756 | { |
| 772 | struct tsl2X7X_chip *chip = iio_priv(indio_dev); | 757 | struct tsl2X7X_chip *chip = iio_priv(indio_dev); |
| 773 | int device_status = chip->tsl2x7x_chip_status; | 758 | int device_status = chip->tsl2x7x_chip_status; |
| @@ -791,9 +776,8 @@ unlock: · 17 unmodified lines | |||
| 791 | return ret; | 776 | return ret; |
| 792 | } | 777 | } |
| 793 | 778 | ||
| 794 | static | 779 | static void tsl2x7x_prox_calculate(int *data, int length, |
| 795 | void tsl2x7x_prox_calculate(int *data, int length, | 780 | struct tsl2x7x_prox_stat *statP) |
| 796 | struct tsl2x7x_prox_stat *statP) | ||
| 797 | { | 781 | { |
| 798 | int i; | 782 | int i; |
| 799 | int sample_sum; | 783 | int sample_sum; |
| @@ -837,25 +821,25 @@ static void tsl2x7x_prox_cal(struct iio_dev *indio_dev) · 37 unmodified lines | |||
| 837 | u8 tmp_irq_settings; | 821 | u8 tmp_irq_settings; |
| 838 | u8 current_state = chip->tsl2x7x_chip_status; | 822 | u8 current_state = chip->tsl2x7x_chip_status; |
| 839 | 823 | ||
| 840 | if (chip->tsl2x7x_settings.prox_max_samples_cal > MAX_SAMPLES_CAL) { | 824 | if (chip->settings.prox_max_samples_cal > MAX_SAMPLES_CAL) { |
| 841 | dev_err(&chip->client->dev, | 825 | dev_err(&chip->client->dev, |
| 842 | "max prox samples cal is too big: %d\n", | 826 | "max prox samples cal is too big: %d\n", |
| 843 | chip->tsl2x7x_settings.prox_max_samples_cal); | 827 | chip->settings.prox_max_samples_cal); |
| 844 | chip->tsl2x7x_settings.prox_max_samples_cal = MAX_SAMPLES_CAL; | 828 | chip->settings.prox_max_samples_cal = MAX_SAMPLES_CAL; |
| 845 | } | 829 | } |
| 846 | 830 | ||
| 847 | /* have to stop to change settings */ | 831 | /* have to stop to change settings */ |
| 848 | tsl2x7x_chip_off(indio_dev); | 832 | tsl2x7x_chip_off(indio_dev); |
| 849 | 833 | ||
| 850 | /* Enable proximity detection save just in case prox not wanted yet*/ | 834 | /* Enable proximity detection save just in case prox not wanted yet*/ |
| 851 | tmp_irq_settings = chip->tsl2x7x_settings.interrupts_en; | 835 | tmp_irq_settings = chip->settings.interrupts_en; |
| 852 | chip->tsl2x7x_settings.interrupts_en |= TSL2X7X_CNTL_PROX_INT_ENBL; | 836 | chip->settings.interrupts_en |= TSL2X7X_CNTL_PROX_INT_ENBL; |
| 853 | 837 | ||
| 854 | /*turn on device if not already on*/ | 838 | /*turn on device if not already on*/ |
| 855 | tsl2x7x_chip_on(indio_dev); | 839 | tsl2x7x_chip_on(indio_dev); |
| 856 | 840 | ||
| 857 | /*gather the samples*/ | 841 | /*gather the samples*/ |
| 858 | for (i = 0; i < chip->tsl2x7x_settings.prox_max_samples_cal; i++) { | 842 | for (i = 0; i < chip->settings.prox_max_samples_cal; i++) { |
| 859 | usleep_range(15000, 17500); | 843 | usleep_range(15000, 17500); |
| 860 | tsl2x7x_get_prox(indio_dev); | 844 | tsl2x7x_get_prox(indio_dev); |
| 861 | prox_history[i] = chip->prox_data; | 845 | prox_history[i] = chip->prox_data; |
| @@ -866,25 +850,25 @@ static void tsl2x7x_prox_cal(struct iio_dev *indio_dev) · 4 unmodified lines | |||
| 866 | tsl2x7x_chip_off(indio_dev); | 850 | tsl2x7x_chip_off(indio_dev); |
| 867 | calP = &prox_stat_data[PROX_STAT_CAL]; | 851 | calP = &prox_stat_data[PROX_STAT_CAL]; |
| 868 | tsl2x7x_prox_calculate(prox_history, | 852 | tsl2x7x_prox_calculate(prox_history, |
| 869 | chip->tsl2x7x_settings.prox_max_samples_cal, | 853 | chip->settings.prox_max_samples_cal, calP); |
| 870 | calP); | 854 | chip->settings.prox_thres_high = (calP->max << 1) - calP->mean; |
| 871 | chip->tsl2x7x_settings.prox_thres_high = (calP->max << 1) - calP->mean; | ||
| 872 | 855 | ||
| 873 | dev_info(&chip->client->dev, " cal min=%d mean=%d max=%d\n", | 856 | dev_info(&chip->client->dev, " cal min=%d mean=%d max=%d\n", |
| 874 | calP->min, calP->mean, calP->max); | 857 | calP->min, calP->mean, calP->max); |
| 875 | dev_info(&chip->client->dev, | 858 | dev_info(&chip->client->dev, |
| 876 | "%s proximity threshold set to %d\n", | 859 | "%s proximity threshold set to %d\n", |
| 877 | chip->client->name, chip->tsl2x7x_settings.prox_thres_high); | 860 | chip->client->name, chip->settings.prox_thres_high); |
| 878 | 861 | ||
| 879 | /* back to the way they were */ | 862 | /* back to the way they were */ |
| 880 | chip->tsl2x7x_settings.interrupts_en = tmp_irq_settings; | 863 | chip->settings.interrupts_en = tmp_irq_settings; |
| 881 | if (current_state == TSL2X7X_CHIP_WORKING) | 864 | if (current_state == TSL2X7X_CHIP_WORKING) |
| 882 | tsl2x7x_chip_on(indio_dev); | 865 | tsl2x7x_chip_on(indio_dev); |
| 883 | } | 866 | } |
| 884 | 867 | ||
| 885 | static ssize_t in_illuminance0_calibscale_available_show(struct device *dev, | 868 | static ssize_t |
| 886 | struct device_attribute *attr, | 869 | in_illuminance0_calibscale_available_show(struct device *dev, |
| 887 | char *buf) | 870 | struct device_attribute *attr, |
| 871 | char *buf) | ||
| 888 | { | 872 | { |
| 889 | struct tsl2X7X_chip *chip = iio_priv(dev_to_iio_dev(dev)); | 873 | struct tsl2X7X_chip *chip = iio_priv(dev_to_iio_dev(dev)); |
| 890 | 874 | ||
| @@ -900,69 +884,23 @@ static ssize_t in_illuminance0_calibscale_available_show(struct device *dev, · 9 unmodified lines | |||
| 900 | return snprintf(buf, PAGE_SIZE, "%s\n", "1 8 16 120"); | 884 | return snprintf(buf, PAGE_SIZE, "%s\n", "1 8 16 120"); |
| 901 | } | 885 | } |
| 902 | 886 | ||
| 903 | static ssize_t in_proximity0_calibscale_available_show(struct device *dev, | 887 | static IIO_CONST_ATTR(in_proximity0_calibscale_available, "1 2 4 8"); |
| 904 | struct device_attribute *attr, | ||
| 905 | char *buf) | ||
| 906 | { | ||
| 907 | return snprintf(buf, PAGE_SIZE, "%s\n", "1 2 4 8"); | ||
| 908 | } | ||
| 909 | |||
| 910 | static ssize_t in_illuminance0_integration_time_show(struct device *dev, | ||
| 911 | struct device_attribute *attr, | ||
| 912 | char *buf) | ||
| 913 | { | ||
| 914 | struct tsl2X7X_chip *chip = iio_priv(dev_to_iio_dev(dev)); | ||
| 915 | int y, z; | ||
| 916 | |||
| 917 | y = (TSL2X7X_MAX_TIMER_CNT - (u8)chip->tsl2x7x_settings.als_time) + 1; | ||
| 918 | z = y * TSL2X7X_MIN_ITIME; | ||
| 919 | y /= 1000; | ||
| 920 | z %= 1000; | ||
| 921 | |||
| 922 | return snprintf(buf, PAGE_SIZE, "%d.%03d\n", y, z); | ||
| 923 | } | ||
| 924 | |||
| 925 | static ssize_t in_illuminance0_integration_time_store(struct device *dev, | ||
| 926 | struct device_attribute *attr, | ||
| 927 | const char *buf, size_t len) | ||
| 928 | { | ||
| 929 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); | ||
| 930 | struct tsl2X7X_chip *chip = iio_priv(indio_dev); | ||
| 931 | struct tsl2x7x_parse_result result; | ||
| 932 | int ret; | ||
| 933 | |||
| 934 | ret = iio_str_to_fixpoint(buf, 100, &result.integer, &result.fract); | ||
| 935 | if (ret) | ||
| 936 | return ret; | ||
| 937 | |||
| 938 | result.fract /= 3; | ||
| 939 | chip->tsl2x7x_settings.als_time = | ||
| 940 | TSL2X7X_MAX_TIMER_CNT - (u8)result.fract; | ||
| 941 | |||
| 942 | dev_info(&chip->client->dev, "%s: als time = %d", | ||
| 943 | __func__, chip->tsl2x7x_settings.als_time); | ||
| 944 | |||
| 945 | tsl2x7x_invoke_change(indio_dev); | ||
| 946 | |||
| 947 | return IIO_VAL_INT_PLUS_MICRO; | ||
| 948 | } | ||
| 949 | 888 | ||
| 950 | static IIO_CONST_ATTR(in_illuminance0_integration_time_available, | 889 | static IIO_CONST_ATTR(in_illuminance0_integration_time_available, |
| 951 | ".00272 - .696"); | 890 | ".00272 - .696"); |
| 952 | 891 | ||
| 953 | static ssize_t in_illuminance0_target_input_show(struct device *dev, | 892 | static ssize_t in_illuminance0_target_input_show(struct device *dev, |
| 954 | struct device_attribute *attr, | 893 | struct device_attribute *attr, |
| 955 | char *buf) | 894 | char *buf) |
| 956 | { | 895 | { |
| 957 | struct tsl2X7X_chip *chip = iio_priv(dev_to_iio_dev(dev)); | 896 | struct tsl2X7X_chip *chip = iio_priv(dev_to_iio_dev(dev)); |
| 958 | 897 | ||
| 959 | return snprintf(buf, PAGE_SIZE, "%d\n", | 898 | return snprintf(buf, PAGE_SIZE, "%d\n", chip->settings.als_cal_target); |
| 960 | chip->tsl2x7x_settings.als_cal_target); | ||
| 961 | } | 899 | } |
| 962 | 900 | ||
| 963 | static ssize_t in_illuminance0_target_input_store(struct device *dev, | 901 | static ssize_t in_illuminance0_target_input_store(struct device *dev, |
| 964 | struct device_attribute *attr, | 902 | struct device_attribute *attr, |
| 965 | const char *buf, size_t len) | 903 | const char *buf, size_t len) |
| 966 | { | 904 | { |
| 967 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); | 905 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); |
| 968 | struct tsl2X7X_chip *chip = iio_priv(indio_dev); | 906 | struct tsl2X7X_chip *chip = iio_priv(indio_dev); |
| @@ -973,7 +911,7 @@ static ssize_t in_illuminance0_target_input_store(struct device *dev, · 4 unmodified lines | |||
| 973 | return -EINVAL; | 911 | return -EINVAL; |
| 974 | 912 | ||
| 975 | if (value) | 913 | if (value) |
| 976 | chip->tsl2x7x_settings.als_cal_target = value; | 914 | chip->settings.als_cal_target = value; |
| 977 | 915 | ||
| 978 | ret = tsl2x7x_invoke_change(indio_dev); | 916 | ret = tsl2x7x_invoke_change(indio_dev); |
| 979 | if (ret < 0) | 917 | if (ret < 0) |
| @@ -982,111 +920,9 @@ static ssize_t in_illuminance0_target_input_store(struct device *dev, · 2 unmodified lines | |||
| 982 | return len; | 920 | return len; |
| 983 | } | 921 | } |
| 984 | 922 | ||
| 985 | /* persistence settings */ | ||
| 986 | static ssize_t in_intensity0_thresh_period_show(struct device *dev, | ||
| 987 | struct device_attribute *attr, | ||
| 988 | char *buf) | ||
| 989 | { | ||
| 990 | struct tsl2X7X_chip *chip = iio_priv(dev_to_iio_dev(dev)); | ||
| 991 | int y, z, filter_delay; | ||
| 992 | |||
| 993 | /* Determine integration time */ | ||
| 994 | y = (TSL2X7X_MAX_TIMER_CNT - (u8)chip->tsl2x7x_settings.als_time) + 1; | ||
| 995 | z = y * TSL2X7X_MIN_ITIME; | ||
| 996 | filter_delay = z * (chip->tsl2x7x_settings.persistence & 0x0F); | ||
| 997 | y = filter_delay / 1000; | ||
| 998 | z = filter_delay % 1000; | ||
| 999 | |||
| 1000 | return snprintf(buf, PAGE_SIZE, "%d.%03d\n", y, z); | ||
| 1001 | } | ||
| 1002 | |||
| 1003 | static ssize_t in_intensity0_thresh_period_store(struct device *dev, | ||
| 1004 | struct device_attribute *attr, | ||
| 1005 | const char *buf, size_t len) | ||
| 1006 | { | ||
| 1007 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); | ||
| 1008 | struct tsl2X7X_chip *chip = iio_priv(indio_dev); | ||
| 1009 | struct tsl2x7x_parse_result result; | ||
| 1010 | int y, z, filter_delay; | ||
| 1011 | int ret; | ||
| 1012 | |||
| 1013 | ret = iio_str_to_fixpoint(buf, 100, &result.integer, &result.fract); | ||
| 1014 | if (ret) | ||
| 1015 | return ret; | ||
| 1016 | |||
| 1017 | y = (TSL2X7X_MAX_TIMER_CNT - (u8)chip->tsl2x7x_settings.als_time) + 1; | ||
| 1018 | z = y * TSL2X7X_MIN_ITIME; | ||
| 1019 | |||
| 1020 | filter_delay = | ||
| 1021 | DIV_ROUND_UP((result.integer * 1000) + result.fract, z); | ||
| 1022 | |||
| 1023 | chip->tsl2x7x_settings.persistence &= 0xF0; | ||
| 1024 | chip->tsl2x7x_settings.persistence |= (filter_delay & 0x0F); | ||
| 1025 | |||
| 1026 | dev_info(&chip->client->dev, "%s: als persistence = %d", | ||
| 1027 | __func__, filter_delay); | ||
| 1028 | |||
| 1029 | ret = tsl2x7x_invoke_change(indio_dev); | ||
| 1030 | if (ret < 0) | ||
| 1031 | return ret; | ||
| 1032 | |||
| 1033 | return IIO_VAL_INT_PLUS_MICRO; | ||
| 1034 | } | ||
| 1035 | |||
| 1036 | static ssize_t in_proximity0_thresh_period_show(struct device *dev, | ||
| 1037 | struct device_attribute *attr, | ||
| 1038 | char *buf) | ||
| 1039 | { | ||
| 1040 | struct tsl2X7X_chip *chip = iio_priv(dev_to_iio_dev(dev)); | ||
| 1041 | int y, z, filter_delay; | ||
| 1042 | |||
| 1043 | /* Determine integration time */ | ||
| 1044 | y = (TSL2X7X_MAX_TIMER_CNT - (u8)chip->tsl2x7x_settings.prx_time) + 1; | ||
| 1045 | z = y * TSL2X7X_MIN_ITIME; | ||
| 1046 | filter_delay = z * ((chip->tsl2x7x_settings.persistence & 0xF0) >> 4); | ||
| 1047 | y = filter_delay / 1000; | ||
| 1048 | z = filter_delay % 1000; | ||
| 1049 | |||
| 1050 | return snprintf(buf, PAGE_SIZE, "%d.%03d\n", y, z); | ||
| 1051 | } | ||
| 1052 | |||
| 1053 | static ssize_t in_proximity0_thresh_period_store(struct device *dev, | ||
| 1054 | struct device_attribute *attr, | ||
| 1055 | const char *buf, size_t len) | ||
| 1056 | { | ||
| 1057 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); | ||
| 1058 | struct tsl2X7X_chip *chip = iio_priv(indio_dev); | ||
| 1059 | struct tsl2x7x_parse_result result; | ||
| 1060 | int y, z, filter_delay; | ||
| 1061 | int ret; | ||
| 1062 | |||
| 1063 | ret = iio_str_to_fixpoint(buf, 100, &result.integer, &result.fract); | ||
| 1064 | if (ret) | ||
| 1065 | return ret; | ||
| 1066 | |||
| 1067 | y = (TSL2X7X_MAX_TIMER_CNT - (u8)chip->tsl2x7x_settings.prx_time) + 1; | ||
| 1068 | z = y * TSL2X7X_MIN_ITIME; | ||
| 1069 | |||
| 1070 | filter_delay = | ||
| 1071 | DIV_ROUND_UP((result.integer * 1000) + result.fract, z); | ||
| 1072 | |||
| 1073 | chip->tsl2x7x_settings.persistence &= 0x0F; | ||
| 1074 | chip->tsl2x7x_settings.persistence |= ((filter_delay << 4) & 0xF0); | ||
| 1075 | |||
| 1076 | dev_info(&chip->client->dev, "%s: prox persistence = %d", | ||
| 1077 | __func__, filter_delay); | ||
| 1078 | |||
| 1079 | ret = tsl2x7x_invoke_change(indio_dev); | ||
| 1080 | if (ret < 0) | ||
| 1081 | return ret; | ||
| 1082 | |||
| 1083 | |||
| 1084 | return IIO_VAL_INT_PLUS_MICRO; | ||
| 1085 | } | ||
| 1086 | |||
| 1087 | static ssize_t in_illuminance0_calibrate_store(struct device *dev, | 923 | static ssize_t in_illuminance0_calibrate_store(struct device *dev, |
| 1088 | struct device_attribute *attr, | 924 | struct device_attribute *attr, |
| 1089 | const char *buf, size_t len) | 925 | const char *buf, size_t len) |
| 1090 | { | 926 | { |
| 1091 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); | 927 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); |
| 1092 | bool value; | 928 | bool value; |
| @@ -1106,14 +942,14 @@ static ssize_t in_illuminance0_calibrate_store(struct device *dev, · 13 unmodified lines | |||
| 1106 | } | 942 | } |
| 1107 | 943 | ||
| 1108 | static ssize_t in_illuminance0_lux_table_show(struct device *dev, | 944 | static ssize_t in_illuminance0_lux_table_show(struct device *dev, |
| 1109 | struct device_attribute *attr, | 945 | struct device_attribute *attr, |
| 1110 | char *buf) | 946 | char *buf) |
| 1111 | { | 947 | { |
| 1112 | struct tsl2X7X_chip *chip = iio_priv(dev_to_iio_dev(dev)); | 948 | struct tsl2X7X_chip *chip = iio_priv(dev_to_iio_dev(dev)); |
| 1113 | int i = 0; | 949 | int i = 0; |
| 1114 | int offset = 0; | 950 | int offset = 0; |
| 1115 | 951 | ||
| 1116 | while (i < (TSL2X7X_MAX_LUX_TABLE_SIZE * 3)) { | 952 | while (i < TSL2X7X_MAX_LUX_TABLE_SIZE) { |
| 1117 | offset += snprintf(buf + offset, PAGE_SIZE, "%u,%u,%u,", | 953 | offset += snprintf(buf + offset, PAGE_SIZE, "%u,%u,%u,", |
| 1118 | chip->tsl2x7x_device_lux[i].ratio, | 954 | chip->tsl2x7x_device_lux[i].ratio, |
| 1119 | chip->tsl2x7x_device_lux[i].ch0, | 955 | chip->tsl2x7x_device_lux[i].ch0, |
| @@ -1134,8 +970,8 @@ static ssize_t in_illuminance0_lux_table_show(struct device *dev, · 14 unmodified lines | |||
| 1134 | } | 970 | } |
| 1135 | 971 | ||
| 1136 | static ssize_t in_illuminance0_lux_table_store(struct device *dev, | 972 | static ssize_t in_illuminance0_lux_table_store(struct device *dev, |
| 1137 | struct device_attribute *attr, | 973 | struct device_attribute *attr, |
| 1138 | const char *buf, size_t len) | 974 | const char *buf, size_t len) |
| 1139 | { | 975 | { |
| 1140 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); | 976 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); |
| 1141 | struct tsl2X7X_chip *chip = iio_priv(indio_dev); | 977 | struct tsl2X7X_chip *chip = iio_priv(indio_dev); |
| @@ -1176,8 +1012,8 @@ static ssize_t in_illuminance0_lux_table_store(struct device *dev, · 34 unmodified lines | |||
| 1176 | } | 1012 | } |
| 1177 | 1013 | ||
| 1178 | static ssize_t in_proximity0_calibrate_store(struct device *dev, | 1014 | static ssize_t in_proximity0_calibrate_store(struct device *dev, |
| 1179 | struct device_attribute *attr, | 1015 | struct device_attribute *attr, |
| 1180 | const char *buf, size_t len) | 1016 | const char *buf, size_t len) |
| 1181 | { | 1017 | { |
| 1182 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); | 1018 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); |
| 1183 | bool value; | 1019 | bool value; |
| @@ -1205,9 +1041,9 @@ static int tsl2x7x_read_interrupt_config(struct iio_dev *indio_dev, · 21 unmodified lines | |||
| 1205 | int ret; | 1041 | int ret; |
| 1206 | 1042 | ||
| 1207 | if (chan->type == IIO_INTENSITY) | 1043 | if (chan->type == IIO_INTENSITY) |
| 1208 | ret = !!(chip->tsl2x7x_settings.interrupts_en & 0x10); | 1044 | ret = !!(chip->settings.interrupts_en & 0x10); |
| 1209 | else | 1045 | else |
| 1210 | ret = !!(chip->tsl2x7x_settings.interrupts_en & 0x20); | 1046 | ret = !!(chip->settings.interrupts_en & 0x20); |
| 1211 | 1047 | ||
| 1212 | return ret; | 1048 | return ret; |
| 1213 | } | 1049 | } |
| @@ -1223,14 +1059,14 @@ static int tsl2x7x_write_interrupt_config(struct iio_dev *indio_dev, · 9 unmodified lines | |||
| 1223 | 1059 | ||
| 1224 | if (chan->type == IIO_INTENSITY) { | 1060 | if (chan->type == IIO_INTENSITY) { |
| 1225 | if (val) | 1061 | if (val) |
| 1226 | chip->tsl2x7x_settings.interrupts_en |= 0x10; | 1062 | chip->settings.interrupts_en |= 0x10; |
| 1227 | else | 1063 | else |
| 1228 | chip->tsl2x7x_settings.interrupts_en &= 0x20; | 1064 | chip->settings.interrupts_en &= 0x20; |
| 1229 | } else { | 1065 | } else { |
| 1230 | if (val) | 1066 | if (val) |
| 1231 | chip->tsl2x7x_settings.interrupts_en |= 0x20; | 1067 | chip->settings.interrupts_en |= 0x20; |
| 1232 | else | 1068 | else |
| 1233 | chip->tsl2x7x_settings.interrupts_en &= 0x10; | 1069 | chip->settings.interrupts_en &= 0x10; |
| 1234 | } | 1070 | } |
| 1235 | 1071 | ||
| 1236 | ret = tsl2x7x_invoke_change(indio_dev); | 1072 | ret = tsl2x7x_invoke_change(indio_dev); |
| @@ -1248,18 +1084,19 @@ static int tsl2x7x_write_event_value(struct iio_dev *indio_dev, · 11 unmodified lines | |||
| 1248 | int val, int val2) | 1084 | int val, int val2) |
| 1249 | { | 1085 | { |
| 1250 | struct tsl2X7X_chip *chip = iio_priv(indio_dev); | 1086 | struct tsl2X7X_chip *chip = iio_priv(indio_dev); |
| 1251 | int ret = -EINVAL; | 1087 | int ret = -EINVAL, y, z, filter_delay; |
| 1088 | u8 time; | ||
| 1252 | 1089 | ||
| 1253 | switch (info) { | 1090 | switch (info) { |
| 1254 | case IIO_EV_INFO_VALUE: | 1091 | case IIO_EV_INFO_VALUE: |
| 1255 | if (chan->type == IIO_INTENSITY) { | 1092 | if (chan->type == IIO_INTENSITY) { |
| 1256 | switch (dir) { | 1093 | switch (dir) { |
| 1257 | case IIO_EV_DIR_RISING: | 1094 | case IIO_EV_DIR_RISING: |
| 1258 | chip->tsl2x7x_settings.als_thresh_high = val; | 1095 | chip->settings.als_thresh_high = val; |
| 1259 | ret = 0; | 1096 | ret = 0; |
| 1260 | break; | 1097 | break; |
| 1261 | case IIO_EV_DIR_FALLING: | 1098 | case IIO_EV_DIR_FALLING: |
| 1262 | chip->tsl2x7x_settings.als_thresh_low = val; | 1099 | chip->settings.als_thresh_low = val; |
| 1263 | ret = 0; | 1100 | ret = 0; |
| 1264 | break; | 1101 | break; |
| 1265 | default: | 1102 | default: |
| @@ -1268,11 +1105,11 @@ static int tsl2x7x_write_event_value(struct iio_dev *indio_dev, · 2 unmodified lines | |||
| 1268 | } else { | 1105 | } else { |
| 1269 | switch (dir) { | 1106 | switch (dir) { |
| 1270 | case IIO_EV_DIR_RISING: | 1107 | case IIO_EV_DIR_RISING: |
| 1271 | chip->tsl2x7x_settings.prox_thres_high = val; | 1108 | chip->settings.prox_thres_high = val; |
| 1272 | ret = 0; | 1109 | ret = 0; |
| 1273 | break; | 1110 | break; |
| 1274 | case IIO_EV_DIR_FALLING: | 1111 | case IIO_EV_DIR_FALLING: |
| 1275 | chip->tsl2x7x_settings.prox_thres_low = val; | 1112 | chip->settings.prox_thres_low = val; |
| 1276 | ret = 0; | 1113 | ret = 0; |
| 1277 | break; | 1114 | break; |
| 1278 | default: | 1115 | default: |
| @@ -1280,6 +1117,33 @@ static int tsl2x7x_write_event_value(struct iio_dev *indio_dev, · 1 unmodified line | |||
| 1280 | } | 1117 | } |
| 1281 | } | 1118 | } |
| 1282 | break; | 1119 | break; |
| 1120 | case IIO_EV_INFO_PERIOD: | ||
| 1121 | if (chan->type == IIO_INTENSITY) | ||
| 1122 | time = chip->settings.als_time; | ||
| 1123 | else | ||
| 1124 | time = chip->settings.prx_time; | ||
| 1125 | |||
| 1126 | y = (TSL2X7X_MAX_TIMER_CNT - time) + 1; | ||
| 1127 | z = y * TSL2X7X_MIN_ITIME; | ||
| 1128 | |||
| 1129 | filter_delay = DIV_ROUND_UP((val * 1000) + val2, z); | ||
| 1130 | |||
| 1131 | if (chan->type == IIO_INTENSITY) { | ||
| 1132 | chip->settings.persistence &= 0xF0; | ||
| 1133 | chip->settings.persistence |= | ||
| 1134 | (filter_delay & 0x0F); | ||
| 1135 | dev_info(&chip->client->dev, "%s: ALS persistence = %d", | ||
| 1136 | __func__, filter_delay); | ||
| 1137 | } else { | ||
| 1138 | chip->settings.persistence &= 0x0F; | ||
| 1139 | chip->settings.persistence |= | ||
| 1140 | ((filter_delay << 4) & 0xF0); | ||
| 1141 | dev_info(&chip->client->dev, | ||
| 1142 | "%s: Proximity persistence = %d", | ||
| 1143 | __func__, filter_delay); | ||
| 1144 | } | ||
| 1145 | ret = 0; | ||
| 1146 | break; | ||
| 1283 | default: | 1147 | default: |
| 1284 | break; | 1148 | break; |
| 1285 | } | 1149 | } |
| @@ -1298,18 +1162,19 @@ static int tsl2x7x_read_event_value(struct iio_dev *indio_dev, · 12 unmodified lines | |||
| 1298 | int *val, int *val2) | 1162 | int *val, int *val2) |
| 1299 | { | 1163 | { |
| 1300 | struct tsl2X7X_chip *chip = iio_priv(indio_dev); | 1164 | struct tsl2X7X_chip *chip = iio_priv(indio_dev); |
| 1301 | int ret = -EINVAL; | 1165 | int ret = -EINVAL, filter_delay, mult; |
| 1166 | u8 time; | ||
| 1302 | 1167 | ||
| 1303 | switch (info) { | 1168 | switch (info) { |
| 1304 | case IIO_EV_INFO_VALUE: | 1169 | case IIO_EV_INFO_VALUE: |
| 1305 | if (chan->type == IIO_INTENSITY) { | 1170 | if (chan->type == IIO_INTENSITY) { |
| 1306 | switch (dir) { | 1171 | switch (dir) { |
| 1307 | case IIO_EV_DIR_RISING: | 1172 | case IIO_EV_DIR_RISING: |
| 1308 | *val = chip->tsl2x7x_settings.als_thresh_high; | 1173 | *val = chip->settings.als_thresh_high; |
| 1309 | ret = IIO_VAL_INT; | 1174 | ret = IIO_VAL_INT; |
| 1310 | break; | 1175 | break; |
| 1311 | case IIO_EV_DIR_FALLING: | 1176 | case IIO_EV_DIR_FALLING: |
| 1312 | *val = chip->tsl2x7x_settings.als_thresh_low; | 1177 | *val = chip->settings.als_thresh_low; |
| 1313 | ret = IIO_VAL_INT; | 1178 | ret = IIO_VAL_INT; |
| 1314 | break; | 1179 | break; |
| 1315 | default: | 1180 | default: |
| @@ -1318,11 +1183,11 @@ static int tsl2x7x_read_event_value(struct iio_dev *indio_dev, · 2 unmodified lines | |||
| 1318 | } else { | 1183 | } else { |
| 1319 | switch (dir) { | 1184 | switch (dir) { |
| 1320 | case IIO_EV_DIR_RISING: | 1185 | case IIO_EV_DIR_RISING: |
| 1321 | *val = chip->tsl2x7x_settings.prox_thres_high; | 1186 | *val = chip->settings.prox_thres_high; |
| 1322 | ret = IIO_VAL_INT; | 1187 | ret = IIO_VAL_INT; |
| 1323 | break; | 1188 | break; |
| 1324 | case IIO_EV_DIR_FALLING: | 1189 | case IIO_EV_DIR_FALLING: |
| 1325 | *val = chip->tsl2x7x_settings.prox_thres_low; | 1190 | *val = chip->settings.prox_thres_low; |
| 1326 | ret = IIO_VAL_INT; | 1191 | ret = IIO_VAL_INT; |
| 1327 | break; | 1192 | break; |
| 1328 | default: | 1193 | default: |
| @@ -1330,6 +1195,23 @@ static int tsl2x7x_read_event_value(struct iio_dev *indio_dev, · 1 unmodified line | |||
| 1330 | } | 1195 | } |
| 1331 | } | 1196 | } |
| 1332 | break; | 1197 | break; |
| 1198 | case IIO_EV_INFO_PERIOD: | ||
| 1199 | if (chan->type == IIO_INTENSITY) { | ||
| 1200 | time = chip->settings.als_time; | ||
| 1201 | mult = chip->settings.persistence & 0x0F; | ||
| 1202 | } else { | ||
| 1203 | time = chip->settings.prx_time; | ||
| 1204 | mult = (chip->settings.persistence & 0xF0) >> 4; | ||
| 1205 | } | ||
| 1206 | |||
| 1207 | /* Determine integration time */ | ||
| 1208 | *val = (TSL2X7X_MAX_TIMER_CNT - time) + 1; | ||
| 1209 | *val2 = *val * TSL2X7X_MIN_ITIME; | ||
| 1210 | filter_delay = *val2 * mult; | ||
| 1211 | *val = filter_delay / 1000; | ||
| 1212 | *val2 = filter_delay % 1000; | ||
| 1213 | ret = IIO_VAL_INT_PLUS_MICRO; | ||
| 1214 | break; | ||
| 1333 | default: | 1215 | default: |
| 1334 | break; | 1216 | break; |
| 1335 | } | 1217 | } |
| @@ -1379,18 +1261,20 @@ static int tsl2x7x_read_raw(struct iio_dev *indio_dev, · 43 unmodified lines | |||
| 1379 | break; | 1261 | break; |
| 1380 | case IIO_CHAN_INFO_CALIBSCALE: | 1262 | case IIO_CHAN_INFO_CALIBSCALE: |
| 1381 | if (chan->type == IIO_LIGHT) | 1263 | if (chan->type == IIO_LIGHT) |
| 1382 | *val = | 1264 | *val = tsl2x7x_als_gain[chip->settings.als_gain]; |
| 1383 | tsl2X7X_als_gainadj[chip->tsl2x7x_settings.als_gain]; | ||
| 1384 | else | 1265 | else |
| 1385 | *val = | 1266 | *val = tsl2x7x_prx_gain[chip->settings.prox_gain]; |
| 1386 | tsl2X7X_prx_gainadj[chip->tsl2x7x_settings.prox_gain]; | ||
| 1387 | ret = IIO_VAL_INT; | 1267 | ret = IIO_VAL_INT; |
| 1388 | break; | 1268 | break; |
| 1389 | case IIO_CHAN_INFO_CALIBBIAS: | 1269 | case IIO_CHAN_INFO_CALIBBIAS: |
| 1390 | *val = chip->tsl2x7x_settings.als_gain_trim; | 1270 | *val = chip->settings.als_gain_trim; |
| 1391 | ret = IIO_VAL_INT; | 1271 | ret = IIO_VAL_INT; |
| 1392 | break; | 1272 | break; |
| 1393 | 1273 | case IIO_CHAN_INFO_INT_TIME: | |
| 1274 | *val = (TSL2X7X_MAX_TIMER_CNT - chip->settings.als_time) + 1; | ||
| 1275 | *val2 = ((*val * TSL2X7X_MIN_ITIME) % 1000) / 1000; | ||
| 1276 | ret = IIO_VAL_INT_PLUS_MICRO; | ||
| 1277 | break; | ||
| 1394 | default: | 1278 | default: |
| 1395 | ret = -EINVAL; | 1279 | ret = -EINVAL; |
| 1396 | } | 1280 | } |
| @@ -1411,13 +1295,13 @@ static int tsl2x7x_write_raw(struct iio_dev *indio_dev, · 14 unmodified lines | |||
| 1411 | if (chan->type == IIO_INTENSITY) { | 1295 | if (chan->type == IIO_INTENSITY) { |
| 1412 | switch (val) { | 1296 | switch (val) { |
| 1413 | case 1: | 1297 | case 1: |
| 1414 | chip->tsl2x7x_settings.als_gain = 0; | 1298 | chip->settings.als_gain = 0; |
| 1415 | break; | 1299 | break; |
| 1416 | case 8: | 1300 | case 8: |
| 1417 | chip->tsl2x7x_settings.als_gain = 1; | 1301 | chip->settings.als_gain = 1; |
| 1418 | break; | 1302 | break; |
| 1419 | case 16: | 1303 | case 16: |
| 1420 | chip->tsl2x7x_settings.als_gain = 2; | 1304 | chip->settings.als_gain = 2; |
| 1421 | break; | 1305 | break; |
| 1422 | case 120: | 1306 | case 120: |
| 1423 | switch (chip->id) { | 1307 | switch (chip->id) { |
| @@ -1428,7 +1312,7 @@ static int tsl2x7x_write_raw(struct iio_dev *indio_dev, · 4 unmodified lines | |||
| 1428 | case tmd2772: | 1312 | case tmd2772: |
| 1429 | return -EINVAL; | 1313 | return -EINVAL; |
| 1430 | } | 1314 | } |
| 1431 | chip->tsl2x7x_settings.als_gain = 3; | 1315 | chip->settings.als_gain = 3; |
| 1432 | break; | 1316 | break; |
| 1433 | case 128: | 1317 | case 128: |
| 1434 | switch (chip->id) { | 1318 | switch (chip->id) { |
| @@ -1439,7 +1323,7 @@ static int tsl2x7x_write_raw(struct iio_dev *indio_dev, · 4 unmodified lines | |||
| 1439 | case tmd2771: | 1323 | case tmd2771: |
| 1440 | return -EINVAL; | 1324 | return -EINVAL; |
| 1441 | } | 1325 | } |
| 1442 | chip->tsl2x7x_settings.als_gain = 3; | 1326 | chip->settings.als_gain = 3; |
| 1443 | break; | 1327 | break; |
| 1444 | default: | 1328 | default: |
| 1445 | return -EINVAL; | 1329 | return -EINVAL; |
| @@ -1447,16 +1331,16 @@ static int tsl2x7x_write_raw(struct iio_dev *indio_dev, · 1 unmodified line | |||
| 1447 | } else { | 1331 | } else { |
| 1448 | switch (val) { | 1332 | switch (val) { |
| 1449 | case 1: | 1333 | case 1: |
| 1450 | chip->tsl2x7x_settings.prox_gain = 0; | 1334 | chip->settings.prox_gain = 0; |
| 1451 | break; | 1335 | break; |
| 1452 | case 2: | 1336 | case 2: |
| 1453 | chip->tsl2x7x_settings.prox_gain = 1; | 1337 | chip->settings.prox_gain = 1; |
| 1454 | break; | 1338 | break; |
| 1455 | case 4: | 1339 | case 4: |
| 1456 | chip->tsl2x7x_settings.prox_gain = 2; | 1340 | chip->settings.prox_gain = 2; |
| 1457 | break; | 1341 | break; |
| 1458 | case 8: | 1342 | case 8: |
| 1459 | chip->tsl2x7x_settings.prox_gain = 3; | 1343 | chip->settings.prox_gain = 3; |
| 1460 | break; | 1344 | break; |
| 1461 | default: | 1345 | default: |
| 1462 | return -EINVAL; | 1346 | return -EINVAL; |
| @@ -1464,9 +1348,15 @@ static int tsl2x7x_write_raw(struct iio_dev *indio_dev, · 1 unmodified line | |||
| 1464 | } | 1348 | } |
| 1465 | break; | 1349 | break; |
| 1466 | case IIO_CHAN_INFO_CALIBBIAS: | 1350 | case IIO_CHAN_INFO_CALIBBIAS: |
| 1467 | chip->tsl2x7x_settings.als_gain_trim = val; | 1351 | chip->settings.als_gain_trim = val; |
| 1468 | break; | 1352 | break; |
| 1353 | case IIO_CHAN_INFO_INT_TIME: | ||
| 1354 | chip->settings.als_time = | ||
| 1355 | TSL2X7X_MAX_TIMER_CNT - (val2 / TSL2X7X_MIN_ITIME); | ||
| 1469 | 1356 | ||
| 1357 | dev_info(&chip->client->dev, "%s: als time = %d", | ||
| 1358 | __func__, chip->settings.als_time); | ||
| 1359 | break; | ||
| 1470 | default: | 1360 | default: |
| 1471 | return -EINVAL; | 1361 | return -EINVAL; |
| 1472 | } | 1362 | } |
| @@ -1474,12 +1364,8 @@ static int tsl2x7x_write_raw(struct iio_dev *indio_dev, · 1 unmodified line | |||
| 1474 | return tsl2x7x_invoke_change(indio_dev); | 1364 | return tsl2x7x_invoke_change(indio_dev); |
| 1475 | } | 1365 | } |
| 1476 | 1366 | ||
| 1477 | static DEVICE_ATTR_RO(in_proximity0_calibscale_available); | ||
| 1478 | |||
| 1479 | static DEVICE_ATTR_RO(in_illuminance0_calibscale_available); | 1367 | static DEVICE_ATTR_RO(in_illuminance0_calibscale_available); |
| 1480 | 1368 | ||
| 1481 | static DEVICE_ATTR_RW(in_illuminance0_integration_time); | ||
| 1482 | |||
| 1483 | static DEVICE_ATTR_RW(in_illuminance0_target_input); | 1369 | static DEVICE_ATTR_RW(in_illuminance0_target_input); |
| 1484 | 1370 | ||
| 1485 | static DEVICE_ATTR_WO(in_illuminance0_calibrate); | 1371 | static DEVICE_ATTR_WO(in_illuminance0_calibrate); |
| @@ -1488,10 +1374,6 @@ static DEVICE_ATTR_WO(in_proximity0_calibrate); · 2 unmodified lines | |||
| 1488 | 1374 | ||
| 1489 | static DEVICE_ATTR_RW(in_illuminance0_lux_table); | 1375 | static DEVICE_ATTR_RW(in_illuminance0_lux_table); |
| 1490 | 1376 | ||
| 1491 | static DEVICE_ATTR_RW(in_intensity0_thresh_period); | ||
| 1492 | |||
| 1493 | static DEVICE_ATTR_RW(in_proximity0_thresh_period); | ||
| 1494 | |||
| 1495 | /* Use the default register values to identify the Taos device */ | 1377 | /* Use the default register values to identify the Taos device */ |
| 1496 | static int tsl2x7x_device_id(int *id, int target) | 1378 | static int tsl2x7x_device_id(int *id, int target) |
| 1497 | { | 1379 | { |
| @@ -1559,7 +1441,6 @@ static irqreturn_t tsl2x7x_event_handler(int irq, void *private) · 61 unmodified lines | |||
| 1559 | 1441 | ||
| 1560 | static struct attribute *tsl2x7x_ALS_device_attrs[] = { | 1442 | static struct attribute *tsl2x7x_ALS_device_attrs[] = { |
| 1561 | &dev_attr_in_illuminance0_calibscale_available.attr, | 1443 | &dev_attr_in_illuminance0_calibscale_available.attr, |
| 1562 | &dev_attr_in_illuminance0_integration_time.attr, | ||
| 1563 | &iio_const_attr_in_illuminance0_integration_time_available.dev_attr.attr, | 1444 | &iio_const_attr_in_illuminance0_integration_time_available.dev_attr.attr, |
| 1564 | &dev_attr_in_illuminance0_target_input.attr, | 1445 | &dev_attr_in_illuminance0_target_input.attr, |
| 1565 | &dev_attr_in_illuminance0_calibrate.attr, | 1446 | &dev_attr_in_illuminance0_calibrate.attr, |
| @@ -1574,49 +1455,31 @@ static struct attribute *tsl2x7x_PRX_device_attrs[] = { · 8 unmodified lines | |||
| 1574 | 1455 | ||
| 1575 | static struct attribute *tsl2x7x_ALSPRX_device_attrs[] = { | 1456 | static struct attribute *tsl2x7x_ALSPRX_device_attrs[] = { |
| 1576 | &dev_attr_in_illuminance0_calibscale_available.attr, | 1457 | &dev_attr_in_illuminance0_calibscale_available.attr, |
| 1577 | &dev_attr_in_illuminance0_integration_time.attr, | ||
| 1578 | &iio_const_attr_in_illuminance0_integration_time_available.dev_attr.attr, | 1458 | &iio_const_attr_in_illuminance0_integration_time_available.dev_attr.attr, |
| 1579 | &dev_attr_in_illuminance0_target_input.attr, | 1459 | &dev_attr_in_illuminance0_target_input.attr, |
| 1580 | &dev_attr_in_illuminance0_calibrate.attr, | 1460 | &dev_attr_in_illuminance0_calibrate.attr, |
| 1581 | &dev_attr_in_illuminance0_lux_table.attr, | 1461 | &dev_attr_in_illuminance0_lux_table.attr, |
| 1582 | &dev_attr_in_proximity0_calibrate.attr, | 1462 | &iio_const_attr_in_proximity0_calibscale_available.dev_attr.attr, |
| 1583 | NULL | 1463 | NULL |
| 1584 | }; | 1464 | }; |
| 1585 | 1465 | ||
| 1586 | static struct attribute *tsl2x7x_PRX2_device_attrs[] = { | 1466 | static struct attribute *tsl2x7x_PRX2_device_attrs[] = { |
| 1587 | &dev_attr_in_proximity0_calibrate.attr, | 1467 | &dev_attr_in_proximity0_calibrate.attr, |
| 1588 | &dev_attr_in_proximity0_calibscale_available.attr, | 1468 | &iio_const_attr_in_proximity0_calibscale_available.dev_attr.attr, |
| 1589 | NULL | 1469 | NULL |
| 1590 | }; | 1470 | }; |
| 1591 | 1471 | ||
| 1592 | static struct attribute *tsl2x7x_ALSPRX2_device_attrs[] = { | 1472 | static struct attribute *tsl2x7x_ALSPRX2_device_attrs[] = { |
| 1593 | &dev_attr_in_illuminance0_calibscale_available.attr, | 1473 | &dev_attr_in_illuminance0_calibscale_available.attr, |
| 1594 | &dev_attr_in_illuminance0_integration_time.attr, | ||
| 1595 | &iio_const_attr_in_illuminance0_integration_time_available.dev_attr.attr, | 1474 | &iio_const_attr_in_illuminance0_integration_time_available.dev_attr.attr, |
| 1596 | &dev_attr_in_illuminance0_target_input.attr, | 1475 | &dev_attr_in_illuminance0_target_input.attr, |
| 1597 | &dev_attr_in_illuminance0_calibrate.attr, | 1476 | &dev_attr_in_illuminance0_calibrate.attr, |
| 1598 | &dev_attr_in_illuminance0_lux_table.attr, | 1477 | &dev_attr_in_illuminance0_lux_table.attr, |
| 1599 | &dev_attr_in_proximity0_calibrate.attr, | 1478 | &dev_attr_in_proximity0_calibrate.attr, |
| 1600 | &dev_attr_in_proximity0_calibscale_available.attr, | 1479 | &iio_const_attr_in_proximity0_calibscale_available.dev_attr.attr, |
| 1601 | NULL | 1480 | NULL |
| 1602 | }; | 1481 | }; |
| 1603 | 1482 | ||
| 1604 | static struct attribute *tsl2X7X_ALS_event_attrs[] = { | ||
| 1605 | &dev_attr_in_intensity0_thresh_period.attr, | ||
| 1606 | NULL, | ||
| 1607 | }; | ||
| 1608 | |||
| 1609 | static struct attribute *tsl2X7X_PRX_event_attrs[] = { | ||
| 1610 | &dev_attr_in_proximity0_thresh_period.attr, | ||
| 1611 | NULL, | ||
| 1612 | }; | ||
| 1613 | |||
| 1614 | static struct attribute *tsl2X7X_ALSPRX_event_attrs[] = { | ||
| 1615 | &dev_attr_in_intensity0_thresh_period.attr, | ||
| 1616 | &dev_attr_in_proximity0_thresh_period.attr, | ||
| 1617 | NULL, | ||
| 1618 | }; | ||
| 1619 | |||
| 1620 | static const struct attribute_group tsl2X7X_device_attr_group_tbl[] = { | 1483 | static const struct attribute_group tsl2X7X_device_attr_group_tbl[] = { |
| 1621 | [ALS] = { | 1484 | [ALS] = { |
| 1622 | .attrs = tsl2x7x_ALS_device_attrs, | 1485 | .attrs = tsl2x7x_ALS_device_attrs, |
| @@ -1635,26 +1498,9 @@ static const struct attribute_group tsl2X7X_device_attr_group_tbl[] = { · 12 unmodified lines | |||
| 1635 | }, | 1498 | }, |
| 1636 | }; | 1499 | }; |
| 1637 | 1500 | ||
| 1638 | static const struct attribute_group tsl2X7X_event_attr_group_tbl[] = { | ||
| 1639 | [ALS] = { | ||
| 1640 | .attrs = tsl2X7X_ALS_event_attrs, | ||
| 1641 | .name = "events", | ||
| 1642 | }, | ||
| 1643 | [PRX] = { | ||
| 1644 | .attrs = tsl2X7X_PRX_event_attrs, | ||
| 1645 | .name = "events", | ||
| 1646 | }, | ||
| 1647 | [ALSPRX] = { | ||
| 1648 | .attrs = tsl2X7X_ALSPRX_event_attrs, | ||
| 1649 | .name = "events", | ||
| 1650 | }, | ||
| 1651 | }; | ||
| 1652 | |||
| 1653 | static const struct iio_info tsl2X7X_device_info[] = { | 1501 | static const struct iio_info tsl2X7X_device_info[] = { |
| 1654 | [ALS] = { | 1502 | [ALS] = { |
| 1655 | .attrs = &tsl2X7X_device_attr_group_tbl[ALS], | 1503 | .attrs = &tsl2X7X_device_attr_group_tbl[ALS], |
| 1656 | .event_attrs = &tsl2X7X_event_attr_group_tbl[ALS], | ||
| 1657 | .driver_module = THIS_MODULE, | ||
| 1658 | .read_raw = &tsl2x7x_read_raw, | 1504 | .read_raw = &tsl2x7x_read_raw, |
| 1659 | .write_raw = &tsl2x7x_write_raw, | 1505 | .write_raw = &tsl2x7x_write_raw, |
| 1660 | .read_event_value = &tsl2x7x_read_event_value, | 1506 | .read_event_value = &tsl2x7x_read_event_value, |
| @@ -1664,8 +1510,6 @@ static const struct iio_info tsl2X7X_device_info[] = { · 3 unmodified lines | |||
| 1664 | }, | 1510 | }, |
| 1665 | [PRX] = { | 1511 | [PRX] = { |
| 1666 | .attrs = &tsl2X7X_device_attr_group_tbl[PRX], | 1512 | .attrs = &tsl2X7X_device_attr_group_tbl[PRX], |
| 1667 | .event_attrs = &tsl2X7X_event_attr_group_tbl[PRX], | ||
| 1668 | .driver_module = THIS_MODULE, | ||
| 1669 | .read_raw = &tsl2x7x_read_raw, | 1513 | .read_raw = &tsl2x7x_read_raw, |
| 1670 | .write_raw = &tsl2x7x_write_raw, | 1514 | .write_raw = &tsl2x7x_write_raw, |
| 1671 | .read_event_value = &tsl2x7x_read_event_value, | 1515 | .read_event_value = &tsl2x7x_read_event_value, |
| @@ -1675,8 +1519,6 @@ static const struct iio_info tsl2X7X_device_info[] = { · 3 unmodified lines | |||
| 1675 | }, | 1519 | }, |
| 1676 | [ALSPRX] = { | 1520 | [ALSPRX] = { |
| 1677 | .attrs = &tsl2X7X_device_attr_group_tbl[ALSPRX], | 1521 | .attrs = &tsl2X7X_device_attr_group_tbl[ALSPRX], |
| 1678 | .event_attrs = &tsl2X7X_event_attr_group_tbl[ALSPRX], | ||
| 1679 | .driver_module = THIS_MODULE, | ||
| 1680 | .read_raw = &tsl2x7x_read_raw, | 1522 | .read_raw = &tsl2x7x_read_raw, |
| 1681 | .write_raw = &tsl2x7x_write_raw, | 1523 | .write_raw = &tsl2x7x_write_raw, |
| 1682 | .read_event_value = &tsl2x7x_read_event_value, | 1524 | .read_event_value = &tsl2x7x_read_event_value, |
| @@ -1686,8 +1528,6 @@ static const struct iio_info tsl2X7X_device_info[] = { · 3 unmodified lines | |||
| 1686 | }, | 1528 | }, |
| 1687 | [PRX2] = { | 1529 | [PRX2] = { |
| 1688 | .attrs = &tsl2X7X_device_attr_group_tbl[PRX2], | 1530 | .attrs = &tsl2X7X_device_attr_group_tbl[PRX2], |
| 1689 | .event_attrs = &tsl2X7X_event_attr_group_tbl[PRX], | ||
| 1690 | .driver_module = THIS_MODULE, | ||
| 1691 | .read_raw = &tsl2x7x_read_raw, | 1531 | .read_raw = &tsl2x7x_read_raw, |
| 1692 | .write_raw = &tsl2x7x_write_raw, | 1532 | .write_raw = &tsl2x7x_write_raw, |
| 1693 | .read_event_value = &tsl2x7x_read_event_value, | 1533 | .read_event_value = &tsl2x7x_read_event_value, |
| @@ -1697,8 +1537,6 @@ static const struct iio_info tsl2X7X_device_info[] = { · 3 unmodified lines | |||
| 1697 | }, | 1537 | }, |
| 1698 | [ALSPRX2] = { | 1538 | [ALSPRX2] = { |
| 1699 | .attrs = &tsl2X7X_device_attr_group_tbl[ALSPRX2], | 1539 | .attrs = &tsl2X7X_device_attr_group_tbl[ALSPRX2], |
| 1700 | .event_attrs = &tsl2X7X_event_attr_group_tbl[ALSPRX], | ||
| 1701 | .driver_module = THIS_MODULE, | ||
| 1702 | .read_raw = &tsl2x7x_read_raw, | 1540 | .read_raw = &tsl2x7x_read_raw, |
| 1703 | .write_raw = &tsl2x7x_write_raw, | 1541 | .write_raw = &tsl2x7x_write_raw, |
| 1704 | .read_event_value = &tsl2x7x_read_event_value, | 1542 | .read_event_value = &tsl2x7x_read_event_value, |
| @@ -1719,6 +1557,10 @@ static const struct iio_event_spec tsl2x7x_events[] = { · 14 unmodified lines | |||
| 1719 | .dir = IIO_EV_DIR_FALLING, | 1557 | .dir = IIO_EV_DIR_FALLING, |
| 1720 | .mask_separate = BIT(IIO_EV_INFO_VALUE) | | 1558 | .mask_separate = BIT(IIO_EV_INFO_VALUE) | |
| 1721 | BIT(IIO_EV_INFO_ENABLE), | 1559 | BIT(IIO_EV_INFO_ENABLE), |
| 1560 | }, { | ||
| 1561 | .type = IIO_EV_TYPE_THRESH, | ||
| 1562 | .dir = IIO_EV_DIR_EITHER, | ||
| 1563 | .mask_separate = BIT(IIO_EV_INFO_PERIOD), | ||
| 1722 | }, | 1564 | }, |
| 1723 | }; | 1565 | }; |
| 1724 | 1566 | ||
| @@ -1729,7 +1571,8 @@ static const struct tsl2x7x_chip_info tsl2x7x_chip_info_tbl[] = { · 4 unmodified lines | |||
| 1729 | .type = IIO_LIGHT, | 1571 | .type = IIO_LIGHT, |
| 1730 | .indexed = 1, | 1572 | .indexed = 1, |
| 1731 | .channel = 0, | 1573 | .channel = 0, |
| 1732 | .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), | 1574 | .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | |
| 1575 | BIT(IIO_CHAN_INFO_INT_TIME), | ||
| 1733 | }, { | 1576 | }, { |
| 1734 | .type = IIO_INTENSITY, | 1577 | .type = IIO_INTENSITY, |
| 1735 | .indexed = 1, | 1578 | .indexed = 1, |
| @@ -1768,7 +1611,8 @@ static const struct tsl2x7x_chip_info tsl2x7x_chip_info_tbl[] = { · 32 unmodified lines | |||
| 1768 | .type = IIO_LIGHT, | 1611 | .type = IIO_LIGHT, |
| 1769 | .indexed = 1, | 1612 | .indexed = 1, |
| 1770 | .channel = 0, | 1613 | .channel = 0, |
| 1771 | .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | 1614 | .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | |
| 1615 | BIT(IIO_CHAN_INFO_INT_TIME), | ||
| 1772 | }, { | 1616 | }, { |
| 1773 | .type = IIO_INTENSITY, | 1617 | .type = IIO_INTENSITY, |
| 1774 | .indexed = 1, | 1618 | .indexed = 1, |
| @@ -1816,7 +1660,8 @@ static const struct tsl2x7x_chip_info tsl2x7x_chip_info_tbl[] = { · 41 unmodified lines | |||
| 1816 | .type = IIO_LIGHT, | 1660 | .type = IIO_LIGHT, |
| 1817 | .indexed = 1, | 1661 | .indexed = 1, |
| 1818 | .channel = 0, | 1662 | .channel = 0, |
| 1819 | .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), | 1663 | .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | |
| 1664 | BIT(IIO_CHAN_INFO_INT_TIME), | ||
| 1820 | }, { | 1665 | }, { |
| 1821 | .type = IIO_INTENSITY, | 1666 | .type = IIO_INTENSITY, |
| 1822 | .indexed = 1, | 1667 | .indexed = 1, |
| @@ -1874,7 +1719,7 @@ static int tsl2x7x_probe(struct i2c_client *clientp, · 51 unmodified lines | |||
| 1874 | return -EINVAL; | 1719 | return -EINVAL; |
| 1875 | } | 1720 | } |
| 1876 | 1721 | ||
| 1877 | ret = i2c_smbus_write_byte(clientp, (TSL2X7X_CMD_REG | TSL2X7X_CNTRL)); | 1722 | ret = i2c_smbus_write_byte(clientp, TSL2X7X_CMD_REG | TSL2X7X_CNTRL); |
| 1878 | if (ret < 0) { | 1723 | if (ret < 0) { |
| 1879 | dev_err(&clientp->dev, "write to cmd reg failed. err = %d\n", | 1724 | dev_err(&clientp->dev, "write to cmd reg failed. err = %d\n", |
| 1880 | ret); | 1725 | ret); |
| @@ -1982,7 +1827,7 @@ static int tsl2x7x_remove(struct i2c_client *client) · 101 unmodified lines | |||
| 1982 | return 0; | 1827 | return 0; |
| 1983 | } | 1828 | } |
| 1984 | 1829 | ||
| 1985 | static struct i2c_device_id tsl2x7x_idtable[] = { | 1830 | static const struct i2c_device_id tsl2x7x_idtable[] = { |
| 1986 | { "tsl2571", tsl2571 }, | 1831 | { "tsl2571", tsl2571 }, |
| 1987 | { "tsl2671", tsl2671 }, | 1832 | { "tsl2671", tsl2671 }, |
| 1988 | { "tmd2671", tmd2671 }, | 1833 | { "tmd2671", tmd2671 }, |
| @@ -23,18 +23,19 @@ · 22 unmodified lines | |||
| 23 | #define __TSL2X7X_H | 23 | #define __TSL2X7X_H |
| 24 | #include <linux/pm.h> | 24 | #include <linux/pm.h> |
| 25 | 25 | ||
| 26 | /* Max number of segments allowable in LUX table */ | ||
| 27 | #define TSL2X7X_MAX_LUX_TABLE_SIZE 9 | ||
| 28 | #define MAX_DEFAULT_TABLE_BYTES (sizeof(int) * TSL2X7X_MAX_LUX_TABLE_SIZE) | ||
| 29 | |||
| 30 | struct iio_dev; | ||
| 31 | |||
| 32 | struct tsl2x7x_lux { | 26 | struct tsl2x7x_lux { |
| 33 | unsigned int ratio; | 27 | unsigned int ratio; |
| 34 | unsigned int ch0; | 28 | unsigned int ch0; |
| 35 | unsigned int ch1; | 29 | unsigned int ch1; |
| 36 | }; | 30 | }; |
| 37 | 31 | ||
| 32 | /* Max number of segments allowable in LUX table */ | ||
| 33 | #define TSL2X7X_MAX_LUX_TABLE_SIZE 9 | ||
| 34 | /* The default LUX tables all have 3 elements. */ | ||
| 35 | #define TSL2X7X_DEF_LUX_TABLE_SZ 3 | ||
| 36 | #define TSL2X7X_DEFAULT_TABLE_BYTES (sizeof(struct tsl2x7x_lux) * \ | ||
| 37 | TSL2X7X_DEF_LUX_TABLE_SZ) | ||
| 38 | |||
| 38 | /** | 39 | /** |
| 39 | * struct tsl2x7x_default_settings - power on defaults unless | 40 | * struct tsl2x7x_default_settings - power on defaults unless |
| 40 | * overridden by platform data. | 41 | * overridden by platform data. |
| @@ -80,7 +80,7 @@ · 79 unmodified lines | |||
| 80 | * @us: actual spi_device | 80 | * @us: actual spi_device |
| 81 | * @tx: transmit buffer | 81 | * @tx: transmit buffer |
| 82 | * @rx: receive buffer | 82 | * @rx: receive buffer |
| 83 | * @buf_lock: mutex to protect tx and rx | 83 | * @buf_lock: mutex to protect tx, rx and write frequency |
| 84 | **/ | 84 | **/ |
| 85 | struct ade7753_state { | 85 | struct ade7753_state { |
| 86 | struct spi_device *us; | 86 | struct spi_device *us; |
| @@ -107,6 +107,19 @@ static int ade7753_spi_write_reg_8(struct device *dev, · 20 unmodified lines | |||
| 107 | return ret; | 107 | return ret; |
| 108 | } | 108 | } |
| 109 | 109 | ||
| 110 | static int __ade7753_spi_write_reg_16(struct device *dev, u8 reg_address, | ||
| 111 | u16 value) | ||
| 112 | { | ||
| 113 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); | ||
| 114 | struct ade7753_state *st = iio_priv(indio_dev); | ||
| 115 | |||
| 116 | st->tx[0] = ADE7753_WRITE_REG(reg_address); | ||
| 117 | st->tx[1] = (value >> 8) & 0xFF; | ||
| 118 | st->tx[2] = value & 0xFF; | ||
| 119 | |||
| 120 | return spi_write(st->us, st->tx, 3); | ||
| 121 | } | ||
| 122 | |||
| 110 | static int ade7753_spi_write_reg_16(struct device *dev, u8 reg_address, | 123 | static int ade7753_spi_write_reg_16(struct device *dev, u8 reg_address, |
| 111 | u16 value) | 124 | u16 value) |
| 112 | { | 125 | { |
| @@ -115,10 +128,7 @@ static int ade7753_spi_write_reg_16(struct device *dev, u8 reg_address, · 2 unmodified lines | |||
| 115 | struct ade7753_state *st = iio_priv(indio_dev); | 128 | struct ade7753_state *st = iio_priv(indio_dev); |
| 116 | 129 | ||
| 117 | mutex_lock(&st->buf_lock); | 130 | mutex_lock(&st->buf_lock); |
| 118 | st->tx[0] = ADE7753_WRITE_REG(reg_address); | 131 | ret = __ade7753_spi_write_reg_16(dev, reg_address, value); |
| 119 | st->tx[1] = (value >> 8) & 0xFF; | ||
| 120 | st->tx[2] = value & 0xFF; | ||
| 121 | ret = spi_write(st->us, st->tx, 3); | ||
| 122 | mutex_unlock(&st->buf_lock); | 132 | mutex_unlock(&st->buf_lock); |
| 123 | 133 | ||
| 124 | return ret; | 134 | return ret; |
| @@ -483,7 +493,7 @@ static ssize_t ade7753_write_frequency(struct device *dev, · 358 unmodified lines | |||
| 483 | if (!val) | 493 | if (!val) |
| 484 | return -EINVAL; | 494 | return -EINVAL; |
| 485 | 495 | ||
| 486 | mutex_lock(&indio_dev->mlock); | 496 | mutex_lock(&st->buf_lock); |
| 487 | 497 | ||
| 488 | t = 27900 / val; | 498 | t = 27900 / val; |
| 489 | if (t > 0) | 499 | if (t > 0) |
| @@ -501,10 +511,10 @@ static ssize_t ade7753_write_frequency(struct device *dev, · 11 unmodified lines | |||
| 501 | reg &= ~(3 << 11); | 511 | reg &= ~(3 << 11); |
| 502 | reg |= t << 11; | 512 | reg |= t << 11; |
| 503 | 513 | ||
| 504 | ret = ade7753_spi_write_reg_16(dev, ADE7753_MODE, reg); | 514 | ret = __ade7753_spi_write_reg_16(dev, ADE7753_MODE, reg); |
| 505 | 515 | ||
| 506 | out: | 516 | out: |
| 507 | mutex_unlock(&indio_dev->mlock); | 517 | mutex_unlock(&st->buf_lock); |
| 508 | 518 | ||
| 509 | return ret ? ret : len; | 519 | return ret ? ret : len; |
| 510 | } | 520 | } |
| @@ -561,7 +571,6 @@ static const struct attribute_group ade7753_attribute_group = { · 50 unmodified lines | |||
| 561 | 571 | ||
| 562 | static const struct iio_info ade7753_info = { | 572 | static const struct iio_info ade7753_info = { |
| 563 | .attrs = &ade7753_attribute_group, | 573 | .attrs = &ade7753_attribute_group, |
| 564 | .driver_module = THIS_MODULE, | ||
| 565 | }; | 574 | }; |
| 566 | 575 | ||
| 567 | static int ade7753_probe(struct spi_device *spi) | 576 | static int ade7753_probe(struct spi_device *spi) |
| @@ -601,7 +601,6 @@ static const struct attribute_group ade7754_attribute_group = { · 600 unmodified lines | |||
| 601 | 601 | ||
| 602 | static const struct iio_info ade7754_info = { | 602 | static const struct iio_info ade7754_info = { |
| 603 | .attrs = &ade7754_attribute_group, | 603 | .attrs = &ade7754_attribute_group, |
| 604 | .driver_module = THIS_MODULE, | ||
| 605 | }; | 604 | }; |
| 606 | 605 | ||
| 607 | static int ade7754_probe(struct spi_device *spi) | 606 | static int ade7754_probe(struct spi_device *spi) |
| @@ -827,7 +827,6 @@ static const struct iio_info ade7758_info = { · 826 unmodified lines | |||
| 827 | .attrs = &ade7758_attribute_group, | 827 | .attrs = &ade7758_attribute_group, |
| 828 | .read_raw = &ade7758_read_raw, | 828 | .read_raw = &ade7758_read_raw, |
| 829 | .write_raw = &ade7758_write_raw, | 829 | .write_raw = &ade7758_write_raw, |
| 830 | .driver_module = THIS_MODULE, | ||
| 831 | }; | 830 | }; |
| 832 | 831 | ||
| 833 | static int ade7758_probe(struct spi_device *spi) | 832 | static int ade7758_probe(struct spi_device *spi) |
| @@ -53,7 +53,6 @@ static int ade7758_trig_try_reen(struct iio_trigger *trig) · 52 unmodified lines | |||
| 53 | } | 53 | } |
| 54 | 54 | ||
| 55 | static const struct iio_trigger_ops ade7758_trigger_ops = { | 55 | static const struct iio_trigger_ops ade7758_trigger_ops = { |
| 56 | .owner = THIS_MODULE, | ||
| 57 | .set_trigger_state = &ade7758_data_rdy_trigger_set_state, | 56 | .set_trigger_state = &ade7758_data_rdy_trigger_set_state, |
| 58 | .try_reenable = &ade7758_trig_try_reen, | 57 | .try_reenable = &ade7758_trig_try_reen, |
| 59 | }; | 58 | }; |
| @@ -60,7 +60,7 @@ · 59 unmodified lines | |||
| 60 | /** | 60 | /** |
| 61 | * struct ade7759_state - device instance specific data | 61 | * struct ade7759_state - device instance specific data |
| 62 | * @us: actual spi_device | 62 | * @us: actual spi_device |
| 63 | * @buf_lock: mutex to protect tx and rx | 63 | * @buf_lock: mutex to protect tx and rx and write frequency |
| 64 | * @tx: transmit buffer | 64 | * @tx: transmit buffer |
| 65 | * @rx: receive buffer | 65 | * @rx: receive buffer |
| 66 | **/ | 66 | **/ |
| @@ -89,19 +89,30 @@ static int ade7759_spi_write_reg_8(struct device *dev, · 22 unmodified lines | |||
| 89 | return ret; | 89 | return ret; |
| 90 | } | 90 | } |
| 91 | 91 | ||
| 92 | static int ade7759_spi_write_reg_16(struct device *dev, | 92 | /*Unlocked version of ade7759_spi_write_reg_16 function */ |
| 93 | static int __ade7759_spi_write_reg_16(struct device *dev, | ||
| 93 | u8 reg_address, | 94 | u8 reg_address, |
| 94 | u16 value) | 95 | u16 value) |
| 95 | { | 96 | { |
| 96 | int ret; | ||
| 97 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); | 97 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); |
| 98 | struct ade7759_state *st = iio_priv(indio_dev); | 98 | struct ade7759_state *st = iio_priv(indio_dev); |
| 99 | 99 | ||
| 100 | mutex_lock(&st->buf_lock); | ||
| 101 | st->tx[0] = ADE7759_WRITE_REG(reg_address); | 100 | st->tx[0] = ADE7759_WRITE_REG(reg_address); |
| 102 | st->tx[1] = (value >> 8) & 0xFF; | 101 | st->tx[1] = (value >> 8) & 0xFF; |
| 103 | st->tx[2] = value & 0xFF; | 102 | st->tx[2] = value & 0xFF; |
| 104 | ret = spi_write(st->us, st->tx, 3); | 103 | return spi_write(st->us, st->tx, 3); |
| 104 | } | ||
| 105 | |||
| 106 | static int ade7759_spi_write_reg_16(struct device *dev, | ||
| 107 | u8 reg_address, | ||
| 108 | u16 value) | ||
| 109 | { | ||
| 110 | int ret; | ||
| 111 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); | ||
| 112 | struct ade7759_state *st = iio_priv(indio_dev); | ||
| 113 | |||
| 114 | mutex_lock(&st->buf_lock); | ||
| 115 | ret = __ade7759_spi_write_reg_16(dev, reg_address, value); | ||
| 105 | mutex_unlock(&st->buf_lock); | 116 | mutex_unlock(&st->buf_lock); |
| 106 | 117 | ||
| 107 | return ret; | 118 | return ret; |
| @@ -429,7 +440,7 @@ static ssize_t ade7759_write_frequency(struct device *dev, · 321 unmodified lines | |||
| 429 | if (!val) | 440 | if (!val) |
| 430 | return -EINVAL; | 441 | return -EINVAL; |
| 431 | 442 | ||
| 432 | mutex_lock(&indio_dev->mlock); | 443 | mutex_lock(&st->buf_lock); |
| 433 | 444 | ||
| 434 | t = 27900 / val; | 445 | t = 27900 / val; |
| 435 | if (t > 0) | 446 | if (t > 0) |
| @@ -447,10 +458,10 @@ static ssize_t ade7759_write_frequency(struct device *dev, · 11 unmodified lines | |||
| 447 | reg &= ~(3 << 13); | 458 | reg &= ~(3 << 13); |
| 448 | reg |= t << 13; | 459 | reg |= t << 13; |
| 449 | 460 | ||
| 450 | ret = ade7759_spi_write_reg_16(dev, ADE7759_MODE, reg); | 461 | ret = __ade7759_spi_write_reg_16(dev, ADE7759_MODE, reg); |
| 451 | 462 | ||
| 452 | out: | 463 | out: |
| 453 | mutex_unlock(&indio_dev->mlock); | 464 | mutex_unlock(&st->buf_lock); |
| 454 | 465 | ||
| 455 | return ret ? ret : len; | 466 | return ret ? ret : len; |
| 456 | } | 467 | } |
| @@ -493,7 +504,6 @@ static const struct attribute_group ade7759_attribute_group = { · 36 unmodified lines | |||
| 493 | 504 | ||
| 494 | static const struct iio_info ade7759_info = { | 505 | static const struct iio_info ade7759_info = { |
| 495 | .attrs = &ade7759_attribute_group, | 506 | .attrs = &ade7759_attribute_group, |
| 496 | .driver_module = THIS_MODULE, | ||
| 497 | }; | 507 | }; |
| 498 | 508 | ||
| 499 | static int ade7759_probe(struct spi_device *spi) | 509 | static int ade7759_probe(struct spi_device *spi) |
| @@ -530,7 +530,6 @@ static const struct attribute_group ade7854_attribute_group = { · 529 unmodified lines | |||
| 530 | 530 | ||
| 531 | static const struct iio_info ade7854_info = { | 531 | static const struct iio_info ade7854_info = { |
| 532 | .attrs = &ade7854_attribute_group, | 532 | .attrs = &ade7854_attribute_group, |
| 533 | .driver_module = THIS_MODULE, | ||
| 534 | }; | 533 | }; |
| 535 | 534 | ||
| 536 | int ade7854_probe(struct iio_dev *indio_dev, struct device *dev) | 535 | int ade7854_probe(struct iio_dev *indio_dev, struct device *dev) |
| @@ -98,7 +98,6 @@ static const struct iio_chan_spec ad2s1200_channels[] = { · 97 unmodified lines | |||
| 98 | 98 | ||
| 99 | static const struct iio_info ad2s1200_info = { | 99 | static const struct iio_info ad2s1200_info = { |
| 100 | .read_raw = ad2s1200_read_raw, | 100 | .read_raw = ad2s1200_read_raw, |
| 101 | .driver_module = THIS_MODULE, | ||
| 102 | }; | 101 | }; |
| 103 | 102 | ||
| 104 | static int ad2s1200_probe(struct spi_device *spi) | 103 | static int ad2s1200_probe(struct spi_device *spi) |
| @@ -638,7 +638,6 @@ error_ret: · 637 unmodified lines | |||
| 638 | static const struct iio_info ad2s1210_info = { | 638 | static const struct iio_info ad2s1210_info = { |
| 639 | .read_raw = ad2s1210_read_raw, | 639 | .read_raw = ad2s1210_read_raw, |
| 640 | .attrs = &ad2s1210_attribute_group, | 640 | .attrs = &ad2s1210_attribute_group, |
| 641 | .driver_module = THIS_MODULE, | ||
| 642 | }; | 641 | }; |
| 643 | 642 | ||
| 644 | static int ad2s1210_setup_gpios(struct ad2s1210_state *st) | 643 | static int ad2s1210_setup_gpios(struct ad2s1210_state *st) |
| @@ -48,7 +48,6 @@ error_ret: · 47 unmodified lines | |||
| 48 | 48 | ||
| 49 | static const struct iio_info ad2s90_info = { | 49 | static const struct iio_info ad2s90_info = { |
| 50 | .read_raw = ad2s90_read_raw, | 50 | .read_raw = ad2s90_read_raw, |
| 51 | .driver_module = THIS_MODULE, | ||
| 52 | }; | 51 | }; |
| 53 | 52 | ||
| 54 | static const struct iio_chan_spec ad2s90_chan = { | 53 | static const struct iio_chan_spec ad2s90_chan = { |
| @@ -172,7 +172,6 @@ static int iio_bfin_tmr_get_number(int irq) · 171 unmodified lines | |||
| 172 | } | 172 | } |
| 173 | 173 | ||
| 174 | static const struct iio_trigger_ops iio_bfin_tmr_trigger_ops = { | 174 | static const struct iio_trigger_ops iio_bfin_tmr_trigger_ops = { |
| 175 | .owner = THIS_MODULE, | ||
| 176 | .set_trigger_state = iio_bfin_tmr_set_state, | 175 | .set_trigger_state = iio_bfin_tmr_set_state, |
| 177 | }; | 176 | }; |
| 178 | 177 | ||
| @@ -1876,8 +1876,7 @@ static int ali_ircc_dma_receive_complete(struct ali_ircc_cb *self) · 1875 unmodified lines | |||
| 1876 | self->stamp = ktime_get(); | 1876 | self->stamp = ktime_get(); |
| 1877 | 1877 | ||
| 1878 | skb = dev_alloc_skb(len+1); | 1878 | skb = dev_alloc_skb(len+1); |
| 1879 | if (skb == NULL) | 1879 | if (!skb) { |
| 1880 | { | ||
| 1881 | self->netdev->stats.rx_dropped++; | 1880 | self->netdev->stats.rx_dropped++; |
| 1882 | 1881 | ||
| 1883 | return FALSE; | 1882 | return FALSE; |
| @@ -290,8 +290,7 @@ static int au1k_irda_set_speed(struct net_device *dev, int speed) · 289 unmodified lines | |||
| 290 | while (irda_read(aup, IR_STATUS) & (IR_RX_STATUS | IR_TX_STATUS)) { | 290 | while (irda_read(aup, IR_STATUS) & (IR_RX_STATUS | IR_TX_STATUS)) { |
| 291 | msleep(20); | 291 | msleep(20); |
| 292 | if (!timeout--) { | 292 | if (!timeout--) { |
| 293 | printk(KERN_ERR "%s: rx/tx disable timeout\n", | 293 | netdev_err(dev, "rx/tx disable timeout\n"); |
| 294 | dev->name); | ||
| 295 | break; | 294 | break; |
| 296 | } | 295 | } |
| 297 | } | 296 | } |
| @@ -349,7 +348,7 @@ static int au1k_irda_set_speed(struct net_device *dev, int speed) · 51 unmodified lines | |||
| 349 | IR_RX_ENABLE); | 348 | IR_RX_ENABLE); |
| 350 | break; | 349 | break; |
| 351 | default: | 350 | default: |
| 352 | printk(KERN_ERR "%s unsupported speed %x\n", dev->name, speed); | 351 | netdev_err(dev, "unsupported speed %x\n", speed); |
| 353 | ret = -EINVAL; | 352 | ret = -EINVAL; |
| 354 | break; | 353 | break; |
| 355 | } | 354 | } |
| @@ -361,18 +360,18 @@ static int au1k_irda_set_speed(struct net_device *dev, int speed) · 5 unmodified lines | |||
| 361 | irda_write(aup, IR_RING_PROMPT, 0); | 360 | irda_write(aup, IR_RING_PROMPT, 0); |
| 362 | 361 | ||
| 363 | if (control & (1 << 14)) { | 362 | if (control & (1 << 14)) { |
| 364 | printk(KERN_ERR "%s: configuration error\n", dev->name); | 363 | netdev_err(dev, "configuration error\n"); |
| 365 | } else { | 364 | } else { |
| 366 | if (control & (1 << 11)) | 365 | if (control & (1 << 11)) |
| 367 | printk(KERN_DEBUG "%s Valid SIR config\n", dev->name); | 366 | netdev_debug(dev, "Valid SIR config\n"); |
| 368 | if (control & (1 << 12)) | 367 | if (control & (1 << 12)) |
| 369 | printk(KERN_DEBUG "%s Valid MIR config\n", dev->name); | 368 | netdev_debug(dev, "Valid MIR config\n"); |
| 370 | if (control & (1 << 13)) | 369 | if (control & (1 << 13)) |
| 371 | printk(KERN_DEBUG "%s Valid FIR config\n", dev->name); | 370 | netdev_debug(dev, "Valid FIR config\n"); |
| 372 | if (control & (1 << 10)) | 371 | if (control & (1 << 10)) |
| 373 | printk(KERN_DEBUG "%s TX enabled\n", dev->name); | 372 | netdev_debug(dev, "TX enabled\n"); |
| 374 | if (control & (1 << 9)) | 373 | if (control & (1 << 9)) |
| 375 | printk(KERN_DEBUG "%s RX enabled\n", dev->name); | 374 | netdev_debug(dev, "RX enabled\n"); |
| 376 | } | 375 | } |
| 377 | 376 | ||
| 378 | return ret; | 377 | return ret; |
| @@ -584,23 +583,21 @@ static int au1k_irda_start(struct net_device *dev) · 205 unmodified lines | |||
| 584 | 583 | ||
| 585 | retval = au1k_init(dev); | 584 | retval = au1k_init(dev); |
| 586 | if (retval) { | 585 | if (retval) { |
| 587 | printk(KERN_ERR "%s: error in au1k_init\n", dev->name); | 586 | netdev_err(dev, "error in au1k_init\n"); |
| 588 | return retval; | 587 | return retval; |
| 589 | } | 588 | } |
| 590 | 589 | ||
| 591 | retval = request_irq(aup->irq_tx, &au1k_irda_interrupt, 0, | 590 | retval = request_irq(aup->irq_tx, &au1k_irda_interrupt, 0, |
| 592 | dev->name, dev); | 591 | dev->name, dev); |
| 593 | if (retval) { | 592 | if (retval) { |
| 594 | printk(KERN_ERR "%s: unable to get IRQ %d\n", | 593 | netdev_err(dev, "unable to get IRQ %d\n", dev->irq); |
| 595 | dev->name, dev->irq); | ||
| 596 | return retval; | 594 | return retval; |
| 597 | } | 595 | } |
| 598 | retval = request_irq(aup->irq_rx, &au1k_irda_interrupt, 0, | 596 | retval = request_irq(aup->irq_rx, &au1k_irda_interrupt, 0, |
| 599 | dev->name, dev); | 597 | dev->name, dev); |
| 600 | if (retval) { | 598 | if (retval) { |
| 601 | free_irq(aup->irq_tx, dev); | 599 | free_irq(aup->irq_tx, dev); |
| 602 | printk(KERN_ERR "%s: unable to get IRQ %d\n", | 600 | netdev_err(dev, "unable to get IRQ %d\n", dev->irq); |
| 603 | dev->name, dev->irq); | ||
| 604 | return retval; | 601 | return retval; |
| 605 | } | 602 | } |
| 606 | 603 | ||
| @@ -673,12 +670,12 @@ static int au1k_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev) · 66 unmodified lines | |||
| 673 | flags = ptxd->flags; | 670 | flags = ptxd->flags; |
| 674 | 671 | ||
| 675 | if (flags & AU_OWN) { | 672 | if (flags & AU_OWN) { |
| 676 | printk(KERN_DEBUG "%s: tx_full\n", dev->name); | 673 | netdev_debug(dev, "tx_full\n"); |
| 677 | netif_stop_queue(dev); | 674 | netif_stop_queue(dev); |
| 678 | aup->tx_full = 1; | 675 | aup->tx_full = 1; |
| 679 | return 1; | 676 | return 1; |
| 680 | } else if (((aup->tx_head + 1) & (NUM_IR_DESC - 1)) == aup->tx_tail) { | 677 | } else if (((aup->tx_head + 1) & (NUM_IR_DESC - 1)) == aup->tx_tail) { |
| 681 | printk(KERN_DEBUG "%s: tx_full\n", dev->name); | 678 | netdev_debug(dev, "tx_full\n"); |
| 682 | netif_stop_queue(dev); | 679 | netif_stop_queue(dev); |
| 683 | aup->tx_full = 1; | 680 | aup->tx_full = 1; |
| 684 | return 1; | 681 | return 1; |
| @@ -688,7 +685,7 @@ static int au1k_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev) · 3 unmodified lines | |||
| 688 | 685 | ||
| 689 | #if 0 | 686 | #if 0 |
| 690 | if (irda_read(aup, IR_RX_BYTE_CNT) != 0) { | 687 | if (irda_read(aup, IR_RX_BYTE_CNT) != 0) { |
| 691 | printk(KERN_DEBUG "tx warning: rx byte cnt %x\n", | 688 | netdev_debug(dev, "tx warning: rx byte cnt %x\n", |
| 692 | irda_read(aup, IR_RX_BYTE_CNT)); | 689 | irda_read(aup, IR_RX_BYTE_CNT)); |
| 693 | } | 690 | } |
| 694 | #endif | 691 | #endif |
| @@ -726,7 +723,7 @@ static void au1k_tx_timeout(struct net_device *dev) · 31 unmodified lines | |||
| 726 | u32 speed; | 723 | u32 speed; |
| 727 | struct au1k_private *aup = netdev_priv(dev); | 724 | struct au1k_private *aup = netdev_priv(dev); |
| 728 | 725 | ||
| 729 | printk(KERN_ERR "%s: tx timeout\n", dev->name); | 726 | netdev_err(dev, "tx timeout\n"); |
| 730 | speed = aup->speed; | 727 | speed = aup->speed; |
| 731 | aup->speed = 0; | 728 | aup->speed = 0; |
| 732 | au1k_irda_set_speed(dev, speed); | 729 | au1k_irda_set_speed(dev, speed); |
| @@ -751,8 +748,7 @@ static int au1k_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd) · 18 unmodified lines | |||
| 751 | ret = au1k_irda_set_speed(dev, | 748 | ret = au1k_irda_set_speed(dev, |
| 752 | rq->ifr_baudrate); | 749 | rq->ifr_baudrate); |
| 753 | else { | 750 | else { |
| 754 | printk(KERN_ERR "%s ioctl: !netif_running\n", | 751 | netdev_err(dev, "ioctl: !netif_running\n"); |
| 755 | dev->name); | ||
| 756 | ret = 0; | 752 | ret = 0; |
| 757 | } | 753 | } |
| 758 | } | 754 | } |
| @@ -868,7 +864,7 @@ out3: · 109 unmodified lines | |||
| 868 | out2: | 864 | out2: |
| 869 | kfree(aup->rx_buff.head); | 865 | kfree(aup->rx_buff.head); |
| 870 | out1: | 866 | out1: |
| 871 | printk(KERN_ERR "au1k_irda_net_init() failed. Returns %d\n", retval); | 867 | netdev_err(dev, "au1k_irda_net_init() failed. Returns %d\n"); |
| 872 | return retval; | 868 | return retval; |
| 873 | } | 869 | } |
| 874 | 870 | ||
| @@ -934,7 +930,7 @@ static int au1k_irda_probe(struct platform_device *pdev) · 59 unmodified lines | |||
| 934 | 930 | ||
| 935 | platform_set_drvdata(pdev, dev); | 931 | platform_set_drvdata(pdev, dev); |
| 936 | 932 | ||
| 937 | printk(KERN_INFO "IrDA: Registered device %s\n", dev->name); | 933 | netdev_info(dev, "IrDA: Registered device\n"); |
| 938 | return 0; | 934 | return 0; |
| 939 | 935 | ||
| 940 | out4: | 936 | out4: |
| @@ -22,6 +22,8 @@ static int max_rate = 57600; · 21 unmodified lines | |||
| 22 | static int max_rate = 115200; | 22 | static int max_rate = 115200; |
| 23 | #endif | 23 | #endif |
| 24 | 24 | ||
| 25 | static void bfin_sir_rx_dma_timeout(struct timer_list *t); | ||
| 26 | |||
| 25 | static void turnaround_delay(int mtt) | 27 | static void turnaround_delay(int mtt) |
| 26 | { | 28 | { |
| 27 | long ticks; | 29 | long ticks; |
| @@ -57,7 +59,7 @@ static void bfin_sir_init_ports(struct bfin_sir_port *sp, struct platform_device · 29 unmodified lines | |||
| 57 | sp->clk = get_sclk(); | 59 | sp->clk = get_sclk(); |
| 58 | #ifdef CONFIG_SIR_BFIN_DMA | 60 | #ifdef CONFIG_SIR_BFIN_DMA |
| 59 | sp->tx_done = 1; | 61 | sp->tx_done = 1; |
| 60 | init_timer(&(sp->rx_dma_timer)); | 62 | timer_setup(&sp->rx_dma_timer, bfin_sir_rx_dma_timeout, 0); |
| 61 | #endif | 63 | #endif |
| 62 | } | 64 | } |
| 63 | 65 | ||
| @@ -317,10 +319,12 @@ static void bfin_sir_dma_rx_chars(struct net_device *dev) · 253 unmodified lines | |||
| 317 | async_unwrap_char(dev, &self->stats, &self->rx_buff, port->rx_dma_buf.buf[i]); | 319 | async_unwrap_char(dev, &self->stats, &self->rx_buff, port->rx_dma_buf.buf[i]); |
| 318 | } | 320 | } |
| 319 | 321 | ||
| 320 | void bfin_sir_rx_dma_timeout(struct net_device *dev) | 322 | static void bfin_sir_rx_dma_timeout(struct timer_list *t) |
| 321 | { | 323 | { |
| 324 | struct bfin_sir_port *port = from_timer(port, t, rx_dma_timer); | ||
| 325 | struct net_device *dev = port->dev; | ||
| 322 | struct bfin_sir_self *self = netdev_priv(dev); | 326 | struct bfin_sir_self *self = netdev_priv(dev); |
| 323 | struct bfin_sir_port *port = self->sir_port; | 327 | |
| 324 | int x_pos, pos; | 328 | int x_pos, pos; |
| 325 | unsigned long flags; | 329 | unsigned long flags; |
| 326 | 330 | ||
| @@ -405,8 +409,6 @@ static int bfin_sir_startup(struct bfin_sir_port *port, struct net_device *dev) · 78 unmodified lines | |||
| 405 | set_dma_start_addr(port->rx_dma_channel, (unsigned long)port->rx_dma_buf.buf); | 409 | set_dma_start_addr(port->rx_dma_channel, (unsigned long)port->rx_dma_buf.buf); |
| 406 | enable_dma(port->rx_dma_channel); | 410 | enable_dma(port->rx_dma_channel); |
| 407 | 411 | ||
| 408 | port->rx_dma_timer.data = (unsigned long)(dev); | ||
| 409 | port->rx_dma_timer.function = (void *)bfin_sir_rx_dma_timeout; | ||
| 410 | 412 | ||
| 411 | #else | 413 | #else |
| 412 | 414 | ||
| @@ -1,5 +1,5 @@ | |||
| 1 | /********************************************************************* | 1 | /********************************************************************* |
| 2 | * | 2 | * |
| 3 | * Filename: esi.c | 3 | * Filename: esi.c |
| 4 | * Version: 1.6 | 4 | * Version: 1.6 |
| 5 | * Description: Driver for the Extended Systems JetEye PC dongle | 5 | * Description: Driver for the Extended Systems JetEye PC dongle |
| @@ -8,25 +8,25 @@ · 2 unmodified lines | |||
| 8 | * Created at: Sat Feb 21 18:54:38 1998 | 8 | * Created at: Sat Feb 21 18:54:38 1998 |
| 9 | * Modified at: Sun Oct 27 22:01:04 2002 | 9 | * Modified at: Sun Oct 27 22:01:04 2002 |
| 10 | * Modified by: Martin Diehl <mad@mdiehl.de> | 10 | * Modified by: Martin Diehl <mad@mdiehl.de> |
| 11 | * | 11 | * |
| 12 | * Copyright (c) 1999 Dag Brattli, <dagb@cs.uit.no>, | 12 | * Copyright (c) 1999 Dag Brattli, <dagb@cs.uit.no>, |
| 13 | * Copyright (c) 1998 Thomas Davis, <ratbert@radiks.net>, | 13 | * Copyright (c) 1998 Thomas Davis, <ratbert@radiks.net>, |
| 14 | * Copyright (c) 2002 Martin Diehl, <mad@mdiehl.de>, | 14 | * Copyright (c) 2002 Martin Diehl, <mad@mdiehl.de>, |
| 15 | * All Rights Reserved. | 15 | * All Rights Reserved. |
| 16 | * | 16 | * |
| 17 | * This program is free software; you can redistribute it and/or | 17 | * This program is free software; you can redistribute it and/or |
| 18 | * modify it under the terms of the GNU General Public License as | 18 | * modify it under the terms of the GNU General Public License as |
| 19 | * published by the Free Software Foundation; either version 2 of | 19 | * published by the Free Software Foundation; either version 2 of |
| 20 | * the License, or (at your option) any later version. | 20 | * the License, or (at your option) any later version. |
| 21 | * | 21 | * |
| 22 | * This program is distributed in the hope that it will be useful, | 22 | * This program is distributed in the hope that it will be useful, |
| 23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | 23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 25 | * GNU General Public License for more details. | 25 | * GNU General Public License for more details. |
| 26 | * | 26 | * |
| 27 | * You should have received a copy of the GNU General Public License | 27 | * You should have received a copy of the GNU General Public License |
| 28 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | 28 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
| 29 | * | 29 | * |
| 30 | ********************************************************************/ | 30 | ********************************************************************/ |
| 31 | 31 | ||
| 32 | #include <linux/module.h> | 32 | #include <linux/module.h> |
| @@ -97,7 +97,7 @@ static int esi_change_speed(struct sir_dev *dev, unsigned speed) · 64 unmodified lines | |||
| 97 | { | 97 | { |
| 98 | int ret = 0; | 98 | int ret = 0; |
| 99 | int dtr, rts; | 99 | int dtr, rts; |
| 100 | 100 | ||
| 101 | switch (speed) { | 101 | switch (speed) { |
| 102 | case 19200: | 102 | case 19200: |
| 103 | dtr = TRUE; | 103 | dtr = TRUE; |
| @@ -117,7 +117,7 @@ static void irda_usb_close(struct irda_usb_cb *self); · 116 unmodified lines | |||
| 117 | static void speed_bulk_callback(struct urb *urb); | 117 | static void speed_bulk_callback(struct urb *urb); |
| 118 | static void write_bulk_callback(struct urb *urb); | 118 | static void write_bulk_callback(struct urb *urb); |
| 119 | static void irda_usb_receive(struct urb *urb); | 119 | static void irda_usb_receive(struct urb *urb); |
| 120 | static void irda_usb_rx_defer_expired(unsigned long data); | 120 | static void irda_usb_rx_defer_expired(struct timer_list *t); |
| 121 | static int irda_usb_net_open(struct net_device *dev); | 121 | static int irda_usb_net_open(struct net_device *dev); |
| 122 | static int irda_usb_net_close(struct net_device *dev); | 122 | static int irda_usb_net_close(struct net_device *dev); |
| 123 | static int irda_usb_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | 123 | static int irda_usb_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
| @@ -334,9 +334,9 @@ static void irda_usb_change_speed_xbofs(struct irda_usb_cb *self) · 210 unmodified lines | |||
| 334 | urb->transfer_flags = 0; | 334 | urb->transfer_flags = 0; |
| 335 | 335 | ||
| 336 | /* Irq disabled -> GFP_ATOMIC */ | 336 | /* Irq disabled -> GFP_ATOMIC */ |
| 337 | if ((ret = usb_submit_urb(urb, GFP_ATOMIC))) { | 337 | ret = usb_submit_urb(urb, GFP_ATOMIC); |
| 338 | if (ret) | ||
| 338 | net_warn_ratelimited("%s(), failed Speed URB\n", __func__); | 339 | net_warn_ratelimited("%s(), failed Speed URB\n", __func__); |
| 339 | } | ||
| 340 | } | 340 | } |
| 341 | 341 | ||
| 342 | /*------------------------------------------------------------------*/ | 342 | /*------------------------------------------------------------------*/ |
| @@ -846,8 +846,7 @@ static void irda_usb_receive(struct urb *urb) · 503 unmodified lines | |||
| 846 | * hot unplug of the dongle... | 846 | * hot unplug of the dongle... |
| 847 | * Lowest effective timer is 10ms... | 847 | * Lowest effective timer is 10ms... |
| 848 | * Jean II */ | 848 | * Jean II */ |
| 849 | self->rx_defer_timer.function = irda_usb_rx_defer_expired; | 849 | self->rx_defer_timer_urb = urb; |
| 850 | self->rx_defer_timer.data = (unsigned long) urb; | ||
| 851 | mod_timer(&self->rx_defer_timer, | 850 | mod_timer(&self->rx_defer_timer, |
| 852 | jiffies + msecs_to_jiffies(10)); | 851 | jiffies + msecs_to_jiffies(10)); |
| 853 | 852 | ||
| @@ -953,20 +952,13 @@ done: · 99 unmodified lines | |||
| 953 | * In case of errors, we want the USB layer to have time to recover. | 952 | * In case of errors, we want the USB layer to have time to recover. |
| 954 | * Now, it is time to resubmit ouur Rx URB... | 953 | * Now, it is time to resubmit ouur Rx URB... |
| 955 | */ | 954 | */ |
| 956 | static void irda_usb_rx_defer_expired(unsigned long data) | 955 | static void irda_usb_rx_defer_expired(struct timer_list *t) |
| 957 | { | 956 | { |
| 958 | struct urb *urb = (struct urb *) data; | 957 | struct irda_usb_cb *self = from_timer(self, t, rx_defer_timer); |
| 958 | struct urb *urb = self->rx_defer_timer_urb; | ||
| 959 | struct sk_buff *skb = (struct sk_buff *) urb->context; | 959 | struct sk_buff *skb = (struct sk_buff *) urb->context; |
| 960 | struct irda_usb_cb *self; | ||
| 961 | struct irda_skb_cb *cb; | ||
| 962 | struct urb *next_urb; | 960 | struct urb *next_urb; |
| 963 | 961 | ||
| 964 | /* Find ourselves */ | ||
| 965 | cb = (struct irda_skb_cb *) skb->cb; | ||
| 966 | IRDA_ASSERT(cb != NULL, return;); | ||
| 967 | self = (struct irda_usb_cb *) cb->context; | ||
| 968 | IRDA_ASSERT(self != NULL, return;); | ||
| 969 | |||
| 970 | /* Same stuff as when Rx is done, see above... */ | 962 | /* Same stuff as when Rx is done, see above... */ |
| 971 | next_urb = self->idle_rx_urb; | 963 | next_urb = self->idle_rx_urb; |
| 972 | urb->context = NULL; | 964 | urb->context = NULL; |
| @@ -1622,7 +1614,7 @@ static int irda_usb_probe(struct usb_interface *intf, · 649 unmodified lines | |||
| 1622 | self = netdev_priv(net); | 1614 | self = netdev_priv(net); |
| 1623 | self->netdev = net; | 1615 | self->netdev = net; |
| 1624 | spin_lock_init(&self->lock); | 1616 | spin_lock_init(&self->lock); |
| 1625 | init_timer(&self->rx_defer_timer); | 1617 | timer_setup(&self->rx_defer_timer, irda_usb_rx_defer_expired, 0); |
| 1626 | 1618 | ||
| 1627 | self->capability = id->driver_info; | 1619 | self->capability = id->driver_info; |
| 1628 | self->needspatch = ((self->capability & IUC_STIR421X) != 0); | 1620 | self->needspatch = ((self->capability & IUC_STIR421X) != 0); |
| @@ -170,5 +170,6 @@ struct irda_usb_cb { · 169 unmodified lines | |||
| 170 | int needspatch; /* device needs firmware patch */ | 170 | int needspatch; /* device needs firmware patch */ |
| 171 | 171 | ||
| 172 | struct timer_list rx_defer_timer; /* Wait for Rx error to clear */ | 172 | struct timer_list rx_defer_timer; /* Wait for Rx error to clear */ |
| 173 | struct urb *rx_defer_timer_urb; /* URB attached to rx_defer_timer */ | ||
| 173 | }; | 174 | }; |
| 174 | 175 | ||
| @@ -605,19 +605,22 @@ static int mcs_speed_change(struct mcs_cb *mcs) · 604 unmodified lines | |||
| 605 | if (mcs->new_speed <= 115200) { | 605 | if (mcs->new_speed <= 115200) { |
| 606 | rval &= ~MCS_FIR; | 606 | rval &= ~MCS_FIR; |
| 607 | 607 | ||
| 608 | if ((rst = (mcs->speed > 115200))) | 608 | rst = mcs->speed > 115200; |
| 609 | if (rst) | ||
| 609 | mcs_set_reg(mcs, MCS_MINRXPW_REG, 0); | 610 | mcs_set_reg(mcs, MCS_MINRXPW_REG, 0); |
| 610 | 611 | ||
| 611 | } else if (mcs->new_speed <= 1152000) { | 612 | } else if (mcs->new_speed <= 1152000) { |
| 612 | rval &= ~MCS_FIR; | 613 | rval &= ~MCS_FIR; |
| 613 | 614 | ||
| 614 | if ((rst = !(mcs->speed == 576000 || mcs->speed == 1152000))) | 615 | rst = !(mcs->speed == 576000 || mcs->speed == 1152000); |
| 616 | if (rst) | ||
| 615 | mcs_set_reg(mcs, MCS_MINRXPW_REG, 5); | 617 | mcs_set_reg(mcs, MCS_MINRXPW_REG, 5); |
| 616 | 618 | ||
| 617 | } else { | 619 | } else { |
| 618 | rval |= MCS_FIR; | 620 | rval |= MCS_FIR; |
| 619 | 621 | ||
| 620 | if ((rst = (mcs->speed != 4000000))) | 622 | rst = mcs->speed != 4000000; |
| 623 | if (rst) | ||
| 621 | mcs_set_reg(mcs, MCS_MINRXPW_REG, 5); | 624 | mcs_set_reg(mcs, MCS_MINRXPW_REG, 5); |
| 622 | 625 | ||
| 623 | } | 626 | } |
| @@ -170,10 +170,10 @@ static void vlsi_proc_pdev(struct seq_file *seq, struct pci_dev *pdev) · 169 unmodified lines | |||
| 170 | seq_printf(seq, "pci-power-state: %u\n", (unsigned) pdev->current_state); | 170 | seq_printf(seq, "pci-power-state: %u\n", (unsigned) pdev->current_state); |
| 171 | seq_printf(seq, "resources: irq=%u / io=0x%04x / dma_mask=0x%016Lx\n", | 171 | seq_printf(seq, "resources: irq=%u / io=0x%04x / dma_mask=0x%016Lx\n", |
| 172 | pdev->irq, (unsigned)pci_resource_start(pdev, 0), (unsigned long long)pdev->dma_mask); | 172 | pdev->irq, (unsigned)pci_resource_start(pdev, 0), (unsigned long long)pdev->dma_mask); |
| 173 | seq_printf(seq, "hw registers: "); | 173 | seq_puts(seq, "hw registers: "); |
| 174 | for (i = 0; i < 0x20; i++) | 174 | for (i = 0; i < 0x20; i++) |
| 175 | seq_printf(seq, "%02x", (unsigned)inb((iobase+i))); | 175 | seq_printf(seq, "%02x", (unsigned)inb((iobase+i))); |
| 176 | seq_printf(seq, "\n"); | 176 | seq_putc(seq, '\n'); |
| 177 | } | 177 | } |
| 178 | 178 | ||
| 179 | static void vlsi_proc_ndev(struct seq_file *seq, struct net_device *ndev) | 179 | static void vlsi_proc_ndev(struct seq_file *seq, struct net_device *ndev) |
| @@ -193,7 +193,7 @@ static void vlsi_proc_ndev(struct seq_file *seq, struct net_device *ndev) · 13 unmodified lines | |||
| 193 | if (!netif_running(ndev)) | 193 | if (!netif_running(ndev)) |
| 194 | return; | 194 | return; |
| 195 | 195 | ||
| 196 | seq_printf(seq, "\nhw-state:\n"); | 196 | seq_puts(seq, "\nhw-state:\n"); |
| 197 | pci_read_config_byte(idev->pdev, VLSI_PCI_IRMISC, &byte); | 197 | pci_read_config_byte(idev->pdev, VLSI_PCI_IRMISC, &byte); |
| 198 | seq_printf(seq, "IRMISC:%s%s%s uart%s", | 198 | seq_printf(seq, "IRMISC:%s%s%s uart%s", |
| 199 | (byte&IRMISC_IRRAIL) ? " irrail" : "", | 199 | (byte&IRMISC_IRRAIL) ? " irrail" : "", |
| @@ -274,7 +274,7 @@ static void vlsi_proc_ndev(struct seq_file *seq, struct net_device *ndev) · 74 unmodified lines | |||
| 274 | word = inw(iobase+VLSI_PIO_RCVBCNT) & RCVBCNT_MASK; | 274 | word = inw(iobase+VLSI_PIO_RCVBCNT) & RCVBCNT_MASK; |
| 275 | seq_printf(seq, "RCVBCNT: rx-fifo filling level = %u\n", word); | 275 | seq_printf(seq, "RCVBCNT: rx-fifo filling level = %u\n", word); |
| 276 | 276 | ||
| 277 | seq_printf(seq, "\nsw-state:\n"); | 277 | seq_puts(seq, "\nsw-state:\n"); |
| 278 | seq_printf(seq, "IrPHY setup: %d baud - %s encoding\n", idev->baud, | 278 | seq_printf(seq, "IrPHY setup: %d baud - %s encoding\n", idev->baud, |
| 279 | (idev->mode==IFF_SIR)?"SIR":((idev->mode==IFF_MIR)?"MIR":"FIR")); | 279 | (idev->mode==IFF_SIR)?"SIR":((idev->mode==IFF_MIR)?"MIR":"FIR")); |
| 280 | sec = div_s64_rem(ktime_us_delta(ktime_get(), idev->last_rx), | 280 | sec = div_s64_rem(ktime_us_delta(ktime_get(), idev->last_rx), |
| @@ -305,10 +305,10 @@ static void vlsi_proc_ring(struct seq_file *seq, struct vlsi_ring *r) · 24 unmodified lines | |||
| 305 | t = atomic_read(&r->tail) & r->mask; | 305 | t = atomic_read(&r->tail) & r->mask; |
| 306 | seq_printf(seq, "head = %d / tail = %d ", h, t); | 306 | seq_printf(seq, "head = %d / tail = %d ", h, t); |
| 307 | if (h == t) | 307 | if (h == t) |
| 308 | seq_printf(seq, "(empty)\n"); | 308 | seq_puts(seq, "(empty)\n"); |
| 309 | else { | 309 | else { |
| 310 | if (((t+1)&r->mask) == h) | 310 | if (((t+1)&r->mask) == h) |
| 311 | seq_printf(seq, "(full)\n"); | 311 | seq_puts(seq, "(full)\n"); |
| 312 | else | 312 | else |
| 313 | seq_printf(seq, "(level = %d)\n", ((unsigned)(t-h) & r->mask)); | 313 | seq_printf(seq, "(level = %d)\n", ((unsigned)(t-h) & r->mask)); |
| 314 | rd = &r->rd[h]; | 314 | rd = &r->rd[h]; |
| @@ -355,13 +355,13 @@ static int vlsi_seq_show(struct seq_file *seq, void *v) · 40 unmodified lines | |||
| 355 | seq_printf(seq, "\nPCI controller down - resume_ok = %d\n", | 355 | seq_printf(seq, "\nPCI controller down - resume_ok = %d\n", |
| 356 | idev->resume_ok); | 356 | idev->resume_ok); |
| 357 | if (netif_running(ndev) && idev->rx_ring && idev->tx_ring) { | 357 | if (netif_running(ndev) && idev->rx_ring && idev->tx_ring) { |
| 358 | seq_printf(seq, "\n--------- RX ring -----------\n\n"); | 358 | seq_puts(seq, "\n--------- RX ring -----------\n\n"); |
| 359 | vlsi_proc_ring(seq, idev->rx_ring); | 359 | vlsi_proc_ring(seq, idev->rx_ring); |
| 360 | seq_printf(seq, "\n--------- TX ring -----------\n\n"); | 360 | seq_puts(seq, "\n--------- TX ring -----------\n\n"); |
| 361 | vlsi_proc_ring(seq, idev->tx_ring); | 361 | vlsi_proc_ring(seq, idev->tx_ring); |
| 362 | } | 362 | } |
| 363 | } | 363 | } |
| 364 | seq_printf(seq, "\n"); | 364 | seq_putc(seq, '\n'); |
| 365 | spin_unlock_irqrestore(&idev->lock, flags); | 365 | spin_unlock_irqrestore(&idev->lock, flags); |
| 366 | 366 | ||
| 367 | return 0; | 367 | return 0; |
| @@ -82,9 +82,9 @@ typedef enum { · 81 unmodified lines | |||
| 82 | extern const char *const irlmp_state[]; | 82 | extern const char *const irlmp_state[]; |
| 83 | extern const char *const irlsap_state[]; | 83 | extern const char *const irlsap_state[]; |
| 84 | 84 | ||
| 85 | void irlmp_watchdog_timer_expired(void *data); | 85 | void irlmp_watchdog_timer_expired(struct timer_list *t); |
| 86 | void irlmp_discovery_timer_expired(void *data); | 86 | void irlmp_discovery_timer_expired(struct timer_list *t); |
| 87 | void irlmp_idle_timer_expired(void *data); | 87 | void irlmp_idle_timer_expired(struct timer_list *t); |
| 88 | 88 | ||
| 89 | void irlmp_do_lap_event(struct lap_cb *self, IRLMP_EVENT event, | 89 | void irlmp_do_lap_event(struct lap_cb *self, IRLMP_EVENT event, |
| 90 | struct sk_buff *skb); | 90 | struct sk_buff *skb); |
| @@ -58,23 +58,23 @@ · 57 unmodified lines | |||
| 58 | #define IR_16000000 0x02 | 58 | #define IR_16000000 0x02 |
| 59 | 59 | ||
| 60 | /* Quality of Service information */ | 60 | /* Quality of Service information */ |
| 61 | typedef struct { | 61 | struct qos_value { |
| 62 | __u32 value; | 62 | __u32 value; |
| 63 | __u16 bits; /* LSB is first byte, MSB is second byte */ | 63 | __u16 bits; /* LSB is first byte, MSB is second byte */ |
| 64 | } qos_value_t; | 64 | }; |
| 65 | 65 | ||
| 66 | struct qos_info { | 66 | struct qos_info { |
| 67 | magic_t magic; | 67 | magic_t magic; |
| 68 | 68 | ||
| 69 | qos_value_t baud_rate; /* IR_11520O | ... */ | 69 | struct qos_value baud_rate; /* IR_11520O | ... */ |
| 70 | qos_value_t max_turn_time; | 70 | struct qos_value max_turn_time; |
| 71 | qos_value_t data_size; | 71 | struct qos_value data_size; |
| 72 | qos_value_t window_size; | 72 | struct qos_value window_size; |
| 73 | qos_value_t additional_bofs; | 73 | struct qos_value additional_bofs; |
| 74 | qos_value_t min_turn_time; | 74 | struct qos_value min_turn_time; |
| 75 | qos_value_t link_disc_time; | 75 | struct qos_value link_disc_time; |
| 76 | 76 | ||
| 77 | qos_value_t power; | 77 | struct qos_value power; |
| 78 | }; | 78 | }; |
| 79 | 79 | ||
| 80 | extern int sysctl_max_baud_rate; | 80 | extern int sysctl_max_baud_rate; |
| @@ -72,14 +72,11 @@ struct lap_cb; · 71 unmodified lines | |||
| 72 | 72 | ||
| 73 | #define WATCHDOG_TIMEOUT (20*HZ) /* 20 sec */ | 73 | #define WATCHDOG_TIMEOUT (20*HZ) /* 20 sec */ |
| 74 | 74 | ||
| 75 | typedef void (*TIMER_CALLBACK)(void *); | 75 | static inline void irda_start_timer(struct timer_list *ptimer, int timeout, |
| 76 | 76 | void (*callback)(struct timer_list *)) | |
| 77 | static inline void irda_start_timer(struct timer_list *ptimer, int timeout, | ||
| 78 | void* data, TIMER_CALLBACK callback) | ||
| 79 | { | 77 | { |
| 80 | ptimer->function = (void (*)(unsigned long)) callback; | 78 | ptimer->function = (TIMER_FUNC_TYPE) callback; |
| 81 | ptimer->data = (unsigned long) data; | 79 | |
| 82 | |||
| 83 | /* Set new value for timer (update or add timer). | 80 | /* Set new value for timer (update or add timer). |
| 84 | * We use mod_timer() because it's more efficient and also | 81 | * We use mod_timer() because it's more efficient and also |
| 85 | * safer with respect to race conditions - Jean II */ | 82 | * safer with respect to race conditions - Jean II */ |
| @@ -429,11 +429,11 @@ static void irda_selective_discovery_indication(discinfo_t *discovery, · 428 unmodified lines | |||
| 429 | * We were waiting for a node to be discovered, but nothing has come up | 429 | * We were waiting for a node to be discovered, but nothing has come up |
| 430 | * so far. Wake up the user and tell him that we failed... | 430 | * so far. Wake up the user and tell him that we failed... |
| 431 | */ | 431 | */ |
| 432 | static void irda_discovery_timeout(u_long priv) | 432 | static void irda_discovery_timeout(struct timer_list *t) |
| 433 | { | 433 | { |
| 434 | struct irda_sock *self; | 434 | struct irda_sock *self; |
| 435 | 435 | ||
| 436 | self = (struct irda_sock *) priv; | 436 | self = from_timer(self, t, watchdog); |
| 437 | BUG_ON(self == NULL); | 437 | BUG_ON(self == NULL); |
| 438 | 438 | ||
| 439 | /* Nothing for the caller */ | 439 | /* Nothing for the caller */ |
| @@ -2505,8 +2505,7 @@ bed: · 2065 unmodified lines | |||
| 2505 | 2505 | ||
| 2506 | /* Set watchdog timer to expire in <val> ms. */ | 2506 | /* Set watchdog timer to expire in <val> ms. */ |
| 2507 | self->errno = 0; | 2507 | self->errno = 0; |
| 2508 | setup_timer(&self->watchdog, irda_discovery_timeout, | 2508 | timer_setup(&self->watchdog, irda_discovery_timeout, 0); |
| 2509 | (unsigned long)self); | ||
| 2510 | mod_timer(&self->watchdog, | 2509 | mod_timer(&self->watchdog, |
| 2511 | jiffies + msecs_to_jiffies(val)); | 2510 | jiffies + msecs_to_jiffies(val)); |
| 2512 | 2511 | ||
| @@ -179,7 +179,7 @@ void irlmp_expire_discoveries(hashbin_t *log, __u32 saddr, int force) · 178 unmodified lines | |||
| 179 | /* Create the client specific buffer */ | 179 | /* Create the client specific buffer */ |
| 180 | n = HASHBIN_GET_SIZE(log); | 180 | n = HASHBIN_GET_SIZE(log); |
| 181 | buffer = kmalloc(n * sizeof(struct irda_device_info), GFP_ATOMIC); | 181 | buffer = kmalloc(n * sizeof(struct irda_device_info), GFP_ATOMIC); |
| 182 | if (buffer == NULL) { | 182 | if (!buffer) { |
| 183 | spin_unlock_irqrestore(&log->hb_spinlock, flags); | 183 | spin_unlock_irqrestore(&log->hb_spinlock, flags); |
| 184 | return; | 184 | return; |
| 185 | } | 185 | } |
| @@ -291,7 +291,7 @@ struct irda_device_info *irlmp_copy_discoveries(hashbin_t *log, int *pn, · 105 unmodified lines | |||
| 291 | /* Create the client specific buffer */ | 291 | /* Create the client specific buffer */ |
| 292 | n = HASHBIN_GET_SIZE(log); | 292 | n = HASHBIN_GET_SIZE(log); |
| 293 | buffer = kmalloc(n * sizeof(struct irda_device_info), GFP_ATOMIC); | 293 | buffer = kmalloc(n * sizeof(struct irda_device_info), GFP_ATOMIC); |
| 294 | if (buffer == NULL) { | 294 | if (!buffer) { |
| 295 | spin_unlock_irqrestore(&log->hb_spinlock, flags); | 295 | spin_unlock_irqrestore(&log->hb_spinlock, flags); |
| 296 | return NULL; | 296 | return NULL; |
| 297 | } | 297 | } |
| @@ -395,7 +395,7 @@ static int ircomm_tty_install(struct tty_driver *driver, struct tty_struct *tty) · 394 unmodified lines | |||
| 395 | self->max_data_size = IRCOMM_TTY_DATA_UNINITIALISED; | 395 | self->max_data_size = IRCOMM_TTY_DATA_UNINITIALISED; |
| 396 | 396 | ||
| 397 | /* Init some important stuff */ | 397 | /* Init some important stuff */ |
| 398 | init_timer(&self->watchdog_timer); | 398 | timer_setup(&self->watchdog_timer, NULL, 0); |
| 399 | spin_lock_init(&self->spinlock); | 399 | spin_lock_init(&self->spinlock); |
| 400 | 400 | ||
| 401 | /* | 401 | /* |
| @@ -52,7 +52,7 @@ static void ircomm_tty_getvalue_confirm(int result, __u16 obj_id, · 51 unmodified lines | |||
| 52 | struct ias_value *value, void *priv); | 52 | struct ias_value *value, void *priv); |
| 53 | static void ircomm_tty_start_watchdog_timer(struct ircomm_tty_cb *self, | 53 | static void ircomm_tty_start_watchdog_timer(struct ircomm_tty_cb *self, |
| 54 | int timeout); | 54 | int timeout); |
| 55 | static void ircomm_tty_watchdog_timer_expired(void *data); | 55 | static void ircomm_tty_watchdog_timer_expired(struct timer_list *timer); |
| 56 | 56 | ||
| 57 | static int ircomm_tty_state_idle(struct ircomm_tty_cb *self, | 57 | static int ircomm_tty_state_idle(struct ircomm_tty_cb *self, |
| 58 | IRCOMM_TTY_EVENT event, | 58 | IRCOMM_TTY_EVENT event, |
| @@ -587,7 +587,7 @@ static void ircomm_tty_start_watchdog_timer(struct ircomm_tty_cb *self, · 528 unmodified lines | |||
| 587 | IRDA_ASSERT(self != NULL, return;); | 587 | IRDA_ASSERT(self != NULL, return;); |
| 588 | IRDA_ASSERT(self->magic == IRCOMM_TTY_MAGIC, return;); | 588 | IRDA_ASSERT(self->magic == IRCOMM_TTY_MAGIC, return;); |
| 589 | 589 | ||
| 590 | irda_start_timer(&self->watchdog_timer, timeout, (void *) self, | 590 | irda_start_timer(&self->watchdog_timer, timeout, |
| 591 | ircomm_tty_watchdog_timer_expired); | 591 | ircomm_tty_watchdog_timer_expired); |
| 592 | } | 592 | } |
| 593 | 593 | ||
| @@ -597,9 +597,9 @@ static void ircomm_tty_start_watchdog_timer(struct ircomm_tty_cb *self, · 3 unmodified lines | |||
| 597 | * Called when the connect procedure have taken to much time. | 597 | * Called when the connect procedure have taken to much time. |
| 598 | * | 598 | * |
| 599 | */ | 599 | */ |
| 600 | static void ircomm_tty_watchdog_timer_expired(void *data) | 600 | static void ircomm_tty_watchdog_timer_expired(struct timer_list *t) |
| 601 | { | 601 | { |
| 602 | struct ircomm_tty_cb *self = (struct ircomm_tty_cb *) data; | 602 | struct ircomm_tty_cb *self = from_timer(self, t, watchdog_timer); |
| 603 | 603 | ||
| 604 | IRDA_ASSERT(self != NULL, return;); | 604 | IRDA_ASSERT(self != NULL, return;); |
| 605 | IRDA_ASSERT(self->magic == IRCOMM_TTY_MAGIC, return;); | 605 | IRDA_ASSERT(self->magic == IRCOMM_TTY_MAGIC, return;); |
| @@ -54,29 +54,30 @@ · 53 unmodified lines | |||
| 54 | 54 | ||
| 55 | static void __irda_task_delete(struct irda_task *task); | 55 | static void __irda_task_delete(struct irda_task *task); |
| 56 | 56 | ||
| 57 | static hashbin_t *dongles = NULL; | 57 | static hashbin_t *dongles; |
| 58 | static hashbin_t *tasks = NULL; | 58 | static hashbin_t *tasks; |
| 59 | 59 | ||
| 60 | static void irda_task_timer_expired(void *data); | 60 | static void irda_task_timer_expired(struct timer_list *timer); |
| 61 | 61 | ||
| 62 | int __init irda_device_init( void) | 62 | int __init irda_device_init(void) |
| 63 | { | 63 | { |
| 64 | dongles = hashbin_new(HB_NOLOCK); | 64 | dongles = hashbin_new(HB_NOLOCK); |
| 65 | if (dongles == NULL) { | 65 | if (!dongles) { |
| 66 | net_warn_ratelimited("IrDA: Can't allocate dongles hashbin!\n"); | 66 | net_warn_ratelimited("IrDA: Can't allocate dongles hashbin!\n"); |
| 67 | return -ENOMEM; | 67 | return -ENOMEM; |
| 68 | } | 68 | } |
| 69 | spin_lock_init(&dongles->hb_spinlock); | 69 | spin_lock_init(&dongles->hb_spinlock); |
| 70 | 70 | ||
| 71 | tasks = hashbin_new(HB_LOCK); | 71 | tasks = hashbin_new(HB_LOCK); |
| 72 | if (tasks == NULL) { | 72 | if (!tasks) { |
| 73 | net_warn_ratelimited("IrDA: Can't allocate tasks hashbin!\n"); | 73 | net_warn_ratelimited("IrDA: Can't allocate tasks hashbin!\n"); |
| 74 | hashbin_delete(dongles, NULL); | 74 | hashbin_delete(dongles, NULL); |
| 75 | return -ENOMEM; | 75 | return -ENOMEM; |
| 76 | } | 76 | } |
| 77 | 77 | ||
| 78 | /* We no longer initialise the driver ourselves here, we let | 78 | /* We no longer initialise the driver ourselves here, we let |
| 79 | * the system do it for us... - Jean II */ | 79 | * the system do it for us... - Jean II |
| 80 | */ | ||
| 80 | 81 | ||
| 81 | return 0; | 82 | return 0; |
| 82 | } | 83 | } |
| @@ -84,6 +85,7 @@ int __init irda_device_init( void) · 1 unmodified line | |||
| 84 | static void leftover_dongle(void *arg) | 85 | static void leftover_dongle(void *arg) |
| 85 | { | 86 | { |
| 86 | struct dongle_reg *reg = arg; | 87 | struct dongle_reg *reg = arg; |
| 88 | |||
| 87 | net_warn_ratelimited("IrDA: Dongle type %x not unregistered\n", | 89 | net_warn_ratelimited("IrDA: Dongle type %x not unregistered\n", |
| 88 | reg->type); | 90 | reg->type); |
| 89 | } | 91 | } |
| @@ -107,7 +109,7 @@ void irda_device_set_media_busy(struct net_device *dev, int status) · 17 unmodified lines | |||
| 107 | 109 | ||
| 108 | pr_debug("%s(%s)\n", __func__, status ? "TRUE" : "FALSE"); | 110 | pr_debug("%s(%s)\n", __func__, status ? "TRUE" : "FALSE"); |
| 109 | 111 | ||
| 110 | self = (struct irlap_cb *) dev->atalk_ptr; | 112 | self = (struct irlap_cb *)dev->atalk_ptr; |
| 111 | 113 | ||
| 112 | /* Some drivers may enable the receive interrupt before calling | 114 | /* Some drivers may enable the receive interrupt before calling |
| 113 | * irlap_open(), or they may disable the receive interrupt | 115 | * irlap_open(), or they may disable the receive interrupt |
| @@ -115,7 +117,8 @@ void irda_device_set_media_busy(struct net_device *dev, int status) · 1 unmodified line | |||
| 115 | * The IrDA stack is protected from this in irlap_driver_rcv(). | 117 | * The IrDA stack is protected from this in irlap_driver_rcv(). |
| 116 | * However, the driver calls directly the wrapper, that calls | 118 | * However, the driver calls directly the wrapper, that calls |
| 117 | * us directly. Make sure we protect ourselves. | 119 | * us directly. Make sure we protect ourselves. |
| 118 | * Jean II */ | 120 | * Jean II |
| 121 | */ | ||
| 119 | if (!self || self->magic != LAP_MAGIC) | 122 | if (!self || self->magic != LAP_MAGIC) |
| 120 | return; | 123 | return; |
| 121 | 124 | ||
| @@ -133,7 +136,6 @@ void irda_device_set_media_busy(struct net_device *dev, int status) · 11 unmodified lines | |||
| 133 | } | 136 | } |
| 134 | EXPORT_SYMBOL(irda_device_set_media_busy); | 137 | EXPORT_SYMBOL(irda_device_set_media_busy); |
| 135 | 138 | ||
| 136 | |||
| 137 | /* | 139 | /* |
| 138 | * Function irda_device_is_receiving (dev) | 140 | * Function irda_device_is_receiving (dev) |
| 139 | * | 141 | * |
| @@ -169,7 +171,7 @@ static void __irda_task_delete(struct irda_task *task) · 29 unmodified lines | |||
| 169 | static void irda_task_delete(struct irda_task *task) | 171 | static void irda_task_delete(struct irda_task *task) |
| 170 | { | 172 | { |
| 171 | /* Unregister task */ | 173 | /* Unregister task */ |
| 172 | hashbin_remove(tasks, (long) task, NULL); | 174 | hashbin_remove(tasks, (long)task, NULL); |
| 173 | 175 | ||
| 174 | __irda_task_delete(task); | 176 | __irda_task_delete(task); |
| 175 | } | 177 | } |
| @@ -231,7 +233,7 @@ static int irda_task_kick(struct irda_task *task) · 55 unmodified lines | |||
| 231 | } | 233 | } |
| 232 | irda_task_delete(task); | 234 | irda_task_delete(task); |
| 233 | } else if (timeout > 0) { | 235 | } else if (timeout > 0) { |
| 234 | irda_start_timer(&task->timer, timeout, (void *) task, | 236 | irda_start_timer(&task->timer, timeout, |
| 235 | irda_task_timer_expired); | 237 | irda_task_timer_expired); |
| 236 | finished = FALSE; | 238 | finished = FALSE; |
| 237 | } else { | 239 | } else { |
| @@ -249,11 +251,9 @@ static int irda_task_kick(struct irda_task *task) · 11 unmodified lines | |||
| 249 | * Task time has expired. We now try to execute task (again), and restart | 251 | * Task time has expired. We now try to execute task (again), and restart |
| 250 | * the timer if the task has not finished yet | 252 | * the timer if the task has not finished yet |
| 251 | */ | 253 | */ |
| 252 | static void irda_task_timer_expired(void *data) | 254 | static void irda_task_timer_expired(struct timer_list *t) |
| 253 | { | 255 | { |
| 254 | struct irda_task *task; | 256 | struct irda_task *task = from_timer(task, t, timer); |
| 255 | |||
| 256 | task = data; | ||
| 257 | 257 | ||
| 258 | irda_task_kick(task); | 258 | irda_task_kick(task); |
| 259 | } | 259 | } |
| @@ -280,8 +280,8 @@ static void irda_device_setup(struct net_device *dev) · 20 unmodified lines | |||
| 280 | 280 | ||
| 281 | /* | 281 | /* |
| 282 | * Funciton alloc_irdadev | 282 | * Funciton alloc_irdadev |
| 283 | * Allocates and sets up an IRDA device in a manner similar to | 283 | * Allocates and sets up an IRDA device in a manner similar to |
| 284 | * alloc_etherdev. | 284 | * alloc_etherdev. |
| 285 | */ | 285 | */ |
| 286 | struct net_device *alloc_irdadev(int sizeof_priv) | 286 | struct net_device *alloc_irdadev(int sizeof_priv) |
| 287 | { | 287 | { |
| @@ -76,12 +76,12 @@ static void iriap_connect_confirm(void *instance, void *sap, · 75 unmodified lines | |||
| 76 | static int iriap_data_indication(void *instance, void *sap, | 76 | static int iriap_data_indication(void *instance, void *sap, |
| 77 | struct sk_buff *skb); | 77 | struct sk_buff *skb); |
| 78 | 78 | ||
| 79 | static void iriap_watchdog_timer_expired(void *data); | 79 | static void iriap_watchdog_timer_expired(struct timer_list *t); |
| 80 | 80 | ||
| 81 | static inline void iriap_start_watchdog_timer(struct iriap_cb *self, | 81 | static inline void iriap_start_watchdog_timer(struct iriap_cb *self, |
| 82 | int timeout) | 82 | int timeout) |
| 83 | { | 83 | { |
| 84 | irda_start_timer(&self->watchdog_timer, timeout, self, | 84 | irda_start_timer(&self->watchdog_timer, timeout, |
| 85 | iriap_watchdog_timer_expired); | 85 | iriap_watchdog_timer_expired); |
| 86 | } | 86 | } |
| 87 | 87 | ||
| @@ -199,7 +199,7 @@ struct iriap_cb *iriap_open(__u8 slsap_sel, int mode, void *priv, · 111 unmodified lines | |||
| 199 | * we connect, so this must have a sane value... Jean II */ | 199 | * we connect, so this must have a sane value... Jean II */ |
| 200 | self->max_header_size = LMP_MAX_HEADER; | 200 | self->max_header_size = LMP_MAX_HEADER; |
| 201 | 201 | ||
| 202 | init_timer(&self->watchdog_timer); | 202 | timer_setup(&self->watchdog_timer, NULL, 0); |
| 203 | 203 | ||
| 204 | hashbin_insert(iriap, (irda_queue_t *) self, (long) self, NULL); | 204 | hashbin_insert(iriap, (irda_queue_t *) self, (long) self, NULL); |
| 205 | 205 | ||
| @@ -946,9 +946,9 @@ void iriap_call_indication(struct iriap_cb *self, struct sk_buff *skb) · 740 unmodified lines | |||
| 946 | * Query has taken too long time, so abort | 946 | * Query has taken too long time, so abort |
| 947 | * | 947 | * |
| 948 | */ | 948 | */ |
| 949 | static void iriap_watchdog_timer_expired(void *data) | 949 | static void iriap_watchdog_timer_expired(struct timer_list *t) |
| 950 | { | 950 | { |
| 951 | struct iriap_cb *self = (struct iriap_cb *) data; | 951 | struct iriap_cb *self = from_timer(self, t, watchdog_timer); |
| 952 | 952 | ||
| 953 | IRDA_ASSERT(self != NULL, return;); | 953 | IRDA_ASSERT(self != NULL, return;); |
| 954 | IRDA_ASSERT(self->magic == IAS_MAGIC, return;); | 954 | IRDA_ASSERT(self->magic == IAS_MAGIC, return;); |
| @@ -68,9 +68,9 @@ static void irlan_check_response_param(struct irlan_cb *self, char *param, · 67 unmodified lines | |||
| 68 | char *value, int val_len); | 68 | char *value, int val_len); |
| 69 | static void irlan_client_open_ctrl_tsap(struct irlan_cb *self); | 69 | static void irlan_client_open_ctrl_tsap(struct irlan_cb *self); |
| 70 | 70 | ||
| 71 | static void irlan_client_kick_timer_expired(void *data) | 71 | static void irlan_client_kick_timer_expired(struct timer_list *t) |
| 72 | { | 72 | { |
| 73 | struct irlan_cb *self = (struct irlan_cb *) data; | 73 | struct irlan_cb *self = from_timer(self, t, client.kick_timer); |
| 74 | 74 | ||
| 75 | IRDA_ASSERT(self != NULL, return;); | 75 | IRDA_ASSERT(self != NULL, return;); |
| 76 | IRDA_ASSERT(self->magic == IRLAN_MAGIC, return;); | 76 | IRDA_ASSERT(self->magic == IRLAN_MAGIC, return;); |
| @@ -89,7 +89,7 @@ static void irlan_client_kick_timer_expired(void *data) · 12 unmodified lines | |||
| 89 | 89 | ||
| 90 | static void irlan_client_start_kick_timer(struct irlan_cb *self, int timeout) | 90 | static void irlan_client_start_kick_timer(struct irlan_cb *self, int timeout) |
| 91 | { | 91 | { |
| 92 | irda_start_timer(&self->client.kick_timer, timeout, (void *) self, | 92 | irda_start_timer(&self->client.kick_timer, timeout, |
| 93 | irlan_client_kick_timer_expired); | 93 | irlan_client_kick_timer_expired); |
| 94 | } | 94 | } |
| 95 | 95 | ||
| @@ -228,8 +228,8 @@ static struct irlan_cb __init *irlan_open(__u32 saddr, __u32 daddr) · 227 unmodified lines | |||
| 228 | 228 | ||
| 229 | self->media = MEDIA_802_3; | 229 | self->media = MEDIA_802_3; |
| 230 | self->disconnect_reason = LM_USER_REQUEST; | 230 | self->disconnect_reason = LM_USER_REQUEST; |
| 231 | init_timer(&self->watchdog_timer); | 231 | timer_setup(&self->watchdog_timer, NULL, 0); |
| 232 | init_timer(&self->client.kick_timer); | 232 | timer_setup(&self->client.kick_timer, NULL, 0); |
| 233 | init_waitqueue_head(&self->open_wait); | 233 | init_waitqueue_head(&self->open_wait); |
| 234 | 234 | ||
| 235 | skb_queue_head_init(&self->client.txq); | 235 | skb_queue_head_init(&self->client.txq); |
| @@ -148,14 +148,14 @@ struct irlap_cb *irlap_open(struct net_device *dev, struct qos_info *qos, · 147 unmodified lines | |||
| 148 | /* Copy to the driver */ | 148 | /* Copy to the driver */ |
| 149 | memcpy(dev->dev_addr, &self->saddr, 4); | 149 | memcpy(dev->dev_addr, &self->saddr, 4); |
| 150 | 150 | ||
| 151 | init_timer(&self->slot_timer); | 151 | timer_setup(&self->slot_timer, NULL, 0); |
| 152 | init_timer(&self->query_timer); | 152 | timer_setup(&self->query_timer, NULL, 0); |
| 153 | init_timer(&self->discovery_timer); | 153 | timer_setup(&self->discovery_timer, NULL, 0); |
| 154 | init_timer(&self->final_timer); | 154 | timer_setup(&self->final_timer, NULL, 0); |
| 155 | init_timer(&self->poll_timer); | 155 | timer_setup(&self->poll_timer, NULL, 0); |
| 156 | init_timer(&self->wd_timer); | 156 | timer_setup(&self->wd_timer, NULL, 0); |
| 157 | init_timer(&self->backoff_timer); | 157 | timer_setup(&self->backoff_timer, NULL, 0); |
| 158 | init_timer(&self->media_busy_timer); | 158 | timer_setup(&self->media_busy_timer, NULL, 0); |
| 159 | 159 | ||
| 160 | irlap_apply_default_connection_parameters(self); | 160 | irlap_apply_default_connection_parameters(self); |
| 161 | 161 | ||
| @@ -163,9 +163,9 @@ static int (*state[])(struct irlap_cb *self, IRLAP_EVENT event, · 162 unmodified lines | |||
| 163 | * Poll timer has expired. Normally we must now send a RR frame to the | 163 | * Poll timer has expired. Normally we must now send a RR frame to the |
| 164 | * remote device | 164 | * remote device |
| 165 | */ | 165 | */ |
| 166 | static void irlap_poll_timer_expired(void *data) | 166 | static void irlap_poll_timer_expired(struct timer_list *t) |
| 167 | { | 167 | { |
| 168 | struct irlap_cb *self = (struct irlap_cb *) data; | 168 | struct irlap_cb *self = from_timer(self, t, poll_timer); |
| 169 | 169 | ||
| 170 | IRDA_ASSERT(self != NULL, return;); | 170 | IRDA_ASSERT(self != NULL, return;); |
| 171 | IRDA_ASSERT(self->magic == LAP_MAGIC, return;); | 171 | IRDA_ASSERT(self->magic == LAP_MAGIC, return;); |
| @@ -222,7 +222,7 @@ static void irlap_start_poll_timer(struct irlap_cb *self, int timeout) · 50 unmodified lines | |||
| 222 | if (timeout == 0) | 222 | if (timeout == 0) |
| 223 | irlap_do_event(self, POLL_TIMER_EXPIRED, NULL, NULL); | 223 | irlap_do_event(self, POLL_TIMER_EXPIRED, NULL, NULL); |
| 224 | else | 224 | else |
| 225 | irda_start_timer(&self->poll_timer, timeout, self, | 225 | irda_start_timer(&self->poll_timer, timeout, |
| 226 | irlap_poll_timer_expired); | 226 | irlap_poll_timer_expired); |
| 227 | } | 227 | } |
| 228 | 228 | ||
| @@ -109,7 +109,7 @@ int __init irlmp_init(void) · 108 unmodified lines | |||
| 109 | irlmp->last_lsap_sel = 0x0f; /* Reserved 0x00-0x0f */ | 109 | irlmp->last_lsap_sel = 0x0f; /* Reserved 0x00-0x0f */ |
| 110 | strcpy(sysctl_devname, "Linux"); | 110 | strcpy(sysctl_devname, "Linux"); |
| 111 | 111 | ||
| 112 | init_timer(&irlmp->discovery_timer); | 112 | timer_setup(&irlmp->discovery_timer, NULL, 0); |
| 113 | 113 | ||
| 114 | /* Do discovery every 3 seconds, conditionally */ | 114 | /* Do discovery every 3 seconds, conditionally */ |
| 115 | if (sysctl_discovery) | 115 | if (sysctl_discovery) |
| @@ -185,7 +185,7 @@ struct lsap_cb *irlmp_open_lsap(__u8 slsap_sel, notify_t *notify, __u8 pid) · 69 unmodified lines | |||
| 185 | self->dlsap_sel = LSAP_ANY; | 185 | self->dlsap_sel = LSAP_ANY; |
| 186 | /* self->connected = FALSE; -> already NULL via memset() */ | 186 | /* self->connected = FALSE; -> already NULL via memset() */ |
| 187 | 187 | ||
| 188 | init_timer(&self->watchdog_timer); | 188 | timer_setup(&self->watchdog_timer, NULL, 0); |
| 189 | 189 | ||
| 190 | self->notify = *notify; | 190 | self->notify = *notify; |
| 191 | 191 | ||
| @@ -311,7 +311,7 @@ void irlmp_register_link(struct irlap_cb *irlap, __u32 saddr, notify_t *notify) · 119 unmodified lines | |||
| 311 | 311 | ||
| 312 | lap->lap_state = LAP_STANDBY; | 312 | lap->lap_state = LAP_STANDBY; |
| 313 | 313 | ||
| 314 | init_timer(&lap->idle_timer); | 314 | timer_setup(&lap->idle_timer, NULL, 0); |
| 315 | 315 | ||
| 316 | /* | 316 | /* |
| 317 | * Insert into queue of LMP links | 317 | * Insert into queue of LMP links |
| @@ -655,7 +655,7 @@ struct lsap_cb *irlmp_dup(struct lsap_cb *orig, void *instance) · 337 unmodified lines | |||
| 655 | /* Not everything is the same */ | 655 | /* Not everything is the same */ |
| 656 | new->notify.instance = instance; | 656 | new->notify.instance = instance; |
| 657 | 657 | ||
| 658 | init_timer(&new->watchdog_timer); | 658 | timer_setup(&new->watchdog_timer, NULL, 0); |
| 659 | 659 | ||
| 660 | hashbin_insert(irlmp->unconnected_lsaps, (irda_queue_t *) new, | 660 | hashbin_insert(irlmp->unconnected_lsaps, (irda_queue_t *) new, |
| 661 | (long) new, NULL); | 661 | (long) new, NULL); |
| @@ -165,7 +165,7 @@ void irlmp_do_lap_event(struct lap_cb *self, IRLMP_EVENT event, · 164 unmodified lines | |||
| 165 | (*lap_state[self->lap_state]) (self, event, skb); | 165 | (*lap_state[self->lap_state]) (self, event, skb); |
| 166 | } | 166 | } |
| 167 | 167 | ||
| 168 | void irlmp_discovery_timer_expired(void *data) | 168 | void irlmp_discovery_timer_expired(struct timer_list *t) |
| 169 | { | 169 | { |
| 170 | /* We always cleanup the log (active & passive discovery) */ | 170 | /* We always cleanup the log (active & passive discovery) */ |
| 171 | irlmp_do_expiry(); | 171 | irlmp_do_expiry(); |
| @@ -176,9 +176,9 @@ void irlmp_discovery_timer_expired(void *data) · 4 unmodified lines | |||
| 176 | irlmp_start_discovery_timer(irlmp, sysctl_discovery_timeout * HZ); | 176 | irlmp_start_discovery_timer(irlmp, sysctl_discovery_timeout * HZ); |
| 177 | } | 177 | } |
| 178 | 178 | ||
| 179 | void irlmp_watchdog_timer_expired(void *data) | 179 | void irlmp_watchdog_timer_expired(struct timer_list *t) |
| 180 | { | 180 | { |
| 181 | struct lsap_cb *self = (struct lsap_cb *) data; | 181 | struct lsap_cb *self = from_timer(self, t, watchdog_timer); |
| 182 | 182 | ||
| 183 | IRDA_ASSERT(self != NULL, return;); | 183 | IRDA_ASSERT(self != NULL, return;); |
| 184 | IRDA_ASSERT(self->magic == LMP_LSAP_MAGIC, return;); | 184 | IRDA_ASSERT(self->magic == LMP_LSAP_MAGIC, return;); |
| @@ -186,9 +186,9 @@ void irlmp_watchdog_timer_expired(void *data) · 1 unmodified line | |||
| 186 | irlmp_do_lsap_event(self, LM_WATCHDOG_TIMEOUT, NULL); | 186 | irlmp_do_lsap_event(self, LM_WATCHDOG_TIMEOUT, NULL); |
| 187 | } | 187 | } |
| 188 | 188 | ||
| 189 | void irlmp_idle_timer_expired(void *data) | 189 | void irlmp_idle_timer_expired(struct timer_list *t) |
| 190 | { | 190 | { |
| 191 | struct lap_cb *self = (struct lap_cb *) data; | 191 | struct lap_cb *self = from_timer(self, t, idle_timer); |
| 192 | 192 | ||
| 193 | IRDA_ASSERT(self != NULL, return;); | 193 | IRDA_ASSERT(self != NULL, return;); |
| 194 | IRDA_ASSERT(self->magic == LMP_LAP_MAGIC, return;); | 194 | IRDA_ASSERT(self->magic == LMP_LAP_MAGIC, return;); |
| @@ -217,7 +217,8 @@ static __u32 hash( const char* name) · 216 unmodified lines | |||
| 217 | 217 | ||
| 218 | while(*name) { | 218 | while(*name) { |
| 219 | h = (h<<4) + *name++; | 219 | h = (h<<4) + *name++; |
| 220 | if ((g = (h & 0xf0000000))) | 220 | g = h & 0xf0000000; |
| 221 | if (g) | ||
| 221 | h ^=g>>24; | 222 | h ^=g>>24; |
| 222 | h &=~g; | 223 | h &=~g; |
| 223 | } | 224 | } |
| @@ -62,7 +62,6 @@ static void irttp_run_rx_queue(struct tsap_cb *self); · 61 unmodified lines | |||
| 62 | static void irttp_flush_queues(struct tsap_cb *self); | 62 | static void irttp_flush_queues(struct tsap_cb *self); |
| 63 | static void irttp_fragment_skb(struct tsap_cb *self, struct sk_buff *skb); | 63 | static void irttp_fragment_skb(struct tsap_cb *self, struct sk_buff *skb); |
| 64 | static struct sk_buff *irttp_reassemble_skb(struct tsap_cb *self); | 64 | static struct sk_buff *irttp_reassemble_skb(struct tsap_cb *self); |
| 65 | static void irttp_todo_expired(unsigned long data); | ||
| 66 | static int irttp_param_max_sdu_size(void *instance, irda_param_t *param, | 65 | static int irttp_param_max_sdu_size(void *instance, irda_param_t *param, |
| 67 | int get); | 66 | int get); |
| 68 | 67 | ||
| @@ -160,9 +159,9 @@ static inline void irttp_start_todo_timer(struct tsap_cb *self, int timeout) · 91 unmodified lines | |||
| 160 | * killed (need user context), and we can't guarantee that here... | 159 | * killed (need user context), and we can't guarantee that here... |
| 161 | * Jean II | 160 | * Jean II |
| 162 | */ | 161 | */ |
| 163 | static void irttp_todo_expired(unsigned long data) | 162 | static void irttp_todo_expired(struct timer_list *t) |
| 164 | { | 163 | { |
| 165 | struct tsap_cb *self = (struct tsap_cb *) data; | 164 | struct tsap_cb *self = from_timer(self, t, todo_timer); |
| 166 | 165 | ||
| 167 | /* Check that we still exist */ | 166 | /* Check that we still exist */ |
| 168 | if (!self || self->magic != TTP_TSAP_MAGIC) | 167 | if (!self || self->magic != TTP_TSAP_MAGIC) |
| @@ -374,7 +373,7 @@ static int irttp_param_max_sdu_size(void *instance, irda_param_t *param, · 205 unmodified lines | |||
| 374 | static void irttp_init_tsap(struct tsap_cb *tsap) | 373 | static void irttp_init_tsap(struct tsap_cb *tsap) |
| 375 | { | 374 | { |
| 376 | spin_lock_init(&tsap->lock); | 375 | spin_lock_init(&tsap->lock); |
| 377 | init_timer(&tsap->todo_timer); | 376 | timer_setup(&tsap->todo_timer, irttp_todo_expired, 0); |
| 378 | 377 | ||
| 379 | skb_queue_head_init(&tsap->rx_queue); | 378 | skb_queue_head_init(&tsap->rx_queue); |
| 380 | skb_queue_head_init(&tsap->tx_queue); | 379 | skb_queue_head_init(&tsap->tx_queue); |
| @@ -410,10 +409,6 @@ struct tsap_cb *irttp_open_tsap(__u8 stsap_sel, int credit, notify_t *notify) · 29 unmodified lines | |||
| 410 | /* Initialize internal objects */ | 409 | /* Initialize internal objects */ |
| 411 | irttp_init_tsap(self); | 410 | irttp_init_tsap(self); |
| 412 | 411 | ||
| 413 | /* Initialise todo timer */ | ||
| 414 | self->todo_timer.data = (unsigned long) self; | ||
| 415 | self->todo_timer.function = &irttp_todo_expired; | ||
| 416 | |||
| 417 | /* Initialize callbacks for IrLMP to use */ | 412 | /* Initialize callbacks for IrLMP to use */ |
| 418 | irda_notify_init(&ttp_notify); | 413 | irda_notify_init(&ttp_notify); |
| 419 | ttp_notify.connect_confirm = irttp_connect_confirm; | 414 | ttp_notify.connect_confirm = irttp_connect_confirm; |
| @@ -34,16 +34,16 @@ · 33 unmodified lines | |||
| 34 | 34 | ||
| 35 | extern int sysctl_slot_timeout; | 35 | extern int sysctl_slot_timeout; |
| 36 | 36 | ||
| 37 | static void irlap_slot_timer_expired(void* data); | 37 | static void irlap_slot_timer_expired(struct timer_list *t); |
| 38 | static void irlap_query_timer_expired(void* data); | 38 | static void irlap_query_timer_expired(struct timer_list *t); |
| 39 | static void irlap_final_timer_expired(void* data); | 39 | static void irlap_final_timer_expired(struct timer_list *t); |
| 40 | static void irlap_wd_timer_expired(void* data); | 40 | static void irlap_wd_timer_expired(struct timer_list *t); |
| 41 | static void irlap_backoff_timer_expired(void* data); | 41 | static void irlap_backoff_timer_expired(struct timer_list *t); |
| 42 | static void irlap_media_busy_expired(void* data); | 42 | static void irlap_media_busy_expired(struct timer_list *t); |
| 43 | 43 | ||
| 44 | void irlap_start_slot_timer(struct irlap_cb *self, int timeout) | 44 | void irlap_start_slot_timer(struct irlap_cb *self, int timeout) |
| 45 | { | 45 | { |
| 46 | irda_start_timer(&self->slot_timer, timeout, (void *) self, | 46 | irda_start_timer(&self->slot_timer, timeout, |
| 47 | irlap_slot_timer_expired); | 47 | irlap_slot_timer_expired); |
| 48 | } | 48 | } |
| 49 | 49 | ||
| @@ -66,32 +66,32 @@ void irlap_start_query_timer(struct irlap_cb *self, int S, int s) · 16 unmodified lines | |||
| 66 | /* Set or re-set the timer. We reset the timer for each received | 66 | /* Set or re-set the timer. We reset the timer for each received |
| 67 | * discovery query, which allow us to automatically adjust to | 67 | * discovery query, which allow us to automatically adjust to |
| 68 | * the speed of the peer discovery (faster or slower). Jean II */ | 68 | * the speed of the peer discovery (faster or slower). Jean II */ |
| 69 | irda_start_timer( &self->query_timer, timeout, (void *) self, | 69 | irda_start_timer(&self->query_timer, timeout, |
| 70 | irlap_query_timer_expired); | 70 | irlap_query_timer_expired); |
| 71 | } | 71 | } |
| 72 | 72 | ||
| 73 | void irlap_start_final_timer(struct irlap_cb *self, int timeout) | 73 | void irlap_start_final_timer(struct irlap_cb *self, int timeout) |
| 74 | { | 74 | { |
| 75 | irda_start_timer(&self->final_timer, timeout, (void *) self, | 75 | irda_start_timer(&self->final_timer, timeout, |
| 76 | irlap_final_timer_expired); | 76 | irlap_final_timer_expired); |
| 77 | } | 77 | } |
| 78 | 78 | ||
| 79 | void irlap_start_wd_timer(struct irlap_cb *self, int timeout) | 79 | void irlap_start_wd_timer(struct irlap_cb *self, int timeout) |
| 80 | { | 80 | { |
| 81 | irda_start_timer(&self->wd_timer, timeout, (void *) self, | 81 | irda_start_timer(&self->wd_timer, timeout, |
| 82 | irlap_wd_timer_expired); | 82 | irlap_wd_timer_expired); |
| 83 | } | 83 | } |
| 84 | 84 | ||
| 85 | void irlap_start_backoff_timer(struct irlap_cb *self, int timeout) | 85 | void irlap_start_backoff_timer(struct irlap_cb *self, int timeout) |
| 86 | { | 86 | { |
| 87 | irda_start_timer(&self->backoff_timer, timeout, (void *) self, | 87 | irda_start_timer(&self->backoff_timer, timeout, |
| 88 | irlap_backoff_timer_expired); | 88 | irlap_backoff_timer_expired); |
| 89 | } | 89 | } |
| 90 | 90 | ||
| 91 | void irlap_start_mbusy_timer(struct irlap_cb *self, int timeout) | 91 | void irlap_start_mbusy_timer(struct irlap_cb *self, int timeout) |
| 92 | { | 92 | { |
| 93 | irda_start_timer(&self->media_busy_timer, timeout, | 93 | irda_start_timer(&self->media_busy_timer, timeout, |
| 94 | (void *) self, irlap_media_busy_expired); | 94 | irlap_media_busy_expired); |
| 95 | } | 95 | } |
| 96 | 96 | ||
| 97 | void irlap_stop_mbusy_timer(struct irlap_cb *self) | 97 | void irlap_stop_mbusy_timer(struct irlap_cb *self) |
| @@ -110,19 +110,19 @@ void irlap_stop_mbusy_timer(struct irlap_cb *self) · 12 unmodified lines | |||
| 110 | 110 | ||
| 111 | void irlmp_start_watchdog_timer(struct lsap_cb *self, int timeout) | 111 | void irlmp_start_watchdog_timer(struct lsap_cb *self, int timeout) |
| 112 | { | 112 | { |
| 113 | irda_start_timer(&self->watchdog_timer, timeout, (void *) self, | 113 | irda_start_timer(&self->watchdog_timer, timeout, |
| 114 | irlmp_watchdog_timer_expired); | 114 | irlmp_watchdog_timer_expired); |
| 115 | } | 115 | } |
| 116 | 116 | ||
| 117 | void irlmp_start_discovery_timer(struct irlmp_cb *self, int timeout) | 117 | void irlmp_start_discovery_timer(struct irlmp_cb *self, int timeout) |
| 118 | { | 118 | { |
| 119 | irda_start_timer(&self->discovery_timer, timeout, (void *) self, | 119 | irda_start_timer(&self->discovery_timer, timeout, |
| 120 | irlmp_discovery_timer_expired); | 120 | irlmp_discovery_timer_expired); |
| 121 | } | 121 | } |
| 122 | 122 | ||
| 123 | void irlmp_start_idle_timer(struct lap_cb *self, int timeout) | 123 | void irlmp_start_idle_timer(struct lap_cb *self, int timeout) |
| 124 | { | 124 | { |
| 125 | irda_start_timer(&self->idle_timer, timeout, (void *) self, | 125 | irda_start_timer(&self->idle_timer, timeout, |
| 126 | irlmp_idle_timer_expired); | 126 | irlmp_idle_timer_expired); |
| 127 | } | 127 | } |
| 128 | 128 | ||
| @@ -138,9 +138,9 @@ void irlmp_stop_idle_timer(struct lap_cb *self) · 9 unmodified lines | |||
| 138 | * IrLAP slot timer has expired | 138 | * IrLAP slot timer has expired |
| 139 | * | 139 | * |
| 140 | */ | 140 | */ |
| 141 | static void irlap_slot_timer_expired(void *data) | 141 | static void irlap_slot_timer_expired(struct timer_list *t) |
| 142 | { | 142 | { |
| 143 | struct irlap_cb *self = (struct irlap_cb *) data; | 143 | struct irlap_cb *self = from_timer(self, t, slot_timer); |
| 144 | 144 | ||
| 145 | IRDA_ASSERT(self != NULL, return;); | 145 | IRDA_ASSERT(self != NULL, return;); |
| 146 | IRDA_ASSERT(self->magic == LAP_MAGIC, return;); | 146 | IRDA_ASSERT(self->magic == LAP_MAGIC, return;); |
| @@ -154,9 +154,9 @@ static void irlap_slot_timer_expired(void *data) · 7 unmodified lines | |||
| 154 | * IrLAP query timer has expired | 154 | * IrLAP query timer has expired |
| 155 | * | 155 | * |
| 156 | */ | 156 | */ |
| 157 | static void irlap_query_timer_expired(void *data) | 157 | static void irlap_query_timer_expired(struct timer_list *t) |
| 158 | { | 158 | { |
| 159 | struct irlap_cb *self = (struct irlap_cb *) data; | 159 | struct irlap_cb *self = from_timer(self, t, query_timer); |
| 160 | 160 | ||
| 161 | IRDA_ASSERT(self != NULL, return;); | 161 | IRDA_ASSERT(self != NULL, return;); |
| 162 | IRDA_ASSERT(self->magic == LAP_MAGIC, return;); | 162 | IRDA_ASSERT(self->magic == LAP_MAGIC, return;); |
| @@ -170,9 +170,9 @@ static void irlap_query_timer_expired(void *data) · 7 unmodified lines | |||
| 170 | * | 170 | * |
| 171 | * | 171 | * |
| 172 | */ | 172 | */ |
| 173 | static void irlap_final_timer_expired(void *data) | 173 | static void irlap_final_timer_expired(struct timer_list *t) |
| 174 | { | 174 | { |
| 175 | struct irlap_cb *self = (struct irlap_cb *) data; | 175 | struct irlap_cb *self = from_timer(self, t, final_timer); |
| 176 | 176 | ||
| 177 | IRDA_ASSERT(self != NULL, return;); | 177 | IRDA_ASSERT(self != NULL, return;); |
| 178 | IRDA_ASSERT(self->magic == LAP_MAGIC, return;); | 178 | IRDA_ASSERT(self->magic == LAP_MAGIC, return;); |
| @@ -186,9 +186,9 @@ static void irlap_final_timer_expired(void *data) · 7 unmodified lines | |||
| 186 | * | 186 | * |
| 187 | * | 187 | * |
| 188 | */ | 188 | */ |
| 189 | static void irlap_wd_timer_expired(void *data) | 189 | static void irlap_wd_timer_expired(struct timer_list *t) |
| 190 | { | 190 | { |
| 191 | struct irlap_cb *self = (struct irlap_cb *) data; | 191 | struct irlap_cb *self = from_timer(self, t, wd_timer); |
| 192 | 192 | ||
| 193 | IRDA_ASSERT(self != NULL, return;); | 193 | IRDA_ASSERT(self != NULL, return;); |
| 194 | IRDA_ASSERT(self->magic == LAP_MAGIC, return;); | 194 | IRDA_ASSERT(self->magic == LAP_MAGIC, return;); |
| @@ -202,9 +202,9 @@ static void irlap_wd_timer_expired(void *data) · 7 unmodified lines | |||
| 202 | * | 202 | * |
| 203 | * | 203 | * |
| 204 | */ | 204 | */ |
| 205 | static void irlap_backoff_timer_expired(void *data) | 205 | static void irlap_backoff_timer_expired(struct timer_list *t) |
| 206 | { | 206 | { |
| 207 | struct irlap_cb *self = (struct irlap_cb *) data; | 207 | struct irlap_cb *self = from_timer(self, t, backoff_timer); |
| 208 | 208 | ||
| 209 | IRDA_ASSERT(self != NULL, return;); | 209 | IRDA_ASSERT(self != NULL, return;); |
| 210 | IRDA_ASSERT(self->magic == LAP_MAGIC, return;); | 210 | IRDA_ASSERT(self->magic == LAP_MAGIC, return;); |
| @@ -218,9 +218,9 @@ static void irlap_backoff_timer_expired(void *data) · 7 unmodified lines | |||
| 218 | * | 218 | * |
| 219 | * | 219 | * |
| 220 | */ | 220 | */ |
| 221 | static void irlap_media_busy_expired(void *data) | 221 | static void irlap_media_busy_expired(struct timer_list *t) |
| 222 | { | 222 | { |
| 223 | struct irlap_cb *self = (struct irlap_cb *) data; | 223 | struct irlap_cb *self = from_timer(self, t, media_busy_timer); |
| 224 | 224 | ||
| 225 | IRDA_ASSERT(self != NULL, return;); | 225 | IRDA_ASSERT(self != NULL, return;); |
| 226 | 226 | ||
| @@ -114,7 +114,7 @@ int ks_wlan_update_phy_information(struct ks_wlan_private *priv) · 113 unmodified lines | |||
| 114 | } | 114 | } |
| 115 | 115 | ||
| 116 | static | 116 | static |
| 117 | void ks_wlan_update_phyinfo_timeout(unsigned long ptr) | 117 | void ks_wlan_update_phyinfo_timeout(struct timer_list *unused) |
| 118 | { | 118 | { |
| 119 | DPRINTK(4, "in_interrupt = %ld\n", in_interrupt()); | 119 | DPRINTK(4, "in_interrupt = %ld\n", in_interrupt()); |
| 120 | atomic_set(&update_phyinfo, 0); | 120 | atomic_set(&update_phyinfo, 0); |
| @@ -473,13 +473,16 @@ static int ks_wlan_set_rate(struct net_device *dev, · 352 unmodified lines | |||
| 473 | priv->reg.rate_set.body[3] = | 473 | priv->reg.rate_set.body[3] = |
| 474 | TX_RATE_11M; | 474 | TX_RATE_11M; |
| 475 | i++; | 475 | i++; |
| 476 | /* fall through */ | ||
| 476 | case 5500000: | 477 | case 5500000: |
| 477 | priv->reg.rate_set.body[2] = TX_RATE_5M; | 478 | priv->reg.rate_set.body[2] = TX_RATE_5M; |
| 478 | i++; | 479 | i++; |
| 480 | /* fall through */ | ||
| 479 | case 2000000: | 481 | case 2000000: |
| 480 | priv->reg.rate_set.body[1] = | 482 | priv->reg.rate_set.body[1] = |
| 481 | TX_RATE_2M | BASIC_RATE; | 483 | TX_RATE_2M | BASIC_RATE; |
| 482 | i++; | 484 | i++; |
| 485 | /* fall through */ | ||
| 483 | case 1000000: | 486 | case 1000000: |
| 484 | priv->reg.rate_set.body[0] = | 487 | priv->reg.rate_set.body[0] = |
| 485 | TX_RATE_1M | BASIC_RATE; | 488 | TX_RATE_1M | BASIC_RATE; |
| @@ -535,14 +538,17 @@ static int ks_wlan_set_rate(struct net_device *dev, · 49 unmodified lines | |||
| 535 | priv->reg.rate_set.body[11] = | 538 | priv->reg.rate_set.body[11] = |
| 536 | TX_RATE_54M; | 539 | TX_RATE_54M; |
| 537 | i++; | 540 | i++; |
| 541 | /* fall through */ | ||
| 538 | case 48000000: | 542 | case 48000000: |
| 539 | priv->reg.rate_set.body[10] = | 543 | priv->reg.rate_set.body[10] = |
| 540 | TX_RATE_48M; | 544 | TX_RATE_48M; |
| 541 | i++; | 545 | i++; |
| 546 | /* fall through */ | ||
| 542 | case 36000000: | 547 | case 36000000: |
| 543 | priv->reg.rate_set.body[9] = | 548 | priv->reg.rate_set.body[9] = |
| 544 | TX_RATE_36M; | 549 | TX_RATE_36M; |
| 545 | i++; | 550 | i++; |
| 551 | /* fall through */ | ||
| 546 | case 24000000: | 552 | case 24000000: |
| 547 | case 18000000: | 553 | case 18000000: |
| 548 | case 12000000: | 554 | case 12000000: |
| @@ -619,14 +625,17 @@ static int ks_wlan_set_rate(struct net_device *dev, · 70 unmodified lines | |||
| 619 | TX_RATE_6M | BASIC_RATE; | 625 | TX_RATE_6M | BASIC_RATE; |
| 620 | i++; | 626 | i++; |
| 621 | } | 627 | } |
| 628 | /* fall through */ | ||
| 622 | case 5500000: | 629 | case 5500000: |
| 623 | priv->reg.rate_set.body[2] = | 630 | priv->reg.rate_set.body[2] = |
| 624 | TX_RATE_5M | BASIC_RATE; | 631 | TX_RATE_5M | BASIC_RATE; |
| 625 | i++; | 632 | i++; |
| 633 | /* fall through */ | ||
| 626 | case 2000000: | 634 | case 2000000: |
| 627 | priv->reg.rate_set.body[1] = | 635 | priv->reg.rate_set.body[1] = |
| 628 | TX_RATE_2M | BASIC_RATE; | 636 | TX_RATE_2M | BASIC_RATE; |
| 629 | i++; | 637 | i++; |
| 638 | /* fall through */ | ||
| 630 | case 1000000: | 639 | case 1000000: |
| 631 | priv->reg.rate_set.body[0] = | 640 | priv->reg.rate_set.body[0] = |
| 632 | TX_RATE_1M | BASIC_RATE; | 641 | TX_RATE_1M | BASIC_RATE; |
| @@ -2010,6 +2019,7 @@ static int ks_wlan_set_mlme(struct net_device *dev, · 1377 unmodified lines | |||
| 2010 | case IW_MLME_DEAUTH: | 2019 | case IW_MLME_DEAUTH: |
| 2011 | if (mlme->reason_code == WLAN_REASON_MIC_FAILURE) | 2020 | if (mlme->reason_code == WLAN_REASON_MIC_FAILURE) |
| 2012 | return 0; | 2021 | return 0; |
| 2022 | /* fall through */ | ||
| 2013 | case IW_MLME_DISASSOC: | 2023 | case IW_MLME_DISASSOC: |
| 2014 | mode = 1; | 2024 | mode = 1; |
| 2015 | return ks_wlan_set_stop_request(dev, NULL, &mode, NULL); | 2025 | return ks_wlan_set_stop_request(dev, NULL, &mode, NULL); |
| @@ -2941,8 +2951,7 @@ int ks_wlan_net_start(struct net_device *dev) · 925 unmodified lines | |||
| 2941 | 2951 | ||
| 2942 | /* phy information update timer */ | 2952 | /* phy information update timer */ |
| 2943 | atomic_set(&update_phyinfo, 0); | 2953 | atomic_set(&update_phyinfo, 0); |
| 2944 | setup_timer(&update_phyinfo_timer, ks_wlan_update_phyinfo_timeout, | 2954 | timer_setup(&update_phyinfo_timer, ks_wlan_update_phyinfo_timeout, 0); |
| 2945 | (unsigned long)priv); | ||
| 2946 | 2955 | ||
| 2947 | /* dummy address set */ | 2956 | /* dummy address set */ |
| 2948 | memcpy(priv->eth_addr, dummy_addr, ETH_ALEN); | 2957 | memcpy(priv->eth_addr, dummy_addr, ETH_ALEN); |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* GPL HEADER START | 2 | /* GPL HEADER START |
| 2 | * | 3 | * |
| 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | 4 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -160,9 +161,9 @@ struct lnet_libmd { · 156 unmodified lines | |||
| 160 | } md_iov; | 161 | } md_iov; |
| 161 | }; | 162 | }; |
| 162 | 163 | ||
| 163 | #define LNET_MD_FLAG_ZOMBIE (1 << 0) | 164 | #define LNET_MD_FLAG_ZOMBIE BIT(0) |
| 164 | #define LNET_MD_FLAG_AUTO_UNLINK (1 << 1) | 165 | #define LNET_MD_FLAG_AUTO_UNLINK BIT(1) |
| 165 | #define LNET_MD_FLAG_ABORTED (1 << 2) | 166 | #define LNET_MD_FLAG_ABORTED BIT(2) |
| 166 | 167 | ||
| 167 | struct lnet_test_peer { | 168 | struct lnet_test_peer { |
| 168 | /* info about peers we are trying to fail */ | 169 | /* info about peers we are trying to fail */ |
| @@ -287,9 +288,9 @@ struct lnet_ni { · 118 unmodified lines | |||
| 287 | * of old LNet, so there shouldn't be any compatibility issue | 288 | * of old LNet, so there shouldn't be any compatibility issue |
| 288 | */ | 289 | */ |
| 289 | #define LNET_PING_FEAT_INVAL (0) /* no feature */ | 290 | #define LNET_PING_FEAT_INVAL (0) /* no feature */ |
| 290 | #define LNET_PING_FEAT_BASE (1 << 0) /* just a ping */ | 291 | #define LNET_PING_FEAT_BASE BIT(0) /* just a ping */ |
| 291 | #define LNET_PING_FEAT_NI_STATUS (1 << 1) /* return NI status */ | 292 | #define LNET_PING_FEAT_NI_STATUS BIT(1) /* return NI status */ |
| 292 | #define LNET_PING_FEAT_RTE_DISABLED (1 << 2) /* Routing enabled */ | 293 | #define LNET_PING_FEAT_RTE_DISABLED BIT(2) /* Routing enabled */ |
| 293 | 294 | ||
| 294 | #define LNET_PING_FEAT_MASK (LNET_PING_FEAT_BASE | \ | 295 | #define LNET_PING_FEAT_MASK (LNET_PING_FEAT_BASE | \ |
| 295 | LNET_PING_FEAT_NI_STATUS) | 296 | LNET_PING_FEAT_NI_STATUS) |
| @@ -440,23 +441,21 @@ struct lnet_rtrbuf { · 144 unmodified lines | |||
| 440 | 441 | ||
| 441 | enum lnet_match_flags { | 442 | enum lnet_match_flags { |
| 442 | /* Didn't match anything */ | 443 | /* Didn't match anything */ |
| 443 | LNET_MATCHMD_NONE = (1 << 0), | 444 | LNET_MATCHMD_NONE = BIT(0), |
| 444 | /* Matched OK */ | 445 | /* Matched OK */ |
| 445 | LNET_MATCHMD_OK = (1 << 1), | 446 | LNET_MATCHMD_OK = BIT(1), |
| 446 | /* Must be discarded */ | 447 | /* Must be discarded */ |
| 447 | LNET_MATCHMD_DROP = (1 << 2), | 448 | LNET_MATCHMD_DROP = BIT(2), |
| 448 | /* match and buffer is exhausted */ | 449 | /* match and buffer is exhausted */ |
| 449 | LNET_MATCHMD_EXHAUSTED = (1 << 3), | 450 | LNET_MATCHMD_EXHAUSTED = BIT(3), |
| 450 | /* match or drop */ | 451 | /* match or drop */ |
| 451 | LNET_MATCHMD_FINISH = (LNET_MATCHMD_OK | LNET_MATCHMD_DROP), | 452 | LNET_MATCHMD_FINISH = (LNET_MATCHMD_OK | LNET_MATCHMD_DROP), |
| 452 | }; | 453 | }; |
| 453 | 454 | ||
| 454 | /* Options for lnet_portal::ptl_options */ | 455 | /* Options for lnet_portal::ptl_options */ |
| 455 | #define LNET_PTL_LAZY (1 << 0) | 456 | #define LNET_PTL_LAZY BIT(0) |
| 456 | #define LNET_PTL_MATCH_UNIQUE (1 << 1) /* unique match, for RDMA */ | 457 | #define LNET_PTL_MATCH_UNIQUE BIT(1) /* unique match, for RDMA */ |
| 457 | #define LNET_PTL_MATCH_WILDCARD (1 << 2) /* wildcard match, | 458 | #define LNET_PTL_MATCH_WILDCARD BIT(2) /* wildcard match, request portal */ |
| 458 | * request portal | ||
| 459 | */ | ||
| 460 | 459 | ||
| 461 | /* parameter for matching operations (GET, PUT) */ | 460 | /* parameter for matching operations (GET, PUT) */ |
| 462 | struct lnet_match_info { | 461 | struct lnet_match_info { |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -176,12 +177,9 @@ struct ksock_peer * · 172 unmodified lines | |||
| 176 | ksocknal_find_peer_locked(struct lnet_ni *ni, struct lnet_process_id id) | 177 | ksocknal_find_peer_locked(struct lnet_ni *ni, struct lnet_process_id id) |
| 177 | { | 178 | { |
| 178 | struct list_head *peer_list = ksocknal_nid2peerlist(id.nid); | 179 | struct list_head *peer_list = ksocknal_nid2peerlist(id.nid); |
| 179 | struct list_head *tmp; | ||
| 180 | struct ksock_peer *peer; | 180 | struct ksock_peer *peer; |
| 181 | 181 | ||
| 182 | list_for_each(tmp, peer_list) { | 182 | list_for_each_entry(peer, peer_list, ksnp_list) { |
| 183 | peer = list_entry(tmp, struct ksock_peer, ksnp_list); | ||
| 184 | |||
| 185 | LASSERT(!peer->ksnp_closing); | 183 | LASSERT(!peer->ksnp_closing); |
| 186 | 184 | ||
| 187 | if (peer->ksnp_ni != ni) | 185 | if (peer->ksnp_ni != ni) |
| @@ -453,7 +451,6 @@ int · 265 unmodified lines | |||
| 453 | ksocknal_add_peer(struct lnet_ni *ni, struct lnet_process_id id, __u32 ipaddr, | 451 | ksocknal_add_peer(struct lnet_ni *ni, struct lnet_process_id id, __u32 ipaddr, |
| 454 | int port) | 452 | int port) |
| 455 | { | 453 | { |
| 456 | struct list_head *tmp; | ||
| 457 | struct ksock_peer *peer; | 454 | struct ksock_peer *peer; |
| 458 | struct ksock_peer *peer2; | 455 | struct ksock_peer *peer2; |
| 459 | struct ksock_route *route; | 456 | struct ksock_route *route; |
| @@ -491,9 +488,7 @@ ksocknal_add_peer(struct lnet_ni *ni, struct lnet_process_id id, __u32 ipaddr, · 31 unmodified lines | |||
| 491 | } | 488 | } |
| 492 | 489 | ||
| 493 | route2 = NULL; | 490 | route2 = NULL; |
| 494 | list_for_each(tmp, &peer->ksnp_routes) { | 491 | list_for_each_entry(route2, &peer->ksnp_routes, ksnr_list) { |
| 495 | route2 = list_entry(tmp, struct ksock_route, ksnr_list); | ||
| 496 | |||
| 497 | if (route2->ksnr_ipaddr == ipaddr) | 492 | if (route2->ksnr_ipaddr == ipaddr) |
| 498 | break; | 493 | break; |
| 499 | 494 | ||
| @@ -1854,12 +1849,10 @@ ksocknal_query(struct lnet_ni *ni, lnet_nid_t nid, unsigned long *when) · 1354 unmodified lines | |||
| 1854 | 1849 | ||
| 1855 | peer = ksocknal_find_peer_locked(ni, id); | 1850 | peer = ksocknal_find_peer_locked(ni, id); |
| 1856 | if (peer) { | 1851 | if (peer) { |
| 1857 | struct list_head *tmp; | ||
| 1858 | struct ksock_conn *conn; | 1852 | struct ksock_conn *conn; |
| 1859 | int bufnob; | 1853 | int bufnob; |
| 1860 | 1854 | ||
| 1861 | list_for_each(tmp, &peer->ksnp_conns) { | 1855 | list_for_each_entry(conn, &peer->ksnp_conns, ksnc_list) { |
| 1862 | conn = list_entry(tmp, struct ksock_conn, ksnc_list); | ||
| 1863 | bufnob = conn->ksnc_sock->sk->sk_wmem_queued; | 1856 | bufnob = conn->ksnc_sock->sk->sk_wmem_queued; |
| 1864 | 1857 | ||
| 1865 | if (bufnob < conn->ksnc_tx_bufnob) { | 1858 | if (bufnob < conn->ksnc_tx_bufnob) { |
| @@ -2316,7 +2309,7 @@ ksocknal_base_shutdown(void) · 450 unmodified lines | |||
| 2316 | switch (ksocknal_data.ksnd_init) { | 2309 | switch (ksocknal_data.ksnd_init) { |
| 2317 | default: | 2310 | default: |
| 2318 | LASSERT(0); | 2311 | LASSERT(0); |
| 2319 | 2312 | /* fall through */ | |
| 2320 | case SOCKNAL_INIT_ALL: | 2313 | case SOCKNAL_INIT_ALL: |
| 2321 | case SOCKNAL_INIT_DATA: | 2314 | case SOCKNAL_INIT_DATA: |
| 2322 | LASSERT(ksocknal_data.ksnd_peers); | 2315 | LASSERT(ksocknal_data.ksnd_peers); |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. | 3 | * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. | 3 | * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved. | 3 | * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved. |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. | 3 | * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* | 2 | /* |
| 2 | * GPL HEADER START | 3 | * GPL HEADER START |
| 3 | * | 4 | * |
| @@ -1,3 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 1 | /* GPL HEADER START | 2 | /* GPL HEADER START |
| 2 | * | 3 | * |
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