Pull MHI update from Manivannan: MHI Host ======== - Free the "img_info::mhi_buf" in the error path of mhi_alloc_bhie_table() to avoid memory leak. - Add support for Qualcomm X100 5G RAN Accelerator card with relevant channel and event config. - Enable MSI-X if the endpoint supports. * tag 'mhi-for-v6.14' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mani/mhi: bus: mhi: host: pci_generic: Enable MSI-X if the endpoint supports bus: mhi: host: pci_generic: Add support for QDU100 device bus: mhi: host: Free mhi_buf vector inside mhi_alloc_bhie_table()
Unified · Split
| @@ -357,6 +357,7 @@ error_alloc_segment: · 356 unmodified lines | |||
| 357 | for (--i, --mhi_buf; i >= 0; i--, mhi_buf--) | 357 | for (--i, --mhi_buf; i >= 0; i--, mhi_buf--) |
| 358 | dma_free_coherent(mhi_cntrl->cntrl_dev, mhi_buf->len, | 358 | dma_free_coherent(mhi_cntrl->cntrl_dev, mhi_buf->len, |
| 359 | mhi_buf->buf, mhi_buf->dma_addr); | 359 | mhi_buf->buf, mhi_buf->dma_addr); |
| 360 | kfree(img_info->mhi_buf); | ||
| 360 | 361 | ||
| 361 | error_alloc_mhi_buf: | 362 | error_alloc_mhi_buf: |
| 362 | kfree(img_info); | 363 | kfree(img_info); |
| @@ -245,6 +245,58 @@ struct mhi_pci_dev_info { · 244 unmodified lines | |||
| 245 | .channel = ch_num, \ | 245 | .channel = ch_num, \ |
| 246 | } | 246 | } |
| 247 | 247 | ||
| 248 | static const struct mhi_channel_config mhi_qcom_qdu100_channels[] = { | ||
| 249 | MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 2), | ||
| 250 | MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 2), | ||
| 251 | MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 128, 1), | ||
| 252 | MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 128, 1), | ||
| 253 | MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 3), | ||
| 254 | MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 3), | ||
| 255 | MHI_CHANNEL_CONFIG_UL(9, "QDSS", 64, 3), | ||
| 256 | MHI_CHANNEL_CONFIG_UL(14, "NMEA", 32, 4), | ||
| 257 | MHI_CHANNEL_CONFIG_DL(15, "NMEA", 32, 4), | ||
| 258 | MHI_CHANNEL_CONFIG_UL(16, "CSM_CTRL", 32, 4), | ||
| 259 | MHI_CHANNEL_CONFIG_DL(17, "CSM_CTRL", 32, 4), | ||
| 260 | MHI_CHANNEL_CONFIG_UL(40, "MHI_PHC", 32, 4), | ||
| 261 | MHI_CHANNEL_CONFIG_DL(41, "MHI_PHC", 32, 4), | ||
| 262 | MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 256, 5), | ||
| 263 | MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 256, 5), | ||
| 264 | }; | ||
| 265 | |||
| 266 | static struct mhi_event_config mhi_qcom_qdu100_events[] = { | ||
| 267 | /* first ring is control+data ring */ | ||
| 268 | MHI_EVENT_CONFIG_CTRL(0, 64), | ||
| 269 | /* SAHARA dedicated event ring */ | ||
| 270 | MHI_EVENT_CONFIG_SW_DATA(1, 256), | ||
| 271 | /* Software channels dedicated event ring */ | ||
| 272 | MHI_EVENT_CONFIG_SW_DATA(2, 64), | ||
| 273 | MHI_EVENT_CONFIG_SW_DATA(3, 256), | ||
| 274 | MHI_EVENT_CONFIG_SW_DATA(4, 256), | ||
| 275 | /* Software IP channels dedicated event ring */ | ||
| 276 | MHI_EVENT_CONFIG_SW_DATA(5, 512), | ||
| 277 | MHI_EVENT_CONFIG_SW_DATA(6, 512), | ||
| 278 | MHI_EVENT_CONFIG_SW_DATA(7, 512), | ||
| 279 | }; | ||
| 280 | |||
| 281 | static const struct mhi_controller_config mhi_qcom_qdu100_config = { | ||
| 282 | .max_channels = 128, | ||
| 283 | .timeout_ms = 120000, | ||
| 284 | .num_channels = ARRAY_SIZE(mhi_qcom_qdu100_channels), | ||
| 285 | .ch_cfg = mhi_qcom_qdu100_channels, | ||
| 286 | .num_events = ARRAY_SIZE(mhi_qcom_qdu100_events), | ||
| 287 | .event_cfg = mhi_qcom_qdu100_events, | ||
| 288 | }; | ||
| 289 | |||
| 290 | static const struct mhi_pci_dev_info mhi_qcom_qdu100_info = { | ||
| 291 | .name = "qcom-qdu100", | ||
| 292 | .fw = "qcom/qdu100/xbl_s.melf", | ||
| 293 | .edl_trigger = true, | ||
| 294 | .config = &mhi_qcom_qdu100_config, | ||
| 295 | .bar_num = MHI_PCI_DEFAULT_BAR_NUM, | ||
| 296 | .dma_data_width = 32, | ||
| 297 | .sideband_wake = false, | ||
| 298 | }; | ||
| 299 | |||
| 248 | static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { | 300 | static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { |
| 249 | MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), | 301 | MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), |
| 250 | MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), | 302 | MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), |
| @@ -742,6 +794,9 @@ static const struct pci_device_id mhi_pci_id_table[] = { · 491 unmodified lines | |||
| 742 | .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info }, | 794 | .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info }, |
| 743 | { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0309), | 795 | { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0309), |
| 744 | .driver_data = (kernel_ulong_t) &mhi_qcom_sdx75_info }, | 796 | .driver_data = (kernel_ulong_t) &mhi_qcom_sdx75_info }, |
| 797 | /* QDU100, x100-DU */ | ||
| 798 | { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0601), | ||
| 799 | .driver_data = (kernel_ulong_t) &mhi_qcom_qdu100_info }, | ||
| 745 | { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1001), /* EM120R-GL (sdx24) */ | 800 | { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1001), /* EM120R-GL (sdx24) */ |
| 746 | .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, | 801 | .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, |
| 747 | { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */ | 802 | { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */ |
| @@ -949,7 +1004,7 @@ static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl, · 201 unmodified lines | |||
| 949 | */ | 1004 | */ |
| 950 | mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events; | 1005 | mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events; |
| 951 | 1006 | ||
| 952 | nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSI); | 1007 | nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSIX | PCI_IRQ_MSI); |
| 953 | if (nr_vectors < 0) { | 1008 | if (nr_vectors < 0) { |
| 954 | dev_err(&pdev->dev, "Error allocating MSI vectors %d\n", | 1009 | dev_err(&pdev->dev, "Error allocating MSI vectors %d\n", |
| 955 | nr_vectors); | 1010 | nr_vectors); |