History

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd: "We have a couple patches in the framework core this time around but they're mostly minor cleanups and some debugfs stuff. The real work that's in here is the typical pile of clk driver updates and new SoC support. Per usual (or maybe just recent trends), Qualcomm gains a handful of SoC drivers additions and has the largest diffstat. After that there are quite a few updates to the Allwinner (sunxi) drivers to support modular drivers and Renesas is heavily updated to add more support for various clks. Overall it looks pretty normal. New Drivers: - Add MDMA and BDMA clks to Ingenic JZ4760 and JZ4770 - MediaTek mt7986 SoC basic support - Clock and reset driver for Toshiba Visconti SoCs - Initial clock driver for the Exynos7885 SoC (Samsung Galaxy A8) - Allwinner D1 clks - Lan966x Generic Clock Controller driver and associated DT bindings - Qualcomm SDX65, SM8450, and MSM8976 GCC clks - Qualcomm SDX65 and SM8450 RPMh clks Updates: - Set suppress_bind_attrs to true for i.MX8ULP driver - Switch from do_div to div64_ul for throughout all i.MX drivers - Fix imx8mn_clko1_sels for i.MX8MN - Remove unused IPG_AUDIO_ROOT from i.MX8MP - Switch parent for audio_root_clk to audio ahb in i.MX8MP driver - Removal of all remaining uses of __clk_lookup() in drivers/clk/samsung - Refactoring of the CPU clocks registration to use common interface - An update of the Exynos850 driver (support for more clock domains) required by the E850-96 development board - Prep for runtime PM and generic power domains on Tegra - Support modular Allwinner clk drivers via platform bus - Lan966x clock driver extended to support clock gating - Add serial (SCI1), watchdog (WDT), timer (OSTM), SPI (RSPI), and thermal (TSU) clocks and resets on Renesas RZ/G2L - Rework SDHI clock handling in the Renesas R-Car Gen3 and RZ/G2 clock drivers, and in the Renesas SDHI driver - Make the Cortex-A55 (I) clock on Renesas RZ/G2L programmable - Document support for the new Renesas R-Car S4-8 (R8A779F0) SoC - Add support for the new Renesas R-Car S4-8 (R8A779F0) SoC - Add GPU clock and resets on Renesas RZ/G2L - Add clk-provider.h to various Qualcomm clk drivers - devm version of clk_hw_register_gate() - kerneldoc fixes in a couple drivers" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (131 commits) clk: visconti: Remove pointless NULL check in visconti_pll_add_lookup() clk: mediatek: add mt7986 clock support clk: mediatek: add mt7986 clock IDs dt-bindings: clock: mediatek: document clk bindings for mediatek mt7986 SoC clk: mediatek: clk-gate: Use regmap_{set/clear}_bits helpers clk: mediatek: clk-gate: Shrink by adding clockgating bit check helper clk: x86: Fix clk_gate_flags for RV_CLK_GATE clk: x86: Use dynamic con_id string during clk registration ACPI: APD: Add a fmw property clk-name drivers: acpi: acpi_apd: Remove unused device property "is-rv" x86: clk: clk-fch: Add support for newer family of AMD's SOC clk: ingenic: Add MDMA and BDMA clocks dt-bindings: clk/ingenic: Add MDMA and BDMA clocks clk: bm1880: remove kfrees on static allocations clk: Drop unused COMMON_CLK_STM32MP157_SCMI config clk: st: clkgen-mux: search reg within node or parent clk: st: clkgen-fsyn: search reg within node or parent clk: Enable/Disable runtime PM for clk_summary MAINTAINERS: Add entries for Toshiba Visconti PLL and clock controller clk: visconti: Add support common clock driver and reset driver ...

Linus Torvalds committed 4 years ago

Commit 455e73a2 parents d9b5941 4afd2a9198 files · +18551 −1240Browse files

Unified · Split

198 files
  1. Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +1 −0
  2. Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt +1 −0
  3. Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +1 −0
  4. Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt +2 −0
  5. Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +1 −0
  6. Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml +4 −0
  7. Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml +60 −0
  8. Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml +97 −0
  9. Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +2 −0
  10. Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml +1 −0
  11. Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml +166 −0
  12. Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml +38 −0
  13. Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml +57 −0
  14. Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml +52 −0
  15. MAINTAINERS +12 −0
  16. drivers/acpi/acpi_apd.c +9 −2
  17. drivers/clk/Kconfig +16 −10
  18. drivers/clk/Makefile +4 −1
  19. drivers/clk/clk-bm1880.c +2 −18
  20. drivers/clk/clk-gate.c +35 −0
  21. drivers/clk/clk-gemini.c +1 −1
  22. drivers/clk/clk-lan966x.c +293 −0
  23. drivers/clk/clk-stm32f4.c +0 −4
  24. drivers/clk/clk-stm32mp1.c +0 −2
  25. drivers/clk/clk-tps68470.c +261 −0
  26. drivers/clk/clk.c +69 −11
  27. drivers/clk/imx/clk-imx8mn.c +3 −3
  28. drivers/clk/imx/clk-imx8mp.c +1 −1
  29. drivers/clk/imx/clk-imx8ulp.c +1 −0
  30. drivers/clk/imx/clk-pllv1.c +8 −9
  31. drivers/clk/imx/clk-pllv3.c +3 −3
  32. drivers/clk/ingenic/jz4760-cgu.c +10 −0
  33. drivers/clk/ingenic/jz4770-cgu.c +5 −0
  34. drivers/clk/mediatek/Kconfig +17 −0
  35. drivers/clk/mediatek/Makefile +4 −0
  36. drivers/clk/mediatek/clk-gate.c +9 −15
  37. drivers/clk/mediatek/clk-mt7986-apmixed.c +100 −0
  38. drivers/clk/mediatek/clk-mt7986-eth.c +132 −0
  39. drivers/clk/mediatek/clk-mt7986-infracfg.c +224 −0
  40. drivers/clk/mediatek/clk-mt7986-topckgen.c +342 −0
  41. drivers/clk/meson/gxbb.c +41 −3
  42. drivers/clk/qcom/Kconfig +24 −0
  43. drivers/clk/qcom/Makefile +3 −0
  44. drivers/clk/qcom/clk-alpha-pll.c +160 −6
  45. drivers/clk/qcom/clk-alpha-pll.h +3 −0
  46. drivers/clk/qcom/clk-rpmh.c +52 −0
  47. drivers/clk/qcom/clk-smd-rpm.c +4 −27
  48. drivers/clk/qcom/gcc-msm8976.c +4155 −0
  49. drivers/clk/qcom/gcc-msm8994.c +1 −0
  50. drivers/clk/qcom/gcc-sc7280.c +1 −1
  51. drivers/clk/qcom/gcc-sdx65.c +1611 −0
  52. drivers/clk/qcom/gcc-sm6350.c +1 −0
  53. drivers/clk/qcom/gcc-sm8350.c +1 −0
  54. drivers/clk/qcom/gcc-sm8450.c +3304 −0
  55. drivers/clk/qcom/lpasscc-sc7280.c +1 −0
  56. drivers/clk/qcom/lpasscc-sdm845.c +1 −0
  57. drivers/clk/qcom/mmcc-apq8084.c +1 −0
  58. drivers/clk/qcom/q6sstop-qcs404.c +1 −0
  59. drivers/clk/qcom/turingcc-qcs404.c +1 −0
  60. drivers/clk/renesas/Kconfig +11 −2
  61. drivers/clk/renesas/Makefile +2 −0
  62. drivers/clk/renesas/r8a774a1-cpg-mssr.c +8 −4
  63. drivers/clk/renesas/r8a774b1-cpg-mssr.c +8 −4
  64. drivers/clk/renesas/r8a774c0-cpg-mssr.c +6 −3
  65. drivers/clk/renesas/r8a774e1-cpg-mssr.c +8 −4
  66. drivers/clk/renesas/r8a7795-cpg-mssr.c +8 −4
  67. drivers/clk/renesas/r8a7796-cpg-mssr.c +8 −4
  68. drivers/clk/renesas/r8a77965-cpg-mssr.c +8 −4
  69. drivers/clk/renesas/r8a77980-cpg-mssr.c +2 −1
  70. drivers/clk/renesas/r8a77990-cpg-mssr.c +6 −3
  71. drivers/clk/renesas/r8a77995-cpg-mssr.c +2 −1
  72. drivers/clk/renesas/r8a779a0-cpg-mssr.c +26 −317
  73. drivers/clk/renesas/r8a779f0-cpg-mssr.c +183 −0
  74. drivers/clk/renesas/r9a07g044-cpg.c +72 −9
  75. drivers/clk/renesas/rcar-cpg-lib.c +27 −184
  76. drivers/clk/renesas/rcar-cpg-lib.h +5 −2
  77. drivers/clk/renesas/rcar-gen3-cpg.c +9 −15
  78. drivers/clk/renesas/rcar-gen3-cpg.h +4 −0
  79. drivers/clk/renesas/rcar-gen4-cpg.c +305 −0
  80. drivers/clk/renesas/rcar-gen4-cpg.h +76 −0
  81. drivers/clk/renesas/renesas-cpg-mssr.c +43 −17
  82. drivers/clk/renesas/renesas-cpg-mssr.h +2 −1
  83. drivers/clk/renesas/rzg2l-cpg.c +15 −3
  84. drivers/clk/renesas/rzg2l-cpg.h +9 −0
  85. drivers/clk/samsung/Makefile +2 −0
  86. drivers/clk/samsung/clk-cpu.c +1 −1
  87. drivers/clk/samsung/clk-cpu.h +0 −7
  88. drivers/clk/samsung/clk-exynos-arm64.c +94 −0
  89. drivers/clk/samsung/clk-exynos-arm64.h +20 −0
  90. drivers/clk/samsung/clk-exynos3250.c +27 −27
  91. drivers/clk/samsung/clk-exynos4.c +24 −17
  92. drivers/clk/samsung/clk-exynos5250.c +12 −9
  93. drivers/clk/samsung/clk-exynos5420.c +19 −10
  94. drivers/clk/samsung/clk-exynos7885.c +597 −0
  95. drivers/clk/samsung/clk-exynos850.c +295 −71
  96. drivers/clk/samsung/clk-pll.c +1 −0
  97. drivers/clk/samsung/clk-pll.h +1 −0
  98. drivers/clk/samsung/clk-s3c2410.c +4 −2
  99. drivers/clk/samsung/clk-s3c64xx.c +6 −2
  100. drivers/clk/samsung/clk-s5pv210.c +6 −2
  101. drivers/clk/samsung/clk.c +0 −14
  102. drivers/clk/samsung/clk.h +17 −19
  103. drivers/clk/socfpga/clk-agilex.c +1 −3
  104. drivers/clk/socfpga/clk-gate.c +2 −2
  105. drivers/clk/socfpga/clk-pll-s10.c +1 −1
  106. drivers/clk/socfpga/clk-s10.c +1 −3
  107. drivers/clk/st/clkgen-fsyn.c +11 −2
  108. drivers/clk/st/clkgen-mux.c +9 −2
  109. drivers/clk/sunxi-ng/Kconfig +30 −19
  110. drivers/clk/sunxi-ng/Makefile +65 −36
  111. drivers/clk/sunxi-ng/ccu-sun20i-d1-r.c +140 −0
  112. drivers/clk/sunxi-ng/ccu-sun20i-d1-r.h +17 −0
  113. drivers/clk/sunxi-ng/ccu-sun20i-d1.c +1390 −0
  114. drivers/clk/sunxi-ng/ccu-sun20i-d1.h +15 −0
  115. drivers/clk/sunxi-ng/ccu-sun4i-a10.c +36 −22
  116. drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c +3 −1
  117. drivers/clk/sunxi-ng/ccu-sun50i-a100.c +3 −1
  118. drivers/clk/sunxi-ng/ccu-sun50i-a64.c +5 −2
  119. drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c +35 −21
  120. drivers/clk/sunxi-ng/ccu-sun50i-h6.c +5 −2
  121. drivers/clk/sunxi-ng/ccu-sun50i-h616.c +23 −10
  122. drivers/clk/sunxi-ng/ccu-sun6i-a31.c +30 −10
  123. drivers/clk/sunxi-ng/ccu-sun8i-a23.c +25 −10
  124. drivers/clk/sunxi-ng/ccu-sun8i-a33.c +30 −10
  125. drivers/clk/sunxi-ng/ccu-sun8i-a83t.c +5 −2
  126. drivers/clk/sunxi-ng/ccu-sun8i-de2.c +6 −3
  127. drivers/clk/sunxi-ng/ccu-sun8i-h3.c +41 −21
  128. drivers/clk/sunxi-ng/ccu-sun8i-r.c +38 −27
  129. drivers/clk/sunxi-ng/ccu-sun8i-r40.c +5 −1
  130. drivers/clk/sunxi-ng/ccu-sun8i-v3s.c +35 −22
  131. drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c +5 −2
  132. drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c +5 −2
  133. drivers/clk/sunxi-ng/ccu-sun9i-a80.c +5 −2
  134. drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c +30 −10
  135. drivers/clk/sunxi-ng/ccu_common.c +6 −0
  136. drivers/clk/sunxi-ng/ccu_div.c +1 −0
  137. drivers/clk/sunxi-ng/ccu_div.h +78 −0
  138. drivers/clk/sunxi-ng/ccu_frac.c +6 −0
  139. drivers/clk/sunxi-ng/ccu_gate.c +4 −0
  140. drivers/clk/sunxi-ng/ccu_gate.h +31 −1
  141. drivers/clk/sunxi-ng/ccu_mp.c +2 −0
  142. drivers/clk/sunxi-ng/ccu_mp.h +49 −0
  143. drivers/clk/sunxi-ng/ccu_mult.c +1 −0
  144. drivers/clk/sunxi-ng/ccu_mux.c +6 −0
  145. drivers/clk/sunxi-ng/ccu_mux.h +33 −0
  146. drivers/clk/sunxi-ng/ccu_nk.c +1 −0
  147. drivers/clk/sunxi-ng/ccu_nkm.c +1 −0
  148. drivers/clk/sunxi-ng/ccu_nkmp.c +1 −0
  149. drivers/clk/sunxi-ng/ccu_nm.c +1 −0
  150. drivers/clk/sunxi-ng/ccu_phase.c +1 −0
  151. drivers/clk/sunxi-ng/ccu_reset.c +1 −0
  152. drivers/clk/sunxi-ng/ccu_sdm.c +6 −0
  153. drivers/clk/tegra/Makefile +1 −0
  154. drivers/clk/tegra/clk-device.c +199 −0
  155. drivers/clk/tegra/clk-pll.c +1 −1
  156. drivers/clk/tegra/clk-super.c +1 −1
  157. drivers/clk/tegra/clk-tegra114.c +1 −1
  158. drivers/clk/tegra/clk-tegra20.c +59 −18
  159. drivers/clk/tegra/clk-tegra30.c +85 −31
  160. drivers/clk/tegra/clk.c +72 −3
  161. drivers/clk/tegra/clk.h +2 −0
  162. drivers/clk/ti/adpll.c +1 −1
  163. drivers/clk/visconti/Kconfig +9 −0
  164. drivers/clk/visconti/Makefile +5 −0
  165. drivers/clk/visconti/clkc-tmpv770x.c +291 −0
  166. drivers/clk/visconti/clkc.c +206 −0
  167. drivers/clk/visconti/clkc.h +76 −0
  168. drivers/clk/visconti/pll-tmpv770x.c +85 −0
  169. drivers/clk/visconti/pll.c +340 −0
  170. drivers/clk/visconti/pll.h +62 −0
  171. drivers/clk/visconti/reset.c +107 −0
  172. drivers/clk/visconti/reset.h +36 −0
  173. drivers/clk/x86/clk-fch.c +34 −14
  174. drivers/clk/zynq/pll.c +6 −6
  175. drivers/mmc/host/Kconfig +1 −0
  176. drivers/mmc/host/renesas_sdhi.h +4 −0
  177. drivers/mmc/host/renesas_sdhi_core.c +32 −13
  178. drivers/mmc/host/renesas_sdhi_internal_dmac.c +21 −0
  179. include/dt-bindings/clock/exynos4.h +3 −1
  180. include/dt-bindings/clock/exynos5250.h +3 −1
  181. include/dt-bindings/clock/exynos7885.h +115 −0
  182. include/dt-bindings/clock/exynos850.h +52 −2
  183. include/dt-bindings/clock/imx8mp-clock.h +0 −1
  184. include/dt-bindings/clock/ingenic,jz4760-cgu.h +2 −0
  185. include/dt-bindings/clock/ingenic,jz4770-cgu.h +1 −0
  186. include/dt-bindings/clock/microchip,lan966x.h +34 −0
  187. include/dt-bindings/clock/mt7986-clk.h +169 −0
  188. include/dt-bindings/clock/qcom,gcc-msm8976.h +240 −0
  189. include/dt-bindings/clock/sun20i-d1-ccu.h +156 −0
  190. include/dt-bindings/clock/sun20i-d1-r-ccu.h +19 −0
  191. include/dt-bindings/clock/toshiba,tmpv770x.h +181 −0
  192. include/dt-bindings/reset/sun20i-d1-ccu.h +77 −0
  193. include/dt-bindings/reset/sun20i-d1-r-ccu.h +16 −0
  194. include/dt-bindings/reset/toshiba,tmpv770x.h +41 −0
  195. include/linux/clk-provider.h +23 −0
  196. include/linux/clk/sunxi-ng.h +0 −15
  197. include/linux/mfd/tps68470.h +11 −0
  198. include/linux/platform_data/clk-fch.h +1 −1
Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt+1−0
@@ -14,6 +14,7 @@ Required Properties: · 13 unmodified lines
1414 - "mediatek,mt7622-apmixedsys"
1515 - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
1616 - "mediatek,mt7629-apmixedsys"
17+ - "mediatek,mt7986-apmixedsys"
1718 - "mediatek,mt8135-apmixedsys"
1819 - "mediatek,mt8167-apmixedsys", "syscon"
1920 - "mediatek,mt8173-apmixedsys"
Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt+1−0
@@ -10,6 +10,7 @@ Required Properties: · 9 unmodified lines
1010 - "mediatek,mt7622-ethsys", "syscon"
1111 - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
1212 - "mediatek,mt7629-ethsys", "syscon"
13+ - "mediatek,mt7986-ethsys", "syscon"
1314 - #clock-cells: Must be 1
1415 - #reset-cells: Must be 1
1516
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt+1−0
@@ -15,6 +15,7 @@ Required Properties: · 14 unmodified lines
1515 - "mediatek,mt7622-infracfg", "syscon"
1616 - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
1717 - "mediatek,mt7629-infracfg", "syscon"
18+ - "mediatek,mt7986-infracfg", "syscon"
1819 - "mediatek,mt8135-infracfg", "syscon"
1920 - "mediatek,mt8167-infracfg", "syscon"
2021 - "mediatek,mt8173-infracfg", "syscon"
Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt+2−0
@@ -8,6 +8,8 @@ Required Properties: · 7 unmodified lines
88 - compatible: Should be:
99 - "mediatek,mt7622-sgmiisys", "syscon"
1010 - "mediatek,mt7629-sgmiisys", "syscon"
11+ - "mediatek,mt7986-sgmiisys_0", "syscon"
12+ - "mediatek,mt7986-sgmiisys_1", "syscon"
1113 - #clock-cells: Must be 1
1214
1315 The SGMIISYS controller uses the common clk binding from
Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt+1−0
@@ -14,6 +14,7 @@ Required Properties: · 13 unmodified lines
1414 - "mediatek,mt7622-topckgen"
1515 - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
1616 - "mediatek,mt7629-topckgen"
17+ - "mediatek,mt7986-topckgen", "syscon"
1718 - "mediatek,mt8135-topckgen"
1819 - "mediatek,mt8167-topckgen", "syscon"
1920 - "mediatek,mt8173-topckgen"
Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml+4−0
@@ -34,6 +34,8 @@ properties: · 33 unmodified lines
3434 - allwinner,sun8i-v3-ccu
3535 - allwinner,sun8i-v3s-ccu
3636 - allwinner,sun9i-a80-ccu
37+ - allwinner,sun20i-d1-ccu
38+ - allwinner,sun20i-d1-r-ccu
3739 - allwinner,sun50i-a64-ccu
3840 - allwinner,sun50i-a64-r-ccu
3941 - allwinner,sun50i-a100-ccu
@@ -79,6 +81,7 @@ if: · 39 unmodified lines
7981 enum:
8082 - allwinner,sun8i-a83t-r-ccu
8183 - allwinner,sun8i-h3-r-ccu
84+ - allwinner,sun20i-d1-r-ccu
8285 - allwinner,sun50i-a64-r-ccu
8386 - allwinner,sun50i-a100-r-ccu
8487 - allwinner,sun50i-h6-r-ccu
@@ -99,6 +102,7 @@ else: · 14 unmodified lines
99102 properties:
100103 compatible:
101104 enum:
105+ - allwinner,sun20i-d1-ccu
102106 - allwinner,sun50i-a100-ccu
103107 - allwinner,sun50i-h6-ccu
104108 - allwinner,sun50i-h616-ccu
Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml+60−0
@@ -0,0 +1,60 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Microchip LAN966X Generic Clock Controller
8+
9+maintainers:
10+ - Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
11+
12+description: |
13+ The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
14+ ddr_clk and sys_clk. This clock controller generates and supplies
15+ clock to various peripherals within the SoC.
16+
17+properties:
18+ compatible:
19+ const: microchip,lan966x-gck
20+
21+ reg:
22+ minItems: 1
23+ items:
24+ - description: Generic clock registers
25+ - description: Optional gate clock registers
26+
27+ clocks:
28+ items:
29+ - description: CPU clock source
30+ - description: DDR clock source
31+ - description: System clock source
32+
33+ clock-names:
34+ items:
35+ - const: cpu
36+ - const: ddr
37+ - const: sys
38+
39+ '#clock-cells':
40+ const: 1
41+
42+required:
43+ - compatible
44+ - reg
45+ - clocks
46+ - clock-names
47+ - '#clock-cells'
48+
49+additionalProperties: false
50+
51+examples:
52+ - |
53+ clks: clock-controller@e00c00a8 {
54+ compatible = "microchip,lan966x-gck";
55+ #clock-cells = <1>;
56+ clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
57+ clock-names = "cpu", "ddr", "sys";
58+ reg = <0xe00c00a8 0x38>;
59+ };
60+...
Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml+97−0
@@ -0,0 +1,97 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8976.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm Global Clock & Reset Controller Binding for MSM8976
8+
9+maintainers:
10+ - Stephen Boyd <sboyd@kernel.org>
11+ - Taniya Das <tdas@codeaurora.org>
12+
13+description: |
14+ Qualcomm global clock control module which supports the clocks, resets and
15+ power domains on MSM8976.
16+
17+ See also:
18+ - dt-bindings/clock/qcom,gcc-msm8976.h
19+
20+properties:
21+ compatible:
22+ enum:
23+ - qcom,gcc-msm8976
24+ - qcom,gcc-msm8976-v1.1
25+
26+ clocks:
27+ items:
28+ - description: XO source
29+ - description: Always-on XO source
30+ - description: Pixel clock from DSI PHY0
31+ - description: Byte clock from DSI PHY0
32+ - description: Pixel clock from DSI PHY1
33+ - description: Byte clock from DSI PHY1
34+
35+ clock-names:
36+ items:
37+ - const: xo
38+ - const: xo_a
39+ - const: dsi0pll
40+ - const: dsi0pllbyte
41+ - const: dsi1pll
42+ - const: dsi1pllbyte
43+
44+ vdd_gfx-supply:
45+ description:
46+ Phandle to voltage regulator providing power to the GX domain.
47+
48+ '#clock-cells':
49+ const: 1
50+
51+ '#reset-cells':
52+ const: 1
53+
54+ '#power-domain-cells':
55+ const: 1
56+
57+ reg:
58+ maxItems: 1
59+
60+required:
61+ - compatible
62+ - reg
63+ - clocks
64+ - clock-names
65+ - vdd_gfx-supply
66+ - '#clock-cells'
67+ - '#reset-cells'
68+ - '#power-domain-cells'
69+
70+additionalProperties: false
71+
72+examples:
73+ - |
74+ clock-controller@1800000 {
75+ compatible = "qcom,gcc-msm8976";
76+ #clock-cells = <1>;
77+ #reset-cells = <1>;
78+ #power-domain-cells = <1>;
79+ reg = <0x1800000 0x80000>;
80+
81+ clocks = <&xo_board>,
82+ <&xo_board>,
83+ <&dsi0_phy 1>,
84+ <&dsi0_phy 0>,
85+ <&dsi1_phy 1>,
86+ <&dsi1_phy 0>;
87+
88+ clock-names = "xo",
89+ "xo_a",
90+ "dsi0pll",
91+ "dsi0pllbyte",
92+ "dsi1pll",
93+ "dsi1pllbyte";
94+
95+ vdd_gfx-supply = <&pm8004_s5>;
96+ };
97+...
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml+2−0
@@ -22,10 +22,12 @@ properties: · 21 unmodified lines
2222 - qcom,sc8180x-rpmh-clk
2323 - qcom,sdm845-rpmh-clk
2424 - qcom,sdx55-rpmh-clk
25+ - qcom,sdx65-rpmh-clk
2526 - qcom,sm6350-rpmh-clk
2627 - qcom,sm8150-rpmh-clk
2728 - qcom,sm8250-rpmh-clk
2829 - qcom,sm8350-rpmh-clk
30+ - qcom,sm8450-rpmh-clk
2931
3032 clocks:
3133 maxItems: 1
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml+1−0
@@ -48,6 +48,7 @@ properties: · 47 unmodified lines
4848 - renesas,r8a77990-cpg-mssr # R-Car E3
4949 - renesas,r8a77995-cpg-mssr # R-Car D3
5050 - renesas,r8a779a0-cpg-mssr # R-Car V3U
51+ - renesas,r8a779f0-cpg-mssr # R-Car S4-8
5152
5253 reg:
5354 maxItems: 1
Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml+166−0
@@ -0,0 +1,166 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Samsung Exynos7885 SoC clock controller
8+
9+maintainers:
10+ - Dávid Virág <virag.david003@gmail.com>
11+ - Chanwoo Choi <cw00.choi@samsung.com>
12+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
13+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
14+ - Tomasz Figa <tomasz.figa@gmail.com>
15+
16+description: |
17+ Exynos7885 clock controller is comprised of several CMU units, generating
18+ clocks for different domains. Those CMU units are modeled as separate device
19+ tree nodes, and might depend on each other. The root clock in that root tree
20+ is an external clock: OSCCLK (26 MHz). This external clock must be defined
21+ as a fixed-rate clock in dts.
22+
23+ CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
24+ dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
25+
26+ Each clock is assigned an identifier and client nodes can use this identifier
27+ to specify the clock which they consume. All clocks available for usage
28+ in clock consumer nodes are defined as preprocessor macros in
29+ 'dt-bindings/clock/exynos7885.h' header.
30+
31+properties:
32+ compatible:
33+ enum:
34+ - samsung,exynos7885-cmu-top
35+ - samsung,exynos7885-cmu-core
36+ - samsung,exynos7885-cmu-peri
37+
38+ clocks:
39+ minItems: 1
40+ maxItems: 10
41+
42+ clock-names:
43+ minItems: 1
44+ maxItems: 10
45+
46+ "#clock-cells":
47+ const: 1
48+
49+ reg:
50+ maxItems: 1
51+
52+allOf:
53+ - if:
54+ properties:
55+ compatible:
56+ contains:
57+ const: samsung,exynos7885-cmu-top
58+
59+ then:
60+ properties:
61+ clocks:
62+ items:
63+ - description: External reference clock (26 MHz)
64+
65+ clock-names:
66+ items:
67+ - const: oscclk
68+
69+ - if:
70+ properties:
71+ compatible:
72+ contains:
73+ const: samsung,exynos7885-cmu-core
74+
75+ then:
76+ properties:
77+ clocks:
78+ items:
79+ - description: External reference clock (26 MHz)
80+ - description: CMU_CORE bus clock (from CMU_TOP)
81+ - description: CCI clock (from CMU_TOP)
82+ - description: G3D clock (from CMU_TOP)
83+
84+ clock-names:
85+ items:
86+ - const: oscclk
87+ - const: dout_core_bus
88+ - const: dout_core_cci
89+ - const: dout_core_g3d
90+
91+ - if:
92+ properties:
93+ compatible:
94+ contains:
95+ const: samsung,exynos7885-cmu-peri
96+
97+ then:
98+ properties:
99+ clocks:
100+ items:
101+ - description: External reference clock (26 MHz)
102+ - description: CMU_PERI bus clock (from CMU_TOP)
103+ - description: SPI0 clock (from CMU_TOP)
104+ - description: SPI1 clock (from CMU_TOP)
105+ - description: UART0 clock (from CMU_TOP)
106+ - description: UART1 clock (from CMU_TOP)
107+ - description: UART2 clock (from CMU_TOP)
108+ - description: USI0 clock (from CMU_TOP)
109+ - description: USI1 clock (from CMU_TOP)
110+ - description: USI2 clock (from CMU_TOP)
111+
112+ clock-names:
113+ items:
114+ - const: oscclk
115+ - const: dout_peri_bus
116+ - const: dout_peri_spi0
117+ - const: dout_peri_spi1
118+ - const: dout_peri_uart0
119+ - const: dout_peri_uart1
120+ - const: dout_peri_uart2
121+ - const: dout_peri_usi0
122+ - const: dout_peri_usi1
123+ - const: dout_peri_usi2
124+
125+required:
126+ - compatible
127+ - "#clock-cells"
128+ - clocks
129+ - clock-names
130+ - reg
131+
132+additionalProperties: false
133+
134+examples:
135+ # Clock controller node for CMU_PERI
136+ - |
137+ #include <dt-bindings/clock/exynos7885.h>
138+
139+ cmu_peri: clock-controller@10010000 {
140+ compatible = "samsung,exynos7885-cmu-peri";
141+ reg = <0x10010000 0x8000>;
142+ #clock-cells = <1>;
143+
144+ clocks = <&oscclk>,
145+ <&cmu_top CLK_DOUT_PERI_BUS>,
146+ <&cmu_top CLK_DOUT_PERI_SPI0>,
147+ <&cmu_top CLK_DOUT_PERI_SPI1>,
148+ <&cmu_top CLK_DOUT_PERI_UART0>,
149+ <&cmu_top CLK_DOUT_PERI_UART1>,
150+ <&cmu_top CLK_DOUT_PERI_UART2>,
151+ <&cmu_top CLK_DOUT_PERI_USI0>,
152+ <&cmu_top CLK_DOUT_PERI_USI1>,
153+ <&cmu_top CLK_DOUT_PERI_USI2>;
154+ clock-names = "oscclk",
155+ "dout_peri_bus",
156+ "dout_peri_spi0",
157+ "dout_peri_spi1",
158+ "dout_peri_uart0",
159+ "dout_peri_uart1",
160+ "dout_peri_uart2",
161+ "dout_peri_usi0",
162+ "dout_peri_usi1",
163+ "dout_peri_usi2";
164+ };
165+
166+...
Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml+38−0
@@ -32,6 +32,8 @@ properties: · 31 unmodified lines
3232 compatible:
3333 enum:
3434 - samsung,exynos850-cmu-top
35+ - samsung,exynos850-cmu-apm
36+ - samsung,exynos850-cmu-cmgp
3537 - samsung,exynos850-cmu-core
3638 - samsung,exynos850-cmu-dpu
3739 - samsung,exynos850-cmu-hsi
@@ -68,6 +70,42 @@ allOf: · 30 unmodified lines
6870 items:
6971 - const: oscclk
7072
73+ - if:
74+ properties:
75+ compatible:
76+ contains:
77+ const: samsung,exynos850-cmu-apm
78+
79+ then:
80+ properties:
81+ clocks:
82+ items:
83+ - description: External reference clock (26 MHz)
84+ - description: CMU_APM bus clock (from CMU_TOP)
85+
86+ clock-names:
87+ items:
88+ - const: oscclk
89+ - const: dout_clkcmu_apm_bus
90+
91+ - if:
92+ properties:
93+ compatible:
94+ contains:
95+ const: samsung,exynos850-cmu-cmgp
96+
97+ then:
98+ properties:
99+ clocks:
100+ items:
101+ - description: External reference clock (26 MHz)
102+ - description: CMU_CMGP bus clock (from CMU_APM)
103+
104+ clock-names:
105+ items:
106+ - const: oscclk
107+ - const: gout_clkcmu_cmgp_bus
108+
71109 - if:
72110 properties:
73111 compatible:
Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml+57−0
@@ -0,0 +1,57 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pipllct.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Toshiba Visconti5 TMPV770X PLL Controller Device Tree Bindings
8+
9+maintainers:
10+ - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
11+
12+description:
13+ Toshia Visconti5 PLL controller which supports the PLLs on TMPV770X.
14+
15+properties:
16+ compatible:
17+ const: toshiba,tmpv7708-pipllct
18+
19+ reg:
20+ maxItems: 1
21+
22+ '#clock-cells':
23+ const: 1
24+
25+ clocks:
26+ description: External reference clock (OSC2)
27+ maxItems: 1
28+
29+required:
30+ - compatible
31+ - reg
32+ - "#clock-cells"
33+ - clocks
34+
35+additionalProperties: false
36+
37+examples:
38+ - |
39+
40+ osc2_clk: osc2-clk {
41+ compatible = "fixed-clock";
42+ clock-frequency = <20000000>;
43+ #clock-cells = <0>;
44+ };
45+
46+ soc {
47+ #address-cells = <2>;
48+ #size-cells = <2>;
49+
50+ pipllct: clock-controller@24220000 {
51+ compatible = "toshiba,tmpv7708-pipllct";
52+ reg = <0 0x24220000 0 0x820>;
53+ #clock-cells = <1>;
54+ clocks = <&osc2_clk>;
55+ };
56+ };
57+...
Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml+52−0
@@ -0,0 +1,52 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pismu.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Toshiba Visconti5 TMPV770x SMU controller Device Tree Bindings
8+
9+maintainers:
10+ - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
11+
12+description:
13+ Toshia Visconti5 SMU (System Management Unit) which supports the clock
14+ and resets on TMPV770x.
15+
16+properties:
17+ compatible:
18+ items:
19+ - const: toshiba,tmpv7708-pismu
20+ - const: syscon
21+
22+ reg:
23+ maxItems: 1
24+
25+ '#clock-cells':
26+ const: 1
27+
28+ '#reset-cells':
29+ const: 1
30+
31+required:
32+ - compatible
33+ - reg
34+ - "#clock-cells"
35+ - "#reset-cells"
36+
37+additionalProperties: false
38+
39+examples:
40+ - |
41+ soc {
42+ #address-cells = <2>;
43+ #size-cells = <2>;
44+
45+ pismu: syscon@24200000 {
46+ compatible = "toshiba,tmpv7708-pismu", "syscon";
47+ reg = <0 0x24200000 0 0x2140>;
48+ #clock-cells = <1>;
49+ #reset-cells = <1>;
50+ };
51+ };
52+...
MAINTAINERS+12−0
@@ -2807,12 +2807,15 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) · 2806 unmodified lines
28072807 S: Supported
28082808 T: git git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti.git
28092809 F: Documentation/devicetree/bindings/arm/toshiba.yaml
2810+F: Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml
2811+F: Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml
28102812 F: Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml
28112813 F: Documentation/devicetree/bindings/gpio/toshiba,gpio-visconti.yaml
28122814 F: Documentation/devicetree/bindings/pci/toshiba,visconti-pcie.yaml
28132815 F: Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml
28142816 F: Documentation/devicetree/bindings/watchdog/toshiba,visconti-wdt.yaml
28152817 F: arch/arm64/boot/dts/toshiba/
2818+F: drivers/clk/visconti/
28162819 F: drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
28172820 F: drivers/gpio/gpio-visconti.c
28182821 F: drivers/pci/controller/dwc/pcie-visconti.c
@@ -15868,6 +15871,15 @@ F: Documentation/admin-guide/media/qcom_camss.rst · 13049 unmodified lines
1586815871 F: Documentation/devicetree/bindings/media/*camss*
1586915872 F: drivers/media/platform/qcom/camss/
1587015873
15874+QUALCOMM CLOCK DRIVERS
15875+M: Bjorn Andersson <bjorn.andersson@linaro.org>
15876+L: linux-arm-msm@vger.kernel.org
15877+S: Supported
15878+T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git
15879+F: Documentation/devicetree/bindings/clock/qcom,*
15880+F: drivers/clk/qcom/
15881+F: include/dt-bindings/clock/qcom,*
15882+
1587115883 QUALCOMM CORE POWER REDUCTION (CPR) AVS DRIVER
1587215884 M: Niklas Cassel <nks@flawful.org>
1587315885 L: linux-pm@vger.kernel.org
drivers/acpi/acpi_apd.c+9−2
@@ -87,8 +87,15 @@ static int fch_misc_setup(struct apd_private_data *pdata) · 86 unmodified lines
8787 if (ret < 0)
8888 return -ENOENT;
8989
90− if (!acpi_dev_get_property(adev, "is-rv", ACPI_TYPE_INTEGER, &obj))
91− clk_data->is_rv = obj->integer.value;
90+ if (!acpi_dev_get_property(adev, "clk-name", ACPI_TYPE_STRING, &obj)) {
91+ clk_data->name = devm_kzalloc(&adev->dev, obj->string.length,
92+ GFP_KERNEL);
93+
94+ strcpy(clk_data->name, obj->string.pointer);
95+ } else {
96+ /* Set default name to mclk if entry missing in firmware */
97+ clk_data->name = "mclk";
98+ }
9299
93100 list_for_each_entry(rentry, &resource_list, node) {
94101 clk_data->base = devm_ioremap(&adev->dev, rentry->res->start,
drivers/clk/Kconfig+16−10
@@ -169,6 +169,14 @@ config COMMON_CLK_CDCE706 · 168 unmodified lines
169169 help
170170 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
171171
172+config COMMON_CLK_TPS68470
173+ tristate "Clock Driver for TI TPS68470 PMIC"
174+ depends on I2C
175+ depends on INTEL_SKL_INT3472 || COMPILE_TEST
176+ select REGMAP_I2C
177+ help
178+ This driver supports the clocks provided by the TPS68470 PMIC.
179+
172180 config COMMON_CLK_CDCE925
173181 tristate "Clock driver for TI CDCE913/925/937/949 devices"
174182 depends on I2C
@@ -221,6 +229,13 @@ config COMMON_CLK_GEMINI · 46 unmodified lines
221229 This driver supports the SoC clocks on the Cortina Systems Gemini
222230 platform, also known as SL3516 or CS3516.
223231
232+config COMMON_CLK_LAN966X
233+ bool "Generic Clock Controller driver for LAN966X SoC"
234+ help
235+ This driver provides support for Generic Clock Controller(GCK) on
236+ LAN966X SoC. GCK generates and supplies clock to various peripherals
237+ within the SoC.
238+
224239 config COMMON_CLK_ASPEED
225240 bool "Clock driver for Aspeed BMC SoCs"
226241 depends on ARCH_ASPEED || COMPILE_TEST
@@ -339,16 +354,6 @@ config COMMON_CLK_STM32MP157 · 112 unmodified lines
339354 help
340355 Support for stm32mp157 SoC family clocks
341356
342−config COMMON_CLK_STM32MP157_SCMI
343− bool "stm32mp157 Clock driver with Trusted Firmware"
344− depends on COMMON_CLK_STM32MP157
345− select COMMON_CLK_SCMI
346− select ARM_SCMI_PROTOCOL
347− default y
348− help
349− Support for stm32mp157 SoC family clocks with Trusted Firmware using
350− SCMI protocol.
351−
352357 config COMMON_CLK_STM32F
353358 def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)
354359 help
@@ -418,6 +423,7 @@ source "drivers/clk/sunxi-ng/Kconfig" · 63 unmodified lines
418423 source "drivers/clk/tegra/Kconfig"
419424 source "drivers/clk/ti/Kconfig"
420425 source "drivers/clk/uniphier/Kconfig"
426+source "drivers/clk/visconti/Kconfig"
421427 source "drivers/clk/x86/Kconfig"
422428 source "drivers/clk/xilinx/Kconfig"
423429 source "drivers/clk/zynqmp/Kconfig"
drivers/clk/Makefile+4−1
@@ -37,6 +37,7 @@ obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o · 36 unmodified lines
3737 obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
3838 obj-$(CONFIG_COMMON_CLK_K210) += clk-k210.o
3939 obj-$(CONFIG_LMK04832) += clk-lmk04832.o
40+obj-$(CONFIG_COMMON_CLK_LAN966X) += clk-lan966x.o
4041 obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o
4142 obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
4243 obj-$(CONFIG_COMMON_CLK_MAX9485) += clk-max9485.o
@@ -63,6 +64,7 @@ obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o · 20 unmodified lines
6364 obj-$(CONFIG_COMMON_CLK_STM32F) += clk-stm32f4.o
6465 obj-$(CONFIG_COMMON_CLK_STM32H7) += clk-stm32h7.o
6566 obj-$(CONFIG_COMMON_CLK_STM32MP157) += clk-stm32mp1.o
67+obj-$(CONFIG_COMMON_CLK_TPS68470) += clk-tps68470.o
6668 obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
6769 obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
6870 obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o
@@ -111,12 +113,13 @@ obj-y += sprd/ · 42 unmodified lines
111113 obj-$(CONFIG_ARCH_STI) += st/
112114 obj-$(CONFIG_SOC_STARFIVE) += starfive/
113115 obj-$(CONFIG_ARCH_SUNXI) += sunxi/
114−obj-$(CONFIG_SUNXI_CCU) += sunxi-ng/
116+obj-y += sunxi-ng/
115117 obj-$(CONFIG_ARCH_TEGRA) += tegra/
116118 obj-y += ti/
117119 obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
118120 obj-$(CONFIG_ARCH_U8500) += ux500/
119121 obj-y += versatile/
122+obj-$(CONFIG_COMMON_CLK_VISCONTI) += visconti/
120123 ifeq ($(CONFIG_COMMON_CLK), y)
121124 obj-$(CONFIG_X86) += x86/
122125 endif
drivers/clk/clk-bm1880.c+2−18
@@ -522,14 +522,6 @@ static struct clk_hw *bm1880_clk_register_pll(struct bm1880_pll_hw_clock *pll_cl · 521 unmodified lines
522522 return hw;
523523 }
524524
525−static void bm1880_clk_unregister_pll(struct clk_hw *hw)
526−{
527− struct bm1880_pll_hw_clock *pll_hw = to_bm1880_pll_clk(hw);
528−
529− clk_hw_unregister(hw);
530− kfree(pll_hw);
531−}
532−
533525 static int bm1880_clk_register_plls(struct bm1880_pll_hw_clock *clks,
534526 int num_clks,
535527 struct bm1880_clock_data *data)
@@ -555,7 +547,7 @@ static int bm1880_clk_register_plls(struct bm1880_pll_hw_clock *clks, · 19 unmodified lines
555547
556548 err_clk:
557549 while (i--)
558− bm1880_clk_unregister_pll(data->hw_data.hws[clks[i].pll.id]);
550+ clk_hw_unregister(data->hw_data.hws[clks[i].pll.id]);
559551
560552 return PTR_ERR(hw);
561553 }
@@ -695,14 +687,6 @@ static struct clk_hw *bm1880_clk_register_div(struct bm1880_div_hw_clock *div_cl · 133 unmodified lines
695687 return hw;
696688 }
697689
698−static void bm1880_clk_unregister_div(struct clk_hw *hw)
699−{
700− struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw);
701−
702− clk_hw_unregister(hw);
703− kfree(div_hw);
704−}
705−
706690 static int bm1880_clk_register_divs(struct bm1880_div_hw_clock *clks,
707691 int num_clks,
708692 struct bm1880_clock_data *data)
@@ -729,7 +713,7 @@ static int bm1880_clk_register_divs(struct bm1880_div_hw_clock *clks, · 20 unmodified lines
729713
730714 err_clk:
731715 while (i--)
732− bm1880_clk_unregister_div(data->hw_data.hws[clks[i].div.id]);
716+ clk_hw_unregister(data->hw_data.hws[clks[i].div.id]);
733717
734718 return PTR_ERR(hw);
735719 }
drivers/clk/clk-gate.c+35−0
@@ -7,6 +7,7 @@ · 6 unmodified lines
77 */
88
99 #include <linux/clk-provider.h>
10+#include <linux/device.h>
1011 #include <linux/module.h>
1112 #include <linux/slab.h>
1213 #include <linux/io.h>
@@ -222,3 +223,37 @@ void clk_hw_unregister_gate(struct clk_hw *hw) · 209 unmodified lines
222223 kfree(gate);
223224 }
224225 EXPORT_SYMBOL_GPL(clk_hw_unregister_gate);
226+
227+static void devm_clk_hw_release_gate(struct device *dev, void *res)
228+{
229+ clk_hw_unregister_gate(*(struct clk_hw **)res);
230+}
231+
232+struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
233+ struct device_node *np, const char *name,
234+ const char *parent_name, const struct clk_hw *parent_hw,
235+ const struct clk_parent_data *parent_data,
236+ unsigned long flags,
237+ void __iomem *reg, u8 bit_idx,
238+ u8 clk_gate_flags, spinlock_t *lock)
239+{
240+ struct clk_hw **ptr, *hw;
241+
242+ ptr = devres_alloc(devm_clk_hw_release_gate, sizeof(*ptr), GFP_KERNEL);
243+ if (!ptr)
244+ return ERR_PTR(-ENOMEM);
245+
246+ hw = __clk_hw_register_gate(dev, np, name, parent_name, parent_hw,
247+ parent_data, flags, reg, bit_idx,
248+ clk_gate_flags, lock);
249+
250+ if (!IS_ERR(hw)) {
251+ *ptr = hw;
252+ devres_add(dev, ptr);
253+ } else {
254+ devres_free(ptr);
255+ }
256+
257+ return hw;
258+}
259+EXPORT_SYMBOL_GPL(__devm_clk_hw_register_gate);
drivers/clk/clk-gemini.c+1−1
@@ -50,7 +50,7 @@ static DEFINE_SPINLOCK(gemini_clk_lock); · 49 unmodified lines
5050 #define PCI_DLL_TAP_SEL_MASK 0x1f
5151
5252 /**
53− * struct gemini_data_data - Gemini gated clocks
53+ * struct gemini_gate_data - Gemini gated clocks
5454 * @bit_idx: the bit used to gate this clock in the clock register
5555 * @name: the clock name
5656 * @parent_name: the name of the parent clock
drivers/clk/clk-lan966x.c+293−0
@@ -0,0 +1,293 @@
1+// SPDX-License-Identifier: GPL-2.0-or-later
2+/*
3+ * Microchip LAN966x SoC Clock driver.
4+ *
5+ * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
6+ *
7+ * Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
8+ */
9+
10+#include <linux/bitfield.h>
11+#include <linux/clk-provider.h>
12+#include <linux/io.h>
13+#include <linux/kernel.h>
14+#include <linux/module.h>
15+#include <linux/of.h>
16+#include <linux/platform_device.h>
17+#include <linux/slab.h>
18+
19+#include <dt-bindings/clock/microchip,lan966x.h>
20+
21+#define GCK_ENA BIT(0)
22+#define GCK_SRC_SEL GENMASK(9, 8)
23+#define GCK_PRESCALER GENMASK(23, 16)
24+
25+#define DIV_MAX 255
26+
27+static const char *clk_names[N_CLOCKS] = {
28+ "qspi0", "qspi1", "qspi2", "sdmmc0",
29+ "pi", "mcan0", "mcan1", "flexcom0",
30+ "flexcom1", "flexcom2", "flexcom3",
31+ "flexcom4", "timer1", "usb_refclk",
32+};
33+
34+struct lan966x_gck {
35+ struct clk_hw hw;
36+ void __iomem *reg;
37+};
38+#define to_lan966x_gck(hw) container_of(hw, struct lan966x_gck, hw)
39+
40+static const struct clk_parent_data lan966x_gck_pdata[] = {
41+ { .fw_name = "cpu", },
42+ { .fw_name = "ddr", },
43+ { .fw_name = "sys", },
44+};
45+
46+static struct clk_init_data init = {
47+ .parent_data = lan966x_gck_pdata,
48+ .num_parents = ARRAY_SIZE(lan966x_gck_pdata),
49+};
50+
51+struct clk_gate_soc_desc {
52+ const char *name;
53+ int bit_idx;
54+};
55+
56+static const struct clk_gate_soc_desc clk_gate_desc[] = {
57+ { "uhphs", 11 },
58+ { "udphs", 10 },
59+ { "mcramc", 9 },
60+ { "hmatrix", 8 },
61+ { }
62+};
63+
64+static DEFINE_SPINLOCK(clk_gate_lock);
65+static void __iomem *base;
66+
67+static int lan966x_gck_enable(struct clk_hw *hw)
68+{
69+ struct lan966x_gck *gck = to_lan966x_gck(hw);
70+ u32 val = readl(gck->reg);
71+
72+ val |= GCK_ENA;
73+ writel(val, gck->reg);
74+
75+ return 0;
76+}
77+
78+static void lan966x_gck_disable(struct clk_hw *hw)
79+{
80+ struct lan966x_gck *gck = to_lan966x_gck(hw);
81+ u32 val = readl(gck->reg);
82+
83+ val &= ~GCK_ENA;
84+ writel(val, gck->reg);
85+}
86+
87+static int lan966x_gck_set_rate(struct clk_hw *hw,
88+ unsigned long rate,
89+ unsigned long parent_rate)
90+{
91+ struct lan966x_gck *gck = to_lan966x_gck(hw);
92+ u32 div, val = readl(gck->reg);
93+
94+ if (rate == 0 || parent_rate == 0)
95+ return -EINVAL;
96+
97+ /* Set Prescalar */
98+ div = parent_rate / rate;
99+ val &= ~GCK_PRESCALER;
100+ val |= FIELD_PREP(GCK_PRESCALER, (div - 1));
101+ writel(val, gck->reg);
102+
103+ return 0;
104+}
105+
106+static long lan966x_gck_round_rate(struct clk_hw *hw, unsigned long rate,
107+ unsigned long *parent_rate)
108+{
109+ unsigned int div;
110+
111+ if (rate == 0 || *parent_rate == 0)
112+ return -EINVAL;
113+
114+ if (rate >= *parent_rate)
115+ return *parent_rate;
116+
117+ div = DIV_ROUND_CLOSEST(*parent_rate, rate);
118+
119+ return *parent_rate / div;
120+}
121+
122+static unsigned long lan966x_gck_recalc_rate(struct clk_hw *hw,
123+ unsigned long parent_rate)
124+{
125+ struct lan966x_gck *gck = to_lan966x_gck(hw);
126+ u32 div, val = readl(gck->reg);
127+
128+ div = FIELD_GET(GCK_PRESCALER, val);
129+
130+ return parent_rate / (div + 1);
131+}
132+
133+static int lan966x_gck_determine_rate(struct clk_hw *hw,
134+ struct clk_rate_request *req)
135+{
136+ struct clk_hw *parent;
137+ int i;
138+
139+ for (i = 0; i < clk_hw_get_num_parents(hw); ++i) {
140+ parent = clk_hw_get_parent_by_index(hw, i);
141+ if (!parent)
142+ continue;
143+
144+ /* Allowed prescaler divider range is 0-255 */
145+ if (clk_hw_get_rate(parent) / req->rate <= DIV_MAX) {
146+ req->best_parent_hw = parent;
147+ req->best_parent_rate = clk_hw_get_rate(parent);
148+
149+ return 0;
150+ }
151+ }
152+
153+ return -EINVAL;
154+}
155+
156+static u8 lan966x_gck_get_parent(struct clk_hw *hw)
157+{
158+ struct lan966x_gck *gck = to_lan966x_gck(hw);
159+ u32 val = readl(gck->reg);
160+
161+ return FIELD_GET(GCK_SRC_SEL, val);
162+}
163+
164+static int lan966x_gck_set_parent(struct clk_hw *hw, u8 index)
165+{
166+ struct lan966x_gck *gck = to_lan966x_gck(hw);
167+ u32 val = readl(gck->reg);
168+
169+ val &= ~GCK_SRC_SEL;
170+ val |= FIELD_PREP(GCK_SRC_SEL, index);
171+ writel(val, gck->reg);
172+
173+ return 0;
174+}
175+
176+static const struct clk_ops lan966x_gck_ops = {
177+ .enable = lan966x_gck_enable,
178+ .disable = lan966x_gck_disable,
179+ .set_rate = lan966x_gck_set_rate,
180+ .round_rate = lan966x_gck_round_rate,
181+ .recalc_rate = lan966x_gck_recalc_rate,
182+ .determine_rate = lan966x_gck_determine_rate,
183+ .set_parent = lan966x_gck_set_parent,
184+ .get_parent = lan966x_gck_get_parent,
185+};
186+
187+static struct clk_hw *lan966x_gck_clk_register(struct device *dev, int i)
188+{
189+ struct lan966x_gck *priv;
190+ int ret;
191+
192+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
193+ if (!priv)
194+ return ERR_PTR(-ENOMEM);
195+
196+ priv->reg = base + (i * 4);
197+ priv->hw.init = &init;
198+ ret = devm_clk_hw_register(dev, &priv->hw);
199+ if (ret)
200+ return ERR_PTR(ret);
201+
202+ return &priv->hw;
203+};
204+
205+static int lan966x_gate_clk_register(struct device *dev,
206+ struct clk_hw_onecell_data *hw_data,
207+ void __iomem *gate_base)
208+{
209+ int i;
210+
211+ for (i = GCK_GATE_UHPHS; i < N_CLOCKS; ++i) {
212+ int idx = i - GCK_GATE_UHPHS;
213+
214+ hw_data->hws[i] =
215+ devm_clk_hw_register_gate(dev, clk_gate_desc[idx].name,
216+ "lan966x", 0, base,
217+ clk_gate_desc[idx].bit_idx,
218+ 0, &clk_gate_lock);
219+
220+ if (IS_ERR(hw_data->hws[i]))
221+ return dev_err_probe(dev, PTR_ERR(hw_data->hws[i]),
222+ "failed to register %s clock\n",
223+ clk_gate_desc[idx].name);
224+ }
225+
226+ return 0;
227+}
228+
229+static int lan966x_clk_probe(struct platform_device *pdev)
230+{
231+ struct clk_hw_onecell_data *hw_data;
232+ struct device *dev = &pdev->dev;
233+ void __iomem *gate_base;
234+ struct resource *res;
235+ int i, ret;
236+
237+ hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, N_CLOCKS),
238+ GFP_KERNEL);
239+ if (!hw_data)
240+ return -ENOMEM;
241+
242+ base = devm_platform_ioremap_resource(pdev, 0);
243+ if (IS_ERR(base))
244+ return PTR_ERR(base);
245+
246+ init.ops = &lan966x_gck_ops;
247+
248+ hw_data->num = GCK_GATE_UHPHS;
249+
250+ for (i = 0; i < GCK_GATE_UHPHS; i++) {
251+ init.name = clk_names[i];
252+ hw_data->hws[i] = lan966x_gck_clk_register(dev, i);
253+ if (IS_ERR(hw_data->hws[i])) {
254+ dev_err(dev, "failed to register %s clock\n",
255+ init.name);
256+ return PTR_ERR(hw_data->hws[i]);
257+ }
258+ }
259+
260+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
261+ if (res) {
262+ gate_base = devm_ioremap_resource(&pdev->dev, res);
263+ if (IS_ERR(gate_base))
264+ return PTR_ERR(gate_base);
265+
266+ hw_data->num = N_CLOCKS;
267+
268+ ret = lan966x_gate_clk_register(dev, hw_data, gate_base);
269+ if (ret)
270+ return ret;
271+ }
272+
273+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data);
274+}
275+
276+static const struct of_device_id lan966x_clk_dt_ids[] = {
277+ { .compatible = "microchip,lan966x-gck", },
278+ { }
279+};
280+MODULE_DEVICE_TABLE(of, lan966x_clk_dt_ids);
281+
282+static struct platform_driver lan966x_clk_driver = {
283+ .probe = lan966x_clk_probe,
284+ .driver = {
285+ .name = "lan966x-clk",
286+ .of_match_table = lan966x_clk_dt_ids,
287+ },
288+};
289+builtin_platform_driver(lan966x_clk_driver);
290+
291+MODULE_AUTHOR("Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>");
292+MODULE_DESCRIPTION("LAN966X clock driver");
293+MODULE_LICENSE("GPL v2");
drivers/clk/clk-stm32f4.c+0−4
@@ -129,7 +129,6 @@ static const struct stm32f4_gate_data stm32f429_gates[] __initconst = { · 128 unmodified lines
129129 { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
130130 { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
131131 { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
132− { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
133132 };
134133
135134 static const struct stm32f4_gate_data stm32f469_gates[] __initconst = {
@@ -211,7 +210,6 @@ static const struct stm32f4_gate_data stm32f469_gates[] __initconst = { · 75 unmodified lines
211210 { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
212211 { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
213212 { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
214− { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
215213 };
216214
217215 static const struct stm32f4_gate_data stm32f746_gates[] __initconst = {
@@ -286,7 +284,6 @@ static const struct stm32f4_gate_data stm32f746_gates[] __initconst = { · 68 unmodified lines
286284 { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
287285 { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
288286 { STM32F4_RCC_APB2ENR, 23, "sai2", "apb2_div" },
289− { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
290287 };
291288
292289 static const struct stm32f4_gate_data stm32f769_gates[] __initconst = {
@@ -364,7 +361,6 @@ static const struct stm32f4_gate_data stm32f769_gates[] __initconst = { · 71 unmodified lines
364361 { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
365362 { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
366363 { STM32F4_RCC_APB2ENR, 23, "sai2", "apb2_div" },
367− { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
368364 { STM32F4_RCC_APB2ENR, 30, "mdio", "apb2_div" },
369365 };
370366
drivers/clk/clk-stm32mp1.c+0−2
@@ -2253,8 +2253,6 @@ static int stm32_rcc_reset_init(struct device *dev, void __iomem *base, · 2252 unmodified lines
22532253 const struct stm32_rcc_match_data *data = match->data;
22542254 struct stm32_reset_data *reset_data = NULL;
22552255
2256− data = match->data;
2257−
22582256 reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
22592257 if (!reset_data)
22602258 return -ENOMEM;
drivers/clk/clk-tps68470.c+261−0
@@ -0,0 +1,261 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Clock driver for TPS68470 PMIC
4+ *
5+ * Copyright (c) 2021 Red Hat Inc.
6+ * Copyright (C) 2018 Intel Corporation
7+ *
8+ * Authors:
9+ * Hans de Goede <hdegoede@redhat.com>
10+ * Zaikuo Wang <zaikuo.wang@intel.com>
11+ * Tianshu Qiu <tian.shu.qiu@intel.com>
12+ * Jian Xu Zheng <jian.xu.zheng@intel.com>
13+ * Yuning Pu <yuning.pu@intel.com>
14+ * Antti Laakso <antti.laakso@intel.com>
15+ */
16+
17+#include <linux/clk-provider.h>
18+#include <linux/clkdev.h>
19+#include <linux/kernel.h>
20+#include <linux/mfd/tps68470.h>
21+#include <linux/module.h>
22+#include <linux/platform_device.h>
23+#include <linux/platform_data/tps68470.h>
24+#include <linux/regmap.h>
25+
26+#define TPS68470_CLK_NAME "tps68470-clk"
27+
28+#define to_tps68470_clkdata(clkd) \
29+ container_of(clkd, struct tps68470_clkdata, clkout_hw)
30+
31+static struct tps68470_clkout_freqs {
32+ unsigned long freq;
33+ unsigned int xtaldiv;
34+ unsigned int plldiv;
35+ unsigned int postdiv;
36+ unsigned int buckdiv;
37+ unsigned int boostdiv;
38+} clk_freqs[] = {
39+/*
40+ * The PLL is used to multiply the crystal oscillator
41+ * frequency range of 3 MHz to 27 MHz by a programmable
42+ * factor of F = (M/N)*(1/P) such that the output
43+ * available at the HCLK_A or HCLK_B pins are in the range
44+ * of 4 MHz to 64 MHz in increments of 0.1 MHz.
45+ *
46+ * hclk_# = osc_in * (((plldiv*2)+320) / (xtaldiv+30)) * (1 / 2^postdiv)
47+ *
48+ * PLL_REF_CLK should be as close as possible to 100kHz
49+ * PLL_REF_CLK = input clk / XTALDIV[7:0] + 30)
50+ *
51+ * PLL_VCO_CLK = (PLL_REF_CLK * (plldiv*2 + 320))
52+ *
53+ * BOOST should be as close as possible to 2Mhz
54+ * BOOST = PLL_VCO_CLK / (BOOSTDIV[4:0] + 16) *
55+ *
56+ * BUCK should be as close as possible to 5.2Mhz
57+ * BUCK = PLL_VCO_CLK / (BUCKDIV[3:0] + 5)
58+ *
59+ * osc_in xtaldiv plldiv postdiv hclk_#
60+ * 20Mhz 170 32 1 19.2Mhz
61+ * 20Mhz 170 40 1 20Mhz
62+ * 20Mhz 170 80 1 24Mhz
63+ */
64+ { 19200000, 170, 32, 1, 2, 3 },
65+ { 20000000, 170, 40, 1, 3, 4 },
66+ { 24000000, 170, 80, 1, 4, 8 },
67+};
68+
69+struct tps68470_clkdata {
70+ struct clk_hw clkout_hw;
71+ struct regmap *regmap;
72+ unsigned long rate;
73+};
74+
75+static int tps68470_clk_is_prepared(struct clk_hw *hw)
76+{
77+ struct tps68470_clkdata *clkdata = to_tps68470_clkdata(hw);
78+ int val;
79+
80+ if (regmap_read(clkdata->regmap, TPS68470_REG_PLLCTL, &val))
81+ return 0;
82+
83+ return val & TPS68470_PLL_EN_MASK;
84+}
85+
86+static int tps68470_clk_prepare(struct clk_hw *hw)
87+{
88+ struct tps68470_clkdata *clkdata = to_tps68470_clkdata(hw);
89+
90+ regmap_write(clkdata->regmap, TPS68470_REG_CLKCFG1,
91+ (TPS68470_PLL_OUTPUT_ENABLE << TPS68470_OUTPUT_A_SHIFT) |
92+ (TPS68470_PLL_OUTPUT_ENABLE << TPS68470_OUTPUT_B_SHIFT));
93+
94+ regmap_update_bits(clkdata->regmap, TPS68470_REG_PLLCTL,
95+ TPS68470_PLL_EN_MASK, TPS68470_PLL_EN_MASK);
96+
97+ /*
98+ * The PLLCTL reg lock bit is set by the PMIC after approx. 4ms and
99+ * does not indicate a true lock, so just wait 4 ms.
100+ */
101+ usleep_range(4000, 5000);
102+
103+ return 0;
104+}
105+
106+static void tps68470_clk_unprepare(struct clk_hw *hw)
107+{
108+ struct tps68470_clkdata *clkdata = to_tps68470_clkdata(hw);
109+
110+ /* Disable clock first ... */
111+ regmap_update_bits(clkdata->regmap, TPS68470_REG_PLLCTL, TPS68470_PLL_EN_MASK, 0);
112+
113+ /* ... and then tri-state the clock outputs. */
114+ regmap_write(clkdata->regmap, TPS68470_REG_CLKCFG1, 0);
115+}
116+
117+static unsigned long tps68470_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
118+{
119+ struct tps68470_clkdata *clkdata = to_tps68470_clkdata(hw);
120+
121+ return clkdata->rate;
122+}
123+
124+/*
125+ * This returns the index of the clk_freqs[] cfg with the closest rate for
126+ * use in tps68470_clk_round_rate(). tps68470_clk_set_rate() checks that
127+ * the rate of the returned cfg is an exact match.
128+ */
129+static unsigned int tps68470_clk_cfg_lookup(unsigned long rate)
130+{
131+ long diff, best_diff = LONG_MAX;
132+ unsigned int i, best_idx = 0;
133+
134+ for (i = 0; i < ARRAY_SIZE(clk_freqs); i++) {
135+ diff = clk_freqs[i].freq - rate;
136+ if (diff == 0)
137+ return i;
138+
139+ diff = abs(diff);
140+ if (diff < best_diff) {
141+ best_diff = diff;
142+ best_idx = i;
143+ }
144+ }
145+
146+ return best_idx;
147+}
148+
149+static long tps68470_clk_round_rate(struct clk_hw *hw, unsigned long rate,
150+ unsigned long *parent_rate)
151+{
152+ unsigned int idx = tps68470_clk_cfg_lookup(rate);
153+
154+ return clk_freqs[idx].freq;
155+}
156+
157+static int tps68470_clk_set_rate(struct clk_hw *hw, unsigned long rate,
158+ unsigned long parent_rate)
159+{
160+ struct tps68470_clkdata *clkdata = to_tps68470_clkdata(hw);
161+ unsigned int idx = tps68470_clk_cfg_lookup(rate);
162+
163+ if (rate != clk_freqs[idx].freq)
164+ return -EINVAL;
165+
166+ regmap_write(clkdata->regmap, TPS68470_REG_BOOSTDIV, clk_freqs[idx].boostdiv);
167+ regmap_write(clkdata->regmap, TPS68470_REG_BUCKDIV, clk_freqs[idx].buckdiv);
168+ regmap_write(clkdata->regmap, TPS68470_REG_PLLSWR, TPS68470_PLLSWR_DEFAULT);
169+ regmap_write(clkdata->regmap, TPS68470_REG_XTALDIV, clk_freqs[idx].xtaldiv);
170+ regmap_write(clkdata->regmap, TPS68470_REG_PLLDIV, clk_freqs[idx].plldiv);
171+ regmap_write(clkdata->regmap, TPS68470_REG_POSTDIV, clk_freqs[idx].postdiv);
172+ regmap_write(clkdata->regmap, TPS68470_REG_POSTDIV2, clk_freqs[idx].postdiv);
173+ regmap_write(clkdata->regmap, TPS68470_REG_CLKCFG2, TPS68470_CLKCFG2_DRV_STR_2MA);
174+
175+ regmap_write(clkdata->regmap, TPS68470_REG_PLLCTL,
176+ TPS68470_OSC_EXT_CAP_DEFAULT << TPS68470_OSC_EXT_CAP_SHIFT |
177+ TPS68470_CLK_SRC_XTAL << TPS68470_CLK_SRC_SHIFT);
178+
179+ clkdata->rate = rate;
180+
181+ return 0;
182+}
183+
184+static const struct clk_ops tps68470_clk_ops = {
185+ .is_prepared = tps68470_clk_is_prepared,
186+ .prepare = tps68470_clk_prepare,
187+ .unprepare = tps68470_clk_unprepare,
188+ .recalc_rate = tps68470_clk_recalc_rate,
189+ .round_rate = tps68470_clk_round_rate,
190+ .set_rate = tps68470_clk_set_rate,
191+};
192+
193+static int tps68470_clk_probe(struct platform_device *pdev)
194+{
195+ struct tps68470_clk_platform_data *pdata = pdev->dev.platform_data;
196+ struct clk_init_data tps68470_clk_initdata = {
197+ .name = TPS68470_CLK_NAME,
198+ .ops = &tps68470_clk_ops,
199+ /* Changing the dividers when the PLL is on is not allowed */
200+ .flags = CLK_SET_RATE_GATE,
201+ };
202+ struct tps68470_clkdata *tps68470_clkdata;
203+ int ret;
204+
205+ tps68470_clkdata = devm_kzalloc(&pdev->dev, sizeof(*tps68470_clkdata),
206+ GFP_KERNEL);
207+ if (!tps68470_clkdata)
208+ return -ENOMEM;
209+
210+ tps68470_clkdata->regmap = dev_get_drvdata(pdev->dev.parent);
211+ tps68470_clkdata->clkout_hw.init = &tps68470_clk_initdata;
212+
213+ /* Set initial rate */
214+ tps68470_clk_set_rate(&tps68470_clkdata->clkout_hw, clk_freqs[0].freq, 0);
215+
216+ ret = devm_clk_hw_register(&pdev->dev, &tps68470_clkdata->clkout_hw);
217+ if (ret)
218+ return ret;
219+
220+ ret = devm_clk_hw_register_clkdev(&pdev->dev, &tps68470_clkdata->clkout_hw,
221+ TPS68470_CLK_NAME, NULL);
222+ if (ret)
223+ return ret;
224+
225+ if (pdata) {
226+ ret = devm_clk_hw_register_clkdev(&pdev->dev,
227+ &tps68470_clkdata->clkout_hw,
228+ pdata->consumer_con_id,
229+ pdata->consumer_dev_name);
230+ }
231+
232+ return ret;
233+}
234+
235+static struct platform_driver tps68470_clk_driver = {
236+ .driver = {
237+ .name = TPS68470_CLK_NAME,
238+ },
239+ .probe = tps68470_clk_probe,
240+};
241+
242+/*
243+ * The ACPI tps68470 probe-ordering depends on the clk/gpio/regulator drivers
244+ * registering before the drivers for the camera-sensors which use them bind.
245+ * subsys_initcall() ensures this when the drivers are builtin.
246+ */
247+static int __init tps68470_clk_init(void)
248+{
249+ return platform_driver_register(&tps68470_clk_driver);
250+}
251+subsys_initcall(tps68470_clk_init);
252+
253+static void __exit tps68470_clk_exit(void)
254+{
255+ platform_driver_unregister(&tps68470_clk_driver);
256+}
257+module_exit(tps68470_clk_exit);
258+
259+MODULE_ALIAS("platform:tps68470-clk");
260+MODULE_DESCRIPTION("clock driver for TPS68470 pmic");
261+MODULE_LICENSE("GPL");
drivers/clk/clk.c+69−11
@@ -424,19 +424,20 @@ static void clk_core_fill_parent_index(struct clk_core *core, u8 index) · 423 unmodified lines
424424
425425 if (entry->hw) {
426426 parent = entry->hw->core;
427− /*
428− * We have a direct reference but it isn't registered yet?
429− * Orphan it and let clk_reparent() update the orphan status
430− * when the parent is registered.
431− */
432− if (!parent)
433− parent = ERR_PTR(-EPROBE_DEFER);
434427 } else {
435428 parent = clk_core_get(core, index);
436429 if (PTR_ERR(parent) == -ENOENT && entry->name)
437430 parent = clk_core_lookup(entry->name);
438431 }
439432
433+ /*
434+ * We have a direct reference but it isn't registered yet?
435+ * Orphan it and let clk_reparent() update the orphan status
436+ * when the parent is registered.
437+ */
438+ if (!parent)
439+ parent = ERR_PTR(-EPROBE_DEFER);
440+
440441 /* Only cache it if it's not an error */
441442 if (!IS_ERR(parent))
442443 entry->core = parent;
@@ -2965,7 +2966,9 @@ static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c, · 2522 unmodified lines
29652966 {
29662967 struct clk_core *child;
29672968
2969+ clk_pm_runtime_get(c);
29682970 clk_summary_show_one(s, c, level);
2971+ clk_pm_runtime_put(c);
29692972
29702973 hlist_for_each_entry(child, &c->children, child_node)
29712974 clk_summary_show_subtree(s, child, level + 1);
@@ -3217,6 +3220,42 @@ static int current_parent_show(struct seq_file *s, void *data) · 245 unmodified lines
32173220 }
32183221 DEFINE_SHOW_ATTRIBUTE(current_parent);
32193222
3223+#ifdef CLOCK_ALLOW_WRITE_DEBUGFS
3224+static ssize_t current_parent_write(struct file *file, const char __user *ubuf,
3225+ size_t count, loff_t *ppos)
3226+{
3227+ struct seq_file *s = file->private_data;
3228+ struct clk_core *core = s->private;
3229+ struct clk_core *parent;
3230+ u8 idx;
3231+ int err;
3232+
3233+ err = kstrtou8_from_user(ubuf, count, 0, &idx);
3234+ if (err < 0)
3235+ return err;
3236+
3237+ parent = clk_core_get_parent_by_index(core, idx);
3238+ if (!parent)
3239+ return -ENOENT;
3240+
3241+ clk_prepare_lock();
3242+ err = clk_core_set_parent_nolock(core, parent);
3243+ clk_prepare_unlock();
3244+ if (err)
3245+ return err;
3246+
3247+ return count;
3248+}
3249+
3250+static const struct file_operations current_parent_rw_fops = {
3251+ .open = current_parent_open,
3252+ .write = current_parent_write,
3253+ .read = seq_read,
3254+ .llseek = seq_lseek,
3255+ .release = single_release,
3256+};
3257+#endif
3258+
32203259 static int clk_duty_cycle_show(struct seq_file *s, void *data)
32213260 {
32223261 struct clk_core *core = s->private;
@@ -3282,8 +3321,12 @@ static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry) · 59 unmodified lines
32823321 #ifdef CLOCK_ALLOW_WRITE_DEBUGFS
32833322 debugfs_create_file("clk_prepare_enable", 0644, root, core,
32843323 &clk_prepare_enable_fops);
3285−#endif
32863324
3325+ if (core->num_parents > 1)
3326+ debugfs_create_file("clk_parent", 0644, root, core,
3327+ &current_parent_rw_fops);
3328+ else
3329+#endif
32873330 if (core->num_parents > 0)
32883331 debugfs_create_file("clk_parent", 0444, root, core,
32893332 &current_parent_fops);
@@ -3343,6 +3386,24 @@ static int __init clk_debug_init(void) · 53 unmodified lines
33433386 {
33443387 struct clk_core *core;
33453388
3389+#ifdef CLOCK_ALLOW_WRITE_DEBUGFS
3390+ pr_warn("\n");
3391+ pr_warn("********************************************************************\n");
3392+ pr_warn("** NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE **\n");
3393+ pr_warn("** **\n");
3394+ pr_warn("** WRITEABLE clk DebugFS SUPPORT HAS BEEN ENABLED IN THIS KERNEL **\n");
3395+ pr_warn("** **\n");
3396+ pr_warn("** This means that this kernel is built to expose clk operations **\n");
3397+ pr_warn("** such as parent or rate setting, enabling, disabling, etc. **\n");
3398+ pr_warn("** to userspace, which may compromise security on your system. **\n");
3399+ pr_warn("** **\n");
3400+ pr_warn("** If you see this message and you are not debugging the **\n");
3401+ pr_warn("** kernel, report this immediately to your vendor! **\n");
3402+ pr_warn("** **\n");
3403+ pr_warn("** NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE **\n");
3404+ pr_warn("********************************************************************\n");
3405+#endif
3406+
33463407 rootdir = debugfs_create_dir("clk", NULL);
33473408
33483409 debugfs_create_file("clk_summary", 0444, rootdir, &all_lists,
@@ -3413,9 +3474,6 @@ static int __clk_core_init(struct clk_core *core) · 64 unmodified lines
34133474 unsigned long rate;
34143475 int phase;
34153476
3416− if (!core)
3417− return -EINVAL;
3418−
34193477 clk_prepare_lock();
34203478
34213479 /*
drivers/clk/imx/clk-imx8mn.c+3−3
@@ -277,9 +277,9 @@ static const char * const imx8mn_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audi · 276 unmodified lines
277277
278278 static const char * const imx8mn_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
279279
280−static const char * const imx8mn_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m",
281− "sys_pll1_200m", "audio_pll2_out", "vpu_pll",
282− "sys_pll1_80m", };
280+static const char * const imx8mn_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy",
281+ "sys_pll1_200m", "audio_pll2_out", "sys_pll2_500m",
282+ "dummy", "sys_pll1_80m", };
283283 static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m",
284284 "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out",
285285 "video_pll1_out", "osc_32k", };
drivers/clk/imx/clk-imx8mp.c+1−1
@@ -700,7 +700,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) · 699 unmodified lines
700700 hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi", ccm_base + 0x45f0, 0);
701701 hws[IMX8MP_CLK_TSENSOR_ROOT] = imx_clk_hw_gate4("tsensor_root_clk", "ipg_root", ccm_base + 0x4620, 0);
702702 hws[IMX8MP_CLK_VPU_ROOT] = imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", ccm_base + 0x4630, 0);
703− hws[IMX8MP_CLK_AUDIO_ROOT] = imx_clk_hw_gate4("audio_root_clk", "ipg_root", ccm_base + 0x4650, 0);
703+ hws[IMX8MP_CLK_AUDIO_ROOT] = imx_clk_hw_gate4("audio_root_clk", "audio_ahb", ccm_base + 0x4650, 0);
704704
705705 hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
706706 hws[IMX8MP_CLK_A53_CORE]->clk,
drivers/clk/imx/clk-imx8ulp.c+1−0
@@ -559,6 +559,7 @@ static struct platform_driver imx8ulp_clk_driver = { · 558 unmodified lines
559559 .probe = imx8ulp_clk_probe,
560560 .driver = {
561561 .name = KBUILD_MODNAME,
562+ .suppress_bind_attrs = true,
562563 .of_match_table = imx8ulp_clk_dt_ids,
563564 },
564565 };
drivers/clk/imx/clk-pllv1.c+8−9
@@ -8,20 +8,19 @@ · 7 unmodified lines
88
99 #include "clk.h"
1010
11+#define MFN_BITS (10)
12+#define MFN_SIGN (BIT(MFN_BITS - 1))
13+#define MFN_MASK (MFN_SIGN - 1)
14+
1115 /**
12− * pll v1
16+ * struct clk_pllv1 - IMX PLLv1 clock descriptor
1317 *
14− * @clk_hw clock source
15− * @parent the parent clock name
16− * @base base address of pll registers
18+ * @hw: clock source
19+ * @base: base address of pll registers
20+ * @type: type of IMX_PLLV1
1721 *
1822 * PLL clock version 1, found on i.MX1/21/25/27/31/35
1923 */
20−
21−#define MFN_BITS (10)
22−#define MFN_SIGN (BIT(MFN_BITS - 1))
23−#define MFN_MASK (MFN_SIGN - 1)
24−
2524 struct clk_pllv1 {
2625 struct clk_hw hw;
2726 void __iomem *base;
drivers/clk/imx/clk-pllv3.c+3−3
@@ -247,7 +247,7 @@ static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, · 246 unmodified lines
247247 div = rate / parent_rate;
248248 temp64 = (u64) (rate - div * parent_rate);
249249 temp64 *= mfd;
250− do_div(temp64, parent_rate);
250+ temp64 = div64_ul(temp64, parent_rate);
251251 mfn = temp64;
252252
253253 temp64 = (u64)parent_rate;
@@ -277,7 +277,7 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, · 23 unmodified lines
277277 div = rate / parent_rate;
278278 temp64 = (u64) (rate - div * parent_rate);
279279 temp64 *= mfd;
280− do_div(temp64, parent_rate);
280+ temp64 = div64_ul(temp64, parent_rate);
281281 mfn = temp64;
282282
283283 val = readl_relaxed(pll->base);
@@ -334,7 +334,7 @@ static struct clk_pllv3_vf610_mf clk_pllv3_vf610_rate_to_mf( · 50 unmodified lines
334334 /* rate = parent_rate * (mfi + mfn/mfd) */
335335 temp64 = rate - parent_rate * mf.mfi;
336336 temp64 *= mf.mfd;
337− do_div(temp64, parent_rate);
337+ temp64 = div64_ul(temp64, parent_rate);
338338 mf.mfn = temp64;
339339 }
340340
drivers/clk/ingenic/jz4760-cgu.c+10−0
@@ -313,6 +313,16 @@ static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = { · 312 unmodified lines
313313 .parents = { JZ4760_CLK_H2CLK, },
314314 .gate = { CGU_REG_CLKGR0, 21 },
315315 },
316+ [JZ4760_CLK_MDMA] = {
317+ "mdma", CGU_CLK_GATE,
318+ .parents = { JZ4760_CLK_HCLK, },
319+ .gate = { CGU_REG_CLKGR0, 25 },
320+ },
321+ [JZ4760_CLK_BDMA] = {
322+ "bdma", CGU_CLK_GATE,
323+ .parents = { JZ4760_CLK_HCLK, },
324+ .gate = { CGU_REG_CLKGR1, 0 },
325+ },
316326 [JZ4760_CLK_I2C0] = {
317327 "i2c0", CGU_CLK_GATE,
318328 .parents = { JZ4760_CLK_EXT, },
drivers/clk/ingenic/jz4770-cgu.c+5−0
@@ -329,6 +329,11 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { · 328 unmodified lines
329329 .parents = { JZ4770_CLK_H2CLK, },
330330 .gate = { CGU_REG_CLKGR0, 21 },
331331 },
332+ [JZ4770_CLK_BDMA] = {
333+ "bdma", CGU_CLK_GATE,
334+ .parents = { JZ4770_CLK_H2CLK, },
335+ .gate = { CGU_REG_CLKGR1, 0 },
336+ },
332337 [JZ4770_CLK_I2C0] = {
333338 "i2c0", CGU_CLK_GATE,
334339 .parents = { JZ4770_CLK_EXT, },
drivers/clk/mediatek/Kconfig+17−0
@@ -344,6 +344,23 @@ config COMMON_CLK_MT7629_HIFSYS · 343 unmodified lines
344344 This driver supports MediaTek MT7629 HIFSYS clocks providing
345345 to PCI-E and USB.
346346
347+config COMMON_CLK_MT7986
348+ bool "Clock driver for MediaTek MT7986"
349+ depends on ARCH_MEDIATEK || COMPILE_TEST
350+ select COMMON_CLK_MEDIATEK
351+ default ARCH_MEDIATEK
352+ help
353+ This driver supports MediaTek MT7986 basic clocks and clocks
354+ required for various peripherals found on MediaTek.
355+
356+config COMMON_CLK_MT7986_ETHSYS
357+ bool "Clock driver for MediaTek MT7986 ETHSYS"
358+ depends on COMMON_CLK_MT7986
359+ default COMMON_CLK_MT7986
360+ help
361+ This driver adds support for clocks for Ethernet and SGMII
362+ required on MediaTek MT7986 SoC.
363+
347364 config COMMON_CLK_MT8135
348365 bool "Clock driver for MediaTek MT8135"
349366 depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
drivers/clk/mediatek/Makefile+4−0
@@ -46,6 +46,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) += clk-mt7622-aud.o · 45 unmodified lines
4646 obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o
4747 obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
4848 obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
49+obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o
50+obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
51+obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
52+obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o
4953 obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
5054 obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o
5155 obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o
drivers/clk/mediatek/clk-gate.c+9−15
@@ -16,28 +16,24 @@ · 15 unmodified lines
1616 #include "clk-mtk.h"
1717 #include "clk-gate.h"
1818
19−static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
19+static u32 mtk_get_clockgating(struct clk_hw *hw)
2020 {
2121 struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
2222 u32 val;
2323
2424 regmap_read(cg->regmap, cg->sta_ofs, &val);
2525
26− val &= BIT(cg->bit);
26+ return val & BIT(cg->bit);
27+}
2728
28− return val == 0;
29+static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
30+{
31+ return mtk_get_clockgating(hw) == 0;
2932 }
3033
3134 static int mtk_cg_bit_is_set(struct clk_hw *hw)
3235 {
33− struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
34− u32 val;
35−
36− regmap_read(cg->regmap, cg->sta_ofs, &val);
37−
38− val &= BIT(cg->bit);
39−
40− return val != 0;
36+ return mtk_get_clockgating(hw) != 0;
4137 }
4238
4339 static void mtk_cg_set_bit(struct clk_hw *hw)
@@ -57,17 +53,15 @@ static void mtk_cg_clr_bit(struct clk_hw *hw) · 13 unmodified lines
5753 static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
5854 {
5955 struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
60− u32 cgbit = BIT(cg->bit);
6156
62− regmap_update_bits(cg->regmap, cg->sta_ofs, cgbit, cgbit);
57+ regmap_set_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit));
6358 }
6459
6560 static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
6661 {
6762 struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
68− u32 cgbit = BIT(cg->bit);
6963
70− regmap_update_bits(cg->regmap, cg->sta_ofs, cgbit, 0);
64+ regmap_clear_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit));
7165 }
7266
7367 static int mtk_cg_enable(struct clk_hw *hw)
drivers/clk/mediatek/clk-mt7986-apmixed.c+100−0
@@ -0,0 +1,100 @@
1+// SPDX-License-Identifier: GPL-1.0
2+/*
3+ * Copyright (c) 2021 MediaTek Inc.
4+ * Author: Sam Shih <sam.shih@mediatek.com>
5+ * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
6+ */
7+
8+#include <linux/clk-provider.h>
9+#include <linux/of.h>
10+#include <linux/of_address.h>
11+#include <linux/of_device.h>
12+#include <linux/platform_device.h>
13+#include "clk-mtk.h"
14+#include "clk-gate.h"
15+#include "clk-mux.h"
16+
17+#include <dt-bindings/clock/mt7986-clk.h>
18+#include <linux/clk.h>
19+
20+#define MT7986_PLL_FMAX (2500UL * MHZ)
21+#define CON0_MT7986_RST_BAR BIT(27)
22+
23+#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
24+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
25+ _div_table, _parent_name) \
26+ { \
27+ .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
28+ .en_mask = _en_mask, .flags = _flags, \
29+ .rst_bar_mask = CON0_MT7986_RST_BAR, .fmax = MT7986_PLL_FMAX, \
30+ .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
31+ .tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \
32+ .pcw_shift = _pcw_shift, .div_table = _div_table, \
33+ .parent_name = _parent_name, \
34+ }
35+
36+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
37+ _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \
38+ PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
39+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \
40+ "clkxtal")
41+
42+static const struct mtk_pll_data plls[] = {
43+ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, 0, 32,
44+ 0x0200, 4, 0, 0x0204, 0),
45+ PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
46+ 0x0210, 4, 0, 0x0214, 0),
47+ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
48+ 0x0220, 4, 0, 0x0224, 0),
49+ PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x00000001, 0, 32,
50+ 0x0230, 4, 0, 0x0234, 0),
51+ PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x00000001, 0,
52+ 32, 0x0240, 4, 0, 0x0244, 0),
53+ PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025c, 0x00000001, 0, 32,
54+ 0x0250, 4, 0, 0x0254, 0),
55+ PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, 0x0260,
56+ 4, 0, 0x0264, 0),
57+ PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
58+ 0x0278, 4, 0, 0x027c, 0),
59+};
60+
61+static const struct of_device_id of_match_clk_mt7986_apmixed[] = {
62+ { .compatible = "mediatek,mt7986-apmixedsys", },
63+ {}
64+};
65+
66+static int clk_mt7986_apmixed_probe(struct platform_device *pdev)
67+{
68+ struct clk_onecell_data *clk_data;
69+ struct device_node *node = pdev->dev.of_node;
70+ int r;
71+
72+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
73+ if (!clk_data)
74+ return -ENOMEM;
75+
76+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
77+
78+ clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
79+
80+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
81+ if (r) {
82+ pr_err("%s(): could not register clock provider: %d\n",
83+ __func__, r);
84+ goto free_apmixed_data;
85+ }
86+ return r;
87+
88+free_apmixed_data:
89+ mtk_free_clk_data(clk_data);
90+ return r;
91+}
92+
93+static struct platform_driver clk_mt7986_apmixed_drv = {
94+ .probe = clk_mt7986_apmixed_probe,
95+ .driver = {
96+ .name = "clk-mt7986-apmixed",
97+ .of_match_table = of_match_clk_mt7986_apmixed,
98+ },
99+};
100+builtin_platform_driver(clk_mt7986_apmixed_drv);
drivers/clk/mediatek/clk-mt7986-eth.c+132−0
@@ -0,0 +1,132 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (c) 2021 MediaTek Inc.
4+ * Author: Sam Shih <sam.shih@mediatek.com>
5+ * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
6+ */
7+
8+#include <linux/clk-provider.h>
9+#include <linux/of.h>
10+#include <linux/of_address.h>
11+#include <linux/of_device.h>
12+#include <linux/platform_device.h>
13+
14+#include "clk-mtk.h"
15+#include "clk-gate.h"
16+
17+#include <dt-bindings/clock/mt7986-clk.h>
18+
19+static const struct mtk_gate_regs sgmii0_cg_regs = {
20+ .set_ofs = 0xe4,
21+ .clr_ofs = 0xe4,
22+ .sta_ofs = 0xe4,
23+};
24+
25+#define GATE_SGMII0(_id, _name, _parent, _shift) \
26+ { \
27+ .id = _id, .name = _name, .parent_name = _parent, \
28+ .regs = &sgmii0_cg_regs, .shift = _shift, \
29+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
30+ }
31+
32+static const struct mtk_gate sgmii0_clks[] __initconst = {
33+ GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en", "top_xtal", 2),
34+ GATE_SGMII0(CLK_SGMII0_RX250M_EN, "sgmii0_rx250m_en", "top_xtal", 3),
35+ GATE_SGMII0(CLK_SGMII0_CDR_REF, "sgmii0_cdr_ref", "top_xtal", 4),
36+ GATE_SGMII0(CLK_SGMII0_CDR_FB, "sgmii0_cdr_fb", "top_xtal", 5),
37+};
38+
39+static const struct mtk_gate_regs sgmii1_cg_regs = {
40+ .set_ofs = 0xe4,
41+ .clr_ofs = 0xe4,
42+ .sta_ofs = 0xe4,
43+};
44+
45+#define GATE_SGMII1(_id, _name, _parent, _shift) \
46+ { \
47+ .id = _id, .name = _name, .parent_name = _parent, \
48+ .regs = &sgmii1_cg_regs, .shift = _shift, \
49+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
50+ }
51+
52+static const struct mtk_gate sgmii1_clks[] __initconst = {
53+ GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en", "top_xtal", 2),
54+ GATE_SGMII1(CLK_SGMII1_RX250M_EN, "sgmii1_rx250m_en", "top_xtal", 3),
55+ GATE_SGMII1(CLK_SGMII1_CDR_REF, "sgmii1_cdr_ref", "top_xtal", 4),
56+ GATE_SGMII1(CLK_SGMII1_CDR_FB, "sgmii1_cdr_fb", "top_xtal", 5),
57+};
58+
59+static const struct mtk_gate_regs eth_cg_regs = {
60+ .set_ofs = 0x30,
61+ .clr_ofs = 0x30,
62+ .sta_ofs = 0x30,
63+};
64+
65+#define GATE_ETH(_id, _name, _parent, _shift) \
66+ { \
67+ .id = _id, .name = _name, .parent_name = _parent, \
68+ .regs = &eth_cg_regs, .shift = _shift, \
69+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
70+ }
71+
72+static const struct mtk_gate eth_clks[] __initconst = {
73+ GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x_sel", 6),
74+ GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m_sel", 7),
75+ GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m_sel", 8),
76+ GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en", "netsys_mcu_sel", 14),
77+ GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_mcu_sel", 15),
78+};
79+
80+static void __init mtk_sgmiisys_0_init(struct device_node *node)
81+{
82+ struct clk_onecell_data *clk_data;
83+ int r;
84+
85+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
86+
87+ mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
88+ clk_data);
89+
90+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
91+ if (r)
92+ pr_err("%s(): could not register clock provider: %d\n",
93+ __func__, r);
94+}
95+CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7986-sgmiisys_0",
96+ mtk_sgmiisys_0_init);
97+
98+static void __init mtk_sgmiisys_1_init(struct device_node *node)
99+{
100+ struct clk_onecell_data *clk_data;
101+ int r;
102+
103+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
104+
105+ mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
106+ clk_data);
107+
108+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
109+
110+ if (r)
111+ pr_err("%s(): could not register clock provider: %d\n",
112+ __func__, r);
113+}
114+CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7986-sgmiisys_1",
115+ mtk_sgmiisys_1_init);
116+
117+static void __init mtk_ethsys_init(struct device_node *node)
118+{
119+ struct clk_onecell_data *clk_data;
120+ int r;
121+
122+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
123+
124+ mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
125+
126+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
127+
128+ if (r)
129+ pr_err("%s(): could not register clock provider: %d\n",
130+ __func__, r);
131+}
132+CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7986-ethsys_ck", mtk_ethsys_init);
drivers/clk/mediatek/clk-mt7986-infracfg.c+224−0
@@ -0,0 +1,224 @@
1+// SPDX-License-Identifier: GPL-1.0
2+/*
3+ * Copyright (c) 2021 MediaTek Inc.
4+ * Author: Sam Shih <sam.shih@mediatek.com>
5+ * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
6+ */
7+
8+#include <linux/clk-provider.h>
9+#include <linux/of.h>
10+#include <linux/of_address.h>
11+#include <linux/of_device.h>
12+#include <linux/platform_device.h>
13+#include "clk-mtk.h"
14+#include "clk-gate.h"
15+#include "clk-mux.h"
16+
17+#include <dt-bindings/clock/mt7986-clk.h>
18+#include <linux/clk.h>
19+
20+static DEFINE_SPINLOCK(mt7986_clk_lock);
21+
22+static const struct mtk_fixed_factor infra_divs[] = {
23+ FACTOR(CLK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", "sysaxi_sel", 1, 2),
24+};
25+
26+static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
27+ "uart_sel" };
28+
29+static const char *const infra_spi_parents[] __initconst = { "i2c_sel",
30+ "spi_sel" };
31+
32+static const char *const infra_pwm_bsel_parents[] __initconst = {
33+ "top_rtc_32p7k", "csw_f26m_sel", "infra_sysaxi_d2", "pwm_sel"
34+};
35+
36+static const char *const infra_pcie_parents[] __initconst = {
37+ "top_rtc_32p7k", "csw_f26m_sel", "top_xtal", "pextp_tl_ck_sel"
38+};
39+
40+static const struct mtk_mux infra_muxes[] = {
41+ /* MODULE_CLK_SEL_0 */
42+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
43+ infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
44+ -1, -1, -1),
45+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
46+ infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
47+ -1, -1, -1),
48+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
49+ infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
50+ -1, -1, -1),
51+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
52+ infra_spi_parents, 0x0018, 0x0010, 0x0014, 4, 1,
53+ -1, -1, -1),
54+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
55+ infra_spi_parents, 0x0018, 0x0010, 0x0014, 5, 1,
56+ -1, -1, -1),
57+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
58+ infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 9,
59+ 2, -1, -1, -1),
60+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
61+ infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 11,
62+ 2, -1, -1, -1),
63+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
64+ infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
65+ 2, -1, -1, -1),
66+ /* MODULE_CLK_SEL_1 */
67+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
68+ infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
69+ -1, -1, -1),
70+};
71+
72+static const struct mtk_gate_regs infra0_cg_regs = {
73+ .set_ofs = 0x40,
74+ .clr_ofs = 0x44,
75+ .sta_ofs = 0x48,
76+};
77+
78+static const struct mtk_gate_regs infra1_cg_regs = {
79+ .set_ofs = 0x50,
80+ .clr_ofs = 0x54,
81+ .sta_ofs = 0x58,
82+};
83+
84+static const struct mtk_gate_regs infra2_cg_regs = {
85+ .set_ofs = 0x60,
86+ .clr_ofs = 0x64,
87+ .sta_ofs = 0x68,
88+};
89+
90+#define GATE_INFRA0(_id, _name, _parent, _shift) \
91+ { \
92+ .id = _id, .name = _name, .parent_name = _parent, \
93+ .regs = &infra0_cg_regs, .shift = _shift, \
94+ .ops = &mtk_clk_gate_ops_setclr, \
95+ }
96+
97+#define GATE_INFRA1(_id, _name, _parent, _shift) \
98+ { \
99+ .id = _id, .name = _name, .parent_name = _parent, \
100+ .regs = &infra1_cg_regs, .shift = _shift, \
101+ .ops = &mtk_clk_gate_ops_setclr, \
102+ }
103+
104+#define GATE_INFRA2(_id, _name, _parent, _shift) \
105+ { \
106+ .id = _id, .name = _name, .parent_name = _parent, \
107+ .regs = &infra2_cg_regs, .shift = _shift, \
108+ .ops = &mtk_clk_gate_ops_setclr, \
109+ }
110+
111+static const struct mtk_gate infra_clks[] = {
112+ /* INFRA0 */
113+ GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_sysaxi_d2", 0),
114+ GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_sysaxi_d2", 1),
115+ GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
116+ GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
117+ GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
118+ GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi_sel", 6),
119+ GATE_INFRA0(CLK_INFRA_EIP97_CK, "infra_eip97", "eip_b_sel", 7),
120+ GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi_sel", 8),
121+ GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
122+ GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l_sel", 10),
123+ GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys_sel", 11),
124+ GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner_sel", 13),
125+ GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
126+ 14),
127+ GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_sysaxi_d2", 15),
128+ GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_sysaxi_d2", 16),
129+ GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_sysaxi_d2", 24),
130+ GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
131+ GATE_INFRA0(CLK_INFRA_TRNG_CK, "infra_trng", "sysaxi_sel", 26),
132+ /* INFRA1 */
133+ GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
134+ GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_sel", 1),
135+ GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
136+ GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
137+ GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
138+ GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x_sel", 8),
139+ GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_sel", 9),
140+ GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_sysaxi_d2",
141+ 10),
142+ GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
143+ GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
144+ GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_sysaxi_d2",
145+ 13),
146+ GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_sysaxi_d2",
147+ 14),
148+ GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "top_rtc_32k", 15),
149+ GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_416m_sel", 16),
150+ GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_250m_sel",
151+ 17),
152+ GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi_sel",
153+ 18),
154+ GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "infra_sysaxi_d2",
155+ 19),
156+ GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "csw_f26m_sel", 20),
157+ GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m_sel", 21),
158+ GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x_sel", 23),
159+ /* INFRA2 */
160+ GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi_sel", 0),
161+ GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "infra_sysaxi_d2",
162+ 1),
163+ GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys_sel", 2),
164+ GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_sel", 3),
165+ GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl_ck_sel", 12),
166+ GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "top_xtal",
167+ 13),
168+ GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m_sel", 14),
169+ GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi_sel", 15),
170+};
171+
172+static int clk_mt7986_infracfg_probe(struct platform_device *pdev)
173+{
174+ struct clk_onecell_data *clk_data;
175+ struct device_node *node = pdev->dev.of_node;
176+ int r;
177+ void __iomem *base;
178+ int nr = ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) +
179+ ARRAY_SIZE(infra_clks);
180+
181+ base = of_iomap(node, 0);
182+ if (!base) {
183+ pr_err("%s(): ioremap failed\n", __func__);
184+ return -ENOMEM;
185+ }
186+
187+ clk_data = mtk_alloc_clk_data(nr);
188+
189+ if (!clk_data)
190+ return -ENOMEM;
191+
192+ mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
193+ mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
194+ &mt7986_clk_lock, clk_data);
195+ mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
196+ clk_data);
197+
198+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
199+ if (r) {
200+ pr_err("%s(): could not register clock provider: %d\n",
201+ __func__, r);
202+ goto free_infracfg_data;
203+ }
204+ return r;
205+
206+free_infracfg_data:
207+ mtk_free_clk_data(clk_data);
208+ return r;
209+
210+}
211+
212+static const struct of_device_id of_match_clk_mt7986_infracfg[] = {
213+ { .compatible = "mediatek,mt7986-infracfg", },
214+ {}
215+};
216+
217+static struct platform_driver clk_mt7986_infracfg_drv = {
218+ .probe = clk_mt7986_infracfg_probe,
219+ .driver = {
220+ .name = "clk-mt7986-infracfg",
221+ .of_match_table = of_match_clk_mt7986_infracfg,
222+ },
223+};
224+builtin_platform_driver(clk_mt7986_infracfg_drv);
drivers/clk/mediatek/clk-mt7986-topckgen.c+342−0
@@ -0,0 +1,342 @@
1+// SPDX-License-Identifier: GPL-1.0
2+/*
3+ * Copyright (c) 2021 MediaTek Inc.
4+ * Author: Sam Shih <sam.shih@mediatek.com>
5+ * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
6+ */
7+
8+#include <linux/clk-provider.h>
9+#include <linux/of.h>
10+#include <linux/of_address.h>
11+#include <linux/of_device.h>
12+#include <linux/platform_device.h>
13+#include "clk-mtk.h"
14+#include "clk-gate.h"
15+#include "clk-mux.h"
16+
17+#include <dt-bindings/clock/mt7986-clk.h>
18+#include <linux/clk.h>
19+
20+static DEFINE_SPINLOCK(mt7986_clk_lock);
21+
22+static const struct mtk_fixed_clk top_fixed_clks[] = {
23+ FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
24+ FIXED_CLK(CLK_TOP_JTAG, "top_jtag", "clkxtal", 50000000),
25+};
26+
27+static const struct mtk_fixed_factor top_divs[] = {
28+ /* XTAL */
29+ FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
30+ FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
31+ FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
32+ /* MPLL */
33+ FACTOR(CLK_TOP_MPLL_D2, "top_mpll_d2", "mpll", 1, 2),
34+ FACTOR(CLK_TOP_MPLL_D4, "top_mpll_d4", "mpll", 1, 4),
35+ FACTOR(CLK_TOP_MPLL_D8, "top_mpll_d8", "mpll", 1, 8),
36+ FACTOR(CLK_TOP_MPLL_D8_D2, "top_mpll_d8_d2", "mpll", 1, 16),
37+ FACTOR(CLK_TOP_MPLL_D3_D2, "top_mpll_d3_d2", "mpll", 1, 6),
38+ /* MMPLL */
39+ FACTOR(CLK_TOP_MMPLL_D2, "top_mmpll_d2", "mmpll", 1, 2),
40+ FACTOR(CLK_TOP_MMPLL_D4, "top_mmpll_d4", "mmpll", 1, 4),
41+ FACTOR(CLK_TOP_MMPLL_D8, "top_mmpll_d8", "mmpll", 1, 8),
42+ FACTOR(CLK_TOP_MMPLL_D8_D2, "top_mmpll_d8_d2", "mmpll", 1, 16),
43+ FACTOR(CLK_TOP_MMPLL_D3_D8, "top_mmpll_d3_d8", "mmpll", 1, 24),
44+ FACTOR(CLK_TOP_MMPLL_U2PHY, "top_mmpll_u2phy", "mmpll", 1, 30),
45+ /* APLL2 */
46+ FACTOR(CLK_TOP_APLL2_D4, "top_apll2_d4", "apll2", 1, 4),
47+ /* NET1PLL */
48+ FACTOR(CLK_TOP_NET1PLL_D4, "top_net1pll_d4", "net1pll", 1, 4),
49+ FACTOR(CLK_TOP_NET1PLL_D5, "top_net1pll_d5", "net1pll", 1, 5),
50+ FACTOR(CLK_TOP_NET1PLL_D5_D2, "top_net1pll_d5_d2", "net1pll", 1, 10),
51+ FACTOR(CLK_TOP_NET1PLL_D5_D4, "top_net1pll_d5_d4", "net1pll", 1, 20),
52+ FACTOR(CLK_TOP_NET1PLL_D8_D2, "top_net1pll_d8_d2", "net1pll", 1, 16),
53+ FACTOR(CLK_TOP_NET1PLL_D8_D4, "top_net1pll_d8_d4", "net1pll", 1, 32),
54+ /* NET2PLL */
55+ FACTOR(CLK_TOP_NET2PLL_D4, "top_net2pll_d4", "net2pll", 1, 4),
56+ FACTOR(CLK_TOP_NET2PLL_D4_D2, "top_net2pll_d4_d2", "net2pll", 1, 8),
57+ FACTOR(CLK_TOP_NET2PLL_D3_D2, "top_net2pll_d3_d2", "net2pll", 1, 2),
58+ /* WEDMCUPLL */
59+ FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "top_wedmcupll_d5_d2", "wedmcupll", 1,
60+ 10),
61+};
62+
63+static const char *const nfi1x_parents[] __initconst = { "top_xtal",
64+ "top_mmpll_d8",
65+ "top_net1pll_d8_d2",
66+ "top_net2pll_d3_d2",
67+ "top_mpll_d4",
68+ "top_mmpll_d8_d2",
69+ "top_wedmcupll_d5_d2",
70+ "top_mpll_d8" };
71+
72+static const char *const spinfi_parents[] __initconst = {
73+ "top_xtal_d2", "top_xtal", "top_net1pll_d5_d4",
74+ "top_mpll_d4", "top_mmpll_d8_d2", "top_wedmcupll_d5_d2",
75+ "top_mmpll_d3_d8", "top_mpll_d8"
76+};
77+
78+static const char *const spi_parents[] __initconst = {
79+ "top_xtal", "top_mpll_d2", "top_mmpll_d8",
80+ "top_net1pll_d8_d2", "top_net2pll_d3_d2", "top_net1pll_d5_d4",
81+ "top_mpll_d4", "top_wedmcupll_d5_d2"
82+};
83+
84+static const char *const uart_parents[] __initconst = { "top_xtal",
85+ "top_mpll_d8",
86+ "top_mpll_d8_d2" };
87+
88+static const char *const pwm_parents[] __initconst = {
89+ "top_xtal", "top_net1pll_d8_d2", "top_net1pll_d5_d4", "top_mpll_d4"
90+};
91+
92+static const char *const i2c_parents[] __initconst = {
93+ "top_xtal", "top_net1pll_d5_d4", "top_mpll_d4", "top_net1pll_d8_d4"
94+};
95+
96+static const char *const pextp_tl_ck_parents[] __initconst = {
97+ "top_xtal", "top_net1pll_d5_d4", "top_net2pll_d4_d2", "top_rtc_32k"
98+};
99+
100+static const char *const emmc_250m_parents[] __initconst = {
101+ "top_xtal", "top_net1pll_d5_d2"
102+};
103+
104+static const char *const emmc_416m_parents[] __initconst = { "top_xtal",
105+ "mpll" };
106+
107+static const char *const f_26m_adc_parents[] __initconst = { "top_xtal",
108+ "top_mpll_d8_d2" };
109+
110+static const char *const dramc_md32_parents[] __initconst = { "top_xtal",
111+ "top_mpll_d2" };
112+
113+static const char *const sysaxi_parents[] __initconst = { "top_xtal",
114+ "top_net1pll_d8_d2",
115+ "top_net2pll_d4" };
116+
117+static const char *const sysapb_parents[] __initconst = { "top_xtal",
118+ "top_mpll_d3_d2",
119+ "top_net2pll_d4_d2" };
120+
121+static const char *const arm_db_main_parents[] __initconst = {
122+ "top_xtal", "top_net2pll_d3_d2"
123+};
124+
125+static const char *const arm_db_jtsel_parents[] __initconst = { "top_jtag",
126+ "top_xtal" };
127+
128+static const char *const netsys_parents[] __initconst = { "top_xtal",
129+ "top_mmpll_d4" };
130+
131+static const char *const netsys_500m_parents[] __initconst = {
132+ "top_xtal", "top_net1pll_d5"
133+};
134+
135+static const char *const netsys_mcu_parents[] __initconst = {
136+ "top_xtal", "wedmcupll", "top_mmpll_d2", "top_net1pll_d4",
137+ "top_net1pll_d5"
138+};
139+
140+static const char *const netsys_2x_parents[] __initconst = {
141+ "top_xtal", "net2pll", "wedmcupll", "top_mmpll_d2"
142+};
143+
144+static const char *const sgm_325m_parents[] __initconst = { "top_xtal",
145+ "sgmpll" };
146+
147+static const char *const sgm_reg_parents[] __initconst = {
148+ "top_xtal", "top_net1pll_d8_d4"
149+};
150+
151+static const char *const a1sys_parents[] __initconst = { "top_xtal",
152+ "top_apll2_d4" };
153+
154+static const char *const conn_mcusys_parents[] __initconst = { "top_xtal",
155+ "top_mmpll_d2" };
156+
157+static const char *const eip_b_parents[] __initconst = { "top_xtal",
158+ "net2pll" };
159+
160+static const char *const aud_l_parents[] __initconst = { "top_xtal", "apll2",
161+ "top_mpll_d8_d2" };
162+
163+static const char *const a_tuner_parents[] __initconst = { "top_xtal",
164+ "top_apll2_d4",
165+ "top_mpll_d8_d2" };
166+
167+static const char *const u2u3_sys_parents[] __initconst = {
168+ "top_xtal", "top_net1pll_d5_d4"
169+};
170+
171+static const char *const da_u2_refsel_parents[] __initconst = {
172+ "top_xtal", "top_mmpll_u2phy"
173+};
174+
175+static const struct mtk_mux top_muxes[] = {
176+ /* CLK_CFG_0 */
177+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
178+ 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
179+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
180+ 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
181+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
182+ 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
183+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
184+ 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
185+ /* CLK_CFG_1 */
186+ MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
187+ 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
188+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
189+ 0x014, 0x018, 8, 2, 15, 0x1C0, 5),
190+ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
191+ 0x014, 0x018, 16, 2, 23, 0x1C0, 6),
192+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
193+ pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2,
194+ 31, 0x1C0, 7),
195+ /* CLK_CFG_2 */
196+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
197+ emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7,
198+ 0x1C0, 8),
199+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel",
200+ emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15,
201+ 0x1C0, 9),
202+ MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",
203+ f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23,
204+ 0x1C0, 10),
205+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents,
206+ 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11),
207+ /* CLK_CFG_3 */
208+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
209+ dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7,
210+ 0x1C0, 12),
211+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents,
212+ 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13),
213+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents,
214+ 0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14),
215+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
216+ arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1,
217+ 31, 0x1C0, 15),
218+ /* CLK_CFG_4 */
219+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel",
220+ arm_db_jtsel_parents, 0x040, 0x044, 0x048, 0, 1, 7,
221+ 0x1C0, 16),
222+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
223+ 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
224+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
225+ netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1,
226+ 23, 0x1C0, 18),
227+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
228+ netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
229+ 0x1C0, 19),
230+ /* CLK_CFG_5 */
231+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
232+ netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
233+ 0x1C0, 20),
234+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
235+ sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
236+ 0x1C0, 21),
237+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
238+ sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23,
239+ 0x1C0, 22),
240+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
241+ 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23),
242+ /* CLK_CFG_6 */
243+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel",
244+ conn_mcusys_parents, 0x060, 0x064, 0x068, 0, 1, 7,
245+ 0x1C0, 24),
246+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents,
247+ 0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25),
248+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel",
249+ f_26m_adc_parents, 0x060, 0x064, 0x068, 16, 1, 23,
250+ 0x1C0, 26),
251+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
252+ f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31,
253+ 0x1C0, 27),
254+ /* CLK_CFG_7 */
255+ MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel",
256+ f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7,
257+ 0x1C0, 28),
258+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
259+ 0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29),
260+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
261+ a_tuner_parents, 0x070, 0x074, 0x078, 16, 2, 23,
262+ 0x1C0, 30),
263+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents,
264+ 0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0),
265+ /* CLK_CFG_8 */
266+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
267+ u2u3_sys_parents, 0x080, 0x084, 0x088, 0, 1, 7,
268+ 0x1C4, 1),
269+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
270+ u2u3_sys_parents, 0x080, 0x084, 0x088, 8, 1, 15,
271+ 0x1C4, 2),
272+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel",
273+ da_u2_refsel_parents, 0x080, 0x084, 0x088, 16, 1,
274+ 23, 0x1C4, 3),
275+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel",
276+ da_u2_refsel_parents, 0x080, 0x084, 0x088, 24, 1,
277+ 31, 0x1C4, 4),
278+ /* CLK_CFG_9 */
279+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
280+ sgm_reg_parents, 0x090, 0x094, 0x098, 0, 1, 7,
281+ 0x1C4, 5),
282+};
283+
284+static int clk_mt7986_topckgen_probe(struct platform_device *pdev)
285+{
286+ struct clk_onecell_data *clk_data;
287+ struct device_node *node = pdev->dev.of_node;
288+ int r;
289+ void __iomem *base;
290+ int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) +
291+ ARRAY_SIZE(top_muxes);
292+
293+ base = of_iomap(node, 0);
294+ if (!base) {
295+ pr_err("%s(): ioremap failed\n", __func__);
296+ return -ENOMEM;
297+ }
298+
299+ clk_data = mtk_alloc_clk_data(nr);
300+ if (!clk_data)
301+ return -ENOMEM;
302+
303+ mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
304+ clk_data);
305+ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
306+ mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
307+ &mt7986_clk_lock, clk_data);
308+
309+ clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAXI_SEL]);
310+ clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAPB_SEL]);
311+ clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_SEL]);
312+ clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_MD32_SEL]);
313+ clk_prepare_enable(clk_data->clks[CLK_TOP_F26M_SEL]);
314+ clk_prepare_enable(clk_data->clks[CLK_TOP_SGM_REG_SEL]);
315+
316+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
317+
318+ if (r) {
319+ pr_err("%s(): could not register clock provider: %d\n",
320+ __func__, r);
321+ goto free_topckgen_data;
322+ }
323+ return r;
324+
325+free_topckgen_data:
326+ mtk_free_clk_data(clk_data);
327+ return r;
328+}
329+
330+static const struct of_device_id of_match_clk_mt7986_topckgen[] = {
331+ { .compatible = "mediatek,mt7986-topckgen", },
332+ {}
333+};
334+
335+static struct platform_driver clk_mt7986_topckgen_drv = {
336+ .probe = clk_mt7986_topckgen_probe,
337+ .driver = {
338+ .name = "clk-mt7986-topckgen",
339+ .of_match_table = of_match_clk_mt7986_topckgen,
340+ },
341+};
342+builtin_platform_driver(clk_mt7986_topckgen_drv);
drivers/clk/meson/gxbb.c+41−3
@@ -713,6 +713,35 @@ static struct clk_regmap gxbb_mpll_prediv = { · 712 unmodified lines
713713 };
714714
715715 static struct clk_regmap gxbb_mpll0_div = {
716+ .data = &(struct meson_clk_mpll_data){
717+ .sdm = {
718+ .reg_off = HHI_MPLL_CNTL7,
719+ .shift = 0,
720+ .width = 14,
721+ },
722+ .sdm_en = {
723+ .reg_off = HHI_MPLL_CNTL,
724+ .shift = 25,
725+ .width = 1,
726+ },
727+ .n2 = {
728+ .reg_off = HHI_MPLL_CNTL7,
729+ .shift = 16,
730+ .width = 9,
731+ },
732+ .lock = &meson_clk_lock,
733+ },
734+ .hw.init = &(struct clk_init_data){
735+ .name = "mpll0_div",
736+ .ops = &meson_clk_mpll_ops,
737+ .parent_hws = (const struct clk_hw *[]) {
738+ &gxbb_mpll_prediv.hw
739+ },
740+ .num_parents = 1,
741+ },
742+};
743+
744+static struct clk_regmap gxl_mpll0_div = {
716745 .data = &(struct meson_clk_mpll_data){
717746 .sdm = {
718747 .reg_off = HHI_MPLL_CNTL7,
@@ -749,7 +778,16 @@ static struct clk_regmap gxbb_mpll0 = { · 30 unmodified lines
749778 .hw.init = &(struct clk_init_data){
750779 .name = "mpll0",
751780 .ops = &clk_regmap_gate_ops,
752− .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll0_div.hw },
781+ .parent_data = &(const struct clk_parent_data) {
782+ /*
783+ * Note:
784+ * GXL and GXBB have different SDM_EN registers. We
785+ * fallback to the global naming string mechanism so
786+ * mpll0_div picks up the appropriate one.
787+ */
788+ .name = "mpll0_div",
789+ .index = -1,
790+ },
753791 .num_parents = 1,
754792 .flags = CLK_SET_RATE_PARENT,
755793 },
@@ -3044,7 +3082,7 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = { · 2288 unmodified lines
30443082 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
30453083 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
30463084 [CLKID_VAPB] = &gxbb_vapb.hw,
3047− [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
3085+ [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw,
30483086 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
30493087 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
30503088 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
@@ -3439,7 +3477,7 @@ static struct clk_regmap *const gxl_clk_regmaps[] = { · 388 unmodified lines
34393477 &gxbb_mpll0,
34403478 &gxbb_mpll1,
34413479 &gxbb_mpll2,
3442− &gxbb_mpll0_div,
3480+ &gxl_mpll0_div,
34433481 &gxbb_mpll1_div,
34443482 &gxbb_mpll2_div,
34453483 &gxbb_cts_amclk_div,
drivers/clk/qcom/Kconfig+24−0
@@ -265,6 +265,14 @@ config MSM_MMCC_8974 · 264 unmodified lines
265265 Say Y if you want to support multimedia devices such as display,
266266 graphics, video encode/decode, camera, etc.
267267
268+config MSM_GCC_8976
269+ tristate "MSM8956/76 Global Clock Controller"
270+ select QCOM_GDSC
271+ help
272+ Support for the global clock controller on msm8956/76 devices.
273+ Say Y if you want to use peripheral devices such as UART, SPI,
274+ i2c, USB, SD/eMMC, SATA, PCIe, etc.
275+
268276 config MSM_MMCC_8994
269277 tristate "MSM8994 Multimedia Clock Controller"
270278 select MSM_GCC_8994
@@ -564,6 +572,14 @@ config SM_CAMCC_8250 · 293 unmodified lines
564572 Support for the camera clock controller on SM8250 devices.
565573 Say Y if you want to support camera devices and camera functionality.
566574
575+config SDX_GCC_65
576+ tristate "SDX65 Global Clock Controller"
577+ select QCOM_GDSC
578+ help
579+ Support for the global clock controller on SDX65 devices.
580+ Say Y if you want to use peripheral devices such as UART,
581+ SPI, I2C, USB, SD/UFS, PCIe etc.
582+
567583 config SM_DISPCC_8250
568584 tristate "SM8150 and SM8250 Display Clock Controller"
569585 depends on SM_GCC_8150 || SM_GCC_8250
@@ -618,6 +634,14 @@ config SM_GCC_8350 · 48 unmodified lines
618634 Say Y if you want to use peripheral devices such as UART,
619635 SPI, I2C, USB, SD/UFS, PCIe etc.
620636
637+config SM_GCC_8450
638+ tristate "SM8450 Global Clock Controller"
639+ select QCOM_GDSC
640+ help
641+ Support for the global clock controller on SM8450 devices.
642+ Say Y if you want to use peripheral devices such as UART,
643+ SPI, I2C, USB, SD/UFS, PCIe etc.
644+
621645 config SM_GPUCC_8150
622646 tristate "SM8150 Graphics Clock Controller"
623647 select SM_GCC_8150
drivers/clk/qcom/Makefile+3−0
@@ -36,6 +36,7 @@ obj-$(CONFIG_MSM_GCC_8939) += gcc-msm8939.o · 35 unmodified lines
3636 obj-$(CONFIG_MSM_GCC_8953) += gcc-msm8953.o
3737 obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
3838 obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
39+obj-$(CONFIG_MSM_GCC_8976) += gcc-msm8976.o
3940 obj-$(CONFIG_MSM_GCC_8994) += gcc-msm8994.o
4041 obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
4142 obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
@@ -83,6 +84,7 @@ obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o · 41 unmodified lines
8384 obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
8485 obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o
8586 obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
87+obj-$(CONFIG_SDX_GCC_65) += gcc-sdx65.o
8688 obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
8789 obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o
8890 obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o
@@ -90,6 +92,7 @@ obj-$(CONFIG_SM_GCC_6350) += gcc-sm6350.o · 1 unmodified line
9092 obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
9193 obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
9294 obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o
95+obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o
9396 obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
9497 obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
9598 obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
drivers/clk/qcom/clk-alpha-pll.c+160−6
@@ -1,6 +1,7 @@
11 // SPDX-License-Identifier: GPL-2.0
22 /*
33 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
4+ * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
45 */
56
67 #include <linux/kernel.h>
@@ -139,6 +140,20 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { · 132 unmodified lines
139140 [PLL_OFF_OPMODE] = 0x28,
140141 [PLL_OFF_STATUS] = 0x38,
141142 },
143+ [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = {
144+ [PLL_OFF_OPMODE] = 0x04,
145+ [PLL_OFF_STATUS] = 0x0c,
146+ [PLL_OFF_L_VAL] = 0x10,
147+ [PLL_OFF_ALPHA_VAL] = 0x14,
148+ [PLL_OFF_USER_CTL] = 0x18,
149+ [PLL_OFF_USER_CTL_U] = 0x1c,
150+ [PLL_OFF_CONFIG_CTL] = 0x20,
151+ [PLL_OFF_CONFIG_CTL_U] = 0x24,
152+ [PLL_OFF_CONFIG_CTL_U1] = 0x28,
153+ [PLL_OFF_TEST_CTL] = 0x2c,
154+ [PLL_OFF_TEST_CTL_U] = 0x30,
155+ [PLL_OFF_TEST_CTL_U1] = 0x34,
156+ },
142157 };
143158 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
144159
@@ -175,6 +190,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); · 30 unmodified lines
175190 #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14)
176191 #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21)
177192
193+/* LUCID EVO PLL specific settings and offsets */
194+#define LUCID_EVO_ENABLE_VOTE_RUN BIT(25)
195+#define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0)
196+
178197 /* ZONDA PLL specific */
179198 #define ZONDA_PLL_OUT_MASK 0xf
180199 #define ZONDA_STAY_IN_CFA BIT(16)
@@ -204,7 +223,7 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, · 23 unmodified lines
204223 if (ret)
205224 return ret;
206225
207− for (count = 100; count > 0; count--) {
226+ for (count = 200; count > 0; count--) {
208227 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
209228 if (ret)
210229 return ret;
@@ -1750,24 +1769,32 @@ static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, · 1539 unmodified lines
17501769 LUCID_5LPE_ALPHA_PLL_ACK_LATCH);
17511770 }
17521771
1753−static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1754− unsigned long parent_rate)
1772+static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1773+ unsigned long parent_rate,
1774+ unsigned long enable_vote_run)
17551775 {
17561776 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1757− int i, val = 0, div, ret;
1777+ struct regmap *regmap = pll->clkr.regmap;
1778+ int i, val, div, ret;
17581779 u32 mask;
17591780
17601781 /*
17611782 * If the PLL is in FSM mode, then treat set_rate callback as a
17621783 * no-operation.
17631784 */
1764− ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1785+ ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
17651786 if (ret)
17661787 return ret;
17671788
1768− if (val & LUCID_5LPE_ENABLE_VOTE_RUN)
1789+ if (val & enable_vote_run)
17691790 return 0;
17701791
1792+ if (!pll->post_div_table) {
1793+ pr_err("Missing the post_div_table for the %s PLL\n",
1794+ clk_hw_get_name(&pll->clkr.hw));
1795+ return -EINVAL;
1796+ }
1797+
17711798 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
17721799 for (i = 0; i < pll->num_post_div; i++) {
17731800 if (pll->post_div_table[i].div == div) {
@@ -1781,6 +1808,12 @@ static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long · 7 unmodified lines
17811808 mask, val << pll->post_div_shift);
17821809 }
17831810
1811+static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1812+ unsigned long parent_rate)
1813+{
1814+ return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN);
1815+}
1816+
17841817 const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = {
17851818 .prepare = alpha_pll_lucid_5lpe_prepare,
17861819 .enable = alpha_pll_lucid_5lpe_enable,
@@ -1960,3 +1993,124 @@ const struct clk_ops clk_alpha_pll_zonda_ops = { · 173 unmodified lines
19601993 .set_rate = clk_zonda_pll_set_rate,
19611994 };
19621995 EXPORT_SYMBOL(clk_alpha_pll_zonda_ops);
1996+
1997+static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)
1998+{
1999+ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2000+ struct regmap *regmap = pll->clkr.regmap;
2001+ u32 val;
2002+ int ret;
2003+
2004+ ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2005+ if (ret)
2006+ return ret;
2007+
2008+ /* If in FSM mode, just vote for it */
2009+ if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2010+ ret = clk_enable_regmap(hw);
2011+ if (ret)
2012+ return ret;
2013+ return wait_for_pll_enable_lock(pll);
2014+ }
2015+
2016+ /* Check if PLL is already enabled */
2017+ ret = trion_pll_is_enabled(pll, regmap);
2018+ if (ret < 0) {
2019+ return ret;
2020+ } else if (ret) {
2021+ pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw));
2022+ return 0;
2023+ }
2024+
2025+ ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2026+ if (ret)
2027+ return ret;
2028+
2029+ /* Set operation mode to RUN */
2030+ regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
2031+
2032+ ret = wait_for_pll_enable_lock(pll);
2033+ if (ret)
2034+ return ret;
2035+
2036+ /* Enable the PLL outputs */
2037+ ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
2038+ if (ret)
2039+ return ret;
2040+
2041+ /* Enable the global PLL outputs */
2042+ ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2043+ if (ret)
2044+ return ret;
2045+
2046+ /* Ensure that the write above goes through before returning. */
2047+ mb();
2048+ return ret;
2049+}
2050+
2051+static void alpha_pll_lucid_evo_disable(struct clk_hw *hw)
2052+{
2053+ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2054+ struct regmap *regmap = pll->clkr.regmap;
2055+ u32 val;
2056+ int ret;
2057+
2058+ ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2059+ if (ret)
2060+ return;
2061+
2062+ /* If in FSM mode, just unvote it */
2063+ if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2064+ clk_disable_regmap(hw);
2065+ return;
2066+ }
2067+
2068+ /* Disable the global PLL output */
2069+ ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2070+ if (ret)
2071+ return;
2072+
2073+ /* Disable the PLL outputs */
2074+ ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
2075+ if (ret)
2076+ return;
2077+
2078+ /* Place the PLL mode in STANDBY */
2079+ regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2080+}
2081+
2082+static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw,
2083+ unsigned long parent_rate)
2084+{
2085+ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2086+ struct regmap *regmap = pll->clkr.regmap;
2087+ u32 l, frac;
2088+
2089+ regmap_read(regmap, PLL_L_VAL(pll), &l);
2090+ l &= LUCID_EVO_PLL_L_VAL_MASK;
2091+ regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
2092+
2093+ return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll));
2094+}
2095+
2096+static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
2097+ unsigned long parent_rate)
2098+{
2099+ return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN);
2100+}
2101+
2102+const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = {
2103+ .enable = alpha_pll_lucid_evo_enable,
2104+ .disable = alpha_pll_lucid_evo_disable,
2105+ .is_enabled = clk_trion_pll_is_enabled,
2106+ .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2107+ .round_rate = clk_alpha_pll_round_rate,
2108+};
2109+EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops);
2110+
2111+const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = {
2112+ .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
2113+ .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
2114+ .set_rate = clk_lucid_evo_pll_postdiv_set_rate,
2115+};
2116+EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops);
drivers/clk/qcom/clk-alpha-pll.h+3−0
@@ -17,6 +17,7 @@ enum { · 16 unmodified lines
1717 CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
1818 CLK_ALPHA_PLL_TYPE_AGERA,
1919 CLK_ALPHA_PLL_TYPE_ZONDA,
20+ CLK_ALPHA_PLL_TYPE_LUCID_EVO,
2021 CLK_ALPHA_PLL_TYPE_MAX,
2122 };
2223
@@ -151,6 +152,8 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops; · 128 unmodified lines
151152
152153 extern const struct clk_ops clk_alpha_pll_zonda_ops;
153154 #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops
155+extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
156+extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
154157
155158 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
156159 const struct alpha_pll_config *config);
drivers/clk/qcom/clk-rpmh.c+52−0
@@ -515,6 +515,32 @@ static const struct clk_rpmh_desc clk_rpmh_sm8350 = { · 514 unmodified lines
515515 /* Resource name must match resource id present in cmd-db */
516516 DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 4);
517517
518+DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4);
519+DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 4);
520+
521+static struct clk_hw *sm8450_rpmh_clocks[] = {
522+ [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
523+ [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
524+ [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1.hw,
525+ [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_ao.hw,
526+ [RPMH_LN_BB_CLK2] = &sm8450_ln_bb_clk2.hw,
527+ [RPMH_LN_BB_CLK2_A] = &sm8450_ln_bb_clk2_ao.hw,
528+ [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
529+ [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
530+ [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
531+ [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
532+ [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
533+ [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
534+ [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw,
535+ [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw,
536+ [RPMH_IPA_CLK] = &sdm845_ipa.hw,
537+};
538+
539+static const struct clk_rpmh_desc clk_rpmh_sm8450 = {
540+ .clks = sm8450_rpmh_clocks,
541+ .num_clks = ARRAY_SIZE(sm8450_rpmh_clocks),
542+};
543+
518544 static struct clk_hw *sc7280_rpmh_clocks[] = {
519545 [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
520546 [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
@@ -556,6 +582,30 @@ static const struct clk_rpmh_desc clk_rpmh_sm6350 = { · 35 unmodified lines
556582 .num_clks = ARRAY_SIZE(sm6350_rpmh_clocks),
557583 };
558584
585+DEFINE_CLK_RPMH_VRM(sdx65, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4);
586+
587+static struct clk_hw *sdx65_rpmh_clocks[] = {
588+ [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
589+ [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
590+ [RPMH_LN_BB_CLK1] = &sdx65_ln_bb_clk1.hw,
591+ [RPMH_LN_BB_CLK1_A] = &sdx65_ln_bb_clk1_ao.hw,
592+ [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
593+ [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
594+ [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
595+ [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
596+ [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
597+ [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
598+ [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw,
599+ [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw,
600+ [RPMH_IPA_CLK] = &sdm845_ipa.hw,
601+ [RPMH_QPIC_CLK] = &sdx55_qpic_clk.hw,
602+};
603+
604+static const struct clk_rpmh_desc clk_rpmh_sdx65 = {
605+ .clks = sdx65_rpmh_clocks,
606+ .num_clks = ARRAY_SIZE(sdx65_rpmh_clocks),
607+};
608+
559609 static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
560610 void *data)
561611 {
@@ -643,10 +693,12 @@ static const struct of_device_id clk_rpmh_match_table[] = { · 81 unmodified lines
643693 { .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x},
644694 { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
645695 { .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55},
696+ { .compatible = "qcom,sdx65-rpmh-clk", .data = &clk_rpmh_sdx65},
646697 { .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350},
647698 { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
648699 { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
649700 { .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350},
701+ { .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450},
650702 { .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280},
651703 { }
652704 };
drivers/clk/qcom/clk-smd-rpm.c+4−27
@@ -17,7 +17,6 @@ · 16 unmodified lines
1717 #include <linux/soc/qcom/smd-rpm.h>
1818
1919 #include <dt-bindings/clock/qcom,rpmcc.h>
20−#include <dt-bindings/mfd/qcom-rpm.h>
2120
2221 #define QCOM_RPM_KEY_SOFTWARE_ENABLE 0x6e657773
2322 #define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY 0x62636370
@@ -151,12 +150,6 @@ struct clk_smd_rpm_req { · 127 unmodified lines
151150 __le32 value;
152151 };
153152
154−struct rpm_cc {
155− struct qcom_rpm *rpm;
156− struct clk_smd_rpm **clks;
157− size_t num_clks;
158−};
159−
160153 struct rpm_smd_clk_desc {
161154 struct clk_smd_rpm **clks;
162155 size_t num_clks;
@@ -196,10 +189,6 @@ static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r, · 33 unmodified lines
196189 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
197190 };
198191
199− /* Buffered clock needs a binary value */
200− if (r->rpm_res_type == QCOM_SMD_RPM_CLK_BUF_A)
201− req.value = cpu_to_le32(!!req.value);
202−
203192 return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
204193 r->rpm_res_type, r->rpm_clk_id, &req,
205194 sizeof(req));
@@ -214,10 +203,6 @@ static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r, · 8 unmodified lines
214203 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
215204 };
216205
217− /* Buffered clock needs a binary value */
218− if (r->rpm_res_type == QCOM_SMD_RPM_CLK_BUF_A)
219− req.value = cpu_to_le32(!!req.value);
220−
221206 return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
222207 r->rpm_res_type, r->rpm_clk_id, &req,
223208 sizeof(req));
@@ -1159,20 +1144,19 @@ MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table); · 935 unmodified lines
11591144 static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec,
11601145 void *data)
11611146 {
1162− struct rpm_cc *rcc = data;
1147+ const struct rpm_smd_clk_desc *desc = data;
11631148 unsigned int idx = clkspec->args[0];
11641149
1165− if (idx >= rcc->num_clks) {
1150+ if (idx >= desc->num_clks) {
11661151 pr_err("%s: invalid index %u\n", __func__, idx);
11671152 return ERR_PTR(-EINVAL);
11681153 }
11691154
1170− return rcc->clks[idx] ? &rcc->clks[idx]->hw : ERR_PTR(-ENOENT);
1155+ return desc->clks[idx] ? &desc->clks[idx]->hw : ERR_PTR(-ENOENT);
11711156 }
11721157
11731158 static int rpm_smd_clk_probe(struct platform_device *pdev)
11741159 {
1175− struct rpm_cc *rcc;
11761160 int ret;
11771161 size_t num_clks, i;
11781162 struct qcom_smd_rpm *rpm;
@@ -1192,13 +1176,6 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) · 13 unmodified lines
11921176 rpm_smd_clks = desc->clks;
11931177 num_clks = desc->num_clks;
11941178
1195− rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc), GFP_KERNEL);
1196− if (!rcc)
1197− return -ENOMEM;
1198−
1199− rcc->clks = rpm_smd_clks;
1200− rcc->num_clks = num_clks;
1201−
12021179 for (i = 0; i < num_clks; i++) {
12031180 if (!rpm_smd_clks[i])
12041181 continue;
@@ -1224,7 +1201,7 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) · 19 unmodified lines
12241201 }
12251202
12261203 ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_smdrpm_clk_hw_get,
1227− rcc);
1204+ (void *)desc);
12281205 if (ret)
12291206 goto err;
12301207
drivers/clk/qcom/gcc-msm8976.c+4155−0
@@ -0,0 +1,4155 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Qualcomm Global Clock Controller driver for MSM8956/76
4+ *
5+ * Copyright (c) 2016-2021, AngeloGioacchino Del Regno
6+ * <angelogioacchino.delregno@somainline.org>
7+ *
8+ * Driver cleanup and modernization
9+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
10+ * Marijn Suijten <marijn.suijten@somainline.org>
11+ *
12+ */
13+
14+#include <linux/clk-provider.h>
15+#include <linux/err.h>
16+#include <linux/kernel.h>
17+#include <linux/module.h>
18+#include <linux/of_device.h>
19+#include <linux/of.h>
20+#include <linux/regmap.h>
21+
22+#include <dt-bindings/clock/qcom,gcc-msm8976.h>
23+
24+#include "clk-pll.h"
25+#include "clk-branch.h"
26+#include "clk-rcg.h"
27+#include "common.h"
28+#include "gdsc.h"
29+#include "reset.h"
30+
31+enum {
32+ P_GPLL0_OUT_MAIN,
33+ P_GPLL0_AUX,
34+ P_GPLL0_OUT,
35+ P_GPLL0_OUT_M,
36+ P_GPLL0_OUT_MDP,
37+ P_GPLL2_AUX,
38+ P_GPLL2_OUT,
39+ P_GPLL4_OUT_MAIN,
40+ P_GPLL4_AUX,
41+ P_GPLL4_OUT,
42+ P_GPLL4_GFX3D,
43+ P_GPLL6_OUT_MAIN,
44+ P_GPLL6_AUX,
45+ P_GPLL6_OUT,
46+ P_GPLL6_GFX3D,
47+ P_DSI0PLL,
48+ P_DSI1PLL,
49+ P_DSI0PLL_BYTE,
50+ P_DSI1PLL_BYTE,
51+ P_XO_A,
52+ P_XO,
53+};
54+
55+static struct clk_pll gpll0 = {
56+ .l_reg = 0x21004,
57+ .m_reg = 0x21008,
58+ .n_reg = 0x2100c,
59+ .config_reg = 0x21014,
60+ .mode_reg = 0x21000,
61+ .status_reg = 0x2101c,
62+ .status_bit = 17,
63+ .clkr.hw.init = &(struct clk_init_data){
64+ .name = "gpll0",
65+ .parent_data = &(const struct clk_parent_data){
66+ .fw_name = "xo",
67+ },
68+ .num_parents = 1,
69+ .ops = &clk_pll_ops,
70+ },
71+};
72+
73+static struct clk_regmap gpll0_vote = {
74+ .enable_reg = 0x45000,
75+ .enable_mask = BIT(0),
76+ .hw.init = &(struct clk_init_data){
77+ .name = "gpll0_vote",
78+ .parent_hws = (const struct clk_hw *[]) {
79+ &gpll0.clkr.hw,
80+ },
81+ .num_parents = 1,
82+ /* This clock is required for other ones to function. */
83+ .flags = CLK_IS_CRITICAL,
84+ .ops = &clk_pll_vote_ops,
85+ },
86+};
87+
88+static struct clk_pll gpll2 = {
89+ .l_reg = 0x4a004,
90+ .m_reg = 0x4a008,
91+ .n_reg = 0x4a00c,
92+ .config_reg = 0x4a014,
93+ .mode_reg = 0x4a000,
94+ .status_reg = 0x4a01c,
95+ .status_bit = 17,
96+ .clkr.hw.init = &(struct clk_init_data){
97+ .name = "gpll2",
98+ .parent_data = &(const struct clk_parent_data){
99+ .fw_name = "xo",
100+ },
101+ .num_parents = 1,
102+ .ops = &clk_pll_ops,
103+ },
104+};
105+
106+static struct clk_regmap gpll2_vote = {
107+ .enable_reg = 0x45000,
108+ .enable_mask = BIT(2),
109+ .hw.init = &(struct clk_init_data){
110+ .name = "gpll2_vote",
111+ .parent_hws = (const struct clk_hw *[]) {
112+ &gpll2.clkr.hw,
113+ },
114+ .num_parents = 1,
115+ .ops = &clk_pll_vote_ops,
116+ },
117+};
118+
119+static const struct pll_freq_tbl gpll3_freq_tbl[] = {
120+ { 1100000000, 57, 7, 24, 0 },
121+ { }
122+};
123+
124+static struct clk_pll gpll3 = {
125+ .l_reg = 0x22004,
126+ .m_reg = 0x22008,
127+ .n_reg = 0x2200c,
128+ .config_reg = 0x22010,
129+ .mode_reg = 0x22000,
130+ .status_reg = 0x22024,
131+ .status_bit = 17,
132+ .freq_tbl = gpll3_freq_tbl,
133+ .clkr.hw.init = &(struct clk_init_data) {
134+ .name = "gpll3",
135+ .parent_data = &(const struct clk_parent_data){
136+ .fw_name = "xo",
137+ },
138+ .num_parents = 1,
139+ .ops = &clk_pll_ops,
140+ },
141+};
142+
143+static struct clk_regmap gpll3_vote = {
144+ .enable_reg = 0x45000,
145+ .enable_mask = BIT(4),
146+ .hw.init = &(struct clk_init_data){
147+ .name = "gpll3_vote",
148+ .parent_hws = (const struct clk_hw *[]) {
149+ &gpll3.clkr.hw,
150+ },
151+ .num_parents = 1,
152+ .ops = &clk_pll_vote_ops,
153+ },
154+};
155+
156+/* GPLL3 at 1100MHz, main output enabled. */
157+static const struct pll_config gpll3_config = {
158+ .l = 57,
159+ .m = 7,
160+ .n = 24,
161+ .vco_val = 0x0,
162+ .vco_mask = 0x3 << 20,
163+ .pre_div_val = 0x0,
164+ .pre_div_mask = 0x7 << 12,
165+ .post_div_val = 0x0,
166+ .post_div_mask = 0x3 << 8,
167+ .mn_ena_mask = BIT(24),
168+ .main_output_mask = BIT(0),
169+ .aux_output_mask = BIT(1),
170+};
171+
172+static struct clk_pll gpll4 = {
173+ .l_reg = 0x24004,
174+ .m_reg = 0x24008,
175+ .n_reg = 0x2400c,
176+ .config_reg = 0x24018,
177+ .mode_reg = 0x24000,
178+ .status_reg = 0x24024,
179+ .status_bit = 17,
180+ .clkr.hw.init = &(struct clk_init_data){
181+ .name = "gpll4",
182+ .parent_data = &(const struct clk_parent_data){
183+ .fw_name = "xo",
184+ },
185+ .num_parents = 1,
186+ .ops = &clk_pll_ops,
187+ },
188+};
189+
190+static struct clk_regmap gpll4_vote = {
191+ .enable_reg = 0x45000,
192+ .enable_mask = BIT(5),
193+ .hw.init = &(struct clk_init_data){
194+ .name = "gpll4_vote",
195+ .parent_hws = (const struct clk_hw *[]) {
196+ &gpll4.clkr.hw,
197+ },
198+ .num_parents = 1,
199+ .ops = &clk_pll_vote_ops,
200+ },
201+};
202+
203+static struct clk_pll gpll6 = {
204+ .mode_reg = 0x37000,
205+ .l_reg = 0x37004,
206+ .m_reg = 0x37008,
207+ .n_reg = 0x3700c,
208+ .config_reg = 0x37014,
209+ .status_reg = 0x3701c,
210+ .status_bit = 17,
211+ .clkr.hw.init = &(struct clk_init_data){
212+ .name = "gpll6",
213+ .parent_data = &(const struct clk_parent_data){
214+ .fw_name = "xo",
215+ },
216+ .num_parents = 1,
217+ .ops = &clk_pll_ops,
218+ },
219+};
220+
221+static struct clk_regmap gpll6_vote = {
222+ .enable_reg = 0x45000,
223+ .enable_mask = BIT(7),
224+ .hw.init = &(struct clk_init_data){
225+ .name = "gpll6_vote",
226+ .parent_hws = (const struct clk_hw *[]) {
227+ &gpll6.clkr.hw,
228+ },
229+ .num_parents = 1,
230+ .ops = &clk_pll_vote_ops,
231+ },
232+};
233+
234+static const struct parent_map gcc_parent_map_1[] = {
235+ { P_XO, 0 },
236+ { P_GPLL0_OUT_MAIN, 1 },
237+ { P_GPLL4_OUT, 2 },
238+};
239+
240+static const struct clk_parent_data gcc_parent_data_1[] = {
241+ { .fw_name = "xo" },
242+ { .hw = &gpll0_vote.hw },
243+ { .hw = &gpll4_vote.hw },
244+};
245+
246+static const struct parent_map gcc_parent_map_v1_1[] = {
247+ { P_XO, 0 },
248+ { P_GPLL0_OUT_MAIN, 1 },
249+ { P_GPLL2_OUT, 4 },
250+};
251+
252+static const struct clk_parent_data gcc_parent_data_v1_1[] = {
253+ { .fw_name = "xo" },
254+ { .hw = &gpll0_vote.hw },
255+ { .hw = &gpll2_vote.hw },
256+};
257+
258+static const struct parent_map gcc_parent_map_2[] = {
259+ { P_XO, 0 },
260+ { P_GPLL0_OUT_MAIN, 1 },
261+ { P_GPLL2_AUX, 3 },
262+ { P_GPLL4_OUT, 2 },
263+};
264+
265+static const struct clk_parent_data gcc_parent_data_2[] = {
266+ { .fw_name = "xo" },
267+ { .hw = &gpll0_vote.hw },
268+ { .hw = &gpll2_vote.hw },
269+ { .hw = &gpll4_vote.hw },
270+};
271+
272+static const struct parent_map gcc_parent_map_3[] = {
273+ { P_XO, 0 },
274+ { P_GPLL0_OUT_MAIN, 1 },
275+ { P_GPLL2_AUX, 3 },
276+ { P_GPLL6_AUX, 2 },
277+};
278+
279+static const struct clk_parent_data gcc_parent_data_3[] = {
280+ { .fw_name = "xo" },
281+ { .hw = &gpll0_vote.hw },
282+ { .hw = &gpll2_vote.hw },
283+ { .hw = &gpll6_vote.hw },
284+};
285+
286+static const struct parent_map gcc_parent_map_4[] = {
287+ { P_XO, 0 },
288+ { P_GPLL0_OUT_MAIN, 1 },
289+};
290+
291+static const struct parent_map gcc_parent_map_4_fs[] = {
292+ { P_XO, 0 },
293+ { P_GPLL0_OUT, 2 },
294+};
295+
296+static const struct parent_map gcc_parent_map_5[] = {
297+ { P_XO, 0 },
298+ { P_GPLL4_OUT, 2 },
299+ { P_GPLL6_OUT_MAIN, 1 },
300+};
301+
302+static const struct clk_parent_data gcc_parent_data_5[] = {
303+ { .fw_name = "xo" },
304+ { .hw = &gpll4_vote.hw },
305+ { .hw = &gpll6_vote.hw },
306+};
307+
308+static const struct parent_map gcc_parent_map_6[] = {
309+ { P_XO, 0 },
310+ { P_GPLL0_OUT_MAIN, 1 },
311+ { P_GPLL4_OUT_MAIN, 5 },
312+};
313+
314+static const struct clk_parent_data gcc_parent_data_6[] = {
315+ { .fw_name = "xo" },
316+ { .hw = &gpll0_vote.hw },
317+ { .hw = &gpll4_vote.hw },
318+};
319+
320+static const struct parent_map gcc_parent_map_7_mdp[] = {
321+ { P_XO, 0 },
322+ { P_GPLL6_OUT, 3 },
323+ { P_GPLL0_OUT_MDP, 6 },
324+};
325+
326+static const struct clk_parent_data gcc_parent_data_7_mdp[] = {
327+ { .fw_name = "xo" },
328+ { .hw = &gpll6_vote.hw },
329+ { .hw = &gpll0_vote.hw },
330+};
331+
332+static const struct parent_map gcc_parent_map_7[] = {
333+ { P_GPLL0_OUT_MAIN, 1 },
334+ { P_GPLL6_OUT, 3 },
335+};
336+
337+static const struct clk_parent_data gcc_parent_data_7[] = {
338+ { .hw = &gpll0_vote.hw },
339+ { .hw = &gpll6_vote.hw },
340+};
341+
342+static const struct parent_map gcc_parent_map_8[] = {
343+ { P_XO, 0 },
344+ { P_GPLL0_OUT_MAIN, 1 },
345+};
346+
347+static const struct clk_parent_data gcc_parent_data_4_8[] = {
348+ { .fw_name = "xo" },
349+ { .hw = &gpll0_vote.hw },
350+};
351+
352+static const struct parent_map gcc_parent_map_8_a[] = {
353+ { P_XO_A, 0 },
354+ { P_GPLL0_OUT_MAIN, 1 },
355+};
356+
357+static const struct clk_parent_data gcc_parent_data_8_a[] = {
358+ { .fw_name = "xo_a" },
359+ { .hw = &gpll0_vote.hw },
360+};
361+
362+static const struct parent_map gcc_parent_map_8_gp[] = {
363+ { P_GPLL0_OUT_MAIN, 1 },
364+};
365+
366+static const struct clk_parent_data gcc_parent_data_8_gp[] = {
367+ { .hw = &gpll0_vote.hw },
368+};
369+
370+static const struct parent_map gcc_parent_map_9[] = {
371+ { P_XO, 0 },
372+ { P_GPLL6_OUT_MAIN, 6 },
373+};
374+
375+static const struct clk_parent_data gcc_parent_data_9[] = {
376+ { .fw_name = "xo" },
377+ { .hw = &gpll6_vote.hw },
378+};
379+
380+static const struct parent_map gcc_parent_map_10[] = {
381+ { P_XO, 0 },
382+};
383+
384+static const struct clk_parent_data gcc_parent_data_10[] = {
385+ { .fw_name = "xo" },
386+};
387+
388+static const struct parent_map gcc_parent_map_sdcc_ice[] = {
389+ { P_XO, 0 },
390+ { P_GPLL0_OUT_M, 3 },
391+};
392+
393+static const struct parent_map gcc_parent_map_cci[] = {
394+ { P_XO, 0 },
395+ { P_GPLL0_AUX, 2 },
396+};
397+
398+static const struct parent_map gcc_parent_map_cpp[] = {
399+ { P_XO, 0 },
400+ { P_GPLL0_OUT_MAIN, 1 },
401+ { P_GPLL4_AUX, 3 },
402+};
403+
404+static const struct parent_map gcc_parent_map_mdss_pix0[] = {
405+ { P_XO, 0 },
406+ { P_DSI0PLL, 1 },
407+};
408+
409+static const struct clk_parent_data gcc_parent_data_mdss_pix0[] = {
410+ { .fw_name = "xo" },
411+ { .fw_name = "dsi0pll" },
412+};
413+
414+static const struct parent_map gcc_parent_map_mdss_pix1[] = {
415+ { P_XO, 0 },
416+ { P_DSI0PLL, 3 },
417+ { P_DSI1PLL, 1 },
418+};
419+
420+static const struct clk_parent_data gcc_parent_data_mdss_pix1[] = {
421+ { .fw_name = "xo" },
422+ { .fw_name = "dsi0pll" },
423+ { .fw_name = "dsi1pll" },
424+};
425+
426+static const struct parent_map gcc_parent_map_mdss_byte0[] = {
427+ { P_XO, 0 },
428+ { P_DSI0PLL_BYTE, 1 },
429+};
430+
431+static const struct clk_parent_data gcc_parent_data_mdss_byte0[] = {
432+ { .fw_name = "xo" },
433+ { .fw_name = "dsi0pllbyte" },
434+};
435+
436+static const struct parent_map gcc_parent_map_mdss_byte1[] = {
437+ { P_XO, 0 },
438+ { P_DSI0PLL_BYTE, 3 },
439+ { P_DSI1PLL_BYTE, 1 },
440+};
441+
442+static const struct clk_parent_data gcc_parent_data_mdss_byte1[] = {
443+ { .fw_name = "xo" },
444+ { .fw_name = "dsi0pllbyte" },
445+ { .fw_name = "dsi1pllbyte" },
446+};
447+
448+static const struct parent_map gcc_parent_map_gfx3d[] = {
449+ { P_XO, 0 },
450+ { P_GPLL0_OUT_MAIN, 1 },
451+ { P_GPLL4_GFX3D, 5 },
452+ { P_GPLL6_GFX3D, 3 },
453+};
454+
455+static const struct clk_parent_data gcc_parent_data_gfx3d[] = {
456+ { .fw_name = "xo" },
457+ { .hw = &gpll0_vote.hw },
458+ { .hw = &gpll4_vote.hw },
459+ { .hw = &gpll6_vote.hw },
460+};
461+
462+static const struct freq_tbl ftbl_aps_0_clk_src[] = {
463+ F(19200000, P_XO, 1, 0, 0),
464+ F(300000000, P_GPLL4_OUT, 4, 0, 0),
465+ F(540000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
466+ { }
467+};
468+
469+static struct clk_rcg2 aps_0_clk_src = {
470+ .cmd_rcgr = 0x78008,
471+ .hid_width = 5,
472+ .parent_map = gcc_parent_map_5,
473+ .freq_tbl = ftbl_aps_0_clk_src,
474+ .clkr.hw.init = &(struct clk_init_data){
475+ .name = "aps_0_clk_src",
476+ .parent_data = gcc_parent_data_5,
477+ .num_parents = ARRAY_SIZE(gcc_parent_data_5),
478+ .ops = &clk_rcg2_ops,
479+ },
480+};
481+
482+static const struct freq_tbl ftbl_aps_1_clk_src[] = {
483+ F(19200000, P_XO, 1, 0, 0),
484+ F(300000000, P_GPLL4_OUT, 4, 0, 0),
485+ F(540000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
486+ { }
487+};
488+
489+static struct clk_rcg2 aps_1_clk_src = {
490+ .cmd_rcgr = 0x79008,
491+ .hid_width = 5,
492+ .parent_map = gcc_parent_map_5,
493+ .freq_tbl = ftbl_aps_1_clk_src,
494+ .clkr.hw.init = &(struct clk_init_data){
495+ .name = "aps_1_clk_src",
496+ .parent_data = gcc_parent_data_5,
497+ .num_parents = ARRAY_SIZE(gcc_parent_data_5),
498+ .ops = &clk_rcg2_ops,
499+ },
500+};
501+
502+static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
503+ F(19200000, P_XO_A, 1, 0, 0),
504+ F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
505+ F(88890000, P_GPLL0_OUT_MAIN, 9, 0, 0),
506+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
507+ { }
508+};
509+
510+static struct clk_rcg2 apss_ahb_clk_src = {
511+ .cmd_rcgr = 0x46000,
512+ .hid_width = 5,
513+ .parent_map = gcc_parent_map_8_a,
514+ .freq_tbl = ftbl_apss_ahb_clk_src,
515+ .clkr.hw.init = &(struct clk_init_data){
516+ .name = "apss_ahb_clk_src",
517+ .parent_data = gcc_parent_data_8_a,
518+ .num_parents = ARRAY_SIZE(gcc_parent_data_8_a),
519+ .ops = &clk_rcg2_ops,
520+ /*
521+ * This clock allows the CPUs to communicate with
522+ * the rest of the SoC. Without it, the brain will
523+ * operate without the rest of the body.
524+ */
525+ .flags = CLK_IS_CRITICAL,
526+ },
527+};
528+
529+static const struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
530+ F(19200000, P_XO, 1, 0, 0),
531+ F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
532+ { }
533+};
534+
535+static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
536+ .cmd_rcgr = 0x200c,
537+ .hid_width = 5,
538+ .parent_map = gcc_parent_map_8,
539+ .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
540+ .clkr.hw.init = &(struct clk_init_data){
541+ .name = "blsp1_qup1_i2c_apps_clk_src",
542+ .parent_data = gcc_parent_data_4_8,
543+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
544+ .ops = &clk_rcg2_ops,
545+ },
546+};
547+
548+static const struct freq_tbl ftbl_blsp_spi_apps_clk_src[] = {
549+ F(960000, P_XO, 10, 1, 2),
550+ F(4800000, P_XO, 4, 0, 0),
551+ F(9600000, P_XO, 2, 0, 0),
552+ F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
553+ F(19200000, P_XO, 1, 0, 0),
554+ F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
555+ F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
556+ { }
557+};
558+
559+static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
560+ .cmd_rcgr = 0x2024,
561+ .mnd_width = 8,
562+ .hid_width = 5,
563+ .parent_map = gcc_parent_map_8,
564+ .freq_tbl = ftbl_blsp_spi_apps_clk_src,
565+ .clkr.hw.init = &(struct clk_init_data){
566+ .name = "blsp1_qup1_spi_apps_clk_src",
567+ .parent_data = gcc_parent_data_4_8,
568+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
569+ .ops = &clk_rcg2_ops,
570+ },
571+};
572+
573+static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
574+ .cmd_rcgr = 0x3000,
575+ .hid_width = 5,
576+ .parent_map = gcc_parent_map_8,
577+ .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
578+ .clkr.hw.init = &(struct clk_init_data){
579+ .name = "blsp1_qup2_i2c_apps_clk_src",
580+ .parent_data = gcc_parent_data_4_8,
581+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
582+ .ops = &clk_rcg2_ops,
583+ },
584+};
585+
586+static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
587+ .cmd_rcgr = 0x3014,
588+ .mnd_width = 8,
589+ .hid_width = 5,
590+ .parent_map = gcc_parent_map_8,
591+ .freq_tbl = ftbl_blsp_spi_apps_clk_src,
592+ .clkr.hw.init = &(struct clk_init_data){
593+ .name = "blsp1_qup2_spi_apps_clk_src",
594+ .parent_data = gcc_parent_data_4_8,
595+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
596+ .ops = &clk_rcg2_ops,
597+ },
598+};
599+
600+static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
601+ .cmd_rcgr = 0x4000,
602+ .hid_width = 5,
603+ .parent_map = gcc_parent_map_8,
604+ .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
605+ .clkr.hw.init = &(struct clk_init_data){
606+ .name = "blsp1_qup3_i2c_apps_clk_src",
607+ .parent_data = gcc_parent_data_4_8,
608+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
609+ .ops = &clk_rcg2_ops,
610+ },
611+};
612+
613+static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
614+ .cmd_rcgr = 0x4024,
615+ .mnd_width = 8,
616+ .hid_width = 5,
617+ .parent_map = gcc_parent_map_8,
618+ .freq_tbl = ftbl_blsp_spi_apps_clk_src,
619+ .clkr.hw.init = &(struct clk_init_data){
620+ .name = "blsp1_qup3_spi_apps_clk_src",
621+ .parent_data = gcc_parent_data_4_8,
622+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
623+ .ops = &clk_rcg2_ops,
624+ },
625+};
626+
627+static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
628+ .cmd_rcgr = 0x5000,
629+ .hid_width = 5,
630+ .parent_map = gcc_parent_map_8,
631+ .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
632+ .clkr.hw.init = &(struct clk_init_data){
633+ .name = "blsp1_qup4_i2c_apps_clk_src",
634+ .parent_data = gcc_parent_data_4_8,
635+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
636+ .ops = &clk_rcg2_ops,
637+ },
638+};
639+
640+static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
641+ .cmd_rcgr = 0x5024,
642+ .mnd_width = 8,
643+ .hid_width = 5,
644+ .parent_map = gcc_parent_map_8,
645+ .freq_tbl = ftbl_blsp_spi_apps_clk_src,
646+ .clkr.hw.init = &(struct clk_init_data){
647+ .name = "blsp1_qup4_spi_apps_clk_src",
648+ .parent_data = gcc_parent_data_4_8,
649+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
650+ .ops = &clk_rcg2_ops,
651+ },
652+};
653+
654+static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
655+ F(3686400, P_GPLL0_OUT_MAIN, 1, 72, 15625),
656+ F(7372800, P_GPLL0_OUT_MAIN, 1, 144, 15625),
657+ F(14745600, P_GPLL0_OUT_MAIN, 1, 288, 15625),
658+ F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
659+ F(19200000, P_XO, 1, 0, 0),
660+ F(24000000, P_GPLL0_OUT_MAIN, 1, 3, 100),
661+ F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
662+ F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),
663+ F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),
664+ F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500),
665+ F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),
666+ F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),
667+ F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),
668+ F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625),
669+ F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),
670+ F(64000000, P_GPLL0_OUT_MAIN, 1, 2, 25),
671+ { }
672+};
673+
674+static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
675+ .cmd_rcgr = 0x2044,
676+ .mnd_width = 16,
677+ .hid_width = 5,
678+ .parent_map = gcc_parent_map_8,
679+ .freq_tbl = ftbl_blsp_uart_apps_clk_src,
680+ .clkr.hw.init = &(struct clk_init_data){
681+ .name = "blsp1_uart1_apps_clk_src",
682+ .parent_data = gcc_parent_data_4_8,
683+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
684+ .ops = &clk_rcg2_ops,
685+ },
686+};
687+
688+static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
689+ .cmd_rcgr = 0x3034,
690+ .mnd_width = 16,
691+ .hid_width = 5,
692+ .parent_map = gcc_parent_map_8,
693+ .freq_tbl = ftbl_blsp_uart_apps_clk_src,
694+ .clkr.hw.init = &(struct clk_init_data){
695+ .name = "blsp1_uart2_apps_clk_src",
696+ .parent_data = gcc_parent_data_4_8,
697+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
698+ .ops = &clk_rcg2_ops,
699+ },
700+};
701+
702+static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
703+ .cmd_rcgr = 0xc00c,
704+ .hid_width = 5,
705+ .parent_map = gcc_parent_map_8,
706+ .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
707+ .clkr.hw.init = &(struct clk_init_data){
708+ .name = "blsp2_qup1_i2c_apps_clk_src",
709+ .parent_data = gcc_parent_data_4_8,
710+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
711+ .ops = &clk_rcg2_ops,
712+ },
713+};
714+
715+static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
716+ .cmd_rcgr = 0xc024,
717+ .mnd_width = 8,
718+ .hid_width = 5,
719+ .parent_map = gcc_parent_map_8,
720+ .freq_tbl = ftbl_blsp_spi_apps_clk_src,
721+ .clkr.hw.init = &(struct clk_init_data){
722+ .name = "blsp2_qup1_spi_apps_clk_src",
723+ .parent_data = gcc_parent_data_4_8,
724+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
725+ .ops = &clk_rcg2_ops,
726+ },
727+};
728+
729+static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
730+ .cmd_rcgr = 0xd000,
731+ .hid_width = 5,
732+ .parent_map = gcc_parent_map_8,
733+ .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
734+ .clkr.hw.init = &(struct clk_init_data){
735+ .name = "blsp2_qup2_i2c_apps_clk_src",
736+ .parent_data = gcc_parent_data_4_8,
737+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
738+ .ops = &clk_rcg2_ops,
739+ },
740+};
741+
742+static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
743+ .cmd_rcgr = 0xd014,
744+ .mnd_width = 8,
745+ .hid_width = 5,
746+ .parent_map = gcc_parent_map_8,
747+ .freq_tbl = ftbl_blsp_spi_apps_clk_src,
748+ .clkr.hw.init = &(struct clk_init_data){
749+ .name = "blsp2_qup2_spi_apps_clk_src",
750+ .parent_data = gcc_parent_data_4_8,
751+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
752+ .ops = &clk_rcg2_ops,
753+ },
754+};
755+
756+static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
757+ .cmd_rcgr = 0xf000,
758+ .hid_width = 5,
759+ .parent_map = gcc_parent_map_8,
760+ .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
761+ .clkr.hw.init = &(struct clk_init_data){
762+ .name = "blsp2_qup3_i2c_apps_clk_src",
763+ .parent_data = gcc_parent_data_4_8,
764+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
765+ .ops = &clk_rcg2_ops,
766+ },
767+};
768+
769+static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
770+ .cmd_rcgr = 0xf024,
771+ .mnd_width = 8,
772+ .hid_width = 5,
773+ .parent_map = gcc_parent_map_8,
774+ .freq_tbl = ftbl_blsp_spi_apps_clk_src,
775+ .clkr.hw.init = &(struct clk_init_data){
776+ .name = "blsp2_qup3_spi_apps_clk_src",
777+ .parent_data = gcc_parent_data_4_8,
778+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
779+ .ops = &clk_rcg2_ops,
780+ },
781+};
782+
783+static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
784+ .cmd_rcgr = 0x18000,
785+ .hid_width = 5,
786+ .parent_map = gcc_parent_map_8,
787+ .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
788+ .clkr.hw.init = &(struct clk_init_data){
789+ .name = "blsp2_qup4_i2c_apps_clk_src",
790+ .parent_data = gcc_parent_data_4_8,
791+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
792+ .ops = &clk_rcg2_ops,
793+ },
794+};
795+
796+static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
797+ .cmd_rcgr = 0x18024,
798+ .mnd_width = 8,
799+ .hid_width = 5,
800+ .parent_map = gcc_parent_map_8,
801+ .freq_tbl = ftbl_blsp_spi_apps_clk_src,
802+ .clkr.hw.init = &(struct clk_init_data){
803+ .name = "blsp2_qup4_spi_apps_clk_src",
804+ .parent_data = gcc_parent_data_4_8,
805+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
806+ .ops = &clk_rcg2_ops,
807+ },
808+};
809+
810+static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
811+ .cmd_rcgr = 0xc044,
812+ .mnd_width = 16,
813+ .hid_width = 5,
814+ .parent_map = gcc_parent_map_8,
815+ .freq_tbl = ftbl_blsp_uart_apps_clk_src,
816+ .clkr.hw.init = &(struct clk_init_data){
817+ .name = "blsp2_uart1_apps_clk_src",
818+ .parent_data = gcc_parent_data_4_8,
819+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
820+ .ops = &clk_rcg2_ops,
821+ },
822+};
823+
824+static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
825+ .cmd_rcgr = 0xd034,
826+ .mnd_width = 16,
827+ .hid_width = 5,
828+ .parent_map = gcc_parent_map_8,
829+ .freq_tbl = ftbl_blsp_uart_apps_clk_src,
830+ .clkr.hw.init = &(struct clk_init_data){
831+ .name = "blsp2_uart2_apps_clk_src",
832+ .parent_data = gcc_parent_data_4_8,
833+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
834+ .ops = &clk_rcg2_ops,
835+ },
836+};
837+
838+static const struct freq_tbl ftbl_cci_clk_src[] = {
839+ F(19200000, P_XO, 1, 0, 0),
840+ F(37500000, P_GPLL0_AUX, 1, 3, 64),
841+ { }
842+};
843+
844+static struct clk_rcg2 cci_clk_src = {
845+ .cmd_rcgr = 0x51000,
846+ .mnd_width = 8,
847+ .hid_width = 5,
848+ .parent_map = gcc_parent_map_cci,
849+ .freq_tbl = ftbl_cci_clk_src,
850+ .clkr.hw.init = &(struct clk_init_data){
851+ .name = "cci_clk_src",
852+ .parent_data = gcc_parent_data_4_8,
853+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
854+ .ops = &clk_rcg2_ops,
855+ },
856+};
857+
858+static const struct freq_tbl ftbl_cpp_clk_src[] = {
859+ F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
860+ F(240000000, P_GPLL4_AUX, 5, 0, 0),
861+ F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
862+ F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
863+ F(480000000, P_GPLL4_AUX, 2.5, 0, 0),
864+ { }
865+};
866+
867+static struct clk_rcg2 cpp_clk_src = {
868+ .cmd_rcgr = 0x58018,
869+ .hid_width = 5,
870+ .parent_map = gcc_parent_map_cpp,
871+ .freq_tbl = ftbl_cpp_clk_src,
872+ .clkr.hw.init = &(struct clk_init_data){
873+ .name = "cpp_clk_src",
874+ .parent_data = gcc_parent_data_6,
875+ .num_parents = ARRAY_SIZE(gcc_parent_data_6),
876+ .ops = &clk_rcg2_ops,
877+ },
878+};
879+
880+static const struct freq_tbl ftbl_csi0_clk_src[] = {
881+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
882+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
883+ F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
884+ { }
885+};
886+
887+static struct clk_rcg2 csi0_clk_src = {
888+ .cmd_rcgr = 0x4e020,
889+ .hid_width = 5,
890+ .parent_map = gcc_parent_map_8,
891+ .freq_tbl = ftbl_csi0_clk_src,
892+ .clkr.hw.init = &(struct clk_init_data){
893+ .name = "csi0_clk_src",
894+ .parent_data = gcc_parent_data_4_8,
895+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
896+ .ops = &clk_rcg2_ops,
897+ },
898+};
899+
900+static const struct freq_tbl ftbl_csi1_clk_src[] = {
901+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
902+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
903+ F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
904+ { }
905+};
906+
907+static struct clk_rcg2 csi1_clk_src = {
908+ .cmd_rcgr = 0x4f020,
909+ .hid_width = 5,
910+ .parent_map = gcc_parent_map_8,
911+ .freq_tbl = ftbl_csi1_clk_src,
912+ .clkr.hw.init = &(struct clk_init_data){
913+ .name = "csi1_clk_src",
914+ .parent_data = gcc_parent_data_4_8,
915+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
916+ .ops = &clk_rcg2_ops,
917+ },
918+};
919+
920+static const struct freq_tbl ftbl_csi2_clk_src[] = {
921+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
922+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
923+ F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
924+ { }
925+};
926+
927+static struct clk_rcg2 csi2_clk_src = {
928+ .cmd_rcgr = 0x3c020,
929+ .hid_width = 5,
930+ .parent_map = gcc_parent_map_8,
931+ .freq_tbl = ftbl_csi2_clk_src,
932+ .clkr.hw.init = &(struct clk_init_data){
933+ .name = "csi2_clk_src",
934+ .parent_data = gcc_parent_data_4_8,
935+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
936+ .ops = &clk_rcg2_ops,
937+ },
938+};
939+
940+static const struct freq_tbl ftbl_camss_gp0_clk_src[] = {
941+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
942+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
943+ F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
944+ { }
945+};
946+
947+static struct clk_rcg2 camss_gp0_clk_src = {
948+ .cmd_rcgr = 0x54000,
949+ .mnd_width = 8,
950+ .hid_width = 5,
951+ .parent_map = gcc_parent_map_8_gp,
952+ .freq_tbl = ftbl_camss_gp0_clk_src,
953+ .clkr.hw.init = &(struct clk_init_data){
954+ .name = "camss_gp0_clk_src",
955+ .parent_data = gcc_parent_data_8_gp,
956+ .num_parents = ARRAY_SIZE(gcc_parent_data_8_gp),
957+ .ops = &clk_rcg2_ops,
958+ },
959+};
960+
961+static const struct freq_tbl ftbl_camss_gp1_clk_src[] = {
962+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
963+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
964+ F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
965+ { }
966+};
967+
968+static struct clk_rcg2 camss_gp1_clk_src = {
969+ .cmd_rcgr = 0x55000,
970+ .mnd_width = 8,
971+ .hid_width = 5,
972+ .parent_map = gcc_parent_map_8_gp,
973+ .freq_tbl = ftbl_camss_gp1_clk_src,
974+ .clkr.hw.init = &(struct clk_init_data){
975+ .name = "camss_gp1_clk_src",
976+ .parent_data = gcc_parent_data_8_gp,
977+ .num_parents = ARRAY_SIZE(gcc_parent_data_8_gp),
978+ .ops = &clk_rcg2_ops,
979+ },
980+};
981+
982+static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
983+ F(133330000, P_GPLL0_OUT_MAIN, 6, 0, 0),
984+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
985+ F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
986+ F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
987+ { }
988+};
989+
990+static struct clk_rcg2 jpeg0_clk_src = {
991+ .cmd_rcgr = 0x57000,
992+ .hid_width = 5,
993+ .parent_map = gcc_parent_map_6,
994+ .freq_tbl = ftbl_jpeg0_clk_src,
995+ .clkr.hw.init = &(struct clk_init_data){
996+ .name = "jpeg0_clk_src",
997+ .parent_data = gcc_parent_data_6,
998+ .num_parents = ARRAY_SIZE(gcc_parent_data_6),
999+ .ops = &clk_rcg2_ops,
1000+ },
1001+};
1002+
1003+static const struct freq_tbl ftbl_mclk_clk_src[] = {
1004+ F(8000000, P_GPLL0_OUT_MAIN, 1, 1, 100),
1005+ F(24000000, P_GPLL6_OUT, 1, 1, 45),
1006+ F(66670000, P_GPLL0_OUT_MAIN, 12, 0, 0),
1007+ { }
1008+};
1009+
1010+static struct clk_rcg2 mclk0_clk_src = {
1011+ .cmd_rcgr = 0x52000,
1012+ .mnd_width = 8,
1013+ .hid_width = 5,
1014+ .parent_map = gcc_parent_map_7,
1015+ .freq_tbl = ftbl_mclk_clk_src,
1016+ .clkr.hw.init = &(struct clk_init_data){
1017+ .name = "mclk0_clk_src",
1018+ .parent_data = gcc_parent_data_7,
1019+ .num_parents = ARRAY_SIZE(gcc_parent_data_7),
1020+ .ops = &clk_rcg2_ops,
1021+ },
1022+};
1023+
1024+static struct clk_rcg2 mclk1_clk_src = {
1025+ .cmd_rcgr = 0x53000,
1026+ .mnd_width = 8,
1027+ .hid_width = 5,
1028+ .parent_map = gcc_parent_map_7,
1029+ .freq_tbl = ftbl_mclk_clk_src,
1030+ .clkr.hw.init = &(struct clk_init_data){
1031+ .name = "mclk1_clk_src",
1032+ .parent_data = gcc_parent_data_7,
1033+ .num_parents = ARRAY_SIZE(gcc_parent_data_7),
1034+ .ops = &clk_rcg2_ops,
1035+ },
1036+};
1037+
1038+static struct clk_rcg2 mclk2_clk_src = {
1039+ .cmd_rcgr = 0x5c000,
1040+ .mnd_width = 8,
1041+ .hid_width = 5,
1042+ .parent_map = gcc_parent_map_7,
1043+ .freq_tbl = ftbl_mclk_clk_src,
1044+ .clkr.hw.init = &(struct clk_init_data){
1045+ .name = "mclk2_clk_src",
1046+ .parent_data = gcc_parent_data_7,
1047+ .num_parents = ARRAY_SIZE(gcc_parent_data_7),
1048+ .ops = &clk_rcg2_ops,
1049+ },
1050+};
1051+
1052+static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = {
1053+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1054+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1055+ F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1056+ { }
1057+};
1058+
1059+static struct clk_rcg2 csi0phytimer_clk_src = {
1060+ .cmd_rcgr = 0x4e000,
1061+ .hid_width = 5,
1062+ .parent_map = gcc_parent_map_8,
1063+ .freq_tbl = ftbl_csi0phytimer_clk_src,
1064+ .clkr.hw.init = &(struct clk_init_data){
1065+ .name = "csi0phytimer_clk_src",
1066+ .parent_data = gcc_parent_data_4_8,
1067+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
1068+ .ops = &clk_rcg2_ops,
1069+ },
1070+};
1071+
1072+static const struct freq_tbl ftbl_csi1phytimer_clk_src[] = {
1073+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1074+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1075+ F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1076+ { }
1077+};
1078+
1079+static struct clk_rcg2 csi1phytimer_clk_src = {
1080+ .cmd_rcgr = 0x4f000,
1081+ .hid_width = 5,
1082+ .parent_map = gcc_parent_map_8,
1083+ .freq_tbl = ftbl_csi1phytimer_clk_src,
1084+ .clkr.hw.init = &(struct clk_init_data){
1085+ .name = "csi1phytimer_clk_src",
1086+ .parent_data = gcc_parent_data_4_8,
1087+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
1088+ .ops = &clk_rcg2_ops,
1089+ },
1090+};
1091+
1092+static const struct freq_tbl ftbl_camss_top_ahb_clk_src[] = {
1093+ F(40000000, P_GPLL0_OUT_MAIN, 10, 1, 2),
1094+ F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1095+ { }
1096+};
1097+
1098+static struct clk_rcg2 camss_top_ahb_clk_src = {
1099+ .cmd_rcgr = 0x5a000,
1100+ .mnd_width = 8,
1101+ .hid_width = 5,
1102+ .parent_map = gcc_parent_map_8,
1103+ .freq_tbl = ftbl_camss_top_ahb_clk_src,
1104+ .clkr.hw.init = &(struct clk_init_data){
1105+ .name = "camss_top_ahb_clk_src",
1106+ .parent_data = gcc_parent_data_4_8,
1107+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
1108+ .ops = &clk_rcg2_ops,
1109+ },
1110+};
1111+
1112+static const struct freq_tbl ftbl_vfe0_clk_src[] = {
1113+ F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1114+ F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1115+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1116+ F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1117+ F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1118+ F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1119+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1120+ F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1121+ F(300000000, P_GPLL4_OUT, 4, 0, 0),
1122+ F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1123+ F(466000000, P_GPLL2_AUX, 2, 0, 0),
1124+ { }
1125+};
1126+
1127+static struct clk_rcg2 vfe0_clk_src = {
1128+ .cmd_rcgr = 0x58000,
1129+ .hid_width = 5,
1130+ .parent_map = gcc_parent_map_2,
1131+ .freq_tbl = ftbl_vfe0_clk_src,
1132+ .clkr.hw.init = &(struct clk_init_data){
1133+ .name = "vfe0_clk_src",
1134+ .parent_data = gcc_parent_data_2,
1135+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1136+ .ops = &clk_rcg2_ops,
1137+ },
1138+};
1139+
1140+static const struct freq_tbl ftbl_vfe1_clk_src[] = {
1141+ F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1142+ F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1143+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1144+ F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1145+ F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1146+ F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1147+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1148+ F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1149+ F(300000000, P_GPLL4_OUT, 4, 0, 0),
1150+ F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1151+ F(466000000, P_GPLL2_AUX, 2, 0, 0),
1152+ { }
1153+};
1154+
1155+static struct clk_rcg2 vfe1_clk_src = {
1156+ .cmd_rcgr = 0x58054,
1157+ .hid_width = 5,
1158+ .parent_map = gcc_parent_map_2,
1159+ .freq_tbl = ftbl_vfe1_clk_src,
1160+ .clkr.hw.init = &(struct clk_init_data){
1161+ .name = "vfe1_clk_src",
1162+ .parent_data = gcc_parent_data_2,
1163+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1164+ .ops = &clk_rcg2_ops,
1165+ },
1166+};
1167+
1168+static const struct freq_tbl ftbl_crypto_clk_src[] = {
1169+ F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1170+ F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1171+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1172+ F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1173+ { }
1174+};
1175+
1176+static struct clk_rcg2 crypto_clk_src = {
1177+ .cmd_rcgr = 0x16004,
1178+ .hid_width = 5,
1179+ .parent_map = gcc_parent_map_8,
1180+ .freq_tbl = ftbl_crypto_clk_src,
1181+ .clkr.hw.init = &(struct clk_init_data){
1182+ .name = "crypto_clk_src",
1183+ .parent_data = gcc_parent_data_4_8,
1184+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
1185+ .ops = &clk_rcg2_ops,
1186+ },
1187+};
1188+
1189+static const struct freq_tbl ftbl_gp1_clk_src[] = {
1190+ F(19200000, P_XO, 1, 0, 0),
1191+ { }
1192+};
1193+
1194+static struct clk_rcg2 gp1_clk_src = {
1195+ .cmd_rcgr = 0x8004,
1196+ .mnd_width = 8,
1197+ .hid_width = 5,
1198+ .parent_map = gcc_parent_map_8_gp,
1199+ .freq_tbl = ftbl_gp1_clk_src,
1200+ .clkr.hw.init = &(struct clk_init_data){
1201+ .name = "gp1_clk_src",
1202+ .parent_hws = (const struct clk_hw *[]) {
1203+ &gpll0_vote.hw,
1204+ },
1205+ .num_parents = 1,
1206+ .ops = &clk_rcg2_ops,
1207+ },
1208+};
1209+
1210+static const struct freq_tbl ftbl_gp2_clk_src[] = {
1211+ F(19200000, P_XO, 1, 0, 0),
1212+ { }
1213+};
1214+
1215+static struct clk_rcg2 gp2_clk_src = {
1216+ .cmd_rcgr = 0x9004,
1217+ .mnd_width = 8,
1218+ .hid_width = 5,
1219+ .parent_map = gcc_parent_map_8_gp,
1220+ .freq_tbl = ftbl_gp2_clk_src,
1221+ .clkr.hw.init = &(struct clk_init_data){
1222+ .name = "gp2_clk_src",
1223+ .parent_hws = (const struct clk_hw *[]) {
1224+ &gpll0_vote.hw,
1225+ },
1226+ .num_parents = 1,
1227+ .ops = &clk_rcg2_ops,
1228+ },
1229+};
1230+
1231+static const struct freq_tbl ftbl_gp3_clk_src[] = {
1232+ F(19200000, P_XO, 1, 0, 0),
1233+ { }
1234+};
1235+
1236+static struct clk_rcg2 gp3_clk_src = {
1237+ .cmd_rcgr = 0xa004,
1238+ .mnd_width = 8,
1239+ .hid_width = 5,
1240+ .parent_map = gcc_parent_map_8_gp,
1241+ .freq_tbl = ftbl_gp3_clk_src,
1242+ .clkr.hw.init = &(struct clk_init_data){
1243+ .name = "gp3_clk_src",
1244+ .parent_hws = (const struct clk_hw *[]) {
1245+ &gpll0_vote.hw,
1246+ },
1247+ .num_parents = 1,
1248+ .ops = &clk_rcg2_ops,
1249+ },
1250+};
1251+
1252+static struct clk_rcg2 byte0_clk_src = {
1253+ .cmd_rcgr = 0x4d044,
1254+ .mnd_width = 0,
1255+ .hid_width = 5,
1256+ .parent_map = gcc_parent_map_mdss_byte0,
1257+ .clkr.hw.init = &(struct clk_init_data){
1258+ .name = "byte0_clk_src",
1259+ .parent_data = gcc_parent_data_mdss_byte0,
1260+ .num_parents = ARRAY_SIZE(gcc_parent_data_mdss_byte0),
1261+ .ops = &clk_byte2_ops,
1262+ .flags = CLK_SET_RATE_PARENT,
1263+ },
1264+};
1265+
1266+static struct clk_rcg2 byte1_clk_src = {
1267+ .cmd_rcgr = 0x4d0b0,
1268+ .mnd_width = 0,
1269+ .hid_width = 5,
1270+ .parent_map = gcc_parent_map_mdss_byte1,
1271+ .clkr.hw.init = &(struct clk_init_data){
1272+ .name = "byte1_clk_src",
1273+ .parent_data = gcc_parent_data_mdss_byte1,
1274+ .num_parents = ARRAY_SIZE(gcc_parent_data_mdss_byte1),
1275+ .ops = &clk_byte2_ops,
1276+ .flags = CLK_SET_RATE_PARENT,
1277+ },
1278+};
1279+
1280+static const struct freq_tbl ftbl_esc0_1_clk_src[] = {
1281+ F(19200000, P_XO, 1, 0, 0),
1282+ { }
1283+};
1284+
1285+static struct clk_rcg2 esc0_clk_src = {
1286+ .cmd_rcgr = 0x4d05c,
1287+ .hid_width = 5,
1288+ .freq_tbl = ftbl_esc0_1_clk_src,
1289+ .parent_map = gcc_parent_map_mdss_byte0,
1290+ .clkr.hw.init = &(struct clk_init_data){
1291+ .name = "esc0_clk_src",
1292+ .parent_data = gcc_parent_data_mdss_byte0,
1293+ .num_parents = ARRAY_SIZE(gcc_parent_data_mdss_byte0),
1294+ .ops = &clk_rcg2_ops,
1295+ },
1296+};
1297+
1298+static struct clk_rcg2 esc1_clk_src = {
1299+ .cmd_rcgr = 0x4d0a8,
1300+ .hid_width = 5,
1301+ .freq_tbl = ftbl_esc0_1_clk_src,
1302+ .parent_map = gcc_parent_map_mdss_byte1,
1303+ .clkr.hw.init = &(struct clk_init_data){
1304+ .name = "esc1_clk_src",
1305+ .parent_data = gcc_parent_data_mdss_byte1,
1306+ .num_parents = ARRAY_SIZE(gcc_parent_data_mdss_byte1),
1307+ .ops = &clk_rcg2_ops,
1308+ },
1309+};
1310+
1311+static const struct freq_tbl ftbl_mdp_clk_src[] = {
1312+ F(50000000, P_GPLL0_OUT_MDP, 16, 0, 0),
1313+ F(80000000, P_GPLL0_OUT_MDP, 10, 0, 0),
1314+ F(100000000, P_GPLL0_OUT_MDP, 8, 0, 0),
1315+ F(145454545, P_GPLL0_OUT_MDP, 5.5, 0, 0),
1316+ F(160000000, P_GPLL0_OUT_MDP, 5, 0, 0),
1317+ F(177777778, P_GPLL0_OUT_MDP, 4.5, 0, 0),
1318+ F(200000000, P_GPLL0_OUT_MDP, 4, 0, 0),
1319+ F(270000000, P_GPLL6_OUT, 4, 0, 0),
1320+ F(320000000, P_GPLL0_OUT_MDP, 2.5, 0, 0),
1321+ F(360000000, P_GPLL6_OUT, 3, 0, 0),
1322+ { }
1323+};
1324+
1325+static struct clk_rcg2 mdp_clk_src = {
1326+ .cmd_rcgr = 0x4d014,
1327+ .hid_width = 5,
1328+ .parent_map = gcc_parent_map_7_mdp,
1329+ .freq_tbl = ftbl_mdp_clk_src,
1330+ .clkr.hw.init = &(struct clk_init_data){
1331+ .name = "mdp_clk_src",
1332+ .parent_data = gcc_parent_data_7_mdp,
1333+ .num_parents = ARRAY_SIZE(gcc_parent_data_7_mdp),
1334+ .ops = &clk_rcg2_ops,
1335+ },
1336+};
1337+
1338+static struct clk_rcg2 pclk0_clk_src = {
1339+ .cmd_rcgr = 0x4d000,
1340+ .mnd_width = 8,
1341+ .hid_width = 5,
1342+ .parent_map = gcc_parent_map_mdss_pix0,
1343+ .clkr.hw.init = &(struct clk_init_data){
1344+ .name = "pclk0_clk_src",
1345+ .parent_data = gcc_parent_data_mdss_pix0,
1346+ .num_parents = ARRAY_SIZE(gcc_parent_data_mdss_pix0),
1347+ .ops = &clk_pixel_ops,
1348+ .flags = CLK_SET_RATE_PARENT,
1349+ },
1350+};
1351+
1352+static struct clk_rcg2 pclk1_clk_src = {
1353+ .cmd_rcgr = 0x4d0b8,
1354+ .mnd_width = 8,
1355+ .hid_width = 5,
1356+ .parent_map = gcc_parent_map_mdss_pix1,
1357+ .clkr.hw.init = &(struct clk_init_data){
1358+ .name = "pclk1_clk_src",
1359+ .parent_data = gcc_parent_data_mdss_pix1,
1360+ .num_parents = ARRAY_SIZE(gcc_parent_data_mdss_pix1),
1361+ .ops = &clk_pixel_ops,
1362+ .flags = CLK_SET_RATE_PARENT,
1363+ },
1364+};
1365+
1366+static const struct freq_tbl ftbl_vsync_clk_src[] = {
1367+ F(19200000, P_XO, 1, 0, 0),
1368+ { }
1369+};
1370+
1371+static struct clk_rcg2 vsync_clk_src = {
1372+ .cmd_rcgr = 0x4d02c,
1373+ .hid_width = 5,
1374+ .parent_map = gcc_parent_map_10,
1375+ .freq_tbl = ftbl_vsync_clk_src,
1376+ .clkr.hw.init = &(struct clk_init_data){
1377+ .name = "vsync_clk_src",
1378+ .parent_data = gcc_parent_data_10,
1379+ .num_parents = ARRAY_SIZE(gcc_parent_data_10),
1380+ .ops = &clk_rcg2_ops,
1381+ },
1382+};
1383+
1384+static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
1385+ F(19200000, P_XO, 1, 0, 0),
1386+ F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1387+ F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1388+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1389+ F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1390+ F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1391+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1392+ F(228571429, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
1393+ F(240000000, P_GPLL6_GFX3D, 4.5, 0, 0),
1394+ F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1395+ F(300000000, P_GPLL4_GFX3D, 4, 0, 0),
1396+ F(360000000, P_GPLL6_GFX3D, 3, 0, 0),
1397+ F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1398+ F(432000000, P_GPLL6_GFX3D, 2.5, 0, 0),
1399+ F(480000000, P_GPLL4_GFX3D, 2.5, 0, 0),
1400+ F(540000000, P_GPLL6_GFX3D, 2, 0, 0),
1401+ F(600000000, P_GPLL4_GFX3D, 2, 0, 0),
1402+ { }
1403+};
1404+
1405+static const struct clk_init_data gfx3d_clk_params = {
1406+ .name = "gfx3d_clk_src",
1407+ .parent_data = gcc_parent_data_gfx3d,
1408+ .num_parents = ARRAY_SIZE(gcc_parent_data_gfx3d),
1409+ .ops = &clk_rcg2_ops,
1410+};
1411+
1412+static struct clk_rcg2 gfx3d_clk_src = {
1413+ .cmd_rcgr = 0x59000,
1414+ .hid_width = 5,
1415+ .parent_map = gcc_parent_map_gfx3d,
1416+ .freq_tbl = ftbl_gfx3d_clk_src,
1417+ .clkr.hw.init = &gfx3d_clk_params,
1418+};
1419+
1420+static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1421+ F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
1422+ { }
1423+};
1424+
1425+static struct clk_rcg2 pdm2_clk_src = {
1426+ .cmd_rcgr = 0x44010,
1427+ .hid_width = 5,
1428+ .parent_map = gcc_parent_map_8,
1429+ .freq_tbl = ftbl_pdm2_clk_src,
1430+ .clkr.hw.init = &(struct clk_init_data){
1431+ .name = "pdm2_clk_src",
1432+ .parent_data = gcc_parent_data_4_8,
1433+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
1434+ .ops = &clk_rcg2_ops,
1435+ },
1436+};
1437+
1438+static const struct freq_tbl ftbl_rbcpr_gfx_clk_src[] = {
1439+ F(19200000, P_XO, 1, 0, 0),
1440+ F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1441+ { }
1442+};
1443+
1444+static struct clk_rcg2 rbcpr_gfx_clk_src = {
1445+ .cmd_rcgr = 0x3a00c,
1446+ .hid_width = 5,
1447+ .parent_map = gcc_parent_map_8,
1448+ .freq_tbl = ftbl_rbcpr_gfx_clk_src,
1449+ .clkr.hw.init = &(struct clk_init_data){
1450+ .name = "rbcpr_gfx_clk_src",
1451+ .parent_data = gcc_parent_data_4_8,
1452+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
1453+ .ops = &clk_rcg2_ops,
1454+ },
1455+};
1456+
1457+static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
1458+ F(144000, P_XO, 16, 3, 25),
1459+ F(400000, P_XO, 12, 1, 4),
1460+ F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
1461+ F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
1462+ F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1463+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1464+ F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1465+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1466+ F(342850000, P_GPLL4_OUT, 3.5, 0, 0),
1467+ F(400000000, P_GPLL4_OUT, 3, 0, 0),
1468+ { }
1469+};
1470+
1471+static const struct freq_tbl ftbl_sdcc1_8976_v1_1_apps_clk_src[] = {
1472+ F(144000, P_XO, 16, 3, 25),
1473+ F(400000, P_XO, 12, 1, 4),
1474+ F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
1475+ F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
1476+ F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1477+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1478+ F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1479+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1480+ F(186400000, P_GPLL2_OUT, 5, 0, 0),
1481+ F(372800000, P_GPLL2_OUT, 2.5, 0, 0),
1482+ { }
1483+};
1484+
1485+static const struct clk_init_data sdcc1_apps_clk_src_8976v1_1_init = {
1486+ .name = "sdcc1_apps_clk_src",
1487+ .parent_data = gcc_parent_data_v1_1,
1488+ .num_parents = ARRAY_SIZE(gcc_parent_data_v1_1),
1489+ .ops = &clk_rcg2_ops,
1490+};
1491+
1492+static struct clk_rcg2 sdcc1_apps_clk_src = {
1493+ .cmd_rcgr = 0x42004,
1494+ .mnd_width = 8,
1495+ .hid_width = 5,
1496+ .parent_map = gcc_parent_map_1,
1497+ .freq_tbl = ftbl_sdcc1_apps_clk_src,
1498+ .clkr.hw.init = &(struct clk_init_data){
1499+ .name = "sdcc1_apps_clk_src",
1500+ .parent_data = gcc_parent_data_1,
1501+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1502+ .ops = &clk_rcg2_ops,
1503+ },
1504+};
1505+
1506+static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
1507+ F(100000000, P_GPLL0_OUT_M, 8, 0, 0),
1508+ F(200000000, P_GPLL0_OUT_M, 4, 0, 0),
1509+ { }
1510+};
1511+
1512+static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1513+ .cmd_rcgr = 0x5d000,
1514+ .mnd_width = 8,
1515+ .hid_width = 5,
1516+ .parent_map = gcc_parent_map_sdcc_ice,
1517+ .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
1518+ .clkr.hw.init = &(struct clk_init_data){
1519+ .name = "sdcc1_ice_core_clk_src",
1520+ .parent_data = gcc_parent_data_4_8,
1521+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
1522+ .ops = &clk_rcg2_ops,
1523+ },
1524+};
1525+
1526+static const struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
1527+ F(144000, P_XO, 16, 3, 25),
1528+ F(400000, P_XO, 12, 1, 4),
1529+ F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
1530+ F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
1531+ F(40000000, P_GPLL0_OUT_MAIN, 10, 1, 2),
1532+ F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1533+ F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1534+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1535+ F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1536+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1537+ { }
1538+};
1539+
1540+static struct clk_rcg2 sdcc2_apps_clk_src = {
1541+ .cmd_rcgr = 0x43004,
1542+ .mnd_width = 8,
1543+ .hid_width = 5,
1544+ .parent_map = gcc_parent_map_4,
1545+ .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
1546+ .clkr.hw.init = &(struct clk_init_data){
1547+ .name = "sdcc2_apps_clk_src",
1548+ .parent_data = gcc_parent_data_4_8,
1549+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
1550+ .ops = &clk_rcg2_ops,
1551+ },
1552+};
1553+
1554+static struct clk_rcg2 sdcc3_apps_clk_src = {
1555+ .cmd_rcgr = 0x39004,
1556+ .mnd_width = 8,
1557+ .hid_width = 5,
1558+ .parent_map = gcc_parent_map_4,
1559+ .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
1560+ .clkr.hw.init = &(struct clk_init_data){
1561+ .name = "sdcc3_apps_clk_src",
1562+ .parent_data = gcc_parent_data_4_8,
1563+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
1564+ .ops = &clk_rcg2_ops,
1565+ },
1566+};
1567+
1568+static const struct freq_tbl ftbl_usb_fs_ic_clk_src[] = {
1569+ F(60000000, P_GPLL6_OUT_MAIN, 6, 1, 3),
1570+ { }
1571+};
1572+
1573+static struct clk_rcg2 usb_fs_ic_clk_src = {
1574+ .cmd_rcgr = 0x3f034,
1575+ .mnd_width = 8,
1576+ .hid_width = 5,
1577+ .parent_map = gcc_parent_map_9,
1578+ .freq_tbl = ftbl_usb_fs_ic_clk_src,
1579+ .clkr.hw.init = &(struct clk_init_data){
1580+ .name = "usb_fs_ic_clk_src",
1581+ .parent_data = gcc_parent_data_9,
1582+ .num_parents = ARRAY_SIZE(gcc_parent_data_9),
1583+ .ops = &clk_rcg2_ops,
1584+ },
1585+};
1586+
1587+static const struct freq_tbl ftbl_usb_fs_system_clk_src[] = {
1588+ F(64000000, P_GPLL0_OUT, 12.5, 0, 0),
1589+ { }
1590+};
1591+
1592+static struct clk_rcg2 usb_fs_system_clk_src = {
1593+ .cmd_rcgr = 0x3f010,
1594+ .mnd_width = 8,
1595+ .hid_width = 5,
1596+ .parent_map = gcc_parent_map_4_fs,
1597+ .freq_tbl = ftbl_usb_fs_system_clk_src,
1598+ .clkr.hw.init = &(struct clk_init_data){
1599+ .name = "usb_fs_system_clk_src",
1600+ .parent_data = gcc_parent_data_4_8,
1601+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
1602+ .ops = &clk_rcg2_ops,
1603+ },
1604+};
1605+
1606+static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1607+ F(57140000, P_GPLL0_OUT_MAIN, 14, 0, 0),
1608+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1609+ F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1610+ F(177780000, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1611+ { }
1612+};
1613+
1614+static struct clk_rcg2 usb_hs_system_clk_src = {
1615+ .cmd_rcgr = 0x41010,
1616+ .hid_width = 5,
1617+ .parent_map = gcc_parent_map_4,
1618+ .freq_tbl = ftbl_usb_hs_system_clk_src,
1619+ .clkr.hw.init = &(struct clk_init_data){
1620+ .name = "usb_hs_system_clk_src",
1621+ .parent_data = gcc_parent_data_4_8,
1622+ .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
1623+ .ops = &clk_rcg2_ops,
1624+ },
1625+};
1626+
1627+static const struct freq_tbl ftbl_vcodec0_clk_src[] = {
1628+ F(72727200, P_GPLL0_OUT_MAIN, 11, 0, 0),
1629+ F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1630+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1631+ F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1632+ F(228570000, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
1633+ F(310667000, P_GPLL2_AUX, 3, 0, 0),
1634+ F(360000000, P_GPLL6_AUX, 3, 0, 0),
1635+ F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1636+ F(466000000, P_GPLL2_AUX, 2, 0, 0),
1637+ { }
1638+};
1639+
1640+static struct clk_rcg2 vcodec0_clk_src = {
1641+ .cmd_rcgr = 0x4c000,
1642+ .mnd_width = 8,
1643+ .hid_width = 5,
1644+ .parent_map = gcc_parent_map_3,
1645+ .freq_tbl = ftbl_vcodec0_clk_src,
1646+ .clkr.hw.init = &(struct clk_init_data){
1647+ .name = "vcodec0_clk_src",
1648+ .parent_data = gcc_parent_data_3,
1649+ .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1650+ .ops = &clk_rcg2_ops,
1651+ },
1652+};
1653+
1654+static struct clk_branch gcc_aps_0_clk = {
1655+ .halt_reg = 0x78004,
1656+ .clkr = {
1657+ .enable_reg = 0x78004,
1658+ .enable_mask = BIT(0),
1659+ .hw.init = &(struct clk_init_data) {
1660+ .name = "gcc_aps_0_clk",
1661+ .parent_hws = (const struct clk_hw *[]) {
1662+ &aps_0_clk_src.clkr.hw,
1663+ },
1664+ .num_parents = 1,
1665+ .flags = CLK_SET_RATE_PARENT,
1666+ .ops = &clk_branch2_ops,
1667+ },
1668+ },
1669+};
1670+
1671+static struct clk_branch gcc_aps_1_clk = {
1672+ .halt_reg = 0x79004,
1673+ .clkr = {
1674+ .enable_reg = 0x79004,
1675+ .enable_mask = BIT(0),
1676+ .hw.init = &(struct clk_init_data) {
1677+ .name = "gcc_aps_1_clk",
1678+ .parent_hws = (const struct clk_hw *[]) {
1679+ &aps_1_clk_src.clkr.hw,
1680+ },
1681+ .num_parents = 1,
1682+ .flags = CLK_SET_RATE_PARENT,
1683+ .ops = &clk_branch2_ops,
1684+ },
1685+ },
1686+};
1687+
1688+static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1689+ .halt_reg = 0x2008,
1690+ .halt_check = BRANCH_HALT,
1691+ .clkr = {
1692+ .enable_reg = 0x2008,
1693+ .enable_mask = BIT(0),
1694+ .hw.init = &(struct clk_init_data) {
1695+ .name = "gcc_blsp1_qup1_i2c_apps_clk",
1696+ .parent_hws = (const struct clk_hw *[]) {
1697+ &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
1698+ },
1699+ .num_parents = 1,
1700+ .flags = CLK_SET_RATE_PARENT,
1701+ .ops = &clk_branch2_ops,
1702+ },
1703+ },
1704+};
1705+
1706+static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1707+ .halt_reg = 0x2004,
1708+ .halt_check = BRANCH_HALT,
1709+ .clkr = {
1710+ .enable_reg = 0x2004,
1711+ .enable_mask = BIT(0),
1712+ .hw.init = &(struct clk_init_data) {
1713+ .name = "gcc_blsp1_qup1_spi_apps_clk",
1714+ .parent_hws = (const struct clk_hw *[]) {
1715+ &blsp1_qup1_spi_apps_clk_src.clkr.hw,
1716+ },
1717+ .num_parents = 1,
1718+ .flags = CLK_SET_RATE_PARENT,
1719+ .ops = &clk_branch2_ops,
1720+ },
1721+ },
1722+};
1723+
1724+static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1725+ .halt_reg = 0x3010,
1726+ .halt_check = BRANCH_HALT,
1727+ .clkr = {
1728+ .enable_reg = 0x3010,
1729+ .enable_mask = BIT(0),
1730+ .hw.init = &(struct clk_init_data) {
1731+ .name = "gcc_blsp1_qup2_i2c_apps_clk",
1732+ .parent_hws = (const struct clk_hw *[]) {
1733+ &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1734+ },
1735+ .num_parents = 1,
1736+ .flags = CLK_SET_RATE_PARENT,
1737+ .ops = &clk_branch2_ops,
1738+ },
1739+ },
1740+};
1741+
1742+static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1743+ .halt_reg = 0x300c,
1744+ .halt_check = BRANCH_HALT,
1745+ .clkr = {
1746+ .enable_reg = 0x300c,
1747+ .enable_mask = BIT(0),
1748+ .hw.init = &(struct clk_init_data) {
1749+ .name = "gcc_blsp1_qup2_spi_apps_clk",
1750+ .parent_hws = (const struct clk_hw *[]) {
1751+ &blsp1_qup2_spi_apps_clk_src.clkr.hw,
1752+ },
1753+ .num_parents = 1,
1754+ .flags = CLK_SET_RATE_PARENT,
1755+ .ops = &clk_branch2_ops,
1756+ },
1757+ },
1758+};
1759+
1760+static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1761+ .halt_reg = 0x4020,
1762+ .halt_check = BRANCH_HALT,
1763+ .clkr = {
1764+ .enable_reg = 0x4020,
1765+ .enable_mask = BIT(0),
1766+ .hw.init = &(struct clk_init_data) {
1767+ .name = "gcc_blsp1_qup3_i2c_apps_clk",
1768+ .parent_hws = (const struct clk_hw *[]) {
1769+ &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
1770+ },
1771+ .num_parents = 1,
1772+ .flags = CLK_SET_RATE_PARENT,
1773+ .ops = &clk_branch2_ops,
1774+ },
1775+ },
1776+};
1777+
1778+static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1779+ .halt_reg = 0x401c,
1780+ .halt_check = BRANCH_HALT,
1781+ .clkr = {
1782+ .enable_reg = 0x401c,
1783+ .enable_mask = BIT(0),
1784+ .hw.init = &(struct clk_init_data) {
1785+ .name = "gcc_blsp1_qup3_spi_apps_clk",
1786+ .parent_hws = (const struct clk_hw *[]) {
1787+ &blsp1_qup3_spi_apps_clk_src.clkr.hw,
1788+ },
1789+ .num_parents = 1,
1790+ .flags = CLK_SET_RATE_PARENT,
1791+ .ops = &clk_branch2_ops,
1792+ },
1793+ },
1794+};
1795+
1796+static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1797+ .halt_reg = 0x5020,
1798+ .halt_check = BRANCH_HALT,
1799+ .clkr = {
1800+ .enable_reg = 0x5020,
1801+ .enable_mask = BIT(0),
1802+ .hw.init = &(struct clk_init_data) {
1803+ .name = "gcc_blsp1_qup4_i2c_apps_clk",
1804+ .parent_hws = (const struct clk_hw *[]) {
1805+ &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
1806+ },
1807+ .num_parents = 1,
1808+ .flags = CLK_SET_RATE_PARENT,
1809+ .ops = &clk_branch2_ops,
1810+ },
1811+ },
1812+};
1813+
1814+static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1815+ .halt_reg = 0x501c,
1816+ .halt_check = BRANCH_HALT,
1817+ .clkr = {
1818+ .enable_reg = 0x501c,
1819+ .enable_mask = BIT(0),
1820+ .hw.init = &(struct clk_init_data) {
1821+ .name = "gcc_blsp1_qup4_spi_apps_clk",
1822+ .parent_hws = (const struct clk_hw *[]) {
1823+ &blsp1_qup4_spi_apps_clk_src.clkr.hw,
1824+ },
1825+ .num_parents = 1,
1826+ .flags = CLK_SET_RATE_PARENT,
1827+ .ops = &clk_branch2_ops,
1828+ },
1829+ },
1830+};
1831+
1832+static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1833+ .halt_reg = 0x203c,
1834+ .halt_check = BRANCH_HALT,
1835+ .clkr = {
1836+ .enable_reg = 0x203c,
1837+ .enable_mask = BIT(0),
1838+ .hw.init = &(struct clk_init_data) {
1839+ .name = "gcc_blsp1_uart1_apps_clk",
1840+ .parent_hws = (const struct clk_hw *[]) {
1841+ &blsp1_uart1_apps_clk_src.clkr.hw,
1842+ },
1843+ .num_parents = 1,
1844+ .flags = CLK_SET_RATE_PARENT,
1845+ .ops = &clk_branch2_ops,
1846+ },
1847+ },
1848+};
1849+
1850+static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1851+ .halt_reg = 0x302c,
1852+ .halt_check = BRANCH_HALT,
1853+ .clkr = {
1854+ .enable_reg = 0x302c,
1855+ .enable_mask = BIT(0),
1856+ .hw.init = &(struct clk_init_data) {
1857+ .name = "gcc_blsp1_uart2_apps_clk",
1858+ .parent_hws = (const struct clk_hw *[]) {
1859+ &blsp1_uart2_apps_clk_src.clkr.hw,
1860+ },
1861+ .num_parents = 1,
1862+ .flags = CLK_SET_RATE_PARENT,
1863+ .ops = &clk_branch2_ops,
1864+ },
1865+ },
1866+};
1867+
1868+static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1869+ .halt_reg = 0xc008,
1870+ .halt_check = BRANCH_HALT,
1871+ .clkr = {
1872+ .enable_reg = 0xc008,
1873+ .enable_mask = BIT(0),
1874+ .hw.init = &(struct clk_init_data) {
1875+ .name = "gcc_blsp2_qup1_i2c_apps_clk",
1876+ .parent_hws = (const struct clk_hw *[]) {
1877+ &blsp2_qup1_i2c_apps_clk_src.clkr.hw,
1878+ },
1879+ .num_parents = 1,
1880+ .flags = CLK_SET_RATE_PARENT,
1881+ .ops = &clk_branch2_ops,
1882+ },
1883+ },
1884+};
1885+
1886+static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1887+ .halt_reg = 0xc004,
1888+ .halt_check = BRANCH_HALT,
1889+ .clkr = {
1890+ .enable_reg = 0xc004,
1891+ .enable_mask = BIT(0),
1892+ .hw.init = &(struct clk_init_data) {
1893+ .name = "gcc_blsp2_qup1_spi_apps_clk",
1894+ .parent_hws = (const struct clk_hw *[]) {
1895+ &blsp2_qup1_spi_apps_clk_src.clkr.hw,
1896+ },
1897+ .num_parents = 1,
1898+ .flags = CLK_SET_RATE_PARENT,
1899+ .ops = &clk_branch2_ops,
1900+ },
1901+ },
1902+};
1903+
1904+static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1905+ .halt_reg = 0xd010,
1906+ .halt_check = BRANCH_HALT,
1907+ .clkr = {
1908+ .enable_reg = 0xd010,
1909+ .enable_mask = BIT(0),
1910+ .hw.init = &(struct clk_init_data) {
1911+ .name = "gcc_blsp2_qup2_i2c_apps_clk",
1912+ .parent_hws = (const struct clk_hw *[]) {
1913+ &blsp2_qup2_i2c_apps_clk_src.clkr.hw,
1914+ },
1915+ .num_parents = 1,
1916+ .flags = CLK_SET_RATE_PARENT,
1917+ .ops = &clk_branch2_ops,
1918+ },
1919+ },
1920+};
1921+
1922+static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1923+ .halt_reg = 0xd00c,
1924+ .halt_check = BRANCH_HALT,
1925+ .clkr = {
1926+ .enable_reg = 0xd00c,
1927+ .enable_mask = BIT(0),
1928+ .hw.init = &(struct clk_init_data) {
1929+ .name = "gcc_blsp2_qup2_spi_apps_clk",
1930+ .parent_hws = (const struct clk_hw *[]) {
1931+ &blsp2_qup2_spi_apps_clk_src.clkr.hw,
1932+ },
1933+ .num_parents = 1,
1934+ .flags = CLK_SET_RATE_PARENT,
1935+ .ops = &clk_branch2_ops,
1936+ },
1937+ },
1938+};
1939+
1940+static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1941+ .halt_reg = 0xf020,
1942+ .halt_check = BRANCH_HALT,
1943+ .clkr = {
1944+ .enable_reg = 0xf020,
1945+ .enable_mask = BIT(0),
1946+ .hw.init = &(struct clk_init_data) {
1947+ .name = "gcc_blsp2_qup3_i2c_apps_clk",
1948+ .parent_hws = (const struct clk_hw *[]) {
1949+ &blsp2_qup3_i2c_apps_clk_src.clkr.hw,
1950+ },
1951+ .num_parents = 1,
1952+ .flags = CLK_SET_RATE_PARENT,
1953+ .ops = &clk_branch2_ops,
1954+ },
1955+ },
1956+};
1957+
1958+static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1959+ .halt_reg = 0xf01c,
1960+ .halt_check = BRANCH_HALT,
1961+ .clkr = {
1962+ .enable_reg = 0xf01c,
1963+ .enable_mask = BIT(0),
1964+ .hw.init = &(struct clk_init_data) {
1965+ .name = "gcc_blsp2_qup3_spi_apps_clk",
1966+ .parent_hws = (const struct clk_hw *[]) {
1967+ &blsp2_qup3_spi_apps_clk_src.clkr.hw,
1968+ },
1969+ .num_parents = 1,
1970+ .flags = CLK_SET_RATE_PARENT,
1971+ .ops = &clk_branch2_ops,
1972+ },
1973+ },
1974+};
1975+
1976+static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1977+ .halt_reg = 0x18020,
1978+ .halt_check = BRANCH_HALT,
1979+ .clkr = {
1980+ .enable_reg = 0x18020,
1981+ .enable_mask = BIT(0),
1982+ .hw.init = &(struct clk_init_data) {
1983+ .name = "gcc_blsp2_qup4_i2c_apps_clk",
1984+ .parent_hws = (const struct clk_hw *[]) {
1985+ &blsp2_qup4_i2c_apps_clk_src.clkr.hw,
1986+ },
1987+ .num_parents = 1,
1988+ .flags = CLK_SET_RATE_PARENT,
1989+ .ops = &clk_branch2_ops,
1990+ },
1991+ },
1992+};
1993+
1994+static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1995+ .halt_reg = 0x1801c,
1996+ .halt_check = BRANCH_HALT,
1997+ .clkr = {
1998+ .enable_reg = 0x1801c,
1999+ .enable_mask = BIT(0),
2000+ .hw.init = &(struct clk_init_data) {
2001+ .name = "gcc_blsp2_qup4_spi_apps_clk",
2002+ .parent_hws = (const struct clk_hw *[]) {
2003+ &blsp2_qup4_spi_apps_clk_src.clkr.hw,
2004+ },
2005+ .num_parents = 1,
2006+ .flags = CLK_SET_RATE_PARENT,
2007+ .ops = &clk_branch2_ops,
2008+ },
2009+ },
2010+};
2011+
2012+static struct clk_branch gcc_blsp2_uart1_apps_clk = {
2013+ .halt_reg = 0xc03c,
2014+ .halt_check = BRANCH_HALT,
2015+ .clkr = {
2016+ .enable_reg = 0xc03c,
2017+ .enable_mask = BIT(0),
2018+ .hw.init = &(struct clk_init_data) {
2019+ .name = "gcc_blsp2_uart1_apps_clk",
2020+ .parent_hws = (const struct clk_hw *[]) {
2021+ &blsp2_uart1_apps_clk_src.clkr.hw,
2022+ },
2023+ .num_parents = 1,
2024+ .flags = CLK_SET_RATE_PARENT,
2025+ .ops = &clk_branch2_ops,
2026+ },
2027+ },
2028+};
2029+
2030+static struct clk_branch gcc_blsp2_uart2_apps_clk = {
2031+ .halt_reg = 0xd02c,
2032+ .halt_check = BRANCH_HALT,
2033+ .clkr = {
2034+ .enable_reg = 0xd02c,
2035+ .enable_mask = BIT(0),
2036+ .hw.init = &(struct clk_init_data) {
2037+ .name = "gcc_blsp2_uart2_apps_clk",
2038+ .parent_hws = (const struct clk_hw *[]) {
2039+ &blsp2_uart2_apps_clk_src.clkr.hw,
2040+ },
2041+ .num_parents = 1,
2042+ .flags = CLK_SET_RATE_PARENT,
2043+ .ops = &clk_branch2_ops,
2044+ },
2045+ },
2046+};
2047+
2048+static struct clk_branch gcc_camss_cci_ahb_clk = {
2049+ .halt_reg = 0x5101c,
2050+ .clkr = {
2051+ .enable_reg = 0x5101c,
2052+ .enable_mask = BIT(0),
2053+ .hw.init = &(struct clk_init_data) {
2054+ .name = "gcc_camss_cci_ahb_clk",
2055+ .parent_hws = (const struct clk_hw *[]) {
2056+ &camss_top_ahb_clk_src.clkr.hw,
2057+ },
2058+ .num_parents = 1,
2059+ .flags = CLK_SET_RATE_PARENT,
2060+ .ops = &clk_branch2_ops,
2061+ },
2062+ },
2063+};
2064+
2065+static struct clk_branch gcc_camss_cci_clk = {
2066+ .halt_reg = 0x51018,
2067+ .clkr = {
2068+ .enable_reg = 0x51018,
2069+ .enable_mask = BIT(0),
2070+ .hw.init = &(struct clk_init_data) {
2071+ .name = "gcc_camss_cci_clk",
2072+ .parent_hws = (const struct clk_hw *[]) {
2073+ &cci_clk_src.clkr.hw,
2074+ },
2075+ .num_parents = 1,
2076+ .flags = CLK_SET_RATE_PARENT,
2077+ .ops = &clk_branch2_ops,
2078+ },
2079+ },
2080+};
2081+
2082+static struct clk_branch gcc_camss_cpp_ahb_clk = {
2083+ .halt_reg = 0x58040,
2084+ .clkr = {
2085+ .enable_reg = 0x58040,
2086+ .enable_mask = BIT(0),
2087+ .hw.init = &(struct clk_init_data) {
2088+ .name = "gcc_camss_cpp_ahb_clk",
2089+ .parent_hws = (const struct clk_hw *[]) {
2090+ &camss_top_ahb_clk_src.clkr.hw,
2091+ },
2092+ .num_parents = 1,
2093+ .flags = CLK_SET_RATE_PARENT,
2094+ .ops = &clk_branch2_ops,
2095+ },
2096+ },
2097+};
2098+
2099+static struct clk_branch gcc_camss_cpp_axi_clk = {
2100+ .halt_reg = 0x58064,
2101+ .clkr = {
2102+ .enable_reg = 0x58064,
2103+ .enable_mask = BIT(0),
2104+ .hw.init = &(struct clk_init_data) {
2105+ .name = "gcc_camss_cpp_axi_clk",
2106+ .ops = &clk_branch2_ops,
2107+ },
2108+ },
2109+};
2110+
2111+static struct clk_branch gcc_camss_cpp_clk = {
2112+ .halt_reg = 0x5803c,
2113+ .clkr = {
2114+ .enable_reg = 0x5803c,
2115+ .enable_mask = BIT(0),
2116+ .hw.init = &(struct clk_init_data) {
2117+ .name = "gcc_camss_cpp_clk",
2118+ .parent_hws = (const struct clk_hw *[]) {
2119+ &cpp_clk_src.clkr.hw,
2120+ },
2121+ .num_parents = 1,
2122+ .flags = CLK_SET_RATE_PARENT,
2123+ .ops = &clk_branch2_ops,
2124+ },
2125+ },
2126+};
2127+
2128+static struct clk_branch gcc_camss_csi0_ahb_clk = {
2129+ .halt_reg = 0x4e040,
2130+ .clkr = {
2131+ .enable_reg = 0x4e040,
2132+ .enable_mask = BIT(0),
2133+ .hw.init = &(struct clk_init_data) {
2134+ .name = "gcc_camss_csi0_ahb_clk",
2135+ .parent_hws = (const struct clk_hw *[]) {
2136+ &camss_top_ahb_clk_src.clkr.hw,
2137+ },
2138+ .num_parents = 1,
2139+ .flags = CLK_SET_RATE_PARENT,
2140+ .ops = &clk_branch2_ops,
2141+ },
2142+ },
2143+};
2144+
2145+static struct clk_branch gcc_camss_csi0_clk = {
2146+ .halt_reg = 0x4e03c,
2147+ .clkr = {
2148+ .enable_reg = 0x4e03c,
2149+ .enable_mask = BIT(0),
2150+ .hw.init = &(struct clk_init_data) {
2151+ .name = "gcc_camss_csi0_clk",
2152+ .parent_hws = (const struct clk_hw *[]) {
2153+ &csi0_clk_src.clkr.hw,
2154+ },
2155+ .num_parents = 1,
2156+ .flags = CLK_SET_RATE_PARENT,
2157+ .ops = &clk_branch2_ops,
2158+ },
2159+ },
2160+};
2161+
2162+static struct clk_branch gcc_camss_csi0phy_clk = {
2163+ .halt_reg = 0x4e048,
2164+ .clkr = {
2165+ .enable_reg = 0x4e048,
2166+ .enable_mask = BIT(0),
2167+ .hw.init = &(struct clk_init_data) {
2168+ .name = "gcc_camss_csi0phy_clk",
2169+ .parent_hws = (const struct clk_hw *[]) {
2170+ &csi0_clk_src.clkr.hw,
2171+ },
2172+ .num_parents = 1,
2173+ .flags = CLK_SET_RATE_PARENT,
2174+ .ops = &clk_branch2_ops,
2175+ },
2176+ },
2177+};
2178+
2179+static struct clk_branch gcc_camss_csi0pix_clk = {
2180+ .halt_reg = 0x4e058,
2181+ .clkr = {
2182+ .enable_reg = 0x4e058,
2183+ .enable_mask = BIT(0),
2184+ .hw.init = &(struct clk_init_data) {
2185+ .name = "gcc_camss_csi0pix_clk",
2186+ .parent_hws = (const struct clk_hw *[]) {
2187+ &csi0_clk_src.clkr.hw,
2188+ },
2189+ .num_parents = 1,
2190+ .flags = CLK_SET_RATE_PARENT,
2191+ .ops = &clk_branch2_ops,
2192+ },
2193+ },
2194+};
2195+
2196+static struct clk_branch gcc_camss_csi0rdi_clk = {
2197+ .halt_reg = 0x4e050,
2198+ .clkr = {
2199+ .enable_reg = 0x4e050,
2200+ .enable_mask = BIT(0),
2201+ .hw.init = &(struct clk_init_data) {
2202+ .name = "gcc_camss_csi0rdi_clk",
2203+ .parent_hws = (const struct clk_hw *[]) {
2204+ &csi0_clk_src.clkr.hw,
2205+ },
2206+ .num_parents = 1,
2207+ .flags = CLK_SET_RATE_PARENT,
2208+ .ops = &clk_branch2_ops,
2209+ },
2210+ },
2211+};
2212+
2213+static struct clk_branch gcc_camss_csi1_ahb_clk = {
2214+ .halt_reg = 0x4f040,
2215+ .clkr = {
2216+ .enable_reg = 0x4f040,
2217+ .enable_mask = BIT(0),
2218+ .hw.init = &(struct clk_init_data) {
2219+ .name = "gcc_camss_csi1_ahb_clk",
2220+ .parent_hws = (const struct clk_hw *[]) {
2221+ &camss_top_ahb_clk_src.clkr.hw,
2222+ },
2223+ .num_parents = 1,
2224+ .flags = CLK_SET_RATE_PARENT,
2225+ .ops = &clk_branch2_ops,
2226+ },
2227+ },
2228+};
2229+
2230+static struct clk_branch gcc_camss_csi1_clk = {
2231+ .halt_reg = 0x4f03c,
2232+ .clkr = {
2233+ .enable_reg = 0x4f03c,
2234+ .enable_mask = BIT(0),
2235+ .hw.init = &(struct clk_init_data) {
2236+ .name = "gcc_camss_csi1_clk",
2237+ .parent_hws = (const struct clk_hw *[]) {
2238+ &csi1_clk_src.clkr.hw,
2239+ },
2240+ .num_parents = 1,
2241+ .flags = CLK_SET_RATE_PARENT,
2242+ .ops = &clk_branch2_ops,
2243+ },
2244+ },
2245+};
2246+
2247+static struct clk_branch gcc_camss_csi1phy_clk = {
2248+ .halt_reg = 0x4f048,
2249+ .clkr = {
2250+ .enable_reg = 0x4f048,
2251+ .enable_mask = BIT(0),
2252+ .hw.init = &(struct clk_init_data) {
2253+ .name = "gcc_camss_csi1phy_clk",
2254+ .parent_hws = (const struct clk_hw *[]) {
2255+ &csi1_clk_src.clkr.hw,
2256+ },
2257+ .num_parents = 1,
2258+ .flags = CLK_SET_RATE_PARENT,
2259+ .ops = &clk_branch2_ops,
2260+ },
2261+ },
2262+};
2263+
2264+static struct clk_branch gcc_camss_csi1pix_clk = {
2265+ .halt_reg = 0x4f058,
2266+ .clkr = {
2267+ .enable_reg = 0x4f058,
2268+ .enable_mask = BIT(0),
2269+ .hw.init = &(struct clk_init_data) {
2270+ .name = "gcc_camss_csi1pix_clk",
2271+ .parent_hws = (const struct clk_hw *[]) {
2272+ &csi1_clk_src.clkr.hw,
2273+ },
2274+ .num_parents = 1,
2275+ .flags = CLK_SET_RATE_PARENT,
2276+ .ops = &clk_branch2_ops,
2277+ },
2278+ },
2279+};
2280+
2281+static struct clk_branch gcc_camss_csi1rdi_clk = {
2282+ .halt_reg = 0x4f050,
2283+ .clkr = {
2284+ .enable_reg = 0x4f050,
2285+ .enable_mask = BIT(0),
2286+ .hw.init = &(struct clk_init_data) {
2287+ .name = "gcc_camss_csi1rdi_clk",
2288+ .parent_hws = (const struct clk_hw *[]) {
2289+ &csi1_clk_src.clkr.hw,
2290+ },
2291+ .num_parents = 1,
2292+ .flags = CLK_SET_RATE_PARENT,
2293+ .ops = &clk_branch2_ops,
2294+ },
2295+ },
2296+};
2297+
2298+static struct clk_branch gcc_camss_csi2_ahb_clk = {
2299+ .halt_reg = 0x3c040,
2300+ .clkr = {
2301+ .enable_reg = 0x3c040,
2302+ .enable_mask = BIT(0),
2303+ .hw.init = &(struct clk_init_data) {
2304+ .name = "gcc_camss_csi2_ahb_clk",
2305+ .parent_hws = (const struct clk_hw *[]) {
2306+ &camss_top_ahb_clk_src.clkr.hw,
2307+ },
2308+ .num_parents = 1,
2309+ .flags = CLK_SET_RATE_PARENT,
2310+ .ops = &clk_branch2_ops,
2311+ },
2312+ },
2313+};
2314+
2315+static struct clk_branch gcc_camss_csi2_clk = {
2316+ .halt_reg = 0x3c03c,
2317+ .clkr = {
2318+ .enable_reg = 0x3c03c,
2319+ .enable_mask = BIT(0),
2320+ .hw.init = &(struct clk_init_data) {
2321+ .name = "gcc_camss_csi2_clk",
2322+ .parent_hws = (const struct clk_hw *[]) {
2323+ &csi2_clk_src.clkr.hw,
2324+ },
2325+ .num_parents = 1,
2326+ .flags = CLK_SET_RATE_PARENT,
2327+ .ops = &clk_branch2_ops,
2328+ },
2329+ },
2330+};
2331+
2332+static struct clk_branch gcc_camss_csi2phy_clk = {
2333+ .halt_reg = 0x3c048,
2334+ .clkr = {
2335+ .enable_reg = 0x3c048,
2336+ .enable_mask = BIT(0),
2337+ .hw.init = &(struct clk_init_data) {
2338+ .name = "gcc_camss_csi2phy_clk",
2339+ .parent_hws = (const struct clk_hw *[]) {
2340+ &csi2_clk_src.clkr.hw,
2341+ },
2342+ .num_parents = 1,
2343+ .flags = CLK_SET_RATE_PARENT,
2344+ .ops = &clk_branch2_ops,
2345+ },
2346+ },
2347+};
2348+
2349+static struct clk_branch gcc_camss_csi2pix_clk = {
2350+ .halt_reg = 0x3c058,
2351+ .clkr = {
2352+ .enable_reg = 0x3c058,
2353+ .enable_mask = BIT(0),
2354+ .hw.init = &(struct clk_init_data) {
2355+ .name = "gcc_camss_csi2pix_clk",
2356+ .parent_hws = (const struct clk_hw *[]) {
2357+ &csi2_clk_src.clkr.hw,
2358+ },
2359+ .num_parents = 1,
2360+ .flags = CLK_SET_RATE_PARENT,
2361+ .ops = &clk_branch2_ops,
2362+ },
2363+ },
2364+};
2365+
2366+static struct clk_branch gcc_camss_csi2rdi_clk = {
2367+ .halt_reg = 0x3c050,
2368+ .clkr = {
2369+ .enable_reg = 0x3c050,
2370+ .enable_mask = BIT(0),
2371+ .hw.init = &(struct clk_init_data) {
2372+ .name = "gcc_camss_csi2rdi_clk",
2373+ .parent_hws = (const struct clk_hw *[]) {
2374+ &csi2_clk_src.clkr.hw,
2375+ },
2376+ .num_parents = 1,
2377+ .flags = CLK_SET_RATE_PARENT,
2378+ .ops = &clk_branch2_ops,
2379+ },
2380+ },
2381+};
2382+
2383+static struct clk_branch gcc_camss_csi_vfe0_clk = {
2384+ .halt_reg = 0x58050,
2385+ .clkr = {
2386+ .enable_reg = 0x58050,
2387+ .enable_mask = BIT(0),
2388+ .hw.init = &(struct clk_init_data) {
2389+ .name = "gcc_camss_csi_vfe0_clk",
2390+ .parent_hws = (const struct clk_hw *[]) {
2391+ &vfe0_clk_src.clkr.hw,
2392+ },
2393+ .num_parents = 1,
2394+ .flags = CLK_SET_RATE_PARENT,
2395+ .ops = &clk_branch2_ops,
2396+ },
2397+ },
2398+};
2399+
2400+static struct clk_branch gcc_camss_csi_vfe1_clk = {
2401+ .halt_reg = 0x58074,
2402+ .clkr = {
2403+ .enable_reg = 0x58074,
2404+ .enable_mask = BIT(0),
2405+ .hw.init = &(struct clk_init_data) {
2406+ .name = "gcc_camss_csi_vfe1_clk",
2407+ .parent_hws = (const struct clk_hw *[]) {
2408+ &vfe1_clk_src.clkr.hw,
2409+ },
2410+ .num_parents = 1,
2411+ .flags = CLK_SET_RATE_PARENT,
2412+ .ops = &clk_branch2_ops,
2413+ },
2414+ },
2415+};
2416+
2417+static struct clk_branch gcc_camss_gp0_clk = {
2418+ .halt_reg = 0x54018,
2419+ .clkr = {
2420+ .enable_reg = 0x54018,
2421+ .enable_mask = BIT(0),
2422+ .hw.init = &(struct clk_init_data) {
2423+ .name = "gcc_camss_gp0_clk",
2424+ .parent_hws = (const struct clk_hw *[]) {
2425+ &camss_gp0_clk_src.clkr.hw,
2426+ },
2427+ .num_parents = 1,
2428+ .flags = CLK_SET_RATE_PARENT,
2429+ .ops = &clk_branch2_ops,
2430+ },
2431+ },
2432+};
2433+
2434+static struct clk_branch gcc_camss_gp1_clk = {
2435+ .halt_reg = 0x55018,
2436+ .clkr = {
2437+ .enable_reg = 0x55018,
2438+ .enable_mask = BIT(0),
2439+ .hw.init = &(struct clk_init_data) {
2440+ .name = "gcc_camss_gp1_clk",
2441+ .parent_hws = (const struct clk_hw *[]) {
2442+ &camss_gp1_clk_src.clkr.hw,
2443+ },
2444+ .num_parents = 1,
2445+ .flags = CLK_SET_RATE_PARENT,
2446+ .ops = &clk_branch2_ops,
2447+ },
2448+ },
2449+};
2450+
2451+static struct clk_branch gcc_camss_ispif_ahb_clk = {
2452+ .halt_reg = 0x50004,
2453+ .clkr = {
2454+ .enable_reg = 0x50004,
2455+ .enable_mask = BIT(0),
2456+ .hw.init = &(struct clk_init_data) {
2457+ .name = "gcc_camss_ispif_ahb_clk",
2458+ .parent_hws = (const struct clk_hw *[]) {
2459+ &camss_top_ahb_clk_src.clkr.hw,
2460+ },
2461+ .num_parents = 1,
2462+ .flags = CLK_SET_RATE_PARENT,
2463+ .ops = &clk_branch2_ops,
2464+ },
2465+ },
2466+};
2467+
2468+static struct clk_branch gcc_camss_jpeg0_clk = {
2469+ .halt_reg = 0x57020,
2470+ .halt_check = BRANCH_HALT,
2471+ .clkr = {
2472+ .enable_reg = 0x57020,
2473+ .enable_mask = BIT(0),
2474+ .hw.init = &(struct clk_init_data) {
2475+ .name = "gcc_camss_jpeg0_clk",
2476+ .parent_hws = (const struct clk_hw *[]) {
2477+ &jpeg0_clk_src.clkr.hw,
2478+ },
2479+ .num_parents = 1,
2480+ .flags = CLK_SET_RATE_PARENT,
2481+ .ops = &clk_branch2_ops,
2482+ },
2483+ },
2484+};
2485+
2486+static struct clk_branch gcc_camss_jpeg_ahb_clk = {
2487+ .halt_reg = 0x57024,
2488+ .clkr = {
2489+ .enable_reg = 0x57024,
2490+ .enable_mask = BIT(0),
2491+ .hw.init = &(struct clk_init_data) {
2492+ .name = "gcc_camss_jpeg_ahb_clk",
2493+ .parent_hws = (const struct clk_hw *[]) {
2494+ &camss_top_ahb_clk_src.clkr.hw,
2495+ },
2496+ .num_parents = 1,
2497+ .flags = CLK_SET_RATE_PARENT,
2498+ .ops = &clk_branch2_ops,
2499+ },
2500+ },
2501+};
2502+
2503+static struct clk_branch gcc_camss_jpeg_axi_clk = {
2504+ .halt_reg = 0x57028,
2505+ .clkr = {
2506+ .enable_reg = 0x57028,
2507+ .enable_mask = BIT(0),
2508+ .hw.init = &(struct clk_init_data) {
2509+ .name = "gcc_camss_jpeg_axi_clk",
2510+ .ops = &clk_branch2_ops,
2511+ },
2512+ },
2513+};
2514+
2515+static struct clk_branch gcc_camss_mclk0_clk = {
2516+ .halt_reg = 0x52018,
2517+ .clkr = {
2518+ .enable_reg = 0x52018,
2519+ .enable_mask = BIT(0),
2520+ .hw.init = &(struct clk_init_data) {
2521+ .name = "gcc_camss_mclk0_clk",
2522+ .parent_hws = (const struct clk_hw *[]) {
2523+ &mclk0_clk_src.clkr.hw,
2524+ },
2525+ .num_parents = 1,
2526+ .flags = CLK_SET_RATE_PARENT,
2527+ .ops = &clk_branch2_ops,
2528+ },
2529+ },
2530+};
2531+
2532+static struct clk_branch gcc_camss_mclk1_clk = {
2533+ .halt_reg = 0x53018,
2534+ .clkr = {
2535+ .enable_reg = 0x53018,
2536+ .enable_mask = BIT(0),
2537+ .hw.init = &(struct clk_init_data) {
2538+ .name = "gcc_camss_mclk1_clk",
2539+ .parent_hws = (const struct clk_hw *[]) {
2540+ &mclk1_clk_src.clkr.hw,
2541+ },
2542+ .num_parents = 1,
2543+ .flags = CLK_SET_RATE_PARENT,
2544+ .ops = &clk_branch2_ops,
2545+ },
2546+ },
2547+};
2548+
2549+static struct clk_branch gcc_camss_mclk2_clk = {
2550+ .halt_reg = 0x5c018,
2551+ .clkr = {
2552+ .enable_reg = 0x5c018,
2553+ .enable_mask = BIT(0),
2554+ .hw.init = &(struct clk_init_data) {
2555+ .name = "gcc_camss_mclk2_clk",
2556+ .parent_hws = (const struct clk_hw *[]) {
2557+ &mclk2_clk_src.clkr.hw,
2558+ },
2559+ .num_parents = 1,
2560+ .ops = &clk_branch2_ops,
2561+ },
2562+ },
2563+};
2564+
2565+static struct clk_branch gcc_camss_micro_ahb_clk = {
2566+ .halt_reg = 0x5600c,
2567+ .clkr = {
2568+ .enable_reg = 0x5600c,
2569+ .enable_mask = BIT(0),
2570+ .hw.init = &(struct clk_init_data) {
2571+ .name = "gcc_camss_micro_ahb_clk",
2572+ .parent_hws = (const struct clk_hw *[]) {
2573+ &camss_top_ahb_clk_src.clkr.hw,
2574+ },
2575+ .num_parents = 1,
2576+ .flags = CLK_SET_RATE_PARENT,
2577+ .ops = &clk_branch2_ops,
2578+ },
2579+ },
2580+};
2581+
2582+static struct clk_branch gcc_camss_csi0phytimer_clk = {
2583+ .halt_reg = 0x4e01c,
2584+ .clkr = {
2585+ .enable_reg = 0x4e01c,
2586+ .enable_mask = BIT(0),
2587+ .hw.init = &(struct clk_init_data) {
2588+ .name = "gcc_camss_csi0phytimer_clk",
2589+ .parent_hws = (const struct clk_hw *[]) {
2590+ &csi0phytimer_clk_src.clkr.hw,
2591+ },
2592+ .num_parents = 1,
2593+ .flags = CLK_SET_RATE_PARENT,
2594+ .ops = &clk_branch2_ops,
2595+ },
2596+ },
2597+};
2598+
2599+static struct clk_branch gcc_camss_csi1phytimer_clk = {
2600+ .halt_reg = 0x4f01c,
2601+ .clkr = {
2602+ .enable_reg = 0x4f01c,
2603+ .enable_mask = BIT(0),
2604+ .hw.init = &(struct clk_init_data) {
2605+ .name = "gcc_camss_csi1phytimer_clk",
2606+ .parent_hws = (const struct clk_hw *[]) {
2607+ &csi1phytimer_clk_src.clkr.hw,
2608+ },
2609+ .num_parents = 1,
2610+ .flags = CLK_SET_RATE_PARENT,
2611+ .ops = &clk_branch2_ops,
2612+ },
2613+ },
2614+};
2615+
2616+static struct clk_branch gcc_camss_ahb_clk = {
2617+ .halt_reg = 0x56004,
2618+ .clkr = {
2619+ .enable_reg = 0x56004,
2620+ .enable_mask = BIT(0),
2621+ .hw.init = &(struct clk_init_data) {
2622+ .name = "gcc_camss_ahb_clk",
2623+ .ops = &clk_branch2_ops,
2624+ },
2625+ },
2626+};
2627+
2628+static struct clk_branch gcc_camss_top_ahb_clk = {
2629+ .halt_reg = 0x5a014,
2630+ .clkr = {
2631+ .enable_reg = 0x5a014,
2632+ .enable_mask = BIT(0),
2633+ .hw.init = &(struct clk_init_data) {
2634+ .name = "gcc_camss_top_ahb_clk",
2635+ .parent_hws = (const struct clk_hw *[]) {
2636+ &camss_top_ahb_clk_src.clkr.hw,
2637+ },
2638+ .num_parents = 1,
2639+ .flags = CLK_SET_RATE_PARENT,
2640+ .ops = &clk_branch2_ops,
2641+ },
2642+ },
2643+};
2644+
2645+static struct clk_branch gcc_camss_vfe0_clk = {
2646+ .halt_reg = 0x58038,
2647+ .clkr = {
2648+ .enable_reg = 0x58038,
2649+ .enable_mask = BIT(0),
2650+ .hw.init = &(struct clk_init_data) {
2651+ .name = "gcc_camss_vfe0_clk",
2652+ .parent_hws = (const struct clk_hw *[]) {
2653+ &vfe0_clk_src.clkr.hw,
2654+ },
2655+ .num_parents = 1,
2656+ .flags = CLK_SET_RATE_PARENT,
2657+ .ops = &clk_branch2_ops,
2658+ },
2659+ },
2660+};
2661+
2662+static struct clk_branch gcc_camss_vfe_ahb_clk = {
2663+ .halt_reg = 0x58044,
2664+ .clkr = {
2665+ .enable_reg = 0x58044,
2666+ .enable_mask = BIT(0),
2667+ .hw.init = &(struct clk_init_data) {
2668+ .name = "gcc_camss_vfe_ahb_clk",
2669+ .parent_hws = (const struct clk_hw *[]) {
2670+ &camss_top_ahb_clk_src.clkr.hw,
2671+ },
2672+ .num_parents = 1,
2673+ .flags = CLK_SET_RATE_PARENT,
2674+ .ops = &clk_branch2_ops,
2675+ },
2676+ },
2677+};
2678+
2679+static struct clk_branch gcc_camss_vfe_axi_clk = {
2680+ .halt_reg = 0x58048,
2681+ .clkr = {
2682+ .enable_reg = 0x58048,
2683+ .enable_mask = BIT(0),
2684+ .hw.init = &(struct clk_init_data) {
2685+ .name = "gcc_camss_vfe_axi_clk",
2686+ .ops = &clk_branch2_ops,
2687+ },
2688+ },
2689+};
2690+
2691+static struct clk_branch gcc_camss_vfe1_ahb_clk = {
2692+ .halt_reg = 0x58060,
2693+ .clkr = {
2694+ .enable_reg = 0x58060,
2695+ .enable_mask = BIT(0),
2696+ .hw.init = &(struct clk_init_data) {
2697+ .name = "gcc_camss_vfe1_ahb_clk",
2698+ .parent_hws = (const struct clk_hw *[]) {
2699+ &camss_top_ahb_clk_src.clkr.hw,
2700+ },
2701+ .num_parents = 1,
2702+ .flags = CLK_SET_RATE_PARENT,
2703+ .ops = &clk_branch2_ops,
2704+ },
2705+ },
2706+};
2707+
2708+static struct clk_branch gcc_camss_vfe1_axi_clk = {
2709+ .halt_reg = 0x58068,
2710+ .clkr = {
2711+ .enable_reg = 0x58068,
2712+ .enable_mask = BIT(0),
2713+ .hw.init = &(struct clk_init_data) {
2714+ .name = "gcc_camss_vfe1_axi_clk",
2715+ .ops = &clk_branch2_ops,
2716+ },
2717+ },
2718+};
2719+
2720+static struct clk_branch gcc_camss_vfe1_clk = {
2721+ .halt_reg = 0x5805c,
2722+ .clkr = {
2723+ .enable_reg = 0x5805c,
2724+ .enable_mask = BIT(0),
2725+ .hw.init = &(struct clk_init_data) {
2726+ .name = "gcc_camss_vfe1_clk",
2727+ .parent_hws = (const struct clk_hw *[]) {
2728+ &vfe1_clk_src.clkr.hw,
2729+ },
2730+ .num_parents = 1,
2731+ .flags = CLK_SET_RATE_PARENT,
2732+ .ops = &clk_branch2_ops,
2733+ },
2734+ },
2735+};
2736+
2737+static struct clk_branch gcc_dcc_clk = {
2738+ .halt_reg = 0x77004,
2739+ .clkr = {
2740+ .enable_reg = 0x77004,
2741+ .enable_mask = BIT(0),
2742+ .hw.init = &(struct clk_init_data) {
2743+ .name = "gcc_dcc_clk",
2744+ .ops = &clk_branch2_ops,
2745+ },
2746+ },
2747+};
2748+
2749+static struct clk_branch gcc_oxili_gmem_clk = {
2750+ .halt_reg = 0x59024,
2751+ .clkr = {
2752+ .enable_reg = 0x59024,
2753+ .enable_mask = BIT(0),
2754+ .hw.init = &(struct clk_init_data) {
2755+ .name = "gcc_oxili_gmem_clk",
2756+ .parent_hws = (const struct clk_hw *[]) {
2757+ &gfx3d_clk_src.clkr.hw,
2758+ },
2759+ .num_parents = 1,
2760+ .flags = CLK_SET_RATE_PARENT,
2761+ .ops = &clk_branch2_ops,
2762+ },
2763+ },
2764+};
2765+
2766+static struct clk_branch gcc_gp1_clk = {
2767+ .halt_reg = 0x8000,
2768+ .halt_check = BRANCH_HALT,
2769+ .clkr = {
2770+ .enable_reg = 0x8000,
2771+ .enable_mask = BIT(0),
2772+ .hw.init = &(struct clk_init_data) {
2773+ .name = "gcc_gp1_clk",
2774+ .parent_hws = (const struct clk_hw *[]) {
2775+ &gp1_clk_src.clkr.hw,
2776+ },
2777+ .num_parents = 1,
2778+ .flags = CLK_SET_RATE_PARENT,
2779+ .ops = &clk_branch2_ops,
2780+ },
2781+ },
2782+};
2783+
2784+static struct clk_branch gcc_gp2_clk = {
2785+ .halt_reg = 0x9000,
2786+ .halt_check = BRANCH_HALT,
2787+ .clkr = {
2788+ .enable_reg = 0x9000,
2789+ .enable_mask = BIT(0),
2790+ .hw.init = &(struct clk_init_data) {
2791+ .name = "gcc_gp2_clk",
2792+ .parent_hws = (const struct clk_hw *[]) {
2793+ &gp2_clk_src.clkr.hw,
2794+ },
2795+ .num_parents = 1,
2796+ .flags = CLK_SET_RATE_PARENT,
2797+ .ops = &clk_branch2_ops,
2798+ },
2799+ },
2800+};
2801+
2802+static struct clk_branch gcc_gp3_clk = {
2803+ .halt_reg = 0xa000,
2804+ .halt_check = BRANCH_HALT,
2805+ .clkr = {
2806+ .enable_reg = 0xa000,
2807+ .enable_mask = BIT(0),
2808+ .hw.init = &(struct clk_init_data) {
2809+ .name = "gcc_gp3_clk",
2810+ .parent_hws = (const struct clk_hw *[]) {
2811+ &gp3_clk_src.clkr.hw,
2812+ },
2813+ .num_parents = 1,
2814+ .flags = CLK_SET_RATE_PARENT,
2815+ .ops = &clk_branch2_ops,
2816+ },
2817+ },
2818+};
2819+
2820+static struct clk_branch gcc_mdss_ahb_clk = {
2821+ .halt_reg = 0x4d07c,
2822+ .halt_check = BRANCH_HALT,
2823+ .clkr = {
2824+ .enable_reg = 0x4d07c,
2825+ .enable_mask = BIT(0),
2826+ .hw.init = &(struct clk_init_data) {
2827+ .name = "gcc_mdss_ahb_clk",
2828+ .ops = &clk_branch2_ops,
2829+ },
2830+ },
2831+};
2832+
2833+static struct clk_branch gcc_mdss_axi_clk = {
2834+ .halt_reg = 0x4d080,
2835+ .halt_check = BRANCH_HALT,
2836+ .clkr = {
2837+ .enable_reg = 0x4d080,
2838+ .enable_mask = BIT(0),
2839+ .hw.init = &(struct clk_init_data) {
2840+ .name = "gcc_mdss_axi_clk",
2841+ .ops = &clk_branch2_ops,
2842+ },
2843+ },
2844+};
2845+
2846+static struct clk_branch gcc_mdss_byte0_clk = {
2847+ .halt_reg = 0x4d094,
2848+ .halt_check = BRANCH_HALT,
2849+ .clkr = {
2850+ .enable_reg = 0x4d094,
2851+ .enable_mask = BIT(0),
2852+ .hw.init = &(struct clk_init_data) {
2853+ .name = "gcc_mdss_byte0_clk",
2854+ .parent_hws = (const struct clk_hw *[]) {
2855+ &byte0_clk_src.clkr.hw,
2856+ },
2857+ .num_parents = 1,
2858+ .flags = CLK_SET_RATE_PARENT,
2859+ .ops = &clk_branch2_ops,
2860+ },
2861+ },
2862+};
2863+
2864+static struct clk_branch gcc_mdss_byte1_clk = {
2865+ .halt_reg = 0x4d0a0,
2866+ .halt_check = BRANCH_HALT,
2867+ .clkr = {
2868+ .enable_reg = 0x4d0a0,
2869+ .enable_mask = BIT(0),
2870+ .hw.init = &(struct clk_init_data) {
2871+ .name = "gcc_mdss_byte1_clk",
2872+ .parent_hws = (const struct clk_hw *[]) {
2873+ &byte1_clk_src.clkr.hw,
2874+ },
2875+ .num_parents = 1,
2876+ .flags = CLK_SET_RATE_PARENT,
2877+ .ops = &clk_branch2_ops,
2878+ },
2879+ },
2880+};
2881+
2882+static struct clk_branch gcc_mdss_esc0_clk = {
2883+ .halt_reg = 0x4d098,
2884+ .halt_check = BRANCH_HALT,
2885+ .clkr = {
2886+ .enable_reg = 0x4d098,
2887+ .enable_mask = BIT(0),
2888+ .hw.init = &(struct clk_init_data) {
2889+ .name = "gcc_mdss_esc0_clk",
2890+ .parent_hws = (const struct clk_hw *[]) {
2891+ &esc0_clk_src.clkr.hw,
2892+ },
2893+ .num_parents = 1,
2894+ .flags = CLK_SET_RATE_PARENT,
2895+ .ops = &clk_branch2_ops,
2896+ },
2897+ },
2898+};
2899+
2900+static struct clk_branch gcc_mdss_esc1_clk = {
2901+ .halt_reg = 0x4d09c,
2902+ .halt_check = BRANCH_HALT,
2903+ .clkr = {
2904+ .enable_reg = 0x4d09c,
2905+ .enable_mask = BIT(0),
2906+ .hw.init = &(struct clk_init_data) {
2907+ .name = "gcc_mdss_esc1_clk",
2908+ .parent_hws = (const struct clk_hw *[]) {
2909+ &esc1_clk_src.clkr.hw,
2910+ },
2911+ .num_parents = 1,
2912+ .flags = CLK_SET_RATE_PARENT,
2913+ .ops = &clk_branch2_ops,
2914+ },
2915+ },
2916+};
2917+
2918+static struct clk_branch gcc_mdss_mdp_clk = {
2919+ .halt_reg = 0x4d088,
2920+ .halt_check = BRANCH_HALT,
2921+ .clkr = {
2922+ .enable_reg = 0x4d088,
2923+ .enable_mask = BIT(0),
2924+ .hw.init = &(struct clk_init_data) {
2925+ .name = "gcc_mdss_mdp_clk",
2926+ .parent_hws = (const struct clk_hw *[]) {
2927+ &mdp_clk_src.clkr.hw,
2928+ },
2929+ .num_parents = 1,
2930+ .flags = CLK_SET_RATE_PARENT,
2931+ .ops = &clk_branch2_ops,
2932+ },
2933+ },
2934+};
2935+
2936+static struct clk_branch gcc_mdss_pclk0_clk = {
2937+ .halt_reg = 0x4d084,
2938+ .halt_check = BRANCH_HALT,
2939+ .clkr = {
2940+ .enable_reg = 0x4d084,
2941+ .enable_mask = BIT(0),
2942+ .hw.init = &(struct clk_init_data) {
2943+ .name = "gcc_mdss_pclk0_clk",
2944+ .parent_hws = (const struct clk_hw *[]) {
2945+ &pclk0_clk_src.clkr.hw,
2946+ },
2947+ .num_parents = 1,
2948+ .flags = CLK_SET_RATE_PARENT,
2949+ .ops = &clk_branch2_ops,
2950+ },
2951+ },
2952+};
2953+
2954+static struct clk_branch gcc_mdss_pclk1_clk = {
2955+ .halt_reg = 0x4d0a4,
2956+ .halt_check = BRANCH_HALT,
2957+ .clkr = {
2958+ .enable_reg = 0x4d0a4,
2959+ .enable_mask = BIT(0),
2960+ .hw.init = &(struct clk_init_data) {
2961+ .name = "gcc_mdss_pclk1_clk",
2962+ .parent_hws = (const struct clk_hw *[]) {
2963+ &pclk1_clk_src.clkr.hw,
2964+ },
2965+ .num_parents = 1,
2966+ .flags = CLK_SET_RATE_PARENT,
2967+ .ops = &clk_branch2_ops,
2968+ },
2969+ },
2970+};
2971+
2972+static struct clk_branch gcc_mdss_vsync_clk = {
2973+ .halt_reg = 0x4d090,
2974+ .halt_check = BRANCH_HALT,
2975+ .clkr = {
2976+ .enable_reg = 0x4d090,
2977+ .enable_mask = BIT(0),
2978+ .hw.init = &(struct clk_init_data) {
2979+ .name = "gcc_mdss_vsync_clk",
2980+ .parent_hws = (const struct clk_hw *[]) {
2981+ &vsync_clk_src.clkr.hw,
2982+ },
2983+ .num_parents = 1,
2984+ .flags = CLK_SET_RATE_PARENT,
2985+ .ops = &clk_branch2_ops,
2986+ },
2987+ },
2988+};
2989+
2990+static struct clk_branch gcc_mss_cfg_ahb_clk = {
2991+ .halt_reg = 0x49000,
2992+ .clkr = {
2993+ .enable_reg = 0x49000,
2994+ .enable_mask = BIT(0),
2995+ .hw.init = &(struct clk_init_data) {
2996+ .name = "gcc_mss_cfg_ahb_clk",
2997+ .ops = &clk_branch2_ops,
2998+ },
2999+ },
3000+};
3001+
3002+static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
3003+ .halt_reg = 0x49004,
3004+ .halt_check = BRANCH_HALT,
3005+ .clkr = {
3006+ .enable_reg = 0x49004,
3007+ .enable_mask = BIT(0),
3008+ .hw.init = &(struct clk_init_data) {
3009+ .name = "gcc_mss_q6_bimc_axi_clk",
3010+ .ops = &clk_branch2_ops,
3011+ },
3012+ },
3013+};
3014+
3015+static struct clk_branch gcc_bimc_gfx_clk = {
3016+ .halt_reg = 0x59048,
3017+ .clkr = {
3018+ .enable_reg = 0x59048,
3019+ .enable_mask = BIT(0),
3020+ .hw.init = &(struct clk_init_data) {
3021+ .name = "gcc_bimc_gfx_clk",
3022+ .ops = &clk_branch2_ops,
3023+ },
3024+ },
3025+};
3026+
3027+static struct clk_branch gcc_oxili_ahb_clk = {
3028+ .halt_reg = 0x59028,
3029+ .clkr = {
3030+ .enable_reg = 0x59028,
3031+ .enable_mask = BIT(0),
3032+ .hw.init = &(struct clk_init_data) {
3033+ .name = "gcc_oxili_ahb_clk",
3034+ .ops = &clk_branch2_ops,
3035+ },
3036+ },
3037+};
3038+
3039+static struct clk_branch gcc_oxili_aon_clk = {
3040+ .halt_reg = 0x59044,
3041+ .clkr = {
3042+ .enable_reg = 0x59044,
3043+ .enable_mask = BIT(0),
3044+ .hw.init = &(struct clk_init_data) {
3045+ .name = "gcc_oxili_aon_clk",
3046+ .parent_hws = (const struct clk_hw *[]) {
3047+ &gfx3d_clk_src.clkr.hw,
3048+ },
3049+ .num_parents = 1,
3050+ .flags = CLK_SET_RATE_PARENT,
3051+ .ops = &clk_branch2_ops,
3052+ },
3053+ },
3054+};
3055+
3056+static struct clk_branch gcc_oxili_gfx3d_clk = {
3057+ .halt_reg = 0x59020,
3058+ .clkr = {
3059+ .enable_reg = 0x59020,
3060+ .enable_mask = BIT(0),
3061+ .hw.init = &(struct clk_init_data) {
3062+ .name = "gcc_oxili_gfx3d_clk",
3063+ .parent_hws = (const struct clk_hw *[]) {
3064+ &gfx3d_clk_src.clkr.hw,
3065+ },
3066+ .num_parents = 1,
3067+ .flags = CLK_SET_RATE_PARENT,
3068+ .ops = &clk_branch2_ops,
3069+ },
3070+ },
3071+};
3072+
3073+static struct clk_branch gcc_oxili_timer_clk = {
3074+ .halt_reg = 0x59040,
3075+ .clkr = {
3076+ .enable_reg = 0x59040,
3077+ .enable_mask = BIT(0),
3078+ .hw.init = &(struct clk_init_data) {
3079+ .name = "gcc_oxili_timer_clk",
3080+ .parent_data = &(const struct clk_parent_data){
3081+ .fw_name = "xo",
3082+ },
3083+ .num_parents = 1,
3084+ .ops = &clk_branch2_ops,
3085+ },
3086+ },
3087+};
3088+
3089+static struct clk_branch gcc_pdm2_clk = {
3090+ .halt_reg = 0x4400c,
3091+ .halt_check = BRANCH_HALT,
3092+ .clkr = {
3093+ .enable_reg = 0x4400c,
3094+ .enable_mask = BIT(0),
3095+ .hw.init = &(struct clk_init_data) {
3096+ .name = "gcc_pdm2_clk",
3097+ .parent_hws = (const struct clk_hw *[]) {
3098+ &pdm2_clk_src.clkr.hw,
3099+ },
3100+ .num_parents = 1,
3101+ .flags = CLK_SET_RATE_PARENT,
3102+ .ops = &clk_branch2_ops,
3103+ },
3104+ },
3105+};
3106+
3107+static struct clk_branch gcc_pdm_ahb_clk = {
3108+ .halt_reg = 0x44004,
3109+ .halt_check = BRANCH_HALT,
3110+ .clkr = {
3111+ .enable_reg = 0x44004,
3112+ .enable_mask = BIT(0),
3113+ .hw.init = &(struct clk_init_data) {
3114+ .name = "gcc_pdm_ahb_clk",
3115+ .ops = &clk_branch2_ops,
3116+ },
3117+ },
3118+};
3119+
3120+static struct clk_branch gcc_rbcpr_gfx_ahb_clk = {
3121+ .halt_reg = 0x3a008,
3122+ .clkr = {
3123+ .enable_reg = 0x3a008,
3124+ .enable_mask = BIT(0),
3125+ .hw.init = &(struct clk_init_data) {
3126+ .name = "gcc_rbcpr_gfx_ahb_clk",
3127+ .ops = &clk_branch2_ops,
3128+ },
3129+ },
3130+};
3131+
3132+static struct clk_branch gcc_rbcpr_gfx_clk = {
3133+ .halt_reg = 0x3a004,
3134+ .clkr = {
3135+ .enable_reg = 0x3a004,
3136+ .enable_mask = BIT(0),
3137+ .hw.init = &(struct clk_init_data) {
3138+ .name = "gcc_rbcpr_gfx_clk",
3139+ .parent_hws = (const struct clk_hw *[]) {
3140+ &rbcpr_gfx_clk_src.clkr.hw,
3141+ },
3142+ .num_parents = 1,
3143+ .flags = CLK_SET_RATE_PARENT,
3144+ .ops = &clk_branch2_ops,
3145+ },
3146+ },
3147+};
3148+
3149+static struct clk_branch gcc_sdcc1_ahb_clk = {
3150+ .halt_reg = 0x4201c,
3151+ .halt_check = BRANCH_HALT,
3152+ .clkr = {
3153+ .enable_reg = 0x4201c,
3154+ .enable_mask = BIT(0),
3155+ .hw.init = &(struct clk_init_data) {
3156+ .name = "gcc_sdcc1_ahb_clk",
3157+ .ops = &clk_branch2_ops,
3158+ },
3159+ },
3160+};
3161+
3162+static struct clk_branch gcc_sdcc1_apps_clk = {
3163+ .halt_reg = 0x42018,
3164+ .halt_check = BRANCH_HALT,
3165+ .clkr = {
3166+ .enable_reg = 0x42018,
3167+ .enable_mask = BIT(0),
3168+ .hw.init = &(struct clk_init_data) {
3169+ .name = "gcc_sdcc1_apps_clk",
3170+ .parent_hws = (const struct clk_hw *[]) {
3171+ &sdcc1_apps_clk_src.clkr.hw,
3172+ },
3173+ .num_parents = 1,
3174+ .flags = CLK_SET_RATE_PARENT,
3175+ .ops = &clk_branch2_ops,
3176+ },
3177+ },
3178+};
3179+
3180+static struct clk_branch gcc_sdcc1_ice_core_clk = {
3181+ .halt_reg = 0x5d014,
3182+ .halt_check = BRANCH_HALT,
3183+ .clkr = {
3184+ .enable_reg = 0x5d014,
3185+ .enable_mask = BIT(0),
3186+ .hw.init = &(struct clk_init_data) {
3187+ .name = "gcc_sdcc1_ice_core_clk",
3188+ .parent_hws = (const struct clk_hw *[]) {
3189+ &sdcc1_ice_core_clk_src.clkr.hw,
3190+ },
3191+ .num_parents = 1,
3192+ .flags = CLK_SET_RATE_PARENT,
3193+ .ops = &clk_branch2_ops,
3194+ },
3195+ },
3196+};
3197+
3198+static struct clk_branch gcc_sdcc2_ahb_clk = {
3199+ .halt_reg = 0x4301c,
3200+ .halt_check = BRANCH_HALT,
3201+ .clkr = {
3202+ .enable_reg = 0x4301c,
3203+ .enable_mask = BIT(0),
3204+ .hw.init = &(struct clk_init_data) {
3205+ .name = "gcc_sdcc2_ahb_clk",
3206+ .ops = &clk_branch2_ops,
3207+ },
3208+ },
3209+};
3210+
3211+static struct clk_branch gcc_sdcc2_apps_clk = {
3212+ .halt_reg = 0x43018,
3213+ .halt_check = BRANCH_HALT,
3214+ .clkr = {
3215+ .enable_reg = 0x43018,
3216+ .enable_mask = BIT(0),
3217+ .hw.init = &(struct clk_init_data) {
3218+ .name = "gcc_sdcc2_apps_clk",
3219+ .parent_hws = (const struct clk_hw *[]) {
3220+ &sdcc2_apps_clk_src.clkr.hw,
3221+ },
3222+ .num_parents = 1,
3223+ .flags = CLK_SET_RATE_PARENT,
3224+ .ops = &clk_branch2_ops,
3225+ },
3226+ },
3227+};
3228+
3229+static struct clk_branch gcc_sdcc3_ahb_clk = {
3230+ .halt_reg = 0x3901c,
3231+ .halt_check = BRANCH_HALT,
3232+ .clkr = {
3233+ .enable_reg = 0x3901c,
3234+ .enable_mask = BIT(0),
3235+ .hw.init = &(struct clk_init_data) {
3236+ .name = "gcc_sdcc3_ahb_clk",
3237+ .ops = &clk_branch2_ops,
3238+ },
3239+ },
3240+};
3241+
3242+static struct clk_branch gcc_sdcc3_apps_clk = {
3243+ .halt_reg = 0x39018,
3244+ .halt_check = BRANCH_HALT,
3245+ .clkr = {
3246+ .enable_reg = 0x39018,
3247+ .enable_mask = BIT(0),
3248+ .hw.init = &(struct clk_init_data) {
3249+ .name = "gcc_sdcc3_apps_clk",
3250+ .parent_hws = (const struct clk_hw *[]) {
3251+ &sdcc3_apps_clk_src.clkr.hw,
3252+ },
3253+ .num_parents = 1,
3254+ .flags = CLK_SET_RATE_PARENT,
3255+ .ops = &clk_branch2_ops,
3256+ },
3257+ },
3258+};
3259+
3260+static struct clk_branch gcc_usb2a_phy_sleep_clk = {
3261+ .halt_reg = 0x4102c,
3262+ .clkr = {
3263+ .enable_reg = 0x4102c,
3264+ .enable_mask = BIT(0),
3265+ .hw.init = &(struct clk_init_data) {
3266+ .name = "gcc_usb2a_phy_sleep_clk",
3267+ .ops = &clk_branch2_ops,
3268+ },
3269+ },
3270+};
3271+
3272+static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = {
3273+ .halt_reg = 0x41030,
3274+ .clkr = {
3275+ .enable_reg = 0x41030,
3276+ .enable_mask = BIT(0),
3277+ .hw.init = &(struct clk_init_data) {
3278+ .name = "gcc_usb_hs_phy_cfg_ahb_clk",
3279+ .ops = &clk_branch2_ops,
3280+ },
3281+ },
3282+};
3283+
3284+static struct clk_branch gcc_usb_fs_ahb_clk = {
3285+ .halt_reg = 0x3f008,
3286+ .clkr = {
3287+ .enable_reg = 0x3f008,
3288+ .enable_mask = BIT(0),
3289+ .hw.init = &(struct clk_init_data) {
3290+ .name = "gcc_usb_fs_ahb_clk",
3291+ .ops = &clk_branch2_ops,
3292+ },
3293+ },
3294+};
3295+
3296+static struct clk_branch gcc_usb_fs_ic_clk = {
3297+ .halt_reg = 0x3f030,
3298+ .clkr = {
3299+ .enable_reg = 0x3f030,
3300+ .enable_mask = BIT(0),
3301+ .hw.init = &(struct clk_init_data) {
3302+ .name = "gcc_usb_fs_ic_clk",
3303+ .parent_hws = (const struct clk_hw *[]) {
3304+ &usb_fs_ic_clk_src.clkr.hw,
3305+ },
3306+ .num_parents = 1,
3307+ .flags = CLK_SET_RATE_PARENT,
3308+ .ops = &clk_branch2_ops,
3309+ },
3310+ },
3311+};
3312+
3313+static struct clk_branch gcc_usb_fs_system_clk = {
3314+ .halt_reg = 0x3f004,
3315+ .clkr = {
3316+ .enable_reg = 0x3f004,
3317+ .enable_mask = BIT(0),
3318+ .hw.init = &(struct clk_init_data) {
3319+ .name = "gcc_usb_fs_system_clk",
3320+ .parent_hws = (const struct clk_hw *[]) {
3321+ &usb_fs_system_clk_src.clkr.hw,
3322+ },
3323+ .num_parents = 1,
3324+ .flags = CLK_SET_RATE_PARENT,
3325+ .ops = &clk_branch2_ops,
3326+ },
3327+ },
3328+};
3329+
3330+static struct clk_branch gcc_usb_hs_ahb_clk = {
3331+ .halt_reg = 0x41008,
3332+ .clkr = {
3333+ .enable_reg = 0x41008,
3334+ .enable_mask = BIT(0),
3335+ .hw.init = &(struct clk_init_data) {
3336+ .name = "gcc_usb_hs_ahb_clk",
3337+ .ops = &clk_branch2_ops,
3338+ },
3339+ },
3340+};
3341+
3342+static struct clk_branch gcc_usb_hs_system_clk = {
3343+ .halt_reg = 0x41004,
3344+ .clkr = {
3345+ .enable_reg = 0x41004,
3346+ .enable_mask = BIT(0),
3347+ .hw.init = &(struct clk_init_data) {
3348+ .name = "gcc_usb_hs_system_clk",
3349+ .parent_hws = (const struct clk_hw *[]) {
3350+ &usb_hs_system_clk_src.clkr.hw,
3351+ },
3352+ .num_parents = 1,
3353+ .flags = CLK_SET_RATE_PARENT,
3354+ .ops = &clk_branch2_ops,
3355+ },
3356+ },
3357+};
3358+
3359+static struct clk_branch gcc_venus0_ahb_clk = {
3360+ .halt_reg = 0x4c020,
3361+ .clkr = {
3362+ .enable_reg = 0x4c020,
3363+ .enable_mask = BIT(0),
3364+ .hw.init = &(struct clk_init_data) {
3365+ .name = "gcc_venus0_ahb_clk",
3366+ .ops = &clk_branch2_ops,
3367+ },
3368+ },
3369+};
3370+
3371+static struct clk_branch gcc_venus0_axi_clk = {
3372+ .halt_reg = 0x4c024,
3373+ .clkr = {
3374+ .enable_reg = 0x4c024,
3375+ .enable_mask = BIT(0),
3376+ .hw.init = &(struct clk_init_data) {
3377+ .name = "gcc_venus0_axi_clk",
3378+ .ops = &clk_branch2_ops,
3379+ },
3380+ },
3381+};
3382+
3383+static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
3384+ .halt_reg = 0x4c02c,
3385+ .clkr = {
3386+ .enable_reg = 0x4c02c,
3387+ .enable_mask = BIT(0),
3388+ .hw.init = &(struct clk_init_data) {
3389+ .name = "gcc_venus0_core0_vcodec0_clk",
3390+ .parent_hws = (const struct clk_hw *[]) {
3391+ &vcodec0_clk_src.clkr.hw,
3392+ },
3393+ .num_parents = 1,
3394+ .flags = CLK_SET_RATE_PARENT,
3395+ .ops = &clk_branch2_ops,
3396+ },
3397+ },
3398+};
3399+
3400+static struct clk_branch gcc_venus0_core1_vcodec0_clk = {
3401+ .halt_reg = 0x4c034,
3402+ .clkr = {
3403+ .enable_reg = 0x4c034,
3404+ .enable_mask = BIT(0),
3405+ .hw.init = &(struct clk_init_data) {
3406+ .name = "gcc_venus0_core1_vcodec0_clk",
3407+ .parent_hws = (const struct clk_hw *[]) {
3408+ &vcodec0_clk_src.clkr.hw,
3409+ },
3410+ .num_parents = 1,
3411+ .flags = CLK_SET_RATE_PARENT,
3412+ .ops = &clk_branch2_ops,
3413+ },
3414+ },
3415+};
3416+
3417+static struct clk_branch gcc_venus0_vcodec0_clk = {
3418+ .halt_reg = 0x4c01c,
3419+ .clkr = {
3420+ .enable_reg = 0x4c01c,
3421+ .enable_mask = BIT(0),
3422+ .hw.init = &(struct clk_init_data) {
3423+ .name = "gcc_venus0_vcodec0_clk",
3424+ .parent_hws = (const struct clk_hw *[]) {
3425+ &vcodec0_clk_src.clkr.hw,
3426+ },
3427+ .num_parents = 1,
3428+ .flags = CLK_SET_RATE_PARENT,
3429+ .ops = &clk_branch2_ops,
3430+ },
3431+ },
3432+};
3433+
3434+/* Vote clocks */
3435+static struct clk_branch gcc_apss_ahb_clk = {
3436+ .halt_reg = 0x4601c,
3437+ .halt_check = BRANCH_HALT_VOTED,
3438+ .clkr = {
3439+ .enable_reg = 0x45004,
3440+ .enable_mask = BIT(14),
3441+ .hw.init = &(struct clk_init_data){
3442+ .name = "gcc_apss_ahb_clk",
3443+ .ops = &clk_branch2_ops,
3444+ },
3445+ },
3446+};
3447+
3448+static struct clk_branch gcc_apss_axi_clk = {
3449+ .halt_reg = 0x46020,
3450+ .halt_check = BRANCH_HALT_VOTED,
3451+ .clkr = {
3452+ .enable_reg = 0x45004,
3453+ .enable_mask = BIT(13),
3454+ .hw.init = &(struct clk_init_data){
3455+ .name = "gcc_apss_axi_clk",
3456+ .ops = &clk_branch2_ops,
3457+ },
3458+ },
3459+};
3460+
3461+static struct clk_branch gcc_blsp1_ahb_clk = {
3462+ .halt_reg = 0x1008,
3463+ .halt_check = BRANCH_HALT_VOTED,
3464+ .clkr = {
3465+ .enable_reg = 0x45004,
3466+ .enable_mask = BIT(10),
3467+ .hw.init = &(struct clk_init_data){
3468+ .name = "gcc_blsp1_ahb_clk",
3469+ .ops = &clk_branch2_ops,
3470+ },
3471+ },
3472+};
3473+
3474+static struct clk_branch gcc_blsp2_ahb_clk = {
3475+ .halt_reg = 0xb008,
3476+ .halt_check = BRANCH_HALT_VOTED,
3477+ .clkr = {
3478+ .enable_reg = 0x45004,
3479+ .enable_mask = BIT(20),
3480+ .hw.init = &(struct clk_init_data){
3481+ .name = "gcc_blsp2_ahb_clk",
3482+ .ops = &clk_branch2_ops,
3483+ },
3484+ },
3485+};
3486+
3487+static struct clk_branch gcc_prng_ahb_clk = {
3488+ .halt_reg = 0x13004,
3489+ .halt_check = BRANCH_HALT_VOTED,
3490+ .clkr = {
3491+ .enable_reg = 0x45004,
3492+ .enable_mask = BIT(8),
3493+ .hw.init = &(struct clk_init_data){
3494+ .name = "gcc_prng_ahb_clk",
3495+ .ops = &clk_branch2_ops,
3496+ },
3497+ },
3498+};
3499+
3500+static struct clk_branch gcc_boot_rom_ahb_clk = {
3501+ .halt_reg = 0x1300c,
3502+ .halt_check = BRANCH_HALT_VOTED,
3503+ .clkr = {
3504+ .enable_reg = 0x45004,
3505+ .enable_mask = BIT(7),
3506+ .hw.init = &(struct clk_init_data){
3507+ .name = "gcc_boot_rom_ahb_clk",
3508+ .ops = &clk_branch2_ops,
3509+ },
3510+ },
3511+};
3512+
3513+static struct clk_branch gcc_crypto_ahb_clk = {
3514+ .halt_reg = 0x16024,
3515+ .halt_check = BRANCH_HALT_VOTED,
3516+ .clkr = {
3517+ .enable_reg = 0x45004,
3518+ .enable_mask = BIT(0),
3519+ .hw.init = &(struct clk_init_data){
3520+ .name = "gcc_crypto_ahb_clk",
3521+ .ops = &clk_branch2_ops,
3522+ },
3523+ },
3524+};
3525+
3526+static struct clk_branch gcc_crypto_axi_clk = {
3527+ .halt_reg = 0x16020,
3528+ .halt_check = BRANCH_HALT_VOTED,
3529+ .clkr = {
3530+ .enable_reg = 0x45004,
3531+ .enable_mask = BIT(1),
3532+ .hw.init = &(struct clk_init_data){
3533+ .name = "gcc_crypto_axi_clk",
3534+ .ops = &clk_branch2_ops,
3535+ },
3536+ },
3537+};
3538+
3539+static struct clk_branch gcc_crypto_clk = {
3540+ .halt_reg = 0x1601c,
3541+ .halt_check = BRANCH_HALT_VOTED,
3542+ .clkr = {
3543+ .enable_reg = 0x45004,
3544+ .enable_mask = BIT(2),
3545+ .hw.init = &(struct clk_init_data){
3546+ .name = "gcc_crypto_clk",
3547+ .parent_hws = (const struct clk_hw *[]) {
3548+ &crypto_clk_src.clkr.hw,
3549+ },
3550+ .num_parents = 1,
3551+ .flags = CLK_SET_RATE_PARENT,
3552+ .ops = &clk_branch2_ops,
3553+ },
3554+ },
3555+};
3556+
3557+static struct clk_branch gcc_cpp_tbu_clk = {
3558+ .halt_reg = 0x12040,
3559+ .halt_check = BRANCH_HALT_VOTED,
3560+ .clkr = {
3561+ .enable_reg = 0x4500c,
3562+ .enable_mask = BIT(14),
3563+ .hw.init = &(struct clk_init_data){
3564+ .name = "gcc_cpp_tbu_clk",
3565+ .ops = &clk_branch2_ops,
3566+ },
3567+ },
3568+};
3569+
3570+static struct clk_branch gcc_gfx_1_tbu_clk = {
3571+ .halt_reg = 0x12098,
3572+ .halt_check = BRANCH_HALT_VOTED,
3573+ .clkr = {
3574+ .enable_reg = 0x4500c,
3575+ .enable_mask = BIT(19),
3576+ .hw.init = &(struct clk_init_data){
3577+ .name = "gcc_gfx_1_tbu_clk",
3578+ .ops = &clk_branch2_ops,
3579+ },
3580+ },
3581+};
3582+
3583+static struct clk_branch gcc_gfx_tbu_clk = {
3584+ .halt_reg = 0x12010,
3585+ .halt_check = BRANCH_HALT_VOTED,
3586+ .clkr = {
3587+ .enable_reg = 0x4500c,
3588+ .enable_mask = BIT(3),
3589+ .hw.init = &(struct clk_init_data){
3590+ .name = "gcc_gfx_tbu_clk",
3591+ .ops = &clk_branch2_ops,
3592+ },
3593+ },
3594+};
3595+
3596+static struct clk_branch gcc_gfx_tcu_clk = {
3597+ .halt_reg = 0x12020,
3598+ .halt_check = BRANCH_HALT_VOTED,
3599+ .clkr = {
3600+ .enable_reg = 0x4500c,
3601+ .enable_mask = BIT(2),
3602+ .hw.init = &(struct clk_init_data){
3603+ .name = "gcc_gfx_tcu_clk",
3604+ .ops = &clk_branch2_ops,
3605+ },
3606+ },
3607+};
3608+
3609+static struct clk_branch gcc_apss_tcu_clk = {
3610+ .halt_reg = 0x12018,
3611+ .halt_check = BRANCH_HALT_VOTED,
3612+ .clkr = {
3613+ .enable_reg = 0x4500c,
3614+ .enable_mask = BIT(1),
3615+ .hw.init = &(struct clk_init_data){
3616+ .name = "gcc_apss_tcu_clk",
3617+ .ops = &clk_branch2_ops,
3618+ },
3619+ },
3620+};
3621+
3622+static struct clk_branch gcc_gtcu_ahb_clk = {
3623+ .halt_reg = 0x12044,
3624+ .halt_check = BRANCH_HALT_VOTED,
3625+ .clkr = {
3626+ .enable_reg = 0x4500c,
3627+ .enable_mask = BIT(13),
3628+ .hw.init = &(struct clk_init_data){
3629+ .name = "gcc_gtcu_ahb_clk",
3630+ .ops = &clk_branch2_ops,
3631+ },
3632+ },
3633+};
3634+
3635+static struct clk_branch gcc_jpeg_tbu_clk = {
3636+ .halt_reg = 0x12034,
3637+ .halt_check = BRANCH_HALT_VOTED,
3638+ .clkr = {
3639+ .enable_reg = 0x4500c,
3640+ .enable_mask = BIT(10),
3641+ .hw.init = &(struct clk_init_data){
3642+ .name = "gcc_jpeg_tbu_clk",
3643+ .ops = &clk_branch2_ops,
3644+ },
3645+ },
3646+};
3647+
3648+static struct clk_branch gcc_mdp_rt_tbu_clk = {
3649+ .halt_reg = 0x1204c,
3650+ .halt_check = BRANCH_HALT_VOTED,
3651+ .clkr = {
3652+ .enable_reg = 0x4500c,
3653+ .enable_mask = BIT(15),
3654+ .hw.init = &(struct clk_init_data){
3655+ .name = "gcc_mdp_rt_tbu_clk",
3656+ .ops = &clk_branch2_ops,
3657+ },
3658+ },
3659+};
3660+
3661+static struct clk_branch gcc_mdp_tbu_clk = {
3662+ .halt_reg = 0x1201c,
3663+ .halt_check = BRANCH_HALT_VOTED,
3664+ .clkr = {
3665+ .enable_reg = 0x4500c,
3666+ .enable_mask = BIT(4),
3667+ .hw.init = &(struct clk_init_data){
3668+ .name = "gcc_mdp_tbu_clk",
3669+ .ops = &clk_branch2_ops,
3670+ },
3671+ },
3672+};
3673+
3674+static struct clk_branch gcc_smmu_cfg_clk = {
3675+ .halt_reg = 0x12038,
3676+ .halt_check = BRANCH_HALT_VOTED,
3677+ .clkr = {
3678+ .enable_reg = 0x4500c,
3679+ .enable_mask = BIT(12),
3680+ .hw.init = &(struct clk_init_data){
3681+ .name = "gcc_smmu_cfg_clk",
3682+ .ops = &clk_branch2_ops,
3683+ },
3684+ },
3685+};
3686+
3687+static struct clk_branch gcc_venus_1_tbu_clk = {
3688+ .halt_reg = 0x1209c,
3689+ .halt_check = BRANCH_HALT_VOTED,
3690+ .clkr = {
3691+ .enable_reg = 0x4500c,
3692+ .enable_mask = BIT(20),
3693+ .hw.init = &(struct clk_init_data){
3694+ .name = "gcc_venus_1_tbu_clk",
3695+ .ops = &clk_branch2_ops,
3696+ },
3697+ },
3698+};
3699+
3700+static struct clk_branch gcc_venus_tbu_clk = {
3701+ .halt_reg = 0x12014,
3702+ .halt_check = BRANCH_HALT_VOTED,
3703+ .clkr = {
3704+ .enable_reg = 0x4500c,
3705+ .enable_mask = BIT(5),
3706+ .hw.init = &(struct clk_init_data){
3707+ .name = "gcc_venus_tbu_clk",
3708+ .ops = &clk_branch2_ops,
3709+ },
3710+ },
3711+};
3712+
3713+static struct clk_branch gcc_vfe1_tbu_clk = {
3714+ .halt_reg = 0x12090,
3715+ .halt_check = BRANCH_HALT_VOTED,
3716+ .clkr = {
3717+ .enable_reg = 0x4500c,
3718+ .enable_mask = BIT(17),
3719+ .hw.init = &(struct clk_init_data){
3720+ .name = "gcc_vfe1_tbu_clk",
3721+ .ops = &clk_branch2_ops,
3722+ },
3723+ },
3724+};
3725+
3726+static struct clk_branch gcc_vfe_tbu_clk = {
3727+ .halt_reg = 0x1203c,
3728+ .halt_check = BRANCH_HALT_VOTED,
3729+ .clkr = {
3730+ .enable_reg = 0x4500c,
3731+ .enable_mask = BIT(9),
3732+ .hw.init = &(struct clk_init_data){
3733+ .name = "gcc_vfe_tbu_clk",
3734+ .ops = &clk_branch2_ops,
3735+ },
3736+ },
3737+};
3738+
3739+static struct gdsc venus_gdsc = {
3740+ .gdscr = 0x4c018,
3741+ .cxcs = (unsigned int []){ 0x4c024, 0x4c01c },
3742+ .cxc_count = 2,
3743+ .pd = {
3744+ .name = "venus_gdsc",
3745+ },
3746+ .pwrsts = PWRSTS_OFF_ON,
3747+};
3748+
3749+static struct gdsc venus_core0_gdsc = {
3750+ .gdscr = 0x4c028,
3751+ .cxcs = (unsigned int []){ 0x4c02c },
3752+ .cxc_count = 1,
3753+ .pd = {
3754+ .name = "venus_core0_gdsc",
3755+ },
3756+ .pwrsts = PWRSTS_OFF_ON,
3757+};
3758+
3759+static struct gdsc venus_core1_gdsc = {
3760+ .gdscr = 0x4c030,
3761+ .pd = {
3762+ .name = "venus_core1_gdsc",
3763+ },
3764+ .pwrsts = PWRSTS_OFF_ON,
3765+};
3766+
3767+static struct gdsc mdss_gdsc = {
3768+ .gdscr = 0x4d078,
3769+ .cxcs = (unsigned int []){ 0x4d080, 0x4d088 },
3770+ .cxc_count = 2,
3771+ .pd = {
3772+ .name = "mdss_gdsc",
3773+ },
3774+ .pwrsts = PWRSTS_OFF_ON,
3775+};
3776+
3777+static struct gdsc jpeg_gdsc = {
3778+ .gdscr = 0x5701c,
3779+ .cxcs = (unsigned int []){ 0x57020, 0x57028 },
3780+ .cxc_count = 2,
3781+ .pd = {
3782+ .name = "jpeg_gdsc",
3783+ },
3784+ .pwrsts = PWRSTS_OFF_ON,
3785+};
3786+
3787+static struct gdsc vfe0_gdsc = {
3788+ .gdscr = 0x58034,
3789+ .cxcs = (unsigned int []){ 0x58038, 0x58048, 0x5600c, 0x58050 },
3790+ .cxc_count = 4,
3791+ .pd = {
3792+ .name = "vfe0_gdsc",
3793+ },
3794+ .pwrsts = PWRSTS_OFF_ON,
3795+};
3796+
3797+static struct gdsc vfe1_gdsc = {
3798+ .gdscr = 0x5806c,
3799+ .cxcs = (unsigned int []){ 0x5805c, 0x58068, 0x5600c, 0x58074 },
3800+ .cxc_count = 4,
3801+ .pd = {
3802+ .name = "vfe1_gdsc",
3803+ },
3804+ .pwrsts = PWRSTS_OFF_ON,
3805+};
3806+
3807+static struct gdsc cpp_gdsc = {
3808+ .gdscr = 0x58078,
3809+ .cxcs = (unsigned int []){ 0x5803c, 0x58064 },
3810+ .cxc_count = 2,
3811+ .pd = {
3812+ .name = "cpp_gdsc",
3813+ },
3814+ .pwrsts = PWRSTS_OFF_ON,
3815+};
3816+
3817+static struct gdsc oxili_cx_gdsc = {
3818+ .gdscr = 0x5904c,
3819+ .cxcs = (unsigned int []){ 0x59020 },
3820+ .cxc_count = 1,
3821+ .pd = {
3822+ .name = "oxili_cx_gdsc",
3823+ },
3824+ .pwrsts = PWRSTS_OFF_ON,
3825+ .flags = VOTABLE,
3826+};
3827+
3828+static struct gdsc oxili_gx_gdsc = {
3829+ .gdscr = 0x5901c,
3830+ .clamp_io_ctrl = 0x5b00c,
3831+ .cxcs = (unsigned int []){ 0x59000, 0x59024 },
3832+ .cxc_count = 2,
3833+ .pd = {
3834+ .name = "oxili_gx_gdsc",
3835+ },
3836+ .pwrsts = PWRSTS_OFF_ON,
3837+ .supply = "vdd_gfx",
3838+ .flags = CLAMP_IO,
3839+};
3840+
3841+static struct clk_regmap *gcc_msm8976_clocks[] = {
3842+ [GPLL0] = &gpll0.clkr,
3843+ [GPLL2] = &gpll2.clkr,
3844+ [GPLL3] = &gpll3.clkr,
3845+ [GPLL4] = &gpll4.clkr,
3846+ [GPLL6] = &gpll6.clkr,
3847+ [GPLL0_CLK_SRC] = &gpll0_vote,
3848+ [GPLL2_CLK_SRC] = &gpll2_vote,
3849+ [GPLL3_CLK_SRC] = &gpll3_vote,
3850+ [GPLL4_CLK_SRC] = &gpll4_vote,
3851+ [GPLL6_CLK_SRC] = &gpll6_vote,
3852+ [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3853+ [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3854+ [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3855+ [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3856+ [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3857+ [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3858+ [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3859+ [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3860+ [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3861+ [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3862+ [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3863+ [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3864+ [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3865+ [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3866+ [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3867+ [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3868+ [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
3869+ [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
3870+ [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3871+ [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3872+ [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
3873+ [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
3874+ [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
3875+ [GCC_CAMSS_CPP_AXI_CLK] = &gcc_camss_cpp_axi_clk.clkr,
3876+ [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
3877+ [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
3878+ [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
3879+ [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
3880+ [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
3881+ [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
3882+ [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
3883+ [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
3884+ [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
3885+ [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
3886+ [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
3887+ [GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr,
3888+ [GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr,
3889+ [GCC_CAMSS_CSI2PHY_CLK] = &gcc_camss_csi2phy_clk.clkr,
3890+ [GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr,
3891+ [GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr,
3892+ [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
3893+ [GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr,
3894+ [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
3895+ [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
3896+ [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
3897+ [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
3898+ [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
3899+ [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
3900+ [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3901+ [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3902+ [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
3903+ [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
3904+ [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3905+ [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3906+ [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
3907+ [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3908+ [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
3909+ [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
3910+ [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
3911+ [GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr,
3912+ [GCC_CAMSS_VFE1_AXI_CLK] = &gcc_camss_vfe1_axi_clk.clkr,
3913+ [GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr,
3914+ [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
3915+ [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3916+ [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3917+ [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3918+ [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
3919+ [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
3920+ [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
3921+ [GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr,
3922+ [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
3923+ [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
3924+ [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3925+ [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3926+ [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3927+ [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3928+ [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3929+ [GCC_RBCPR_GFX_AHB_CLK] = &gcc_rbcpr_gfx_ahb_clk.clkr,
3930+ [GCC_RBCPR_GFX_CLK] = &gcc_rbcpr_gfx_clk.clkr,
3931+ [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3932+ [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3933+ [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3934+ [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3935+ [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3936+ [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
3937+ [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
3938+ [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3939+ [GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
3940+ [GCC_USB_FS_AHB_CLK] = &gcc_usb_fs_ahb_clk.clkr,
3941+ [GCC_USB_FS_IC_CLK] = &gcc_usb_fs_ic_clk.clkr,
3942+ [GCC_USB_FS_SYSTEM_CLK] = &gcc_usb_fs_system_clk.clkr,
3943+ [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3944+ [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3945+ [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
3946+ [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
3947+ [GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
3948+ [GCC_VENUS0_CORE1_VCODEC0_CLK] = &gcc_venus0_core1_vcodec0_clk.clkr,
3949+ [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
3950+ [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
3951+ [GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
3952+ [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3953+ [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3954+ [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3955+ [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3956+ [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3957+ [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3958+ [GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
3959+ [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
3960+ [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
3961+ [GCC_MDP_RT_TBU_CLK] = &gcc_mdp_rt_tbu_clk.clkr,
3962+ [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
3963+ [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
3964+ [GCC_VENUS_1_TBU_CLK] = &gcc_venus_1_tbu_clk.clkr,
3965+ [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
3966+ [GCC_VFE1_TBU_CLK] = &gcc_vfe1_tbu_clk.clkr,
3967+ [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
3968+ [GCC_APS_0_CLK] = &gcc_aps_0_clk.clkr,
3969+ [GCC_APS_1_CLK] = &gcc_aps_1_clk.clkr,
3970+ [APS_0_CLK_SRC] = &aps_0_clk_src.clkr,
3971+ [APS_1_CLK_SRC] = &aps_1_clk_src.clkr,
3972+ [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3973+ [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3974+ [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3975+ [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3976+ [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3977+ [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3978+ [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3979+ [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3980+ [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3981+ [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3982+ [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3983+ [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3984+ [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3985+ [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3986+ [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3987+ [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3988+ [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3989+ [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
3990+ [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
3991+ [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3992+ [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3993+ [CCI_CLK_SRC] = &cci_clk_src.clkr,
3994+ [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3995+ [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3996+ [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3997+ [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3998+ [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3999+ [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
4000+ [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
4001+ [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
4002+ [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
4003+ [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
4004+ [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
4005+ [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
4006+ [CAMSS_TOP_AHB_CLK_SRC] = &camss_top_ahb_clk_src.clkr,
4007+ [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
4008+ [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
4009+ [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
4010+ [GP1_CLK_SRC] = &gp1_clk_src.clkr,
4011+ [GP2_CLK_SRC] = &gp2_clk_src.clkr,
4012+ [GP3_CLK_SRC] = &gp3_clk_src.clkr,
4013+ [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
4014+ [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
4015+ [MDP_CLK_SRC] = &mdp_clk_src.clkr,
4016+ [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
4017+ [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
4018+ [RBCPR_GFX_CLK_SRC] = &rbcpr_gfx_clk_src.clkr,
4019+ [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
4020+ [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
4021+ [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
4022+ [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
4023+ [USB_FS_IC_CLK_SRC] = &usb_fs_ic_clk_src.clkr,
4024+ [USB_FS_SYSTEM_CLK_SRC] = &usb_fs_system_clk_src.clkr,
4025+ [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
4026+ [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
4027+ [GCC_MDSS_BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
4028+ [GCC_MDSS_BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
4029+ [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
4030+ [GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr,
4031+ [GCC_MDSS_PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
4032+ [GCC_MDSS_PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
4033+ [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
4034+ [GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr,
4035+ [GCC_GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
4036+ [GCC_GFX3D_OXILI_CLK] = &gcc_oxili_gfx3d_clk.clkr,
4037+ [GCC_GFX3D_BIMC_CLK] = &gcc_bimc_gfx_clk.clkr,
4038+ [GCC_GFX3D_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
4039+ [GCC_GFX3D_OXILI_AON_CLK] = &gcc_oxili_aon_clk.clkr,
4040+ [GCC_GFX3D_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
4041+ [GCC_GFX3D_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr,
4042+ [GCC_GFX3D_TBU0_CLK] = &gcc_gfx_tbu_clk.clkr,
4043+ [GCC_GFX3D_TBU1_CLK] = &gcc_gfx_1_tbu_clk.clkr,
4044+ [GCC_GFX3D_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
4045+ [GCC_GFX3D_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
4046+};
4047+
4048+static const struct qcom_reset_map gcc_msm8976_resets[] = {
4049+ [RST_CAMSS_MICRO_BCR] = { 0x56008 },
4050+ [RST_USB_HS_BCR] = { 0x41000 },
4051+ [RST_QUSB2_PHY_BCR] = { 0x4103c },
4052+ [RST_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
4053+ [RST_USB_HS_PHY_CFG_AHB_BCR] = { 0x41038 },
4054+ [RST_USB_FS_BCR] = { 0x3f000 },
4055+ [RST_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
4056+ [RST_CAMSS_CSI_VFE1_BCR] = { 0x58070 },
4057+ [RST_CAMSS_VFE1_BCR] = { 0x5807c },
4058+ [RST_CAMSS_CPP_BCR] = { 0x58080 },
4059+};
4060+
4061+static struct gdsc *gcc_msm8976_gdscs[] = {
4062+ [VENUS_GDSC] = &venus_gdsc,
4063+ [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
4064+ [VENUS_CORE1_GDSC] = &venus_core1_gdsc,
4065+ [MDSS_GDSC] = &mdss_gdsc,
4066+ [JPEG_GDSC] = &jpeg_gdsc,
4067+ [VFE0_GDSC] = &vfe0_gdsc,
4068+ [VFE1_GDSC] = &vfe1_gdsc,
4069+ [CPP_GDSC] = &cpp_gdsc,
4070+ [OXILI_GX_GDSC] = &oxili_gx_gdsc,
4071+ [OXILI_CX_GDSC] = &oxili_cx_gdsc,
4072+};
4073+
4074+static const struct regmap_config gcc_msm8976_regmap_config = {
4075+ .reg_bits = 32,
4076+ .reg_stride = 4,
4077+ .val_bits = 32,
4078+ .max_register = 0x7fffc,
4079+ .fast_io = true,
4080+};
4081+
4082+static const struct qcom_cc_desc gcc_msm8976_desc = {
4083+ .config = &gcc_msm8976_regmap_config,
4084+ .clks = gcc_msm8976_clocks,
4085+ .num_clks = ARRAY_SIZE(gcc_msm8976_clocks),
4086+ .resets = gcc_msm8976_resets,
4087+ .num_resets = ARRAY_SIZE(gcc_msm8976_resets),
4088+ .gdscs = gcc_msm8976_gdscs,
4089+ .num_gdscs = ARRAY_SIZE(gcc_msm8976_gdscs),
4090+};
4091+
4092+static const struct of_device_id gcc_msm8976_match_table[] = {
4093+ { .compatible = "qcom,gcc-msm8976" }, /* Also valid for 8x56 */
4094+ { .compatible = "qcom,gcc-msm8976-v1.1" },
4095+ { }
4096+};
4097+MODULE_DEVICE_TABLE(of, gcc_msm8976_match_table);
4098+
4099+static int gcc_msm8976_probe(struct platform_device *pdev)
4100+{
4101+ struct regmap *regmap;
4102+ int ret;
4103+
4104+ if (of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-msm8976-v1.1")) {
4105+ sdcc1_apps_clk_src.parent_map = gcc_parent_map_v1_1;
4106+ sdcc1_apps_clk_src.freq_tbl = ftbl_sdcc1_8976_v1_1_apps_clk_src;
4107+ sdcc1_apps_clk_src.clkr.hw.init = &sdcc1_apps_clk_src_8976v1_1_init;
4108+ }
4109+
4110+ regmap = qcom_cc_map(pdev, &gcc_msm8976_desc);
4111+ if (IS_ERR(regmap))
4112+ return PTR_ERR(regmap);
4113+
4114+ /* Set Sleep and Wakeup cycles to 0 for GMEM clock */
4115+ ret = regmap_update_bits(regmap, gcc_oxili_gmem_clk.clkr.enable_reg, 0xff0, 0);
4116+ if (ret)
4117+ return ret;
4118+
4119+ clk_pll_configure_sr_hpm_lp(&gpll3, regmap, &gpll3_config, true);
4120+
4121+ /* Enable AUX2 clock for APSS */
4122+ ret = regmap_update_bits(regmap, 0x60000, BIT(2), BIT(2));
4123+ if (ret)
4124+ return ret;
4125+
4126+ /* Set Sleep cycles to 0 for OXILI clock */
4127+ ret = regmap_update_bits(regmap, gcc_oxili_gfx3d_clk.clkr.enable_reg, 0xf0, 0);
4128+ if (ret)
4129+ return ret;
4130+
4131+ return qcom_cc_really_probe(pdev, &gcc_msm8976_desc, regmap);
4132+}
4133+
4134+static struct platform_driver gcc_msm8976_driver = {
4135+ .probe = gcc_msm8976_probe,
4136+ .driver = {
4137+ .name = "qcom,gcc-msm8976",
4138+ .of_match_table = gcc_msm8976_match_table,
4139+ },
4140+};
4141+
4142+static int __init gcc_msm8976_init(void)
4143+{
4144+ return platform_driver_register(&gcc_msm8976_driver);
4145+}
4146+core_initcall(gcc_msm8976_init);
4147+
4148+static void __exit gcc_msm8976_exit(void)
4149+{
4150+ platform_driver_unregister(&gcc_msm8976_driver);
4151+}
4152+module_exit(gcc_msm8976_exit);
4153+
4154+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>");
4155+MODULE_LICENSE("GPL v2");
drivers/clk/qcom/gcc-msm8994.c+1−0
@@ -2,6 +2,7 @@ · 1 unmodified line
22 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
33 */
44
5+#include <linux/clk-provider.h>
56 #include <linux/kernel.h>
67 #include <linux/init.h>
78 #include <linux/err.h>
drivers/clk/qcom/gcc-sc7280.c+1−1
@@ -2917,7 +2917,7 @@ static struct clk_branch gcc_cfg_noc_lpass_clk = { · 2916 unmodified lines
29172917 .enable_mask = BIT(0),
29182918 .hw.init = &(struct clk_init_data){
29192919 .name = "gcc_cfg_noc_lpass_clk",
2920− .ops = &clk_branch2_ops,
2920+ .ops = &clk_branch2_aon_ops,
29212921 },
29222922 },
29232923 };
drivers/clk/qcom/gcc-sdx65.c+1611−0
@@ -0,0 +1,1611 @@
1+// SPDX-License-Identifier: GPL-2.0-only
2+/*
3+ * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
4+ */
5+
6+#include <linux/clk-provider.h>
7+#include <linux/err.h>
8+#include <linux/kernel.h>
9+#include <linux/module.h>
10+#include <linux/of_device.h>
11+#include <linux/of.h>
12+#include <linux/regmap.h>
13+
14+#include <dt-bindings/clock/qcom,gcc-sdx65.h>
15+
16+#include "clk-alpha-pll.h"
17+#include "clk-branch.h"
18+#include "clk-rcg.h"
19+#include "clk-regmap.h"
20+#include "clk-regmap-divider.h"
21+#include "clk-regmap-mux.h"
22+#include "common.h"
23+#include "gdsc.h"
24+#include "reset.h"
25+
26+enum {
27+ P_BI_TCXO,
28+ P_GPLL0_OUT_EVEN,
29+ P_GPLL0_OUT_MAIN,
30+ P_PCIE_PIPE_CLK,
31+ P_SLEEP_CLK,
32+ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
33+};
34+
35+static struct clk_alpha_pll gpll0 = {
36+ .offset = 0x0,
37+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
38+ .clkr = {
39+ .enable_reg = 0x6d000,
40+ .enable_mask = BIT(0),
41+ .hw.init = &(struct clk_init_data){
42+ .name = "gpll0",
43+ .parent_data = &(const struct clk_parent_data){
44+ .fw_name = "bi_tcxo",
45+ },
46+ .num_parents = 1,
47+ .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
48+ },
49+ },
50+};
51+
52+static const struct clk_div_table post_div_table_gpll0_out_even[] = {
53+ { 0x1, 2 },
54+ { }
55+};
56+
57+static struct clk_alpha_pll_postdiv gpll0_out_even = {
58+ .offset = 0x0,
59+ .post_div_shift = 10,
60+ .post_div_table = post_div_table_gpll0_out_even,
61+ .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
62+ .width = 4,
63+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
64+ .clkr.hw.init = &(struct clk_init_data){
65+ .name = "gpll0_out_even",
66+ .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
67+ .num_parents = 1,
68+ .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
69+ },
70+};
71+
72+static const struct parent_map gcc_parent_map_0[] = {
73+ { P_BI_TCXO, 0 },
74+ { P_GPLL0_OUT_MAIN, 1 },
75+ { P_GPLL0_OUT_EVEN, 6 },
76+};
77+
78+static const struct clk_parent_data gcc_parent_data_0[] = {
79+ { .fw_name = "bi_tcxo" },
80+ { .hw = &gpll0.clkr.hw },
81+ { .hw = &gpll0_out_even.clkr.hw },
82+};
83+
84+static const struct clk_parent_data gcc_parent_data_0_ao[] = {
85+ { .fw_name = "bi_tcxo_ao" },
86+ { .hw = &gpll0.clkr.hw },
87+ { .hw = &gpll0_out_even.clkr.hw },
88+};
89+
90+static const struct parent_map gcc_parent_map_2[] = {
91+ { P_BI_TCXO, 0 },
92+ { P_GPLL0_OUT_MAIN, 1 },
93+ { P_SLEEP_CLK, 5 },
94+ { P_GPLL0_OUT_EVEN, 6 },
95+};
96+
97+static const struct clk_parent_data gcc_parent_data_2[] = {
98+ { .fw_name = "bi_tcxo" },
99+ { .hw = &gpll0.clkr.hw },
100+ { .fw_name = "sleep_clk" },
101+ { .hw = &gpll0_out_even.clkr.hw },
102+};
103+
104+static const struct parent_map gcc_parent_map_3[] = {
105+ { P_BI_TCXO, 0 },
106+ { P_SLEEP_CLK, 5 },
107+};
108+
109+static const struct clk_parent_data gcc_parent_data_3[] = {
110+ { .fw_name = "bi_tcxo" },
111+ { .fw_name = "sleep_clk" },
112+};
113+
114+static const struct parent_map gcc_parent_map_4[] = {
115+ { P_BI_TCXO, 2 },
116+};
117+
118+static const struct parent_map gcc_parent_map_5[] = {
119+ { P_PCIE_PIPE_CLK, 0 },
120+ { P_BI_TCXO, 2 },
121+};
122+
123+static const struct clk_parent_data gcc_parent_data_5[] = {
124+ { .fw_name = "pcie_pipe_clk"},
125+ { .fw_name = "bi_tcxo"},
126+};
127+
128+static const struct parent_map gcc_parent_map_6[] = {
129+ { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
130+ { P_BI_TCXO, 2 },
131+};
132+
133+static const struct clk_parent_data gcc_parent_data_6[] = {
134+ { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk"},
135+ { .fw_name = "bi_tcxo"},
136+};
137+
138+static struct clk_regmap_mux gcc_pcie_aux_clk_src = {
139+ .reg = 0x43060,
140+ .shift = 0,
141+ .width = 2,
142+ .parent_map = gcc_parent_map_4,
143+ .clkr = {
144+ .hw.init = &(struct clk_init_data){
145+ .name = "gcc_pcie_aux_clk_src",
146+ .parent_data = &(const struct clk_parent_data){
147+ .fw_name = "bi_tcxo",
148+ },
149+ .num_parents = 1,
150+ .ops = &clk_regmap_mux_closest_ops,
151+ },
152+ },
153+};
154+
155+static struct clk_regmap_mux gcc_pcie_pipe_clk_src = {
156+ .reg = 0x43044,
157+ .shift = 0,
158+ .width = 2,
159+ .parent_map = gcc_parent_map_5,
160+ .clkr = {
161+ .hw.init = &(struct clk_init_data){
162+ .name = "gcc_pcie_pipe_clk_src",
163+ .parent_data = gcc_parent_data_5,
164+ .num_parents = 2,
165+ .ops = &clk_regmap_mux_closest_ops,
166+ },
167+ },
168+};
169+
170+static struct clk_regmap_mux gcc_usb3_phy_pipe_clk_src = {
171+ .reg = 0x1706c,
172+ .shift = 0,
173+ .width = 2,
174+ .parent_map = gcc_parent_map_6,
175+ .clkr = {
176+ .hw.init = &(struct clk_init_data){
177+ .name = "gcc_usb3_phy_pipe_clk_src",
178+ .parent_data = gcc_parent_data_6,
179+ .num_parents = 2,
180+ .ops = &clk_regmap_mux_closest_ops,
181+ },
182+ },
183+};
184+
185+static const struct freq_tbl ftbl_gcc_blsp1_qup1_i2c_apps_clk_src[] = {
186+ F(9600000, P_BI_TCXO, 2, 0, 0),
187+ F(19200000, P_BI_TCXO, 1, 0, 0),
188+ F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
189+ { }
190+};
191+
192+static struct clk_rcg2 gcc_blsp1_qup1_i2c_apps_clk_src = {
193+ .cmd_rcgr = 0x1c024,
194+ .mnd_width = 8,
195+ .hid_width = 5,
196+ .parent_map = gcc_parent_map_0,
197+ .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
198+ .clkr.hw.init = &(struct clk_init_data){
199+ .name = "gcc_blsp1_qup1_i2c_apps_clk_src",
200+ .parent_data = gcc_parent_data_0,
201+ .num_parents = 3,
202+ .flags = CLK_SET_RATE_PARENT,
203+ .ops = &clk_rcg2_ops,
204+ },
205+};
206+
207+static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = {
208+ F(960000, P_BI_TCXO, 10, 1, 2),
209+ F(4800000, P_BI_TCXO, 4, 0, 0),
210+ F(9600000, P_BI_TCXO, 2, 0, 0),
211+ F(15000000, P_GPLL0_OUT_EVEN, 5, 1, 4),
212+ F(19200000, P_BI_TCXO, 1, 0, 0),
213+ F(24000000, P_GPLL0_OUT_MAIN, 12.5, 1, 2),
214+ F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
215+ F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
216+ { }
217+};
218+
219+static struct clk_rcg2 gcc_blsp1_qup1_spi_apps_clk_src = {
220+ .cmd_rcgr = 0x1c00c,
221+ .mnd_width = 8,
222+ .hid_width = 5,
223+ .parent_map = gcc_parent_map_0,
224+ .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
225+ .clkr.hw.init = &(struct clk_init_data){
226+ .name = "gcc_blsp1_qup1_spi_apps_clk_src",
227+ .parent_data = gcc_parent_data_0,
228+ .num_parents = 3,
229+ .flags = CLK_SET_RATE_PARENT,
230+ .ops = &clk_rcg2_ops,
231+ },
232+};
233+
234+static struct clk_rcg2 gcc_blsp1_qup2_i2c_apps_clk_src = {
235+ .cmd_rcgr = 0x1e024,
236+ .mnd_width = 8,
237+ .hid_width = 5,
238+ .parent_map = gcc_parent_map_0,
239+ .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
240+ .clkr.hw.init = &(struct clk_init_data){
241+ .name = "gcc_blsp1_qup2_i2c_apps_clk_src",
242+ .parent_data = gcc_parent_data_0,
243+ .num_parents = 3,
244+ .flags = CLK_SET_RATE_PARENT,
245+ .ops = &clk_rcg2_ops,
246+ },
247+};
248+
249+static struct clk_rcg2 gcc_blsp1_qup2_spi_apps_clk_src = {
250+ .cmd_rcgr = 0x1e00c,
251+ .mnd_width = 8,
252+ .hid_width = 5,
253+ .parent_map = gcc_parent_map_0,
254+ .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
255+ .clkr.hw.init = &(struct clk_init_data){
256+ .name = "gcc_blsp1_qup2_spi_apps_clk_src",
257+ .parent_data = gcc_parent_data_0,
258+ .num_parents = 3,
259+ .flags = CLK_SET_RATE_PARENT,
260+ .ops = &clk_rcg2_ops,
261+ },
262+};
263+
264+static struct clk_rcg2 gcc_blsp1_qup3_i2c_apps_clk_src = {
265+ .cmd_rcgr = 0x20024,
266+ .mnd_width = 8,
267+ .hid_width = 5,
268+ .parent_map = gcc_parent_map_0,
269+ .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
270+ .clkr.hw.init = &(struct clk_init_data){
271+ .name = "gcc_blsp1_qup3_i2c_apps_clk_src",
272+ .parent_data = gcc_parent_data_0,
273+ .num_parents = 3,
274+ .flags = CLK_SET_RATE_PARENT,
275+ .ops = &clk_rcg2_ops,
276+ },
277+};
278+
279+static struct clk_rcg2 gcc_blsp1_qup3_spi_apps_clk_src = {
280+ .cmd_rcgr = 0x2000c,
281+ .mnd_width = 8,
282+ .hid_width = 5,
283+ .parent_map = gcc_parent_map_0,
284+ .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
285+ .clkr.hw.init = &(struct clk_init_data){
286+ .name = "gcc_blsp1_qup3_spi_apps_clk_src",
287+ .parent_data = gcc_parent_data_0,
288+ .num_parents = 3,
289+ .flags = CLK_SET_RATE_PARENT,
290+ .ops = &clk_rcg2_ops,
291+ },
292+};
293+
294+static struct clk_rcg2 gcc_blsp1_qup4_i2c_apps_clk_src = {
295+ .cmd_rcgr = 0x22024,
296+ .mnd_width = 8,
297+ .hid_width = 5,
298+ .parent_map = gcc_parent_map_0,
299+ .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
300+ .clkr.hw.init = &(struct clk_init_data){
301+ .name = "gcc_blsp1_qup4_i2c_apps_clk_src",
302+ .parent_data = gcc_parent_data_0,
303+ .num_parents = 3,
304+ .flags = CLK_SET_RATE_PARENT,
305+ .ops = &clk_rcg2_ops,
306+ },
307+};
308+
309+static struct clk_rcg2 gcc_blsp1_qup4_spi_apps_clk_src = {
310+ .cmd_rcgr = 0x2200c,
311+ .mnd_width = 8,
312+ .hid_width = 5,
313+ .parent_map = gcc_parent_map_0,
314+ .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
315+ .clkr.hw.init = &(struct clk_init_data){
316+ .name = "gcc_blsp1_qup4_spi_apps_clk_src",
317+ .parent_data = gcc_parent_data_0,
318+ .num_parents = 3,
319+ .flags = CLK_SET_RATE_PARENT,
320+ .ops = &clk_rcg2_ops,
321+ },
322+};
323+
324+static const struct freq_tbl ftbl_gcc_blsp1_uart1_apps_clk_src[] = {
325+ F(3686400, P_GPLL0_OUT_EVEN, 1, 192, 15625),
326+ F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
327+ F(9600000, P_BI_TCXO, 2, 0, 0),
328+ F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
329+ F(16000000, P_GPLL0_OUT_EVEN, 1, 4, 75),
330+ F(19200000, P_BI_TCXO, 1, 0, 0),
331+ F(19354839, P_GPLL0_OUT_MAIN, 15.5, 1, 2),
332+ F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
333+ F(20689655, P_GPLL0_OUT_MAIN, 14.5, 1, 2),
334+ F(21428571, P_GPLL0_OUT_MAIN, 14, 1, 2),
335+ F(22222222, P_GPLL0_OUT_MAIN, 13.5, 1, 2),
336+ F(23076923, P_GPLL0_OUT_MAIN, 13, 1, 2),
337+ F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5),
338+ F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
339+ F(26086957, P_GPLL0_OUT_MAIN, 11.5, 1, 2),
340+ F(27272727, P_GPLL0_OUT_MAIN, 11, 1, 2),
341+ F(28571429, P_GPLL0_OUT_MAIN, 10.5, 1, 2),
342+ F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75),
343+ F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
344+ F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375),
345+ F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
346+ F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375),
347+ F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75),
348+ F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625),
349+ F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
350+ F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
351+ { }
352+};
353+
354+static struct clk_rcg2 gcc_blsp1_uart1_apps_clk_src = {
355+ .cmd_rcgr = 0x1d00c,
356+ .mnd_width = 16,
357+ .hid_width = 5,
358+ .parent_map = gcc_parent_map_0,
359+ .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
360+ .clkr.hw.init = &(struct clk_init_data){
361+ .name = "gcc_blsp1_uart1_apps_clk_src",
362+ .parent_data = gcc_parent_data_0,
363+ .num_parents = 3,
364+ .flags = CLK_SET_RATE_PARENT,
365+ .ops = &clk_rcg2_ops,
366+ },
367+};
368+
369+static struct clk_rcg2 gcc_blsp1_uart2_apps_clk_src = {
370+ .cmd_rcgr = 0x1f00c,
371+ .mnd_width = 16,
372+ .hid_width = 5,
373+ .parent_map = gcc_parent_map_0,
374+ .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
375+ .clkr.hw.init = &(struct clk_init_data){
376+ .name = "gcc_blsp1_uart2_apps_clk_src",
377+ .parent_data = gcc_parent_data_0,
378+ .num_parents = 3,
379+ .flags = CLK_SET_RATE_PARENT,
380+ .ops = &clk_rcg2_ops,
381+ },
382+};
383+
384+static struct clk_rcg2 gcc_blsp1_uart3_apps_clk_src = {
385+ .cmd_rcgr = 0x2100c,
386+ .mnd_width = 16,
387+ .hid_width = 5,
388+ .parent_map = gcc_parent_map_0,
389+ .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
390+ .clkr.hw.init = &(struct clk_init_data){
391+ .name = "gcc_blsp1_uart3_apps_clk_src",
392+ .parent_data = gcc_parent_data_0,
393+ .num_parents = 3,
394+ .flags = CLK_SET_RATE_PARENT,
395+ .ops = &clk_rcg2_ops,
396+ },
397+};
398+
399+static struct clk_rcg2 gcc_blsp1_uart4_apps_clk_src = {
400+ .cmd_rcgr = 0x2300c,
401+ .mnd_width = 16,
402+ .hid_width = 5,
403+ .parent_map = gcc_parent_map_0,
404+ .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
405+ .clkr.hw.init = &(struct clk_init_data){
406+ .name = "gcc_blsp1_uart4_apps_clk_src",
407+ .parent_data = gcc_parent_data_0,
408+ .num_parents = 3,
409+ .flags = CLK_SET_RATE_PARENT,
410+ .ops = &clk_rcg2_ops,
411+ },
412+};
413+
414+static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
415+ F(19200000, P_BI_TCXO, 1, 0, 0),
416+ F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
417+ F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
418+ F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
419+ { }
420+};
421+
422+static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
423+ .cmd_rcgr = 0x3000c,
424+ .mnd_width = 0,
425+ .hid_width = 5,
426+ .parent_map = gcc_parent_map_0,
427+ .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
428+ .clkr.hw.init = &(struct clk_init_data){
429+ .name = "gcc_cpuss_ahb_clk_src",
430+ .parent_data = gcc_parent_data_0_ao,
431+ .num_parents = 3,
432+ .flags = CLK_SET_RATE_PARENT,
433+ .ops = &clk_rcg2_ops,
434+ },
435+};
436+
437+static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
438+ F(19200000, P_BI_TCXO, 1, 0, 0),
439+ F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
440+ F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
441+ F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
442+ { }
443+};
444+
445+static struct clk_rcg2 gcc_gp1_clk_src = {
446+ .cmd_rcgr = 0x37004,
447+ .mnd_width = 16,
448+ .hid_width = 5,
449+ .parent_map = gcc_parent_map_2,
450+ .freq_tbl = ftbl_gcc_gp1_clk_src,
451+ .clkr.hw.init = &(struct clk_init_data){
452+ .name = "gcc_gp1_clk_src",
453+ .parent_data = gcc_parent_data_2,
454+ .num_parents = 4,
455+ .flags = CLK_SET_RATE_PARENT,
456+ .ops = &clk_rcg2_ops,
457+ },
458+};
459+
460+static struct clk_rcg2 gcc_gp2_clk_src = {
461+ .cmd_rcgr = 0x38004,
462+ .mnd_width = 16,
463+ .hid_width = 5,
464+ .parent_map = gcc_parent_map_2,
465+ .freq_tbl = ftbl_gcc_gp1_clk_src,
466+ .clkr.hw.init = &(struct clk_init_data){
467+ .name = "gcc_gp2_clk_src",
468+ .parent_data = gcc_parent_data_2,
469+ .num_parents = 4,
470+ .flags = CLK_SET_RATE_PARENT,
471+ .ops = &clk_rcg2_ops,
472+ },
473+};
474+
475+static struct clk_rcg2 gcc_gp3_clk_src = {
476+ .cmd_rcgr = 0x39004,
477+ .mnd_width = 16,
478+ .hid_width = 5,
479+ .parent_map = gcc_parent_map_2,
480+ .freq_tbl = ftbl_gcc_gp1_clk_src,
481+ .clkr.hw.init = &(struct clk_init_data){
482+ .name = "gcc_gp3_clk_src",
483+ .parent_data = gcc_parent_data_2,
484+ .num_parents = 4,
485+ .flags = CLK_SET_RATE_PARENT,
486+ .ops = &clk_rcg2_ops,
487+ },
488+};
489+
490+static const struct freq_tbl ftbl_gcc_pcie_aux_phy_clk_src[] = {
491+ F(19200000, P_BI_TCXO, 1, 0, 0),
492+ { }
493+};
494+
495+static struct clk_rcg2 gcc_pcie_aux_phy_clk_src = {
496+ .cmd_rcgr = 0x43048,
497+ .mnd_width = 16,
498+ .hid_width = 5,
499+ .parent_map = gcc_parent_map_3,
500+ .freq_tbl = ftbl_gcc_pcie_aux_phy_clk_src,
501+ .clkr.hw.init = &(struct clk_init_data){
502+ .name = "gcc_pcie_aux_phy_clk_src",
503+ .parent_data = gcc_parent_data_3,
504+ .num_parents = 2,
505+ .flags = CLK_SET_RATE_PARENT,
506+ .ops = &clk_rcg2_ops,
507+ },
508+};
509+
510+static const struct freq_tbl ftbl_gcc_pcie_rchng_phy_clk_src[] = {
511+ F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
512+ { }
513+};
514+
515+static struct clk_rcg2 gcc_pcie_rchng_phy_clk_src = {
516+ .cmd_rcgr = 0x43064,
517+ .mnd_width = 0,
518+ .hid_width = 5,
519+ .parent_map = gcc_parent_map_2,
520+ .freq_tbl = ftbl_gcc_pcie_rchng_phy_clk_src,
521+ .clkr.hw.init = &(struct clk_init_data){
522+ .name = "gcc_pcie_rchng_phy_clk_src",
523+ .parent_data = gcc_parent_data_2,
524+ .num_parents = 4,
525+ .flags = CLK_SET_RATE_PARENT,
526+ .ops = &clk_rcg2_ops,
527+ },
528+};
529+
530+static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
531+ F(19200000, P_BI_TCXO, 1, 0, 0),
532+ F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
533+ { }
534+};
535+
536+static struct clk_rcg2 gcc_pdm2_clk_src = {
537+ .cmd_rcgr = 0x24010,
538+ .mnd_width = 0,
539+ .hid_width = 5,
540+ .parent_map = gcc_parent_map_0,
541+ .freq_tbl = ftbl_gcc_pdm2_clk_src,
542+ .clkr.hw.init = &(struct clk_init_data){
543+ .name = "gcc_pdm2_clk_src",
544+ .parent_data = gcc_parent_data_0,
545+ .num_parents = 3,
546+ .flags = CLK_SET_RATE_PARENT,
547+ .ops = &clk_rcg2_ops,
548+ },
549+};
550+
551+static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
552+ F(400000, P_BI_TCXO, 12, 1, 4),
553+ F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
554+ F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
555+ F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
556+ F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
557+ { }
558+};
559+
560+static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
561+ .cmd_rcgr = 0x1a010,
562+ .mnd_width = 8,
563+ .hid_width = 5,
564+ .parent_map = gcc_parent_map_0,
565+ .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
566+ .clkr.hw.init = &(struct clk_init_data){
567+ .name = "gcc_sdcc1_apps_clk_src",
568+ .parent_data = gcc_parent_data_0,
569+ .num_parents = 3,
570+ .flags = CLK_SET_RATE_PARENT,
571+ .ops = &clk_rcg2_ops,
572+ },
573+};
574+
575+static const struct freq_tbl ftbl_gcc_usb30_master_clk_src[] = {
576+ F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
577+ { }
578+};
579+
580+static struct clk_rcg2 gcc_usb30_master_clk_src = {
581+ .cmd_rcgr = 0x17030,
582+ .mnd_width = 8,
583+ .hid_width = 5,
584+ .parent_map = gcc_parent_map_0,
585+ .freq_tbl = ftbl_gcc_usb30_master_clk_src,
586+ .clkr.hw.init = &(struct clk_init_data){
587+ .name = "gcc_usb30_master_clk_src",
588+ .parent_data = gcc_parent_data_0,
589+ .num_parents = 3,
590+ .flags = CLK_SET_RATE_PARENT,
591+ .ops = &clk_rcg2_ops,
592+ },
593+};
594+
595+static struct clk_rcg2 gcc_usb30_mock_utmi_clk_src = {
596+ .cmd_rcgr = 0x17048,
597+ .mnd_width = 0,
598+ .hid_width = 5,
599+ .parent_map = gcc_parent_map_0,
600+ .freq_tbl = ftbl_gcc_pcie_aux_phy_clk_src,
601+ .clkr.hw.init = &(struct clk_init_data){
602+ .name = "gcc_usb30_mock_utmi_clk_src",
603+ .parent_data = gcc_parent_data_0,
604+ .num_parents = 3,
605+ .flags = CLK_SET_RATE_PARENT,
606+ .ops = &clk_rcg2_ops,
607+ },
608+};
609+
610+static const struct freq_tbl ftbl_gcc_usb3_phy_aux_clk_src[] = {
611+ F(1000000, P_BI_TCXO, 1, 5, 96),
612+ F(19200000, P_BI_TCXO, 1, 0, 0),
613+ { }
614+};
615+
616+static struct clk_rcg2 gcc_usb3_phy_aux_clk_src = {
617+ .cmd_rcgr = 0x17070,
618+ .mnd_width = 16,
619+ .hid_width = 5,
620+ .parent_map = gcc_parent_map_3,
621+ .freq_tbl = ftbl_gcc_usb3_phy_aux_clk_src,
622+ .clkr.hw.init = &(struct clk_init_data){
623+ .name = "gcc_usb3_phy_aux_clk_src",
624+ .parent_data = gcc_parent_data_3,
625+ .num_parents = 2,
626+ .flags = CLK_SET_RATE_PARENT,
627+ .ops = &clk_rcg2_ops,
628+ },
629+};
630+
631+static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = {
632+ .reg = 0x30024,
633+ .shift = 0,
634+ .width = 4,
635+ .clkr.hw.init = &(struct clk_init_data) {
636+ .name = "gcc_cpuss_ahb_postdiv_clk_src",
637+ .parent_data = &(const struct clk_parent_data){
638+ .hw = &gcc_cpuss_ahb_clk_src.clkr.hw,
639+ },
640+ .num_parents = 1,
641+ .flags = CLK_SET_RATE_PARENT,
642+ .ops = &clk_regmap_div_ro_ops,
643+ },
644+};
645+
646+static struct clk_regmap_div gcc_usb30_mock_utmi_postdiv_clk_src = {
647+ .reg = 0x17060,
648+ .shift = 0,
649+ .width = 4,
650+ .clkr.hw.init = &(struct clk_init_data) {
651+ .name = "gcc_usb30_mock_utmi_postdiv_clk_src",
652+ .parent_data = &(const struct clk_parent_data){
653+ .hw = &gcc_usb30_mock_utmi_clk_src.clkr.hw,
654+ },
655+ .num_parents = 1,
656+ .flags = CLK_SET_RATE_PARENT,
657+ .ops = &clk_regmap_div_ro_ops,
658+ },
659+};
660+
661+static struct clk_branch gcc_ahb_pcie_link_clk = {
662+ .halt_reg = 0x2e004,
663+ .halt_check = BRANCH_HALT,
664+ .clkr = {
665+ .enable_reg = 0x2e004,
666+ .enable_mask = BIT(0),
667+ .hw.init = &(struct clk_init_data){
668+ .name = "gcc_ahb_pcie_link_clk",
669+ .ops = &clk_branch2_ops,
670+ },
671+ },
672+};
673+
674+static struct clk_branch gcc_blsp1_ahb_clk = {
675+ .halt_reg = 0x1b004,
676+ .halt_check = BRANCH_HALT_VOTED,
677+ .clkr = {
678+ .enable_reg = 0x6d008,
679+ .enable_mask = BIT(14),
680+ .hw.init = &(struct clk_init_data){
681+ .name = "gcc_blsp1_ahb_clk",
682+ .ops = &clk_branch2_ops,
683+ },
684+ },
685+};
686+
687+static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
688+ .halt_reg = 0x1c008,
689+ .halt_check = BRANCH_HALT,
690+ .clkr = {
691+ .enable_reg = 0x1c008,
692+ .enable_mask = BIT(0),
693+ .hw.init = &(struct clk_init_data){
694+ .name = "gcc_blsp1_qup1_i2c_apps_clk",
695+ .parent_data = &(const struct clk_parent_data){
696+ .hw = &gcc_blsp1_qup1_i2c_apps_clk_src.clkr.hw,
697+ },
698+ .num_parents = 1,
699+ .flags = CLK_SET_RATE_PARENT,
700+ .ops = &clk_branch2_ops,
701+ },
702+ },
703+};
704+
705+static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
706+ .halt_reg = 0x1c004,
707+ .halt_check = BRANCH_HALT,
708+ .clkr = {
709+ .enable_reg = 0x1c004,
710+ .enable_mask = BIT(0),
711+ .hw.init = &(struct clk_init_data){
712+ .name = "gcc_blsp1_qup1_spi_apps_clk",
713+ .parent_data = &(const struct clk_parent_data){
714+ .hw = &gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw,
715+ },
716+ .num_parents = 1,
717+ .flags = CLK_SET_RATE_PARENT,
718+ .ops = &clk_branch2_ops,
719+ },
720+ },
721+};
722+
723+static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
724+ .halt_reg = 0x1e008,
725+ .halt_check = BRANCH_HALT,
726+ .clkr = {
727+ .enable_reg = 0x1e008,
728+ .enable_mask = BIT(0),
729+ .hw.init = &(struct clk_init_data){
730+ .name = "gcc_blsp1_qup2_i2c_apps_clk",
731+ .parent_data = &(const struct clk_parent_data){
732+ .hw = &gcc_blsp1_qup2_i2c_apps_clk_src.clkr.hw,
733+ },
734+ .num_parents = 1,
735+ .flags = CLK_SET_RATE_PARENT,
736+ .ops = &clk_branch2_ops,
737+ },
738+ },
739+};
740+
741+static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
742+ .halt_reg = 0x1e004,
743+ .halt_check = BRANCH_HALT,
744+ .clkr = {
745+ .enable_reg = 0x1e004,
746+ .enable_mask = BIT(0),
747+ .hw.init = &(struct clk_init_data){
748+ .name = "gcc_blsp1_qup2_spi_apps_clk",
749+ .parent_data = &(const struct clk_parent_data){
750+ .hw = &gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw,
751+ },
752+ .num_parents = 1,
753+ .flags = CLK_SET_RATE_PARENT,
754+ .ops = &clk_branch2_ops,
755+ },
756+ },
757+};
758+
759+static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
760+ .halt_reg = 0x20008,
761+ .halt_check = BRANCH_HALT,
762+ .clkr = {
763+ .enable_reg = 0x20008,
764+ .enable_mask = BIT(0),
765+ .hw.init = &(struct clk_init_data){
766+ .name = "gcc_blsp1_qup3_i2c_apps_clk",
767+ .parent_data = &(const struct clk_parent_data){
768+ .hw = &gcc_blsp1_qup3_i2c_apps_clk_src.clkr.hw,
769+ },
770+ .num_parents = 1,
771+ .flags = CLK_SET_RATE_PARENT,
772+ .ops = &clk_branch2_ops,
773+ },
774+ },
775+};
776+
777+static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
778+ .halt_reg = 0x20004,
779+ .halt_check = BRANCH_HALT,
780+ .clkr = {
781+ .enable_reg = 0x20004,
782+ .enable_mask = BIT(0),
783+ .hw.init = &(struct clk_init_data){
784+ .name = "gcc_blsp1_qup3_spi_apps_clk",
785+ .parent_data = &(const struct clk_parent_data){
786+ .hw = &gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw,
787+ },
788+ .num_parents = 1,
789+ .flags = CLK_SET_RATE_PARENT,
790+ .ops = &clk_branch2_ops,
791+ },
792+ },
793+};
794+
795+static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
796+ .halt_reg = 0x22008,
797+ .halt_check = BRANCH_HALT,
798+ .clkr = {
799+ .enable_reg = 0x22008,
800+ .enable_mask = BIT(0),
801+ .hw.init = &(struct clk_init_data){
802+ .name = "gcc_blsp1_qup4_i2c_apps_clk",
803+ .parent_data = &(const struct clk_parent_data){
804+ .hw = &gcc_blsp1_qup4_i2c_apps_clk_src.clkr.hw,
805+ },
806+ .num_parents = 1,
807+ .flags = CLK_SET_RATE_PARENT,
808+ .ops = &clk_branch2_ops,
809+ },
810+ },
811+};
812+
813+static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
814+ .halt_reg = 0x22004,
815+ .halt_check = BRANCH_HALT,
816+ .clkr = {
817+ .enable_reg = 0x22004,
818+ .enable_mask = BIT(0),
819+ .hw.init = &(struct clk_init_data){
820+ .name = "gcc_blsp1_qup4_spi_apps_clk",
821+ .parent_data = &(const struct clk_parent_data){
822+ .hw = &gcc_blsp1_qup4_spi_apps_clk_src.clkr.hw,
823+ },
824+ .num_parents = 1,
825+ .flags = CLK_SET_RATE_PARENT,
826+ .ops = &clk_branch2_ops,
827+ },
828+ },
829+};
830+
831+static struct clk_branch gcc_blsp1_sleep_clk = {
832+ .halt_reg = 0x1b00c,
833+ .halt_check = BRANCH_HALT_VOTED,
834+ .clkr = {
835+ .enable_reg = 0x6d008,
836+ .enable_mask = BIT(15),
837+ .hw.init = &(struct clk_init_data){
838+ .name = "gcc_blsp1_sleep_clk",
839+ .ops = &clk_branch2_ops,
840+ },
841+ },
842+};
843+
844+static struct clk_branch gcc_blsp1_uart1_apps_clk = {
845+ .halt_reg = 0x1d004,
846+ .halt_check = BRANCH_HALT,
847+ .clkr = {
848+ .enable_reg = 0x1d004,
849+ .enable_mask = BIT(0),
850+ .hw.init = &(struct clk_init_data){
851+ .name = "gcc_blsp1_uart1_apps_clk",
852+ .parent_data = &(const struct clk_parent_data){
853+ .hw = &gcc_blsp1_uart1_apps_clk_src.clkr.hw,
854+ },
855+ .num_parents = 1,
856+ .flags = CLK_SET_RATE_PARENT,
857+ .ops = &clk_branch2_ops,
858+ },
859+ },
860+};
861+
862+static struct clk_branch gcc_blsp1_uart2_apps_clk = {
863+ .halt_reg = 0x1f004,
864+ .halt_check = BRANCH_HALT,
865+ .clkr = {
866+ .enable_reg = 0x1f004,
867+ .enable_mask = BIT(0),
868+ .hw.init = &(struct clk_init_data){
869+ .name = "gcc_blsp1_uart2_apps_clk",
870+ .parent_data = &(const struct clk_parent_data){
871+ .hw = &gcc_blsp1_uart2_apps_clk_src.clkr.hw,
872+ },
873+ .num_parents = 1,
874+ .flags = CLK_SET_RATE_PARENT,
875+ .ops = &clk_branch2_ops,
876+ },
877+ },
878+};
879+
880+static struct clk_branch gcc_blsp1_uart3_apps_clk = {
881+ .halt_reg = 0x21004,
882+ .halt_check = BRANCH_HALT,
883+ .clkr = {
884+ .enable_reg = 0x21004,
885+ .enable_mask = BIT(0),
886+ .hw.init = &(struct clk_init_data){
887+ .name = "gcc_blsp1_uart3_apps_clk",
888+ .parent_data = &(const struct clk_parent_data){
889+ .hw = &gcc_blsp1_uart3_apps_clk_src.clkr.hw,
890+ },
891+ .num_parents = 1,
892+ .flags = CLK_SET_RATE_PARENT,
893+ .ops = &clk_branch2_ops,
894+ },
895+ },
896+};
897+
898+static struct clk_branch gcc_blsp1_uart4_apps_clk = {
899+ .halt_reg = 0x23004,
900+ .halt_check = BRANCH_HALT,
901+ .clkr = {
902+ .enable_reg = 0x23004,
903+ .enable_mask = BIT(0),
904+ .hw.init = &(struct clk_init_data){
905+ .name = "gcc_blsp1_uart4_apps_clk",
906+ .parent_data = &(const struct clk_parent_data){
907+ .hw = &gcc_blsp1_uart4_apps_clk_src.clkr.hw,
908+ },
909+ .num_parents = 1,
910+ .flags = CLK_SET_RATE_PARENT,
911+ .ops = &clk_branch2_ops,
912+ },
913+ },
914+};
915+
916+static struct clk_branch gcc_boot_rom_ahb_clk = {
917+ .halt_reg = 0x27004,
918+ .halt_check = BRANCH_HALT_VOTED,
919+ .hwcg_reg = 0x27004,
920+ .hwcg_bit = 1,
921+ .clkr = {
922+ .enable_reg = 0x6d008,
923+ .enable_mask = BIT(10),
924+ .hw.init = &(struct clk_init_data){
925+ .name = "gcc_boot_rom_ahb_clk",
926+ .ops = &clk_branch2_ops,
927+ },
928+ },
929+};
930+
931+static struct clk_branch gcc_gp1_clk = {
932+ .halt_reg = 0x37000,
933+ .halt_check = BRANCH_HALT,
934+ .clkr = {
935+ .enable_reg = 0x37000,
936+ .enable_mask = BIT(0),
937+ .hw.init = &(struct clk_init_data){
938+ .name = "gcc_gp1_clk",
939+ .parent_data = &(const struct clk_parent_data){
940+ .hw = &gcc_gp1_clk_src.clkr.hw,
941+ },
942+ .num_parents = 1,
943+ .flags = CLK_SET_RATE_PARENT,
944+ .ops = &clk_branch2_ops,
945+ },
946+ },
947+};
948+
949+static struct clk_branch gcc_gp2_clk = {
950+ .halt_reg = 0x38000,
951+ .halt_check = BRANCH_HALT,
952+ .clkr = {
953+ .enable_reg = 0x38000,
954+ .enable_mask = BIT(0),
955+ .hw.init = &(struct clk_init_data){
956+ .name = "gcc_gp2_clk",
957+ .parent_data = &(const struct clk_parent_data){
958+ .hw = &gcc_gp2_clk_src.clkr.hw,
959+ },
960+ .num_parents = 1,
961+ .flags = CLK_SET_RATE_PARENT,
962+ .ops = &clk_branch2_ops,
963+ },
964+ },
965+};
966+
967+static struct clk_branch gcc_gp3_clk = {
968+ .halt_reg = 0x39000,
969+ .halt_check = BRANCH_HALT,
970+ .clkr = {
971+ .enable_reg = 0x39000,
972+ .enable_mask = BIT(0),
973+ .hw.init = &(struct clk_init_data){
974+ .name = "gcc_gp3_clk",
975+ .parent_data = &(const struct clk_parent_data){
976+ .hw = &gcc_gp3_clk_src.clkr.hw,
977+ },
978+ .num_parents = 1,
979+ .flags = CLK_SET_RATE_PARENT,
980+ .ops = &clk_branch2_ops,
981+ },
982+ },
983+};
984+
985+static struct clk_branch gcc_pcie_0_clkref_en = {
986+ .halt_reg = 0x88004,
987+ /*
988+ * The clock controller does not handle the status bit for
989+ * the clocks with gdscs(powerdomains) in hw controlled mode
990+ * and hence avoid checking for the status bit of those clocks
991+ * by setting the BRANCH_HALT_DELAY flag
992+ */
993+ .halt_check = BRANCH_HALT_DELAY,
994+ .clkr = {
995+ .enable_reg = 0x88004,
996+ .enable_mask = BIT(0),
997+ .hw.init = &(struct clk_init_data){
998+ .name = "gcc_pcie_0_clkref_en",
999+ .ops = &clk_branch2_ops,
1000+ },
1001+ },
1002+};
1003+
1004+static struct clk_branch gcc_pcie_aux_clk = {
1005+ .halt_reg = 0x43034,
1006+ /*
1007+ * The clock controller does not handle the status bit for
1008+ * the clocks with gdscs(powerdomains) in hw controlled mode
1009+ * and hence avoid checking for the status bit of those clocks
1010+ * by setting the BRANCH_HALT_DELAY flag
1011+ */
1012+ .halt_check = BRANCH_HALT_DELAY,
1013+ .hwcg_reg = 0x43034,
1014+ .hwcg_bit = 1,
1015+ .clkr = {
1016+ .enable_reg = 0x6d010,
1017+ .enable_mask = BIT(3),
1018+ .hw.init = &(struct clk_init_data){
1019+ .name = "gcc_pcie_aux_clk",
1020+ .parent_data = &(const struct clk_parent_data){
1021+ .hw = &gcc_pcie_aux_clk_src.clkr.hw,
1022+ },
1023+ .num_parents = 1,
1024+ .flags = CLK_SET_RATE_PARENT,
1025+ .ops = &clk_branch2_ops,
1026+ },
1027+ },
1028+};
1029+
1030+static struct clk_branch gcc_pcie_cfg_ahb_clk = {
1031+ .halt_reg = 0x4302c,
1032+ .halt_check = BRANCH_HALT_VOTED,
1033+ .hwcg_reg = 0x4302c,
1034+ .hwcg_bit = 1,
1035+ .clkr = {
1036+ .enable_reg = 0x6d010,
1037+ .enable_mask = BIT(2),
1038+ .hw.init = &(struct clk_init_data){
1039+ .name = "gcc_pcie_cfg_ahb_clk",
1040+ .ops = &clk_branch2_ops,
1041+ },
1042+ },
1043+};
1044+
1045+static struct clk_branch gcc_pcie_mstr_axi_clk = {
1046+ .halt_reg = 0x43024,
1047+ .halt_check = BRANCH_HALT_VOTED,
1048+ .hwcg_reg = 0x43024,
1049+ .hwcg_bit = 1,
1050+ .clkr = {
1051+ .enable_reg = 0x6d010,
1052+ .enable_mask = BIT(1),
1053+ .hw.init = &(struct clk_init_data){
1054+ .name = "gcc_pcie_mstr_axi_clk",
1055+ .ops = &clk_branch2_ops,
1056+ },
1057+ },
1058+};
1059+
1060+static struct clk_branch gcc_pcie_pipe_clk = {
1061+ .halt_reg = 0x4303c,
1062+ /*
1063+ * The clock controller does not handle the status bit for
1064+ * the clocks with gdscs(powerdomains) in hw controlled mode
1065+ * and hence avoid checking for the status bit of those clocks
1066+ * by setting the BRANCH_HALT_DELAY flag
1067+ */
1068+ .halt_check = BRANCH_HALT_DELAY,
1069+ .hwcg_reg = 0x4303c,
1070+ .hwcg_bit = 1,
1071+ .clkr = {
1072+ .enable_reg = 0x6d010,
1073+ .enable_mask = BIT(4),
1074+ .hw.init = &(struct clk_init_data){
1075+ .name = "gcc_pcie_pipe_clk",
1076+ .parent_data = &(const struct clk_parent_data){
1077+ .hw = &gcc_pcie_pipe_clk_src.clkr.hw,
1078+ },
1079+ .num_parents = 1,
1080+ .flags = CLK_SET_RATE_PARENT,
1081+ .ops = &clk_branch2_ops,
1082+ },
1083+ },
1084+};
1085+
1086+static struct clk_branch gcc_pcie_rchng_phy_clk = {
1087+ .halt_reg = 0x43030,
1088+ .halt_check = BRANCH_HALT_VOTED,
1089+ .hwcg_reg = 0x43030,
1090+ .hwcg_bit = 1,
1091+ .clkr = {
1092+ .enable_reg = 0x6d010,
1093+ .enable_mask = BIT(7),
1094+ .hw.init = &(struct clk_init_data){
1095+ .name = "gcc_pcie_rchng_phy_clk",
1096+ .parent_data = &(const struct clk_parent_data){
1097+ .hw = &gcc_pcie_rchng_phy_clk_src.clkr.hw,
1098+ },
1099+ .num_parents = 1,
1100+ .flags = CLK_SET_RATE_PARENT,
1101+ .ops = &clk_branch2_ops,
1102+ },
1103+ },
1104+};
1105+
1106+static struct clk_branch gcc_pcie_sleep_clk = {
1107+ .halt_reg = 0x43038,
1108+ .halt_check = BRANCH_HALT_VOTED,
1109+ .hwcg_reg = 0x43038,
1110+ .hwcg_bit = 1,
1111+ .clkr = {
1112+ .enable_reg = 0x6d010,
1113+ .enable_mask = BIT(6),
1114+ .hw.init = &(struct clk_init_data){
1115+ .name = "gcc_pcie_sleep_clk",
1116+ .parent_data = &(const struct clk_parent_data){
1117+ .hw = &gcc_pcie_aux_phy_clk_src.clkr.hw,
1118+ },
1119+ .num_parents = 1,
1120+ .flags = CLK_SET_RATE_PARENT,
1121+ .ops = &clk_branch2_ops,
1122+ },
1123+ },
1124+};
1125+
1126+static struct clk_branch gcc_pcie_slv_axi_clk = {
1127+ .halt_reg = 0x4301c,
1128+ .halt_check = BRANCH_HALT_VOTED,
1129+ .hwcg_reg = 0x4301c,
1130+ .hwcg_bit = 1,
1131+ .clkr = {
1132+ .enable_reg = 0x6d010,
1133+ .enable_mask = BIT(0),
1134+ .hw.init = &(struct clk_init_data){
1135+ .name = "gcc_pcie_slv_axi_clk",
1136+ .ops = &clk_branch2_ops,
1137+ },
1138+ },
1139+};
1140+
1141+static struct clk_branch gcc_pcie_slv_q2a_axi_clk = {
1142+ .halt_reg = 0x43018,
1143+ .halt_check = BRANCH_HALT_VOTED,
1144+ .hwcg_reg = 0x43018,
1145+ .hwcg_bit = 1,
1146+ .clkr = {
1147+ .enable_reg = 0x6d010,
1148+ .enable_mask = BIT(5),
1149+ .hw.init = &(struct clk_init_data){
1150+ .name = "gcc_pcie_slv_q2a_axi_clk",
1151+ .ops = &clk_branch2_ops,
1152+ },
1153+ },
1154+};
1155+
1156+static struct clk_branch gcc_pdm2_clk = {
1157+ .halt_reg = 0x2400c,
1158+ .halt_check = BRANCH_HALT,
1159+ .clkr = {
1160+ .enable_reg = 0x2400c,
1161+ .enable_mask = BIT(0),
1162+ .hw.init = &(struct clk_init_data){
1163+ .name = "gcc_pdm2_clk",
1164+ .parent_data = &(const struct clk_parent_data){
1165+ .hw = &gcc_pdm2_clk_src.clkr.hw,
1166+ },
1167+ .num_parents = 1,
1168+ .flags = CLK_SET_RATE_PARENT,
1169+ .ops = &clk_branch2_ops,
1170+ },
1171+ },
1172+};
1173+
1174+static struct clk_branch gcc_pdm_ahb_clk = {
1175+ .halt_reg = 0x24004,
1176+ .halt_check = BRANCH_HALT,
1177+ .hwcg_reg = 0x24004,
1178+ .hwcg_bit = 1,
1179+ .clkr = {
1180+ .enable_reg = 0x24004,
1181+ .enable_mask = BIT(0),
1182+ .hw.init = &(struct clk_init_data){
1183+ .name = "gcc_pdm_ahb_clk",
1184+ .ops = &clk_branch2_ops,
1185+ },
1186+ },
1187+};
1188+
1189+static struct clk_branch gcc_pdm_xo4_clk = {
1190+ .halt_reg = 0x24008,
1191+ .halt_check = BRANCH_HALT,
1192+ .clkr = {
1193+ .enable_reg = 0x24008,
1194+ .enable_mask = BIT(0),
1195+ .hw.init = &(struct clk_init_data){
1196+ .name = "gcc_pdm_xo4_clk",
1197+ .ops = &clk_branch2_ops,
1198+ },
1199+ },
1200+};
1201+
1202+static struct clk_branch gcc_rx1_usb2_clkref_en = {
1203+ .halt_reg = 0x88008,
1204+ .halt_check = BRANCH_HALT,
1205+ .clkr = {
1206+ .enable_reg = 0x88008,
1207+ .enable_mask = BIT(0),
1208+ .hw.init = &(struct clk_init_data){
1209+ .name = "gcc_rx1_usb2_clkref_en",
1210+ .ops = &clk_branch2_ops,
1211+ },
1212+ },
1213+};
1214+
1215+static struct clk_branch gcc_sdcc1_ahb_clk = {
1216+ .halt_reg = 0x1a00c,
1217+ .halt_check = BRANCH_HALT,
1218+ .clkr = {
1219+ .enable_reg = 0x1a00c,
1220+ .enable_mask = BIT(0),
1221+ .hw.init = &(struct clk_init_data){
1222+ .name = "gcc_sdcc1_ahb_clk",
1223+ .ops = &clk_branch2_ops,
1224+ },
1225+ },
1226+};
1227+
1228+static struct clk_branch gcc_sdcc1_apps_clk = {
1229+ .halt_reg = 0x1a004,
1230+ .halt_check = BRANCH_HALT,
1231+ .clkr = {
1232+ .enable_reg = 0x1a004,
1233+ .enable_mask = BIT(0),
1234+ .hw.init = &(struct clk_init_data){
1235+ .name = "gcc_sdcc1_apps_clk",
1236+ .parent_data = &(const struct clk_parent_data){
1237+ .hw = &gcc_sdcc1_apps_clk_src.clkr.hw,
1238+ },
1239+ .num_parents = 1,
1240+ .flags = CLK_SET_RATE_PARENT,
1241+ .ops = &clk_branch2_ops,
1242+ },
1243+ },
1244+};
1245+
1246+static struct clk_branch gcc_usb30_master_clk = {
1247+ .halt_reg = 0x17018,
1248+ .halt_check = BRANCH_HALT,
1249+ .clkr = {
1250+ .enable_reg = 0x17018,
1251+ .enable_mask = BIT(0),
1252+ .hw.init = &(struct clk_init_data){
1253+ .name = "gcc_usb30_master_clk",
1254+ .parent_data = &(const struct clk_parent_data){
1255+ .hw = &gcc_usb30_master_clk_src.clkr.hw,
1256+ },
1257+ .num_parents = 1,
1258+ .flags = CLK_SET_RATE_PARENT,
1259+ .ops = &clk_branch2_ops,
1260+ },
1261+ },
1262+};
1263+
1264+static struct clk_branch gcc_usb30_mock_utmi_clk = {
1265+ .halt_reg = 0x1702c,
1266+ .halt_check = BRANCH_HALT,
1267+ .clkr = {
1268+ .enable_reg = 0x1702c,
1269+ .enable_mask = BIT(0),
1270+ .hw.init = &(struct clk_init_data){
1271+ .name = "gcc_usb30_mock_utmi_clk",
1272+ .parent_data = &(const struct clk_parent_data){
1273+ .hw =
1274+ &gcc_usb30_mock_utmi_postdiv_clk_src.clkr.hw,
1275+ },
1276+ .num_parents = 1,
1277+ .flags = CLK_SET_RATE_PARENT,
1278+ .ops = &clk_branch2_ops,
1279+ },
1280+ },
1281+};
1282+
1283+static struct clk_branch gcc_usb30_mstr_axi_clk = {
1284+ .halt_reg = 0x17020,
1285+ .halt_check = BRANCH_HALT,
1286+ .clkr = {
1287+ .enable_reg = 0x17020,
1288+ .enable_mask = BIT(0),
1289+ .hw.init = &(struct clk_init_data){
1290+ .name = "gcc_usb30_mstr_axi_clk",
1291+ .ops = &clk_branch2_ops,
1292+ },
1293+ },
1294+};
1295+
1296+static struct clk_branch gcc_usb30_sleep_clk = {
1297+ .halt_reg = 0x17028,
1298+ .halt_check = BRANCH_HALT,
1299+ .clkr = {
1300+ .enable_reg = 0x17028,
1301+ .enable_mask = BIT(0),
1302+ .hw.init = &(struct clk_init_data){
1303+ .name = "gcc_usb30_sleep_clk",
1304+ .ops = &clk_branch2_ops,
1305+ },
1306+ },
1307+};
1308+
1309+static struct clk_branch gcc_usb30_slv_ahb_clk = {
1310+ .halt_reg = 0x17024,
1311+ .halt_check = BRANCH_HALT,
1312+ .clkr = {
1313+ .enable_reg = 0x17024,
1314+ .enable_mask = BIT(0),
1315+ .hw.init = &(struct clk_init_data){
1316+ .name = "gcc_usb30_slv_ahb_clk",
1317+ .ops = &clk_branch2_ops,
1318+ },
1319+ },
1320+};
1321+
1322+static struct clk_branch gcc_usb3_phy_aux_clk = {
1323+ .halt_reg = 0x17064,
1324+ .halt_check = BRANCH_HALT,
1325+ .clkr = {
1326+ .enable_reg = 0x17064,
1327+ .enable_mask = BIT(0),
1328+ .hw.init = &(struct clk_init_data){
1329+ .name = "gcc_usb3_phy_aux_clk",
1330+ .parent_data = &(const struct clk_parent_data){
1331+ .hw = &gcc_usb3_phy_aux_clk_src.clkr.hw,
1332+ },
1333+ .num_parents = 1,
1334+ .flags = CLK_SET_RATE_PARENT,
1335+ .ops = &clk_branch2_ops,
1336+ },
1337+ },
1338+};
1339+
1340+static struct gdsc usb30_gdsc = {
1341+ .gdscr = 0x17004,
1342+ .pd = {
1343+ .name = "usb30_gdsc",
1344+ },
1345+ .pwrsts = PWRSTS_OFF_ON,
1346+};
1347+
1348+static struct gdsc pcie_gdsc = {
1349+ .gdscr = 0x43004,
1350+ .pd = {
1351+ .name = "pcie_gdsc",
1352+ },
1353+ .pwrsts = PWRSTS_OFF_ON,
1354+};
1355+
1356+static struct clk_branch gcc_usb3_phy_pipe_clk = {
1357+ .halt_reg = 0x17068,
1358+ /*
1359+ * The clock controller does not handle the status bit for
1360+ * the clocks with gdscs(powerdomains) in hw controlled mode
1361+ * and hence avoid checking for the status bit of those clocks
1362+ * by setting the BRANCH_HALT_DELAY flag
1363+ */
1364+ .halt_check = BRANCH_HALT_DELAY,
1365+ .hwcg_reg = 0x17068,
1366+ .hwcg_bit = 1,
1367+ .clkr = {
1368+ .enable_reg = 0x17068,
1369+ .enable_mask = BIT(0),
1370+ .hw.init = &(struct clk_init_data){
1371+ .name = "gcc_usb3_phy_pipe_clk",
1372+ .parent_data = &(const struct clk_parent_data){
1373+ .hw = &gcc_usb3_phy_pipe_clk_src.clkr.hw,
1374+ },
1375+ .num_parents = 1,
1376+ .flags = CLK_SET_RATE_PARENT,
1377+ .ops = &clk_branch2_ops,
1378+ },
1379+ },
1380+};
1381+
1382+static struct clk_branch gcc_usb3_prim_clkref_en = {
1383+ .halt_reg = 0x88000,
1384+ .halt_check = BRANCH_HALT,
1385+ .clkr = {
1386+ .enable_reg = 0x88000,
1387+ .enable_mask = BIT(0),
1388+ .hw.init = &(struct clk_init_data){
1389+ .name = "gcc_usb3_prim_clkref_en",
1390+ .ops = &clk_branch2_ops,
1391+ },
1392+ },
1393+};
1394+
1395+static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
1396+ .halt_reg = 0x19008,
1397+ .halt_check = BRANCH_HALT,
1398+ .hwcg_reg = 0x19008,
1399+ .hwcg_bit = 1,
1400+ .clkr = {
1401+ .enable_reg = 0x19008,
1402+ .enable_mask = BIT(0),
1403+ .hw.init = &(struct clk_init_data){
1404+ .name = "gcc_usb_phy_cfg_ahb2phy_clk",
1405+ .ops = &clk_branch2_ops,
1406+ },
1407+ },
1408+};
1409+
1410+static struct clk_branch gcc_xo_div4_clk = {
1411+ .halt_reg = 0x2e010,
1412+ .halt_check = BRANCH_HALT,
1413+ .clkr = {
1414+ .enable_reg = 0x2e010,
1415+ .enable_mask = BIT(0),
1416+ .hw.init = &(struct clk_init_data){
1417+ .name = "gcc_xo_div4_clk",
1418+ .ops = &clk_branch2_ops,
1419+ },
1420+ },
1421+};
1422+
1423+static struct clk_branch gcc_xo_pcie_link_clk = {
1424+ .halt_reg = 0x2e008,
1425+ .halt_check = BRANCH_HALT,
1426+ .hwcg_reg = 0x2e008,
1427+ .hwcg_bit = 1,
1428+ .clkr = {
1429+ .enable_reg = 0x2e008,
1430+ .enable_mask = BIT(0),
1431+ .hw.init = &(struct clk_init_data){
1432+ .name = "gcc_xo_pcie_link_clk",
1433+ .ops = &clk_branch2_ops,
1434+ },
1435+ },
1436+};
1437+
1438+static struct clk_regmap *gcc_sdx65_clocks[] = {
1439+ [GCC_AHB_PCIE_LINK_CLK] = &gcc_ahb_pcie_link_clk.clkr,
1440+ [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
1441+ [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
1442+ [GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC] = &gcc_blsp1_qup1_i2c_apps_clk_src.clkr,
1443+ [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
1444+ [GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup1_spi_apps_clk_src.clkr,
1445+ [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
1446+ [GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC] = &gcc_blsp1_qup2_i2c_apps_clk_src.clkr,
1447+ [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
1448+ [GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup2_spi_apps_clk_src.clkr,
1449+ [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
1450+ [GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC] = &gcc_blsp1_qup3_i2c_apps_clk_src.clkr,
1451+ [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
1452+ [GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup3_spi_apps_clk_src.clkr,
1453+ [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
1454+ [GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC] = &gcc_blsp1_qup4_i2c_apps_clk_src.clkr,
1455+ [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
1456+ [GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup4_spi_apps_clk_src.clkr,
1457+ [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
1458+ [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
1459+ [GCC_BLSP1_UART1_APPS_CLK_SRC] = &gcc_blsp1_uart1_apps_clk_src.clkr,
1460+ [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
1461+ [GCC_BLSP1_UART2_APPS_CLK_SRC] = &gcc_blsp1_uart2_apps_clk_src.clkr,
1462+ [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
1463+ [GCC_BLSP1_UART3_APPS_CLK_SRC] = &gcc_blsp1_uart3_apps_clk_src.clkr,
1464+ [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
1465+ [GCC_BLSP1_UART4_APPS_CLK_SRC] = &gcc_blsp1_uart4_apps_clk_src.clkr,
1466+ [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
1467+ [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
1468+ [GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr,
1469+ [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
1470+ [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
1471+ [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
1472+ [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
1473+ [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
1474+ [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
1475+ [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,
1476+ [GCC_PCIE_AUX_CLK] = &gcc_pcie_aux_clk.clkr,
1477+ [GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr,
1478+ [GCC_PCIE_AUX_PHY_CLK_SRC] = &gcc_pcie_aux_phy_clk_src.clkr,
1479+ [GCC_PCIE_CFG_AHB_CLK] = &gcc_pcie_cfg_ahb_clk.clkr,
1480+ [GCC_PCIE_MSTR_AXI_CLK] = &gcc_pcie_mstr_axi_clk.clkr,
1481+ [GCC_PCIE_PIPE_CLK] = &gcc_pcie_pipe_clk.clkr,
1482+ [GCC_PCIE_PIPE_CLK_SRC] = &gcc_pcie_pipe_clk_src.clkr,
1483+ [GCC_PCIE_RCHNG_PHY_CLK] = &gcc_pcie_rchng_phy_clk.clkr,
1484+ [GCC_PCIE_RCHNG_PHY_CLK_SRC] = &gcc_pcie_rchng_phy_clk_src.clkr,
1485+ [GCC_PCIE_SLEEP_CLK] = &gcc_pcie_sleep_clk.clkr,
1486+ [GCC_PCIE_SLV_AXI_CLK] = &gcc_pcie_slv_axi_clk.clkr,
1487+ [GCC_PCIE_SLV_Q2A_AXI_CLK] = &gcc_pcie_slv_q2a_axi_clk.clkr,
1488+ [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
1489+ [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
1490+ [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
1491+ [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
1492+ [GCC_RX1_USB2_CLKREF_EN] = &gcc_rx1_usb2_clkref_en.clkr,
1493+ [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
1494+ [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
1495+ [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
1496+ [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
1497+ [GCC_USB30_MASTER_CLK_SRC] = &gcc_usb30_master_clk_src.clkr,
1498+ [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
1499+ [GCC_USB30_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mock_utmi_clk_src.clkr,
1500+ [GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mock_utmi_postdiv_clk_src.clkr,
1501+ [GCC_USB30_MSTR_AXI_CLK] = &gcc_usb30_mstr_axi_clk.clkr,
1502+ [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
1503+ [GCC_USB30_SLV_AHB_CLK] = &gcc_usb30_slv_ahb_clk.clkr,
1504+ [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
1505+ [GCC_USB3_PHY_AUX_CLK_SRC] = &gcc_usb3_phy_aux_clk_src.clkr,
1506+ [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
1507+ [GCC_USB3_PHY_PIPE_CLK_SRC] = &gcc_usb3_phy_pipe_clk_src.clkr,
1508+ [GCC_USB3_PRIM_CLKREF_EN] = &gcc_usb3_prim_clkref_en.clkr,
1509+ [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
1510+ [GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
1511+ [GCC_XO_PCIE_LINK_CLK] = &gcc_xo_pcie_link_clk.clkr,
1512+ [GPLL0] = &gpll0.clkr,
1513+ [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
1514+};
1515+
1516+static const struct qcom_reset_map gcc_sdx65_resets[] = {
1517+ [GCC_BLSP1_QUP1_BCR] = { 0x1c000 },
1518+ [GCC_BLSP1_QUP2_BCR] = { 0x1e000 },
1519+ [GCC_BLSP1_QUP3_BCR] = { 0x20000 },
1520+ [GCC_BLSP1_QUP4_BCR] = { 0x22000 },
1521+ [GCC_BLSP1_UART1_BCR] = { 0x1d000 },
1522+ [GCC_BLSP1_UART2_BCR] = { 0x1f000 },
1523+ [GCC_BLSP1_UART3_BCR] = { 0x21000 },
1524+ [GCC_BLSP1_UART4_BCR] = { 0x23000 },
1525+ [GCC_PCIE_BCR] = { 0x43000 },
1526+ [GCC_PCIE_LINK_DOWN_BCR] = { 0x77000 },
1527+ [GCC_PCIE_NOCSR_COM_PHY_BCR] = { 0x78008 },
1528+ [GCC_PCIE_PHY_BCR] = { 0x44000 },
1529+ [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x78000 },
1530+ [GCC_PCIE_PHY_COM_BCR] = { 0x78004 },
1531+ [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x7800c },
1532+ [GCC_PDM_BCR] = { 0x24000 },
1533+ [GCC_QUSB2PHY_BCR] = { 0x19000 },
1534+ [GCC_SDCC1_BCR] = { 0x1a000 },
1535+ [GCC_TCSR_PCIE_BCR] = { 0x57000 },
1536+ [GCC_USB30_BCR] = { 0x17000 },
1537+ [GCC_USB3_PHY_BCR] = { 0x18000 },
1538+ [GCC_USB3PHY_PHY_BCR] = { 0x18004 },
1539+ [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x19004 },
1540+};
1541+
1542+static struct gdsc *gcc_sdx65_gdscs[] = {
1543+ [USB30_GDSC] = &usb30_gdsc,
1544+ [PCIE_GDSC] = &pcie_gdsc,
1545+};
1546+
1547+static const struct regmap_config gcc_sdx65_regmap_config = {
1548+ .reg_bits = 32,
1549+ .reg_stride = 4,
1550+ .val_bits = 32,
1551+ .max_register = 0x1f101c,
1552+ .fast_io = true,
1553+};
1554+
1555+static const struct qcom_cc_desc gcc_sdx65_desc = {
1556+ .config = &gcc_sdx65_regmap_config,
1557+ .clks = gcc_sdx65_clocks,
1558+ .num_clks = ARRAY_SIZE(gcc_sdx65_clocks),
1559+ .resets = gcc_sdx65_resets,
1560+ .num_resets = ARRAY_SIZE(gcc_sdx65_resets),
1561+ .gdscs = gcc_sdx65_gdscs,
1562+ .num_gdscs = ARRAY_SIZE(gcc_sdx65_gdscs),
1563+};
1564+
1565+static const struct of_device_id gcc_sdx65_match_table[] = {
1566+ { .compatible = "qcom,gcc-sdx65" },
1567+ { }
1568+};
1569+MODULE_DEVICE_TABLE(of, gcc_sdx65_match_table);
1570+
1571+static int gcc_sdx65_probe(struct platform_device *pdev)
1572+{
1573+ struct regmap *regmap;
1574+
1575+ regmap = qcom_cc_map(pdev, &gcc_sdx65_desc);
1576+ if (IS_ERR(regmap))
1577+ return PTR_ERR(regmap);
1578+ /*
1579+ * Keep the clocks always-ON as they are critical to the functioning
1580+ * of the system:
1581+ * GCC_SYS_NOC_CPUSS_AHB_CLK, GCC_CPUSS_AHB_CLK, GCC_CPUSS_GNOC_CLK
1582+ */
1583+ regmap_update_bits(regmap, 0x6d008, BIT(0), BIT(0));
1584+ regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21));
1585+ regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22));
1586+
1587+ return qcom_cc_really_probe(pdev, &gcc_sdx65_desc, regmap);
1588+}
1589+
1590+static struct platform_driver gcc_sdx65_driver = {
1591+ .probe = gcc_sdx65_probe,
1592+ .driver = {
1593+ .name = "gcc-sdx65",
1594+ .of_match_table = gcc_sdx65_match_table,
1595+ },
1596+};
1597+
1598+static int __init gcc_sdx65_init(void)
1599+{
1600+ return platform_driver_register(&gcc_sdx65_driver);
1601+}
1602+subsys_initcall(gcc_sdx65_init);
1603+
1604+static void __exit gcc_sdx65_exit(void)
1605+{
1606+ platform_driver_unregister(&gcc_sdx65_driver);
1607+}
1608+module_exit(gcc_sdx65_exit);
1609+
1610+MODULE_DESCRIPTION("QTI GCC SDX65 Driver");
1611+MODULE_LICENSE("GPL v2");
drivers/clk/qcom/gcc-sm6350.c+1−0
@@ -4,6 +4,7 @@ · 3 unmodified lines
44 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
55 */
66
7+#include <linux/clk-provider.h>
78 #include <linux/module.h>
89 #include <linux/platform_device.h>
910 #include <linux/regmap.h>
drivers/clk/qcom/gcc-sm8350.c+1−0
@@ -4,6 +4,7 @@ · 3 unmodified lines
44 * Copyright (c) 2020-2021, Linaro Limited
55 */
66
7+#include <linux/clk-provider.h>
78 #include <linux/module.h>
89 #include <linux/platform_device.h>
910 #include <linux/regmap.h>
drivers/clk/qcom/gcc-sm8450.c+3304−0
@@ -0,0 +1,3304 @@
1+// SPDX-License-Identifier: GPL-2.0-only
2+/*
3+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4+ * Copyright (c) 2021, Linaro Limited
5+ */
6+
7+#include <linux/clk-provider.h>
8+#include <linux/module.h>
9+#include <linux/of_device.h>
10+#include <linux/regmap.h>
11+
12+#include <dt-bindings/clock/qcom,gcc-sm8450.h>
13+
14+#include "clk-alpha-pll.h"
15+#include "clk-branch.h"
16+#include "clk-rcg.h"
17+#include "clk-regmap.h"
18+#include "clk-regmap-divider.h"
19+#include "clk-regmap-mux.h"
20+#include "gdsc.h"
21+#include "reset.h"
22+
23+enum {
24+ P_BI_TCXO,
25+ P_GCC_GPLL0_OUT_EVEN,
26+ P_GCC_GPLL0_OUT_MAIN,
27+ P_GCC_GPLL4_OUT_MAIN,
28+ P_GCC_GPLL9_OUT_MAIN,
29+ P_PCIE_0_PIPE_CLK,
30+ P_PCIE_1_PHY_AUX_CLK,
31+ P_PCIE_1_PIPE_CLK,
32+ P_SLEEP_CLK,
33+ P_UFS_PHY_RX_SYMBOL_0_CLK,
34+ P_UFS_PHY_RX_SYMBOL_1_CLK,
35+ P_UFS_PHY_TX_SYMBOL_0_CLK,
36+ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
37+};
38+
39+static struct clk_alpha_pll gcc_gpll0 = {
40+ .offset = 0x0,
41+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
42+ .clkr = {
43+ .enable_reg = 0x62018,
44+ .enable_mask = BIT(0),
45+ .hw.init = &(struct clk_init_data){
46+ .name = "gcc_gpll0",
47+ .parent_data = &(const struct clk_parent_data){
48+ .fw_name = "bi_tcxo",
49+ },
50+ .num_parents = 1,
51+ .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
52+ },
53+ },
54+};
55+
56+static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
57+ { 0x1, 2 },
58+ { }
59+};
60+
61+static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
62+ .offset = 0x0,
63+ .post_div_shift = 10,
64+ .post_div_table = post_div_table_gcc_gpll0_out_even,
65+ .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
66+ .width = 4,
67+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
68+ .clkr.hw.init = &(struct clk_init_data){
69+ .name = "gcc_gpll0_out_even",
70+ .parent_data = &(const struct clk_parent_data){
71+ .hw = &gcc_gpll0.clkr.hw,
72+ },
73+ .num_parents = 1,
74+ .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
75+ },
76+};
77+
78+static struct clk_alpha_pll gcc_gpll4 = {
79+ .offset = 0x4000,
80+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
81+ .clkr = {
82+ .enable_reg = 0x62018,
83+ .enable_mask = BIT(4),
84+ .hw.init = &(struct clk_init_data){
85+ .name = "gcc_gpll4",
86+ .parent_data = &(const struct clk_parent_data){
87+ .fw_name = "bi_tcxo",
88+ },
89+ .num_parents = 1,
90+ .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
91+ },
92+ },
93+};
94+
95+static struct clk_alpha_pll gcc_gpll9 = {
96+ .offset = 0x9000,
97+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
98+ .clkr = {
99+ .enable_reg = 0x62018,
100+ .enable_mask = BIT(9),
101+ .hw.init = &(struct clk_init_data){
102+ .name = "gcc_gpll9",
103+ .parent_data = &(const struct clk_parent_data){
104+ .fw_name = "bi_tcxo",
105+ },
106+ .num_parents = 1,
107+ .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
108+ },
109+ },
110+};
111+
112+static const struct parent_map gcc_parent_map_0[] = {
113+ { P_BI_TCXO, 0 },
114+ { P_GCC_GPLL0_OUT_MAIN, 1 },
115+ { P_GCC_GPLL0_OUT_EVEN, 6 },
116+};
117+
118+static const struct clk_parent_data gcc_parent_data_0[] = {
119+ { .fw_name = "bi_tcxo" },
120+ { .hw = &gcc_gpll0.clkr.hw },
121+ { .hw = &gcc_gpll0_out_even.clkr.hw },
122+};
123+
124+static const struct parent_map gcc_parent_map_1[] = {
125+ { P_BI_TCXO, 0 },
126+ { P_GCC_GPLL0_OUT_MAIN, 1 },
127+ { P_SLEEP_CLK, 5 },
128+ { P_GCC_GPLL0_OUT_EVEN, 6 },
129+};
130+
131+static const struct clk_parent_data gcc_parent_data_1[] = {
132+ { .fw_name = "bi_tcxo" },
133+ { .hw = &gcc_gpll0.clkr.hw },
134+ { .fw_name = "sleep_clk" },
135+ { .hw = &gcc_gpll0_out_even.clkr.hw },
136+};
137+
138+static const struct parent_map gcc_parent_map_2[] = {
139+ { P_BI_TCXO, 0 },
140+ { P_SLEEP_CLK, 5 },
141+};
142+
143+static const struct clk_parent_data gcc_parent_data_2[] = {
144+ { .fw_name = "bi_tcxo" },
145+ { .fw_name = "sleep_clk" },
146+};
147+
148+static const struct parent_map gcc_parent_map_3[] = {
149+ { P_BI_TCXO, 0 },
150+};
151+
152+static const struct clk_parent_data gcc_parent_data_3[] = {
153+ { .fw_name = "bi_tcxo" },
154+};
155+
156+static const struct parent_map gcc_parent_map_4[] = {
157+ { P_PCIE_0_PIPE_CLK, 0 },
158+ { P_BI_TCXO, 2 },
159+};
160+
161+static const struct clk_parent_data gcc_parent_data_4[] = {
162+ { .fw_name = "pcie_0_pipe_clk", },
163+ { .fw_name = "bi_tcxo", },
164+};
165+
166+static const struct parent_map gcc_parent_map_5[] = {
167+ { P_PCIE_1_PHY_AUX_CLK, 0 },
168+ { P_BI_TCXO, 2 },
169+};
170+
171+static const struct clk_parent_data gcc_parent_data_5[] = {
172+ { .fw_name = "pcie_1_phy_aux_clk" },
173+ { .fw_name = "bi_tcxo" },
174+};
175+
176+static const struct parent_map gcc_parent_map_6[] = {
177+ { P_PCIE_1_PIPE_CLK, 0 },
178+ { P_BI_TCXO, 2 },
179+};
180+
181+static const struct clk_parent_data gcc_parent_data_6[] = {
182+ { .fw_name = "pcie_1_pipe_clk" },
183+ { .fw_name = "bi_tcxo" },
184+};
185+
186+static const struct parent_map gcc_parent_map_7[] = {
187+ { P_BI_TCXO, 0 },
188+ { P_GCC_GPLL0_OUT_MAIN, 1 },
189+ { P_GCC_GPLL9_OUT_MAIN, 2 },
190+ { P_GCC_GPLL4_OUT_MAIN, 5 },
191+ { P_GCC_GPLL0_OUT_EVEN, 6 },
192+};
193+
194+static const struct clk_parent_data gcc_parent_data_7[] = {
195+ { .fw_name = "bi_tcxo" },
196+ { .hw = &gcc_gpll0.clkr.hw },
197+ { .hw = &gcc_gpll9.clkr.hw },
198+ { .hw = &gcc_gpll4.clkr.hw },
199+ { .hw = &gcc_gpll0_out_even.clkr.hw },
200+};
201+
202+static const struct parent_map gcc_parent_map_8[] = {
203+ { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
204+ { P_BI_TCXO, 2 },
205+};
206+
207+static const struct clk_parent_data gcc_parent_data_8[] = {
208+ { .fw_name = "ufs_phy_rx_symbol_0_clk" },
209+ { .fw_name = "bi_tcxo" },
210+};
211+
212+static const struct parent_map gcc_parent_map_9[] = {
213+ { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
214+ { P_BI_TCXO, 2 },
215+};
216+
217+static const struct clk_parent_data gcc_parent_data_9[] = {
218+ { .fw_name = "ufs_phy_rx_symbol_1_clk" },
219+ { .fw_name = "bi_tcxo" },
220+};
221+
222+static const struct parent_map gcc_parent_map_10[] = {
223+ { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
224+ { P_BI_TCXO, 2 },
225+};
226+
227+static const struct clk_parent_data gcc_parent_data_10[] = {
228+ { .fw_name = "ufs_phy_tx_symbol_0_clk" },
229+ { .fw_name = "bi_tcxo" },
230+};
231+
232+static const struct parent_map gcc_parent_map_11[] = {
233+ { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
234+ { P_BI_TCXO, 2 },
235+};
236+
237+static const struct clk_parent_data gcc_parent_data_11[] = {
238+ { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
239+ { .fw_name = "bi_tcxo" },
240+};
241+
242+static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
243+ .reg = 0x7b060,
244+ .shift = 0,
245+ .width = 2,
246+ .parent_map = gcc_parent_map_4,
247+ .clkr = {
248+ .hw.init = &(struct clk_init_data){
249+ .name = "gcc_pcie_0_pipe_clk_src",
250+ .parent_data = gcc_parent_data_4,
251+ .num_parents = ARRAY_SIZE(gcc_parent_data_4),
252+ .ops = &clk_regmap_mux_closest_ops,
253+ },
254+ },
255+};
256+
257+static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = {
258+ .reg = 0x9d080,
259+ .shift = 0,
260+ .width = 2,
261+ .parent_map = gcc_parent_map_5,
262+ .clkr = {
263+ .hw.init = &(struct clk_init_data){
264+ .name = "gcc_pcie_1_phy_aux_clk_src",
265+ .parent_data = gcc_parent_data_5,
266+ .num_parents = ARRAY_SIZE(gcc_parent_data_5),
267+ .ops = &clk_regmap_mux_closest_ops,
268+ },
269+ },
270+};
271+
272+static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
273+ .reg = 0x9d064,
274+ .shift = 0,
275+ .width = 2,
276+ .parent_map = gcc_parent_map_6,
277+ .clkr = {
278+ .hw.init = &(struct clk_init_data){
279+ .name = "gcc_pcie_1_pipe_clk_src",
280+ .parent_data = gcc_parent_data_6,
281+ .num_parents = ARRAY_SIZE(gcc_parent_data_6),
282+ .ops = &clk_regmap_mux_closest_ops,
283+ },
284+ },
285+};
286+
287+static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
288+ .reg = 0x87060,
289+ .shift = 0,
290+ .width = 2,
291+ .parent_map = gcc_parent_map_8,
292+ .clkr = {
293+ .hw.init = &(struct clk_init_data){
294+ .name = "gcc_ufs_phy_rx_symbol_0_clk_src",
295+ .parent_data = gcc_parent_data_8,
296+ .num_parents = ARRAY_SIZE(gcc_parent_data_8),
297+ .ops = &clk_regmap_mux_closest_ops,
298+ },
299+ },
300+};
301+
302+static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
303+ .reg = 0x870d0,
304+ .shift = 0,
305+ .width = 2,
306+ .parent_map = gcc_parent_map_9,
307+ .clkr = {
308+ .hw.init = &(struct clk_init_data){
309+ .name = "gcc_ufs_phy_rx_symbol_1_clk_src",
310+ .parent_data = gcc_parent_data_9,
311+ .num_parents = ARRAY_SIZE(gcc_parent_data_9),
312+ .ops = &clk_regmap_mux_closest_ops,
313+ },
314+ },
315+};
316+
317+static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
318+ .reg = 0x87050,
319+ .shift = 0,
320+ .width = 2,
321+ .parent_map = gcc_parent_map_10,
322+ .clkr = {
323+ .hw.init = &(struct clk_init_data){
324+ .name = "gcc_ufs_phy_tx_symbol_0_clk_src",
325+ .parent_data = gcc_parent_data_10,
326+ .num_parents = ARRAY_SIZE(gcc_parent_data_10),
327+ .ops = &clk_regmap_mux_closest_ops,
328+ },
329+ },
330+};
331+
332+static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
333+ .reg = 0x49068,
334+ .shift = 0,
335+ .width = 2,
336+ .parent_map = gcc_parent_map_11,
337+ .clkr = {
338+ .hw.init = &(struct clk_init_data){
339+ .name = "gcc_usb3_prim_phy_pipe_clk_src",
340+ .parent_data = gcc_parent_data_11,
341+ .num_parents = ARRAY_SIZE(gcc_parent_data_11),
342+ .ops = &clk_regmap_mux_closest_ops,
343+ },
344+ },
345+};
346+
347+static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
348+ F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
349+ F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
350+ F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
351+ { }
352+};
353+
354+static struct clk_rcg2 gcc_gp1_clk_src = {
355+ .cmd_rcgr = 0x74004,
356+ .mnd_width = 8,
357+ .hid_width = 5,
358+ .parent_map = gcc_parent_map_1,
359+ .freq_tbl = ftbl_gcc_gp1_clk_src,
360+ .clkr.hw.init = &(struct clk_init_data){
361+ .name = "gcc_gp1_clk_src",
362+ .parent_data = gcc_parent_data_1,
363+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
364+ .flags = CLK_SET_RATE_PARENT,
365+ .ops = &clk_rcg2_ops,
366+ },
367+};
368+
369+static struct clk_rcg2 gcc_gp2_clk_src = {
370+ .cmd_rcgr = 0x75004,
371+ .mnd_width = 8,
372+ .hid_width = 5,
373+ .parent_map = gcc_parent_map_1,
374+ .freq_tbl = ftbl_gcc_gp1_clk_src,
375+ .clkr.hw.init = &(struct clk_init_data){
376+ .name = "gcc_gp2_clk_src",
377+ .parent_data = gcc_parent_data_1,
378+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
379+ .flags = CLK_SET_RATE_PARENT,
380+ .ops = &clk_rcg2_ops,
381+ },
382+};
383+
384+static struct clk_rcg2 gcc_gp3_clk_src = {
385+ .cmd_rcgr = 0x76004,
386+ .mnd_width = 8,
387+ .hid_width = 5,
388+ .parent_map = gcc_parent_map_1,
389+ .freq_tbl = ftbl_gcc_gp1_clk_src,
390+ .clkr.hw.init = &(struct clk_init_data){
391+ .name = "gcc_gp3_clk_src",
392+ .parent_data = gcc_parent_data_1,
393+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
394+ .flags = CLK_SET_RATE_PARENT,
395+ .ops = &clk_rcg2_ops,
396+ },
397+};
398+
399+static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
400+ F(19200000, P_BI_TCXO, 1, 0, 0),
401+ { }
402+};
403+
404+static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
405+ .cmd_rcgr = 0x7b064,
406+ .mnd_width = 16,
407+ .hid_width = 5,
408+ .parent_map = gcc_parent_map_2,
409+ .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
410+ .clkr.hw.init = &(struct clk_init_data){
411+ .name = "gcc_pcie_0_aux_clk_src",
412+ .parent_data = gcc_parent_data_2,
413+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
414+ .flags = CLK_SET_RATE_PARENT,
415+ .ops = &clk_rcg2_ops,
416+ },
417+};
418+
419+static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
420+ F(19200000, P_BI_TCXO, 1, 0, 0),
421+ F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
422+ { }
423+};
424+
425+static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
426+ .cmd_rcgr = 0x7b048,
427+ .mnd_width = 0,
428+ .hid_width = 5,
429+ .parent_map = gcc_parent_map_0,
430+ .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
431+ .clkr.hw.init = &(struct clk_init_data){
432+ .name = "gcc_pcie_0_phy_rchng_clk_src",
433+ .parent_data = gcc_parent_data_0,
434+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
435+ .flags = CLK_SET_RATE_PARENT,
436+ .ops = &clk_rcg2_ops,
437+ },
438+};
439+
440+static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
441+ .cmd_rcgr = 0x9d068,
442+ .mnd_width = 16,
443+ .hid_width = 5,
444+ .parent_map = gcc_parent_map_2,
445+ .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
446+ .clkr.hw.init = &(struct clk_init_data){
447+ .name = "gcc_pcie_1_aux_clk_src",
448+ .parent_data = gcc_parent_data_2,
449+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
450+ .flags = CLK_SET_RATE_PARENT,
451+ .ops = &clk_rcg2_ops,
452+ },
453+};
454+
455+static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
456+ .cmd_rcgr = 0x9d04c,
457+ .mnd_width = 0,
458+ .hid_width = 5,
459+ .parent_map = gcc_parent_map_0,
460+ .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
461+ .clkr.hw.init = &(struct clk_init_data){
462+ .name = "gcc_pcie_1_phy_rchng_clk_src",
463+ .parent_data = gcc_parent_data_0,
464+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
465+ .flags = CLK_SET_RATE_PARENT,
466+ .ops = &clk_rcg2_ops,
467+ },
468+};
469+
470+static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
471+ F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
472+ { }
473+};
474+
475+static struct clk_rcg2 gcc_pdm2_clk_src = {
476+ .cmd_rcgr = 0x43010,
477+ .mnd_width = 0,
478+ .hid_width = 5,
479+ .parent_map = gcc_parent_map_0,
480+ .freq_tbl = ftbl_gcc_pdm2_clk_src,
481+ .clkr.hw.init = &(struct clk_init_data){
482+ .name = "gcc_pdm2_clk_src",
483+ .parent_data = gcc_parent_data_0,
484+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
485+ .flags = CLK_SET_RATE_PARENT,
486+ .ops = &clk_rcg2_ops,
487+ },
488+};
489+
490+static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
491+ F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
492+ F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
493+ F(19200000, P_BI_TCXO, 1, 0, 0),
494+ F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
495+ F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
496+ F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
497+ F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
498+ F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
499+ F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
500+ F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
501+ F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
502+ { }
503+};
504+
505+static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
506+ .name = "gcc_qupv3_wrap0_s0_clk_src",
507+ .parent_data = gcc_parent_data_0,
508+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
509+ .flags = CLK_SET_RATE_PARENT,
510+ .ops = &clk_rcg2_ops,
511+};
512+
513+static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
514+ .cmd_rcgr = 0x27014,
515+ .mnd_width = 16,
516+ .hid_width = 5,
517+ .parent_map = gcc_parent_map_0,
518+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
519+ .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
520+};
521+
522+static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
523+ .name = "gcc_qupv3_wrap0_s1_clk_src",
524+ .parent_data = gcc_parent_data_0,
525+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
526+ .flags = CLK_SET_RATE_PARENT,
527+ .ops = &clk_rcg2_ops,
528+};
529+
530+static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
531+ .cmd_rcgr = 0x27148,
532+ .mnd_width = 16,
533+ .hid_width = 5,
534+ .parent_map = gcc_parent_map_0,
535+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
536+ .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
537+};
538+
539+static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
540+ .name = "gcc_qupv3_wrap0_s2_clk_src",
541+ .parent_data = gcc_parent_data_0,
542+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
543+ .flags = CLK_SET_RATE_PARENT,
544+ .ops = &clk_rcg2_ops,
545+};
546+
547+static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
548+ .cmd_rcgr = 0x2727c,
549+ .mnd_width = 16,
550+ .hid_width = 5,
551+ .parent_map = gcc_parent_map_0,
552+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
553+ .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
554+};
555+
556+static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
557+ .name = "gcc_qupv3_wrap0_s3_clk_src",
558+ .parent_data = gcc_parent_data_0,
559+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
560+ .flags = CLK_SET_RATE_PARENT,
561+ .ops = &clk_rcg2_ops,
562+};
563+
564+static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
565+ .cmd_rcgr = 0x273b0,
566+ .mnd_width = 16,
567+ .hid_width = 5,
568+ .parent_map = gcc_parent_map_0,
569+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
570+ .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
571+};
572+
573+static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
574+ .name = "gcc_qupv3_wrap0_s4_clk_src",
575+ .parent_data = gcc_parent_data_0,
576+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
577+ .flags = CLK_SET_RATE_PARENT,
578+ .ops = &clk_rcg2_ops,
579+};
580+
581+static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
582+ .cmd_rcgr = 0x274e4,
583+ .mnd_width = 16,
584+ .hid_width = 5,
585+ .parent_map = gcc_parent_map_0,
586+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
587+ .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
588+};
589+
590+static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s5_clk_src[] = {
591+ F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
592+ F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
593+ F(19200000, P_BI_TCXO, 1, 0, 0),
594+ F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
595+ F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
596+ F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
597+ F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
598+ F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0),
599+ { }
600+};
601+
602+static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
603+ .name = "gcc_qupv3_wrap0_s5_clk_src",
604+ .parent_data = gcc_parent_data_0,
605+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
606+ .flags = CLK_SET_RATE_PARENT,
607+ .ops = &clk_rcg2_ops,
608+};
609+
610+static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
611+ .cmd_rcgr = 0x27618,
612+ .mnd_width = 16,
613+ .hid_width = 5,
614+ .parent_map = gcc_parent_map_0,
615+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src,
616+ .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
617+};
618+
619+static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
620+ .name = "gcc_qupv3_wrap0_s6_clk_src",
621+ .parent_data = gcc_parent_data_0,
622+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
623+ .flags = CLK_SET_RATE_PARENT,
624+ .ops = &clk_rcg2_ops,
625+};
626+
627+static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
628+ .cmd_rcgr = 0x2774c,
629+ .mnd_width = 16,
630+ .hid_width = 5,
631+ .parent_map = gcc_parent_map_0,
632+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
633+ .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
634+};
635+
636+static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
637+ .name = "gcc_qupv3_wrap0_s7_clk_src",
638+ .parent_data = gcc_parent_data_0,
639+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
640+ .flags = CLK_SET_RATE_PARENT,
641+ .ops = &clk_rcg2_ops,
642+};
643+
644+static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
645+ .cmd_rcgr = 0x27880,
646+ .mnd_width = 16,
647+ .hid_width = 5,
648+ .parent_map = gcc_parent_map_0,
649+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
650+ .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
651+};
652+
653+static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = {
654+ F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
655+ F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
656+ F(19200000, P_BI_TCXO, 1, 0, 0),
657+ F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
658+ F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
659+ F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
660+ F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
661+ F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
662+ F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
663+ F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
664+ F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
665+ F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
666+ F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
667+ F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
668+ F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
669+ { }
670+};
671+
672+static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
673+ .name = "gcc_qupv3_wrap1_s0_clk_src",
674+ .parent_data = gcc_parent_data_0,
675+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
676+ .flags = CLK_SET_RATE_PARENT,
677+ .ops = &clk_rcg2_ops,
678+};
679+
680+static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
681+ .cmd_rcgr = 0x28014,
682+ .mnd_width = 16,
683+ .hid_width = 5,
684+ .parent_map = gcc_parent_map_0,
685+ .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
686+ .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
687+};
688+
689+static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
690+ .name = "gcc_qupv3_wrap1_s1_clk_src",
691+ .parent_data = gcc_parent_data_0,
692+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
693+ .flags = CLK_SET_RATE_PARENT,
694+ .ops = &clk_rcg2_ops,
695+};
696+
697+static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
698+ .cmd_rcgr = 0x28148,
699+ .mnd_width = 16,
700+ .hid_width = 5,
701+ .parent_map = gcc_parent_map_0,
702+ .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
703+ .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
704+};
705+
706+static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
707+ .name = "gcc_qupv3_wrap1_s2_clk_src",
708+ .parent_data = gcc_parent_data_0,
709+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
710+ .flags = CLK_SET_RATE_PARENT,
711+ .ops = &clk_rcg2_ops,
712+};
713+
714+static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
715+ .cmd_rcgr = 0x2827c,
716+ .mnd_width = 16,
717+ .hid_width = 5,
718+ .parent_map = gcc_parent_map_0,
719+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
720+ .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
721+};
722+
723+static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
724+ .name = "gcc_qupv3_wrap1_s3_clk_src",
725+ .parent_data = gcc_parent_data_0,
726+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
727+ .flags = CLK_SET_RATE_PARENT,
728+ .ops = &clk_rcg2_ops,
729+};
730+
731+static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
732+ .cmd_rcgr = 0x283b0,
733+ .mnd_width = 16,
734+ .hid_width = 5,
735+ .parent_map = gcc_parent_map_0,
736+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
737+ .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
738+};
739+
740+static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
741+ .name = "gcc_qupv3_wrap1_s4_clk_src",
742+ .parent_data = gcc_parent_data_0,
743+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
744+ .flags = CLK_SET_RATE_PARENT,
745+ .ops = &clk_rcg2_ops,
746+};
747+
748+static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
749+ .cmd_rcgr = 0x284e4,
750+ .mnd_width = 16,
751+ .hid_width = 5,
752+ .parent_map = gcc_parent_map_0,
753+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
754+ .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
755+};
756+
757+static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
758+ .name = "gcc_qupv3_wrap1_s5_clk_src",
759+ .parent_data = gcc_parent_data_0,
760+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
761+ .flags = CLK_SET_RATE_PARENT,
762+ .ops = &clk_rcg2_ops,
763+};
764+
765+static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
766+ .cmd_rcgr = 0x28618,
767+ .mnd_width = 16,
768+ .hid_width = 5,
769+ .parent_map = gcc_parent_map_0,
770+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
771+ .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
772+};
773+
774+static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
775+ .name = "gcc_qupv3_wrap1_s6_clk_src",
776+ .parent_data = gcc_parent_data_0,
777+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
778+ .flags = CLK_SET_RATE_PARENT,
779+ .ops = &clk_rcg2_ops,
780+};
781+
782+static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
783+ .cmd_rcgr = 0x2874c,
784+ .mnd_width = 16,
785+ .hid_width = 5,
786+ .parent_map = gcc_parent_map_0,
787+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
788+ .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
789+};
790+
791+static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
792+ .name = "gcc_qupv3_wrap2_s0_clk_src",
793+ .parent_data = gcc_parent_data_0,
794+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
795+ .flags = CLK_SET_RATE_PARENT,
796+ .ops = &clk_rcg2_ops,
797+};
798+
799+static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
800+ .cmd_rcgr = 0x2e014,
801+ .mnd_width = 16,
802+ .hid_width = 5,
803+ .parent_map = gcc_parent_map_0,
804+ .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
805+ .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
806+};
807+
808+static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
809+ .name = "gcc_qupv3_wrap2_s1_clk_src",
810+ .parent_data = gcc_parent_data_0,
811+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
812+ .flags = CLK_SET_RATE_PARENT,
813+ .ops = &clk_rcg2_ops,
814+};
815+
816+static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
817+ .cmd_rcgr = 0x2e148,
818+ .mnd_width = 16,
819+ .hid_width = 5,
820+ .parent_map = gcc_parent_map_0,
821+ .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
822+ .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
823+};
824+
825+static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
826+ .name = "gcc_qupv3_wrap2_s2_clk_src",
827+ .parent_data = gcc_parent_data_0,
828+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
829+ .flags = CLK_SET_RATE_PARENT,
830+ .ops = &clk_rcg2_ops,
831+};
832+
833+static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
834+ .cmd_rcgr = 0x2e27c,
835+ .mnd_width = 16,
836+ .hid_width = 5,
837+ .parent_map = gcc_parent_map_0,
838+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
839+ .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
840+};
841+
842+static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
843+ .name = "gcc_qupv3_wrap2_s3_clk_src",
844+ .parent_data = gcc_parent_data_0,
845+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
846+ .flags = CLK_SET_RATE_PARENT,
847+ .ops = &clk_rcg2_ops,
848+};
849+
850+static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
851+ .cmd_rcgr = 0x2e3b0,
852+ .mnd_width = 16,
853+ .hid_width = 5,
854+ .parent_map = gcc_parent_map_0,
855+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
856+ .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
857+};
858+
859+static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
860+ .name = "gcc_qupv3_wrap2_s4_clk_src",
861+ .parent_data = gcc_parent_data_0,
862+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
863+ .flags = CLK_SET_RATE_PARENT,
864+ .ops = &clk_rcg2_ops,
865+};
866+
867+static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
868+ .cmd_rcgr = 0x2e4e4,
869+ .mnd_width = 16,
870+ .hid_width = 5,
871+ .parent_map = gcc_parent_map_0,
872+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
873+ .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
874+};
875+
876+static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
877+ .name = "gcc_qupv3_wrap2_s5_clk_src",
878+ .parent_data = gcc_parent_data_0,
879+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
880+ .flags = CLK_SET_RATE_PARENT,
881+ .ops = &clk_rcg2_ops,
882+};
883+
884+static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
885+ .cmd_rcgr = 0x2e618,
886+ .mnd_width = 16,
887+ .hid_width = 5,
888+ .parent_map = gcc_parent_map_0,
889+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
890+ .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
891+};
892+
893+static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
894+ .name = "gcc_qupv3_wrap2_s6_clk_src",
895+ .parent_data = gcc_parent_data_0,
896+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
897+ .flags = CLK_SET_RATE_PARENT,
898+ .ops = &clk_rcg2_ops,
899+};
900+
901+static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
902+ .cmd_rcgr = 0x2e74c,
903+ .mnd_width = 16,
904+ .hid_width = 5,
905+ .parent_map = gcc_parent_map_0,
906+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
907+ .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
908+};
909+
910+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
911+ F(400000, P_BI_TCXO, 12, 1, 4),
912+ F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
913+ F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
914+ F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
915+ F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
916+ { }
917+};
918+
919+static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
920+ .cmd_rcgr = 0x24014,
921+ .mnd_width = 8,
922+ .hid_width = 5,
923+ .parent_map = gcc_parent_map_7,
924+ .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
925+ .clkr.hw.init = &(struct clk_init_data){
926+ .name = "gcc_sdcc2_apps_clk_src",
927+ .parent_data = gcc_parent_data_7,
928+ .num_parents = ARRAY_SIZE(gcc_parent_data_7),
929+ .flags = CLK_SET_RATE_PARENT,
930+ .ops = &clk_rcg2_ops,
931+ },
932+};
933+
934+static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
935+ F(400000, P_BI_TCXO, 12, 1, 4),
936+ F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
937+ F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
938+ { }
939+};
940+
941+static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
942+ .cmd_rcgr = 0x26014,
943+ .mnd_width = 8,
944+ .hid_width = 5,
945+ .parent_map = gcc_parent_map_0,
946+ .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
947+ .clkr.hw.init = &(struct clk_init_data){
948+ .name = "gcc_sdcc4_apps_clk_src",
949+ .parent_data = gcc_parent_data_0,
950+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
951+ .flags = CLK_SET_RATE_PARENT,
952+ .ops = &clk_rcg2_ops,
953+ },
954+};
955+
956+static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
957+ F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
958+ F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
959+ F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
960+ F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
961+ { }
962+};
963+
964+static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
965+ .cmd_rcgr = 0x8702c,
966+ .mnd_width = 8,
967+ .hid_width = 5,
968+ .parent_map = gcc_parent_map_0,
969+ .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
970+ .clkr.hw.init = &(struct clk_init_data){
971+ .name = "gcc_ufs_phy_axi_clk_src",
972+ .parent_data = gcc_parent_data_0,
973+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
974+ .flags = CLK_SET_RATE_PARENT,
975+ .ops = &clk_rcg2_ops,
976+ },
977+};
978+
979+static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
980+ F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
981+ F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
982+ F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
983+ { }
984+};
985+
986+static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
987+ .cmd_rcgr = 0x87074,
988+ .mnd_width = 0,
989+ .hid_width = 5,
990+ .parent_map = gcc_parent_map_0,
991+ .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
992+ .clkr.hw.init = &(struct clk_init_data){
993+ .name = "gcc_ufs_phy_ice_core_clk_src",
994+ .parent_data = gcc_parent_data_0,
995+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
996+ .flags = CLK_SET_RATE_PARENT,
997+ .ops = &clk_rcg2_ops,
998+ },
999+};
1000+
1001+static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
1002+ F(9600000, P_BI_TCXO, 2, 0, 0),
1003+ F(19200000, P_BI_TCXO, 1, 0, 0),
1004+ { }
1005+};
1006+
1007+static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1008+ .cmd_rcgr = 0x870a8,
1009+ .mnd_width = 0,
1010+ .hid_width = 5,
1011+ .parent_map = gcc_parent_map_3,
1012+ .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
1013+ .clkr.hw.init = &(struct clk_init_data){
1014+ .name = "gcc_ufs_phy_phy_aux_clk_src",
1015+ .parent_data = gcc_parent_data_3,
1016+ .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1017+ .flags = CLK_SET_RATE_PARENT,
1018+ .ops = &clk_rcg2_ops,
1019+ },
1020+};
1021+
1022+static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1023+ .cmd_rcgr = 0x8708c,
1024+ .mnd_width = 0,
1025+ .hid_width = 5,
1026+ .parent_map = gcc_parent_map_0,
1027+ .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1028+ .clkr.hw.init = &(struct clk_init_data){
1029+ .name = "gcc_ufs_phy_unipro_core_clk_src",
1030+ .parent_data = gcc_parent_data_0,
1031+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1032+ .flags = CLK_SET_RATE_PARENT,
1033+ .ops = &clk_rcg2_ops,
1034+ },
1035+};
1036+
1037+static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1038+ F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1039+ F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1040+ F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1041+ F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1042+ { }
1043+};
1044+
1045+static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1046+ .cmd_rcgr = 0x49028,
1047+ .mnd_width = 8,
1048+ .hid_width = 5,
1049+ .parent_map = gcc_parent_map_0,
1050+ .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1051+ .clkr.hw.init = &(struct clk_init_data){
1052+ .name = "gcc_usb30_prim_master_clk_src",
1053+ .parent_data = gcc_parent_data_0,
1054+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1055+ .flags = CLK_SET_RATE_PARENT,
1056+ .ops = &clk_rcg2_ops,
1057+ },
1058+};
1059+
1060+static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1061+ .cmd_rcgr = 0x49040,
1062+ .mnd_width = 0,
1063+ .hid_width = 5,
1064+ .parent_map = gcc_parent_map_0,
1065+ .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1066+ .clkr.hw.init = &(struct clk_init_data){
1067+ .name = "gcc_usb30_prim_mock_utmi_clk_src",
1068+ .parent_data = gcc_parent_data_0,
1069+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1070+ .flags = CLK_SET_RATE_PARENT,
1071+ .ops = &clk_rcg2_ops,
1072+ },
1073+};
1074+
1075+static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1076+ .cmd_rcgr = 0x4906c,
1077+ .mnd_width = 0,
1078+ .hid_width = 5,
1079+ .parent_map = gcc_parent_map_2,
1080+ .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1081+ .clkr.hw.init = &(struct clk_init_data){
1082+ .name = "gcc_usb3_prim_phy_aux_clk_src",
1083+ .parent_data = gcc_parent_data_2,
1084+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1085+ .flags = CLK_SET_RATE_PARENT,
1086+ .ops = &clk_rcg2_ops,
1087+ },
1088+};
1089+
1090+static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1091+ .reg = 0x49058,
1092+ .shift = 0,
1093+ .width = 4,
1094+ .clkr.hw.init = &(struct clk_init_data) {
1095+ .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1096+ .parent_data = &(const struct clk_parent_data){
1097+ .hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1098+ },
1099+ .num_parents = 1,
1100+ .flags = CLK_SET_RATE_PARENT,
1101+ .ops = &clk_regmap_div_ro_ops,
1102+ },
1103+};
1104+
1105+static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = {
1106+ .halt_reg = 0x7b08c,
1107+ .halt_check = BRANCH_HALT_SKIP,
1108+ .hwcg_reg = 0x7b08c,
1109+ .hwcg_bit = 1,
1110+ .clkr = {
1111+ .enable_reg = 0x62000,
1112+ .enable_mask = BIT(12),
1113+ .hw.init = &(struct clk_init_data){
1114+ .name = "gcc_aggre_noc_pcie_0_axi_clk",
1115+ .ops = &clk_branch2_ops,
1116+ },
1117+ },
1118+};
1119+
1120+static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = {
1121+ .halt_reg = 0x9d098,
1122+ .halt_check = BRANCH_HALT_SKIP,
1123+ .hwcg_reg = 0x9d098,
1124+ .hwcg_bit = 1,
1125+ .clkr = {
1126+ .enable_reg = 0x62000,
1127+ .enable_mask = BIT(11),
1128+ .hw.init = &(struct clk_init_data){
1129+ .name = "gcc_aggre_noc_pcie_1_axi_clk",
1130+ .ops = &clk_branch2_ops,
1131+ },
1132+ },
1133+};
1134+
1135+static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1136+ .halt_reg = 0x870d4,
1137+ .halt_check = BRANCH_HALT_VOTED,
1138+ .hwcg_reg = 0x870d4,
1139+ .hwcg_bit = 1,
1140+ .clkr = {
1141+ .enable_reg = 0x870d4,
1142+ .enable_mask = BIT(0),
1143+ .hw.init = &(struct clk_init_data){
1144+ .name = "gcc_aggre_ufs_phy_axi_clk",
1145+ .parent_data = &(const struct clk_parent_data){
1146+ .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
1147+ },
1148+ .num_parents = 1,
1149+ .flags = CLK_SET_RATE_PARENT,
1150+ .ops = &clk_branch2_ops,
1151+ },
1152+ },
1153+};
1154+
1155+static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1156+ .halt_reg = 0x870d4,
1157+ .halt_check = BRANCH_HALT_VOTED,
1158+ .hwcg_reg = 0x870d4,
1159+ .hwcg_bit = 1,
1160+ .clkr = {
1161+ .enable_reg = 0x870d4,
1162+ .enable_mask = BIT(1),
1163+ .hw.init = &(struct clk_init_data){
1164+ .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1165+ .parent_data = &(const struct clk_parent_data){
1166+ .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
1167+ },
1168+ .num_parents = 1,
1169+ .flags = CLK_SET_RATE_PARENT,
1170+ .ops = &clk_branch2_ops,
1171+ },
1172+ },
1173+};
1174+
1175+static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1176+ .halt_reg = 0x49088,
1177+ .halt_check = BRANCH_HALT_VOTED,
1178+ .hwcg_reg = 0x49088,
1179+ .hwcg_bit = 1,
1180+ .clkr = {
1181+ .enable_reg = 0x49088,
1182+ .enable_mask = BIT(0),
1183+ .hw.init = &(struct clk_init_data){
1184+ .name = "gcc_aggre_usb3_prim_axi_clk",
1185+ .parent_data = &(const struct clk_parent_data){
1186+ .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
1187+ },
1188+ .num_parents = 1,
1189+ .flags = CLK_SET_RATE_PARENT,
1190+ .ops = &clk_branch2_ops,
1191+ },
1192+ },
1193+};
1194+
1195+static struct clk_branch gcc_boot_rom_ahb_clk = {
1196+ .halt_reg = 0x48004,
1197+ .halt_check = BRANCH_HALT_VOTED,
1198+ .hwcg_reg = 0x48004,
1199+ .hwcg_bit = 1,
1200+ .clkr = {
1201+ .enable_reg = 0x62000,
1202+ .enable_mask = BIT(10),
1203+ .hw.init = &(struct clk_init_data){
1204+ .name = "gcc_boot_rom_ahb_clk",
1205+ .ops = &clk_branch2_ops,
1206+ },
1207+ },
1208+};
1209+
1210+static struct clk_branch gcc_camera_hf_axi_clk = {
1211+ .halt_reg = 0x36010,
1212+ .halt_check = BRANCH_HALT_SKIP,
1213+ .hwcg_reg = 0x36010,
1214+ .hwcg_bit = 1,
1215+ .clkr = {
1216+ .enable_reg = 0x36010,
1217+ .enable_mask = BIT(0),
1218+ .hw.init = &(struct clk_init_data){
1219+ .name = "gcc_camera_hf_axi_clk",
1220+ .ops = &clk_branch2_ops,
1221+ },
1222+ },
1223+};
1224+
1225+static struct clk_branch gcc_camera_sf_axi_clk = {
1226+ .halt_reg = 0x36018,
1227+ .halt_check = BRANCH_HALT_SKIP,
1228+ .hwcg_reg = 0x36018,
1229+ .hwcg_bit = 1,
1230+ .clkr = {
1231+ .enable_reg = 0x36018,
1232+ .enable_mask = BIT(0),
1233+ .hw.init = &(struct clk_init_data){
1234+ .name = "gcc_camera_sf_axi_clk",
1235+ .ops = &clk_branch2_ops,
1236+ },
1237+ },
1238+};
1239+
1240+static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {
1241+ .halt_reg = 0x20030,
1242+ .halt_check = BRANCH_HALT_VOTED,
1243+ .hwcg_reg = 0x20030,
1244+ .hwcg_bit = 1,
1245+ .clkr = {
1246+ .enable_reg = 0x62000,
1247+ .enable_mask = BIT(20),
1248+ .hw.init = &(struct clk_init_data){
1249+ .name = "gcc_cfg_noc_pcie_anoc_ahb_clk",
1250+ .ops = &clk_branch2_ops,
1251+ },
1252+ },
1253+};
1254+
1255+static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1256+ .halt_reg = 0x49084,
1257+ .halt_check = BRANCH_HALT_VOTED,
1258+ .hwcg_reg = 0x49084,
1259+ .hwcg_bit = 1,
1260+ .clkr = {
1261+ .enable_reg = 0x49084,
1262+ .enable_mask = BIT(0),
1263+ .hw.init = &(struct clk_init_data){
1264+ .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1265+ .parent_data = &(const struct clk_parent_data){
1266+ .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
1267+ },
1268+ .num_parents = 1,
1269+ .flags = CLK_SET_RATE_PARENT,
1270+ .ops = &clk_branch2_ops,
1271+ },
1272+ },
1273+};
1274+
1275+static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1276+ .halt_reg = 0x81154,
1277+ .halt_check = BRANCH_HALT_SKIP,
1278+ .hwcg_reg = 0x81154,
1279+ .hwcg_bit = 1,
1280+ .clkr = {
1281+ .enable_reg = 0x81154,
1282+ .enable_mask = BIT(0),
1283+ .hw.init = &(struct clk_init_data){
1284+ .name = "gcc_ddrss_gpu_axi_clk",
1285+ .ops = &clk_branch2_aon_ops,
1286+ },
1287+ },
1288+};
1289+
1290+static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = {
1291+ .halt_reg = 0x9d094,
1292+ .halt_check = BRANCH_HALT_SKIP,
1293+ .hwcg_reg = 0x9d094,
1294+ .hwcg_bit = 1,
1295+ .clkr = {
1296+ .enable_reg = 0x62000,
1297+ .enable_mask = BIT(19),
1298+ .hw.init = &(struct clk_init_data){
1299+ .name = "gcc_ddrss_pcie_sf_tbu_clk",
1300+ .ops = &clk_branch2_ops,
1301+ },
1302+ },
1303+};
1304+
1305+static struct clk_branch gcc_disp_hf_axi_clk = {
1306+ .halt_reg = 0x3700c,
1307+ .halt_check = BRANCH_HALT_SKIP,
1308+ .hwcg_reg = 0x3700c,
1309+ .hwcg_bit = 1,
1310+ .clkr = {
1311+ .enable_reg = 0x3700c,
1312+ .enable_mask = BIT(0),
1313+ .hw.init = &(struct clk_init_data){
1314+ .name = "gcc_disp_hf_axi_clk",
1315+ .ops = &clk_branch2_ops,
1316+ },
1317+ },
1318+};
1319+
1320+static struct clk_branch gcc_disp_sf_axi_clk = {
1321+ .halt_reg = 0x37014,
1322+ .halt_check = BRANCH_HALT_SKIP,
1323+ .hwcg_reg = 0x37014,
1324+ .hwcg_bit = 1,
1325+ .clkr = {
1326+ .enable_reg = 0x37014,
1327+ .enable_mask = BIT(0),
1328+ .hw.init = &(struct clk_init_data){
1329+ .name = "gcc_disp_sf_axi_clk",
1330+ .ops = &clk_branch2_ops,
1331+ },
1332+ },
1333+};
1334+
1335+static struct clk_branch gcc_eusb3_0_clkref_en = {
1336+ .halt_reg = 0x9c00c,
1337+ .halt_check = BRANCH_HALT,
1338+ .clkr = {
1339+ .enable_reg = 0x9c00c,
1340+ .enable_mask = BIT(0),
1341+ .hw.init = &(struct clk_init_data){
1342+ .name = "gcc_eusb3_0_clkref_en",
1343+ .ops = &clk_branch2_ops,
1344+ },
1345+ },
1346+};
1347+
1348+static struct clk_branch gcc_gp1_clk = {
1349+ .halt_reg = 0x74000,
1350+ .halt_check = BRANCH_HALT,
1351+ .clkr = {
1352+ .enable_reg = 0x74000,
1353+ .enable_mask = BIT(0),
1354+ .hw.init = &(struct clk_init_data){
1355+ .name = "gcc_gp1_clk",
1356+ .parent_data = &(const struct clk_parent_data){
1357+ .hw = &gcc_gp1_clk_src.clkr.hw,
1358+ },
1359+ .num_parents = 1,
1360+ .flags = CLK_SET_RATE_PARENT,
1361+ .ops = &clk_branch2_ops,
1362+ },
1363+ },
1364+};
1365+
1366+static struct clk_branch gcc_gp2_clk = {
1367+ .halt_reg = 0x75000,
1368+ .halt_check = BRANCH_HALT,
1369+ .clkr = {
1370+ .enable_reg = 0x75000,
1371+ .enable_mask = BIT(0),
1372+ .hw.init = &(struct clk_init_data){
1373+ .name = "gcc_gp2_clk",
1374+ .parent_data = &(const struct clk_parent_data){
1375+ .hw = &gcc_gp2_clk_src.clkr.hw,
1376+ },
1377+ .num_parents = 1,
1378+ .flags = CLK_SET_RATE_PARENT,
1379+ .ops = &clk_branch2_ops,
1380+ },
1381+ },
1382+};
1383+
1384+static struct clk_branch gcc_gp3_clk = {
1385+ .halt_reg = 0x76000,
1386+ .halt_check = BRANCH_HALT,
1387+ .clkr = {
1388+ .enable_reg = 0x76000,
1389+ .enable_mask = BIT(0),
1390+ .hw.init = &(struct clk_init_data){
1391+ .name = "gcc_gp3_clk",
1392+ .parent_data = &(const struct clk_parent_data){
1393+ .hw = &gcc_gp3_clk_src.clkr.hw,
1394+ },
1395+ .num_parents = 1,
1396+ .flags = CLK_SET_RATE_PARENT,
1397+ .ops = &clk_branch2_ops,
1398+ },
1399+ },
1400+};
1401+
1402+static struct clk_branch gcc_gpu_gpll0_clk_src = {
1403+ .halt_check = BRANCH_HALT_DELAY,
1404+ .clkr = {
1405+ .enable_reg = 0x62000,
1406+ .enable_mask = BIT(15),
1407+ .hw.init = &(struct clk_init_data){
1408+ .name = "gcc_gpu_gpll0_clk_src",
1409+ .parent_data = &(const struct clk_parent_data){
1410+ .hw = &gcc_gpll0.clkr.hw,
1411+ },
1412+ .num_parents = 1,
1413+ .flags = CLK_SET_RATE_PARENT,
1414+ .ops = &clk_branch2_ops,
1415+ },
1416+ },
1417+};
1418+
1419+static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1420+ .halt_check = BRANCH_HALT_DELAY,
1421+ .clkr = {
1422+ .enable_reg = 0x62000,
1423+ .enable_mask = BIT(16),
1424+ .hw.init = &(struct clk_init_data){
1425+ .name = "gcc_gpu_gpll0_div_clk_src",
1426+ .parent_data = &(const struct clk_parent_data){
1427+ .hw = &gcc_gpll0_out_even.clkr.hw,
1428+ },
1429+ .num_parents = 1,
1430+ .flags = CLK_SET_RATE_PARENT,
1431+ .ops = &clk_branch2_ops,
1432+ },
1433+ },
1434+};
1435+
1436+static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1437+ .halt_reg = 0x81010,
1438+ .halt_check = BRANCH_HALT_VOTED,
1439+ .hwcg_reg = 0x81010,
1440+ .hwcg_bit = 1,
1441+ .clkr = {
1442+ .enable_reg = 0x81010,
1443+ .enable_mask = BIT(0),
1444+ .hw.init = &(struct clk_init_data){
1445+ .name = "gcc_gpu_memnoc_gfx_clk",
1446+ .ops = &clk_branch2_ops,
1447+ },
1448+ },
1449+};
1450+
1451+static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1452+ .halt_reg = 0x81018,
1453+ .halt_check = BRANCH_HALT_DELAY,
1454+ .clkr = {
1455+ .enable_reg = 0x81018,
1456+ .enable_mask = BIT(0),
1457+ .hw.init = &(struct clk_init_data){
1458+ .name = "gcc_gpu_snoc_dvm_gfx_clk",
1459+ .ops = &clk_branch2_ops,
1460+ },
1461+ },
1462+};
1463+
1464+static struct clk_branch gcc_pcie_0_aux_clk = {
1465+ .halt_reg = 0x7b034,
1466+ .halt_check = BRANCH_HALT_VOTED,
1467+ .clkr = {
1468+ .enable_reg = 0x62008,
1469+ .enable_mask = BIT(3),
1470+ .hw.init = &(struct clk_init_data){
1471+ .name = "gcc_pcie_0_aux_clk",
1472+ .parent_data = &(const struct clk_parent_data){
1473+ .hw = &gcc_pcie_0_aux_clk_src.clkr.hw,
1474+ },
1475+ .num_parents = 1,
1476+ .flags = CLK_SET_RATE_PARENT,
1477+ .ops = &clk_branch2_ops,
1478+ },
1479+ },
1480+};
1481+
1482+static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1483+ .halt_reg = 0x7b030,
1484+ .halt_check = BRANCH_HALT_VOTED,
1485+ .hwcg_reg = 0x7b030,
1486+ .hwcg_bit = 1,
1487+ .clkr = {
1488+ .enable_reg = 0x62008,
1489+ .enable_mask = BIT(2),
1490+ .hw.init = &(struct clk_init_data){
1491+ .name = "gcc_pcie_0_cfg_ahb_clk",
1492+ .ops = &clk_branch2_ops,
1493+ },
1494+ },
1495+};
1496+
1497+static struct clk_branch gcc_pcie_0_clkref_en = {
1498+ .halt_reg = 0x9c004,
1499+ .halt_check = BRANCH_HALT,
1500+ .clkr = {
1501+ .enable_reg = 0x9c004,
1502+ .enable_mask = BIT(0),
1503+ .hw.init = &(struct clk_init_data){
1504+ .name = "gcc_pcie_0_clkref_en",
1505+ .ops = &clk_branch2_ops,
1506+ },
1507+ },
1508+};
1509+
1510+static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1511+ .halt_reg = 0x7b028,
1512+ .halt_check = BRANCH_HALT_SKIP,
1513+ .clkr = {
1514+ .enable_reg = 0x62008,
1515+ .enable_mask = BIT(1),
1516+ .hw.init = &(struct clk_init_data){
1517+ .name = "gcc_pcie_0_mstr_axi_clk",
1518+ .ops = &clk_branch2_ops,
1519+ },
1520+ },
1521+};
1522+
1523+static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
1524+ .halt_reg = 0x7b044,
1525+ .halt_check = BRANCH_HALT_VOTED,
1526+ .clkr = {
1527+ .enable_reg = 0x62000,
1528+ .enable_mask = BIT(22),
1529+ .hw.init = &(struct clk_init_data){
1530+ .name = "gcc_pcie_0_phy_rchng_clk",
1531+ .parent_data = &(const struct clk_parent_data){
1532+ .hw = &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
1533+ },
1534+ .num_parents = 1,
1535+ .flags = CLK_SET_RATE_PARENT,
1536+ .ops = &clk_branch2_ops,
1537+ },
1538+ },
1539+};
1540+
1541+static struct clk_branch gcc_pcie_0_pipe_clk = {
1542+ .halt_reg = 0x7b03c,
1543+ .halt_check = BRANCH_HALT_SKIP,
1544+ .clkr = {
1545+ .enable_reg = 0x62008,
1546+ .enable_mask = BIT(4),
1547+ .hw.init = &(struct clk_init_data){
1548+ .name = "gcc_pcie_0_pipe_clk",
1549+ .parent_data = &(const struct clk_parent_data){
1550+ .hw = &gcc_pcie_0_pipe_clk_src.clkr.hw,
1551+ },
1552+ .num_parents = 1,
1553+ .flags = CLK_SET_RATE_PARENT,
1554+ .ops = &clk_branch2_ops,
1555+ },
1556+ },
1557+};
1558+
1559+static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1560+ .halt_reg = 0x7b020,
1561+ .halt_check = BRANCH_HALT_VOTED,
1562+ .hwcg_reg = 0x7b020,
1563+ .hwcg_bit = 1,
1564+ .clkr = {
1565+ .enable_reg = 0x62008,
1566+ .enable_mask = BIT(0),
1567+ .hw.init = &(struct clk_init_data){
1568+ .name = "gcc_pcie_0_slv_axi_clk",
1569+ .ops = &clk_branch2_ops,
1570+ },
1571+ },
1572+};
1573+
1574+static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1575+ .halt_reg = 0x7b01c,
1576+ .halt_check = BRANCH_HALT_VOTED,
1577+ .clkr = {
1578+ .enable_reg = 0x62008,
1579+ .enable_mask = BIT(5),
1580+ .hw.init = &(struct clk_init_data){
1581+ .name = "gcc_pcie_0_slv_q2a_axi_clk",
1582+ .ops = &clk_branch2_ops,
1583+ },
1584+ },
1585+};
1586+
1587+static struct clk_branch gcc_pcie_1_aux_clk = {
1588+ .halt_reg = 0x9d030,
1589+ .halt_check = BRANCH_HALT_VOTED,
1590+ .clkr = {
1591+ .enable_reg = 0x62000,
1592+ .enable_mask = BIT(29),
1593+ .hw.init = &(struct clk_init_data){
1594+ .name = "gcc_pcie_1_aux_clk",
1595+ .parent_data = &(const struct clk_parent_data){
1596+ .hw = &gcc_pcie_1_aux_clk_src.clkr.hw,
1597+ },
1598+ .num_parents = 1,
1599+ .flags = CLK_SET_RATE_PARENT,
1600+ .ops = &clk_branch2_ops,
1601+ },
1602+ },
1603+};
1604+
1605+static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1606+ .halt_reg = 0x9d02c,
1607+ .halt_check = BRANCH_HALT_VOTED,
1608+ .hwcg_reg = 0x9d02c,
1609+ .hwcg_bit = 1,
1610+ .clkr = {
1611+ .enable_reg = 0x62000,
1612+ .enable_mask = BIT(28),
1613+ .hw.init = &(struct clk_init_data){
1614+ .name = "gcc_pcie_1_cfg_ahb_clk",
1615+ .ops = &clk_branch2_ops,
1616+ },
1617+ },
1618+};
1619+
1620+static struct clk_branch gcc_pcie_1_clkref_en = {
1621+ .halt_reg = 0x9c008,
1622+ .halt_check = BRANCH_HALT,
1623+ .clkr = {
1624+ .enable_reg = 0x9c008,
1625+ .enable_mask = BIT(0),
1626+ .hw.init = &(struct clk_init_data){
1627+ .name = "gcc_pcie_1_clkref_en",
1628+ .ops = &clk_branch2_ops,
1629+ },
1630+ },
1631+};
1632+
1633+static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1634+ .halt_reg = 0x9d024,
1635+ .halt_check = BRANCH_HALT_SKIP,
1636+ .clkr = {
1637+ .enable_reg = 0x62000,
1638+ .enable_mask = BIT(27),
1639+ .hw.init = &(struct clk_init_data){
1640+ .name = "gcc_pcie_1_mstr_axi_clk",
1641+ .ops = &clk_branch2_ops,
1642+ },
1643+ },
1644+};
1645+
1646+static struct clk_branch gcc_pcie_1_phy_aux_clk = {
1647+ .halt_reg = 0x9d038,
1648+ .halt_check = BRANCH_HALT_VOTED,
1649+ .clkr = {
1650+ .enable_reg = 0x62000,
1651+ .enable_mask = BIT(24),
1652+ .hw.init = &(struct clk_init_data){
1653+ .name = "gcc_pcie_1_phy_aux_clk",
1654+ .parent_data = &(const struct clk_parent_data){
1655+ .hw = &gcc_pcie_1_phy_aux_clk_src.clkr.hw,
1656+ },
1657+ .num_parents = 1,
1658+ .flags = CLK_SET_RATE_PARENT,
1659+ .ops = &clk_branch2_ops,
1660+ },
1661+ },
1662+};
1663+
1664+static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
1665+ .halt_reg = 0x9d048,
1666+ .halt_check = BRANCH_HALT_VOTED,
1667+ .clkr = {
1668+ .enable_reg = 0x62000,
1669+ .enable_mask = BIT(23),
1670+ .hw.init = &(struct clk_init_data){
1671+ .name = "gcc_pcie_1_phy_rchng_clk",
1672+ .parent_data = &(const struct clk_parent_data){
1673+ .hw = &gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
1674+ },
1675+ .num_parents = 1,
1676+ .flags = CLK_SET_RATE_PARENT,
1677+ .ops = &clk_branch2_ops,
1678+ },
1679+ },
1680+};
1681+
1682+static struct clk_branch gcc_pcie_1_pipe_clk = {
1683+ .halt_reg = 0x9d040,
1684+ .halt_check = BRANCH_HALT_SKIP,
1685+ .clkr = {
1686+ .enable_reg = 0x62000,
1687+ .enable_mask = BIT(30),
1688+ .hw.init = &(struct clk_init_data){
1689+ .name = "gcc_pcie_1_pipe_clk",
1690+ .parent_data = &(const struct clk_parent_data){
1691+ .hw = &gcc_pcie_1_pipe_clk_src.clkr.hw,
1692+ },
1693+ .num_parents = 1,
1694+ .flags = CLK_SET_RATE_PARENT,
1695+ .ops = &clk_branch2_ops,
1696+ },
1697+ },
1698+};
1699+
1700+static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1701+ .halt_reg = 0x9d01c,
1702+ .halt_check = BRANCH_HALT_VOTED,
1703+ .hwcg_reg = 0x9d01c,
1704+ .hwcg_bit = 1,
1705+ .clkr = {
1706+ .enable_reg = 0x62000,
1707+ .enable_mask = BIT(26),
1708+ .hw.init = &(struct clk_init_data){
1709+ .name = "gcc_pcie_1_slv_axi_clk",
1710+ .ops = &clk_branch2_ops,
1711+ },
1712+ },
1713+};
1714+
1715+static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1716+ .halt_reg = 0x9d018,
1717+ .halt_check = BRANCH_HALT_VOTED,
1718+ .clkr = {
1719+ .enable_reg = 0x62000,
1720+ .enable_mask = BIT(25),
1721+ .hw.init = &(struct clk_init_data){
1722+ .name = "gcc_pcie_1_slv_q2a_axi_clk",
1723+ .ops = &clk_branch2_ops,
1724+ },
1725+ },
1726+};
1727+
1728+static struct clk_branch gcc_pdm2_clk = {
1729+ .halt_reg = 0x4300c,
1730+ .halt_check = BRANCH_HALT,
1731+ .clkr = {
1732+ .enable_reg = 0x4300c,
1733+ .enable_mask = BIT(0),
1734+ .hw.init = &(struct clk_init_data){
1735+ .name = "gcc_pdm2_clk",
1736+ .parent_data = &(const struct clk_parent_data){
1737+ .hw = &gcc_pdm2_clk_src.clkr.hw,
1738+ },
1739+ .num_parents = 1,
1740+ .flags = CLK_SET_RATE_PARENT,
1741+ .ops = &clk_branch2_ops,
1742+ },
1743+ },
1744+};
1745+
1746+static struct clk_branch gcc_pdm_ahb_clk = {
1747+ .halt_reg = 0x43004,
1748+ .halt_check = BRANCH_HALT_VOTED,
1749+ .hwcg_reg = 0x43004,
1750+ .hwcg_bit = 1,
1751+ .clkr = {
1752+ .enable_reg = 0x43004,
1753+ .enable_mask = BIT(0),
1754+ .hw.init = &(struct clk_init_data){
1755+ .name = "gcc_pdm_ahb_clk",
1756+ .ops = &clk_branch2_ops,
1757+ },
1758+ },
1759+};
1760+
1761+static struct clk_branch gcc_pdm_xo4_clk = {
1762+ .halt_reg = 0x43008,
1763+ .halt_check = BRANCH_HALT,
1764+ .clkr = {
1765+ .enable_reg = 0x43008,
1766+ .enable_mask = BIT(0),
1767+ .hw.init = &(struct clk_init_data){
1768+ .name = "gcc_pdm_xo4_clk",
1769+ .ops = &clk_branch2_ops,
1770+ },
1771+ },
1772+};
1773+
1774+static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
1775+ .halt_reg = 0x36008,
1776+ .halt_check = BRANCH_HALT_VOTED,
1777+ .hwcg_reg = 0x36008,
1778+ .hwcg_bit = 1,
1779+ .clkr = {
1780+ .enable_reg = 0x36008,
1781+ .enable_mask = BIT(0),
1782+ .hw.init = &(struct clk_init_data){
1783+ .name = "gcc_qmip_camera_nrt_ahb_clk",
1784+ .ops = &clk_branch2_ops,
1785+ },
1786+ },
1787+};
1788+
1789+static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
1790+ .halt_reg = 0x3600c,
1791+ .halt_check = BRANCH_HALT_VOTED,
1792+ .hwcg_reg = 0x3600c,
1793+ .hwcg_bit = 1,
1794+ .clkr = {
1795+ .enable_reg = 0x3600c,
1796+ .enable_mask = BIT(0),
1797+ .hw.init = &(struct clk_init_data){
1798+ .name = "gcc_qmip_camera_rt_ahb_clk",
1799+ .ops = &clk_branch2_ops,
1800+ },
1801+ },
1802+};
1803+
1804+static struct clk_branch gcc_qmip_disp_ahb_clk = {
1805+ .halt_reg = 0x37008,
1806+ .halt_check = BRANCH_HALT_VOTED,
1807+ .hwcg_reg = 0x37008,
1808+ .hwcg_bit = 1,
1809+ .clkr = {
1810+ .enable_reg = 0x37008,
1811+ .enable_mask = BIT(0),
1812+ .hw.init = &(struct clk_init_data){
1813+ .name = "gcc_qmip_disp_ahb_clk",
1814+ .ops = &clk_branch2_ops,
1815+ },
1816+ },
1817+};
1818+
1819+static struct clk_branch gcc_qmip_gpu_ahb_clk = {
1820+ .halt_reg = 0x81008,
1821+ .halt_check = BRANCH_HALT_VOTED,
1822+ .hwcg_reg = 0x81008,
1823+ .hwcg_bit = 1,
1824+ .clkr = {
1825+ .enable_reg = 0x81008,
1826+ .enable_mask = BIT(0),
1827+ .hw.init = &(struct clk_init_data){
1828+ .name = "gcc_qmip_gpu_ahb_clk",
1829+ .ops = &clk_branch2_ops,
1830+ },
1831+ },
1832+};
1833+
1834+static struct clk_branch gcc_qmip_pcie_ahb_clk = {
1835+ .halt_reg = 0x7b018,
1836+ .halt_check = BRANCH_HALT_VOTED,
1837+ .hwcg_reg = 0x7b018,
1838+ .hwcg_bit = 1,
1839+ .clkr = {
1840+ .enable_reg = 0x7b018,
1841+ .enable_mask = BIT(0),
1842+ .hw.init = &(struct clk_init_data){
1843+ .name = "gcc_qmip_pcie_ahb_clk",
1844+ .ops = &clk_branch2_ops,
1845+ },
1846+ },
1847+};
1848+
1849+static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = {
1850+ .halt_reg = 0x42014,
1851+ .halt_check = BRANCH_HALT_VOTED,
1852+ .hwcg_reg = 0x42014,
1853+ .hwcg_bit = 1,
1854+ .clkr = {
1855+ .enable_reg = 0x42014,
1856+ .enable_mask = BIT(0),
1857+ .hw.init = &(struct clk_init_data){
1858+ .name = "gcc_qmip_video_cv_cpu_ahb_clk",
1859+ .ops = &clk_branch2_ops,
1860+ },
1861+ },
1862+};
1863+
1864+static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
1865+ .halt_reg = 0x42008,
1866+ .halt_check = BRANCH_HALT_VOTED,
1867+ .hwcg_reg = 0x42008,
1868+ .hwcg_bit = 1,
1869+ .clkr = {
1870+ .enable_reg = 0x42008,
1871+ .enable_mask = BIT(0),
1872+ .hw.init = &(struct clk_init_data){
1873+ .name = "gcc_qmip_video_cvp_ahb_clk",
1874+ .ops = &clk_branch2_ops,
1875+ },
1876+ },
1877+};
1878+
1879+static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {
1880+ .halt_reg = 0x42010,
1881+ .halt_check = BRANCH_HALT_VOTED,
1882+ .hwcg_reg = 0x42010,
1883+ .hwcg_bit = 1,
1884+ .clkr = {
1885+ .enable_reg = 0x42010,
1886+ .enable_mask = BIT(0),
1887+ .hw.init = &(struct clk_init_data){
1888+ .name = "gcc_qmip_video_v_cpu_ahb_clk",
1889+ .ops = &clk_branch2_ops,
1890+ },
1891+ },
1892+};
1893+
1894+static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
1895+ .halt_reg = 0x4200c,
1896+ .halt_check = BRANCH_HALT_VOTED,
1897+ .hwcg_reg = 0x4200c,
1898+ .hwcg_bit = 1,
1899+ .clkr = {
1900+ .enable_reg = 0x4200c,
1901+ .enable_mask = BIT(0),
1902+ .hw.init = &(struct clk_init_data){
1903+ .name = "gcc_qmip_video_vcodec_ahb_clk",
1904+ .ops = &clk_branch2_ops,
1905+ },
1906+ },
1907+};
1908+
1909+static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
1910+ .halt_reg = 0x3300c,
1911+ .halt_check = BRANCH_HALT_VOTED,
1912+ .clkr = {
1913+ .enable_reg = 0x62008,
1914+ .enable_mask = BIT(9),
1915+ .hw.init = &(struct clk_init_data){
1916+ .name = "gcc_qupv3_wrap0_core_2x_clk",
1917+ .ops = &clk_branch2_ops,
1918+ },
1919+ },
1920+};
1921+
1922+static struct clk_branch gcc_qupv3_wrap0_core_clk = {
1923+ .halt_reg = 0x33000,
1924+ .halt_check = BRANCH_HALT_VOTED,
1925+ .clkr = {
1926+ .enable_reg = 0x62008,
1927+ .enable_mask = BIT(8),
1928+ .hw.init = &(struct clk_init_data){
1929+ .name = "gcc_qupv3_wrap0_core_clk",
1930+ .ops = &clk_branch2_ops,
1931+ },
1932+ },
1933+};
1934+
1935+static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
1936+ .halt_reg = 0x2700c,
1937+ .halt_check = BRANCH_HALT_VOTED,
1938+ .clkr = {
1939+ .enable_reg = 0x62008,
1940+ .enable_mask = BIT(10),
1941+ .hw.init = &(struct clk_init_data){
1942+ .name = "gcc_qupv3_wrap0_s0_clk",
1943+ .parent_data = &(const struct clk_parent_data){
1944+ .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
1945+ },
1946+ .num_parents = 1,
1947+ .flags = CLK_SET_RATE_PARENT,
1948+ .ops = &clk_branch2_ops,
1949+ },
1950+ },
1951+};
1952+
1953+static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
1954+ .halt_reg = 0x27140,
1955+ .halt_check = BRANCH_HALT_VOTED,
1956+ .clkr = {
1957+ .enable_reg = 0x62008,
1958+ .enable_mask = BIT(11),
1959+ .hw.init = &(struct clk_init_data){
1960+ .name = "gcc_qupv3_wrap0_s1_clk",
1961+ .parent_data = &(const struct clk_parent_data){
1962+ .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
1963+ },
1964+ .num_parents = 1,
1965+ .flags = CLK_SET_RATE_PARENT,
1966+ .ops = &clk_branch2_ops,
1967+ },
1968+ },
1969+};
1970+
1971+static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
1972+ .halt_reg = 0x27274,
1973+ .halt_check = BRANCH_HALT_VOTED,
1974+ .clkr = {
1975+ .enable_reg = 0x62008,
1976+ .enable_mask = BIT(12),
1977+ .hw.init = &(struct clk_init_data){
1978+ .name = "gcc_qupv3_wrap0_s2_clk",
1979+ .parent_data = &(const struct clk_parent_data){
1980+ .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
1981+ },
1982+ .num_parents = 1,
1983+ .flags = CLK_SET_RATE_PARENT,
1984+ .ops = &clk_branch2_ops,
1985+ },
1986+ },
1987+};
1988+
1989+static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
1990+ .halt_reg = 0x273a8,
1991+ .halt_check = BRANCH_HALT_VOTED,
1992+ .clkr = {
1993+ .enable_reg = 0x62008,
1994+ .enable_mask = BIT(13),
1995+ .hw.init = &(struct clk_init_data){
1996+ .name = "gcc_qupv3_wrap0_s3_clk",
1997+ .parent_data = &(const struct clk_parent_data){
1998+ .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
1999+ },
2000+ .num_parents = 1,
2001+ .flags = CLK_SET_RATE_PARENT,
2002+ .ops = &clk_branch2_ops,
2003+ },
2004+ },
2005+};
2006+
2007+static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2008+ .halt_reg = 0x274dc,
2009+ .halt_check = BRANCH_HALT_VOTED,
2010+ .clkr = {
2011+ .enable_reg = 0x62008,
2012+ .enable_mask = BIT(14),
2013+ .hw.init = &(struct clk_init_data){
2014+ .name = "gcc_qupv3_wrap0_s4_clk",
2015+ .parent_data = &(const struct clk_parent_data){
2016+ .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2017+ },
2018+ .num_parents = 1,
2019+ .flags = CLK_SET_RATE_PARENT,
2020+ .ops = &clk_branch2_ops,
2021+ },
2022+ },
2023+};
2024+
2025+static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2026+ .halt_reg = 0x27610,
2027+ .halt_check = BRANCH_HALT_VOTED,
2028+ .clkr = {
2029+ .enable_reg = 0x62008,
2030+ .enable_mask = BIT(15),
2031+ .hw.init = &(struct clk_init_data){
2032+ .name = "gcc_qupv3_wrap0_s5_clk",
2033+ .parent_data = &(const struct clk_parent_data){
2034+ .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2035+ },
2036+ .num_parents = 1,
2037+ .flags = CLK_SET_RATE_PARENT,
2038+ .ops = &clk_branch2_ops,
2039+ },
2040+ },
2041+};
2042+
2043+static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2044+ .halt_reg = 0x27744,
2045+ .halt_check = BRANCH_HALT_VOTED,
2046+ .clkr = {
2047+ .enable_reg = 0x62008,
2048+ .enable_mask = BIT(16),
2049+ .hw.init = &(struct clk_init_data){
2050+ .name = "gcc_qupv3_wrap0_s6_clk",
2051+ .parent_data = &(const struct clk_parent_data){
2052+ .hw = &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
2053+ },
2054+ .num_parents = 1,
2055+ .flags = CLK_SET_RATE_PARENT,
2056+ .ops = &clk_branch2_ops,
2057+ },
2058+ },
2059+};
2060+
2061+static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2062+ .halt_reg = 0x27878,
2063+ .halt_check = BRANCH_HALT_VOTED,
2064+ .clkr = {
2065+ .enable_reg = 0x62008,
2066+ .enable_mask = BIT(17),
2067+ .hw.init = &(struct clk_init_data){
2068+ .name = "gcc_qupv3_wrap0_s7_clk",
2069+ .parent_data = &(const struct clk_parent_data){
2070+ .hw = &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
2071+ },
2072+ .num_parents = 1,
2073+ .flags = CLK_SET_RATE_PARENT,
2074+ .ops = &clk_branch2_ops,
2075+ },
2076+ },
2077+};
2078+
2079+static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
2080+ .halt_reg = 0x3314c,
2081+ .halt_check = BRANCH_HALT_VOTED,
2082+ .clkr = {
2083+ .enable_reg = 0x62008,
2084+ .enable_mask = BIT(18),
2085+ .hw.init = &(struct clk_init_data){
2086+ .name = "gcc_qupv3_wrap1_core_2x_clk",
2087+ .ops = &clk_branch2_ops,
2088+ },
2089+ },
2090+};
2091+
2092+static struct clk_branch gcc_qupv3_wrap1_core_clk = {
2093+ .halt_reg = 0x33140,
2094+ .halt_check = BRANCH_HALT_VOTED,
2095+ .clkr = {
2096+ .enable_reg = 0x62008,
2097+ .enable_mask = BIT(19),
2098+ .hw.init = &(struct clk_init_data){
2099+ .name = "gcc_qupv3_wrap1_core_clk",
2100+ .ops = &clk_branch2_ops,
2101+ },
2102+ },
2103+};
2104+
2105+static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2106+ .halt_reg = 0x2800c,
2107+ .halt_check = BRANCH_HALT_VOTED,
2108+ .clkr = {
2109+ .enable_reg = 0x62008,
2110+ .enable_mask = BIT(22),
2111+ .hw.init = &(struct clk_init_data){
2112+ .name = "gcc_qupv3_wrap1_s0_clk",
2113+ .parent_data = &(const struct clk_parent_data){
2114+ .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2115+ },
2116+ .num_parents = 1,
2117+ .flags = CLK_SET_RATE_PARENT,
2118+ .ops = &clk_branch2_ops,
2119+ },
2120+ },
2121+};
2122+
2123+static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2124+ .halt_reg = 0x28140,
2125+ .halt_check = BRANCH_HALT_VOTED,
2126+ .clkr = {
2127+ .enable_reg = 0x62008,
2128+ .enable_mask = BIT(23),
2129+ .hw.init = &(struct clk_init_data){
2130+ .name = "gcc_qupv3_wrap1_s1_clk",
2131+ .parent_data = &(const struct clk_parent_data){
2132+ .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2133+ },
2134+ .num_parents = 1,
2135+ .flags = CLK_SET_RATE_PARENT,
2136+ .ops = &clk_branch2_ops,
2137+ },
2138+ },
2139+};
2140+
2141+static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2142+ .halt_reg = 0x28274,
2143+ .halt_check = BRANCH_HALT_VOTED,
2144+ .clkr = {
2145+ .enable_reg = 0x62008,
2146+ .enable_mask = BIT(24),
2147+ .hw.init = &(struct clk_init_data){
2148+ .name = "gcc_qupv3_wrap1_s2_clk",
2149+ .parent_data = &(const struct clk_parent_data){
2150+ .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2151+ },
2152+ .num_parents = 1,
2153+ .flags = CLK_SET_RATE_PARENT,
2154+ .ops = &clk_branch2_ops,
2155+ },
2156+ },
2157+};
2158+
2159+static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2160+ .halt_reg = 0x283a8,
2161+ .halt_check = BRANCH_HALT_VOTED,
2162+ .clkr = {
2163+ .enable_reg = 0x62008,
2164+ .enable_mask = BIT(25),
2165+ .hw.init = &(struct clk_init_data){
2166+ .name = "gcc_qupv3_wrap1_s3_clk",
2167+ .parent_data = &(const struct clk_parent_data){
2168+ .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2169+ },
2170+ .num_parents = 1,
2171+ .flags = CLK_SET_RATE_PARENT,
2172+ .ops = &clk_branch2_ops,
2173+ },
2174+ },
2175+};
2176+
2177+static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2178+ .halt_reg = 0x284dc,
2179+ .halt_check = BRANCH_HALT_VOTED,
2180+ .clkr = {
2181+ .enable_reg = 0x62008,
2182+ .enable_mask = BIT(26),
2183+ .hw.init = &(struct clk_init_data){
2184+ .name = "gcc_qupv3_wrap1_s4_clk",
2185+ .parent_data = &(const struct clk_parent_data){
2186+ .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2187+ },
2188+ .num_parents = 1,
2189+ .flags = CLK_SET_RATE_PARENT,
2190+ .ops = &clk_branch2_ops,
2191+ },
2192+ },
2193+};
2194+
2195+static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2196+ .halt_reg = 0x28610,
2197+ .halt_check = BRANCH_HALT_VOTED,
2198+ .clkr = {
2199+ .enable_reg = 0x62008,
2200+ .enable_mask = BIT(27),
2201+ .hw.init = &(struct clk_init_data){
2202+ .name = "gcc_qupv3_wrap1_s5_clk",
2203+ .parent_data = &(const struct clk_parent_data){
2204+ .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2205+ },
2206+ .num_parents = 1,
2207+ .flags = CLK_SET_RATE_PARENT,
2208+ .ops = &clk_branch2_ops,
2209+ },
2210+ },
2211+};
2212+
2213+static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
2214+ .halt_reg = 0x28744,
2215+ .halt_check = BRANCH_HALT_VOTED,
2216+ .clkr = {
2217+ .enable_reg = 0x62008,
2218+ .enable_mask = BIT(28),
2219+ .hw.init = &(struct clk_init_data){
2220+ .name = "gcc_qupv3_wrap1_s6_clk",
2221+ .parent_data = &(const struct clk_parent_data){
2222+ .hw = &gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
2223+ },
2224+ .num_parents = 1,
2225+ .flags = CLK_SET_RATE_PARENT,
2226+ .ops = &clk_branch2_ops,
2227+ },
2228+ },
2229+};
2230+
2231+static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
2232+ .halt_reg = 0x3328c,
2233+ .halt_check = BRANCH_HALT_VOTED,
2234+ .clkr = {
2235+ .enable_reg = 0x62010,
2236+ .enable_mask = BIT(3),
2237+ .hw.init = &(struct clk_init_data){
2238+ .name = "gcc_qupv3_wrap2_core_2x_clk",
2239+ .ops = &clk_branch2_ops,
2240+ },
2241+ },
2242+};
2243+
2244+static struct clk_branch gcc_qupv3_wrap2_core_clk = {
2245+ .halt_reg = 0x33280,
2246+ .halt_check = BRANCH_HALT_VOTED,
2247+ .clkr = {
2248+ .enable_reg = 0x62010,
2249+ .enable_mask = BIT(0),
2250+ .hw.init = &(struct clk_init_data){
2251+ .name = "gcc_qupv3_wrap2_core_clk",
2252+ .ops = &clk_branch2_ops,
2253+ },
2254+ },
2255+};
2256+
2257+static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2258+ .halt_reg = 0x2e00c,
2259+ .halt_check = BRANCH_HALT_VOTED,
2260+ .clkr = {
2261+ .enable_reg = 0x62010,
2262+ .enable_mask = BIT(4),
2263+ .hw.init = &(struct clk_init_data){
2264+ .name = "gcc_qupv3_wrap2_s0_clk",
2265+ .parent_data = &(const struct clk_parent_data){
2266+ .hw = &gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
2267+ },
2268+ .num_parents = 1,
2269+ .flags = CLK_SET_RATE_PARENT,
2270+ .ops = &clk_branch2_ops,
2271+ },
2272+ },
2273+};
2274+
2275+static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2276+ .halt_reg = 0x2e140,
2277+ .halt_check = BRANCH_HALT_VOTED,
2278+ .clkr = {
2279+ .enable_reg = 0x62010,
2280+ .enable_mask = BIT(5),
2281+ .hw.init = &(struct clk_init_data){
2282+ .name = "gcc_qupv3_wrap2_s1_clk",
2283+ .parent_data = &(const struct clk_parent_data){
2284+ .hw = &gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
2285+ },
2286+ .num_parents = 1,
2287+ .flags = CLK_SET_RATE_PARENT,
2288+ .ops = &clk_branch2_ops,
2289+ },
2290+ },
2291+};
2292+
2293+static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2294+ .halt_reg = 0x2e274,
2295+ .halt_check = BRANCH_HALT_VOTED,
2296+ .clkr = {
2297+ .enable_reg = 0x62010,
2298+ .enable_mask = BIT(6),
2299+ .hw.init = &(struct clk_init_data){
2300+ .name = "gcc_qupv3_wrap2_s2_clk",
2301+ .parent_data = &(const struct clk_parent_data){
2302+ .hw = &gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
2303+ },
2304+ .num_parents = 1,
2305+ .flags = CLK_SET_RATE_PARENT,
2306+ .ops = &clk_branch2_ops,
2307+ },
2308+ },
2309+};
2310+
2311+static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2312+ .halt_reg = 0x2e3a8,
2313+ .halt_check = BRANCH_HALT_VOTED,
2314+ .clkr = {
2315+ .enable_reg = 0x62010,
2316+ .enable_mask = BIT(7),
2317+ .hw.init = &(struct clk_init_data){
2318+ .name = "gcc_qupv3_wrap2_s3_clk",
2319+ .parent_data = &(const struct clk_parent_data){
2320+ .hw = &gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
2321+ },
2322+ .num_parents = 1,
2323+ .flags = CLK_SET_RATE_PARENT,
2324+ .ops = &clk_branch2_ops,
2325+ },
2326+ },
2327+};
2328+
2329+static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2330+ .halt_reg = 0x2e4dc,
2331+ .halt_check = BRANCH_HALT_VOTED,
2332+ .clkr = {
2333+ .enable_reg = 0x62010,
2334+ .enable_mask = BIT(8),
2335+ .hw.init = &(struct clk_init_data){
2336+ .name = "gcc_qupv3_wrap2_s4_clk",
2337+ .parent_data = &(const struct clk_parent_data){
2338+ .hw = &gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
2339+ },
2340+ .num_parents = 1,
2341+ .flags = CLK_SET_RATE_PARENT,
2342+ .ops = &clk_branch2_ops,
2343+ },
2344+ },
2345+};
2346+
2347+static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2348+ .halt_reg = 0x2e610,
2349+ .halt_check = BRANCH_HALT_VOTED,
2350+ .clkr = {
2351+ .enable_reg = 0x62010,
2352+ .enable_mask = BIT(9),
2353+ .hw.init = &(struct clk_init_data){
2354+ .name = "gcc_qupv3_wrap2_s5_clk",
2355+ .parent_data = &(const struct clk_parent_data){
2356+ .hw = &gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
2357+ },
2358+ .num_parents = 1,
2359+ .flags = CLK_SET_RATE_PARENT,
2360+ .ops = &clk_branch2_ops,
2361+ },
2362+ },
2363+};
2364+
2365+static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
2366+ .halt_reg = 0x2e744,
2367+ .halt_check = BRANCH_HALT_VOTED,
2368+ .clkr = {
2369+ .enable_reg = 0x62010,
2370+ .enable_mask = BIT(10),
2371+ .hw.init = &(struct clk_init_data){
2372+ .name = "gcc_qupv3_wrap2_s6_clk",
2373+ .parent_data = &(const struct clk_parent_data){
2374+ .hw = &gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
2375+ },
2376+ .num_parents = 1,
2377+ .flags = CLK_SET_RATE_PARENT,
2378+ .ops = &clk_branch2_ops,
2379+ },
2380+ },
2381+};
2382+
2383+static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2384+ .halt_reg = 0x27004,
2385+ .halt_check = BRANCH_HALT_VOTED,
2386+ .hwcg_reg = 0x27004,
2387+ .hwcg_bit = 1,
2388+ .clkr = {
2389+ .enable_reg = 0x62008,
2390+ .enable_mask = BIT(6),
2391+ .hw.init = &(struct clk_init_data){
2392+ .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2393+ .ops = &clk_branch2_ops,
2394+ },
2395+ },
2396+};
2397+
2398+static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2399+ .halt_reg = 0x27008,
2400+ .halt_check = BRANCH_HALT_VOTED,
2401+ .hwcg_reg = 0x27008,
2402+ .hwcg_bit = 1,
2403+ .clkr = {
2404+ .enable_reg = 0x62008,
2405+ .enable_mask = BIT(7),
2406+ .hw.init = &(struct clk_init_data){
2407+ .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2408+ .ops = &clk_branch2_ops,
2409+ },
2410+ },
2411+};
2412+
2413+static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2414+ .halt_reg = 0x28004,
2415+ .halt_check = BRANCH_HALT_VOTED,
2416+ .hwcg_reg = 0x28004,
2417+ .hwcg_bit = 1,
2418+ .clkr = {
2419+ .enable_reg = 0x62008,
2420+ .enable_mask = BIT(20),
2421+ .hw.init = &(struct clk_init_data){
2422+ .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2423+ .ops = &clk_branch2_ops,
2424+ },
2425+ },
2426+};
2427+
2428+static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2429+ .halt_reg = 0x28008,
2430+ .halt_check = BRANCH_HALT_VOTED,
2431+ .hwcg_reg = 0x28008,
2432+ .hwcg_bit = 1,
2433+ .clkr = {
2434+ .enable_reg = 0x62008,
2435+ .enable_mask = BIT(21),
2436+ .hw.init = &(struct clk_init_data){
2437+ .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2438+ .ops = &clk_branch2_ops,
2439+ },
2440+ },
2441+};
2442+
2443+static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
2444+ .halt_reg = 0x2e004,
2445+ .halt_check = BRANCH_HALT_VOTED,
2446+ .hwcg_reg = 0x2e004,
2447+ .hwcg_bit = 1,
2448+ .clkr = {
2449+ .enable_reg = 0x62010,
2450+ .enable_mask = BIT(2),
2451+ .hw.init = &(struct clk_init_data){
2452+ .name = "gcc_qupv3_wrap_2_m_ahb_clk",
2453+ .ops = &clk_branch2_ops,
2454+ },
2455+ },
2456+};
2457+
2458+static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
2459+ .halt_reg = 0x2e008,
2460+ .halt_check = BRANCH_HALT_VOTED,
2461+ .hwcg_reg = 0x2e008,
2462+ .hwcg_bit = 1,
2463+ .clkr = {
2464+ .enable_reg = 0x62010,
2465+ .enable_mask = BIT(1),
2466+ .hw.init = &(struct clk_init_data){
2467+ .name = "gcc_qupv3_wrap_2_s_ahb_clk",
2468+ .ops = &clk_branch2_ops,
2469+ },
2470+ },
2471+};
2472+
2473+static struct clk_branch gcc_sdcc2_ahb_clk = {
2474+ .halt_reg = 0x2400c,
2475+ .halt_check = BRANCH_HALT,
2476+ .clkr = {
2477+ .enable_reg = 0x2400c,
2478+ .enable_mask = BIT(0),
2479+ .hw.init = &(struct clk_init_data){
2480+ .name = "gcc_sdcc2_ahb_clk",
2481+ .ops = &clk_branch2_ops,
2482+ },
2483+ },
2484+};
2485+
2486+static struct clk_branch gcc_sdcc2_apps_clk = {
2487+ .halt_reg = 0x24004,
2488+ .halt_check = BRANCH_HALT,
2489+ .clkr = {
2490+ .enable_reg = 0x24004,
2491+ .enable_mask = BIT(0),
2492+ .hw.init = &(struct clk_init_data){
2493+ .name = "gcc_sdcc2_apps_clk",
2494+ .parent_data = &(const struct clk_parent_data){
2495+ .hw = &gcc_sdcc2_apps_clk_src.clkr.hw,
2496+ },
2497+ .num_parents = 1,
2498+ .flags = CLK_SET_RATE_PARENT,
2499+ .ops = &clk_branch2_ops,
2500+ },
2501+ },
2502+};
2503+
2504+static struct clk_branch gcc_sdcc2_at_clk = {
2505+ .halt_reg = 0x24010,
2506+ .halt_check = BRANCH_HALT_VOTED,
2507+ .hwcg_reg = 0x24010,
2508+ .hwcg_bit = 1,
2509+ .clkr = {
2510+ .enable_reg = 0x24010,
2511+ .enable_mask = BIT(0),
2512+ .hw.init = &(struct clk_init_data){
2513+ .name = "gcc_sdcc2_at_clk",
2514+ .ops = &clk_branch2_ops,
2515+ },
2516+ },
2517+};
2518+
2519+static struct clk_branch gcc_sdcc4_ahb_clk = {
2520+ .halt_reg = 0x2600c,
2521+ .halt_check = BRANCH_HALT,
2522+ .clkr = {
2523+ .enable_reg = 0x2600c,
2524+ .enable_mask = BIT(0),
2525+ .hw.init = &(struct clk_init_data){
2526+ .name = "gcc_sdcc4_ahb_clk",
2527+ .ops = &clk_branch2_ops,
2528+ },
2529+ },
2530+};
2531+
2532+static struct clk_branch gcc_sdcc4_apps_clk = {
2533+ .halt_reg = 0x26004,
2534+ .halt_check = BRANCH_HALT,
2535+ .clkr = {
2536+ .enable_reg = 0x26004,
2537+ .enable_mask = BIT(0),
2538+ .hw.init = &(struct clk_init_data){
2539+ .name = "gcc_sdcc4_apps_clk",
2540+ .parent_data = &(const struct clk_parent_data){
2541+ .hw = &gcc_sdcc4_apps_clk_src.clkr.hw,
2542+ },
2543+ .num_parents = 1,
2544+ .flags = CLK_SET_RATE_PARENT,
2545+ .ops = &clk_branch2_ops,
2546+ },
2547+ },
2548+};
2549+
2550+static struct clk_branch gcc_sdcc4_at_clk = {
2551+ .halt_reg = 0x26010,
2552+ .halt_check = BRANCH_HALT_VOTED,
2553+ .hwcg_reg = 0x26010,
2554+ .hwcg_bit = 1,
2555+ .clkr = {
2556+ .enable_reg = 0x26010,
2557+ .enable_mask = BIT(0),
2558+ .hw.init = &(struct clk_init_data){
2559+ .name = "gcc_sdcc4_at_clk",
2560+ .ops = &clk_branch2_ops,
2561+ },
2562+ },
2563+};
2564+
2565+static struct clk_branch gcc_ufs_0_clkref_en = {
2566+ .halt_reg = 0x9c000,
2567+ .halt_check = BRANCH_HALT,
2568+ .clkr = {
2569+ .enable_reg = 0x9c000,
2570+ .enable_mask = BIT(0),
2571+ .hw.init = &(struct clk_init_data){
2572+ .name = "gcc_ufs_0_clkref_en",
2573+ .ops = &clk_branch2_ops,
2574+ },
2575+ },
2576+};
2577+
2578+static struct clk_branch gcc_ufs_phy_ahb_clk = {
2579+ .halt_reg = 0x87020,
2580+ .halt_check = BRANCH_HALT_VOTED,
2581+ .hwcg_reg = 0x87020,
2582+ .hwcg_bit = 1,
2583+ .clkr = {
2584+ .enable_reg = 0x87020,
2585+ .enable_mask = BIT(0),
2586+ .hw.init = &(struct clk_init_data){
2587+ .name = "gcc_ufs_phy_ahb_clk",
2588+ .ops = &clk_branch2_ops,
2589+ },
2590+ },
2591+};
2592+
2593+static struct clk_branch gcc_ufs_phy_axi_clk = {
2594+ .halt_reg = 0x87018,
2595+ .halt_check = BRANCH_HALT_VOTED,
2596+ .hwcg_reg = 0x87018,
2597+ .hwcg_bit = 1,
2598+ .clkr = {
2599+ .enable_reg = 0x87018,
2600+ .enable_mask = BIT(0),
2601+ .hw.init = &(struct clk_init_data){
2602+ .name = "gcc_ufs_phy_axi_clk",
2603+ .parent_data = &(const struct clk_parent_data){
2604+ .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
2605+ },
2606+ .num_parents = 1,
2607+ .flags = CLK_SET_RATE_PARENT,
2608+ .ops = &clk_branch2_ops,
2609+ },
2610+ },
2611+};
2612+
2613+static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
2614+ .halt_reg = 0x87018,
2615+ .halt_check = BRANCH_HALT_VOTED,
2616+ .hwcg_reg = 0x87018,
2617+ .hwcg_bit = 1,
2618+ .clkr = {
2619+ .enable_reg = 0x87018,
2620+ .enable_mask = BIT(1),
2621+ .hw.init = &(struct clk_init_data){
2622+ .name = "gcc_ufs_phy_axi_hw_ctl_clk",
2623+ .parent_data = &(const struct clk_parent_data){
2624+ .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
2625+ },
2626+ .num_parents = 1,
2627+ .flags = CLK_SET_RATE_PARENT,
2628+ .ops = &clk_branch2_ops,
2629+ },
2630+ },
2631+};
2632+
2633+static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2634+ .halt_reg = 0x8706c,
2635+ .halt_check = BRANCH_HALT_VOTED,
2636+ .hwcg_reg = 0x8706c,
2637+ .hwcg_bit = 1,
2638+ .clkr = {
2639+ .enable_reg = 0x8706c,
2640+ .enable_mask = BIT(0),
2641+ .hw.init = &(struct clk_init_data){
2642+ .name = "gcc_ufs_phy_ice_core_clk",
2643+ .parent_data = &(const struct clk_parent_data){
2644+ .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2645+ },
2646+ .num_parents = 1,
2647+ .flags = CLK_SET_RATE_PARENT,
2648+ .ops = &clk_branch2_ops,
2649+ },
2650+ },
2651+};
2652+
2653+static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
2654+ .halt_reg = 0x8706c,
2655+ .halt_check = BRANCH_HALT_VOTED,
2656+ .hwcg_reg = 0x8706c,
2657+ .hwcg_bit = 1,
2658+ .clkr = {
2659+ .enable_reg = 0x8706c,
2660+ .enable_mask = BIT(1),
2661+ .hw.init = &(struct clk_init_data){
2662+ .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
2663+ .parent_data = &(const struct clk_parent_data){
2664+ .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2665+ },
2666+ .num_parents = 1,
2667+ .flags = CLK_SET_RATE_PARENT,
2668+ .ops = &clk_branch2_ops,
2669+ },
2670+ },
2671+};
2672+
2673+static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2674+ .halt_reg = 0x870a4,
2675+ .halt_check = BRANCH_HALT_VOTED,
2676+ .hwcg_reg = 0x870a4,
2677+ .hwcg_bit = 1,
2678+ .clkr = {
2679+ .enable_reg = 0x870a4,
2680+ .enable_mask = BIT(0),
2681+ .hw.init = &(struct clk_init_data){
2682+ .name = "gcc_ufs_phy_phy_aux_clk",
2683+ .parent_data = &(const struct clk_parent_data){
2684+ .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2685+ },
2686+ .num_parents = 1,
2687+ .flags = CLK_SET_RATE_PARENT,
2688+ .ops = &clk_branch2_ops,
2689+ },
2690+ },
2691+};
2692+
2693+static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
2694+ .halt_reg = 0x870a4,
2695+ .halt_check = BRANCH_HALT_VOTED,
2696+ .hwcg_reg = 0x870a4,
2697+ .hwcg_bit = 1,
2698+ .clkr = {
2699+ .enable_reg = 0x870a4,
2700+ .enable_mask = BIT(1),
2701+ .hw.init = &(struct clk_init_data){
2702+ .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
2703+ .parent_data = &(const struct clk_parent_data){
2704+ .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2705+ },
2706+ .num_parents = 1,
2707+ .flags = CLK_SET_RATE_PARENT,
2708+ .ops = &clk_branch2_ops,
2709+ },
2710+ },
2711+};
2712+
2713+static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2714+ .halt_reg = 0x87028,
2715+ .halt_check = BRANCH_HALT_DELAY,
2716+ .clkr = {
2717+ .enable_reg = 0x87028,
2718+ .enable_mask = BIT(0),
2719+ .hw.init = &(struct clk_init_data){
2720+ .name = "gcc_ufs_phy_rx_symbol_0_clk",
2721+ .parent_data = &(const struct clk_parent_data){
2722+ .hw = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
2723+ },
2724+ .num_parents = 1,
2725+ .flags = CLK_SET_RATE_PARENT,
2726+ .ops = &clk_branch2_ops,
2727+ },
2728+ },
2729+};
2730+
2731+static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2732+ .halt_reg = 0x870c0,
2733+ .halt_check = BRANCH_HALT_DELAY,
2734+ .clkr = {
2735+ .enable_reg = 0x870c0,
2736+ .enable_mask = BIT(0),
2737+ .hw.init = &(struct clk_init_data){
2738+ .name = "gcc_ufs_phy_rx_symbol_1_clk",
2739+ .parent_data = &(const struct clk_parent_data){
2740+ .hw = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
2741+ },
2742+ .num_parents = 1,
2743+ .flags = CLK_SET_RATE_PARENT,
2744+ .ops = &clk_branch2_ops,
2745+ },
2746+ },
2747+};
2748+
2749+static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2750+ .halt_reg = 0x87024,
2751+ .halt_check = BRANCH_HALT_DELAY,
2752+ .clkr = {
2753+ .enable_reg = 0x87024,
2754+ .enable_mask = BIT(0),
2755+ .hw.init = &(struct clk_init_data){
2756+ .name = "gcc_ufs_phy_tx_symbol_0_clk",
2757+ .parent_data = &(const struct clk_parent_data){
2758+ .hw = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
2759+ },
2760+ .num_parents = 1,
2761+ .flags = CLK_SET_RATE_PARENT,
2762+ .ops = &clk_branch2_ops,
2763+ },
2764+ },
2765+};
2766+
2767+static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2768+ .halt_reg = 0x87064,
2769+ .halt_check = BRANCH_HALT_VOTED,
2770+ .hwcg_reg = 0x87064,
2771+ .hwcg_bit = 1,
2772+ .clkr = {
2773+ .enable_reg = 0x87064,
2774+ .enable_mask = BIT(0),
2775+ .hw.init = &(struct clk_init_data){
2776+ .name = "gcc_ufs_phy_unipro_core_clk",
2777+ .parent_data = &(const struct clk_parent_data){
2778+ .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2779+ },
2780+ .num_parents = 1,
2781+ .flags = CLK_SET_RATE_PARENT,
2782+ .ops = &clk_branch2_ops,
2783+ },
2784+ },
2785+};
2786+
2787+static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
2788+ .halt_reg = 0x87064,
2789+ .halt_check = BRANCH_HALT_VOTED,
2790+ .hwcg_reg = 0x87064,
2791+ .hwcg_bit = 1,
2792+ .clkr = {
2793+ .enable_reg = 0x87064,
2794+ .enable_mask = BIT(1),
2795+ .hw.init = &(struct clk_init_data){
2796+ .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
2797+ .parent_data = &(const struct clk_parent_data){
2798+ .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2799+ },
2800+ .num_parents = 1,
2801+ .flags = CLK_SET_RATE_PARENT,
2802+ .ops = &clk_branch2_ops,
2803+ },
2804+ },
2805+};
2806+
2807+static struct clk_branch gcc_usb30_prim_master_clk = {
2808+ .halt_reg = 0x49018,
2809+ .halt_check = BRANCH_HALT,
2810+ .clkr = {
2811+ .enable_reg = 0x49018,
2812+ .enable_mask = BIT(0),
2813+ .hw.init = &(struct clk_init_data){
2814+ .name = "gcc_usb30_prim_master_clk",
2815+ .parent_data = &(const struct clk_parent_data){
2816+ .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
2817+ },
2818+ .num_parents = 1,
2819+ .flags = CLK_SET_RATE_PARENT,
2820+ .ops = &clk_branch2_ops,
2821+ },
2822+ },
2823+};
2824+
2825+static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2826+ .halt_reg = 0x49024,
2827+ .halt_check = BRANCH_HALT,
2828+ .clkr = {
2829+ .enable_reg = 0x49024,
2830+ .enable_mask = BIT(0),
2831+ .hw.init = &(struct clk_init_data){
2832+ .name = "gcc_usb30_prim_mock_utmi_clk",
2833+ .parent_data = &(const struct clk_parent_data){
2834+ .hw = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
2835+ },
2836+ .num_parents = 1,
2837+ .flags = CLK_SET_RATE_PARENT,
2838+ .ops = &clk_branch2_ops,
2839+ },
2840+ },
2841+};
2842+
2843+static struct clk_branch gcc_usb30_prim_sleep_clk = {
2844+ .halt_reg = 0x49020,
2845+ .halt_check = BRANCH_HALT,
2846+ .clkr = {
2847+ .enable_reg = 0x49020,
2848+ .enable_mask = BIT(0),
2849+ .hw.init = &(struct clk_init_data){
2850+ .name = "gcc_usb30_prim_sleep_clk",
2851+ .ops = &clk_branch2_ops,
2852+ },
2853+ },
2854+};
2855+
2856+static struct clk_branch gcc_usb3_0_clkref_en = {
2857+ .halt_reg = 0x9c010,
2858+ .halt_check = BRANCH_HALT,
2859+ .clkr = {
2860+ .enable_reg = 0x9c010,
2861+ .enable_mask = BIT(0),
2862+ .hw.init = &(struct clk_init_data){
2863+ .name = "gcc_usb3_0_clkref_en",
2864+ .ops = &clk_branch2_ops,
2865+ },
2866+ },
2867+};
2868+
2869+static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2870+ .halt_reg = 0x4905c,
2871+ .halt_check = BRANCH_HALT,
2872+ .clkr = {
2873+ .enable_reg = 0x4905c,
2874+ .enable_mask = BIT(0),
2875+ .hw.init = &(struct clk_init_data){
2876+ .name = "gcc_usb3_prim_phy_aux_clk",
2877+ .parent_data = &(const struct clk_parent_data){
2878+ .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2879+ },
2880+ .num_parents = 1,
2881+ .flags = CLK_SET_RATE_PARENT,
2882+ .ops = &clk_branch2_ops,
2883+ },
2884+ },
2885+};
2886+
2887+static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2888+ .halt_reg = 0x49060,
2889+ .halt_check = BRANCH_HALT,
2890+ .clkr = {
2891+ .enable_reg = 0x49060,
2892+ .enable_mask = BIT(0),
2893+ .hw.init = &(struct clk_init_data){
2894+ .name = "gcc_usb3_prim_phy_com_aux_clk",
2895+ .parent_data = &(const struct clk_parent_data){
2896+ .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2897+ },
2898+ .num_parents = 1,
2899+ .flags = CLK_SET_RATE_PARENT,
2900+ .ops = &clk_branch2_ops,
2901+ },
2902+ },
2903+};
2904+
2905+static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2906+ .halt_reg = 0x49064,
2907+ .halt_check = BRANCH_HALT_DELAY,
2908+ .hwcg_reg = 0x49064,
2909+ .hwcg_bit = 1,
2910+ .clkr = {
2911+ .enable_reg = 0x49064,
2912+ .enable_mask = BIT(0),
2913+ .hw.init = &(struct clk_init_data){
2914+ .name = "gcc_usb3_prim_phy_pipe_clk",
2915+ .parent_data = &(const struct clk_parent_data){
2916+ .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
2917+ },
2918+ .num_parents = 1,
2919+ .flags = CLK_SET_RATE_PARENT,
2920+ .ops = &clk_branch2_ops,
2921+ },
2922+ },
2923+};
2924+
2925+static struct clk_branch gcc_video_axi0_clk = {
2926+ .halt_reg = 0x42018,
2927+ .halt_check = BRANCH_HALT_SKIP,
2928+ .hwcg_reg = 0x42018,
2929+ .hwcg_bit = 1,
2930+ .clkr = {
2931+ .enable_reg = 0x42018,
2932+ .enable_mask = BIT(0),
2933+ .hw.init = &(struct clk_init_data){
2934+ .name = "gcc_video_axi0_clk",
2935+ .ops = &clk_branch2_ops,
2936+ },
2937+ },
2938+};
2939+
2940+static struct clk_branch gcc_video_axi1_clk = {
2941+ .halt_reg = 0x42020,
2942+ .halt_check = BRANCH_HALT_SKIP,
2943+ .hwcg_reg = 0x42020,
2944+ .hwcg_bit = 1,
2945+ .clkr = {
2946+ .enable_reg = 0x42020,
2947+ .enable_mask = BIT(0),
2948+ .hw.init = &(struct clk_init_data){
2949+ .name = "gcc_video_axi1_clk",
2950+ .ops = &clk_branch2_ops,
2951+ },
2952+ },
2953+};
2954+
2955+static struct gdsc pcie_0_gdsc = {
2956+ .gdscr = 0x7b004,
2957+ .pd = {
2958+ .name = "pcie_0_gdsc",
2959+ },
2960+ .pwrsts = PWRSTS_OFF_ON,
2961+};
2962+
2963+static struct gdsc pcie_1_gdsc = {
2964+ .gdscr = 0x9d004,
2965+ .pd = {
2966+ .name = "pcie_1_gdsc",
2967+ },
2968+ .pwrsts = PWRSTS_OFF_ON,
2969+};
2970+
2971+static struct gdsc ufs_phy_gdsc = {
2972+ .gdscr = 0x87004,
2973+ .pd = {
2974+ .name = "ufs_phy_gdsc",
2975+ },
2976+ .pwrsts = PWRSTS_OFF_ON,
2977+};
2978+
2979+static struct gdsc usb30_prim_gdsc = {
2980+ .gdscr = 0x49004,
2981+ .pd = {
2982+ .name = "usb30_prim_gdsc",
2983+ },
2984+ .pwrsts = PWRSTS_OFF_ON,
2985+};
2986+
2987+static struct clk_regmap *gcc_sm8450_clocks[] = {
2988+ [GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr,
2989+ [GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr,
2990+ [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
2991+ [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
2992+ [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
2993+ [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2994+ [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
2995+ [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
2996+ [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,
2997+ [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
2998+ [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
2999+ [GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr,
3000+ [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3001+ [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
3002+ [GCC_EUSB3_0_CLKREF_EN] = &gcc_eusb3_0_clkref_en.clkr,
3003+ [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3004+ [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3005+ [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3006+ [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3007+ [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3008+ [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3009+ [GCC_GPLL0] = &gcc_gpll0.clkr,
3010+ [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
3011+ [GCC_GPLL4] = &gcc_gpll4.clkr,
3012+ [GCC_GPLL9] = &gcc_gpll9.clkr,
3013+ [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3014+ [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3015+ [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3016+ [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3017+ [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3018+ [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3019+ [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3020+ [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,
3021+ [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3022+ [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
3023+ [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
3024+ [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3025+ [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
3026+ [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3027+ [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3028+ [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3029+ [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3030+ [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3031+ [GCC_PCIE_1_CLKREF_EN] = &gcc_pcie_1_clkref_en.clkr,
3032+ [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3033+ [GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr,
3034+ [GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr,
3035+ [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
3036+ [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
3037+ [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3038+ [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
3039+ [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3040+ [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3041+ [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3042+ [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3043+ [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3044+ [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3045+ [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3046+ [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3047+ [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3048+ [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,
3049+ [GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr,
3050+ [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr,
3051+ [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
3052+ [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr,
3053+ [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3054+ [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3055+ [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3056+ [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3057+ [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3058+ [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3059+ [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3060+ [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3061+ [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3062+ [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3063+ [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3064+ [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3065+ [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3066+ [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3067+ [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3068+ [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3069+ [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3070+ [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3071+ [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3072+ [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
3073+ [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
3074+ [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3075+ [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3076+ [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3077+ [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3078+ [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3079+ [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3080+ [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3081+ [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3082+ [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3083+ [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3084+ [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3085+ [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3086+ [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3087+ [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3088+ [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
3089+ [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
3090+ [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
3091+ [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
3092+ [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
3093+ [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
3094+ [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
3095+ [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
3096+ [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
3097+ [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
3098+ [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
3099+ [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
3100+ [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
3101+ [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
3102+ [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
3103+ [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
3104+ [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3105+ [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3106+ [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3107+ [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3108+ [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
3109+ [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
3110+ [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3111+ [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3112+ [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3113+ [GCC_SDCC2_AT_CLK] = &gcc_sdcc2_at_clk.clkr,
3114+ [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3115+ [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3116+ [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3117+ [GCC_SDCC4_AT_CLK] = &gcc_sdcc4_at_clk.clkr,
3118+ [GCC_UFS_0_CLKREF_EN] = &gcc_ufs_0_clkref_en.clkr,
3119+ [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3120+ [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3121+ [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3122+ [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
3123+ [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3124+ [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3125+ [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
3126+ [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3127+ [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3128+ [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
3129+ [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3130+ [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
3131+ [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3132+ [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
3133+ [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3134+ [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
3135+ [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3136+ [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
3137+ [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
3138+ [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3139+ [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3140+ [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3141+ [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3142+ [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3143+ [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3144+ [GCC_USB3_0_CLKREF_EN] = &gcc_usb3_0_clkref_en.clkr,
3145+ [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3146+ [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3147+ [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3148+ [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3149+ [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
3150+ [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3151+ [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
3152+};
3153+
3154+static const struct qcom_reset_map gcc_sm8450_resets[] = {
3155+ [GCC_CAMERA_BCR] = { 0x36000 },
3156+ [GCC_DISPLAY_BCR] = { 0x37000 },
3157+ [GCC_GPU_BCR] = { 0x81000 },
3158+ [GCC_PCIE_0_BCR] = { 0x7b000 },
3159+ [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x7c014 },
3160+ [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x7c020 },
3161+ [GCC_PCIE_0_PHY_BCR] = { 0x7c01c },
3162+ [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x7c028 },
3163+ [GCC_PCIE_1_BCR] = { 0x9d000 },
3164+ [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x9e014 },
3165+ [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x9e020 },
3166+ [GCC_PCIE_1_PHY_BCR] = { 0x9e01c },
3167+ [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x9e000 },
3168+ [GCC_PCIE_PHY_BCR] = { 0x7f000 },
3169+ [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c },
3170+ [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },
3171+ [GCC_PDM_BCR] = { 0x43000 },
3172+ [GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 },
3173+ [GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 },
3174+ [GCC_QUPV3_WRAPPER_2_BCR] = { 0x2e000 },
3175+ [GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 },
3176+ [GCC_QUSB2PHY_SEC_BCR] = { 0x22004 },
3177+ [GCC_SDCC2_BCR] = { 0x24000 },
3178+ [GCC_SDCC4_BCR] = { 0x26000 },
3179+ [GCC_UFS_PHY_BCR] = { 0x87000 },
3180+ [GCC_USB30_PRIM_BCR] = { 0x49000 },
3181+ [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 },
3182+ [GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 },
3183+ [GCC_USB3_PHY_PRIM_BCR] = { 0x60000 },
3184+ [GCC_USB3_PHY_SEC_BCR] = { 0x6000c },
3185+ [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 },
3186+ [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 },
3187+ [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 },
3188+ [GCC_VIDEO_AXI0_CLK_ARES] = { 0x42018, 2 },
3189+ [GCC_VIDEO_AXI1_CLK_ARES] = { 0x42020, 2 },
3190+ [GCC_VIDEO_BCR] = { 0x42000 },
3191+};
3192+
3193+static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3194+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3195+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3196+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3197+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3198+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3199+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3200+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3201+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
3202+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3203+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3204+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3205+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3206+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3207+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3208+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
3209+ DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
3210+ DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
3211+ DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
3212+ DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
3213+ DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
3214+ DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
3215+ DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),
3216+};
3217+
3218+static struct gdsc *gcc_sm8450_gdscs[] = {
3219+ [PCIE_0_GDSC] = &pcie_0_gdsc,
3220+ [PCIE_1_GDSC] = &pcie_1_gdsc,
3221+ [UFS_PHY_GDSC] = &ufs_phy_gdsc,
3222+ [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3223+};
3224+
3225+static const struct regmap_config gcc_sm8450_regmap_config = {
3226+ .reg_bits = 32,
3227+ .reg_stride = 4,
3228+ .val_bits = 32,
3229+ .max_register = 0x1f1030,
3230+ .fast_io = true,
3231+};
3232+
3233+static const struct qcom_cc_desc gcc_sm8450_desc = {
3234+ .config = &gcc_sm8450_regmap_config,
3235+ .clks = gcc_sm8450_clocks,
3236+ .num_clks = ARRAY_SIZE(gcc_sm8450_clocks),
3237+ .resets = gcc_sm8450_resets,
3238+ .num_resets = ARRAY_SIZE(gcc_sm8450_resets),
3239+ .gdscs = gcc_sm8450_gdscs,
3240+ .num_gdscs = ARRAY_SIZE(gcc_sm8450_gdscs),
3241+};
3242+
3243+static const struct of_device_id gcc_sm8450_match_table[] = {
3244+ { .compatible = "qcom,gcc-sm8450" },
3245+ { }
3246+};
3247+MODULE_DEVICE_TABLE(of, gcc_sm8450_match_table);
3248+
3249+static int gcc_sm8450_probe(struct platform_device *pdev)
3250+{
3251+ struct regmap *regmap;
3252+ int ret;
3253+
3254+ regmap = qcom_cc_map(pdev, &gcc_sm8450_desc);
3255+ if (IS_ERR(regmap))
3256+ return PTR_ERR(regmap);
3257+
3258+ ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
3259+ ARRAY_SIZE(gcc_dfs_clocks));
3260+ if (ret)
3261+ return ret;
3262+
3263+ /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
3264+ regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
3265+
3266+ /*
3267+ * Keep the critical clock always-On
3268+ * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk,
3269+ * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk,
3270+ * gcc_video_xo_clk
3271+ */
3272+ regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0));
3273+ regmap_update_bits(regmap, 0x36020, BIT(0), BIT(0));
3274+ regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0));
3275+ regmap_update_bits(regmap, 0x3701c, BIT(0), BIT(0));
3276+ regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0));
3277+ regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0));
3278+ regmap_update_bits(regmap, 0x42028, BIT(0), BIT(0));
3279+
3280+ return qcom_cc_really_probe(pdev, &gcc_sm8450_desc, regmap);
3281+}
3282+
3283+static struct platform_driver gcc_sm8450_driver = {
3284+ .probe = gcc_sm8450_probe,
3285+ .driver = {
3286+ .name = "gcc-sm8450",
3287+ .of_match_table = gcc_sm8450_match_table,
3288+ },
3289+};
3290+
3291+static int __init gcc_sm8450_init(void)
3292+{
3293+ return platform_driver_register(&gcc_sm8450_driver);
3294+}
3295+subsys_initcall(gcc_sm8450_init);
3296+
3297+static void __exit gcc_sm8450_exit(void)
3298+{
3299+ platform_driver_unregister(&gcc_sm8450_driver);
3300+}
3301+module_exit(gcc_sm8450_exit);
3302+
3303+MODULE_DESCRIPTION("QTI GCC SM8450 Driver");
3304+MODULE_LICENSE("GPL v2");
drivers/clk/qcom/lpasscc-sc7280.c+1−0
@@ -3,6 +3,7 @@ · 2 unmodified lines
33 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
44 */
55
6+#include <linux/clk-provider.h>
67 #include <linux/platform_device.h>
78 #include <linux/pm_clock.h>
89 #include <linux/pm_runtime.h>
drivers/clk/qcom/lpasscc-sdm845.c+1−0
@@ -3,6 +3,7 @@ · 2 unmodified lines
33 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
44 */
55
6+#include <linux/clk-provider.h>
67 #include <linux/platform_device.h>
78 #include <linux/module.h>
89 #include <linux/of_address.h>
drivers/clk/qcom/mmcc-apq8084.c+1−0
@@ -3,6 +3,7 @@ · 2 unmodified lines
33 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
44 */
55
6+#include <linux/clk-provider.h>
67 #include <linux/kernel.h>
78 #include <linux/platform_device.h>
89 #include <linux/module.h>
drivers/clk/qcom/q6sstop-qcs404.c+1−0
@@ -4,6 +4,7 @@ · 3 unmodified lines
44 */
55
66 #include <linux/bitops.h>
7+#include <linux/clk-provider.h>
78 #include <linux/err.h>
89 #include <linux/module.h>
910 #include <linux/platform_device.h>
drivers/clk/qcom/turingcc-qcs404.c+1−0
@@ -4,6 +4,7 @@ · 3 unmodified lines
44 */
55
66 #include <linux/bitops.h>
7+#include <linux/clk-provider.h>
78 #include <linux/err.h>
89 #include <linux/platform_device.h>
910 #include <linux/module.h>
drivers/clk/renesas/Kconfig+11−2
@@ -31,6 +31,7 @@ config CLK_RENESAS · 30 unmodified lines
3131 select CLK_R8A77990 if ARCH_R8A77990
3232 select CLK_R8A77995 if ARCH_R8A77995
3333 select CLK_R8A779A0 if ARCH_R8A779A0
34+ select CLK_R8A779F0 if ARCH_R8A779F0
3435 select CLK_R9A06G032 if ARCH_R9A06G032
3536 select CLK_R9A07G044 if ARCH_R9A07G044
3637 select CLK_SH73A0 if ARCH_SH73A0
@@ -149,8 +150,11 @@ config CLK_R8A77995 · 112 unmodified lines
149150
150151 config CLK_R8A779A0
151152 bool "R-Car V3U clock support" if COMPILE_TEST
152− select CLK_RCAR_CPG_LIB
153− select CLK_RENESAS_CPG_MSSR
153+ select CLK_RCAR_GEN4_CPG
154+
155+config CLK_R8A779F0
156+ bool "R-Car S4-8 clock support" if COMPILE_TEST
157+ select CLK_RCAR_GEN4_CPG
154158
155159 config CLK_R9A06G032
156160 bool "RZ/N1D clock support" if COMPILE_TEST
@@ -178,6 +182,11 @@ config CLK_RCAR_GEN3_CPG · 21 unmodified lines
178182 select CLK_RCAR_CPG_LIB
179183 select CLK_RENESAS_CPG_MSSR
180184
185+config CLK_RCAR_GEN4_CPG
186+ bool "R-Car Gen4 clock support" if COMPILE_TEST
187+ select CLK_RCAR_CPG_LIB
188+ select CLK_RENESAS_CPG_MSSR
189+
181190 config CLK_RCAR_USB2_CLOCK_SEL
182191 bool "Renesas R-Car USB2 clock selector support"
183192 depends on ARCH_RENESAS || COMPILE_TEST
drivers/clk/renesas/Makefile+2−0
@@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o · 27 unmodified lines
2828 obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
2929 obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
3030 obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
31+obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
3132 obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
3233 obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
3334 obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
@@ -36,6 +37,7 @@ obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o · 2 unmodified lines
3637 obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o
3738 obj-$(CONFIG_CLK_RCAR_GEN2_CPG) += rcar-gen2-cpg.o
3839 obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o
40+obj-$(CONFIG_CLK_RCAR_GEN4_CPG) += rcar-gen4-cpg.o
3941 obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) += rcar-usb2-clock-sel.o
4042 obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o
4143
drivers/clk/renesas/r8a774a1-cpg-mssr.c+8−4
@@ -100,10 +100,14 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { · 99 unmodified lines
100100 DEF_FIXED("s3d2", R8A774A1_CLK_S3D2, CLK_S3, 2, 1),
101101 DEF_FIXED("s3d4", R8A774A1_CLK_S3D4, CLK_S3, 4, 1),
102102
103− DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, CLK_SDSRC, 0x074),
104− DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078),
105− DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268),
106− DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c),
103+ DEF_GEN3_SDH("sd0h", R8A774A1_CLK_SD0H, CLK_SDSRC, 0x074),
104+ DEF_GEN3_SDH("sd1h", R8A774A1_CLK_SD1H, CLK_SDSRC, 0x078),
105+ DEF_GEN3_SDH("sd2h", R8A774A1_CLK_SD2H, CLK_SDSRC, 0x268),
106+ DEF_GEN3_SDH("sd3h", R8A774A1_CLK_SD3H, CLK_SDSRC, 0x26c),
107+ DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, R8A774A1_CLK_SD0H, 0x074),
108+ DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, R8A774A1_CLK_SD1H, 0x078),
109+ DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, R8A774A1_CLK_SD2H, 0x268),
110+ DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, R8A774A1_CLK_SD3H, 0x26c),
107111
108112 DEF_FIXED("cl", R8A774A1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
109113 DEF_FIXED("cp", R8A774A1_CLK_CP, CLK_EXTAL, 2, 1),
drivers/clk/renesas/r8a774b1-cpg-mssr.c+8−4
@@ -97,10 +97,14 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = { · 96 unmodified lines
9797 DEF_FIXED("s3d2", R8A774B1_CLK_S3D2, CLK_S3, 2, 1),
9898 DEF_FIXED("s3d4", R8A774B1_CLK_S3D4, CLK_S3, 4, 1),
9999
100− DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, CLK_SDSRC, 0x074),
101− DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, CLK_SDSRC, 0x078),
102− DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, CLK_SDSRC, 0x268),
103− DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, CLK_SDSRC, 0x26c),
100+ DEF_GEN3_SDH("sd0h", R8A774B1_CLK_SD0H, CLK_SDSRC, 0x074),
101+ DEF_GEN3_SDH("sd1h", R8A774B1_CLK_SD1H, CLK_SDSRC, 0x078),
102+ DEF_GEN3_SDH("sd2h", R8A774B1_CLK_SD2H, CLK_SDSRC, 0x268),
103+ DEF_GEN3_SDH("sd3h", R8A774B1_CLK_SD3H, CLK_SDSRC, 0x26c),
104+ DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, R8A774B1_CLK_SD0H, 0x074),
105+ DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, R8A774B1_CLK_SD1H, 0x078),
106+ DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, R8A774B1_CLK_SD2H, 0x268),
107+ DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, R8A774B1_CLK_SD3H, 0x26c),
104108
105109 DEF_FIXED("cl", R8A774B1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
106110 DEF_FIXED("cp", R8A774B1_CLK_CP, CLK_EXTAL, 2, 1),
drivers/clk/renesas/r8a774c0-cpg-mssr.c+6−3
@@ -108,9 +108,12 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = { · 107 unmodified lines
108108 DEF_FIXED("s3d2", R8A774C0_CLK_S3D2, CLK_S3, 2, 1),
109109 DEF_FIXED("s3d4", R8A774C0_CLK_S3D4, CLK_S3, 4, 1),
110110
111− DEF_GEN3_SD("sd0", R8A774C0_CLK_SD0, CLK_SDSRC, 0x0074),
112− DEF_GEN3_SD("sd1", R8A774C0_CLK_SD1, CLK_SDSRC, 0x0078),
113− DEF_GEN3_SD("sd3", R8A774C0_CLK_SD3, CLK_SDSRC, 0x026c),
111+ DEF_GEN3_SDH("sd0h", R8A774C0_CLK_SD0H, CLK_SDSRC, 0x0074),
112+ DEF_GEN3_SDH("sd1h", R8A774C0_CLK_SD1H, CLK_SDSRC, 0x0078),
113+ DEF_GEN3_SDH("sd3h", R8A774C0_CLK_SD3H, CLK_SDSRC, 0x026c),
114+ DEF_GEN3_SD("sd0", R8A774C0_CLK_SD0, R8A774C0_CLK_SD0H, 0x0074),
115+ DEF_GEN3_SD("sd1", R8A774C0_CLK_SD1, R8A774C0_CLK_SD1H, 0x0078),
116+ DEF_GEN3_SD("sd3", R8A774C0_CLK_SD3, R8A774C0_CLK_SD3H, 0x026c),
114117
115118 DEF_FIXED("cl", R8A774C0_CLK_CL, CLK_PLL1, 48, 1),
116119 DEF_FIXED("cp", R8A774C0_CLK_CP, CLK_EXTAL, 2, 1),
drivers/clk/renesas/r8a774e1-cpg-mssr.c+8−4
@@ -100,10 +100,14 @@ static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = { · 99 unmodified lines
100100 DEF_FIXED("s3d2", R8A774E1_CLK_S3D2, CLK_S3, 2, 1),
101101 DEF_FIXED("s3d4", R8A774E1_CLK_S3D4, CLK_S3, 4, 1),
102102
103− DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, CLK_SDSRC, 0x074),
104− DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, CLK_SDSRC, 0x078),
105− DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, CLK_SDSRC, 0x268),
106− DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, CLK_SDSRC, 0x26c),
103+ DEF_GEN3_SDH("sd0h", R8A774E1_CLK_SD0H, CLK_SDSRC, 0x074),
104+ DEF_GEN3_SDH("sd1h", R8A774E1_CLK_SD1H, CLK_SDSRC, 0x078),
105+ DEF_GEN3_SDH("sd2h", R8A774E1_CLK_SD2H, CLK_SDSRC, 0x268),
106+ DEF_GEN3_SDH("sd3h", R8A774E1_CLK_SD3H, CLK_SDSRC, 0x26c),
107+ DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, R8A774E1_CLK_SD0H, 0x074),
108+ DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, R8A774E1_CLK_SD1H, 0x078),
109+ DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, R8A774E1_CLK_SD2H, 0x268),
110+ DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, R8A774E1_CLK_SD3H, 0x26c),
107111
108112 DEF_FIXED("cl", R8A774E1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
109113 DEF_FIXED("cr", R8A774E1_CLK_CR, CLK_PLL1_DIV4, 2, 1),
drivers/clk/renesas/r8a7795-cpg-mssr.c+8−4
@@ -104,10 +104,14 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { · 103 unmodified lines
104104 DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
105105 DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
106106
107− DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
108− DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
109− DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
110− DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
107+ DEF_GEN3_SDH("sd0h", R8A7795_CLK_SD0H, CLK_SDSRC, 0x074),
108+ DEF_GEN3_SDH("sd1h", R8A7795_CLK_SD1H, CLK_SDSRC, 0x078),
109+ DEF_GEN3_SDH("sd2h", R8A7795_CLK_SD2H, CLK_SDSRC, 0x268),
110+ DEF_GEN3_SDH("sd3h", R8A7795_CLK_SD3H, CLK_SDSRC, 0x26c),
111+ DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, R8A7795_CLK_SD0H, 0x074),
112+ DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, R8A7795_CLK_SD1H, 0x078),
113+ DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, R8A7795_CLK_SD2H, 0x268),
114+ DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, R8A7795_CLK_SD3H, 0x26c),
111115
112116 DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
113117 DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1),
drivers/clk/renesas/r8a7796-cpg-mssr.c+8−4
@@ -106,10 +106,14 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { · 105 unmodified lines
106106 DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1),
107107 DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1),
108108
109− DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
110− DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
111− DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
112− DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
109+ DEF_GEN3_SDH("sd0h", R8A7796_CLK_SD0H, CLK_SDSRC, 0x074),
110+ DEF_GEN3_SDH("sd1h", R8A7796_CLK_SD1H, CLK_SDSRC, 0x078),
111+ DEF_GEN3_SDH("sd2h", R8A7796_CLK_SD2H, CLK_SDSRC, 0x268),
112+ DEF_GEN3_SDH("sd3h", R8A7796_CLK_SD3H, CLK_SDSRC, 0x26c),
113+ DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, R8A7796_CLK_SD0H, 0x074),
114+ DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, R8A7796_CLK_SD1H, 0x078),
115+ DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, R8A7796_CLK_SD2H, 0x268),
116+ DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, R8A7796_CLK_SD3H, 0x26c),
113117
114118 DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
115119 DEF_FIXED("cr", R8A7796_CLK_CR, CLK_PLL1_DIV4, 2, 1),
drivers/clk/renesas/r8a77965-cpg-mssr.c+8−4
@@ -101,10 +101,14 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { · 100 unmodified lines
101101 DEF_FIXED("s3d2", R8A77965_CLK_S3D2, CLK_S3, 2, 1),
102102 DEF_FIXED("s3d4", R8A77965_CLK_S3D4, CLK_S3, 4, 1),
103103
104− DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, CLK_SDSRC, 0x074),
105− DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, CLK_SDSRC, 0x078),
106− DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268),
107− DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c),
104+ DEF_GEN3_SDH("sd0h", R8A77965_CLK_SD0H, CLK_SDSRC, 0x074),
105+ DEF_GEN3_SDH("sd1h", R8A77965_CLK_SD1H, CLK_SDSRC, 0x078),
106+ DEF_GEN3_SDH("sd2h", R8A77965_CLK_SD2H, CLK_SDSRC, 0x268),
107+ DEF_GEN3_SDH("sd3h", R8A77965_CLK_SD3H, CLK_SDSRC, 0x26c),
108+ DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, R8A77965_CLK_SD0H, 0x074),
109+ DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, R8A77965_CLK_SD1H, 0x078),
110+ DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, R8A77965_CLK_SD2H, 0x268),
111+ DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, R8A77965_CLK_SD3H, 0x26c),
108112
109113 DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1),
110114 DEF_FIXED("cr", R8A77965_CLK_CR, CLK_PLL1_DIV4, 2, 1),
drivers/clk/renesas/r8a77980-cpg-mssr.c+2−1
@@ -96,7 +96,8 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = { · 95 unmodified lines
9696 DEF_FIXED("s3d2", R8A77980_CLK_S3D2, CLK_S3, 2, 1),
9797 DEF_FIXED("s3d4", R8A77980_CLK_S3D4, CLK_S3, 4, 1),
9898
99− DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, CLK_SDSRC, 0x0074),
99+ DEF_GEN3_SDH("sd0h", R8A77980_CLK_SD0H, CLK_SDSRC, 0x0074),
100+ DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, R8A77980_CLK_SD0H, 0x0074),
100101
101102 DEF_FIXED("cl", R8A77980_CLK_CL, CLK_PLL1_DIV2, 48, 1),
102103 DEF_FIXED("cp", R8A77980_CLK_CP, CLK_EXTAL, 2, 1),
drivers/clk/renesas/r8a77990-cpg-mssr.c+6−3
@@ -100,9 +100,12 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { · 99 unmodified lines
100100 DEF_FIXED("s3d2", R8A77990_CLK_S3D2, CLK_S3, 2, 1),
101101 DEF_FIXED("s3d4", R8A77990_CLK_S3D4, CLK_S3, 4, 1),
102102
103− DEF_GEN3_SD("sd0", R8A77990_CLK_SD0, CLK_SDSRC, 0x0074),
104− DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, CLK_SDSRC, 0x0078),
105− DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, CLK_SDSRC, 0x026c),
103+ DEF_GEN3_SDH("sd0h", R8A77990_CLK_SD0H, CLK_SDSRC, 0x0074),
104+ DEF_GEN3_SDH("sd1h", R8A77990_CLK_SD1H, CLK_SDSRC, 0x0078),
105+ DEF_GEN3_SDH("sd3h", R8A77990_CLK_SD3H, CLK_SDSRC, 0x026c),
106+ DEF_GEN3_SD("sd0", R8A77990_CLK_SD0, R8A77990_CLK_SD0H, 0x0074),
107+ DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, R8A77990_CLK_SD1H, 0x0078),
108+ DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, R8A77990_CLK_SD3H, 0x026c),
106109
107110 DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1),
108111 DEF_FIXED("cr", R8A77990_CLK_CR, CLK_PLL1D2, 2, 1),
drivers/clk/renesas/r8a77995-cpg-mssr.c+2−1
@@ -103,7 +103,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = { · 102 unmodified lines
103103 DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
104104 DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
105105
106− DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268),
106+ DEF_GEN3_SDH("sd0h", R8A77995_CLK_SD0H, CLK_SDSRC, 0x268),
107+ DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, R8A77995_CLK_SD0H, 0x268),
107108
108109 DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244),
109110 DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014),
drivers/clk/renesas/r8a779a0-cpg-mssr.c+26−317
@@ -10,46 +10,19 @@ · 9 unmodified lines
1010 * Copyright (C) 2015 Renesas Electronics Corp.
1111 */
1212
13−#include <linux/bug.h>
1413 #include <linux/bitfield.h>
1514 #include <linux/clk.h>
1615 #include <linux/clk-provider.h>
1716 #include <linux/device.h>
1817 #include <linux/err.h>
1918 #include <linux/init.h>
20−#include <linux/io.h>
2119 #include <linux/kernel.h>
22−#include <linux/pm.h>
23−#include <linux/slab.h>
2420 #include <linux/soc/renesas/rcar-rst.h>
2521
2622 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
2723
28−#include "rcar-cpg-lib.h"
2924 #include "renesas-cpg-mssr.h"
30−
31−enum rcar_r8a779a0_clk_types {
32− CLK_TYPE_R8A779A0_MAIN = CLK_TYPE_CUSTOM,
33− CLK_TYPE_R8A779A0_PLL1,
34− CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */
35− CLK_TYPE_R8A779A0_PLL5,
36− CLK_TYPE_R8A779A0_Z,
37− CLK_TYPE_R8A779A0_SD,
38− CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */
39− CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */
40− CLK_TYPE_R8A779A0_RPCSRC,
41− CLK_TYPE_R8A779A0_RPC,
42− CLK_TYPE_R8A779A0_RPCD2,
43−};
44−
45−struct rcar_r8a779a0_cpg_pll_config {
46− u8 extal_div;
47− u8 pll1_mult;
48− u8 pll1_div;
49− u8 pll5_mult;
50− u8 pll5_div;
51− u8 osc_prediv;
52−};
25+#include "rcar-gen4-cpg.h"
5326
5427 enum clk_ids {
5528 /* Core Clock Outputs exported to DT */
@@ -85,33 +58,18 @@ enum clk_ids { · 29 unmodified lines
8558 };
8659
8760 #define DEF_PLL(_name, _id, _offset) \
88− DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \
61+ DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \
8962 .offset = _offset)
9063
91−#define DEF_Z(_name, _id, _parent, _div, _offset) \
92− DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_Z, _parent, .div = _div, \
93− .offset = _offset)
94−
95−#define DEF_SD(_name, _id, _parent, _offset) \
96− DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SD, _parent, .offset = _offset)
97−
98−#define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
99− DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL, \
100− (_parent0) << 16 | (_parent1), \
101− .div = (_div0) << 16 | (_div1), .offset = _md)
102−
103−#define DEF_OSC(_name, _id, _parent, _div) \
104− DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div)
105−
10664 static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
10765 /* External Clock Inputs */
10866 DEF_INPUT("extal", CLK_EXTAL),
10967 DEF_INPUT("extalr", CLK_EXTALR),
11068
11169 /* Internal Core Clocks */
112− DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL),
113− DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN),
114− DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN),
70+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
71+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
72+ DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
11573 DEF_PLL(".pll20", CLK_PLL20, 0x0834),
11674 DEF_PLL(".pll21", CLK_PLL21, 0x0838),
11775 DEF_PLL(".pll30", CLK_PLL30, 0x083c),
@@ -128,14 +86,14 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { · 10 unmodified lines
12886 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1),
12987 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV4, 1, 1),
13088 DEF_RATE(".oco", CLK_OCO, 32768),
131− DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_R8A779A0_RPCSRC, CLK_PLL5),
132− DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_R8A779A0_RPC, CLK_RPCSRC),
133− DEF_BASE("rpcd2", R8A779A0_CLK_RPCD2, CLK_TYPE_R8A779A0_RPCD2,
89+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
90+ DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
91+ DEF_BASE("rpcd2", R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2,
13492 R8A779A0_CLK_RPC),
13593
13694 /* Core Clock Outputs */
137− DEF_Z("z0", R8A779A0_CLK_Z0, CLK_PLL20, 2, 0),
138− DEF_Z("z1", R8A779A0_CLK_Z1, CLK_PLL21, 2, 8),
95+ DEF_GEN4_Z("z0", R8A779A0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL20, 2, 0),
96+ DEF_GEN4_Z("z1", R8A779A0_CLK_Z1, CLK_TYPE_GEN4_Z, CLK_PLL21, 2, 8),
13997 DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1),
14098 DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1),
14199 DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1),
@@ -159,15 +117,16 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { · 17 unmodified lines
159117 DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1),
160118 DEF_FIXED("cl16mck", R8A779A0_CLK_CL16MCK, CLK_PLL1_DIV2, 64, 1),
161119
162− DEF_SD("sd0", R8A779A0_CLK_SD0, CLK_SDSRC, 0x870),
120+ DEF_GEN4_SDH("sdh0", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870),
121+ DEF_GEN4_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, 0x870),
163122
164123 DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
165124 DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
166125 DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
167126 DEF_DIV6P1("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 0x884),
168127
169− DEF_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8),
170− DEF_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
128+ DEF_GEN4_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8),
129+ DEF_GEN4_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
171130 };
172131
173132 static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
@@ -271,256 +230,6 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { · 97 unmodified lines
271230 DEF_MOD("vspx3", 1031, R8A779A0_CLK_S1D1),
272231 };
273232
274−static const struct rcar_r8a779a0_cpg_pll_config *cpg_pll_config __initdata;
275−static unsigned int cpg_clk_extalr __initdata;
276−static u32 cpg_mode __initdata;
277−
278−/*
279− * Z0 Clock & Z1 Clock
280− */
281−#define CPG_FRQCRB 0x00000804
282−#define CPG_FRQCRB_KICK BIT(31)
283−#define CPG_FRQCRC 0x00000808
284−
285−struct cpg_z_clk {
286− struct clk_hw hw;
287− void __iomem *reg;
288− void __iomem *kick_reg;
289− unsigned long max_rate; /* Maximum rate for normal mode */
290− unsigned int fixed_div;
291− u32 mask;
292−};
293−
294−#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
295−
296−static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
297− unsigned long parent_rate)
298−{
299− struct cpg_z_clk *zclk = to_z_clk(hw);
300− unsigned int mult;
301− u32 val;
302−
303− val = readl(zclk->reg) & zclk->mask;
304− mult = 32 - (val >> __ffs(zclk->mask));
305−
306− return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,
307− 32 * zclk->fixed_div);
308−}
309−
310−static int cpg_z_clk_determine_rate(struct clk_hw *hw,
311− struct clk_rate_request *req)
312−{
313− struct cpg_z_clk *zclk = to_z_clk(hw);
314− unsigned int min_mult, max_mult, mult;
315− unsigned long rate, prate;
316−
317− rate = min(req->rate, req->max_rate);
318− if (rate <= zclk->max_rate) {
319− /* Set parent rate to initial value for normal modes */
320− prate = zclk->max_rate;
321− } else {
322− /* Set increased parent rate for boost modes */
323− prate = rate;
324− }
325− req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
326− prate * zclk->fixed_div);
327−
328− prate = req->best_parent_rate / zclk->fixed_div;
329− min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
330− max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);
331− if (max_mult < min_mult)
332− return -EINVAL;
333−
334− mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate);
335− mult = clamp(mult, min_mult, max_mult);
336−
337− req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);
338− return 0;
339−}
340−
341−static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
342− unsigned long parent_rate)
343−{
344− struct cpg_z_clk *zclk = to_z_clk(hw);
345− unsigned int mult;
346− unsigned int i;
347−
348− mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,
349− parent_rate);
350− mult = clamp(mult, 1U, 32U);
351−
352− if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
353− return -EBUSY;
354−
355− cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask));
356−
357− /*
358− * Set KICK bit in FRQCRB to update hardware setting and wait for
359− * clock change completion.
360− */
361− cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK);
362−
363− /*
364− * Note: There is no HW information about the worst case latency.
365− *
366− * Using experimental measurements, it seems that no more than
367− * ~10 iterations are needed, independently of the CPU rate.
368− * Since this value might be dependent on external xtal rate, pll1
369− * rate or even the other emulation clocks rate, use 1000 as a
370− * "super" safe value.
371− */
372− for (i = 1000; i; i--) {
373− if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
374− return 0;
375−
376− cpu_relax();
377− }
378−
379− return -ETIMEDOUT;
380−}
381−
382−static const struct clk_ops cpg_z_clk_ops = {
383− .recalc_rate = cpg_z_clk_recalc_rate,
384− .determine_rate = cpg_z_clk_determine_rate,
385− .set_rate = cpg_z_clk_set_rate,
386−};
387−
388−static struct clk * __init cpg_z_clk_register(const char *name,
389− const char *parent_name,
390− void __iomem *reg,
391− unsigned int div,
392− unsigned int offset)
393−{
394− struct clk_init_data init = {};
395− struct cpg_z_clk *zclk;
396− struct clk *clk;
397−
398− zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
399− if (!zclk)
400− return ERR_PTR(-ENOMEM);
401−
402− init.name = name;
403− init.ops = &cpg_z_clk_ops;
404− init.flags = CLK_SET_RATE_PARENT;
405− init.parent_names = &parent_name;
406− init.num_parents = 1;
407−
408− zclk->reg = reg + CPG_FRQCRC;
409− zclk->kick_reg = reg + CPG_FRQCRB;
410− zclk->hw.init = &init;
411− zclk->mask = GENMASK(offset + 4, offset);
412− zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
413−
414− clk = clk_register(NULL, &zclk->hw);
415− if (IS_ERR(clk)) {
416− kfree(zclk);
417− return clk;
418− }
419−
420− zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) /
421− zclk->fixed_div;
422− return clk;
423−}
424−
425−/*
426− * RPC Clocks
427− */
428−#define CPG_RPCCKCR 0x874
429−
430−static const struct clk_div_table cpg_rpcsrc_div_table[] = {
431− { 0, 4 }, { 1, 6 }, { 2, 5 }, { 3, 6 }, { 0, 0 },
432−};
433−
434−static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
435− const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
436− struct clk **clks, void __iomem *base,
437− struct raw_notifier_head *notifiers)
438−{
439− const struct clk *parent;
440− unsigned int mult = 1;
441− unsigned int div = 1;
442− u32 value;
443−
444− parent = clks[core->parent & 0xffff]; /* some types use high bits */
445− if (IS_ERR(parent))
446− return ERR_CAST(parent);
447−
448− switch (core->type) {
449− case CLK_TYPE_R8A779A0_MAIN:
450− div = cpg_pll_config->extal_div;
451− break;
452−
453− case CLK_TYPE_R8A779A0_PLL1:
454− mult = cpg_pll_config->pll1_mult;
455− div = cpg_pll_config->pll1_div;
456− break;
457−
458− case CLK_TYPE_R8A779A0_PLL2X_3X:
459− value = readl(base + core->offset);
460− mult = (((value >> 24) & 0x7f) + 1) * 2;
461− break;
462−
463− case CLK_TYPE_R8A779A0_PLL5:
464− mult = cpg_pll_config->pll5_mult;
465− div = cpg_pll_config->pll5_div;
466− break;
467−
468− case CLK_TYPE_R8A779A0_Z:
469− return cpg_z_clk_register(core->name, __clk_get_name(parent),
470− base, core->div, core->offset);
471−
472− case CLK_TYPE_R8A779A0_SD:
473− return cpg_sd_clk_register(core->name, base, core->offset,
474− __clk_get_name(parent), notifiers,
475− false);
476− break;
477−
478− case CLK_TYPE_R8A779A0_MDSEL:
479− /*
480− * Clock selectable between two parents and two fixed dividers
481− * using a mode pin
482− */
483− if (cpg_mode & BIT(core->offset)) {
484− div = core->div & 0xffff;
485− } else {
486− parent = clks[core->parent >> 16];
487− if (IS_ERR(parent))
488− return ERR_CAST(parent);
489− div = core->div >> 16;
490− }
491− mult = 1;
492− break;
493−
494− case CLK_TYPE_R8A779A0_OSC:
495− /*
496− * Clock combining OSC EXTAL predivider and a fixed divider
497− */
498− div = cpg_pll_config->osc_prediv * core->div;
499− break;
500−
501− case CLK_TYPE_R8A779A0_RPCSRC:
502− return clk_register_divider_table(NULL, core->name,
503− __clk_get_name(parent), 0,
504− base + CPG_RPCCKCR, 3, 2, 0,
505− cpg_rpcsrc_div_table,
506− &cpg_lock);
507−
508− case CLK_TYPE_R8A779A0_RPC:
509− return cpg_rpc_clk_register(core->name, base + CPG_RPCCKCR,
510− __clk_get_name(parent), notifiers);
511−
512− case CLK_TYPE_R8A779A0_RPCD2:
513− return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR,
514− __clk_get_name(parent));
515−
516− default:
517− return ERR_PTR(-EINVAL);
518− }
519−
520− return clk_register_fixed_factor(NULL, core->name,
521− __clk_get_name(parent), 0, mult, div);
522−}
523−
524233 static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {
525234 MOD_CLK_ID(907), /* RWDT */
526235 };
@@ -539,17 +248,19 @@ static const unsigned int r8a779a0_crit_mod_clks[] __initconst = { · 12 unmodified lines
539248 */
540249 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
541250 (((md) & BIT(13)) >> 13))
542−
543−static const struct rcar_r8a779a0_cpg_pll_config cpg_pll_configs[4] = {
544− /* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */
545− { 1, 128, 1, 192, 1, 16, },
546− { 1, 106, 1, 160, 1, 19, },
547− { 0, 0, 0, 0, 0, 0, },
548− { 2, 128, 1, 192, 1, 32, },
251+static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
252+ /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
253+ { 1, 128, 1, 0, 0, 0, 0, 192, 1, 0, 0, 16, },
254+ { 1, 106, 1, 0, 0, 0, 0, 160, 1, 0, 0, 19, },
255+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
256+ { 2, 128, 1, 0, 0, 0, 0, 192, 1, 0, 0, 32, },
549257 };
550258
259+
551260 static int __init r8a779a0_cpg_mssr_init(struct device *dev)
552261 {
262+ const struct rcar_gen4_cpg_pll_config *cpg_pll_config;
263+ u32 cpg_mode;
553264 int error;
554265
555266 error = rcar_rst_read_mode_pins(&cpg_mode);
@@ -557,10 +268,8 @@ static int __init r8a779a0_cpg_mssr_init(struct device *dev) · 1 unmodified line
557268 return error;
558269
559270 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
560− cpg_clk_extalr = CLK_EXTALR;
561− spin_lock_init(&cpg_lock);
562271
563− return 0;
272+ return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
564273 }
565274
566275 const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = {
@@ -581,7 +290,7 @@ const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = { · 14 unmodified lines
581290
582291 /* Callbacks */
583292 .init = r8a779a0_cpg_mssr_init,
584− .cpg_clk_register = rcar_r8a779a0_cpg_clk_register,
293+ .cpg_clk_register = rcar_gen4_cpg_clk_register,
585294
586− .reg_layout = CLK_REG_LAYOUT_RCAR_V3U,
295+ .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
587296 };
drivers/clk/renesas/r8a779f0-cpg-mssr.c+183−0
@@ -0,0 +1,183 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * r8a779f0 Clock Pulse Generator / Module Standby and Software Reset
4+ *
5+ * Copyright (C) 2021 Renesas Electronics Corp.
6+ *
7+ * Based on r8a779a0-cpg-mssr.c
8+ */
9+
10+#include <linux/bitfield.h>
11+#include <linux/clk.h>
12+#include <linux/clk-provider.h>
13+#include <linux/device.h>
14+#include <linux/err.h>
15+#include <linux/kernel.h>
16+#include <linux/soc/renesas/rcar-rst.h>
17+
18+#include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
19+
20+#include "renesas-cpg-mssr.h"
21+#include "rcar-gen4-cpg.h"
22+
23+enum clk_ids {
24+ /* Core Clock Outputs exported to DT */
25+ LAST_DT_CORE_CLK = R8A779F0_CLK_R,
26+
27+ /* External Input Clocks */
28+ CLK_EXTAL,
29+ CLK_EXTALR,
30+
31+ /* Internal Core Clocks */
32+ CLK_MAIN,
33+ CLK_PLL1,
34+ CLK_PLL2,
35+ CLK_PLL3,
36+ CLK_PLL5,
37+ CLK_PLL6,
38+ CLK_PLL1_DIV2,
39+ CLK_PLL2_DIV2,
40+ CLK_PLL3_DIV2,
41+ CLK_PLL5_DIV2,
42+ CLK_PLL5_DIV4,
43+ CLK_PLL6_DIV2,
44+ CLK_S0,
45+ CLK_SDSRC,
46+ CLK_RPCSRC,
47+ CLK_OCO,
48+
49+ /* Module Clocks */
50+ MOD_CLK_BASE
51+};
52+
53+static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
54+ /* External Clock Inputs */
55+ DEF_INPUT("extal", CLK_EXTAL),
56+ DEF_INPUT("extalr", CLK_EXTALR),
57+
58+ /* Internal Core Clocks */
59+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
60+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
61+ DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN),
62+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
63+ DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
64+ DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
65+
66+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
67+ DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1),
68+ DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1),
69+ DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
70+ DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
71+ DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1),
72+ DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
73+ DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
74+ DEF_RATE(".oco", CLK_OCO, 32768),
75+
76+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
77+ DEF_BASE(".rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
78+ DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC),
79+
80+ /* Core Clock Outputs */
81+ DEF_FIXED("s0d2", R8A779F0_CLK_S0D2, CLK_S0, 2, 1),
82+ DEF_FIXED("s0d3", R8A779F0_CLK_S0D3, CLK_S0, 3, 1),
83+ DEF_FIXED("s0d4", R8A779F0_CLK_S0D4, CLK_S0, 4, 1),
84+ DEF_FIXED("cl16m", R8A779F0_CLK_CL16M, CLK_S0, 48, 1),
85+ DEF_FIXED("s0d2_mm", R8A779F0_CLK_S0D2_MM, CLK_S0, 2, 1),
86+ DEF_FIXED("s0d3_mm", R8A779F0_CLK_S0D3_MM, CLK_S0, 3, 1),
87+ DEF_FIXED("s0d4_mm", R8A779F0_CLK_S0D4_MM, CLK_S0, 4, 1),
88+ DEF_FIXED("cl16m_mm", R8A779F0_CLK_CL16M_MM, CLK_S0, 48, 1),
89+ DEF_FIXED("s0d2_rt", R8A779F0_CLK_S0D2_RT, CLK_S0, 2, 1),
90+ DEF_FIXED("s0d3_rt", R8A779F0_CLK_S0D3_RT, CLK_S0, 3, 1),
91+ DEF_FIXED("s0d4_rt", R8A779F0_CLK_S0D4_RT, CLK_S0, 4, 1),
92+ DEF_FIXED("s0d6_rt", R8A779F0_CLK_S0D6_RT, CLK_S0, 6, 1),
93+ DEF_FIXED("cl16m_rt", R8A779F0_CLK_CL16M_RT, CLK_S0, 48, 1),
94+ DEF_FIXED("s0d3_per", R8A779F0_CLK_S0D3_PER, CLK_S0, 3, 1),
95+ DEF_FIXED("s0d6_per", R8A779F0_CLK_S0D6_PER, CLK_S0, 6, 1),
96+ DEF_FIXED("s0d12_per", R8A779F0_CLK_S0D12_PER, CLK_S0, 12, 1),
97+ DEF_FIXED("s0d24_per", R8A779F0_CLK_S0D24_PER, CLK_S0, 24, 1),
98+ DEF_FIXED("cl16m_per", R8A779F0_CLK_CL16M_PER, CLK_S0, 48, 1),
99+ DEF_FIXED("s0d2_hsc", R8A779F0_CLK_S0D2_HSC, CLK_S0, 2, 1),
100+ DEF_FIXED("s0d3_hsc", R8A779F0_CLK_S0D3_HSC, CLK_S0, 3, 1),
101+ DEF_FIXED("s0d4_hsc", R8A779F0_CLK_S0D4_HSC, CLK_S0, 4, 1),
102+ DEF_FIXED("s0d6_hsc", R8A779F0_CLK_S0D6_HSC, CLK_S0, 6, 1),
103+ DEF_FIXED("s0d12_hsc", R8A779F0_CLK_S0D12_HSC, CLK_S0, 12, 1),
104+ DEF_FIXED("cl16m_hsc", R8A779F0_CLK_CL16M_HSC, CLK_S0, 48, 1),
105+ DEF_FIXED("s0d2_cc", R8A779F0_CLK_S0D2_CC, CLK_S0, 2, 1),
106+ DEF_FIXED("rsw2", R8A779F0_CLK_RSW2, CLK_PLL5, 2, 1),
107+ DEF_FIXED("cbfusa", R8A779F0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
108+ DEF_FIXED("cpex", R8A779F0_CLK_CPEX, CLK_EXTAL, 2, 1),
109+
110+ DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, CLK_SDSRC, 0x870),
111+ DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
112+
113+ DEF_GEN4_OSC("osc", R8A779F0_CLK_OSC, CLK_EXTAL, 8),
114+ DEF_GEN4_MDSEL("r", R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
115+};
116+
117+static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
118+ DEF_MOD("scif0", 702, R8A779F0_CLK_S0D12_PER),
119+ DEF_MOD("scif1", 703, R8A779F0_CLK_S0D12_PER),
120+ DEF_MOD("scif3", 704, R8A779F0_CLK_S0D12_PER),
121+ DEF_MOD("scif4", 705, R8A779F0_CLK_S0D12_PER),
122+};
123+
124+/*
125+ * CPG Clock Data
126+ */
127+/*
128+ * MD EXTAL PLL1 PLL2 PLL3 PLL5 PLL6 OSC
129+ * 14 13 (MHz)
130+ * ----------------------------------------------------------------
131+ * 0 0 16 / 1 x200 x150 x200 x200 x134 /15
132+ * 0 1 20 / 1 x160 x120 x160 x160 x106 /19
133+ * 1 0 Prohibited setting
134+ * 1 1 40 / 2 x160 x120 x160 x160 x106 /38
135+ */
136+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
137+ (((md) & BIT(13)) >> 13))
138+
139+static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
140+ /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
141+ { 1, 200, 1, 150, 1, 200, 1, 200, 1, 134, 1, 15, },
142+ { 1, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 19, },
143+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
144+ { 2, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 38, },
145+};
146+
147+static int __init r8a779f0_cpg_mssr_init(struct device *dev)
148+{
149+ const struct rcar_gen4_cpg_pll_config *cpg_pll_config;
150+ u32 cpg_mode;
151+ int error;
152+
153+ error = rcar_rst_read_mode_pins(&cpg_mode);
154+ if (error)
155+ return error;
156+
157+ cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
158+ if (!cpg_pll_config->extal_div) {
159+ dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
160+ return -EINVAL;
161+ }
162+
163+ return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
164+}
165+
166+const struct cpg_mssr_info r8a779f0_cpg_mssr_info __initconst = {
167+ /* Core Clocks */
168+ .core_clks = r8a779f0_core_clks,
169+ .num_core_clks = ARRAY_SIZE(r8a779f0_core_clks),
170+ .last_dt_core_clk = LAST_DT_CORE_CLK,
171+ .num_total_core_clks = MOD_CLK_BASE,
172+
173+ /* Module Clocks */
174+ .mod_clks = r8a779f0_mod_clks,
175+ .num_mod_clks = ARRAY_SIZE(r8a779f0_mod_clks),
176+ .num_hw_mod_clks = 28 * 32,
177+
178+ /* Callbacks */
179+ .init = r8a779f0_cpg_mssr_init,
180+ .cpg_clk_register = rcar_gen4_cpg_clk_register,
181+
182+ .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
183+};
drivers/clk/renesas/r9a07g044-cpg.c+72−9
@@ -26,15 +26,15 @@ enum clk_ids { · 25 unmodified lines
2626 CLK_PLL1,
2727 CLK_PLL2,
2828 CLK_PLL2_DIV2,
29− CLK_PLL2_DIV16,
30− CLK_PLL2_DIV20,
29+ CLK_PLL2_DIV2_8,
30+ CLK_PLL2_DIV2_10,
3131 CLK_PLL3,
3232 CLK_PLL3_400,
3333 CLK_PLL3_533,
3434 CLK_PLL3_DIV2,
35+ CLK_PLL3_DIV2_2,
3536 CLK_PLL3_DIV2_4,
3637 CLK_PLL3_DIV2_4_2,
37− CLK_PLL3_DIV4,
3838 CLK_SEL_PLL3_3,
3939 CLK_DIV_PLL3_C,
4040 CLK_PLL4,
@@ -50,12 +50,21 @@ enum clk_ids { · 9 unmodified lines
5050 CLK_PLL2_SDHI_266,
5151 CLK_SD0_DIV4,
5252 CLK_SD1_DIV4,
53+ CLK_SEL_GPU2,
5354
5455 /* Module Clocks */
5556 MOD_CLK_BASE,
5657 };
5758
5859 /* Divider tables */
60+static const struct clk_div_table dtable_1_8[] = {
61+ {0, 1},
62+ {1, 2},
63+ {2, 4},
64+ {3, 8},
65+ {0, 0},
66+};
67+
5968 static const struct clk_div_table dtable_1_32[] = {
6069 {0, 1},
6170 {1, 2},
@@ -69,6 +78,7 @@ static const struct clk_div_table dtable_1_32[] = { · 7 unmodified lines
6978 static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
7079 static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
7180 static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
81+static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
7282
7383 static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
7484 /* External Clock Inputs */
@@ -94,13 +104,13 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { · 19 unmodified lines
94104 DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2),
95105 DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2),
96106
97− DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16),
98− DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20),
107+ DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
108+ DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),
99109
100110 DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
111+ DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2),
101112 DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
102113 DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
103− DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
104114 DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3,
105115 sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY),
106116 DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,
@@ -108,13 +118,16 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { · 1 unmodified line
108118
109119 DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),
110120 DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
121+ DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2,
122+ sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY),
111123
112124 /* Core output clk */
113− DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
114− DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
125+ DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
126+ CLK_DIVIDER_HIWORD_MASK),
127+ DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,
115128 dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
116129 DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
117− DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
130+ DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),
118131 DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
119132 DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
120133 DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),
@@ -132,6 +145,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { · 11 unmodified lines
132145 sel_shdi, ARRAY_SIZE(sel_shdi)),
133146 DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
134147 DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
148+ DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8,
149+ CLK_DIVIDER_HIWORD_MASK),
135150 };
136151
137152 static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
@@ -145,6 +160,24 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { · 7 unmodified lines
145160 0x52c, 0),
146161 DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
147162 0x52c, 1),
163+ DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0,
164+ 0x534, 0),
165+ DEF_MOD("ostm1_clk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0,
166+ 0x534, 1),
167+ DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
168+ 0x534, 2),
169+ DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,
170+ 0x548, 0),
171+ DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
172+ 0x548, 1),
173+ DEF_MOD("wdt1_pclk", R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0,
174+ 0x548, 2),
175+ DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK,
176+ 0x548, 3),
177+ DEF_MOD("wdt2_pclk", R9A07G044_WDT2_PCLK, R9A07G044_CLK_P0,
178+ 0x548, 4),
179+ DEF_MOD("wdt2_clk", R9A07G044_WDT2_CLK, R9A07G044_OSCCLK,
180+ 0x548, 5),
148181 DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1,
149182 0x550, 0),
150183 DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0,
@@ -165,6 +198,12 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { · 14 unmodified lines
165198 0x554, 6),
166199 DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1,
167200 0x554, 7),
201+ DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G,
202+ 0x558, 0),
203+ DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1,
204+ 0x558, 1),
205+ DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
206+ 0x558, 2),
168207 DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
169208 0x570, 0),
170209 DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
@@ -217,6 +256,14 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { · 46 unmodified lines
217256 0x584, 4),
218257 DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
219258 0x588, 0),
259+ DEF_MOD("sci1", R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0,
260+ 0x588, 1),
261+ DEF_MOD("rspi0", R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0,
262+ 0x590, 0),
263+ DEF_MOD("rspi1", R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0,
264+ 0x590, 1),
265+ DEF_MOD("rspi2", R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0,
266+ 0x590, 2),
220267 DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,
221268 0x594, 0),
222269 DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
@@ -225,6 +272,8 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { · 2 unmodified lines
225272 0x5a8, 0),
226273 DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0,
227274 0x5a8, 1),
275+ DEF_MOD("tsu_pclk", R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU,
276+ 0x5ac, 0),
228277 };
229278
230279 static struct rzg2l_reset r9a07g044_resets[] = {
@@ -233,9 +282,18 @@ static struct rzg2l_reset r9a07g044_resets[] = { · 2 unmodified lines
233282 DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
234283 DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
235284 DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
285+ DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
286+ DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
287+ DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
288+ DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
289+ DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
290+ DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2),
236291 DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
237292 DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
238293 DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
294+ DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
295+ DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
296+ DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
239297 DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
240298 DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
241299 DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
@@ -256,6 +314,10 @@ static struct rzg2l_reset r9a07g044_resets[] = { · 14 unmodified lines
256314 DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
257315 DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
258316 DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
317+ DEF_RST(R9A07G044_SCI1_RST, 0x888, 1),
318+ DEF_RST(R9A07G044_RSPI0_RST, 0x890, 0),
319+ DEF_RST(R9A07G044_RSPI1_RST, 0x890, 1),
320+ DEF_RST(R9A07G044_RSPI2_RST, 0x890, 2),
259321 DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0),
260322 DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1),
261323 DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),
@@ -263,6 +325,7 @@ static struct rzg2l_reset r9a07g044_resets[] = { · 1 unmodified line
263325 DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),
264326 DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
265327 DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
328+ DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0),
266329 };
267330
268331 static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
drivers/clk/renesas/rcar-cpg-lib.c+27−184
@@ -65,206 +65,49 @@ void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, · 64 unmodified lines
6565 /*
6666 * SDn Clock
6767 */
68−#define CPG_SD_STP_HCK BIT(9)
69−#define CPG_SD_STP_CK BIT(8)
70−
71−#define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
72−#define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
73−
74−#define CPG_SD_DIV_TABLE_DATA(stp_hck, sd_srcfc, sd_fc, sd_div) \
75−{ \
76− .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
77− ((sd_srcfc) << 2) | \
78− ((sd_fc) << 0), \
79− .div = (sd_div), \
80−}
8168
82−struct sd_div_table {
83− u32 val;
84− unsigned int div;
85−};
69+#define SDnSRCFC_SHIFT 2
70+#define STPnHCK BIT(9 - SDnSRCFC_SHIFT)
8671
87−struct sd_clock {
88− struct clk_hw hw;
89− const struct sd_div_table *div_table;
90− struct cpg_simple_notifier csn;
91− unsigned int div_num;
92− unsigned int cur_div_idx;
93−};
94−
95−/* SDn divider
96− * sd_srcfc sd_fc div
97− * stp_hck (div) (div) = sd_srcfc x sd_fc
98− *---------------------------------------------------------
99− * 0 0 (1) 1 (4) 4 : SDR104 / HS200 / HS400 (8 TAP)
100− * 0 1 (2) 1 (4) 8 : SDR50
101− * 1 2 (4) 1 (4) 16 : HS / SDR25
102− * 1 3 (8) 1 (4) 32 : NS / SDR12
103− * 1 4 (16) 1 (4) 64
104− * 0 0 (1) 0 (2) 2
105− * 0 1 (2) 0 (2) 4 : SDR104 / HS200 / HS400 (4 TAP)
106− * 1 2 (4) 0 (2) 8
107− * 1 3 (8) 0 (2) 16
108− * 1 4 (16) 0 (2) 32
109− *
110− * NOTE: There is a quirk option to ignore the first row of the dividers
111− * table when searching for suitable settings. This is because HS400 on
112− * early ES versions of H3 and M3-W requires a specific setting to work.
113− */
114−static const struct sd_div_table cpg_sd_div_table[] = {
115−/* CPG_SD_DIV_TABLE_DATA(stp_hck, sd_srcfc, sd_fc, sd_div) */
116− CPG_SD_DIV_TABLE_DATA(0, 0, 1, 4),
117− CPG_SD_DIV_TABLE_DATA(0, 1, 1, 8),
118− CPG_SD_DIV_TABLE_DATA(1, 2, 1, 16),
119− CPG_SD_DIV_TABLE_DATA(1, 3, 1, 32),
120− CPG_SD_DIV_TABLE_DATA(1, 4, 1, 64),
121− CPG_SD_DIV_TABLE_DATA(0, 0, 0, 2),
122− CPG_SD_DIV_TABLE_DATA(0, 1, 0, 4),
123− CPG_SD_DIV_TABLE_DATA(1, 2, 0, 8),
124− CPG_SD_DIV_TABLE_DATA(1, 3, 0, 16),
125− CPG_SD_DIV_TABLE_DATA(1, 4, 0, 32),
72+static const struct clk_div_table cpg_sdh_div_table[] = {
73+ { 0, 1 }, { 1, 2 }, { STPnHCK | 2, 4 }, { STPnHCK | 3, 8 },
74+ { STPnHCK | 4, 16 }, { 0, 0 },
12675 };
12776
128−#define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
129−
130−static int cpg_sd_clock_enable(struct clk_hw *hw)
131−{
132− struct sd_clock *clock = to_sd_clock(hw);
133−
134− cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK,
135− clock->div_table[clock->cur_div_idx].val &
136− CPG_SD_STP_MASK);
137−
138− return 0;
139−}
140−
141−static void cpg_sd_clock_disable(struct clk_hw *hw)
142−{
143− struct sd_clock *clock = to_sd_clock(hw);
144−
145− cpg_reg_modify(clock->csn.reg, 0, CPG_SD_STP_MASK);
146−}
147−
148−static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
77+struct clk * __init cpg_sdh_clk_register(const char *name,
78+ void __iomem *sdnckcr, const char *parent_name,
79+ struct raw_notifier_head *notifiers)
14980 {
150− struct sd_clock *clock = to_sd_clock(hw);
151−
152− return !(readl(clock->csn.reg) & CPG_SD_STP_MASK);
153−}
81+ struct cpg_simple_notifier *csn;
82+ struct clk *clk;
15483
155−static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
156− unsigned long parent_rate)
157−{
158− struct sd_clock *clock = to_sd_clock(hw);
84+ csn = kzalloc(sizeof(*csn), GFP_KERNEL);
85+ if (!csn)
86+ return ERR_PTR(-ENOMEM);
15987
160− return DIV_ROUND_CLOSEST(parent_rate,
161− clock->div_table[clock->cur_div_idx].div);
162−}
88+ csn->reg = sdnckcr;
16389
164−static int cpg_sd_clock_determine_rate(struct clk_hw *hw,
165− struct clk_rate_request *req)
166−{
167− unsigned long best_rate = ULONG_MAX, diff_min = ULONG_MAX;
168− struct sd_clock *clock = to_sd_clock(hw);
169− unsigned long calc_rate, diff;
170− unsigned int i;
171−
172− for (i = 0; i < clock->div_num; i++) {
173− calc_rate = DIV_ROUND_CLOSEST(req->best_parent_rate,
174− clock->div_table[i].div);
175− if (calc_rate < req->min_rate || calc_rate > req->max_rate)
176− continue;
177−
178− diff = calc_rate > req->rate ? calc_rate - req->rate
179− : req->rate - calc_rate;
180− if (diff < diff_min) {
181− best_rate = calc_rate;
182− diff_min = diff;
183− }
90+ clk = clk_register_divider_table(NULL, name, parent_name, 0, sdnckcr,
91+ SDnSRCFC_SHIFT, 8, 0, cpg_sdh_div_table,
92+ &cpg_lock);
93+ if (IS_ERR(clk)) {
94+ kfree(csn);
95+ return clk;
18496 }
18597
186− if (best_rate == ULONG_MAX)
187− return -EINVAL;
188−
189− req->rate = best_rate;
190− return 0;
191−}
192−
193−static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
194− unsigned long parent_rate)
195−{
196− struct sd_clock *clock = to_sd_clock(hw);
197− unsigned int i;
198−
199− for (i = 0; i < clock->div_num; i++)
200− if (rate == DIV_ROUND_CLOSEST(parent_rate,
201− clock->div_table[i].div))
202− break;
203−
204− if (i >= clock->div_num)
205− return -EINVAL;
206−
207− clock->cur_div_idx = i;
208−
209− cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK | CPG_SD_FC_MASK,
210− clock->div_table[i].val &
211− (CPG_SD_STP_MASK | CPG_SD_FC_MASK));
212−
213− return 0;
98+ cpg_simple_notifier_register(notifiers, csn);
99+ return clk;
214100 }
215101
216−static const struct clk_ops cpg_sd_clock_ops = {
217− .enable = cpg_sd_clock_enable,
218− .disable = cpg_sd_clock_disable,
219− .is_enabled = cpg_sd_clock_is_enabled,
220− .recalc_rate = cpg_sd_clock_recalc_rate,
221− .determine_rate = cpg_sd_clock_determine_rate,
222− .set_rate = cpg_sd_clock_set_rate,
102+static const struct clk_div_table cpg_sd_div_table[] = {
103+ { 0, 2 }, { 1, 4 }, { 0, 0 },
223104 };
224105
225106 struct clk * __init cpg_sd_clk_register(const char *name,
226− void __iomem *base, unsigned int offset, const char *parent_name,
227− struct raw_notifier_head *notifiers, bool skip_first)
107+ void __iomem *sdnckcr, const char *parent_name)
228108 {
229− struct clk_init_data init = {};
230− struct sd_clock *clock;
231− struct clk *clk;
232− u32 val;
233−
234− clock = kzalloc(sizeof(*clock), GFP_KERNEL);
235− if (!clock)
236− return ERR_PTR(-ENOMEM);
237−
238− init.name = name;
239− init.ops = &cpg_sd_clock_ops;
240− init.flags = CLK_SET_RATE_PARENT;
241− init.parent_names = &parent_name;
242− init.num_parents = 1;
243−
244− clock->csn.reg = base + offset;
245− clock->hw.init = &init;
246− clock->div_table = cpg_sd_div_table;
247− clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
248−
249− if (skip_first) {
250− clock->div_table++;
251− clock->div_num--;
252− }
253−
254− val = readl(clock->csn.reg) & ~CPG_SD_FC_MASK;
255− val |= CPG_SD_STP_MASK | (clock->div_table[0].val & CPG_SD_FC_MASK);
256− writel(val, clock->csn.reg);
257−
258− clk = clk_register(NULL, &clock->hw);
259− if (IS_ERR(clk))
260− goto free_clock;
261−
262− cpg_simple_notifier_register(notifiers, &clock->csn);
263− return clk;
264−
265−free_clock:
266− kfree(clock);
267− return clk;
109+ return clk_register_divider_table(NULL, name, parent_name, 0, sdnckcr,
110+ 0, 2, 0, cpg_sd_div_table, &cpg_lock);
268111 }
269112
270113 struct rpc_clock {
drivers/clk/renesas/rcar-cpg-lib.h+5−2
@@ -26,9 +26,12 @@ void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, · 25 unmodified lines
2626
2727 void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set);
2828
29+struct clk * __init cpg_sdh_clk_register(const char *name,
30+ void __iomem *sdnckcr, const char *parent_name,
31+ struct raw_notifier_head *notifiers);
32+
2933 struct clk * __init cpg_sd_clk_register(const char *name,
30− void __iomem *base, unsigned int offset, const char *parent_name,
31− struct raw_notifier_head *notifiers, bool skip_first);
34+ void __iomem *sdnckcr, const char *parent_name);
3235
3336 struct clk * __init cpg_rpc_clk_register(const char *name,
3437 void __iomem *rpcckcr, const char *parent_name,
drivers/clk/renesas/rcar-gen3-cpg.c+9−15
@@ -312,29 +312,20 @@ static u32 cpg_quirks __initdata; · 311 unmodified lines
312312
313313 #define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */
314314 #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
315−#define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */
316315
317316
318317 static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
319318 {
320319 .soc_id = "r8a7795", .revision = "ES1.0",
321− .data = (void *)(PLL_ERRATA | RCKCR_CKSEL | SD_SKIP_FIRST),
320+ .data = (void *)(PLL_ERRATA | RCKCR_CKSEL),
322321 },
323322 {
324323 .soc_id = "r8a7795", .revision = "ES1.*",
325− .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST),
326− },
327− {
328− .soc_id = "r8a7795", .revision = "ES2.0",
329− .data = (void *)SD_SKIP_FIRST,
324+ .data = (void *)(RCKCR_CKSEL),
330325 },
331326 {
332327 .soc_id = "r8a7796", .revision = "ES1.0",
333− .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST),
334− },
335− {
336− .soc_id = "r8a7796", .revision = "ES1.1",
337− .data = (void *)SD_SKIP_FIRST,
328+ .data = (void *)(RCKCR_CKSEL),
338329 },
339330 { /* sentinel */ }
340331 };
@@ -401,10 +392,13 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, · 60 unmodified lines
401392 mult *= 2;
402393 break;
403394
395+ case CLK_TYPE_GEN3_SDH:
396+ return cpg_sdh_clk_register(core->name, base + core->offset,
397+ __clk_get_name(parent), notifiers);
398+
404399 case CLK_TYPE_GEN3_SD:
405− return cpg_sd_clk_register(core->name, base, core->offset,
406− __clk_get_name(parent), notifiers,
407− cpg_quirks & SD_SKIP_FIRST);
400+ return cpg_sd_clk_register(core->name, base + core->offset,
401+ __clk_get_name(parent));
408402
409403 case CLK_TYPE_GEN3_R:
410404 if (cpg_quirks & RCKCR_CKSEL) {
drivers/clk/renesas/rcar-gen3-cpg.h+4−0
@@ -17,6 +17,7 @@ enum rcar_gen3_clk_types { · 16 unmodified lines
1717 CLK_TYPE_GEN3_PLL2,
1818 CLK_TYPE_GEN3_PLL3,
1919 CLK_TYPE_GEN3_PLL4,
20+ CLK_TYPE_GEN3_SDH,
2021 CLK_TYPE_GEN3_SD,
2122 CLK_TYPE_GEN3_R,
2223 CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
@@ -32,6 +33,9 @@ enum rcar_gen3_clk_types { · 9 unmodified lines
3233 CLK_TYPE_GEN3_SOC_BASE,
3334 };
3435
36+#define DEF_GEN3_SDH(_name, _id, _parent, _offset) \
37+ DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset)
38+
3539 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \
3640 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
3741
drivers/clk/renesas/rcar-gen4-cpg.c+305−0
@@ -0,0 +1,305 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * R-Car Gen4 Clock Pulse Generator
4+ *
5+ * Copyright (C) 2021 Renesas Electronics Corp.
6+ *
7+ * Based on rcar-gen3-cpg.c
8+ *
9+ * Copyright (C) 2015-2018 Glider bvba
10+ * Copyright (C) 2019 Renesas Electronics Corp.
11+ */
12+
13+#include <linux/bitfield.h>
14+#include <linux/clk.h>
15+#include <linux/clk-provider.h>
16+#include <linux/device.h>
17+#include <linux/err.h>
18+#include <linux/init.h>
19+#include <linux/io.h>
20+#include <linux/slab.h>
21+
22+#include "renesas-cpg-mssr.h"
23+#include "rcar-gen4-cpg.h"
24+#include "rcar-cpg-lib.h"
25+
26+static const struct rcar_gen4_cpg_pll_config *cpg_pll_config __initconst;
27+static unsigned int cpg_clk_extalr __initdata;
28+static u32 cpg_mode __initdata;
29+
30+/*
31+ * Z0 Clock & Z1 Clock
32+ */
33+#define CPG_FRQCRB 0x00000804
34+#define CPG_FRQCRB_KICK BIT(31)
35+#define CPG_FRQCRC 0x00000808
36+
37+struct cpg_z_clk {
38+ struct clk_hw hw;
39+ void __iomem *reg;
40+ void __iomem *kick_reg;
41+ unsigned long max_rate; /* Maximum rate for normal mode */
42+ unsigned int fixed_div;
43+ u32 mask;
44+};
45+
46+#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
47+
48+static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
49+ unsigned long parent_rate)
50+{
51+ struct cpg_z_clk *zclk = to_z_clk(hw);
52+ unsigned int mult;
53+ u32 val;
54+
55+ val = readl(zclk->reg) & zclk->mask;
56+ mult = 32 - (val >> __ffs(zclk->mask));
57+
58+ return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,
59+ 32 * zclk->fixed_div);
60+}
61+
62+static int cpg_z_clk_determine_rate(struct clk_hw *hw,
63+ struct clk_rate_request *req)
64+{
65+ struct cpg_z_clk *zclk = to_z_clk(hw);
66+ unsigned int min_mult, max_mult, mult;
67+ unsigned long rate, prate;
68+
69+ rate = min(req->rate, req->max_rate);
70+ if (rate <= zclk->max_rate) {
71+ /* Set parent rate to initial value for normal modes */
72+ prate = zclk->max_rate;
73+ } else {
74+ /* Set increased parent rate for boost modes */
75+ prate = rate;
76+ }
77+ req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
78+ prate * zclk->fixed_div);
79+
80+ prate = req->best_parent_rate / zclk->fixed_div;
81+ min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
82+ max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);
83+ if (max_mult < min_mult)
84+ return -EINVAL;
85+
86+ mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate);
87+ mult = clamp(mult, min_mult, max_mult);
88+
89+ req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);
90+ return 0;
91+}
92+
93+static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
94+ unsigned long parent_rate)
95+{
96+ struct cpg_z_clk *zclk = to_z_clk(hw);
97+ unsigned int mult;
98+ unsigned int i;
99+
100+ mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,
101+ parent_rate);
102+ mult = clamp(mult, 1U, 32U);
103+
104+ if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
105+ return -EBUSY;
106+
107+ cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask));
108+
109+ /*
110+ * Set KICK bit in FRQCRB to update hardware setting and wait for
111+ * clock change completion.
112+ */
113+ cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK);
114+
115+ /*
116+ * Note: There is no HW information about the worst case latency.
117+ *
118+ * Using experimental measurements, it seems that no more than
119+ * ~10 iterations are needed, independently of the CPU rate.
120+ * Since this value might be dependent on external xtal rate, pll1
121+ * rate or even the other emulation clocks rate, use 1000 as a
122+ * "super" safe value.
123+ */
124+ for (i = 1000; i; i--) {
125+ if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
126+ return 0;
127+
128+ cpu_relax();
129+ }
130+
131+ return -ETIMEDOUT;
132+}
133+
134+static const struct clk_ops cpg_z_clk_ops = {
135+ .recalc_rate = cpg_z_clk_recalc_rate,
136+ .determine_rate = cpg_z_clk_determine_rate,
137+ .set_rate = cpg_z_clk_set_rate,
138+};
139+
140+static struct clk * __init cpg_z_clk_register(const char *name,
141+ const char *parent_name,
142+ void __iomem *reg,
143+ unsigned int div,
144+ unsigned int offset)
145+{
146+ struct clk_init_data init = {};
147+ struct cpg_z_clk *zclk;
148+ struct clk *clk;
149+
150+ zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
151+ if (!zclk)
152+ return ERR_PTR(-ENOMEM);
153+
154+ init.name = name;
155+ init.ops = &cpg_z_clk_ops;
156+ init.flags = CLK_SET_RATE_PARENT;
157+ init.parent_names = &parent_name;
158+ init.num_parents = 1;
159+
160+ zclk->reg = reg + CPG_FRQCRC;
161+ zclk->kick_reg = reg + CPG_FRQCRB;
162+ zclk->hw.init = &init;
163+ zclk->mask = GENMASK(offset + 4, offset);
164+ zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
165+
166+ clk = clk_register(NULL, &zclk->hw);
167+ if (IS_ERR(clk)) {
168+ kfree(zclk);
169+ return clk;
170+ }
171+
172+ zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) /
173+ zclk->fixed_div;
174+ return clk;
175+}
176+
177+/*
178+ * RPC Clocks
179+ */
180+static const struct clk_div_table cpg_rpcsrc_div_table[] = {
181+ { 0, 4 }, { 1, 6 }, { 2, 5 }, { 3, 6 }, { 0, 0 },
182+};
183+
184+struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
185+ const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
186+ struct clk **clks, void __iomem *base,
187+ struct raw_notifier_head *notifiers)
188+{
189+ const struct clk *parent;
190+ unsigned int mult = 1;
191+ unsigned int div = 1;
192+ u32 value;
193+
194+ parent = clks[core->parent & 0xffff]; /* some types use high bits */
195+ if (IS_ERR(parent))
196+ return ERR_CAST(parent);
197+
198+ switch (core->type) {
199+ case CLK_TYPE_GEN4_MAIN:
200+ div = cpg_pll_config->extal_div;
201+ break;
202+
203+ case CLK_TYPE_GEN4_PLL1:
204+ mult = cpg_pll_config->pll1_mult;
205+ div = cpg_pll_config->pll1_div;
206+ break;
207+
208+ case CLK_TYPE_GEN4_PLL2:
209+ mult = cpg_pll_config->pll2_mult;
210+ div = cpg_pll_config->pll2_div;
211+ break;
212+
213+ case CLK_TYPE_GEN4_PLL3:
214+ mult = cpg_pll_config->pll3_mult;
215+ div = cpg_pll_config->pll3_div;
216+ break;
217+
218+ case CLK_TYPE_GEN4_PLL5:
219+ mult = cpg_pll_config->pll5_mult;
220+ div = cpg_pll_config->pll5_div;
221+ break;
222+
223+ case CLK_TYPE_GEN4_PLL6:
224+ mult = cpg_pll_config->pll6_mult;
225+ div = cpg_pll_config->pll6_div;
226+ break;
227+
228+ case CLK_TYPE_GEN4_PLL2X_3X:
229+ value = readl(base + core->offset);
230+ mult = (((value >> 24) & 0x7f) + 1) * 2;
231+ break;
232+
233+ case CLK_TYPE_GEN4_Z:
234+ return cpg_z_clk_register(core->name, __clk_get_name(parent),
235+ base, core->div, core->offset);
236+
237+ case CLK_TYPE_GEN4_SDSRC:
238+ div = ((readl(base + SD0CKCR1) >> 29) & 0x03) + 4;
239+ break;
240+
241+ case CLK_TYPE_GEN4_SDH:
242+ return cpg_sdh_clk_register(core->name, base + core->offset,
243+ __clk_get_name(parent), notifiers);
244+
245+ case CLK_TYPE_GEN4_SD:
246+ return cpg_sd_clk_register(core->name, base + core->offset,
247+ __clk_get_name(parent));
248+
249+ case CLK_TYPE_GEN4_MDSEL:
250+ /*
251+ * Clock selectable between two parents and two fixed dividers
252+ * using a mode pin
253+ */
254+ if (cpg_mode & BIT(core->offset)) {
255+ div = core->div & 0xffff;
256+ } else {
257+ parent = clks[core->parent >> 16];
258+ if (IS_ERR(parent))
259+ return ERR_CAST(parent);
260+ div = core->div >> 16;
261+ }
262+ mult = 1;
263+ break;
264+
265+ case CLK_TYPE_GEN4_OSC:
266+ /*
267+ * Clock combining OSC EXTAL predivider and a fixed divider
268+ */
269+ div = cpg_pll_config->osc_prediv * core->div;
270+ break;
271+
272+ case CLK_TYPE_GEN4_RPCSRC:
273+ return clk_register_divider_table(NULL, core->name,
274+ __clk_get_name(parent), 0,
275+ base + CPG_RPCCKCR, 3, 2, 0,
276+ cpg_rpcsrc_div_table,
277+ &cpg_lock);
278+
279+ case CLK_TYPE_GEN4_RPC:
280+ return cpg_rpc_clk_register(core->name, base + CPG_RPCCKCR,
281+ __clk_get_name(parent), notifiers);
282+
283+ case CLK_TYPE_GEN4_RPCD2:
284+ return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR,
285+ __clk_get_name(parent));
286+
287+ default:
288+ return ERR_PTR(-EINVAL);
289+ }
290+
291+ return clk_register_fixed_factor(NULL, core->name,
292+ __clk_get_name(parent), 0, mult, div);
293+}
294+
295+int __init rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config,
296+ unsigned int clk_extalr, u32 mode)
297+{
298+ cpg_pll_config = config;
299+ cpg_clk_extalr = clk_extalr;
300+ cpg_mode = mode;
301+
302+ spin_lock_init(&cpg_lock);
303+
304+ return 0;
305+}
drivers/clk/renesas/rcar-gen4-cpg.h+76−0
@@ -0,0 +1,76 @@
1+/* SPDX-License-Identifier: GPL-2.0 */
2+/*
3+ * R-Car Gen4 Clock Pulse Generator
4+ *
5+ * Copyright (C) 2021 Renesas Electronics Corp.
6+ *
7+ */
8+
9+#ifndef __CLK_RENESAS_RCAR_GEN4_CPG_H__
10+#define __CLK_RENESAS_RCAR_GEN4_CPG_H__
11+
12+enum rcar_gen4_clk_types {
13+ CLK_TYPE_GEN4_MAIN = CLK_TYPE_CUSTOM,
14+ CLK_TYPE_GEN4_PLL1,
15+ CLK_TYPE_GEN4_PLL2,
16+ CLK_TYPE_GEN4_PLL2X_3X, /* r8a779a0 only */
17+ CLK_TYPE_GEN4_PLL3,
18+ CLK_TYPE_GEN4_PLL5,
19+ CLK_TYPE_GEN4_PLL6,
20+ CLK_TYPE_GEN4_SDSRC,
21+ CLK_TYPE_GEN4_SDH,
22+ CLK_TYPE_GEN4_SD,
23+ CLK_TYPE_GEN4_MDSEL, /* Select parent/divider using mode pin */
24+ CLK_TYPE_GEN4_Z,
25+ CLK_TYPE_GEN4_OSC, /* OSC EXTAL predivider and fixed divider */
26+ CLK_TYPE_GEN4_RPCSRC,
27+ CLK_TYPE_GEN4_RPC,
28+ CLK_TYPE_GEN4_RPCD2,
29+
30+ /* SoC specific definitions start here */
31+ CLK_TYPE_GEN4_SOC_BASE,
32+};
33+
34+#define DEF_GEN4_SDH(_name, _id, _parent, _offset) \
35+ DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
36+
37+#define DEF_GEN4_SD(_name, _id, _parent, _offset) \
38+ DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
39+
40+#define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
41+ DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \
42+ (_parent0) << 16 | (_parent1), \
43+ .div = (_div0) << 16 | (_div1), .offset = _md)
44+
45+#define DEF_GEN4_OSC(_name, _id, _parent, _div) \
46+ DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
47+
48+#define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \
49+ DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
50+
51+struct rcar_gen4_cpg_pll_config {
52+ u8 extal_div;
53+ u8 pll1_mult;
54+ u8 pll1_div;
55+ u8 pll2_mult;
56+ u8 pll2_div;
57+ u8 pll3_mult;
58+ u8 pll3_div;
59+ u8 pll5_mult;
60+ u8 pll5_div;
61+ u8 pll6_mult;
62+ u8 pll6_div;
63+ u8 osc_prediv;
64+};
65+
66+#define CPG_RPCCKCR 0x874
67+#define SD0CKCR1 0x8a4
68+
69+struct clk *rcar_gen4_cpg_clk_register(struct device *dev,
70+ const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
71+ struct clk **clks, void __iomem *base,
72+ struct raw_notifier_head *notifiers);
73+int rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config,
74+ unsigned int clk_extalr, u32 mode);
75+
76+#endif
drivers/clk/renesas/renesas-cpg-mssr.c+43−17
@@ -57,9 +57,11 @@ static const u16 mstpsr[] = { · 56 unmodified lines
5757 0x9A0, 0x9A4, 0x9A8, 0x9AC,
5858 };
5959
60−static const u16 mstpsr_for_v3u[] = {
60+static const u16 mstpsr_for_gen4[] = {
6161 0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
62− 0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38,
62+ 0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38, 0x2E3C,
63+ 0x2E40, 0x2E44, 0x2E48, 0x2E4C, 0x2E50, 0x2E54, 0x2E58, 0x2E5C,
64+ 0x2E60, 0x2E64, 0x2E68, 0x2E6C,
6365 };
6466
6567 /*
@@ -71,9 +73,11 @@ static const u16 smstpcr[] = { · 5 unmodified lines
7173 0x990, 0x994, 0x998, 0x99C,
7274 };
7375
74−static const u16 mstpcr_for_v3u[] = {
76+static const u16 mstpcr_for_gen4[] = {
7577 0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
76− 0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38,
78+ 0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38, 0x2D3C,
79+ 0x2D40, 0x2D44, 0x2D48, 0x2D4C, 0x2D50, 0x2D54, 0x2D58, 0x2D5C,
80+ 0x2D60, 0x2D64, 0x2D68, 0x2D6C,
7781 };
7882
7983 /*
@@ -95,9 +99,11 @@ static const u16 srcr[] = { · 15 unmodified lines
9599 0x920, 0x924, 0x928, 0x92C,
96100 };
97101
98−static const u16 srcr_for_v3u[] = {
102+static const u16 srcr_for_gen4[] = {
99103 0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C,
100− 0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38,
104+ 0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, 0x2C3C,
105+ 0x2C40, 0x2C44, 0x2C48, 0x2C4C, 0x2C50, 0x2C54, 0x2C58, 0x2C5C,
106+ 0x2C60, 0x2C64, 0x2C68, 0x2C6C,
101107 };
102108
103109 /*
@@ -109,9 +115,11 @@ static const u16 srstclr[] = { · 5 unmodified lines
109115 0x960, 0x964, 0x968, 0x96C,
110116 };
111117
112−static const u16 srstclr_for_v3u[] = {
118+static const u16 srstclr_for_gen4[] = {
113119 0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C,
114− 0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8,
120+ 0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8, 0x2CBC,
121+ 0x2CC0, 0x2CC4, 0x2CC8, 0x2CCC, 0x2CD0, 0x2CD4, 0x2CD8, 0x2CDC,
122+ 0x2CE0, 0x2CE4, 0x2CE8, 0x2CEC,
115123 };
116124
117125 /**
@@ -158,7 +166,7 @@ struct cpg_mssr_priv { · 40 unmodified lines
158166 struct {
159167 u32 mask;
160168 u32 val;
161− } smstpcr_saved[ARRAY_SIZE(mstpsr_for_v3u)];
169+ } smstpcr_saved[ARRAY_SIZE(mstpsr_for_gen4)];
162170
163171 struct clk *clks[];
164172 };
@@ -552,6 +560,11 @@ void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev) · 387 unmodified lines
552560 pm_clk_destroy(dev);
553561 }
554562
563+static void cpg_mssr_genpd_remove(void *data)
564+{
565+ pm_genpd_remove(data);
566+}
567+
555568 static int __init cpg_mssr_add_clk_domain(struct device *dev,
556569 const unsigned int *core_pm_clks,
557570 unsigned int num_core_pm_clks)
@@ -560,6 +573,7 @@ static int __init cpg_mssr_add_clk_domain(struct device *dev, · 2 unmodified lines
560573 struct generic_pm_domain *genpd;
561574 struct cpg_mssr_clk_domain *pd;
562575 size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
576+ int ret;
563577
564578 pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL);
565579 if (!pd)
@@ -574,11 +588,17 @@ static int __init cpg_mssr_add_clk_domain(struct device *dev, · 8 unmodified lines
574588 GENPD_FLAG_ACTIVE_WAKEUP;
575589 genpd->attach_dev = cpg_mssr_attach_dev;
576590 genpd->detach_dev = cpg_mssr_detach_dev;
577− pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
591+ ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
592+ if (ret)
593+ return ret;
594+
595+ ret = devm_add_action_or_reset(dev, cpg_mssr_genpd_remove, genpd);
596+ if (ret)
597+ return ret;
598+
578599 cpg_mssr_clk_domain = pd;
579600
580− of_genpd_add_provider_simple(np, genpd);
581− return 0;
601+ return of_genpd_add_provider_simple(np, genpd);
582602 }
583603
584604 #ifdef CONFIG_RESET_CONTROLLER
@@ -827,6 +847,12 @@ static const struct of_device_id cpg_mssr_match[] = { · 242 unmodified lines
827847 .compatible = "renesas,r8a779a0-cpg-mssr",
828848 .data = &r8a779a0_cpg_mssr_info,
829849 },
850+#endif
851+#ifdef CONFIG_CLK_R8A779F0
852+ {
853+ .compatible = "renesas,r8a779f0-cpg-mssr",
854+ .data = &r8a779f0_cpg_mssr_info,
855+ },
830856 #endif
831857 { /* sentinel */ }
832858 };
@@ -970,11 +996,11 @@ static int __init cpg_mssr_common_init(struct device *dev, · 137 unmodified lines
970996 priv->reset_clear_regs = srstclr;
971997 } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
972998 priv->control_regs = stbcr;
973− } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) {
974− priv->status_regs = mstpsr_for_v3u;
975− priv->control_regs = mstpcr_for_v3u;
976− priv->reset_regs = srcr_for_v3u;
977− priv->reset_clear_regs = srstclr_for_v3u;
999+ } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) {
1000+ priv->status_regs = mstpsr_for_gen4;
1001+ priv->control_regs = mstpcr_for_gen4;
1002+ priv->reset_regs = srcr_for_gen4;
1003+ priv->reset_clear_regs = srstclr_for_gen4;
9781004 } else {
9791005 error = -EINVAL;
9801006 goto out_err;
drivers/clk/renesas/renesas-cpg-mssr.h+2−1
@@ -88,7 +88,7 @@ struct device_node; · 87 unmodified lines
8888 enum clk_reg_layout {
8989 CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,
9090 CLK_REG_LAYOUT_RZ_A,
91− CLK_REG_LAYOUT_RCAR_V3U,
91+ CLK_REG_LAYOUT_RCAR_GEN4,
9292 };
9393
9494 /**
@@ -178,6 +178,7 @@ extern const struct cpg_mssr_info r8a77980_cpg_mssr_info; · 83 unmodified lines
178178 extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
179179 extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
180180 extern const struct cpg_mssr_info r8a779a0_cpg_mssr_info;
181+extern const struct cpg_mssr_info r8a779f0_cpg_mssr_info;
181182
182183 void __init cpg_mssr_early_init(struct device_node *np,
183184 const struct cpg_mssr_info *info);
drivers/clk/renesas/rzg2l-cpg.c+15−3
@@ -74,6 +74,7 @@ struct sd_hw_data { · 73 unmodified lines
7474 * @clks: Array containing all Core and Module Clocks
7575 * @num_core_clks: Number of Core Clocks in clks[]
7676 * @num_mod_clks: Number of Module Clocks in clks[]
77+ * @num_resets: Number of Module Resets in info->resets[]
7778 * @last_dt_core_clk: ID of the last Core Clock exported to DT
7879 * @notifiers: Notifier chain to save/restore clock state for system resume
7980 * @info: Pointer to platform data
@@ -850,10 +851,16 @@ static void rzg2l_cpg_detach_dev(struct generic_pm_domain *unused, struct device · 770 unmodified lines
850851 pm_clk_destroy(dev);
851852 }
852853
854+static void rzg2l_cpg_genpd_remove(void *data)
855+{
856+ pm_genpd_remove(data);
857+}
858+
853859 static int __init rzg2l_cpg_add_clk_domain(struct device *dev)
854860 {
855861 struct device_node *np = dev->of_node;
856862 struct generic_pm_domain *genpd;
863+ int ret;
857864
858865 genpd = devm_kzalloc(dev, sizeof(*genpd), GFP_KERNEL);
859866 if (!genpd)
@@ -864,10 +871,15 @@ static int __init rzg2l_cpg_add_clk_domain(struct device *dev) · 4 unmodified lines
864871 GENPD_FLAG_ACTIVE_WAKEUP;
865872 genpd->attach_dev = rzg2l_cpg_attach_dev;
866873 genpd->detach_dev = rzg2l_cpg_detach_dev;
867− pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
874+ ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
875+ if (ret)
876+ return ret;
868877
869− of_genpd_add_provider_simple(np, genpd);
870− return 0;
878+ ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, genpd);
879+ if (ret)
880+ return ret;
881+
882+ return of_genpd_add_provider_simple(np, genpd);
871883 }
872884
873885 static int __init rzg2l_cpg_probe(struct platform_device *pdev)
drivers/clk/renesas/rzg2l-cpg.h+9−0
@@ -9,11 +9,14 @@ · 8 unmodified lines
99 #ifndef __RENESAS_RZG2L_CPG_H__
1010 #define __RENESAS_RZG2L_CPG_H__
1111
12+#define CPG_PL1_DDIV (0x200)
1213 #define CPG_PL2_DDIV (0x204)
1314 #define CPG_PL3A_DDIV (0x208)
15+#define CPG_PL6_DDIV (0x210)
1416 #define CPG_PL2SDHI_DSEL (0x218)
1517 #define CPG_CLKSTATUS (0x280)
1618 #define CPG_PL3_SSEL (0x408)
19+#define CPG_PL6_SSEL (0x414)
1720 #define CPG_PL6_ETH_SSEL (0x418)
1821
1922 #define CPG_CLKSTATUS_SELSDHI0_STS BIT(28)
@@ -29,16 +32,19 @@ · 9 unmodified lines
2932
3033 #define DDIV_PACK(offset, bitpos, size) \
3134 (((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
35+#define DIVPL1A DDIV_PACK(CPG_PL1_DDIV, 0, 2)
3236 #define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3)
3337 #define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3)
3438 #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3)
3539 #define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3)
40+#define DIVGPU DDIV_PACK(CPG_PL6_DDIV, 0, 2)
3641
3742 #define SEL_PLL_PACK(offset, bitpos, size) \
3843 (((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
3944
4045 #define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1)
4146 #define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1)
47+#define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1)
4248
4349 #define SEL_SDHI0 DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2)
4450 #define SEL_SDHI1 DDIV_PACK(CPG_PL2SDHI_DSEL, 4, 2)
@@ -168,6 +174,9 @@ struct rzg2l_reset { · 123 unmodified lines
168174 * @num_mod_clks: Number of entries in mod_clks[]
169175 * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
170176 *
177+ * @resets: Array of Module Reset definitions
178+ * @num_resets: Number of entries in resets[]
179+ *
171180 * @crit_mod_clks: Array with Module Clock IDs of critical clocks that
172181 * should not be disabled without a knowledgeable driver
173182 * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
drivers/clk/samsung/Makefile+2−0
@@ -16,7 +16,9 @@ obj-$(CONFIG_EXYNOS_5420_COMMON_CLK) += clk-exynos5-subcmu.o · 15 unmodified lines
1616 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o
1717 obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o
1818 obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o
19+obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos-arm64.o
1920 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
21+obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o
2022 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
2123 obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
2224 obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
drivers/clk/samsung/clk-cpu.c+1−1
@@ -400,7 +400,7 @@ static int exynos5433_cpuclk_notifier_cb(struct notifier_block *nb, · 399 unmodified lines
400400 }
401401
402402 /* helper function to register a CPU clock */
403−int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
403+static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
404404 unsigned int lookup_id, const char *name,
405405 const struct clk_hw *parent, const struct clk_hw *alt_parent,
406406 unsigned long offset, const struct exynos_cpuclk_cfg_data *cfg,
drivers/clk/samsung/clk-cpu.h+0−7
@@ -62,11 +62,4 @@ struct exynos_cpuclk { · 61 unmodified lines
6262 #define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2)
6363 };
6464
65−int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
66− unsigned int lookup_id, const char *name,
67− const struct clk_hw *parent, const struct clk_hw *alt_parent,
68− unsigned long offset,
69− const struct exynos_cpuclk_cfg_data *cfg,
70− unsigned long num_cfgs, unsigned long flags);
71−
7265 #endif /* __SAMSUNG_CLK_CPU_H */
drivers/clk/samsung/clk-exynos-arm64.c+94−0
@@ -0,0 +1,94 @@
1+// SPDX-License-Identifier: GPL-2.0-only
2+/*
3+ * Copyright (C) 2021 Linaro Ltd.
4+ * Copyright (C) 2021 Dávid Virág <virag.david003@gmail.com>
5+ * Author: Sam Protsenko <semen.protsenko@linaro.org>
6+ * Author: Dávid Virág <virag.david003@gmail.com>
7+ *
8+ * This file contains shared functions used by some arm64 Exynos SoCs,
9+ * such as Exynos7885 or Exynos850 to register and init CMUs.
10+ */
11+#include <linux/clk.h>
12+#include <linux/of_address.h>
13+
14+#include "clk-exynos-arm64.h"
15+
16+/* Gate register bits */
17+#define GATE_MANUAL BIT(20)
18+#define GATE_ENABLE_HWACG BIT(28)
19+
20+/* Gate register offsets range */
21+#define GATE_OFF_START 0x2000
22+#define GATE_OFF_END 0x2fff
23+
24+/**
25+ * exynos_arm64_init_clocks - Set clocks initial configuration
26+ * @np: CMU device tree node with "reg" property (CMU addr)
27+ * @reg_offs: Register offsets array for clocks to init
28+ * @reg_offs_len: Number of register offsets in reg_offs array
29+ *
30+ * Set manual control mode for all gate clocks.
31+ */
32+static void __init exynos_arm64_init_clocks(struct device_node *np,
33+ const unsigned long *reg_offs, size_t reg_offs_len)
34+{
35+ void __iomem *reg_base;
36+ size_t i;
37+
38+ reg_base = of_iomap(np, 0);
39+ if (!reg_base)
40+ panic("%s: failed to map registers\n", __func__);
41+
42+ for (i = 0; i < reg_offs_len; ++i) {
43+ void __iomem *reg = reg_base + reg_offs[i];
44+ u32 val;
45+
46+ /* Modify only gate clock registers */
47+ if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END)
48+ continue;
49+
50+ val = readl(reg);
51+ val |= GATE_MANUAL;
52+ val &= ~GATE_ENABLE_HWACG;
53+ writel(val, reg);
54+ }
55+
56+ iounmap(reg_base);
57+}
58+
59+/**
60+ * exynos_arm64_register_cmu - Register specified Exynos CMU domain
61+ * @dev: Device object; may be NULL if this function is not being
62+ * called from platform driver probe function
63+ * @np: CMU device tree node
64+ * @cmu: CMU data
65+ *
66+ * Register specified CMU domain, which includes next steps:
67+ *
68+ * 1. Enable parent clock of @cmu CMU
69+ * 2. Set initial registers configuration for @cmu CMU clocks
70+ * 3. Register @cmu CMU clocks using Samsung clock framework API
71+ */
72+void __init exynos_arm64_register_cmu(struct device *dev,
73+ struct device_node *np, const struct samsung_cmu_info *cmu)
74+{
75+ /* Keep CMU parent clock running (needed for CMU registers access) */
76+ if (cmu->clk_name) {
77+ struct clk *parent_clk;
78+
79+ if (dev)
80+ parent_clk = clk_get(dev, cmu->clk_name);
81+ else
82+ parent_clk = of_clk_get_by_name(np, cmu->clk_name);
83+
84+ if (IS_ERR(parent_clk)) {
85+ pr_err("%s: could not find bus clock %s; err = %ld\n",
86+ __func__, cmu->clk_name, PTR_ERR(parent_clk));
87+ } else {
88+ clk_prepare_enable(parent_clk);
89+ }
90+ }
91+
92+ exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
93+ samsung_cmu_register_one(np, cmu);
94+}
drivers/clk/samsung/clk-exynos-arm64.h+20−0
@@ -0,0 +1,20 @@
1+/* SPDX-License-Identifier: GPL-2.0-only */
2+/*
3+ * Copyright (C) 2021 Linaro Ltd.
4+ * Copyright (C) 2021 Dávid Virág <virag.david003@gmail.com>
5+ * Author: Sam Protsenko <semen.protsenko@linaro.org>
6+ * Author: Dávid Virág <virag.david003@gmail.com>
7+ *
8+ * This file contains shared functions used by some arm64 Exynos SoCs,
9+ * such as Exynos7885 or Exynos850 to register and init CMUs.
10+ */
11+
12+#ifndef __CLK_EXYNOS_ARM64_H
13+#define __CLK_EXYNOS_ARM64_H
14+
15+#include "clk.h"
16+
17+void exynos_arm64_register_cmu(struct device *dev,
18+ struct device_node *np, const struct samsung_cmu_info *cmu);
19+
20+#endif /* __CLK_EXYNOS_ARM64_H */
drivers/clk/samsung/clk-exynos3250.c+27−27
@@ -748,6 +748,31 @@ static const struct samsung_pll_clock exynos3250_plls[] __initconst = { · 747 unmodified lines
748748 UPLL_LOCK, UPLL_CON0, exynos3250_pll_rates),
749749 };
750750
751+#define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) \
752+ (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
753+ ((corem) << 4))
754+#define E3250_CPU_DIV1(hpm, copy) \
755+ (((hpm) << 4) | ((copy) << 0))
756+
757+static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {
758+ { 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), },
759+ { 900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
760+ { 800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
761+ { 700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
762+ { 600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
763+ { 500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
764+ { 400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
765+ { 300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), },
766+ { 200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), },
767+ { 100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), },
768+ { 0 },
769+};
770+
771+static const struct samsung_cpu_clock exynos3250_cpu_clks[] __initconst = {
772+ CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
773+ CLK_CPU_HAS_DIV1, 0x14200, e3250_armclk_d),
774+};
775+
751776 static void __init exynos3_core_down_clock(void __iomem *reg_base)
752777 {
753778 unsigned int tmp;
@@ -780,46 +805,21 @@ static const struct samsung_cmu_info cmu_info __initconst = { · 26 unmodified lines
780805 .nr_gate_clks = ARRAY_SIZE(gate_clks),
781806 .fixed_factor_clks = fixed_factor_clks,
782807 .nr_fixed_factor_clks = ARRAY_SIZE(fixed_factor_clks),
808+ .cpu_clks = exynos3250_cpu_clks,
809+ .nr_cpu_clks = ARRAY_SIZE(exynos3250_cpu_clks),
783810 .nr_clk_ids = CLK_NR_CLKS,
784811 .clk_regs = exynos3250_cmu_clk_regs,
785812 .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs),
786813 };
787814
788−#define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) \
789− (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
790− ((corem) << 4))
791−#define E3250_CPU_DIV1(hpm, copy) \
792− (((hpm) << 4) | ((copy) << 0))
793−
794−static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {
795− { 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), },
796− { 900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
797− { 800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
798− { 700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
799− { 600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
800− { 500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
801− { 400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
802− { 300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), },
803− { 200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), },
804− { 100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), },
805− { 0 },
806−};
807−
808815 static void __init exynos3250_cmu_init(struct device_node *np)
809816 {
810817 struct samsung_clk_provider *ctx;
811− struct clk_hw **hws;
812818
813819 ctx = samsung_cmu_register_one(np, &cmu_info);
814820 if (!ctx)
815821 return;
816822
817− hws = ctx->clk_data.hws;
818− exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
819− hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL_USER_C],
820− 0x14200, e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d),
821− CLK_CPU_HAS_DIV1);
822−
823823 exynos3_core_down_clock(ctx->reg_base);
824824 }
825825 CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
drivers/clk/samsung/clk-exynos4.c+24−17
@@ -437,7 +437,7 @@ static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = { · 436 unmodified lines
437437
438438 /* list of mux clocks supported in exynos4210 soc */
439439 static const struct samsung_mux_clock exynos4210_mux_early[] __initconst = {
440− MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
440+ MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
441441 };
442442
443443 static const struct samsung_mux_clock exynos4210_mux_clks[] __initconst = {
@@ -603,7 +603,7 @@ static const struct samsung_div_clock exynos4_div_clks[] __initconst = { · 159 unmodified lines
603603 DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
604604 DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
605605 DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
606− DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
606+ DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
607607 DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
608608 DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
609609 DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
@@ -1228,6 +1228,16 @@ static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = { · 618 unmodified lines
12281228 { 0 },
12291229 };
12301230
1231+static const struct samsung_cpu_clock exynos4210_cpu_clks[] __initconst = {
1232+ CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_SCLK_MPLL,
1233+ CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4210_armclk_d),
1234+};
1235+
1236+static const struct samsung_cpu_clock exynos4412_cpu_clks[] __initconst = {
1237+ CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
1238+ CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4412_armclk_d),
1239+};
1240+
12311241 /* register exynos4 clocks */
12321242 static void __init exynos4_clk_init(struct device_node *np,
12331243 enum exynos4_soc soc)
@@ -1254,21 +1264,21 @@ static void __init exynos4_clk_init(struct device_node *np, · 20 unmodified lines
12541264 samsung_clk_register_mux(ctx, exynos4210_mux_early,
12551265 ARRAY_SIZE(exynos4210_mux_early));
12561266
1257− if (_get_rate("fin_pll") == 24000000) {
1267+ if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) {
12581268 exynos4210_plls[apll].rate_table =
12591269 exynos4210_apll_rates;
12601270 exynos4210_plls[epll].rate_table =
12611271 exynos4210_epll_rates;
12621272 }
12631273
1264− if (_get_rate("mout_vpllsrc") == 24000000)
1274+ if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24000000)
12651275 exynos4210_plls[vpll].rate_table =
12661276 exynos4210_vpll_rates;
12671277
12681278 samsung_clk_register_pll(ctx, exynos4210_plls,
12691279 ARRAY_SIZE(exynos4210_plls), reg_base);
12701280 } else {
1271− if (_get_rate("fin_pll") == 24000000) {
1281+ if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) {
12721282 exynos4x12_plls[apll].rate_table =
12731283 exynos4x12_apll_rates;
12741284 exynos4x12_plls[epll].rate_table =
@@ -1304,10 +1314,8 @@ static void __init exynos4_clk_init(struct device_node *np, · 29 unmodified lines
13041314 samsung_clk_register_fixed_factor(ctx,
13051315 exynos4210_fixed_factor_clks,
13061316 ARRAY_SIZE(exynos4210_fixed_factor_clks));
1307− exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1308− hws[CLK_MOUT_APLL], hws[CLK_SCLK_MPLL], 0x14200,
1309− e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
1310− CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
1317+ samsung_clk_register_cpu(ctx, exynos4210_cpu_clks,
1318+ ARRAY_SIZE(exynos4210_cpu_clks));
13111319 } else {
13121320 samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
13131321 ARRAY_SIZE(exynos4x12_mux_clks));
@@ -1318,11 +1326,8 @@ static void __init exynos4_clk_init(struct device_node *np, · 4 unmodified lines
13181326 samsung_clk_register_fixed_factor(ctx,
13191327 exynos4x12_fixed_factor_clks,
13201328 ARRAY_SIZE(exynos4x12_fixed_factor_clks));
1321−
1322− exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1323− hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL_USER_C], 0x14200,
1324− e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
1325− CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
1329+ samsung_clk_register_cpu(ctx, exynos4412_cpu_clks,
1330+ ARRAY_SIZE(exynos4412_cpu_clks));
13261331 }
13271332
13281333 if (soc == EXYNOS4X12)
@@ -1344,9 +1349,11 @@ static void __init exynos4_clk_init(struct device_node *np, · 15 unmodified lines
13441349 pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
13451350 "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
13461351 exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
1347− _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
1348− _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
1349− _get_rate("div_core2"));
1352+ clk_hw_get_rate(hws[CLK_SCLK_APLL]),
1353+ clk_hw_get_rate(hws[CLK_SCLK_MPLL]),
1354+ clk_hw_get_rate(hws[CLK_SCLK_EPLL]),
1355+ clk_hw_get_rate(hws[CLK_SCLK_VPLL]),
1356+ clk_hw_get_rate(hws[CLK_DIV_CORE2]));
13501357 }
13511358
13521359
drivers/clk/samsung/clk-exynos5250.c+12−9
@@ -239,7 +239,7 @@ static const struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __ · 238 unmodified lines
239239 };
240240
241241 static const struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initconst = {
242− MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
242+ MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
243243 };
244244
245245 static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {
@@ -351,7 +351,7 @@ static const struct samsung_div_clock exynos5250_div_clks[] __initconst = { · 105 unmodified lines
351351 */
352352 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
353353 DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
354− DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
354+ DIV(CLK_DIV_ARM2, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
355355
356356 /*
357357 * CMU_TOP
@@ -772,6 +772,11 @@ static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = { · 414 unmodified lines
772772 { 0 },
773773 };
774774
775+static const struct samsung_cpu_clock exynos5250_cpu_clks[] __initconst = {
776+ CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL, CLK_CPU_HAS_DIV1, 0x200,
777+ exynos5250_armclk_d),
778+};
779+
775780 static const struct of_device_id ext_clk_match[] __initconst = {
776781 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
777782 { },
@@ -801,12 +806,12 @@ static void __init exynos5250_clk_init(struct device_node *np) · 23 unmodified lines
801806 samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks,
802807 ARRAY_SIZE(exynos5250_pll_pmux_clks));
803808
804− if (_get_rate("fin_pll") == 24 * MHZ) {
809+ if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) {
805810 exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
806811 exynos5250_plls[apll].rate_table = apll_24mhz_tbl;
807812 }
808813
809− if (_get_rate("mout_vpllsrc") == 24 * MHZ)
814+ if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24 * MHZ)
810815 exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;
811816
812817 samsung_clk_register_pll(ctx, exynos5250_plls,
@@ -822,10 +827,8 @@ static void __init exynos5250_clk_init(struct device_node *np) · 9 unmodified lines
822827 ARRAY_SIZE(exynos5250_div_clks));
823828 samsung_clk_register_gate(ctx, exynos5250_gate_clks,
824829 ARRAY_SIZE(exynos5250_gate_clks));
825− exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
826− hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL], 0x200,
827− exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d),
828− CLK_CPU_HAS_DIV1);
830+ samsung_clk_register_cpu(ctx, exynos5250_cpu_clks,
831+ ARRAY_SIZE(exynos5250_cpu_clks));
829832
830833 /*
831834 * Enable arm clock down (in idle) and set arm divider
@@ -855,6 +858,6 @@ static void __init exynos5250_clk_init(struct device_node *np) · 23 unmodified lines
855858 samsung_clk_of_add_provider(np, ctx);
856859
857860 pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
858− _get_rate("div_arm2"));
861+ clk_hw_get_rate(hws[CLK_DIV_ARM2]));
859862 }
860863 CLK_OF_DECLARE_DRIVER(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
drivers/clk/samsung/clk-exynos5420.c+19−10
@@ -1551,6 +1551,20 @@ static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { · 1550 unmodified lines
15511551 { 0 },
15521552 };
15531553
1554+static const struct samsung_cpu_clock exynos5420_cpu_clks[] __initconst = {
1555+ CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, 0x200,
1556+ exynos5420_eglclk_d),
1557+ CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, 0x28200,
1558+ exynos5420_kfcclk_d),
1559+};
1560+
1561+static const struct samsung_cpu_clock exynos5800_cpu_clks[] __initconst = {
1562+ CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, 0x200,
1563+ exynos5800_eglclk_d),
1564+ CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, 0x28200,
1565+ exynos5420_kfcclk_d),
1566+};
1567+
15541568 static const struct of_device_id ext_clk_match[] __initconst = {
15551569 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
15561570 { },
@@ -1580,7 +1594,7 @@ static void __init exynos5x_clk_init(struct device_node *np, · 23 unmodified lines
15801594 ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
15811595 ext_clk_match);
15821596
1583− if (_get_rate("fin_pll") == 24 * MHZ) {
1597+ if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) {
15841598 exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
15851599 exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
15861600 exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
@@ -1625,17 +1639,12 @@ static void __init exynos5x_clk_init(struct device_node *np, · 38 unmodified lines
16251639 }
16261640
16271641 if (soc == EXYNOS5420) {
1628− exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1629− hws[CLK_MOUT_APLL], hws[CLK_MOUT_MSPLL_CPU], 0x200,
1630− exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
1642+ samsung_clk_register_cpu(ctx, exynos5420_cpu_clks,
1643+ ARRAY_SIZE(exynos5420_cpu_clks));
16311644 } else {
1632− exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1633− hws[CLK_MOUT_APLL], hws[CLK_MOUT_MSPLL_CPU], 0x200,
1634− exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
1645+ samsung_clk_register_cpu(ctx, exynos5800_cpu_clks,
1646+ ARRAY_SIZE(exynos5800_cpu_clks));
16351647 }
1636− exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
1637− hws[CLK_MOUT_KPLL], hws[CLK_MOUT_MSPLL_KFC], 0x28200,
1638− exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
16391648
16401649 samsung_clk_extended_sleep_init(reg_base,
16411650 exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs),
drivers/clk/samsung/clk-exynos7885.c+597−0
@@ -0,0 +1,597 @@
1+// SPDX-License-Identifier: GPL-2.0-only
2+/*
3+ * Copyright (C) 2021 Dávid Virág <virag.david003@gmail.com>
4+ * Author: Dávid Virág <virag.david003@gmail.com>
5+ *
6+ * Common Clock Framework support for Exynos7885 SoC.
7+ */
8+
9+#include <linux/clk.h>
10+#include <linux/clk-provider.h>
11+#include <linux/of.h>
12+#include <linux/of_device.h>
13+#include <linux/platform_device.h>
14+
15+#include <dt-bindings/clock/exynos7885.h>
16+
17+#include "clk.h"
18+#include "clk-exynos-arm64.h"
19+
20+/* ---- CMU_TOP ------------------------------------------------------------- */
21+
22+/* Register Offset definitions for CMU_TOP (0x12060000) */
23+#define PLL_LOCKTIME_PLL_SHARED0 0x0000
24+#define PLL_LOCKTIME_PLL_SHARED1 0x0004
25+#define PLL_CON0_PLL_SHARED0 0x0100
26+#define PLL_CON0_PLL_SHARED1 0x0120
27+#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
28+#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
29+#define CLK_CON_MUX_MUX_CLKCMU_CORE_G3D 0x101c
30+#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1058
31+#define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0 0x105c
32+#define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1 0x1060
33+#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART0 0x1064
34+#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART1 0x1068
35+#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART2 0x106c
36+#define CLK_CON_MUX_MUX_CLKCMU_PERI_USI0 0x1070
37+#define CLK_CON_MUX_MUX_CLKCMU_PERI_USI1 0x1074
38+#define CLK_CON_MUX_MUX_CLKCMU_PERI_USI2 0x1078
39+#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x181c
40+#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1820
41+#define CLK_CON_DIV_CLKCMU_CORE_G3D 0x1824
42+#define CLK_CON_DIV_CLKCMU_PERI_BUS 0x1874
43+#define CLK_CON_DIV_CLKCMU_PERI_SPI0 0x1878
44+#define CLK_CON_DIV_CLKCMU_PERI_SPI1 0x187c
45+#define CLK_CON_DIV_CLKCMU_PERI_UART0 0x1880
46+#define CLK_CON_DIV_CLKCMU_PERI_UART1 0x1884
47+#define CLK_CON_DIV_CLKCMU_PERI_UART2 0x1888
48+#define CLK_CON_DIV_CLKCMU_PERI_USI0 0x188c
49+#define CLK_CON_DIV_CLKCMU_PERI_USI1 0x1890
50+#define CLK_CON_DIV_CLKCMU_PERI_USI2 0x1894
51+#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x189c
52+#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18a0
53+#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18a4
54+#define CLK_CON_DIV_PLL_SHARED0_DIV5 0x18a8
55+#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x18ac
56+#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x18b0
57+#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18b4
58+#define CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1 0x2004
59+#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
60+#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
61+#define CLK_CON_GAT_GATE_CLKCMU_CORE_G3D 0x2024
62+#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x207c
63+#define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0 0x2080
64+#define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1 0x2084
65+#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART0 0x2088
66+#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART2 0x208c
67+#define CLK_CON_GAT_GATE_CLKCMU_PERI_USI0 0x2090
68+#define CLK_CON_GAT_GATE_CLKCMU_PERI_USI1 0x2094
69+#define CLK_CON_GAT_GATE_CLKCMU_PERI_USI2 0x2098
70+
71+static const unsigned long top_clk_regs[] __initconst = {
72+ PLL_LOCKTIME_PLL_SHARED0,
73+ PLL_LOCKTIME_PLL_SHARED1,
74+ PLL_CON0_PLL_SHARED0,
75+ PLL_CON0_PLL_SHARED1,
76+ CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
77+ CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
78+ CLK_CON_MUX_MUX_CLKCMU_CORE_G3D,
79+ CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
80+ CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0,
81+ CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1,
82+ CLK_CON_MUX_MUX_CLKCMU_PERI_UART0,
83+ CLK_CON_MUX_MUX_CLKCMU_PERI_UART1,
84+ CLK_CON_MUX_MUX_CLKCMU_PERI_UART2,
85+ CLK_CON_MUX_MUX_CLKCMU_PERI_USI0,
86+ CLK_CON_MUX_MUX_CLKCMU_PERI_USI1,
87+ CLK_CON_MUX_MUX_CLKCMU_PERI_USI2,
88+ CLK_CON_DIV_CLKCMU_CORE_BUS,
89+ CLK_CON_DIV_CLKCMU_CORE_CCI,
90+ CLK_CON_DIV_CLKCMU_CORE_G3D,
91+ CLK_CON_DIV_CLKCMU_PERI_BUS,
92+ CLK_CON_DIV_CLKCMU_PERI_SPI0,
93+ CLK_CON_DIV_CLKCMU_PERI_SPI1,
94+ CLK_CON_DIV_CLKCMU_PERI_UART0,
95+ CLK_CON_DIV_CLKCMU_PERI_UART1,
96+ CLK_CON_DIV_CLKCMU_PERI_UART2,
97+ CLK_CON_DIV_CLKCMU_PERI_USI0,
98+ CLK_CON_DIV_CLKCMU_PERI_USI1,
99+ CLK_CON_DIV_CLKCMU_PERI_USI2,
100+ CLK_CON_DIV_PLL_SHARED0_DIV2,
101+ CLK_CON_DIV_PLL_SHARED0_DIV3,
102+ CLK_CON_DIV_PLL_SHARED0_DIV4,
103+ CLK_CON_DIV_PLL_SHARED0_DIV5,
104+ CLK_CON_DIV_PLL_SHARED1_DIV2,
105+ CLK_CON_DIV_PLL_SHARED1_DIV3,
106+ CLK_CON_DIV_PLL_SHARED1_DIV4,
107+ CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1,
108+ CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
109+ CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
110+ CLK_CON_GAT_GATE_CLKCMU_CORE_G3D,
111+ CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
112+ CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0,
113+ CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1,
114+ CLK_CON_GAT_GATE_CLKCMU_PERI_UART0,
115+ CLK_CON_GAT_GATE_CLKCMU_PERI_UART2,
116+ CLK_CON_GAT_GATE_CLKCMU_PERI_USI0,
117+ CLK_CON_GAT_GATE_CLKCMU_PERI_USI1,
118+ CLK_CON_GAT_GATE_CLKCMU_PERI_USI2,
119+};
120+
121+static const struct samsung_pll_clock top_pll_clks[] __initconst = {
122+ PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
123+ PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0,
124+ NULL),
125+ PLL(pll_1417x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
126+ PLL_LOCKTIME_PLL_SHARED1, PLL_CON0_PLL_SHARED1,
127+ NULL),
128+};
129+
130+/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
131+PNAME(mout_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
132+ "dout_shared0_div3", "dout_shared0_div3" };
133+PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2",
134+ "dout_shared0_div3", "dout_shared0_div3" };
135+PNAME(mout_core_g3d_p) = { "dout_shared0_div2", "dout_shared1_div2",
136+ "dout_shared0_div3", "dout_shared0_div3" };
137+
138+/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
139+PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
140+PNAME(mout_peri_spi0_p) = { "oscclk", "dout_shared0_div4" };
141+PNAME(mout_peri_spi1_p) = { "oscclk", "dout_shared0_div4" };
142+PNAME(mout_peri_uart0_p) = { "oscclk", "dout_shared0_div4" };
143+PNAME(mout_peri_uart1_p) = { "oscclk", "dout_shared0_div4" };
144+PNAME(mout_peri_uart2_p) = { "oscclk", "dout_shared0_div4" };
145+PNAME(mout_peri_usi0_p) = { "oscclk", "dout_shared0_div4" };
146+PNAME(mout_peri_usi1_p) = { "oscclk", "dout_shared0_div4" };
147+PNAME(mout_peri_usi2_p) = { "oscclk", "dout_shared0_div4" };
148+
149+static const struct samsung_mux_clock top_mux_clks[] __initconst = {
150+ /* CORE */
151+ MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
152+ CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
153+ MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p,
154+ CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2),
155+ MUX(CLK_MOUT_CORE_G3D, "mout_core_g3d", mout_core_g3d_p,
156+ CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, 0, 2),
157+
158+ /* PERI */
159+ MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
160+ CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
161+ MUX(CLK_MOUT_PERI_SPI0, "mout_peri_spi0", mout_peri_spi0_p,
162+ CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0, 0, 1),
163+ MUX(CLK_MOUT_PERI_SPI1, "mout_peri_spi1", mout_peri_spi1_p,
164+ CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1, 0, 1),
165+ MUX(CLK_MOUT_PERI_UART0, "mout_peri_uart0", mout_peri_uart0_p,
166+ CLK_CON_MUX_MUX_CLKCMU_PERI_UART0, 0, 1),
167+ MUX(CLK_MOUT_PERI_UART1, "mout_peri_uart1", mout_peri_uart1_p,
168+ CLK_CON_MUX_MUX_CLKCMU_PERI_UART1, 0, 1),
169+ MUX(CLK_MOUT_PERI_UART2, "mout_peri_uart2", mout_peri_uart2_p,
170+ CLK_CON_MUX_MUX_CLKCMU_PERI_UART2, 0, 1),
171+ MUX(CLK_MOUT_PERI_USI0, "mout_peri_usi0", mout_peri_usi0_p,
172+ CLK_CON_MUX_MUX_CLKCMU_PERI_USI0, 0, 1),
173+ MUX(CLK_MOUT_PERI_USI1, "mout_peri_usi1", mout_peri_usi1_p,
174+ CLK_CON_MUX_MUX_CLKCMU_PERI_USI1, 0, 1),
175+ MUX(CLK_MOUT_PERI_USI2, "mout_peri_usi2", mout_peri_usi2_p,
176+ CLK_CON_MUX_MUX_CLKCMU_PERI_USI2, 0, 1),
177+};
178+
179+static const struct samsung_div_clock top_div_clks[] __initconst = {
180+ /* TOP */
181+ DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "fout_shared0_pll",
182+ CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
183+ DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "fout_shared0_pll",
184+ CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
185+ DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "fout_shared0_pll",
186+ CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
187+ DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "fout_shared0_pll",
188+ CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
189+ DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "fout_shared1_pll",
190+ CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
191+ DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "fout_shared1_pll",
192+ CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
193+ DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "fout_shared1_pll",
194+ CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
195+
196+ /* CORE */
197+ DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
198+ CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 3),
199+ DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci",
200+ CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 3),
201+ DIV(CLK_DOUT_CORE_G3D, "dout_core_g3d", "gout_core_g3d",
202+ CLK_CON_DIV_CLKCMU_CORE_G3D, 0, 3),
203+
204+ /* PERI */
205+ DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
206+ CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
207+ DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "gout_peri_spi0",
208+ CLK_CON_DIV_CLKCMU_PERI_SPI0, 0, 6),
209+ DIV(CLK_DOUT_PERI_SPI1, "dout_peri_spi1", "gout_peri_spi1",
210+ CLK_CON_DIV_CLKCMU_PERI_SPI1, 0, 6),
211+ DIV(CLK_DOUT_PERI_UART0, "dout_peri_uart0", "gout_peri_uart0",
212+ CLK_CON_DIV_CLKCMU_PERI_UART0, 0, 4),
213+ DIV(CLK_DOUT_PERI_UART1, "dout_peri_uart1", "gout_peri_uart1",
214+ CLK_CON_DIV_CLKCMU_PERI_UART1, 0, 4),
215+ DIV(CLK_DOUT_PERI_UART2, "dout_peri_uart2", "gout_peri_uart2",
216+ CLK_CON_DIV_CLKCMU_PERI_UART2, 0, 4),
217+ DIV(CLK_DOUT_PERI_USI0, "dout_peri_usi0", "gout_peri_usi0",
218+ CLK_CON_DIV_CLKCMU_PERI_USI0, 0, 4),
219+ DIV(CLK_DOUT_PERI_USI1, "dout_peri_usi1", "gout_peri_usi1",
220+ CLK_CON_DIV_CLKCMU_PERI_USI1, 0, 4),
221+ DIV(CLK_DOUT_PERI_USI2, "dout_peri_usi2", "gout_peri_usi2",
222+ CLK_CON_DIV_CLKCMU_PERI_USI2, 0, 4),
223+};
224+
225+static const struct samsung_gate_clock top_gate_clks[] __initconst = {
226+ /* CORE */
227+ GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus",
228+ CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
229+ GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci",
230+ CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0),
231+ GATE(CLK_GOUT_CORE_G3D, "gout_core_g3d", "mout_core_g3d",
232+ CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, 21, 0, 0),
233+
234+ /* PERI */
235+ GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
236+ CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
237+ GATE(CLK_GOUT_PERI_SPI0, "gout_peri_spi0", "mout_peri_spi0",
238+ CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0, 21, 0, 0),
239+ GATE(CLK_GOUT_PERI_SPI1, "gout_peri_spi1", "mout_peri_spi1",
240+ CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1, 21, 0, 0),
241+ GATE(CLK_GOUT_PERI_UART0, "gout_peri_uart0", "mout_peri_uart0",
242+ CLK_CON_GAT_GATE_CLKCMU_PERI_UART0, 21, 0, 0),
243+ GATE(CLK_GOUT_PERI_UART1, "gout_peri_uart1", "mout_peri_uart1",
244+ CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1, 21, 0, 0),
245+ GATE(CLK_GOUT_PERI_UART2, "gout_peri_uart2", "mout_peri_uart2",
246+ CLK_CON_GAT_GATE_CLKCMU_PERI_UART2, 21, 0, 0),
247+ GATE(CLK_GOUT_PERI_USI0, "gout_peri_usi0", "mout_peri_usi0",
248+ CLK_CON_GAT_GATE_CLKCMU_PERI_USI0, 21, 0, 0),
249+ GATE(CLK_GOUT_PERI_USI1, "gout_peri_usi1", "mout_peri_usi1",
250+ CLK_CON_GAT_GATE_CLKCMU_PERI_USI1, 21, 0, 0),
251+ GATE(CLK_GOUT_PERI_USI2, "gout_peri_usi2", "mout_peri_usi2",
252+ CLK_CON_GAT_GATE_CLKCMU_PERI_USI2, 21, 0, 0),
253+};
254+
255+static const struct samsung_cmu_info top_cmu_info __initconst = {
256+ .pll_clks = top_pll_clks,
257+ .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
258+ .mux_clks = top_mux_clks,
259+ .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
260+ .div_clks = top_div_clks,
261+ .nr_div_clks = ARRAY_SIZE(top_div_clks),
262+ .gate_clks = top_gate_clks,
263+ .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
264+ .nr_clk_ids = TOP_NR_CLK,
265+ .clk_regs = top_clk_regs,
266+ .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
267+};
268+
269+static void __init exynos7885_cmu_top_init(struct device_node *np)
270+{
271+ exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
272+}
273+
274+/* Register CMU_TOP early, as it's a dependency for other early domains */
275+CLK_OF_DECLARE(exynos7885_cmu_top, "samsung,exynos7885-cmu-top",
276+ exynos7885_cmu_top_init);
277+
278+/* ---- CMU_PERI ------------------------------------------------------------ */
279+
280+/* Register Offset definitions for CMU_PERI (0x10010000) */
281+#define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0100
282+#define PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER 0x0120
283+#define PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER 0x0140
284+#define PLL_CON0_MUX_CLKCMU_PERI_UART0_USER 0x0160
285+#define PLL_CON0_MUX_CLKCMU_PERI_UART1_USER 0x0180
286+#define PLL_CON0_MUX_CLKCMU_PERI_UART2_USER 0x01a0
287+#define PLL_CON0_MUX_CLKCMU_PERI_USI0_USER 0x01c0
288+#define PLL_CON0_MUX_CLKCMU_PERI_USI1_USER 0x01e0
289+#define PLL_CON0_MUX_CLKCMU_PERI_USI2_USER 0x0200
290+#define CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK 0x2024
291+#define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028
292+#define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x202c
293+#define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2030
294+#define CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK 0x2034
295+#define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x2038
296+#define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x203c
297+#define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2040
298+#define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2044
299+#define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x2048
300+#define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x204c
301+#define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2050
302+#define CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK 0x2054
303+#define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2058
304+#define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x205c
305+#define CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK 0x2060
306+#define CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK 0x2064
307+#define CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK 0x2068
308+#define CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK 0x206c
309+#define CLK_CON_GAT_GOUT_PERI_UART_0_PCLK 0x2070
310+#define CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK 0x2074
311+#define CLK_CON_GAT_GOUT_PERI_UART_1_PCLK 0x2078
312+#define CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK 0x207c
313+#define CLK_CON_GAT_GOUT_PERI_UART_2_PCLK 0x2080
314+#define CLK_CON_GAT_GOUT_PERI_USI0_PCLK 0x2084
315+#define CLK_CON_GAT_GOUT_PERI_USI0_SCLK 0x2088
316+#define CLK_CON_GAT_GOUT_PERI_USI1_PCLK 0x208c
317+#define CLK_CON_GAT_GOUT_PERI_USI1_SCLK 0x2090
318+#define CLK_CON_GAT_GOUT_PERI_USI2_PCLK 0x2094
319+#define CLK_CON_GAT_GOUT_PERI_USI2_SCLK 0x2098
320+#define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x20a0
321+#define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20b0
322+#define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK 0x20b4
323+#define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK 0x20b8
324+
325+static const unsigned long peri_clk_regs[] __initconst = {
326+ PLL_CON0_MUX_CLKCMU_PERI_BUS_USER,
327+ PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER,
328+ PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER,
329+ PLL_CON0_MUX_CLKCMU_PERI_UART0_USER,
330+ PLL_CON0_MUX_CLKCMU_PERI_UART1_USER,
331+ PLL_CON0_MUX_CLKCMU_PERI_UART2_USER,
332+ PLL_CON0_MUX_CLKCMU_PERI_USI0_USER,
333+ PLL_CON0_MUX_CLKCMU_PERI_USI1_USER,
334+ PLL_CON0_MUX_CLKCMU_PERI_USI2_USER,
335+ CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK,
336+ CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK,
337+ CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK,
338+ CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK,
339+ CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK,
340+ CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK,
341+ CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK,
342+ CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK,
343+ CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK,
344+ CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK,
345+ CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK,
346+ CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK,
347+ CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK,
348+ CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK,
349+ CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK,
350+ CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK,
351+ CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK,
352+ CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK,
353+ CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK,
354+ CLK_CON_GAT_GOUT_PERI_UART_0_PCLK,
355+ CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK,
356+ CLK_CON_GAT_GOUT_PERI_UART_1_PCLK,
357+ CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK,
358+ CLK_CON_GAT_GOUT_PERI_UART_2_PCLK,
359+ CLK_CON_GAT_GOUT_PERI_USI0_PCLK,
360+ CLK_CON_GAT_GOUT_PERI_USI0_SCLK,
361+ CLK_CON_GAT_GOUT_PERI_USI1_PCLK,
362+ CLK_CON_GAT_GOUT_PERI_USI1_SCLK,
363+ CLK_CON_GAT_GOUT_PERI_USI2_PCLK,
364+ CLK_CON_GAT_GOUT_PERI_USI2_SCLK,
365+ CLK_CON_GAT_GOUT_PERI_MCT_PCLK,
366+ CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK,
367+ CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK,
368+ CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK,
369+};
370+
371+/* List of parent clocks for Muxes in CMU_PERI */
372+PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" };
373+PNAME(mout_peri_spi0_user_p) = { "oscclk", "dout_peri_spi0" };
374+PNAME(mout_peri_spi1_user_p) = { "oscclk", "dout_peri_spi1" };
375+PNAME(mout_peri_uart0_user_p) = { "oscclk", "dout_peri_uart0" };
376+PNAME(mout_peri_uart1_user_p) = { "oscclk", "dout_peri_uart1" };
377+PNAME(mout_peri_uart2_user_p) = { "oscclk", "dout_peri_uart2" };
378+PNAME(mout_peri_usi0_user_p) = { "oscclk", "dout_peri_usi0" };
379+PNAME(mout_peri_usi1_user_p) = { "oscclk", "dout_peri_usi1" };
380+PNAME(mout_peri_usi2_user_p) = { "oscclk", "dout_peri_usi2" };
381+
382+static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
383+ MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p,
384+ PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1),
385+ MUX(CLK_MOUT_PERI_SPI0_USER, "mout_peri_spi0_user", mout_peri_spi0_user_p,
386+ PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER, 4, 1),
387+ MUX(CLK_MOUT_PERI_SPI1_USER, "mout_peri_spi1_user", mout_peri_spi1_user_p,
388+ PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER, 4, 1),
389+ MUX(CLK_MOUT_PERI_UART0_USER, "mout_peri_uart0_user",
390+ mout_peri_uart0_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART0_USER, 4, 1),
391+ MUX(CLK_MOUT_PERI_UART1_USER, "mout_peri_uart1_user",
392+ mout_peri_uart1_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART1_USER, 4, 1),
393+ MUX(CLK_MOUT_PERI_UART2_USER, "mout_peri_uart2_user",
394+ mout_peri_uart2_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART2_USER, 4, 1),
395+ MUX(CLK_MOUT_PERI_USI0_USER, "mout_peri_usi0_user",
396+ mout_peri_usi0_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI0_USER, 4, 1),
397+ MUX(CLK_MOUT_PERI_USI1_USER, "mout_peri_usi1_user",
398+ mout_peri_usi1_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI1_USER, 4, 1),
399+ MUX(CLK_MOUT_PERI_USI2_USER, "mout_peri_usi2_user",
400+ mout_peri_usi2_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI2_USER, 4, 1),
401+};
402+
403+static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
404+ /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
405+ GATE(CLK_GOUT_GPIO_TOP_PCLK, "gout_gpio_top_pclk",
406+ "mout_peri_bus_user",
407+ CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK, 21, CLK_IGNORE_UNUSED, 0),
408+ GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user",
409+ CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0),
410+ GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user",
411+ CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0),
412+ GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user",
413+ CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0),
414+ GATE(CLK_GOUT_HSI2C3_PCLK, "gout_hsi2c3_pclk", "mout_peri_bus_user",
415+ CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK, 21, 0, 0),
416+ GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user",
417+ CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0),
418+ GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user",
419+ CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0),
420+ GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user",
421+ CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0),
422+ GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user",
423+ CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0),
424+ GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user",
425+ CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0),
426+ GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user",
427+ CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0),
428+ GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user",
429+ CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0),
430+ GATE(CLK_GOUT_I2C7_PCLK, "gout_i2c7_pclk", "mout_peri_bus_user",
431+ CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK, 21, 0, 0),
432+ GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk",
433+ "mout_peri_bus_user",
434+ CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0),
435+ GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user",
436+ CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0),
437+ GATE(CLK_GOUT_SPI0_EXT_CLK, "gout_spi0_ipclk", "mout_peri_spi0_user",
438+ CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK, 21, 0, 0),
439+ GATE(CLK_GOUT_SPI1_PCLK, "gout_spi1_pclk", "mout_peri_bus_user",
440+ CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK, 21, 0, 0),
441+ GATE(CLK_GOUT_SPI1_EXT_CLK, "gout_spi1_ipclk", "mout_peri_spi1_user",
442+ CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK, 21, 0, 0),
443+ GATE(CLK_GOUT_UART0_EXT_UCLK, "gout_uart0_ext_uclk", "mout_peri_uart0_user",
444+ CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK, 21, 0, 0),
445+ GATE(CLK_GOUT_UART0_PCLK, "gout_uart0_pclk", "mout_peri_bus_user",
446+ CLK_CON_GAT_GOUT_PERI_UART_0_PCLK, 21, 0, 0),
447+ GATE(CLK_GOUT_UART1_EXT_UCLK, "gout_uart1_ext_uclk", "mout_peri_uart1_user",
448+ CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK, 21, 0, 0),
449+ GATE(CLK_GOUT_UART1_PCLK, "gout_uart1_pclk", "mout_peri_bus_user",
450+ CLK_CON_GAT_GOUT_PERI_UART_1_PCLK, 21, 0, 0),
451+ GATE(CLK_GOUT_UART2_EXT_UCLK, "gout_uart2_ext_uclk", "mout_peri_uart2_user",
452+ CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK, 21, 0, 0),
453+ GATE(CLK_GOUT_UART2_PCLK, "gout_uart2_pclk", "mout_peri_bus_user",
454+ CLK_CON_GAT_GOUT_PERI_UART_2_PCLK, 21, 0, 0),
455+ GATE(CLK_GOUT_USI0_PCLK, "gout_usi0_pclk", "mout_peri_bus_user",
456+ CLK_CON_GAT_GOUT_PERI_USI0_PCLK, 21, 0, 0),
457+ GATE(CLK_GOUT_USI0_SCLK, "gout_usi0_sclk", "mout_peri_usi0_user",
458+ CLK_CON_GAT_GOUT_PERI_USI0_SCLK, 21, 0, 0),
459+ GATE(CLK_GOUT_USI1_PCLK, "gout_usi1_pclk", "mout_peri_bus_user",
460+ CLK_CON_GAT_GOUT_PERI_USI1_PCLK, 21, 0, 0),
461+ GATE(CLK_GOUT_USI1_SCLK, "gout_usi1_sclk", "mout_peri_usi1_user",
462+ CLK_CON_GAT_GOUT_PERI_USI1_SCLK, 21, 0, 0),
463+ GATE(CLK_GOUT_USI2_PCLK, "gout_usi2_pclk", "mout_peri_bus_user",
464+ CLK_CON_GAT_GOUT_PERI_USI2_PCLK, 21, 0, 0),
465+ GATE(CLK_GOUT_USI2_SCLK, "gout_usi2_sclk", "mout_peri_usi2_user",
466+ CLK_CON_GAT_GOUT_PERI_USI2_SCLK, 21, 0, 0),
467+ GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user",
468+ CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0),
469+ GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk",
470+ "mout_peri_bus_user",
471+ CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0),
472+ GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user",
473+ CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK, 21, 0, 0),
474+ GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user",
475+ CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK, 21, 0, 0),
476+};
477+
478+static const struct samsung_cmu_info peri_cmu_info __initconst = {
479+ .mux_clks = peri_mux_clks,
480+ .nr_mux_clks = ARRAY_SIZE(peri_mux_clks),
481+ .gate_clks = peri_gate_clks,
482+ .nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
483+ .nr_clk_ids = PERI_NR_CLK,
484+ .clk_regs = peri_clk_regs,
485+ .nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
486+ .clk_name = "dout_peri_bus",
487+};
488+
489+static void __init exynos7885_cmu_peri_init(struct device_node *np)
490+{
491+ exynos_arm64_register_cmu(NULL, np, &peri_cmu_info);
492+}
493+
494+/* Register CMU_PERI early, as it's needed for MCT timer */
495+CLK_OF_DECLARE(exynos7885_cmu_peri, "samsung,exynos7885-cmu-peri",
496+ exynos7885_cmu_peri_init);
497+
498+/* ---- CMU_CORE ------------------------------------------------------------ */
499+
500+/* Register Offset definitions for CMU_CORE (0x12000000) */
501+#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0100
502+#define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0120
503+#define PLL_CON0_MUX_CLKCMU_CORE_G3D_USER 0x0140
504+#define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000
505+#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
506+#define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2054
507+#define CLK_CON_GAT_GOUT_CORE_GIC400_CLK 0x2058
508+
509+static const unsigned long core_clk_regs[] __initconst = {
510+ PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
511+ PLL_CON0_MUX_CLKCMU_CORE_CCI_USER,
512+ PLL_CON0_MUX_CLKCMU_CORE_G3D_USER,
513+ CLK_CON_MUX_MUX_CLK_CORE_GIC,
514+ CLK_CON_DIV_DIV_CLK_CORE_BUSP,
515+ CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK,
516+ CLK_CON_GAT_GOUT_CORE_GIC400_CLK,
517+};
518+
519+/* List of parent clocks for Muxes in CMU_CORE */
520+PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" };
521+PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" };
522+PNAME(mout_core_g3d_user_p) = { "oscclk", "dout_core_g3d" };
523+PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" };
524+
525+static const struct samsung_mux_clock core_mux_clks[] __initconst = {
526+ MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p,
527+ PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
528+ MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p,
529+ PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1),
530+ MUX(CLK_MOUT_CORE_G3D_USER, "mout_core_g3d_user", mout_core_g3d_user_p,
531+ PLL_CON0_MUX_CLKCMU_CORE_G3D_USER, 4, 1),
532+ MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p,
533+ CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1),
534+};
535+
536+static const struct samsung_div_clock core_div_clks[] __initconst = {
537+ DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user",
538+ CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2),
539+};
540+
541+static const struct samsung_gate_clock core_gate_clks[] __initconst = {
542+ /* CCI (interconnect) clock must be always running */
543+ GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user",
544+ CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0),
545+ /* GIC (interrupt controller) clock must be always running */
546+ GATE(CLK_GOUT_GIC400_CLK, "gout_gic400_clk", "mout_core_gic",
547+ CLK_CON_GAT_GOUT_CORE_GIC400_CLK, 21, CLK_IS_CRITICAL, 0),
548+};
549+
550+static const struct samsung_cmu_info core_cmu_info __initconst = {
551+ .mux_clks = core_mux_clks,
552+ .nr_mux_clks = ARRAY_SIZE(core_mux_clks),
553+ .div_clks = core_div_clks,
554+ .nr_div_clks = ARRAY_SIZE(core_div_clks),
555+ .gate_clks = core_gate_clks,
556+ .nr_gate_clks = ARRAY_SIZE(core_gate_clks),
557+ .nr_clk_ids = CORE_NR_CLK,
558+ .clk_regs = core_clk_regs,
559+ .nr_clk_regs = ARRAY_SIZE(core_clk_regs),
560+ .clk_name = "dout_core_bus",
561+};
562+
563+/* ---- platform_driver ----------------------------------------------------- */
564+
565+static int __init exynos7885_cmu_probe(struct platform_device *pdev)
566+{
567+ const struct samsung_cmu_info *info;
568+ struct device *dev = &pdev->dev;
569+
570+ info = of_device_get_match_data(dev);
571+ exynos_arm64_register_cmu(dev, dev->of_node, info);
572+
573+ return 0;
574+}
575+
576+static const struct of_device_id exynos7885_cmu_of_match[] = {
577+ {
578+ .compatible = "samsung,exynos7885-cmu-core",
579+ .data = &core_cmu_info,
580+ }, {
581+ },
582+};
583+
584+static struct platform_driver exynos7885_cmu_driver __refdata = {
585+ .driver = {
586+ .name = "exynos7885-cmu",
587+ .of_match_table = exynos7885_cmu_of_match,
588+ .suppress_bind_attrs = true,
589+ },
590+ .probe = exynos7885_cmu_probe,
591+};
592+
593+static int __init exynos7885_cmu_init(void)
594+{
595+ return platform_driver_register(&exynos7885_cmu_driver);
596+}
597+core_initcall(exynos7885_cmu_init);
drivers/clk/samsung/clk-exynos850.c+295−71
@@ -9,56 +9,13 @@ · 8 unmodified lines
99 #include <linux/clk.h>
1010 #include <linux/clk-provider.h>
1111 #include <linux/of.h>
12−#include <linux/of_address.h>
1312 #include <linux/of_device.h>
1413 #include <linux/platform_device.h>
1514
1615 #include <dt-bindings/clock/exynos850.h>
1716
1817 #include "clk.h"
19−
20−/* Gate register bits */
21−#define GATE_MANUAL BIT(20)
22−#define GATE_ENABLE_HWACG BIT(28)
23−
24−/* Gate register offsets range */
25−#define GATE_OFF_START 0x2000
26−#define GATE_OFF_END 0x2fff
27−
28−/**
29− * exynos850_init_clocks - Set clocks initial configuration
30− * @np: CMU device tree node with "reg" property (CMU addr)
31− * @reg_offs: Register offsets array for clocks to init
32− * @reg_offs_len: Number of register offsets in reg_offs array
33− *
34− * Set manual control mode for all gate clocks.
35− */
36−static void __init exynos850_init_clocks(struct device_node *np,
37− const unsigned long *reg_offs, size_t reg_offs_len)
38−{
39− void __iomem *reg_base;
40− size_t i;
41−
42− reg_base = of_iomap(np, 0);
43− if (!reg_base)
44− panic("%s: failed to map registers\n", __func__);
45−
46− for (i = 0; i < reg_offs_len; ++i) {
47− void __iomem *reg = reg_base + reg_offs[i];
48− u32 val;
49−
50− /* Modify only gate clock registers */
51− if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END)
52− continue;
53−
54− val = readl(reg);
55− val |= GATE_MANUAL;
56− val &= ~GATE_ENABLE_HWACG;
57− writel(val, reg);
58− }
59−
60− iounmap(reg_base);
61−}
18+#include "clk-exynos-arm64.h"
6219
6320 /* ---- CMU_TOP ------------------------------------------------------------- */
6421
@@ -72,6 +29,7 @@ static void __init exynos850_init_clocks(struct device_node *np, · 7 unmodified lines
7229 #define PLL_CON3_PLL_SHARED0 0x014c
7330 #define PLL_CON0_PLL_SHARED1 0x0180
7431 #define PLL_CON3_PLL_SHARED1 0x018c
32+#define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000
7533 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
7634 #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
7735 #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
@@ -83,6 +41,7 @@ static void __init exynos850_init_clocks(struct device_node *np, · 5 unmodified lines
8341 #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070
8442 #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
8543 #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
44+#define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c
8645 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820
8746 #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824
8847 #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
@@ -100,6 +59,7 @@ static void __init exynos850_init_clocks(struct device_node *np, · 11 unmodified lines
10059 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898
10160 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c
10261 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0
62+#define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008
10363 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
10464 #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
10565 #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
@@ -122,6 +82,7 @@ static const unsigned long top_clk_regs[] __initconst = { · 16 unmodified lines
12282 PLL_CON3_PLL_SHARED0,
12383 PLL_CON0_PLL_SHARED1,
12484 PLL_CON3_PLL_SHARED1,
85+ CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
12586 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
12687 CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
12788 CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD,
@@ -133,6 +94,7 @@ static const unsigned long top_clk_regs[] __initconst = { · 5 unmodified lines
13394 CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
13495 CLK_CON_MUX_MUX_CLKCMU_PERI_IP,
13596 CLK_CON_MUX_MUX_CLKCMU_PERI_UART,
97+ CLK_CON_DIV_CLKCMU_APM_BUS,
13698 CLK_CON_DIV_CLKCMU_CORE_BUS,
13799 CLK_CON_DIV_CLKCMU_CORE_CCI,
138100 CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD,
@@ -150,6 +112,7 @@ static const unsigned long top_clk_regs[] __initconst = { · 11 unmodified lines
150112 CLK_CON_DIV_PLL_SHARED1_DIV2,
151113 CLK_CON_DIV_PLL_SHARED1_DIV3,
152114 CLK_CON_DIV_PLL_SHARED1_DIV4,
115+ CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
153116 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
154117 CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
155118 CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD,
@@ -183,6 +146,8 @@ static const struct samsung_pll_clock top_pll_clks[] __initconst = { · 27 unmodified lines
183146 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
184147 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
185148 PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
149+/* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */
150+PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" };
186151 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
187152 PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3",
188153 "dout_shared1_div3", "dout_shared0_div4" };
@@ -222,6 +187,10 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = { · 33 unmodified lines
222187 MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
223188 PLL_CON0_PLL_MMC, 4, 1),
224189
190+ /* APM */
191+ MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus",
192+ mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
193+
225194 /* CORE */
226195 MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
227196 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
@@ -268,6 +237,10 @@ static const struct samsung_div_clock top_div_clks[] __initconst = { · 40 unmodified lines
268237 DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
269238 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
270239
240+ /* APM */
241+ DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus",
242+ "gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
243+
271244 /* CORE */
272245 DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
273246 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
@@ -310,6 +283,10 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = { · 36 unmodified lines
310283 GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss",
311284 CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0),
312285
286+ /* APM */
287+ GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus",
288+ "mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0),
289+
313290 /* DPU */
314291 GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
315292 CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
@@ -347,13 +324,248 @@ static const struct samsung_cmu_info top_cmu_info __initconst = { · 31 unmodified lines
347324
348325 static void __init exynos850_cmu_top_init(struct device_node *np)
349326 {
350− exynos850_init_clocks(np, top_clk_regs, ARRAY_SIZE(top_clk_regs));
351− samsung_cmu_register_one(np, &top_cmu_info);
327+ exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
352328 }
353329
330+/* Register CMU_TOP early, as it's a dependency for other early domains */
354331 CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top",
355332 exynos850_cmu_top_init);
356333
334+/* ---- CMU_APM ------------------------------------------------------------- */
335+
336+/* Register Offset definitions for CMU_APM (0x11800000) */
337+#define PLL_CON0_MUX_CLKCMU_APM_BUS_USER 0x0600
338+#define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER 0x0610
339+#define PLL_CON0_MUX_CLK_RCO_APM_USER 0x0620
340+#define PLL_CON0_MUX_DLL_USER 0x0630
341+#define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS 0x1000
342+#define CLK_CON_MUX_MUX_CLK_APM_BUS 0x1004
343+#define CLK_CON_MUX_MUX_CLK_APM_I3C 0x1008
344+#define CLK_CON_DIV_CLKCMU_CHUB_BUS 0x1800
345+#define CLK_CON_DIV_DIV_CLK_APM_BUS 0x1804
346+#define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808
347+#define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000
348+#define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014
349+#define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2018
350+#define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2020
351+#define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024
352+#define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028
353+#define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034
354+#define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038
355+#define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc
356+#define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0
357+
358+static const unsigned long apm_clk_regs[] __initconst = {
359+ PLL_CON0_MUX_CLKCMU_APM_BUS_USER,
360+ PLL_CON0_MUX_CLK_RCO_APM_I3C_USER,
361+ PLL_CON0_MUX_CLK_RCO_APM_USER,
362+ PLL_CON0_MUX_DLL_USER,
363+ CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS,
364+ CLK_CON_MUX_MUX_CLK_APM_BUS,
365+ CLK_CON_MUX_MUX_CLK_APM_I3C,
366+ CLK_CON_DIV_CLKCMU_CHUB_BUS,
367+ CLK_CON_DIV_DIV_CLK_APM_BUS,
368+ CLK_CON_DIV_DIV_CLK_APM_I3C,
369+ CLK_CON_GAT_CLKCMU_CMGP_BUS,
370+ CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS,
371+ CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK,
372+ CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK,
373+ CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK,
374+ CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK,
375+ CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK,
376+ CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK,
377+ CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK,
378+ CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK,
379+};
380+
381+/* List of parent clocks for Muxes in CMU_APM */
382+PNAME(mout_apm_bus_user_p) = { "oscclk_rco_apm", "dout_clkcmu_apm_bus" };
383+PNAME(mout_rco_apm_i3c_user_p) = { "oscclk_rco_apm", "clk_rco_i3c_pmic" };
384+PNAME(mout_rco_apm_user_p) = { "oscclk_rco_apm", "clk_rco_apm__alv" };
385+PNAME(mout_dll_user_p) = { "oscclk_rco_apm", "clk_dll_dco" };
386+PNAME(mout_clkcmu_chub_bus_p) = { "mout_apm_bus_user", "mout_dll_user" };
387+PNAME(mout_apm_bus_p) = { "mout_rco_apm_user", "mout_apm_bus_user",
388+ "mout_dll_user", "oscclk_rco_apm" };
389+PNAME(mout_apm_i3c_p) = { "dout_apm_i3c", "mout_rco_apm_i3c_user" };
390+
391+static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {
392+ FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000),
393+ FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000),
394+ FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000),
395+ FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000),
396+};
397+
398+static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
399+ MUX(CLK_MOUT_APM_BUS_USER, "mout_apm_bus_user", mout_apm_bus_user_p,
400+ PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 4, 1),
401+ MUX(CLK_MOUT_RCO_APM_I3C_USER, "mout_rco_apm_i3c_user",
402+ mout_rco_apm_i3c_user_p, PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 4, 1),
403+ MUX(CLK_MOUT_RCO_APM_USER, "mout_rco_apm_user", mout_rco_apm_user_p,
404+ PLL_CON0_MUX_CLK_RCO_APM_USER, 4, 1),
405+ MUX(CLK_MOUT_DLL_USER, "mout_dll_user", mout_dll_user_p,
406+ PLL_CON0_MUX_DLL_USER, 4, 1),
407+ MUX(CLK_MOUT_CLKCMU_CHUB_BUS, "mout_clkcmu_chub_bus",
408+ mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1),
409+ MUX(CLK_MOUT_APM_BUS, "mout_apm_bus", mout_apm_bus_p,
410+ CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2),
411+ MUX(CLK_MOUT_APM_I3C, "mout_apm_i3c", mout_apm_i3c_p,
412+ CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1),
413+};
414+
415+static const struct samsung_div_clock apm_div_clks[] __initconst = {
416+ DIV(CLK_DOUT_CLKCMU_CHUB_BUS, "dout_clkcmu_chub_bus",
417+ "gout_clkcmu_chub_bus",
418+ CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3),
419+ DIV(CLK_DOUT_APM_BUS, "dout_apm_bus", "mout_apm_bus",
420+ CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3),
421+ DIV(CLK_DOUT_APM_I3C, "dout_apm_i3c", "mout_apm_bus",
422+ CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3),
423+};
424+
425+static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
426+ GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus",
427+ CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0),
428+ GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus",
429+ "mout_clkcmu_chub_bus",
430+ CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0),
431+ GATE(CLK_GOUT_RTC_PCLK, "gout_rtc_pclk", "dout_apm_bus",
432+ CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0),
433+ GATE(CLK_GOUT_TOP_RTC_PCLK, "gout_top_rtc_pclk", "dout_apm_bus",
434+ CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0),
435+ GATE(CLK_GOUT_I3C_PCLK, "gout_i3c_pclk", "dout_apm_bus",
436+ CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0),
437+ GATE(CLK_GOUT_I3C_SCLK, "gout_i3c_sclk", "mout_apm_i3c",
438+ CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0),
439+ GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus",
440+ CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0),
441+ /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
442+ GATE(CLK_GOUT_GPIO_ALIVE_PCLK, "gout_gpio_alive_pclk", "dout_apm_bus",
443+ CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED,
444+ 0),
445+ GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus",
446+ CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, 0, 0),
447+ GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus",
448+ CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0),
449+};
450+
451+static const struct samsung_cmu_info apm_cmu_info __initconst = {
452+ .mux_clks = apm_mux_clks,
453+ .nr_mux_clks = ARRAY_SIZE(apm_mux_clks),
454+ .div_clks = apm_div_clks,
455+ .nr_div_clks = ARRAY_SIZE(apm_div_clks),
456+ .gate_clks = apm_gate_clks,
457+ .nr_gate_clks = ARRAY_SIZE(apm_gate_clks),
458+ .fixed_clks = apm_fixed_clks,
459+ .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks),
460+ .nr_clk_ids = APM_NR_CLK,
461+ .clk_regs = apm_clk_regs,
462+ .nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
463+ .clk_name = "dout_clkcmu_apm_bus",
464+};
465+
466+/* ---- CMU_CMGP ------------------------------------------------------------ */
467+
468+/* Register Offset definitions for CMU_CMGP (0x11c00000) */
469+#define CLK_CON_MUX_CLK_CMGP_ADC 0x1000
470+#define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 0x1004
471+#define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 0x1008
472+#define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800
473+#define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 0x1804
474+#define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 0x1808
475+#define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c
476+#define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010
477+#define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018
478+#define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK 0x2040
479+#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044
480+#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048
481+#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c
482+#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK 0x2050
483+
484+static const unsigned long cmgp_clk_regs[] __initconst = {
485+ CLK_CON_MUX_CLK_CMGP_ADC,
486+ CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0,
487+ CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1,
488+ CLK_CON_DIV_DIV_CLK_CMGP_ADC,
489+ CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0,
490+ CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1,
491+ CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0,
492+ CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1,
493+ CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK,
494+ CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK,
495+ CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK,
496+ CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK,
497+ CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK,
498+ CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK,
499+};
500+
501+/* List of parent clocks for Muxes in CMU_CMGP */
502+PNAME(mout_cmgp_usi0_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" };
503+PNAME(mout_cmgp_usi1_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" };
504+PNAME(mout_cmgp_adc_p) = { "oscclk", "dout_cmgp_adc" };
505+
506+static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = {
507+ FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000),
508+};
509+
510+static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = {
511+ MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p,
512+ CLK_CON_MUX_CLK_CMGP_ADC, 0, 1),
513+ MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p,
514+ CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1),
515+ MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p,
516+ CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1),
517+};
518+
519+static const struct samsung_div_clock cmgp_div_clks[] __initconst = {
520+ DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus",
521+ CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4),
522+ DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0",
523+ CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5),
524+ DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1",
525+ CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5),
526+};
527+
528+static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = {
529+ GATE(CLK_GOUT_CMGP_ADC_S0_PCLK, "gout_adc_s0_pclk",
530+ "gout_clkcmu_cmgp_bus",
531+ CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0),
532+ GATE(CLK_GOUT_CMGP_ADC_S1_PCLK, "gout_adc_s1_pclk",
533+ "gout_clkcmu_cmgp_bus",
534+ CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0),
535+ /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
536+ GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_gpio_cmgp_pclk",
537+ "gout_clkcmu_cmgp_bus",
538+ CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0),
539+ GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0",
540+ CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0),
541+ GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk",
542+ "gout_clkcmu_cmgp_bus",
543+ CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0),
544+ GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1",
545+ CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0),
546+ GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk",
547+ "gout_clkcmu_cmgp_bus",
548+ CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0),
549+ GATE(CLK_GOUT_SYSREG_CMGP_PCLK, "gout_sysreg_cmgp_pclk",
550+ "gout_clkcmu_cmgp_bus",
551+ CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0),
552+};
553+
554+static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
555+ .mux_clks = cmgp_mux_clks,
556+ .nr_mux_clks = ARRAY_SIZE(cmgp_mux_clks),
557+ .div_clks = cmgp_div_clks,
558+ .nr_div_clks = ARRAY_SIZE(cmgp_div_clks),
559+ .gate_clks = cmgp_gate_clks,
560+ .nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks),
561+ .fixed_clks = cmgp_fixed_clks,
562+ .nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks),
563+ .nr_clk_ids = CMGP_NR_CLK,
564+ .clk_regs = cmgp_clk_regs,
565+ .nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs),
566+ .clk_name = "gout_clkcmu_cmgp_bus",
567+};
568+
357569 /* ---- CMU_HSI ------------------------------------------------------------- */
358570
359571 /* Register Offset definitions for CMU_HSI (0x13400000) */
@@ -413,8 +625,9 @@ static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { · 53 unmodified lines
413625 CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0),
414626 GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "oscclk",
415627 CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0),
628+ /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
416629 GATE(CLK_GOUT_GPIO_HSI_PCLK, "gout_gpio_hsi_pclk", "mout_hsi_bus_user",
417− CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, 0, 0),
630+ CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
418631 GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user",
419632 CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0),
420633 GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
@@ -597,9 +810,10 @@ static const struct samsung_gate_clock peri_gate_clks[] __initconst = { · 176 unmodified lines
597810 CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0),
598811 GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user",
599812 CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0),
813+ /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
600814 GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk",
601815 "mout_peri_bus_user",
602− CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, 0, 0),
816+ CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
603817 };
604818
605819 static const struct samsung_cmu_info peri_cmu_info __initconst = {
@@ -615,6 +829,15 @@ static const struct samsung_cmu_info peri_cmu_info __initconst = { · 9 unmodified lines
615829 .clk_name = "dout_peri_bus",
616830 };
617831
832+static void __init exynos850_cmu_peri_init(struct device_node *np)
833+{
834+ exynos_arm64_register_cmu(NULL, np, &peri_cmu_info);
835+}
836+
837+/* Register CMU_PERI early, as it's needed for MCT timer */
838+CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri",
839+ exynos850_cmu_peri_init);
840+
618841 /* ---- CMU_CORE ------------------------------------------------------------ */
619842
620843 /* Register Offset definitions for CMU_CORE (0x12000000) */
@@ -626,10 +849,12 @@ static const struct samsung_cmu_info peri_cmu_info __initconst = { · 5 unmodified lines
626849 #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
627850 #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038
628851 #define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040
852+#define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044
629853 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8
630854 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec
631855 #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128
632856 #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c
857+#define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130
633858
634859 static const unsigned long core_clk_regs[] __initconst = {
635860 PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
@@ -640,10 +865,12 @@ static const unsigned long core_clk_regs[] __initconst = { · 4 unmodified lines
640865 CLK_CON_DIV_DIV_CLK_CORE_BUSP,
641866 CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK,
642867 CLK_CON_GAT_GOUT_CORE_GIC_CLK,
868+ CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK,
643869 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK,
644870 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
645871 CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK,
646872 CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK,
873+ CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK,
647874 };
648875
649876 /* List of parent clocks for Muxes in CMU_CORE */
@@ -673,10 +900,12 @@ static const struct samsung_div_clock core_div_clks[] __initconst = { · 23 unmodified lines
673900 };
674901
675902 static const struct samsung_gate_clock core_gate_clks[] __initconst = {
903+ /* CCI (interconnect) clock must be always running */
676904 GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user",
677− CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, 0, 0),
905+ CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0),
906+ /* GIC (interrupt controller) clock must be always running */
678907 GATE(CLK_GOUT_GIC_CLK, "gout_gic_clk", "mout_core_gic",
679− CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, 0, 0),
908+ CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, CLK_IS_CRITICAL, 0),
680909 GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp",
681910 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0),
682911 GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin",
@@ -686,6 +915,12 @@ static const struct samsung_gate_clock core_gate_clks[] __initconst = { · 3 unmodified lines
686915 CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0),
687916 GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp",
688917 CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0),
918+ /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
919+ GATE(CLK_GOUT_GPIO_CORE_PCLK, "gout_gpio_core_pclk", "dout_core_busp",
920+ CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0),
921+ GATE(CLK_GOUT_SYSREG_CORE_PCLK, "gout_sysreg_core_pclk",
922+ "dout_core_busp",
923+ CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0),
689924 };
690925
691926 static const struct samsung_cmu_info core_cmu_info __initconst = {
@@ -742,8 +977,10 @@ static const struct samsung_div_clock dpu_div_clks[] __initconst = { · 50 unmodified lines
742977 };
743978
744979 static const struct samsung_gate_clock dpu_gate_clks[] __initconst = {
980+ /* TODO: Should be enabled in DSIM driver */
745981 GATE(CLK_GOUT_DPU_CMU_DPU_PCLK, "gout_dpu_cmu_dpu_pclk",
746− "dout_dpu_busp", CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, 0, 0),
982+ "dout_dpu_busp",
983+ CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
747984 GATE(CLK_GOUT_DPU_DECON0_ACLK, "gout_dpu_decon0_aclk", "mout_dpu_user",
748985 CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0),
749986 GATE(CLK_GOUT_DPU_DMA_ACLK, "gout_dpu_dma_aclk", "mout_dpu_user",
@@ -779,36 +1016,23 @@ static int __init exynos850_cmu_probe(struct platform_device *pdev) · 29 unmodified lines
7791016 {
7801017 const struct samsung_cmu_info *info;
7811018 struct device *dev = &pdev->dev;
782− struct device_node *np = dev->of_node;
7831019
7841020 info = of_device_get_match_data(dev);
785− exynos850_init_clocks(np, info->clk_regs, info->nr_clk_regs);
786− samsung_cmu_register_one(np, info);
787−
788− /* Keep bus clock running, so it's possible to access CMU registers */
789− if (info->clk_name) {
790− struct clk *bus_clk;
791−
792− bus_clk = clk_get(dev, info->clk_name);
793− if (IS_ERR(bus_clk)) {
794− pr_err("%s: could not find bus clock %s; err = %ld\n",
795− __func__, info->clk_name, PTR_ERR(bus_clk));
796− } else {
797− clk_prepare_enable(bus_clk);
798− }
799− }
1021+ exynos_arm64_register_cmu(dev, dev->of_node, info);
8001022
8011023 return 0;
8021024 }
8031025
804−/* CMUs which belong to Power Domains and need runtime PM to be implemented */
8051026 static const struct of_device_id exynos850_cmu_of_match[] = {
8061027 {
1028+ .compatible = "samsung,exynos850-cmu-apm",
1029+ .data = &apm_cmu_info,
1030+ }, {
1031+ .compatible = "samsung,exynos850-cmu-cmgp",
1032+ .data = &cmgp_cmu_info,
1033+ }, {
8071034 .compatible = "samsung,exynos850-cmu-hsi",
8081035 .data = &hsi_cmu_info,
809− }, {
810− .compatible = "samsung,exynos850-cmu-peri",
811− .data = &peri_cmu_info,
8121036 }, {
8131037 .compatible = "samsung,exynos850-cmu-core",
8141038 .data = &core_cmu_info,
drivers/clk/samsung/clk-pll.c+1−0
@@ -1476,6 +1476,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, · 1475 unmodified lines
14761476 else
14771477 init.ops = &samsung_pll35xx_clk_ops;
14781478 break;
1479+ case pll_1417x:
14791480 case pll_0822x:
14801481 pll->enable_offs = PLL0822X_ENABLE_SHIFT;
14811482 pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
drivers/clk/samsung/clk-pll.h+1−0
@@ -32,6 +32,7 @@ enum samsung_pll_type { · 31 unmodified lines
3232 pll_2550xx,
3333 pll_2650x,
3434 pll_2650xx,
35+ pll_1417x,
3536 pll_1450x,
3637 pll_1451x,
3738 pll_1452x,
drivers/clk/samsung/clk-s3c2410.c+4−2
@@ -323,6 +323,7 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f, · 322 unmodified lines
323323 void __iomem *base)
324324 {
325325 struct samsung_clk_provider *ctx;
326+ struct clk_hw **hws;
326327 reg_base = base;
327328
328329 if (np) {
@@ -332,13 +333,14 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f, · 3 unmodified lines
332333 }
333334
334335 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
336+ hws = ctx->clk_data.hws;
335337
336338 /* Register external clocks only in non-dt cases */
337339 if (!np)
338340 s3c2410_common_clk_register_fixed_ext(ctx, xti_f);
339341
340342 if (current_soc == S3C2410) {
341− if (_get_rate("xti") == 12 * MHZ) {
343+ if (clk_hw_get_rate(hws[XTI]) == 12 * MHZ) {
342344 s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl;
343345 s3c2410_plls[upll].rate_table = pll_s3c2410_12mhz_tbl;
344346 }
@@ -348,7 +350,7 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f, · 3 unmodified lines
348350 ARRAY_SIZE(s3c2410_plls), reg_base);
349351
350352 } else { /* S3C2440, S3C2442 */
351− if (_get_rate("xti") == 12 * MHZ) {
353+ if (clk_hw_get_rate(hws[XTI]) == 12 * MHZ) {
352354 /*
353355 * plls follow different calculation schemes, with the
354356 * upll following the same scheme as the s3c2410 plls
drivers/clk/samsung/clk-s3c64xx.c+6−2
@@ -394,6 +394,7 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f, · 393 unmodified lines
394394 void __iomem *base)
395395 {
396396 struct samsung_clk_provider *ctx;
397+ struct clk_hw **hws;
397398
398399 reg_base = base;
399400 is_s3c6400 = s3c6400;
@@ -405,6 +406,7 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f, · 5 unmodified lines
405406 }
406407
407408 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
409+ hws = ctx->clk_data.hws;
408410
409411 /* Register external clocks. */
410412 if (!np)
@@ -459,8 +461,10 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f, · 48 unmodified lines
459461 pr_info("%s clocks: apll = %lu, mpll = %lu\n"
460462 "\tepll = %lu, arm_clk = %lu\n",
461463 is_s3c6400 ? "S3C6400" : "S3C6410",
462− _get_rate("fout_apll"), _get_rate("fout_mpll"),
463− _get_rate("fout_epll"), _get_rate("armclk"));
464+ clk_hw_get_rate(hws[MOUT_APLL]),
465+ clk_hw_get_rate(hws[MOUT_MPLL]),
466+ clk_hw_get_rate(hws[MOUT_EPLL]),
467+ clk_hw_get_rate(hws[ARMCLK]));
464468 }
465469
466470 static void __init s3c6400_clk_init(struct device_node *np)
drivers/clk/samsung/clk-s5pv210.c+6−2
@@ -741,8 +741,10 @@ static void __init __s5pv210_clk_init(struct device_node *np, · 740 unmodified lines
741741 bool is_s5p6442)
742742 {
743743 struct samsung_clk_provider *ctx;
744+ struct clk_hw **hws;
744745
745746 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
747+ hws = ctx->clk_data.hws;
746748
747749 samsung_clk_register_mux(ctx, early_mux_clks,
748750 ARRAY_SIZE(early_mux_clks));
@@ -789,8 +791,10 @@ static void __init __s5pv210_clk_init(struct device_node *np, · 40 unmodified lines
789791 pr_info("%s clocks: mout_apll = %ld, mout_mpll = %ld\n"
790792 "\tmout_epll = %ld, mout_vpll = %ld\n",
791793 is_s5p6442 ? "S5P6442" : "S5PV210",
792− _get_rate("mout_apll"), _get_rate("mout_mpll"),
793− _get_rate("mout_epll"), _get_rate("mout_vpll"));
794+ clk_hw_get_rate(hws[MOUT_APLL]),
795+ clk_hw_get_rate(hws[MOUT_MPLL]),
796+ clk_hw_get_rate(hws[MOUT_EPLL]),
797+ clk_hw_get_rate(hws[MOUT_VPLL]));
794798 }
795799
796800 static void __init s5pv210_clk_dt_init(struct device_node *np)
drivers/clk/samsung/clk.c+0−14
@@ -268,20 +268,6 @@ void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx, · 267 unmodified lines
268268 samsung_clk_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk);
269269 }
270270
271−/* utility function to get the rate of a specified clock */
272−unsigned long _get_rate(const char *clk_name)
273−{
274− struct clk *clk;
275−
276− clk = __clk_lookup(clk_name);
277− if (!clk) {
278− pr_err("%s: could not find clock %s\n", __func__, clk_name);
279− return 0;
280− }
281−
282− return clk_get_rate(clk);
283−}
284−
285271 #ifdef CONFIG_PM_SLEEP
286272 static int samsung_clk_suspend(void)
287273 {
drivers/clk/samsung/clk.h+17−19
@@ -337,54 +337,52 @@ struct samsung_cmu_info { · 336 unmodified lines
337337 const char *clk_name;
338338 };
339339
340−extern struct samsung_clk_provider *__init samsung_clk_init(
340+struct samsung_clk_provider * samsung_clk_init(
341341 struct device_node *np, void __iomem *base,
342342 unsigned long nr_clks);
343−extern void __init samsung_clk_of_add_provider(struct device_node *np,
343+void samsung_clk_of_add_provider(struct device_node *np,
344344 struct samsung_clk_provider *ctx);
345−extern void __init samsung_clk_of_register_fixed_ext(
345+void samsung_clk_of_register_fixed_ext(
346346 struct samsung_clk_provider *ctx,
347347 struct samsung_fixed_rate_clock *fixed_rate_clk,
348348 unsigned int nr_fixed_rate_clk,
349349 const struct of_device_id *clk_matches);
350350
351−extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
351+void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
352352 struct clk_hw *clk_hw, unsigned int id);
353353
354−extern void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx,
354+void samsung_clk_register_alias(struct samsung_clk_provider *ctx,
355355 const struct samsung_clock_alias *list,
356356 unsigned int nr_clk);
357−extern void __init samsung_clk_register_fixed_rate(
357+void samsung_clk_register_fixed_rate(
358358 struct samsung_clk_provider *ctx,
359359 const struct samsung_fixed_rate_clock *clk_list,
360360 unsigned int nr_clk);
361−extern void __init samsung_clk_register_fixed_factor(
361+void samsung_clk_register_fixed_factor(
362362 struct samsung_clk_provider *ctx,
363363 const struct samsung_fixed_factor_clock *list,
364364 unsigned int nr_clk);
365−extern void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
365+void samsung_clk_register_mux(struct samsung_clk_provider *ctx,
366366 const struct samsung_mux_clock *clk_list,
367367 unsigned int nr_clk);
368−extern void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
368+void samsung_clk_register_div(struct samsung_clk_provider *ctx,
369369 const struct samsung_div_clock *clk_list,
370370 unsigned int nr_clk);
371−extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
371+void samsung_clk_register_gate(struct samsung_clk_provider *ctx,
372372 const struct samsung_gate_clock *clk_list,
373373 unsigned int nr_clk);
374−extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
374+void samsung_clk_register_pll(struct samsung_clk_provider *ctx,
375375 const struct samsung_pll_clock *pll_list,
376376 unsigned int nr_clk, void __iomem *base);
377−extern void samsung_clk_register_cpu(struct samsung_clk_provider *ctx,
377+void samsung_clk_register_cpu(struct samsung_clk_provider *ctx,
378378 const struct samsung_cpu_clock *list, unsigned int nr_clk);
379379
380−extern struct samsung_clk_provider __init *samsung_cmu_register_one(
380+struct samsung_clk_provider *samsung_cmu_register_one(
381381 struct device_node *,
382382 const struct samsung_cmu_info *);
383383
384−extern unsigned long _get_rate(const char *clk_name);
385−
386384 #ifdef CONFIG_PM_SLEEP
387−extern void samsung_clk_extended_sleep_init(void __iomem *reg_base,
385+void samsung_clk_extended_sleep_init(void __iomem *reg_base,
388386 const unsigned long *rdump,
389387 unsigned long nr_rdump,
390388 const struct samsung_clk_reg_dump *rsuspend,
@@ -399,13 +397,13 @@ static inline void samsung_clk_extended_sleep_init(void __iomem *reg_base, · 8 unmodified lines
399397 #define samsung_clk_sleep_init(reg_base, rdump, nr_rdump) \
400398 samsung_clk_extended_sleep_init(reg_base, rdump, nr_rdump, NULL, 0)
401399
402−extern void samsung_clk_save(void __iomem *base,
400+void samsung_clk_save(void __iomem *base,
403401 struct samsung_clk_reg_dump *rd,
404402 unsigned int num_regs);
405−extern void samsung_clk_restore(void __iomem *base,
403+void samsung_clk_restore(void __iomem *base,
406404 const struct samsung_clk_reg_dump *rd,
407405 unsigned int num_regs);
408−extern struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
406+struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
409407 const unsigned long *rdump,
410408 unsigned long nr_rdump);
411409
drivers/clk/socfpga/clk-agilex.c+1−3
@@ -500,12 +500,10 @@ static int n5x_clkmgr_init(struct platform_device *pdev) · 499 unmodified lines
500500 struct device_node *np = pdev->dev.of_node;
501501 struct device *dev = &pdev->dev;
502502 struct stratix10_clock_data *clk_data;
503− struct resource *res;
504503 void __iomem *base;
505504 int i, num_clks;
506505
507− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
508− base = devm_ioremap_resource(dev, res);
506+ base = devm_platform_ioremap_resource(pdev, 0);
509507 if (IS_ERR(base))
510508 return PTR_ERR(base);
511509
drivers/clk/socfpga/clk-gate.c+2−2
@@ -34,7 +34,7 @@ static u8 socfpga_clk_get_parent(struct clk_hw *hwclk) · 33 unmodified lines
3434
3535 if (streq(name, SOCFPGA_L4_MP_CLK)) {
3636 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
37− return l4_src &= 0x1;
37+ return l4_src & 0x1;
3838 }
3939 if (streq(name, SOCFPGA_L4_SP_CLK)) {
4040 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
@@ -43,7 +43,7 @@ static u8 socfpga_clk_get_parent(struct clk_hw *hwclk) · 2 unmodified lines
4343
4444 perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
4545 if (streq(name, SOCFPGA_MMC_CLK))
46− return perpll_src &= 0x3;
46+ return perpll_src & 0x3;
4747 if (streq(name, SOCFPGA_NAND_CLK) ||
4848 streq(name, SOCFPGA_NAND_X_CLK))
4949 return (perpll_src >> 2) & 3;
drivers/clk/socfpga/clk-pll-s10.c+1−1
@@ -113,7 +113,7 @@ static unsigned long clk_boot_clk_recalc_rate(struct clk_hw *hwclk, · 112 unmodified lines
113113 SWCTRLBTCLKSEL_MASK) >>
114114 SWCTRLBTCLKSEL_SHIFT);
115115 div += 1;
116− return parent_rate /= div;
116+ return parent_rate / div;
117117 }
118118
119119
drivers/clk/socfpga/clk-s10.c+1−3
@@ -388,12 +388,10 @@ static int s10_clkmgr_init(struct platform_device *pdev) · 387 unmodified lines
388388 struct device_node *np = pdev->dev.of_node;
389389 struct device *dev = &pdev->dev;
390390 struct stratix10_clock_data *clk_data;
391− struct resource *res;
392391 void __iomem *base;
393392 int i, num_clks;
394393
395− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
396− base = devm_ioremap_resource(dev, res);
394+ base = devm_platform_ioremap_resource(pdev, 0);
397395 if (IS_ERR(base)) {
398396 pr_err("%s: failed to map clock registers\n", __func__);
399397 return PTR_ERR(base);
drivers/clk/st/clkgen-fsyn.c+11−2
@@ -988,9 +988,18 @@ static void __init st_of_quadfs_setup(struct device_node *np, · 987 unmodified lines
988988 void __iomem *reg;
989989 spinlock_t *lock;
990990
991+ /*
992+ * First check for reg property within the node to keep backward
993+ * compatibility, then if reg doesn't exist look at the parent node
994+ */
991995 reg = of_iomap(np, 0);
992− if (!reg)
993− return;
996+ if (!reg) {
997+ reg = of_iomap(of_get_parent(np), 0);
998+ if (!reg) {
999+ pr_err("%s: Failed to get base address\n", __func__);
1000+ return;
1001+ }
1002+ }
9941003
9951004 clk_parent_name = of_clk_get_parent_name(np, 0);
9961005 if (!clk_parent_name)
drivers/clk/st/clkgen-mux.c+9−2
@@ -57,10 +57,17 @@ static void __init st_of_clkgen_mux_setup(struct device_node *np, · 56 unmodified lines
5757 const char **parents;
5858 int num_parents = 0;
5959
60+ /*
61+ * First check for reg property within the node to keep backward
62+ * compatibility, then if reg doesn't exist look at the parent node
63+ */
6064 reg = of_iomap(np, 0);
6165 if (!reg) {
62− pr_err("%s: Failed to get base address\n", __func__);
63− return;
66+ reg = of_iomap(of_get_parent(np), 0);
67+ if (!reg) {
68+ pr_err("%s: Failed to get base address\n", __func__);
69+ return;
70+ }
6471 }
6572
6673 parents = clkgen_mux_get_parents(np, &num_parents);
drivers/clk/sunxi-ng/Kconfig+30−19
@@ -1,6 +1,6 @@
11 # SPDX-License-Identifier: GPL-2.0-only
22 config SUNXI_CCU
3− bool "Clock support for Allwinner SoCs"
3+ tristate "Clock support for Allwinner SoCs"
44 depends on ARCH_SUNXI || COMPILE_TEST
55 select RESET_CONTROLLER
66 default ARCH_SUNXI
@@ -8,42 +8,52 @@ config SUNXI_CCU · 1 unmodified line
88 if SUNXI_CCU
99
1010 config SUNIV_F1C100S_CCU
11− bool "Support for the Allwinner newer F1C100s CCU"
11+ tristate "Support for the Allwinner newer F1C100s CCU"
1212 default MACH_SUNIV
1313 depends on MACH_SUNIV || COMPILE_TEST
1414
15+config SUN20I_D1_CCU
16+ tristate "Support for the Allwinner D1 CCU"
17+ default RISCV && ARCH_SUNXI
18+ depends on (RISCV && ARCH_SUNXI) || COMPILE_TEST
19+
20+config SUN20I_D1_R_CCU
21+ tristate "Support for the Allwinner D1 PRCM CCU"
22+ default RISCV && ARCH_SUNXI
23+ depends on (RISCV && ARCH_SUNXI) || COMPILE_TEST
24+
1525 config SUN50I_A64_CCU
16− bool "Support for the Allwinner A64 CCU"
26+ tristate "Support for the Allwinner A64 CCU"
1727 default ARM64 && ARCH_SUNXI
1828 depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
1929
2030 config SUN50I_A100_CCU
21− bool "Support for the Allwinner A100 CCU"
31+ tristate "Support for the Allwinner A100 CCU"
2232 default ARM64 && ARCH_SUNXI
2333 depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
2434
2535 config SUN50I_A100_R_CCU
26− bool "Support for the Allwinner A100 PRCM CCU"
36+ tristate "Support for the Allwinner A100 PRCM CCU"
2737 default ARM64 && ARCH_SUNXI
2838 depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
2939
3040 config SUN50I_H6_CCU
31− bool "Support for the Allwinner H6 CCU"
41+ tristate "Support for the Allwinner H6 CCU"
3242 default ARM64 && ARCH_SUNXI
3343 depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
3444
3545 config SUN50I_H616_CCU
36− bool "Support for the Allwinner H616 CCU"
46+ tristate "Support for the Allwinner H616 CCU"
3747 default ARM64 && ARCH_SUNXI
3848 depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
3949
4050 config SUN50I_H6_R_CCU
41− bool "Support for the Allwinner H6 and H616 PRCM CCU"
51+ tristate "Support for the Allwinner H6 and H616 PRCM CCU"
4252 default ARM64 && ARCH_SUNXI
4353 depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
4454
4555 config SUN4I_A10_CCU
46− bool "Support for the Allwinner A10/A20 CCU"
56+ tristate "Support for the Allwinner A10/A20 CCU"
4757 default MACH_SUN4I
4858 default MACH_SUN7I
4959 depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST
@@ -52,53 +62,54 @@ config SUN5I_CCU · 2 unmodified lines
5262 bool "Support for the Allwinner sun5i family CCM"
5363 default MACH_SUN5I
5464 depends on MACH_SUN5I || COMPILE_TEST
65+ depends on SUNXI_CCU=y
5566
5667 config SUN6I_A31_CCU
57− bool "Support for the Allwinner A31/A31s CCU"
68+ tristate "Support for the Allwinner A31/A31s CCU"
5869 default MACH_SUN6I
5970 depends on MACH_SUN6I || COMPILE_TEST
6071
6172 config SUN8I_A23_CCU
62− bool "Support for the Allwinner A23 CCU"
73+ tristate "Support for the Allwinner A23 CCU"
6374 default MACH_SUN8I
6475 depends on MACH_SUN8I || COMPILE_TEST
6576
6677 config SUN8I_A33_CCU
67− bool "Support for the Allwinner A33 CCU"
78+ tristate "Support for the Allwinner A33 CCU"
6879 default MACH_SUN8I
6980 depends on MACH_SUN8I || COMPILE_TEST
7081
7182 config SUN8I_A83T_CCU
72− bool "Support for the Allwinner A83T CCU"
83+ tristate "Support for the Allwinner A83T CCU"
7384 default MACH_SUN8I
7485 depends on MACH_SUN8I || COMPILE_TEST
7586
7687 config SUN8I_H3_CCU
77− bool "Support for the Allwinner H3 CCU"
88+ tristate "Support for the Allwinner H3 CCU"
7889 default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
7990 depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST
8091
8192 config SUN8I_V3S_CCU
82− bool "Support for the Allwinner V3s CCU"
93+ tristate "Support for the Allwinner V3s CCU"
8394 default MACH_SUN8I
8495 depends on MACH_SUN8I || COMPILE_TEST
8596
8697 config SUN8I_DE2_CCU
87− bool "Support for the Allwinner SoCs DE2 CCU"
98+ tristate "Support for the Allwinner SoCs DE2 CCU"
8899 default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
89100
90101 config SUN8I_R40_CCU
91− bool "Support for the Allwinner R40 CCU"
102+ tristate "Support for the Allwinner R40 CCU"
92103 default MACH_SUN8I
93104 depends on MACH_SUN8I || COMPILE_TEST
94105
95106 config SUN9I_A80_CCU
96− bool "Support for the Allwinner A80 CCU"
107+ tristate "Support for the Allwinner A80 CCU"
97108 default MACH_SUN9I
98109 depends on MACH_SUN9I || COMPILE_TEST
99110
100111 config SUN8I_R_CCU
101− bool "Support for Allwinner SoCs' PRCM CCUs"
112+ tristate "Support for Allwinner SoCs' PRCM CCUs"
102113 default MACH_SUN8I || (ARCH_SUNXI && ARM64)
103114
104115 endif
drivers/clk/sunxi-ng/Makefile+65−36
@@ -1,44 +1,73 @@
11 # SPDX-License-Identifier: GPL-2.0
2+
3+obj-$(CONFIG_SUNXI_CCU) += sunxi-ccu.o
4+
25 # Common objects
3−obj-y += ccu_common.o
4−obj-y += ccu_mmc_timing.o
5−obj-y += ccu_reset.o
6+sunxi-ccu-y += ccu_common.o
7+sunxi-ccu-y += ccu_mmc_timing.o
8+sunxi-ccu-y += ccu_reset.o
69
710 # Base clock types
8−obj-y += ccu_div.o
9−obj-y += ccu_frac.o
10−obj-y += ccu_gate.o
11−obj-y += ccu_mux.o
12−obj-y += ccu_mult.o
13−obj-y += ccu_phase.o
14−obj-y += ccu_sdm.o
11+sunxi-ccu-y += ccu_div.o
12+sunxi-ccu-y += ccu_frac.o
13+sunxi-ccu-y += ccu_gate.o
14+sunxi-ccu-y += ccu_mux.o
15+sunxi-ccu-y += ccu_mult.o
16+sunxi-ccu-y += ccu_phase.o
17+sunxi-ccu-y += ccu_sdm.o
1518
1619 # Multi-factor clocks
17−obj-y += ccu_nk.o
18−obj-y += ccu_nkm.o
19−obj-y += ccu_nkmp.o
20−obj-y += ccu_nm.o
21−obj-y += ccu_mp.o
20+sunxi-ccu-y += ccu_nk.o
21+sunxi-ccu-y += ccu_nkm.o
22+sunxi-ccu-y += ccu_nkmp.o
23+sunxi-ccu-y += ccu_nm.o
24+sunxi-ccu-y += ccu_mp.o
2225
2326 # SoC support
24−obj-$(CONFIG_SUNIV_F1C100S_CCU) += ccu-suniv-f1c100s.o
25−obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
26−obj-$(CONFIG_SUN50I_A100_CCU) += ccu-sun50i-a100.o
27−obj-$(CONFIG_SUN50I_A100_R_CCU) += ccu-sun50i-a100-r.o
28−obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o
29−obj-$(CONFIG_SUN50I_H616_CCU) += ccu-sun50i-h616.o
30−obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o
31−obj-$(CONFIG_SUN4I_A10_CCU) += ccu-sun4i-a10.o
32−obj-$(CONFIG_SUN5I_CCU) += ccu-sun5i.o
33−obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o
34−obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o
35−obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o
36−obj-$(CONFIG_SUN8I_A83T_CCU) += ccu-sun8i-a83t.o
37−obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
38−obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o
39−obj-$(CONFIG_SUN8I_DE2_CCU) += ccu-sun8i-de2.o
40−obj-$(CONFIG_SUN8I_R_CCU) += ccu-sun8i-r.o
41−obj-$(CONFIG_SUN8I_R40_CCU) += ccu-sun8i-r40.o
42−obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o
43−obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o
44−obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o
27+obj-$(CONFIG_SUNIV_F1C100S_CCU) += suniv-f1c100s-ccu.o
28+obj-$(CONFIG_SUN20I_D1_CCU) += sun20i-d1-ccu.o
29+obj-$(CONFIG_SUN20I_D1_R_CCU) += sun20i-d1-r-ccu.o
30+obj-$(CONFIG_SUN50I_A64_CCU) += sun50i-a64-ccu.o
31+obj-$(CONFIG_SUN50I_A100_CCU) += sun50i-a100-ccu.o
32+obj-$(CONFIG_SUN50I_A100_R_CCU) += sun50i-a100-r-ccu.o
33+obj-$(CONFIG_SUN50I_H6_CCU) += sun50i-h6-ccu.o
34+obj-$(CONFIG_SUN50I_H6_R_CCU) += sun50i-h6-r-ccu.o
35+obj-$(CONFIG_SUN50I_H616_CCU) += sun50i-h616-ccu.o
36+obj-$(CONFIG_SUN4I_A10_CCU) += sun4i-a10-ccu.o
37+obj-$(CONFIG_SUN5I_CCU) += sun5i-ccu.o
38+obj-$(CONFIG_SUN6I_A31_CCU) += sun6i-a31-ccu.o
39+obj-$(CONFIG_SUN8I_A23_CCU) += sun8i-a23-ccu.o
40+obj-$(CONFIG_SUN8I_A33_CCU) += sun8i-a33-ccu.o
41+obj-$(CONFIG_SUN8I_A83T_CCU) += sun8i-a83t-ccu.o
42+obj-$(CONFIG_SUN8I_H3_CCU) += sun8i-h3-ccu.o
43+obj-$(CONFIG_SUN8I_R40_CCU) += sun8i-r40-ccu.o
44+obj-$(CONFIG_SUN8I_V3S_CCU) += sun8i-v3s-ccu.o
45+obj-$(CONFIG_SUN8I_DE2_CCU) += sun8i-de2-ccu.o
46+obj-$(CONFIG_SUN8I_R_CCU) += sun8i-r-ccu.o
47+obj-$(CONFIG_SUN9I_A80_CCU) += sun9i-a80-ccu.o
48+obj-$(CONFIG_SUN9I_A80_CCU) += sun9i-a80-de-ccu.o
49+obj-$(CONFIG_SUN9I_A80_CCU) += sun9i-a80-usb-ccu.o
50+
51+suniv-f1c100s-ccu-y += ccu-suniv-f1c100s.o
52+sun20i-d1-ccu-y += ccu-sun20i-d1.o
53+sun20i-d1-r-ccu-y += ccu-sun20i-d1-r.o
54+sun50i-a64-ccu-y += ccu-sun50i-a64.o
55+sun50i-a100-ccu-y += ccu-sun50i-a100.o
56+sun50i-a100-r-ccu-y += ccu-sun50i-a100-r.o
57+sun50i-h6-ccu-y += ccu-sun50i-h6.o
58+sun50i-h6-r-ccu-y += ccu-sun50i-h6-r.o
59+sun50i-h616-ccu-y += ccu-sun50i-h616.o
60+sun4i-a10-ccu-y += ccu-sun4i-a10.o
61+sun5i-ccu-y += ccu-sun5i.o
62+sun6i-a31-ccu-y += ccu-sun6i-a31.o
63+sun8i-a23-ccu-y += ccu-sun8i-a23.o
64+sun8i-a33-ccu-y += ccu-sun8i-a33.o
65+sun8i-a83t-ccu-y += ccu-sun8i-a83t.o
66+sun8i-h3-ccu-y += ccu-sun8i-h3.o
67+sun8i-r40-ccu-y += ccu-sun8i-r40.o
68+sun8i-v3s-ccu-y += ccu-sun8i-v3s.o
69+sun8i-de2-ccu-y += ccu-sun8i-de2.o
70+sun8i-r-ccu-y += ccu-sun8i-r.o
71+sun9i-a80-ccu-y += ccu-sun9i-a80.o
72+sun9i-a80-de-ccu-y += ccu-sun9i-a80-de.o
73+sun9i-a80-usb-ccu-y += ccu-sun9i-a80-usb.o
drivers/clk/sunxi-ng/ccu-sun20i-d1-r.c+140−0
@@ -0,0 +1,140 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (c) 2020 huangzhenwei@allwinnertech.com
4+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
5+ */
6+
7+#include <linux/clk-provider.h>
8+#include <linux/module.h>
9+#include <linux/platform_device.h>
10+
11+#include "ccu_common.h"
12+#include "ccu_reset.h"
13+
14+#include "ccu_gate.h"
15+#include "ccu_mp.h"
16+
17+#include "ccu-sun20i-d1-r.h"
18+
19+static const struct clk_parent_data r_ahb_apb0_parents[] = {
20+ { .fw_name = "hosc" },
21+ { .fw_name = "losc" },
22+ { .fw_name = "iosc" },
23+ { .fw_name = "pll-periph" },
24+};
25+static SUNXI_CCU_MP_DATA_WITH_MUX(r_ahb_clk, "r-ahb",
26+ r_ahb_apb0_parents, 0x000,
27+ 0, 5, /* M */
28+ 8, 2, /* P */
29+ 24, 3, /* mux */
30+ 0);
31+static const struct clk_hw *r_ahb_hw = &r_ahb_clk.common.hw;
32+
33+static SUNXI_CCU_MP_DATA_WITH_MUX(r_apb0_clk, "r-apb0",
34+ r_ahb_apb0_parents, 0x00c,
35+ 0, 5, /* M */
36+ 8, 2, /* P */
37+ 24, 3, /* mux */
38+ 0);
39+static const struct clk_hw *r_apb0_hw = &r_apb0_clk.common.hw;
40+
41+static SUNXI_CCU_GATE_HWS(bus_r_timer_clk, "bus-r-timer", &r_apb0_hw,
42+ 0x11c, BIT(0), 0);
43+static SUNXI_CCU_GATE_HWS(bus_r_twd_clk, "bus-r-twd", &r_apb0_hw,
44+ 0x12c, BIT(0), 0);
45+static SUNXI_CCU_GATE_HWS(bus_r_ppu_clk, "bus-r-ppu", &r_apb0_hw,
46+ 0x1ac, BIT(0), 0);
47+
48+static const struct clk_parent_data r_ir_rx_parents[] = {
49+ { .fw_name = "losc" },
50+ { .fw_name = "hosc" },
51+};
52+static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_ir_rx_clk, "r-ir-rx",
53+ r_ir_rx_parents, 0x1c0,
54+ 0, 5, /* M */
55+ 8, 2, /* P */
56+ 24, 2, /* mux */
57+ BIT(31), /* gate */
58+ 0);
59+
60+static SUNXI_CCU_GATE_HWS(bus_r_ir_rx_clk, "bus-r-ir-rx", &r_apb0_hw,
61+ 0x1cc, BIT(0), 0);
62+static SUNXI_CCU_GATE_HWS(bus_r_rtc_clk, "bus-r-rtc", &r_ahb_hw,
63+ 0x20c, BIT(0), 0);
64+static SUNXI_CCU_GATE_HWS(bus_r_cpucfg_clk, "bus-r-cpucfg", &r_apb0_hw,
65+ 0x22c, BIT(0), 0);
66+
67+static struct ccu_common *sun20i_d1_r_ccu_clks[] = {
68+ &r_ahb_clk.common,
69+ &r_apb0_clk.common,
70+ &bus_r_timer_clk.common,
71+ &bus_r_twd_clk.common,
72+ &bus_r_ppu_clk.common,
73+ &r_ir_rx_clk.common,
74+ &bus_r_ir_rx_clk.common,
75+ &bus_r_rtc_clk.common,
76+ &bus_r_cpucfg_clk.common,
77+};
78+
79+static struct clk_hw_onecell_data sun20i_d1_r_hw_clks = {
80+ .num = CLK_NUMBER,
81+ .hws = {
82+ [CLK_R_AHB] = &r_ahb_clk.common.hw,
83+ [CLK_R_APB0] = &r_apb0_clk.common.hw,
84+ [CLK_BUS_R_TIMER] = &bus_r_timer_clk.common.hw,
85+ [CLK_BUS_R_TWD] = &bus_r_twd_clk.common.hw,
86+ [CLK_BUS_R_PPU] = &bus_r_ppu_clk.common.hw,
87+ [CLK_R_IR_RX] = &r_ir_rx_clk.common.hw,
88+ [CLK_BUS_R_IR_RX] = &bus_r_ir_rx_clk.common.hw,
89+ [CLK_BUS_R_RTC] = &bus_r_rtc_clk.common.hw,
90+ [CLK_BUS_R_CPUCFG] = &bus_r_cpucfg_clk.common.hw,
91+ },
92+};
93+
94+static struct ccu_reset_map sun20i_d1_r_ccu_resets[] = {
95+ [RST_BUS_R_TIMER] = { 0x11c, BIT(16) },
96+ [RST_BUS_R_TWD] = { 0x12c, BIT(16) },
97+ [RST_BUS_R_PPU] = { 0x1ac, BIT(16) },
98+ [RST_BUS_R_IR_RX] = { 0x1cc, BIT(16) },
99+ [RST_BUS_R_RTC] = { 0x20c, BIT(16) },
100+ [RST_BUS_R_CPUCFG] = { 0x22c, BIT(16) },
101+};
102+
103+static const struct sunxi_ccu_desc sun20i_d1_r_ccu_desc = {
104+ .ccu_clks = sun20i_d1_r_ccu_clks,
105+ .num_ccu_clks = ARRAY_SIZE(sun20i_d1_r_ccu_clks),
106+
107+ .hw_clks = &sun20i_d1_r_hw_clks,
108+
109+ .resets = sun20i_d1_r_ccu_resets,
110+ .num_resets = ARRAY_SIZE(sun20i_d1_r_ccu_resets),
111+};
112+
113+static int sun20i_d1_r_ccu_probe(struct platform_device *pdev)
114+{
115+ void __iomem *reg;
116+
117+ reg = devm_platform_ioremap_resource(pdev, 0);
118+ if (IS_ERR(reg))
119+ return PTR_ERR(reg);
120+
121+ return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun20i_d1_r_ccu_desc);
122+}
123+
124+static const struct of_device_id sun20i_d1_r_ccu_ids[] = {
125+ { .compatible = "allwinner,sun20i-d1-r-ccu" },
126+ { }
127+};
128+
129+static struct platform_driver sun20i_d1_r_ccu_driver = {
130+ .probe = sun20i_d1_r_ccu_probe,
131+ .driver = {
132+ .name = "sun20i-d1-r-ccu",
133+ .suppress_bind_attrs = true,
134+ .of_match_table = sun20i_d1_r_ccu_ids,
135+ },
136+};
137+module_platform_driver(sun20i_d1_r_ccu_driver);
138+
139+MODULE_IMPORT_NS(SUNXI_CCU);
140+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu-sun20i-d1-r.h+17−0
@@ -0,0 +1,17 @@
1+/* SPDX-License-Identifier: GPL-2.0 */
2+/*
3+ * Copyright (c) 2020 frank@allwinnertech.com
4+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
5+ */
6+
7+#ifndef _CCU_SUN20I_D1_R_H
8+#define _CCU_SUN20I_D1_R_H
9+
10+#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
11+#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
12+
13+#define CLK_R_APB0 1
14+
15+#define CLK_NUMBER (CLK_BUS_R_CPUCFG + 1)
16+
17+#endif /* _CCU_SUN20I_D1_R_H */
drivers/clk/sunxi-ng/ccu-sun20i-d1.c+1390−0
@@ -0,0 +1,1390 @@
1+// SPDX-License-Identifier: GPL-2.0
2+/*
3+ * Copyright (c) 2020 huangzhenwei@allwinnertech.com
4+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
5+ */
6+
7+#include <linux/clk-provider.h>
8+#include <linux/io.h>
9+#include <linux/module.h>
10+#include <linux/platform_device.h>
11+
12+#include "../clk.h"
13+
14+#include "ccu_common.h"
15+#include "ccu_reset.h"
16+
17+#include "ccu_div.h"
18+#include "ccu_gate.h"
19+#include "ccu_mp.h"
20+#include "ccu_mult.h"
21+#include "ccu_nk.h"
22+#include "ccu_nkm.h"
23+#include "ccu_nkmp.h"
24+#include "ccu_nm.h"
25+
26+#include "ccu-sun20i-d1.h"
27+
28+static const struct clk_parent_data osc24M[] = {
29+ { .fw_name = "hosc" }
30+};
31+
32+/*
33+ * For the CPU PLL, the output divider is described as "only for testing"
34+ * in the user manual. So it's not modelled and forced to 0.
35+ */
36+#define SUN20I_D1_PLL_CPUX_REG 0x000
37+static struct ccu_mult pll_cpux_clk = {
38+ .enable = BIT(27),
39+ .lock = BIT(28),
40+ .mult = _SUNXI_CCU_MULT_MIN(8, 8, 12),
41+ .common = {
42+ .reg = 0x000,
43+ .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-cpux", osc24M,
44+ &ccu_mult_ops,
45+ CLK_SET_RATE_UNGATE),
46+ },
47+};
48+
49+/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
50+#define SUN20I_D1_PLL_DDR0_REG 0x010
51+static struct ccu_nkmp pll_ddr0_clk = {
52+ .enable = BIT(27),
53+ .lock = BIT(28),
54+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
55+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
56+ .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
57+ .common = {
58+ .reg = 0x010,
59+ .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ddr0", osc24M,
60+ &ccu_nkmp_ops,
61+ CLK_SET_RATE_UNGATE),
62+ },
63+};
64+
65+#define SUN20I_D1_PLL_PERIPH0_REG 0x020
66+static struct ccu_nm pll_periph0_4x_clk = {
67+ .enable = BIT(27),
68+ .lock = BIT(28),
69+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
70+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
71+ .common = {
72+ .reg = 0x020,
73+ .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-periph0-4x", osc24M,
74+ &ccu_nm_ops,
75+ CLK_SET_RATE_UNGATE),
76+ },
77+};
78+
79+static const struct clk_hw *pll_periph0_4x_hws[] = {
80+ &pll_periph0_4x_clk.common.hw
81+};
82+static SUNXI_CCU_M_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
83+ pll_periph0_4x_hws, 0x020, 16, 3, 0);
84+static SUNXI_CCU_M_HWS(pll_periph0_800M_clk, "pll-periph0-800M",
85+ pll_periph0_4x_hws, 0x020, 20, 3, 0);
86+
87+static const struct clk_hw *pll_periph0_2x_hws[] = {
88+ &pll_periph0_2x_clk.common.hw
89+};
90+static CLK_FIXED_FACTOR_HWS(pll_periph0_clk, "pll-periph0",
91+ pll_periph0_2x_hws, 2, 1, 0);
92+
93+static const struct clk_hw *pll_periph0_hws[] = { &pll_periph0_clk.hw };
94+static CLK_FIXED_FACTOR_HWS(pll_periph0_div3_clk, "pll-periph0-div3",
95+ pll_periph0_2x_hws, 6, 1, 0);
96+
97+/*
98+ * For Video PLLs, the output divider is described as "only for testing"
99+ * in the user manual. So it's not modelled and forced to 0.
100+ */
101+#define SUN20I_D1_PLL_VIDEO0_REG 0x040
102+static struct ccu_nm pll_video0_4x_clk = {
103+ .enable = BIT(27),
104+ .lock = BIT(28),
105+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
106+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
107+ .common = {
108+ .reg = 0x040,
109+ .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video0-4x", osc24M,
110+ &ccu_nm_ops,
111+ CLK_SET_RATE_UNGATE),
112+ },
113+};
114+
115+static const struct clk_hw *pll_video0_4x_hws[] = {
116+ &pll_video0_4x_clk.common.hw
117+};
118+static CLK_FIXED_FACTOR_HWS(pll_video0_2x_clk, "pll-video0-2x",
119+ pll_video0_4x_hws, 2, 1, CLK_SET_RATE_PARENT);
120+static CLK_FIXED_FACTOR_HWS(pll_video0_clk, "pll-video0",
121+ pll_video0_4x_hws, 4, 1, CLK_SET_RATE_PARENT);
122+
123+#define SUN20I_D1_PLL_VIDEO1_REG 0x048
124+static struct ccu_nm pll_video1_4x_clk = {
125+ .enable = BIT(27),
126+ .lock = BIT(28),
127+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
128+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
129+ .common = {
130+ .reg = 0x048,
131+ .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video1-4x", osc24M,
132+ &ccu_nm_ops,
133+ CLK_SET_RATE_UNGATE),
134+ },
135+};
136+
137+static const struct clk_hw *pll_video1_4x_hws[] = {
138+ &pll_video1_4x_clk.common.hw
139+};
140+static CLK_FIXED_FACTOR_HWS(pll_video1_2x_clk, "pll-video1-2x",
141+ pll_video1_4x_hws, 2, 1, CLK_SET_RATE_PARENT);
142+static CLK_FIXED_FACTOR_HWS(pll_video1_clk, "pll-video1",
143+ pll_video1_4x_hws, 4, 1, CLK_SET_RATE_PARENT);
144+
145+#define SUN20I_D1_PLL_VE_REG 0x058
146+static struct ccu_nkmp pll_ve_clk = {
147+ .enable = BIT(27),
148+ .lock = BIT(28),
149+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
150+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
151+ .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
152+ .common = {
153+ .reg = 0x058,
154+ .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ve", osc24M,
155+ &ccu_nkmp_ops,
156+ CLK_SET_RATE_UNGATE),
157+ },
158+};
159+
160+/*
161+ * PLL_AUDIO0 has m0, m1 dividers in addition to the usual N, M factors.
162+ * Since we only need one frequency from this PLL (22.5792 x 4 == 90.3168 MHz),
163+ * ignore them for now. Enforce the default for them, which is m1 = 0, m0 = 0.
164+ * The M factor must be an even number to produce a 50% duty cycle output.
165+ */
166+#define SUN20I_D1_PLL_AUDIO0_REG 0x078
167+static struct ccu_sdm_setting pll_audio0_sdm_table[] = {
168+ { .rate = 90316800, .pattern = 0xc001288d, .m = 6, .n = 22 },
169+};
170+
171+static struct ccu_nm pll_audio0_4x_clk = {
172+ .enable = BIT(27),
173+ .lock = BIT(28),
174+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
175+ .m = _SUNXI_CCU_DIV(16, 6),
176+ .sdm = _SUNXI_CCU_SDM(pll_audio0_sdm_table, BIT(24),
177+ 0x178, BIT(31)),
178+ .common = {
179+ .reg = 0x078,
180+ .features = CCU_FEATURE_SIGMA_DELTA_MOD,
181+ .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-audio0-4x", osc24M,
182+ &ccu_nm_ops,
183+ CLK_SET_RATE_UNGATE),
184+ },
185+};
186+
187+static const struct clk_hw *pll_audio0_4x_hws[] = {
188+ &pll_audio0_4x_clk.common.hw
189+};
190+static CLK_FIXED_FACTOR_HWS(pll_audio0_2x_clk, "pll-audio0-2x",
191+ pll_audio0_4x_hws, 2, 1, 0);
192+static CLK_FIXED_FACTOR_HWS(pll_audio0_clk, "pll-audio0",
193+ pll_audio0_4x_hws, 4, 1, 0);
194+
195+/*
196+ * PLL_AUDIO1 doesn't need Fractional-N. The output is usually 614.4 MHz for
197+ * audio. The ADC or DAC should divide the PLL output further to 24.576 MHz.
198+ */
199+#define SUN20I_D1_PLL_AUDIO1_REG 0x080
200+static struct ccu_nm pll_audio1_clk = {
201+ .enable = BIT(27),
202+ .lock = BIT(28),
203+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
204+ .m = _SUNXI_CCU_DIV(1, 1),
205+ .common = {
206+ .reg = 0x080,
207+ .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-audio1", osc24M,
208+ &ccu_nm_ops,
209+ CLK_SET_RATE_UNGATE),
210+ },
211+};
212+
213+static const struct clk_hw *pll_audio1_hws[] = {
214+ &pll_audio1_clk.common.hw
215+};
216+static SUNXI_CCU_M_HWS(pll_audio1_div2_clk, "pll-audio1-div2",
217+ pll_audio1_hws, 0x080, 16, 3, 0);
218+static SUNXI_CCU_M_HWS(pll_audio1_div5_clk, "pll-audio1-div5",
219+ pll_audio1_hws, 0x080, 20, 3, 0);
220+
221+/*
222+ * The CPUX gate is not modelled - it is in a separate register (0x504)
223+ * and has a special key field. The clock does not need to be ungated anyway.
224+ */
225+static const struct clk_parent_data cpux_parents[] = {
226+ { .fw_name = "hosc" },
227+ { .fw_name = "losc" },
228+ { .fw_name = "iosc" },
229+ { .hw = &pll_cpux_clk.common.hw },
230+ { .hw = &pll_periph0_clk.hw },
231+ { .hw = &pll_periph0_2x_clk.common.hw },
232+ { .hw = &pll_periph0_800M_clk.common.hw },
233+};
234+static SUNXI_CCU_MUX_DATA(cpux_clk, "cpux", cpux_parents,
235+ 0x500, 24, 3, CLK_SET_RATE_PARENT);
236+
237+static const struct clk_hw *cpux_hws[] = { &cpux_clk.common.hw };
238+static SUNXI_CCU_M_HWS(cpux_axi_clk, "cpux-axi",
239+ cpux_hws, 0x500, 0, 2, 0);
240+static SUNXI_CCU_M_HWS(cpux_apb_clk, "cpux-apb",
241+ cpux_hws, 0x500, 8, 2, 0);
242+
243+static const struct clk_parent_data psi_ahb_parents[] = {
244+ { .fw_name = "hosc" },
245+ { .fw_name = "losc" },
246+ { .fw_name = "iosc" },
247+ { .hw = &pll_periph0_clk.hw },
248+};
249+static SUNXI_CCU_MP_DATA_WITH_MUX(psi_ahb_clk, "psi-ahb", psi_ahb_parents, 0x510,
250+ 0, 2, /* M */
251+ 8, 2, /* P */
252+ 24, 2, /* mux */
253+ 0);
254+
255+static const struct clk_parent_data apb0_apb1_parents[] = {
256+ { .fw_name = "hosc" },
257+ { .fw_name = "losc" },
258+ { .hw = &psi_ahb_clk.common.hw },
259+ { .hw = &pll_periph0_clk.hw },
260+};
261+static SUNXI_CCU_MP_DATA_WITH_MUX(apb0_clk, "apb0", apb0_apb1_parents, 0x520,
262+ 0, 5, /* M */
263+ 8, 2, /* P */
264+ 24, 2, /* mux */
265+ 0);
266+
267+static SUNXI_CCU_MP_DATA_WITH_MUX(apb1_clk, "apb1", apb0_apb1_parents, 0x524,
268+ 0, 5, /* M */
269+ 8, 2, /* P */
270+ 24, 2, /* mux */
271+ 0);
272+
273+static const struct clk_hw *psi_ahb_hws[] = { &psi_ahb_clk.common.hw };
274+static const struct clk_hw *apb0_hws[] = { &apb0_clk.common.hw };
275+static const struct clk_hw *apb1_hws[] = { &apb1_clk.common.hw };
276+
277+static const struct clk_hw *de_di_g2d_parents[] = {
278+ &pll_periph0_2x_clk.common.hw,
279+ &pll_video0_4x_clk.common.hw,
280+ &pll_video1_4x_clk.common.hw,
281+ &pll_audio1_div2_clk.common.hw,
282+};
283+static SUNXI_CCU_M_HW_WITH_MUX_GATE(de_clk, "de", de_di_g2d_parents, 0x600,
284+ 0, 5, /* M */
285+ 24, 3, /* mux */
286+ BIT(31), /* gate */
287+ CLK_SET_RATE_PARENT);
288+
289+static SUNXI_CCU_GATE_HWS(bus_de_clk, "bus-de", psi_ahb_hws,
290+ 0x60c, BIT(0), 0);
291+
292+static SUNXI_CCU_M_HW_WITH_MUX_GATE(di_clk, "di", de_di_g2d_parents, 0x620,
293+ 0, 5, /* M */
294+ 24, 3, /* mux */
295+ BIT(31), /* gate */
296+ CLK_SET_RATE_PARENT);
297+
298+static SUNXI_CCU_GATE_HWS(bus_di_clk, "bus-di", psi_ahb_hws,
299+ 0x62c, BIT(0), 0);
300+
301+static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, "g2d", de_di_g2d_parents, 0x630,
302+ 0, 5, /* M */
303+ 24, 3, /* mux */
304+ BIT(31), /* gate */
305+ 0);
306+
307+static SUNXI_CCU_GATE_HWS(bus_g2d_clk, "bus-g2d", psi_ahb_hws,
308+ 0x63c, BIT(0), 0);
309+
310+static const struct clk_parent_data ce_parents[] = {
311+ { .fw_name = "hosc" },
312+ { .hw = &pll_periph0_2x_clk.common.hw },
313+ { .hw = &pll_periph0_clk.hw },
314+};
315+static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
316+ 0, 4, /* M */
317+ 8, 2, /* P */
318+ 24, 3, /* mux */
319+ BIT(31), /* gate */
320+ 0);
321+
322+static SUNXI_CCU_GATE_HWS(bus_ce_clk, "bus-ce", psi_ahb_hws,
323+ 0x68c, BIT(0), 0);
324+
325+static const struct clk_hw *ve_parents[] = {
326+ &pll_ve_clk.common.hw,
327+ &pll_periph0_2x_clk.common.hw,
328+};
329+static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
330+ 0, 5, /* M */
331+ 24, 1, /* mux */
332+ BIT(31), /* gate */
333+ CLK_SET_RATE_PARENT);
334+
335+static SUNXI_CCU_GATE_HWS(bus_ve_clk, "bus-ve", psi_ahb_hws,
336+ 0x69c, BIT(0), 0);
337+
338+static SUNXI_CCU_GATE_HWS(bus_dma_clk, "bus-dma", psi_ahb_hws,
339+ 0x70c, BIT(0), 0);
340+
341+static SUNXI_CCU_GATE_HWS(bus_msgbox0_clk, "bus-msgbox0", psi_ahb_hws,
342+ 0x71c, BIT(0), 0);
343+static SUNXI_CCU_GATE_HWS(bus_msgbox1_clk, "bus-msgbox1", psi_ahb_hws,
344+ 0x71c, BIT(1), 0);
345+static SUNXI_CCU_GATE_HWS(bus_msgbox2_clk, "bus-msgbox2", psi_ahb_hws,
346+ 0x71c, BIT(2), 0);
347+
348+static SUNXI_CCU_GATE_HWS(bus_spinlock_clk, "bus-spinlock", psi_ahb_hws,
349+ 0x72c, BIT(0), 0);
350+
351+static SUNXI_CCU_GATE_HWS(bus_hstimer_clk, "bus-hstimer", psi_ahb_hws,
352+ 0x73c, BIT(0), 0);
353+
354+static SUNXI_CCU_GATE_DATA(avs_clk, "avs", osc24M,
355+ 0x740, BIT(31), 0);
356+
357+static SUNXI_CCU_GATE_HWS(bus_dbg_clk, "bus-dbg", psi_ahb_hws,
358+ 0x78c, BIT(0), 0);
359+
360+static SUNXI_CCU_GATE_HWS(bus_pwm_clk, "bus-pwm", apb0_hws,
361+ 0x7ac, BIT(0), 0);
362+
363+static SUNXI_CCU_GATE_HWS(bus_iommu_clk, "bus-iommu", apb0_hws,
364+ 0x7bc, BIT(0), 0);
365+
366+static const struct clk_hw *dram_parents[] = {
367+ &pll_ddr0_clk.common.hw,
368+ &pll_audio1_div2_clk.common.hw,
369+ &pll_periph0_2x_clk.common.hw,
370+ &pll_periph0_800M_clk.common.hw,
371+};
372+static SUNXI_CCU_MP_HW_WITH_MUX_GATE(dram_clk, "dram", dram_parents, 0x800,
373+ 0, 2, /* M */
374+ 8, 2, /* P */
375+ 24, 2, /* mux */
376+ BIT(31), CLK_IS_CRITICAL);
377+
378+static CLK_FIXED_FACTOR_HW(mbus_clk, "mbus",
379+ &dram_clk.common.hw, 4, 1, 0);
380+
381+static const struct clk_hw *mbus_hws[] = { &mbus_clk.hw };
382+
383+static SUNXI_CCU_GATE_HWS(mbus_dma_clk, "mbus-dma", mbus_hws,
384+ 0x804, BIT(0), 0);
385+static SUNXI_CCU_GATE_HWS(mbus_ve_clk, "mbus-ve", mbus_hws,
386+ 0x804, BIT(1), 0);
387+static SUNXI_CCU_GATE_HWS(mbus_ce_clk, "mbus-ce", mbus_hws,
388+ 0x804, BIT(2), 0);
389+static SUNXI_CCU_GATE_HWS(mbus_tvin_clk, "mbus-tvin", mbus_hws,
390+ 0x804, BIT(7), 0);
391+static SUNXI_CCU_GATE_HWS(mbus_csi_clk, "mbus-csi", mbus_hws,
392+ 0x804, BIT(8), 0);
393+static SUNXI_CCU_GATE_HWS(mbus_g2d_clk, "mbus-g2d", mbus_hws,
394+ 0x804, BIT(10), 0);
395+static SUNXI_CCU_GATE_HWS(mbus_riscv_clk, "mbus-riscv", mbus_hws,
396+ 0x804, BIT(11), 0);
397+
398+static SUNXI_CCU_GATE_HWS(bus_dram_clk, "bus-dram", psi_ahb_hws,
399+ 0x80c, BIT(0), CLK_IS_CRITICAL);
400+
401+static const struct clk_parent_data mmc0_mmc1_parents[] = {
402+ { .fw_name = "hosc" },
403+ { .hw = &pll_periph0_clk.hw },
404+ { .hw = &pll_periph0_2x_clk.common.hw },
405+ { .hw = &pll_audio1_div2_clk.common.hw },
406+};
407+static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc0_mmc1_parents, 0x830,
408+ 0, 4, /* M */
409+ 8, 2, /* P */
410+ 24, 3, /* mux */
411+ BIT(31), /* gate */
412+ 0);
413+
414+static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc0_mmc1_parents, 0x834,
415+ 0, 4, /* M */
416+ 8, 2, /* P */
417+ 24, 3, /* mux */
418+ BIT(31), /* gate */
419+ 0);
420+
421+static const struct clk_parent_data mmc2_parents[] = {
422+ { .fw_name = "hosc" },
423+ { .hw = &pll_periph0_clk.hw },
424+ { .hw = &pll_periph0_2x_clk.common.hw },
425+ { .hw = &pll_periph0_800M_clk.common.hw },
426+ { .hw = &pll_audio1_div2_clk.common.hw },
427+};
428+static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc2_parents, 0x838,
429+ 0, 4, /* M */
430+ 8, 2, /* P */
431+ 24, 3, /* mux */
432+ BIT(31), /* gate */
433+ 0);
434+
435+static SUNXI_CCU_GATE_HWS(bus_mmc0_clk, "bus-mmc0", psi_ahb_hws,
436+ 0x84c, BIT(0), 0);
437+static SUNXI_CCU_GATE_HWS(bus_mmc1_clk, "bus-mmc1", psi_ahb_hws,
438+ 0x84c, BIT(1), 0);
439+static SUNXI_CCU_GATE_HWS(bus_mmc2_clk, "bus-mmc2", psi_ahb_hws,
440+ 0x84c, BIT(2), 0);
441+
442+static SUNXI_CCU_GATE_HWS(bus_uart0_clk, "bus-uart0", apb1_hws,
443+ 0x90c, BIT(0), 0);
444+static SUNXI_CCU_GATE_HWS(bus_uart1_clk, "bus-uart1", apb1_hws,
445+ 0x90c, BIT(1), 0);
446+static SUNXI_CCU_GATE_HWS(bus_uart2_clk, "bus-uart2", apb1_hws,
447+ 0x90c, BIT(2), 0);
448+static SUNXI_CCU_GATE_HWS(bus_uart3_clk, "bus-uart3", apb1_hws,
449+ 0x90c, BIT(3), 0);
450+static SUNXI_CCU_GATE_HWS(bus_uart4_clk, "bus-uart4", apb1_hws,
451+ 0x90c, BIT(4), 0);
452+static SUNXI_CCU_GATE_HWS(bus_uart5_clk, "bus-uart5", apb1_hws,
453+ 0x90c, BIT(5), 0);
454+
455+static SUNXI_CCU_GATE_HWS(bus_i2c0_clk, "bus-i2c0", apb1_hws,
456+ 0x91c, BIT(0), 0);
457+static SUNXI_CCU_GATE_HWS(bus_i2c1_clk, "bus-i2c1", apb1_hws,
458+ 0x91c, BIT(1), 0);
459+static SUNXI_CCU_GATE_HWS(bus_i2c2_clk, "bus-i2c2", apb1_hws,
460+ 0x91c, BIT(2), 0);
461+static SUNXI_CCU_GATE_HWS(bus_i2c3_clk, "bus-i2c3", apb1_hws,
462+ 0x91c, BIT(3), 0);
463+
464+static const struct clk_parent_data spi_parents[] = {
465+ { .fw_name = "hosc" },
466+ { .hw = &pll_periph0_clk.hw },
467+ { .hw = &pll_periph0_2x_clk.common.hw },
468+ { .hw = &pll_audio1_div2_clk.common.hw },
469+ { .hw = &pll_audio1_div5_clk.common.hw },
470+};
471+static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi0_clk, "spi0", spi_parents, 0x940,
472+ 0, 4, /* M */
473+ 8, 2, /* P */
474+ 24, 3, /* mux */
475+ BIT(31), /* gate */
476+ 0);
477+
478+static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi1_clk, "spi1", spi_parents, 0x944,
479+ 0, 4, /* M */
480+ 8, 2, /* P */
481+ 24, 3, /* mux */
482+ BIT(31), /* gate */
483+ 0);
484+
485+static SUNXI_CCU_GATE_HWS(bus_spi0_clk, "bus-spi0", psi_ahb_hws,
486+ 0x96c, BIT(0), 0);
487+static SUNXI_CCU_GATE_HWS(bus_spi1_clk, "bus-spi1", psi_ahb_hws,
488+ 0x96c, BIT(1), 0);
489+
490+static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac_25M_clk, "emac-25M", pll_periph0_hws,
491+ 0x970, BIT(31) | BIT(30), 24, 0);
492+
493+static SUNXI_CCU_GATE_HWS(bus_emac_clk, "bus-emac", psi_ahb_hws,
494+ 0x97c, BIT(0), 0);
495+
496+static const struct clk_parent_data ir_tx_ledc_parents[] = {
497+ { .fw_name = "hosc" },
498+ { .hw = &pll_periph0_clk.hw },
499+};
500+static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_tx_ledc_parents, 0x9c0,
501+ 0, 4, /* M */
502+ 8, 2, /* P */
503+ 24, 3, /* mux */
504+ BIT(31), /* gate */
505+ 0);
506+
507+static SUNXI_CCU_GATE_HWS(bus_ir_tx_clk, "bus-ir-tx", apb0_hws,
508+ 0x9cc, BIT(0), 0);
509+
510+static SUNXI_CCU_GATE_HWS(bus_gpadc_clk, "bus-gpadc", apb0_hws,
511+ 0x9ec, BIT(0), 0);
512+
513+static SUNXI_CCU_GATE_HWS(bus_ths_clk, "bus-ths", apb0_hws,
514+ 0x9fc, BIT(0), 0);
515+
516+static const struct clk_hw *i2s_spdif_tx_parents[] = {
517+ &pll_audio0_clk.hw,
518+ &pll_audio0_4x_clk.common.hw,
519+ &pll_audio1_div2_clk.common.hw,
520+ &pll_audio1_div5_clk.common.hw,
521+};
522+static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s0_clk, "i2s0", i2s_spdif_tx_parents, 0xa10,
523+ 0, 5, /* M */
524+ 8, 2, /* P */
525+ 24, 3, /* mux */
526+ BIT(31), /* gate */
527+ 0);
528+
529+static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s1_clk, "i2s1", i2s_spdif_tx_parents, 0xa14,
530+ 0, 5, /* M */
531+ 8, 2, /* P */
532+ 24, 3, /* mux */
533+ BIT(31), /* gate */
534+ 0);
535+
536+static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s2_clk, "i2s2", i2s_spdif_tx_parents, 0xa18,
537+ 0, 5, /* M */
538+ 8, 2, /* P */
539+ 24, 3, /* mux */
540+ BIT(31), /* gate */
541+ 0);
542+
543+static const struct clk_hw *i2s2_asrc_parents[] = {
544+ &pll_audio0_4x_clk.common.hw,
545+ &pll_periph0_clk.hw,
546+ &pll_audio1_div2_clk.common.hw,
547+ &pll_audio1_div5_clk.common.hw,
548+};
549+static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s2_asrc_clk, "i2s2-asrc", i2s2_asrc_parents, 0xa1c,
550+ 0, 5, /* M */
551+ 8, 2, /* P */
552+ 24, 3, /* mux */
553+ BIT(31), /* gate */
554+ 0);
555+
556+static SUNXI_CCU_GATE_HWS(bus_i2s0_clk, "bus-i2s0", apb0_hws,
557+ 0xa20, BIT(0), 0);
558+static SUNXI_CCU_GATE_HWS(bus_i2s1_clk, "bus-i2s1", apb0_hws,
559+ 0xa20, BIT(1), 0);
560+static SUNXI_CCU_GATE_HWS(bus_i2s2_clk, "bus-i2s2", apb0_hws,
561+ 0xa20, BIT(2), 0);
562+
563+static SUNXI_CCU_MP_HW_WITH_MUX_GATE(spdif_tx_clk, "spdif-tx", i2s_spdif_tx_parents, 0xa24,
564+ 0, 5, /* M */
565+ 8, 2, /* P */
566+ 24, 3, /* mux */
567+ BIT(31), /* gate */
568+ 0);
569+
570+static const struct clk_hw *spdif_rx_parents[] = {
571+ &pll_periph0_clk.hw,
572+ &pll_audio1_div2_clk.common.hw,
573+ &pll_audio1_div5_clk.common.hw,
574+};
575+static SUNXI_CCU_MP_HW_WITH_MUX_GATE(spdif_rx_clk, "spdif-rx", spdif_rx_parents, 0xa28,
576+ 0, 5, /* M */
577+ 8, 2, /* P */
578+ 24, 3, /* mux */
579+ BIT(31), /* gate */
580+ 0);
581+
582+static SUNXI_CCU_GATE_HWS(bus_spdif_clk, "bus-spdif", apb0_hws,
583+ 0xa2c, BIT(0), 0);
584+
585+static const struct clk_hw *dmic_codec_parents[] = {
586+ &pll_audio0_clk.hw,
587+ &pll_audio1_div2_clk.common.hw,
588+ &pll_audio1_div5_clk.common.hw,
589+};
590+static SUNXI_CCU_MP_HW_WITH_MUX_GATE(dmic_clk, "dmic", dmic_codec_parents, 0xa40,
591+ 0, 5, /* M */
592+ 8, 2, /* P */
593+ 24, 3, /* mux */
594+ BIT(31), /* gate */
595+ 0);
596+
597+static SUNXI_CCU_GATE_HWS(bus_dmic_clk, "bus-dmic", apb0_hws,
598+ 0xa4c, BIT(0), 0);
599+
600+static SUNXI_CCU_MP_HW_WITH_MUX_GATE(audio_dac_clk, "audio-dac", dmic_codec_parents, 0xa50,
601+ 0, 5, /* M */
602+ 8, 2, /* P */
603+ 24, 3, /* mux */
604+ BIT(31), /* gate */
605+ 0);
606+
607+static SUNXI_CCU_MP_HW_WITH_MUX_GATE(audio_adc_clk, "audio-adc", dmic_codec_parents, 0xa54,
608+ 0, 5, /* M */
609+ 8, 2, /* P */
610+ 24, 3, /* mux */
611+ BIT(31), /* gate */
612+ 0);
613+
614+static SUNXI_CCU_GATE_HWS(bus_audio_clk, "bus-audio", apb0_hws,
615+ 0xa5c, BIT(0), 0);
616+
617+
618+/*
619+ * The first parent is a 48 MHz input clock divided by 4. That 48 MHz clock is
620+ * a 2x multiplier from osc24M synchronized by pll-periph0, and is also used by
621+ * the OHCI module.
622+ */
623+static const struct clk_parent_data usb_ohci_parents[] = {
624+ { .hw = &pll_periph0_clk.hw },
625+ { .fw_name = "hosc" },
626+ { .fw_name = "losc" },
627+};
628+static const struct ccu_mux_fixed_prediv usb_ohci_predivs[] = {
629+ { .index = 0, .div = 50 },
630+ { .index = 1, .div = 2 },
631+};
632+
633+static struct ccu_mux usb_ohci0_clk = {
634+ .enable = BIT(31),
635+ .mux = {
636+ .shift = 24,
637+ .width = 2,
638+ .fixed_predivs = usb_ohci_predivs,
639+ .n_predivs = ARRAY_SIZE(usb_ohci_predivs),
640+ },
641+ .common = {
642+ .reg = 0xa70,
643+ .features = CCU_FEATURE_FIXED_PREDIV,
644+ .hw.init = CLK_HW_INIT_PARENTS_DATA("usb-ohci0",
645+ usb_ohci_parents,
646+ &ccu_mux_ops,
647+ 0),
648+ },
649+};
650+
651+static struct ccu_mux usb_ohci1_clk = {
652+ .enable = BIT(31),
653+ .mux = {
654+ .shift = 24,
655+ .width = 2,
656+ .fixed_predivs = usb_ohci_predivs,
657+ .n_predivs = ARRAY_SIZE(usb_ohci_predivs),
658+ },
659+ .common = {
660+ .reg = 0xa74,
661+ .features = CCU_FEATURE_FIXED_PREDIV,
662+ .hw.init = CLK_HW_INIT_PARENTS_DATA("usb-ohci1",
663+ usb_ohci_parents,
664+ &ccu_mux_ops,
665+ 0),
666+ },
667+};
668+
669+static SUNXI_CCU_GATE_HWS(bus_ohci0_clk, "bus-ohci0", psi_ahb_hws,
670+ 0xa8c, BIT(0), 0);
671+static SUNXI_CCU_GATE_HWS(bus_ohci1_clk, "bus-ohci1", psi_ahb_hws,
672+ 0xa8c, BIT(1), 0);
673+static SUNXI_CCU_GATE_HWS(bus_ehci0_clk, "bus-ehci0", psi_ahb_hws,
674+ 0xa8c, BIT(4), 0);
675+static SUNXI_CCU_GATE_HWS(bus_ehci1_clk, "bus-ehci1", psi_ahb_hws,
676+ 0xa8c, BIT(5), 0);
677+static SUNXI_CCU_GATE_HWS(bus_otg_clk, "bus-otg", psi_ahb_hws,
678+ 0xa8c, BIT(8), 0);
679+
680+static SUNXI_CCU_GATE_HWS(bus_lradc_clk, "bus-lradc", apb0_hws,
681+ 0xa9c, BIT(0), 0);
682+
683+static SUNXI_CCU_GATE_HWS(bus_dpss_top_clk, "bus-dpss-top", psi_ahb_hws,
684+ 0xabc, BIT(0), 0);
685+
686+static SUNXI_CCU_GATE_DATA(hdmi_24M_clk, "hdmi-24M", osc24M,
687+ 0xb04, BIT(31), 0);
688+
689+static SUNXI_CCU_GATE_HWS_WITH_PREDIV(hdmi_cec_32k_clk, "hdmi-cec-32k",
690+ pll_periph0_2x_hws,
691+ 0xb10, BIT(30), 36621, 0);
692+
693+static const struct clk_parent_data hdmi_cec_parents[] = {
694+ { .fw_name = "losc" },
695+ { .hw = &hdmi_cec_32k_clk.common.hw },
696+};
697+static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_cec_clk, "hdmi-cec", hdmi_cec_parents, 0xb10,
698+ 24, 1, /* mux */
699+ BIT(31), /* gate */
700+ 0);
701+
702+static SUNXI_CCU_GATE_HWS(bus_hdmi_clk, "bus-hdmi", psi_ahb_hws,
703+ 0xb1c, BIT(0), 0);
704+
705+static const struct clk_parent_data mipi_dsi_parents[] = {
706+ { .fw_name = "hosc" },
707+ { .hw = &pll_periph0_clk.hw },
708+ { .hw = &pll_video0_2x_clk.hw },
709+ { .hw = &pll_video1_2x_clk.hw },
710+ { .hw = &pll_audio1_div2_clk.common.hw },
711+};
712+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", mipi_dsi_parents, 0xb24,
713+ 0, 4, /* M */
714+ 24, 3, /* mux */
715+ BIT(31), /* gate */
716+ CLK_SET_RATE_PARENT);
717+
718+static SUNXI_CCU_GATE_HWS(bus_mipi_dsi_clk, "bus-mipi-dsi", psi_ahb_hws,
719+ 0xb4c, BIT(0), 0);
720+
721+static const struct clk_hw *tcon_tve_parents[] = {
722+ &pll_video0_clk.hw,
723+ &pll_video0_4x_clk.common.hw,
724+ &pll_video1_clk.hw,
725+ &pll_video1_4x_clk.common.hw,
726+ &pll_periph0_2x_clk.common.hw,
727+ &pll_audio1_div2_clk.common.hw,
728+};
729+static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_tve_parents, 0xb60,
730+ 0, 4, /* M */
731+ 8, 2, /* P */
732+ 24, 3, /* mux */
733+ BIT(31), /* gate */
734+ CLK_SET_RATE_PARENT);
735+
736+static SUNXI_CCU_GATE_HWS(bus_tcon_lcd0_clk, "bus-tcon-lcd0", psi_ahb_hws,
737+ 0xb7c, BIT(0), 0);
738+
739+static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tcon_tv_clk, "tcon-tv", tcon_tve_parents, 0xb80,
740+ 0, 4, /* M */
741+ 8, 2, /* P */
742+ 24, 3, /* mux */
743+ BIT(31), /* gate */
744+ CLK_SET_RATE_PARENT);
745+
746+static SUNXI_CCU_GATE_HWS(bus_tcon_tv_clk, "bus-tcon-tv", psi_ahb_hws,
747+ 0xb9c, BIT(0), 0);
748+
749+static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tve_clk, "tve", tcon_tve_parents, 0xbb0,
750+ 0, 4, /* M */
751+ 8, 2, /* P */
752+ 24, 3, /* mux */
753+ BIT(31), /* gate */
754+ 0);
755+
756+static SUNXI_CCU_GATE_HWS(bus_tve_top_clk, "bus-tve-top", psi_ahb_hws,
757+ 0xbbc, BIT(0), 0);
758+static SUNXI_CCU_GATE_HWS(bus_tve_clk, "bus-tve", psi_ahb_hws,
759+ 0xbbc, BIT(1), 0);
760+
761+static const struct clk_parent_data tvd_parents[] = {
762+ { .fw_name = "hosc" },
763+ { .hw = &pll_video0_clk.hw },
764+ { .hw = &pll_video1_clk.hw },
765+ { .hw = &pll_periph0_clk.hw },
766+};
767+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(tvd_clk, "tvd", tvd_parents, 0xbc0,
768+ 0, 5, /* M */
769+ 24, 3, /* mux */
770+ BIT(31), /* gate */
771+ 0);
772+
773+static SUNXI_CCU_GATE_HWS(bus_tvd_top_clk, "bus-tvd-top", psi_ahb_hws,
774+ 0xbdc, BIT(0), 0);
775+static SUNXI_CCU_GATE_HWS(bus_tvd_clk, "bus-tvd", psi_ahb_hws,
776+ 0xbdc, BIT(1), 0);
777+
778+static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(ledc_clk, "ledc", ir_tx_ledc_parents, 0xbf0,
779+ 0, 4, /* M */
780+ 8, 2, /* P */
781+ 24, 1, /* mux */
782+ BIT(31), /* gate */
783+ 0);
784+
785+static SUNXI_CCU_GATE_HWS(bus_ledc_clk, "bus-ledc", psi_ahb_hws,
786+ 0xbfc, BIT(0), 0);
787+
788+static const struct clk_hw *csi_top_parents[] = {
789+ &pll_periph0_2x_clk.common.hw,
790+ &pll_video0_2x_clk.hw,
791+ &pll_video1_2x_clk.hw,
792+};
793+static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_top_clk, "csi-top", csi_top_parents, 0xc04,
794+ 0, 4, /* M */
795+ 24, 3, /* mux */
796+ BIT(31), /* gate */
797+ 0);
798+
799+static const struct clk_parent_data csi_mclk_parents[] = {
800+ { .fw_name = "hosc" },
801+ { .hw = &pll_periph0_clk.hw },
802+ { .hw = &pll_video0_clk.hw },
803+ { .hw = &pll_video1_clk.hw },
804+ { .hw = &pll_audio1_div2_clk.common.hw },
805+ { .hw = &pll_audio1_div5_clk.common.hw },
806+};
807+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents, 0xc08,
808+ 0, 5, /* M */
809+ 24, 3, /* mux */
810+ BIT(31), /* gate */
811+ 0);
812+
813+static SUNXI_CCU_GATE_HWS(bus_csi_clk, "bus-csi", psi_ahb_hws,
814+ 0xc1c, BIT(0), 0);
815+
816+static const struct clk_parent_data tpadc_parents[] = {
817+ { .fw_name = "hosc" },
818+ { .hw = &pll_audio0_clk.hw },
819+};
820+static SUNXI_CCU_MUX_DATA_WITH_GATE(tpadc_clk, "tpadc", tpadc_parents, 0xc50,
821+ 24, 3, /* mux */
822+ BIT(31), /* gate */
823+ 0);
824+
825+static SUNXI_CCU_GATE_HWS(bus_tpadc_clk, "bus-tpadc", apb0_hws,
826+ 0xc5c, BIT(0), 0);
827+
828+static SUNXI_CCU_GATE_HWS(bus_tzma_clk, "bus-tzma", apb0_hws,
829+ 0xc6c, BIT(0), 0);
830+
831+static const struct clk_parent_data dsp_parents[] = {
832+ { .fw_name = "hosc" },
833+ { .fw_name = "losc" },
834+ { .fw_name = "iosc" },
835+ { .hw = &pll_periph0_2x_clk.common.hw },
836+ { .hw = &pll_audio1_div2_clk.common.hw },
837+};
838+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(dsp_clk, "dsp", dsp_parents, 0xc70,
839+ 0, 5, /* M */
840+ 24, 3, /* mux */
841+ BIT(31), /* gate */
842+ 0);
843+
844+static SUNXI_CCU_GATE_HWS(bus_dsp_cfg_clk, "bus-dsp-cfg", psi_ahb_hws,
845+ 0xc7c, BIT(1), 0);
846+
847+/*
848+ * The RISC-V gate is not modelled - it is in a separate register (0xd04)
849+ * and has a special key field. The clock is critical anyway.
850+ */
851+static const struct clk_parent_data riscv_parents[] = {
852+ { .fw_name = "hosc" },
853+ { .fw_name = "losc" },
854+ { .fw_name = "iosc" },
855+ { .hw = &pll_periph0_800M_clk.common.hw },
856+ { .hw = &pll_periph0_clk.hw },
857+ { .hw = &pll_cpux_clk.common.hw },
858+ { .hw = &pll_audio1_div2_clk.common.hw },
859+};
860+static SUNXI_CCU_M_DATA_WITH_MUX(riscv_clk, "riscv", riscv_parents, 0xd00,
861+ 0, 5, /* M */
862+ 24, 3, /* mux */
863+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
864+
865+/* The riscv-axi clk must be divided by at least 2. */
866+static struct clk_div_table riscv_axi_table[] = {
867+ { .val = 1, .div = 2 },
868+ { .val = 2, .div = 3 },
869+ { .val = 3, .div = 4 },
870+ { /* Sentinel */ }
871+};
872+static SUNXI_CCU_DIV_TABLE_HW(riscv_axi_clk, "riscv-axi", &riscv_clk.common.hw,
873+ 0xd00, 8, 2, riscv_axi_table, 0);
874+
875+static SUNXI_CCU_GATE_HWS(bus_riscv_cfg_clk, "bus-riscv-cfg", psi_ahb_hws,
876+ 0xd0c, BIT(0), CLK_IS_CRITICAL);
877+
878+static SUNXI_CCU_GATE_DATA(fanout_24M_clk, "fanout-24M", osc24M,
879+ 0xf30, BIT(0), 0);
880+static SUNXI_CCU_GATE_DATA_WITH_PREDIV(fanout_12M_clk, "fanout-12M", osc24M,
881+ 0xf30, BIT(1), 2, 0);
882+static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M", pll_periph0_2x_hws,
883+ 0xf30, BIT(2), 75, 0);
884+static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M", pll_periph0_hws,
885+ 0xf30, BIT(3), 24, 0);
886+static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_32k_clk, "fanout-32k", pll_periph0_2x_hws,
887+ 0xf30, BIT(4), 36621, 0);
888+
889+/* This clock has a second divider that is not modelled and forced to 0. */
890+#define SUN20I_D1_FANOUT_27M_REG 0xf34
891+static const struct clk_hw *fanout_27M_parents[] = {
892+ &pll_video0_clk.hw,
893+ &pll_video1_clk.hw,
894+};
895+static SUNXI_CCU_M_HW_WITH_MUX_GATE(fanout_27M_clk, "fanout-27M", fanout_27M_parents, 0xf34,
896+ 0, 5, /* M */
897+ 24, 2, /* mux */
898+ BIT(31), /* gate */
899+ 0);
900+
901+static SUNXI_CCU_M_HWS_WITH_GATE(fanout_pclk_clk, "fanout-pclk", apb0_hws, 0xf38,
902+ 0, 5, /* M */
903+ BIT(31), /* gate */
904+ 0);
905+
906+static const struct clk_hw *fanout_parents[] = {
907+ &fanout_32k_clk.common.hw,
908+ &fanout_12M_clk.common.hw,
909+ &fanout_16M_clk.common.hw,
910+ &fanout_24M_clk.common.hw,
911+ &fanout_25M_clk.common.hw,
912+ &fanout_27M_clk.common.hw,
913+ &fanout_pclk_clk.common.hw,
914+};
915+static SUNXI_CCU_MUX_HW_WITH_GATE(fanout0_clk, "fanout0", fanout_parents, 0xf3c,
916+ 0, 3, /* mux */
917+ BIT(21), /* gate */
918+ 0);
919+static SUNXI_CCU_MUX_HW_WITH_GATE(fanout1_clk, "fanout1", fanout_parents, 0xf3c,
920+ 3, 3, /* mux */
921+ BIT(22), /* gate */
922+ 0);
923+static SUNXI_CCU_MUX_HW_WITH_GATE(fanout2_clk, "fanout2", fanout_parents, 0xf3c,
924+ 6, 3, /* mux */
925+ BIT(23), /* gate */
926+ 0);
927+
928+static struct ccu_common *sun20i_d1_ccu_clks[] = {
929+ &pll_cpux_clk.common,
930+ &pll_ddr0_clk.common,
931+ &pll_periph0_4x_clk.common,
932+ &pll_periph0_2x_clk.common,
933+ &pll_periph0_800M_clk.common,
934+ &pll_video0_4x_clk.common,
935+ &pll_video1_4x_clk.common,
936+ &pll_ve_clk.common,
937+ &pll_audio0_4x_clk.common,
938+ &pll_audio1_clk.common,
939+ &pll_audio1_div2_clk.common,
940+ &pll_audio1_div5_clk.common,
941+ &cpux_clk.common,
942+ &cpux_axi_clk.common,
943+ &cpux_apb_clk.common,
944+ &psi_ahb_clk.common,
945+ &apb0_clk.common,
946+ &apb1_clk.common,
947+ &de_clk.common,
948+ &bus_de_clk.common,
949+ &di_clk.common,
950+ &bus_di_clk.common,
951+ &g2d_clk.common,
952+ &bus_g2d_clk.common,
953+ &ce_clk.common,
954+ &bus_ce_clk.common,
955+ &ve_clk.common,
956+ &bus_ve_clk.common,
957+ &bus_dma_clk.common,
958+ &bus_msgbox0_clk.common,
959+ &bus_msgbox1_clk.common,
960+ &bus_msgbox2_clk.common,
961+ &bus_spinlock_clk.common,
962+ &bus_hstimer_clk.common,
963+ &avs_clk.common,
964+ &bus_dbg_clk.common,
965+ &bus_pwm_clk.common,
966+ &bus_iommu_clk.common,
967+ &dram_clk.common,
968+ &mbus_dma_clk.common,
969+ &mbus_ve_clk.common,
970+ &mbus_ce_clk.common,
971+ &mbus_tvin_clk.common,
972+ &mbus_csi_clk.common,
973+ &mbus_g2d_clk.common,
974+ &mbus_riscv_clk.common,
975+ &bus_dram_clk.common,
976+ &mmc0_clk.common,
977+ &mmc1_clk.common,
978+ &mmc2_clk.common,
979+ &bus_mmc0_clk.common,
980+ &bus_mmc1_clk.common,
981+ &bus_mmc2_clk.common,
982+ &bus_uart0_clk.common,
983+ &bus_uart1_clk.common,
984+ &bus_uart2_clk.common,
985+ &bus_uart3_clk.common,
986+ &bus_uart4_clk.common,
987+ &bus_uart5_clk.common,
988+ &bus_i2c0_clk.common,
989+ &bus_i2c1_clk.common,
990+ &bus_i2c2_clk.common,
991+ &bus_i2c3_clk.common,
992+ &spi0_clk.common,
993+ &spi1_clk.common,
994+ &bus_spi0_clk.common,
995+ &bus_spi1_clk.common,
996+ &emac_25M_clk.common,
997+ &bus_emac_clk.common,
998+ &ir_tx_clk.common,
999+ &bus_ir_tx_clk.common,
1000+ &bus_gpadc_clk.common,
1001+ &bus_ths_clk.common,
1002+ &i2s0_clk.common,
1003+ &i2s1_clk.common,
1004+ &i2s2_clk.common,
1005+ &i2s2_asrc_clk.common,
1006+ &bus_i2s0_clk.common,
1007+ &bus_i2s1_clk.common,
1008+ &bus_i2s2_clk.common,
1009+ &spdif_tx_clk.common,
1010+ &spdif_rx_clk.common,
1011+ &bus_spdif_clk.common,
1012+ &dmic_clk.common,
1013+ &bus_dmic_clk.common,
1014+ &audio_dac_clk.common,
1015+ &audio_adc_clk.common,
1016+ &bus_audio_clk.common,
1017+ &usb_ohci0_clk.common,
1018+ &usb_ohci1_clk.common,
1019+ &bus_ohci0_clk.common,
1020+ &bus_ohci1_clk.common,
1021+ &bus_ehci0_clk.common,
1022+ &bus_ehci1_clk.common,
1023+ &bus_otg_clk.common,
1024+ &bus_lradc_clk.common,
1025+ &bus_dpss_top_clk.common,
1026+ &hdmi_24M_clk.common,
1027+ &hdmi_cec_32k_clk.common,
1028+ &hdmi_cec_clk.common,
1029+ &bus_hdmi_clk.common,
1030+ &mipi_dsi_clk.common,
1031+ &bus_mipi_dsi_clk.common,
1032+ &tcon_lcd0_clk.common,
1033+ &bus_tcon_lcd0_clk.common,
1034+ &tcon_tv_clk.common,
1035+ &bus_tcon_tv_clk.common,
1036+ &tve_clk.common,
1037+ &bus_tve_top_clk.common,
1038+ &bus_tve_clk.common,
1039+ &tvd_clk.common,
1040+ &bus_tvd_top_clk.common,
1041+ &bus_tvd_clk.common,
1042+ &ledc_clk.common,
1043+ &bus_ledc_clk.common,
1044+ &csi_top_clk.common,
1045+ &csi_mclk_clk.common,
1046+ &bus_csi_clk.common,
1047+ &tpadc_clk.common,
1048+ &bus_tpadc_clk.common,
1049+ &bus_tzma_clk.common,
1050+ &dsp_clk.common,
1051+ &bus_dsp_cfg_clk.common,
1052+ &riscv_clk.common,
1053+ &riscv_axi_clk.common,
1054+ &bus_riscv_cfg_clk.common,
1055+ &fanout_24M_clk.common,
1056+ &fanout_12M_clk.common,
1057+ &fanout_16M_clk.common,
1058+ &fanout_25M_clk.common,
1059+ &fanout_32k_clk.common,
1060+ &fanout_27M_clk.common,
1061+ &fanout_pclk_clk.common,
1062+ &fanout0_clk.common,
1063+ &fanout1_clk.common,
1064+ &fanout2_clk.common,
1065+};
1066+
1067+static struct clk_hw_onecell_data sun20i_d1_hw_clks = {
1068+ .num = CLK_NUMBER,
1069+ .hws = {
1070+ [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
1071+ [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
1072+ [CLK_PLL_PERIPH0_4X] = &pll_periph0_4x_clk.common.hw,
1073+ [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.common.hw,
1074+ [CLK_PLL_PERIPH0_800M] = &pll_periph0_800M_clk.common.hw,
1075+ [CLK_PLL_PERIPH0] = &pll_periph0_clk.hw,
1076+ [CLK_PLL_PERIPH0_DIV3] = &pll_periph0_div3_clk.hw,
1077+ [CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.common.hw,
1078+ [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
1079+ [CLK_PLL_VIDEO0] = &pll_video0_clk.hw,
1080+ [CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.common.hw,
1081+ [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
1082+ [CLK_PLL_VIDEO1] = &pll_video1_clk.hw,
1083+ [CLK_PLL_VE] = &pll_ve_clk.common.hw,
1084+ [CLK_PLL_AUDIO0_4X] = &pll_audio0_4x_clk.common.hw,
1085+ [CLK_PLL_AUDIO0_2X] = &pll_audio0_2x_clk.hw,
1086+ [CLK_PLL_AUDIO0] = &pll_audio0_clk.hw,
1087+ [CLK_PLL_AUDIO1] = &pll_audio1_clk.common.hw,
1088+ [CLK_PLL_AUDIO1_DIV2] = &pll_audio1_div2_clk.common.hw,
1089+ [CLK_PLL_AUDIO1_DIV5] = &pll_audio1_div5_clk.common.hw,
1090+ [CLK_CPUX] = &cpux_clk.common.hw,
1091+ [CLK_CPUX_AXI] = &cpux_axi_clk.common.hw,
1092+ [CLK_CPUX_APB] = &cpux_apb_clk.common.hw,
1093+ [CLK_PSI_AHB] = &psi_ahb_clk.common.hw,
1094+ [CLK_APB0] = &apb0_clk.common.hw,
1095+ [CLK_APB1] = &apb1_clk.common.hw,
1096+ [CLK_MBUS] = &mbus_clk.hw,
1097+ [CLK_DE] = &de_clk.common.hw,
1098+ [CLK_BUS_DE] = &bus_de_clk.common.hw,
1099+ [CLK_DI] = &di_clk.common.hw,
1100+ [CLK_BUS_DI] = &bus_di_clk.common.hw,
1101+ [CLK_G2D] = &g2d_clk.common.hw,
1102+ [CLK_BUS_G2D] = &bus_g2d_clk.common.hw,
1103+ [CLK_CE] = &ce_clk.common.hw,
1104+ [CLK_BUS_CE] = &bus_ce_clk.common.hw,
1105+ [CLK_VE] = &ve_clk.common.hw,
1106+ [CLK_BUS_VE] = &bus_ve_clk.common.hw,
1107+ [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
1108+ [CLK_BUS_MSGBOX0] = &bus_msgbox0_clk.common.hw,
1109+ [CLK_BUS_MSGBOX1] = &bus_msgbox1_clk.common.hw,
1110+ [CLK_BUS_MSGBOX2] = &bus_msgbox2_clk.common.hw,
1111+ [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
1112+ [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
1113+ [CLK_AVS] = &avs_clk.common.hw,
1114+ [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
1115+ [CLK_BUS_PWM] = &bus_pwm_clk.common.hw,
1116+ [CLK_BUS_IOMMU] = &bus_iommu_clk.common.hw,
1117+ [CLK_DRAM] = &dram_clk.common.hw,
1118+ [CLK_MBUS_DMA] = &mbus_dma_clk.common.hw,
1119+ [CLK_MBUS_VE] = &mbus_ve_clk.common.hw,
1120+ [CLK_MBUS_CE] = &mbus_ce_clk.common.hw,
1121+ [CLK_MBUS_TVIN] = &mbus_tvin_clk.common.hw,
1122+ [CLK_MBUS_CSI] = &mbus_csi_clk.common.hw,
1123+ [CLK_MBUS_G2D] = &mbus_g2d_clk.common.hw,
1124+ [CLK_MBUS_RISCV] = &mbus_riscv_clk.common.hw,
1125+ [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
1126+ [CLK_MMC0] = &mmc0_clk.common.hw,
1127+ [CLK_MMC1] = &mmc1_clk.common.hw,
1128+ [CLK_MMC2] = &mmc2_clk.common.hw,
1129+ [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
1130+ [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
1131+ [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
1132+ [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
1133+ [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
1134+ [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
1135+ [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
1136+ [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
1137+ [CLK_BUS_UART5] = &bus_uart5_clk.common.hw,
1138+ [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
1139+ [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
1140+ [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
1141+ [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
1142+ [CLK_SPI0] = &spi0_clk.common.hw,
1143+ [CLK_SPI1] = &spi1_clk.common.hw,
1144+ [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
1145+ [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
1146+ [CLK_EMAC_25M] = &emac_25M_clk.common.hw,
1147+ [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
1148+ [CLK_IR_TX] = &ir_tx_clk.common.hw,
1149+ [CLK_BUS_IR_TX] = &bus_ir_tx_clk.common.hw,
1150+ [CLK_BUS_GPADC] = &bus_gpadc_clk.common.hw,
1151+ [CLK_BUS_THS] = &bus_ths_clk.common.hw,
1152+ [CLK_I2S0] = &i2s0_clk.common.hw,
1153+ [CLK_I2S1] = &i2s1_clk.common.hw,
1154+ [CLK_I2S2] = &i2s2_clk.common.hw,
1155+ [CLK_I2S2_ASRC] = &i2s2_asrc_clk.common.hw,
1156+ [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
1157+ [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
1158+ [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
1159+ [CLK_SPDIF_TX] = &spdif_tx_clk.common.hw,
1160+ [CLK_SPDIF_RX] = &spdif_rx_clk.common.hw,
1161+ [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
1162+ [CLK_DMIC] = &dmic_clk.common.hw,
1163+ [CLK_BUS_DMIC] = &bus_dmic_clk.common.hw,
1164+ [CLK_AUDIO_DAC] = &audio_dac_clk.common.hw,
1165+ [CLK_AUDIO_ADC] = &audio_adc_clk.common.hw,
1166+ [CLK_BUS_AUDIO] = &bus_audio_clk.common.hw,
1167+ [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
1168+ [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
1169+ [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
1170+ [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
1171+ [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
1172+ [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
1173+ [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
1174+ [CLK_BUS_LRADC] = &bus_lradc_clk.common.hw,
1175+ [CLK_BUS_DPSS_TOP] = &bus_dpss_top_clk.common.hw,
1176+ [CLK_HDMI_24M] = &hdmi_24M_clk.common.hw,
1177+ [CLK_HDMI_CEC_32K] = &hdmi_cec_32k_clk.common.hw,
1178+ [CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw,
1179+ [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
1180+ [CLK_MIPI_DSI] = &mipi_dsi_clk.common.hw,
1181+ [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
1182+ [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw,
1183+ [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw,
1184+ [CLK_TCON_TV] = &tcon_tv_clk.common.hw,
1185+ [CLK_BUS_TCON_TV] = &bus_tcon_tv_clk.common.hw,
1186+ [CLK_TVE] = &tve_clk.common.hw,
1187+ [CLK_BUS_TVE_TOP] = &bus_tve_top_clk.common.hw,
1188+ [CLK_BUS_TVE] = &bus_tve_clk.common.hw,
1189+ [CLK_TVD] = &tvd_clk.common.hw,
1190+ [CLK_BUS_TVD_TOP] = &bus_tvd_top_clk.common.hw,
1191+ [CLK_BUS_TVD] = &bus_tvd_clk.common.hw,
1192+ [CLK_LEDC] = &ledc_clk.common.hw,
1193+ [CLK_BUS_LEDC] = &bus_ledc_clk.common.hw,
1194+ [CLK_CSI_TOP] = &csi_top_clk.common.hw,
1195+ [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
1196+ [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
1197+ [CLK_TPADC] = &tpadc_clk.common.hw,
1198+ [CLK_BUS_TPADC] = &bus_tpadc_clk.common.hw,
1199+ [CLK_BUS_TZMA] = &bus_tzma_clk.common.hw,
1200+ [CLK_DSP] = &dsp_clk.common.hw,
1201+ [CLK_BUS_DSP_CFG] = &bus_dsp_cfg_clk.common.hw,
1202+ [CLK_RISCV] = &riscv_clk.common.hw,
1203+ [CLK_RISCV_AXI] = &riscv_axi_clk.common.hw,
1204+ [CLK_BUS_RISCV_CFG] = &bus_riscv_cfg_clk.common.hw,
1205+ [CLK_FANOUT_24M] = &fanout_24M_clk.common.hw,
1206+ [CLK_FANOUT_12M] = &fanout_12M_clk.common.hw,
1207+ [CLK_FANOUT_16M] = &fanout_16M_clk.common.hw,
1208+ [CLK_FANOUT_25M] = &fanout_25M_clk.common.hw,
1209+ [CLK_FANOUT_32K] = &fanout_32k_clk.common.hw,
1210+ [CLK_FANOUT_27M] = &fanout_27M_clk.common.hw,
1211+ [CLK_FANOUT_PCLK] = &fanout_pclk_clk.common.hw,
1212+ [CLK_FANOUT0] = &fanout0_clk.common.hw,
1213+ [CLK_FANOUT1] = &fanout1_clk.common.hw,
1214+ [CLK_FANOUT2] = &fanout2_clk.common.hw,
1215+ },
1216+};
1217+
1218+static struct ccu_reset_map sun20i_d1_ccu_resets[] = {
1219+ [RST_MBUS] = { 0x540, BIT(30) },
1220+ [RST_BUS_DE] = { 0x60c, BIT(16) },
1221+ [RST_BUS_DI] = { 0x62c, BIT(16) },
1222+ [RST_BUS_G2D] = { 0x63c, BIT(16) },
1223+ [RST_BUS_CE] = { 0x68c, BIT(16) },
1224+ [RST_BUS_VE] = { 0x69c, BIT(16) },
1225+ [RST_BUS_DMA] = { 0x70c, BIT(16) },
1226+ [RST_BUS_MSGBOX0] = { 0x71c, BIT(16) },
1227+ [RST_BUS_MSGBOX1] = { 0x71c, BIT(17) },
1228+ [RST_BUS_MSGBOX2] = { 0x71c, BIT(18) },
1229+ [RST_BUS_SPINLOCK] = { 0x72c, BIT(16) },
1230+ [RST_BUS_HSTIMER] = { 0x73c, BIT(16) },
1231+ [RST_BUS_DBG] = { 0x78c, BIT(16) },
1232+ [RST_BUS_PWM] = { 0x7ac, BIT(16) },
1233+ [RST_BUS_DRAM] = { 0x80c, BIT(16) },
1234+ [RST_BUS_MMC0] = { 0x84c, BIT(16) },
1235+ [RST_BUS_MMC1] = { 0x84c, BIT(17) },
1236+ [RST_BUS_MMC2] = { 0x84c, BIT(18) },
1237+ [RST_BUS_UART0] = { 0x90c, BIT(16) },
1238+ [RST_BUS_UART1] = { 0x90c, BIT(17) },
1239+ [RST_BUS_UART2] = { 0x90c, BIT(18) },
1240+ [RST_BUS_UART3] = { 0x90c, BIT(19) },
1241+ [RST_BUS_UART4] = { 0x90c, BIT(20) },
1242+ [RST_BUS_UART5] = { 0x90c, BIT(21) },
1243+ [RST_BUS_I2C0] = { 0x91c, BIT(16) },
1244+ [RST_BUS_I2C1] = { 0x91c, BIT(17) },
1245+ [RST_BUS_I2C2] = { 0x91c, BIT(18) },
1246+ [RST_BUS_I2C3] = { 0x91c, BIT(19) },
1247+ [RST_BUS_SPI0] = { 0x96c, BIT(16) },
1248+ [RST_BUS_SPI1] = { 0x96c, BIT(17) },
1249+ [RST_BUS_EMAC] = { 0x97c, BIT(16) },
1250+ [RST_BUS_IR_TX] = { 0x9cc, BIT(16) },
1251+ [RST_BUS_GPADC] = { 0x9ec, BIT(16) },
1252+ [RST_BUS_THS] = { 0x9fc, BIT(16) },
1253+ [RST_BUS_I2S0] = { 0xa20, BIT(16) },
1254+ [RST_BUS_I2S1] = { 0xa20, BIT(17) },
1255+ [RST_BUS_I2S2] = { 0xa20, BIT(18) },
1256+ [RST_BUS_SPDIF] = { 0xa2c, BIT(16) },
1257+ [RST_BUS_DMIC] = { 0xa4c, BIT(16) },
1258+ [RST_BUS_AUDIO] = { 0xa5c, BIT(16) },
1259+ [RST_USB_PHY0] = { 0xa70, BIT(30) },
1260+ [RST_USB_PHY1] = { 0xa74, BIT(30) },
1261+ [RST_BUS_OHCI0] = { 0xa8c, BIT(16) },
1262+ [RST_BUS_OHCI1] = { 0xa8c, BIT(17) },
1263+ [RST_BUS_EHCI0] = { 0xa8c, BIT(20) },
1264+ [RST_BUS_EHCI1] = { 0xa8c, BIT(21) },
1265+ [RST_BUS_OTG] = { 0xa8c, BIT(24) },
1266+ [RST_BUS_LRADC] = { 0xa9c, BIT(16) },
1267+ [RST_BUS_DPSS_TOP] = { 0xabc, BIT(16) },
1268+ [RST_BUS_HDMI_MAIN] = { 0xb1c, BIT(16) },
1269+ [RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) },
1270+ [RST_BUS_MIPI_DSI] = { 0xb4c, BIT(16) },
1271+ [RST_BUS_TCON_LCD0] = { 0xb7c, BIT(16) },
1272+ [RST_BUS_TCON_TV] = { 0xb9c, BIT(16) },
1273+ [RST_BUS_LVDS0] = { 0xbac, BIT(16) },
1274+ [RST_BUS_TVE_TOP] = { 0xbbc, BIT(16) },
1275+ [RST_BUS_TVE] = { 0xbbc, BIT(17) },
1276+ [RST_BUS_TVD_TOP] = { 0xbdc, BIT(16) },
1277+ [RST_BUS_TVD] = { 0xbdc, BIT(17) },
1278+ [RST_BUS_LEDC] = { 0xbfc, BIT(16) },
1279+ [RST_BUS_CSI] = { 0xc1c, BIT(16) },
1280+ [RST_BUS_TPADC] = { 0xc5c, BIT(16) },
1281+ [RST_DSP] = { 0xc7c, BIT(16) },
1282+ [RST_BUS_DSP_CFG] = { 0xc7c, BIT(17) },
1283+ [RST_BUS_DSP_DBG] = { 0xc7c, BIT(18) },
1284+ [RST_BUS_RISCV_CFG] = { 0xd0c, BIT(16) },
1285+};
1286+
1287+static const struct sunxi_ccu_desc sun20i_d1_ccu_desc = {
1288+ .ccu_clks = sun20i_d1_ccu_clks,
1289+ .num_ccu_clks = ARRAY_SIZE(sun20i_d1_ccu_clks),
1290+
1291+ .hw_clks = &sun20i_d1_hw_clks,
1292+
1293+ .resets = sun20i_d1_ccu_resets,
1294+ .num_resets = ARRAY_SIZE(sun20i_d1_ccu_resets),
1295+};
1296+
1297+static const u32 pll_regs[] = {
1298+ SUN20I_D1_PLL_CPUX_REG,
1299+ SUN20I_D1_PLL_DDR0_REG,
1300+ SUN20I_D1_PLL_PERIPH0_REG,
1301+ SUN20I_D1_PLL_VIDEO0_REG,
1302+ SUN20I_D1_PLL_VIDEO1_REG,
1303+ SUN20I_D1_PLL_VE_REG,
1304+ SUN20I_D1_PLL_AUDIO0_REG,
1305+ SUN20I_D1_PLL_AUDIO1_REG,
1306+};
1307+
1308+static const u32 pll_video_regs[] = {
1309+ SUN20I_D1_PLL_VIDEO0_REG,
1310+ SUN20I_D1_PLL_VIDEO1_REG,
1311+};
1312+
1313+static struct ccu_mux_nb sun20i_d1_riscv_nb = {
1314+ .common = &riscv_clk.common,
1315+ .cm = &riscv_clk.mux,
1316+ .delay_us = 1,
1317+ .bypass_index = 4, /* index of pll-periph0 */
1318+};
1319+
1320+static int sun20i_d1_ccu_probe(struct platform_device *pdev)
1321+{
1322+ void __iomem *reg;
1323+ u32 val;
1324+ int i, ret;
1325+
1326+ reg = devm_platform_ioremap_resource(pdev, 0);
1327+ if (IS_ERR(reg))
1328+ return PTR_ERR(reg);
1329+
1330+ /* Enable the enable, LDO, and lock bits on all PLLs. */
1331+ for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
1332+ val = readl(reg + pll_regs[i]);
1333+ val |= BIT(31) | BIT(30) | BIT(29);
1334+ writel(val, reg + pll_regs[i]);
1335+ }
1336+
1337+ /* Force PLL_CPUX factor M to 0. */
1338+ val = readl(reg + SUN20I_D1_PLL_CPUX_REG);
1339+ val &= ~GENMASK(1, 0);
1340+ writel(val, reg + SUN20I_D1_PLL_CPUX_REG);
1341+
1342+ /*
1343+ * Force the output divider of video PLLs to 0.
1344+ *
1345+ * See the comment before pll-video0 definition for the reason.
1346+ */
1347+ for (i = 0; i < ARRAY_SIZE(pll_video_regs); i++) {
1348+ val = readl(reg + pll_video_regs[i]);
1349+ val &= ~BIT(0);
1350+ writel(val, reg + pll_video_regs[i]);
1351+ }
1352+
1353+ /* Enforce m1 = 0, m0 = 0 for PLL_AUDIO0 */
1354+ val = readl(reg + SUN20I_D1_PLL_AUDIO0_REG);
1355+ val &= ~BIT(1) | BIT(0);
1356+ writel(val, reg + SUN20I_D1_PLL_AUDIO0_REG);
1357+
1358+ /* Force fanout-27M factor N to 0. */
1359+ val = readl(reg + SUN20I_D1_FANOUT_27M_REG);
1360+ val &= ~GENMASK(9, 8);
1361+ writel(val, reg + SUN20I_D1_FANOUT_27M_REG);
1362+
1363+ ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun20i_d1_ccu_desc);
1364+ if (ret)
1365+ return ret;
1366+
1367+ /* Reparent CPU during PLL CPUX rate changes */
1368+ ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
1369+ &sun20i_d1_riscv_nb);
1370+
1371+ return 0;
1372+}
1373+
1374+static const struct of_device_id sun20i_d1_ccu_ids[] = {
1375+ { .compatible = "allwinner,sun20i-d1-ccu" },
1376+ { }
1377+};
1378+
1379+static struct platform_driver sun20i_d1_ccu_driver = {
1380+ .probe = sun20i_d1_ccu_probe,
1381+ .driver = {
1382+ .name = "sun20i-d1-ccu",
1383+ .suppress_bind_attrs = true,
1384+ .of_match_table = sun20i_d1_ccu_ids,
1385+ },
1386+};
1387+module_platform_driver(sun20i_d1_ccu_driver);
1388+
1389+MODULE_IMPORT_NS(SUNXI_CCU);
1390+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu-sun20i-d1.h+15−0
@@ -0,0 +1,15 @@
1+/* SPDX-License-Identifier: GPL-2.0 */
2+/*
3+ * Copyright (c) 2020 frank@allwinnertech.com
4+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
5+ */
6+
7+#ifndef _CCU_SUN20I_D1_H_
8+#define _CCU_SUN20I_D1_H_
9+
10+#include <dt-bindings/clock/sun20i-d1-ccu.h>
11+#include <dt-bindings/reset/sun20i-d1-ccu.h>
12+
13+#define CLK_NUMBER (CLK_FANOUT2 + 1)
14+
15+#endif /* _CCU_SUN20I_D1_H_ */
drivers/clk/sunxi-ng/ccu-sun4i-a10.c+36−22
@@ -7,7 +7,9 @@ · 6 unmodified lines
77
88 #include <linux/clk-provider.h>
99 #include <linux/io.h>
10−#include <linux/of_address.h>
10+#include <linux/module.h>
11+#include <linux/of_device.h>
12+#include <linux/platform_device.h>
1113
1214 #include "ccu_common.h"
1315 #include "ccu_reset.h"
@@ -1425,18 +1427,19 @@ static const struct sunxi_ccu_desc sun7i_a20_ccu_desc = { · 1411 unmodified lines
14251427 .num_resets = ARRAY_SIZE(sunxi_a10_a20_ccu_resets),
14261428 };
14271429
1428−static void __init sun4i_ccu_init(struct device_node *node,
1429− const struct sunxi_ccu_desc *desc)
1430+static int sun4i_a10_ccu_probe(struct platform_device *pdev)
14301431 {
1432+ const struct sunxi_ccu_desc *desc;
14311433 void __iomem *reg;
14321434 u32 val;
14331435
1434− reg = of_io_request_and_map(node, 0, of_node_full_name(node));
1435− if (IS_ERR(reg)) {
1436− pr_err("%s: Could not map the clock registers\n",
1437− of_node_full_name(node));
1438− return;
1439− }
1436+ desc = of_device_get_match_data(&pdev->dev);
1437+ if (!desc)
1438+ return -EINVAL;
1439+
1440+ reg = devm_platform_ioremap_resource(pdev, 0);
1441+ if (IS_ERR(reg))
1442+ return PTR_ERR(reg);
14401443
14411444 val = readl(reg + SUN4I_PLL_AUDIO_REG);
14421445
@@ -1464,19 +1467,30 @@ static void __init sun4i_ccu_init(struct device_node *node, · 21 unmodified lines
14641467 val &= ~GENMASK(7, 6);
14651468 writel(val | (2 << 6), reg + SUN4I_AHB_REG);
14661469
1467− of_sunxi_ccu_probe(node, reg, desc);
1470+ return devm_sunxi_ccu_probe(&pdev->dev, reg, desc);
14681471 }
14691472
1470−static void __init sun4i_a10_ccu_setup(struct device_node *node)
1471−{
1472− sun4i_ccu_init(node, &sun4i_a10_ccu_desc);
1473−}
1474−CLK_OF_DECLARE(sun4i_a10_ccu, "allwinner,sun4i-a10-ccu",
1475− sun4i_a10_ccu_setup);
1473+static const struct of_device_id sun4i_a10_ccu_ids[] = {
1474+ {
1475+ .compatible = "allwinner,sun4i-a10-ccu",
1476+ .data = &sun4i_a10_ccu_desc,
1477+ },
1478+ {
1479+ .compatible = "allwinner,sun7i-a20-ccu",
1480+ .data = &sun7i_a20_ccu_desc,
1481+ },
1482+ { }
1483+};
14761484
1477−static void __init sun7i_a20_ccu_setup(struct device_node *node)
1478−{
1479− sun4i_ccu_init(node, &sun7i_a20_ccu_desc);
1480−}
1481−CLK_OF_DECLARE(sun7i_a20_ccu, "allwinner,sun7i-a20-ccu",
1482− sun7i_a20_ccu_setup);
1485+static struct platform_driver sun4i_a10_ccu_driver = {
1486+ .probe = sun4i_a10_ccu_probe,
1487+ .driver = {
1488+ .name = "sun4i-a10-ccu",
1489+ .suppress_bind_attrs = true,
1490+ .of_match_table = sun4i_a10_ccu_ids,
1491+ },
1492+};
1493+module_platform_driver(sun4i_a10_ccu_driver);
1494+
1495+MODULE_IMPORT_NS(SUNXI_CCU);
1496+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c+3−1
@@ -5,7 +5,6 @@ · 4 unmodified lines
55
66 #include <linux/clk-provider.h>
77 #include <linux/module.h>
8−#include <linux/of_address.h>
98 #include <linux/platform_device.h>
109
1110 #include "ccu_common.h"
@@ -213,3 +212,6 @@ static struct platform_driver sun50i_a100_r_ccu_driver = { · 201 unmodified lines
213212 },
214213 };
215214 module_platform_driver(sun50i_a100_r_ccu_driver);
215+
216+MODULE_IMPORT_NS(SUNXI_CCU);
217+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu-sun50i-a100.c+3−1
@@ -6,7 +6,6 @@ · 5 unmodified lines
66 #include <linux/clk-provider.h>
77 #include <linux/io.h>
88 #include <linux/module.h>
9−#include <linux/of_address.h>
109 #include <linux/platform_device.h>
1110
1211 #include "ccu_common.h"
@@ -1275,3 +1274,6 @@ static struct platform_driver sun50i_a100_ccu_driver = { · 1262 unmodified lines
12751274 },
12761275 };
12771276 module_platform_driver(sun50i_a100_ccu_driver);
1277+
1278+MODULE_IMPORT_NS(SUNXI_CCU);
1279+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu-sun50i-a64.c+5−2
@@ -5,7 +5,7 @@ · 4 unmodified lines
55
66 #include <linux/clk-provider.h>
77 #include <linux/io.h>
8−#include <linux/of_address.h>
8+#include <linux/module.h>
99 #include <linux/platform_device.h>
1010
1111 #include "ccu_common.h"
@@ -980,4 +980,7 @@ static struct platform_driver sun50i_a64_ccu_driver = { · 968 unmodified lines
980980 .of_match_table = sun50i_a64_ccu_ids,
981981 },
982982 };
983−builtin_platform_driver(sun50i_a64_ccu_driver);
983+module_platform_driver(sun50i_a64_ccu_driver);
984+
985+MODULE_IMPORT_NS(SUNXI_CCU);
986+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c+35−21
@@ -4,7 +4,8 @@ · 3 unmodified lines
44 */
55
66 #include <linux/clk-provider.h>
7−#include <linux/of_address.h>
7+#include <linux/module.h>
8+#include <linux/of_device.h>
89 #include <linux/platform_device.h>
910
1011 #include "ccu_common.h"
@@ -221,30 +222,43 @@ static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = { · 210 unmodified lines
221222 .num_resets = ARRAY_SIZE(sun50i_h616_r_ccu_resets),
222223 };
223224
224−static void __init sunxi_r_ccu_init(struct device_node *node,
225− const struct sunxi_ccu_desc *desc)
225+static int sun50i_h6_r_ccu_probe(struct platform_device *pdev)
226226 {
227+ const struct sunxi_ccu_desc *desc;
227228 void __iomem *reg;
228229
229− reg = of_io_request_and_map(node, 0, of_node_full_name(node));
230− if (IS_ERR(reg)) {
231− pr_err("%pOF: Could not map the clock registers\n", node);
232− return;
233− }
230+ desc = of_device_get_match_data(&pdev->dev);
231+ if (!desc)
232+ return -EINVAL;
234233
235− of_sunxi_ccu_probe(node, reg, desc);
236−}
234+ reg = devm_platform_ioremap_resource(pdev, 0);
235+ if (IS_ERR(reg))
236+ return PTR_ERR(reg);
237237
238−static void __init sun50i_h6_r_ccu_setup(struct device_node *node)
239−{
240− sunxi_r_ccu_init(node, &sun50i_h6_r_ccu_desc);
238+ return devm_sunxi_ccu_probe(&pdev->dev, reg, desc);
241239 }
242−CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu",
243− sun50i_h6_r_ccu_setup);
244240
245−static void __init sun50i_h616_r_ccu_setup(struct device_node *node)
246−{
247− sunxi_r_ccu_init(node, &sun50i_h616_r_ccu_desc);
248−}
249−CLK_OF_DECLARE(sun50i_h616_r_ccu, "allwinner,sun50i-h616-r-ccu",
250− sun50i_h616_r_ccu_setup);
241+static const struct of_device_id sun50i_h6_r_ccu_ids[] = {
242+ {
243+ .compatible = "allwinner,sun50i-h6-r-ccu",
244+ .data = &sun50i_h6_r_ccu_desc,
245+ },
246+ {
247+ .compatible = "allwinner,sun50i-h616-r-ccu",
248+ .data = &sun50i_h616_r_ccu_desc,
249+ },
250+ { }
251+};
252+
253+static struct platform_driver sun50i_h6_r_ccu_driver = {
254+ .probe = sun50i_h6_r_ccu_probe,
255+ .driver = {
256+ .name = "sun50i-h6-r-ccu",
257+ .suppress_bind_attrs = true,
258+ .of_match_table = sun50i_h6_r_ccu_ids,
259+ },
260+};
261+module_platform_driver(sun50i_h6_r_ccu_driver);
262+
263+MODULE_IMPORT_NS(SUNXI_CCU);
264+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu-sun50i-h6.c+5−2
@@ -5,7 +5,7 @@ · 4 unmodified lines
55
66 #include <linux/clk-provider.h>
77 #include <linux/io.h>
8−#include <linux/of_address.h>
8+#include <linux/module.h>
99 #include <linux/platform_device.h>
1010
1111 #include "ccu_common.h"
@@ -1254,4 +1254,7 @@ static struct platform_driver sun50i_h6_ccu_driver = { · 1242 unmodified lines
12541254 .of_match_table = sun50i_h6_ccu_ids,
12551255 },
12561256 };
1257−builtin_platform_driver(sun50i_h6_ccu_driver);
1257+module_platform_driver(sun50i_h6_ccu_driver);
1258+
1259+MODULE_IMPORT_NS(SUNXI_CCU);
1260+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu-sun50i-h616.c+23−10
@@ -7,7 +7,7 @@ · 6 unmodified lines
77
88 #include <linux/clk-provider.h>
99 #include <linux/io.h>
10−#include <linux/of_address.h>
10+#include <linux/module.h>
1111 #include <linux/platform_device.h>
1212
1313 #include "ccu_common.h"
@@ -1082,17 +1082,15 @@ static const u32 usb2_clk_regs[] = { · 1068 unmodified lines
10821082 SUN50I_H616_USB3_CLK_REG,
10831083 };
10841084
1085−static void __init sun50i_h616_ccu_setup(struct device_node *node)
1085+static int sun50i_h616_ccu_probe(struct platform_device *pdev)
10861086 {
10871087 void __iomem *reg;
10881088 u32 val;
10891089 int i;
10901090
1091− reg = of_io_request_and_map(node, 0, of_node_full_name(node));
1092− if (IS_ERR(reg)) {
1093− pr_err("%pOF: Could not map clock registers\n", node);
1094− return;
1095− }
1091+ reg = devm_platform_ioremap_resource(pdev, 0);
1092+ if (IS_ERR(reg))
1093+ return PTR_ERR(reg);
10961094
10971095 /* Enable the lock bits and the output enable bits on all PLLs */
10981096 for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
@@ -1141,8 +1139,23 @@ static void __init sun50i_h616_ccu_setup(struct device_node *node) · 42 unmodified lines
11411139 val |= BIT(24);
11421140 writel(val, reg + SUN50I_H616_HDMI_CEC_CLK_REG);
11431141
1144− of_sunxi_ccu_probe(node, reg, &sun50i_h616_ccu_desc);
1142+ return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h616_ccu_desc);
11451143 }
11461144
1147−CLK_OF_DECLARE(sun50i_h616_ccu, "allwinner,sun50i-h616-ccu",
1148− sun50i_h616_ccu_setup);
1145+static const struct of_device_id sun50i_h616_ccu_ids[] = {
1146+ { .compatible = "allwinner,sun50i-h616-ccu" },
1147+ { }
1148+};
1149+
1150+static struct platform_driver sun50i_h616_ccu_driver = {
1151+ .probe = sun50i_h616_ccu_probe,
1152+ .driver = {
1153+ .name = "sun50i-h616-ccu",
1154+ .suppress_bind_attrs = true,
1155+ .of_match_table = sun50i_h616_ccu_ids,
1156+ },
1157+};
1158+module_platform_driver(sun50i_h616_ccu_driver);
1159+
1160+MODULE_IMPORT_NS(SUNXI_CCU);
1161+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu-sun6i-a31.c+30−10
@@ -9,7 +9,8 @@ · 8 unmodified lines
99
1010 #include <linux/clk-provider.h>
1111 #include <linux/io.h>
12−#include <linux/of_address.h>
12+#include <linux/module.h>
13+#include <linux/platform_device.h>
1314
1415 #include "ccu_common.h"
1516 #include "ccu_reset.h"
@@ -1226,16 +1227,15 @@ static struct ccu_mux_nb sun6i_a31_cpu_nb = { · 1210 unmodified lines
12261227 .bypass_index = 1, /* index of 24 MHz oscillator */
12271228 };
12281229
1229−static void __init sun6i_a31_ccu_setup(struct device_node *node)
1230+static int sun6i_a31_ccu_probe(struct platform_device *pdev)
12301231 {
12311232 void __iomem *reg;
1233+ int ret;
12321234 u32 val;
12331235
1234− reg = of_io_request_and_map(node, 0, of_node_full_name(node));
1235− if (IS_ERR(reg)) {
1236− pr_err("%pOF: Could not map the clock registers\n", node);
1237− return;
1238− }
1236+ reg = devm_platform_ioremap_resource(pdev, 0);
1237+ if (IS_ERR(reg))
1238+ return PTR_ERR(reg);
12391239
12401240 /* Force the PLL-Audio-1x divider to 1 */
12411241 val = readl(reg + SUN6I_A31_PLL_AUDIO_REG);
@@ -1257,10 +1257,30 @@ static void __init sun6i_a31_ccu_setup(struct device_node *node) · 15 unmodified lines
12571257 val |= 0x3 << 12;
12581258 writel(val, reg + SUN6I_A31_AHB1_REG);
12591259
1260− of_sunxi_ccu_probe(node, reg, &sun6i_a31_ccu_desc);
1260+ ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun6i_a31_ccu_desc);
1261+ if (ret)
1262+ return ret;
12611263
12621264 ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
12631265 &sun6i_a31_cpu_nb);
1266+
1267+ return 0;
12641268 }
1265−CLK_OF_DECLARE(sun6i_a31_ccu, "allwinner,sun6i-a31-ccu",
1266− sun6i_a31_ccu_setup);
1269+
1270+static const struct of_device_id sun6i_a31_ccu_ids[] = {
1271+ { .compatible = "allwinner,sun6i-a31-ccu" },
1272+ { }
1273+};
1274+
1275+static struct platform_driver sun6i_a31_ccu_driver = {
1276+ .probe = sun6i_a31_ccu_probe,
1277+ .driver = {
1278+ .name = "sun6i-a31-ccu",
1279+ .suppress_bind_attrs = true,
1280+ .of_match_table = sun6i_a31_ccu_ids,
1281+ },
1282+};
1283+module_platform_driver(sun6i_a31_ccu_driver);
1284+
1285+MODULE_IMPORT_NS(SUNXI_CCU);
1286+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu-sun8i-a23.c+25−10
@@ -5,7 +5,8 @@ · 4 unmodified lines
55
66 #include <linux/clk-provider.h>
77 #include <linux/io.h>
8−#include <linux/of_address.h>
8+#include <linux/module.h>
9+#include <linux/platform_device.h>
910
1011 #include "ccu_common.h"
1112 #include "ccu_reset.h"
@@ -724,16 +725,14 @@ static const struct sunxi_ccu_desc sun8i_a23_ccu_desc = { · 712 unmodified lines
724725 .num_resets = ARRAY_SIZE(sun8i_a23_ccu_resets),
725726 };
726727
727−static void __init sun8i_a23_ccu_setup(struct device_node *node)
728+static int sun8i_a23_ccu_probe(struct platform_device *pdev)
728729 {
729730 void __iomem *reg;
730731 u32 val;
731732
732− reg = of_io_request_and_map(node, 0, of_node_full_name(node));
733− if (IS_ERR(reg)) {
734− pr_err("%pOF: Could not map the clock registers\n", node);
735− return;
736− }
733+ reg = devm_platform_ioremap_resource(pdev, 0);
734+ if (IS_ERR(reg))
735+ return PTR_ERR(reg);
737736
738737 /* Force the PLL-Audio-1x divider to 1 */
739738 val = readl(reg + SUN8I_A23_PLL_AUDIO_REG);
@@ -745,7 +744,23 @@ static void __init sun8i_a23_ccu_setup(struct device_node *node) · 5 unmodified lines
745744 val &= ~BIT(16);
746745 writel(val, reg + SUN8I_A23_PLL_MIPI_REG);
747746
748− of_sunxi_ccu_probe(node, reg, &sun8i_a23_ccu_desc);
747+ return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_a23_ccu_desc);
749748 }
750−CLK_OF_DECLARE(sun8i_a23_ccu, "allwinner,sun8i-a23-ccu",
751− sun8i_a23_ccu_setup);
749+
750+static const struct of_device_id sun8i_a23_ccu_ids[] = {
751+ { .compatible = "allwinner,sun8i-a23-ccu" },
752+ { }
753+};
754+
755+static struct platform_driver sun8i_a23_ccu_driver = {
756+ .probe = sun8i_a23_ccu_probe,
757+ .driver = {
758+ .name = "sun8i-a23-ccu",
759+ .suppress_bind_attrs = true,
760+ .of_match_table = sun8i_a23_ccu_ids,
761+ },
762+};
763+module_platform_driver(sun8i_a23_ccu_driver);
764+
765+MODULE_IMPORT_NS(SUNXI_CCU);
766+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu-sun8i-a33.c+30−10
@@ -5,7 +5,8 @@ · 4 unmodified lines
55
66 #include <linux/clk-provider.h>
77 #include <linux/io.h>
8−#include <linux/of_address.h>
8+#include <linux/module.h>
9+#include <linux/platform_device.h>
910
1011 #include "ccu_common.h"
1112 #include "ccu_reset.h"
@@ -784,16 +785,15 @@ static struct ccu_mux_nb sun8i_a33_cpu_nb = { · 772 unmodified lines
784785 .bypass_index = 1, /* index of 24 MHz oscillator */
785786 };
786787
787−static void __init sun8i_a33_ccu_setup(struct device_node *node)
788+static int sun8i_a33_ccu_probe(struct platform_device *pdev)
788789 {
789790 void __iomem *reg;
791+ int ret;
790792 u32 val;
791793
792− reg = of_io_request_and_map(node, 0, of_node_full_name(node));
793− if (IS_ERR(reg)) {
794− pr_err("%pOF: Could not map the clock registers\n", node);
795− return;
796− }
794+ reg = devm_platform_ioremap_resource(pdev, 0);
795+ if (IS_ERR(reg))
796+ return PTR_ERR(reg);
797797
798798 /* Force the PLL-Audio-1x divider to 1 */
799799 val = readl(reg + SUN8I_A33_PLL_AUDIO_REG);
@@ -805,7 +805,9 @@ static void __init sun8i_a33_ccu_setup(struct device_node *node) · 5 unmodified lines
805805 val &= ~BIT(16);
806806 writel(val, reg + SUN8I_A33_PLL_MIPI_REG);
807807
808− of_sunxi_ccu_probe(node, reg, &sun8i_a33_ccu_desc);
808+ ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_a33_ccu_desc);
809+ if (ret)
810+ return ret;
809811
810812 /* Gate then ungate PLL CPU after any rate changes */
811813 ccu_pll_notifier_register(&sun8i_a33_pll_cpu_nb);
@@ -813,6 +815,24 @@ static void __init sun8i_a33_ccu_setup(struct device_node *node) · 1 unmodified line
813815 /* Reparent CPU during PLL CPU rate changes */
814816 ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
815817 &sun8i_a33_cpu_nb);
818+
819+ return 0;
816820 }
817−CLK_OF_DECLARE(sun8i_a33_ccu, "allwinner,sun8i-a33-ccu",
818− sun8i_a33_ccu_setup);
821+
822+static const struct of_device_id sun8i_a33_ccu_ids[] = {
823+ { .compatible = "allwinner,sun8i-a33-ccu" },
824+ { }
825+};
826+
827+static struct platform_driver sun8i_a33_ccu_driver = {
828+ .probe = sun8i_a33_ccu_probe,
829+ .driver = {
830+ .name = "sun8i-a33-ccu",
831+ .suppress_bind_attrs = true,
832+ .of_match_table = sun8i_a33_ccu_ids,
833+ },
834+};
835+module_platform_driver(sun8i_a33_ccu_driver);
836+
837+MODULE_IMPORT_NS(SUNXI_CCU);
838+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c+5−2
@@ -5,7 +5,7 @@ · 4 unmodified lines
55
66 #include <linux/clk-provider.h>
77 #include <linux/io.h>
8−#include <linux/of_address.h>
8+#include <linux/module.h>
99 #include <linux/platform_device.h>
1010
1111 #include "ccu_common.h"
@@ -920,4 +920,7 @@ static struct platform_driver sun8i_a83t_ccu_driver = { · 908 unmodified lines
920920 .of_match_table = sun8i_a83t_ccu_ids,
921921 },
922922 };
923−builtin_platform_driver(sun8i_a83t_ccu_driver);
923+module_platform_driver(sun8i_a83t_ccu_driver);
924+
925+MODULE_IMPORT_NS(SUNXI_CCU);
926+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu-sun8i-de2.c+6−3
@@ -5,8 +5,8 @@ · 4 unmodified lines
55
66 #include <linux/clk.h>
77 #include <linux/clk-provider.h>
8−#include <linux/of_address.h>
9−#include <linux/of_platform.h>
8+#include <linux/module.h>
9+#include <linux/of_device.h>
1010 #include <linux/platform_device.h>
1111 #include <linux/reset.h>
1212
@@ -394,4 +394,7 @@ static struct platform_driver sunxi_de2_clk_driver = { · 381 unmodified lines
394394 .of_match_table = sunxi_de2_clk_ids,
395395 },
396396 };
397−builtin_platform_driver(sunxi_de2_clk_driver);
397+module_platform_driver(sunxi_de2_clk_driver);
398+
399+MODULE_IMPORT_NS(SUNXI_CCU);
400+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu-sun8i-h3.c+41−21
@@ -5,7 +5,9 @@ · 4 unmodified lines
55
66 #include <linux/clk-provider.h>
77 #include <linux/io.h>
8−#include <linux/of_address.h>
8+#include <linux/module.h>
9+#include <linux/of_device.h>
10+#include <linux/platform_device.h>
911
1012 #include "ccu_common.h"
1113 #include "ccu_reset.h"
@@ -1137,24 +1139,29 @@ static struct ccu_mux_nb sun8i_h3_cpu_nb = { · 1125 unmodified lines
11371139 .bypass_index = 1, /* index of 24 MHz oscillator */
11381140 };
11391141
1140−static void __init sunxi_h3_h5_ccu_init(struct device_node *node,
1141− const struct sunxi_ccu_desc *desc)
1142+static int sun8i_h3_ccu_probe(struct platform_device *pdev)
11421143 {
1144+ const struct sunxi_ccu_desc *desc;
11431145 void __iomem *reg;
1146+ int ret;
11441147 u32 val;
11451148
1146− reg = of_io_request_and_map(node, 0, of_node_full_name(node));
1147− if (IS_ERR(reg)) {
1148− pr_err("%pOF: Could not map the clock registers\n", node);
1149− return;
1150− }
1149+ desc = of_device_get_match_data(&pdev->dev);
1150+ if (!desc)
1151+ return -EINVAL;
1152+
1153+ reg = devm_platform_ioremap_resource(pdev, 0);
1154+ if (IS_ERR(reg))
1155+ return PTR_ERR(reg);
11511156
11521157 /* Force the PLL-Audio-1x divider to 1 */
11531158 val = readl(reg + SUN8I_H3_PLL_AUDIO_REG);
11541159 val &= ~GENMASK(19, 16);
11551160 writel(val | (0 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
11561161
1157− of_sunxi_ccu_probe(node, reg, desc);
1162+ ret = devm_sunxi_ccu_probe(&pdev->dev, reg, desc);
1163+ if (ret)
1164+ return ret;
11581165
11591166 /* Gate then ungate PLL CPU after any rate changes */
11601167 ccu_pll_notifier_register(&sun8i_h3_pll_cpu_nb);
@@ -1162,18 +1169,31 @@ static void __init sunxi_h3_h5_ccu_init(struct device_node *node, · 1 unmodified line
11621169 /* Reparent CPU during PLL CPU rate changes */
11631170 ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
11641171 &sun8i_h3_cpu_nb);
1165−}
11661172
1167−static void __init sun8i_h3_ccu_setup(struct device_node *node)
1168−{
1169− sunxi_h3_h5_ccu_init(node, &sun8i_h3_ccu_desc);
1173+ return 0;
11701174 }
1171−CLK_OF_DECLARE(sun8i_h3_ccu, "allwinner,sun8i-h3-ccu",
1172− sun8i_h3_ccu_setup);
11731175
1174−static void __init sun50i_h5_ccu_setup(struct device_node *node)
1175−{
1176− sunxi_h3_h5_ccu_init(node, &sun50i_h5_ccu_desc);
1177−}
1178−CLK_OF_DECLARE(sun50i_h5_ccu, "allwinner,sun50i-h5-ccu",
1179− sun50i_h5_ccu_setup);
1176+static const struct of_device_id sun8i_h3_ccu_ids[] = {
1177+ {
1178+ .compatible = "allwinner,sun8i-h3-ccu",
1179+ .data = &sun8i_h3_ccu_desc,
1180+ },
1181+ {
1182+ .compatible = "allwinner,sun50i-h5-ccu",
1183+ .data = &sun50i_h5_ccu_desc,
1184+ },
1185+ { }
1186+};
1187+
1188+static struct platform_driver sun8i_h3_ccu_driver = {
1189+ .probe = sun8i_h3_ccu_probe,
1190+ .driver = {
1191+ .name = "sun8i-h3-ccu",
1192+ .suppress_bind_attrs = true,
1193+ .of_match_table = sun8i_h3_ccu_ids,
1194+ },
1195+};
1196+module_platform_driver(sun8i_h3_ccu_driver);
1197+
1198+MODULE_IMPORT_NS(SUNXI_CCU);
1199+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu-sun8i-r.c+38−27
@@ -4,7 +4,8 @@ · 3 unmodified lines
44 */
55
66 #include <linux/clk-provider.h>
7−#include <linux/of_address.h>
7+#include <linux/module.h>
8+#include <linux/of_device.h>
89 #include <linux/platform_device.h>
910
1011 #include "ccu_common.h"
@@ -254,37 +255,47 @@ static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = { · 243 unmodified lines
254255 .num_resets = ARRAY_SIZE(sun50i_a64_r_ccu_resets),
255256 };
256257
257−static void __init sunxi_r_ccu_init(struct device_node *node,
258− const struct sunxi_ccu_desc *desc)
258+static int sun8i_r_ccu_probe(struct platform_device *pdev)
259259 {
260+ const struct sunxi_ccu_desc *desc;
260261 void __iomem *reg;
261262
262− reg = of_io_request_and_map(node, 0, of_node_full_name(node));
263− if (IS_ERR(reg)) {
264− pr_err("%pOF: Could not map the clock registers\n", node);
265− return;
266− }
263+ desc = of_device_get_match_data(&pdev->dev);
264+ if (!desc)
265+ return -EINVAL;
267266
268− of_sunxi_ccu_probe(node, reg, desc);
269−}
267+ reg = devm_platform_ioremap_resource(pdev, 0);
268+ if (IS_ERR(reg))
269+ return PTR_ERR(reg);
270270
271−static void __init sun8i_a83t_r_ccu_setup(struct device_node *node)
272−{
273− sunxi_r_ccu_init(node, &sun8i_a83t_r_ccu_desc);
271+ return devm_sunxi_ccu_probe(&pdev->dev, reg, desc);
274272 }
275−CLK_OF_DECLARE(sun8i_a83t_r_ccu, "allwinner,sun8i-a83t-r-ccu",
276− sun8i_a83t_r_ccu_setup);
277273
278−static void __init sun8i_h3_r_ccu_setup(struct device_node *node)
279−{
280− sunxi_r_ccu_init(node, &sun8i_h3_r_ccu_desc);
281−}
282−CLK_OF_DECLARE(sun8i_h3_r_ccu, "allwinner,sun8i-h3-r-ccu",
283− sun8i_h3_r_ccu_setup);
274+static const struct of_device_id sun8i_r_ccu_ids[] = {
275+ {
276+ .compatible = "allwinner,sun8i-a83t-r-ccu",
277+ .data = &sun8i_a83t_r_ccu_desc,
278+ },
279+ {
280+ .compatible = "allwinner,sun8i-h3-r-ccu",
281+ .data = &sun8i_h3_r_ccu_desc,
282+ },
283+ {
284+ .compatible = "allwinner,sun50i-a64-r-ccu",
285+ .data = &sun50i_a64_r_ccu_desc,
286+ },
287+ { }
288+};
284289
285−static void __init sun50i_a64_r_ccu_setup(struct device_node *node)
286−{
287− sunxi_r_ccu_init(node, &sun50i_a64_r_ccu_desc);
288−}
289−CLK_OF_DECLARE(sun50i_a64_r_ccu, "allwinner,sun50i-a64-r-ccu",
290− sun50i_a64_r_ccu_setup);
290+static struct platform_driver sun8i_r_ccu_driver = {
291+ .probe = sun8i_r_ccu_probe,
292+ .driver = {
293+ .name = "sun8i-r-ccu",
294+ .suppress_bind_attrs = true,
295+ .of_match_table = sun8i_r_ccu_ids,
296+ },
297+};
298+module_platform_driver(sun8i_r_ccu_driver);
299+
300+MODULE_IMPORT_NS(SUNXI_CCU);
301+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu-sun8i-r40.c+5−1
@@ -5,6 +5,7 @@ · 4 unmodified lines
55
66 #include <linux/clk-provider.h>
77 #include <linux/io.h>
8+#include <linux/module.h>
89 #include <linux/platform_device.h>
910 #include <linux/regmap.h>
1011
@@ -1371,4 +1372,7 @@ static struct platform_driver sun8i_r40_ccu_driver = { · 1360 unmodified lines
13711372 .of_match_table = sun8i_r40_ccu_ids,
13721373 },
13731374 };
1374−builtin_platform_driver(sun8i_r40_ccu_driver);
1375+module_platform_driver(sun8i_r40_ccu_driver);
1376+
1377+MODULE_IMPORT_NS(SUNXI_CCU);
1378+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c+35−22
@@ -8,7 +8,9 @@ · 7 unmodified lines
88
99 #include <linux/clk-provider.h>
1010 #include <linux/io.h>
11−#include <linux/of_address.h>
11+#include <linux/module.h>
12+#include <linux/of_device.h>
13+#include <linux/platform_device.h>
1214
1315 #include "ccu_common.h"
1416 #include "ccu_reset.h"
@@ -805,38 +807,49 @@ static const struct sunxi_ccu_desc sun8i_v3_ccu_desc = { · 790 unmodified lines
805807 .num_resets = ARRAY_SIZE(sun8i_v3_ccu_resets),
806808 };
807809
808−static void __init sun8i_v3_v3s_ccu_init(struct device_node *node,
809− const struct sunxi_ccu_desc *ccu_desc)
810+static int sun8i_v3s_ccu_probe(struct platform_device *pdev)
810811 {
812+ const struct sunxi_ccu_desc *desc;
811813 void __iomem *reg;
812814 u32 val;
813815
814− reg = of_io_request_and_map(node, 0, of_node_full_name(node));
815− if (IS_ERR(reg)) {
816− pr_err("%pOF: Could not map the clock registers\n", node);
817− return;
818− }
816+ desc = of_device_get_match_data(&pdev->dev);
817+ if (!desc)
818+ return -EINVAL;
819+
820+ reg = devm_platform_ioremap_resource(pdev, 0);
821+ if (IS_ERR(reg))
822+ return PTR_ERR(reg);
819823
820824 /* Force the PLL-Audio-1x divider to 1 */
821825 val = readl(reg + SUN8I_V3S_PLL_AUDIO_REG);
822826 val &= ~GENMASK(19, 16);
823827 writel(val, reg + SUN8I_V3S_PLL_AUDIO_REG);
824828
825− of_sunxi_ccu_probe(node, reg, ccu_desc);
826−}
827−
828−static void __init sun8i_v3s_ccu_setup(struct device_node *node)
829−{
830− sun8i_v3_v3s_ccu_init(node, &sun8i_v3s_ccu_desc);
829+ return devm_sunxi_ccu_probe(&pdev->dev, reg, desc);
831830 }
832831
833−static void __init sun8i_v3_ccu_setup(struct device_node *node)
834−{
835− sun8i_v3_v3s_ccu_init(node, &sun8i_v3_ccu_desc);
836−}
832+static const struct of_device_id sun8i_v3s_ccu_ids[] = {
833+ {
834+ .compatible = "allwinner,sun8i-v3-ccu",
835+ .data = &sun8i_v3_ccu_desc,
836+ },
837+ {
838+ .compatible = "allwinner,sun8i-v3s-ccu",
839+ .data = &sun8i_v3s_ccu_desc,
840+ },
841+ { }
842+};
837843
838−CLK_OF_DECLARE(sun8i_v3s_ccu, "allwinner,sun8i-v3s-ccu",
839− sun8i_v3s_ccu_setup);
844+static struct platform_driver sun8i_v3s_ccu_driver = {
845+ .probe = sun8i_v3s_ccu_probe,
846+ .driver = {
847+ .name = "sun8i-v3s-ccu",
848+ .suppress_bind_attrs = true,
849+ .of_match_table = sun8i_v3s_ccu_ids,
850+ },
851+};
852+module_platform_driver(sun8i_v3s_ccu_driver);
840853
841−CLK_OF_DECLARE(sun8i_v3_ccu, "allwinner,sun8i-v3-ccu",
842− sun8i_v3_ccu_setup);
854+MODULE_IMPORT_NS(SUNXI_CCU);
855+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c+5−2
@@ -5,7 +5,7 @@ · 4 unmodified lines
55
66 #include <linux/clk.h>
77 #include <linux/clk-provider.h>
8−#include <linux/of_address.h>
8+#include <linux/module.h>
99 #include <linux/platform_device.h>
1010 #include <linux/reset.h>
1111
@@ -270,4 +270,7 @@ static struct platform_driver sun9i_a80_de_clk_driver = { · 258 unmodified lines
270270 .of_match_table = sun9i_a80_de_clk_ids,
271271 },
272272 };
273−builtin_platform_driver(sun9i_a80_de_clk_driver);
273+module_platform_driver(sun9i_a80_de_clk_driver);
274+
275+MODULE_IMPORT_NS(SUNXI_CCU);
276+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c+5−2
@@ -5,7 +5,7 @@ · 4 unmodified lines
55
66 #include <linux/clk.h>
77 #include <linux/clk-provider.h>
8−#include <linux/of_address.h>
8+#include <linux/module.h>
99 #include <linux/platform_device.h>
1010
1111 #include "ccu_common.h"
@@ -138,4 +138,7 @@ static struct platform_driver sun9i_a80_usb_clk_driver = { · 126 unmodified lines
138138 .of_match_table = sun9i_a80_usb_clk_ids,
139139 },
140140 };
141−builtin_platform_driver(sun9i_a80_usb_clk_driver);
141+module_platform_driver(sun9i_a80_usb_clk_driver);
142+
143+MODULE_IMPORT_NS(SUNXI_CCU);
144+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu-sun9i-a80.c+5−2
@@ -5,7 +5,7 @@ · 4 unmodified lines
55
66 #include <linux/clk-provider.h>
77 #include <linux/io.h>
8−#include <linux/of_address.h>
8+#include <linux/module.h>
99 #include <linux/platform_device.h>
1010
1111 #include "ccu_common.h"
@@ -1245,4 +1245,7 @@ static struct platform_driver sun9i_a80_ccu_driver = { · 1233 unmodified lines
12451245 .of_match_table = sun9i_a80_ccu_ids,
12461246 },
12471247 };
1248−builtin_platform_driver(sun9i_a80_ccu_driver);
1248+module_platform_driver(sun9i_a80_ccu_driver);
1249+
1250+MODULE_IMPORT_NS(SUNXI_CCU);
1251+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c+30−10
@@ -6,7 +6,8 @@ · 5 unmodified lines
66
77 #include <linux/clk-provider.h>
88 #include <linux/io.h>
9−#include <linux/of_address.h>
9+#include <linux/module.h>
10+#include <linux/platform_device.h>
1011
1112 #include "ccu_common.h"
1213 #include "ccu_reset.h"
@@ -522,23 +523,24 @@ static struct ccu_mux_nb suniv_cpu_nb = { · 509 unmodified lines
522523 .bypass_index = 1, /* index of 24 MHz oscillator */
523524 };
524525
525−static void __init suniv_f1c100s_ccu_setup(struct device_node *node)
526+static int suniv_f1c100s_ccu_probe(struct platform_device *pdev)
526527 {
527528 void __iomem *reg;
529+ int ret;
528530 u32 val;
529531
530− reg = of_io_request_and_map(node, 0, of_node_full_name(node));
531− if (IS_ERR(reg)) {
532− pr_err("%pOF: Could not map the clock registers\n", node);
533− return;
534− }
532+ reg = devm_platform_ioremap_resource(pdev, 0);
533+ if (IS_ERR(reg))
534+ return PTR_ERR(reg);
535535
536536 /* Force the PLL-Audio-1x divider to 4 */
537537 val = readl(reg + SUNIV_PLL_AUDIO_REG);
538538 val &= ~GENMASK(19, 16);
539539 writel(val | (3 << 16), reg + SUNIV_PLL_AUDIO_REG);
540540
541− of_sunxi_ccu_probe(node, reg, &suniv_ccu_desc);
541+ ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &suniv_ccu_desc);
542+ if (ret)
543+ return ret;
542544
543545 /* Gate then ungate PLL CPU after any rate changes */
544546 ccu_pll_notifier_register(&suniv_pll_cpu_nb);
@@ -546,6 +548,24 @@ static void __init suniv_f1c100s_ccu_setup(struct device_node *node) · 1 unmodified line
546548 /* Reparent CPU during PLL CPU rate changes */
547549 ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
548550 &suniv_cpu_nb);
551+
552+ return 0;
549553 }
550−CLK_OF_DECLARE(suniv_f1c100s_ccu, "allwinner,suniv-f1c100s-ccu",
551− suniv_f1c100s_ccu_setup);
554+
555+static const struct of_device_id suniv_f1c100s_ccu_ids[] = {
556+ { .compatible = "allwinner,suniv-f1c100s-ccu" },
557+ { }
558+};
559+
560+static struct platform_driver suniv_f1c100s_ccu_driver = {
561+ .probe = suniv_f1c100s_ccu_probe,
562+ .driver = {
563+ .name = "suniv-f1c100s-ccu",
564+ .suppress_bind_attrs = true,
565+ .of_match_table = suniv_f1c100s_ccu_ids,
566+ },
567+};
568+module_platform_driver(suniv_f1c100s_ccu_driver);
569+
570+MODULE_IMPORT_NS(SUNXI_CCU);
571+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu_common.c+6−0
@@ -9,6 +9,7 @@ · 8 unmodified lines
99 #include <linux/clk-provider.h>
1010 #include <linux/device.h>
1111 #include <linux/iopoll.h>
12+#include <linux/module.h>
1213 #include <linux/slab.h>
1314
1415 #include "ccu_common.h"
@@ -36,6 +37,7 @@ void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock) · 21 unmodified lines
3637
3738 WARN_ON(readl_relaxed_poll_timeout(addr, reg, reg & lock, 100, 70000));
3839 }
40+EXPORT_SYMBOL_NS_GPL(ccu_helper_wait_for_lock, SUNXI_CCU);
3941
4042 /*
4143 * This clock notifier is called when the frequency of a PLL clock is
@@ -83,6 +85,7 @@ int ccu_pll_notifier_register(struct ccu_pll_nb *pll_nb) · 41 unmodified lines
8385 return clk_notifier_register(pll_nb->common->hw.clk,
8486 &pll_nb->clk_nb);
8587 }
88+EXPORT_SYMBOL_NS_GPL(ccu_pll_notifier_register, SUNXI_CCU);
8689
8790 static int sunxi_ccu_probe(struct sunxi_ccu *ccu, struct device *dev,
8891 struct device_node *node, void __iomem *reg,
@@ -194,6 +197,7 @@ int devm_sunxi_ccu_probe(struct device *dev, void __iomem *reg, · 105 unmodified lines
194197
195198 return 0;
196199 }
200+EXPORT_SYMBOL_NS_GPL(devm_sunxi_ccu_probe, SUNXI_CCU);
197201
198202 void of_sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
199203 const struct sunxi_ccu_desc *desc)
@@ -211,3 +215,5 @@ void of_sunxi_ccu_probe(struct device_node *node, void __iomem *reg, · 11 unmodified lines
211215 kfree(ccu);
212216 }
213217 }
218+
219+MODULE_LICENSE("GPL");
drivers/clk/sunxi-ng/ccu_div.c+1−0
@@ -141,3 +141,4 @@ const struct clk_ops ccu_div_ops = { · 140 unmodified lines
141141 .recalc_rate = ccu_div_recalc_rate,
142142 .set_rate = ccu_div_set_rate,
143143 };
144+EXPORT_SYMBOL_NS_GPL(ccu_div_ops, SUNXI_CCU);
drivers/clk/sunxi-ng/ccu_div.h+78−0
@@ -108,6 +108,22 @@ struct ccu_div { · 107 unmodified lines
108108 _shift, _width, _table, 0, \
109109 _flags)
110110
111+#define SUNXI_CCU_DIV_TABLE_HW(_struct, _name, _parent, _reg, \
112+ _shift, _width, \
113+ _table, _flags) \
114+ struct ccu_div _struct = { \
115+ .div = _SUNXI_CCU_DIV_TABLE(_shift, _width, \
116+ _table), \
117+ .common = { \
118+ .reg = _reg, \
119+ .hw.init = CLK_HW_INIT_HW(_name, \
120+ _parent, \
121+ &ccu_div_ops, \
122+ _flags), \
123+ } \
124+ }
125+
126+
111127 #define SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
112128 _parents, _table, \
113129 _reg, \
@@ -166,6 +182,68 @@ struct ccu_div { · 52 unmodified lines
166182 SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \
167183 _mshift, _mwidth, 0, _flags)
168184
185+#define SUNXI_CCU_M_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
186+ _mshift, _mwidth, \
187+ _muxshift, _muxwidth, \
188+ _gate, _flags) \
189+ struct ccu_div _struct = { \
190+ .enable = _gate, \
191+ .div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
192+ .mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
193+ .common = { \
194+ .reg = _reg, \
195+ .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
196+ _parents, \
197+ &ccu_div_ops, \
198+ _flags), \
199+ }, \
200+ }
201+
202+#define SUNXI_CCU_M_DATA_WITH_MUX(_struct, _name, _parents, _reg, \
203+ _mshift, _mwidth, \
204+ _muxshift, _muxwidth, \
205+ _flags) \
206+ SUNXI_CCU_M_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
207+ _mshift, _mwidth, \
208+ _muxshift, _muxwidth, \
209+ 0, _flags)
210+
211+#define SUNXI_CCU_M_HW_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
212+ _mshift, _mwidth, _muxshift, _muxwidth, \
213+ _gate, _flags) \
214+ struct ccu_div _struct = { \
215+ .enable = _gate, \
216+ .div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
217+ .mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
218+ .common = { \
219+ .reg = _reg, \
220+ .hw.init = CLK_HW_INIT_PARENTS_HW(_name, \
221+ _parents, \
222+ &ccu_div_ops, \
223+ _flags), \
224+ }, \
225+ }
226+
227+#define SUNXI_CCU_M_HWS_WITH_GATE(_struct, _name, _parent, _reg, \
228+ _mshift, _mwidth, _gate, \
229+ _flags) \
230+ struct ccu_div _struct = { \
231+ .enable = _gate, \
232+ .div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
233+ .common = { \
234+ .reg = _reg, \
235+ .hw.init = CLK_HW_INIT_HWS(_name, \
236+ _parent, \
237+ &ccu_div_ops, \
238+ _flags), \
239+ }, \
240+ }
241+
242+#define SUNXI_CCU_M_HWS(_struct, _name, _parent, _reg, _mshift, \
243+ _mwidth, _flags) \
244+ SUNXI_CCU_M_HWS_WITH_GATE(_struct, _name, _parent, _reg, \
245+ _mshift, _mwidth, 0, _flags)
246+
169247 static inline struct ccu_div *hw_to_ccu_div(struct clk_hw *hw)
170248 {
171249 struct ccu_common *common = hw_to_ccu_common(hw);
drivers/clk/sunxi-ng/ccu_frac.c+6−0
@@ -18,6 +18,7 @@ bool ccu_frac_helper_is_enabled(struct ccu_common *common, · 17 unmodified lines
1818
1919 return !(readl(common->base + common->reg) & cf->enable);
2020 }
21+EXPORT_SYMBOL_NS_GPL(ccu_frac_helper_is_enabled, SUNXI_CCU);
2122
2223 void ccu_frac_helper_enable(struct ccu_common *common,
2324 struct ccu_frac_internal *cf)
@@ -33,6 +34,7 @@ void ccu_frac_helper_enable(struct ccu_common *common, · 9 unmodified lines
3334 writel(reg & ~cf->enable, common->base + common->reg);
3435 spin_unlock_irqrestore(common->lock, flags);
3536 }
37+EXPORT_SYMBOL_NS_GPL(ccu_frac_helper_enable, SUNXI_CCU);
3638
3739 void ccu_frac_helper_disable(struct ccu_common *common,
3840 struct ccu_frac_internal *cf)
@@ -48,6 +50,7 @@ void ccu_frac_helper_disable(struct ccu_common *common, · 9 unmodified lines
4850 writel(reg | cf->enable, common->base + common->reg);
4951 spin_unlock_irqrestore(common->lock, flags);
5052 }
53+EXPORT_SYMBOL_NS_GPL(ccu_frac_helper_disable, SUNXI_CCU);
5154
5255 bool ccu_frac_helper_has_rate(struct ccu_common *common,
5356 struct ccu_frac_internal *cf,
@@ -58,6 +61,7 @@ bool ccu_frac_helper_has_rate(struct ccu_common *common, · 4 unmodified lines
5861
5962 return (cf->rates[0] == rate) || (cf->rates[1] == rate);
6063 }
64+EXPORT_SYMBOL_NS_GPL(ccu_frac_helper_has_rate, SUNXI_CCU);
6165
6266 unsigned long ccu_frac_helper_read_rate(struct ccu_common *common,
6367 struct ccu_frac_internal *cf)
@@ -79,6 +83,7 @@ unsigned long ccu_frac_helper_read_rate(struct ccu_common *common, · 15 unmodified lines
7983
8084 return (reg & cf->select) ? cf->rates[1] : cf->rates[0];
8185 }
86+EXPORT_SYMBOL_NS_GPL(ccu_frac_helper_read_rate, SUNXI_CCU);
8287
8388 int ccu_frac_helper_set_rate(struct ccu_common *common,
8489 struct ccu_frac_internal *cf,
@@ -107,3 +112,4 @@ int ccu_frac_helper_set_rate(struct ccu_common *common, · 22 unmodified lines
107112
108113 return 0;
109114 }
115+EXPORT_SYMBOL_NS_GPL(ccu_frac_helper_set_rate, SUNXI_CCU);
drivers/clk/sunxi-ng/ccu_gate.c+4−0
@@ -24,6 +24,7 @@ void ccu_gate_helper_disable(struct ccu_common *common, u32 gate) · 23 unmodified lines
2424
2525 spin_unlock_irqrestore(common->lock, flags);
2626 }
27+EXPORT_SYMBOL_NS_GPL(ccu_gate_helper_disable, SUNXI_CCU);
2728
2829 static void ccu_gate_disable(struct clk_hw *hw)
2930 {
@@ -49,6 +50,7 @@ int ccu_gate_helper_enable(struct ccu_common *common, u32 gate) · 19 unmodified lines
4950
5051 return 0;
5152 }
53+EXPORT_SYMBOL_NS_GPL(ccu_gate_helper_enable, SUNXI_CCU);
5254
5355 static int ccu_gate_enable(struct clk_hw *hw)
5456 {
@@ -64,6 +66,7 @@ int ccu_gate_helper_is_enabled(struct ccu_common *common, u32 gate) · 9 unmodified lines
6466
6567 return readl(common->base + common->reg) & gate;
6668 }
69+EXPORT_SYMBOL_NS_GPL(ccu_gate_helper_is_enabled, SUNXI_CCU);
6770
6871 static int ccu_gate_is_enabled(struct clk_hw *hw)
6972 {
@@ -124,3 +127,4 @@ const struct clk_ops ccu_gate_ops = { · 54 unmodified lines
124127 .set_rate = ccu_gate_set_rate,
125128 .recalc_rate = ccu_gate_recalc_rate,
126129 };
130+EXPORT_SYMBOL_NS_GPL(ccu_gate_ops, SUNXI_CCU);
drivers/clk/sunxi-ng/ccu_gate.h+31−1
@@ -53,7 +53,7 @@ struct ccu_gate { · 52 unmodified lines
5353 }
5454
5555 /*
56− * The following two macros allow the re-use of the data structure
56+ * The following macros allow the re-use of the data structure
5757 * holding the parent info.
5858 */
5959 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \
@@ -68,6 +68,21 @@ struct ccu_gate { · 8 unmodified lines
6868 } \
6969 }
7070
71+#define SUNXI_CCU_GATE_HWS_WITH_PREDIV(_struct, _name, _parent, _reg, \
72+ _gate, _prediv, _flags) \
73+ struct ccu_gate _struct = { \
74+ .enable = _gate, \
75+ .common = { \
76+ .reg = _reg, \
77+ .prediv = _prediv, \
78+ .features = CCU_FEATURE_ALL_PREDIV, \
79+ .hw.init = CLK_HW_INIT_HWS(_name, \
80+ _parent, \
81+ &ccu_gate_ops, \
82+ _flags), \
83+ } \
84+ }
85+
7186 #define SUNXI_CCU_GATE_DATA(_struct, _name, _data, _reg, _gate, _flags) \
7287 struct ccu_gate _struct = { \
7388 .enable = _gate, \
@@ -81,6 +96,21 @@ struct ccu_gate { · 7 unmodified lines
8196 } \
8297 }
8398
99+#define SUNXI_CCU_GATE_DATA_WITH_PREDIV(_struct, _name, _parent, _reg, \
100+ _gate, _prediv, _flags) \
101+ struct ccu_gate _struct = { \
102+ .enable = _gate, \
103+ .common = { \
104+ .reg = _reg, \
105+ .prediv = _prediv, \
106+ .features = CCU_FEATURE_ALL_PREDIV, \
107+ .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
108+ _parent, \
109+ &ccu_gate_ops, \
110+ _flags), \
111+ } \
112+ }
113+
84114 static inline struct ccu_gate *hw_to_ccu_gate(struct clk_hw *hw)
85115 {
86116 struct ccu_common *common = hw_to_ccu_common(hw);
drivers/clk/sunxi-ng/ccu_mp.c+2−0
@@ -245,6 +245,7 @@ const struct clk_ops ccu_mp_ops = { · 244 unmodified lines
245245 .recalc_rate = ccu_mp_recalc_rate,
246246 .set_rate = ccu_mp_set_rate,
247247 };
248+EXPORT_SYMBOL_NS_GPL(ccu_mp_ops, SUNXI_CCU);
248249
249250 /*
250251 * Support for MMC timing mode switching
@@ -325,3 +326,4 @@ const struct clk_ops ccu_mp_mmc_ops = { · 74 unmodified lines
325326 .recalc_rate = ccu_mp_mmc_recalc_rate,
326327 .set_rate = ccu_mp_mmc_set_rate,
327328 };
329+EXPORT_SYMBOL_NS_GPL(ccu_mp_mmc_ops, SUNXI_CCU);
drivers/clk/sunxi-ng/ccu_mp.h+49−0
@@ -82,6 +82,55 @@ struct ccu_mp { · 81 unmodified lines
8282 _muxshift, _muxwidth, \
8383 0, _flags)
8484
85+#define SUNXI_CCU_MP_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
86+ _mshift, _mwidth, \
87+ _pshift, _pwidth, \
88+ _muxshift, _muxwidth, \
89+ _gate, _flags) \
90+ struct ccu_mp _struct = { \
91+ .enable = _gate, \
92+ .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
93+ .p = _SUNXI_CCU_DIV(_pshift, _pwidth), \
94+ .mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
95+ .common = { \
96+ .reg = _reg, \
97+ .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
98+ _parents, \
99+ &ccu_mp_ops, \
100+ _flags), \
101+ } \
102+ }
103+
104+#define SUNXI_CCU_MP_DATA_WITH_MUX(_struct, _name, _parents, _reg, \
105+ _mshift, _mwidth, \
106+ _pshift, _pwidth, \
107+ _muxshift, _muxwidth, \
108+ _flags) \
109+ SUNXI_CCU_MP_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
110+ _mshift, _mwidth, \
111+ _pshift, _pwidth, \
112+ _muxshift, _muxwidth, \
113+ 0, _flags)
114+
115+#define SUNXI_CCU_MP_HW_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
116+ _mshift, _mwidth, \
117+ _pshift, _pwidth, \
118+ _muxshift, _muxwidth, \
119+ _gate, _flags) \
120+ struct ccu_mp _struct = { \
121+ .enable = _gate, \
122+ .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
123+ .p = _SUNXI_CCU_DIV(_pshift, _pwidth), \
124+ .mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
125+ .common = { \
126+ .reg = _reg, \
127+ .hw.init = CLK_HW_INIT_PARENTS_HW(_name, \
128+ _parents, \
129+ &ccu_mp_ops, \
130+ _flags), \
131+ } \
132+ }
133+
85134 static inline struct ccu_mp *hw_to_ccu_mp(struct clk_hw *hw)
86135 {
87136 struct ccu_common *common = hw_to_ccu_common(hw);
drivers/clk/sunxi-ng/ccu_mult.c+1−0
@@ -170,3 +170,4 @@ const struct clk_ops ccu_mult_ops = { · 169 unmodified lines
170170 .recalc_rate = ccu_mult_recalc_rate,
171171 .set_rate = ccu_mult_set_rate,
172172 };
173+EXPORT_SYMBOL_NS_GPL(ccu_mult_ops, SUNXI_CCU);
drivers/clk/sunxi-ng/ccu_mux.c+6−0
@@ -64,6 +64,7 @@ unsigned long ccu_mux_helper_apply_prediv(struct ccu_common *common, · 63 unmodified lines
6464 {
6565 return parent_rate / ccu_mux_get_prediv(common, cm, parent_index);
6666 }
67+EXPORT_SYMBOL_NS_GPL(ccu_mux_helper_apply_prediv, SUNXI_CCU);
6768
6869 static unsigned long ccu_mux_helper_unapply_prediv(struct ccu_common *common,
6970 struct ccu_mux_internal *cm,
@@ -152,6 +153,7 @@ out: · 82 unmodified lines
152153 req->rate = best_rate;
153154 return 0;
154155 }
156+EXPORT_SYMBOL_NS_GPL(ccu_mux_helper_determine_rate, SUNXI_CCU);
155157
156158 u8 ccu_mux_helper_get_parent(struct ccu_common *common,
157159 struct ccu_mux_internal *cm)
@@ -174,6 +176,7 @@ u8 ccu_mux_helper_get_parent(struct ccu_common *common, · 16 unmodified lines
174176
175177 return parent;
176178 }
179+EXPORT_SYMBOL_NS_GPL(ccu_mux_helper_get_parent, SUNXI_CCU);
177180
178181 int ccu_mux_helper_set_parent(struct ccu_common *common,
179182 struct ccu_mux_internal *cm,
@@ -195,6 +198,7 @@ int ccu_mux_helper_set_parent(struct ccu_common *common, · 15 unmodified lines
195198
196199 return 0;
197200 }
201+EXPORT_SYMBOL_NS_GPL(ccu_mux_helper_set_parent, SUNXI_CCU);
198202
199203 static void ccu_mux_disable(struct clk_hw *hw)
200204 {
@@ -251,6 +255,7 @@ const struct clk_ops ccu_mux_ops = { · 50 unmodified lines
251255 .determine_rate = __clk_mux_determine_rate,
252256 .recalc_rate = ccu_mux_recalc_rate,
253257 };
258+EXPORT_SYMBOL_NS_GPL(ccu_mux_ops, SUNXI_CCU);
254259
255260 /*
256261 * This clock notifier is called when the frequency of the of the parent
@@ -285,3 +290,4 @@ int ccu_mux_notifier_register(struct clk *clk, struct ccu_mux_nb *mux_nb) · 28 unmodified lines
285290
286291 return clk_notifier_register(clk, &mux_nb->clk_nb);
287292 }
293+EXPORT_SYMBOL_NS_GPL(ccu_mux_notifier_register, SUNXI_CCU);
drivers/clk/sunxi-ng/ccu_mux.h+33−0
@@ -72,6 +72,39 @@ struct ccu_mux { · 71 unmodified lines
7272 SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, NULL, \
7373 _reg, _shift, _width, 0, _flags)
7474
75+#define SUNXI_CCU_MUX_DATA_WITH_GATE(_struct, _name, _parents, _reg, \
76+ _shift, _width, _gate, _flags) \
77+ struct ccu_mux _struct = { \
78+ .enable = _gate, \
79+ .mux = _SUNXI_CCU_MUX(_shift, _width), \
80+ .common = { \
81+ .reg = _reg, \
82+ .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
83+ _parents, \
84+ &ccu_mux_ops, \
85+ _flags), \
86+ } \
87+ }
88+
89+#define SUNXI_CCU_MUX_DATA(_struct, _name, _parents, _reg, \
90+ _shift, _width, _flags) \
91+ SUNXI_CCU_MUX_DATA_WITH_GATE(_struct, _name, _parents, _reg, \
92+ _shift, _width, 0, _flags)
93+
94+#define SUNXI_CCU_MUX_HW_WITH_GATE(_struct, _name, _parents, _reg, \
95+ _shift, _width, _gate, _flags) \
96+ struct ccu_mux _struct = { \
97+ .enable = _gate, \
98+ .mux = _SUNXI_CCU_MUX(_shift, _width), \
99+ .common = { \
100+ .reg = _reg, \
101+ .hw.init = CLK_HW_INIT_PARENTS_HW(_name, \
102+ _parents, \
103+ &ccu_mux_ops, \
104+ _flags), \
105+ } \
106+ }
107+
75108 static inline struct ccu_mux *hw_to_ccu_mux(struct clk_hw *hw)
76109 {
77110 struct ccu_common *common = hw_to_ccu_common(hw);
drivers/clk/sunxi-ng/ccu_nk.c+1−0
@@ -157,3 +157,4 @@ const struct clk_ops ccu_nk_ops = { · 156 unmodified lines
157157 .round_rate = ccu_nk_round_rate,
158158 .set_rate = ccu_nk_set_rate,
159159 };
160+EXPORT_SYMBOL_NS_GPL(ccu_nk_ops, SUNXI_CCU);
drivers/clk/sunxi-ng/ccu_nkm.c+1−0
@@ -206,3 +206,4 @@ const struct clk_ops ccu_nkm_ops = { · 205 unmodified lines
206206 .recalc_rate = ccu_nkm_recalc_rate,
207207 .set_rate = ccu_nkm_set_rate,
208208 };
209+EXPORT_SYMBOL_NS_GPL(ccu_nkm_ops, SUNXI_CCU);
drivers/clk/sunxi-ng/ccu_nkmp.c+1−0
@@ -230,3 +230,4 @@ const struct clk_ops ccu_nkmp_ops = { · 229 unmodified lines
230230 .round_rate = ccu_nkmp_round_rate,
231231 .set_rate = ccu_nkmp_set_rate,
232232 };
233+EXPORT_SYMBOL_NS_GPL(ccu_nkmp_ops, SUNXI_CCU);
drivers/clk/sunxi-ng/ccu_nm.c+1−0
@@ -238,3 +238,4 @@ const struct clk_ops ccu_nm_ops = { · 237 unmodified lines
238238 .round_rate = ccu_nm_round_rate,
239239 .set_rate = ccu_nm_set_rate,
240240 };
241+EXPORT_SYMBOL_NS_GPL(ccu_nm_ops, SUNXI_CCU);
drivers/clk/sunxi-ng/ccu_phase.c+1−0
@@ -121,3 +121,4 @@ const struct clk_ops ccu_phase_ops = { · 120 unmodified lines
121121 .get_phase = ccu_phase_get_phase,
122122 .set_phase = ccu_phase_set_phase,
123123 };
124+EXPORT_SYMBOL_NS_GPL(ccu_phase_ops, SUNXI_CCU);
drivers/clk/sunxi-ng/ccu_reset.c+1−0
@@ -75,3 +75,4 @@ const struct reset_control_ops ccu_reset_ops = { · 74 unmodified lines
7575 .reset = ccu_reset_reset,
7676 .status = ccu_reset_status,
7777 };
78+EXPORT_SYMBOL_NS_GPL(ccu_reset_ops, SUNXI_CCU);
drivers/clk/sunxi-ng/ccu_sdm.c+6−0
@@ -20,6 +20,7 @@ bool ccu_sdm_helper_is_enabled(struct ccu_common *common, · 19 unmodified lines
2020
2121 return !!(readl(common->base + sdm->tuning_reg) & sdm->tuning_enable);
2222 }
23+EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_is_enabled, SUNXI_CCU);
2324
2425 void ccu_sdm_helper_enable(struct ccu_common *common,
2526 struct ccu_sdm_internal *sdm,
@@ -49,6 +50,7 @@ void ccu_sdm_helper_enable(struct ccu_common *common, · 23 unmodified lines
4950 writel(reg | sdm->enable, common->base + common->reg);
5051 spin_unlock_irqrestore(common->lock, flags);
5152 }
53+EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_enable, SUNXI_CCU);
5254
5355 void ccu_sdm_helper_disable(struct ccu_common *common,
5456 struct ccu_sdm_internal *sdm)
@@ -69,6 +71,7 @@ void ccu_sdm_helper_disable(struct ccu_common *common, · 14 unmodified lines
6971 writel(reg & ~sdm->tuning_enable, common->base + sdm->tuning_reg);
7072 spin_unlock_irqrestore(common->lock, flags);
7173 }
74+EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_disable, SUNXI_CCU);
7275
7376 /*
7477 * Sigma delta modulation provides a way to do fractional-N frequency
@@ -102,6 +105,7 @@ bool ccu_sdm_helper_has_rate(struct ccu_common *common, · 27 unmodified lines
102105
103106 return false;
104107 }
108+EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_has_rate, SUNXI_CCU);
105109
106110 unsigned long ccu_sdm_helper_read_rate(struct ccu_common *common,
107111 struct ccu_sdm_internal *sdm,
@@ -132,6 +136,7 @@ unsigned long ccu_sdm_helper_read_rate(struct ccu_common *common, · 24 unmodified lines
132136 /* We can't calculate the effective clock rate, so just fail. */
133137 return 0;
134138 }
139+EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_read_rate, SUNXI_CCU);
135140
136141 int ccu_sdm_helper_get_factors(struct ccu_common *common,
137142 struct ccu_sdm_internal *sdm,
@@ -153,3 +158,4 @@ int ccu_sdm_helper_get_factors(struct ccu_common *common, · 15 unmodified lines
153158 /* nothing found */
154159 return -EINVAL;
155160 }
161+EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_get_factors, SUNXI_CCU);
drivers/clk/tegra/Makefile+1−0
@@ -1,6 +1,7 @@
11 # SPDX-License-Identifier: GPL-2.0
22 obj-y += clk.o
33 obj-y += clk-audio-sync.o
4+obj-y += clk-device.o
45 obj-y += clk-dfll.o
56 obj-y += clk-divider.o
67 obj-y += clk-periph.o
drivers/clk/tegra/clk-device.c+199−0
@@ -0,0 +1,199 @@
1+// SPDX-License-Identifier: GPL-2.0-only
2+
3+#include <linux/clk.h>
4+#include <linux/clk-provider.h>
5+#include <linux/mutex.h>
6+#include <linux/of_device.h>
7+#include <linux/platform_device.h>
8+#include <linux/pm_domain.h>
9+#include <linux/pm_opp.h>
10+#include <linux/pm_runtime.h>
11+#include <linux/slab.h>
12+
13+#include <soc/tegra/common.h>
14+
15+#include "clk.h"
16+
17+/*
18+ * This driver manages performance state of the core power domain for the
19+ * independent PLLs and system clocks. We created a virtual clock device
20+ * for such clocks, see tegra_clk_dev_register().
21+ */
22+
23+struct tegra_clk_device {
24+ struct notifier_block clk_nb;
25+ struct device *dev;
26+ struct clk_hw *hw;
27+ struct mutex lock;
28+};
29+
30+static int tegra_clock_set_pd_state(struct tegra_clk_device *clk_dev,
31+ unsigned long rate)
32+{
33+ struct device *dev = clk_dev->dev;
34+ struct dev_pm_opp *opp;
35+ unsigned int pstate;
36+
37+ opp = dev_pm_opp_find_freq_ceil(dev, &rate);
38+ if (opp == ERR_PTR(-ERANGE)) {
39+ /*
40+ * Some clocks may be unused by a particular board and they
41+ * may have uninitiated clock rate that is overly high. In
42+ * this case clock is expected to be disabled, but still we
43+ * need to set up performance state of the power domain and
44+ * not error out clk initialization. A typical example is
45+ * a PCIe clock on Android tablets.
46+ */
47+ dev_dbg(dev, "failed to find ceil OPP for %luHz\n", rate);
48+ opp = dev_pm_opp_find_freq_floor(dev, &rate);
49+ }
50+
51+ if (IS_ERR(opp)) {
52+ dev_err(dev, "failed to find OPP for %luHz: %pe\n", rate, opp);
53+ return PTR_ERR(opp);
54+ }
55+
56+ pstate = dev_pm_opp_get_required_pstate(opp, 0);
57+ dev_pm_opp_put(opp);
58+
59+ return dev_pm_genpd_set_performance_state(dev, pstate);
60+}
61+
62+static int tegra_clock_change_notify(struct notifier_block *nb,
63+ unsigned long msg, void *data)
64+{
65+ struct clk_notifier_data *cnd = data;
66+ struct tegra_clk_device *clk_dev;
67+ int err = 0;
68+
69+ clk_dev = container_of(nb, struct tegra_clk_device, clk_nb);
70+
71+ mutex_lock(&clk_dev->lock);
72+ switch (msg) {
73+ case PRE_RATE_CHANGE:
74+ if (cnd->new_rate > cnd->old_rate)
75+ err = tegra_clock_set_pd_state(clk_dev, cnd->new_rate);
76+ break;
77+
78+ case ABORT_RATE_CHANGE:
79+ err = tegra_clock_set_pd_state(clk_dev, cnd->old_rate);
80+ break;
81+
82+ case POST_RATE_CHANGE:
83+ if (cnd->new_rate < cnd->old_rate)
84+ err = tegra_clock_set_pd_state(clk_dev, cnd->new_rate);
85+ break;
86+
87+ default:
88+ break;
89+ }
90+ mutex_unlock(&clk_dev->lock);
91+
92+ return notifier_from_errno(err);
93+}
94+
95+static int tegra_clock_sync_pd_state(struct tegra_clk_device *clk_dev)
96+{
97+ unsigned long rate;
98+ int ret;
99+
100+ mutex_lock(&clk_dev->lock);
101+
102+ rate = clk_hw_get_rate(clk_dev->hw);
103+ ret = tegra_clock_set_pd_state(clk_dev, rate);
104+
105+ mutex_unlock(&clk_dev->lock);
106+
107+ return ret;
108+}
109+
110+static int tegra_clock_probe(struct platform_device *pdev)
111+{
112+ struct tegra_core_opp_params opp_params = {};
113+ struct tegra_clk_device *clk_dev;
114+ struct device *dev = &pdev->dev;
115+ struct clk *clk;
116+ int err;
117+
118+ if (!dev->pm_domain)
119+ return -EINVAL;
120+
121+ clk_dev = devm_kzalloc(dev, sizeof(*clk_dev), GFP_KERNEL);
122+ if (!clk_dev)
123+ return -ENOMEM;
124+
125+ clk = devm_clk_get(dev, NULL);
126+ if (IS_ERR(clk))
127+ return PTR_ERR(clk);
128+
129+ clk_dev->dev = dev;
130+ clk_dev->hw = __clk_get_hw(clk);
131+ clk_dev->clk_nb.notifier_call = tegra_clock_change_notify;
132+ mutex_init(&clk_dev->lock);
133+
134+ platform_set_drvdata(pdev, clk_dev);
135+
136+ /*
137+ * Runtime PM was already enabled for this device by the parent clk
138+ * driver and power domain state should be synced under clk_dev lock,
139+ * hence we don't use the common OPP helper that initializes OPP
140+ * state. For some clocks common OPP helper may fail to find ceil
141+ * rate, it's handled by this driver.
142+ */
143+ err = devm_tegra_core_dev_init_opp_table(dev, &opp_params);
144+ if (err)
145+ return err;
146+
147+ err = clk_notifier_register(clk, &clk_dev->clk_nb);
148+ if (err) {
149+ dev_err(dev, "failed to register clk notifier: %d\n", err);
150+ return err;
151+ }
152+
153+ /*
154+ * The driver is attaching to a potentially active/resumed clock, hence
155+ * we need to sync the power domain performance state in a accordance to
156+ * the clock rate if clock is resumed.
157+ */
158+ err = tegra_clock_sync_pd_state(clk_dev);
159+ if (err)
160+ goto unreg_clk;
161+
162+ return 0;
163+
164+unreg_clk:
165+ clk_notifier_unregister(clk, &clk_dev->clk_nb);
166+
167+ return err;
168+}
169+
170+/*
171+ * Tegra GENPD driver enables clocks during NOIRQ phase. It can't be done
172+ * for clocks served by this driver because runtime PM is unavailable in
173+ * NOIRQ phase. We will keep clocks resumed during suspend to mitigate this
174+ * problem. In practice this makes no difference from a power management
175+ * perspective since voltage is kept at a nominal level during suspend anyways.
176+ */
177+static const struct dev_pm_ops tegra_clock_pm = {
178+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_resume_and_get, pm_runtime_put)
179+};
180+
181+static const struct of_device_id tegra_clock_match[] = {
182+ { .compatible = "nvidia,tegra20-sclk" },
183+ { .compatible = "nvidia,tegra30-sclk" },
184+ { .compatible = "nvidia,tegra30-pllc" },
185+ { .compatible = "nvidia,tegra30-plle" },
186+ { .compatible = "nvidia,tegra30-pllm" },
187+ { }
188+};
189+
190+static struct platform_driver tegra_clock_driver = {
191+ .driver = {
192+ .name = "tegra-clock",
193+ .of_match_table = tegra_clock_match,
194+ .pm = &tegra_clock_pm,
195+ .suppress_bind_attrs = true,
196+ },
197+ .probe = tegra_clock_probe,
198+};
199+builtin_platform_driver(tegra_clock_driver);
drivers/clk/tegra/clk-pll.c+1−1
@@ -1914,7 +1914,7 @@ static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, · 1913 unmodified lines
19141914 /* Data in .init is copied by clk_register(), so stack variable OK */
19151915 pll->hw.init = &init;
19161916
1917− return clk_register(NULL, &pll->hw);
1917+ return tegra_clk_dev_register(&pll->hw);
19181918 }
19191919
19201920 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
drivers/clk/tegra/clk-super.c+1−1
@@ -226,7 +226,7 @@ struct clk *tegra_clk_register_super_mux(const char *name, · 225 unmodified lines
226226 /* Data in .init is copied by clk_register(), so stack variable OK */
227227 super->hw.init = &init;
228228
229− clk = clk_register(NULL, &super->hw);
229+ clk = tegra_clk_dev_register(&super->hw);
230230 if (IS_ERR(clk))
231231 kfree(super);
232232
drivers/clk/tegra/clk-tegra114.c+1−1
@@ -1158,7 +1158,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { · 1157 unmodified lines
11581158 { TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0 },
11591159 { TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 },
11601160 { TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 },
1161− { TEGRA114_CLK_VDE, TEGRA114_CLK_CLK_MAX, 600000000, 0 },
1161+ { TEGRA114_CLK_VDE, TEGRA114_CLK_PLL_P, 408000000, 0 },
11621162 { TEGRA114_CLK_SPDIF_IN_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
11631163 { TEGRA114_CLK_I2S0_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
11641164 { TEGRA114_CLK_I2S1_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
drivers/clk/tegra/clk-tegra20.c+59−18
@@ -6,8 +6,11 @@ · 5 unmodified lines
66 #include <linux/io.h>
77 #include <linux/clk-provider.h>
88 #include <linux/clkdev.h>
9+#include <linux/init.h>
910 #include <linux/of.h>
1011 #include <linux/of_address.h>
12+#include <linux/of_device.h>
13+#include <linux/platform_device.h>
1114 #include <linux/clk/tegra.h>
1215 #include <linux/delay.h>
1316 #include <dt-bindings/clock/tegra20-car.h>
@@ -414,7 +417,7 @@ static struct tegra_clk_pll_params pll_e_params = { · 400 unmodified lines
414417 .fixed_rate = 100000000,
415418 };
416419
417−static struct tegra_devclk devclks[] __initdata = {
420+static struct tegra_devclk devclks[] = {
418421 { .con_id = "pll_c", .dt_id = TEGRA20_CLK_PLL_C },
419422 { .con_id = "pll_c_out1", .dt_id = TEGRA20_CLK_PLL_C_OUT1 },
420423 { .con_id = "pll_p", .dt_id = TEGRA20_CLK_PLL_P },
@@ -710,13 +713,6 @@ static void tegra20_super_clk_init(void) · 289 unmodified lines
710713 NULL);
711714 clks[TEGRA20_CLK_CCLK] = clk;
712715
713− /* SCLK */
714− clk = tegra_clk_register_super_mux("sclk", sclk_parents,
715− ARRAY_SIZE(sclk_parents),
716− CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
717− clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
718− clks[TEGRA20_CLK_SCLK] = clk;
719−
720716 /* twd */
721717 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4);
722718 clks[TEGRA20_CLK_TWD] = clk;
@@ -1014,7 +1010,7 @@ static struct tegra_cpu_car_ops tegra20_cpu_car_ops = { · 291 unmodified lines
10141010 #endif
10151011 };
10161012
1017−static struct tegra_clk_init_table init_table[] __initdata = {
1013+static struct tegra_clk_init_table init_table[] = {
10181014 { TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1 },
10191015 { TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1 },
10201016 { TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1 },
@@ -1052,11 +1048,6 @@ static struct tegra_clk_init_table init_table[] __initdata = { · 31 unmodified lines
10521048 { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
10531049 };
10541050
1055−static void __init tegra20_clock_apply_init_table(void)
1056−{
1057− tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX);
1058−}
1059−
10601051 /*
10611052 * Some clocks may be used by different drivers depending on the board
10621053 * configuration. List those here to register them twice in the clock lookup
@@ -1076,6 +1067,8 @@ static const struct of_device_id pmc_match[] __initconst = { · 13 unmodified lines
10761067 { },
10771068 };
10781069
1070+static bool tegra20_car_initialized;
1071+
10791072 static struct clk *tegra20_clk_src_onecell_get(struct of_phandle_args *clkspec,
10801073 void *data)
10811074 {
@@ -1083,6 +1076,16 @@ static struct clk *tegra20_clk_src_onecell_get(struct of_phandle_args *clkspec, · 1 unmodified line
10831076 struct clk_hw *hw;
10841077 struct clk *clk;
10851078
1079+ /*
1080+ * Timer clocks are needed early, the rest of the clocks shouldn't be
1081+ * available to device drivers until clock tree is fully initialized.
1082+ */
1083+ if (clkspec->args[0] != TEGRA20_CLK_RTC &&
1084+ clkspec->args[0] != TEGRA20_CLK_TWD &&
1085+ clkspec->args[0] != TEGRA20_CLK_TIMER &&
1086+ !tegra20_car_initialized)
1087+ return ERR_PTR(-EPROBE_DEFER);
1088+
10861089 clk = of_clk_src_onecell_get(clkspec, data);
10871090 if (IS_ERR(clk))
10881091 return clk;
@@ -1149,10 +1152,48 @@ static void __init tegra20_clock_init(struct device_node *np) · 60 unmodified lines
11491152 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX);
11501153
11511154 tegra_add_of_provider(np, tegra20_clk_src_onecell_get);
1152− tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1153−
1154− tegra_clk_apply_init_table = tegra20_clock_apply_init_table;
11551155
11561156 tegra_cpu_car_ops = &tegra20_cpu_car_ops;
11571157 }
1158−CLK_OF_DECLARE(tegra20, "nvidia,tegra20-car", tegra20_clock_init);
1158+CLK_OF_DECLARE_DRIVER(tegra20, "nvidia,tegra20-car", tegra20_clock_init);
1159+
1160+/*
1161+ * Clocks that use runtime PM can't be created at the tegra20_clock_init
1162+ * time because drivers' base isn't initialized yet, and thus platform
1163+ * devices can't be created for the clocks. Hence we need to split the
1164+ * registration of the clocks into two phases. The first phase registers
1165+ * essential clocks which don't require RPM and are actually used during
1166+ * early boot. The second phase registers clocks which use RPM and this
1167+ * is done when device drivers' core API is ready.
1168+ */
1169+static int tegra20_car_probe(struct platform_device *pdev)
1170+{
1171+ struct clk *clk;
1172+
1173+ clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1174+ ARRAY_SIZE(sclk_parents),
1175+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1176+ clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
1177+ clks[TEGRA20_CLK_SCLK] = clk;
1178+
1179+ tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1180+ tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX);
1181+ tegra20_car_initialized = true;
1182+
1183+ return 0;
1184+}
1185+
1186+static const struct of_device_id tegra20_car_match[] = {
1187+ { .compatible = "nvidia,tegra20-car" },
1188+ { }
1189+};
1190+
1191+static struct platform_driver tegra20_car_driver = {
1192+ .driver = {
1193+ .name = "tegra20-car",
1194+ .of_match_table = tegra20_car_match,
1195+ .suppress_bind_attrs = true,
1196+ },
1197+ .probe = tegra20_car_probe,
1198+};
1199+builtin_platform_driver(tegra20_car_driver);
drivers/clk/tegra/clk-tegra30.c+85−31
@@ -7,8 +7,11 @@ · 6 unmodified lines
77 #include <linux/delay.h>
88 #include <linux/clk-provider.h>
99 #include <linux/clkdev.h>
10+#include <linux/init.h>
1011 #include <linux/of.h>
1112 #include <linux/of_address.h>
13+#include <linux/of_device.h>
14+#include <linux/platform_device.h>
1215 #include <linux/clk/tegra.h>
1316
1417 #include <soc/tegra/pmc.h>
@@ -532,7 +535,7 @@ static unsigned long tegra30_input_freq[] = { · 517 unmodified lines
532535 [12] = 26000000,
533536 };
534537
535−static struct tegra_devclk devclks[] __initdata = {
538+static struct tegra_devclk devclks[] = {
536539 { .con_id = "pll_c", .dt_id = TEGRA30_CLK_PLL_C },
537540 { .con_id = "pll_c_out1", .dt_id = TEGRA30_CLK_PLL_C_OUT1 },
538541 { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },
@@ -812,11 +815,6 @@ static void __init tegra30_pll_init(void) · 273 unmodified lines
812815 {
813816 struct clk *clk;
814817
815− /* PLLC */
816− clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
817− &pll_c_params, NULL);
818− clks[TEGRA30_CLK_PLL_C] = clk;
819−
820818 /* PLLC_OUT1 */
821819 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
822820 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
@@ -826,11 +824,6 @@ static void __init tegra30_pll_init(void) · 3 unmodified lines
826824 0, NULL);
827825 clks[TEGRA30_CLK_PLL_C_OUT1] = clk;
828826
829− /* PLLM */
830− clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
831− CLK_SET_RATE_GATE, &pll_m_params, NULL);
832− clks[TEGRA30_CLK_PLL_M] = clk;
833−
834827 /* PLLM_OUT1 */
835828 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
836829 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
@@ -880,9 +873,6 @@ static void __init tegra30_pll_init(void) · 43 unmodified lines
880873 ARRAY_SIZE(pll_e_parents),
881874 CLK_SET_RATE_NO_REPARENT,
882875 clk_base + PLLE_AUX, 2, 1, 0, NULL);
883− clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
884− CLK_GET_RATE_NOCACHE, &pll_e_params, NULL);
885− clks[TEGRA30_CLK_PLL_E] = clk;
886876 }
887877
888878 static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
@@ -971,14 +961,6 @@ static void __init tegra30_super_clk_init(void) · 82 unmodified lines
971961 NULL);
972962 clks[TEGRA30_CLK_CCLK_LP] = clk;
973963
974− /* SCLK */
975− clk = tegra_clk_register_super_mux("sclk", sclk_parents,
976− ARRAY_SIZE(sclk_parents),
977− CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
978− clk_base + SCLK_BURST_POLICY,
979− 0, 4, 0, 0, NULL);
980− clks[TEGRA30_CLK_SCLK] = clk;
981−
982964 /* twd */
983965 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",
984966 CLK_SET_RATE_PARENT, 1, 2);
@@ -1214,7 +1196,7 @@ static struct tegra_cpu_car_ops tegra30_cpu_car_ops = { · 229 unmodified lines
12141196 #endif
12151197 };
12161198
1217−static struct tegra_clk_init_table init_table[] __initdata = {
1199+static struct tegra_clk_init_table init_table[] = {
12181200 { TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0 },
12191201 { TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0 },
12201202 { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
@@ -1259,11 +1241,6 @@ static struct tegra_clk_init_table init_table[] __initdata = { · 38 unmodified lines
12591241 { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
12601242 };
12611243
1262−static void __init tegra30_clock_apply_init_table(void)
1263−{
1264− tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX);
1265−}
1266−
12671244 /*
12681245 * Some clocks may be used by different drivers depending on the board
12691246 * configuration. List those here to register them twice in the clock lookup
@@ -1294,12 +1271,24 @@ static struct tegra_audio_clk_info tegra30_audio_plls[] = { · 24 unmodified lines
12941271 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
12951272 };
12961273
1274+static bool tegra30_car_initialized;
1275+
12971276 static struct clk *tegra30_clk_src_onecell_get(struct of_phandle_args *clkspec,
12981277 void *data)
12991278 {
13001279 struct clk_hw *hw;
13011280 struct clk *clk;
13021281
1282+ /*
1283+ * Timer clocks are needed early, the rest of the clocks shouldn't be
1284+ * available to device drivers until clock tree is fully initialized.
1285+ */
1286+ if (clkspec->args[0] != TEGRA30_CLK_RTC &&
1287+ clkspec->args[0] != TEGRA30_CLK_TWD &&
1288+ clkspec->args[0] != TEGRA30_CLK_TIMER &&
1289+ !tegra30_car_initialized)
1290+ return ERR_PTR(-EPROBE_DEFER);
1291+
13031292 clk = of_clk_src_onecell_get(clkspec, data);
13041293 if (IS_ERR(clk))
13051294 return clk;
@@ -1357,10 +1346,75 @@ static void __init tegra30_clock_init(struct device_node *np) · 51 unmodified lines
13571346 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
13581347
13591348 tegra_add_of_provider(np, tegra30_clk_src_onecell_get);
1349+
1350+ tegra_cpu_car_ops = &tegra30_cpu_car_ops;
1351+}
1352+CLK_OF_DECLARE_DRIVER(tegra30, "nvidia,tegra30-car", tegra30_clock_init);
1353+
1354+/*
1355+ * Clocks that use runtime PM can't be created at the tegra30_clock_init
1356+ * time because drivers' base isn't initialized yet, and thus platform
1357+ * devices can't be created for the clocks. Hence we need to split the
1358+ * registration of the clocks into two phases. The first phase registers
1359+ * essential clocks which don't require RPM and are actually used during
1360+ * early boot. The second phase registers clocks which use RPM and this
1361+ * is done when device drivers' core API is ready.
1362+ */
1363+static int tegra30_car_probe(struct platform_device *pdev)
1364+{
1365+ struct clk *clk;
1366+
1367+ /* PLLC */
1368+ clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
1369+ &pll_c_params, NULL);
1370+ clks[TEGRA30_CLK_PLL_C] = clk;
1371+
1372+ /* PLLE */
1373+ clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
1374+ CLK_GET_RATE_NOCACHE, &pll_e_params, NULL);
1375+ clks[TEGRA30_CLK_PLL_E] = clk;
1376+
1377+ /* PLLM */
1378+ clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
1379+ CLK_SET_RATE_GATE, &pll_m_params, NULL);
1380+ clks[TEGRA30_CLK_PLL_M] = clk;
1381+
1382+ /* SCLK */
1383+ clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1384+ ARRAY_SIZE(sclk_parents),
1385+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1386+ clk_base + SCLK_BURST_POLICY,
1387+ 0, 4, 0, 0, NULL);
1388+ clks[TEGRA30_CLK_SCLK] = clk;
1389+
13601390 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1391+ tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX);
1392+ tegra30_car_initialized = true;
13611393
1362− tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
1394+ return 0;
1395+}
13631396
1364− tegra_cpu_car_ops = &tegra30_cpu_car_ops;
1397+static const struct of_device_id tegra30_car_match[] = {
1398+ { .compatible = "nvidia,tegra30-car" },
1399+ { }
1400+};
1401+
1402+static struct platform_driver tegra30_car_driver = {
1403+ .driver = {
1404+ .name = "tegra30-car",
1405+ .of_match_table = tegra30_car_match,
1406+ .suppress_bind_attrs = true,
1407+ },
1408+ .probe = tegra30_car_probe,
1409+};
1410+
1411+/*
1412+ * Clock driver must be registered before memory controller driver,
1413+ * which doesn't support deferred probing for today and is registered
1414+ * from arch init-level.
1415+ */
1416+static int tegra30_car_init(void)
1417+{
1418+ return platform_driver_register(&tegra30_car_driver);
13651419 }
1366−CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init);
1420+postcore_initcall(tegra30_car_init);
drivers/clk/tegra/clk.c+72−3
@@ -9,14 +9,19 @@ · 8 unmodified lines
99 #include <linux/delay.h>
1010 #include <linux/io.h>
1111 #include <linux/of.h>
12+#include <linux/of_device.h>
1213 #include <linux/clk/tegra.h>
14+#include <linux/platform_device.h>
15+#include <linux/pm_runtime.h>
1316 #include <linux/reset-controller.h>
17+#include <linux/string.h>
1418
1519 #include <soc/tegra/fuse.h>
1620
1721 #include "clk.h"
1822
1923 /* Global data of Tegra CPU CAR ops */
24+static struct device_node *tegra_car_np;
2025 static struct tegra_cpu_car_ops dummy_car_ops;
2126 struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
2227
@@ -261,8 +266,8 @@ void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, · 238 unmodified lines
261266 }
262267 }
263268
264−void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
265− struct clk *clks[], int clk_max)
269+void tegra_init_from_table(struct tegra_clk_init_table *tbl,
270+ struct clk *clks[], int clk_max)
266271 {
267272 struct clk *clk;
268273
@@ -320,6 +325,8 @@ void __init tegra_add_of_provider(struct device_node *np, · 51 unmodified lines
320325 {
321326 int i;
322327
328+ tegra_car_np = np;
329+
323330 for (i = 0; i < clk_num; i++) {
324331 if (IS_ERR(clks[i])) {
325332 pr_err
@@ -348,7 +355,7 @@ void __init tegra_init_special_resets(unsigned int num, · 22 unmodified lines
348355 special_reset_deassert = deassert;
349356 }
350357
351−void __init tegra_register_devclks(struct tegra_devclk *dev_clks, int num)
358+void tegra_register_devclks(struct tegra_devclk *dev_clks, int num)
352359 {
353360 int i;
354361
@@ -372,6 +379,68 @@ struct clk ** __init tegra_lookup_dt_id(int clk_id, · 17 unmodified lines
372379 return NULL;
373380 }
374381
382+static struct device_node *tegra_clk_get_of_node(struct clk_hw *hw)
383+{
384+ struct device_node *np;
385+ char *node_name;
386+
387+ node_name = kstrdup(hw->init->name, GFP_KERNEL);
388+ if (!node_name)
389+ return NULL;
390+
391+ strreplace(node_name, '_', '-');
392+
393+ for_each_child_of_node(tegra_car_np, np) {
394+ if (!strcmp(np->name, node_name))
395+ break;
396+ }
397+
398+ kfree(node_name);
399+
400+ return np;
401+}
402+
403+struct clk *tegra_clk_dev_register(struct clk_hw *hw)
404+{
405+ struct platform_device *pdev, *parent;
406+ const char *dev_name = NULL;
407+ struct device *dev = NULL;
408+ struct device_node *np;
409+
410+ np = tegra_clk_get_of_node(hw);
411+
412+ if (!of_device_is_available(np))
413+ goto put_node;
414+
415+ dev_name = kasprintf(GFP_KERNEL, "tegra_clk_%s", hw->init->name);
416+ if (!dev_name)
417+ goto put_node;
418+
419+ parent = of_find_device_by_node(tegra_car_np);
420+ if (parent) {
421+ pdev = of_platform_device_create(np, dev_name, &parent->dev);
422+ put_device(&parent->dev);
423+
424+ if (!pdev) {
425+ pr_err("%s: failed to create device for %pOF\n",
426+ __func__, np);
427+ goto free_name;
428+ }
429+
430+ dev = &pdev->dev;
431+ pm_runtime_enable(dev);
432+ } else {

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