lael-labs/linux

drivers/gpu/drm/amd/amdgpu/Makefile+2−1

@@ -81,7 +81,8 @@ amdgpu-y += \ · 80 unmodified lines
81	# add DF block	81	# add DF block
82	amdgpu-y += \	82	amdgpu-y += \
83	df_v1_7.o \	83	df_v1_7.o \
84	df_v3_6.o	84	df_v3_6.o \
		85	df_v4_3.o
85		86
86	# add GMC block	87	# add GMC block
87	amdgpu-y += \	88	amdgpu-y += \

drivers/gpu/drm/amd/amdgpu/amdgpu.h+10−4

  * Modules parameters.
  */
 extern int amdgpu_modeset;
-extern int amdgpu_vram_limit;
+extern unsigned int amdgpu_vram_limit;
 extern int amdgpu_vis_vram_limit;
 extern int amdgpu_gart_size;
 extern int amdgpu_gtt_size;
 extern uint amdgpu_smu_memory_pool_size;
 extern int amdgpu_smu_pptable_id;
 extern uint amdgpu_dc_feature_mask;
+extern uint amdgpu_freesync_vid_mode;
 extern uint amdgpu_dc_debug_mask;
 extern uint amdgpu_dc_visual_confirm;
 extern uint amdgpu_dm_abm_level;
 				struct drm_file *filp);
 /* VRAM scratch page for HDP bug, default vram page */
-struct amdgpu_vram_scratch {
+struct amdgpu_mem_scratch {
 	struct amdgpu_bo		*robj;
 	volatile uint32_t		*ptr;
 	u64				gpu_addr;
 #define AMDGPU_PRODUCT_NAME_LEN 64
 struct amdgpu_reset_domain;
+/*
+ * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise.
+ */
+#define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size)
 struct amdgpu_device {
 	struct device			*dev;
 	struct pci_dev			*pdev;
 	/* memory management */
 	struct amdgpu_mman		mman;
-	struct amdgpu_vram_scratch	vram_scratch;
+	struct amdgpu_mem_scratch	mem_scratch;
 	struct amdgpu_wb		wb;
 	atomic64_t			num_bytes_moved;
 	atomic64_t			num_evictions;
 	struct amdgpu_vkms_output       *amdgpu_vkms_output;
 	struct amdgpu_mode_info		mode_info;
 	/* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
-	struct work_struct		hotplug_work;
+	struct delayed_work         hotplug_work;
 	struct amdgpu_irq_src		crtc_irq;
 	struct amdgpu_irq_src		vline0_irq;
 	struct amdgpu_irq_src		vupdate_irq;

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c+21−1

@@ -996,13 +996,33 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) · 995 unmodified lines
996	}	996	}
997	}	997	}
998		998
		999	if (amdgpu_connector->detected_hpd_without_ddc) {
		1000	force = true;
		1001	amdgpu_connector->detected_hpd_without_ddc = false;
		1002	}
		1003
999	if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {	1004	if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1000	ret = connector->status;	1005	ret = connector->status;
1001	goto exit;	1006	goto exit;
1002	}	1007	}
1003		1008
1004	if (amdgpu_connector->ddc_bus)	1009	if (amdgpu_connector->ddc_bus) {
1005	dret = amdgpu_display_ddc_probe(amdgpu_connector, false);	1010	dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
		1011
		1012	/* Sometimes the pins required for the DDC probe on DVI
		1013	* connectors don't make contact at the same time that the ones
		1014	* for HPD do. If the DDC probe fails even though we had an HPD
		1015	* signal, try again later
		1016	*/
		1017	if (!dret && !force &&
		1018	amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
		1019	DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n");
		1020	amdgpu_connector->detected_hpd_without_ddc = true;
		1021	schedule_delayed_work(&adev->hotplug_work,
		1022	msecs_to_jiffies(1000));
		1023	goto exit;
		1024	}
		1025	}
1006	if (dret) {	1026	if (dret) {
1007	amdgpu_connector->detected_by_load = false;	1027	amdgpu_connector->detected_by_load = false;
1008	amdgpu_connector_free_edid(connector);	1028	amdgpu_connector_free_edid(connector);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+31−41

 }
 /**
- * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
+ * amdgpu_device_mem_scratch_init - allocate the VRAM scratch page
  *
  * @adev: amdgpu_device pointer
  *
  * Allocates a scratch page of VRAM for use by various things in the
  * driver.
  */
-static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
+static int amdgpu_device_mem_scratch_init(struct amdgpu_device *adev)
 {
-	return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
+	return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE,
-				       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
+				       AMDGPU_GEM_DOMAIN_VRAM |
-				       &adev->vram_scratch.robj,
+				       AMDGPU_GEM_DOMAIN_GTT,
-				       &adev->vram_scratch.gpu_addr,
+				       &adev->mem_scratch.robj,
-				       (void **)&adev->vram_scratch.ptr);
+				       &adev->mem_scratch.gpu_addr,
+				       (void **)&adev->mem_scratch.ptr);
 }
 /**
- * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
+ * amdgpu_device_mem_scratch_fini - Free the VRAM scratch page
  *
  * @adev: amdgpu_device pointer
  *
  * Frees the VRAM scratch page.
  */
-static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
+static void amdgpu_device_mem_scratch_fini(struct amdgpu_device *adev)
 {
-	amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
+	amdgpu_bo_free_kernel(&adev->mem_scratch.robj, NULL, NULL);
 }
 /**
 			if (amdgpu_sriov_vf(adev))
 				amdgpu_virt_exchange_data(adev);
-			r = amdgpu_device_vram_scratch_init(adev);
+			r = amdgpu_device_mem_scratch_init(adev);
 			if (r) {
-				DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
+				DRM_ERROR("amdgpu_mem_scratch_init failed %d\n", r);
 				goto init_failed;
 			}
 			r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
 			/* right after GMC hw init, we create CSA */
 			if (amdgpu_mcbp) {
 				r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
-								AMDGPU_GEM_DOMAIN_VRAM,
+							       AMDGPU_GEM_DOMAIN_VRAM |
-								AMDGPU_CSA_SIZE);
+							       AMDGPU_GEM_DOMAIN_GTT,
+							       AMDGPU_CSA_SIZE);
 				if (r) {
 					DRM_ERROR("allocate CSA failed %d\n", r);
 					goto init_failed;
 		i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
 		if (!adev->ip_blocks[i].status.late_initialized)
 			continue;
-		/* skip CG for GFX on S0ix */
+		/* skip CG for GFX, SDMA on S0ix */
 		if (adev->in_s0ix &&
-		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX)
+		    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
+		     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
 			continue;
 		/* skip CG for VCE/UVD, it's handled specially */
 		if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
 		i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
 		if (!adev->ip_blocks[i].status.late_initialized)
 			continue;
-		/* skip PG for GFX on S0ix */
+		/* skip PG for GFX, SDMA on S0ix */
 		if (adev->in_s0ix &&
-		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX)
+		    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
+		     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
 			continue;
 		/* skip CG for VCE/UVD, it's handled specially */
 		if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
 			amdgpu_ucode_free_bo(adev);
 			amdgpu_free_static_csa(&adev->virt.csa_obj);
 			amdgpu_device_wb_fini(adev);
-			amdgpu_device_vram_scratch_fini(adev);
+			amdgpu_device_mem_scratch_fini(adev);
 			amdgpu_ib_pool_fini(adev);
 		}
 		     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_MES))
 			continue;
+		/* SDMA 5.x+ is part of GFX power domain so it's covered by GFXOFF */
+		if (adev->in_s0ix &&
+		    (adev->ip_versions[SDMA0_HWIP][0] >= IP_VERSION(5, 0, 0)) &&
+		    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
+			continue;
 		/* XXX handle errors */
 		r = adev->ip_blocks[i].version->funcs->suspend(adev);
 		/* XXX handle errors */
 			return r;
 		}
 		adev->ip_blocks[i].status.hw = true;
-		if (adev->in_s0ix && adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
-			/* disable gfxoff for IP resume. The gfxoff will be re-enabled in
-			 * amdgpu_device_resume() after IP resume.
-			 */
-			amdgpu_gfx_off_ctrl(adev, false);
-			DRM_DEBUG("will disable gfxoff for re-initializing other blocks\n");
-		}
 	}
 	return 0;
 	/* Make sure IB tests flushed */
 	flush_delayed_work(&adev->delayed_init_work);
-	if (adev->in_s0ix) {
-		/* re-enable gfxoff after IP resume. This re-enables gfxoff after
-		 * it was disabled for IP resume in amdgpu_device_ip_resume_phase2().
-		 */
-		amdgpu_gfx_off_ctrl(adev, true);
-		DRM_DEBUG("will enable gfxoff for the mission mode\n");
-	}
 	if (fbcon)
 		drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false);
 	if (!amdgpu_ras_is_poison_mode_supported(adev))
 		return true;
-	if (!amdgpu_device_ip_check_soft_reset(adev)) {
-		dev_info(adev->dev,"Timeout, but no hardware hang detected.\n");
-		return false;
-	}
 	if (amdgpu_sriov_vf(adev))
 		return true;
 		if (!need_full_reset)
 			need_full_reset = amdgpu_device_ip_need_full_reset(adev);
-		if (!need_full_reset && amdgpu_gpu_recovery) {
+		if (!need_full_reset && amdgpu_gpu_recovery &&
+		    amdgpu_device_ip_check_soft_reset(adev)) {
 			amdgpu_device_ip_pre_soft_reset(adev);
 			r = amdgpu_device_ip_soft_reset(adev);
 			amdgpu_device_ip_post_soft_reset(adev);

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c+4−0

 #include "gmc_v9_0.h"
 #include "df_v1_7.h"
 #include "df_v3_6.h"
+#include "df_v4_3.h"
 #include "nbio_v6_1.h"
 #include "nbio_v7_0.h"
 #include "nbio_v7_4.h"
 	case IP_VERSION(3, 5, 2):
 		adev->df.funcs = &df_v1_7_funcs;
 		break;
+	case IP_VERSION(4, 3, 0):
+		adev->df.funcs = &df_v4_3_funcs;
+		break;
 	default:
 		break;
 	}

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c+1−1

@@ -63,7 +63,7 @@ · 62 unmodified lines
63	void amdgpu_display_hotplug_work_func(struct work_struct *work)	63	void amdgpu_display_hotplug_work_func(struct work_struct *work)
64	{	64	{
65	struct amdgpu_device *adev = container_of(work, struct amdgpu_device,	65	struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
66	hotplug_work);	66	hotplug_work.work);
67	struct drm_device *dev = adev_to_drm(adev);	67	struct drm_device *dev = adev_to_drm(adev);
68	struct drm_mode_config *mode_config = &dev->mode_config;	68	struct drm_mode_config *mode_config = &dev->mode_config;
69	struct drm_connector *connector;	69	struct drm_connector *connector;

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+32−3

@@ -105,13 +105,15 @@ · 104 unmodified lines
105	* - 3.46.0 - To enable hot plug amdgpu tests in libdrm	105	* - 3.46.0 - To enable hot plug amdgpu tests in libdrm
106	* - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags	106	* - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
107	* - 3.48.0 - Add IP discovery version info to HW INFO	107	* - 3.48.0 - Add IP discovery version info to HW INFO
108	* 3.49.0 - Add gang submit into CS IOCTL	108	* - 3.49.0 - Add gang submit into CS IOCTL
		109	* - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock
		110	* Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock
109	*/	111	*/
110	#define KMS_DRIVER_MAJOR 3	112	#define KMS_DRIVER_MAJOR 3
111	#define KMS_DRIVER_MINOR 49	113	#define KMS_DRIVER_MINOR 50
112	#define KMS_DRIVER_PATCHLEVEL 0	114	#define KMS_DRIVER_PATCHLEVEL 0
113		115
114	int amdgpu_vram_limit;	116	unsigned int amdgpu_vram_limit = UINT_MAX;
115	int amdgpu_vis_vram_limit;	117	int amdgpu_vis_vram_limit;
116	int amdgpu_gart_size = -1; /* auto */	118	int amdgpu_gart_size = -1; /* auto */
117	int amdgpu_gtt_size = -1; /* auto */	119	int amdgpu_gtt_size = -1; /* auto */
@@ -181,6 +183,7 @@ int amdgpu_mes_kiq; · 63 unmodified lines
181	int amdgpu_noretry = -1;	183	int amdgpu_noretry = -1;
182	int amdgpu_force_asic_type = -1;	184	int amdgpu_force_asic_type = -1;
183	int amdgpu_tmz = -1; /* auto */	185	int amdgpu_tmz = -1; /* auto */
		186	uint amdgpu_freesync_vid_mode;
184	int amdgpu_reset_method = -1; /* auto */	187	int amdgpu_reset_method = -1; /* auto */
185	int amdgpu_num_kcq = -1;	188	int amdgpu_num_kcq = -1;
186	int amdgpu_smartshift_bias;	189	int amdgpu_smartshift_bias;
@@ -879,6 +882,32 @@ module_param_named(backlight, amdgpu_backlight, bint, 0444); · 692 unmodified lines
879	MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");	882	MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
880	module_param_named(tmz, amdgpu_tmz, int, 0444);	883	module_param_named(tmz, amdgpu_tmz, int, 0444);
881		884
		885	/**
		886	* DOC: freesync_video (uint)
		887	* Enable the optimization to adjust front porch timing to achieve seamless
		888	* mode change experience when setting a freesync supported mode for which full
		889	* modeset is not needed.
		890	*
		891	* The Display Core will add a set of modes derived from the base FreeSync
		892	* video mode into the corresponding connector's mode list based on commonly
		893	* used refresh rates and VRR range of the connected display, when users enable
		894	* this feature. From the userspace perspective, they can see a seamless mode
		895	* change experience when the change between different refresh rates under the
		896	* same resolution. Additionally, userspace applications such as Video playback
		897	* can read this modeset list and change the refresh rate based on the video
		898	* frame rate. Finally, the userspace can also derive an appropriate mode for a
		899	* particular refresh rate based on the FreeSync Mode and add it to the
		900	* connector's mode list.
		901	*
		902	* Note: This is an experimental feature.
		903	*
		904	* The default value: 0 (off).
		905	*/
		906	MODULE_PARM_DESC(
		907	freesync_video,
		908	"Enable freesync modesetting optimization feature (0 = off (default), 1 = on)");
		909	module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);
		910
882	/**	911	/**
883	* DOC: reset_method (int)	912	* DOC: reset_method (int)
884	* GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)	913	* GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c+5−2

 		 * KIQ MQD no matter SRIOV or Bare-metal
 		 */
 		r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
-					    AMDGPU_GEM_DOMAIN_VRAM, &ring->mqd_obj,
+					    AMDGPU_GEM_DOMAIN_VRAM |
-					    &ring->mqd_gpu_addr, &ring->mqd_ptr);
+					    AMDGPU_GEM_DOMAIN_GTT,
+					    &ring->mqd_obj,
+					    &ring->mqd_gpu_addr,
+					    &ring->mqd_ptr);
 		if (r) {
 			dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
 			return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c+8−1

 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
 			      u64 base)
 {
+	uint64_t vis_limit = (uint64_t)amdgpu_vis_vram_limit << 20;
 	uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
 	mc->vram_start = base;
 	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
-	if (limit && limit < mc->real_vram_size)
+	if (limit < mc->real_vram_size)
 		mc->real_vram_size = limit;
+	if (vis_limit && vis_limit < mc->visible_vram_size)
+		mc->visible_vram_size = vis_limit;
+	if (mc->real_vram_size < mc->visible_vram_size)
+		mc->visible_vram_size = mc->real_vram_size;
 	if (mc->xgmi.num_physical_nodes == 0) {
 		mc->fb_start = mc->vram_start;
 		mc->fb_end = mc->vram_end;

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c+26−2

@@ -785,9 +785,15 @@ int amdgpu_info_ioctl(struct drm_device dev, void data, struct drm_file *filp) · 784 unmodified lines
785	if (adev->pm.dpm_enabled) {	785	if (adev->pm.dpm_enabled) {
786	dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;	786	dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
787	dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;	787	dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
		788	dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10;
		789	dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10;
788	} else {	790	} else {
789	dev_info->max_engine_clock = adev->clock.default_sclk * 10;	791	dev_info->max_engine_clock =
790	dev_info->max_memory_clock = adev->clock.default_mclk * 10;	792	dev_info->min_engine_clock =
		793	adev->clock.default_sclk * 10;
		794	dev_info->max_memory_clock =
		795	dev_info->min_memory_clock =
		796	adev->clock.default_mclk * 10;
791	}	797	}
792	dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;	798	dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
793	dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *	799	dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
@@ -1014,6 +1020,24 @@ int amdgpu_info_ioctl(struct drm_device dev, void data, struct drm_file *filp) · 220 unmodified lines
1014	}	1020	}
1015	ui32 /= 100;	1021	ui32 /= 100;
1016	break;	1022	break;
		1023	case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK:
		1024	/* get peak pstate sclk in Mhz */
		1025	if (amdgpu_dpm_read_sensor(adev,
		1026	AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
		1027	(void *)&ui32, &ui32_size)) {
		1028	return -EINVAL;
		1029	}
		1030	ui32 /= 100;
		1031	break;
		1032	case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK:
		1033	/* get peak pstate mclk in Mhz */
		1034	if (amdgpu_dpm_read_sensor(adev,
		1035	AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
		1036	(void *)&ui32, &ui32_size)) {
		1037	return -EINVAL;
		1038	}
		1039	ui32 /= 100;
		1040	break;
1017	default:	1041	default:
1018	DRM_DEBUG_KMS("Invalid request %d\n",	1042	DRM_DEBUG_KMS("Invalid request %d\n",
1019	info->sensor_info.type);	1043	info->sensor_info.type);

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h+1−0

@@ -534,6 +534,7 @@ struct amdgpu_connector { · 533 unmodified lines
534	void *con_priv;	534	void *con_priv;
535	bool dac_load_detect;	535	bool dac_load_detect;
536	bool detected_by_load; /* if the connection status was determined by load */	536	bool detected_by_load; /* if the connection status was determined by load */
		537	bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */
537	uint16_t connector_object_id;	538	uint16_t connector_object_id;
538	struct amdgpu_hpd hpd;	539	struct amdgpu_hpd hpd;
539	struct amdgpu_router router;	540	struct amdgpu_router router;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c+16−10

 	/* allocate 4k Page of Local Frame Buffer memory for ring */
 	ring->ring_size = 0x1000;
 	ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
-				      AMDGPU_GEM_DOMAIN_VRAM,
+				      AMDGPU_GEM_DOMAIN_VRAM |
+				      AMDGPU_GEM_DOMAIN_GTT,
 				      &adev->firmware.rbuf,
 				      &ring->ring_mem_mc_addr,
 				      (void **)&ring->ring_mem);
 	if (!psp->tmr_bo) {
 		pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
-		ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_ALIGNMENT,
+		ret = amdgpu_bo_create_kernel(psp->adev, tmr_size,
-					      AMDGPU_GEM_DOMAIN_VRAM,
+					      PSP_TMR_ALIGNMENT,
-					      &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
+					      AMDGPU_HAS_VRAM(psp->adev) ?
+					      AMDGPU_GEM_DOMAIN_VRAM :
+					      AMDGPU_GEM_DOMAIN_GTT,
+					      &psp->tmr_bo, &psp->tmr_mc_addr,
+					      pptr);
 	}
 	return ret;
 	* physical) for ta to host memory
 	*/
 	return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
-				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
+				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM |
+				      AMDGPU_GEM_DOMAIN_GTT,
 				      &mem_ctx->shared_bo,
 				      &mem_ctx->shared_mc_addr,
 				      &mem_ctx->shared_buf);
 static int psp_securedisplay_initialize(struct psp_context *psp)
 {
 	int ret;
-	struct securedisplay_cmd *securedisplay_cmd;
+	struct ta_securedisplay_cmd *securedisplay_cmd;
 	/*
 	 * TODO: bypass the initialize in sriov for now
 	/* LFB address which is aligned to 1MB boundary per PSP request */
 	ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
-						AMDGPU_GEM_DOMAIN_VRAM,
+				      AMDGPU_GEM_DOMAIN_VRAM |
-						&fw_buf_bo,
+				      AMDGPU_GEM_DOMAIN_GTT,
-						&fw_pri_mc_addr,
+				      &fw_buf_bo, &fw_pri_mc_addr,
-						&fw_pri_cpu_addr);
+				      &fw_pri_cpu_addr);
 	if (ret)
 		goto rel_buf;

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c+132−55

@@ -706,13 +706,23 @@ static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, · 705 unmodified lines
706	return 0;	706	return 0;
707	}	707	}
708		708
		709	static int amdgpu_ras_check_feature_allowed(struct amdgpu_device *adev,
		710	struct ras_common_if *head)
		711	{
		712	if (amdgpu_ras_is_feature_allowed(adev, head) \|\|
		713	amdgpu_ras_is_poison_mode_supported(adev))
		714	return 1;
		715	else
		716	return 0;
		717	}
		718
709	/* wrapper of psp_ras_enable_features */	719	/* wrapper of psp_ras_enable_features */
710	int amdgpu_ras_feature_enable(struct amdgpu_device *adev,	720	int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
711	struct ras_common_if *head, bool enable)	721	struct ras_common_if *head, bool enable)
712	{	722	{
713	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);	723	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
714	union ta_ras_cmd_input *info;	724	union ta_ras_cmd_input *info;
715	int ret;	725	int ret = 0;
716		726
717	if (!con)	727	if (!con)
718	return -EINVAL;	728	return -EINVAL;
@@ -736,7 +746,8 @@ int amdgpu_ras_feature_enable(struct amdgpu_device *adev, · 17 unmodified lines
736	}	746	}
737		747
738	/* Do not enable if it is not allowed. */	748	/* Do not enable if it is not allowed. */
739	WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));	749	if (enable && !amdgpu_ras_check_feature_allowed(adev, head))
		750	goto out;
740		751
741	/* Only enable ras feature operation handle on host side */	752	/* Only enable ras feature operation handle on host side */
742	if (head->block == AMDGPU_RAS_BLOCK__GFX &&	753	if (head->block == AMDGPU_RAS_BLOCK__GFX &&
@@ -754,7 +765,6 @@ int amdgpu_ras_feature_enable(struct amdgpu_device *adev, · 11 unmodified lines
754		765
755	/* setup the obj */	766	/* setup the obj */
756	__amdgpu_ras_feature_enable(adev, head, enable);	767	__amdgpu_ras_feature_enable(adev, head, enable);
757	ret = 0;
758	out:	768	out:
759	if (head->block == AMDGPU_RAS_BLOCK__GFX)	769	if (head->block == AMDGPU_RAS_BLOCK__GFX)
760	kfree(info);	770	kfree(info);
@@ -1087,6 +1097,10 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev, · 326 unmodified lines
1087	info->head.block,	1097	info->head.block,
1088	info->head.sub_block_index);	1098	info->head.sub_block_index);
1089		1099
		1100	/* inject on guest isn't allowed, return success directly */
		1101	if (amdgpu_sriov_vf(adev))
		1102	return 0;
		1103
1090	if (!obj)	1104	if (!obj)
1091	return -EINVAL;	1105	return -EINVAL;
1092		1106
@@ -1122,11 +1136,54 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev, · 29 unmodified lines
1122	}	1136	}
1123		1137
1124	/**	1138	/**
1125	* amdgpu_ras_query_error_count -- Get error counts of all IPs	1139	* amdgpu_ras_query_error_count_helper -- Get error counter for specific IP
		1140	* @adev: pointer to AMD GPU device
		1141	* @ce_count: pointer to an integer to be set to the count of correctible errors.
		1142	* @ue_count: pointer to an integer to be set to the count of uncorrectible errors.
		1143	* @query_info: pointer to ras_query_if
		1144	*
		1145	* Return 0 for query success or do nothing, otherwise return an error
		1146	* on failures
		1147	*/
		1148	static int amdgpu_ras_query_error_count_helper(struct amdgpu_device *adev,
		1149	unsigned long *ce_count,
		1150	unsigned long *ue_count,
		1151	struct ras_query_if *query_info)
		1152	{
		1153	int ret;
		1154
		1155	if (!query_info)
		1156	/* do nothing if query_info is not specified */
		1157	return 0;
		1158
		1159	ret = amdgpu_ras_query_error_status(adev, query_info);
		1160	if (ret)
		1161	return ret;
		1162
		1163	*ce_count += query_info->ce_count;
		1164	*ue_count += query_info->ue_count;
		1165
		1166	/* some hardware/IP supports read to clear
		1167	* no need to explictly reset the err status after the query call */
		1168	if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
		1169	adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
		1170	if (amdgpu_ras_reset_error_status(adev, query_info->head.block))
		1171	dev_warn(adev->dev,
		1172	"Failed to reset error counter and error status\n");
		1173	}
		1174
		1175	return 0;
		1176	}
		1177
		1178	/**
		1179	* amdgpu_ras_query_error_count -- Get error counts of all IPs or specific IP
1126	* @adev: pointer to AMD GPU device	1180	* @adev: pointer to AMD GPU device
1127	* @ce_count: pointer to an integer to be set to the count of correctible errors.	1181	* @ce_count: pointer to an integer to be set to the count of correctible errors.
1128	* @ue_count: pointer to an integer to be set to the count of uncorrectible	1182	* @ue_count: pointer to an integer to be set to the count of uncorrectible
1129	* errors.	1183	* errors.
		1184	* @query_info: pointer to ras_query_if if the query request is only for
		1185	* specific ip block; if info is NULL, then the qurey request is for
		1186	* all the ip blocks that support query ras error counters/status
1130	*	1187	*
1131	* If set, @ce_count or @ue_count, count and return the corresponding	1188	* If set, @ce_count or @ue_count, count and return the corresponding
1132	* error counts in those integer pointers. Return 0 if the device	1189	* error counts in those integer pointers. Return 0 if the device
@@ -1134,11 +1191,13 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev, · 1 unmodified line
1134	*/	1191	*/
1135	int amdgpu_ras_query_error_count(struct amdgpu_device *adev,	1192	int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1136	unsigned long *ce_count,	1193	unsigned long *ce_count,
1137	unsigned long *ue_count)	1194	unsigned long *ue_count,
		1195	struct ras_query_if *query_info)
1138	{	1196	{
1139	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);	1197	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1140	struct ras_manager *obj;	1198	struct ras_manager *obj;
1141	unsigned long ce, ue;	1199	unsigned long ce, ue;
		1200	int ret;
1142		1201
1143	if (!adev->ras_enabled \|\| !con)	1202	if (!adev->ras_enabled \|\| !con)
1144	return -EOPNOTSUPP;	1203	return -EOPNOTSUPP;
@@ -1150,26 +1209,23 @@ int amdgpu_ras_query_error_count(struct amdgpu_device *adev, · 5 unmodified lines
1150		1209
1151	ce = 0;	1210	ce = 0;
1152	ue = 0;	1211	ue = 0;
1153	list_for_each_entry(obj, &con->head, node) {	1212	if (!query_info) {
1154	struct ras_query_if info = {	1213	/* query all the ip blocks that support ras query interface */
1155	.head = obj->head,	1214	list_for_each_entry(obj, &con->head, node) {
1156	};	1215	struct ras_query_if info = {
1157	int res;	1216	.head = obj->head,
1158		1217	};
1159	res = amdgpu_ras_query_error_status(adev, &info);
1160	if (res)
1161	return res;
1162		1218
1163	if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&	1219	ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, &info);
1164	adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
1165	if (amdgpu_ras_reset_error_status(adev, info.head.block))
1166	dev_warn(adev->dev, "Failed to reset error counter and error status");
1167	}	1220	}
1168		1221	} else {
1169	ce += info.ce_count;	1222	/* query specific ip block */
1170	ue += info.ue_count;	1223	ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, query_info);
1171	}	1224	}
1172		1225
		1226	if (ret)
		1227	return ret;
		1228
1173	if (ce_count)	1229	if (ce_count)
1174	*ce_count = ce;	1230	*ce_count = ce;
1175		1231
@@ -2344,22 +2400,24 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev) · 1168 unmodified lines
2344		2400
2345	if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {	2401	if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2346	dev_info(adev->dev, "SRAM ECC is active.\n");	2402	dev_info(adev->dev, "SRAM ECC is active.\n");
2347	if (!amdgpu_sriov_vf(adev)) {	2403	if (!amdgpu_sriov_vf(adev))
2348	adev->ras_hw_enabled \|= ~(1 << AMDGPU_RAS_BLOCK__UMC \|	2404	adev->ras_hw_enabled \|= ~(1 << AMDGPU_RAS_BLOCK__UMC \|
2349	1 << AMDGPU_RAS_BLOCK__DF);	2405	1 << AMDGPU_RAS_BLOCK__DF);
2350		2406	else
2351	if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(2, 6, 0) \|\|
2352	adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 0))
2353	adev->ras_hw_enabled \|= (1 << AMDGPU_RAS_BLOCK__VCN \|
2354	1 << AMDGPU_RAS_BLOCK__JPEG);
2355	else
2356	adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN \|
2357	1 << AMDGPU_RAS_BLOCK__JPEG);
2358	} else {
2359	adev->ras_hw_enabled \|= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF \|	2407	adev->ras_hw_enabled \|= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF \|
2360	1 << AMDGPU_RAS_BLOCK__SDMA \|	2408	1 << AMDGPU_RAS_BLOCK__SDMA \|
2361	1 << AMDGPU_RAS_BLOCK__GFX);	2409	1 << AMDGPU_RAS_BLOCK__GFX);
2362	}	2410
		2411	/* VCN/JPEG RAS can be supported on both bare metal and
		2412	* SRIOV environment
		2413	*/
		2414	if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(2, 6, 0) \|\|
		2415	adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 0))
		2416	adev->ras_hw_enabled \|= (1 << AMDGPU_RAS_BLOCK__VCN \|
		2417	1 << AMDGPU_RAS_BLOCK__JPEG);
		2418	else
		2419	adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN \|
		2420	1 << AMDGPU_RAS_BLOCK__JPEG);
2363	} else {	2421	} else {
2364	dev_info(adev->dev, "SRAM ECC is not presented.\n");	2422	dev_info(adev->dev, "SRAM ECC is not presented.\n");
2365	}	2423	}
@@ -2395,7 +2453,7 @@ static void amdgpu_ras_counte_dw(struct work_struct *work) · 29 unmodified lines
2395		2453
2396	/* Cache new values.	2454	/* Cache new values.
2397	*/	2455	*/
2398	if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) {	2456	if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL) == 0) {
2399	atomic_set(&con->ras_ce_count, ce_count);	2457	atomic_set(&con->ras_ce_count, ce_count);
2400	atomic_set(&con->ras_ue_count, ue_count);	2458	atomic_set(&con->ras_ue_count, ue_count);
2401	}	2459	}
@@ -2405,11 +2463,42 @@ Out: · 3 unmodified lines
2405	pm_runtime_put_autosuspend(dev->dev);	2463	pm_runtime_put_autosuspend(dev->dev);
2406	}	2464	}
2407		2465
		2466	static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev)
		2467	{
		2468	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
		2469	bool df_poison, umc_poison;
		2470
		2471	/* poison setting is useless on SRIOV guest */
		2472	if (amdgpu_sriov_vf(adev) \|\| !con)
		2473	return;
		2474
		2475	/* Init poison supported flag, the default value is false */
		2476	if (adev->gmc.xgmi.connected_to_cpu) {
		2477	/* enabled by default when GPU is connected to CPU */
		2478	con->poison_supported = true;
		2479	} else if (adev->df.funcs &&
		2480	adev->df.funcs->query_ras_poison_mode &&
		2481	adev->umc.ras &&
		2482	adev->umc.ras->query_ras_poison_mode) {
		2483	df_poison =
		2484	adev->df.funcs->query_ras_poison_mode(adev);
		2485	umc_poison =
		2486	adev->umc.ras->query_ras_poison_mode(adev);
		2487
		2488	/* Only poison is set in both DF and UMC, we can support it */
		2489	if (df_poison && umc_poison)
		2490	con->poison_supported = true;
		2491	else if (df_poison != umc_poison)
		2492	dev_warn(adev->dev,
		2493	"Poison setting is inconsistent in DF/UMC(%d:%d)!\n",
		2494	df_poison, umc_poison);
		2495	}
		2496	}
		2497
2408	int amdgpu_ras_init(struct amdgpu_device *adev)	2498	int amdgpu_ras_init(struct amdgpu_device *adev)
2409	{	2499	{
2410	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);	2500	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2411	int r;	2501	int r;
2412	bool df_poison, umc_poison;
2413		2502
2414	if (con)	2503	if (con)
2415	return 0;	2504	return 0;
@@ -2484,26 +2573,7 @@ int amdgpu_ras_init(struct amdgpu_device *adev) · 68 unmodified lines
2484	goto release_con;	2573	goto release_con;
2485	}	2574	}
2486		2575
2487	/* Init poison supported flag, the default value is false */	2576	amdgpu_ras_query_poison_mode(adev);
2488	if (adev->gmc.xgmi.connected_to_cpu) {
2489	/* enabled by default when GPU is connected to CPU */
2490	con->poison_supported = true;
2491	}
2492	else if (adev->df.funcs &&
2493	adev->df.funcs->query_ras_poison_mode &&
2494	adev->umc.ras &&
2495	adev->umc.ras->query_ras_poison_mode) {
2496	df_poison =
2497	adev->df.funcs->query_ras_poison_mode(adev);
2498	umc_poison =
2499	adev->umc.ras->query_ras_poison_mode(adev);
2500	/* Only poison is set in both DF and UMC, we can support it */
2501	if (df_poison && umc_poison)
2502	con->poison_supported = true;
2503	else if (df_poison != umc_poison)
2504	dev_warn(adev->dev, "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",
2505	df_poison, umc_poison);
2506	}
2507		2577
2508	if (amdgpu_ras_fs_init(adev)) {	2578	if (amdgpu_ras_fs_init(adev)) {
2509	r = -EINVAL;	2579	r = -EINVAL;
@@ -2564,6 +2634,7 @@ int amdgpu_ras_block_late_init(struct amdgpu_device *adev, · 54 unmodified lines
2564	{	2634	{
2565	struct amdgpu_ras_block_object *ras_obj = NULL;	2635	struct amdgpu_ras_block_object *ras_obj = NULL;
2566	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);	2636	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
		2637	struct ras_query_if *query_info;
2567	unsigned long ue_count, ce_count;	2638	unsigned long ue_count, ce_count;
2568	int r;	2639	int r;
2569		2640
@@ -2605,11 +2676,17 @@ int amdgpu_ras_block_late_init(struct amdgpu_device *adev, · 35 unmodified lines
2605		2676
2606	/* Those are the cached values at init.	2677	/* Those are the cached values at init.
2607	*/	2678	*/
2608	if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) {	2679	query_info = kzalloc(sizeof(struct ras_query_if), GFP_KERNEL);
		2680	if (!query_info)
		2681	return -ENOMEM;
		2682	memcpy(&query_info->head, ras_block, sizeof(struct ras_common_if));
		2683
		2684	if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, query_info) == 0) {
2609	atomic_set(&con->ras_ce_count, ce_count);	2685	atomic_set(&con->ras_ce_count, ce_count);
2610	atomic_set(&con->ras_ue_count, ue_count);	2686	atomic_set(&con->ras_ue_count, ue_count);
2611	}	2687	}
2612		2688
		2689	kfree(query_info);
2613	return 0;	2690	return 0;
2614		2691
2615	interrupt:	2692	interrupt:

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h+2−1

@@ -540,7 +540,8 @@ void amdgpu_ras_suspend(struct amdgpu_device *adev); · 539 unmodified lines
540		540
541	int amdgpu_ras_query_error_count(struct amdgpu_device *adev,	541	int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
542	unsigned long *ce_count,	542	unsigned long *ce_count,
543	unsigned long *ue_count);	543	unsigned long *ue_count,
		544	struct ras_query_if *query_info);
544		545
545	/* error handling functions */	546	/* error handling functions */
546	int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,	547	int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c+6−3

 	/* allocate save restore block */
 	r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
-				      AMDGPU_GEM_DOMAIN_VRAM,
+				      AMDGPU_GEM_DOMAIN_VRAM |
+				      AMDGPU_GEM_DOMAIN_GTT,
 				      &adev->gfx.rlc.save_restore_obj,
 				      &adev->gfx.rlc.save_restore_gpu_addr,
 				      (void **)&adev->gfx.rlc.sr_ptr);
 	/* allocate clear state block */
 	adev->gfx.rlc.clear_state_size = dws = adev->gfx.rlc.funcs->get_csb_size(adev);
 	r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE,
-				      AMDGPU_GEM_DOMAIN_VRAM,
+				      AMDGPU_GEM_DOMAIN_VRAM |
+				      AMDGPU_GEM_DOMAIN_GTT,
 				      &adev->gfx.rlc.clear_state_obj,
 				      &adev->gfx.rlc.clear_state_gpu_addr,
 				      (void **)&adev->gfx.rlc.cs_ptr);
 	int r;
 	r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
-				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
+				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM |
+				      AMDGPU_GEM_DOMAIN_GTT,
 				      &adev->gfx.rlc.cp_table_obj,
 				      &adev->gfx.rlc.cp_table_gpu_addr,
 				      (void **)&adev->gfx.rlc.cp_table_ptr);

drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c+4−4

@@ -77,11 +77,11 @@ void psp_securedisplay_parse_resp_status(struct psp_context *psp, · 76 unmodified lines
77	}	77	}
78	}	78	}
79		79
80	void psp_prep_securedisplay_cmd_buf(struct psp_context psp, struct securedisplay_cmd *cmd,	80	void psp_prep_securedisplay_cmd_buf(struct psp_context psp, struct ta_securedisplay_cmd *cmd,
81	enum ta_securedisplay_command command_id)	81	enum ta_securedisplay_command command_id)
82	{	82	{
83	cmd = (struct securedisplay_cmd )psp->securedisplay_context.context.mem_context.shared_buf;	83	cmd = (struct ta_securedisplay_cmd )psp->securedisplay_context.context.mem_context.shared_buf;
84	memset(*cmd, 0, sizeof(struct securedisplay_cmd));	84	memset(*cmd, 0, sizeof(struct ta_securedisplay_cmd));
85	(*cmd)->status = TA_SECUREDISPLAY_STATUS__GENERIC_FAILURE;	85	(*cmd)->status = TA_SECUREDISPLAY_STATUS__GENERIC_FAILURE;
86	(*cmd)->cmd_id = command_id;	86	(*cmd)->cmd_id = command_id;
87	}	87	}
@@ -93,7 +93,7 @@ static ssize_t amdgpu_securedisplay_debugfs_write(struct file *f, const char __u · 5 unmodified lines
93	{	93	{
94	struct amdgpu_device adev = (struct amdgpu_device )file_inode(f)->i_private;	94	struct amdgpu_device adev = (struct amdgpu_device )file_inode(f)->i_private;
95	struct psp_context *psp = &adev->psp;	95	struct psp_context *psp = &adev->psp;
96	struct securedisplay_cmd *securedisplay_cmd;	96	struct ta_securedisplay_cmd *securedisplay_cmd;
97	struct drm_device *dev = adev_to_drm(adev);	97	struct drm_device *dev = adev_to_drm(adev);
98	uint32_t phy_id;	98	uint32_t phy_id;
99	uint32_t op;	99	uint32_t op;

drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.h+1−1

@@ -30,7 +30,7 @@ · 29 unmodified lines
30	void amdgpu_securedisplay_debugfs_init(struct amdgpu_device *adev);	30	void amdgpu_securedisplay_debugfs_init(struct amdgpu_device *adev);
31	void psp_securedisplay_parse_resp_status(struct psp_context *psp,	31	void psp_securedisplay_parse_resp_status(struct psp_context *psp,
32	enum ta_securedisplay_status status);	32	enum ta_securedisplay_status status);
33	void psp_prep_securedisplay_cmd_buf(struct psp_context psp, struct securedisplay_cmd *cmd,	33	void psp_prep_securedisplay_cmd_buf(struct psp_context psp, struct ta_securedisplay_cmd *cmd,
34	enum ta_securedisplay_command command_id);	34	enum ta_securedisplay_command command_id);
35		35
36	#endif	36	#endif

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c+8−15

 		/* reserve vram for mem train according to TMR location */
 		amdgpu_ttm_training_data_block_init(adev);
 		ret = amdgpu_bo_create_kernel_at(adev,
-					 ctx->c2p_train_data_offset,
+						 ctx->c2p_train_data_offset,
-					 ctx->train_data_size,
+						 ctx->train_data_size,
-					 &ctx->c2p_bo,
+						 &ctx->c2p_bo,
-					 NULL);
+						 NULL);
 		if (ret) {
 			DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
 			amdgpu_ttm_training_reserve_vram_fini(adev);
 	}
 	ret = amdgpu_bo_create_kernel_at(adev,
-				adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
+					 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
-				adev->mman.discovery_tmr_size,
+					 adev->mman.discovery_tmr_size,
-				&adev->mman.discovery_memory,
+					 &adev->mman.discovery_memory,
-				NULL);
+					 NULL);
 	if (ret) {
 		DRM_ERROR("alloc tmr failed(%d)!\n", ret);
 		amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
 {
 	uint64_t gtt_size;
 	int r;
-	u64 vis_vram_limit;
 	mutex_init(&adev->mman.gtt_window_lock);
 		return r;
 	}
-	/* Reduce size of CPU-visible VRAM if requested */
-	vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
-	if (amdgpu_vis_vram_limit > 0 &&
-	    vis_vram_limit <= adev->gmc.visible_vram_size)
-		adev->gmc.visible_vram_size = vis_vram_limit;
 	/* Change the size here instead of the init above so only lpfn is affected */
 	amdgpu_ttm_set_buffer_funcs_status(adev, false);
 #ifdef CONFIG_64BIT

drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c+26−18

@@ -169,25 +169,33 @@ int amdgpu_umc_poison_handler(struct amdgpu_device *adev, bool reset) · 168 unmodified lines
169	{	169	{
170	int ret = AMDGPU_RAS_SUCCESS;	170	int ret = AMDGPU_RAS_SUCCESS;
171		171
172	if (!adev->gmc.xgmi.connected_to_cpu) {	172	if (!amdgpu_sriov_vf(adev)) {
173	struct ras_err_data err_data = {0, 0, 0, NULL};	173	if (!adev->gmc.xgmi.connected_to_cpu) {
174	struct ras_common_if head = {	174	struct ras_err_data err_data = {0, 0, 0, NULL};
175	.block = AMDGPU_RAS_BLOCK__UMC,	175	struct ras_common_if head = {
176	};	176	.block = AMDGPU_RAS_BLOCK__UMC,
177	struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head);	177	};
178		178	struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head);
179	ret = amdgpu_umc_do_page_retirement(adev, &err_data, NULL, reset);	179
180		180	ret = amdgpu_umc_do_page_retirement(adev, &err_data, NULL, reset);
181	if (ret == AMDGPU_RAS_SUCCESS && obj) {	181
182	obj->err_data.ue_count += err_data.ue_count;	182	if (ret == AMDGPU_RAS_SUCCESS && obj) {
183	obj->err_data.ce_count += err_data.ce_count;	183	obj->err_data.ue_count += err_data.ue_count;
		184	obj->err_data.ce_count += err_data.ce_count;
		185	}
		186	} else if (reset) {
		187	/* MCA poison handler is only responsible for GPU reset,
		188	* let MCA notifier do page retirement.
		189	*/
		190	kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
		191	amdgpu_ras_reset_gpu(adev);
184	}	192	}
185	} else if (reset) {	193	} else {
186	/* MCA poison handler is only responsible for GPU reset,	194	if (adev->virt.ops && adev->virt.ops->ras_poison_handler)
187	* let MCA notifier do page retirement.	195	adev->virt.ops->ras_poison_handler(adev);
188	*/	196	else
189	kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);	197	dev_warn(adev->dev,
190	amdgpu_ras_reset_gpu(adev);	198	"No ras_poison_handler interface in SRIOV!\n");
191	}	199	}
192		200
193	return ret;	201	return ret;

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c+5−2

 		if (adev->uvd.harvest_config & (1 << j))
 			continue;
 		r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
-					    AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.inst[j].vcpu_bo,
+					    AMDGPU_GEM_DOMAIN_VRAM |
-					    &adev->uvd.inst[j].gpu_addr, &adev->uvd.inst[j].cpu_addr);
+					    AMDGPU_GEM_DOMAIN_GTT,
+					    &adev->uvd.inst[j].vcpu_bo,
+					    &adev->uvd.inst[j].gpu_addr,
+					    &adev->uvd.inst[j].cpu_addr);
 		if (r) {
 			dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
 			return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c+3−1

 				(binary_id << 8));
 	r = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
-				    AMDGPU_GEM_DOMAIN_VRAM, &adev->vce.vcpu_bo,
+				    AMDGPU_GEM_DOMAIN_VRAM |
+				    AMDGPU_GEM_DOMAIN_GTT,
+				    &adev->vce.vcpu_bo,
 				    &adev->vce.gpu_addr, &adev->vce.cpu_addr);
 	if (r) {
 		dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c+20−6

 			continue;
 		r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
-						AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo,
+					    AMDGPU_GEM_DOMAIN_VRAM |
-						&adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr);
+					    AMDGPU_GEM_DOMAIN_GTT,
+					    &adev->vcn.inst[i].vcpu_bo,
+					    &adev->vcn.inst[i].gpu_addr,
+					    &adev->vcn.inst[i].cpu_addr);
 		if (r) {
 			dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
 			return r;
 		if (adev->vcn.indirect_sram) {
 			r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
-					AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].dpg_sram_bo,
+					AMDGPU_GEM_DOMAIN_VRAM |
-					&adev->vcn.inst[i].dpg_sram_gpu_addr, &adev->vcn.inst[i].dpg_sram_cpu_addr);
+					AMDGPU_GEM_DOMAIN_GTT,
+					&adev->vcn.inst[i].dpg_sram_bo,
+					&adev->vcn.inst[i].dpg_sram_gpu_addr,
+					&adev->vcn.inst[i].dpg_sram_cpu_addr);
 			if (r) {
 				dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r);
 				return r;
 	if (!ras_if)
 		return 0;
-	ih_data.head = *ras_if;
+	if (!amdgpu_sriov_vf(adev)) {
-	amdgpu_ras_interrupt_dispatch(adev, &ih_data);
+		ih_data.head = *ras_if;
+		amdgpu_ras_interrupt_dispatch(adev, &ih_data);
+	} else {
+		if (adev->virt.ops && adev->virt.ops->ras_poison_handler)
+			adev->virt.ops->ras_poison_handler(adev);
+		else
+			dev_warn(adev->dev,
+				"No ras_poison_handler interface in SRIOV for VCN!\n");
+	}
 	return 0;
 }

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c+2−1

@@ -232,7 +232,8 @@ int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev) · 231 unmodified lines
232	return 0;	232	return 0;
233		233
234	r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,	234	r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
235	AMDGPU_GEM_DOMAIN_VRAM,	235	AMDGPU_GEM_DOMAIN_VRAM \|
		236	AMDGPU_GEM_DOMAIN_GTT,
236	&adev->virt.mm_table.bo,	237	&adev->virt.mm_table.bo,
237	&adev->virt.mm_table.gpu_addr,	238	&adev->virt.mm_table.gpu_addr,
238	(void *)&adev->virt.mm_table.cpu_addr);	239	(void *)&adev->virt.mm_table.cpu_addr);

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h+1−0

@@ -88,6 +88,7 @@ struct amdgpu_virt_ops { · 87 unmodified lines
88	int (wait_reset)(struct amdgpu_device adev);	88	int (wait_reset)(struct amdgpu_device adev);
89	void (trans_msg)(struct amdgpu_device adev, enum idh_request req,	89	void (trans_msg)(struct amdgpu_device adev, enum idh_request req,
90	u32 data1, u32 data2, u32 data3);	90	u32 data1, u32 data2, u32 data3);
		91	void (ras_poison_handler)(struct amdgpu_device adev);
91	};	92	};
92		93
93	/*	94	/*

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c+3−3

@@ -2837,7 +2837,7 @@ static int dce_v10_0_sw_init(void *handle) · 2836 unmodified lines
2837	if (r)	2837	if (r)
2838	return r;	2838	return r;
2839		2839
2840	INIT_WORK(&adev->hotplug_work,	2840	INIT_DELAYED_WORK(&adev->hotplug_work,
2841	amdgpu_display_hotplug_work_func);	2841	amdgpu_display_hotplug_work_func);
2842		2842
2843	drm_kms_helper_poll_init(adev_to_drm(adev));	2843	drm_kms_helper_poll_init(adev_to_drm(adev));
@@ -2902,7 +2902,7 @@ static int dce_v10_0_hw_fini(void *handle) · 58 unmodified lines
2902		2902
2903	dce_v10_0_pageflip_interrupt_fini(adev);	2903	dce_v10_0_pageflip_interrupt_fini(adev);
2904		2904
2905	flush_work(&adev->hotplug_work);	2905	flush_delayed_work(&adev->hotplug_work);
2906		2906
2907	return 0;	2907	return 0;
2908	}	2908	}
@@ -3302,7 +3302,7 @@ static int dce_v10_0_hpd_irq(struct amdgpu_device *adev, · 393 unmodified lines
3302		3302
3303	if (disp_int & mask) {	3303	if (disp_int & mask) {
3304	dce_v10_0_hpd_int_ack(adev, hpd);	3304	dce_v10_0_hpd_int_ack(adev, hpd);
3305	schedule_work(&adev->hotplug_work);	3305	schedule_delayed_work(&adev->hotplug_work, 0);
3306	DRM_DEBUG("IH: HPD%d\n", hpd + 1);	3306	DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3307	}	3307	}
3308		3308

drivers/gpu/drm/amd/amdgpu/dce_v11_0.c+3−3

@@ -2956,7 +2956,7 @@ static int dce_v11_0_sw_init(void *handle) · 2955 unmodified lines
2956	if (r)	2956	if (r)
2957	return r;	2957	return r;
2958		2958
2959	INIT_WORK(&adev->hotplug_work,	2959	INIT_DELAYED_WORK(&adev->hotplug_work,
2960	amdgpu_display_hotplug_work_func);	2960	amdgpu_display_hotplug_work_func);
2961		2961
2962	drm_kms_helper_poll_init(adev_to_drm(adev));	2962	drm_kms_helper_poll_init(adev_to_drm(adev));
@@ -3032,7 +3032,7 @@ static int dce_v11_0_hw_fini(void *handle) · 69 unmodified lines
3032		3032
3033	dce_v11_0_pageflip_interrupt_fini(adev);	3033	dce_v11_0_pageflip_interrupt_fini(adev);
3034		3034
3035	flush_work(&adev->hotplug_work);	3035	flush_delayed_work(&adev->hotplug_work);
3036		3036
3037	return 0;	3037	return 0;
3038	}	3038	}
@@ -3426,7 +3426,7 @@ static int dce_v11_0_hpd_irq(struct amdgpu_device *adev, · 387 unmodified lines
3426		3426
3427	if (disp_int & mask) {	3427	if (disp_int & mask) {
3428	dce_v11_0_hpd_int_ack(adev, hpd);	3428	dce_v11_0_hpd_int_ack(adev, hpd);
3429	schedule_work(&adev->hotplug_work);	3429	schedule_delayed_work(&adev->hotplug_work, 0);
3430	DRM_DEBUG("IH: HPD%d\n", hpd + 1);	3430	DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3431	}	3431	}
3432		3432

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c+3−3

@@ -2715,7 +2715,7 @@ static int dce_v6_0_sw_init(void *handle) · 2714 unmodified lines
2715	return r;	2715	return r;
2716		2716
2717	/* Pre-DCE11 */	2717	/* Pre-DCE11 */
2718	INIT_WORK(&adev->hotplug_work,	2718	INIT_DELAYED_WORK(&adev->hotplug_work,
2719	amdgpu_display_hotplug_work_func);	2719	amdgpu_display_hotplug_work_func);
2720		2720
2721	drm_kms_helper_poll_init(adev_to_drm(adev));	2721	drm_kms_helper_poll_init(adev_to_drm(adev));
@@ -2776,7 +2776,7 @@ static int dce_v6_0_hw_fini(void *handle) · 54 unmodified lines
2776		2776
2777	dce_v6_0_pageflip_interrupt_fini(adev);	2777	dce_v6_0_pageflip_interrupt_fini(adev);
2778		2778
2779	flush_work(&adev->hotplug_work);	2779	flush_delayed_work(&adev->hotplug_work);
2780		2780
2781	return 0;	2781	return 0;
2782	}	2782	}
@@ -3103,7 +3103,7 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev, · 320 unmodified lines
3103	tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);	3103	tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
3104	tmp \|= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;	3104	tmp \|= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3105	WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);	3105	WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
3106	schedule_work(&adev->hotplug_work);	3106	schedule_delayed_work(&adev->hotplug_work, 0);
3107	DRM_DEBUG("IH: HPD%d\n", hpd + 1);	3107	DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3108	}	3108	}
3109		3109

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c+3−3

@@ -2739,7 +2739,7 @@ static int dce_v8_0_sw_init(void *handle) · 2738 unmodified lines
2739	return r;	2739	return r;
2740		2740
2741	/* Pre-DCE11 */	2741	/* Pre-DCE11 */
2742	INIT_WORK(&adev->hotplug_work,	2742	INIT_DELAYED_WORK(&adev->hotplug_work,
2743	amdgpu_display_hotplug_work_func);	2743	amdgpu_display_hotplug_work_func);
2744		2744
2745	drm_kms_helper_poll_init(adev_to_drm(adev));	2745	drm_kms_helper_poll_init(adev_to_drm(adev));
@@ -2802,7 +2802,7 @@ static int dce_v8_0_hw_fini(void *handle) · 56 unmodified lines
2802		2802
2803	dce_v8_0_pageflip_interrupt_fini(adev);	2803	dce_v8_0_pageflip_interrupt_fini(adev);
2804		2804
2805	flush_work(&adev->hotplug_work);	2805	flush_delayed_work(&adev->hotplug_work);
2806		2806
2807	return 0;	2807	return 0;
2808	}	2808	}
@@ -3195,7 +3195,7 @@ static int dce_v8_0_hpd_irq(struct amdgpu_device *adev, · 386 unmodified lines
3195	tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);	3195	tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
3196	tmp \|= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;	3196	tmp \|= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3197	WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);	3197	WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
3198	schedule_work(&adev->hotplug_work);	3198	schedule_delayed_work(&adev->hotplug_work, 0);
3199	DRM_DEBUG("IH: HPD%d\n", hpd + 1);	3199	DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3200	}	3200	}
3201		3201

drivers/gpu/drm/amd/amdgpu/df_v4_3.c+61−0

@@ -0,0 +1,61 @@
	1	/*
	2	* Copyright 2022 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include "amdgpu.h"
	24	#include "df_v4_3.h"
	25
	26	#include "df/df_4_3_offset.h"
	27	#include "df/df_4_3_sh_mask.h"
	28
	29	static bool df_v4_3_query_ras_poison_mode(struct amdgpu_device *adev)
	30	{
	31	uint32_t hw_assert_msklo, hw_assert_mskhi;
	32	uint32_t v0, v1, v28, v31;
	33
	34	hw_assert_msklo = RREG32_SOC15(DF, 0,
	35	regDF_CS_UMC_AON0_HardwareAssertMaskLow);
	36	hw_assert_mskhi = RREG32_SOC15(DF, 0,
	37	regDF_NCS_PG0_HardwareAssertMaskHigh);
	38
	39	v0 = REG_GET_FIELD(hw_assert_msklo,
	40	DF_CS_UMC_AON0_HardwareAssertMaskLow, HWAssertMsk0);
	41	v1 = REG_GET_FIELD(hw_assert_msklo,
	42	DF_CS_UMC_AON0_HardwareAssertMaskLow, HWAssertMsk1);
	43	v28 = REG_GET_FIELD(hw_assert_mskhi,
	44	DF_NCS_PG0_HardwareAssertMaskHigh, HWAssertMsk28);
	45	v31 = REG_GET_FIELD(hw_assert_mskhi,
	46	DF_NCS_PG0_HardwareAssertMaskHigh, HWAssertMsk31);
	47
	48	if (v0 && v1 && v28 && v31)
	49	return true;
	50	else if (!v0 && !v1 && !v28 && !v31)
	51	return false;
	52	else {
	53	dev_warn(adev->dev, "DF poison setting is inconsistent(%d:%d:%d:%d)!\n",
	54	v0, v1, v28, v31);
	55	return false;
	56	}
	57	}
	58
	59	const struct amdgpu_df_funcs df_v4_3_funcs = {
	60	.query_ras_poison_mode = df_v4_3_query_ras_poison_mode,
	61	};

drivers/gpu/drm/amd/amdgpu/df_v4_3.h+31−0

@@ -0,0 +1,31 @@
	1	/*
	2	* Copyright 2022 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#ifndef __DF_V4_3_H__
	25	#define __DF_V4_3_H__
	26
	27	#include "soc15_common.h"
	28
	29	extern const struct amdgpu_df_funcs df_v4_3_funcs;
	30
	31	#endif

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c+23−10

 	total_size = gfx_v11_0_calc_toc_total_size(adev);
 	r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024,
-			AMDGPU_GEM_DOMAIN_VRAM,
+				      AMDGPU_GEM_DOMAIN_VRAM |
-			&adev->gfx.rlc.rlc_autoload_bo,
+				      AMDGPU_GEM_DOMAIN_GTT,
-			&adev->gfx.rlc.rlc_autoload_gpu_addr,
+				      &adev->gfx.rlc.rlc_autoload_bo,
-			(void **)&adev->gfx.rlc.rlc_autoload_ptr);
+				      &adev->gfx.rlc.rlc_autoload_gpu_addr,
+				      (void **)&adev->gfx.rlc.rlc_autoload_ptr);
 	if (r) {
 		dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
 	/* 64kb align */
 	r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
-				      64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
+				      64 * 1024,
+				      AMDGPU_GEM_DOMAIN_VRAM |
+				      AMDGPU_GEM_DOMAIN_GTT,
 				      &adev->gfx.pfp.pfp_fw_obj,
 				      &adev->gfx.pfp.pfp_fw_gpu_addr,
 				      (void **)&adev->gfx.pfp.pfp_fw_ptr);
 	}
 	r = amdgpu_bo_create_reserved(adev, fw_data_size,
-				      64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
+				      64 * 1024,
+				      AMDGPU_GEM_DOMAIN_VRAM |
+				      AMDGPU_GEM_DOMAIN_GTT,
 				      &adev->gfx.pfp.pfp_fw_data_obj,
 				      &adev->gfx.pfp.pfp_fw_data_gpu_addr,
 				      (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
 	/* 64kb align*/
 	r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
-				      64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
+				      64 * 1024,
+				      AMDGPU_GEM_DOMAIN_VRAM |
+				      AMDGPU_GEM_DOMAIN_GTT,
 				      &adev->gfx.me.me_fw_obj,
 				      &adev->gfx.me.me_fw_gpu_addr,
 				      (void **)&adev->gfx.me.me_fw_ptr);
 	}
 	r = amdgpu_bo_create_reserved(adev, fw_data_size,
-				      64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
+				      64 * 1024,
+				      AMDGPU_GEM_DOMAIN_VRAM |
+				      AMDGPU_GEM_DOMAIN_GTT,
 				      &adev->gfx.me.me_fw_data_obj,
 				      &adev->gfx.me.me_fw_data_gpu_addr,
 				      (void **)&adev->gfx.me.me_fw_data_ptr);
 	fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes);
 	r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
-				      64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
+				      64 * 1024,
+				      AMDGPU_GEM_DOMAIN_VRAM |
+				      AMDGPU_GEM_DOMAIN_GTT,
 				      &adev->gfx.mec.mec_fw_obj,
 				      &adev->gfx.mec.mec_fw_gpu_addr,
 				      (void **)&fw_ucode_ptr);
 	}
 	r = amdgpu_bo_create_reserved(adev, fw_data_size,
-				      64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
+				      64 * 1024,
+				      AMDGPU_GEM_DOMAIN_VRAM |
+				      AMDGPU_GEM_DOMAIN_GTT,
 				      &adev->gfx.mec.mec_fw_data_obj,
 				      &adev->gfx.mec.mec_fw_data_gpu_addr,
 				      (void **)&fw_data_ptr);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c+2−1

@@ -2375,7 +2375,8 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) · 2374 unmodified lines
2375	dws = adev->gfx.rlc.clear_state_size + (256 / 4);	2375	dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2376		2376
2377	r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,	2377	r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2378	AMDGPU_GEM_DOMAIN_VRAM,	2378	AMDGPU_GEM_DOMAIN_VRAM \|
		2379	AMDGPU_GEM_DOMAIN_GTT,
2379	&adev->gfx.rlc.clear_state_obj,	2380	&adev->gfx.rlc.clear_state_obj,
2380	&adev->gfx.rlc.clear_state_gpu_addr,	2381	&adev->gfx.rlc.clear_state_gpu_addr,
2381	(void **)&adev->gfx.rlc.cs_ptr);	2382	(void **)&adev->gfx.rlc.cs_ptr);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c+2−1

@@ -2772,7 +2772,8 @@ static int gfx_v7_0_mec_init(struct amdgpu_device *adev) · 2771 unmodified lines
2772	* GFX7_MEC_HPD_SIZE * 2;	2772	* GFX7_MEC_HPD_SIZE * 2;
2773		2773
2774	r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,	2774	r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
2775	AMDGPU_GEM_DOMAIN_VRAM,	2775	AMDGPU_GEM_DOMAIN_VRAM \|
		2776	AMDGPU_GEM_DOMAIN_GTT,
2776	&adev->gfx.mec.hpd_eop_obj,	2777	&adev->gfx.mec.hpd_eop_obj,
2777	&adev->gfx.mec.hpd_eop_gpu_addr,	2778	&adev->gfx.mec.hpd_eop_gpu_addr,
2778	(void **)&hpd);	2779	(void **)&hpd);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c+2−1

 	mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE;
 	if (mec_hpd_size) {
 		r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
-					      AMDGPU_GEM_DOMAIN_VRAM,
+					      AMDGPU_GEM_DOMAIN_VRAM |
+					      AMDGPU_GEM_DOMAIN_GTT,
 					      &adev->gfx.mec.hpd_eop_obj,
 					      &adev->gfx.mec.hpd_eop_gpu_addr,
 					      (void **)&hpd);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c+2−1

 	mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
 	if (mec_hpd_size) {
 		r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
-					      AMDGPU_GEM_DOMAIN_VRAM,
+					      AMDGPU_GEM_DOMAIN_VRAM |
+					      AMDGPU_GEM_DOMAIN_GTT,
 					      &adev->gfx.mec.hpd_eop_obj,
 					      &adev->gfx.mec.hpd_eop_gpu_addr,
 					      (void **)&hpd);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c+1−1

@@ -120,7 +120,7 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) · 119 unmodified lines
120	max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);	120	max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
121		121
122	/* Set default page address. */	122	/* Set default page address. */
123	value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);	123	value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
124	WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,	124	WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
125	(u32)(value >> 12));	125	(u32)(value >> 12));
126	WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,	126	WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c+1−1

@@ -165,7 +165,7 @@ static void gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev) · 164 unmodified lines
165	max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);	165	max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
166		166
167	/* Set default page address. */	167	/* Set default page address. */
168	value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);	168	value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
169	WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,	169	WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
170	(u32)(value >> 12));	170	(u32)(value >> 12));
171	WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,	171	WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c+1−1

@@ -167,7 +167,7 @@ static void gfxhub_v2_1_init_system_aperture_regs(struct amdgpu_device *adev) · 166 unmodified lines
167	max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);	167	max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
168		168
169	/* Set default page address. */	169	/* Set default page address. */
170	value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);	170	value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
171	WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,	171	WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
172	(u32)(value >> 12));	172	(u32)(value >> 12));
173	WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,	173	WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c+1−1

@@ -163,7 +163,7 @@ static void gfxhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev) · 162 unmodified lines
163	adev->gmc.vram_end >> 18);	163	adev->gmc.vram_end >> 18);
164		164
165	/* Set default page address. */	165	/* Set default page address. */
166	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start	166	value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start
167	+ adev->vm_manager.vram_base_offset;	167	+ adev->vm_manager.vram_base_offset;
168	WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,	168	WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
169	(u32)(value >> 12));	169	(u32)(value >> 12));

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c+1−1

@@ -169,7 +169,7 @@ static void gfxhub_v3_0_3_init_system_aperture_regs(struct amdgpu_device *adev) · 168 unmodified lines
169	adev->gmc.vram_end >> 18);	169	adev->gmc.vram_end >> 18);
170		170
171	/* Set default page address. */	171	/* Set default page address. */
172	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start	172	value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start
173	+ adev->vm_manager.vram_base_offset;	173	+ adev->vm_manager.vram_base_offset;
174	WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,	174	WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
175	(u32)(value >> 12));	175	(u32)(value >> 12));

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c+27−12

@@ -78,13 +78,25 @@ gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, · 77 unmodified lines
78	/* MM HUB */	78	/* MM HUB */
79	amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false);	79	amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false);
80	/* GFX HUB */	80	/* GFX HUB */
81	amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);	81	/* This works because this interrupt is only
		82	* enabled at init/resume and disabled in
		83	* fini/suspend, so the overall state doesn't
		84	* change over the course of suspend/resume.
		85	*/
		86	if (!adev->in_s0ix)
		87	amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);
82	break;	88	break;
83	case AMDGPU_IRQ_STATE_ENABLE:	89	case AMDGPU_IRQ_STATE_ENABLE:
84	/* MM HUB */	90	/* MM HUB */
85	amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true);	91	amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true);
86	/* GFX HUB */	92	/* GFX HUB */
87	amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);	93	/* This works because this interrupt is only
		94	* enabled at init/resume and disabled in
		95	* fini/suspend, so the overall state doesn't
		96	* change over the course of suspend/resume.
		97	*/
		98	if (!adev->in_s0ix)
		99	amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);
88	break;	100	break;
89	default:	101	default:
90	break;	102	break;
@@ -835,10 +847,7 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev) · 744 unmodified lines
835	}	847	}
836	#endif	848	#endif
837		849
838	/* In case the PCI BAR is larger than the actual amount of vram */
839	adev->gmc.visible_vram_size = adev->gmc.aper_size;	850	adev->gmc.visible_vram_size = adev->gmc.aper_size;
840	if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
841	adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
842		851
843	/* set the gart size */	852	/* set the gart size */
844	if (amdgpu_gart_size == -1) {	853	if (amdgpu_gart_size == -1) {
@@ -1061,9 +1070,12 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) · 216 unmodified lines
1061	}	1070	}
1062		1071
1063	amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);	1072	amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
1064	r = adev->gfxhub.funcs->gart_enable(adev);	1073
1065	if (r)	1074	if (!adev->in_s0ix) {
1066	return r;	1075	r = adev->gfxhub.funcs->gart_enable(adev);
		1076	if (r)
		1077	return r;
		1078	}
1067		1079
1068	r = adev->mmhub.funcs->gart_enable(adev);	1080	r = adev->mmhub.funcs->gart_enable(adev);
1069	if (r)	1081	if (r)
@@ -1077,10 +1089,12 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) · 7 unmodified lines
1077	value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?	1089	value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
1078	false : true;	1090	false : true;
1079		1091
1080	adev->gfxhub.funcs->set_fault_enable_default(adev, value);	1092	if (!adev->in_s0ix)
		1093	adev->gfxhub.funcs->set_fault_enable_default(adev, value);
1081	adev->mmhub.funcs->set_fault_enable_default(adev, value);	1094	adev->mmhub.funcs->set_fault_enable_default(adev, value);
1082	gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);	1095	gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
1083	gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);	1096	if (!adev->in_s0ix)
		1097	gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
1084		1098
1085	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",	1099	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1086	(unsigned)(adev->gmc.gart_size >> 20),	1100	(unsigned)(adev->gmc.gart_size >> 20),
@@ -1101,7 +1115,7 @@ static int gmc_v10_0_hw_init(void *handle) · 14 unmodified lines
1101	* harvestable groups in gc_utcl2 need to be programmed before any GFX block	1115	* harvestable groups in gc_utcl2 need to be programmed before any GFX block
1102	* register setup within GMC, or else system hang when harvesting SA.	1116	* register setup within GMC, or else system hang when harvesting SA.
1103	*/	1117	*/
1104	if (adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest)	1118	if (!adev->in_s0ix && adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest)
1105	adev->gfxhub.funcs->utcl2_harvest(adev);	1119	adev->gfxhub.funcs->utcl2_harvest(adev);
1106		1120
1107	r = gmc_v10_0_gart_enable(adev);	1121	r = gmc_v10_0_gart_enable(adev);
@@ -1129,7 +1143,8 @@ static int gmc_v10_0_hw_init(void *handle) · 21 unmodified lines
1129	*/	1143	*/
1130	static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)	1144	static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
1131	{	1145	{
1132	adev->gfxhub.funcs->gart_disable(adev);	1146	if (!adev->in_s0ix)
		1147	adev->gfxhub.funcs->gart_disable(adev);
1133	adev->mmhub.funcs->gart_disable(adev);	1148	adev->mmhub.funcs->gart_disable(adev);
1134	}	1149	}
1135		1150

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c+14−2

 		/* MM HUB */
 		amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false);
 		/* GFX HUB */
-		amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);
+		/* This works because this interrupt is only
+		 * enabled at init/resume and disabled in
+		 * fini/suspend, so the overall state doesn't
+		 * change over the course of suspend/resume.
+		 */
+		if (!adev->in_s0ix)
+			amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);
 		break;
 	case AMDGPU_IRQ_STATE_ENABLE:
 		/* MM HUB */
 		amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true);
 		/* GFX HUB */
-		amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);
+		/* This works because this interrupt is only
+		 * enabled at init/resume and disabled in
+		 * fini/suspend, so the overall state doesn't
+		 * change over the course of suspend/resume.
+		 */
+		if (!adev->in_s0ix)
+			amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);
 		break;
 	default:
 		break;

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c+1−1

@@ -258,7 +258,7 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev) · 257 unmodified lines
258	WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,	258	WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
259	adev->gmc.vram_end >> 12);	259	adev->gmc.vram_end >> 12);
260	WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,	260	WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
261	adev->vram_scratch.gpu_addr >> 12);	261	adev->mem_scratch.gpu_addr >> 12);
262	WREG32(mmMC_VM_AGP_BASE, 0);	262	WREG32(mmMC_VM_AGP_BASE, 0);
263	WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);	263	WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
264	WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);	264	WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c+1−4

 	WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 	       adev->gmc.vram_end >> 12);
 	WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
-	       adev->vram_scratch.gpu_addr >> 12);
+	       adev->mem_scratch.gpu_addr >> 12);
 	WREG32(mmMC_VM_AGP_BASE, 0);
 	WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 	WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 	}
 #endif
-	/* In case the PCI BAR is larger than the actual amount of vram */
 	adev->gmc.visible_vram_size = adev->gmc.aper_size;
-	if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
-		adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 	/* set the gart size */
 	if (amdgpu_gart_size == -1) {

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c+1−4

 	WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 	       adev->gmc.vram_end >> 12);
 	WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
-	       adev->vram_scratch.gpu_addr >> 12);
+	       adev->mem_scratch.gpu_addr >> 12);
 	if (amdgpu_sriov_vf(adev)) {
 		tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;
 	}
 #endif
-	/* In case the PCI BAR is larger than the actual amount of vram */
 	adev->gmc.visible_vram_size = adev->gmc.aper_size;
-	if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
-		adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 	/* set the gart size */
 	if (amdgpu_gart_size == -1) {

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c+30−9

@@ -484,6 +484,14 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, · 483 unmodified lines
484	for (i = 0; i < 16; i++) {	484	for (i = 0; i < 16; i++) {
485	reg = hub->vm_context0_cntl + i;	485	reg = hub->vm_context0_cntl + i;
486		486
		487	/* This works because this interrupt is only
		488	* enabled at init/resume and disabled in
		489	* fini/suspend, so the overall state doesn't
		490	* change over the course of suspend/resume.
		491	*/
		492	if (adev->in_s0ix && (j == AMDGPU_GFXHUB_0))
		493	continue;
		494
487	if (j == AMDGPU_GFXHUB_0)	495	if (j == AMDGPU_GFXHUB_0)
488	tmp = RREG32_SOC15_IP(GC, reg);	496	tmp = RREG32_SOC15_IP(GC, reg);
489	else	497	else
@@ -504,6 +512,14 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, · 14 unmodified lines
504	for (i = 0; i < 16; i++) {	512	for (i = 0; i < 16; i++) {
505	reg = hub->vm_context0_cntl + i;	513	reg = hub->vm_context0_cntl + i;
506		514
		515	/* This works because this interrupt is only
		516	* enabled at init/resume and disabled in
		517	* fini/suspend, so the overall state doesn't
		518	* change over the course of suspend/resume.
		519	*/
		520	if (adev->in_s0ix && (j == AMDGPU_GFXHUB_0))
		521	continue;
		522
507	if (j == AMDGPU_GFXHUB_0)	523	if (j == AMDGPU_GFXHUB_0)
508	tmp = RREG32_SOC15_IP(GC, reg);	524	tmp = RREG32_SOC15_IP(GC, reg);
509	else	525	else
@@ -1536,10 +1552,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) · 1026 unmodified lines
1536	}	1552	}
1537		1553
1538	#endif	1554	#endif
1539	/* In case the PCI BAR is larger than the actual amount of vram */
1540	adev->gmc.visible_vram_size = adev->gmc.aper_size;	1555	adev->gmc.visible_vram_size = adev->gmc.aper_size;
1541	if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
1542	adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
1543		1556
1544	/* set the gart size */	1557	/* set the gart size */
1545	if (amdgpu_gart_size == -1) {	1558	if (amdgpu_gart_size == -1) {
@@ -1862,9 +1875,12 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) · 316 unmodified lines
1862	}	1875	}
1863		1876
1864	amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);	1877	amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
1865	r = adev->gfxhub.funcs->gart_enable(adev);	1878
1866	if (r)	1879	if (!adev->in_s0ix) {
1867	return r;	1880	r = adev->gfxhub.funcs->gart_enable(adev);
		1881	if (r)
		1882	return r;
		1883	}
1868		1884
1869	r = adev->mmhub.funcs->gart_enable(adev);	1885	r = adev->mmhub.funcs->gart_enable(adev);
1870	if (r)	1886	if (r)
@@ -1911,11 +1927,15 @@ static int gmc_v9_0_hw_init(void *handle) · 40 unmodified lines
1911	value = true;	1927	value = true;
1912		1928
1913	if (!amdgpu_sriov_vf(adev)) {	1929	if (!amdgpu_sriov_vf(adev)) {
1914	adev->gfxhub.funcs->set_fault_enable_default(adev, value);	1930	if (!adev->in_s0ix)
		1931	adev->gfxhub.funcs->set_fault_enable_default(adev, value);
1915	adev->mmhub.funcs->set_fault_enable_default(adev, value);	1932	adev->mmhub.funcs->set_fault_enable_default(adev, value);
1916	}	1933	}
1917	for (i = 0; i < adev->num_vmhubs; ++i)	1934	for (i = 0; i < adev->num_vmhubs; ++i) {
		1935	if (adev->in_s0ix && (i == AMDGPU_GFXHUB_0))
		1936	continue;
1918	gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);	1937	gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
		1938	}
1919		1939
1920	if (adev->umc.funcs && adev->umc.funcs->init_registers)	1940	if (adev->umc.funcs && adev->umc.funcs->init_registers)
1921	adev->umc.funcs->init_registers(adev);	1941	adev->umc.funcs->init_registers(adev);
@@ -1939,7 +1959,8 @@ static int gmc_v9_0_hw_init(void *handle) · 17 unmodified lines
1939	*/	1959	*/
1940	static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)	1960	static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1941	{	1961	{
1942	adev->gfxhub.funcs->gart_disable(adev);	1962	if (!adev->in_s0ix)
		1963	adev->gfxhub.funcs->gart_disable(adev);
1943	adev->mmhub.funcs->gart_disable(adev);	1964	adev->mmhub.funcs->gart_disable(adev);
1944	}	1965	}
1945		1966

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c+6−2

 	fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
 	r = amdgpu_bo_create_reserved(adev, fw_size,
-				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
+				      PAGE_SIZE,
+				      AMDGPU_GEM_DOMAIN_VRAM |
+				      AMDGPU_GEM_DOMAIN_GTT,
 				      &adev->mes.ucode_fw_obj[pipe],
 				      &adev->mes.ucode_fw_gpu_addr[pipe],
 				      (void **)&adev->mes.ucode_fw_ptr[pipe]);
 	fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
 	r = amdgpu_bo_create_reserved(adev, fw_size,
-				      64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
+				      64 * 1024,
+				      AMDGPU_GEM_DOMAIN_VRAM |
+				      AMDGPU_GEM_DOMAIN_GTT,
 				      &adev->mes.data_fw_obj[pipe],
 				      &adev->mes.data_fw_gpu_addr[pipe],
 				      (void **)&adev->mes.data_fw_ptr[pipe]);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c+1−1

@@ -114,7 +114,7 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) · 113 unmodified lines
114	return;	114	return;
115		115
116	/* Set default page address. */	116	/* Set default page address. */
117	value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);	117	value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
118	WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,	118	WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
119	(u32)(value >> 12));	119	(u32)(value >> 12));
120	WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,	120	WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c+1−1

@@ -134,7 +134,7 @@ static void mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device *adev) · 133 unmodified lines
134	}	134	}
135		135
136	/* Set default page address. */	136	/* Set default page address. */
137	value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);	137	value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
138	WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,	138	WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
139	(u32)(value >> 12));	139	(u32)(value >> 12));
140	WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,	140	WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c+1−1

@@ -234,7 +234,7 @@ static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev) · 233 unmodified lines
234	}	234	}
235		235
236	/* Set default page address. */	236	/* Set default page address. */
237	value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);	237	value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
238	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,	238	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
239	(u32)(value >> 12));	239	(u32)(value >> 12));
240	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,	240	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c+1−1

@@ -164,7 +164,7 @@ static void mmhub_v2_3_init_system_aperture_regs(struct amdgpu_device *adev) · 163 unmodified lines
164	max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);	164	max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
165		165
166	/* Set default page address. */	166	/* Set default page address. */
167	value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);	167	value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
168	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,	168	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
169	(u32)(value >> 12));	169	(u32)(value >> 12));
170	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,	170	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c+1−1

@@ -188,7 +188,7 @@ static void mmhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev) · 187 unmodified lines
188	}	188	}
189		189
190	/* Set default page address. */	190	/* Set default page address. */
191	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +	191	value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start +
192	adev->vm_manager.vram_base_offset;	192	adev->vm_manager.vram_base_offset;
193	WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,	193	WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
194	(u32)(value >> 12));	194	(u32)(value >> 12));

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c+1−1

@@ -188,7 +188,7 @@ static void mmhub_v3_0_1_init_system_aperture_regs(struct amdgpu_device *adev) · 187 unmodified lines
188	adev->gmc.vram_end >> 18);	188	adev->gmc.vram_end >> 18);
189		189
190	/* Set default page address. */	190	/* Set default page address. */
191	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +	191	value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start +
192	adev->vm_manager.vram_base_offset;	192	adev->vm_manager.vram_base_offset;
193	WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,	193	WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
194	(u32)(value >> 12));	194	(u32)(value >> 12));

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c+1−1

@@ -181,7 +181,7 @@ static void mmhub_v3_0_2_init_system_aperture_regs(struct amdgpu_device *adev) · 180 unmodified lines
181	}	181	}
182		182
183	/* Set default page address. */	183	/* Set default page address. */
184	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +	184	value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start +
185	adev->vm_manager.vram_base_offset;	185	adev->vm_manager.vram_base_offset;
186	WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,	186	WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
187	(u32)(value >> 12));	187	(u32)(value >> 12));

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c+1−1

@@ -136,7 +136,7 @@ static void mmhub_v9_4_init_system_aperture_regs(struct amdgpu_device *adev, · 135 unmodified lines
136	max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);	136	max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
137		137
138	/* Set default page address. */	138	/* Set default page address. */
139	value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);	139	value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
140	WREG32_SOC15_OFFSET(	140	WREG32_SOC15_OFFSET(
141	MMHUB, 0,	141	MMHUB, 0,
142	mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,	142	mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c+6−0

 	return xgpu_ai_send_access_requests(adev, IDH_REQ_GPU_INIT_DATA);
 }
+static void xgpu_ai_ras_poison_handler(struct amdgpu_device *adev)
+{
+	xgpu_ai_send_access_requests(adev, IDH_RAS_POISON);
+}
 const struct amdgpu_virt_ops xgpu_ai_virt_ops = {
 	.req_full_gpu	= xgpu_ai_request_full_gpu_access,
 	.rel_full_gpu	= xgpu_ai_release_full_gpu_access,
 	.wait_reset = NULL,
 	.trans_msg = xgpu_ai_mailbox_trans_msg,
 	.req_init_data  = xgpu_ai_request_init_data,
+	.ras_poison_handler = xgpu_ai_ras_poison_handler,
 };

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h+1−0

@@ -39,6 +39,7 @@ enum idh_request { · 38 unmodified lines
39		39
40	IDH_LOG_VF_ERROR = 200,	40	IDH_LOG_VF_ERROR = 200,
41	IDH_READY_TO_RESET = 201,	41	IDH_READY_TO_RESET = 201,
		42	IDH_RAS_POISON = 202,
42	};	43	};
43		44
44	enum idh_event {	45	enum idh_event {

drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c+6−0

 	amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
 }
+static void xgpu_nv_ras_poison_handler(struct amdgpu_device *adev)
+{
+	xgpu_nv_send_access_requests(adev, IDH_RAS_POISON);
+}
 const struct amdgpu_virt_ops xgpu_nv_virt_ops = {
 	.req_full_gpu	= xgpu_nv_request_full_gpu_access,
 	.rel_full_gpu	= xgpu_nv_release_full_gpu_access,
 	.reset_gpu = xgpu_nv_request_reset,
 	.wait_reset = NULL,
 	.trans_msg = xgpu_nv_mailbox_trans_msg,
+	.ras_poison_handler = xgpu_nv_ras_poison_handler,
 };

drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h+1−0

@@ -39,6 +39,7 @@ enum idh_request { · 38 unmodified lines
39		39
40	IDH_LOG_VF_ERROR = 200,	40	IDH_LOG_VF_ERROR = 200,
41	IDH_READY_TO_RESET = 201,	41	IDH_READY_TO_RESET = 201,
		42	IDH_RAS_POISON = 202,
42	};	43	};
43		44
44	enum idh_event {	45	enum idh_event {

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c+0−8

 			msleep(1000);
 	}
-	/* TODO: check whether can submit a doorbell request to raise
-	 * a doorbell fence to exit gfxoff.
-	 */
-	if (adev->in_s0ix)
-		amdgpu_gfx_off_ctrl(adev, false);
 	sdma_v5_2_soft_reset(adev);
 	/* unhalt the MEs */
 	sdma_v5_2_enable(adev, true);
 	/* start the gfx rings and rlc compute queues */
 	r = sdma_v5_2_gfx_resume(adev);
-	if (adev->in_s0ix)
-		amdgpu_gfx_off_ctrl(adev, true);
 	if (r)
 		return r;
 	r = sdma_v5_2_rlc_resume(adev);

drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h+12−12

@@ -55,10 +55,10 @@ enum ta_securedisplay_status { · 54 unmodified lines
55	TA_SECUREDISPLAY_STATUS__MAX = 0x7FFFFFFF,/* Maximum Value for status*/	55	TA_SECUREDISPLAY_STATUS__MAX = 0x7FFFFFFF,/* Maximum Value for status*/
56	};	56	};
57		57
58	/** @enum ta_securedisplay_max_phy	58	/** @enum ta_securedisplay_phy_ID
59	* Physical ID number to use for reading corresponding DIO Scratch register for ROI	59	* Physical ID number to use for reading corresponding DIO Scratch register for ROI
60	*/	60	*/
61	enum ta_securedisplay_max_phy {	61	enum ta_securedisplay_phy_ID {
62	TA_SECUREDISPLAY_PHY0 = 0,	62	TA_SECUREDISPLAY_PHY0 = 0,
63	TA_SECUREDISPLAY_PHY1 = 1,	63	TA_SECUREDISPLAY_PHY1 = 1,
64	TA_SECUREDISPLAY_PHY2 = 2,	64	TA_SECUREDISPLAY_PHY2 = 2,
@@ -139,16 +139,16 @@ union ta_securedisplay_cmd_output { · 74 unmodified lines
139	uint32_t reserved[4];	139	uint32_t reserved[4];
140	};	140	};
141		141
142	/** @struct securedisplay_cmd	142	/** @struct ta_securedisplay_cmd
143	* Secure Display Command which is shared buffer memory	143	* Secure display command which is shared buffer memory
144	*/	144	*/
145	struct securedisplay_cmd {	145	struct ta_securedisplay_cmd {
146	uint32_t cmd_id; /* +0 Bytes Command ID */	146	uint32_t cmd_id; /*< +0 Bytes Command ID /
147	enum ta_securedisplay_status status; /* +4 Bytes Status of Secure Display TA */	147	enum ta_securedisplay_status status; /*< +4 Bytes Status code returned by the secure display TA /
148	uint32_t reserved[2]; /* +8 Bytes Reserved */	148	uint32_t reserved[2]; /*< +8 Bytes Reserved /
149	union ta_securedisplay_cmd_input securedisplay_in_message; /* +16 Bytes Input Buffer */	149	union ta_securedisplay_cmd_input securedisplay_in_message; /*< +16 Bytes Command input buffer /
150	union ta_securedisplay_cmd_output securedisplay_out_message;/* +32 Bytes Output Buffer */	150	union ta_securedisplay_cmd_output securedisplay_out_message; /*< +32 Bytes Command output buffer /
151	/*@note Total 48 Bytes /	151	/*@note Total 48 Bytes /
152	};	152	};
153		153
154	#endif //_TA_SECUREDISPLAY_IF_H	154	#endif //_TA_SECUREDISPLAY_IF_H

drivers/gpu/drm/amd/amdgpu/umc_v8_10.c+4−20

@@ -340,29 +340,13 @@ static void umc_v8_10_err_cnt_init(struct amdgpu_device *adev) · 339 unmodified lines
340	}	340	}
341	}	341	}
342		342
343	static uint32_t umc_v8_10_query_ras_poison_mode_per_channel(
344	struct amdgpu_device *adev,
345	uint32_t umc_reg_offset)
346	{
347	uint32_t ecc_ctrl_addr, ecc_ctrl;
348
349	ecc_ctrl_addr =
350	SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccCtrl);
351	ecc_ctrl = RREG32_PCIE((ecc_ctrl_addr +
352	umc_reg_offset) * 4);
353
354	return REG_GET_FIELD(ecc_ctrl, UMCCH0_0_GeccCtrl, UCFatalEn);
355	}
356
357	static bool umc_v8_10_query_ras_poison_mode(struct amdgpu_device *adev)	343	static bool umc_v8_10_query_ras_poison_mode(struct amdgpu_device *adev)
358	{	344	{
359	uint32_t umc_reg_offset = 0;	345	/*
360		346	* Force return true, because UMCCH0_0_GeccCtrl
361	/* Enabling fatal error in umc node0 instance0 channel0 will be	347	* is not accessible from host side
362	* considered as fatal error mode
363	*/	348	*/
364	umc_reg_offset = get_umc_v8_10_reg_offset(adev, 0, 0, 0);	349	return true;
365	return !umc_v8_10_query_ras_poison_mode_per_channel(adev, umc_reg_offset);
366	}	350	}
367		351
368	const struct amdgpu_ras_block_hw_ops umc_v8_10_ras_hw_ops = {	352	const struct amdgpu_ras_block_hw_ops umc_v8_10_ras_hw_ops = {

drivers/gpu/drm/amd/amdkfd/kfd_device.c+0−11

 			f2g = &gfx_v8_kfd2kgd;
 		break;
 	case CHIP_FIJI:
-		gfx_target_version = 80003;
-		f2g = &gfx_v8_kfd2kgd;
-		break;
 	case CHIP_POLARIS10:
 		gfx_target_version = 80003;
 		f2g = &gfx_v8_kfd2kgd;
 		break;
 	case CHIP_POLARIS11:
-		gfx_target_version = 80003;
-		if (!vf)
-			f2g = &gfx_v8_kfd2kgd;
-		break;
 	case CHIP_POLARIS12:
-		gfx_target_version = 80003;
-		if (!vf)
-			f2g = &gfx_v8_kfd2kgd;
-		break;
 	case CHIP_VEGAM:
 		gfx_target_version = 80003;
 		if (!vf)

drivers/gpu/drm/amd/amdkfd/kfd_topology.c+1−1

@@ -801,7 +801,7 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, · 800 unmodified lines
801		801
802	p2plink->attr.name = "properties";	802	p2plink->attr.name = "properties";
803	p2plink->attr.mode = KFD_SYSFS_FILE_MODE;	803	p2plink->attr.mode = KFD_SYSFS_FILE_MODE;
804	sysfs_attr_init(&iolink->attr);	804	sysfs_attr_init(&p2plink->attr);
805	ret = sysfs_create_file(p2plink->kobj, &p2plink->attr);	805	ret = sysfs_create_file(p2plink->kobj, &p2plink->attr);
806	if (ret < 0)	806	if (ret < 0)
807	return ret;	807	return ret;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+252−112

 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 				    struct amdgpu_dm_connector *amdgpu_dm_connector,
-				    uint32_t link_index,
+				    u32 link_index,
 				    struct amdgpu_encoder *amdgpu_encoder);
 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 				  struct amdgpu_encoder *aencoder,
 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 				  u32 *vbl, u32 *position)
 {
-	uint32_t v_blank_start, v_blank_end, h_position, v_position;
+	u32 v_blank_start, v_blank_end, h_position, v_position;
 	if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 		return -EINVAL;
 	struct amdgpu_device *adev = irq_params->adev;
 	unsigned long flags;
 	struct drm_pending_vblank_event *e;
-	uint32_t vpos, hpos, v_blank_start, v_blank_end;
+	u32 vpos, hpos, v_blank_start, v_blank_end;
 	bool vrr_active;
 	amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 	struct drm_connector *connector;
 	struct drm_connector_list_iter iter;
 	struct dc_link *link;
-	uint8_t link_index = 0;
+	u8 link_index = 0;
 	struct drm_device *dev;
 	if (adev == NULL)
 	struct amdgpu_device *adev = irq_params->adev;
 	struct amdgpu_display_manager *dm = &adev->dm;
 	struct dmcub_trace_buf_entry entry = { 0 };
-	uint32_t count = 0;
+	u32 count = 0;
 	struct dmub_hpd_work *dmub_hpd_wrk;
 	struct dc_link *plink = NULL;
 	struct dmub_srv_hw_params hw_params;
 	enum dmub_status status;
 	const unsigned char *fw_inst_const, *fw_bss_data;
-	uint32_t i, fw_inst_const_size, fw_bss_data_size;
+	u32 i, fw_inst_const_size, fw_bss_data_size;
 	bool has_hw_support;
 	if (!dmub_srv)
 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
 {
-	uint64_t pt_base;
+	u64 pt_base;
-	uint32_t logical_addr_low;
+	u32 logical_addr_low;
-	uint32_t logical_addr_high;
+	u32 logical_addr_high;
-	uint32_t agp_base, agp_bot, agp_top;
+	u32 agp_base, agp_bot, agp_top;
 	PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
 	memset(pa_config, 0, sizeof(*pa_config));
 	}
 #endif
 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
-	adev->dm.crc_rd_wrk = amdgpu_dm_crtc_secure_display_create_work();
+	adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
+	if (!adev->dm.secure_display_ctxs) {
+		DRM_ERROR("amdgpu: failed to initialize secure_display_ctxs.\n");
+	}
 #endif
 	if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
 		init_completion(&adev->dm.dmub_aux_transfer_done);
 	amdgpu_dm_destroy_drm_device(&adev->dm);
 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
-	if (adev->dm.crc_rd_wrk) {
+	if (adev->dm.secure_display_ctxs) {
-		flush_work(&adev->dm.crc_rd_wrk->notify_ta_work);
+		for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
-		kfree(adev->dm.crc_rd_wrk);
+			if (adev->dm.secure_display_ctxs[i].crtc) {
-		adev->dm.crc_rd_wrk = NULL;
+				flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
+				flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
+			}
+		}
+		kfree(adev->dm.secure_display_ctxs);
+		adev->dm.secure_display_ctxs = NULL;
 	}
 #endif
 #ifdef CONFIG_DRM_AMD_DC_HDCP
 	 * TODO: Move this into GART.
 	 */
 	r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
-				    AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo,
+				    AMDGPU_GEM_DOMAIN_VRAM |
+				    AMDGPU_GEM_DOMAIN_GTT,
+				    &adev->dm.dmub_bo,
 				    &adev->dm.dmub_bo_gpu_addr,
 				    &adev->dm.dmub_bo_cpu_addr);
 	if (r)
 				DRM_ERROR("DM_MST: Failed to start MST\n");
 				aconnector->dc_link->type =
 					dc_connection_single;
+				ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
+								     aconnector->dc_link);
 				break;
 			}
 		}
 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
 					     struct drm_crtc *crtc)
 {
-	uint32_t i;
+	u32 i;
 	struct drm_connector_state *new_con_state;
 	struct drm_connector *connector;
 	struct drm_crtc *crtc_from_state;
 	drm_for_each_connector_iter(connector, &iter) {
 		aconnector = to_amdgpu_dm_connector(connector);
+		if (!aconnector->dc_link)
+			continue;
 		/*
 		 * this is the case when traversing through already created
 		 * MST connectors, should be skipped
 		 */
-		if (aconnector->dc_link &&
+		if (aconnector->dc_link->type == dc_connection_mst_branch)
-		    aconnector->dc_link->type == dc_connection_mst_branch)
 			continue;
 		mutex_lock(&aconnector->hpd_lock);
 static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
 {
-	uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
+	u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
-	uint8_t dret;
+	u8 dret;
 	bool new_irq_handled = false;
 	int dpcd_addr;
 	int dpcd_bytes_to_read;
 	while (dret == dpcd_bytes_to_read &&
 		process_count < max_process_count) {
-		uint8_t retry;
+		u8 retry;
 		dret = 0;
 		process_count++;
 				dpcd_bytes_to_read - 1;
 			for (retry = 0; retry < 3; retry++) {
-				uint8_t wret;
+				u8 wret;
 				wret = drm_dp_dpcd_write(
 					&aconnector->dm_dp_aux.aux,
 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 {
 	struct amdgpu_display_manager *dm = &adev->dm;
-	int32_t i;
+	s32 i;
 	struct amdgpu_dm_connector *aconnector = NULL;
 	struct amdgpu_encoder *aencoder = NULL;
 	struct amdgpu_mode_info *mode_info = &adev->mode_info;
-	uint32_t link_cnt;
+	u32 link_cnt;
-	int32_t primary_planes;
+	s32 primary_planes;
 	enum dc_connection_type new_connection_type = dc_connection_none;
 	const struct dc_plane_cap *plane;
 	bool psr_feature_enabled = false;
 static int
 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
 			    const struct drm_plane_state *plane_state,
-			    const uint64_t tiling_flags,
+			    const u64 tiling_flags,
 			    struct dc_plane_info *plane_info,
 			    struct dc_plane_address *address,
 			    bool tmz_surface,
 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
 				      struct rect *dirty_rect, int32_t x,
-				      int32_t y, int32_t width, int32_t height,
+				      s32 y, s32 width, s32 height,
 				      int *i, bool ffu)
 {
 	if (*i > DC_MAX_DIRTY_RECTS)
 {
 	struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
 	struct rect *dirty_rects = flip_addrs->dirty_rects;
-	uint32_t num_clips;
+	u32 num_clips;
 	struct drm_mode_rect *clips;
 	bool bb_changed;
 	bool fb_changed;
-	uint32_t i = 0;
+	u32 i = 0;
 	/*
 	 * Cursor plane has it's own dirty rect update interface. See
 convert_color_depth_from_display_info(const struct drm_connector *connector,
 				      bool is_y420, int requested_bpc)
 {
-	uint8_t bpc;
+	u8 bpc;
 	if (is_y420) {
 		bpc = 8;
 				    uint32_t max_dsc_target_bpp_limit_override)
 {
 	const struct dc_link_settings *verified_link_cap = NULL;
-	uint32_t link_bw_in_kbps;
+	u32 link_bw_in_kbps;
-	uint32_t edp_min_bpp_x16, edp_max_bpp_x16;
+	u32 edp_min_bpp_x16, edp_max_bpp_x16;
 	struct dc *dc = sink->ctx->dc;
 	struct dc_dsc_bw_range bw_range = {0};
 	struct dc_dsc_config dsc_cfg = {0};
 					struct dsc_dec_dpcd_caps *dsc_caps)
 {
 	struct drm_connector *drm_connector = &aconnector->base;
-	uint32_t link_bandwidth_kbps;
+	u32 link_bandwidth_kbps;
 	struct dc *dc = sink->ctx->dc;
-	uint32_t max_supported_bw_in_kbps, timing_bw_in_kbps;
+	u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
-	uint32_t dsc_max_supported_bw_in_kbps;
+	u32 dsc_max_supported_bw_in_kbps;
-	uint32_t max_dsc_target_bpp_limit_override =
+	u32 max_dsc_target_bpp_limit_override =
 		drm_connector->display_info.max_dsc_bpp;
 	link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
 		 */
 		DRM_DEBUG_DRIVER("No preferred mode found\n");
 	} else {
-		recalculate_timing = is_freesync_video_mode(&mode, aconnector);
+		recalculate_timing = amdgpu_freesync_vid_mode &&
+				 is_freesync_video_mode(&mode, aconnector);
 		if (recalculate_timing) {
 			freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
 			drm_mode_copy(&saved_mode, &mode);
 	const struct drm_display_mode *m;
 	struct drm_display_mode *new_mode;
 	uint i;
-	uint32_t new_modes_count = 0;
+	u32 new_modes_count = 0;
 	/* Standard FPS values
 	 *
 	 * 60 	        - Commonly used
 	 * 48,72,96,120 - Multiples of 24
 	 */
-	static const uint32_t common_rates[] = {
+	static const u32 common_rates[] = {
 		23976, 24000, 25000, 29970, 30000,
 		48000, 50000, 60000, 72000, 96000, 120000
 	};
 		return 0;
 	for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
-		uint64_t target_vtotal, target_vtotal_diff;
+		u64 target_vtotal, target_vtotal_diff;
-		uint64_t num, den;
+		u64 num, den;
 		if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
 			continue;
 	struct amdgpu_dm_connector *amdgpu_dm_connector =
 		to_amdgpu_dm_connector(connector);
-	if (!edid)
+	if (!(amdgpu_freesync_vid_mode && edid))
 		return;
 	if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
  */
 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 				    struct amdgpu_dm_connector *aconnector,
-				    uint32_t link_index,
+				    u32 link_index,
 				    struct amdgpu_encoder *aencoder)
 {
 	int res = 0;
 }
 #ifdef CONFIG_DRM_AMD_DC_HDCP
-static bool is_content_protection_different(struct drm_connector_state *state,
+static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
-					    const struct drm_connector_state *old_state,
+					    struct drm_crtc_state *old_crtc_state,
-					    const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w)
+					    struct drm_connector_state *new_conn_state,
+					    struct drm_connector_state *old_conn_state,
+					    const struct drm_connector *connector,
+					    struct hdcp_workqueue *hdcp_w)
 {
 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 	struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
-	/* Handle: Type0/1 change */
+	pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
-	if (old_state->hdcp_content_type != state->hdcp_content_type &&
+		connector->index, connector->status, connector->dpms);
-	    state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
+	pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
-		state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+		old_conn_state->content_protection, new_conn_state->content_protection);
+	if (old_crtc_state)
+		pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
+		old_crtc_state->enable,
+		old_crtc_state->active,
+		old_crtc_state->mode_changed,
+		old_crtc_state->active_changed,
+		old_crtc_state->connectors_changed);
+	if (new_crtc_state)
+		pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
+		new_crtc_state->enable,
+		new_crtc_state->active,
+		new_crtc_state->mode_changed,
+		new_crtc_state->active_changed,
+		new_crtc_state->connectors_changed);
+	/* hdcp content type change */
+	if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
+	    new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
+		new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+		pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
 		return true;
 	}
-	/* CP is being re enabled, ignore this
+	/* CP is being re enabled, ignore this */
-	 *
+	if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
-	 * Handles:	ENABLED -> DESIRED
+	    new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
-	 */
+		if (new_crtc_state && new_crtc_state->mode_changed) {
-	if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
+			new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
-	    state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
+			pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
-		state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
+			return true;
+		};
+		new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
+		pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
 		return false;
 	}
 	 *
 	 * Handles:	UNDESIRED -> ENABLED
 	 */
-	if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
+	if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
-	    state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
+	    new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
-		state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+		new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
 	/* Stream removed and re-enabled
 	 *
 	 *
 	 * Handles:	DESIRED -> DESIRED (Special case)
 	 */
-	if (!(old_state->crtc && old_state->crtc->enabled) &&
+	if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
-		state->crtc && state->crtc->enabled &&
+		new_conn_state->crtc && new_conn_state->crtc->enabled &&
 		connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
 		dm_con_state->update_hdcp = false;
+		pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
+			__func__);
 		return true;
 	}
 	 *
 	 * Handles:	DESIRED -> DESIRED (Special case)
 	 */
-	if (dm_con_state->update_hdcp && state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
+	if (dm_con_state->update_hdcp &&
-	    connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
+	new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
+	connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
 		dm_con_state->update_hdcp = false;
+		pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
+			__func__);
 		return true;
 	}
-	/*
+	if (old_conn_state->content_protection == new_conn_state->content_protection) {
-	 * Handles:	UNDESIRED -> UNDESIRED
+		if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
-	 *		DESIRED -> DESIRED
+			if (new_crtc_state && new_crtc_state->mode_changed) {
-	 *		ENABLED -> ENABLED
+				pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
-	 */
+					__func__);
-	if (old_state->content_protection == state->content_protection)
+				return true;
+			};
+			pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
+				__func__);
+			return false;
+		};
+		pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
 		return false;
+	}
-	/*
+	if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
-	 * Handles:	UNDESIRED -> DESIRED
+		pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
-	 *		DESIRED -> UNDESIRED
+			__func__);
-	 *		ENABLED -> UNDESIRED
-	 */
-	if (state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED)
 		return true;
+	}
-	/*
+	pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
-	 * Handles:	DESIRED -> ENABLED
-	 */
 	return false;
 }
 #endif
 static void remove_stream(struct amdgpu_device *adev,
 			  struct amdgpu_crtc *acrtc,
 			  struct dc_stream_state *stream)
 				    struct drm_crtc *pcrtc,
 				    bool wait_for_vblank)
 {
-	uint32_t i;
+	u32 i;
-	uint64_t timestamp_ns;
+	u64 timestamp_ns;
 	struct drm_plane *plane;
 	struct drm_plane_state *old_plane_state, *new_plane_state;
 	struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
 			to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
 	int planes_count = 0, vpos, hpos;
 	unsigned long flags;
-	uint32_t target_vblank, last_flip_vblank;
+	u32 target_vblank, last_flip_vblank;
 	bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
 	bool cursor_update = false;
 	bool pflip_present = false;
 	struct amdgpu_display_manager *dm = &adev->dm;
 	struct dm_atomic_state *dm_state;
 	struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
-	uint32_t i, j;
+	u32 i, j;
 	struct drm_crtc *crtc;
 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 	unsigned long flags;
 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
 		struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
+		pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
+		if (!connector)
+			continue;
+		pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
+			connector->index, connector->status, connector->dpms);
+		pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
+			old_con_state->content_protection, new_con_state->content_protection);
+		if (aconnector->dc_sink) {
+			if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
+				aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
+				pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
+				aconnector->dc_sink->edid_caps.display_name);
+			}
+		}
 		new_crtc_state = NULL;
+		old_crtc_state = NULL;
-		if (acrtc)
+		if (acrtc) {
 			new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
+			old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
+		}
+		if (old_crtc_state)
+			pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
+			old_crtc_state->enable,
+			old_crtc_state->active,
+			old_crtc_state->mode_changed,
+			old_crtc_state->active_changed,
+			old_crtc_state->connectors_changed);
+		if (new_crtc_state)
+			pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
+			new_crtc_state->enable,
+			new_crtc_state->active,
+			new_crtc_state->mode_changed,
+			new_crtc_state->active_changed,
+			new_crtc_state->connectors_changed);
+	}
+	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
+		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
+		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
+		struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
+		new_crtc_state = NULL;
+		old_crtc_state = NULL;
+		if (acrtc) {
+			new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
+			old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
+		}
 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
 			continue;
 		}
-		if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
+		if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
+											old_con_state, connector, adev->dm.hdcp_workqueue)) {
+			/* when display is unplugged from mst hub, connctor will
+			 * be destroyed within dm_dp_mst_connector_destroy. connector
+			 * hdcp perperties, like type, undesired, desired, enabled,
+			 * will be lost. So, save hdcp properties into hdcp_work within
+			 * amdgpu_dm_atomic_commit_tail. if the same display is
+			 * plugged back with same display index, its hdcp properties
+			 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
+			 */
+			bool enable_encryption = false;
+			if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
+				enable_encryption = true;
+			if (aconnector->dc_link && aconnector->dc_sink &&
+				aconnector->dc_link->type == dc_connection_mst_branch) {
+				struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
+				struct hdcp_workqueue *hdcp_w =
+					&hdcp_work[aconnector->dc_link->link_index];
+				hdcp_w->hdcp_content_type[connector->index] =
+					new_con_state->hdcp_content_type;
+				hdcp_w->content_protection[connector->index] =
+					new_con_state->content_protection;
+			}
+			if (new_crtc_state && new_crtc_state->mode_changed &&
+				new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
+				enable_encryption = true;
+			DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
 			hdcp_update_display(
 				adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
-				new_con_state->hdcp_content_type,
+				new_con_state->hdcp_content_type, enable_encryption);
-				new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED);
+		}
 	}
 #endif
 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
 #ifdef CONFIG_DEBUG_FS
 		enum amdgpu_dm_pipe_crc_source cur_crc_src;
-#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
-		struct crc_rd_work *crc_rd_wrk;
-#endif
 #endif
 		/* Count number of newly disabled CRTCs for dropping PM refs later. */
 		if (old_crtc_state->active && !new_crtc_state->active)
 		update_stream_irq_parameters(dm, dm_new_crtc_state);
 #ifdef CONFIG_DEBUG_FS
-#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
-		crc_rd_wrk = dm->crc_rd_wrk;
-#endif
 		spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 		cur_crc_src = acrtc->dm_irq_params.crc_src;
 		spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 				if (amdgpu_dm_crc_window_is_activated(crtc)) {
 					spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 					acrtc->dm_irq_params.window_param.update_win = true;
+					/**
+					 * It takes 2 frames for HW to stably generate CRC when
+					 * resuming from suspend, so we set skip_frame_cnt 2.
+					 */
 					acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
-					spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock);
-					crc_rd_wrk->crtc = crtc;
-					spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock);
 					spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 				}
 #endif
 	struct drm_display_mode *mode = &new_crtc_state->base.mode;
 	int vrefresh = drm_mode_vrefresh(mode);
 	bool fs_vid_mode = false;
+	bool drr_active = false;
 	new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
 					vrefresh >= aconnector->min_vfreq &&
 					vrefresh <= aconnector->max_vfreq;
-	if (new_crtc_state->vrr_supported) {
+	drr_active = new_crtc_state->vrr_supported &&
+		new_crtc_state->freesync_config.state != VRR_STATE_DISABLED &&
+		new_crtc_state->freesync_config.state != VRR_STATE_INACTIVE &&
+		new_crtc_state->freesync_config.state != VRR_STATE_UNSUPPORTED;
+	if (drr_active)
 		new_crtc_state->stream->ignore_msa_timing_param = true;
-		fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
+	if (new_crtc_state->vrr_supported) {
+		fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
 		config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
 		config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
 		config.vsif_supported = true;
 }
 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
-	uint64_t num, den, res;
+	u64 num, den, res;
 	struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
 	dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
 		 * TODO: Refactor this function to allow this check to work
 		 * in all conditions.
 		 */
-		if (dm_new_crtc_state->stream &&
+		if (amdgpu_freesync_vid_mode &&
+		    dm_new_crtc_state->stream &&
 		    is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
 			goto skip_modeset;
 		if (!dm_old_crtc_state->stream)
 			goto skip_modeset;
-		if (dm_new_crtc_state->stream &&
+		if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
 		    is_timing_unchanged_for_freesync(new_crtc_state,
 						     old_crtc_state)) {
 			new_crtc_state->mode_changed = false;
 			set_freesync_fixed_config(dm_new_crtc_state);
 			goto skip_modeset;
-		} else if (aconnector &&
+		} else if (amdgpu_freesync_vid_mode && aconnector &&
 			   is_freesync_video_mode(&new_crtc_state->mode,
 						  aconnector)) {
 			struct drm_display_mode *high_mode;
 static bool is_dp_capable_without_timing_msa(struct dc *dc,
 					     struct amdgpu_dm_connector *amdgpu_dm_connector)
 {
-	uint8_t dpcd_data;
+	u8 dpcd_data;
 	bool capable = false;
 	if (amdgpu_dm_connector->dc_link &&
 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
 		unsigned int offset,
 		unsigned int total_length,
-		uint8_t *data,
+		u8 *data,
 		unsigned int length,
 		struct amdgpu_hdmi_vsdb_info *vsdb)
 {
 }
 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
-		uint8_t *edid_ext, int len,
+		u8 *edid_ext, int len,
 		struct amdgpu_hdmi_vsdb_info *vsdb_info)
 {
 	int i;
 }
 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
-		uint8_t *edid_ext, int len,
+		u8 *edid_ext, int len,
 		struct amdgpu_hdmi_vsdb_info *vsdb_info)
 {
 	int i;
 }
 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
-		uint8_t *edid_ext, int len,
+		u8 *edid_ext, int len,
 		struct amdgpu_hdmi_vsdb_info *vsdb_info)
 {
 	struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
 		struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
 {
-	uint8_t *edid_ext = NULL;
+	u8 *edid_ext = NULL;
 	int i;
 	bool valid_vsdb_found = false;
 }
 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
-		       uint32_t value, const char *func_name)
+		       u32 value, const char *func_name)
 {
 #ifdef DM_CHECK_ADDR_0
 	if (address == 0) {
 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
 			  const char *func_name)
 {
-	uint32_t value;
+	u32 value;
 #ifdef DM_CHECK_ADDR_0
 	if (address == 0) {
 		DC_ERR("invalid register read; address = 0\n");

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h+4−3

 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 	/**
-	 * @crc_rd_wrk:
+	 * @secure_display_ctxs:
 	 *
-	 * Work to be executed in a separate thread to communicate with PSP.
+	 * Store the ROI information and the work_struct to command dmub and psp for
+	 * all crtcs.
 	 */
-	struct crc_rd_work *crc_rd_wrk;
+	struct secure_display_context *secure_display_ctxs;
 #endif
 	/**
 	 * @hpd_rx_offload_wq:

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c+87−74

@@ -101,35 +101,44 @@ static void amdgpu_dm_set_crc_window_default(struct drm_crtc *crtc) · 100 unmodified lines
101		101
102	static void amdgpu_dm_crtc_notify_ta_to_read(struct work_struct *work)	102	static void amdgpu_dm_crtc_notify_ta_to_read(struct work_struct *work)
103	{	103	{
104	struct crc_rd_work *crc_rd_wrk;	104	struct secure_display_context *secure_display_ctx;
105	struct amdgpu_device *adev;
106	struct psp_context *psp;	105	struct psp_context *psp;
107	struct securedisplay_cmd *securedisplay_cmd;	106	struct ta_securedisplay_cmd *securedisplay_cmd;
108	struct drm_crtc *crtc;	107	struct drm_crtc *crtc;
109	uint8_t phy_id;	108	struct dc_stream_state *stream;
		109	uint8_t phy_inst;
110	int ret;	110	int ret;
111		111
112	crc_rd_wrk = container_of(work, struct crc_rd_work, notify_ta_work);	112	secure_display_ctx = container_of(work, struct secure_display_context, notify_ta_work);
113	spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock);	113	crtc = secure_display_ctx->crtc;
114	crtc = crc_rd_wrk->crtc;
115		114
116	if (!crtc) {	115	if (!crtc) {
117	spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock);
118	return;	116	return;
119	}	117	}
120		118
121	adev = drm_to_adev(crtc->dev);	119	psp = &drm_to_adev(crtc->dev)->psp;
122	psp = &adev->psp;	120
123	phy_id = crc_rd_wrk->phy_inst;	121	if (!psp->securedisplay_context.context.initialized) {
124	spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock);	122	DRM_DEBUG_DRIVER("Secure Display fails to notify PSP TA\n");
		123	return;
		124	}
		125
		126	stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream;
		127	phy_inst = stream->link->link_enc_hw_inst;
125		128
		129	/* need lock for multiple crtcs to use the command buffer */
126	mutex_lock(&psp->securedisplay_context.mutex);	130	mutex_lock(&psp->securedisplay_context.mutex);
127		131
128	psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,	132	psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
129	TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC);	133	TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC);
130	securedisplay_cmd->securedisplay_in_message.send_roi_crc.phy_id =	134
131	phy_id;	135	securedisplay_cmd->securedisplay_in_message.send_roi_crc.phy_id = phy_inst;
		136
		137	/* PSP TA is expected to finish data transmission over I2C within current frame,
		138	* even there are up to 4 crtcs request to send in this frame.
		139	*/
132	ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC);	140	ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC);
		141
133	if (!ret) {	142	if (!ret) {
134	if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {	143	if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
135	psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);	144	psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
@@ -142,17 +151,23 @@ static void amdgpu_dm_crtc_notify_ta_to_read(struct work_struct *work) · 6 unmodified lines
142	static void	151	static void
143	amdgpu_dm_forward_crc_window(struct work_struct *work)	152	amdgpu_dm_forward_crc_window(struct work_struct *work)
144	{	153	{
145	struct crc_fw_work *crc_fw_wrk;	154	struct secure_display_context *secure_display_ctx;
146	struct amdgpu_display_manager *dm;	155	struct amdgpu_display_manager *dm;
		156	struct drm_crtc *crtc;
		157	struct dc_stream_state *stream;
147		158
148	crc_fw_wrk = container_of(work, struct crc_fw_work, forward_roi_work);	159	secure_display_ctx = container_of(work, struct secure_display_context, forward_roi_work);
149	dm = crc_fw_wrk->dm;	160	crtc = secure_display_ctx->crtc;
		161
		162	if (!crtc)
		163	return;
		164
		165	dm = &drm_to_adev(crtc->dev)->dm;
		166	stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream;
150		167
151	mutex_lock(&dm->dc_lock);	168	mutex_lock(&dm->dc_lock);
152	dc_stream_forward_crc_window(dm->dc, &crc_fw_wrk->rect, crc_fw_wrk->stream, crc_fw_wrk->is_stop_cmd);	169	dc_stream_forward_crc_window(stream, &secure_display_ctx->rect, false);
153	mutex_unlock(&dm->dc_lock);	170	mutex_unlock(&dm->dc_lock);
154
155	kfree(crc_fw_wrk);
156	}	171	}
157		172
158	bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc)	173	bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc)
@@ -189,6 +204,9 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, · 30 unmodified lines
189	struct dm_crtc_state *dm_crtc_state,	204	struct dm_crtc_state *dm_crtc_state,
190	enum amdgpu_dm_pipe_crc_source source)	205	enum amdgpu_dm_pipe_crc_source source)
191	{	206	{
		207	#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
		208	int i;
		209	#endif
192	struct amdgpu_device *adev = drm_to_adev(crtc->dev);	210	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
193	struct dc_stream_state *stream_state = dm_crtc_state->stream;	211	struct dc_stream_state *stream_state = dm_crtc_state->stream;
194	bool enable = amdgpu_dm_is_valid_crc_source(source);	212	bool enable = amdgpu_dm_is_valid_crc_source(source);
@@ -200,21 +218,18 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, · 5 unmodified lines
200		218
201	mutex_lock(&adev->dm.dc_lock);	219	mutex_lock(&adev->dm.dc_lock);
202		220
203	/* Enable CRTC CRC generation if necessary. */	221	/* Enable or disable CRTC CRC generation */
204	if (dm_is_crc_source_crtc(source) \|\| source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) {	222	if (dm_is_crc_source_crtc(source) \|\| source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) {
205	#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)	223	#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
		224	/* Disable secure_display if it was enabled */
206	if (!enable) {	225	if (!enable) {
207	if (adev->dm.crc_rd_wrk) {	226	for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
208	flush_work(&adev->dm.crc_rd_wrk->notify_ta_work);	227	if (adev->dm.secure_display_ctxs[i].crtc == crtc) {
209	spin_lock_irq(&adev->dm.crc_rd_wrk->crc_rd_work_lock);
210
211	if (adev->dm.crc_rd_wrk->crtc == crtc) {
212	/* stop ROI update on this crtc */	228	/* stop ROI update on this crtc */
213	dc_stream_forward_crc_window(stream_state->ctx->dc,	229	flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
214	NULL, stream_state, true);	230	flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
215	adev->dm.crc_rd_wrk->crtc = NULL;	231	dc_stream_forward_crc_window(stream_state, NULL, true);
216	}	232	}
217	spin_unlock_irq(&adev->dm.crc_rd_wrk->crc_rd_work_lock);
218	}	233	}
219	}	234	}
220	#endif	235	#endif
@@ -347,6 +362,7 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc crtc, const char src_name) · 126 unmodified lines
347	}	362	}
348		363
349	#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)	364	#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
		365	/* Reset secure_display when we change crc source from debugfs */
350	amdgpu_dm_set_crc_window_default(crtc);	366	amdgpu_dm_set_crc_window_default(crtc);
351	#endif	367	#endif
352		368
@@ -456,14 +472,12 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc) · 103 unmodified lines
456	#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)	472	#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
457	void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc)	473	void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc)
458	{	474	{
459	struct dc_stream_state *stream_state;
460	struct drm_device *drm_dev = NULL;	475	struct drm_device *drm_dev = NULL;
461	enum amdgpu_dm_pipe_crc_source cur_crc_src;	476	enum amdgpu_dm_pipe_crc_source cur_crc_src;
462	struct amdgpu_crtc *acrtc = NULL;	477	struct amdgpu_crtc *acrtc = NULL;
463	struct amdgpu_device *adev = NULL;	478	struct amdgpu_device *adev = NULL;
464	struct crc_rd_work *crc_rd_wrk;	479	struct secure_display_context *secure_display_ctx = NULL;
465	struct crc_fw_work *crc_fw_wrk;	480	unsigned long flags1;
466	unsigned long flags1, flags2;
467		481
468	if (crtc == NULL)	482	if (crtc == NULL)
469	return;	483	return;
@@ -473,75 +487,74 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) · 3 unmodified lines
473	drm_dev = crtc->dev;	487	drm_dev = crtc->dev;
474		488
475	spin_lock_irqsave(&drm_dev->event_lock, flags1);	489	spin_lock_irqsave(&drm_dev->event_lock, flags1);
476	stream_state = acrtc->dm_irq_params.stream;
477	cur_crc_src = acrtc->dm_irq_params.crc_src;	490	cur_crc_src = acrtc->dm_irq_params.crc_src;
478		491
479	/* Early return if CRC capture is not enabled. */	492	/* Early return if CRC capture is not enabled. */
480	if (!amdgpu_dm_is_valid_crc_source(cur_crc_src))	493	if (!amdgpu_dm_is_valid_crc_source(cur_crc_src) \|\|
		494	!dm_is_crc_source_crtc(cur_crc_src))
481	goto cleanup;	495	goto cleanup;
482		496
483	if (!dm_is_crc_source_crtc(cur_crc_src))	497	if (!acrtc->dm_irq_params.window_param.activated)
484	goto cleanup;	498	goto cleanup;
485		499
486	if (!acrtc->dm_irq_params.window_param.activated)	500	if (acrtc->dm_irq_params.window_param.skip_frame_cnt) {
		501	acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1;
487	goto cleanup;	502	goto cleanup;
		503	}
488		504
489	if (acrtc->dm_irq_params.window_param.update_win) {	505	secure_display_ctx = &adev->dm.secure_display_ctxs[acrtc->crtc_id];
490	if (acrtc->dm_irq_params.window_param.skip_frame_cnt) {	506	if (WARN_ON(secure_display_ctx->crtc != crtc)) {
491	acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1;	507	/* We have set the crtc when creating secure_display_context,
492	goto cleanup;	508	* don't expect it to be changed here.
493	}	509	*/
		510	secure_display_ctx->crtc = crtc;
		511	}
494		512
		513	if (acrtc->dm_irq_params.window_param.update_win) {
495	/* prepare work for dmub to update ROI */	514	/* prepare work for dmub to update ROI */
496	crc_fw_wrk = kzalloc(sizeof(*crc_fw_wrk), GFP_ATOMIC);	515	secure_display_ctx->rect.x = acrtc->dm_irq_params.window_param.x_start;
497	if (!crc_fw_wrk)	516	secure_display_ctx->rect.y = acrtc->dm_irq_params.window_param.y_start;
498	goto cleanup;	517	secure_display_ctx->rect.width = acrtc->dm_irq_params.window_param.x_end -
499
500	INIT_WORK(&crc_fw_wrk->forward_roi_work, amdgpu_dm_forward_crc_window);
501	crc_fw_wrk->dm = &adev->dm;
502	crc_fw_wrk->stream = stream_state;
503	crc_fw_wrk->rect.x = acrtc->dm_irq_params.window_param.x_start;
504	crc_fw_wrk->rect.y = acrtc->dm_irq_params.window_param.y_start;
505	crc_fw_wrk->rect.width = acrtc->dm_irq_params.window_param.x_end -
506	acrtc->dm_irq_params.window_param.x_start;	518	acrtc->dm_irq_params.window_param.x_start;
507	crc_fw_wrk->rect.height = acrtc->dm_irq_params.window_param.y_end -	519	secure_display_ctx->rect.height = acrtc->dm_irq_params.window_param.y_end -
508	acrtc->dm_irq_params.window_param.y_start;	520	acrtc->dm_irq_params.window_param.y_start;
509	schedule_work(&crc_fw_wrk->forward_roi_work);	521	schedule_work(&secure_display_ctx->forward_roi_work);
510		522
511	acrtc->dm_irq_params.window_param.update_win = false;	523	acrtc->dm_irq_params.window_param.update_win = false;
		524
		525	/* Statically skip 1 frame, because we may need to wait below things
		526	* before sending ROI to dmub:
		527	* 1. We defer the work by using system workqueue.
		528	* 2. We may need to wait for dc_lock before accessing dmub.
		529	*/
512	acrtc->dm_irq_params.window_param.skip_frame_cnt = 1;	530	acrtc->dm_irq_params.window_param.skip_frame_cnt = 1;
513		531
514	} else {	532	} else {
515	if (acrtc->dm_irq_params.window_param.skip_frame_cnt) {	533	/* prepare work for psp to read ROI/CRC and send to I2C */
516	acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1;	534	schedule_work(&secure_display_ctx->notify_ta_work);
517	goto cleanup;
518	}
519
520	if (adev->dm.crc_rd_wrk) {
521	crc_rd_wrk = adev->dm.crc_rd_wrk;
522	spin_lock_irqsave(&crc_rd_wrk->crc_rd_work_lock, flags2);
523	crc_rd_wrk->phy_inst = stream_state->link->link_enc_hw_inst;
524	spin_unlock_irqrestore(&crc_rd_wrk->crc_rd_work_lock, flags2);
525	schedule_work(&crc_rd_wrk->notify_ta_work);
526	}
527	}	535	}
528		536
529	cleanup:	537	cleanup:
530	spin_unlock_irqrestore(&drm_dev->event_lock, flags1);	538	spin_unlock_irqrestore(&drm_dev->event_lock, flags1);
531	}	539	}
532		540
533	struct crc_rd_work *amdgpu_dm_crtc_secure_display_create_work(void)	541	struct secure_display_context *
		542	amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev)
534	{	543	{
535	struct crc_rd_work *crc_rd_wrk = NULL;	544	struct secure_display_context *secure_display_ctxs = NULL;
		545	int i;
536		546
537	crc_rd_wrk = kzalloc(sizeof(*crc_rd_wrk), GFP_KERNEL);	547	secure_display_ctxs = kcalloc(AMDGPU_MAX_CRTCS, sizeof(struct secure_display_context), GFP_KERNEL);
538		548
539	if (!crc_rd_wrk)	549	if (!secure_display_ctxs)
540	return NULL;	550	return NULL;
541		551
542	spin_lock_init(&crc_rd_wrk->crc_rd_work_lock);	552	for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
543	INIT_WORK(&crc_rd_wrk->notify_ta_work, amdgpu_dm_crtc_notify_ta_to_read);	553	INIT_WORK(&secure_display_ctxs[i].forward_roi_work, amdgpu_dm_forward_crc_window);
		554	INIT_WORK(&secure_display_ctxs[i].notify_ta_work, amdgpu_dm_crtc_notify_ta_to_read);
		555	secure_display_ctxs[i].crtc = &adev->mode_info.crtcs[i]->base;
		556	}
544		557
545	return crc_rd_wrk;	558	return secure_display_ctxs;
546	}	559	}
547	#endif	560	#endif

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h+11−15

@@ -45,7 +45,7 @@ struct crc_window_param { · 44 unmodified lines
45	uint16_t y_start;	45	uint16_t y_start;
46	uint16_t x_end;	46	uint16_t x_end;
47	uint16_t y_end;	47	uint16_t y_end;
48	/* CRC windwo is activated or not*/	48	/* CRC window is activated or not*/
49	bool activated;	49	bool activated;
50	/* Update crc window during vertical blank or not */	50	/* Update crc window during vertical blank or not */
51	bool update_win;	51	bool update_win;
@@ -53,22 +53,17 @@ struct crc_window_param { · 1 unmodified line
53	int skip_frame_cnt;	53	int skip_frame_cnt;
54	};	54	};
55		55
56	/* read_work for driver to call PSP to read */	56	struct secure_display_context {
57	struct crc_rd_work {	57	/* work to notify PSP TA*/
58	struct work_struct notify_ta_work;	58	struct work_struct notify_ta_work;
59	/* To protect crc_rd_work carried fields*/
60	spinlock_t crc_rd_work_lock;
61	struct drm_crtc *crtc;
62	uint8_t phy_inst;
63	};
64		59
65	/* forward_work for driver to forward ROI to dmu */	60	/* work to forward ROI to dmcu/dmub */
66	struct crc_fw_work {
67	struct work_struct forward_roi_work;	61	struct work_struct forward_roi_work;
68	struct amdgpu_display_manager *dm;	62
69	struct dc_stream_state *stream;	63	struct drm_crtc *crtc;
		64
		65	/* Region of Interest (ROI) */
70	struct rect rect;	66	struct rect rect;
71	bool is_stop_cmd;
72	};	67	};
73	#endif	68	#endif
74		69
@@ -100,11 +95,12 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc); · 25 unmodified lines
100	#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY	95	#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
101	bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc);	96	bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc);
102	void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc);	97	void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc);
103	struct crc_rd_work *amdgpu_dm_crtc_secure_display_create_work(void);	98	struct secure_display_context *amdgpu_dm_crtc_secure_display_create_contexts(
		99	struct amdgpu_device *adev);
104	#else	100	#else
105	#define amdgpu_dm_crc_window_is_activated(x)	101	#define amdgpu_dm_crc_window_is_activated(x)
106	#define amdgpu_dm_crtc_handle_crc_window_irq(x)	102	#define amdgpu_dm_crtc_handle_crc_window_irq(x)
107	#define amdgpu_dm_crtc_secure_display_create_work()	103	#define amdgpu_dm_crtc_secure_display_create_contexts()
108	#endif	104	#endif
109		105
110	#endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */	106	#endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c+24−86

 	for (i = 0; i < MAX_PIPES; i++) {
 		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
-		if (pipe_ctx && pipe_ctx->stream &&
+		if (pipe_ctx->stream &&
 		    pipe_ctx->stream->link == aconnector->dc_link)
 			break;
 	}
-	if (!pipe_ctx) {
-		kfree(rd_buf);
-		return -ENXIO;
-	}
 	dsc = pipe_ctx->stream_res.dsc;
 	if (dsc)
 		dsc->funcs->dsc_read_state(dsc, &dsc_state);
 	for (i = 0; i < MAX_PIPES; i++) {
 		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
-		if (pipe_ctx && pipe_ctx->stream &&
+		if (pipe_ctx->stream &&
 		    pipe_ctx->stream->link == aconnector->dc_link)
 			break;
 	}
-	if (!pipe_ctx || !pipe_ctx->stream)
+	if (!pipe_ctx->stream)
 		goto done;
 	// Get CRTC state
 	for (i = 0; i < MAX_PIPES; i++) {
 		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
-		if (pipe_ctx && pipe_ctx->stream &&
+		if (pipe_ctx->stream &&
 		    pipe_ctx->stream->link == aconnector->dc_link)
 			break;
 	}
-	if (!pipe_ctx) {
-		kfree(rd_buf);
-		return -ENXIO;
-	}
 	dsc = pipe_ctx->stream_res.dsc;
 	if (dsc)
 		dsc->funcs->dsc_read_state(dsc, &dsc_state);
 	for (i = 0; i < MAX_PIPES; i++) {
 		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
-		if (pipe_ctx && pipe_ctx->stream &&
+		if (pipe_ctx->stream &&
 		    pipe_ctx->stream->link == aconnector->dc_link)
 			break;
 	}
-	if (!pipe_ctx || !pipe_ctx->stream)
+	if (!pipe_ctx->stream)
 		goto done;
 	// Safely get CRTC state
 	for (i = 0; i < MAX_PIPES; i++) {
 		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
-		if (pipe_ctx && pipe_ctx->stream &&
+		if (pipe_ctx->stream &&
 		    pipe_ctx->stream->link == aconnector->dc_link)
 			break;
 	}
-	if (!pipe_ctx) {
-		kfree(rd_buf);
-		return -ENXIO;
-	}
 	dsc = pipe_ctx->stream_res.dsc;
 	if (dsc)
 		dsc->funcs->dsc_read_state(dsc, &dsc_state);
 	for (i = 0; i < MAX_PIPES; i++) {
 		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
-		if (pipe_ctx && pipe_ctx->stream &&
+		if (pipe_ctx->stream &&
 		    pipe_ctx->stream->link == aconnector->dc_link)
 			break;
 	}
-	if (!pipe_ctx || !pipe_ctx->stream)
+	if (!pipe_ctx->stream)
 		goto done;
 	// Get CRTC state
 	for (i = 0; i < MAX_PIPES; i++) {
 		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
-		if (pipe_ctx && pipe_ctx->stream &&
+		if (pipe_ctx->stream &&
 		    pipe_ctx->stream->link == aconnector->dc_link)
 			break;
 	}
-	if (!pipe_ctx) {
-		kfree(rd_buf);
-		return -ENXIO;
-	}
 	dsc = pipe_ctx->stream_res.dsc;
 	if (dsc)
 		dsc->funcs->dsc_read_state(dsc, &dsc_state);
 	for (i = 0; i < MAX_PIPES; i++) {
 		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
-		if (pipe_ctx && pipe_ctx->stream &&
+		if (pipe_ctx->stream &&
 		    pipe_ctx->stream->link == aconnector->dc_link)
 			break;
 	}
-	if (!pipe_ctx || !pipe_ctx->stream)
+	if (!pipe_ctx->stream)
 		goto done;
 	// Get CRTC state
 	for (i = 0; i < MAX_PIPES; i++) {
 		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
-		if (pipe_ctx && pipe_ctx->stream &&
+		if (pipe_ctx->stream &&
 		    pipe_ctx->stream->link == aconnector->dc_link)
 			break;
 	}
-	if (!pipe_ctx) {
-		kfree(rd_buf);
-		return -ENXIO;
-	}
 	dsc = pipe_ctx->stream_res.dsc;
 	if (dsc)
 		dsc->funcs->dsc_read_state(dsc, &dsc_state);
 	for (i = 0; i < MAX_PIPES; i++) {
 		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
-		if (pipe_ctx && pipe_ctx->stream &&
+		if (pipe_ctx->stream &&
 		    pipe_ctx->stream->link == aconnector->dc_link)
 			break;
 	}
-	if (!pipe_ctx) {
-		kfree(rd_buf);
-		return -ENXIO;
-	}
 	dsc = pipe_ctx->stream_res.dsc;
 	if (dsc)
 		dsc->funcs->dsc_read_state(dsc, &dsc_state);
 	for (i = 0; i < MAX_PIPES; i++) {
 		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
-		if (pipe_ctx && pipe_ctx->stream &&
+		if (pipe_ctx->stream &&
 		    pipe_ctx->stream->link == aconnector->dc_link)
 			break;
 	}
-	if (!pipe_ctx) {
-		kfree(rd_buf);
-		return -ENXIO;
-	}
 	dsc = pipe_ctx->stream_res.dsc;
 	if (dsc)
 		dsc->funcs->dsc_read_state(dsc, &dsc_state);
 	for (i = 0; i < MAX_PIPES; i++) {
 		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
-		if (pipe_ctx && pipe_ctx->stream &&
+		if (pipe_ctx->stream &&
 		    pipe_ctx->stream->link == aconnector->dc_link)
 			break;
 	}
-	if (!pipe_ctx) {
-		kfree(rd_buf);
-		return -ENXIO;
-	}
 	dsc = pipe_ctx->stream_res.dsc;
 	if (dsc)
 		dsc->funcs->dsc_read_state(dsc, &dsc_state);
  */
 static int crc_win_update_set(void *data, u64 val)
 {
-	struct drm_crtc *new_crtc = data;
+	struct drm_crtc *crtc = data;
-	struct drm_crtc *old_crtc = NULL;
+	struct amdgpu_crtc *acrtc;
-	struct amdgpu_crtc *new_acrtc, *old_acrtc;
+	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
-	struct amdgpu_device *adev = drm_to_adev(new_crtc->dev);
-	struct crc_rd_work *crc_rd_wrk = adev->dm.crc_rd_wrk;
-	if (!crc_rd_wrk)
-		return 0;
 	if (val) {
-		new_acrtc = to_amdgpu_crtc(new_crtc);
+		acrtc = to_amdgpu_crtc(crtc);
 		mutex_lock(&adev->dm.dc_lock);
 		/* PSR may write to OTG CRC window control register,
 		 * so close it before starting secure_display.
 		 */
-		amdgpu_dm_psr_disable(new_acrtc->dm_irq_params.stream);
+		amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream);
 		spin_lock_irq(&adev_to_drm(adev)->event_lock);
-		spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock);
-		if (crc_rd_wrk->crtc) {
-			old_crtc = crc_rd_wrk->crtc;
-			old_acrtc = to_amdgpu_crtc(old_crtc);
-		}
-		if (old_crtc && old_crtc != new_crtc) {
+		acrtc->dm_irq_params.window_param.activated = true;
-			old_acrtc->dm_irq_params.window_param.activated = false;
+		acrtc->dm_irq_params.window_param.update_win = true;
-			old_acrtc->dm_irq_params.window_param.update_win = false;
+		acrtc->dm_irq_params.window_param.skip_frame_cnt = 0;
-			old_acrtc->dm_irq_params.window_param.skip_frame_cnt = 0;
-			new_acrtc->dm_irq_params.window_param.activated = true;
-			new_acrtc->dm_irq_params.window_param.update_win = true;
-			new_acrtc->dm_irq_params.window_param.skip_frame_cnt = 0;
-			crc_rd_wrk->crtc = new_crtc;
-		} else {
-			new_acrtc->dm_irq_params.window_param.activated = true;
-			new_acrtc->dm_irq_params.window_param.update_win = true;
-			new_acrtc->dm_irq_params.window_param.skip_frame_cnt = 0;
-			crc_rd_wrk->crtc = new_crtc;
-		}
-		spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock);
 		spin_unlock_irq(&adev_to_drm(adev)->event_lock);
 		mutex_unlock(&adev->dm.dc_lock);
 	}

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h+14−0

@@ -52,6 +52,20 @@ struct hdcp_workqueue { · 51 unmodified lines
52	struct mod_hdcp_link link;	52	struct mod_hdcp_link link;
53		53
54	enum mod_hdcp_encryption_status encryption_status;	54	enum mod_hdcp_encryption_status encryption_status;
		55
		56	/* when display is unplugged from mst hub, connctor will be
		57	* destroyed within dm_dp_mst_connector_destroy. connector
		58	* hdcp perperties, like type, undesired, desired, enabled,
		59	* will be lost. So, save hdcp properties into hdcp_work within
		60	* amdgpu_dm_atomic_commit_tail. if the same display is
		61	* plugged back with same display index, its hdcp properties
		62	* will be retrieved from hdcp_work within dm_dp_mst_get_modes
		63	*/
		64	/* un-desired, desired, enabled */
		65	unsigned int content_protection[AMDGPU_DM_MAX_DISPLAY_INDEX];
		66	/* hdcp1.x, hdcp2.x */
		67	unsigned int hdcp_content_type[AMDGPU_DM_MAX_DISPLAY_INDEX];
		68
55	uint8_t max_link;	69	uint8_t max_link;
56		70
57	uint8_t *srm;	71	uint8_t *srm;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c+26−0

@@ -32,6 +32,10 @@ · 31 unmodified lines
32	#include "amdgpu_dm.h"	32	#include "amdgpu_dm.h"
33	#include "amdgpu_dm_mst_types.h"	33	#include "amdgpu_dm_mst_types.h"
34		34
		35	#ifdef CONFIG_DRM_AMD_DC_HDCP
		36	#include "amdgpu_dm_hdcp.h"
		37	#endif
		38
35	#include "dc.h"	39	#include "dc.h"
36	#include "dm_helpers.h"	40	#include "dm_helpers.h"
37		41
@@ -344,6 +348,28 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) · 306 unmodified lines
344	/* dc_link_add_remote_sink returns a new reference */	348	/* dc_link_add_remote_sink returns a new reference */
345	aconnector->dc_sink = dc_sink;	349	aconnector->dc_sink = dc_sink;
346		350
		351	/* when display is unplugged from mst hub, connctor will be
		352	* destroyed within dm_dp_mst_connector_destroy. connector
		353	* hdcp perperties, like type, undesired, desired, enabled,
		354	* will be lost. So, save hdcp properties into hdcp_work within
		355	* amdgpu_dm_atomic_commit_tail. if the same display is
		356	* plugged back with same display index, its hdcp properties
		357	* will be retrieved from hdcp_work within dm_dp_mst_get_modes
		358	*/
		359	#ifdef CONFIG_DRM_AMD_DC_HDCP
		360	if (aconnector->dc_sink && connector->state) {
		361	struct drm_device *dev = connector->dev;
		362	struct amdgpu_device *adev = drm_to_adev(dev);
		363	struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
		364	struct hdcp_workqueue *hdcp_w = &hdcp_work[aconnector->dc_link->link_index];
		365
		366	connector->state->hdcp_content_type =
		367	hdcp_w->hdcp_content_type[connector->index];
		368	connector->state->content_protection =
		369	hdcp_w->content_protection[connector->index];
		370	}
		371	#endif
		372
347	if (aconnector->dc_sink) {	373	if (aconnector->dc_sink) {
348	amdgpu_dm_update_freesync_caps(	374	amdgpu_dm_update_freesync_caps(
349	connector, aconnector->edid);	375	connector, aconnector->edid);

drivers/gpu/drm/amd/display/dc/core/dc.c+54−52

 }
 /**
- *  dc_stream_adjust_vmin_vmax:
+ *  dc_stream_adjust_vmin_vmax - look up pipe context & update parts of DRR
+ *  @dc:     dc reference
+ *  @stream: Initial dc stream state
+ *  @adjust: Updated parameters for vertical_total_min and vertical_total_max
  *
  *  Looks up the pipe context of dc_stream_state and updates the
  *  vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
  *  Rate, which is a power-saving feature that targets reducing panel
  *  refresh rate while the screen is static
  *
- *  @dc:     dc reference
+ *  Return: %true if the pipe context is found and adjusted;
- *  @stream: Initial dc stream state
+ *          %false if the pipe context is not found.
- *  @adjust: Updated parameters for vertical_total_min and vertical_total_max
  */
 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 		struct dc_stream_state *stream,
 }
 /**
- * dc_stream_get_last_used_drr_vtotal - dc_stream_get_last_vrr_vtotal
+ * dc_stream_get_last_used_drr_vtotal - Looks up the pipe context of
+ * dc_stream_state and gets the last VTOTAL used by DRR (Dynamic Refresh Rate)
  *
  * @dc: [in] dc reference
  * @stream: [in] Initial dc stream state
- * @adjust: [in] Updated parameters for vertical_total_min and
+ * @refresh_rate: [in] new refresh_rate
  *
- * Looks up the pipe context of dc_stream_state and gets the last VTOTAL used
+ * Return: %true if the pipe context is found and there is an associated
- * by DRR (Dynamic Refresh Rate)
+ *         timing_generator for the DC;
+ *         %false if the pipe context is not found or there is no
+ *         timing_generator for the DC.
  */
 bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,
 		struct dc_stream_state *stream,
 }
 bool
-dc_stream_forward_crc_window(struct dc *dc,
+dc_stream_forward_crc_window(struct dc_stream_state *stream,
-		struct rect *rect, struct dc_stream_state *stream, bool is_stop)
+		struct rect *rect, bool is_stop)
 {
 	struct dmcu *dmcu;
 	struct dc_dmub_srv *dmub_srv;
 	struct otg_phy_mux mux_mapping;
 	struct pipe_ctx *pipe;
 	int i;
+	struct dc *dc = stream->ctx->dc;
 	for (i = 0; i < MAX_PIPES; i++) {
 		pipe = &dc->current_state->res_ctx.pipe_ctx[i];
  *              once.
  *
  * By default, only CRC0 is configured, and the entire frame is used to
- * calculate the crc.
+ * calculate the CRC.
+ *
+ * Return: %false if the stream is not found or CRC capture is not supported;
+ *         %true if the stream has been configured.
  */
 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 			     struct crc_params *crc_window, bool enable, bool continuous)
  * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
  *
  * Return:
- * false if stream is not found, or if CRCs are not enabled.
+ * %false if stream is not found, or if CRCs are not enabled.
  */
 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
 		       uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
  *
  * Applies given context to the hardware and copy it into current context.
  * It's up to the user to release the src context afterwards.
+ *
+ * Return: an enum dc_status result code for the operation
  */
 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
 {
 		return result == DC_OK;
 	}
-	if (!streams_changed(dc, context->streams, context->stream_count))
+	if (!streams_changed(dc, context->streams, context->stream_count)) {
 		return DC_OK;
+	}
 	DC_LOG_DC("%s: %d streams\n",
 				__func__, context->stream_count);
 	struct pipe_ctx *top_pipe_to_program = NULL;
 	bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST);
 	bool subvp_prev_use = false;
+	bool subvp_curr_use = false;
 	// Once we apply the new subvp context to hardware it won't be in the
 	// dc->current_state anymore, so we have to cache it before we apply
 			break;
 	}
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
+			subvp_curr_use = true;
+			break;
+		}
+	}
 	if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
 		struct pipe_ctx *mpcc_pipe;
 		struct pipe_ctx *odm_pipe;
 					top_pipe_to_program->stream_res.tg);
 		}
-	/* For phantom pipe OTG enable, it has to be done after any previous pipe
+	if (subvp_curr_use) {
-	 * that was in use has already been programmed at gotten its double buffer
+		/* If enabling subvp or transitioning from subvp->subvp, enable the
-	 * update for "disable".
+		 * phantom streams before we program front end for the phantom pipes.
-	 */
+		 */
-	if (update_type != UPDATE_TYPE_FAST) {
+		if (update_type != UPDATE_TYPE_FAST) {
-		for (i = 0; i < dc->res_pool->pipe_count; i++) {
+			if (dc->hwss.enable_phantom_streams)
-			struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+				dc->hwss.enable_phantom_streams(dc, context);
-			struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
-			/* If an active, non-phantom pipe is being transitioned into a phantom
-			 * pipe, wait for the double buffer update to complete first before we do
-			 * ANY phantom pipe programming.
-			 */
-			if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM &&
-					old_pipe->stream && old_pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) {
-				old_pipe->stream_res.tg->funcs->wait_for_state(
-						old_pipe->stream_res.tg,
-						CRTC_STATE_VBLANK);
-				old_pipe->stream_res.tg->funcs->wait_for_state(
-						old_pipe->stream_res.tg,
-						CRTC_STATE_VACTIVE);
-			}
 		}
-		for (i = 0; i < dc->res_pool->pipe_count; i++) {
+	}
-			struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
-			if ((new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) ||
+	if (subvp_prev_use && !subvp_curr_use) {
-					subvp_prev_use) {
+		/* If disabling subvp, disable phantom streams after front end
-				// If old context or new context has phantom pipes, apply
+		 * programming has completed (we turn on phantom OTG in order
-				// the phantom timings now. We can't change the phantom
+		 * to complete the plane disable for phantom pipes).
-				// pipe configuration safely without driver acquiring
+		 */
-				// the DMCUB lock first.
+		dc->hwss.apply_ctx_to_hw(dc, context);
-				dc->hwss.apply_ctx_to_hw(dc, context);
-				break;
-			}
-		}
 	}
 	if (update_type != UPDATE_TYPE_FAST)
 /**
  * dc_enable_dmub_outbox - Enables DMUB unsolicited notification
  *
- * dc: [in] dc structure
+ * @dc: [in] dc structure
  *
  * Enables DMUB unsolicited notifications to x86 via outbox.
  */
 /**
  * dc_process_dmub_dpia_hpd_int_enable - Submits DPIA DPD interruption
  *
- * @dc [in]: dc structure
+ * @dc: [in] dc structure
- * @hpd_int_enable [in]: 1 for hpd int enable, 0 to disable
+ * @hpd_int_enable: [in] 1 for hpd int enable, 0 to disable
  *
  * Submits dpia hpd int enable command to dmub via inbox message
  */
 }
 /**
- * dc_extended_blank_supported 0 Decide whether extended blank is supported
+ * dc_extended_blank_supported - Decide whether extended blank is supported
  *
  * @dc: [in] Current DC state
  *
  * ability to enter z9/z10.
  *
  * Return:
- * Indicate whether extended blank is supported (true or false)
+ * Indicate whether extended blank is supported (%true or %false)
  */
 bool dc_extended_blank_supported(struct dc *dc)
 {

drivers/gpu/drm/amd/display/dc/core/dc_link.c+0−9

 	if (false == dc_link_construct(link, init_params))
 		goto construct_fail;
-	/*
-	 * Must use preferred_link_setting, not reported_link_cap or verified_link_cap,
-	 * since struct preferred_link_setting won't be reset after S3.
-	 */
-	link->preferred_link_setting.dpcd_source_device_specific_field_support = true;
 	return link;
 construct_fail:
 	if (link_setting != NULL) {
 		link->preferred_link_setting = *link_setting;
-		if (dp_get_link_encoding_format(link_setting) == DP_128b_132b_ENCODING)
-			/* TODO: add dc update for acquiring link res  */
-			skip_immediate_retrain = true;
 	} else {
 		link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
 		link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;

drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c+0−1

@@ -82,7 +82,6 @@ struct dp_hdmi_dongle_signature_data { · 81 unmodified lines
82	#define HDMI_SCDC_STATUS_FLAGS 0x40	82	#define HDMI_SCDC_STATUS_FLAGS 0x40
83	#define HDMI_SCDC_ERR_DETECT 0x50	83	#define HDMI_SCDC_ERR_DETECT 0x50
84	#define HDMI_SCDC_TEST_CONFIG 0xC0	84	#define HDMI_SCDC_TEST_CONFIG 0xC0
85	#define HDMI_SCDC_DEVICE_ID 0xD3
86		85
87	union hdmi_scdc_update_read_data {	86	union hdmi_scdc_update_read_data {
88	uint8_t byte[2];	87	uint8_t byte[2];

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c+67−70

@@ -4094,6 +4094,12 @@ static void dp_test_send_link_training(struct dc_link *link) · 4093 unmodified lines
4094	dp_retrain_link_dp_test(link, &link_settings, false);	4094	dp_retrain_link_dp_test(link, &link_settings, false);
4095	}	4095	}
4096		4096
		4097	static bool is_dp_phy_sqaure_pattern(enum dp_test_pattern test_pattern)
		4098	{
		4099	return (DP_TEST_PATTERN_SQUARE_BEGIN <= test_pattern &&
		4100	test_pattern <= DP_TEST_PATTERN_SQUARE_END);
		4101	}
		4102
4097	/* TODO Raven hbr2 compliance eye output is unstable	4103	/* TODO Raven hbr2 compliance eye output is unstable
4098	* (toggling on and off) with debugger break	4104	* (toggling on and off) with debugger break
4099	* This caueses intermittent PHY automation failure	4105	* This caueses intermittent PHY automation failure
@@ -4111,6 +4117,8 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link) · 11 unmodified lines
4111	union lane_adjust dpcd_lane_adjust;	4117	union lane_adjust dpcd_lane_adjust;
4112	unsigned int lane;	4118	unsigned int lane;
4113	struct link_training_settings link_training_settings;	4119	struct link_training_settings link_training_settings;
		4120	unsigned char no_preshoot = 0;
		4121	unsigned char no_deemphasis = 0;
4114		4122
4115	dpcd_test_pattern.raw = 0;	4123	dpcd_test_pattern.raw = 0;
4116	memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));	4124	memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
@@ -4204,8 +4212,21 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link) · 87 unmodified lines
4204	case PHY_TEST_PATTERN_264BIT_CUSTOM:	4212	case PHY_TEST_PATTERN_264BIT_CUSTOM:
4205	test_pattern = DP_TEST_PATTERN_264BIT_CUSTOM;	4213	test_pattern = DP_TEST_PATTERN_264BIT_CUSTOM;
4206	break;	4214	break;
4207	case PHY_TEST_PATTERN_SQUARE_PULSE:	4215	case PHY_TEST_PATTERN_SQUARE:
4208	test_pattern = DP_TEST_PATTERN_SQUARE_PULSE;	4216	test_pattern = DP_TEST_PATTERN_SQUARE;
		4217	break;
		4218	case PHY_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED:
		4219	test_pattern = DP_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED;
		4220	no_preshoot = 1;
		4221	break;
		4222	case PHY_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED:
		4223	test_pattern = DP_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED;
		4224	no_deemphasis = 1;
		4225	break;
		4226	case PHY_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED:
		4227	test_pattern = DP_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED;
		4228	no_preshoot = 1;
		4229	no_deemphasis = 1;
4209	break;	4230	break;
4210	default:	4231	default:
4211	test_pattern = DP_TEST_PATTERN_VIDEO_MODE;	4232	test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
@@ -4222,7 +4243,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link) · 10 unmodified lines
4222	test_pattern_size);	4243	test_pattern_size);
4223	}	4244	}
4224		4245
4225	if (test_pattern == DP_TEST_PATTERN_SQUARE_PULSE) {	4246	if (is_dp_phy_sqaure_pattern(test_pattern)) {
4226	test_pattern_size = 1; // Square pattern data is 1 byte (DP spec)	4247	test_pattern_size = 1; // Square pattern data is 1 byte (DP spec)
4227	core_link_read_dpcd(	4248	core_link_read_dpcd(
4228	link,	4249	link,
@@ -4259,8 +4280,10 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link) · 30 unmodified lines
4259	((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);	4280	((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
4260	} else if (dp_get_link_encoding_format(&link->cur_link_settings) ==	4281	} else if (dp_get_link_encoding_format(&link->cur_link_settings) ==
4261	DP_128b_132b_ENCODING) {	4282	DP_128b_132b_ENCODING) {
4262	link_training_settings.hw_lane_settings[lane].FFE_PRESET.raw =	4283	link_training_settings.hw_lane_settings[lane].FFE_PRESET.settings.level =
4263	dpcd_lane_adjust.tx_ffe.PRESET_VALUE;	4284	dpcd_lane_adjust.tx_ffe.PRESET_VALUE;
		4285	link_training_settings.hw_lane_settings[lane].FFE_PRESET.settings.no_preshoot = no_preshoot;
		4286	link_training_settings.hw_lane_settings[lane].FFE_PRESET.settings.no_deemphasis = no_deemphasis;
4264	}	4287	}
4265	}	4288	}
4266		4289
@@ -6114,7 +6137,7 @@ bool dc_link_dp_set_test_pattern( · 1847 unmodified lines
6114	* MuteAudioEndpoint(pPathMode->pDisplayPath, true);	6137	* MuteAudioEndpoint(pPathMode->pDisplayPath, true);
6115	*/	6138	*/
6116	/* Blank stream */	6139	/* Blank stream */
6117	pipes->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc);	6140	link->dc->hwss.blank_stream(pipe_ctx);
6118	}	6141	}
6119		6142
6120	dp_set_hw_test_pattern(link, &pipe_ctx->link_res, test_pattern,	6143	dp_set_hw_test_pattern(link, &pipe_ctx->link_res, test_pattern,
@@ -6178,8 +6201,17 @@ bool dc_link_dp_set_test_pattern( · 57 unmodified lines
6178	case DP_TEST_PATTERN_264BIT_CUSTOM:	6201	case DP_TEST_PATTERN_264BIT_CUSTOM:
6179	pattern = PHY_TEST_PATTERN_264BIT_CUSTOM;	6202	pattern = PHY_TEST_PATTERN_264BIT_CUSTOM;
6180	break;	6203	break;
6181	case DP_TEST_PATTERN_SQUARE_PULSE:	6204	case DP_TEST_PATTERN_SQUARE:
6182	pattern = PHY_TEST_PATTERN_SQUARE_PULSE;	6205	pattern = PHY_TEST_PATTERN_SQUARE;
		6206	break;
		6207	case DP_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED:
		6208	pattern = PHY_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED;
		6209	break;
		6210	case DP_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED:
		6211	pattern = PHY_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED;
		6212	break;
		6213	case DP_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED:
		6214	pattern = PHY_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED;
6183	break;	6215	break;
6184	default:	6216	default:
6185	return false;	6217	return false;
@@ -6190,14 +6222,12 @@ bool dc_link_dp_set_test_pattern( · 4 unmodified lines
6190	return false;	6222	return false;
6191		6223
6192	if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {	6224	if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
6193	#if defined(CONFIG_DRM_AMD_DC_DCN)	6225	if (is_dp_phy_sqaure_pattern(test_pattern))
6194	if (test_pattern == DP_TEST_PATTERN_SQUARE_PULSE)
6195	core_link_write_dpcd(link,	6226	core_link_write_dpcd(link,
6196	DP_LINK_SQUARE_PATTERN,	6227	DP_LINK_SQUARE_PATTERN,
6197	p_custom_pattern,	6228	p_custom_pattern,
6198	1);	6229	1);
6199		6230
6200	#endif
6201	/* tell receiver that we are sending qualification	6231	/* tell receiver that we are sending qualification
6202	* pattern DP 1.2 or later - DP receiver's link quality	6232	* pattern DP 1.2 or later - DP receiver's link quality
6203	* pattern is set using DPCD LINK_QUAL_LANEx_SET	6233	* pattern is set using DPCD LINK_QUAL_LANEx_SET
@@ -6554,18 +6584,10 @@ void dpcd_set_source_specific_data(struct dc_link *link) · 350 unmodified lines
6554		6584
6555	uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;	6585	uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
6556		6586
6557	if (link->preferred_link_setting.dpcd_source_device_specific_field_support) {	6587	result_write_min_hblank = core_link_write_dpcd(link,
6558	result_write_min_hblank = core_link_write_dpcd(link,	6588	DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
6559	DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),	6589	sizeof(hblank_size));
6560	sizeof(hblank_size));
6561
6562	if (result_write_min_hblank == DC_ERROR_UNEXPECTED)
6563	link->preferred_link_setting.dpcd_source_device_specific_field_support = false;
6564	} else {
6565	DC_LOG_DC("Sink device does not support 00340h DPCD write. Skipping on purpose.\n");
6566	}
6567	}	6590	}
6568
6569	DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,	6591	DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
6570	WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,	6592	WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
6571	"result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",	6593	"result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
@@ -7254,59 +7276,35 @@ void dp_retrain_link_dp_test(struct dc_link *link, · 682 unmodified lines
7254	struct dc_link_settings *link_setting,	7276	struct dc_link_settings *link_setting,
7255	bool skip_video_pattern)	7277	bool skip_video_pattern)
7256	{	7278	{
7257	struct pipe_ctx *pipes =	7279	struct pipe_ctx *pipe;
7258	&link->dc->current_state->res_ctx.pipe_ctx[0];
7259	unsigned int i;	7280	unsigned int i;
7260	bool do_fallback = false;
7261		7281
		7282	udelay(100);
7262		7283
7263	for (i = 0; i < MAX_PIPES; i++) {	7284	for (i = 0; i < MAX_PIPES; i++) {
7264	if (pipes[i].stream != NULL &&	7285	pipe = &link->dc->current_state->res_ctx.pipe_ctx[i];
7265	!pipes[i].top_pipe && !pipes[i].prev_odm_pipe &&	7286	if (pipe->stream != NULL &&
7266	pipes[i].stream->link != NULL &&	7287	pipe->stream->link == link &&
7267	pipes[i].stream_res.stream_enc != NULL &&	7288	!pipe->stream->dpms_off &&
7268	pipes[i].stream->link == link) {	7289	!pipe->top_pipe && !pipe->prev_odm_pipe) {
7269	udelay(100);	7290	core_link_disable_stream(pipe);
7270		7291	pipe->link_config.dp_link_settings = *link_setting;
7271	pipes[i].stream_res.stream_enc->funcs->dp_blank(link,	7292	update_dp_encoder_resources_for_test_harness(
7272	pipes[i].stream_res.stream_enc);	7293	link->dc,
7273		7294	pipe->stream->ctx->dc->current_state,
7274	/* disable any test pattern that might be active */	7295	pipe);
7275	dp_set_hw_test_pattern(link, &pipes[i].link_res,	7296	}
7276	DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);	7297	}
7277
7278	dp_receiver_power_ctrl(link, false);
7279
7280	link->dc->hwss.disable_stream(&pipes[i]);
7281	if ((&pipes[i])->stream_res.audio && !link->dc->debug.az_endpoint_mute_only)
7282	(&pipes[i])->stream_res.audio->funcs->az_disable((&pipes[i])->stream_res.audio);
7283
7284	if (link->link_enc)
7285	link->link_enc->funcs->disable_output(
7286	link->link_enc,
7287	SIGNAL_TYPE_DISPLAY_PORT);
7288
7289	/* Clear current link setting. */
7290	memset(&link->cur_link_settings, 0,
7291	sizeof(link->cur_link_settings));
7292
7293	if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
7294	do_fallback = true;
7295
7296	perform_link_training_with_retries(
7297	link_setting,
7298	skip_video_pattern,
7299	LINK_TRAINING_ATTEMPTS,
7300	&pipes[i],
7301	SIGNAL_TYPE_DISPLAY_PORT,
7302	do_fallback);
7303
7304	link->dc->hwss.enable_stream(&pipes[i]);
7305
7306	link->dc->hwss.unblank_stream(&pipes[i],
7307	link_setting);
7308		7298
7309	link->dc->hwss.enable_audio_stream(&pipes[i]);	7299	for (i = 0; i < MAX_PIPES; i++) {
		7300	pipe = &link->dc->current_state->res_ctx.pipe_ctx[i];
		7301	if (pipe->stream != NULL &&
		7302	pipe->stream->link == link &&
		7303	!pipe->stream->dpms_off &&
		7304	!pipe->top_pipe && !pipe->prev_odm_pipe) {
		7305	core_link_enable_stream(
		7306	pipe->stream->ctx->dc->current_state,
		7307	pipe);
7310	}	7308	}
7311	}	7309	}
7312	}	7310	}
@@ -7496,7 +7494,6 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_u · 183 unmodified lines
7496	dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;	7494	dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
7497	dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;	7495	dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
7498		7496
7499	DC_LOG_DSC(" ");
7500	dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]);	7497	dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]);
7501	memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps));	7498	memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps));
7502	if (dc_is_dp_signal(stream->signal)) {	7499	if (dc_is_dp_signal(stream->signal)) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c+51−3

@@ -3810,6 +3810,8 @@ void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc, · 3809 unmodified lines
3810	int i;	3810	int i;
3811	struct pipe_ctx pipe_ctx, pipe_ctx_check;	3811	struct pipe_ctx pipe_ctx, pipe_ctx_check;
3812		3812
		3813	DC_LOGGER_INIT(dc->ctx->logger);
		3814
3813	pipe_ctx = &context->res_ctx.pipe_ctx[disabled_master_pipe_idx];	3815	pipe_ctx = &context->res_ctx.pipe_ctx[disabled_master_pipe_idx];
3814	if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx) != disabled_master_pipe_idx) \|\|	3816	if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx) != disabled_master_pipe_idx) \|\|
3815	!IS_PIPE_SYNCD_VALID(pipe_ctx))	3817	!IS_PIPE_SYNCD_VALID(pipe_ctx))
@@ -3820,9 +3822,16 @@ void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc, · 4 unmodified lines
3820	pipe_ctx_check = &context->res_ctx.pipe_ctx[i];	3822	pipe_ctx_check = &context->res_ctx.pipe_ctx[i];
3821		3823
3822	if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_check) == disabled_master_pipe_idx) &&	3824	if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_check) == disabled_master_pipe_idx) &&
3823	IS_PIPE_SYNCD_VALID(pipe_ctx_check) && (i != disabled_master_pipe_idx))	3825	IS_PIPE_SYNCD_VALID(pipe_ctx_check) && (i != disabled_master_pipe_idx)) {
3824	DC_ERR("DC: Failure: pipe_idx[%d] syncd with disabled master pipe_idx[%d]\n",	3826	/* On dcn32, this error isn't fatal since hw supports odm transition in fast update*/
3825	i, disabled_master_pipe_idx);	3827	if (dc->ctx->dce_version == DCN_VERSION_3_2 \|\|
		3828	dc->ctx->dce_version == DCN_VERSION_3_21)
		3829	DC_LOG_DEBUG("DC: pipe_idx[%d] syncd with disabled master pipe_idx[%d]\n",
		3830	i, disabled_master_pipe_idx);
		3831	else
		3832	DC_ERR("DC: Failure: pipe_idx[%d] syncd with disabled master pipe_idx[%d]\n",
		3833	i, disabled_master_pipe_idx);
		3834	}
3826	}	3835	}
3827	}	3836	}
3828		3837
@@ -3981,3 +3990,42 @@ bool dc_resource_acquire_secondary_pipe_for_mpc_odm( · 152 unmodified lines
3981		3990
3982	return true;	3991	return true;
3983	}	3992	}
		3993
		3994	enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc,
		3995	struct dc_state *context,
		3996	struct pipe_ctx *pipe_ctx)
		3997	{
		3998	if (dp_get_link_encoding_format(&pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {
		3999	if (pipe_ctx->stream_res.hpo_dp_stream_enc == NULL) {
		4000	pipe_ctx->stream_res.hpo_dp_stream_enc =
		4001	find_first_free_match_hpo_dp_stream_enc_for_link(
		4002	&context->res_ctx, dc->res_pool, pipe_ctx->stream);
		4003
		4004	if (!pipe_ctx->stream_res.hpo_dp_stream_enc)
		4005	return DC_NO_STREAM_ENC_RESOURCE;
		4006
		4007	update_hpo_dp_stream_engine_usage(
		4008	&context->res_ctx, dc->res_pool,
		4009	pipe_ctx->stream_res.hpo_dp_stream_enc,
		4010	true);
		4011	}
		4012
		4013	if (pipe_ctx->link_res.hpo_dp_link_enc == NULL) {
		4014	if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, dc->res_pool, pipe_ctx, pipe_ctx->stream))
		4015	return DC_NO_LINK_ENC_RESOURCE;
		4016	}
		4017	} else {
		4018	if (pipe_ctx->stream_res.hpo_dp_stream_enc) {
		4019	update_hpo_dp_stream_engine_usage(
		4020	&context->res_ctx, dc->res_pool,
		4021	pipe_ctx->stream_res.hpo_dp_stream_enc,
		4022	false);
		4023	pipe_ctx->stream_res.hpo_dp_stream_enc = NULL;
		4024	}
		4025	if (pipe_ctx->link_res.hpo_dp_link_enc)
		4026	remove_hpo_dp_link_enc_from_ctx(&context->res_ctx, pipe_ctx, pipe_ctx->stream);
		4027	}
		4028
		4029	return DC_OK;
		4030	}
		4031

drivers/gpu/drm/amd/display/dc/core/dc_stat.c+1−0

@@ -65,6 +65,7 @@ void dc_stat_get_dmub_notification(const struct dc *dc, struct dmub_notification · 64 unmodified lines
65	/* For HPD/HPD RX, convert dpia port index into link index */	65	/* For HPD/HPD RX, convert dpia port index into link index */
66	if (notify->type == DMUB_NOTIFICATION_HPD \|\|	66	if (notify->type == DMUB_NOTIFICATION_HPD \|\|
67	notify->type == DMUB_NOTIFICATION_HPD_IRQ \|\|	67	notify->type == DMUB_NOTIFICATION_HPD_IRQ \|\|
		68	notify->type == DMUB_NOTIFICATION_DPIA_NOTIFICATION \|\|
68	notify->type == DMUB_NOTIFICATION_SET_CONFIG_REPLY) {	69	notify->type == DMUB_NOTIFICATION_SET_CONFIG_REPLY) {
69	notify->link_index =	70	notify->link_index =
70	get_link_index_from_dpia_port_index(dc, notify->link_index);	71	get_link_index_from_dpia_port_index(dc, notify->link_index);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c+8−1

 	}
 	if (!isDrc) {
+		ASSERT(stream->num_wb_info + 1 <= MAX_DWB_PIPES);
 		stream->writeback_info[stream->num_wb_info++] = *wb_info;
 	}
 		return false;
 	}
+	if (stream->num_wb_info > MAX_DWB_PIPES) {
+		dm_error("DC: num_wb_info is invalid!\n");
+		return false;
+	}
 //	stream->writeback_info[dwb_pipe_inst].wb_enabled = false;
 	for (i = 0; i < stream->num_wb_info; i++) {
 		/*dynamic update*/
 		if (stream->writeback_info[i].wb_enabled) {
 			if (j < i)
 				/* trim the array */
-				stream->writeback_info[j] = stream->writeback_info[i];
+				memcpy(&stream->writeback_info[j], &stream->writeback_info[i],
+						sizeof(struct dc_writeback_info));
 			j++;
 		}
 	}

drivers/gpu/drm/amd/display/dc/dc.h+2−1

 struct set_config_cmd_payload;
 struct dmub_notification;
-#define DC_VER "3.2.215"
+#define DC_VER "3.2.217"
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
 	enum lttpr_mode lttpr_mode_override;
 	unsigned int dsc_delay_factor_wa_x1000;
 	unsigned int min_prefetch_in_strobe_ns;
+	bool disable_unbounded_requesting;
 };
 struct gpu_info_soc_bounding_box_v1_0;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h+3−1

 	enum dc_link_spread link_spread;
 	bool use_link_rate_set;
 	uint8_t link_rate_set;
-	bool dpcd_source_device_specific_field_support;
 };
 union dc_dp_ffe_preset {
 #ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL
 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL		0x2216
 #endif
+#ifndef DP_LINK_SQUARE_PATTERN
+#define DP_LINK_SQUARE_PATTERN				0x10F
+#endif
 #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX
 #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX		0x2217
 #endif

drivers/gpu/drm/amd/display/dc/dc_link.h+9−6

 		unsigned int *inst_out)
 {
 	struct dc_link *edp_links[MAX_NUM_EDP];
-	int edp_num;
+	int edp_num, i;
-	if (link->connector_signal != SIGNAL_TYPE_EDP)
+	*inst_out = 0;
+	if (link->connector_signal != SIGNAL_TYPE_EDP || !link->local_sink)
 		return false;
 	get_edp_links(dc, edp_links, &edp_num);
-	if ((edp_num > 1) && (link->link_index > edp_links[0]->link_index))
+	for (i = 0; i < edp_num; i++) {
-		*inst_out = 1;
+		if (link == edp_links[i])
-	else
+			break;
-		*inst_out = 0;
+		if (edp_links[i]->local_sink)
+			(*inst_out)++;
+	}
 	return true;
 }

drivers/gpu/drm/amd/display/dc/dc_stream.h+1−2

@@ -543,9 +543,8 @@ bool dc_stream_get_crtc_position(struct dc *dc, · 542 unmodified lines
543	unsigned int *nom_v_pos);	543	unsigned int *nom_v_pos);
544		544
545	#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)	545	#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
546	bool dc_stream_forward_crc_window(struct dc *dc,	546	bool dc_stream_forward_crc_window(struct dc_stream_state *stream,
547	struct rect *rect,	547	struct rect *rect,
548	struct dc_stream_state *stream,
549	bool is_stop);	548	bool is_stop);
550	#endif	549	#endif
551		550

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c+13−0

@@ -1142,6 +1142,10 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) · 1141 unmodified lines
1142	struct dc_link *link = stream->link;	1142	struct dc_link *link = stream->link;
1143	struct dc *dc = pipe_ctx->stream->ctx->dc;	1143	struct dc *dc = pipe_ctx->stream->ctx->dc;
1144	const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);	1144	const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
		1145	struct dccg *dccg = dc->res_pool->dccg;
		1146	struct timing_generator *tg = pipe_ctx->stream_res.tg;
		1147	struct dtbclk_dto_params dto_params = {0};
		1148	int dp_hpo_inst;
1145		1149
1146	if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {	1150	if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {
1147	pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(	1151	pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
@@ -1161,6 +1165,15 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) · 13 unmodified lines
1161		1165
1162	link_hwss->reset_stream_encoder(pipe_ctx);	1166	link_hwss->reset_stream_encoder(pipe_ctx);
1163		1167
		1168	if (is_dp_128b_132b_signal(pipe_ctx)) {
		1169	dto_params.otg_inst = tg->inst;
		1170	dto_params.timing = &pipe_ctx->stream->timing;
		1171	dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
		1172	dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
		1173	dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);
		1174	dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);
		1175	}
		1176
1164	if (is_dp_128b_132b_signal(pipe_ctx)) {	1177	if (is_dp_128b_132b_signal(pipe_ctx)) {
1165	/* TODO: This looks like a bug to me as we are disabling HPO IO when	1178	/* TODO: This looks like a bug to me as we are disabling HPO IO when
1166	* we are just disabling a single HPO stream. Shouldn't we disable HPO	1179	* we are just disabling a single HPO stream. Shouldn't we disable HPO

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c+0−1

@@ -200,7 +200,6 @@ static void dsc2_set_config(struct display_stream_compressor *dsc, const struct · 199 unmodified lines
200	bool is_config_ok;	200	bool is_config_ok;
201	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);	201	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
202		202
203	DC_LOG_DSC(" ");
204	DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);	203	DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);
205	dsc_config_log(dsc, dsc_cfg);	204	dsc_config_log(dsc, dsc_cfg);
206	is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg);	205	is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c+86−0

@@ -582,6 +582,9 @@ void dcn20_plane_atomic_disable(struct dc dc, struct pipe_ctx pipe_ctx) · 581 unmodified lines
582	if (pipe_ctx->stream_res.gsl_group != 0)	582	if (pipe_ctx->stream_res.gsl_group != 0)
583	dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);	583	dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
584		584
		585	if (hubp->funcs->hubp_update_mall_sel)
		586	hubp->funcs->hubp_update_mall_sel(hubp, 0, false);
		587
585	dc->hwss.set_flip_control_gsl(pipe_ctx, false);	588	dc->hwss.set_flip_control_gsl(pipe_ctx, false);
586		589
587	hubp->funcs->hubp_clk_cntl(hubp, false);	590	hubp->funcs->hubp_clk_cntl(hubp, false);
@@ -605,6 +608,9 @@ void dcn20_plane_atomic_disable(struct dc dc, struct pipe_ctx pipe_ctx) · 17 unmodified lines
605		608
606	void dcn20_disable_plane(struct dc dc, struct pipe_ctx pipe_ctx)	609	void dcn20_disable_plane(struct dc dc, struct pipe_ctx pipe_ctx)
607	{	610	{
		611	bool is_phantom = pipe_ctx->plane_state && pipe_ctx->plane_state->is_phantom;
		612	struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL;
		613
608	DC_LOGGER_INIT(dc->ctx->logger);	614	DC_LOGGER_INIT(dc->ctx->logger);
609		615
610	if (!pipe_ctx->plane_res.hubp \|\| pipe_ctx->plane_res.hubp->power_gated)	616	if (!pipe_ctx->plane_res.hubp \|\| pipe_ctx->plane_res.hubp->power_gated)
@@ -612,6 +618,12 @@ void dcn20_disable_plane(struct dc dc, struct pipe_ctx pipe_ctx) · 1 unmodified line
612		618
613	dcn20_plane_atomic_disable(dc, pipe_ctx);	619	dcn20_plane_atomic_disable(dc, pipe_ctx);
614		620
		621	/* Turn back off the phantom OTG after the phantom plane is fully disabled
		622	*/
		623	if (is_phantom)
		624	if (tg && tg->funcs->disable_phantom_crtc)
		625	tg->funcs->disable_phantom_crtc(tg);
		626
615	DC_LOG_DC("Power down front end %d\n",	627	DC_LOG_DC("Power down front end %d\n",
616	pipe_ctx->pipe_idx);	628	pipe_ctx->pipe_idx);
617	}	629	}
@@ -1803,6 +1815,18 @@ void dcn20_program_front_end_for_ctx( · 1185 unmodified lines
1803	dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],	1815	dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
1804	&context->res_ctx.pipe_ctx[i]);	1816	&context->res_ctx.pipe_ctx[i]);
1805		1817
		1818	/* When disabling phantom pipes, turn on phantom OTG first (so we can get double
		1819	* buffer updates properly)
		1820	*/
		1821	for (i = 0; i < dc->res_pool->pipe_count; i++)
		1822	if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
		1823	&& dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
		1824	struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg;
		1825
		1826	if (tg->funcs->enable_crtc)
		1827	tg->funcs->enable_crtc(tg);
		1828	}
		1829
1806	/* OTG blank before disabling all front ends */	1830	/* OTG blank before disabling all front ends */
1807	for (i = 0; i < dc->res_pool->pipe_count; i++)	1831	for (i = 0; i < dc->res_pool->pipe_count; i++)
1808	if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable	1832	if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
@@ -2615,6 +2639,37 @@ void dcn20_update_mpcc(struct dc dc, struct pipe_ctx pipe_ctx) · 806 unmodified lines
2615	hubp->mpcc_id = mpcc_id;	2639	hubp->mpcc_id = mpcc_id;
2616	}	2640	}
2617		2641
		2642	static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link)
		2643	{
		2644	switch (link->link_enc->transmitter) {
		2645	case TRANSMITTER_UNIPHY_A:
		2646	return PHYD32CLKA;
		2647	case TRANSMITTER_UNIPHY_B:
		2648	return PHYD32CLKB;
		2649	case TRANSMITTER_UNIPHY_C:
		2650	return PHYD32CLKC;
		2651	case TRANSMITTER_UNIPHY_D:
		2652	return PHYD32CLKD;
		2653	case TRANSMITTER_UNIPHY_E:
		2654	return PHYD32CLKE;
		2655	default:
		2656	return PHYD32CLKA;
		2657	}
		2658	}
		2659
		2660	static int get_odm_segment_count(struct pipe_ctx *pipe_ctx)
		2661	{
		2662	struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
		2663	int count = 1;
		2664
		2665	while (odm_pipe != NULL) {
		2666	count++;
		2667	odm_pipe = odm_pipe->next_odm_pipe;
		2668	}
		2669
		2670	return count;
		2671	}
		2672
2618	void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)	2673	void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
2619	{	2674	{
2620	enum dc_lane_count lane_count =	2675	enum dc_lane_count lane_count =
@@ -2628,12 +2683,43 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) · 7 unmodified lines
2628	struct timing_generator *tg = pipe_ctx->stream_res.tg;	2683	struct timing_generator *tg = pipe_ctx->stream_res.tg;
2629	const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);	2684	const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
2630	struct dc *dc = pipe_ctx->stream->ctx->dc;	2685	struct dc *dc = pipe_ctx->stream->ctx->dc;
		2686	struct dtbclk_dto_params dto_params = {0};
		2687	struct dccg *dccg = dc->res_pool->dccg;
		2688	enum phyd32clk_clock_source phyd32clk;
		2689	int dp_hpo_inst;
		2690	struct dce_hwseq *hws = dc->hwseq;
		2691	unsigned int k1_div = PIXEL_RATE_DIV_NA;
		2692	unsigned int k2_div = PIXEL_RATE_DIV_NA;
2631		2693
2632	if (is_dp_128b_132b_signal(pipe_ctx)) {	2694	if (is_dp_128b_132b_signal(pipe_ctx)) {
2633	if (dc->hwseq->funcs.setup_hpo_hw_control)	2695	if (dc->hwseq->funcs.setup_hpo_hw_control)
2634	dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, true);	2696	dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, true);
2635	}	2697	}
2636		2698
		2699	if (is_dp_128b_132b_signal(pipe_ctx)) {
		2700	dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
		2701	dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst);
		2702
		2703	phyd32clk = get_phyd32clk_src(link);
		2704	dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);
		2705
		2706	dto_params.otg_inst = tg->inst;
		2707	dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
		2708	dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);
		2709	dto_params.timing = &pipe_ctx->stream->timing;
		2710	dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);
		2711	dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
		2712	}
		2713
		2714	if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
		2715	hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
		2716
		2717	dc->res_pool->dccg->funcs->set_pixel_rate_div(
		2718	dc->res_pool->dccg,
		2719	pipe_ctx->stream_res.tg->inst,
		2720	k1_div, k2_div);
		2721	}
		2722
2637	link_hwss->setup_stream_encoder(pipe_ctx);	2723	link_hwss->setup_stream_encoder(pipe_ctx);
2638		2724
2639	if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {	2725	if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c+3−0

@@ -1389,6 +1389,9 @@ enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, · 1388 unmodified lines
1389	for (i = 0; i < dc->res_pool->pipe_count; i++) {	1389	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1390	struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];	1390	struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
1391		1391
		1392	if (pipe_ctx->top_pipe)
		1393	continue;
		1394
1392	if (pipe_ctx->stream != dc_stream)	1395	if (pipe_ctx->stream != dc_stream)
1393	continue;	1396	continue;
1394		1397

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c+2−1

@@ -1414,7 +1414,8 @@ static struct resource_funcs dcn301_res_pool_funcs = { · 1413 unmodified lines
1414	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,	1414	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1415	.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,	1415	.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1416	.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,	1416	.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1417	.update_bw_bounding_box = dcn301_update_bw_bounding_box	1417	.update_bw_bounding_box = dcn301_update_bw_bounding_box,
		1418	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state
1418	};	1419	};
1419		1420
1420	static bool dcn301_resource_construct(	1421	static bool dcn301_resource_construct(

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.c+4−1

 		REG_UPDATE(DP_DPHY_SYM32_CONTROL,
 				MODE, DP2_TEST_PATTERN);
 		break;
-	case DP_TEST_PATTERN_SQUARE_PULSE:
+	case DP_TEST_PATTERN_SQUARE:
+	case DP_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED:
+	case DP_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED:
+	case DP_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED:
 		REG_SET(DP_DPHY_SYM32_TP_SQ_PULSE, 0,
 				TP_SQ_PULSE_WIDTH, tp_params->custom_pattern[0]);

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c+0−40

@@ -623,43 +623,3 @@ void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable) · 622 unmodified lines
623	if (hws->ctx->dc->debug.hpo_optimization)	623	if (hws->ctx->dc->debug.hpo_optimization)
624	REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable);	624	REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable);
625	}	625	}
626	void dcn31_set_drr(struct pipe_ctx **pipe_ctx,
627	int num_pipes, struct dc_crtc_timing_adjust adjust)
628	{
629	int i = 0;
630	struct drr_params params = {0};
631	unsigned int event_triggers = 0x2;/Bit[1]: OTG_TRIG_A/
632	unsigned int num_frames = 2;
633	params.vertical_total_max = adjust.v_total_max;
634	params.vertical_total_min = adjust.v_total_min;
635	params.vertical_total_mid = adjust.v_total_mid;
636	params.vertical_total_mid_frame_num = adjust.v_total_mid_frame_num;
637	for (i = 0; i < num_pipes; i++) {
638	if ((pipe_ctx[i]->stream_res.tg != NULL) && pipe_ctx[i]->stream_res.tg->funcs) {
639	if (pipe_ctx[i]->stream_res.tg->funcs->set_drr)
640	pipe_ctx[i]->stream_res.tg->funcs->set_drr(
641	pipe_ctx[i]->stream_res.tg, &params);
642	if (adjust.v_total_max != 0 && adjust.v_total_min != 0)
643	if (pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control)
644	pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
645	pipe_ctx[i]->stream_res.tg,
646	event_triggers, num_frames);
647	}
648	}
649	}
650	void dcn31_set_static_screen_control(struct pipe_ctx **pipe_ctx,
651	int num_pipes, const struct dc_static_screen_params *params)
652	{
653	unsigned int i;
654	unsigned int triggers = 0;
655	if (params->triggers.surface_update)
656	triggers \|= 0x600;/bit 9 and bit10 : 110 0000 0000/
657	if (params->triggers.cursor_update)
658	triggers \|= 0x10;/bit4/
659	if (params->triggers.force_trigger)
660	triggers \|= 0x1;
661	for (i = 0; i < num_pipes; i++)
662	pipe_ctx[i]->stream_res.tg->funcs->
663	set_static_screen_control(pipe_ctx[i]->stream_res.tg,
664	triggers, params->num_frames);
665	}

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h+0−4

@@ -56,8 +56,4 @@ bool dcn31_is_abm_supported(struct dc *dc, · 55 unmodified lines
56	void dcn31_init_pipes(struct dc dc, struct dc_state context);	56	void dcn31_init_pipes(struct dc dc, struct dc_state context);
57	void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);	57	void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);
58		58
59	void dcn31_set_static_screen_control(struct pipe_ctx **pipe_ctx,
60	int num_pipes, const struct dc_static_screen_params *params);
61	void dcn31_set_drr(struct pipe_ctx **pipe_ctx,
62	int num_pipes, struct dc_crtc_timing_adjust adjust);
63	#endif /* __DC_HWSS_DCN31_H__ */	59	#endif /* __DC_HWSS_DCN31_H__ */

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c+2−2

@@ -64,9 +64,9 @@ static const struct hw_sequencer_funcs dcn31_funcs = { · 63 unmodified lines
64	.prepare_bandwidth = dcn20_prepare_bandwidth,	64	.prepare_bandwidth = dcn20_prepare_bandwidth,
65	.optimize_bandwidth = dcn20_optimize_bandwidth,	65	.optimize_bandwidth = dcn20_optimize_bandwidth,
66	.update_bandwidth = dcn20_update_bandwidth,	66	.update_bandwidth = dcn20_update_bandwidth,
67	.set_drr = dcn31_set_drr,	67	.set_drr = dcn10_set_drr,
68	.get_position = dcn10_get_position,	68	.get_position = dcn10_get_position,
69	.set_static_screen_control = dcn31_set_static_screen_control,	69	.set_static_screen_control = dcn10_set_static_screen_control,
70	.setup_stereo = dcn10_setup_stereo,	70	.setup_stereo = dcn10_setup_stereo,
71	.set_avmute = dcn30_set_avmute,	71	.set_avmute = dcn30_set_avmute,
72	.log_hw_state = dcn10_log_hw_state,	72	.log_hw_state = dcn10_log_hw_state,

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c+1−28

@@ -40,7 +40,6 @@ · 39 unmodified lines
40	#define FN(reg_name, field_name) \	40	#define FN(reg_name, field_name) \
41	optc1->tg_shift->field_name, optc1->tg_mask->field_name	41	optc1->tg_shift->field_name, optc1->tg_mask->field_name
42		42
43	#define STATIC_SCREEN_EVENT_MASK_DRR_DOUBLE_BUFFER_UPDATE_EN 0x2000 /bit 13/
44	static void optc31_set_odm_combine(struct timing_generator optc, int opp_id, int opp_cnt,	43	static void optc31_set_odm_combine(struct timing_generator optc, int opp_id, int opp_cnt,
45	struct dc_crtc_timing *timing)	44	struct dc_crtc_timing *timing)
46	{	45	{
@@ -232,32 +231,6 @@ void optc3_init_odm(struct timing_generator *optc) · 185 unmodified lines
232	OPTC_MEM_SEL, 0);	231	OPTC_MEM_SEL, 0);
233	optc1->opp_count = 1;	232	optc1->opp_count = 1;
234	}	233	}
235	void optc31_set_static_screen_control(
236	struct timing_generator *optc,
237	uint32_t event_triggers,
238	uint32_t num_frames)
239	{
240	struct optc *optc1 = DCN10TG_FROM_TG(optc);
241	uint32_t framecount;
242	uint32_t events;
243
244	if (num_frames > 0xFF)
245	num_frames = 0xFF;
246	REG_GET_2(OTG_STATIC_SCREEN_CONTROL,
247	OTG_STATIC_SCREEN_EVENT_MASK, &events,
248	OTG_STATIC_SCREEN_FRAME_COUNT, &framecount);
249
250	if (events == event_triggers && num_frames == framecount)
251	return;
252	if ((event_triggers & STATIC_SCREEN_EVENT_MASK_DRR_DOUBLE_BUFFER_UPDATE_EN)
253	!= 0)
254	event_triggers = event_triggers &
255	~STATIC_SCREEN_EVENT_MASK_DRR_DOUBLE_BUFFER_UPDATE_EN;
256
257	REG_UPDATE_2(OTG_STATIC_SCREEN_CONTROL,
258	OTG_STATIC_SCREEN_EVENT_MASK, event_triggers,
259	OTG_STATIC_SCREEN_FRAME_COUNT, num_frames);
260	}
261		234
262	static struct timing_generator_funcs dcn31_tg_funcs = {	235	static struct timing_generator_funcs dcn31_tg_funcs = {
263	.validate_timing = optc1_validate_timing,	236	.validate_timing = optc1_validate_timing,
@@ -293,7 +266,7 @@ static struct timing_generator_funcs dcn31_tg_funcs = { · 29 unmodified lines
293	.set_drr = optc31_set_drr,	266	.set_drr = optc31_set_drr,
294	.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,	267	.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
295	.set_vtotal_min_max = optc1_set_vtotal_min_max,	268	.set_vtotal_min_max = optc1_set_vtotal_min_max,
296	.set_static_screen_control = optc31_set_static_screen_control,	269	.set_static_screen_control = optc1_set_static_screen_control,
297	.program_stereo = optc1_program_stereo,	270	.program_stereo = optc1_program_stereo,
298	.is_stereo_left_eye = optc1_is_stereo_left_eye,	271	.is_stereo_left_eye = optc1_is_stereo_left_eye,
299	.tg_init = optc3_tg_init,	272	.tg_init = optc3_tg_init,

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h+1−4

@@ -263,8 +263,5 @@ bool optc31_immediate_disable_crtc(struct timing_generator *optc); · 262 unmodified lines
263	void optc31_set_drr(struct timing_generator optc, const struct drr_params params);	263	void optc31_set_drr(struct timing_generator optc, const struct drr_params params);
264		264
265	void optc3_init_odm(struct timing_generator *optc);	265	void optc3_init_odm(struct timing_generator *optc);
266	void optc31_set_static_screen_control(	266
267	struct timing_generator *optc,
268	uint32_t event_triggers,
269	uint32_t num_frames);
270	#endif /* __DC_OPTC_DCN31_H__ */	267	#endif /* __DC_OPTC_DCN31_H__ */

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c+3−3

 	struct dc_link *link,
 	struct stream_encoder *enc)
 {
-	/* New to DCN314 - disable the FIFO before VID stream disable. */
-	enc314_disable_fifo(enc);
 	enc1_stream_encoder_dp_blank(link, enc);
+	/* Disable FIFO after the DP vid stream is disabled to avoid corruption. */
+	enc314_disable_fifo(enc);
 }
 static void enc314_stream_encoder_dp_unblank(

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c+2−2

@@ -66,9 +66,9 @@ static const struct hw_sequencer_funcs dcn314_funcs = { · 65 unmodified lines
66	.prepare_bandwidth = dcn20_prepare_bandwidth,	66	.prepare_bandwidth = dcn20_prepare_bandwidth,
67	.optimize_bandwidth = dcn20_optimize_bandwidth,	67	.optimize_bandwidth = dcn20_optimize_bandwidth,
68	.update_bandwidth = dcn20_update_bandwidth,	68	.update_bandwidth = dcn20_update_bandwidth,
69	.set_drr = dcn31_set_drr,	69	.set_drr = dcn10_set_drr,
70	.get_position = dcn10_get_position,	70	.get_position = dcn10_get_position,
71	.set_static_screen_control = dcn31_set_static_screen_control,	71	.set_static_screen_control = dcn10_set_static_screen_control,
72	.setup_stereo = dcn10_setup_stereo,	72	.setup_stereo = dcn10_setup_stereo,
73	.set_avmute = dcn30_set_avmute,	73	.set_avmute = dcn30_set_avmute,
74	.log_hw_state = dcn10_log_hw_state,	74	.log_hw_state = dcn10_log_hw_state,

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c+1−2

 		.set_drr = optc31_set_drr,
 		.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
 		.set_vtotal_min_max = optc1_set_vtotal_min_max,
-		.set_static_screen_control = optc31_set_static_screen_control,
+		.set_static_screen_control = optc1_set_static_screen_control,
 		.program_stereo = optc1_program_stereo,
 		.is_stereo_left_eye = optc1_is_stereo_left_eye,
 		.tg_init = optc3_tg_init,
 		.set_dsc_config = optc3_set_dsc_config,
 		.get_dsc_status = optc2_get_dsc_status,
 		.set_dwb_source = NULL,
-		.set_odm_combine = optc314_set_odm_combine,
 		.get_optc_source = optc2_get_optc_source,
 		.set_out_mux = optc3_set_out_mux,
 		.set_drr_trigger_window = optc3_set_drr_trigger_window,

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c+38−1

@@ -188,7 +188,8 @@ static bool dcn32_check_no_memory_request_for_cab(struct dc *dc) · 187 unmodified lines
188		188
189	/* First, check no-memory-request case */	189	/* First, check no-memory-request case */
190	for (i = 0; i < dc->current_state->stream_count; i++) {	190	for (i = 0; i < dc->current_state->stream_count; i++) {
191	if (dc->current_state->stream_status[i].plane_count)	191	if ((dc->current_state->stream_status[i].plane_count) &&
		192	(dc->current_state->streams[i]->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED))
192	/* Fail eligibility on a visible stream */	193	/* Fail eligibility on a visible stream */
193	break;	194	break;
194	}	195	}
@@ -1450,3 +1451,39 @@ void dcn32_update_dsc_pg(struct dc *dc, · 1255 unmodified lines
1450	}	1451	}
1451	}	1452	}
1452	}	1453	}
		1454
		1455	void dcn32_enable_phantom_streams(struct dc dc, struct dc_state context)
		1456	{
		1457	unsigned int i;
		1458
		1459	for (i = 0; i < dc->res_pool->pipe_count; i++) {
		1460	struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
		1461	struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
		1462
		1463	/* If an active, non-phantom pipe is being transitioned into a phantom
		1464	* pipe, wait for the double buffer update to complete first before we do
		1465	* ANY phantom pipe programming.
		1466	*/
		1467	if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM &&
		1468	old_pipe->stream && old_pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) {
		1469	old_pipe->stream_res.tg->funcs->wait_for_state(
		1470	old_pipe->stream_res.tg,
		1471	CRTC_STATE_VBLANK);
		1472	old_pipe->stream_res.tg->funcs->wait_for_state(
		1473	old_pipe->stream_res.tg,
		1474	CRTC_STATE_VACTIVE);
		1475	}
		1476	}
		1477	for (i = 0; i < dc->res_pool->pipe_count; i++) {
		1478	struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
		1479
		1480	if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
		1481	// If old context or new context has phantom pipes, apply
		1482	// the phantom timings now. We can't change the phantom
		1483	// pipe configuration safely without driver acquiring
		1484	// the DMCUB lock first.
		1485	dc->hwss.apply_ctx_to_hw(dc, context);
		1486	break;
		1487	}
		1488	}
		1489	}

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h+2−0

@@ -102,4 +102,6 @@ void dcn32_update_dsc_pg(struct dc *dc, · 101 unmodified lines
102	struct dc_state *context,	102	struct dc_state *context,
103	bool safe_to_disable);	103	bool safe_to_disable);
104		104
		105	void dcn32_enable_phantom_streams(struct dc dc, struct dc_state context);
		106
105	#endif /* __DC_HWSS_DCN32_H__ */	107	#endif /* __DC_HWSS_DCN32_H__ */

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c+1−0

@@ -106,6 +106,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = { · 105 unmodified lines
106	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,	106	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
107	.get_dcc_en_bits = dcn10_get_dcc_en_bits,	107	.get_dcc_en_bits = dcn10_get_dcc_en_bits,
108	.commit_subvp_config = dcn32_commit_subvp_config,	108	.commit_subvp_config = dcn32_commit_subvp_config,
		109	.enable_phantom_streams = dcn32_enable_phantom_streams,
109	.subvp_pipe_control_lock = dcn32_subvp_pipe_control_lock,	110	.subvp_pipe_control_lock = dcn32_subvp_pipe_control_lock,
110	.update_visual_confirm_color = dcn20_update_visual_confirm_color,	111	.update_visual_confirm_color = dcn20_update_visual_confirm_color,
111	.update_phantom_vp_position = dcn32_update_phantom_vp_position,	112	.update_phantom_vp_position = dcn32_update_phantom_vp_position,

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c+1−0

@@ -726,6 +726,7 @@ static const struct dc_debug_options debug_defaults_drv = { · 725 unmodified lines
726	.allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback"	726	.allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback"
727	.alloc_extra_way_for_cursor = true,	727	.alloc_extra_way_for_cursor = true,
728	.min_prefetch_in_strobe_ns = 60000, // 60us	728	.min_prefetch_in_strobe_ns = 60000, // 60us
		729	.disable_unbounded_requesting = false,
729	};	730	};
730		731
731	static const struct dc_debug_options debug_defaults_diags = {	732	static const struct dc_debug_options debug_defaults_diags = {

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h+1−0

@@ -112,6 +112,7 @@ bool dcn32_subvp_in_use(struct dc *dc, · 111 unmodified lines
112	bool dcn32_mpo_in_use(struct dc_state *context);	112	bool dcn32_mpo_in_use(struct dc_state *context);
113		113
114	bool dcn32_any_surfaces_rotated(struct dc dc, struct dc_state context);	114	bool dcn32_any_surfaces_rotated(struct dc dc, struct dc_state context);
		115	bool dcn32_is_center_timing(struct pipe_ctx *pipe);
115		116
116	struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer(	117	struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
117	struct dc_state *state,	118	struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c+15−1

 	return false;
 }
+bool dcn32_is_center_timing(struct pipe_ctx *pipe)
+{
+	bool is_center_timing = false;
+	if (pipe->stream) {
+		if (pipe->stream->timing.v_addressable != pipe->stream->dst.height ||
+				pipe->stream->timing.v_addressable != pipe->stream->src.height) {
+			is_center_timing = true;
+		}
+	}
+	return is_center_timing;
+}
 /**
  * *******************************************************************************************
  * dcn32_determine_det_override: Determine DET allocation for each pipe
 	int i, pipe_cnt;
 	struct resource_context *res_ctx = &context->res_ctx;
 	struct pipe_ctx *pipe;
+	bool disable_unbounded_requesting = dc->debug.disable_z9_mpc || dc->debug.disable_unbounded_requesting;
 	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
 	 */
 	if (pipe_cnt == 1) {
 		pipes[0].pipe.src.det_size_override = DCN3_2_MAX_DET_SIZE;
-		if (pipe->plane_state && !dc->debug.disable_z9_mpc && pipe->plane_state->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
+		if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
 			if (!is_dual_plane(pipe->plane_state->format)) {
 				pipes[0].pipe.src.det_size_override = DCN3_2_DEFAULT_DET_SIZE;
 				pipes[0].pipe.src.unbounded_req_mode = true;

drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c+1−0

@@ -724,6 +724,7 @@ static const struct dc_debug_options debug_defaults_drv = { · 723 unmodified lines
724	.allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback"	724	.allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback"
725	.alloc_extra_way_for_cursor = true,	725	.alloc_extra_way_for_cursor = true,
726	.min_prefetch_in_strobe_ns = 60000, // 60us	726	.min_prefetch_in_strobe_ns = 60000, // 60us
		727	.disable_unbounded_requesting = false,
727	};	728	};
728		729
729	static const struct dc_debug_options debug_defaults_diags = {	730	static const struct dc_debug_options debug_defaults_diags = {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c+21−4

 		 *   to combine this with SubVP can cause issues with the scheduling).
 		 * - Not TMZ surface
 		 */
-		if (pipe->plane_state && !pipe->top_pipe &&
+		if (pipe->plane_state && !pipe->top_pipe && !dcn32_is_center_timing(pipe) &&
 				pipe->stream->mall_stream_config.type == SUBVP_NONE && refresh_rate < 120 && !pipe->plane_state->address.tmz_surface &&
 				vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0) {
 			while (pipe) {
 	}
 	// Use ignore_msa_timing_param flag to identify as DRR
 	if (found && context->res_ctx.pipe_ctx[vblank_index].stream->ignore_msa_timing_param) {
-		// SUBVP + DRR case
+		// SUBVP + DRR case -- don't enable SubVP + DRR for HDMI VRR cases
-		schedulable = subvp_drr_schedulable(dc, context, &context->res_ctx.pipe_ctx[vblank_index]);
+		if (context->res_ctx.pipe_ctx[vblank_index].stream->allow_freesync)
+			schedulable = subvp_drr_schedulable(dc, context, &context->res_ctx.pipe_ctx[vblank_index]);
+		else
+			schedulable = false;
 	} else if (found) {
 		main_timing = &subvp_pipe->stream->timing;
 		phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
 			pipes[0].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, *pipe_cnt, 0);
 			*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
+			/* Check that vlevel requested supports pstate or not
+			 * if not, select the lowest vlevel that supports it
+			 */
+			for (i = *vlevel; i < context->bw_ctx.dml.soc.num_states; i++) {
+				if (vba->DRAMClockChangeSupport[i][vba->maxMpcComb] != dm_dram_clock_change_unsupported) {
+					*vlevel = i;
+					break;
+				}
+			}
 			if (*vlevel < context->bw_ctx.dml.soc.num_states &&
 			    vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported
 			    && subvp_validate_static_schedulability(dc, context, *vlevel)) {
 					    pipe->stream->mall_stream_config.type == SUBVP_NONE) {
 						non_subvp_pipes++;
 						// Use ignore_msa_timing_param flag to identify as DRR
-						if (pipe->stream->ignore_msa_timing_param) {
+						if (pipe->stream->ignore_msa_timing_param && pipe->stream->allow_freesync) {
 							drr_pipe_found = true;
 							drr_pipe_index = i;
 						}
 		context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
 			dm_prefetch_support_fclk_and_stutter;
+		context->bw_ctx.dml.validate_max_state = fast_validate;
 		vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
 		/* Last attempt with Prefetch mode 2 (dm_prefetch_support_stutter == 3) */
 				dm_prefetch_support_stutter;
 			vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
 		}
+		context->bw_ctx.dml.validate_max_state = false;
 		if (vlevel < context->bw_ctx.dml.soc.num_states) {
 			memset(split, 0, sizeof(split));
 				dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
 			memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
 			memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
+			memset(&pipe->link_res, 0, sizeof(pipe->link_res));
 			repopulate_pipes = true;
 		} else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
 			struct pipe_ctx *top_pipe = pipe->top_pipe;
 			pipe->stream = NULL;
 			memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
 			memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
+			memset(&pipe->link_res, 0, sizeof(pipe->link_res));
 			repopulate_pipes = true;
 		} else
 			ASSERT(0); /* Should never try to merge master pipe */

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c+20−17

@@ -1707,7 +1707,7 @@ static void mode_support_configuration(struct vba_vars_st *v, · 1706 unmodified lines
1707	void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)	1707	void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)
1708	{	1708	{
1709	struct vba_vars_st *v = &mode_lib->vba;	1709	struct vba_vars_st *v = &mode_lib->vba;
1710	int i, j;	1710	int i, j, start_state;
1711	unsigned int k, m;	1711	unsigned int k, m;
1712	unsigned int MaximumMPCCombine;	1712	unsigned int MaximumMPCCombine;
1713	unsigned int NumberOfNonCombinedSurfaceOfMaximumBandwidth;	1713	unsigned int NumberOfNonCombinedSurfaceOfMaximumBandwidth;
@@ -1720,7 +1720,10 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 6 unmodified lines
1720	#endif	1720	#endif
1721		1721
1722	/MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION/	1722	/MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION/
1723		1723	if (mode_lib->validate_max_state)
		1724	start_state = v->soc.num_states - 1;
		1725	else
		1726	start_state = 0;
1724	/Scale Ratio, taps Support Check/	1727	/Scale Ratio, taps Support Check/
1725		1728
1726	mode_lib->vba.ScaleRatioAndTapsSupport = true;	1729	mode_lib->vba.ScaleRatioAndTapsSupport = true;
@@ -2009,7 +2012,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 282 unmodified lines
2009	mode_lib->vba.MPCCombineMethodIncompatible = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsNeededForPStateChangeAndVoltage	2012	mode_lib->vba.MPCCombineMethodIncompatible = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsNeededForPStateChangeAndVoltage
2010	&& v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsPossible;	2013	&& v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsPossible;
2011		2014
2012	for (i = 0; i < v->soc.num_states; i++) {	2015	for (i = start_state; i < v->soc.num_states; i++) {
2013	for (j = 0; j < 2; j++) {	2016	for (j = 0; j < 2; j++) {
2014	mode_lib->vba.TotalNumberOfActiveDPP[i][j] = 0;	2017	mode_lib->vba.TotalNumberOfActiveDPP[i][j] = 0;
2015	mode_lib->vba.TotalAvailablePipesSupport[i][j] = true;	2018	mode_lib->vba.TotalAvailablePipesSupport[i][j] = true;
@@ -2286,7 +2289,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 270 unmodified lines
2286	}	2289	}
2287	}	2290	}
2288		2291
2289	for (i = 0; i < v->soc.num_states; ++i) {	2292	for (i = start_state; i < v->soc.num_states; ++i) {
2290	mode_lib->vba.ExceededMultistreamSlots[i] = false;	2293	mode_lib->vba.ExceededMultistreamSlots[i] = false;
2291	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {	2294	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
2292	if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == k) {	2295	if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == k) {
@@ -2386,7 +2389,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 93 unmodified lines
2386	}	2389	}
2387	}	2390	}
2388		2391
2389	for (i = 0; i < v->soc.num_states; ++i) {	2392	for (i = start_state; i < v->soc.num_states; ++i) {
2390	mode_lib->vba.DTBCLKRequiredMoreThanSupported[i] = false;	2393	mode_lib->vba.DTBCLKRequiredMoreThanSupported[i] = false;
2391	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {	2394	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
2392	if (mode_lib->vba.BlendingAndTiming[k] == k	2395	if (mode_lib->vba.BlendingAndTiming[k] == k
@@ -2403,7 +2406,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 10 unmodified lines
2403	}	2406	}
2404	}	2407	}
2405		2408
2406	for (i = 0; i < v->soc.num_states; ++i) {	2409	for (i = start_state; i < v->soc.num_states; ++i) {
2407	mode_lib->vba.ODMCombine2To1SupportCheckOK[i] = true;	2410	mode_lib->vba.ODMCombine2To1SupportCheckOK[i] = true;
2408	mode_lib->vba.ODMCombine4To1SupportCheckOK[i] = true;	2411	mode_lib->vba.ODMCombine4To1SupportCheckOK[i] = true;
2409	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {	2412	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
@@ -2421,7 +2424,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 11 unmodified lines
2421	}	2424	}
2422	}	2425	}
2423		2426
2424	for (i = 0; i < v->soc.num_states; i++) {	2427	for (i = start_state; i < v->soc.num_states; i++) {
2425	mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = false;	2428	mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = false;
2426	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {	2429	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
2427	if (mode_lib->vba.BlendingAndTiming[k] == k) {	2430	if (mode_lib->vba.BlendingAndTiming[k] == k) {
@@ -2458,7 +2461,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 30 unmodified lines
2458	/* Check DSC Unit and Slices Support */	2461	/* Check DSC Unit and Slices Support */
2459	v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired = 0;	2462	v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired = 0;
2460		2463
2461	for (i = 0; i < v->soc.num_states; ++i) {	2464	for (i = start_state; i < v->soc.num_states; ++i) {
2462	mode_lib->vba.NotEnoughDSCUnits[i] = false;	2465	mode_lib->vba.NotEnoughDSCUnits[i] = false;
2463	mode_lib->vba.NotEnoughDSCSlices[i] = false;	2466	mode_lib->vba.NotEnoughDSCSlices[i] = false;
2464	v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired = 0;	2467	v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired = 0;
@@ -2493,7 +2496,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 28 unmodified lines
2493	}	2496	}
2494		2497
2495	/DSC Delay per state/	2498	/DSC Delay per state/
2496	for (i = 0; i < v->soc.num_states; ++i) {	2499	for (i = start_state; i < v->soc.num_states; ++i) {
2497	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {	2500	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
2498	mode_lib->vba.DSCDelayPerState[i][k] = dml32_DSCDelayRequirement(	2501	mode_lib->vba.DSCDelayPerState[i][k] = dml32_DSCDelayRequirement(
2499	mode_lib->vba.RequiresDSC[i][k], mode_lib->vba.ODMCombineEnablePerState[i][k],	2502	mode_lib->vba.RequiresDSC[i][k], mode_lib->vba.ODMCombineEnablePerState[i][k],
@@ -2520,7 +2523,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 20 unmodified lines
2520		2523
2521	//Calculate Swath, DET Configuration, DCFCLKDeepSleep	2524	//Calculate Swath, DET Configuration, DCFCLKDeepSleep
2522	//	2525	//
2523	for (i = 0; i < (int) v->soc.num_states; ++i) {	2526	for (i = start_state; i < (int) v->soc.num_states; ++i) {
2524	for (j = 0; j <= 1; ++j) {	2527	for (j = 0; j <= 1; ++j) {
2525	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {	2528	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
2526	mode_lib->vba.RequiredDPPCLKThisState[k] = mode_lib->vba.RequiredDPPCLK[i][j][k];	2529	mode_lib->vba.RequiredDPPCLKThisState[k] = mode_lib->vba.RequiredDPPCLK[i][j][k];
@@ -2655,7 +2658,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 128 unmodified lines
2655	mode_lib->vba.SurfaceSizeInMALL,	2658	mode_lib->vba.SurfaceSizeInMALL,
2656	&mode_lib->vba.ExceededMALLSize);	2659	&mode_lib->vba.ExceededMALLSize);
2657		2660
2658	for (i = 0; i < v->soc.num_states; i++) {	2661	for (i = start_state; i < v->soc.num_states; i++) {
2659	for (j = 0; j < 2; j++) {	2662	for (j = 0; j < 2; j++) {
2660	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {	2663	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
2661	mode_lib->vba.swath_width_luma_ub_this_state[k] =	2664	mode_lib->vba.swath_width_luma_ub_this_state[k] =
@@ -2882,7 +2885,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 220 unmodified lines
2882	}	2885	}
2883		2886
2884	//Calculate Return BW	2887	//Calculate Return BW
2885	for (i = 0; i < (int) v->soc.num_states; ++i) {	2888	for (i = start_state; i < (int) v->soc.num_states; ++i) {
2886	for (j = 0; j <= 1; ++j) {	2889	for (j = 0; j <= 1; ++j) {
2887	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {	2890	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
2888	if (mode_lib->vba.BlendingAndTiming[k] == k) {	2891	if (mode_lib->vba.BlendingAndTiming[k] == k) {
@@ -2961,7 +2964,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 72 unmodified lines
2961	&mode_lib->vba.MinPrefetchMode,	2964	&mode_lib->vba.MinPrefetchMode,
2962	&mode_lib->vba.MaxPrefetchMode);	2965	&mode_lib->vba.MaxPrefetchMode);
2963		2966
2964	for (i = 0; i < (int) v->soc.num_states; ++i) {	2967	for (i = start_state; i < (int) v->soc.num_states; ++i) {
2965	for (j = 0; j <= 1; ++j)	2968	for (j = 0; j <= 1; ++j)
2966	mode_lib->vba.DCFCLKState[i][j] = mode_lib->vba.DCFCLKPerState[i];	2969	mode_lib->vba.DCFCLKState[i][j] = mode_lib->vba.DCFCLKPerState[i];
2967	}	2970	}
@@ -3083,7 +3086,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 115 unmodified lines
3083	mode_lib->vba.DCFCLKState);	3086	mode_lib->vba.DCFCLKState);
3084	} // UseMinimumRequiredDCFCLK == true	3087	} // UseMinimumRequiredDCFCLK == true
3085		3088
3086	for (i = 0; i < (int) v->soc.num_states; ++i) {	3089	for (i = start_state; i < (int) v->soc.num_states; ++i) {
3087	for (j = 0; j <= 1; ++j) {	3090	for (j = 0; j <= 1; ++j) {
3088	mode_lib->vba.ReturnBWPerState[i][j] = dml32_get_return_bw_mbps(&mode_lib->vba.soc, i,	3091	mode_lib->vba.ReturnBWPerState[i][j] = dml32_get_return_bw_mbps(&mode_lib->vba.soc, i,
3089	mode_lib->vba.HostVMEnable, mode_lib->vba.DCFCLKState[i][j],	3092	mode_lib->vba.HostVMEnable, mode_lib->vba.DCFCLKState[i][j],
@@ -3092,7 +3095,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 2 unmodified lines
3092	}	3095	}
3093		3096
3094	//Re-ordering Buffer Support Check	3097	//Re-ordering Buffer Support Check
3095	for (i = 0; i < (int) v->soc.num_states; ++i) {	3098	for (i = start_state; i < (int) v->soc.num_states; ++i) {
3096	for (j = 0; j <= 1; ++j) {	3099	for (j = 0; j <= 1; ++j) {
3097	if ((mode_lib->vba.ROBBufferSizeInKByte - mode_lib->vba.PixelChunkSizeInKByte) * 1024	3100	if ((mode_lib->vba.ROBBufferSizeInKByte - mode_lib->vba.PixelChunkSizeInKByte) * 1024
3098	/ mode_lib->vba.ReturnBWPerState[i][j]	3101	/ mode_lib->vba.ReturnBWPerState[i][j]
@@ -3114,7 +3117,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 15 unmodified lines
3114	+ mode_lib->vba.ReadBandwidthChroma[k];	3117	+ mode_lib->vba.ReadBandwidthChroma[k];
3115	}	3118	}
3116		3119
3117	for (i = 0; i < (int) v->soc.num_states; ++i) {	3120	for (i = start_state; i < (int) v->soc.num_states; ++i) {
3118	for (j = 0; j <= 1; ++j) {	3121	for (j = 0; j <= 1; ++j) {
3119	mode_lib->vba.MaxTotalVerticalActiveAvailableBandwidth[i][j] =	3122	mode_lib->vba.MaxTotalVerticalActiveAvailableBandwidth[i][j] =
3120	dml_min3(mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLKState[i][j]	3123	dml_min3(mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLKState[i][j]
@@ -3138,7 +3141,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 17 unmodified lines
3138		3141
3139	/* Prefetch Check */	3142	/* Prefetch Check */
3140		3143
3141	for (i = 0; i < (int) v->soc.num_states; ++i) {	3144	for (i = start_state; i < (int) v->soc.num_states; ++i) {
3142	for (j = 0; j <= 1; ++j) {	3145	for (j = 0; j <= 1; ++j) {
3143		3146
3144	mode_lib->vba.TimeCalc = 24 / mode_lib->vba.ProjectedDCFCLKDeepSleep[i][j];	3147	mode_lib->vba.TimeCalc = 24 / mode_lib->vba.ProjectedDCFCLKDeepSleep[i][j];

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c+3−3

@@ -6257,12 +6257,12 @@ bool dml32_CalculateDETSwathFillLatencyHiding(unsigned int NumberOfActiveSurface · 6256 unmodified lines
6257	double SwathSizePerSurfaceC[DC__NUM_DPP__MAX];	6257	double SwathSizePerSurfaceC[DC__NUM_DPP__MAX];
6258	bool NotEnoughDETSwathFillLatencyHiding = false;	6258	bool NotEnoughDETSwathFillLatencyHiding = false;
6259		6259
6260	/* calculate sum of single swath size for all pipes in bytes*/	6260	/* calculate sum of single swath size for all pipes in bytes */
6261	for (k = 0; k < NumberOfActiveSurfaces; k++) {	6261	for (k = 0; k < NumberOfActiveSurfaces; k++) {
6262	SwathSizePerSurfaceY[k] += SwathHeightY[k] * SwathWidthY[k] * BytePerPixelInDETY[k] * NumOfDPP[k];	6262	SwathSizePerSurfaceY[k] = SwathHeightY[k] * SwathWidthY[k] * BytePerPixelInDETY[k] * NumOfDPP[k];
6263		6263
6264	if (SwathHeightC[k] != 0)	6264	if (SwathHeightC[k] != 0)
6265	SwathSizePerSurfaceC[k] += SwathHeightC[k] * SwathWidthC[k] * BytePerPixelInDETC[k] * NumOfDPP[k];	6265	SwathSizePerSurfaceC[k] = SwathHeightC[k] * SwathWidthC[k] * BytePerPixelInDETC[k] * NumOfDPP[k];
6266	else	6266	else
6267	SwathSizePerSurfaceC[k] = 0;	6267	SwathSizePerSurfaceC[k] = 0;
6268		6268

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c+1−1

@@ -136,7 +136,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = { · 135 unmodified lines
136	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,	136	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
137	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,	137	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
138	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,	138	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
139	.pct_ideal_sdp_bw_after_urgent = 100.0,	139	.pct_ideal_sdp_bw_after_urgent = 90.0,
140	.pct_ideal_fabric_bw_after_urgent = 67.0,	140	.pct_ideal_fabric_bw_after_urgent = 67.0,
141	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0,	141	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0,
142	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented	142	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented

drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h+1−0

@@ -91,6 +91,7 @@ struct display_mode_lib { · 90 unmodified lines
91	struct dal_logger *logger;	91	struct dal_logger *logger;
92	struct dml_funcs funcs;	92	struct dml_funcs funcs;
93	struct _vcs_dpi_display_e2e_pipe_params_st dml_pipe_state[6];	93	struct _vcs_dpi_display_e2e_pipe_params_st dml_pipe_state[6];
		94	bool validate_max_state;
94	};	95	};
95		96
96	void dml_init_instance(struct display_mode_lib *lib,	97	void dml_init_instance(struct display_mode_lib *lib,

drivers/gpu/drm/amd/display/dc/inc/core_types.h+9−9

 	 */
 	struct resource_context res_ctx;
-	/**
-	 * @bw_ctx: The output from bandwidth and watermark calculations and the DML
-	 *
-	 * Each context must have its own instance of VBA, and in order to
-	 * initialize and obtain IP and SOC, the base DML instance from DC is
-	 * initially copied into every context.
-	 */
-	struct bw_context bw_ctx;
 	/**
 	 * @pp_display_cfg: PowerPlay clocks and settings
 	 * Note: this is a big struct, do *not* put on stack!
 	struct clk_mgr *clk_mgr;
+	/**
+	 * @bw_ctx: The output from bandwidth and watermark calculations and the DML
+	 *
+	 * Each context must have its own instance of VBA, and in order to
+	 * initialize and obtain IP and SOC, the base DML instance from DC is
+	 * initially copied into every context.
+	 */
+	struct bw_context bw_ctx;
 	/**
 	 * @refcount: refcount reference
 	 *

drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h+1−0

@@ -266,6 +266,7 @@ struct hw_sequencer_funcs { · 265 unmodified lines
266	void (apply_update_flags_for_phantom)(struct pipe_ctx phantom_pipe);	266	void (apply_update_flags_for_phantom)(struct pipe_ctx phantom_pipe);
267		267
268	void (commit_subvp_config)(struct dc dc, struct dc_state *context);	268	void (commit_subvp_config)(struct dc dc, struct dc_state *context);
		269	void (enable_phantom_streams)(struct dc dc, struct dc_state *context);
269	void (subvp_pipe_control_lock)(struct dc dc,	270	void (subvp_pipe_control_lock)(struct dc dc,
270	struct dc_state *context,	271	struct dc_state *context,
271	bool lock,	272	bool lock,

drivers/gpu/drm/amd/display/dc/inc/resource.h+9−0

@@ -236,4 +236,13 @@ bool dc_resource_acquire_secondary_pipe_for_mpc_odm( · 235 unmodified lines
236	struct pipe_ctx *pri_pipe,	236	struct pipe_ctx *pri_pipe,
237	struct pipe_ctx *sec_pipe,	237	struct pipe_ctx *sec_pipe,
238	bool odm);	238	bool odm);
		239
		240	/* A test harness interface that modifies dp encoder resources in the given dc
		241	* state and bypasses the need to revalidate. The interface assumes that the
		242	* test harness interface is called with pre-validated link config stored in the
		243	* pipe_ctx and updates dp encoder resources according to the link config.
		244	*/
		245	enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc,
		246	struct dc_state *context,
		247	struct pipe_ctx *pipe_ctx);
239	#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */	248	#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c+0−5

 	.ack = NULL
 };
-static const struct irq_source_info_funcs dmub_outbox_irq_info_funcs = {
-	.set = NULL,
-	.ack = NULL
-};
 #undef BASE_INNER
 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c+0−37

@@ -87,57 +87,20 @@ static void set_hpo_dp_hblank_min_symbol_width(struct pipe_ctx *pipe_ctx, · 86 unmodified lines
87	hblank_min_symbol_width);	87	hblank_min_symbol_width);
88	}	88	}
89		89
90	static int get_odm_segment_count(struct pipe_ctx *pipe_ctx)
91	{
92	struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
93	int count = 1;
94
95	while (odm_pipe != NULL) {
96	count++;
97	odm_pipe = odm_pipe->next_odm_pipe;
98	}
99
100	return count;
101	}
102
103	static void setup_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx)	90	static void setup_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx)
104	{	91	{
105	struct dc *dc = pipe_ctx->stream->ctx->dc;
106	struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;	92	struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
107	struct hpo_dp_link_encoder *link_enc = pipe_ctx->link_res.hpo_dp_link_enc;	93	struct hpo_dp_link_encoder *link_enc = pipe_ctx->link_res.hpo_dp_link_enc;
108	struct dccg *dccg = dc->res_pool->dccg;
109	struct timing_generator *tg = pipe_ctx->stream_res.tg;
110	struct dtbclk_dto_params dto_params = {0};
111	enum phyd32clk_clock_source phyd32clk = get_phyd32clk_src(pipe_ctx->stream->link);
112		94
113	dto_params.otg_inst = tg->inst;
114	dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
115	dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);
116	dto_params.timing = &pipe_ctx->stream->timing;
117	dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);
118
119	dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, stream_enc->inst);
120	dccg->funcs->enable_symclk32_se(dccg, stream_enc->inst, phyd32clk);
121	dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
122	stream_enc->funcs->enable_stream(stream_enc);	95	stream_enc->funcs->enable_stream(stream_enc);
123	stream_enc->funcs->map_stream_to_link(stream_enc, stream_enc->inst, link_enc->inst);	96	stream_enc->funcs->map_stream_to_link(stream_enc, stream_enc->inst, link_enc->inst);
124	}	97	}
125		98
126	static void reset_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx)	99	static void reset_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx)
127	{	100	{
128	struct dc *dc = pipe_ctx->stream->ctx->dc;
129	struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;	101	struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
130	struct dccg *dccg = dc->res_pool->dccg;
131	struct timing_generator *tg = pipe_ctx->stream_res.tg;
132	struct dtbclk_dto_params dto_params = {0};
133
134	dto_params.otg_inst = tg->inst;
135	dto_params.timing = &pipe_ctx->stream->timing;
136		102
137	stream_enc->funcs->disable(stream_enc);	103	stream_enc->funcs->disable(stream_enc);
138	dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
139	dccg->funcs->disable_symclk32_se(dccg, stream_enc->inst);
140	dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, stream_enc->inst);
141	}	104	}
142		105
143	static void setup_hpo_dp_stream_attribute(struct pipe_ctx *pipe_ctx)	106	static void setup_hpo_dp_stream_attribute(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dmub/dmub_srv.h+3−0

 	DMUB_NOTIFICATION_HPD,
 	DMUB_NOTIFICATION_HPD_IRQ,
 	DMUB_NOTIFICATION_SET_CONFIG_REPLY,
+	DMUB_NOTIFICATION_DPIA_NOTIFICATION,
 	DMUB_NOTIFICATION_MAX
 };
  * @pending_notification: Indicates there are other pending notifications
  * @aux_reply: aux reply
  * @hpd_status: hpd status
+ * @bw_alloc_reply: BW Allocation reply from CM/DPIA
  */
 struct dmub_notification {
 	enum dmub_notification_type type;
 		struct aux_reply_data aux_reply;
 		enum dp_hpd_status hpd_status;
 		enum set_config_status sc_status;
+		struct dpia_notification_reply_data bw_alloc_reply;
 	};
 };

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h+83−0

@@ -770,6 +770,7 @@ enum dmub_out_cmd_type { · 769 unmodified lines
770	* Command type used for SET_CONFIG Reply notification	770	* Command type used for SET_CONFIG Reply notification
771	*/	771	*/
772	DMUB_OUT_CMD__SET_CONFIG_REPLY = 3,	772	DMUB_OUT_CMD__SET_CONFIG_REPLY = 3,
		773	DMUB_OUT_CMD__DPIA_NOTIFICATION = 5
773	};	774	};
774		775
775	/* DMUB_CMD__DPIA command sub-types. */	776	/* DMUB_CMD__DPIA command sub-types. */
@@ -1516,6 +1517,84 @@ struct dp_hpd_data { · 740 unmodified lines
1516	uint8_t pad;	1517	uint8_t pad;
1517	};	1518	};
1518		1519
		1520	/**
		1521	* DPIA NOTIFICATION Response Type
		1522	*/
		1523	enum dpia_notify_bw_alloc_status {
		1524
		1525	DPIA_BW_REQ_FAILED = 0,
		1526	DPIA_BW_REQ_SUCCESS,
		1527	DPIA_EST_BW_CHANGED,
		1528	DPIA_BW_ALLOC_CAPS_CHANGED
		1529	};
		1530
		1531	/* DMUB_OUT_CMD__DPIA_NOTIFY Reply command - OutBox Cmd */
		1532	/**
		1533	* Data passed to driver from FW in a DMUB_OUT_CMD__DPIA_NOTIFY command.
		1534	*/
		1535	struct dpia_notification_reply_data {
		1536	uint8_t allocated_bw;
		1537	uint8_t estimated_bw;
		1538	};
		1539
		1540	struct dpia_notification_common {
		1541	bool shared;
		1542	};
		1543
		1544	struct dpia_bw_allocation_notify_data {
		1545	union {
		1546	struct {
		1547	uint16_t cm_bw_alloc_support: 1; /*< USB4 CM BW Allocation mode support /
		1548	uint16_t bw_request_failed: 1; /*< BW_Request_Failed /
		1549	uint16_t bw_request_succeeded: 1; /*< BW_Request_Succeeded /
		1550	uint16_t est_bw_changed: 1; /*< Estimated_BW changed /
		1551	uint16_t bw_alloc_cap_changed: 1; /*< BW_Allocation_Capabiity_Changed /
		1552	uint16_t reserved: 11;
		1553	} bits;
		1554	uint16_t flags;
		1555	};
		1556	uint8_t cm_id; /*< CM ID /
		1557	uint8_t group_id; /*< Group ID /
		1558	uint8_t granularity; /*< BW Allocation Granularity /
		1559	uint8_t estimated_bw; /*< Estimated_BW /
		1560	uint8_t allocated_bw; /*< Allocated_BW /
		1561	uint8_t reserved;
		1562	};
		1563
		1564	union dpia_notification_data {
		1565	struct dpia_notification_common common_data;
		1566	struct dpia_bw_allocation_notify_data dpia_bw_alloc; /*< Used for DPIA BW Allocation mode notification /
		1567	};
		1568
		1569	enum dmub_cmd_dpia_notification_type {
		1570	DPIA_NOTIFY__BW_ALLOCATION = 0,
		1571	};
		1572
		1573	struct dpia_notification_header {
		1574	uint8_t instance; /*< DPIA Instance /
		1575	uint8_t reserved[3];
		1576	enum dmub_cmd_dpia_notification_type type; /*< DPIA notification type /
		1577	};
		1578
		1579	struct dpia_notification_payload {
		1580	struct dpia_notification_header header;
		1581	union dpia_notification_data data; /*< DPIA notification data /
		1582	};
		1583
		1584	/**
		1585	* Definition of a DMUB_OUT_CMD__DPIA_NOTIFY command.
		1586	*/
		1587	struct dmub_rb_cmd_dpia_notification {
		1588	/**
		1589	* Command header.
		1590	*/
		1591	struct dmub_cmd_header header; /*< DPIA notification header /
		1592	/**
		1593	* Data passed to driver from FW in a DMUB_OUT_CMD__DPIA_NOTIFY command.
		1594	*/
		1595	struct dpia_notification_payload payload; /*< DPIA notification payload /
		1596	};
		1597
1519	/**	1598	/**
1520	* Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command.	1599	* Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1521	*/	1600	*/
@@ -3422,6 +3501,10 @@ union dmub_rb_out_cmd { · 1900 unmodified lines
3422	* SET_CONFIG reply command.	3501	* SET_CONFIG reply command.
3423	*/	3502	*/
3424	struct dmub_rb_cmd_dp_set_config_reply set_config_reply;	3503	struct dmub_rb_cmd_dp_set_config_reply set_config_reply;
		3504	/**
		3505	* BW ALLOCATION notification command.
		3506	*/
		3507	struct dmub_rb_cmd_dpia_notification dpia_notify;
3425	};	3508	};
3426	#pragma pack(pop)	3509	#pragma pack(pop)
3427		3510

drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c+21−0

@@ -92,6 +92,27 @@ enum dmub_status dmub_srv_stat_get_notification(struct dmub_srv *dmub, · 91 unmodified lines
92	notify->link_index = cmd.set_config_reply.set_config_reply_control.instance;	92	notify->link_index = cmd.set_config_reply.set_config_reply_control.instance;
93	notify->sc_status = cmd.set_config_reply.set_config_reply_control.status;	93	notify->sc_status = cmd.set_config_reply.set_config_reply_control.status;
94	break;	94	break;
		95	case DMUB_OUT_CMD__DPIA_NOTIFICATION:
		96	notify->type = DMUB_NOTIFICATION_DPIA_NOTIFICATION;
		97	notify->link_index = cmd.dpia_notify.payload.header.instance;
		98
		99	if (cmd.dpia_notify.payload.header.type == DPIA_NOTIFY__BW_ALLOCATION) {
		100
		101	if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.bw_request_failed) {
		102	notify->result = DPIA_BW_REQ_FAILED;
		103	} else if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.bw_request_succeeded) {
		104	notify->result = DPIA_BW_REQ_SUCCESS;
		105	notify->bw_alloc_reply.allocated_bw =
		106	cmd.dpia_notify.payload.data.dpia_bw_alloc.allocated_bw;
		107	} else if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.est_bw_changed) {
		108	notify->result = DPIA_EST_BW_CHANGED;
		109	notify->bw_alloc_reply.estimated_bw =
		110	cmd.dpia_notify.payload.data.dpia_bw_alloc.estimated_bw;
		111	} else if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.bw_alloc_cap_changed) {
		112	notify->result = DPIA_BW_ALLOC_CAPS_CHANGED;
		113	}
		114	}
		115	break;
95	default:	116	default:
96	notify->type = DMUB_NOTIFICATION_NO_DATA;	117	notify->type = DMUB_NOTIFICATION_NO_DATA;
97	break;	118	break;

drivers/gpu/drm/amd/display/include/dpcd_defs.h+4−1

 	PHY_TEST_PATTERN_PRBS23 = 0x30,
 	PHY_TEST_PATTERN_PRBS31 = 0x38,
 	PHY_TEST_PATTERN_264BIT_CUSTOM = 0x40,
-	PHY_TEST_PATTERN_SQUARE_PULSE = 0x48,
+	PHY_TEST_PATTERN_SQUARE = 0x48,
+	PHY_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED = 0x49,
+	PHY_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED = 0x4A,
+	PHY_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED = 0x4B,
 };
 enum dpcd_test_dyn_range {

drivers/gpu/drm/amd/display/include/link_service_types.h+6−1

 	DP_TEST_PATTERN_PRBS23,
 	DP_TEST_PATTERN_PRBS31,
 	DP_TEST_PATTERN_264BIT_CUSTOM,
-	DP_TEST_PATTERN_SQUARE_PULSE,
+	DP_TEST_PATTERN_SQUARE_BEGIN,
+	DP_TEST_PATTERN_SQUARE = DP_TEST_PATTERN_SQUARE_BEGIN,
+	DP_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED,
+	DP_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED,
+	DP_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED,
+	DP_TEST_PATTERN_SQUARE_END = DP_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED,
 	/* Link Training Patterns */
 	DP_TEST_PATTERN_TRAINING_PATTERN1,

drivers/gpu/drm/amd/include/asic_reg/df/df_4_3_offset.h+30−0

@@ -0,0 +1,30 @@
	1	/*
	2	* Copyright (C) 2022 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included
	12	* in all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
	15	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
	18	* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	19	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*/
	21
	22	#ifndef _df_4_3_OFFSET_HEADER
	23	#define _df_4_3_OFFSET_HEADER
	24
	25	#define regDF_CS_UMC_AON0_HardwareAssertMaskLow 0x0e3e
	26	#define regDF_CS_UMC_AON0_HardwareAssertMaskLow_BASE_IDX 4
	27	#define regDF_NCS_PG0_HardwareAssertMaskHigh 0x0e3f
	28	#define regDF_NCS_PG0_HardwareAssertMaskHigh_BASE_IDX 4
	29
	30	#endif

drivers/gpu/drm/amd/include/asic_reg/df/df_4_3_sh_mask.h+157−0

@@ -0,0 +1,157 @@
	1	/*
	2	* Copyright (C) 2022 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included
	12	* in all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
	15	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
	18	* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	19	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*/
	21
	22	#ifndef _df_4_3_SH_MASK_HEADER
	23	#define _df_4_3_SH_MASK_HEADER
	24
	25	//DF_CS_UMC_AON0_HardwareAssertMaskLow
	26	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk0__SHIFT 0x0
	27	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk1__SHIFT 0x1
	28	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk2__SHIFT 0x2
	29	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk3__SHIFT 0x3
	30	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk4__SHIFT 0x4
	31	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk5__SHIFT 0x5
	32	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk6__SHIFT 0x6
	33	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk7__SHIFT 0x7
	34	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk8__SHIFT 0x8
	35	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk9__SHIFT 0x9
	36	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk10__SHIFT 0xa
	37	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk11__SHIFT 0xb
	38	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk12__SHIFT 0xc
	39	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk13__SHIFT 0xd
	40	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk14__SHIFT 0xe
	41	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk15__SHIFT 0xf
	42	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk16__SHIFT 0x10
	43	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk17__SHIFT 0x11
	44	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk18__SHIFT 0x12
	45	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk19__SHIFT 0x13
	46	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk20__SHIFT 0x14
	47	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk21__SHIFT 0x15
	48	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk22__SHIFT 0x16
	49	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk23__SHIFT 0x17
	50	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk24__SHIFT 0x18
	51	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk25__SHIFT 0x19
	52	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk26__SHIFT 0x1a
	53	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk27__SHIFT 0x1b
	54	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk28__SHIFT 0x1c
	55	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk29__SHIFT 0x1d
	56	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk30__SHIFT 0x1e
	57	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk31__SHIFT 0x1f
	58	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk0_MASK 0x00000001L
	59	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk1_MASK 0x00000002L
	60	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk2_MASK 0x00000004L
	61	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk3_MASK 0x00000008L
	62	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk4_MASK 0x00000010L
	63	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk5_MASK 0x00000020L
	64	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk6_MASK 0x00000040L
	65	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk7_MASK 0x00000080L
	66	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk8_MASK 0x00000100L
	67	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk9_MASK 0x00000200L
	68	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk10_MASK 0x00000400L
	69	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk11_MASK 0x00000800L
	70	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk12_MASK 0x00001000L
	71	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk13_MASK 0x00002000L
	72	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk14_MASK 0x00004000L
	73	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk15_MASK 0x00008000L
	74	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk16_MASK 0x00010000L
	75	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk17_MASK 0x00020000L
	76	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk18_MASK 0x00040000L
	77	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk19_MASK 0x00080000L
	78	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk20_MASK 0x00100000L
	79	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk21_MASK 0x00200000L
	80	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk22_MASK 0x00400000L
	81	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk23_MASK 0x00800000L
	82	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk24_MASK 0x01000000L
	83	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk25_MASK 0x02000000L
	84	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk26_MASK 0x04000000L
	85	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk27_MASK 0x08000000L
	86	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk28_MASK 0x10000000L
	87	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk29_MASK 0x20000000L
	88	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk30_MASK 0x40000000L
	89	#define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk31_MASK 0x80000000L
	90
	91	//DF_NCS_PG0_HardwareAssertMaskHigh
	92	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk0__SHIFT 0x0
	93	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk1__SHIFT 0x1
	94	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk2__SHIFT 0x2
	95	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk3__SHIFT 0x3
	96	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk4__SHIFT 0x4
	97	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk5__SHIFT 0x5
	98	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk6__SHIFT 0x6
	99	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk7__SHIFT 0x7
	100	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk8__SHIFT 0x8
	101	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk9__SHIFT 0x9
	102	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk10__SHIFT 0xa
	103	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk11__SHIFT 0xb
	104	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk12__SHIFT 0xc
	105	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk13__SHIFT 0xd
	106	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk14__SHIFT 0xe
	107	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk15__SHIFT 0xf
	108	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk16__SHIFT 0x10
	109	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk17__SHIFT 0x11
	110	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk18__SHIFT 0x12
	111	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk19__SHIFT 0x13
	112	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk20__SHIFT 0x14
	113	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk21__SHIFT 0x15
	114	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk22__SHIFT 0x16
	115	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk23__SHIFT 0x17
	116	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk24__SHIFT 0x18
	117	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk25__SHIFT 0x19
	118	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk26__SHIFT 0x1a
	119	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk27__SHIFT 0x1b
	120	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk28__SHIFT 0x1c
	121	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk29__SHIFT 0x1d
	122	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk30__SHIFT 0x1e
	123	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk31__SHIFT 0x1f
	124	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk0_MASK 0x00000001L
	125	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk1_MASK 0x00000002L
	126	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk2_MASK 0x00000004L
	127	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk3_MASK 0x00000008L
	128	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk4_MASK 0x00000010L
	129	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk5_MASK 0x00000020L
	130	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk6_MASK 0x00000040L
	131	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk7_MASK 0x00000080L
	132	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk8_MASK 0x00000100L
	133	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk9_MASK 0x00000200L
	134	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk10_MASK 0x00000400L
	135	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk11_MASK 0x00000800L
	136	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk12_MASK 0x00001000L
	137	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk13_MASK 0x00002000L
	138	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk14_MASK 0x00004000L
	139	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk15_MASK 0x00008000L
	140	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk16_MASK 0x00010000L
	141	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk17_MASK 0x00020000L
	142	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk18_MASK 0x00040000L
	143	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk19_MASK 0x00080000L
	144	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk20_MASK 0x00100000L
	145	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk21_MASK 0x00200000L
	146	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk22_MASK 0x00400000L
	147	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk23_MASK 0x00800000L
	148	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk24_MASK 0x01000000L
	149	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk25_MASK 0x02000000L
	150	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk26_MASK 0x04000000L
	151	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk27_MASK 0x08000000L
	152	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk28_MASK 0x10000000L
	153	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk29_MASK 0x20000000L
	154	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk30_MASK 0x40000000L
	155	#define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk31_MASK 0x80000000L
	156
	157	#endif

drivers/gpu/drm/amd/include/kgd_pp_interface.h+2−0

@@ -139,6 +139,8 @@ enum amd_pp_sensors { · 138 unmodified lines
139	AMDGPU_PP_SENSOR_MIN_FAN_RPM,	139	AMDGPU_PP_SENSOR_MIN_FAN_RPM,
140	AMDGPU_PP_SENSOR_MAX_FAN_RPM,	140	AMDGPU_PP_SENSOR_MAX_FAN_RPM,
141	AMDGPU_PP_SENSOR_VCN_POWER_STATE,	141	AMDGPU_PP_SENSOR_VCN_POWER_STATE,
		142	AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
		143	AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
142	};	144	};
143		145
144	enum amd_pp_task {	146	enum amd_pp_task {

drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c+8−2

 	switch (idx) {
 	case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
-		*((uint32_t *)value) = hwmgr->pstate_sclk;
+		*((uint32_t *)value) = hwmgr->pstate_sclk * 100;
 		return 0;
 	case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
-		*((uint32_t *)value) = hwmgr->pstate_mclk;
+		*((uint32_t *)value) = hwmgr->pstate_mclk * 100;
+		return 0;
+	case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK:
+		*((uint32_t *)value) = hwmgr->pstate_sclk_peak * 100;
+		return 0;
+	case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK:
+		*((uint32_t *)value) = hwmgr->pstate_mclk_peak * 100;
 		return 0;
 	case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
 		*((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMinRPM;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c+13−3

 	return 0;
 }
+static void smu10_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr)
+{
+	hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK;
+	hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK;
+	smum_send_msg_to_smc(hwmgr,
+			     PPSMC_MSG_GetMaxGfxclkFrequency,
+			     &hwmgr->pstate_sclk_peak);
+	hwmgr->pstate_mclk_peak = SMU10_UMD_PSTATE_PEAK_FCLK;
+}
 static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 {
 	struct amdgpu_device *adev = hwmgr->adev;
 			return ret;
 	}
+	smu10_populate_umdpstate_clocks(hwmgr);
 	return 0;
 }
 	hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
-	hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK * 100;
-	hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK * 100;
 	/* enable the pp_od_clk_voltage sysfs file */
 	hwmgr->od_enabled = 1;
 	/* disabled fine grain tuning function by default */

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c+63−13

@@ -1501,6 +1501,65 @@ static int smu7_populate_edc_leakage_registers(struct pp_hwmgr *hwmgr) · 1500 unmodified lines
1501	return ret;	1501	return ret;
1502	}	1502	}
1503		1503
		1504	static void smu7_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr)
		1505	{
		1506	struct smu7_hwmgr data = (struct smu7_hwmgr )(hwmgr->backend);
		1507	struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;
		1508	struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk =
		1509	hwmgr->dyn_state.vddc_dependency_on_sclk;
		1510	struct phm_ppt_v1_information *table_info =
		1511	(struct phm_ppt_v1_information *)(hwmgr->pptable);
		1512	struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk =
		1513	table_info->vdd_dep_on_sclk;
		1514	int32_t tmp_sclk, count, percentage;
		1515
		1516	if (golden_dpm_table->mclk_table.count == 1) {
		1517	percentage = 70;
		1518	hwmgr->pstate_mclk = golden_dpm_table->mclk_table.dpm_levels[0].value;
		1519	} else {
		1520	percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value /
		1521	golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
		1522	hwmgr->pstate_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value;
		1523	}
		1524
		1525	tmp_sclk = hwmgr->pstate_mclk * percentage / 100;
		1526
		1527	if (hwmgr->pp_table_version == PP_TABLE_V0) {
		1528	for (count = vddc_dependency_on_sclk->count - 1; count >= 0; count--) {
		1529	if (tmp_sclk >= vddc_dependency_on_sclk->entries[count].clk) {
		1530	hwmgr->pstate_sclk = vddc_dependency_on_sclk->entries[count].clk;
		1531	break;
		1532	}
		1533	}
		1534	if (count < 0)
		1535	hwmgr->pstate_sclk = vddc_dependency_on_sclk->entries[0].clk;
		1536
		1537	hwmgr->pstate_sclk_peak =
		1538	vddc_dependency_on_sclk->entries[vddc_dependency_on_sclk->count - 1].clk;
		1539	} else if (hwmgr->pp_table_version == PP_TABLE_V1) {
		1540	for (count = vdd_dep_on_sclk->count - 1; count >= 0; count--) {
		1541	if (tmp_sclk >= vdd_dep_on_sclk->entries[count].clk) {
		1542	hwmgr->pstate_sclk = vdd_dep_on_sclk->entries[count].clk;
		1543	break;
		1544	}
		1545	}
		1546	if (count < 0)
		1547	hwmgr->pstate_sclk = vdd_dep_on_sclk->entries[0].clk;
		1548
		1549	hwmgr->pstate_sclk_peak =
		1550	vdd_dep_on_sclk->entries[vdd_dep_on_sclk->count - 1].clk;
		1551	}
		1552
		1553	hwmgr->pstate_mclk_peak =
		1554	golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
		1555
		1556	/* make sure the output is in Mhz */
		1557	hwmgr->pstate_sclk /= 100;
		1558	hwmgr->pstate_mclk /= 100;
		1559	hwmgr->pstate_sclk_peak /= 100;
		1560	hwmgr->pstate_mclk_peak /= 100;
		1561	}
		1562
1504	static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)	1563	static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1505	{	1564	{
1506	int tmp_result = 0;	1565	int tmp_result = 0;
@@ -1625,6 +1684,8 @@ static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr) · 118 unmodified lines
1625	PP_ASSERT_WITH_CODE((0 == tmp_result),	1684	PP_ASSERT_WITH_CODE((0 == tmp_result),
1626	"pcie performance request failed!", result = tmp_result);	1685	"pcie performance request failed!", result = tmp_result);
1627		1686
		1687	smu7_populate_umdpstate_clocks(hwmgr);
		1688
1628	return 0;	1689	return 0;
1629	}	1690	}
1630		1691
@@ -3143,15 +3204,12 @@ static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_le · 1512 unmodified lines
3143	for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;	3204	for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
3144	count >= 0; count--) {	3205	count >= 0; count--) {
3145	if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) {	3206	if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) {
3146	tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk;
3147	*sclk_mask = count;	3207	*sclk_mask = count;
3148	break;	3208	break;
3149	}	3209	}
3150	}	3210	}
3151	if (count < 0 \|\| level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {	3211	if (count < 0 \|\| level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
3152	*sclk_mask = 0;	3212	*sclk_mask = 0;
3153	tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk;
3154	}
3155		3213
3156	if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)	3214	if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
3157	*sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;	3215	*sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
@@ -3161,15 +3219,12 @@ static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_le · 3 unmodified lines
3161		3219
3162	for (count = table_info->vdd_dep_on_sclk->count-1; count >= 0; count--) {	3220	for (count = table_info->vdd_dep_on_sclk->count-1; count >= 0; count--) {
3163	if (tmp_sclk >= table_info->vdd_dep_on_sclk->entries[count].clk) {	3221	if (tmp_sclk >= table_info->vdd_dep_on_sclk->entries[count].clk) {
3164	tmp_sclk = table_info->vdd_dep_on_sclk->entries[count].clk;
3165	*sclk_mask = count;	3222	*sclk_mask = count;
3166	break;	3223	break;
3167	}	3224	}
3168	}	3225	}
3169	if (count < 0 \|\| level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {	3226	if (count < 0 \|\| level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
3170	*sclk_mask = 0;	3227	*sclk_mask = 0;
3171	tmp_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3172	}
3173		3228
3174	if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)	3229	if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
3175	*sclk_mask = table_info->vdd_dep_on_sclk->count - 1;	3230	*sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
@@ -3181,8 +3236,6 @@ static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_le · 5 unmodified lines
3181	*mclk_mask = golden_dpm_table->mclk_table.count - 1;	3236	*mclk_mask = golden_dpm_table->mclk_table.count - 1;
3182		3237
3183	*pcie_mask = data->dpm_table.pcie_speed_table.count - 1;	3238	*pcie_mask = data->dpm_table.pcie_speed_table.count - 1;
3184	hwmgr->pstate_sclk = tmp_sclk;
3185	hwmgr->pstate_mclk = tmp_mclk;
3186		3239
3187	return 0;	3240	return 0;
3188	}	3241	}
@@ -3195,9 +3248,6 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr, · 6 unmodified lines
3195	uint32_t mclk_mask = 0;	3248	uint32_t mclk_mask = 0;
3196	uint32_t pcie_mask = 0;	3249	uint32_t pcie_mask = 0;
3197		3250
3198	if (hwmgr->pstate_sclk == 0)
3199	smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
3200
3201	switch (level) {	3251	switch (level) {
3202	case AMD_DPM_FORCED_LEVEL_HIGH:	3252	case AMD_DPM_FORCED_LEVEL_HIGH:
3203	ret = smu7_force_dpm_highest(hwmgr);	3253	ret = smu7_force_dpm_highest(hwmgr);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c+14−2

 	data->acp_boot_level = 0xff;
 }
+static void smu8_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr)
+{
+	struct phm_clock_voltage_dependency_table *table =
+				hwmgr->dyn_state.vddc_dependency_on_sclk;
+	hwmgr->pstate_sclk = table->entries[0].clk / 100;
+	hwmgr->pstate_mclk = 0;
+	hwmgr->pstate_sclk_peak = table->entries[table->count - 1].clk / 100;
+	hwmgr->pstate_mclk_peak = 0;
+}
 static int smu8_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 {
 	smu8_program_voting_clients(hwmgr);
 	smu8_program_bootup_state(hwmgr);
 	smu8_reset_acp_boot_level(hwmgr);
+	smu8_populate_umdpstate_clocks(hwmgr);
 	return 0;
 }
 	data->sclk_dpm.soft_min_clk = table->entries[0].clk;
 	data->sclk_dpm.hard_min_clk = table->entries[0].clk;
-	hwmgr->pstate_sclk = table->entries[0].clk;
-	hwmgr->pstate_mclk = 0;
 	level = smu8_get_max_sclk_level(hwmgr) - 1;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c+26−5

 	return 0;
 }
+static void vega10_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr)
+{
+	struct phm_ppt_v2_information *table_info =
+			(struct phm_ppt_v2_information *)(hwmgr->pptable);
+	if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL &&
+	    table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) {
+		hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk;
+		hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk;
+	} else {
+		hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
+		hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[0].clk;
+	}
+	hwmgr->pstate_sclk_peak = table_info->vdd_dep_on_sclk->entries[table_info->vdd_dep_on_sclk->count - 1].clk;
+	hwmgr->pstate_mclk_peak = table_info->vdd_dep_on_mclk->entries[table_info->vdd_dep_on_mclk->count - 1].clk;
+	/* make sure the output is in Mhz */
+	hwmgr->pstate_sclk /= 100;
+	hwmgr->pstate_mclk /= 100;
+	hwmgr->pstate_sclk_peak /= 100;
+	hwmgr->pstate_mclk_peak /= 100;
+}
 static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 {
 	struct vega10_hwmgr *data = hwmgr->backend;
 				    result = tmp_result);
 	}
+	vega10_populate_umdpstate_clocks(hwmgr);
 	return result;
 }
 		*sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL;
 		*soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL;
 		*mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL;
-		hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk;
-		hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk;
 	}
 	if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
 	uint32_t mclk_mask = 0;
 	uint32_t soc_mask = 0;
-	if (hwmgr->pstate_sclk == 0)
-		vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
 	switch (level) {
 	case AMD_DPM_FORCED_LEVEL_HIGH:
 		ret = vega10_force_dpm_highest(hwmgr);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c+22−0

@@ -1026,6 +1026,25 @@ static int vega12_get_all_clock_ranges(struct pp_hwmgr *hwmgr) · 1025 unmodified lines
1026	return 0;	1026	return 0;
1027	}	1027	}
1028		1028
		1029	static void vega12_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr)
		1030	{
		1031	struct vega12_hwmgr data = (struct vega12_hwmgr )(hwmgr->backend);
		1032	struct vega12_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
		1033	struct vega12_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
		1034
		1035	if (gfx_dpm_table->count > VEGA12_UMD_PSTATE_GFXCLK_LEVEL &&
		1036	mem_dpm_table->count > VEGA12_UMD_PSTATE_MCLK_LEVEL) {
		1037	hwmgr->pstate_sclk = gfx_dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
		1038	hwmgr->pstate_mclk = mem_dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
		1039	} else {
		1040	hwmgr->pstate_sclk = gfx_dpm_table->dpm_levels[0].value;
		1041	hwmgr->pstate_mclk = mem_dpm_table->dpm_levels[0].value;
		1042	}
		1043
		1044	hwmgr->pstate_sclk_peak = gfx_dpm_table->dpm_levels[gfx_dpm_table->count].value;
		1045	hwmgr->pstate_mclk_peak = mem_dpm_table->dpm_levels[mem_dpm_table->count].value;
		1046	}
		1047
1029	static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr)	1048	static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1030	{	1049	{
1031	int tmp_result, result = 0;	1050	int tmp_result, result = 0;
@@ -1077,6 +1096,9 @@ static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr) · 45 unmodified lines
1077	PP_ASSERT_WITH_CODE(!result,	1096	PP_ASSERT_WITH_CODE(!result,
1078	"Failed to setup default DPM tables!",	1097	"Failed to setup default DPM tables!",
1079	return result);	1098	return result);
		1099
		1100	vega12_populate_umdpstate_clocks(hwmgr);
		1101
1080	return result;	1102	return result;
1081	}	1103	}
1082		1104

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c+7−13

 	return 0;
 }
-static int vega20_populate_umdpstate_clocks(
+static void vega20_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr)
-		struct pp_hwmgr *hwmgr)
 {
 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 	struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table);
 	struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table);
-	hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value;
-	hwmgr->pstate_mclk = mem_table->dpm_levels[0].value;
 	if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
 	    mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
 		hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
 		hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
+	} else {
+		hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value;
+		hwmgr->pstate_mclk = mem_table->dpm_levels[0].value;
 	}
-	hwmgr->pstate_sclk = hwmgr->pstate_sclk * 100;
+	hwmgr->pstate_sclk_peak = gfx_table->dpm_levels[gfx_table->count - 1].value;
-	hwmgr->pstate_mclk = hwmgr->pstate_mclk * 100;
+	hwmgr->pstate_mclk_peak = mem_table->dpm_levels[mem_table->count - 1].value;
-	return 0;
 }
 static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr,
 			"[EnableDPMTasks] Failed to initialize odn settings!",
 			return result);
-	result = vega20_populate_umdpstate_clocks(hwmgr);
+	vega20_populate_umdpstate_clocks(hwmgr);
-	PP_ASSERT_WITH_CODE(!result,
-			"[EnableDPMTasks] Failed to populate umdpstate clocks!",
-			return result);
 	result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetPptLimit,
 			POWER_SOURCE_AC << 16, &hwmgr->default_power_limit);

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h+2−0

@@ -809,6 +809,8 @@ struct pp_hwmgr { · 808 unmodified lines
809	uint32_t workload_prority[Workload_Policy_Max];	809	uint32_t workload_prority[Workload_Policy_Max];
810	uint32_t workload_setting[Workload_Policy_Max];	810	uint32_t workload_setting[Workload_Policy_Max];
811	bool gfxoff_state_changed_by_workload;	811	bool gfxoff_state_changed_by_workload;
		812	uint32_t pstate_sclk_peak;
		813	uint32_t pstate_mclk_peak;
812	};	814	};
813		815
814	int hwmgr_early_init(struct pp_hwmgr *hwmgr);	816	int hwmgr_early_init(struct pp_hwmgr *hwmgr);

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c+4−6

 	/* allocate space for watermarks table */
 	r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
-			sizeof(Watermarks_t),
+			sizeof(Watermarks_t), PAGE_SIZE,
-			PAGE_SIZE,
+			AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT,
-			AMDGPU_GEM_DOMAIN_VRAM,
 			&priv->smu_tables.entry[SMU10_WMTABLE].handle,
 			&priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,
 			&priv->smu_tables.entry[SMU10_WMTABLE].table);
 	/* allocate space for watermarks table */
 	r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
-			sizeof(DpmClocks_t),
+			sizeof(DpmClocks_t), PAGE_SIZE,
-			PAGE_SIZE,
+			AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT,
-			AMDGPU_GEM_DOMAIN_VRAM,
 			&priv->smu_tables.entry[SMU10_CLOCKTABLE].handle,
 			&priv->smu_tables.entry[SMU10_CLOCKTABLE].mc_addr,
 			&priv->smu_tables.entry[SMU10_CLOCKTABLE].table);

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c+8−0

@@ -2473,6 +2473,14 @@ static int smu_read_sensor(void *handle, · 2472 unmodified lines
2473	((uint32_t )data) = pstate_table->uclk_pstate.standard * 100;	2473	((uint32_t )data) = pstate_table->uclk_pstate.standard * 100;
2474	*size = 4;	2474	*size = 4;
2475	break;	2475	break;
		2476	case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK:
		2477	((uint32_t )data) = pstate_table->gfxclk_pstate.peak * 100;
		2478	*size = 4;
		2479	break;
		2480	case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK:
		2481	((uint32_t )data) = pstate_table->uclk_pstate.peak * 100;
		2482	*size = 4;
		2483	break;
2476	case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:	2484	case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2477	ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data);	2485	ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data);
2478	*size = 8;	2486	*size = 8;

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h+0−5

 				   enum smu_clk_type clk_type,
 				   struct smu_13_0_dpm_table *single_dpm_table);
-int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
-				  enum smu_clk_type clk_type,
-				  uint32_t *min_value,
-				  uint32_t *max_value);
 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu);
 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c+2−41

@@ -1261,7 +1261,8 @@ int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu, · 1260 unmodified lines
1261	uint32_t speed)	1261	uint32_t speed)
1262	{	1262	{
1263	struct amdgpu_device *adev = smu->adev;	1263	struct amdgpu_device *adev = smu->adev;
1264	uint32_t tach_period, crystal_clock_freq;	1264	uint32_t crystal_clock_freq = 2500;
		1265	uint32_t tach_period;
1265	int ret;	1266	int ret;
1266		1267
1267	if (!speed)	1268	if (!speed)
@@ -1271,7 +1272,6 @@ int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu, · 3 unmodified lines
1271	if (ret)	1272	if (ret)
1272	return ret;	1273	return ret;
1273		1274
1274	crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1275	tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);	1275	tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1276	WREG32_SOC15(THM, 0, regCG_TACH_CTRL,	1276	WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1277	REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),	1277	REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
@@ -2064,45 +2064,6 @@ int smu_v13_0_set_single_dpm_table(struct smu_context *smu, · 786 unmodified lines
2064	return 0;	2064	return 0;
2065	}	2065	}
2066		2066
2067	int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
2068	enum smu_clk_type clk_type,
2069	uint32_t *min_value,
2070	uint32_t *max_value)
2071	{
2072	uint32_t level_count = 0;
2073	int ret = 0;
2074
2075	if (!min_value && !max_value)
2076	return -EINVAL;
2077
2078	if (min_value) {
2079	/* by default, level 0 clock value as min value */
2080	ret = smu_v13_0_get_dpm_freq_by_index(smu,
2081	clk_type,
2082	0,
2083	min_value);
2084	if (ret)
2085	return ret;
2086	}
2087
2088	if (max_value) {
2089	ret = smu_v13_0_get_dpm_level_count(smu,
2090	clk_type,
2091	&level_count);
2092	if (ret)
2093	return ret;
2094
2095	ret = smu_v13_0_get_dpm_freq_by_index(smu,
2096	clk_type,
2097	level_count - 1,
2098	max_value);
2099	if (ret)
2100	return ret;
2101	}
2102
2103	return ret;
2104	}
2105
2106	int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)	2067	int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
2107	{	2068	{
2108	struct amdgpu_device *adev = smu->adev;	2069	struct amdgpu_device *adev = smu->adev;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c+4−2

 	FEA_MAP(SOC_PCC),
 	[SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
 	[SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
+	[SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT},
 };
 static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,			WORKLOAD_PPLIB_VR_BIT),
 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,		WORKLOAD_PPLIB_COMPUTE_BIT),
 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
+	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D,		WORKLOAD_PPLIB_WINDOW_3D_BIT),
 };
 static const uint8_t smu_v13_0_0_throttler_map[] = {
 			title[0], title[1], title[2], title[3], title[4], title[5],
 			title[6], title[7], title[8], title[9]);
-	for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
+	for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
 		/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
 		workload_type = smu_cmn_to_asic_specific_index(smu,
 							       CMN2ASIC_MAPPING_WORKLOAD,
 	smu->power_profile_mode = input[size];
-	if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
+	if (smu->power_profile_mode >= PP_SMC_POWER_PROFILE_COUNT) {
 		dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
 		return -EINVAL;
 	}

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c+1−0

@@ -192,6 +192,7 @@ static struct cmn2asic_mapping smu_v13_0_7_feature_mask_map[SMU_FEATURE_COUNT] = · 191 unmodified lines
192	FEA_MAP(SOC_PCC),	192	FEA_MAP(SOC_PCC),
193	[SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT},	193	[SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
194	[SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},	194	[SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
		195	[SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT},
195	};	196	};
196		197
197	static struct cmn2asic_mapping smu_v13_0_7_table_map[SMU_TABLE_COUNT] = {	198	static struct cmn2asic_mapping smu_v13_0_7_table_map[SMU_TABLE_COUNT] = {

drivers/gpu/drm/radeon/atombios.h+5−5

@@ -4020,7 +4020,7 @@ typedef struct _ATOM_DISPLAY_OBJECT_PATH · 4019 unmodified lines
4020	USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH	4020	USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH
4021	USHORT usConnObjectId; //Connector Object ID	4021	USHORT usConnObjectId; //Connector Object ID
4022	USHORT usGPUObjectId; //GPU ID	4022	USHORT usGPUObjectId; //GPU ID
4023	USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector.	4023	USHORT usGraphicObjIds[]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector.
4024	}ATOM_DISPLAY_OBJECT_PATH;	4024	}ATOM_DISPLAY_OBJECT_PATH;
4025		4025
4026	typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH	4026	typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH
@@ -4037,7 +4037,7 @@ typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE · 10 unmodified lines
4037	UCHAR ucNumOfDispPath;	4037	UCHAR ucNumOfDispPath;
4038	UCHAR ucVersion;	4038	UCHAR ucVersion;
4039	UCHAR ucPadding[2];	4039	UCHAR ucPadding[2];
4040	ATOM_DISPLAY_OBJECT_PATH asDispPath[1];	4040	ATOM_DISPLAY_OBJECT_PATH asDispPath[];
4041	}ATOM_DISPLAY_OBJECT_PATH_TABLE;	4041	}ATOM_DISPLAY_OBJECT_PATH_TABLE;
4042		4042
4043		4043
@@ -4053,7 +4053,7 @@ typedef struct _ATOM_OBJECT_TABLE //Above 4 object table · 9 unmodified lines
4053	{	4053	{
4054	UCHAR ucNumberOfObjects;	4054	UCHAR ucNumberOfObjects;
4055	UCHAR ucPadding[3];	4055	UCHAR ucPadding[3];
4056	ATOM_OBJECT asObjects[1];	4056	ATOM_OBJECT asObjects[];
4057	}ATOM_OBJECT_TABLE;	4057	}ATOM_OBJECT_TABLE;
4058		4058
4059	typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure	4059	typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure
@@ -4615,7 +4615,7 @@ typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3 · 555 unmodified lines
4615	UCHAR ucPhaseDelay; // phase delay in unit of micro second	4615	UCHAR ucPhaseDelay; // phase delay in unit of micro second
4616	UCHAR ucReserved;	4616	UCHAR ucReserved;
4617	ULONG ulGpioMaskVal; // GPIO Mask value	4617	ULONG ulGpioMaskVal; // GPIO Mask value
4618	VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1];	4618	VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[];
4619	}ATOM_GPIO_VOLTAGE_OBJECT_V3;	4619	}ATOM_GPIO_VOLTAGE_OBJECT_V3;
4620		4620
4621	typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3	4621	typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
@@ -7964,7 +7964,7 @@ typedef struct { · 3342 unmodified lines
7964		7964
7965	typedef struct {	7965	typedef struct {
7966	VFCT_IMAGE_HEADER VbiosHeader;	7966	VFCT_IMAGE_HEADER VbiosHeader;
7967	UCHAR VbiosContent[1];	7967	UCHAR VbiosContent[];
7968	}GOP_VBIOS_CONTENT;	7968	}GOP_VBIOS_CONTENT;
7969		7969
7970	typedef struct {	7970	typedef struct {

include/drm/display/drm_dp.h+6−0

 #define DP_DOWNSPREAD_CTRL		    0x107
 # define DP_SPREAD_AMP_0_5		    (1 << 4)
+# define DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE  (1 << 6)
 # define DP_MSA_TIMING_PAR_IGNORE_EN	    (1 << 7) /* eDP */
 #define DP_MAIN_LINK_CHANNEL_CODING_SET	    0x108
 # define DP_VSC_EXT_CEA_SDP_SUPPORTED			(1 << 6)  /* DP 1.4 */
 # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED		(1 << 7)  /* DP 1.4 */
+#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1         0x2214 /* 2.0 E11 */
+# define DP_ADAPTIVE_SYNC_SDP_SUPPORTED    (1 << 0)
+# define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1)
+# define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED  (1 << 4)
 #define DP_128B132B_SUPPORTED_LINK_RATES       0x2215 /* 2.0 */
 # define DP_UHBR10                             (1 << 0)
 # define DP_UHBR20                             (1 << 1)

include/uapi/drm/amdgpu_drm.h+6−0

 	#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK		0x8
 	/* Subquery id: Query GPU stable pstate memory clock */
 	#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK		0x9
+	/* Subquery id: Query GPU peak pstate shader clock */
+	#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK			0xa
+	/* Subquery id: Query GPU peak pstate memory clock */
+	#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK			0xb
 /* Number of VRAM page faults on CPU access. */
 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS	0x1E
 #define AMDGPU_INFO_VRAM_LOST_COUNTER		0x1F
 	__u32 pa_sc_tile_steering_override;
 	/* disabled TCCs */
 	__u64 tcc_disabled_mask;
+	__u64 min_engine_clock;
+	__u64 min_memory_clock;
 };
 struct drm_amdgpu_info_hw_ip {

Merge tag 'amd-drm-next-6.3-2023-01-06' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

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