History

Merge tag 'drm-next-2023-08-30' of git://anongit.freedesktop.org/drm/drm

Pull drm updates from Dave Airlie: "The drm core grew a new generic gpu virtual address manager, and new execution locking helpers. These are used by nouveau now to provide uAPI support for the userspace Vulkan driver. AMD had a bunch of new IP core support, loads of refactoring around fbdev, but mostly just the usual amount of stuff across the board. core: - fix gfp flags in drmm_kmalloc gpuva: - add new generic GPU VA manager (for nouveau initially) syncobj: - add new DRM_IOCTL_SYNCOBJ_EVENTFD ioctl dma-buf: - acquire resv lock for mmap() in exporters - support dma-buf self import automatically - docs fixes backlight: - fix fbdev interactions atomic: - improve logging prime: - remove struct gem_prim_mmap plus driver updates gem: - drm_exec: add locking over multiple GEM objects - fix lockdep checking fbdev: - make fbdev userspace interfaces optional - use linux device instead of fbdev device - use deferred i/o helper macros in various drivers - Make FB core selectable without drivers - Remove obsolete flags FBINFO_DEFAULT and FBINFO_FLAG_DEFAULT - Add helper macros and Kconfig tokens for DMA-allocated framebuffer ttm: - support init_on_free - swapout fixes panel: - panel-edp: Support AUO B116XAB01.4 - Support Visionox R66451 plus DT bindings - ld9040: - Backlight support - magic improved - Kconfig fix - Convert to of_device_get_match_data() - Fix Kconfig dependencies - simple: - Set bpc value to fix warning - Set connector type for AUO T215HVN01 - Support Innolux G156HCE-L01 plus DT bindings - ili9881: Support TDO TL050HDV35 LCD panel plus DT bindings - startek: Support KD070FHFID015 MIPI-DSI panel plus DT bindings - sitronix-st7789v: - Support Inanbo T28CP45TN89 plus DT bindings - Support EDT ET028013DMA plus DT bindings - Various cleanups - edp: Add timings for N140HCA-EAC - Allow panels and touchscreens to power sequence together - Fix Innolux G156HCE-L01 LVDS clock bridge: - debugfs for chains support - dw-hdmi: - Improve support for YUV420 bus format - CEC suspend/resume - update EDID on HDMI detect - dw-mipi-dsi: Fix enable/disable of DSI controller - lt9611uxc: Use MODULE_FIRMWARE() - ps8640: Remove broken EDID code - samsung-dsim: Fix command transfer - tc358764: - Handle HS/VS polarity - Use BIT() macro - Various cleanups - adv7511: Fix low refresh rate - anx7625: - Switch to macros instead of hardcoded values - locking fixes - tc358767: fix hardware delays - sitronix-st7789v: - Support panel orientation - Support rotation property - Add support for Jasonic JT240MHQS-HWT-EK-E3 plus DT bindings amdgpu: - SDMA 6.1.0 support - HDP 6.1 support - SMUIO 14.0 support - PSP 14.0 support - IH 6.1 support - Lots of checkpatch cleanups - GFX 9.4.3 updates - Add USB PD and IFWI flashing documentation - GPUVM updates - RAS fixes - DRR fixes - FAMS fixes - Virtual display fixes - Soft IH fixes - SMU13 fixes - Rework PSP firmware loading for other IPs - Kernel doc fixes - DCN 3.0.1 fixes - LTTPR fixes - DP MST fixes - DCN 3.1.6 fixes - SMU 13.x fixes - PSP 13.x fixes - SubVP fixes - GC 9.4.3 fixes - Display bandwidth calculation fixes - VCN4 secure submission fixes - Allow building DC on RISC-V - Add visible FB info to bo_print_info - HBR3 fixes - GFX9 MCBP fix - GMC10 vmhub index fix - GMC11 vmhub index fix - Create a new doorbell manager - SR-IOV fixes - initial freesync panel replay support - revert zpos properly until igt regression is fixeed - use TTM to manage doorbell BAR - Expose both current and average power via hwmon if supported amdkfd: - Cleanup CRIU dma-buf handling - Use KIQ to unmap HIQ - GFX 9.4.3 debugger updates - GFX 9.4.2 debugger fixes - Enable cooperative groups fof gfx11 - SVM fixes - Convert older APUs to use dGPU path like newer APUs - Drop IOMMUv2 path as it is no longer used - TBA fix for aldebaran i915: - ICL+ DSI modeset sequence - HDCP improvements - MTL display fixes and cleanups - HSW/BDW PSR1 restored - Init DDI ports in VBT order - General display refactors - Start using plane scale factor for relative data rate - Use shmem for dpt objects - Expose RPS thresholds in sysfs - Apply GuC SLPC min frequency softlimit correctly - Extend Wa_14015795083 to TGL, RKL, DG1 and ADL - Fix a VMA UAF for multi-gt platform - Do not use stolen on MTL due to HW bug - Check HuC and GuC version compatibility on MTL - avoid infinite GPU waits due to premature release of request memory - Fixes and updates for GSC memory allocation - Display SDVO fixes - Take stolen handling out of FBC code - Make i915_coherent_map_type GT-centric - Simplify shmem_create_from_object map_type msm: - SM6125 MDSS support - DPU: SM6125 DPU support - DSI: runtime PM support, burst mode support - DSI PHY: SM6125 support in 14nm DSI PHY driver - GPU: prepare for a7xx - fix a690 firmware - disable relocs on a6xx and newer radeon: - Lots of checkpatch cleanups ast: - improve device-model detection - Represent BMV as virtual connector - Report DP connection status nouveau: - add new exec/bind interface to support Vulkan - document some getparam ioctls - improve VRAM detection - various fixes/cleanups - workraound DPCD issues ivpu: - MMU updates - debugfs support - Support vpu4 virtio: - add sync object support atmel-hlcdc: - Support inverted pixclock polarity etnaviv: - runtime PM cleanups - hang handling fixes exynos: - use fbdev DMA helpers - fix possible NULL ptr dereference komeda: - always attach encoder omapdrm: - use fbdev DMA helpers ingenic: - kconfig regmap fixes loongson: - support display controller mediatek: - Small mtk-dpi cleanups - DisplayPort: support eDP and aux-bus - Fix coverity issues - Fix potential memory leak if vmap() fail mgag200: - minor fixes mxsfb: - support disabling overlay planes panfrost: - fix sync in IRQ handling ssd130x: - Support per-controller default resolution plus DT bindings - Reduce memory-allocation overhead - Improve intermediate buffer size computation - Fix allocation of temporary buffers - Fix pitch computation - Fix shadow plane allocation tegra: - use fbdev DMA helpers - Convert to devm_platform_ioremap_resource() - support bridge/connector - enable PM tidss: - Support TI AM625 plus DT bindings - Implement new connector model plus driver updates vkms: - improve write back support - docs fixes - support gamma LUT zynqmp-dpsub: - misc fixes" * tag 'drm-next-2023-08-30' of git://anongit.freedesktop.org/drm/drm: (1327 commits) drm/gpuva_mgr: remove unused prev pointer in __drm_gpuva_sm_map() drm/tests/drm_kunit_helpers: Place correct function name in the comment header drm/nouveau: uapi: don't pass NO_PREFETCH flag implicitly drm/nouveau: uvmm: fix unset region pointer on remap drm/nouveau: sched: avoid job races between entities drm/i915: Fix HPD polling, reenabling the output poll work as needed drm: Add an HPD poll helper to reschedule the poll work drm/i915: Fix TLB-Invalidation seqno store drm/ttm/tests: Fix type conversion in ttm_pool_test drm/msm/a6xx: Bail out early if setting GPU OOB fails drm/msm/a6xx: Move LLC accessors to the common header drm/msm/a6xx: Introduce a6xx_llc_read drm/ttm/tests: Require MMU when testing drm/panel: simple: Fix Innolux G156HCE-L01 LVDS clock Revert "Revert "drm/amdgpu/display: change pipe policy for DCN 2.0"" drm/amdgpu: Add memory vendor information drm/amd: flush any delayed gfxoff on suspend entry drm/amdgpu: skip fence GFX interrupts disable/enable for S0ix drm/amdgpu: Remove gfxoff check in GFX v9.4.3 drm/amd/pm: Update pci link speed for smu v13.0.6 ...

Linus Torvalds committed 3 years ago

Commit 461f35f2 parents 53ea7f6 3698a751422 files · +45937 −17413Browse files

Showing the changes to include/uapi (6 of 1422 files). Show all

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6 files
  1. include/uapi/drm/amdgpu_drm.h +6 −1
  2. include/uapi/drm/drm.h +69 −15
  3. include/uapi/drm/drm_mode.h +5 −2
  4. include/uapi/drm/ivpu_accel.h +8 −1
  5. include/uapi/drm/nouveau_drm.h +268 −3
  6. include/uapi/drm/virtgpu_drm.h +15 −1
include/uapi/drm/amdgpu_drm.h+6−1
@@ -94,6 +94,9 @@ extern "C" { · 93 unmodified lines
94 *94 *
95 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines95 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines
96 * for appending data.96 * for appending data.
97 *
98 * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for
99 * signalling user mode queues.
97 */100 */
98#define AMDGPU_GEM_DOMAIN_CPU 0x1101#define AMDGPU_GEM_DOMAIN_CPU 0x1
99#define AMDGPU_GEM_DOMAIN_GTT 0x2102#define AMDGPU_GEM_DOMAIN_GTT 0x2
@@ -101,12 +104,14 @@ extern "C" { · 1 unmodified line
101#define AMDGPU_GEM_DOMAIN_GDS 0x8104#define AMDGPU_GEM_DOMAIN_GDS 0x8
102#define AMDGPU_GEM_DOMAIN_GWS 0x10105#define AMDGPU_GEM_DOMAIN_GWS 0x10
103#define AMDGPU_GEM_DOMAIN_OA 0x20106#define AMDGPU_GEM_DOMAIN_OA 0x20
107#define AMDGPU_GEM_DOMAIN_DOORBELL 0x40
104#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \108#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
105 AMDGPU_GEM_DOMAIN_GTT | \109 AMDGPU_GEM_DOMAIN_GTT | \
106 AMDGPU_GEM_DOMAIN_VRAM | \110 AMDGPU_GEM_DOMAIN_VRAM | \
107 AMDGPU_GEM_DOMAIN_GDS | \111 AMDGPU_GEM_DOMAIN_GDS | \
108 AMDGPU_GEM_DOMAIN_GWS | \112 AMDGPU_GEM_DOMAIN_GWS | \
109 AMDGPU_GEM_DOMAIN_OA)113 AMDGPU_GEM_DOMAIN_OA | \
114 AMDGPU_GEM_DOMAIN_DOORBELL)
110 115
111/* Flag that CPU access will be required for the case of VRAM domain */116/* Flag that CPU access will be required for the case of VRAM domain */
112#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)117#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
include/uapi/drm/drm.h+69−15
@@ -673,8 +673,11 @@ struct drm_gem_open { · 672 unmodified lines
673 * Bitfield of supported PRIME sharing capabilities. See &DRM_PRIME_CAP_IMPORT673 * Bitfield of supported PRIME sharing capabilities. See &DRM_PRIME_CAP_IMPORT
674 * and &DRM_PRIME_CAP_EXPORT.674 * and &DRM_PRIME_CAP_EXPORT.
675 *675 *
676 * PRIME buffers are exposed as dma-buf file descriptors. See676 * Starting from kernel version 6.6, both &DRM_PRIME_CAP_IMPORT and
677 * Documentation/gpu/drm-mm.rst, section "PRIME Buffer Sharing".677 * &DRM_PRIME_CAP_EXPORT are always advertised.
678 *
679 * PRIME buffers are exposed as dma-buf file descriptors.
680 * See :ref:`prime_buffer_sharing`.
678 */681 */
679#define DRM_CAP_PRIME 0x5682#define DRM_CAP_PRIME 0x5
680/**683/**
@@ -682,6 +685,8 @@ struct drm_gem_open { · 1 unmodified line
682 *685 *
683 * If this bit is set in &DRM_CAP_PRIME, the driver supports importing PRIME686 * If this bit is set in &DRM_CAP_PRIME, the driver supports importing PRIME
684 * buffers via the &DRM_IOCTL_PRIME_FD_TO_HANDLE ioctl.687 * buffers via the &DRM_IOCTL_PRIME_FD_TO_HANDLE ioctl.
688 *
689 * Starting from kernel version 6.6, this bit is always set in &DRM_CAP_PRIME.
685 */690 */
686#define DRM_PRIME_CAP_IMPORT 0x1691#define DRM_PRIME_CAP_IMPORT 0x1
687/**692/**
@@ -689,6 +694,8 @@ struct drm_gem_open { · 1 unmodified line
689 *694 *
690 * If this bit is set in &DRM_CAP_PRIME, the driver supports exporting PRIME695 * If this bit is set in &DRM_CAP_PRIME, the driver supports exporting PRIME
691 * buffers via the &DRM_IOCTL_PRIME_HANDLE_TO_FD ioctl.696 * buffers via the &DRM_IOCTL_PRIME_HANDLE_TO_FD ioctl.
697 *
698 * Starting from kernel version 6.6, this bit is always set in &DRM_CAP_PRIME.
692 */699 */
693#define DRM_PRIME_CAP_EXPORT 0x2700#define DRM_PRIME_CAP_EXPORT 0x2
694/**701/**
@@ -756,15 +763,14 @@ struct drm_gem_open { · 61 unmodified lines
756/**763/**
757 * DRM_CAP_SYNCOBJ764 * DRM_CAP_SYNCOBJ
758 *765 *
759 * If set to 1, the driver supports sync objects. See766 * If set to 1, the driver supports sync objects. See :ref:`drm_sync_objects`.
760 * Documentation/gpu/drm-mm.rst, section "DRM Sync Objects".
761 */767 */
762#define DRM_CAP_SYNCOBJ 0x13768#define DRM_CAP_SYNCOBJ 0x13
763/**769/**
764 * DRM_CAP_SYNCOBJ_TIMELINE770 * DRM_CAP_SYNCOBJ_TIMELINE
765 *771 *
766 * If set to 1, the driver supports timeline operations on sync objects. See772 * If set to 1, the driver supports timeline operations on sync objects. See
767 * Documentation/gpu/drm-mm.rst, section "DRM Sync Objects".773 * :ref:`drm_sync_objects`.
768 */774 */
769#define DRM_CAP_SYNCOBJ_TIMELINE 0x14775#define DRM_CAP_SYNCOBJ_TIMELINE 0x14
770 776
@@ -909,6 +915,27 @@ struct drm_syncobj_timeline_wait { · 138 unmodified lines
909 __u32 pad;915 __u32 pad;
910};916};
911 917
918/**
919 * struct drm_syncobj_eventfd
920 * @handle: syncobj handle.
921 * @flags: Zero to wait for the point to be signalled, or
922 * &DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE to wait for a fence to be
923 * available for the point.
924 * @point: syncobj timeline point (set to zero for binary syncobjs).
925 * @fd: Existing eventfd to sent events to.
926 * @pad: Must be zero.
927 *
928 * Register an eventfd to be signalled by a syncobj. The eventfd counter will
929 * be incremented by one.
930 */
931struct drm_syncobj_eventfd {
932 __u32 handle;
933 __u32 flags;
934 __u64 point;
935 __s32 fd;
936 __u32 pad;
937};
938
912 939
913struct drm_syncobj_array {940struct drm_syncobj_array {
914 __u64 handles;941 __u64 handles;
@@ -1169,6 +1196,8 @@ extern "C" { · 254 unmodified lines
1169 */1196 */
1170#define DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2)1197#define DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2)
1171 1198
1199#define DRM_IOCTL_SYNCOBJ_EVENTFD DRM_IOWR(0xCF, struct drm_syncobj_eventfd)
1200
1172/*1201/*
1173 * Device specific ioctls should only be in their respective headers1202 * Device specific ioctls should only be in their respective headers
1174 * The device specific ioctl range is from 0x40 to 0x9f.1203 * The device specific ioctl range is from 0x40 to 0x9f.
@@ -1180,25 +1209,50 @@ extern "C" { · 5 unmodified lines
1180#define DRM_COMMAND_BASE 0x401209#define DRM_COMMAND_BASE 0x40
1181#define DRM_COMMAND_END 0xA01210#define DRM_COMMAND_END 0xA0
1182 1211
1183/*1212/**
1184 * Header for events written back to userspace on the drm fd. The1213 * struct drm_event - Header for DRM events
1185 * type defines the type of event, the length specifies the total1214 * @type: event type.
1186 * length of the event (including the header), and user_data is1215 * @length: total number of payload bytes (including header).
1187 * typically a 64 bit value passed with the ioctl that triggered the
1188 * event. A read on the drm fd will always only return complete
1189 * events, that is, if for example the read buffer is 100 bytes, and
1190 * there are two 64 byte events pending, only one will be returned.
1191 *1216 *
1192 * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and1217 * This struct is a header for events written back to user-space on the DRM FD.
1193 * up are chipset specific.1218 * A read on the DRM FD will always only return complete events: e.g. if the
1219 * read buffer is 100 bytes large and there are two 64 byte events pending,
1220 * only one will be returned.
1221 *
1222 * Event types 0 - 0x7fffffff are generic DRM events, 0x80000000 and
1223 * up are chipset specific. Generic DRM events include &DRM_EVENT_VBLANK,
1224 * &DRM_EVENT_FLIP_COMPLETE and &DRM_EVENT_CRTC_SEQUENCE.
1194 */1225 */
1195struct drm_event {1226struct drm_event {
1196 __u32 type;1227 __u32 type;
1197 __u32 length;1228 __u32 length;
1198};1229};
1199 1230
1231/**
1232 * DRM_EVENT_VBLANK - vertical blanking event
1233 *
1234 * This event is sent in response to &DRM_IOCTL_WAIT_VBLANK with the
1235 * &_DRM_VBLANK_EVENT flag set.
1236 *
1237 * The event payload is a struct drm_event_vblank.
1238 */
1200#define DRM_EVENT_VBLANK 0x011239#define DRM_EVENT_VBLANK 0x01
1240/**
1241 * DRM_EVENT_FLIP_COMPLETE - page-flip completion event
1242 *
1243 * This event is sent in response to an atomic commit or legacy page-flip with
1244 * the &DRM_MODE_PAGE_FLIP_EVENT flag set.
1245 *
1246 * The event payload is a struct drm_event_vblank.
1247 */
1201#define DRM_EVENT_FLIP_COMPLETE 0x021248#define DRM_EVENT_FLIP_COMPLETE 0x02
1249/**
1250 * DRM_EVENT_CRTC_SEQUENCE - CRTC sequence event
1251 *
1252 * This event is sent in response to &DRM_IOCTL_CRTC_QUEUE_SEQUENCE.
1253 *
1254 * The event payload is a struct drm_event_crtc_sequence.
1255 */
1202#define DRM_EVENT_CRTC_SEQUENCE 0x031256#define DRM_EVENT_CRTC_SEQUENCE 0x03
1203 1257
1204struct drm_event_vblank {1258struct drm_event_vblank {
include/uapi/drm/drm_mode.h+5−2
@@ -488,6 +488,9 @@ struct drm_mode_get_connector { · 487 unmodified lines
488 * This is not an object ID. This is a per-type connector number. Each488 * This is not an object ID. This is a per-type connector number. Each
489 * (type, type_id) combination is unique across all connectors of a DRM489 * (type, type_id) combination is unique across all connectors of a DRM
490 * device.490 * device.
491 *
492 * The (type, type_id) combination is not a stable identifier: the
493 * type_id can change depending on the driver probe order.
491 */494 */
492 __u32 connector_type_id;495 __u32 connector_type_id;
493 496
@@ -883,7 +886,7 @@ struct hdr_metadata_infoframe { · 389 unmodified lines
883 */886 */
884 struct {887 struct {
885 __u16 x, y;888 __u16 x, y;
886 } display_primaries[3];889 } display_primaries[3];
887 /**890 /**
888 * @white_point: White Point of Colorspace Data.891 * @white_point: White Point of Colorspace Data.
889 * These are coded as unsigned 16-bit values in units of892 * These are coded as unsigned 16-bit values in units of
@@ -894,7 +897,7 @@ struct hdr_metadata_infoframe { · 4 unmodified lines
894 */897 */
895 struct {898 struct {
896 __u16 x, y;899 __u16 x, y;
897 } white_point;900 } white_point;
898 /**901 /**
899 * @max_display_mastering_luminance: Max Mastering Display Luminance.902 * @max_display_mastering_luminance: Max Mastering Display Luminance.
900 * This value is coded as an unsigned 16-bit value in units of 1 cd/m2,903 * This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
include/uapi/drm/ivpu_accel.h+8−1
@@ -60,6 +60,7 @@ extern "C" { · 59 unmodified lines
60#define DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID 1060#define DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID 10
61#define DRM_IVPU_PARAM_TILE_CONFIG 1161#define DRM_IVPU_PARAM_TILE_CONFIG 11
62#define DRM_IVPU_PARAM_SKU 1262#define DRM_IVPU_PARAM_SKU 12
63#define DRM_IVPU_PARAM_CAPABILITIES 13
63 64
64#define DRM_IVPU_PLATFORM_TYPE_SILICON 065#define DRM_IVPU_PLATFORM_TYPE_SILICON 0
65 66
@@ -68,6 +69,9 @@ extern "C" { · 2 unmodified lines
68#define DRM_IVPU_CONTEXT_PRIORITY_FOCUS 269#define DRM_IVPU_CONTEXT_PRIORITY_FOCUS 2
69#define DRM_IVPU_CONTEXT_PRIORITY_REALTIME 370#define DRM_IVPU_CONTEXT_PRIORITY_REALTIME 3
70 71
72#define DRM_IVPU_CAP_METRIC_STREAMER 1
73#define DRM_IVPU_CAP_DMA_MEMORY_RANGE 2
74
71/**75/**
72 * struct drm_ivpu_param - Get/Set VPU parameters76 * struct drm_ivpu_param - Get/Set VPU parameters
73 */77 */
@@ -129,8 +133,10 @@ struct drm_ivpu_param { · 55 unmodified lines
129 __u64 value;133 __u64 value;
130};134};
131 135
132#define DRM_IVPU_BO_HIGH_MEM 0x00000001136#define DRM_IVPU_BO_SHAVE_MEM 0x00000001
137#define DRM_IVPU_BO_HIGH_MEM DRM_IVPU_BO_SHAVE_MEM
133#define DRM_IVPU_BO_MAPPABLE 0x00000002138#define DRM_IVPU_BO_MAPPABLE 0x00000002
139#define DRM_IVPU_BO_DMA_MEM 0x00000004
134 140
135#define DRM_IVPU_BO_CACHED 0x00000000141#define DRM_IVPU_BO_CACHED 0x00000000
136#define DRM_IVPU_BO_UNCACHED 0x00010000142#define DRM_IVPU_BO_UNCACHED 0x00010000
@@ -140,6 +146,7 @@ struct drm_ivpu_param { · 3 unmodified lines
140#define DRM_IVPU_BO_FLAGS \146#define DRM_IVPU_BO_FLAGS \
141 (DRM_IVPU_BO_HIGH_MEM | \147 (DRM_IVPU_BO_HIGH_MEM | \
142 DRM_IVPU_BO_MAPPABLE | \148 DRM_IVPU_BO_MAPPABLE | \
149 DRM_IVPU_BO_DMA_MEM | \
143 DRM_IVPU_BO_CACHE_MASK)150 DRM_IVPU_BO_CACHE_MASK)
144 151
145/**152/**
include/uapi/drm/nouveau_drm.h+268−3
@@ -33,11 +33,51 @@ · 32 unmodified lines
33extern "C" {33extern "C" {
34#endif34#endif
35 35
36#define NOUVEAU_GETPARAM_PCI_VENDOR 3
37#define NOUVEAU_GETPARAM_PCI_DEVICE 4
38#define NOUVEAU_GETPARAM_BUS_TYPE 5
39#define NOUVEAU_GETPARAM_FB_SIZE 8
40#define NOUVEAU_GETPARAM_AGP_SIZE 9
41#define NOUVEAU_GETPARAM_CHIPSET_ID 11
42#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
43#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
44#define NOUVEAU_GETPARAM_PTIMER_TIME 14
45#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
46#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
47struct drm_nouveau_getparam {
48 __u64 param;
49 __u64 value;
50};
51
52struct drm_nouveau_channel_alloc {
53 __u32 fb_ctxdma_handle;
54 __u32 tt_ctxdma_handle;
55
56 __s32 channel;
57 __u32 pushbuf_domains;
58
59 /* Notifier memory */
60 __u32 notifier_handle;
61
62 /* DRM-enforced subchannel assignments */
63 struct {
64 __u32 handle;
65 __u32 grclass;
66 } subchan[8];
67 __u32 nr_subchan;
68};
69
70struct drm_nouveau_channel_free {
71 __s32 channel;
72};
73
36#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)74#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
37#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)75#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
38#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)76#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
39#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)77#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
40#define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)78#define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)
79/* The BO will never be shared via import or export. */
80#define NOUVEAU_GEM_DOMAIN_NO_SHARE (1 << 5)
41 81
42#define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */82#define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */
43#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff0083#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
@@ -98,6 +138,7 @@ struct drm_nouveau_gem_pushbuf_push { · 54 unmodified lines
98 __u32 pad;138 __u32 pad;
99 __u64 offset;139 __u64 offset;
100 __u64 length;140 __u64 length;
141#define NOUVEAU_GEM_PUSHBUF_NO_PREFETCH (1 << 23)
101};142};
102 143
103struct drm_nouveau_gem_pushbuf {144struct drm_nouveau_gem_pushbuf {
@@ -126,16 +167,233 @@ struct drm_nouveau_gem_cpu_fini { · 22 unmodified lines
126 __u32 handle;167 __u32 handle;
127};168};
128 169
129#define DRM_NOUVEAU_GETPARAM 0x00 /* deprecated */170/**
171 * struct drm_nouveau_sync - sync object
172 *
173 * This structure serves as synchronization mechanism for (potentially)
174 * asynchronous operations such as EXEC or VM_BIND.
175 */
176struct drm_nouveau_sync {
177 /**
178 * @flags: the flags for a sync object
179 *
180 * The first 8 bits are used to determine the type of the sync object.
181 */
182 __u32 flags;
183#define DRM_NOUVEAU_SYNC_SYNCOBJ 0x0
184#define DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ 0x1
185#define DRM_NOUVEAU_SYNC_TYPE_MASK 0xf
186 /**
187 * @handle: the handle of the sync object
188 */
189 __u32 handle;
190 /**
191 * @timeline_value:
192 *
193 * The timeline point of the sync object in case the syncobj is of
194 * type DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ.
195 */
196 __u64 timeline_value;
197};
198
199/**
200 * struct drm_nouveau_vm_init - GPU VA space init structure
201 *
202 * Used to initialize the GPU's VA space for a user client, telling the kernel
203 * which portion of the VA space is managed by the UMD and kernel respectively.
204 *
205 * For the UMD to use the VM_BIND uAPI, this must be called before any BOs or
206 * channels are created; if called afterwards DRM_IOCTL_NOUVEAU_VM_INIT fails
207 * with -ENOSYS.
208 */
209struct drm_nouveau_vm_init {
210 /**
211 * @kernel_managed_addr: start address of the kernel managed VA space
212 * region
213 */
214 __u64 kernel_managed_addr;
215 /**
216 * @kernel_managed_size: size of the kernel managed VA space region in
217 * bytes
218 */
219 __u64 kernel_managed_size;
220};
221
222/**
223 * struct drm_nouveau_vm_bind_op - VM_BIND operation
224 *
225 * This structure represents a single VM_BIND operation. UMDs should pass
226 * an array of this structure via struct drm_nouveau_vm_bind's &op_ptr field.
227 */
228struct drm_nouveau_vm_bind_op {
229 /**
230 * @op: the operation type
231 */
232 __u32 op;
233/**
234 * @DRM_NOUVEAU_VM_BIND_OP_MAP:
235 *
236 * Map a GEM object to the GPU's VA space. Optionally, the
237 * &DRM_NOUVEAU_VM_BIND_SPARSE flag can be passed to instruct the kernel to
238 * create sparse mappings for the given range.
239 */
240#define DRM_NOUVEAU_VM_BIND_OP_MAP 0x0
241/**
242 * @DRM_NOUVEAU_VM_BIND_OP_UNMAP:
243 *
244 * Unmap an existing mapping in the GPU's VA space. If the region the mapping
245 * is located in is a sparse region, new sparse mappings are created where the
246 * unmapped (memory backed) mapping was mapped previously. To remove a sparse
247 * region the &DRM_NOUVEAU_VM_BIND_SPARSE must be set.
248 */
249#define DRM_NOUVEAU_VM_BIND_OP_UNMAP 0x1
250 /**
251 * @flags: the flags for a &drm_nouveau_vm_bind_op
252 */
253 __u32 flags;
254/**
255 * @DRM_NOUVEAU_VM_BIND_SPARSE:
256 *
257 * Indicates that an allocated VA space region should be sparse.
258 */
259#define DRM_NOUVEAU_VM_BIND_SPARSE (1 << 8)
260 /**
261 * @handle: the handle of the DRM GEM object to map
262 */
263 __u32 handle;
264 /**
265 * @pad: 32 bit padding, should be 0
266 */
267 __u32 pad;
268 /**
269 * @addr:
270 *
271 * the address the VA space region or (memory backed) mapping should be mapped to
272 */
273 __u64 addr;
274 /**
275 * @bo_offset: the offset within the BO backing the mapping
276 */
277 __u64 bo_offset;
278 /**
279 * @range: the size of the requested mapping in bytes
280 */
281 __u64 range;
282};
283
284/**
285 * struct drm_nouveau_vm_bind - structure for DRM_IOCTL_NOUVEAU_VM_BIND
286 */
287struct drm_nouveau_vm_bind {
288 /**
289 * @op_count: the number of &drm_nouveau_vm_bind_op
290 */
291 __u32 op_count;
292 /**
293 * @flags: the flags for a &drm_nouveau_vm_bind ioctl
294 */
295 __u32 flags;
296/**
297 * @DRM_NOUVEAU_VM_BIND_RUN_ASYNC:
298 *
299 * Indicates that the given VM_BIND operation should be executed asynchronously
300 * by the kernel.
301 *
302 * If this flag is not supplied the kernel executes the associated operations
303 * synchronously and doesn't accept any &drm_nouveau_sync objects.
304 */
305#define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1
306 /**
307 * @wait_count: the number of wait &drm_nouveau_syncs
308 */
309 __u32 wait_count;
310 /**
311 * @sig_count: the number of &drm_nouveau_syncs to signal when finished
312 */
313 __u32 sig_count;
314 /**
315 * @wait_ptr: pointer to &drm_nouveau_syncs to wait for
316 */
317 __u64 wait_ptr;
318 /**
319 * @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished
320 */
321 __u64 sig_ptr;
322 /**
323 * @op_ptr: pointer to the &drm_nouveau_vm_bind_ops to execute
324 */
325 __u64 op_ptr;
326};
327
328/**
329 * struct drm_nouveau_exec_push - EXEC push operation
330 *
331 * This structure represents a single EXEC push operation. UMDs should pass an
332 * array of this structure via struct drm_nouveau_exec's &push_ptr field.
333 */
334struct drm_nouveau_exec_push {
335 /**
336 * @va: the virtual address of the push buffer mapping
337 */
338 __u64 va;
339 /**
340 * @va_len: the length of the push buffer mapping
341 */
342 __u32 va_len;
343 /**
344 * @flags: the flags for this push buffer mapping
345 */
346 __u32 flags;
347#define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1
348};
349
350/**
351 * struct drm_nouveau_exec - structure for DRM_IOCTL_NOUVEAU_EXEC
352 */
353struct drm_nouveau_exec {
354 /**
355 * @channel: the channel to execute the push buffer in
356 */
357 __u32 channel;
358 /**
359 * @push_count: the number of &drm_nouveau_exec_push ops
360 */
361 __u32 push_count;
362 /**
363 * @wait_count: the number of wait &drm_nouveau_syncs
364 */
365 __u32 wait_count;
366 /**
367 * @sig_count: the number of &drm_nouveau_syncs to signal when finished
368 */
369 __u32 sig_count;
370 /**
371 * @wait_ptr: pointer to &drm_nouveau_syncs to wait for
372 */
373 __u64 wait_ptr;
374 /**
375 * @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished
376 */
377 __u64 sig_ptr;
378 /**
379 * @push_ptr: pointer to &drm_nouveau_exec_push ops
380 */
381 __u64 push_ptr;
382};
383
384#define DRM_NOUVEAU_GETPARAM 0x00
130#define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */385#define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */
131#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 /* deprecated */386#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
132#define DRM_NOUVEAU_CHANNEL_FREE 0x03 /* deprecated */387#define DRM_NOUVEAU_CHANNEL_FREE 0x03
133#define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */388#define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */
134#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */389#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
135#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */390#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */
136#define DRM_NOUVEAU_NVIF 0x07391#define DRM_NOUVEAU_NVIF 0x07
137#define DRM_NOUVEAU_SVM_INIT 0x08392#define DRM_NOUVEAU_SVM_INIT 0x08
138#define DRM_NOUVEAU_SVM_BIND 0x09393#define DRM_NOUVEAU_SVM_BIND 0x09
394#define DRM_NOUVEAU_VM_INIT 0x10
395#define DRM_NOUVEAU_VM_BIND 0x11
396#define DRM_NOUVEAU_EXEC 0x12
139#define DRM_NOUVEAU_GEM_NEW 0x40397#define DRM_NOUVEAU_GEM_NEW 0x40
140#define DRM_NOUVEAU_GEM_PUSHBUF 0x41398#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
141#define DRM_NOUVEAU_GEM_CPU_PREP 0x42399#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
@@ -188,6 +446,10 @@ struct drm_nouveau_svm_bind { · 46 unmodified lines
188#define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31)446#define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31)
189 447
190 448
449#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
450#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
451#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
452
191#define DRM_IOCTL_NOUVEAU_SVM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init)453#define DRM_IOCTL_NOUVEAU_SVM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init)
192#define DRM_IOCTL_NOUVEAU_SVM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind)454#define DRM_IOCTL_NOUVEAU_SVM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind)
193 455
@@ -197,6 +459,9 @@ struct drm_nouveau_svm_bind { · 3 unmodified lines
197#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)459#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
198#define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)460#define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
199 461
462#define DRM_IOCTL_NOUVEAU_VM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_INIT, struct drm_nouveau_vm_init)
463#define DRM_IOCTL_NOUVEAU_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_BIND, struct drm_nouveau_vm_bind)
464#define DRM_IOCTL_NOUVEAU_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_EXEC, struct drm_nouveau_exec)
200#if defined(__cplusplus)465#if defined(__cplusplus)
201}466}
202#endif467#endif
include/uapi/drm/virtgpu_drm.h+15−1
@@ -64,6 +64,16 @@ struct drm_virtgpu_map { · 63 unmodified lines
64 __u32 pad;64 __u32 pad;
65};65};
66 66
67#define VIRTGPU_EXECBUF_SYNCOBJ_RESET 0x01
68#define VIRTGPU_EXECBUF_SYNCOBJ_FLAGS ( \
69 VIRTGPU_EXECBUF_SYNCOBJ_RESET | \
70 0)
71struct drm_virtgpu_execbuffer_syncobj {
72 __u32 handle;
73 __u32 flags;
74 __u64 point;
75};
76
67/* fence_fd is modified on success if VIRTGPU_EXECBUF_FENCE_FD_OUT flag is set. */77/* fence_fd is modified on success if VIRTGPU_EXECBUF_FENCE_FD_OUT flag is set. */
68struct drm_virtgpu_execbuffer {78struct drm_virtgpu_execbuffer {
69 __u32 flags;79 __u32 flags;
@@ -73,7 +83,11 @@ struct drm_virtgpu_execbuffer { · 3 unmodified lines
73 __u32 num_bo_handles;83 __u32 num_bo_handles;
74 __s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */84 __s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */
75 __u32 ring_idx; /* command ring index (see VIRTGPU_EXECBUF_RING_IDX) */85 __u32 ring_idx; /* command ring index (see VIRTGPU_EXECBUF_RING_IDX) */
76 __u32 pad;86 __u32 syncobj_stride; /* size of @drm_virtgpu_execbuffer_syncobj */
87 __u32 num_in_syncobjs;
88 __u32 num_out_syncobjs;
89 __u64 in_syncobjs;
90 __u64 out_syncobjs;
77};91};
78 92
79#define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */93#define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */