History

Merge tag 'drm-fixes-2020-05-01' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie: "Regular scheduled fixes for graphics. Nothing to extreme bunch of amdgpu fixes, i915 and qxl fixes, along with some misc ones. All seems to be progressing normally. core: - EDID off by one DTD fix - DP mst write return code fix dma-buf: - fix SET_NAME ioctl uapi - doc fixes amdgpu: - Fix a green screen on resume issue - PM fixes for SR-IOV SDMA fix for navi - Renoir display fixes - Cursor and pageflip stuttering fixes - Misc additional display fixes - (uapi) Add additional DCC tiling flags for navi1x i915: - Fix selftest refcnt leak (Xiyu) - Fix gem vma lock (Chris) - Fix gt's i915_request.timeline acquire by checking if cacheline is valid (Chris) - Fix IRQ postinistall fault masks (Matt) qxl: - use after gree fix - fix lost kunmap - release leak fix virtio: - context destruction fix" * tag 'drm-fixes-2020-05-01' of git://anongit.freedesktop.org/drm/drm: (26 commits) dma-buf: fix documentation build warnings drm/qxl: qxl_release use after free drm/qxl: lost qxl_bo_kunmap_atomic_page in qxl_image_init_helper() drm/i915: Use proper fault mask in interrupt postinstall too drm/amd/display: Use cursor locking to prevent flip delays drm/amd/display: Update downspread percent to match spreadsheet for DCN2.1 drm/amd/display: Defer cursor update around VUPDATE for all ASIC drm/amd/display: fix rn soc bb update drm/amd/display: check if REFCLK_CNTL register is present drm/amdgpu: bump version for invalidate L2 before SDMA IBs drm/amdgpu: invalidate L2 before SDMA IBs (v2) drm/amdgpu: add tiling flags from Mesa drm/amd/powerplay: avoid using pm_en before it is initialized revised Revert "drm/amd/powerplay: avoid using pm_en before it is initialized" drm/qxl: qxl_release leak in qxl_hw_surface_alloc() drm/qxl: qxl_release leak in qxl_draw_dirty_fb() drm/virtio: only destroy created contexts drm/dp_mst: Fix drm_dp_send_dpcd_write() return code drm/i915/gt: Check cacheline is valid before acquiring drm/i915/gem: Hold obj->vma.lock over for_each_ggtt_vma() ...

Linus Torvalds committed 6 years ago

Commit 477bfeb2 parents cebcff3 e3dcd8640 files · +290 −154Browse files

Unified · Split

40 files
  1. drivers/dma-buf/dma-buf.c +4 −3
  2. drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +2 −1
  3. drivers/gpu/drm/amd/amdgpu/navi10_sdma_pkt_open.h +16 −0
  4. drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +13 −1
  5. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +29 −9
  6. drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +27 −0
  7. drivers/gpu/drm/amd/display/dc/core/dc_stream.c +4 −36
  8. drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +1 −0
  9. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +10 −0
  10. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +1 −0
  11. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c +1 −0
  12. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +15 −0
  13. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h +14 −6
  14. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +12 −2
  15. drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +2 −1
  16. drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c +1 −0
  17. drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c +1 −0
  18. drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h +2 −1
  19. drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +4 −0
  20. drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c +1 −0
  21. drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +33 −44
  22. drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +16 −0
  23. drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +1 −0
  24. drivers/gpu/drm/amd/powerplay/amd_powerplay.c +5 −4
  25. drivers/gpu/drm/drm_dp_mst_topology.c +6 −2
  26. drivers/gpu/drm/drm_edid.c +1 −1
  27. drivers/gpu/drm/i915/gem/i915_gem_tiling.c +18 −2
  28. drivers/gpu/drm/i915/gem/selftests/huge_pages.c +8 −4
  29. drivers/gpu/drm/i915/gt/intel_timeline.c +2 −0
  30. drivers/gpu/drm/i915/i915_irq.c +2 −4
  31. drivers/gpu/drm/i915/i915_vma.c +6 −4
  32. drivers/gpu/drm/qxl/qxl_cmd.c +5 −5
  33. drivers/gpu/drm/qxl/qxl_display.c +3 −3
  34. drivers/gpu/drm/qxl/qxl_draw.c +4 −3
  35. drivers/gpu/drm/qxl/qxl_image.c +2 −1
  36. drivers/gpu/drm/qxl/qxl_ioctl.c +1 −4
  37. drivers/gpu/drm/virtio/virtgpu_kms.c +6 −11
  38. include/linux/dma-buf.h +1 −2
  39. include/uapi/drm/amdgpu_drm.h +4 −0
  40. include/uapi/linux/dma-buf.h +6 −0
drivers/dma-buf/dma-buf.c+4−3
@@ -388,7 +388,8 @@ static long dma_buf_ioctl(struct file *file, · 387 unmodified lines
388 388
389 return ret;389 return ret;
390 390
391 case DMA_BUF_SET_NAME:391 case DMA_BUF_SET_NAME_A:
392 case DMA_BUF_SET_NAME_B:
392 return dma_buf_set_name(dmabuf, (const char __user *)arg);393 return dma_buf_set_name(dmabuf, (const char __user *)arg);
393 394
394 default:395 default:
@@ -655,8 +656,8 @@ EXPORT_SYMBOL_GPL(dma_buf_put); · 260 unmodified lines
655 * calls attach() of dma_buf_ops to allow device-specific attach functionality656 * calls attach() of dma_buf_ops to allow device-specific attach functionality
656 * @dmabuf: [in] buffer to attach device to.657 * @dmabuf: [in] buffer to attach device to.
657 * @dev: [in] device to be attached.658 * @dev: [in] device to be attached.
658 * @importer_ops [in] importer operations for the attachment659 * @importer_ops: [in] importer operations for the attachment
659 * @importer_priv [in] importer private pointer for the attachment660 * @importer_priv: [in] importer private pointer for the attachment
660 *661 *
661 * Returns struct dma_buf_attachment pointer for this attachment. Attachments662 * Returns struct dma_buf_attachment pointer for this attachment. Attachments
662 * must be cleaned up by calling dma_buf_detach().663 * must be cleaned up by calling dma_buf_detach().
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+2−1
@@ -85,9 +85,10 @@ · 84 unmodified lines
85 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches85 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
86 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask86 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
87 * - 3.36.0 - Allow reading more status registers on si/cik87 * - 3.36.0 - Allow reading more status registers on si/cik
88 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
88 */89 */
89#define KMS_DRIVER_MAJOR 390#define KMS_DRIVER_MAJOR 3
90#define KMS_DRIVER_MINOR 3691#define KMS_DRIVER_MINOR 37
91#define KMS_DRIVER_PATCHLEVEL 092#define KMS_DRIVER_PATCHLEVEL 0
92 93
93int amdgpu_vram_limit = 0;94int amdgpu_vram_limit = 0;
drivers/gpu/drm/amd/amdgpu/navi10_sdma_pkt_open.h+16−0
@@ -73,6 +73,22 @@ · 72 unmodified lines
73#define SDMA_OP_AQL_COPY 073#define SDMA_OP_AQL_COPY 0
74#define SDMA_OP_AQL_BARRIER_OR 074#define SDMA_OP_AQL_BARRIER_OR 0
75 75
76#define SDMA_GCR_RANGE_IS_PA (1 << 18)
77#define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16)
78#define SDMA_GCR_GL2_WB (1 << 15)
79#define SDMA_GCR_GL2_INV (1 << 14)
80#define SDMA_GCR_GL2_DISCARD (1 << 13)
81#define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11)
82#define SDMA_GCR_GL2_US (1 << 10)
83#define SDMA_GCR_GL1_INV (1 << 9)
84#define SDMA_GCR_GLV_INV (1 << 8)
85#define SDMA_GCR_GLK_INV (1 << 7)
86#define SDMA_GCR_GLK_WB (1 << 6)
87#define SDMA_GCR_GLM_INV (1 << 5)
88#define SDMA_GCR_GLM_WB (1 << 4)
89#define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2)
90#define SDMA_GCR_GLI_INV(x) (((x) & 0x3) << 0)
91
76/*define for op field*/92/*define for op field*/
77#define SDMA_PKT_HEADER_op_offset 093#define SDMA_PKT_HEADER_op_offset 0
78#define SDMA_PKT_HEADER_op_mask 0x000000FF94#define SDMA_PKT_HEADER_op_mask 0x000000FF
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c+13−1
@@ -382,6 +382,18 @@ static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring, · 381 unmodified lines
382 unsigned vmid = AMDGPU_JOB_GET_VMID(job);382 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
383 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);383 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
384 384
385 /* Invalidate L2, because if we don't do it, we might get stale cache
386 * lines from previous IBs.
387 */
388 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
389 amdgpu_ring_write(ring, 0);
390 amdgpu_ring_write(ring, (SDMA_GCR_GL2_INV |
391 SDMA_GCR_GL2_WB |
392 SDMA_GCR_GLM_INV |
393 SDMA_GCR_GLM_WB) << 16);
394 amdgpu_ring_write(ring, 0xffffff80);
395 amdgpu_ring_write(ring, 0xffff);
396
385 /* An IB packet must end on a 8 DW boundary--the next dword397 /* An IB packet must end on a 8 DW boundary--the next dword
386 * must be on a 8-dword boundary. Our IB packet below is 6398 * must be on a 8-dword boundary. Our IB packet below is 6
387 * dwords long, thus add x number of NOPs, such that, in399 * dwords long, thus add x number of NOPs, such that, in
@@ -1595,7 +1607,7 @@ static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = { · 1207 unmodified lines
1595 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +1607 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1596 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +1608 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1597 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */1609 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1598 .emit_ib_size = 7 + 6, /* sdma_v5_0_ring_emit_ib */1610 .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1599 .emit_ib = sdma_v5_0_ring_emit_ib,1611 .emit_ib = sdma_v5_0_ring_emit_ib,
1600 .emit_fence = sdma_v5_0_ring_emit_fence,1612 .emit_fence = sdma_v5_0_ring_emit_fence,
1601 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,1613 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+29−9
@@ -3340,7 +3340,8 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev, · 3339 unmodified lines
3340 const union dc_tiling_info *tiling_info,3340 const union dc_tiling_info *tiling_info,
3341 const uint64_t info,3341 const uint64_t info,
3342 struct dc_plane_dcc_param *dcc,3342 struct dc_plane_dcc_param *dcc,
3343 struct dc_plane_address *address)3343 struct dc_plane_address *address,
3344 bool force_disable_dcc)
3344{3345{
3345 struct dc *dc = adev->dm.dc;3346 struct dc *dc = adev->dm.dc;
3346 struct dc_dcc_surface_param input;3347 struct dc_dcc_surface_param input;
@@ -3352,6 +3353,9 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev, · 5 unmodified lines
3352 memset(&input, 0, sizeof(input));3353 memset(&input, 0, sizeof(input));
3353 memset(&output, 0, sizeof(output));3354 memset(&output, 0, sizeof(output));
3354 3355
3356 if (force_disable_dcc)
3357 return 0;
3358
3355 if (!offset)3359 if (!offset)
3356 return 0;3360 return 0;
3357 3361
@@ -3401,7 +3405,8 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev, · 43 unmodified lines
3401 union dc_tiling_info *tiling_info,3405 union dc_tiling_info *tiling_info,
3402 struct plane_size *plane_size,3406 struct plane_size *plane_size,
3403 struct dc_plane_dcc_param *dcc,3407 struct dc_plane_dcc_param *dcc,
3404 struct dc_plane_address *address)3408 struct dc_plane_address *address,
3409 bool force_disable_dcc)
3405{3410{
3406 const struct drm_framebuffer *fb = &afb->base;3411 const struct drm_framebuffer *fb = &afb->base;
3407 int ret;3412 int ret;
@@ -3507,7 +3512,8 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev, · 99 unmodified lines
3507 3512
3508 ret = fill_plane_dcc_attributes(adev, afb, format, rotation,3513 ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
3509 plane_size, tiling_info,3514 plane_size, tiling_info,
3510 tiling_flags, dcc, address);3515 tiling_flags, dcc, address,
3516 force_disable_dcc);
3511 if (ret)3517 if (ret)
3512 return ret;3518 return ret;
3513 }3519 }
@@ -3599,7 +3605,8 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, · 85 unmodified lines
3599 const struct drm_plane_state *plane_state,3605 const struct drm_plane_state *plane_state,
3600 const uint64_t tiling_flags,3606 const uint64_t tiling_flags,
3601 struct dc_plane_info *plane_info,3607 struct dc_plane_info *plane_info,
3602 struct dc_plane_address *address)3608 struct dc_plane_address *address,
3609 bool force_disable_dcc)
3603{3610{
3604 const struct drm_framebuffer *fb = plane_state->fb;3611 const struct drm_framebuffer *fb = plane_state->fb;
3605 const struct amdgpu_framebuffer *afb =3612 const struct amdgpu_framebuffer *afb =
@@ -3681,7 +3688,8 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, · 75 unmodified lines
3681 plane_info->rotation, tiling_flags,3688 plane_info->rotation, tiling_flags,
3682 &plane_info->tiling_info,3689 &plane_info->tiling_info,
3683 &plane_info->plane_size,3690 &plane_info->plane_size,
3684 &plane_info->dcc, address);3691 &plane_info->dcc, address,
3692 force_disable_dcc);
3685 if (ret)3693 if (ret)
3686 return ret;3694 return ret;
3687 3695
@@ -3704,6 +3712,7 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, · 16 unmodified lines
3704 struct dc_plane_info plane_info;3712 struct dc_plane_info plane_info;
3705 uint64_t tiling_flags;3713 uint64_t tiling_flags;
3706 int ret;3714 int ret;
3715 bool force_disable_dcc = false;
3707 3716
3708 ret = fill_dc_scaling_info(plane_state, &scaling_info);3717 ret = fill_dc_scaling_info(plane_state, &scaling_info);
3709 if (ret)3718 if (ret)
@@ -3718,9 +3727,11 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, · 8 unmodified lines
3718 if (ret)3727 if (ret)
3719 return ret;3728 return ret;
3720 3729
3730 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
3721 ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,3731 ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,
3722 &plane_info,3732 &plane_info,
3723 &dc_plane_state->address);3733 &dc_plane_state->address,
3734 force_disable_dcc);
3724 if (ret)3735 if (ret)
3725 return ret;3736 return ret;
3726 3737
@@ -5342,6 +5353,7 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, · 1615 unmodified lines
5342 uint64_t tiling_flags;5353 uint64_t tiling_flags;
5343 uint32_t domain;5354 uint32_t domain;
5344 int r;5355 int r;
5356 bool force_disable_dcc = false;
5345 5357
5346 dm_plane_state_old = to_dm_plane_state(plane->state);5358 dm_plane_state_old = to_dm_plane_state(plane->state);
5347 dm_plane_state_new = to_dm_plane_state(new_state);5359 dm_plane_state_new = to_dm_plane_state(new_state);
@@ -5400,11 +5412,13 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, · 52 unmodified lines
5400 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {5412 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
5401 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;5413 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
5402 5414
5415 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5403 fill_plane_buffer_attributes(5416 fill_plane_buffer_attributes(
5404 adev, afb, plane_state->format, plane_state->rotation,5417 adev, afb, plane_state->format, plane_state->rotation,
5405 tiling_flags, &plane_state->tiling_info,5418 tiling_flags, &plane_state->tiling_info,
5406 &plane_state->plane_size, &plane_state->dcc,5419 &plane_state->plane_size, &plane_state->dcc,
5407 &plane_state->address);5420 &plane_state->address,
5421 force_disable_dcc);
5408 }5422 }
5409 5423
5410 return 0;5424 return 0;
@@ -6676,7 +6690,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 1265 unmodified lines
6676 fill_dc_plane_info_and_addr(6690 fill_dc_plane_info_and_addr(
6677 dm->adev, new_plane_state, tiling_flags,6691 dm->adev, new_plane_state, tiling_flags,
6678 &bundle->plane_infos[planes_count],6692 &bundle->plane_infos[planes_count],
6679 &bundle->flip_addrs[planes_count].address);6693 &bundle->flip_addrs[planes_count].address,
6694 false);
6695
6696 DRM_DEBUG_DRIVER("plane: id=%d dcc_en=%d\n",
6697 new_plane_state->plane->index,
6698 bundle->plane_infos[planes_count].dcc.enable);
6680 6699
6681 bundle->surface_updates[planes_count].plane_info =6700 bundle->surface_updates[planes_count].plane_info =
6682 &bundle->plane_infos[planes_count];6701 &bundle->plane_infos[planes_count];
@@ -8096,7 +8115,8 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm, · 1413 unmodified lines
8096 ret = fill_dc_plane_info_and_addr(8115 ret = fill_dc_plane_info_and_addr(
8097 dm->adev, new_plane_state, tiling_flags,8116 dm->adev, new_plane_state, tiling_flags,
8098 plane_info,8117 plane_info,
8099 &flip_addr->address);8118 &flip_addr->address,
8119 false);
8100 if (ret)8120 if (ret)
8101 goto cleanup;8121 goto cleanup;
8102 8122
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c+27−0
@@ -2908,6 +2908,12 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd · 2907 unmodified lines
2908 sizeof(hpd_irq_dpcd_data),2908 sizeof(hpd_irq_dpcd_data),
2909 "Status: ");2909 "Status: ");
2910 2910
2911 for (i = 0; i < MAX_PIPES; i++) {
2912 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
2913 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
2914 link->dc->hwss.blank_stream(pipe_ctx);
2915 }
2916
2911 for (i = 0; i < MAX_PIPES; i++) {2917 for (i = 0; i < MAX_PIPES; i++) {
2912 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];2918 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
2913 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)2919 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
@@ -2927,6 +2933,12 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd · 13 unmodified lines
2927 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)2933 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2928 dc_link_reallocate_mst_payload(link);2934 dc_link_reallocate_mst_payload(link);
2929 2935
2936 for (i = 0; i < MAX_PIPES; i++) {
2937 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
2938 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
2939 link->dc->hwss.unblank_stream(pipe_ctx, &previous_link_settings);
2940 }
2941
2930 status = false;2942 status = false;
2931 if (out_link_loss)2943 if (out_link_loss)
2932 *out_link_loss = true;2944 *out_link_loss = true;
@@ -4227,6 +4239,21 @@ void dp_set_fec_enable(struct dc_link *link, bool enable) · 1294 unmodified lines
4227void dpcd_set_source_specific_data(struct dc_link *link)4239void dpcd_set_source_specific_data(struct dc_link *link)
4228{4240{
4229 const uint32_t post_oui_delay = 30; // 30ms4241 const uint32_t post_oui_delay = 30; // 30ms
4242 uint8_t dspc = 0;
4243 enum dc_status ret = DC_ERROR_UNEXPECTED;
4244
4245 ret = core_link_read_dpcd(link, DP_DOWN_STREAM_PORT_COUNT, &dspc,
4246 sizeof(dspc));
4247
4248 if (ret != DC_OK) {
4249 DC_LOG_ERROR("Error in DP aux read transaction,"
4250 " not writing source specific data\n");
4251 return;
4252 }
4253
4254 /* Return if OUI unsupported */
4255 if (!(dspc & DP_OUI_SUPPORT))
4256 return;
4230 4257
4231 if (!link->dc->vendor_signature.is_valid) {4258 if (!link->dc->vendor_signature.is_valid) {
4232 struct dpcd_amd_signature amd_signature;4259 struct dpcd_amd_signature amd_signature;
drivers/gpu/drm/amd/display/dc/core/dc_stream.c+4−36
@@ -231,34 +231,6 @@ struct dc_stream_status *dc_stream_get_status( · 230 unmodified lines
231 return dc_stream_get_status_from_state(dc->current_state, stream);231 return dc_stream_get_status_from_state(dc->current_state, stream);
232}232}
233 233
234static void delay_cursor_until_vupdate(struct pipe_ctx *pipe_ctx, struct dc *dc)
235{
236#if defined(CONFIG_DRM_AMD_DC_DCN)
237 unsigned int vupdate_line;
238 unsigned int lines_to_vupdate, us_to_vupdate, vpos, nvpos;
239 struct dc_stream_state *stream = pipe_ctx->stream;
240 unsigned int us_per_line;
241
242 if (stream->ctx->asic_id.chip_family == FAMILY_RV &&
243 ASICREV_IS_RAVEN(stream->ctx->asic_id.hw_internal_rev)) {
244
245 vupdate_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
246 if (!dc_stream_get_crtc_position(dc, &stream, 1, &vpos, &nvpos))
247 return;
248
249 if (vpos >= vupdate_line)
250 return;
251
252 us_per_line = stream->timing.h_total * 10000 / stream->timing.pix_clk_100hz;
253 lines_to_vupdate = vupdate_line - vpos;
254 us_to_vupdate = lines_to_vupdate * us_per_line;
255
256 /* 70 us is a conservative estimate of cursor update time*/
257 if (us_to_vupdate < 70)
258 udelay(us_to_vupdate);
259 }
260#endif
261}
262 234
263/**235/**
264 * dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address236 * dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address
@@ -298,9 +270,7 @@ bool dc_stream_set_cursor_attributes( · 33 unmodified lines
298 270
299 if (!pipe_to_program) {271 if (!pipe_to_program) {
300 pipe_to_program = pipe_ctx;272 pipe_to_program = pipe_ctx;
301 273 dc->hwss.cursor_lock(dc, pipe_to_program, true);
302 delay_cursor_until_vupdate(pipe_ctx, dc);
303 dc->hwss.pipe_control_lock(dc, pipe_to_program, true);
304 }274 }
305 275
306 dc->hwss.set_cursor_attribute(pipe_ctx);276 dc->hwss.set_cursor_attribute(pipe_ctx);
@@ -309,7 +279,7 @@ bool dc_stream_set_cursor_attributes( · 2 unmodified lines
309 }279 }
310 280
311 if (pipe_to_program)281 if (pipe_to_program)
312 dc->hwss.pipe_control_lock(dc, pipe_to_program, false);282 dc->hwss.cursor_lock(dc, pipe_to_program, false);
313 283
314 return true;284 return true;
315}285}
@@ -349,16 +319,14 @@ bool dc_stream_set_cursor_position( · 33 unmodified lines
349 319
350 if (!pipe_to_program) {320 if (!pipe_to_program) {
351 pipe_to_program = pipe_ctx;321 pipe_to_program = pipe_ctx;
352 322 dc->hwss.cursor_lock(dc, pipe_to_program, true);
353 delay_cursor_until_vupdate(pipe_ctx, dc);
354 dc->hwss.pipe_control_lock(dc, pipe_to_program, true);
355 }323 }
356 324
357 dc->hwss.set_cursor_position(pipe_ctx);325 dc->hwss.set_cursor_position(pipe_ctx);
358 }326 }
359 327
360 if (pipe_to_program)328 if (pipe_to_program)
361 dc->hwss.pipe_control_lock(dc, pipe_to_program, false);329 dc->hwss.cursor_lock(dc, pipe_to_program, false);
362 330
363 return true;331 return true;
364}332}
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c+1−0
@@ -2757,6 +2757,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { · 2756 unmodified lines
2757 .disable_plane = dce110_power_down_fe,2757 .disable_plane = dce110_power_down_fe,
2758 .pipe_control_lock = dce_pipe_control_lock,2758 .pipe_control_lock = dce_pipe_control_lock,
2759 .interdependent_update_lock = NULL,2759 .interdependent_update_lock = NULL,
2760 .cursor_lock = dce_pipe_control_lock,
2760 .prepare_bandwidth = dce110_prepare_bandwidth,2761 .prepare_bandwidth = dce110_prepare_bandwidth,
2761 .optimize_bandwidth = dce110_optimize_bandwidth,2762 .optimize_bandwidth = dce110_optimize_bandwidth,
2762 .set_drr = set_drr,2763 .set_drr = set_drr,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c+10−0
@@ -1625,6 +1625,16 @@ void dcn10_pipe_control_lock( · 1624 unmodified lines
1625 hws->funcs.verify_allow_pstate_change_high(dc);1625 hws->funcs.verify_allow_pstate_change_high(dc);
1626}1626}
1627 1627
1628void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock)
1629{
1630 /* cursor lock is per MPCC tree, so only need to lock one pipe per stream */
1631 if (!pipe || pipe->top_pipe)
1632 return;
1633
1634 dc->res_pool->mpc->funcs->cursor_lock(dc->res_pool->mpc,
1635 pipe->stream_res.opp->inst, lock);
1636}
1637
1628static bool wait_for_reset_trigger_to_occur(1638static bool wait_for_reset_trigger_to_occur(
1629 struct dc_context *dc_ctx,1639 struct dc_context *dc_ctx,
1630 struct timing_generator *tg)1640 struct timing_generator *tg)
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h+1−0
@@ -49,6 +49,7 @@ void dcn10_pipe_control_lock( · 48 unmodified lines
49 struct dc *dc,49 struct dc *dc,
50 struct pipe_ctx *pipe,50 struct pipe_ctx *pipe,
51 bool lock);51 bool lock);
52void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);
52void dcn10_blank_pixel_data(53void dcn10_blank_pixel_data(
53 struct dc *dc,54 struct dc *dc,
54 struct pipe_ctx *pipe_ctx,55 struct pipe_ctx *pipe_ctx,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c+1−0
@@ -50,6 +50,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { · 49 unmodified lines
50 .disable_audio_stream = dce110_disable_audio_stream,50 .disable_audio_stream = dce110_disable_audio_stream,
51 .disable_plane = dcn10_disable_plane,51 .disable_plane = dcn10_disable_plane,
52 .pipe_control_lock = dcn10_pipe_control_lock,52 .pipe_control_lock = dcn10_pipe_control_lock,
53 .cursor_lock = dcn10_cursor_lock,
53 .interdependent_update_lock = dcn10_lock_all_pipes,54 .interdependent_update_lock = dcn10_lock_all_pipes,
54 .prepare_bandwidth = dcn10_prepare_bandwidth,55 .prepare_bandwidth = dcn10_prepare_bandwidth,
55 .optimize_bandwidth = dcn10_optimize_bandwidth,56 .optimize_bandwidth = dcn10_optimize_bandwidth,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c+15−0
@@ -223,6 +223,9 @@ struct mpcc *mpc1_insert_plane( · 222 unmodified lines
223 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id);223 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id);
224 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id);224 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id);
225 225
226 /* Configure VUPDATE lock set for this MPCC to map to the OPP */
227 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, tree->opp_id);
228
226 /* update mpc tree mux setting */229 /* update mpc tree mux setting */
227 if (tree->opp_list == insert_above_mpcc) {230 if (tree->opp_list == insert_above_mpcc) {
228 /* insert the toppest mpcc */231 /* insert the toppest mpcc */
@@ -318,6 +321,7 @@ void mpc1_remove_mpcc( · 89 unmodified lines
318 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);321 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
319 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);322 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
320 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);323 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
324 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
321 325
322 /* mark this mpcc as not in use */326 /* mark this mpcc as not in use */
323 mpc10->mpcc_in_use_mask &= ~(1 << mpcc_id);327 mpc10->mpcc_in_use_mask &= ~(1 << mpcc_id);
@@ -328,6 +332,7 @@ void mpc1_remove_mpcc( · 4 unmodified lines
328 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);332 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
329 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);333 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
330 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);334 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
335 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
331 }336 }
332}337}
333 338
@@ -361,6 +366,7 @@ void mpc1_mpc_init(struct mpc *mpc) · 27 unmodified lines
361 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);366 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
362 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);367 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
363 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);368 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
369 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
364 370
365 mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);371 mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);
366 }372 }
@@ -381,6 +387,7 @@ void mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id) · 14 unmodified lines
381 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);387 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
382 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);388 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
383 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);389 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
390 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
384 391
385 mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);392 mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);
386 393
@@ -453,6 +460,13 @@ void mpc1_read_mpcc_state( · 66 unmodified lines
453 MPCC_BUSY, &s->busy);460 MPCC_BUSY, &s->busy);
454}461}
455 462
463void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock)
464{
465 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
466
467 REG_SET(CUR[opp_id], 0, CUR_VUPDATE_LOCK_SET, lock ? 1 : 0);
468}
469
456static const struct mpc_funcs dcn10_mpc_funcs = {470static const struct mpc_funcs dcn10_mpc_funcs = {
457 .read_mpcc_state = mpc1_read_mpcc_state,471 .read_mpcc_state = mpc1_read_mpcc_state,
458 .insert_plane = mpc1_insert_plane,472 .insert_plane = mpc1_insert_plane,
@@ -464,6 +478,7 @@ static const struct mpc_funcs dcn10_mpc_funcs = { · 5 unmodified lines
464 .assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect,478 .assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect,
465 .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,479 .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
466 .update_blending = mpc1_update_blending,480 .update_blending = mpc1_update_blending,
481 .cursor_lock = mpc1_cursor_lock,
467 .set_denorm = NULL,482 .set_denorm = NULL,
468 .set_denorm_clamp = NULL,483 .set_denorm_clamp = NULL,
469 .set_output_csc = NULL,484 .set_output_csc = NULL,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h+14−6
@@ -39,11 +39,12 @@ · 38 unmodified lines
39 SRII(MPCC_BG_G_Y, MPCC, inst),\39 SRII(MPCC_BG_G_Y, MPCC, inst),\
40 SRII(MPCC_BG_R_CR, MPCC, inst),\40 SRII(MPCC_BG_R_CR, MPCC, inst),\
41 SRII(MPCC_BG_B_CB, MPCC, inst),\41 SRII(MPCC_BG_B_CB, MPCC, inst),\
42 SRII(MPCC_BG_B_CB, MPCC, inst),\42 SRII(MPCC_SM_CONTROL, MPCC, inst),\
43 SRII(MPCC_SM_CONTROL, MPCC, inst)43 SRII(MPCC_UPDATE_LOCK_SEL, MPCC, inst)
44 44
45#define MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst) \45#define MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst) \
46 SRII(MUX, MPC_OUT, inst)46 SRII(MUX, MPC_OUT, inst),\
47 VUPDATE_SRII(CUR, VUPDATE_LOCK_SET, inst)
47 48
48#define MPC_COMMON_REG_VARIABLE_LIST \49#define MPC_COMMON_REG_VARIABLE_LIST \
49 uint32_t MPCC_TOP_SEL[MAX_MPCC]; \50 uint32_t MPCC_TOP_SEL[MAX_MPCC]; \
@@ -55,7 +56,9 @@ · 5 unmodified lines
55 uint32_t MPCC_BG_R_CR[MAX_MPCC]; \56 uint32_t MPCC_BG_R_CR[MAX_MPCC]; \
56 uint32_t MPCC_BG_B_CB[MAX_MPCC]; \57 uint32_t MPCC_BG_B_CB[MAX_MPCC]; \
57 uint32_t MPCC_SM_CONTROL[MAX_MPCC]; \58 uint32_t MPCC_SM_CONTROL[MAX_MPCC]; \
58 uint32_t MUX[MAX_OPP];59 uint32_t MUX[MAX_OPP]; \
60 uint32_t MPCC_UPDATE_LOCK_SEL[MAX_MPCC]; \
61 uint32_t CUR[MAX_OPP];
59 62
60#define MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\63#define MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
61 SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\64 SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\
@@ -78,7 +81,8 @@ · 16 unmodified lines
78 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FIELD_ALT, mask_sh),\81 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FIELD_ALT, mask_sh),\
79 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_FRAME_POL, mask_sh),\82 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_FRAME_POL, mask_sh),\
80 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_TOP_POL, mask_sh),\83 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_TOP_POL, mask_sh),\
81 SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh)84 SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh),\
85 SF(MPCC0_MPCC_UPDATE_LOCK_SEL, MPCC_UPDATE_LOCK_SEL, mask_sh)
82 86
83#define MPC_REG_FIELD_LIST(type) \87#define MPC_REG_FIELD_LIST(type) \
84 type MPCC_TOP_SEL;\88 type MPCC_TOP_SEL;\
@@ -101,7 +105,9 @@ · 16 unmodified lines
101 type MPCC_SM_FIELD_ALT;\105 type MPCC_SM_FIELD_ALT;\
102 type MPCC_SM_FORCE_NEXT_FRAME_POL;\106 type MPCC_SM_FORCE_NEXT_FRAME_POL;\
103 type MPCC_SM_FORCE_NEXT_TOP_POL;\107 type MPCC_SM_FORCE_NEXT_TOP_POL;\
104 type MPC_OUT_MUX;108 type MPC_OUT_MUX;\
109 type MPCC_UPDATE_LOCK_SEL;\
110 type CUR_VUPDATE_LOCK_SET;
105 111
106struct dcn_mpc_registers {112struct dcn_mpc_registers {
107 MPC_COMMON_REG_VARIABLE_LIST113 MPC_COMMON_REG_VARIABLE_LIST
@@ -192,4 +198,6 @@ void mpc1_read_mpcc_state( · 84 unmodified lines
192 int mpcc_inst,198 int mpcc_inst,
193 struct mpcc_state *s);199 struct mpcc_state *s);
194 200
201void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock);
202
195#endif203#endif
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c+12−2
@@ -181,6 +181,14 @@ enum dcn10_clk_src_array_id { · 180 unmodified lines
181 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \181 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
182 mm ## block ## id ## _ ## reg_name182 mm ## block ## id ## _ ## reg_name
183 183
184#define VUPDATE_SRII(reg_name, block, id)\
185 .reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \
186 mm ## reg_name ## 0 ## _ ## block ## id
187
188/* set field/register/bitfield name */
189#define SFRB(field_name, reg_name, bitfield, post_fix)\
190 .field_name = reg_name ## __ ## bitfield ## post_fix
191
184/* NBIO */192/* NBIO */
185#define NBIO_BASE_INNER(seg) \193#define NBIO_BASE_INNER(seg) \
186 NBIF_BASE__INST0_SEG ## seg194 NBIF_BASE__INST0_SEG ## seg
@@ -419,11 +427,13 @@ static const struct dcn_mpc_registers mpc_regs = { · 232 unmodified lines
419};427};
420 428
421static const struct dcn_mpc_shift mpc_shift = {429static const struct dcn_mpc_shift mpc_shift = {
422 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)430 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT),\
431 SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, __SHIFT)
423};432};
424 433
425static const struct dcn_mpc_mask mpc_mask = {434static const struct dcn_mpc_mask mpc_mask = {
426 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),435 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),\
436 SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, _MASK)
427};437};
428 438
429#define tg_regs(id)\439#define tg_regs(id)\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c+2−1
@@ -2294,7 +2294,8 @@ void dcn20_fpga_init_hw(struct dc *dc) · 2293 unmodified lines
2294 2294
2295 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);2295 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
2296 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);2296 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
2297 REG_WRITE(REFCLK_CNTL, 0);2297 if (REG(REFCLK_CNTL))
2298 REG_WRITE(REFCLK_CNTL, 0);
2298 //2299 //
2299 2300
2300 2301
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c+1−0
@@ -52,6 +52,7 @@ static const struct hw_sequencer_funcs dcn20_funcs = { · 51 unmodified lines
52 .disable_plane = dcn20_disable_plane,52 .disable_plane = dcn20_disable_plane,
53 .pipe_control_lock = dcn20_pipe_control_lock,53 .pipe_control_lock = dcn20_pipe_control_lock,
54 .interdependent_update_lock = dcn10_lock_all_pipes,54 .interdependent_update_lock = dcn10_lock_all_pipes,
55 .cursor_lock = dcn10_cursor_lock,
55 .prepare_bandwidth = dcn20_prepare_bandwidth,56 .prepare_bandwidth = dcn20_prepare_bandwidth,
56 .optimize_bandwidth = dcn20_optimize_bandwidth,57 .optimize_bandwidth = dcn20_optimize_bandwidth,
57 .update_bandwidth = dcn20_update_bandwidth,58 .update_bandwidth = dcn20_update_bandwidth,
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c+1−0
@@ -545,6 +545,7 @@ const struct mpc_funcs dcn20_mpc_funcs = { · 544 unmodified lines
545 .mpc_init = mpc1_mpc_init,545 .mpc_init = mpc1_mpc_init,
546 .mpc_init_single_inst = mpc1_mpc_init_single_inst,546 .mpc_init_single_inst = mpc1_mpc_init_single_inst,
547 .update_blending = mpc2_update_blending,547 .update_blending = mpc2_update_blending,
548 .cursor_lock = mpc1_cursor_lock,
548 .get_mpcc_for_dpp = mpc2_get_mpcc_for_dpp,549 .get_mpcc_for_dpp = mpc2_get_mpcc_for_dpp,
549 .wait_for_idle = mpc2_assert_idle_mpcc,550 .wait_for_idle = mpc2_assert_idle_mpcc,
550 .assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect,551 .assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect,
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h+2−1
@@ -179,7 +179,8 @@ · 178 unmodified lines
179 SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\179 SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\
180 SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\180 SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\
181 SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\181 SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\
182 SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh)182 SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\
183 SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh)
183 184
184/*185/*
185 * DCN2 MPC_OCSC debug status register:186 * DCN2 MPC_OCSC debug status register:
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c+4−0
@@ -508,6 +508,10 @@ enum dcn20_clk_src_array_id { · 507 unmodified lines
508 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \508 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
509 mm ## block ## id ## _ ## reg_name509 mm ## block ## id ## _ ## reg_name
510 510
511#define VUPDATE_SRII(reg_name, block, id)\
512 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
513 mm ## reg_name ## _ ## block ## id
514
511/* NBIO */515/* NBIO */
512#define NBIO_BASE_INNER(seg) \516#define NBIO_BASE_INNER(seg) \
513 NBIO_BASE__INST0_SEG ## seg517 NBIO_BASE__INST0_SEG ## seg
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c+1−0
@@ -53,6 +53,7 @@ static const struct hw_sequencer_funcs dcn21_funcs = { · 52 unmodified lines
53 .disable_plane = dcn20_disable_plane,53 .disable_plane = dcn20_disable_plane,
54 .pipe_control_lock = dcn20_pipe_control_lock,54 .pipe_control_lock = dcn20_pipe_control_lock,
55 .interdependent_update_lock = dcn10_lock_all_pipes,55 .interdependent_update_lock = dcn10_lock_all_pipes,
56 .cursor_lock = dcn10_cursor_lock,
56 .prepare_bandwidth = dcn20_prepare_bandwidth,57 .prepare_bandwidth = dcn20_prepare_bandwidth,
57 .optimize_bandwidth = dcn20_optimize_bandwidth,58 .optimize_bandwidth = dcn20_optimize_bandwidth,
58 .update_bandwidth = dcn20_update_bandwidth,59 .update_bandwidth = dcn20_update_bandwidth,
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c+33−44
@@ -284,7 +284,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { · 283 unmodified lines
284 .dram_channel_width_bytes = 4,284 .dram_channel_width_bytes = 4,
285 .fabric_datapath_to_dcn_data_return_bytes = 32,285 .fabric_datapath_to_dcn_data_return_bytes = 32,
286 .dcn_downspread_percent = 0.5,286 .dcn_downspread_percent = 0.5,
287 .downspread_percent = 0.5,287 .downspread_percent = 0.38,
288 .dram_page_open_time_ns = 50.0,288 .dram_page_open_time_ns = 50.0,
289 .dram_rw_turnaround_time_ns = 17.5,289 .dram_rw_turnaround_time_ns = 17.5,
290 .dram_return_buffer_per_channel_bytes = 8192,290 .dram_return_buffer_per_channel_bytes = 8192,
@@ -340,6 +340,10 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { · 49 unmodified lines
340 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \340 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
341 mm ## block ## id ## _ ## reg_name341 mm ## block ## id ## _ ## reg_name
342 342
343#define VUPDATE_SRII(reg_name, block, id)\
344 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
345 mm ## reg_name ## _ ## block ## id
346
343/* NBIO */347/* NBIO */
344#define NBIO_BASE_INNER(seg) \348#define NBIO_BASE_INNER(seg) \
345 NBIF0_BASE__INST0_SEG ## seg349 NBIF0_BASE__INST0_SEG ## seg
@@ -1374,64 +1378,49 @@ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param · 1028 unmodified lines
1374{1378{
1375 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);1379 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
1376 struct clk_limit_table *clk_table = &bw_params->clk_table;1380 struct clk_limit_table *clk_table = &bw_params->clk_table;
1377 unsigned int i, j, k;1381 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
1378 int closest_clk_lvl;1382 unsigned int i, j, closest_clk_lvl;
1379 1383
1380 // Default clock levels are used for diags, which may lead to overclocking.1384 // Default clock levels are used for diags, which may lead to overclocking.
1381 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) && !IS_DIAG_DC(dc->ctx->dce_environment)) {1385 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
1382 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;1386 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1383 dcn2_1_ip.max_num_dpp = pool->base.pipe_count;1387 dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
1384 dcn2_1_soc.num_chans = bw_params->num_channels;1388 dcn2_1_soc.num_chans = bw_params->num_channels;
1385 1389
1386 /* Vmin: leave lowest DCN clocks, override with dcfclk, fclk, memclk from fuse */1390 ASSERT(clk_table->num_entries);
1387 dcn2_1_soc.clock_limits[0].state = 0;1391 for (i = 0; i < clk_table->num_entries; i++) {
1388 dcn2_1_soc.clock_limits[0].dcfclk_mhz = clk_table->entries[0].dcfclk_mhz;1392 /* loop backwards*/
1389 dcn2_1_soc.clock_limits[0].fabricclk_mhz = clk_table->entries[0].fclk_mhz;1393 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) {
1390 dcn2_1_soc.clock_limits[0].socclk_mhz = clk_table->entries[0].socclk_mhz;
1391 dcn2_1_soc.clock_limits[0].dram_speed_mts = clk_table->entries[0].memclk_mhz * 2;
1392
1393 /*
1394 * Other levels: find closest DCN clocks that fit the given clock limit using dcfclk
1395 * as indicator
1396 */
1397
1398 closest_clk_lvl = -1;
1399 /* index currently being filled */
1400 k = 1;
1401 for (i = 1; i < clk_table->num_entries; i++) {
1402 /* loop backwards, skip duplicate state*/
1403 for (j = dcn2_1_soc.num_states - 1; j >= k; j--) {
1404 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {1394 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
1405 closest_clk_lvl = j;1395 closest_clk_lvl = j;
1406 break;1396 break;
1407 }1397 }
1408 }1398 }
1409 1399
1410 /* if found a lvl that fits, use the DCN clks from it, if not, go to next clk limit*/1400 clock_limits[i].state = i;
1411 if (closest_clk_lvl != -1) {1401 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1412 dcn2_1_soc.clock_limits[k].state = i;1402 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1413 dcn2_1_soc.clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;1403 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
1414 dcn2_1_soc.clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;1404 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
1415 dcn2_1_soc.clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;1405
1416 dcn2_1_soc.clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;1406 clock_limits[i].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
1417 1407 clock_limits[i].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
1418 dcn2_1_soc.clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;1408 clock_limits[i].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
1419 dcn2_1_soc.clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;1409 clock_limits[i].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
1420 dcn2_1_soc.clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;1410 clock_limits[i].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
1421 dcn2_1_soc.clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;1411 clock_limits[i].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
1422 dcn2_1_soc.clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;1412 clock_limits[i].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
1423 dcn2_1_soc.clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;1413 }
1424 dcn2_1_soc.clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;1414 for (i = 0; i < clk_table->num_entries; i++)
1425 k++;1415 dcn2_1_soc.clock_limits[i] = clock_limits[i];
1426 }1416 if (clk_table->num_entries) {
1417 dcn2_1_soc.num_states = clk_table->num_entries;
1418 /* duplicate last level */
1419 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
1420 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
1427 }1421 }
1428 dcn2_1_soc.num_states = k;
1429 }1422 }
1430 1423
1431 /* duplicate last level */
1432 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
1433 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
1434
1435 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);1424 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1436}1425}
1437 1426
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h+16−0
@@ -210,6 +210,22 @@ struct mpc_funcs { · 209 unmodified lines
210 struct mpcc_blnd_cfg *blnd_cfg,210 struct mpcc_blnd_cfg *blnd_cfg,
211 int mpcc_id);211 int mpcc_id);
212 212
213 /*
214 * Lock cursor updates for the specified OPP.
215 * OPP defines the set of MPCC that are locked together for cursor.
216 *
217 * Parameters:
218 * [in] mpc - MPC context.
219 * [in] opp_id - The OPP to lock cursor updates on
220 * [in] lock - lock/unlock the OPP
221 *
222 * Return: void
223 */
224 void (*cursor_lock)(
225 struct mpc *mpc,
226 int opp_id,
227 bool lock);
228
213 struct mpcc* (*get_mpcc_for_dpp)(229 struct mpcc* (*get_mpcc_for_dpp)(
214 struct mpc_tree *tree,230 struct mpc_tree *tree,
215 int dpp_id);231 int dpp_id);
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h+1−0
@@ -86,6 +86,7 @@ struct hw_sequencer_funcs { · 85 unmodified lines
86 struct dc_state *context, bool lock);86 struct dc_state *context, bool lock);
87 void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx,87 void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx,
88 bool flip_immediate);88 bool flip_immediate);
89 void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock);
89 90
90 /* Timing Related */91 /* Timing Related */
91 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,92 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
drivers/gpu/drm/amd/powerplay/amd_powerplay.c+5−4
@@ -1435,7 +1435,8 @@ static int pp_get_asic_baco_capability(void *handle, bool *cap) · 1434 unmodified lines
1435 if (!hwmgr)1435 if (!hwmgr)
1436 return -EINVAL;1436 return -EINVAL;
1437 1437
1438 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_capability)1438 if (!(hwmgr->not_vf && amdgpu_dpm) ||
1439 !hwmgr->hwmgr_func->get_asic_baco_capability)
1439 return 0;1440 return 0;
1440 1441
1441 mutex_lock(&hwmgr->smu_lock);1442 mutex_lock(&hwmgr->smu_lock);
@@ -1452,8 +1453,7 @@ static int pp_get_asic_baco_state(void *handle, int *state) · 10 unmodified lines
1452 if (!hwmgr)1453 if (!hwmgr)
1453 return -EINVAL;1454 return -EINVAL;
1454 1455
1455 if (!(hwmgr->not_vf && amdgpu_dpm) ||1456 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_state)
1456 !hwmgr->hwmgr_func->get_asic_baco_state)
1457 return 0;1457 return 0;
1458 1458
1459 mutex_lock(&hwmgr->smu_lock);1459 mutex_lock(&hwmgr->smu_lock);
@@ -1470,7 +1470,8 @@ static int pp_set_asic_baco_state(void *handle, int state) · 10 unmodified lines
1470 if (!hwmgr)1470 if (!hwmgr)
1471 return -EINVAL;1471 return -EINVAL;
1472 1472
1473 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_asic_baco_state)1473 if (!(hwmgr->not_vf && amdgpu_dpm) ||
1474 !hwmgr->hwmgr_func->set_asic_baco_state)
1474 return 0;1475 return 0;
1475 1476
1476 mutex_lock(&hwmgr->smu_lock);1477 mutex_lock(&hwmgr->smu_lock);
drivers/gpu/drm/drm_dp_mst_topology.c+6−2
@@ -3442,8 +3442,12 @@ static int drm_dp_send_dpcd_write(struct drm_dp_mst_topology_mgr *mgr, · 3441 unmodified lines
3442 drm_dp_queue_down_tx(mgr, txmsg);3442 drm_dp_queue_down_tx(mgr, txmsg);
3443 3443
3444 ret = drm_dp_mst_wait_tx_reply(mstb, txmsg);3444 ret = drm_dp_mst_wait_tx_reply(mstb, txmsg);
3445 if (ret > 0 && txmsg->reply.reply_type == DP_SIDEBAND_REPLY_NAK)3445 if (ret > 0) {
3446 ret = -EIO;3446 if (txmsg->reply.reply_type == DP_SIDEBAND_REPLY_NAK)
3447 ret = -EIO;
3448 else
3449 ret = size;
3450 }
3447 3451
3448 kfree(txmsg);3452 kfree(txmsg);
3449fail_put:3453fail_put:
drivers/gpu/drm/drm_edid.c+1−1
@@ -5111,7 +5111,7 @@ static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *d · 5110 unmodified lines
5111 struct drm_display_mode *mode;5111 struct drm_display_mode *mode;
5112 unsigned pixel_clock = (timings->pixel_clock[0] |5112 unsigned pixel_clock = (timings->pixel_clock[0] |
5113 (timings->pixel_clock[1] << 8) |5113 (timings->pixel_clock[1] << 8) |
5114 (timings->pixel_clock[2] << 16));5114 (timings->pixel_clock[2] << 16)) + 1;
5115 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;5115 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
5116 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;5116 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
5117 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;5117 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
drivers/gpu/drm/i915/gem/i915_gem_tiling.c+18−2
@@ -182,21 +182,35 @@ i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj, · 181 unmodified lines
182 int tiling_mode, unsigned int stride)182 int tiling_mode, unsigned int stride)
183{183{
184 struct i915_ggtt *ggtt = &to_i915(obj->base.dev)->ggtt;184 struct i915_ggtt *ggtt = &to_i915(obj->base.dev)->ggtt;
185 struct i915_vma *vma;185 struct i915_vma *vma, *vn;
186 LIST_HEAD(unbind);
186 int ret = 0;187 int ret = 0;
187 188
188 if (tiling_mode == I915_TILING_NONE)189 if (tiling_mode == I915_TILING_NONE)
189 return 0;190 return 0;
190 191
191 mutex_lock(&ggtt->vm.mutex);192 mutex_lock(&ggtt->vm.mutex);
193
194 spin_lock(&obj->vma.lock);
192 for_each_ggtt_vma(vma, obj) {195 for_each_ggtt_vma(vma, obj) {
196 GEM_BUG_ON(vma->vm != &ggtt->vm);
197
193 if (i915_vma_fence_prepare(vma, tiling_mode, stride))198 if (i915_vma_fence_prepare(vma, tiling_mode, stride))
194 continue;199 continue;
195 200
201 list_move(&vma->vm_link, &unbind);
202 }
203 spin_unlock(&obj->vma.lock);
204
205 list_for_each_entry_safe(vma, vn, &unbind, vm_link) {
196 ret = __i915_vma_unbind(vma);206 ret = __i915_vma_unbind(vma);
197 if (ret)207 if (ret) {
208 /* Restore the remaining vma on an error */
209 list_splice(&unbind, &ggtt->vm.bound_list);
198 break;210 break;
211 }
199 }212 }
213
200 mutex_unlock(&ggtt->vm.mutex);214 mutex_unlock(&ggtt->vm.mutex);
201 215
202 return ret;216 return ret;
@@ -268,6 +282,7 @@ i915_gem_object_set_tiling(struct drm_i915_gem_object *obj, · 65 unmodified lines
268 }282 }
269 mutex_unlock(&obj->mm.lock);283 mutex_unlock(&obj->mm.lock);
270 284
285 spin_lock(&obj->vma.lock);
271 for_each_ggtt_vma(vma, obj) {286 for_each_ggtt_vma(vma, obj) {
272 vma->fence_size =287 vma->fence_size =
273 i915_gem_fence_size(i915, vma->size, tiling, stride);288 i915_gem_fence_size(i915, vma->size, tiling, stride);
@@ -278,6 +293,7 @@ i915_gem_object_set_tiling(struct drm_i915_gem_object *obj, · 4 unmodified lines
278 if (vma->fence)293 if (vma->fence)
279 vma->fence->dirty = true;294 vma->fence->dirty = true;
280 }295 }
296 spin_unlock(&obj->vma.lock);
281 297
282 obj->tiling_and_stride = tiling | stride;298 obj->tiling_and_stride = tiling | stride;
283 i915_gem_object_unlock(obj);299 i915_gem_object_unlock(obj);
drivers/gpu/drm/i915/gem/selftests/huge_pages.c+8−4
@@ -1477,8 +1477,10 @@ static int igt_ppgtt_pin_update(void *arg) · 1476 unmodified lines
1477 unsigned int page_size = BIT(first);1477 unsigned int page_size = BIT(first);
1478 1478
1479 obj = i915_gem_object_create_internal(dev_priv, page_size);1479 obj = i915_gem_object_create_internal(dev_priv, page_size);
1480 if (IS_ERR(obj))1480 if (IS_ERR(obj)) {
1481 return PTR_ERR(obj);1481 err = PTR_ERR(obj);
1482 goto out_vm;
1483 }
1482 1484
1483 vma = i915_vma_instance(obj, vm, NULL);1485 vma = i915_vma_instance(obj, vm, NULL);
1484 if (IS_ERR(vma)) {1486 if (IS_ERR(vma)) {
@@ -1531,8 +1533,10 @@ static int igt_ppgtt_pin_update(void *arg) · 46 unmodified lines
1531 }1533 }
1532 1534
1533 obj = i915_gem_object_create_internal(dev_priv, PAGE_SIZE);1535 obj = i915_gem_object_create_internal(dev_priv, PAGE_SIZE);
1534 if (IS_ERR(obj))1536 if (IS_ERR(obj)) {
1535 return PTR_ERR(obj);1537 err = PTR_ERR(obj);
1538 goto out_vm;
1539 }
1536 1540
1537 vma = i915_vma_instance(obj, vm, NULL);1541 vma = i915_vma_instance(obj, vm, NULL);
1538 if (IS_ERR(vma)) {1542 if (IS_ERR(vma)) {
drivers/gpu/drm/i915/gt/intel_timeline.c+2−0
@@ -521,6 +521,8 @@ int intel_timeline_read_hwsp(struct i915_request *from, · 520 unmodified lines
521 521
522 rcu_read_lock();522 rcu_read_lock();
523 cl = rcu_dereference(from->hwsp_cacheline);523 cl = rcu_dereference(from->hwsp_cacheline);
524 if (i915_request_completed(from)) /* confirm cacheline is valid */
525 goto unlock;
524 if (unlikely(!i915_active_acquire_if_busy(&cl->active)))526 if (unlikely(!i915_active_acquire_if_busy(&cl->active)))
525 goto unlock; /* seqno wrapped and completed! */527 goto unlock; /* seqno wrapped and completed! */
526 if (unlikely(i915_request_completed(from)))528 if (unlikely(i915_request_completed(from)))
drivers/gpu/drm/i915/i915_irq.c+2−4
@@ -3358,7 +3358,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) · 3357 unmodified lines
3358{3358{
3359 struct intel_uncore *uncore = &dev_priv->uncore;3359 struct intel_uncore *uncore = &dev_priv->uncore;
3360 3360
3361 u32 de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;3361 u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |
3362 GEN8_PIPE_CDCLK_CRC_DONE;
3362 u32 de_pipe_enables;3363 u32 de_pipe_enables;
3363 u32 de_port_masked = GEN8_AUX_CHANNEL_A;3364 u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3364 u32 de_port_enables;3365 u32 de_port_enables;
@@ -3369,13 +3370,10 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) · 4 unmodified lines
3369 de_misc_masked |= GEN8_DE_MISC_GSE;3370 de_misc_masked |= GEN8_DE_MISC_GSE;
3370 3371
3371 if (INTEL_GEN(dev_priv) >= 9) {3372 if (INTEL_GEN(dev_priv) >= 9) {
3372 de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3373 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |3373 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3374 GEN9_AUX_CHANNEL_D;3374 GEN9_AUX_CHANNEL_D;
3375 if (IS_GEN9_LP(dev_priv))3375 if (IS_GEN9_LP(dev_priv))
3376 de_port_masked |= BXT_DE_PORT_GMBUS;3376 de_port_masked |= BXT_DE_PORT_GMBUS;
3377 } else {
3378 de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3379 }3377 }
3380 3378
3381 if (INTEL_GEN(dev_priv) >= 11)3379 if (INTEL_GEN(dev_priv) >= 11)
drivers/gpu/drm/i915/i915_vma.c+6−4
@@ -158,16 +158,18 @@ vma_create(struct drm_i915_gem_object *obj, · 157 unmodified lines
158 158
159 GEM_BUG_ON(!IS_ALIGNED(vma->size, I915_GTT_PAGE_SIZE));159 GEM_BUG_ON(!IS_ALIGNED(vma->size, I915_GTT_PAGE_SIZE));
160 160
161 spin_lock(&obj->vma.lock);
162
161 if (i915_is_ggtt(vm)) {163 if (i915_is_ggtt(vm)) {
162 if (unlikely(overflows_type(vma->size, u32)))164 if (unlikely(overflows_type(vma->size, u32)))
163 goto err_vma;165 goto err_unlock;
164 166
165 vma->fence_size = i915_gem_fence_size(vm->i915, vma->size,167 vma->fence_size = i915_gem_fence_size(vm->i915, vma->size,
166 i915_gem_object_get_tiling(obj),168 i915_gem_object_get_tiling(obj),
167 i915_gem_object_get_stride(obj));169 i915_gem_object_get_stride(obj));
168 if (unlikely(vma->fence_size < vma->size || /* overflow */170 if (unlikely(vma->fence_size < vma->size || /* overflow */
169 vma->fence_size > vm->total))171 vma->fence_size > vm->total))
170 goto err_vma;172 goto err_unlock;
171 173
172 GEM_BUG_ON(!IS_ALIGNED(vma->fence_size, I915_GTT_MIN_ALIGNMENT));174 GEM_BUG_ON(!IS_ALIGNED(vma->fence_size, I915_GTT_MIN_ALIGNMENT));
173 175
@@ -179,8 +181,6 @@ vma_create(struct drm_i915_gem_object *obj, · 5 unmodified lines
179 __set_bit(I915_VMA_GGTT_BIT, __i915_vma_flags(vma));181 __set_bit(I915_VMA_GGTT_BIT, __i915_vma_flags(vma));
180 }182 }
181 183
182 spin_lock(&obj->vma.lock);
183
184 rb = NULL;184 rb = NULL;
185 p = &obj->vma.tree.rb_node;185 p = &obj->vma.tree.rb_node;
186 while (*p) {186 while (*p) {
@@ -225,6 +225,8 @@ vma_create(struct drm_i915_gem_object *obj, · 38 unmodified lines
225 225
226 return vma;226 return vma;
227 227
228err_unlock:
229 spin_unlock(&obj->vma.lock);
228err_vma:230err_vma:
229 i915_vma_free(vma);231 i915_vma_free(vma);
230 return ERR_PTR(-E2BIG);232 return ERR_PTR(-E2BIG);
drivers/gpu/drm/qxl/qxl_cmd.c+5−5
@@ -480,9 +480,10 @@ int qxl_hw_surface_alloc(struct qxl_device *qdev, · 479 unmodified lines
480 return ret;480 return ret;
481 481
482 ret = qxl_release_reserve_list(release, true);482 ret = qxl_release_reserve_list(release, true);
483 if (ret)483 if (ret) {
484 qxl_release_free(qdev, release);
484 return ret;485 return ret;
485 486 }
486 cmd = (struct qxl_surface_cmd *)qxl_release_map(qdev, release);487 cmd = (struct qxl_surface_cmd *)qxl_release_map(qdev, release);
487 cmd->type = QXL_SURFACE_CMD_CREATE;488 cmd->type = QXL_SURFACE_CMD_CREATE;
488 cmd->flags = QXL_SURF_FLAG_KEEP_DATA;489 cmd->flags = QXL_SURF_FLAG_KEEP_DATA;
@@ -499,8 +500,8 @@ int qxl_hw_surface_alloc(struct qxl_device *qdev, · 10 unmodified lines
499 /* no need to add a release to the fence for this surface bo,500 /* no need to add a release to the fence for this surface bo,
500 since it is only released when we ask to destroy the surface501 since it is only released when we ask to destroy the surface
501 and it would never signal otherwise */502 and it would never signal otherwise */
502 qxl_push_command_ring_release(qdev, release, QXL_CMD_SURFACE, false);
503 qxl_release_fence_buffer_objects(release);503 qxl_release_fence_buffer_objects(release);
504 qxl_push_command_ring_release(qdev, release, QXL_CMD_SURFACE, false);
504 505
505 surf->hw_surf_alloc = true;506 surf->hw_surf_alloc = true;
506 spin_lock(&qdev->surf_id_idr_lock);507 spin_lock(&qdev->surf_id_idr_lock);
@@ -542,9 +543,8 @@ int qxl_hw_surface_dealloc(struct qxl_device *qdev, · 35 unmodified lines
542 cmd->surface_id = id;543 cmd->surface_id = id;
543 qxl_release_unmap(qdev, release, &cmd->release_info);544 qxl_release_unmap(qdev, release, &cmd->release_info);
544 545
545 qxl_push_command_ring_release(qdev, release, QXL_CMD_SURFACE, false);
546
547 qxl_release_fence_buffer_objects(release);546 qxl_release_fence_buffer_objects(release);
547 qxl_push_command_ring_release(qdev, release, QXL_CMD_SURFACE, false);
548 548
549 return 0;549 return 0;
550}550}
drivers/gpu/drm/qxl/qxl_display.c+3−3
@@ -510,8 +510,8 @@ static int qxl_primary_apply_cursor(struct drm_plane *plane) · 509 unmodified lines
510 cmd->u.set.visible = 1;510 cmd->u.set.visible = 1;
511 qxl_release_unmap(qdev, release, &cmd->release_info);511 qxl_release_unmap(qdev, release, &cmd->release_info);
512 512
513 qxl_push_cursor_ring_release(qdev, release, QXL_CMD_CURSOR, false);
514 qxl_release_fence_buffer_objects(release);513 qxl_release_fence_buffer_objects(release);
514 qxl_push_cursor_ring_release(qdev, release, QXL_CMD_CURSOR, false);
515 515
516 return ret;516 return ret;
517 517
@@ -652,8 +652,8 @@ static void qxl_cursor_atomic_update(struct drm_plane *plane, · 134 unmodified lines
652 cmd->u.position.y = plane->state->crtc_y + fb->hot_y;652 cmd->u.position.y = plane->state->crtc_y + fb->hot_y;
653 653
654 qxl_release_unmap(qdev, release, &cmd->release_info);654 qxl_release_unmap(qdev, release, &cmd->release_info);
655 qxl_push_cursor_ring_release(qdev, release, QXL_CMD_CURSOR, false);
656 qxl_release_fence_buffer_objects(release);655 qxl_release_fence_buffer_objects(release);
656 qxl_push_cursor_ring_release(qdev, release, QXL_CMD_CURSOR, false);
657 657
658 if (old_cursor_bo != NULL)658 if (old_cursor_bo != NULL)
659 qxl_bo_unpin(old_cursor_bo);659 qxl_bo_unpin(old_cursor_bo);
@@ -700,8 +700,8 @@ static void qxl_cursor_atomic_disable(struct drm_plane *plane, · 40 unmodified lines
700 cmd->type = QXL_CURSOR_HIDE;700 cmd->type = QXL_CURSOR_HIDE;
701 qxl_release_unmap(qdev, release, &cmd->release_info);701 qxl_release_unmap(qdev, release, &cmd->release_info);
702 702
703 qxl_push_cursor_ring_release(qdev, release, QXL_CMD_CURSOR, false);
704 qxl_release_fence_buffer_objects(release);703 qxl_release_fence_buffer_objects(release);
704 qxl_push_cursor_ring_release(qdev, release, QXL_CMD_CURSOR, false);
705}705}
706 706
707static void qxl_update_dumb_head(struct qxl_device *qdev,707static void qxl_update_dumb_head(struct qxl_device *qdev,
drivers/gpu/drm/qxl/qxl_draw.c+4−3
@@ -209,9 +209,10 @@ void qxl_draw_dirty_fb(struct qxl_device *qdev, · 208 unmodified lines
209 goto out_release_backoff;209 goto out_release_backoff;
210 210
211 rects = drawable_set_clipping(qdev, num_clips, clips_bo);211 rects = drawable_set_clipping(qdev, num_clips, clips_bo);
212 if (!rects)212 if (!rects) {
213 ret = -EINVAL;
213 goto out_release_backoff;214 goto out_release_backoff;
214 215 }
215 drawable = (struct qxl_drawable *)qxl_release_map(qdev, release);216 drawable = (struct qxl_drawable *)qxl_release_map(qdev, release);
216 217
217 drawable->clip.type = SPICE_CLIP_TYPE_RECTS;218 drawable->clip.type = SPICE_CLIP_TYPE_RECTS;
@@ -242,8 +243,8 @@ void qxl_draw_dirty_fb(struct qxl_device *qdev, · 24 unmodified lines
242 }243 }
243 qxl_bo_kunmap(clips_bo);244 qxl_bo_kunmap(clips_bo);
244 245
245 qxl_push_command_ring_release(qdev, release, QXL_CMD_DRAW, false);
246 qxl_release_fence_buffer_objects(release);246 qxl_release_fence_buffer_objects(release);
247 qxl_push_command_ring_release(qdev, release, QXL_CMD_DRAW, false);
247 248
248out_release_backoff:249out_release_backoff:
249 if (ret)250 if (ret)
drivers/gpu/drm/qxl/qxl_image.c+2−1
@@ -212,7 +212,8 @@ qxl_image_init_helper(struct qxl_device *qdev, · 211 unmodified lines
212 break;212 break;
213 default:213 default:
214 DRM_ERROR("unsupported image bit depth\n");214 DRM_ERROR("unsupported image bit depth\n");
215 return -EINVAL; /* TODO: cleanup */215 qxl_bo_kunmap_atomic_page(qdev, image_bo, ptr);
216 return -EINVAL;
216 }217 }
217 image->u.bitmap.flags = QXL_BITMAP_TOP_DOWN;218 image->u.bitmap.flags = QXL_BITMAP_TOP_DOWN;
218 image->u.bitmap.x = width;219 image->u.bitmap.x = width;
drivers/gpu/drm/qxl/qxl_ioctl.c+1−4
@@ -261,11 +261,8 @@ static int qxl_process_single_command(struct qxl_device *qdev, · 260 unmodified lines
261 apply_surf_reloc(qdev, &reloc_info[i]);261 apply_surf_reloc(qdev, &reloc_info[i]);
262 }262 }
263 263
264 qxl_release_fence_buffer_objects(release);
264 ret = qxl_push_command_ring_release(qdev, release, cmd->type, true);265 ret = qxl_push_command_ring_release(qdev, release, cmd->type, true);
265 if (ret)
266 qxl_release_backoff_reserve_list(release);
267 else
268 qxl_release_fence_buffer_objects(release);
269 266
270out_free_bos:267out_free_bos:
271out_free_release:268out_free_release:
drivers/gpu/drm/virtio/virtgpu_kms.c+6−11
@@ -53,14 +53,6 @@ static void virtio_gpu_config_changed_work_func(struct work_struct *work) · 52 unmodified lines
53 events_clear, &events_clear);53 events_clear, &events_clear);
54}54}
55 55
56static void virtio_gpu_context_destroy(struct virtio_gpu_device *vgdev,
57 uint32_t ctx_id)
58{
59 virtio_gpu_cmd_context_destroy(vgdev, ctx_id);
60 virtio_gpu_notify(vgdev);
61 ida_free(&vgdev->ctx_id_ida, ctx_id - 1);
62}
63
64static void virtio_gpu_init_vq(struct virtio_gpu_queue *vgvq,56static void virtio_gpu_init_vq(struct virtio_gpu_queue *vgvq,
65 void (*work_func)(struct work_struct *work))57 void (*work_func)(struct work_struct *work))
66{58{
@@ -275,14 +267,17 @@ int virtio_gpu_driver_open(struct drm_device *dev, struct drm_file *file) · 208 unmodified lines
275void virtio_gpu_driver_postclose(struct drm_device *dev, struct drm_file *file)267void virtio_gpu_driver_postclose(struct drm_device *dev, struct drm_file *file)
276{268{
277 struct virtio_gpu_device *vgdev = dev->dev_private;269 struct virtio_gpu_device *vgdev = dev->dev_private;
278 struct virtio_gpu_fpriv *vfpriv;270 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
279 271
280 if (!vgdev->has_virgl_3d)272 if (!vgdev->has_virgl_3d)
281 return;273 return;
282 274
283 vfpriv = file->driver_priv;275 if (vfpriv->context_created) {
276 virtio_gpu_cmd_context_destroy(vgdev, vfpriv->ctx_id);
277 virtio_gpu_notify(vgdev);
278 }
284 279
285 virtio_gpu_context_destroy(vgdev, vfpriv->ctx_id);280 ida_free(&vgdev->ctx_id_ida, vfpriv->ctx_id - 1);
286 mutex_destroy(&vfpriv->context_lock);281 mutex_destroy(&vfpriv->context_lock);
287 kfree(vfpriv);282 kfree(vfpriv);
288 file->driver_priv = NULL;283 file->driver_priv = NULL;
include/linux/dma-buf.h+1−2
@@ -329,13 +329,12 @@ struct dma_buf { · 328 unmodified lines
329 329
330/**330/**
331 * struct dma_buf_attach_ops - importer operations for an attachment331 * struct dma_buf_attach_ops - importer operations for an attachment
332 * @move_notify: [optional] notification that the DMA-buf is moving
333 *332 *
334 * Attachment operations implemented by the importer.333 * Attachment operations implemented by the importer.
335 */334 */
336struct dma_buf_attach_ops {335struct dma_buf_attach_ops {
337 /**336 /**
338 * @move_notify337 * @move_notify: [optional] notification that the DMA-buf is moving
339 *338 *
340 * If this callback is provided the framework can avoid pinning the339 * If this callback is provided the framework can avoid pinning the
341 * backing store while mappings exists.340 * backing store while mappings exists.
include/uapi/drm/amdgpu_drm.h+4−0
@@ -346,6 +346,10 @@ struct drm_amdgpu_gem_userptr { · 345 unmodified lines
346#define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF346#define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF
347#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43347#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43
348#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1348#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1
349#define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44
350#define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1
351#define AMDGPU_TILING_SCANOUT_SHIFT 63
352#define AMDGPU_TILING_SCANOUT_MASK 0x1
349 353
350/* Set/Get helpers for tiling flags. */354/* Set/Get helpers for tiling flags. */
351#define AMDGPU_TILING_SET(field, value) \355#define AMDGPU_TILING_SET(field, value) \
include/uapi/linux/dma-buf.h+6−0
@@ -39,6 +39,12 @@ struct dma_buf_sync { · 38 unmodified lines
39 39
40#define DMA_BUF_BASE 'b'40#define DMA_BUF_BASE 'b'
41#define DMA_BUF_IOCTL_SYNC _IOW(DMA_BUF_BASE, 0, struct dma_buf_sync)41#define DMA_BUF_IOCTL_SYNC _IOW(DMA_BUF_BASE, 0, struct dma_buf_sync)
42
43/* 32/64bitness of this uapi was botched in android, there's no difference
44 * between them in actual uapi, they're just different numbers.
45 */
42#define DMA_BUF_SET_NAME _IOW(DMA_BUF_BASE, 1, const char *)46#define DMA_BUF_SET_NAME _IOW(DMA_BUF_BASE, 1, const char *)
47#define DMA_BUF_SET_NAME_A _IOW(DMA_BUF_BASE, 1, u32)
48#define DMA_BUF_SET_NAME_B _IOW(DMA_BUF_BASE, 1, u64)
43 49
44#endif50#endif