Pull drm fixes from Dave Airlie: "Regular scheduled fixes for graphics. Nothing to extreme bunch of amdgpu fixes, i915 and qxl fixes, along with some misc ones. All seems to be progressing normally. core: - EDID off by one DTD fix - DP mst write return code fix dma-buf: - fix SET_NAME ioctl uapi - doc fixes amdgpu: - Fix a green screen on resume issue - PM fixes for SR-IOV SDMA fix for navi - Renoir display fixes - Cursor and pageflip stuttering fixes - Misc additional display fixes - (uapi) Add additional DCC tiling flags for navi1x i915: - Fix selftest refcnt leak (Xiyu) - Fix gem vma lock (Chris) - Fix gt's i915_request.timeline acquire by checking if cacheline is valid (Chris) - Fix IRQ postinistall fault masks (Matt) qxl: - use after gree fix - fix lost kunmap - release leak fix virtio: - context destruction fix" * tag 'drm-fixes-2020-05-01' of git://anongit.freedesktop.org/drm/drm: (26 commits) dma-buf: fix documentation build warnings drm/qxl: qxl_release use after free drm/qxl: lost qxl_bo_kunmap_atomic_page in qxl_image_init_helper() drm/i915: Use proper fault mask in interrupt postinstall too drm/amd/display: Use cursor locking to prevent flip delays drm/amd/display: Update downspread percent to match spreadsheet for DCN2.1 drm/amd/display: Defer cursor update around VUPDATE for all ASIC drm/amd/display: fix rn soc bb update drm/amd/display: check if REFCLK_CNTL register is present drm/amdgpu: bump version for invalidate L2 before SDMA IBs drm/amdgpu: invalidate L2 before SDMA IBs (v2) drm/amdgpu: add tiling flags from Mesa drm/amd/powerplay: avoid using pm_en before it is initialized revised Revert "drm/amd/powerplay: avoid using pm_en before it is initialized" drm/qxl: qxl_release leak in qxl_hw_surface_alloc() drm/qxl: qxl_release leak in qxl_draw_dirty_fb() drm/virtio: only destroy created contexts drm/dp_mst: Fix drm_dp_send_dpcd_write() return code drm/i915/gt: Check cacheline is valid before acquiring drm/i915/gem: Hold obj->vma.lock over for_each_ggtt_vma() ...
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| @@ -346,6 +346,10 @@ struct drm_amdgpu_gem_userptr { · 345 unmodified lines | |||
| 346 | #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF | 346 | #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF |
| 347 | #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 | 347 | #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 |
| 348 | #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 | 348 | #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 |
| 349 | #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 | ||
| 350 | #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 | ||
| 351 | #define AMDGPU_TILING_SCANOUT_SHIFT 63 | ||
| 352 | #define AMDGPU_TILING_SCANOUT_MASK 0x1 | ||
| 349 | 353 | ||
| 350 | /* Set/Get helpers for tiling flags. */ | 354 | /* Set/Get helpers for tiling flags. */ |
| 351 | #define AMDGPU_TILING_SET(field, value) \ | 355 | #define AMDGPU_TILING_SET(field, value) \ |
| @@ -39,6 +39,12 @@ struct dma_buf_sync { · 38 unmodified lines | |||
| 39 | 39 | ||
| 40 | #define DMA_BUF_BASE 'b' | 40 | #define DMA_BUF_BASE 'b' |
| 41 | #define DMA_BUF_IOCTL_SYNC _IOW(DMA_BUF_BASE, 0, struct dma_buf_sync) | 41 | #define DMA_BUF_IOCTL_SYNC _IOW(DMA_BUF_BASE, 0, struct dma_buf_sync) |
| 42 | |||
| 43 | /* 32/64bitness of this uapi was botched in android, there's no difference | ||
| 44 | * between them in actual uapi, they're just different numbers. | ||
| 45 | */ | ||
| 42 | #define DMA_BUF_SET_NAME _IOW(DMA_BUF_BASE, 1, const char *) | 46 | #define DMA_BUF_SET_NAME _IOW(DMA_BUF_BASE, 1, const char *) |
| 47 | #define DMA_BUF_SET_NAME_A _IOW(DMA_BUF_BASE, 1, u32) | ||
| 48 | #define DMA_BUF_SET_NAME_B _IOW(DMA_BUF_BASE, 1, u64) | ||
| 43 | 49 | ||
| 44 | #endif | 50 | #endif |