Merge tag 'drm-next-2021-08-31-1' of git://anongit.freedesktop.org/drm/drm

Pull drm updates from Dave Airlie: "Highlights: - i915 has seen a lot of refactoring and uAPI cleanups due to a change in the upstream direction going forward This has all been audited with known userspace, but there may be some pitfalls that were missed. - i915 now uses common TTM to enable discrete memory on DG1/2 GPUs - i915 enables Jasper and Elkhart Lake by default and has preliminary XeHP/DG2 support - amdgpu adds support for Cyan Skillfish - lots of implicit fencing rules documented and fixed up in drivers - msm now uses the core scheduler - the irq midlayer has been removed for non-legacy drivers - the sysfb code now works on more than x86. Otherwise the usual smattering of stuff everywhere, panels, bridges, refactorings. Detailed summary: core: - extract i915 eDP backlight into core - DP aux bus support - drm_device.irq_enabled removed - port drivers to native irq interfaces - export gem shadow plane handling for vgem - print proper driver name in framebuffer registration - driver fixes for implicit fencing rules - ARM fixed rate compression modifier added - updated fb damage handling - rmfb ioctl logging/docs - drop drm_gem_object_put_locked - define DRM_FORMAT_MAX_PLANES - add gem fb vmap/vunmap helpers - add lockdep_assert(once) helpers - mark drm irq midlayer as legacy - use offset adjusted bo mapping conversion vgaarb: - cleanups fbdev: - extend efifb handling to all arches - div by 0 fixes for multiple drivers udmabuf: - add hugepage mapping support dma-buf: - non-dynamic exporter fixups - document implicit fencing rules amdgpu: - Initial Cyan Skillfish support - switch virtual DCE over to vkms based atomic - VCN/JPEG power down fixes - NAVI PCIE link handling fixes - AMD HDMI freesync fixes - Yellow Carp + Beige Goby fixes - Clockgating/S0ix/SMU/EEPROM fixes - embed hw fence in job - rework dma-resv handling - ensure eviction to system ram amdkfd: - uapi: SVM address range query added - sysfs leak fix - GPUVM TLB optimizations - vmfault/migration counters i915: - Enable JSL and EHL by default - preliminary XeHP/DG2 support - remove all CNL support (never shipped) - move to TTM for discrete memory support - allow mixed object mmap handling - GEM uAPI spring cleaning - add I915_MMAP_OBJECT_FIXED - reinstate ADL-P mmap ioctls - drop a bunch of unused by userspace features - disable and remove GPU relocations - revert some i915 misfeatures - major refactoring of GuC for Gen11+ - execbuffer object locking separate step - reject caching/set-domain on discrete - Enable pipe DMC loading on XE-LPD and ADL-P - add PSF GV point support - Refactor and fix DDI buffer translations - Clean up FBC CFB allocation code - Finish INTEL_GEN() and friends macro conversions nouveau: - add eDP backlight support - implicit fence fix msm: - a680/7c3 support - drm/scheduler conversion panfrost: - rework GPU reset virtio: - fix fencing for planes ast: - add detect support bochs: - move to tiny GPU driver vc4: - use hotplug irqs - HDMI codec support vmwgfx: - use internal vmware device headers ingenic: - demidlayering irq rcar-du: - shutdown fixes - convert to bridge connector helpers zynqmp-dsub: - misc fixes mgag200: - convert PLL handling to atomic mediatek: - MT8133 AAL support - gem mmap object support - MT8167 support etnaviv: - NXP Layerscape LS1028A SoC support - GEM mmap cleanups tegra: - new user API exynos: - missing unlock fix - build warning fix - use refcount_t" * tag 'drm-next-2021-08-31-1' of git://anongit.freedesktop.org/drm/drm: (1318 commits) drm/amd/display: Move AllowDRAMSelfRefreshOrDRAMClockChangeInVblank to bounding box drm/amd/display: Remove duplicate dml init drm/amd/display: Update bounding box states (v2) drm/amd/display: Update number of DCN3 clock states drm/amdgpu: disable GFX CGCG in aldebaran drm/amdgpu: Clear RAS interrupt status on aldebaran drm/amdgpu: Add support for RAS XGMI err query drm/amdkfd: Account for SH/SE count when setting up cu masks. drm/amdgpu: rename amdgpu_bo_get_preferred_pin_domain drm/amdgpu: drop redundant cancel_delayed_work_sync call drm/amdgpu: add missing cleanups for more ASICs on UVD/VCE suspend drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend drm/amdkfd: map SVM range with correct access permission drm/amdkfd: check access permisson to restore retry fault drm/amdgpu: Update RAS XGMI Error Query drm/amdgpu: Add driver infrastructure for MCA RAS drm/amd/display: Add Logging for HDMI color depth information drm/amd/amdgpu: consolidate PSP TA init shared buf functions drm/amd/amdgpu: add name field back to ras_common_if drm/amdgpu: Fix build with missing pm_suspend_target_state module export ...

Linus Torvalds committed 5 years ago

Commit 477f70c2 parents 835d31d 8f0284f1124 files · +62925 −35691Browse files

Showing the changes to include/uapi (10 of 1124 files). Show all

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10 files

include/uapi/drm/drm.h +12 −2
include/uapi/drm/drm_fourcc.h +106 −3
include/uapi/drm/drm_mode.h +88 −4
include/uapi/drm/i915_drm.h +417 −81
include/uapi/drm/msm_drm.h +13 −1
include/uapi/drm/tegra_drm.h +402 −23
include/uapi/drm/v3d_drm.h +136 −0
include/uapi/drm/vmwgfx_drm.h +41 −0
include/uapi/linux/dma-buf.h +49 −1
include/uapi/linux/kfd_ioctl.h +9 −7

include/uapi/drm/drm.h+12−2

 /**
  * DRM_CAP_VBLANK_HIGH_CRTC
  *
- * If set to 1, the kernel supports specifying a CRTC index in the high bits of
+ * If set to 1, the kernel supports specifying a :ref:`CRTC index<crtc_index>`
- * &drm_wait_vblank_request.type.
+ * in the high bits of &drm_wait_vblank_request.type.
  *
  * Starting kernel version 2.6.39, this capability is always set to 1.
  */
 #define DRM_IOCTL_MODE_GETPROPBLOB	DRM_IOWR(0xAC, struct drm_mode_get_blob)
 #define DRM_IOCTL_MODE_GETFB		DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
 #define DRM_IOCTL_MODE_ADDFB		DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
+/**
+ * DRM_IOCTL_MODE_RMFB - Remove a framebuffer.
+ *
+ * This removes a framebuffer previously added via ADDFB/ADDFB2. The IOCTL
+ * argument is a framebuffer object ID.
+ *
+ * Warning: removing a framebuffer currently in-use on an enabled plane will
+ * disable that plane. The CRTC the plane is linked to may also be disabled
+ * (depending on driver capabilities).
+ */
 #define DRM_IOCTL_MODE_RMFB		DRM_IOWR(0xAF, unsigned int)
 #define DRM_IOCTL_MODE_PAGE_FLIP	DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
 #define DRM_IOCTL_MODE_DIRTYFB		DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)

include/uapi/drm/drm_fourcc.h+106−3

@@ -900,9 +900,9 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) · 899 unmodified lines
900		900
901	/*	901	/*
902	* The top 4 bits (out of the 56 bits alloted for specifying vendor specific	902	* The top 4 bits (out of the 56 bits alloted for specifying vendor specific
903	* modifiers) denote the category for modifiers. Currently we have only two	903	* modifiers) denote the category for modifiers. Currently we have three
904	* categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen	904	* categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
905	* different categories.	905	* sixteen different categories.
906	*/	906	*/
907	#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \	907	#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
908	fourcc_mod_code(ARM, ((__u64)(__type) << 52) \| ((__val) & 0x000fffffffffffffULL))	908	fourcc_mod_code(ARM, ((__u64)(__type) << 52) \| ((__val) & 0x000fffffffffffffULL))
@@ -1017,6 +1017,109 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) · 108 unmodified lines
1017	*/	1017	*/
1018	#define AFBC_FORMAT_MOD_USM (1ULL << 12)	1018	#define AFBC_FORMAT_MOD_USM (1ULL << 12)
1019		1019
		1020	/*
		1021	* Arm Fixed-Rate Compression (AFRC) modifiers
		1022	*
		1023	* AFRC is a proprietary fixed rate image compression protocol and format,
		1024	* designed to provide guaranteed bandwidth and memory footprint
		1025	* reductions in graphics and media use-cases.
		1026	*
		1027	* AFRC buffers consist of one or more planes, with the same components
		1028	* and meaning as an uncompressed buffer using the same pixel format.
		1029	*
		1030	* Within each plane, the pixel/luma/chroma values are grouped into
		1031	* "coding unit" blocks which are individually compressed to a
		1032	* fixed size (in bytes). All coding units within a given plane of a buffer
		1033	* store the same number of values, and have the same compressed size.
		1034	*
		1035	* The coding unit size is configurable, allowing different rates of compression.
		1036	*
		1037	* The start of each AFRC buffer plane must be aligned to an alignment granule which
		1038	* depends on the coding unit size.
		1039	*
		1040	* Coding Unit Size Plane Alignment
		1041	* ---------------- ---------------
		1042	* 16 bytes 1024 bytes
		1043	* 24 bytes 512 bytes
		1044	* 32 bytes 2048 bytes
		1045	*
		1046	* Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned
		1047	* to a multiple of the paging tile dimensions.
		1048	* The dimensions of each paging tile depend on whether the buffer is optimised for
		1049	* scanline (SCAN layout) or rotated (ROT layout) access.
		1050	*
		1051	* Layout Paging Tile Width Paging Tile Height
		1052	* ------ ----------------- ------------------
		1053	* SCAN 16 coding units 4 coding units
		1054	* ROT 8 coding units 8 coding units
		1055	*
		1056	* The dimensions of each coding unit depend on the number of components
		1057	* in the compressed plane and whether the buffer is optimised for
		1058	* scanline (SCAN layout) or rotated (ROT layout) access.
		1059	*
		1060	* Number of Components in Plane Layout Coding Unit Width Coding Unit Height
		1061	* ----------------------------- --------- ----------------- ------------------
		1062	* 1 SCAN 16 samples 4 samples
		1063	* Example: 16x4 luma samples in a 'Y' plane
		1064	* 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
		1065	* ----------------------------- --------- ----------------- ------------------
		1066	* 1 ROT 8 samples 8 samples
		1067	* Example: 8x8 luma samples in a 'Y' plane
		1068	* 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
		1069	* ----------------------------- --------- ----------------- ------------------
		1070	* 2 DONT CARE 8 samples 4 samples
		1071	* Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
		1072	* ----------------------------- --------- ----------------- ------------------
		1073	* 3 DONT CARE 4 samples 4 samples
		1074	* Example: 4x4 pixels in an RGB buffer without alpha
		1075	* ----------------------------- --------- ----------------- ------------------
		1076	* 4 DONT CARE 4 samples 4 samples
		1077	* Example: 4x4 pixels in an RGB buffer with alpha
		1078	*/
		1079
		1080	#define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02
		1081
		1082	#define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \
		1083	DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode)
		1084
		1085	/*
		1086	* AFRC coding unit size modifier.
		1087	*
		1088	* Indicates the number of bytes used to store each compressed coding unit for
		1089	* one or more planes in an AFRC encoded buffer. The coding unit size for chrominance
		1090	* is the same for both Cb and Cr, which may be stored in separate planes.
		1091	*
		1092	* AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store
		1093	* each compressed coding unit in the first plane of the buffer. For RGBA buffers
		1094	* this is the only plane, while for semi-planar and fully-planar YUV buffers,
		1095	* this corresponds to the luma plane.
		1096	*
		1097	* AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store
		1098	* each compressed coding unit in the second and third planes in the buffer.
		1099	* For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s).
		1100	*
		1101	* For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified
		1102	* and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero.
		1103	* For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and
		1104	* AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified.
		1105	*/
		1106	#define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf
		1107	#define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL)
		1108	#define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL)
		1109	#define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL)
		1110
		1111	#define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size)
		1112	#define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4)
		1113
		1114	/*
		1115	* AFRC scanline memory layout.
		1116	*
		1117	* Indicates if the buffer uses the scanline-optimised layout
		1118	* for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
		1119	* The memory layout is the same for all planes.
		1120	*/
		1121	#define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8)
		1122
1020	/*	1123	/*
1021	* Arm 16x16 Block U-Interleaved modifier	1124	* Arm 16x16 Block U-Interleaved modifier
1022	*	1125	*

include/uapi/drm/drm_mode.h+88−4

@@ -312,16 +312,48 @@ struct drm_mode_set_plane { · 311 unmodified lines
312	__u32 src_w;	312	__u32 src_w;
313	};	313	};
314		314
		315	/**
		316	* struct drm_mode_get_plane - Get plane metadata.
		317	*
		318	* Userspace can perform a GETPLANE ioctl to retrieve information about a
		319	* plane.
		320	*
		321	* To retrieve the number of formats supported, set @count_format_types to zero
		322	* and call the ioctl. @count_format_types will be updated with the value.
		323	*
		324	* To retrieve these formats, allocate an array with the memory needed to store
		325	* @count_format_types formats. Point @format_type_ptr to this array and call
		326	* the ioctl again (with @count_format_types still set to the value returned in
		327	* the first ioctl call).
		328	*/
315	struct drm_mode_get_plane {	329	struct drm_mode_get_plane {
		330	/**
		331	* @plane_id: Object ID of the plane whose information should be
		332	* retrieved. Set by caller.
		333	*/
316	__u32 plane_id;	334	__u32 plane_id;
317		335
		336	/** @crtc_id: Object ID of the current CRTC. */
318	__u32 crtc_id;	337	__u32 crtc_id;
		338	/** @fb_id: Object ID of the current fb. */
319	__u32 fb_id;	339	__u32 fb_id;
320		340
		341	/**
		342	* @possible_crtcs: Bitmask of CRTC's compatible with the plane. CRTC's
		343	* are created and they receive an index, which corresponds to their
		344	* position in the bitmask. Bit N corresponds to
		345	* :ref:`CRTC index<crtc_index>` N.
		346	*/
321	__u32 possible_crtcs;	347	__u32 possible_crtcs;
		348	/** @gamma_size: Never used. */
322	__u32 gamma_size;	349	__u32 gamma_size;
323		350
		351	/** @count_format_types: Number of formats. */
324	__u32 count_format_types;	352	__u32 count_format_types;
		353	/**
		354	* @format_type_ptr: Pointer to ``__u32`` array of formats that are
		355	* supported by the plane. These formats do not require modifiers.
		356	*/
325	__u64 format_type_ptr;	357	__u64 format_type_ptr;
326	};	358	};
327		359
@@ -509,22 +541,74 @@ struct drm_mode_get_connector { · 181 unmodified lines
509	*/	541	*/
510	#define DRM_MODE_PROP_ATOMIC 0x80000000	542	#define DRM_MODE_PROP_ATOMIC 0x80000000
511		543
		544	/**
		545	* struct drm_mode_property_enum - Description for an enum/bitfield entry.
		546	* @value: numeric value for this enum entry.
		547	* @name: symbolic name for this enum entry.
		548	*
		549	* See struct drm_property_enum for details.
		550	*/
512	struct drm_mode_property_enum {	551	struct drm_mode_property_enum {
513	__u64 value;	552	__u64 value;
514	char name[DRM_PROP_NAME_LEN];	553	char name[DRM_PROP_NAME_LEN];
515	};	554	};
516		555
		556	/**
		557	* struct drm_mode_get_property - Get property metadata.
		558	*
		559	* User-space can perform a GETPROPERTY ioctl to retrieve information about a
		560	* property. The same property may be attached to multiple objects, see
		561	* "Modeset Base Object Abstraction".
		562	*
		563	* The meaning of the @values_ptr field changes depending on the property type.
		564	* See &drm_property.flags for more details.
		565	*
		566	* The @enum_blob_ptr and @count_enum_blobs fields are only meaningful when the
		567	* property has the type &DRM_MODE_PROP_ENUM or &DRM_MODE_PROP_BITMASK. For
		568	* backwards compatibility, the kernel will always set @count_enum_blobs to
		569	* zero when the property has the type &DRM_MODE_PROP_BLOB. User-space must
		570	* ignore these two fields if the property has a different type.
		571	*
		572	* User-space is expected to retrieve values and enums by performing this ioctl
		573	* at least twice: the first time to retrieve the number of elements, the
		574	* second time to retrieve the elements themselves.
		575	*
		576	* To retrieve the number of elements, set @count_values and @count_enum_blobs
		577	* to zero, then call the ioctl. @count_values will be updated with the number
		578	* of elements. If the property has the type &DRM_MODE_PROP_ENUM or
		579	* &DRM_MODE_PROP_BITMASK, @count_enum_blobs will be updated as well.
		580	*
		581	* To retrieve the elements themselves, allocate an array for @values_ptr and
		582	* set @count_values to its capacity. If the property has the type
		583	* &DRM_MODE_PROP_ENUM or &DRM_MODE_PROP_BITMASK, allocate an array for
		584	* @enum_blob_ptr and set @count_enum_blobs to its capacity. Calling the ioctl
		585	* again will fill the arrays.
		586	*/
517	struct drm_mode_get_property {	587	struct drm_mode_get_property {
518	__u64 values_ptr; /* values and blob lengths */	588	/** @values_ptr: Pointer to a ``__u64`` array. */
519	__u64 enum_blob_ptr; /* enum and blob id ptrs */	589	__u64 values_ptr;
		590	/** @enum_blob_ptr: Pointer to a struct drm_mode_property_enum array. */
		591	__u64 enum_blob_ptr;
520		592
		593	/**
		594	* @prop_id: Object ID of the property which should be retrieved. Set
		595	* by the caller.
		596	*/
521	__u32 prop_id;	597	__u32 prop_id;
		598	/**
		599	* @flags: ``DRM_MODE_PROP_*`` bitfield. See &drm_property.flags for
		600	* a definition of the flags.
		601	*/
522	__u32 flags;	602	__u32 flags;
		603	/**
		604	* @name: Symbolic property name. User-space should use this field to
		605	* recognize properties.
		606	*/
523	char name[DRM_PROP_NAME_LEN];	607	char name[DRM_PROP_NAME_LEN];
524		608
		609	/** @count_values: Number of elements in @values_ptr. */
525	__u32 count_values;	610	__u32 count_values;
526	/* This is only used to count enum values, not blobs. The _blobs is	611	/** @count_enum_blobs: Number of elements in @enum_blob_ptr. */
527	* simply because of a historical reason, i.e. backwards compat. */
528	__u32 count_enum_blobs;	612	__u32 count_enum_blobs;
529	};	613	};
530		614

include/uapi/drm/i915_drm.h+417−81

@@ -572,6 +572,15 @@ typedef struct drm_i915_irq_wait { · 571 unmodified lines
572	#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)	572	#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
573	#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)	573	#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
574	#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)	574	#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
		575	/*
		576	* Indicates the 2k user priority levels are statically mapped into 3 buckets as
		577	* follows:
		578	*
		579	* -1k to -1 Low priority
		580	* 0 Normal priority
		581	* 1 to 1k Highest priority
		582	*/
		583	#define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5)
575		584
576	#define I915_PARAM_HUC_STATUS 42	585	#define I915_PARAM_HUC_STATUS 42
577		586
@@ -674,6 +683,9 @@ typedef struct drm_i915_irq_wait { · 96 unmodified lines
674	*/	683	*/
675	#define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55	684	#define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55
676		685
		686	/* Query if the kernel supports the I915_USERPTR_PROBE flag. */
		687	#define I915_PARAM_HAS_USERPTR_PROBE 56
		688
677	/* Must be kept compact -- no holes and well documented */	689	/* Must be kept compact -- no holes and well documented */
678		690
679	typedef struct drm_i915_getparam {	691	typedef struct drm_i915_getparam {
@@ -849,45 +861,113 @@ struct drm_i915_gem_mmap_gtt { · 169 unmodified lines
849	__u64 offset;	861	__u64 offset;
850	};	862	};
851		863
		864	/**
		865	* struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object.
		866	*
		867	* This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl,
		868	* and is used to retrieve the fake offset to mmap an object specified by &handle.
		869	*
		870	* The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+.
		871	* `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave
		872	* as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`.
		873	*/
852	struct drm_i915_gem_mmap_offset {	874	struct drm_i915_gem_mmap_offset {
853	/** Handle for the object being mapped. */	875	/** @handle: Handle for the object being mapped. */
854	__u32 handle;	876	__u32 handle;
		877	/** @pad: Must be zero */
855	__u32 pad;	878	__u32 pad;
856	/**	879	/**
857	* Fake offset to use for subsequent mmap call	880	* @offset: The fake offset to use for subsequent mmap call
858	*	881	*
859	* This is a fixed-size type for 32/64 compatibility.	882	* This is a fixed-size type for 32/64 compatibility.
860	*/	883	*/
861	__u64 offset;	884	__u64 offset;
862		885
863	/**	886	/**
864	* Flags for extended behaviour.	887	* @flags: Flags for extended behaviour.
		888	*
		889	* It is mandatory that one of the `MMAP_OFFSET` types
		890	* should be included:
865	*	891	*
866	* It is mandatory that one of the MMAP_OFFSET types	892	* - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT. (Write-Combined)
867	* (GTT, WC, WB, UC, etc) should be included.	893	* - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching.
		894	* - `I915_MMAP_OFFSET_WB`: Use Write-Back caching.
		895	* - `I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching.
		896	*
		897	* On devices with local memory `I915_MMAP_OFFSET_FIXED` is the only valid
		898	* type. On devices without local memory, this caching mode is invalid.
		899	*
		900	* As caching mode when specifying `I915_MMAP_OFFSET_FIXED`, WC or WB will
		901	* be used, depending on the object placement on creation. WB will be used
		902	* when the object can only exist in system memory, WC otherwise.
868	*/	903	*/
869	__u64 flags;	904	__u64 flags;
870	#define I915_MMAP_OFFSET_GTT 0
871	#define I915_MMAP_OFFSET_WC 1
872	#define I915_MMAP_OFFSET_WB 2
873	#define I915_MMAP_OFFSET_UC 3
874		905
875	/*	906	#define I915_MMAP_OFFSET_GTT 0
876	* Zero-terminated chain of extensions.	907	#define I915_MMAP_OFFSET_WC 1
		908	#define I915_MMAP_OFFSET_WB 2
		909	#define I915_MMAP_OFFSET_UC 3
		910	#define I915_MMAP_OFFSET_FIXED 4
		911
		912	/**
		913	* @extensions: Zero-terminated chain of extensions.
877	*	914	*
878	* No current extensions defined; mbz.	915	* No current extensions defined; mbz.
879	*/	916	*/
880	__u64 extensions;	917	__u64 extensions;
881	};	918	};
882		919
		920	/**
		921	* struct drm_i915_gem_set_domain - Adjust the objects write or read domain, in
		922	* preparation for accessing the pages via some CPU domain.
		923	*
		924	* Specifying a new write or read domain will flush the object out of the
		925	* previous domain(if required), before then updating the objects domain
		926	* tracking with the new domain.
		927	*
		928	* Note this might involve waiting for the object first if it is still active on
		929	* the GPU.
		930	*
		931	* Supported values for @read_domains and @write_domain:
		932	*
		933	* - I915_GEM_DOMAIN_WC: Uncached write-combined domain
		934	* - I915_GEM_DOMAIN_CPU: CPU cache domain
		935	* - I915_GEM_DOMAIN_GTT: Mappable aperture domain
		936	*
		937	* All other domains are rejected.
		938	*
		939	* Note that for discrete, starting from DG1, this is no longer supported, and
		940	* is instead rejected. On such platforms the CPU domain is effectively static,
		941	* where we also only support a single &drm_i915_gem_mmap_offset cache mode,
		942	* which can't be set explicitly and instead depends on the object placements,
		943	* as per the below.
		944	*
		945	* Implicit caching rules, starting from DG1:
		946	*
		947	* - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions)
		948	* contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and
		949	* mapped as write-combined only.
		950	*
		951	* - Everything else is always allocated and mapped as write-back, with the
		952	* guarantee that everything is also coherent with the GPU.
		953	*
		954	* Note that this is likely to change in the future again, where we might need
		955	* more flexibility on future devices, so making this all explicit as part of a
		956	* new &drm_i915_gem_create_ext extension is probable.
		957	*/
883	struct drm_i915_gem_set_domain {	958	struct drm_i915_gem_set_domain {
884	/** Handle for the object */	959	/** @handle: Handle for the object. */
885	__u32 handle;	960	__u32 handle;
886		961
887	/** New read domains */	962	/** @read_domains: New read domains. */
888	__u32 read_domains;	963	__u32 read_domains;
889		964
890	/** New write domain */	965	/**
		966	* @write_domain: New write domain.
		967	*
		968	* Note that having something in the write domain implies it's in the
		969	* read domain, and only that read domain.
		970	*/
891	__u32 write_domain;	971	__u32 write_domain;
892	};	972	};
893		973
@@ -1348,12 +1428,11 @@ struct drm_i915_gem_busy { · 454 unmodified lines
1348	* reading from the object simultaneously.	1428	* reading from the object simultaneously.
1349	*	1429	*
1350	* The value of each engine class is the same as specified in the	1430	* The value of each engine class is the same as specified in the
1351	* I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.	1431	* I915_CONTEXT_PARAM_ENGINES context parameter and via perf, i.e.
1352	* I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.	1432	* I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
1353	* reported as active itself. Some hardware may have parallel	1433	* Some hardware may have parallel execution engines, e.g. multiple
1354	* execution engines, e.g. multiple media engines, which are	1434	* media engines, which are mapped to the same class identifier and so
1355	* mapped to the same class identifier and so are not separately	1435	* are not separately reported for busyness.
1356	* reported for busyness.
1357	*	1436	*
1358	* Caveat emptor:	1437	* Caveat emptor:
1359	* Only the boolean result of this query is reliable; that is whether	1438	* Only the boolean result of this query is reliable; that is whether
@@ -1364,43 +1443,79 @@ struct drm_i915_gem_busy { · 4 unmodified lines
1364	};	1443	};
1365		1444
1366	/**	1445	/**
1367	* I915_CACHING_NONE	1446	* struct drm_i915_gem_caching - Set or get the caching for given object
1368	*	1447	* handle.
1369	* GPU access is not coherent with cpu caches. Default for machines without an	1448	*
1370	* LLC.	1449	* Allow userspace to control the GTT caching bits for a given object when the
1371	*/	1450	* object is later mapped through the ppGTT(or GGTT on older platforms lacking
1372	#define I915_CACHING_NONE 0	1451	* ppGTT support, or if the object is used for scanout). Note that this might
1373	/**	1452	* require unbinding the object from the GTT first, if its current caching value
1374	* I915_CACHING_CACHED	1453	* doesn't match.
1375	*	1454	*
1376	* GPU access is coherent with cpu caches and furthermore the data is cached in	1455	* Note that this all changes on discrete platforms, starting from DG1, the
1377	* last-level caches shared between cpu cores and the gpu GT. Default on	1456	* set/get caching is no longer supported, and is now rejected. Instead the CPU
1378	* machines with HAS_LLC.	1457	* caching attributes(WB vs WC) will become an immutable creation time property
		1458	* for the object, along with the GTT caching level. For now we don't expose any
		1459	* new uAPI for this, instead on DG1 this is all implicit, although this largely
		1460	* shouldn't matter since DG1 is coherent by default(without any way of
		1461	* controlling it).
		1462	*
		1463	* Implicit caching rules, starting from DG1:
		1464	*
		1465	* - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions)
		1466	* contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and
		1467	* mapped as write-combined only.
		1468	*
		1469	* - Everything else is always allocated and mapped as write-back, with the
		1470	* guarantee that everything is also coherent with the GPU.
		1471	*
		1472	* Note that this is likely to change in the future again, where we might need
		1473	* more flexibility on future devices, so making this all explicit as part of a
		1474	* new &drm_i915_gem_create_ext extension is probable.
		1475	*
		1476	* Side note: Part of the reason for this is that changing the at-allocation-time CPU
		1477	* caching attributes for the pages might be required(and is expensive) if we
		1478	* need to then CPU map the pages later with different caching attributes. This
		1479	* inconsistent caching behaviour, while supported on x86, is not universally
		1480	* supported on other architectures. So for simplicity we opt for setting
		1481	* everything at creation time, whilst also making it immutable, on discrete
		1482	* platforms.
1379	*/	1483	*/
1380	#define I915_CACHING_CACHED 1
1381	/**
1382	* I915_CACHING_DISPLAY
1383	*
1384	* Special GPU caching mode which is coherent with the scanout engines.
1385	* Transparently falls back to I915_CACHING_NONE on platforms where no special
1386	* cache mode (like write-through or gfdt flushing) is available. The kernel
1387	* automatically sets this mode when using a buffer as a scanout target.
1388	* Userspace can manually set this mode to avoid a costly stall and clflush in
1389	* the hotpath of drawing the first frame.
1390	*/
1391	#define I915_CACHING_DISPLAY 2
1392
1393	struct drm_i915_gem_caching {	1484	struct drm_i915_gem_caching {
1394	/**	1485	/**
1395	* Handle of the buffer to set/get the caching level of. */	1486	* @handle: Handle of the buffer to set/get the caching level.
		1487	*/
1396	__u32 handle;	1488	__u32 handle;
1397		1489
1398	/**	1490	/**
1399	* Cacheing level to apply or return value	1491	* @caching: The GTT caching level to apply or possible return value.
		1492	*
		1493	* The supported @caching values:
1400	*	1494	*
1401	* bits0-15 are for generic caching control (i.e. the above defined	1495	* I915_CACHING_NONE:
1402	* values). bits16-31 are reserved for platform-specific variations	1496	*
1403	* (e.g. l3$ caching on gen7). */	1497	* GPU access is not coherent with CPU caches. Default for machines
		1498	* without an LLC. This means manual flushing might be needed, if we
		1499	* want GPU access to be coherent.
		1500	*
		1501	* I915_CACHING_CACHED:
		1502	*
		1503	* GPU access is coherent with CPU caches and furthermore the data is
		1504	* cached in last-level caches shared between CPU cores and the GPU GT.
		1505	*
		1506	* I915_CACHING_DISPLAY:
		1507	*
		1508	* Special GPU caching mode which is coherent with the scanout engines.
		1509	* Transparently falls back to I915_CACHING_NONE on platforms where no
		1510	* special cache mode (like write-through or gfdt flushing) is
		1511	* available. The kernel automatically sets this mode when using a
		1512	* buffer as a scanout target. Userspace can manually set this mode to
		1513	* avoid a costly stall and clflush in the hotpath of drawing the first
		1514	* frame.
		1515	*/
		1516	#define I915_CACHING_NONE 0
		1517	#define I915_CACHING_CACHED 1
		1518	#define I915_CACHING_DISPLAY 2
1404	__u32 caching;	1519	__u32 caching;
1405	};	1520	};
1406		1521
@@ -1639,6 +1754,10 @@ struct drm_i915_gem_context_param { · 232 unmodified lines
1639	__u32 size;	1754	__u32 size;
1640	__u64 param;	1755	__u64 param;
1641	#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1	1756	#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
		1757	/* I915_CONTEXT_PARAM_NO_ZEROMAP has been removed. On the off chance
		1758	* someone somewhere has attempted to use it, never re-use this context
		1759	* param number.
		1760	*/
1642	#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2	1761	#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
1643	#define I915_CONTEXT_PARAM_GTT_SIZE 0x3	1762	#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
1644	#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4	1763	#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
@@ -1723,24 +1842,8 @@ struct drm_i915_gem_context_param { · 78 unmodified lines
1723	*/	1842	*/
1724	#define I915_CONTEXT_PARAM_PERSISTENCE 0xb	1843	#define I915_CONTEXT_PARAM_PERSISTENCE 0xb
1725		1844
1726	/*	1845	/* This API has been removed. On the off chance someone somewhere has
1727	* I915_CONTEXT_PARAM_RINGSIZE:	1846	* attempted to use it, never re-use this context param number.
1728	*
1729	* Sets the size of the CS ringbuffer to use for logical ring contexts. This
1730	* applies a limit of how many batches can be queued to HW before the caller
1731	* is blocked due to lack of space for more commands.
1732	*
1733	* Only reliably possible to be set prior to first use, i.e. during
1734	* construction. At any later point, the current execution must be flushed as
1735	* the ring can only be changed while the context is idle. Note, the ringsize
1736	* can be specified as a constructor property, see
1737	* I915_CONTEXT_CREATE_EXT_SETPARAM, but can also be set later if required.
1738	*
1739	* Only applies to the current set of engine and lost when those engines
1740	* are replaced by a new mapping (see I915_CONTEXT_PARAM_ENGINES).
1741	*
1742	* Must be between 4 - 512 KiB, in intervals of page size [4 KiB].
1743	* Default is 16 KiB.
1744	*/	1847	*/
1745	#define I915_CONTEXT_PARAM_RINGSIZE 0xc	1848	#define I915_CONTEXT_PARAM_RINGSIZE 0xc
1746	/* Must be kept compact -- no holes and well documented */	1849	/* Must be kept compact -- no holes and well documented */
@@ -1807,6 +1910,69 @@ struct drm_i915_gem_context_param_sseu { · 60 unmodified lines
1807	__u32 rsvd;	1910	__u32 rsvd;
1808	};	1911	};
1809		1912
		1913	/**
		1914	* DOC: Virtual Engine uAPI
		1915	*
		1916	* Virtual engine is a concept where userspace is able to configure a set of
		1917	* physical engines, submit a batch buffer, and let the driver execute it on any
		1918	* engine from the set as it sees fit.
		1919	*
		1920	* This is primarily useful on parts which have multiple instances of a same
		1921	* class engine, like for example GT3+ Skylake parts with their two VCS engines.
		1922	*
		1923	* For instance userspace can enumerate all engines of a certain class using the
		1924	* previously described `Engine Discovery uAPI`_. After that userspace can
		1925	* create a GEM context with a placeholder slot for the virtual engine (using
		1926	* `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class
		1927	* and instance respectively) and finally using the
		1928	* `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in
		1929	* the same reserved slot.
		1930	*
		1931	* Example of creating a virtual engine and submitting a batch buffer to it:
		1932	*
		1933	* .. code-block:: C
		1934	*
		1935	* I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = {
		1936	* .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE,
		1937	* .engine_index = 0, // Place this virtual engine into engine map slot 0
		1938	* .num_siblings = 2,
		1939	* .engines = { { I915_ENGINE_CLASS_VIDEO, 0 },
		1940	* { I915_ENGINE_CLASS_VIDEO, 1 }, },
		1941	* };
		1942	* I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
		1943	* .engines = { { I915_ENGINE_CLASS_INVALID,
		1944	* I915_ENGINE_CLASS_INVALID_NONE } },
		1945	* .extensions = to_user_pointer(&virtual), // Chains after load_balance extension
		1946	* };
		1947	* struct drm_i915_gem_context_create_ext_setparam p_engines = {
		1948	* .base = {
		1949	* .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
		1950	* },
		1951	* .param = {
		1952	* .param = I915_CONTEXT_PARAM_ENGINES,
		1953	* .value = to_user_pointer(&engines),
		1954	* .size = sizeof(engines),
		1955	* },
		1956	* };
		1957	* struct drm_i915_gem_context_create_ext create = {
		1958	* .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
		1959	* .extensions = to_user_pointer(&p_engines);
		1960	* };
		1961	*
		1962	* ctx_id = gem_context_create_ext(drm_fd, &create);
		1963	*
		1964	* // Now we have created a GEM context with its engine map containing a
		1965	* // single virtual engine. Submissions to this slot can go either to
		1966	* // vcs0 or vcs1, depending on the load balancing algorithm used inside
		1967	* // the driver. The load balancing is dynamic from one batch buffer to
		1968	* // another and transparent to userspace.
		1969	*
		1970	* ...
		1971	* execbuf.rsvd1 = ctx_id;
		1972	* execbuf.flags = 0; // Submits to index 0 which is the virtual engine
		1973	* gem_execbuf(drm_fd, &execbuf);
		1974	*/
		1975
1810	/*	1976	/*
1811	* i915_context_engines_load_balance:	1977	* i915_context_engines_load_balance:
1812	*	1978	*
@@ -1883,6 +2049,61 @@ struct i915_context_engines_bond { · 70 unmodified lines
1883	struct i915_engine_class_instance engines[N__]; \	2049	struct i915_engine_class_instance engines[N__]; \
1884	} __attribute__((packed)) name__	2050	} __attribute__((packed)) name__
1885		2051
		2052	/**
		2053	* DOC: Context Engine Map uAPI
		2054	*
		2055	* Context engine map is a new way of addressing engines when submitting batch-
		2056	* buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT`
		2057	* inside the flags field of `struct drm_i915_gem_execbuffer2`.
		2058	*
		2059	* To use it created GEM contexts need to be configured with a list of engines
		2060	* the user is intending to submit to. This is accomplished using the
		2061	* `I915_CONTEXT_PARAM_ENGINES` parameter and `struct
		2062	* i915_context_param_engines`.
		2063	*
		2064	* For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the
		2065	* configured map.
		2066	*
		2067	* Example of creating such context and submitting against it:
		2068	*
		2069	* .. code-block:: C
		2070	*
		2071	* I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = {
		2072	* .engines = { { I915_ENGINE_CLASS_RENDER, 0 },
		2073	* { I915_ENGINE_CLASS_COPY, 0 } }
		2074	* };
		2075	* struct drm_i915_gem_context_create_ext_setparam p_engines = {
		2076	* .base = {
		2077	* .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
		2078	* },
		2079	* .param = {
		2080	* .param = I915_CONTEXT_PARAM_ENGINES,
		2081	* .value = to_user_pointer(&engines),
		2082	* .size = sizeof(engines),
		2083	* },
		2084	* };
		2085	* struct drm_i915_gem_context_create_ext create = {
		2086	* .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
		2087	* .extensions = to_user_pointer(&p_engines);
		2088	* };
		2089	*
		2090	* ctx_id = gem_context_create_ext(drm_fd, &create);
		2091	*
		2092	* // We have now created a GEM context with two engines in the map:
		2093	* // Index 0 points to rcs0 while index 1 points to bcs0. Other engines
		2094	* // will not be accessible from this context.
		2095	*
		2096	* ...
		2097	* execbuf.rsvd1 = ctx_id;
		2098	* execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context
		2099	* gem_execbuf(drm_fd, &execbuf);
		2100	*
		2101	* ...
		2102	* execbuf.rsvd1 = ctx_id;
		2103	* execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context
		2104	* gem_execbuf(drm_fd, &execbuf);
		2105	*/
		2106
1886	struct i915_context_param_engines {	2107	struct i915_context_param_engines {
1887	__u64 extensions; /* linked chain of extension blocks, 0 terminates */	2108	__u64 extensions; /* linked chain of extension blocks, 0 terminates */
1888	#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */	2109	#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
@@ -1901,20 +2122,10 @@ struct drm_i915_gem_context_create_ext_setparam { · 12 unmodified lines
1901	struct drm_i915_gem_context_param param;	2122	struct drm_i915_gem_context_param param;
1902	};	2123	};
1903		2124
1904	struct drm_i915_gem_context_create_ext_clone {	2125	/* This API has been removed. On the off chance someone somewhere has
		2126	* attempted to use it, never re-use this extension number.
		2127	*/
1905	#define I915_CONTEXT_CREATE_EXT_CLONE 1	2128	#define I915_CONTEXT_CREATE_EXT_CLONE 1
1906	struct i915_user_extension base;
1907	__u32 clone_id;
1908	__u32 flags;
1909	#define I915_CONTEXT_CLONE_ENGINES (1u << 0)
1910	#define I915_CONTEXT_CLONE_FLAGS (1u << 1)
1911	#define I915_CONTEXT_CLONE_SCHEDATTR (1u << 2)
1912	#define I915_CONTEXT_CLONE_SSEU (1u << 3)
1913	#define I915_CONTEXT_CLONE_TIMELINE (1u << 4)
1914	#define I915_CONTEXT_CLONE_VM (1u << 5)
1915	#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_VM << 1)
1916	__u64 rsvd;
1917	};
1918		2129
1919	struct drm_i915_gem_context_destroy {	2130	struct drm_i915_gem_context_destroy {
1920	__u32 ctx_id;	2131	__u32 ctx_id;
@@ -1986,14 +2197,69 @@ struct drm_i915_reset_stats { · 65 unmodified lines
1986	__u32 pad;	2197	__u32 pad;
1987	};	2198	};
1988		2199
		2200	/**
		2201	* struct drm_i915_gem_userptr - Create GEM object from user allocated memory.
		2202	*
		2203	* Userptr objects have several restrictions on what ioctls can be used with the
		2204	* object handle.
		2205	*/
1989	struct drm_i915_gem_userptr {	2206	struct drm_i915_gem_userptr {
		2207	/**
		2208	* @user_ptr: The pointer to the allocated memory.
		2209	*
		2210	* Needs to be aligned to PAGE_SIZE.
		2211	*/
1990	__u64 user_ptr;	2212	__u64 user_ptr;
		2213
		2214	/**
		2215	* @user_size:
		2216	*
		2217	* The size in bytes for the allocated memory. This will also become the
		2218	* object size.
		2219	*
		2220	* Needs to be aligned to PAGE_SIZE, and should be at least PAGE_SIZE,
		2221	* or larger.
		2222	*/
1991	__u64 user_size;	2223	__u64 user_size;
		2224
		2225	/**
		2226	* @flags:
		2227	*
		2228	* Supported flags:
		2229	*
		2230	* I915_USERPTR_READ_ONLY:
		2231	*
		2232	* Mark the object as readonly, this also means GPU access can only be
		2233	* readonly. This is only supported on HW which supports readonly access
		2234	* through the GTT. If the HW can't support readonly access, an error is
		2235	* returned.
		2236	*
		2237	* I915_USERPTR_PROBE:
		2238	*
		2239	* Probe the provided @user_ptr range and validate that the @user_ptr is
		2240	* indeed pointing to normal memory and that the range is also valid.
		2241	* For example if some garbage address is given to the kernel, then this
		2242	* should complain.
		2243	*
		2244	* Returns -EFAULT if the probe failed.
		2245	*
		2246	* Note that this doesn't populate the backing pages, and also doesn't
		2247	* guarantee that the object will remain valid when the object is
		2248	* eventually used.
		2249	*
		2250	* The kernel supports this feature if I915_PARAM_HAS_USERPTR_PROBE
		2251	* returns a non-zero value.
		2252	*
		2253	* I915_USERPTR_UNSYNCHRONIZED:
		2254	*
		2255	* NOT USED. Setting this flag will result in an error.
		2256	*/
1992	__u32 flags;	2257	__u32 flags;
1993	#define I915_USERPTR_READ_ONLY 0x1	2258	#define I915_USERPTR_READ_ONLY 0x1
		2259	#define I915_USERPTR_PROBE 0x2
1994	#define I915_USERPTR_UNSYNCHRONIZED 0x80000000	2260	#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
1995	/**	2261	/**
1996	* Returned handle for the object.	2262	* @handle: Returned handle for the object.
1997	*	2263	*
1998	* Object handles are nonzero.	2264	* Object handles are nonzero.
1999	*/	2265	*/
@@ -2376,6 +2642,76 @@ struct drm_i915_query_topology_info { · 376 unmodified lines
2376	__u8 data[];	2642	__u8 data[];
2377	};	2643	};
2378		2644
		2645	/**
		2646	* DOC: Engine Discovery uAPI
		2647	*
		2648	* Engine discovery uAPI is a way of enumerating physical engines present in a
		2649	* GPU associated with an open i915 DRM file descriptor. This supersedes the old
		2650	* way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like
		2651	* `I915_PARAM_HAS_BLT`.
		2652	*
		2653	* The need for this interface came starting with Icelake and newer GPUs, which
		2654	* started to establish a pattern of having multiple engines of a same class,
		2655	* where not all instances were always completely functionally equivalent.
		2656	*
		2657	* Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the
		2658	* `DRM_I915_QUERY_ENGINE_INFO` as the queried item id.
		2659	*
		2660	* Example for getting the list of engines:
		2661	*
		2662	* .. code-block:: C
		2663	*
		2664	* struct drm_i915_query_engine_info *info;
		2665	* struct drm_i915_query_item item = {
		2666	* .query_id = DRM_I915_QUERY_ENGINE_INFO;
		2667	* };
		2668	* struct drm_i915_query query = {
		2669	* .num_items = 1,
		2670	* .items_ptr = (uintptr_t)&item,
		2671	* };
		2672	* int err, i;
		2673	*
		2674	* // First query the size of the blob we need, this needs to be large
		2675	* // enough to hold our array of engines. The kernel will fill out the
		2676	* // item.length for us, which is the number of bytes we need.
		2677	* //
		2678	* // Alternatively a large buffer can be allocated straight away enabling
		2679	* // querying in one pass, in which case item.length should contain the
		2680	* // length of the provided buffer.
		2681	* err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
		2682	* if (err) ...
		2683	*
		2684	* info = calloc(1, item.length);
		2685	* // Now that we allocated the required number of bytes, we call the ioctl
		2686	* // again, this time with the data_ptr pointing to our newly allocated
		2687	* // blob, which the kernel can then populate with info on all engines.
		2688	* item.data_ptr = (uintptr_t)&info,
		2689	*
		2690	* err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
		2691	* if (err) ...
		2692	*
		2693	* // We can now access each engine in the array
		2694	* for (i = 0; i < info->num_engines; i++) {
		2695	* struct drm_i915_engine_info einfo = info->engines[i];
		2696	* u16 class = einfo.engine.class;
		2697	* u16 instance = einfo.engine.instance;
		2698	* ....
		2699	* }
		2700	*
		2701	* free(info);
		2702	*
		2703	* Each of the enumerated engines, apart from being defined by its class and
		2704	* instance (see `struct i915_engine_class_instance`), also can have flags and
		2705	* capabilities defined as documented in i915_drm.h.
		2706	*
		2707	* For instance video engines which support HEVC encoding will have the
		2708	* `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set.
		2709	*
		2710	* Engine discovery only fully comes to its own when combined with the new way
		2711	* of addressing engines when submitting batch buffers using contexts with
		2712	* engine maps configured.
		2713	*/
		2714
2379	/**	2715	/**
2380	* struct drm_i915_engine_info	2716	* struct drm_i915_engine_info
2381	*	2717	*

include/uapi/drm/msm_drm.h+13−1

 #define MSM_PARAM_MAX_FREQ   0x04
 #define MSM_PARAM_TIMESTAMP  0x05
 #define MSM_PARAM_GMEM_BASE  0x06
-#define MSM_PARAM_NR_RINGS   0x07
+#define MSM_PARAM_PRIORITIES 0x07  /* The # of priority levels */
 #define MSM_PARAM_PP_PGTABLE 0x08  /* => 1 for per-process pagetables, else 0 */
 #define MSM_PARAM_FAULTS     0x09
 #define MSM_PARAM_SUSPENDS   0x0a
+/* For backwards compat.  The original support for preemption was based on
+ * a single ring per priority level so # of priority levels equals the #
+ * of rings.  With drm/scheduler providing additional levels of priority,
+ * the number of priorities is greater than the # of rings.  The param is
+ * renamed to better reflect this.
+ */
+#define MSM_PARAM_NR_RINGS   MSM_PARAM_PRIORITIES
 struct drm_msm_param {
 	__u32 pipe;           /* in, MSM_PIPE_x */
 	__u32 param;          /* in, MSM_PARAM_x */
 #define MSM_SUBMITQUEUE_FLAGS (0)
+/*
+ * The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1,
+ * a lower numeric value is higher priority.
+ */
 struct drm_msm_submitqueue {
 	__u32 flags;   /* in, MSM_SUBMITQUEUE_x */
 	__u32 prio;    /* in, Priority level */

include/uapi/drm/tegra_drm.h+402−23

@@ -1,24 +1,5 @@
1	/*	1	/* SPDX-License-Identifier: MIT */
2	* Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.	2	/* Copyright (c) 2012-2020 NVIDIA Corporation */
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice shall be included in
12	* all copies or substantial portions of the Software.
13	*
14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20	* OTHER DEALINGS IN THE SOFTWARE.
21	*/
22		3
23	#ifndef _UAPI_TEGRA_DRM_H_	4	#ifndef _UAPI_TEGRA_DRM_H_
24	#define _UAPI_TEGRA_DRM_H_	5	#define _UAPI_TEGRA_DRM_H_
@@ -29,6 +10,8 @@ · 4 unmodified lines
29	extern "C" {	10	extern "C" {
30	#endif	11	#endif
31		12
		13	/* Tegra DRM legacy UAPI. Only enabled with STAGING */
		14
32	#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)	15	#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)
33	#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)	16	#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
34		17
@@ -649,8 +632,8 @@ struct drm_tegra_gem_get_flags { · 614 unmodified lines
649	#define DRM_TEGRA_SYNCPT_READ 0x02	632	#define DRM_TEGRA_SYNCPT_READ 0x02
650	#define DRM_TEGRA_SYNCPT_INCR 0x03	633	#define DRM_TEGRA_SYNCPT_INCR 0x03
651	#define DRM_TEGRA_SYNCPT_WAIT 0x04	634	#define DRM_TEGRA_SYNCPT_WAIT 0x04
652	#define DRM_TEGRA_OPEN_CHANNEL 0x05	635	#define DRM_TEGRA_OPEN_CHANNEL 0x05
653	#define DRM_TEGRA_CLOSE_CHANNEL 0x06	636	#define DRM_TEGRA_CLOSE_CHANNEL 0x06
654	#define DRM_TEGRA_GET_SYNCPT 0x07	637	#define DRM_TEGRA_GET_SYNCPT 0x07
655	#define DRM_TEGRA_SUBMIT 0x08	638	#define DRM_TEGRA_SUBMIT 0x08
656	#define DRM_TEGRA_GET_SYNCPT_BASE 0x09	639	#define DRM_TEGRA_GET_SYNCPT_BASE 0x09
@@ -674,6 +657,402 @@ struct drm_tegra_gem_get_flags { · 17 unmodified lines
674	#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)	657	#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
675	#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)	658	#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
676		659
		660	/* New Tegra DRM UAPI */
		661
		662	/*
		663	* Reported by the driver in the `capabilities` field.
		664	*
		665	* DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT: If set, the engine is cache coherent
		666	* with regard to the system memory.
		667	*/
		668	#define DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT (1 << 0)
		669
		670	struct drm_tegra_channel_open {
		671	/**
		672	* @host1x_class: [in]
		673	*
		674	* Host1x class of the engine that will be programmed using this
		675	* channel.
		676	*/
		677	__u32 host1x_class;
		678
		679	/**
		680	* @flags: [in]
		681	*
		682	* Flags.
		683	*/
		684	__u32 flags;
		685
		686	/**
		687	* @context: [out]
		688	*
		689	* Opaque identifier corresponding to the opened channel.
		690	*/
		691	__u32 context;
		692
		693	/**
		694	* @version: [out]
		695	*
		696	* Version of the engine hardware. This can be used by userspace
		697	* to determine how the engine needs to be programmed.
		698	*/
		699	__u32 version;
		700
		701	/**
		702	* @capabilities: [out]
		703	*
		704	* Flags describing the hardware capabilities.
		705	*/
		706	__u32 capabilities;
		707	__u32 padding;
		708	};
		709
		710	struct drm_tegra_channel_close {
		711	/**
		712	* @context: [in]
		713	*
		714	* Identifier of the channel to close.
		715	*/
		716	__u32 context;
		717	__u32 padding;
		718	};
		719
		720	/*
		721	* Mapping flags that can be used to influence how the mapping is created.
		722	*
		723	* DRM_TEGRA_CHANNEL_MAP_READ: create mapping that allows HW read access
		724	* DRM_TEGRA_CHANNEL_MAP_WRITE: create mapping that allows HW write access
		725	*/
		726	#define DRM_TEGRA_CHANNEL_MAP_READ (1 << 0)
		727	#define DRM_TEGRA_CHANNEL_MAP_WRITE (1 << 1)
		728	#define DRM_TEGRA_CHANNEL_MAP_READ_WRITE (DRM_TEGRA_CHANNEL_MAP_READ \| \
		729	DRM_TEGRA_CHANNEL_MAP_WRITE)
		730
		731	struct drm_tegra_channel_map {
		732	/**
		733	* @context: [in]
		734	*
		735	* Identifier of the channel to which make memory available for.
		736	*/
		737	__u32 context;
		738
		739	/**
		740	* @handle: [in]
		741	*
		742	* GEM handle of the memory to map.
		743	*/
		744	__u32 handle;
		745
		746	/**
		747	* @flags: [in]
		748	*
		749	* Flags.
		750	*/
		751	__u32 flags;
		752
		753	/**
		754	* @mapping: [out]
		755	*
		756	* Identifier corresponding to the mapping, to be used for
		757	* relocations or unmapping later.
		758	*/
		759	__u32 mapping;
		760	};
		761
		762	struct drm_tegra_channel_unmap {
		763	/**
		764	* @context: [in]
		765	*
		766	* Channel identifier of the channel to unmap memory from.
		767	*/
		768	__u32 context;
		769
		770	/**
		771	* @mapping: [in]
		772	*
		773	* Mapping identifier of the memory mapping to unmap.
		774	*/
		775	__u32 mapping;
		776	};
		777
		778	/* Submission */
		779
		780	/**
		781	* Specify that bit 39 of the patched-in address should be set to switch
		782	* swizzling between Tegra and non-Tegra sector layout on systems that store
		783	* surfaces in system memory in non-Tegra sector layout.
		784	*/
		785	#define DRM_TEGRA_SUBMIT_RELOC_SECTOR_LAYOUT (1 << 0)
		786
		787	struct drm_tegra_submit_buf {
		788	/**
		789	* @mapping: [in]
		790	*
		791	* Identifier of the mapping to use in the submission.
		792	*/
		793	__u32 mapping;
		794
		795	/**
		796	* @flags: [in]
		797	*
		798	* Flags.
		799	*/
		800	__u32 flags;
		801
		802	/**
		803	* Information for relocation patching.
		804	*/
		805	struct {
		806	/**
		807	* @target_offset: [in]
		808	*
		809	* Offset from the start of the mapping of the data whose
		810	* address is to be patched into the gather.
		811	*/
		812	__u64 target_offset;
		813
		814	/**
		815	* @gather_offset_words: [in]
		816	*
		817	* Offset in words from the start of the gather data to
		818	* where the address should be patched into.
		819	*/
		820	__u32 gather_offset_words;
		821
		822	/**
		823	* @shift: [in]
		824	*
		825	* Number of bits the address should be shifted right before
		826	* patching in.
		827	*/
		828	__u32 shift;
		829	} reloc;
		830	};
		831
		832	/**
		833	* Execute `words` words of Host1x opcodes specified in the `gather_data_ptr`
		834	* buffer. Each GATHER_UPTR command uses successive words from the buffer.
		835	*/
		836	#define DRM_TEGRA_SUBMIT_CMD_GATHER_UPTR 0
		837	/**
		838	* Wait for a syncpoint to reach a value before continuing with further
		839	* commands.
		840	*/
		841	#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT 1
		842	/**
		843	* Wait for a syncpoint to reach a value before continuing with further
		844	* commands. The threshold is calculated relative to the start of the job.
		845	*/
		846	#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT_RELATIVE 2
		847
		848	struct drm_tegra_submit_cmd_gather_uptr {
		849	__u32 words;
		850	__u32 reserved[3];
		851	};
		852
		853	struct drm_tegra_submit_cmd_wait_syncpt {
		854	__u32 id;
		855	__u32 value;
		856	__u32 reserved[2];
		857	};
		858
		859	struct drm_tegra_submit_cmd {
		860	/**
		861	* @type: [in]
		862	*
		863	* Command type to execute. One of the DRM_TEGRA_SUBMIT_CMD*
		864	* defines.
		865	*/
		866	__u32 type;
		867
		868	/**
		869	* @flags: [in]
		870	*
		871	* Flags.
		872	*/
		873	__u32 flags;
		874
		875	union {
		876	struct drm_tegra_submit_cmd_gather_uptr gather_uptr;
		877	struct drm_tegra_submit_cmd_wait_syncpt wait_syncpt;
		878	__u32 reserved[4];
		879	};
		880	};
		881
		882	struct drm_tegra_submit_syncpt {
		883	/**
		884	* @id: [in]
		885	*
		886	* ID of the syncpoint that the job will increment.
		887	*/
		888	__u32 id;
		889
		890	/**
		891	* @flags: [in]
		892	*
		893	* Flags.
		894	*/
		895	__u32 flags;
		896
		897	/**
		898	* @increments: [in]
		899	*
		900	* Number of times the job will increment this syncpoint.
		901	*/
		902	__u32 increments;
		903
		904	/**
		905	* @value: [out]
		906	*
		907	* Value the syncpoint will have once the job has completed all
		908	* its specified syncpoint increments.
		909	*
		910	* Note that the kernel may increment the syncpoint before or after
		911	* the job. These increments are not reflected in this field.
		912	*
		913	* If the job hangs or times out, not all of the increments may
		914	* get executed.
		915	*/
		916	__u32 value;
		917	};
		918
		919	struct drm_tegra_channel_submit {
		920	/**
		921	* @context: [in]
		922	*
		923	* Identifier of the channel to submit this job to.
		924	*/
		925	__u32 context;
		926
		927	/**
		928	* @num_bufs: [in]
		929	*
		930	* Number of elements in the `bufs_ptr` array.
		931	*/
		932	__u32 num_bufs;
		933
		934	/**
		935	* @num_cmds: [in]
		936	*
		937	* Number of elements in the `cmds_ptr` array.
		938	*/
		939	__u32 num_cmds;
		940
		941	/**
		942	* @gather_data_words: [in]
		943	*
		944	* Number of 32-bit words in the `gather_data_ptr` array.
		945	*/
		946	__u32 gather_data_words;
		947
		948	/**
		949	* @bufs_ptr: [in]
		950	*
		951	* Pointer to an array of drm_tegra_submit_buf structures.
		952	*/
		953	__u64 bufs_ptr;
		954
		955	/**
		956	* @cmds_ptr: [in]
		957	*
		958	* Pointer to an array of drm_tegra_submit_cmd structures.
		959	*/
		960	__u64 cmds_ptr;
		961
		962	/**
		963	* @gather_data_ptr: [in]
		964	*
		965	* Pointer to an array of Host1x opcodes to be used by GATHER_UPTR
		966	* commands.
		967	*/
		968	__u64 gather_data_ptr;
		969
		970	/**
		971	* @syncobj_in: [in]
		972	*
		973	* Handle for DRM syncobj that will be waited before submission.
		974	* Ignored if zero.
		975	*/
		976	__u32 syncobj_in;
		977
		978	/**
		979	* @syncobj_out: [in]
		980	*
		981	* Handle for DRM syncobj that will have its fence replaced with
		982	* the job's completion fence. Ignored if zero.
		983	*/
		984	__u32 syncobj_out;
		985
		986	/**
		987	* @syncpt_incr: [in,out]
		988	*
		989	* Information about the syncpoint the job will increment.
		990	*/
		991	struct drm_tegra_submit_syncpt syncpt;
		992	};
		993
		994	struct drm_tegra_syncpoint_allocate {
		995	/**
		996	* @id: [out]
		997	*
		998	* ID of allocated syncpoint.
		999	*/
		1000	__u32 id;
		1001	__u32 padding;
		1002	};
		1003
		1004	struct drm_tegra_syncpoint_free {
		1005	/**
		1006	* @id: [in]
		1007	*
		1008	* ID of syncpoint to free.
		1009	*/
		1010	__u32 id;
		1011	__u32 padding;
		1012	};
		1013
		1014	struct drm_tegra_syncpoint_wait {
		1015	/**
		1016	* @timeout: [in]
		1017	*
		1018	* Absolute timestamp at which the wait will time out.
		1019	*/
		1020	__s64 timeout_ns;
		1021
		1022	/**
		1023	* @id: [in]
		1024	*
		1025	* ID of syncpoint to wait on.
		1026	*/
		1027	__u32 id;
		1028
		1029	/**
		1030	* @threshold: [in]
		1031	*
		1032	* Threshold to wait for.
		1033	*/
		1034	__u32 threshold;
		1035
		1036	/**
		1037	* @value: [out]
		1038	*
		1039	* Value of the syncpoint upon wait completion.
		1040	*/
		1041	__u32 value;
		1042
		1043	__u32 padding;
		1044	};
		1045
		1046	#define DRM_IOCTL_TEGRA_CHANNEL_OPEN DRM_IOWR(DRM_COMMAND_BASE + 0x10, struct drm_tegra_channel_open)
		1047	#define DRM_IOCTL_TEGRA_CHANNEL_CLOSE DRM_IOWR(DRM_COMMAND_BASE + 0x11, struct drm_tegra_channel_close)
		1048	#define DRM_IOCTL_TEGRA_CHANNEL_MAP DRM_IOWR(DRM_COMMAND_BASE + 0x12, struct drm_tegra_channel_map)
		1049	#define DRM_IOCTL_TEGRA_CHANNEL_UNMAP DRM_IOWR(DRM_COMMAND_BASE + 0x13, struct drm_tegra_channel_unmap)
		1050	#define DRM_IOCTL_TEGRA_CHANNEL_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + 0x14, struct drm_tegra_channel_submit)
		1051
		1052	#define DRM_IOCTL_TEGRA_SYNCPOINT_ALLOCATE DRM_IOWR(DRM_COMMAND_BASE + 0x20, struct drm_tegra_syncpoint_allocate)
		1053	#define DRM_IOCTL_TEGRA_SYNCPOINT_FREE DRM_IOWR(DRM_COMMAND_BASE + 0x21, struct drm_tegra_syncpoint_free)
		1054	#define DRM_IOCTL_TEGRA_SYNCPOINT_WAIT DRM_IOWR(DRM_COMMAND_BASE + 0x22, struct drm_tegra_syncpoint_wait)
		1055
677	#if defined(__cplusplus)	1056	#if defined(__cplusplus)
678	}	1057	}
679	#endif	1058	#endif

include/uapi/drm/v3d_drm.h+136−0

@@ -38,6 +38,9 @@ extern "C" { · 37 unmodified lines
38	#define DRM_V3D_GET_BO_OFFSET 0x05	38	#define DRM_V3D_GET_BO_OFFSET 0x05
39	#define DRM_V3D_SUBMIT_TFU 0x06	39	#define DRM_V3D_SUBMIT_TFU 0x06
40	#define DRM_V3D_SUBMIT_CSD 0x07	40	#define DRM_V3D_SUBMIT_CSD 0x07
		41	#define DRM_V3D_PERFMON_CREATE 0x08
		42	#define DRM_V3D_PERFMON_DESTROY 0x09
		43	#define DRM_V3D_PERFMON_GET_VALUES 0x0a
41		44
42	#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)	45	#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
43	#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)	46	#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
@@ -47,6 +50,12 @@ extern "C" { · 3 unmodified lines
47	#define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)	50	#define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
48	#define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)	51	#define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
49	#define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)	52	#define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)
		53	#define DRM_IOCTL_V3D_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_CREATE, \
		54	struct drm_v3d_perfmon_create)
		55	#define DRM_IOCTL_V3D_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_DESTROY, \
		56	struct drm_v3d_perfmon_destroy)
		57	#define DRM_IOCTL_V3D_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_VALUES, \
		58	struct drm_v3d_perfmon_get_values)
50		59
51	#define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01	60	#define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01
52		61
@@ -127,6 +136,11 @@ struct drm_v3d_submit_cl { · 74 unmodified lines
127	__u32 bo_handle_count;	136	__u32 bo_handle_count;
128		137
129	__u32 flags;	138	__u32 flags;
		139
		140	/* ID of the perfmon to attach to this job. 0 means no perfmon. */
		141	__u32 perfmon_id;
		142
		143	__u32 pad;
130	};	144	};
131		145
132	/**	146	/**
@@ -195,6 +209,7 @@ enum drm_v3d_param { · 62 unmodified lines
195	DRM_V3D_PARAM_SUPPORTS_TFU,	209	DRM_V3D_PARAM_SUPPORTS_TFU,
196	DRM_V3D_PARAM_SUPPORTS_CSD,	210	DRM_V3D_PARAM_SUPPORTS_CSD,
197	DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,	211	DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,
		212	DRM_V3D_PARAM_SUPPORTS_PERFMON,
198	};	213	};
199		214
200	struct drm_v3d_get_param {	215	struct drm_v3d_get_param {
@@ -258,6 +273,127 @@ struct drm_v3d_submit_csd { · 57 unmodified lines
258	__u32 in_sync;	273	__u32 in_sync;
259	/* Sync object to signal when the CSD job is done. */	274	/* Sync object to signal when the CSD job is done. */
260	__u32 out_sync;	275	__u32 out_sync;
		276
		277	/* ID of the perfmon to attach to this job. 0 means no perfmon. */
		278	__u32 perfmon_id;
		279	};
		280
		281	enum {
		282	V3D_PERFCNT_FEP_VALID_PRIMTS_NO_PIXELS,
		283	V3D_PERFCNT_FEP_VALID_PRIMS,
		284	V3D_PERFCNT_FEP_EZ_NFCLIP_QUADS,
		285	V3D_PERFCNT_FEP_VALID_QUADS,
		286	V3D_PERFCNT_TLB_QUADS_STENCIL_FAIL,
		287	V3D_PERFCNT_TLB_QUADS_STENCILZ_FAIL,
		288	V3D_PERFCNT_TLB_QUADS_STENCILZ_PASS,
		289	V3D_PERFCNT_TLB_QUADS_ZERO_COV,
		290	V3D_PERFCNT_TLB_QUADS_NONZERO_COV,
		291	V3D_PERFCNT_TLB_QUADS_WRITTEN,
		292	V3D_PERFCNT_PTB_PRIM_VIEWPOINT_DISCARD,
		293	V3D_PERFCNT_PTB_PRIM_CLIP,
		294	V3D_PERFCNT_PTB_PRIM_REV,
		295	V3D_PERFCNT_QPU_IDLE_CYCLES,
		296	V3D_PERFCNT_QPU_ACTIVE_CYCLES_VERTEX_COORD_USER,
		297	V3D_PERFCNT_QPU_ACTIVE_CYCLES_FRAG,
		298	V3D_PERFCNT_QPU_CYCLES_VALID_INSTR,
		299	V3D_PERFCNT_QPU_CYCLES_TMU_STALL,
		300	V3D_PERFCNT_QPU_CYCLES_SCOREBOARD_STALL,
		301	V3D_PERFCNT_QPU_CYCLES_VARYINGS_STALL,
		302	V3D_PERFCNT_QPU_IC_HIT,
		303	V3D_PERFCNT_QPU_IC_MISS,
		304	V3D_PERFCNT_QPU_UC_HIT,
		305	V3D_PERFCNT_QPU_UC_MISS,
		306	V3D_PERFCNT_TMU_TCACHE_ACCESS,
		307	V3D_PERFCNT_TMU_TCACHE_MISS,
		308	V3D_PERFCNT_VPM_VDW_STALL,
		309	V3D_PERFCNT_VPM_VCD_STALL,
		310	V3D_PERFCNT_BIN_ACTIVE,
		311	V3D_PERFCNT_RDR_ACTIVE,
		312	V3D_PERFCNT_L2T_HITS,
		313	V3D_PERFCNT_L2T_MISSES,
		314	V3D_PERFCNT_CYCLE_COUNT,
		315	V3D_PERFCNT_QPU_CYCLES_STALLED_VERTEX_COORD_USER,
		316	V3D_PERFCNT_QPU_CYCLES_STALLED_FRAGMENT,
		317	V3D_PERFCNT_PTB_PRIMS_BINNED,
		318	V3D_PERFCNT_AXI_WRITES_WATCH_0,
		319	V3D_PERFCNT_AXI_READS_WATCH_0,
		320	V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_0,
		321	V3D_PERFCNT_AXI_READ_STALLS_WATCH_0,
		322	V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_0,
		323	V3D_PERFCNT_AXI_READ_BYTES_WATCH_0,
		324	V3D_PERFCNT_AXI_WRITES_WATCH_1,
		325	V3D_PERFCNT_AXI_READS_WATCH_1,
		326	V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_1,
		327	V3D_PERFCNT_AXI_READ_STALLS_WATCH_1,
		328	V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_1,
		329	V3D_PERFCNT_AXI_READ_BYTES_WATCH_1,
		330	V3D_PERFCNT_TLB_PARTIAL_QUADS,
		331	V3D_PERFCNT_TMU_CONFIG_ACCESSES,
		332	V3D_PERFCNT_L2T_NO_ID_STALL,
		333	V3D_PERFCNT_L2T_COM_QUE_STALL,
		334	V3D_PERFCNT_L2T_TMU_WRITES,
		335	V3D_PERFCNT_TMU_ACTIVE_CYCLES,
		336	V3D_PERFCNT_TMU_STALLED_CYCLES,
		337	V3D_PERFCNT_CLE_ACTIVE,
		338	V3D_PERFCNT_L2T_TMU_READS,
		339	V3D_PERFCNT_L2T_CLE_READS,
		340	V3D_PERFCNT_L2T_VCD_READS,
		341	V3D_PERFCNT_L2T_TMUCFG_READS,
		342	V3D_PERFCNT_L2T_SLC0_READS,
		343	V3D_PERFCNT_L2T_SLC1_READS,
		344	V3D_PERFCNT_L2T_SLC2_READS,
		345	V3D_PERFCNT_L2T_TMU_W_MISSES,
		346	V3D_PERFCNT_L2T_TMU_R_MISSES,
		347	V3D_PERFCNT_L2T_CLE_MISSES,
		348	V3D_PERFCNT_L2T_VCD_MISSES,
		349	V3D_PERFCNT_L2T_TMUCFG_MISSES,
		350	V3D_PERFCNT_L2T_SLC0_MISSES,
		351	V3D_PERFCNT_L2T_SLC1_MISSES,
		352	V3D_PERFCNT_L2T_SLC2_MISSES,
		353	V3D_PERFCNT_CORE_MEM_WRITES,
		354	V3D_PERFCNT_L2T_MEM_WRITES,
		355	V3D_PERFCNT_PTB_MEM_WRITES,
		356	V3D_PERFCNT_TLB_MEM_WRITES,
		357	V3D_PERFCNT_CORE_MEM_READS,
		358	V3D_PERFCNT_L2T_MEM_READS,
		359	V3D_PERFCNT_PTB_MEM_READS,
		360	V3D_PERFCNT_PSE_MEM_READS,
		361	V3D_PERFCNT_TLB_MEM_READS,
		362	V3D_PERFCNT_GMP_MEM_READS,
		363	V3D_PERFCNT_PTB_W_MEM_WORDS,
		364	V3D_PERFCNT_TLB_W_MEM_WORDS,
		365	V3D_PERFCNT_PSE_R_MEM_WORDS,
		366	V3D_PERFCNT_TLB_R_MEM_WORDS,
		367	V3D_PERFCNT_TMU_MRU_HITS,
		368	V3D_PERFCNT_COMPUTE_ACTIVE,
		369	V3D_PERFCNT_NUM,
		370	};
		371
		372	#define DRM_V3D_MAX_PERF_COUNTERS 32
		373
		374	struct drm_v3d_perfmon_create {
		375	__u32 id;
		376	__u32 ncounters;
		377	__u8 counters[DRM_V3D_MAX_PERF_COUNTERS];
		378	};
		379
		380	struct drm_v3d_perfmon_destroy {
		381	__u32 id;
		382	};
		383
		384	/*
		385	* Returns the values of the performance counters tracked by this
		386	* perfmon (as an array of ncounters u64 values).
		387	*
		388	* No implicit synchronization is performed, so the user has to
		389	* guarantee that any jobs using this perfmon have already been
		390	* completed (probably by blocking on the seqno returned by the
		391	* last exec that used the perfmon).
		392	*/
		393	struct drm_v3d_perfmon_get_values {
		394	__u32 id;
		395	__u32 pad;
		396	__u64 values_ptr;
261	};	397	};
262		398
263	#if defined(__cplusplus)	399	#if defined(__cplusplus)

include/uapi/drm/vmwgfx_drm.h+41−0

@@ -72,6 +72,9 @@ extern "C" { · 71 unmodified lines
72	#define DRM_VMW_GB_SURFACE_CREATE_EXT 27	72	#define DRM_VMW_GB_SURFACE_CREATE_EXT 27
73	#define DRM_VMW_GB_SURFACE_REF_EXT 28	73	#define DRM_VMW_GB_SURFACE_REF_EXT 28
74	#define DRM_VMW_MSG 29	74	#define DRM_VMW_MSG 29
		75	#define DRM_VMW_MKSSTAT_RESET 30
		76	#define DRM_VMW_MKSSTAT_ADD 31
		77	#define DRM_VMW_MKSSTAT_REMOVE 32
75		78
76	/*************************************************************************/	79	/*************************************************************************/
77	/**	80	/**
@@ -1236,6 +1239,44 @@ struct drm_vmw_msg_arg { · 1158 unmodified lines
1236	__u32 receive_len;	1239	__u32 receive_len;
1237	};	1240	};
1238		1241
		1242	/**
		1243	* struct drm_vmw_mksstat_add_arg
		1244	*
		1245	* @stat: Pointer to user-space stat-counters array, page-aligned.
		1246	* @info: Pointer to user-space counter-infos array, page-aligned.
		1247	* @strs: Pointer to user-space stat strings, page-aligned.
		1248	* @stat_len: Length in bytes of stat-counters array.
		1249	* @info_len: Length in bytes of counter-infos array.
		1250	* @strs_len: Length in bytes of the stat strings, terminators included.
		1251	* @description: Pointer to instance descriptor string; will be truncated
		1252	* to MKS_GUEST_STAT_INSTANCE_DESC_LENGTH chars.
		1253	* @id: Output identifier of the produced record; -1 if error.
		1254	*
		1255	* Argument to the DRM_VMW_MKSSTAT_ADD ioctl.
		1256	*/
		1257	struct drm_vmw_mksstat_add_arg {
		1258	__u64 stat;
		1259	__u64 info;
		1260	__u64 strs;
		1261	__u64 stat_len;
		1262	__u64 info_len;
		1263	__u64 strs_len;
		1264	__u64 description;
		1265	__u64 id;
		1266	};
		1267
		1268	/**
		1269	* struct drm_vmw_mksstat_remove_arg
		1270	*
		1271	* @id: Identifier of the record being disposed, originally obtained through
		1272	* DRM_VMW_MKSSTAT_ADD ioctl.
		1273	*
		1274	* Argument to the DRM_VMW_MKSSTAT_REMOVE ioctl.
		1275	*/
		1276	struct drm_vmw_mksstat_remove_arg {
		1277	__u64 id;
		1278	};
		1279
1239	#if defined(__cplusplus)	1280	#if defined(__cplusplus)
1240	}	1281	}
1241	#endif	1282	#endif

include/uapi/linux/dma-buf.h+49−1

@@ -22,8 +22,56 @@ · 21 unmodified lines
22		22
23	#include <linux/types.h>	23	#include <linux/types.h>
24		24
25	/* begin/end dma-buf functions used for userspace mmap. */	25	/**
		26	* struct dma_buf_sync - Synchronize with CPU access.
		27	*
		28	* When a DMA buffer is accessed from the CPU via mmap, it is not always
		29	* possible to guarantee coherency between the CPU-visible map and underlying
		30	* memory. To manage coherency, DMA_BUF_IOCTL_SYNC must be used to bracket
		31	* any CPU access to give the kernel the chance to shuffle memory around if
		32	* needed.
		33	*
		34	* Prior to accessing the map, the client must call DMA_BUF_IOCTL_SYNC
		35	* with DMA_BUF_SYNC_START and the appropriate read/write flags. Once the
		36	* access is complete, the client should call DMA_BUF_IOCTL_SYNC with
		37	* DMA_BUF_SYNC_END and the same read/write flags.
		38	*
		39	* The synchronization provided via DMA_BUF_IOCTL_SYNC only provides cache
		40	* coherency. It does not prevent other processes or devices from
		41	* accessing the memory at the same time. If synchronization with a GPU or
		42	* other device driver is required, it is the client's responsibility to
		43	* wait for buffer to be ready for reading or writing before calling this
		44	* ioctl with DMA_BUF_SYNC_START. Likewise, the client must ensure that
		45	* follow-up work is not submitted to GPU or other device driver until
		46	* after this ioctl has been called with DMA_BUF_SYNC_END?
		47	*
		48	* If the driver or API with which the client is interacting uses implicit
		49	* synchronization, waiting for prior work to complete can be done via
		50	* poll() on the DMA buffer file descriptor. If the driver or API requires
		51	* explicit synchronization, the client may have to wait on a sync_file or
		52	* other synchronization primitive outside the scope of the DMA buffer API.
		53	*/
26	struct dma_buf_sync {	54	struct dma_buf_sync {
		55	/**
		56	* @flags: Set of access flags
		57	*
		58	* DMA_BUF_SYNC_START:
		59	* Indicates the start of a map access session.
		60	*
		61	* DMA_BUF_SYNC_END:
		62	* Indicates the end of a map access session.
		63	*
		64	* DMA_BUF_SYNC_READ:
		65	* Indicates that the mapped DMA buffer will be read by the
		66	* client via the CPU map.
		67	*
		68	* DMA_BUF_SYNC_WRITE:
		69	* Indicates that the mapped DMA buffer will be written by the
		70	* client via the CPU map.
		71	*
		72	* DMA_BUF_SYNC_RW:
		73	* An alias for DMA_BUF_SYNC_READ \| DMA_BUF_SYNC_WRITE.
		74	*/
27	__u64 flags;	75	__u64 flags;
28	};	76	};
29		77

include/uapi/linux/kfd_ioctl.h+9−7

  * - 1.3 - Add SMI events support
  * - 1.4 - Indicate new SRAM EDC bit in device properties
  * - 1.5 - Add SVM API
+ * - 1.6 - Query clear flags in SVM get_attr API
  */
 #define KFD_IOCTL_MAJOR_VERSION 1
-#define KFD_IOCTL_MINOR_VERSION 5
+#define KFD_IOCTL_MINOR_VERSION 6
 struct kfd_ioctl_get_version_args {
 	__u32 major_version;	/* from KFD */
  * @KFD_IOCTL_SVM_ATTR_PREFERRED_LOC or
  * @KFD_IOCTL_SVM_ATTR_PREFETCH_LOC resepctively. For
  * @KFD_IOCTL_SVM_ATTR_SET_FLAGS, flags of all pages will be
- * aggregated by bitwise AND. The minimum  migration granularity
+ * aggregated by bitwise AND. That means, a flag will be set in the
- * throughout the range will be returned for
+ * output, if that flag is set for all pages in the range. For
- * @KFD_IOCTL_SVM_ATTR_GRANULARITY.
+ * @KFD_IOCTL_SVM_ATTR_CLR_FLAGS, flags of all pages will be
+ * aggregated by bitwise NOR. That means, a flag will be set in the
+ * output, if that flag is clear for all pages in the range.
+ * The minimum migration granularity throughout the range will be
+ * returned for @KFD_IOCTL_SVM_ATTR_GRANULARITY.
  *
  * Querying of accessibility attributes works by initializing the
  * attribute type to @KFD_IOCTL_SVM_ATTR_ACCESS and the value to the
  * GPUID being queried. Multiple attributes can be given to allow
  * querying multiple GPUIDs. The ioctl function overwrites the
  * attribute type to indicate the access for the specified GPU.
- *
- * @KFD_IOCTL_SVM_ATTR_CLR_FLAGS is invalid for
- * @KFD_IOCTL_SVM_OP_GET_ATTR.
  */
 struct kfd_ioctl_svm_args {
 	__u64 start_addr;