Pull drm updates from Dave Airlie: "Highlights: - i915 has seen a lot of refactoring and uAPI cleanups due to a change in the upstream direction going forward This has all been audited with known userspace, but there may be some pitfalls that were missed. - i915 now uses common TTM to enable discrete memory on DG1/2 GPUs - i915 enables Jasper and Elkhart Lake by default and has preliminary XeHP/DG2 support - amdgpu adds support for Cyan Skillfish - lots of implicit fencing rules documented and fixed up in drivers - msm now uses the core scheduler - the irq midlayer has been removed for non-legacy drivers - the sysfb code now works on more than x86. Otherwise the usual smattering of stuff everywhere, panels, bridges, refactorings. Detailed summary: core: - extract i915 eDP backlight into core - DP aux bus support - drm_device.irq_enabled removed - port drivers to native irq interfaces - export gem shadow plane handling for vgem - print proper driver name in framebuffer registration - driver fixes for implicit fencing rules - ARM fixed rate compression modifier added - updated fb damage handling - rmfb ioctl logging/docs - drop drm_gem_object_put_locked - define DRM_FORMAT_MAX_PLANES - add gem fb vmap/vunmap helpers - add lockdep_assert(once) helpers - mark drm irq midlayer as legacy - use offset adjusted bo mapping conversion vgaarb: - cleanups fbdev: - extend efifb handling to all arches - div by 0 fixes for multiple drivers udmabuf: - add hugepage mapping support dma-buf: - non-dynamic exporter fixups - document implicit fencing rules amdgpu: - Initial Cyan Skillfish support - switch virtual DCE over to vkms based atomic - VCN/JPEG power down fixes - NAVI PCIE link handling fixes - AMD HDMI freesync fixes - Yellow Carp + Beige Goby fixes - Clockgating/S0ix/SMU/EEPROM fixes - embed hw fence in job - rework dma-resv handling - ensure eviction to system ram amdkfd: - uapi: SVM address range query added - sysfs leak fix - GPUVM TLB optimizations - vmfault/migration counters i915: - Enable JSL and EHL by default - preliminary XeHP/DG2 support - remove all CNL support (never shipped) - move to TTM for discrete memory support - allow mixed object mmap handling - GEM uAPI spring cleaning - add I915_MMAP_OBJECT_FIXED - reinstate ADL-P mmap ioctls - drop a bunch of unused by userspace features - disable and remove GPU relocations - revert some i915 misfeatures - major refactoring of GuC for Gen11+ - execbuffer object locking separate step - reject caching/set-domain on discrete - Enable pipe DMC loading on XE-LPD and ADL-P - add PSF GV point support - Refactor and fix DDI buffer translations - Clean up FBC CFB allocation code - Finish INTEL_GEN() and friends macro conversions nouveau: - add eDP backlight support - implicit fence fix msm: - a680/7c3 support - drm/scheduler conversion panfrost: - rework GPU reset virtio: - fix fencing for planes ast: - add detect support bochs: - move to tiny GPU driver vc4: - use hotplug irqs - HDMI codec support vmwgfx: - use internal vmware device headers ingenic: - demidlayering irq rcar-du: - shutdown fixes - convert to bridge connector helpers zynqmp-dsub: - misc fixes mgag200: - convert PLL handling to atomic mediatek: - MT8133 AAL support - gem mmap object support - MT8167 support etnaviv: - NXP Layerscape LS1028A SoC support - GEM mmap cleanups tegra: - new user API exynos: - missing unlock fix - build warning fix - use refcount_t" * tag 'drm-next-2021-08-31-1' of git://anongit.freedesktop.org/drm/drm: (1318 commits) drm/amd/display: Move AllowDRAMSelfRefreshOrDRAMClockChangeInVblank to bounding box drm/amd/display: Remove duplicate dml init drm/amd/display: Update bounding box states (v2) drm/amd/display: Update number of DCN3 clock states drm/amdgpu: disable GFX CGCG in aldebaran drm/amdgpu: Clear RAS interrupt status on aldebaran drm/amdgpu: Add support for RAS XGMI err query drm/amdkfd: Account for SH/SE count when setting up cu masks. drm/amdgpu: rename amdgpu_bo_get_preferred_pin_domain drm/amdgpu: drop redundant cancel_delayed_work_sync call drm/amdgpu: add missing cleanups for more ASICs on UVD/VCE suspend drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend drm/amdkfd: map SVM range with correct access permission drm/amdkfd: check access permisson to restore retry fault drm/amdgpu: Update RAS XGMI Error Query drm/amdgpu: Add driver infrastructure for MCA RAS drm/amd/display: Add Logging for HDMI color depth information drm/amd/amdgpu: consolidate PSP TA init shared buf functions drm/amd/amdgpu: add name field back to ras_common_if drm/amdgpu: Fix build with missing pm_suspend_target_state module export ...
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| @@ -22,8 +22,56 @@ · 21 unmodified lines | |||
| 22 | 22 | ||
| 23 | #include <linux/types.h> | 23 | #include <linux/types.h> |
| 24 | 24 | ||
| 25 | /* begin/end dma-buf functions used for userspace mmap. */ | 25 | /** |
| 26 | * struct dma_buf_sync - Synchronize with CPU access. | ||
| 27 | * | ||
| 28 | * When a DMA buffer is accessed from the CPU via mmap, it is not always | ||
| 29 | * possible to guarantee coherency between the CPU-visible map and underlying | ||
| 30 | * memory. To manage coherency, DMA_BUF_IOCTL_SYNC must be used to bracket | ||
| 31 | * any CPU access to give the kernel the chance to shuffle memory around if | ||
| 32 | * needed. | ||
| 33 | * | ||
| 34 | * Prior to accessing the map, the client must call DMA_BUF_IOCTL_SYNC | ||
| 35 | * with DMA_BUF_SYNC_START and the appropriate read/write flags. Once the | ||
| 36 | * access is complete, the client should call DMA_BUF_IOCTL_SYNC with | ||
| 37 | * DMA_BUF_SYNC_END and the same read/write flags. | ||
| 38 | * | ||
| 39 | * The synchronization provided via DMA_BUF_IOCTL_SYNC only provides cache | ||
| 40 | * coherency. It does not prevent other processes or devices from | ||
| 41 | * accessing the memory at the same time. If synchronization with a GPU or | ||
| 42 | * other device driver is required, it is the client's responsibility to | ||
| 43 | * wait for buffer to be ready for reading or writing before calling this | ||
| 44 | * ioctl with DMA_BUF_SYNC_START. Likewise, the client must ensure that | ||
| 45 | * follow-up work is not submitted to GPU or other device driver until | ||
| 46 | * after this ioctl has been called with DMA_BUF_SYNC_END? | ||
| 47 | * | ||
| 48 | * If the driver or API with which the client is interacting uses implicit | ||
| 49 | * synchronization, waiting for prior work to complete can be done via | ||
| 50 | * poll() on the DMA buffer file descriptor. If the driver or API requires | ||
| 51 | * explicit synchronization, the client may have to wait on a sync_file or | ||
| 52 | * other synchronization primitive outside the scope of the DMA buffer API. | ||
| 53 | */ | ||
| 26 | struct dma_buf_sync { | 54 | struct dma_buf_sync { |
| 55 | /** | ||
| 56 | * @flags: Set of access flags | ||
| 57 | * | ||
| 58 | * DMA_BUF_SYNC_START: | ||
| 59 | * Indicates the start of a map access session. | ||
| 60 | * | ||
| 61 | * DMA_BUF_SYNC_END: | ||
| 62 | * Indicates the end of a map access session. | ||
| 63 | * | ||
| 64 | * DMA_BUF_SYNC_READ: | ||
| 65 | * Indicates that the mapped DMA buffer will be read by the | ||
| 66 | * client via the CPU map. | ||
| 67 | * | ||
| 68 | * DMA_BUF_SYNC_WRITE: | ||
| 69 | * Indicates that the mapped DMA buffer will be written by the | ||
| 70 | * client via the CPU map. | ||
| 71 | * | ||
| 72 | * DMA_BUF_SYNC_RW: | ||
| 73 | * An alias for DMA_BUF_SYNC_READ | DMA_BUF_SYNC_WRITE. | ||
| 74 | */ | ||
| 27 | __u64 flags; | 75 | __u64 flags; |
| 28 | }; | 76 | }; |
| 29 | 77 | ||
| @@ -31,9 +31,10 @@ · 30 unmodified lines | |||
| 31 | * - 1.3 - Add SMI events support | 31 | * - 1.3 - Add SMI events support |
| 32 | * - 1.4 - Indicate new SRAM EDC bit in device properties | 32 | * - 1.4 - Indicate new SRAM EDC bit in device properties |
| 33 | * - 1.5 - Add SVM API | 33 | * - 1.5 - Add SVM API |
| 34 | * - 1.6 - Query clear flags in SVM get_attr API | ||
| 34 | */ | 35 | */ |
| 35 | #define KFD_IOCTL_MAJOR_VERSION 1 | 36 | #define KFD_IOCTL_MAJOR_VERSION 1 |
| 36 | #define KFD_IOCTL_MINOR_VERSION 5 | 37 | #define KFD_IOCTL_MINOR_VERSION 6 |
| 37 | 38 | ||
| 38 | struct kfd_ioctl_get_version_args { | 39 | struct kfd_ioctl_get_version_args { |
| 39 | __u32 major_version; /* from KFD */ | 40 | __u32 major_version; /* from KFD */ |
| @@ -575,18 +576,19 @@ struct kfd_ioctl_svm_attribute { · 535 unmodified lines | |||
| 575 | * @KFD_IOCTL_SVM_ATTR_PREFERRED_LOC or | 576 | * @KFD_IOCTL_SVM_ATTR_PREFERRED_LOC or |
| 576 | * @KFD_IOCTL_SVM_ATTR_PREFETCH_LOC resepctively. For | 577 | * @KFD_IOCTL_SVM_ATTR_PREFETCH_LOC resepctively. For |
| 577 | * @KFD_IOCTL_SVM_ATTR_SET_FLAGS, flags of all pages will be | 578 | * @KFD_IOCTL_SVM_ATTR_SET_FLAGS, flags of all pages will be |
| 578 | * aggregated by bitwise AND. The minimum migration granularity | 579 | * aggregated by bitwise AND. That means, a flag will be set in the |
| 579 | * throughout the range will be returned for | 580 | * output, if that flag is set for all pages in the range. For |
| 580 | * @KFD_IOCTL_SVM_ATTR_GRANULARITY. | 581 | * @KFD_IOCTL_SVM_ATTR_CLR_FLAGS, flags of all pages will be |
| 582 | * aggregated by bitwise NOR. That means, a flag will be set in the | ||
| 583 | * output, if that flag is clear for all pages in the range. | ||
| 584 | * The minimum migration granularity throughout the range will be | ||
| 585 | * returned for @KFD_IOCTL_SVM_ATTR_GRANULARITY. | ||
| 581 | * | 586 | * |
| 582 | * Querying of accessibility attributes works by initializing the | 587 | * Querying of accessibility attributes works by initializing the |
| 583 | * attribute type to @KFD_IOCTL_SVM_ATTR_ACCESS and the value to the | 588 | * attribute type to @KFD_IOCTL_SVM_ATTR_ACCESS and the value to the |
| 584 | * GPUID being queried. Multiple attributes can be given to allow | 589 | * GPUID being queried. Multiple attributes can be given to allow |
| 585 | * querying multiple GPUIDs. The ioctl function overwrites the | 590 | * querying multiple GPUIDs. The ioctl function overwrites the |
| 586 | * attribute type to indicate the access for the specified GPU. | 591 | * attribute type to indicate the access for the specified GPU. |
| 587 | * | ||
| 588 | * @KFD_IOCTL_SVM_ATTR_CLR_FLAGS is invalid for | ||
| 589 | * @KFD_IOCTL_SVM_OP_GET_ATTR. | ||
| 590 | */ | 592 | */ |
| 591 | struct kfd_ioctl_svm_args { | 593 | struct kfd_ioctl_svm_args { |
| 592 | __u64 start_addr; | 594 | __u64 start_addr; |