lael-labs/linux

Documentation/core-api/irq/irq-domain.rst+25−3

@@ -55,8 +55,24 @@ exist then it will allocate a new Linux irq_desc, associate it with · 54 unmodified lines
55	the hwirq, and call the .map() callback so the driver can perform any	55	the hwirq, and call the .map() callback so the driver can perform any
56	required hardware setup.	56	required hardware setup.
57		57
58	When an interrupt is received, irq_find_mapping() function should	58	Once a mapping has been established, it can be retrieved or used via a
59	be used to find the Linux IRQ number from the hwirq number.	59	variety of methods:
		60
		61	- irq_resolve_mapping() returns a pointer to the irq_desc structure
		62	for a given domain and hwirq number, and NULL if there was no
		63	mapping.
		64	- irq_find_mapping() returns a Linux IRQ number for a given domain and
		65	hwirq number, and 0 if there was no mapping
		66	- irq_linear_revmap() is now identical to irq_find_mapping(), and is
		67	deprecated
		68	- generic_handle_domain_irq() handles an interrupt described by a
		69	domain and a hwirq number
		70	- handle_domain_irq() does the same thing for root interrupt
		71	controllers and deals with the set_irq_reg()/irq_enter() sequences
		72	that most architecture requires
		73
		74	Note that irq domain lookups must happen in contexts that are
		75	compatible with a RCU read-side critical section.
60		76
61	The irq_create_mapping() function must be called atleast once	77	The irq_create_mapping() function must be called atleast once
62	before any call to irq_find_mapping(), lest the descriptor will not	78	before any call to irq_find_mapping(), lest the descriptor will not
@@ -137,7 +153,9 @@ required. Calling irq_create_direct_mapping() will allocate a Linux · 74 unmodified lines
137	IRQ number and call the .map() callback so that driver can program the	153	IRQ number and call the .map() callback so that driver can program the
138	Linux IRQ number into the hardware.	154	Linux IRQ number into the hardware.
139		155
140	Most drivers cannot use this mapping.	156	Most drivers cannot use this mapping, and it is now gated on the
		157	CONFIG_IRQ_DOMAIN_NOMAP option. Please refrain from introducing new
		158	users of this API.
141		159
142	Legacy	160	Legacy
143	------	161	------
@@ -157,6 +175,10 @@ for IRQ numbers that are passed to struct device registrations. In that · 13 unmodified lines
157	case the Linux IRQ numbers cannot be dynamically assigned and the legacy	175	case the Linux IRQ numbers cannot be dynamically assigned and the legacy
158	mapping should be used.	176	mapping should be used.
159		177
		178	As the name implies, the *_legacy() functions are deprecated and only
		179	exist to ease the support of ancient platforms. No new users should be
		180	added.
		181
160	The legacy map assumes a contiguous range of IRQ numbers has already	182	The legacy map assumes a contiguous range of IRQ numbers has already
161	been allocated for the controller and that the IRQ number can be	183	been allocated for the controller and that the IRQ number can be
162	calculated by adding a fixed offset to the hwirq number, and	184	calculated by adding a fixed offset to the hwirq number, and

Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml+4−1

@@ -22,7 +22,10 @@ properties: · 21 unmodified lines
22	maxItems: 1	22	maxItems: 1
23		23
24	clocks:	24	clocks:
25	maxItems: 1	25	minItems: 1
		26	items:
		27	- description: APB interface clock source
		28	- description: GPIO debounce reference clock source
26		29
27	gpio-controller: true	30	gpio-controller: true
28		31

arch/arc/kernel/mcip.c+1−1

@@ -352,7 +352,7 @@ static void idu_cascade_isr(struct irq_desc *desc) · 351 unmodified lines
352	irq_hw_number_t idu_hwirq = core_hwirq - FIRST_EXT_IRQ;	352	irq_hw_number_t idu_hwirq = core_hwirq - FIRST_EXT_IRQ;
353		353
354	chained_irq_enter(core_chip, desc);	354	chained_irq_enter(core_chip, desc);
355	generic_handle_irq(irq_find_mapping(idu_domain, idu_hwirq));	355	generic_handle_domain_irq(idu_domain, idu_hwirq);
356	chained_irq_exit(core_chip, desc);	356	chained_irq_exit(core_chip, desc);
357	}	357	}
358		358

arch/arm/common/sa1111.c+2−10

 	return irq_create_mapping(sachip->irqdomain, hwirq);
 }
-static void sa1111_handle_irqdomain(struct irq_domain *irqdomain, int irq)
-{
-	struct irq_desc *d = irq_to_desc(irq_linear_revmap(irqdomain, irq));
-	if (d)
-		generic_handle_irq_desc(d);
-}
 /*
  * SA1111 interrupt support.  Since clearing an IRQ while there are
  * active IRQs causes the interrupt output to pulse, the upper levels
 	for (i = 0; stat0; i++, stat0 >>= 1)
 		if (stat0 & 1)
-			sa1111_handle_irqdomain(irqdomain, i);
+			generic_handle_domain_irq(irqdomain, i);
 	for (i = 32; stat1; i++, stat1 >>= 1)
 		if (stat1 & 1)
-			sa1111_handle_irqdomain(irqdomain, i);
+			generic_handle_domain_irq(irqdomain, i);
 	/* For level-based interrupts */
 	desc->irq_data.chip->irq_unmask(&desc->irq_data);

arch/arm/mach-pxa/pxa_cplds_irqs.c+2−4

 	do {
 		pending = readl(fpga->base + FPGA_IRQ_SET_CLR) & fpga->irq_mask;
-		for_each_set_bit(bit, &pending, CPLDS_NB_IRQ) {
+		for_each_set_bit(bit, &pending, CPLDS_NB_IRQ)
-			generic_handle_irq(irq_find_mapping(fpga->irqdomain,
+			generic_handle_domain_irq(fpga->irqdomain, bit);
-							    bit));
-		}
 	} while (pending);
 	return IRQ_HANDLED;

arch/arm/mach-s3c/irq-s3c24xx.c+2−3

 	struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc);
 	struct s3c_irq_intc *intc = irq_data->intc;
 	struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
-	unsigned int n, offset, irq;
+	unsigned int n, offset;
 	unsigned long src, msk;
 	/* we're using individual domains for the non-dt case
 	while (src) {
 		n = __ffs(src);
 		src &= ~(1 << n);
-		irq = irq_find_mapping(sub_intc->domain, offset + n);
+		generic_handle_domain_irq(sub_intc->domain, offset + n);
-		generic_handle_irq(irq);
 	}
 	chained_irq_exit(chip, desc);

arch/mips/ath25/ar2315.c+7−7

@@ -69,24 +69,24 @@ static void ar2315_misc_irq_handler(struct irq_desc *desc) · 68 unmodified lines
69	{	69	{
70	u32 pending = ar2315_rst_reg_read(AR2315_ISR) &	70	u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
71	ar2315_rst_reg_read(AR2315_IMR);	71	ar2315_rst_reg_read(AR2315_IMR);
72	unsigned nr, misc_irq = 0;	72	unsigned nr;
		73	int ret = 0;
73		74
74	if (pending) {	75	if (pending) {
75	struct irq_domain *domain = irq_desc_get_handler_data(desc);	76	struct irq_domain *domain = irq_desc_get_handler_data(desc);
76		77
77	nr = __ffs(pending);	78	nr = __ffs(pending);
78	misc_irq = irq_find_mapping(domain, nr);
79	}
80		79
81	if (misc_irq) {
82	if (nr == AR2315_MISC_IRQ_GPIO)	80	if (nr == AR2315_MISC_IRQ_GPIO)
83	ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);	81	ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
84	else if (nr == AR2315_MISC_IRQ_WATCHDOG)	82	else if (nr == AR2315_MISC_IRQ_WATCHDOG)
85	ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);	83	ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
86	generic_handle_irq(misc_irq);	84
87	} else {	85	ret = generic_handle_domain_irq(domain, nr);
88	spurious_interrupt();
89	}	86	}
		87
		88	if (!pending \|\| ret)
		89	spurious_interrupt();
90	}	90	}
91		91
92	static void ar2315_misc_irq_unmask(struct irq_data *d)	92	static void ar2315_misc_irq_unmask(struct irq_data *d)

arch/mips/ath25/ar5312.c+6−7

 {
 	u32 pending = ar5312_rst_reg_read(AR5312_ISR) &
 		      ar5312_rst_reg_read(AR5312_IMR);
-	unsigned nr, misc_irq = 0;
+	unsigned nr;
+	int ret = 0;
 	if (pending) {
 		struct irq_domain *domain = irq_desc_get_handler_data(desc);
 		nr = __ffs(pending);
-		misc_irq = irq_find_mapping(domain, nr);
-	}
-	if (misc_irq) {
+		ret = generic_handle_domain_irq(domain, nr);
-		generic_handle_irq(misc_irq);
 		if (nr == AR5312_MISC_IRQ_TIMER)
 			ar5312_rst_reg_read(AR5312_TIMER);
-	} else {
-		spurious_interrupt();
 	}
+	if (!pending || ret)
+		spurious_interrupt();
 }
 /* Enable the specified AR5312_MISC_IRQ interrupt */

arch/mips/lantiq/irq.c+1−1

@@ -300,7 +300,7 @@ static void ltq_hw_irq_handler(struct irq_desc *desc) · 299 unmodified lines
300	*/	300	*/
301	irq = __fls(irq);	301	irq = __fls(irq);
302	hwirq = irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module);	302	hwirq = irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module);
303	generic_handle_irq(irq_linear_revmap(ltq_domain, hwirq));	303	generic_handle_domain_irq(ltq_domain, hwirq);
304		304
305	/* if this is a EBU irq, we need to ack it or get a deadlock */	305	/* if this is a EBU irq, we need to ack it or get a deadlock */
306	if (irq == LTQ_ICU_EBU_IRQ && !module && LTQ_EBU_PCC_ISTAT != 0)	306	if (irq == LTQ_ICU_EBU_IRQ && !module && LTQ_EBU_PCC_ISTAT != 0)

arch/mips/pci/pci-ar2315.c+3−5

 	struct ar2315_pci_ctrl *apc = irq_desc_get_handler_data(desc);
 	u32 pending = ar2315_pci_reg_read(apc, AR2315_PCI_ISR) &
 		      ar2315_pci_reg_read(apc, AR2315_PCI_IMR);
-	unsigned pci_irq = 0;
+	int ret = 0;
 	if (pending)
-		pci_irq = irq_find_mapping(apc->domain, __ffs(pending));
+		ret = generic_handle_domain_irq(apc->domain, __ffs(pending));
-	if (pci_irq)
+	if (!pending || ret)
-		generic_handle_irq(pci_irq);
-	else
 		spurious_interrupt();
 }

arch/mips/pci/pci-rt3883.c+2−3

@@ -140,10 +140,9 @@ static void rt3883_pci_irq_handler(struct irq_desc *desc) · 139 unmodified lines
140	}	140	}
141		141
142	while (pending) {	142	while (pending) {
143	unsigned irq, bit = __ffs(pending);	143	unsigned bit = __ffs(pending);
144		144
145	irq = irq_find_mapping(rpc->irq_domain, bit);	145	generic_handle_domain_irq(rpc->irq_domain, bit);
146	generic_handle_irq(irq);
147		146
148	pending &= ~BIT(bit);	147	pending &= ~BIT(bit);
149	}	148	}

arch/mips/ralink/irq.c+1−1

@@ -100,7 +100,7 @@ static void ralink_intc_irq_handler(struct irq_desc *desc) · 99 unmodified lines
100		100
101	if (pending) {	101	if (pending) {
102	struct irq_domain *domain = irq_desc_get_handler_data(desc);	102	struct irq_domain *domain = irq_desc_get_handler_data(desc);
103	generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));	103	generic_handle_domain_irq(domain, __ffs(pending));
104	} else {	104	} else {
105	spurious_interrupt();	105	spurious_interrupt();
106	}	106	}

arch/mips/sgi-ip27/ip27-irq.c+6−10

 	unsigned long *mask = per_cpu(irq_enable_mask, cpu);
 	struct irq_domain *domain;
 	u64 pend0;
-	int irq;
+	int ret;
 	/* copied from Irix intpend0() */
 	pend0 = LOCAL_HUB_L(PI_INT_PEND0);
 #endif
 	{
 		domain = irq_desc_get_handler_data(desc);
-		irq = irq_linear_revmap(domain, __ffs(pend0));
+		ret = generic_handle_domain_irq(domain, __ffs(pend0));
-		if (irq)
+		if (ret)
-			generic_handle_irq(irq);
-		else
 			spurious_interrupt();
 	}
 	unsigned long *mask = per_cpu(irq_enable_mask, cpu);
 	struct irq_domain *domain;
 	u64 pend1;
-	int irq;
+	int ret;
 	/* copied from Irix intpend0() */
 	pend1 = LOCAL_HUB_L(PI_INT_PEND1);
 		return;
 	domain = irq_desc_get_handler_data(desc);
-	irq = irq_linear_revmap(domain, __ffs(pend1) + 64);
+	ret = generic_handle_domain_irq(domain, __ffs(pend1) + 64);
-	if (irq)
+	if (ret)
-		generic_handle_irq(irq);
-	else
 		spurious_interrupt();
 	LOCAL_HUB_L(PI_INT_PEND1);

arch/mips/sgi-ip30/ip30-irq.c+3−5

 	int cpu = smp_processor_id();
 	struct irq_domain *domain;
 	u64 pend, mask;
-	int irq;
+	int ret;
 	pend = heart_read(&heart_regs->isr);
 	mask = (heart_read(&heart_regs->imr[cpu]) &
 #endif
 	{
 		domain = irq_desc_get_handler_data(desc);
-		irq = irq_linear_revmap(domain, __ffs(pend));
+		ret = generic_handle_domain_irq(domain, __ffs(pend));
-		if (irq)
+		if (ret)
-			generic_handle_irq(irq);
-		else
 			spurious_interrupt();
 	}
 }

arch/nios2/kernel/irq.c+1−3

 asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs)
 {
 	struct pt_regs *oldregs = set_irq_regs(regs);
-	int irq;
 	irq_enter();
-	irq = irq_find_mapping(NULL, hwirq);
+	generic_handle_domain_irq(NULL, hwirq);
-	generic_handle_irq(irq);
 	irq_exit();
 	set_irq_regs(oldregs);

arch/powerpc/platforms/4xx/uic.c+1−3

 	struct uic *uic = irq_desc_get_handler_data(desc);
 	u32 msr;
 	int src;
-	int subvirq;
 	raw_spin_lock(&desc->lock);
 	if (irqd_is_level_type(idata))
 	src = 32 - ffs(msr);
-	subvirq = irq_linear_revmap(uic->irqhost, src);
+	generic_handle_domain_irq(uic->irqhost, src);
-	generic_handle_irq(subvirq);
 uic_irq_ret:
 	raw_spin_lock(&desc->lock);

arch/powerpc/platforms/512x/mpc5121_ads_cpld.c+10−13

 	.irq_unmask = cpld_unmask_irq,
 };
-static int
+static unsigned int
 cpld_pic_get_irq(int offset, u8 ignore, u8 __iomem *statusp,
 			    u8 __iomem *maskp)
 {
-	int cpld_irq;
 	u8 status = in_8(statusp);
 	u8 mask = in_8(maskp);
 	status |= (ignore | mask);
 	if (status == 0xff)
-		return 0;
+		return ~0;
-	cpld_irq = ffz(status) + offset;
-	return irq_linear_revmap(cpld_pic_host, cpld_irq);
+	return ffz(status) + offset;
 }
 static void cpld_pic_cascade(struct irq_desc *desc)
 {
-	unsigned int irq;
+	unsigned int hwirq;
-	irq = cpld_pic_get_irq(0, PCI_IGNORE, &cpld_regs->pci_status,
+	hwirq = cpld_pic_get_irq(0, PCI_IGNORE, &cpld_regs->pci_status,
 		&cpld_regs->pci_mask);
-	if (irq) {
+	if (hwirq != ~0) {
-		generic_handle_irq(irq);
+		generic_handle_domain_irq(cpld_pic_host, hwirq);
 		return;
 	}
-	irq = cpld_pic_get_irq(8, MISC_IGNORE, &cpld_regs->misc_status,
+	hwirq = cpld_pic_get_irq(8, MISC_IGNORE, &cpld_regs->misc_status,
 		&cpld_regs->misc_mask);
-	if (irq) {
+	if (hwirq != ~0) {
-		generic_handle_irq(irq);
+		generic_handle_domain_irq(cpld_pic_host, hwirq);
 		return;
 	}
 }

arch/powerpc/platforms/52xx/media5200.c+4−5

 static void media5200_irq_cascade(struct irq_desc *desc)
 {
 	struct irq_chip *chip = irq_desc_get_chip(desc);
-	int sub_virq, val;
+	int val;
 	u32 status, enable;
 	/* Mask off the cascaded IRQ */
 	enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS);
 	val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT);
 	if (val) {
-		sub_virq = irq_linear_revmap(media5200_irq.irqhost, val - 1);
+		generic_handle_domain_irq(media5200_irq.irqhost, val - 1);
-		/* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i subvirq=%i\n",
+		/* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i\n",
-		 *          __func__, virq, status, enable, val - 1, sub_virq);
+		 *          __func__, virq, status, enable, val - 1);
 		 */
-		generic_handle_irq(sub_virq);
 	}
 	/* Processing done; can reenable the cascade now */

arch/powerpc/platforms/52xx/mpc52xx_gpt.c+2−5

 static void mpc52xx_gpt_irq_cascade(struct irq_desc *desc)
 {
 	struct mpc52xx_gpt_priv *gpt = irq_desc_get_handler_data(desc);
-	int sub_virq;
 	u32 status;
 	status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK;
-	if (status) {
+	if (status)
-		sub_virq = irq_linear_revmap(gpt->irqhost, 0);
+		generic_handle_domain_irq(gpt->irqhost, 0);
-		generic_handle_irq(sub_virq);
-	}
 }
 static int mpc52xx_gpt_irq_map(struct irq_domain *h, unsigned int virq,

arch/powerpc/platforms/82xx/pq2ads-pci-pic.c+2−4

 			break;
 		for (bit = 0; pend != 0; ++bit, pend <<= 1) {
-			if (pend & 0x80000000) {
+			if (pend & 0x80000000)
-				int virq = irq_linear_revmap(priv->host, bit);
+				generic_handle_domain_irq(priv->host, bit);
-				generic_handle_irq(virq);
-			}
 		}
 	}
 }

arch/powerpc/platforms/cell/interrupt.c+2−6

 			out_be64(&node_iic->iic_is, ack);
 		/* handle them */
 		for (cascade = 63; cascade >= 0; cascade--)
-			if (bits & (0x8000000000000000UL >> cascade)) {
+			if (bits & (0x8000000000000000UL >> cascade))
-				unsigned int cirq =
+				generic_handle_domain_irq(iic_host,
-					irq_linear_revmap(iic_host,
 							  base | cascade);
-				if (cirq)
-					generic_handle_irq(cirq);
-			}
 		/* post-ack level interrupts */
 		ack = bits & ~IIC_ISR_EDGE_MASK;
 		if (ack)

arch/powerpc/platforms/cell/spider-pic.c+3−8

 {
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 	struct spider_pic *pic = irq_desc_get_handler_data(desc);
-	unsigned int cs, virq;
+	unsigned int cs;
 	cs = in_be32(pic->regs + TIR_CS) >> 24;
-	if (cs == SPIDER_IRQ_INVALID)
+	if (cs != SPIDER_IRQ_INVALID)
-		virq = 0;
+		generic_handle_domain_irq(pic->host, cs);
-	else
-		virq = irq_linear_revmap(pic->host, cs);
-	if (virq)
-		generic_handle_irq(virq);
 	chip->irq_eoi(&desc->irq_data);
 }

arch/powerpc/platforms/embedded6xx/hlwd-pic.c+7−8

 static unsigned int __hlwd_pic_get_irq(struct irq_domain *h)
 {
 	void __iomem *io_base = h->host_data;
-	int irq;
 	u32 irq_status;
 	irq_status = in_be32(io_base + HW_BROADWAY_ICR) &
 	if (irq_status == 0)
 		return 0;	/* no more IRQs pending */
-	irq = __ffs(irq_status);
+	return __ffs(irq_status);
-	return irq_linear_revmap(h, irq);
 }
 static void hlwd_pic_irq_cascade(struct irq_desc *desc)
 {
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 	struct irq_domain *irq_domain = irq_desc_get_handler_data(desc);
-	unsigned int virq;
+	unsigned int hwirq;
 	raw_spin_lock(&desc->lock);
 	chip->irq_mask(&desc->irq_data); /* IRQ_LEVEL */
 	raw_spin_unlock(&desc->lock);
-	virq = __hlwd_pic_get_irq(irq_domain);
+	hwirq = __hlwd_pic_get_irq(irq_domain);
-	if (virq)
+	if (hwirq)
-		generic_handle_irq(virq);
+		generic_handle_domain_irq(irq_domain, hwirq);
 	else
 		pr_err("spurious interrupt!\n");
 unsigned int hlwd_pic_get_irq(void)
 {
-	return __hlwd_pic_get_irq(hlwd_irq_host);
+	unsigned int hwirq = __hlwd_pic_get_irq(hlwd_irq_host);
+	return hwirq ? irq_linear_revmap(hlwd_irq_host, hwirq) : 0;
 }
 /*

arch/powerpc/platforms/powernv/opal-irqchip.c+4−7

 	e = READ_ONCE(last_outstanding_events) & opal_event_irqchip.mask;
 again:
 	while (e) {
-		int virq, hwirq;
+		int hwirq;
 		hwirq = fls64(e) - 1;
 		e &= ~BIT_ULL(hwirq);
 		local_irq_disable();
-		virq = irq_find_mapping(opal_event_irqchip.domain, hwirq);
+		irq_enter();
-		if (virq) {
+		generic_handle_domain_irq(opal_event_irqchip.domain, hwirq);
-			irq_enter();
+		irq_exit();
-			generic_handle_irq(virq);
-			irq_exit();
-		}
 		local_irq_enable();
 		cond_resched();

arch/powerpc/sysdev/fsl_mpic_err.c+4−7

 	struct mpic *mpic = (struct mpic *) data;
 	u32 eisr, eimr;
 	int errint;
-	unsigned int cascade_irq;
 	eisr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EISR);
 	eimr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EIMR);
 		return IRQ_NONE;
 	while (eisr) {
+		int ret;
 		errint = __builtin_clz(eisr);
-		cascade_irq = irq_linear_revmap(mpic->irqhost,
+		ret = generic_handle_domain_irq(mpic->irqhost,
-				 mpic->err_int_vecs[errint]);
+						mpic->err_int_vecs[errint]);
-		WARN_ON(!cascade_irq);
+		if (WARN_ON(ret)) {
-		if (cascade_irq) {
-			generic_handle_irq(cascade_irq);
-		} else {
 			eimr |=  1 << (31 - errint);
 			mpic_fsl_err_write(mpic->err_regs, eimr);
 		}

arch/powerpc/sysdev/fsl_msi.c+4−8

@@ -266,7 +266,6 @@ out_free: · 265 unmodified lines
266		266
267	static irqreturn_t fsl_msi_cascade(int irq, void *data)	267	static irqreturn_t fsl_msi_cascade(int irq, void *data)
268	{	268	{
269	unsigned int cascade_irq;
270	struct fsl_msi *msi_data;	269	struct fsl_msi *msi_data;
271	int msir_index = -1;	270	int msir_index = -1;
272	u32 msir_value = 0;	271	u32 msir_value = 0;
@@ -279,9 +278,6 @@ static irqreturn_t fsl_msi_cascade(int irq, void *data) · 6 unmodified lines
279		278
280	msir_index = cascade_data->index;	279	msir_index = cascade_data->index;
281		280
282	if (msir_index >= NR_MSI_REG_MAX)
283	cascade_irq = 0;
284
285	switch (msi_data->feature & FSL_PIC_IP_MASK) {	281	switch (msi_data->feature & FSL_PIC_IP_MASK) {
286	case FSL_PIC_IP_MPIC:	282	case FSL_PIC_IP_MPIC:
287	msir_value = fsl_msi_read(msi_data->msi_regs,	283	msir_value = fsl_msi_read(msi_data->msi_regs,
@@ -305,15 +301,15 @@ static irqreturn_t fsl_msi_cascade(int irq, void *data) · 17 unmodified lines
305	}	301	}
306		302
307	while (msir_value) {	303	while (msir_value) {
		304	int err;
308	intr_index = ffs(msir_value) - 1;	305	intr_index = ffs(msir_value) - 1;
309		306
310	cascade_irq = irq_linear_revmap(msi_data->irqhost,	307	err = generic_handle_domain_irq(msi_data->irqhost,
311	msi_hwirq(msi_data, msir_index,	308	msi_hwirq(msi_data, msir_index,
312	intr_index + have_shift));	309	intr_index + have_shift));
313	if (cascade_irq) {	310	if (!err)
314	generic_handle_irq(cascade_irq);
315	ret = IRQ_HANDLED;	311	ret = IRQ_HANDLED;
316	}	312
317	have_shift += intr_index + 1;	313	have_shift += intr_index + 1;
318	msir_value = msir_value >> (intr_index + 1);	314	msir_value = msir_value >> (intr_index + 1);
319	}	315	}

arch/sh/boards/mach-se/7343/irq.c+1−1

@@ -38,7 +38,7 @@ static void se7343_irq_demux(struct irq_desc *desc) · 37 unmodified lines
38	mask = ioread16(se7343_irq_regs + PA_CPLD_ST_REG);	38	mask = ioread16(se7343_irq_regs + PA_CPLD_ST_REG);
39		39
40	for_each_set_bit(bit, &mask, SE7343_FPGA_IRQ_NR)	40	for_each_set_bit(bit, &mask, SE7343_FPGA_IRQ_NR)
41	generic_handle_irq(irq_linear_revmap(se7343_irq_domain, bit));	41	generic_handle_domain_irq(se7343_irq_domain, bit);
42		42
43	chip->irq_unmask(data);	43	chip->irq_unmask(data);
44	}	44	}

arch/sh/boards/mach-se/7722/irq.c+1−1

@@ -37,7 +37,7 @@ static void se7722_irq_demux(struct irq_desc *desc) · 36 unmodified lines
37	mask = ioread16(se7722_irq_regs + IRQ01_STS_REG);	37	mask = ioread16(se7722_irq_regs + IRQ01_STS_REG);
38		38
39	for_each_set_bit(bit, &mask, SE7722_FPGA_IRQ_NR)	39	for_each_set_bit(bit, &mask, SE7722_FPGA_IRQ_NR)
40	generic_handle_irq(irq_linear_revmap(se7722_irq_domain, bit));	40	generic_handle_domain_irq(se7722_irq_domain, bit);
41		41
42	chip->irq_unmask(data);	42	chip->irq_unmask(data);
43	}	43	}

arch/sh/boards/mach-x3proto/gpio.c+1−1

@@ -68,7 +68,7 @@ static void x3proto_gpio_irq_handler(struct irq_desc *desc) · 67 unmodified lines
68		68
69	mask = __raw_readw(KEYDETR);	69	mask = __raw_readw(KEYDETR);
70	for_each_set_bit(pin, &mask, NR_BASEBOARD_GPIOS)	70	for_each_set_bit(pin, &mask, NR_BASEBOARD_GPIOS)
71	generic_handle_irq(irq_linear_revmap(x3proto_irq_domain, pin));	71	generic_handle_domain_irq(x3proto_irq_domain, pin);
72		72
73	chip->irq_unmask(data);	73	chip->irq_unmask(data);
74	}	74	}

arch/xtensa/kernel/irq.c+1−3

 asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs)
 {
-	int irq = irq_find_mapping(NULL, hwirq);
 #ifdef CONFIG_DEBUG_STACKOVERFLOW
 	/* Debugging check for stack overflow: is there less than 1KB free? */
 	{
 			       sp - sizeof(struct thread_info));
 	}
 #endif
-	generic_handle_irq(irq);
+	generic_handle_domain_irq(NULL, hwirq);
 }
 int arch_show_interrupts(struct seq_file *p, int prec)

drivers/edac/altera_edac.c+2−5

 	regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
 	bits = irq_status;
-	for_each_set_bit(bit, &bits, 32) {
+	for_each_set_bit(bit, &bits, 32)
-		irq = irq_linear_revmap(edac->domain, dberr * 32 + bit);
+		generic_handle_domain_irq(edac->domain, dberr * 32 + bit);
-		if (irq)
-			generic_handle_irq(irq);
-	}
 	chained_irq_exit(chip, desc);
 }

drivers/gpio/Kconfig+8−0

@@ -520,6 +520,14 @@ config GPIO_REG · 519 unmodified lines
520	A 32-bit single register GPIO fixed in/out implementation. This	520	A 32-bit single register GPIO fixed in/out implementation. This
521	can be used to represent any register as a set of GPIO signals.	521	can be used to represent any register as a set of GPIO signals.
522		522
		523	config GPIO_ROCKCHIP
		524	tristate "Rockchip GPIO support"
		525	depends on ARCH_ROCKCHIP \|\| COMPILE_TEST
		526	select GPIOLIB_IRQCHIP
		527	default ARCH_ROCKCHIP
		528	help
		529	Say yes here to support GPIO on Rockchip SoCs.
		530
523	config GPIO_SAMA5D2_PIOBU	531	config GPIO_SAMA5D2_PIOBU
524	tristate "SAMA5D2 PIOBU GPIO support"	532	tristate "SAMA5D2 PIOBU GPIO support"
525	depends on MFD_SYSCON	533	depends on MFD_SYSCON

drivers/gpio/Makefile+1−0

@@ -128,6 +128,7 @@ obj-$(CONFIG_GPIO_RDA) += gpio-rda.o · 127 unmodified lines
128	obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o	128	obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
129	obj-$(CONFIG_GPIO_REALTEK_OTTO) += gpio-realtek-otto.o	129	obj-$(CONFIG_GPIO_REALTEK_OTTO) += gpio-realtek-otto.o
130	obj-$(CONFIG_GPIO_REG) += gpio-reg.o	130	obj-$(CONFIG_GPIO_REG) += gpio-reg.o
		131	obj-$(CONFIG_GPIO_ROCKCHIP) += gpio-rockchip.o
131	obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o	132	obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o
132	obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) += gpio-sama5d2-piobu.o	133	obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) += gpio-sama5d2-piobu.o
133	obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o	134	obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o

drivers/gpio/gpio-104-dio-48e.c+2−2

@@ -336,8 +336,8 @@ static irqreturn_t dio48e_irq_handler(int irq, void *dev_id) · 335 unmodified lines
336	unsigned long gpio;	336	unsigned long gpio;
337		337
338	for_each_set_bit(gpio, &irq_mask, 2)	338	for_each_set_bit(gpio, &irq_mask, 2)
339	generic_handle_irq(irq_find_mapping(chip->irq.domain,	339	generic_handle_domain_irq(chip->irq.domain,
340	19 + gpio*24));	340	19 + gpio*24);
341		341
342	raw_spin_lock(&dio48egpio->lock);	342	raw_spin_lock(&dio48egpio->lock);
343		343

drivers/gpio/gpio-104-idi-48.c+2−2

@@ -223,8 +223,8 @@ static irqreturn_t idi_48_irq_handler(int irq, void *dev_id) · 222 unmodified lines
223	for_each_set_bit(bit_num, &irq_mask, 8) {	223	for_each_set_bit(bit_num, &irq_mask, 8) {
224	gpio = bit_num + boundary * 8;	224	gpio = bit_num + boundary * 8;
225		225
226	generic_handle_irq(irq_find_mapping(chip->irq.domain,	226	generic_handle_domain_irq(chip->irq.domain,
227	gpio));	227	gpio);
228	}	228	}
229	}	229	}
230		230

drivers/gpio/gpio-104-idio-16.c+1−1

@@ -208,7 +208,7 @@ static irqreturn_t idio_16_irq_handler(int irq, void *dev_id) · 207 unmodified lines
208	int gpio;	208	int gpio;
209		209
210	for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)	210	for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
211	generic_handle_irq(irq_find_mapping(chip->irq.domain, gpio));	211	generic_handle_domain_irq(chip->irq.domain, gpio);
212		212
213	raw_spin_lock(&idio16gpio->lock);	213	raw_spin_lock(&idio16gpio->lock);
214		214

drivers/gpio/gpio-altera.c+5−6

@@ -201,9 +201,8 @@ static void altera_gpio_irq_edge_handler(struct irq_desc *desc) · 200 unmodified lines
201	(readl(mm_gc->regs + ALTERA_GPIO_EDGE_CAP) &	201	(readl(mm_gc->regs + ALTERA_GPIO_EDGE_CAP) &
202	readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK)))) {	202	readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK)))) {
203	writel(status, mm_gc->regs + ALTERA_GPIO_EDGE_CAP);	203	writel(status, mm_gc->regs + ALTERA_GPIO_EDGE_CAP);
204	for_each_set_bit(i, &status, mm_gc->gc.ngpio) {	204	for_each_set_bit(i, &status, mm_gc->gc.ngpio)
205	generic_handle_irq(irq_find_mapping(irqdomain, i));	205	generic_handle_domain_irq(irqdomain, i);
206	}
207	}	206	}
208		207
209	chained_irq_exit(chip, desc);	208	chained_irq_exit(chip, desc);
@@ -228,9 +227,9 @@ static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc) · 18 unmodified lines
228	status = readl(mm_gc->regs + ALTERA_GPIO_DATA);	227	status = readl(mm_gc->regs + ALTERA_GPIO_DATA);
229	status &= readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);	228	status &= readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
230		229
231	for_each_set_bit(i, &status, mm_gc->gc.ngpio) {	230	for_each_set_bit(i, &status, mm_gc->gc.ngpio)
232	generic_handle_irq(irq_find_mapping(irqdomain, i));	231	generic_handle_domain_irq(irqdomain, i);
233	}	232
234	chained_irq_exit(chip, desc);	233	chained_irq_exit(chip, desc);
235	}	234	}
236		235

drivers/gpio/gpio-aspeed-sgpio.c+3−6

 	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 	struct irq_chip *ic = irq_desc_get_chip(desc);
 	struct aspeed_sgpio *data = gpiochip_get_data(gc);
-	unsigned int i, p, girq;
+	unsigned int i, p;
 	unsigned long reg;
 	chained_irq_enter(ic, desc);
 		reg = ioread32(bank_reg(data, bank, reg_irq_status));
-		for_each_set_bit(p, &reg, 32) {
+		for_each_set_bit(p, &reg, 32)
-			girq = irq_find_mapping(gc->irq.domain, i * 32 + p);
+			generic_handle_domain_irq(gc->irq.domain, i * 32 + p);
-			generic_handle_irq(girq);
-		}
 	}
 	chained_irq_exit(ic, desc);

drivers/gpio/gpio-aspeed.c+3−6

 	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 	struct irq_chip *ic = irq_desc_get_chip(desc);
 	struct aspeed_gpio *data = gpiochip_get_data(gc);
-	unsigned int i, p, girq, banks;
+	unsigned int i, p, banks;
 	unsigned long reg;
 	struct aspeed_gpio *gpio = gpiochip_get_data(gc);
 		reg = ioread32(bank_reg(data, bank, reg_irq_status));
-		for_each_set_bit(p, &reg, 32) {
+		for_each_set_bit(p, &reg, 32)
-			girq = irq_find_mapping(gc->irq.domain, i * 32 + p);
+			generic_handle_domain_irq(gc->irq.domain, i * 32 + p);
-			generic_handle_irq(girq);
-		}
 	}
 	chained_irq_exit(ic, desc);

drivers/gpio/gpio-ath79.c+2−5

 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
-	if (pending) {
+	for_each_set_bit(irq, &pending, gc->ngpio)
-		for_each_set_bit(irq, &pending, gc->ngpio)
+		generic_handle_domain_irq(gc->irq.domain, irq);
-			generic_handle_irq(
-				irq_linear_revmap(gc->irq.domain, irq));
-	}
 	chained_irq_exit(irqchip, desc);
 }

drivers/gpio/gpio-bcm-kona.c+2−4

 		    (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
 		for_each_set_bit(bit, &sta, 32) {
 			int hwirq = GPIO_PER_BANK * bank_id + bit;
-			int child_irq =
-				irq_find_mapping(bank->kona_gpio->irq_domain,
-						 hwirq);
 			/*
 			 * Clear interrupt before handler is called so we don't
 			 * miss any interrupt occurred during executing them.
 			writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
 			       BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
 			/* Invoke interrupt handler */
-			generic_handle_irq(child_irq);
+			generic_handle_domain_irq(bank->kona_gpio->irq_domain,
+						  hwirq);
 		}
 	}

drivers/gpio/gpio-brcmstb.c+2−3

 	unsigned long status;
 	while ((status = brcmstb_gpio_get_active_irqs(bank))) {
-		unsigned int irq, offset;
+		unsigned int offset;
 		for_each_set_bit(offset, &status, 32) {
 			if (offset >= bank->width)
 				dev_warn(&priv->pdev->dev,
 					 "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
 					 bank->id, offset);
-			irq = irq_linear_revmap(domain, hwbase + offset);
+			generic_handle_domain_irq(domain, hwbase + offset);
-			generic_handle_irq(irq);
 		}
 	}
 }

drivers/gpio/gpio-cadence.c+1−1

@@ -133,7 +133,7 @@ static void cdns_gpio_irq_handler(struct irq_desc *desc) · 132 unmodified lines
133	~ioread32(cgpio->regs + CDNS_GPIO_IRQ_MASK);	133	~ioread32(cgpio->regs + CDNS_GPIO_IRQ_MASK);
134		134
135	for_each_set_bit(hwirq, &status, chip->ngpio)	135	for_each_set_bit(hwirq, &status, chip->ngpio)
136	generic_handle_irq(irq_find_mapping(chip->irq.domain, hwirq));	136	generic_handle_domain_irq(chip->irq.domain, hwirq);
137		137
138	chained_irq_exit(irqchip, desc);	138	chained_irq_exit(irqchip, desc);
139	}	139	}

drivers/gpio/gpio-davinci.c+1−2

@@ -369,8 +369,7 @@ static void gpio_irq_handler(struct irq_desc *desc) · 368 unmodified lines
369	*/	369	*/
370	hw_irq = (bank_num / 2) * 32 + bit;	370	hw_irq = (bank_num / 2) * 32 + bit;
371		371
372	generic_handle_irq(	372	generic_handle_domain_irq(d->irq_domain, hw_irq);
373	irq_find_mapping(d->irq_domain, hw_irq));
374	}	373	}
375	}	374	}
376	chained_irq_exit(irq_desc_get_chip(desc), desc);	375	chained_irq_exit(irq_desc_get_chip(desc), desc);

drivers/gpio/gpio-dln2.c+9−13

 static void dln2_gpio_event(struct platform_device *pdev, u16 echo,
 			    const void *data, int len)
 {
-	int pin, irq;
+	int pin, ret;
 	const struct {
 		__le16 count;
 		return;
 	}
-	irq = irq_find_mapping(dln2->gpio.irq.domain, pin);
-	if (!irq) {
-		dev_err(dln2->gpio.parent, "pin %d not mapped to IRQ\n", pin);
-		return;
-	}
 	switch (dln2->irq_type[pin]) {
 	case DLN2_GPIO_EVENT_CHANGE_RISING:
-		if (event->value)
+		if (!event->value)
-			generic_handle_irq(irq);
+			return;
 		break;
 	case DLN2_GPIO_EVENT_CHANGE_FALLING:
-		if (!event->value)
+		if (event->value)
-			generic_handle_irq(irq);
+			return;
 		break;
-	default:
-		generic_handle_irq(irq);
 	}
+	ret = generic_handle_domain_irq(dln2->gpio.irq.domain, pin);
+	if (unlikely(ret))
+		dev_err(dln2->gpio.parent, "pin %d not mapped to IRQ\n", pin);
 }
 static int dln2_gpio_probe(struct platform_device *pdev)

drivers/gpio/gpio-em.c+1−1

@@ -173,7 +173,7 @@ static irqreturn_t em_gio_irq_handler(int irq, void *dev_id) · 172 unmodified lines
173	while ((pending = em_gio_read(p, GIO_MST))) {	173	while ((pending = em_gio_read(p, GIO_MST))) {
174	offset = __ffs(pending);	174	offset = __ffs(pending);
175	em_gio_write(p, GIO_IIR, BIT(offset));	175	em_gio_write(p, GIO_IIR, BIT(offset));
176	generic_handle_irq(irq_find_mapping(p->irq_domain, offset));	176	generic_handle_domain_irq(p->irq_domain, offset);
177	irqs_handled++;	177	irqs_handled++;
178	}	178	}
179		179

drivers/gpio/gpio-ep93xx.c+4−4

@@ -128,13 +128,13 @@ static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) · 127 unmodified lines
128	*/	128	*/
129	stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);	129	stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
130	for_each_set_bit(offset, &stat, 8)	130	for_each_set_bit(offset, &stat, 8)
131	generic_handle_irq(irq_find_mapping(epg->gc[0].gc.irq.domain,	131	generic_handle_domain_irq(epg->gc[0].gc.irq.domain,
132	offset));	132	offset);
133		133
134	stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);	134	stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
135	for_each_set_bit(offset, &stat, 8)	135	for_each_set_bit(offset, &stat, 8)
136	generic_handle_irq(irq_find_mapping(epg->gc[1].gc.irq.domain,	136	generic_handle_domain_irq(epg->gc[1].gc.irq.domain,
137	offset));	137	offset);
138		138
139	chained_irq_exit(irqchip, desc);	139	chained_irq_exit(irqchip, desc);
140	}	140	}

drivers/gpio/gpio-ftgpio010.c+1−2

@@ -149,8 +149,7 @@ static void ftgpio_gpio_irq_handler(struct irq_desc *desc) · 148 unmodified lines
149	stat = readl(g->base + GPIO_INT_STAT_RAW);	149	stat = readl(g->base + GPIO_INT_STAT_RAW);
150	if (stat)	150	if (stat)
151	for_each_set_bit(offset, &stat, gc->ngpio)	151	for_each_set_bit(offset, &stat, gc->ngpio)
152	generic_handle_irq(irq_find_mapping(gc->irq.domain,	152	generic_handle_domain_irq(gc->irq.domain, offset);
153	offset));
154		153
155	chained_irq_exit(irqchip, desc);	154	chained_irq_exit(irqchip, desc);
156	}	155	}

drivers/gpio/gpio-hisi.c+2−2

@@ -186,8 +186,8 @@ static void hisi_gpio_irq_handler(struct irq_desc *desc) · 185 unmodified lines
186		186
187	chained_irq_enter(irq_c, desc);	187	chained_irq_enter(irq_c, desc);
188	for_each_set_bit(hwirq, &irq_msk, HISI_GPIO_LINE_NUM_MAX)	188	for_each_set_bit(hwirq, &irq_msk, HISI_GPIO_LINE_NUM_MAX)
189	generic_handle_irq(irq_find_mapping(hisi_gpio->chip.irq.domain,	189	generic_handle_domain_irq(hisi_gpio->chip.irq.domain,
190	hwirq));	190	hwirq);
191	chained_irq_exit(irq_c, desc);	191	chained_irq_exit(irq_c, desc);
192	}	192	}
193		193

drivers/gpio/gpio-hlwd.c+2−5

@@ -97,11 +97,8 @@ static void hlwd_gpio_irqhandler(struct irq_desc *desc) · 96 unmodified lines
97		97
98	chained_irq_enter(chip, desc);	98	chained_irq_enter(chip, desc);
99		99
100	for_each_set_bit(hwirq, &pending, 32) {	100	for_each_set_bit(hwirq, &pending, 32)
101	int irq = irq_find_mapping(hlwd->gpioc.irq.domain, hwirq);	101	generic_handle_domain_irq(hlwd->gpioc.irq.domain, hwirq);
102
103	generic_handle_irq(irq);
104	}
105		102
106	chained_irq_exit(chip, desc);	103	chained_irq_exit(chip, desc);
107	}	104	}

drivers/gpio/gpio-merrifield.c+2−6

 		/* Only interrupts that are enabled */
 		pending &= enabled;
-		for_each_set_bit(gpio, &pending, 32) {
+		for_each_set_bit(gpio, &pending, 32)
-			unsigned int irq;
+			generic_handle_domain_irq(gc->irq.domain, base + gpio);
-			irq = irq_find_mapping(gc->irq.domain, base + gpio);
-			generic_handle_irq(irq);
-		}
 	}
 	chained_irq_exit(irqchip, desc);

drivers/gpio/gpio-mpc8xxx.c+1−1

@@ -120,7 +120,7 @@ static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data) · 119 unmodified lines
120	mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)	120	mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
121	& gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);	121	& gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
122	for_each_set_bit(i, &mask, 32)	122	for_each_set_bit(i, &mask, 32)
123	generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 31 - i));	123	generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i);
124		124
125	return IRQ_HANDLED;	125	return IRQ_HANDLED;
126	}	126	}

drivers/gpio/gpio-mt7621.c+1−3

@@ -95,9 +95,7 @@ mediatek_gpio_irq_handler(int irq, void *data) · 94 unmodified lines
95	pending = mtk_gpio_r32(rg, GPIO_REG_STAT);	95	pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
96		96
97	for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {	97	for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
98	u32 map = irq_find_mapping(gc->irq.domain, bit);	98	generic_handle_domain_irq(gc->irq.domain, bit);
99
100	generic_handle_irq(map);
101	mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));	99	mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
102	ret \|= IRQ_HANDLED;	100	ret \|= IRQ_HANDLED;
103	}	101	}

drivers/gpio/gpio-mxc.c+1−1

@@ -241,7 +241,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) · 240 unmodified lines
241	if (port->both_edges & (1 << irqoffset))	241	if (port->both_edges & (1 << irqoffset))
242	mxc_flip_edge(port, irqoffset);	242	mxc_flip_edge(port, irqoffset);
243		243
244	generic_handle_irq(irq_find_mapping(port->domain, irqoffset));	244	generic_handle_domain_irq(port->domain, irqoffset);
245		245
246	irq_stat &= ~(1 << irqoffset);	246	irq_stat &= ~(1 << irqoffset);
247	}	247	}

drivers/gpio/gpio-mxs.c+1−1

@@ -157,7 +157,7 @@ static void mxs_gpio_irq_handler(struct irq_desc *desc) · 156 unmodified lines
157	if (port->both_edges & (1 << irqoffset))	157	if (port->both_edges & (1 << irqoffset))
158	mxs_flip_edge(port, irqoffset);	158	mxs_flip_edge(port, irqoffset);
159		159
160	generic_handle_irq(irq_find_mapping(port->domain, irqoffset));	160	generic_handle_domain_irq(port->domain, irqoffset);
161	irq_stat &= ~(1 << irqoffset);	161	irq_stat &= ~(1 << irqoffset);
162	}	162	}
163	}	163	}

drivers/gpio/gpio-omap.c+1−2

@@ -611,8 +611,7 @@ static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank) · 610 unmodified lines
611		611
612	raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);	612	raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
613		613
614	generic_handle_irq(irq_find_mapping(bank->chip.irq.domain,	614	generic_handle_domain_irq(bank->chip.irq.domain, bit);
615	bit));
616		615
617	raw_spin_unlock_irqrestore(&bank->wa_lock,	616	raw_spin_unlock_irqrestore(&bank->wa_lock,
618	wa_lock_flags);	617	wa_lock_flags);

drivers/gpio/gpio-pci-idio-16.c+1−1

@@ -260,7 +260,7 @@ static irqreturn_t idio_16_irq_handler(int irq, void *dev_id) · 259 unmodified lines
260	return IRQ_NONE;	260	return IRQ_NONE;
261		261
262	for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)	262	for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
263	generic_handle_irq(irq_find_mapping(chip->irq.domain, gpio));	263	generic_handle_domain_irq(chip->irq.domain, gpio);
264		264
265	raw_spin_lock(&idio16gpio->lock);	265	raw_spin_lock(&idio16gpio->lock);
266		266

drivers/gpio/gpio-pcie-idio-24.c+1−2

@@ -468,8 +468,7 @@ static irqreturn_t idio_24_irq_handler(int irq, void *dev_id) · 467 unmodified lines
468	irq_mask = idio24gpio->irq_mask & irq_status;	468	irq_mask = idio24gpio->irq_mask & irq_status;
469		469
470	for_each_set_bit(gpio, &irq_mask, chip->ngpio - 24)	470	for_each_set_bit(gpio, &irq_mask, chip->ngpio - 24)
471	generic_handle_irq(irq_find_mapping(chip->irq.domain,	471	generic_handle_domain_irq(chip->irq.domain, gpio + 24);
472	gpio + 24));
473		472
474	raw_spin_lock(&idio24gpio->lock);	473	raw_spin_lock(&idio24gpio->lock);
475		474

drivers/gpio/gpio-pl061.c+2−2

@@ -223,8 +223,8 @@ static void pl061_irq_handler(struct irq_desc *desc) · 222 unmodified lines
223	pending = readb(pl061->base + GPIOMIS);	223	pending = readb(pl061->base + GPIOMIS);
224	if (pending) {	224	if (pending) {
225	for_each_set_bit(offset, &pending, PL061_GPIO_NR)	225	for_each_set_bit(offset, &pending, PL061_GPIO_NR)
226	generic_handle_irq(irq_find_mapping(gc->irq.domain,	226	generic_handle_domain_irq(gc->irq.domain,
227	offset));	227	offset);
228	}	228	}
229		229
230	chained_irq_exit(irqchip, desc);	230	chained_irq_exit(irqchip, desc);

drivers/gpio/gpio-pxa.c+4−5

 			for_each_set_bit(n, &gedr, BITS_PER_LONG) {
 				loop = 1;
-				generic_handle_irq(
+				generic_handle_domain_irq(pchip->irqdomain,
-					irq_find_mapping(pchip->irqdomain,
+							  gpio + n);
-							 gpio + n));
 			}
 		}
 		handled += loop;
 	struct pxa_gpio_chip *pchip = d;
 	if (in_irq == pchip->irq0) {
-		generic_handle_irq(irq_find_mapping(pchip->irqdomain, 0));
+		generic_handle_domain_irq(pchip->irqdomain, 0);
 	} else if (in_irq == pchip->irq1) {
-		generic_handle_irq(irq_find_mapping(pchip->irqdomain, 1));
+		generic_handle_domain_irq(pchip->irqdomain, 1);
 	} else {
 		pr_err("%s() unknown irq %d\n", __func__, in_irq);
 		return IRQ_NONE;

drivers/gpio/gpio-rcar.c+2−2

@@ -213,8 +213,8 @@ static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id) · 212 unmodified lines
213	gpio_rcar_read(p, INTMSK))) {	213	gpio_rcar_read(p, INTMSK))) {
214	offset = __ffs(pending);	214	offset = __ffs(pending);
215	gpio_rcar_write(p, INTCLR, BIT(offset));	215	gpio_rcar_write(p, INTCLR, BIT(offset));
216	generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,	216	generic_handle_domain_irq(p->gpio_chip.irq.domain,
217	offset));	217	offset);
218	irqs_handled++;	218	irqs_handled++;
219	}	219	}
220		220

drivers/gpio/gpio-rda.c+3−5

 	struct irq_chip *ic = irq_desc_get_chip(desc);
 	struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
 	unsigned long status;
-	u32 n, girq;
+	u32 n;
 	chained_irq_enter(ic, desc);
 	/* Only lower 8 bits are capable of generating interrupts */
 	status &= RDA_GPIO_IRQ_MASK;
-	for_each_set_bit(n, &status, RDA_GPIO_BANK_NR) {
+	for_each_set_bit(n, &status, RDA_GPIO_BANK_NR)
-		girq = irq_find_mapping(chip->irq.domain, n);
+		generic_handle_domain_irq(chip->irq.domain, n);
-		generic_handle_irq(girq);
-	}
 	chained_irq_exit(ic, desc);
 }

drivers/gpio/gpio-realtek-otto.c+2−5

 	struct irq_chip *irq_chip = irq_desc_get_chip(desc);
 	unsigned int lines_done;
 	unsigned int port_pin_count;
-	unsigned int irq;
 	unsigned long status;
 	int offset;
 	for (lines_done = 0; lines_done < gc->ngpio; lines_done += 8) {
 		status = realtek_gpio_read_isr(ctrl, lines_done / 8);
 		port_pin_count = min(gc->ngpio - lines_done, 8U);
-		for_each_set_bit(offset, &status, port_pin_count) {
+		for_each_set_bit(offset, &status, port_pin_count)
-			irq = irq_find_mapping(gc->irq.domain, offset);
+			generic_handle_domain_irq(gc->irq.domain, offset);
-			generic_handle_irq(irq);
-		}
 	}
 	chained_irq_exit(irq_chip, desc);

drivers/gpio/gpio-rockchip.c+771−0

@@ -0,0 +1,771 @@
	1	// SPDX-License-Identifier: GPL-2.0-only
	2	/*
	3	* Copyright (c) 2013 MundoReader S.L.
	4	* Author: Heiko Stuebner <heiko@sntech.de>
	5	*
	6	* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
	7	*/
	8
	9	#include <linux/bitops.h>
	10	#include <linux/clk.h>
	11	#include <linux/device.h>
	12	#include <linux/err.h>
	13	#include <linux/gpio/driver.h>
	14	#include <linux/init.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/io.h>
	17	#include <linux/module.h>
	18	#include <linux/of.h>
	19	#include <linux/of_address.h>
	20	#include <linux/of_device.h>
	21	#include <linux/of_irq.h>
	22	#include <linux/regmap.h>
	23
	24	#include "../pinctrl/core.h"
	25	#include "../pinctrl/pinctrl-rockchip.h"
	26
	27	#define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */
	28	#define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */
	29
	30	static const struct rockchip_gpio_regs gpio_regs_v1 = {
	31	.port_dr = 0x00,
	32	.port_ddr = 0x04,
	33	.int_en = 0x30,
	34	.int_mask = 0x34,
	35	.int_type = 0x38,
	36	.int_polarity = 0x3c,
	37	.int_status = 0x40,
	38	.int_rawstatus = 0x44,
	39	.debounce = 0x48,
	40	.port_eoi = 0x4c,
	41	.ext_port = 0x50,
	42	};
	43
	44	static const struct rockchip_gpio_regs gpio_regs_v2 = {
	45	.port_dr = 0x00,
	46	.port_ddr = 0x08,
	47	.int_en = 0x10,
	48	.int_mask = 0x18,
	49	.int_type = 0x20,
	50	.int_polarity = 0x28,
	51	.int_bothedge = 0x30,
	52	.int_status = 0x50,
	53	.int_rawstatus = 0x58,
	54	.debounce = 0x38,
	55	.dbclk_div_en = 0x40,
	56	.dbclk_div_con = 0x48,
	57	.port_eoi = 0x60,
	58	.ext_port = 0x70,
	59	.version_id = 0x78,
	60	};
	61
	62	static inline void gpio_writel_v2(u32 val, void __iomem *reg)
	63	{
	64	writel((val & 0xffff) \| 0xffff0000, reg);
	65	writel((val >> 16) \| 0xffff0000, reg + 0x4);
	66	}
	67
	68	static inline u32 gpio_readl_v2(void __iomem *reg)
	69	{
	70	return readl(reg + 0x4) << 16 \| readl(reg);
	71	}
	72
	73	static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank,
	74	u32 value, unsigned int offset)
	75	{
	76	void __iomem *reg = bank->reg_base + offset;
	77
	78	if (bank->gpio_type == GPIO_TYPE_V2)
	79	gpio_writel_v2(value, reg);
	80	else
	81	writel(value, reg);
	82	}
	83
	84	static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank,
	85	unsigned int offset)
	86	{
	87	void __iomem *reg = bank->reg_base + offset;
	88	u32 value;
	89
	90	if (bank->gpio_type == GPIO_TYPE_V2)
	91	value = gpio_readl_v2(reg);
	92	else
	93	value = readl(reg);
	94
	95	return value;
	96	}
	97
	98	static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank,
	99	u32 bit, u32 value,
	100	unsigned int offset)
	101	{
	102	void __iomem *reg = bank->reg_base + offset;
	103	u32 data;
	104
	105	if (bank->gpio_type == GPIO_TYPE_V2) {
	106	if (value)
	107	data = BIT(bit % 16) \| BIT(bit % 16 + 16);
	108	else
	109	data = BIT(bit % 16 + 16);
	110	writel(data, bit >= 16 ? reg + 0x4 : reg);
	111	} else {
	112	data = readl(reg);
	113	data &= ~BIT(bit);
	114	if (value)
	115	data \|= BIT(bit);
	116	writel(data, reg);
	117	}
	118	}
	119
	120	static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank,
	121	u32 bit, unsigned int offset)
	122	{
	123	void __iomem *reg = bank->reg_base + offset;
	124	u32 data;
	125
	126	if (bank->gpio_type == GPIO_TYPE_V2) {
	127	data = readl(bit >= 16 ? reg + 0x4 : reg);
	128	data >>= bit % 16;
	129	} else {
	130	data = readl(reg);
	131	data >>= bit;
	132	}
	133
	134	return data & (0x1);
	135	}
	136
	137	static int rockchip_gpio_get_direction(struct gpio_chip *chip,
	138	unsigned int offset)
	139	{
	140	struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
	141	u32 data;
	142
	143	data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
	144	if (data & BIT(offset))
	145	return GPIO_LINE_DIRECTION_OUT;
	146
	147	return GPIO_LINE_DIRECTION_IN;
	148	}
	149
	150	static int rockchip_gpio_set_direction(struct gpio_chip *chip,
	151	unsigned int offset, bool input)
	152	{
	153	struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
	154	unsigned long flags;
	155	u32 data = input ? 0 : 1;
	156
	157	raw_spin_lock_irqsave(&bank->slock, flags);
	158	rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
	159	raw_spin_unlock_irqrestore(&bank->slock, flags);
	160
	161	return 0;
	162	}
	163
	164	static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset,
	165	int value)
	166	{
	167	struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
	168	unsigned long flags;
	169
	170	raw_spin_lock_irqsave(&bank->slock, flags);
	171	rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr);
	172	raw_spin_unlock_irqrestore(&bank->slock, flags);
	173	}
	174
	175	static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset)
	176	{
	177	struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
	178	u32 data;
	179
	180	data = readl(bank->reg_base + bank->gpio_regs->ext_port);
	181	data >>= offset;
	182	data &= 1;
	183
	184	return data;
	185	}
	186
	187	static int rockchip_gpio_set_debounce(struct gpio_chip *gc,
	188	unsigned int offset,
	189	unsigned int debounce)
	190	{
	191	struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
	192	const struct rockchip_gpio_regs *reg = bank->gpio_regs;
	193	unsigned long flags, div_reg, freq, max_debounce;
	194	bool div_debounce_support;
	195	unsigned int cur_div_reg;
	196	u64 div;
	197
	198	if (!IS_ERR(bank->db_clk)) {
	199	div_debounce_support = true;
	200	freq = clk_get_rate(bank->db_clk);
	201	max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq;
	202	if (debounce > max_debounce)
	203	return -EINVAL;
	204
	205	div = debounce * freq;
	206	div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1;
	207	} else {
	208	div_debounce_support = false;
	209	}
	210
	211	raw_spin_lock_irqsave(&bank->slock, flags);
	212
	213	/* Only the v1 needs to configure div_en and div_con for dbclk */
	214	if (debounce) {
	215	if (div_debounce_support) {
	216	/* Configure the max debounce from consumers */
	217	cur_div_reg = readl(bank->reg_base +
	218	reg->dbclk_div_con);
	219	if (cur_div_reg < div_reg)
	220	writel(div_reg, bank->reg_base +
	221	reg->dbclk_div_con);
	222	rockchip_gpio_writel_bit(bank, offset, 1,
	223	reg->dbclk_div_en);
	224	}
	225
	226	rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce);
	227	} else {
	228	if (div_debounce_support)
	229	rockchip_gpio_writel_bit(bank, offset, 0,
	230	reg->dbclk_div_en);
	231
	232	rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce);
	233	}
	234
	235	raw_spin_unlock_irqrestore(&bank->slock, flags);
	236
	237	/* Enable or disable dbclk at last */
	238	if (div_debounce_support) {
	239	if (debounce)
	240	clk_prepare_enable(bank->db_clk);
	241	else
	242	clk_disable_unprepare(bank->db_clk);
	243	}
	244
	245	return 0;
	246	}
	247
	248	static int rockchip_gpio_direction_input(struct gpio_chip *gc,
	249	unsigned int offset)
	250	{
	251	return rockchip_gpio_set_direction(gc, offset, true);
	252	}
	253
	254	static int rockchip_gpio_direction_output(struct gpio_chip *gc,
	255	unsigned int offset, int value)
	256	{
	257	rockchip_gpio_set(gc, offset, value);
	258
	259	return rockchip_gpio_set_direction(gc, offset, false);
	260	}
	261
	262	/*
	263	* gpiolib set_config callback function. The setting of the pin
	264	* mux function as 'gpio output' will be handled by the pinctrl subsystem
	265	* interface.
	266	*/
	267	static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
	268	unsigned long config)
	269	{
	270	enum pin_config_param param = pinconf_to_config_param(config);
	271
	272	switch (param) {
	273	case PIN_CONFIG_INPUT_DEBOUNCE:
	274	rockchip_gpio_set_debounce(gc, offset, true);
	275	/*
	276	* Rockchip's gpio could only support up to one period
	277	* of the debounce clock(pclk), which is far away from
	278	* satisftying the requirement, as pclk is usually near
	279	* 100MHz shared by all peripherals. So the fact is it
	280	* has crippled debounce capability could only be useful
	281	* to prevent any spurious glitches from waking up the system
	282	* if the gpio is conguired as wakeup interrupt source. Let's
	283	* still return -ENOTSUPP as before, to make sure the caller
	284	* of gpiod_set_debounce won't change its behaviour.
	285	*/
	286	return -ENOTSUPP;
	287	default:
	288	return -ENOTSUPP;
	289	}
	290	}
	291
	292	/*
	293	* gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
	294	* and a virtual IRQ, if not already present.
	295	*/
	296	static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
	297	{
	298	struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
	299	unsigned int virq;
	300
	301	if (!bank->domain)
	302	return -ENXIO;
	303
	304	virq = irq_create_mapping(bank->domain, offset);
	305
	306	return (virq) ? : -ENXIO;
	307	}
	308
	309	static const struct gpio_chip rockchip_gpiolib_chip = {
	310	.request = gpiochip_generic_request,
	311	.free = gpiochip_generic_free,
	312	.set = rockchip_gpio_set,
	313	.get = rockchip_gpio_get,
	314	.get_direction = rockchip_gpio_get_direction,
	315	.direction_input = rockchip_gpio_direction_input,
	316	.direction_output = rockchip_gpio_direction_output,
	317	.set_config = rockchip_gpio_set_config,
	318	.to_irq = rockchip_gpio_to_irq,
	319	.owner = THIS_MODULE,
	320	};
	321
	322	static void rockchip_irq_demux(struct irq_desc *desc)
	323	{
	324	struct irq_chip *chip = irq_desc_get_chip(desc);
	325	struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
	326	u32 pend;
	327
	328	dev_dbg(bank->dev, "got irq for bank %s\n", bank->name);
	329
	330	chained_irq_enter(chip, desc);
	331
	332	pend = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status);
	333
	334	while (pend) {
	335	unsigned int irq, virq;
	336
	337	irq = __ffs(pend);
	338	pend &= ~BIT(irq);
	339	virq = irq_find_mapping(bank->domain, irq);
	340
	341	if (!virq) {
	342	dev_err(bank->dev, "unmapped irq %d\n", irq);
	343	continue;
	344	}
	345
	346	dev_dbg(bank->dev, "handling irq %d\n", irq);
	347
	348	/*
	349	* Triggering IRQ on both rising and falling edge
	350	* needs manual intervention.
	351	*/
	352	if (bank->toggle_edge_mode & BIT(irq)) {
	353	u32 data, data_old, polarity;
	354	unsigned long flags;
	355
	356	data = readl_relaxed(bank->reg_base +
	357	bank->gpio_regs->ext_port);
	358	do {
	359	raw_spin_lock_irqsave(&bank->slock, flags);
	360
	361	polarity = readl_relaxed(bank->reg_base +
	362	bank->gpio_regs->int_polarity);
	363	if (data & BIT(irq))
	364	polarity &= ~BIT(irq);
	365	else
	366	polarity \|= BIT(irq);
	367	writel(polarity,
	368	bank->reg_base +
	369	bank->gpio_regs->int_polarity);
	370
	371	raw_spin_unlock_irqrestore(&bank->slock, flags);
	372
	373	data_old = data;
	374	data = readl_relaxed(bank->reg_base +
	375	bank->gpio_regs->ext_port);
	376	} while ((data & BIT(irq)) != (data_old & BIT(irq)));
	377	}
	378
	379	generic_handle_irq(virq);
	380	}
	381
	382	chained_irq_exit(chip, desc);
	383	}
	384
	385	static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
	386	{
	387	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	388	struct rockchip_pin_bank *bank = gc->private;
	389	u32 mask = BIT(d->hwirq);
	390	u32 polarity;
	391	u32 level;
	392	u32 data;
	393	unsigned long flags;
	394	int ret = 0;
	395
	396	raw_spin_lock_irqsave(&bank->slock, flags);
	397
	398	rockchip_gpio_writel_bit(bank, d->hwirq, 0,
	399	bank->gpio_regs->port_ddr);
	400
	401	raw_spin_unlock_irqrestore(&bank->slock, flags);
	402
	403	if (type & IRQ_TYPE_EDGE_BOTH)
	404	irq_set_handler_locked(d, handle_edge_irq);
	405	else
	406	irq_set_handler_locked(d, handle_level_irq);
	407
	408	raw_spin_lock_irqsave(&bank->slock, flags);
	409
	410	level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type);
	411	polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);
	412
	413	switch (type) {
	414	case IRQ_TYPE_EDGE_BOTH:
	415	if (bank->gpio_type == GPIO_TYPE_V2) {
	416	bank->toggle_edge_mode &= ~mask;
	417	rockchip_gpio_writel_bit(bank, d->hwirq, 1,
	418	bank->gpio_regs->int_bothedge);
	419	goto out;
	420	} else {
	421	bank->toggle_edge_mode \|= mask;
	422	level \|= mask;
	423
	424	/*
	425	* Determine gpio state. If 1 next interrupt should be
	426	* falling otherwise rising.
	427	*/
	428	data = readl(bank->reg_base + bank->gpio_regs->ext_port);
	429	if (data & mask)
	430	polarity &= ~mask;
	431	else
	432	polarity \|= mask;
	433	}
	434	break;
	435	case IRQ_TYPE_EDGE_RISING:
	436	bank->toggle_edge_mode &= ~mask;
	437	level \|= mask;
	438	polarity \|= mask;
	439	break;
	440	case IRQ_TYPE_EDGE_FALLING:
	441	bank->toggle_edge_mode &= ~mask;
	442	level \|= mask;
	443	polarity &= ~mask;
	444	break;
	445	case IRQ_TYPE_LEVEL_HIGH:
	446	bank->toggle_edge_mode &= ~mask;
	447	level &= ~mask;
	448	polarity \|= mask;
	449	break;
	450	case IRQ_TYPE_LEVEL_LOW:
	451	bank->toggle_edge_mode &= ~mask;
	452	level &= ~mask;
	453	polarity &= ~mask;
	454	break;
	455	default:
	456	ret = -EINVAL;
	457	goto out;
	458	}
	459
	460	rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type);
	461	rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity);
	462	out:
	463	raw_spin_unlock_irqrestore(&bank->slock, flags);
	464
	465	return ret;
	466	}
	467
	468	static void rockchip_irq_suspend(struct irq_data *d)
	469	{
	470	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	471	struct rockchip_pin_bank *bank = gc->private;
	472
	473	bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
	474	irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
	475	}
	476
	477	static void rockchip_irq_resume(struct irq_data *d)
	478	{
	479	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	480	struct rockchip_pin_bank *bank = gc->private;
	481
	482	irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
	483	}
	484
	485	static void rockchip_irq_enable(struct irq_data *d)
	486	{
	487	irq_gc_mask_clr_bit(d);
	488	}
	489
	490	static void rockchip_irq_disable(struct irq_data *d)
	491	{
	492	irq_gc_mask_set_bit(d);
	493	}
	494
	495	static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
	496	{
	497	unsigned int clr = IRQ_NOREQUEST \| IRQ_NOPROBE \| IRQ_NOAUTOEN;
	498	struct irq_chip_generic *gc;
	499	int ret;
	500
	501	bank->domain = irq_domain_add_linear(bank->of_node, 32,
	502	&irq_generic_chip_ops, NULL);
	503	if (!bank->domain) {
	504	dev_warn(bank->dev, "could not init irq domain for bank %s\n",
	505	bank->name);
	506	return -EINVAL;
	507	}
	508
	509	ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
	510	"rockchip_gpio_irq",
	511	handle_level_irq,
	512	clr, 0, 0);
	513	if (ret) {
	514	dev_err(bank->dev, "could not alloc generic chips for bank %s\n",
	515	bank->name);
	516	irq_domain_remove(bank->domain);
	517	return -EINVAL;
	518	}
	519
	520	gc = irq_get_domain_generic_chip(bank->domain, 0);
	521	if (bank->gpio_type == GPIO_TYPE_V2) {
	522	gc->reg_writel = gpio_writel_v2;
	523	gc->reg_readl = gpio_readl_v2;
	524	}
	525
	526	gc->reg_base = bank->reg_base;
	527	gc->private = bank;
	528	gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask;
	529	gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi;
	530	gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
	531	gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
	532	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
	533	gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
	534	gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
	535	gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
	536	gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
	537	gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
	538	gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
	539	gc->wake_enabled = IRQ_MSK(bank->nr_pins);
	540
	541	/*
	542	* Linux assumes that all interrupts start out disabled/masked.
	543	* Our driver only uses the concept of masked and always keeps
	544	* things enabled, so for us that's all masked and all enabled.
	545	*/
	546	rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask);
	547	rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi);
	548	rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en);
	549	gc->mask_cache = 0xffffffff;
	550
	551	irq_set_chained_handler_and_data(bank->irq,
	552	rockchip_irq_demux, bank);
	553
	554	return 0;
	555	}
	556
	557	static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank)
	558	{
	559	struct gpio_chip *gc;
	560	int ret;
	561
	562	bank->gpio_chip = rockchip_gpiolib_chip;
	563
	564	gc = &bank->gpio_chip;
	565	gc->base = bank->pin_base;
	566	gc->ngpio = bank->nr_pins;
	567	gc->label = bank->name;
	568	gc->parent = bank->dev;
	569	#ifdef CONFIG_OF_GPIO
	570	gc->of_node = of_node_get(bank->of_node);
	571	#endif
	572
	573	ret = gpiochip_add_data(gc, bank);
	574	if (ret) {
	575	dev_err(bank->dev, "failed to add gpiochip %s, %d\n",
	576	gc->label, ret);
	577	return ret;
	578	}
	579
	580	/*
	581	* For DeviceTree-supported systems, the gpio core checks the
	582	* pinctrl's device node for the "gpio-ranges" property.
	583	* If it is present, it takes care of adding the pin ranges
	584	* for the driver. In this case the driver can skip ahead.
	585	*
	586	* In order to remain compatible with older, existing DeviceTree
	587	* files which don't set the "gpio-ranges" property or systems that
	588	* utilize ACPI the driver has to call gpiochip_add_pin_range().
	589	*/
	590	if (!of_property_read_bool(bank->of_node, "gpio-ranges")) {
	591	struct device_node *pctlnp = of_get_parent(bank->of_node);
	592	struct pinctrl_dev *pctldev = NULL;
	593
	594	if (!pctlnp)
	595	return -ENODATA;
	596
	597	pctldev = of_pinctrl_get(pctlnp);
	598	if (!pctldev)
	599	return -ENODEV;
	600
	601	ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0,
	602	gc->base, gc->ngpio);
	603	if (ret) {
	604	dev_err(bank->dev, "Failed to add pin range\n");
	605	goto fail;
	606	}
	607	}
	608
	609	ret = rockchip_interrupts_register(bank);
	610	if (ret) {
	611	dev_err(bank->dev, "failed to register interrupt, %d\n", ret);
	612	goto fail;
	613	}
	614
	615	return 0;
	616
	617	fail:
	618	gpiochip_remove(&bank->gpio_chip);
	619
	620	return ret;
	621	}
	622
	623	static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
	624	{
	625	struct resource res;
	626	int id = 0;
	627
	628	if (of_address_to_resource(bank->of_node, 0, &res)) {
	629	dev_err(bank->dev, "cannot find IO resource for bank\n");
	630	return -ENOENT;
	631	}
	632
	633	bank->reg_base = devm_ioremap_resource(bank->dev, &res);
	634	if (IS_ERR(bank->reg_base))
	635	return PTR_ERR(bank->reg_base);
	636
	637	bank->irq = irq_of_parse_and_map(bank->of_node, 0);
	638	if (!bank->irq)
	639	return -EINVAL;
	640
	641	bank->clk = of_clk_get(bank->of_node, 0);
	642	if (IS_ERR(bank->clk))
	643	return PTR_ERR(bank->clk);
	644
	645	clk_prepare_enable(bank->clk);
	646	id = readl(bank->reg_base + gpio_regs_v2.version_id);
	647
	648	/* If not gpio v2, that is default to v1. */
	649	if (id == GPIO_TYPE_V2) {
	650	bank->gpio_regs = &gpio_regs_v2;
	651	bank->gpio_type = GPIO_TYPE_V2;
	652	bank->db_clk = of_clk_get(bank->of_node, 1);
	653	if (IS_ERR(bank->db_clk)) {
	654	dev_err(bank->dev, "cannot find debounce clk\n");
	655	clk_disable_unprepare(bank->clk);
	656	return -EINVAL;
	657	}
	658	} else {
	659	bank->gpio_regs = &gpio_regs_v1;
	660	bank->gpio_type = GPIO_TYPE_V1;
	661	}
	662
	663	return 0;
	664	}
	665
	666	static struct rockchip_pin_bank *
	667	rockchip_gpio_find_bank(struct pinctrl_dev *pctldev, int id)
	668	{
	669	struct rockchip_pinctrl *info;
	670	struct rockchip_pin_bank *bank;
	671	int i, found = 0;
	672
	673	info = pinctrl_dev_get_drvdata(pctldev);
	674	bank = info->ctrl->pin_banks;
	675	for (i = 0; i < info->ctrl->nr_banks; i++, bank++) {
	676	if (bank->bank_num == id) {
	677	found = 1;
	678	break;
	679	}
	680	}
	681
	682	return found ? bank : NULL;
	683	}
	684
	685	static int rockchip_gpio_probe(struct platform_device *pdev)
	686	{
	687	struct device *dev = &pdev->dev;
	688	struct device_node *np = dev->of_node;
	689	struct device_node *pctlnp = of_get_parent(np);
	690	struct pinctrl_dev *pctldev = NULL;
	691	struct rockchip_pin_bank *bank = NULL;
	692	static int gpio;
	693	int id, ret;
	694
	695	if (!np \|\| !pctlnp)
	696	return -ENODEV;
	697
	698	pctldev = of_pinctrl_get(pctlnp);
	699	if (!pctldev)
	700	return -EPROBE_DEFER;
	701
	702	id = of_alias_get_id(np, "gpio");
	703	if (id < 0)
	704	id = gpio++;
	705
	706	bank = rockchip_gpio_find_bank(pctldev, id);
	707	if (!bank)
	708	return -EINVAL;
	709
	710	bank->dev = dev;
	711	bank->of_node = np;
	712
	713	raw_spin_lock_init(&bank->slock);
	714
	715	ret = rockchip_get_bank_data(bank);
	716	if (ret)
	717	return ret;
	718
	719	ret = rockchip_gpiolib_register(bank);
	720	if (ret) {
	721	clk_disable_unprepare(bank->clk);
	722	return ret;
	723	}
	724
	725	platform_set_drvdata(pdev, bank);
	726	dev_info(dev, "probed %pOF\n", np);
	727
	728	return 0;
	729	}
	730
	731	static int rockchip_gpio_remove(struct platform_device *pdev)
	732	{
	733	struct rockchip_pin_bank *bank = platform_get_drvdata(pdev);
	734
	735	clk_disable_unprepare(bank->clk);
	736	gpiochip_remove(&bank->gpio_chip);
	737
	738	return 0;
	739	}
	740
	741	static const struct of_device_id rockchip_gpio_match[] = {
	742	{ .compatible = "rockchip,gpio-bank", },
	743	{ .compatible = "rockchip,rk3188-gpio-bank0" },
	744	{ },
	745	};
	746
	747	static struct platform_driver rockchip_gpio_driver = {
	748	.probe = rockchip_gpio_probe,
	749	.remove = rockchip_gpio_remove,
	750	.driver = {
	751	.name = "rockchip-gpio",
	752	.of_match_table = rockchip_gpio_match,
	753	},
	754	};
	755
	756	static int __init rockchip_gpio_init(void)
	757	{
	758	return platform_driver_register(&rockchip_gpio_driver);
	759	}
	760	postcore_initcall(rockchip_gpio_init);
	761
	762	static void __exit rockchip_gpio_exit(void)
	763	{
	764	platform_driver_unregister(&rockchip_gpio_driver);
	765	}
	766	module_exit(rockchip_gpio_exit);
	767
	768	MODULE_DESCRIPTION("Rockchip gpio driver");
	769	MODULE_ALIAS("platform:rockchip-gpio");
	770	MODULE_LICENSE("GPL v2");
	771	MODULE_DEVICE_TABLE(of, rockchip_gpio_match);

drivers/gpio/gpio-sch.c+1−1

@@ -259,7 +259,7 @@ static u32 sch_gpio_gpe_handler(acpi_handle gpe_device, u32 gpe, void *context) · 258 unmodified lines
259		259
260	pending = (resume_status << sch->resume_base) \| core_status;	260	pending = (resume_status << sch->resume_base) \| core_status;
261	for_each_set_bit(offset, &pending, sch->chip.ngpio)	261	for_each_set_bit(offset, &pending, sch->chip.ngpio)
262	generic_handle_irq(irq_find_mapping(gc->irq.domain, offset));	262	generic_handle_domain_irq(gc->irq.domain, offset);
263		263
264	/* Set returning value depending on whether we handled an interrupt */	264	/* Set returning value depending on whether we handled an interrupt */
265	ret = pending ? ACPI_INTERRUPT_HANDLED : ACPI_INTERRUPT_NOT_HANDLED;	265	ret = pending ? ACPI_INTERRUPT_HANDLED : ACPI_INTERRUPT_NOT_HANDLED;

drivers/gpio/gpio-sodaville.c+1−1

@@ -84,7 +84,7 @@ static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data) · 83 unmodified lines
84	return IRQ_NONE;	84	return IRQ_NONE;
85		85
86	for_each_set_bit(irq_bit, &irq_stat, 32)	86	for_each_set_bit(irq_bit, &irq_stat, 32)
87	generic_handle_irq(irq_find_mapping(sd->id, irq_bit));	87	generic_handle_domain_irq(sd->id, irq_bit);
88		88
89	return IRQ_HANDLED;	89	return IRQ_HANDLED;
90	}	90	}

drivers/gpio/gpio-sprd.c+4−8

 	struct gpio_chip *chip = irq_desc_get_handler_data(desc);
 	struct irq_chip *ic = irq_desc_get_chip(desc);
 	struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip);
-	u32 bank, n, girq;
+	u32 bank, n;
 	chained_irq_enter(ic, desc);
 		unsigned long reg = readl_relaxed(base + SPRD_GPIO_MIS) &
 			SPRD_GPIO_BANK_MASK;
-		for_each_set_bit(n, &reg, SPRD_GPIO_BANK_NR) {
+		for_each_set_bit(n, &reg, SPRD_GPIO_BANK_NR)
-			girq = irq_find_mapping(chip->irq.domain,
+			generic_handle_domain_irq(chip->irq.domain,
-						bank * SPRD_GPIO_BANK_NR + n);
+						  bank * SPRD_GPIO_BANK_NR + n);
-			generic_handle_irq(girq);
-		}
 	}
 	chained_irq_exit(ic, desc);
 }

drivers/gpio/gpio-tb10x.c+1−1

@@ -100,7 +100,7 @@ static irqreturn_t tb10x_gpio_irq_cascade(int irq, void *data) · 99 unmodified lines
100	int i;	100	int i;
101		101
102	for_each_set_bit(i, &bits, 32)	102	for_each_set_bit(i, &bits, 32)
103	generic_handle_irq(irq_find_mapping(tb10x_gpio->domain, i));	103	generic_handle_domain_irq(tb10x_gpio->domain, i);
104		104
105	return IRQ_HANDLED;	105	return IRQ_HANDLED;
106	}	106	}

drivers/gpio/gpio-tegra.c+4−5

 		lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
 		for_each_set_bit(pin, &sta, 8) {
+			int ret;
 			tegra_gpio_writel(tgi, 1 << pin,
 					  GPIO_INT_CLR(tgi, gpio));
 				chained_irq_exit(chip, desc);
 			}
-			irq = irq_find_mapping(domain, gpio + pin);
+			ret = generic_handle_domain_irq(domain, gpio + pin);
-			if (WARN_ON(irq == 0))
+			WARN_RATELIMIT(ret, "hwirq = %d", gpio + pin);
-				continue;
-			generic_handle_irq(irq);
 		}
 	}

drivers/gpio/gpio-tegra186.c+3−6

 	for (i = 0; i < gpio->soc->num_ports; i++) {
 		const struct tegra_gpio_port *port = &gpio->soc->ports[i];
-		unsigned int pin, irq;
+		unsigned int pin;
 		unsigned long value;
 		void __iomem *base;
 		value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
 		for_each_set_bit(pin, &value, port->pins) {
-			irq = irq_find_mapping(domain, offset + pin);
+			int ret = generic_handle_domain_irq(domain, offset + pin);
-			if (WARN_ON(irq == 0))
+			WARN_RATELIMIT(ret, "hwirq = %d", offset + pin);
-				continue;
-			generic_handle_irq(irq);
 		}
 skip:

drivers/gpio/gpio-tqmx86.c+4−6

 	struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
 	struct irq_chip *irq_chip = irq_desc_get_chip(desc);
 	unsigned long irq_bits;
-	int i = 0, child_irq;
+	int i = 0;
 	u8 irq_status;
 	chained_irq_enter(irq_chip, desc);
 	tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS);
 	irq_bits = irq_status;
-	for_each_set_bit(i, &irq_bits, TQMX86_NGPI) {
+	for_each_set_bit(i, &irq_bits, TQMX86_NGPI)
-		child_irq = irq_find_mapping(gpio->chip.irq.domain,
+		generic_handle_domain_irq(gpio->chip.irq.domain,
-					     i + TQMX86_NGPO);
+					  i + TQMX86_NGPO);
-		generic_handle_irq(child_irq);
-	}
 	chained_irq_exit(irq_chip, desc);
 }

drivers/gpio/gpio-vf610.c+1−1

@@ -149,7 +149,7 @@ static void vf610_gpio_irq_handler(struct irq_desc *desc) · 148 unmodified lines
149	for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {	149	for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
150	vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);	150	vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
151		151
152	generic_handle_irq(irq_find_mapping(port->gc.irq.domain, pin));	152	generic_handle_domain_irq(port->gc.irq.domain, pin);
153	}	153	}
154		154
155	chained_irq_exit(chip, desc);	155	chained_irq_exit(chip, desc);

drivers/gpio/gpio-ws16c48.c+2−2

@@ -339,8 +339,8 @@ static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id) · 338 unmodified lines
339	for_each_set_bit(port, &int_pending, 3) {	339	for_each_set_bit(port, &int_pending, 3) {
340	int_id = inb(ws16c48gpio->base + 8 + port);	340	int_id = inb(ws16c48gpio->base + 8 + port);
341	for_each_set_bit(gpio, &int_id, 8)	341	for_each_set_bit(gpio, &int_id, 8)
342	generic_handle_irq(irq_find_mapping(	342	generic_handle_domain_irq(chip->irq.domain,
343	chip->irq.domain, gpio + 8*port));	343	gpio + 8*port);
344	}	344	}
345		345
346	int_pending = inb(ws16c48gpio->base + 6) & 0x7;	346	int_pending = inb(ws16c48gpio->base + 6) & 0x7;

drivers/gpio/gpio-xgs-iproc.c+1−1

@@ -185,7 +185,7 @@ static irqreturn_t iproc_gpio_irq_handler(int irq, void *data) · 184 unmodified lines
185	int_bits = level \| event;	185	int_bits = level \| event;
186		186
187	for_each_set_bit(bit, &int_bits, gc->ngpio)	187	for_each_set_bit(bit, &int_bits, gc->ngpio)
188	generic_handle_irq(irq_linear_revmap(gc->irq.domain, bit));	188	generic_handle_domain_irq(gc->irq.domain, bit);
189	}	189	}
190		190
191	return int_bits ? IRQ_HANDLED : IRQ_NONE;	191	return int_bits ? IRQ_HANDLED : IRQ_NONE;

drivers/gpio/gpio-xilinx.c+1−1

@@ -538,7 +538,7 @@ static void xgpio_irqhandler(struct irq_desc *desc) · 537 unmodified lines
538		538
539	for_each_set_bit(bit, all, 64) {	539	for_each_set_bit(bit, all, 64) {
540	irq_offset = xgpio_from_bit(chip, bit);	540	irq_offset = xgpio_from_bit(chip, bit);
541	generic_handle_irq(irq_find_mapping(gc->irq.domain, irq_offset));	541	generic_handle_domain_irq(gc->irq.domain, irq_offset);
542	}	542	}
543		543
544	chained_irq_exit(irqchip, desc);	544	chained_irq_exit(irqchip, desc);

drivers/gpio/gpio-xlp.c+1−2

@@ -216,8 +216,7 @@ static void xlp_gpio_generic_handler(struct irq_desc *desc) · 215 unmodified lines
216	}	216	}
217		217
218	if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ))	218	if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ))
219	generic_handle_irq(irq_find_mapping(	219	generic_handle_domain_irq(priv->chip.irq.domain, gpio);
220	priv->chip.irq.domain, gpio));
221	}	220	}
222	chained_irq_exit(irqchip, desc);	221	chained_irq_exit(irqchip, desc);
223	}	222	}

drivers/gpio/gpio-zynq.c+2−6

 	if (!pending)
 		return;
-	for_each_set_bit(offset, &pending, 32) {
+	for_each_set_bit(offset, &pending, 32)
-		unsigned int gpio_irq;
+		generic_handle_domain_irq(irqdomain, offset + bank_offset);
-		gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
-		generic_handle_irq(gpio_irq);
-	}
 }
 /**

drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c+1−1

@@ -502,7 +502,7 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev, · 501 unmodified lines
502		502
503	} else if ((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) &&	503	} else if ((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) &&
504	adev->irq.virq[src_id]) {	504	adev->irq.virq[src_id]) {
505	generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));	505	generic_handle_domain_irq(adev->irq.domain, src_id);
506		506
507	} else if (!adev->irq.client[client_id].sources) {	507	} else if (!adev->irq.client[client_id].sources) {
508	DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",	508	DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",

drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c+4−11

 	while (interrupts) {
 		irq_hw_number_t hwirq = fls(interrupts) - 1;
-		unsigned int mapping;
 		int rc;
-		mapping = irq_find_mapping(dpu_mdss->irq_controller.domain,
+		rc = generic_handle_domain_irq(dpu_mdss->irq_controller.domain,
-					   hwirq);
+					       hwirq);
-		if (mapping == 0) {
-			DRM_ERROR("couldn't find irq mapping for %lu\n", hwirq);
-			break;
-		}
-		rc = generic_handle_irq(mapping);
 		if (rc < 0) {
-			DRM_ERROR("handle irq fail: irq=%lu mapping=%u rc=%d\n",
+			DRM_ERROR("handle irq fail: irq=%lu rc=%d\n",
-				  hwirq, mapping, rc);
+				  hwirq, rc);
 			break;
 		}

drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c+1−2

@@ -50,8 +50,7 @@ static irqreturn_t mdss_irq(int irq, void *arg) · 49 unmodified lines
50	while (intr) {	50	while (intr) {
51	irq_hw_number_t hwirq = fls(intr) - 1;	51	irq_hw_number_t hwirq = fls(intr) - 1;
52		52
53	generic_handle_irq(irq_find_mapping(	53	generic_handle_domain_irq(mdp5_mdss->irqcontroller.domain, hwirq);
54	mdp5_mdss->irqcontroller.domain, hwirq));
55	intr &= ~(1 << hwirq);	54	intr &= ~(1 << hwirq);
56	}	55	}
57		56

drivers/gpu/ipu-v3/ipu-common.c+4−7

 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
 {
 	unsigned long status;
-	int i, bit, irq;
+	int i, bit;
 	for (i = 0; i < num_regs; i++) {
 		status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
 		status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
-		for_each_set_bit(bit, &status, 32) {
+		for_each_set_bit(bit, &status, 32)
-			irq = irq_linear_revmap(ipu->domain,
+			generic_handle_domain_irq(ipu->domain,
-						regs[i] * 32 + bit);
+						  regs[i] * 32 + bit);
-			if (irq)
-				generic_handle_irq(irq);
-		}
 	}
 }

drivers/irqchip/irq-alpine-msi.c+2−4

 		goto err_priv;
 	}
-	priv->msi_map = kcalloc(BITS_TO_LONGS(priv->num_spis),
+	priv->msi_map = bitmap_zalloc(priv->num_spis, GFP_KERNEL);
-				sizeof(*priv->msi_map),
-				GFP_KERNEL);
 	if (!priv->msi_map) {
 		ret = -ENOMEM;
 		goto err_priv;
 	return 0;
 err_map:
-	kfree(priv->msi_map);
+	bitmap_free(priv->msi_map);
 err_priv:
 	kfree(priv);
 	return ret;

drivers/irqchip/irq-apple-aic.c+1−1

@@ -226,7 +226,7 @@ static void aic_irq_eoi(struct irq_data *d) · 225 unmodified lines
226	* Reading the interrupt reason automatically acknowledges and masks	226	* Reading the interrupt reason automatically acknowledges and masks
227	* the IRQ, so we just unmask it here if needed.	227	* the IRQ, so we just unmask it here if needed.
228	*/	228	*/
229	if (!irqd_irq_disabled(d) && !irqd_irq_masked(d))	229	if (!irqd_irq_masked(d))
230	aic_irq_unmask(d);	230	aic_irq_unmask(d);
231	}	231	}
232		232

drivers/irqchip/irq-gic-v2m.c+2−3

 	list_for_each_entry_safe(v2m, tmp, &v2m_nodes, entry) {
 		list_del(&v2m->entry);
-		kfree(v2m->bm);
+		bitmap_free(v2m->bm);
 		iounmap(v2m->base);
 		of_node_put(to_of_node(v2m->fwnode));
 		if (is_fwnode_irqchip(v2m->fwnode))
 			break;
 		}
 	}
-	v2m->bm = kcalloc(BITS_TO_LONGS(v2m->nr_spis), sizeof(long),
+	v2m->bm = bitmap_zalloc(v2m->nr_spis, GFP_KERNEL);
-			  GFP_KERNEL);
 	if (!v2m->bm) {
 		ret = -ENOMEM;
 		goto err_iounmap;

drivers/irqchip/irq-gic-v3-its.c+3−3

@@ -2140,7 +2140,7 @@ static unsigned long its_lpi_alloc(int nr_irqs, u32 base, int *nr_ids) · 2139 unmodified lines
2140	if (err)	2140	if (err)
2141	goto out;	2141	goto out;
2142		2142
2143	bitmap = kcalloc(BITS_TO_LONGS(nr_irqs), sizeof (long), GFP_ATOMIC);	2143	bitmap = bitmap_zalloc(nr_irqs, GFP_ATOMIC);
2144	if (!bitmap)	2144	if (!bitmap)
2145	goto out;	2145	goto out;
2146		2146
@@ -2156,7 +2156,7 @@ out: · 9 unmodified lines
2156	static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)	2156	static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)
2157	{	2157	{
2158	WARN_ON(free_lpi_range(base, nr_ids));	2158	WARN_ON(free_lpi_range(base, nr_ids));
2159	kfree(bitmap);	2159	bitmap_free(bitmap);
2160	}	2160	}
2161		2161
2162	static void gic_reset_prop_table(void *va)	2162	static void gic_reset_prop_table(void *va)
@@ -3387,7 +3387,7 @@ static struct its_device its_create_device(struct its_node its, u32 dev_id, · 1224 unmodified lines
3387	if (!dev \|\| !itt \|\| !col_map \|\| (!lpi_map && alloc_lpis)) {	3387	if (!dev \|\| !itt \|\| !col_map \|\| (!lpi_map && alloc_lpis)) {
3388	kfree(dev);	3388	kfree(dev);
3389	kfree(itt);	3389	kfree(itt);
3390	kfree(lpi_map);	3390	bitmap_free(lpi_map);
3391	kfree(col_map);	3391	kfree(col_map);
3392	return NULL;	3392	return NULL;
3393	}	3393	}

drivers/irqchip/irq-gic-v3-mbi.c+2−3

 		if (ret)
 			goto err_free_mbi;
-		mbi_ranges[n].bm = kcalloc(BITS_TO_LONGS(mbi_ranges[n].nr_spis),
+		mbi_ranges[n].bm = bitmap_zalloc(mbi_ranges[n].nr_spis, GFP_KERNEL);
-					   sizeof(long), GFP_KERNEL);
 		if (!mbi_ranges[n].bm) {
 			ret = -ENOMEM;
 			goto err_free_mbi;
 err_free_mbi:
 	if (mbi_ranges) {
 		for (n = 0; n < mbi_range_nr; n++)
-			kfree(mbi_ranges[n].bm);
+			bitmap_free(mbi_ranges[n].bm);
 		kfree(mbi_ranges);
 	}

drivers/irqchip/irq-gic-v3.c+72−12

 DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities);
 EXPORT_SYMBOL(gic_nonsecure_priorities);
+/*
+ * When the Non-secure world has access to group 0 interrupts (as a
+ * consequence of SCR_EL3.FIQ == 0), reading the ICC_RPR_EL1 register will
+ * return the Distributor's view of the interrupt priority.
+ *
+ * When GIC security is enabled (GICD_CTLR.DS == 0), the interrupt priority
+ * written by software is moved to the Non-secure range by the Distributor.
+ *
+ * If both are true (which is when gic_nonsecure_priorities gets enabled),
+ * we need to shift down the priority programmed by software to match it
+ * against the value returned by ICC_RPR_EL1.
+ */
+#define GICD_INT_RPR_PRI(priority)					\
+	({								\
+		u32 __priority = (priority);				\
+		if (static_branch_unlikely(&gic_nonsecure_priorities))	\
+			__priority = 0x80 | (__priority >> 1);		\
+									\
+		__priority;						\
+	})
 /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */
 static refcount_t *ppi_nmi_refs;
 	writeb_relaxed(prio, base + offset + index);
 }
-static u32 gic_get_ppi_index(struct irq_data *d)
+static u32 __gic_get_ppi_index(irq_hw_number_t hwirq)
 {
-	switch (get_intid_range(d)) {
+	switch (__get_intid_range(hwirq)) {
 	case PPI_RANGE:
-		return d->hwirq - 16;
+		return hwirq - 16;
 	case EPPI_RANGE:
-		return d->hwirq - EPPI_BASE_INTID + 16;
+		return hwirq - EPPI_BASE_INTID + 16;
 	default:
 		unreachable();
 	}
 }
+static u32 gic_get_ppi_index(struct irq_data *d)
+{
+	return __gic_get_ppi_index(d->hwirq);
+}
 static int gic_irq_nmi_setup(struct irq_data *d)
 {
 	struct irq_desc *desc = irq_to_desc(d->irq);
 		return;
 	if (gic_supports_nmi() &&
-	    unlikely(gic_read_rpr() == GICD_INT_NMI_PRI)) {
+	    unlikely(gic_read_rpr() == GICD_INT_RPR_PRI(GICD_INT_NMI_PRI))) {
 		gic_handle_nmi(irqnr, regs);
 		return;
 	}
 	}
 }
+static bool fwspec_is_partitioned_ppi(struct irq_fwspec *fwspec,
+				      irq_hw_number_t hwirq)
+{
+	enum gic_intid_range range;
+	if (!gic_data.ppi_descs)
+		return false;
+	if (!is_of_node(fwspec->fwnode))
+		return false;
+	if (fwspec->param_count < 4 || !fwspec->param[3])
+		return false;
+	range = __get_intid_range(hwirq);
+	if (range != PPI_RANGE && range != EPPI_RANGE)
+		return false;
+	return true;
+}
 static int gic_irq_domain_select(struct irq_domain *d,
 				 struct irq_fwspec *fwspec,
 				 enum irq_domain_bus_token bus_token)
 {
+	unsigned int type, ret, ppi_idx;
+	irq_hw_number_t hwirq;
 	/* Not for us */
         if (fwspec->fwnode != d->fwnode)
 		return 0;
 	if (!is_of_node(fwspec->fwnode))
 		return 1;
+	ret = gic_irq_domain_translate(d, fwspec, &hwirq, &type);
+	if (WARN_ON_ONCE(ret))
+		return 0;
+	if (!fwspec_is_partitioned_ppi(fwspec, hwirq))
+		return d == gic_data.domain;
 	/*
 	 * If this is a PPI and we have a 4th (non-null) parameter,
 	 * then we need to match the partition domain.
 	 */
-	if (fwspec->param_count >= 4 &&
+	ppi_idx = __gic_get_ppi_index(hwirq);
-	    fwspec->param[0] == 1 && fwspec->param[3] != 0 &&
+	return d == partition_get_domain(gic_data.ppi_descs[ppi_idx]);
-	    gic_data.ppi_descs)
-		return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]);
-	return d == gic_data.domain;
 }
 static const struct irq_domain_ops gic_irq_domain_ops = {
 				      unsigned long *hwirq,
 				      unsigned int *type)
 {
+	unsigned long ppi_intid;
 	struct device_node *np;
+	unsigned int ppi_idx;
 	int ret;
 	if (!gic_data.ppi_descs)
 	if (WARN_ON(!np))
 		return -EINVAL;
-	ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]],
+	ret = gic_irq_domain_translate(d, fwspec, &ppi_intid, type);
+	if (WARN_ON_ONCE(ret))
+		return 0;
+	ppi_idx = __gic_get_ppi_index(ppi_intid);
+	ret = partition_translate_id(gic_data.ppi_descs[ppi_idx],
 				     of_node_to_fwnode(np));
 	if (ret < 0)
 		return ret;

drivers/irqchip/irq-loongson-pch-pic.c+18−1

 	case IRQ_TYPE_EDGE_RISING:
 		pch_pic_bitset(priv, PCH_PIC_EDGE, d->hwirq);
 		pch_pic_bitclr(priv, PCH_PIC_POL, d->hwirq);
+		irq_set_handler_locked(d, handle_edge_irq);
 		break;
 	case IRQ_TYPE_EDGE_FALLING:
 		pch_pic_bitset(priv, PCH_PIC_EDGE, d->hwirq);
 		pch_pic_bitset(priv, PCH_PIC_POL, d->hwirq);
+		irq_set_handler_locked(d, handle_edge_irq);
 		break;
 	case IRQ_TYPE_LEVEL_HIGH:
 		pch_pic_bitclr(priv, PCH_PIC_EDGE, d->hwirq);
 		pch_pic_bitclr(priv, PCH_PIC_POL, d->hwirq);
+		irq_set_handler_locked(d, handle_level_irq);
 		break;
 	case IRQ_TYPE_LEVEL_LOW:
 		pch_pic_bitclr(priv, PCH_PIC_EDGE, d->hwirq);
 		pch_pic_bitset(priv, PCH_PIC_POL, d->hwirq);
+		irq_set_handler_locked(d, handle_level_irq);
 		break;
 	default:
 		ret = -EINVAL;
 	return ret;
 }
+static void pch_pic_ack_irq(struct irq_data *d)
+{
+	unsigned int reg;
+	struct pch_pic *priv = irq_data_get_irq_chip_data(d);
+	reg = readl(priv->base + PCH_PIC_EDGE + PIC_REG_IDX(d->hwirq) * 4);
+	if (reg & BIT(PIC_REG_BIT(d->hwirq))) {
+		writel(BIT(PIC_REG_BIT(d->hwirq)),
+			priv->base + PCH_PIC_CLR + PIC_REG_IDX(d->hwirq) * 4);
+	}
+	irq_chip_ack_parent(d);
+}
 static struct irq_chip pch_pic_irq_chip = {
 	.name			= "PCH PIC",
 	.irq_mask		= pch_pic_mask_irq,
 	.irq_unmask		= pch_pic_unmask_irq,
-	.irq_ack		= irq_chip_ack_parent,
+	.irq_ack		= pch_pic_ack_irq,
 	.irq_set_affinity	= irq_chip_set_affinity_parent,
 	.irq_set_type		= pch_pic_set_type,
 };

drivers/irqchip/irq-ls-scfg-msi.c+1−4

 	msi_data->irqs_num = MSI_IRQS_PER_MSIR *
 			     (1 << msi_data->cfg->ibs_shift);
-	msi_data->used = devm_kcalloc(&pdev->dev,
+	msi_data->used = devm_bitmap_zalloc(&pdev->dev, msi_data->irqs_num, GFP_KERNEL);
-				    BITS_TO_LONGS(msi_data->irqs_num),
-				    sizeof(*msi_data->used),
-				    GFP_KERNEL);
 	if (!msi_data->used)
 		return -ENOMEM;
 	/*

drivers/irqchip/irq-mtk-sysirq.c+1−0

@@ -65,6 +65,7 @@ static struct irq_chip mtk_sysirq_chip = { · 64 unmodified lines
65	.irq_set_type = mtk_sysirq_set_type,	65	.irq_set_type = mtk_sysirq_set_type,
66	.irq_retrigger = irq_chip_retrigger_hierarchy,	66	.irq_retrigger = irq_chip_retrigger_hierarchy,
67	.irq_set_affinity = irq_chip_set_affinity_parent,	67	.irq_set_affinity = irq_chip_set_affinity_parent,
		68	.flags = IRQCHIP_SKIP_SET_WAKE,
68	};	69	};
69		70
70	static int mtk_sysirq_domain_translate(struct irq_domain *d,	71	static int mtk_sysirq_domain_translate(struct irq_domain *d,

drivers/irqchip/irq-mvebu-gicp.c+1−3

@@ -210,9 +210,7 @@ static int mvebu_gicp_probe(struct platform_device *pdev) · 209 unmodified lines
210	gicp->spi_cnt += gicp->spi_ranges[i].count;	210	gicp->spi_cnt += gicp->spi_ranges[i].count;
211	}	211	}
212		212
213	gicp->spi_bitmap = devm_kcalloc(&pdev->dev,	213	gicp->spi_bitmap = devm_bitmap_zalloc(&pdev->dev, gicp->spi_cnt, GFP_KERNEL);
214	BITS_TO_LONGS(gicp->spi_cnt), sizeof(long),
215	GFP_KERNEL);
216	if (!gicp->spi_bitmap)	214	if (!gicp->spi_bitmap)
217	return -ENOMEM;	215	return -ENOMEM;
218		216

drivers/irqchip/irq-mvebu-odmi.c+2−3

 	if (!odmis)
 		return -ENOMEM;
-	odmis_bm = kcalloc(BITS_TO_LONGS(odmis_count * NODMIS_PER_FRAME),
+	odmis_bm = bitmap_zalloc(odmis_count * NODMIS_PER_FRAME, GFP_KERNEL);
-			   sizeof(long), GFP_KERNEL);
 	if (!odmis_bm) {
 		ret = -ENOMEM;
 		goto err_alloc;
 		if (odmi->base && !IS_ERR(odmi->base))
 			iounmap(odmis[i].base);
 	}
-	kfree(odmis_bm);
+	bitmap_free(odmis_bm);
 err_alloc:
 	kfree(odmis);
 	return ret;

drivers/irqchip/irq-partition-percpu.c+1−2

@@ -215,8 +215,7 @@ struct partition_desc partition_create_desc(struct fwnode_handle fwnode, · 214 unmodified lines
215	goto out;	215	goto out;
216	desc->domain = d;	216	desc->domain = d;
217		217
218	desc->bitmap = kcalloc(BITS_TO_LONGS(nr_parts), sizeof(long),	218	desc->bitmap = bitmap_zalloc(nr_parts, GFP_KERNEL);
219	GFP_KERNEL);
220	if (WARN_ON(!desc->bitmap))	219	if (WARN_ON(!desc->bitmap))
221	goto out;	220	goto out;
222		221

drivers/irqchip/qcom-pdc.c+11−57

 	return readl_relaxed(pdc_base + reg + i * sizeof(u32));
 }
-static int qcom_pdc_gic_get_irqchip_state(struct irq_data *d,
-					  enum irqchip_irq_state which,
-					  bool *state)
-{
-	if (d->hwirq == GPIO_NO_WAKE_IRQ)
-		return 0;
-	return irq_chip_get_parent_state(d, which, state);
-}
-static int qcom_pdc_gic_set_irqchip_state(struct irq_data *d,
-					  enum irqchip_irq_state which,
-					  bool value)
-{
-	if (d->hwirq == GPIO_NO_WAKE_IRQ)
-		return 0;
-	return irq_chip_set_parent_state(d, which, value);
-}
 static void pdc_enable_intr(struct irq_data *d, bool on)
 {
 	int pin_out = d->hwirq;
 static void qcom_pdc_gic_disable(struct irq_data *d)
 {
-	if (d->hwirq == GPIO_NO_WAKE_IRQ)
-		return;
 	pdc_enable_intr(d, false);
 	irq_chip_disable_parent(d);
 }
 static void qcom_pdc_gic_enable(struct irq_data *d)
 {
-	if (d->hwirq == GPIO_NO_WAKE_IRQ)
-		return;
 	pdc_enable_intr(d, true);
 	irq_chip_enable_parent(d);
 }
-static void qcom_pdc_gic_mask(struct irq_data *d)
-{
-	if (d->hwirq == GPIO_NO_WAKE_IRQ)
-		return;
-	irq_chip_mask_parent(d);
-}
-static void qcom_pdc_gic_unmask(struct irq_data *d)
-{
-	if (d->hwirq == GPIO_NO_WAKE_IRQ)
-		return;
-	irq_chip_unmask_parent(d);
-}
 /*
  * GIC does not handle falling edge or active low. To allow falling edge and
  * active low interrupts to be handled at GIC, PDC has an inverter that inverts
  */
 static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
 {
-	int pin_out = d->hwirq;
 	enum pdc_irq_config_bits pdc_type;
 	enum pdc_irq_config_bits old_pdc_type;
 	int ret;
-	if (pin_out == GPIO_NO_WAKE_IRQ)
-		return 0;
 	switch (type) {
 	case IRQ_TYPE_EDGE_RISING:
 		pdc_type = PDC_EDGE_RISING;
 		return -EINVAL;
 	}
-	old_pdc_type = pdc_reg_read(IRQ_i_CFG, pin_out);
+	old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq);
-	pdc_reg_write(IRQ_i_CFG, pin_out, pdc_type);
+	pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type);
 	ret = irq_chip_set_type_parent(d, type);
 	if (ret)
 static struct irq_chip qcom_pdc_gic_chip = {
 	.name			= "PDC",
 	.irq_eoi		= irq_chip_eoi_parent,
-	.irq_mask		= qcom_pdc_gic_mask,
+	.irq_mask		= irq_chip_mask_parent,
-	.irq_unmask		= qcom_pdc_gic_unmask,
+	.irq_unmask		= irq_chip_unmask_parent,
 	.irq_disable		= qcom_pdc_gic_disable,
 	.irq_enable		= qcom_pdc_gic_enable,
-	.irq_get_irqchip_state	= qcom_pdc_gic_get_irqchip_state,
+	.irq_get_irqchip_state	= irq_chip_get_parent_state,
-	.irq_set_irqchip_state	= qcom_pdc_gic_set_irqchip_state,
+	.irq_set_irqchip_state	= irq_chip_set_parent_state,
 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
 	.irq_set_type		= qcom_pdc_gic_set_type,
 	.flags			= IRQCHIP_MASK_ON_SUSPEND |
 	parent_hwirq = get_parent_hwirq(hwirq);
 	if (parent_hwirq == PDC_NO_PARENT_IRQ)
-		return 0;
+		return irq_domain_disconnect_hierarchy(domain->parent, virq);
 	if (type & IRQ_TYPE_EDGE_BOTH)
 		type = IRQ_TYPE_EDGE_RISING;
 	if (ret)
 		return ret;
+	if (hwirq == GPIO_NO_WAKE_IRQ)
+		return irq_domain_disconnect_hierarchy(domain, virq);
 	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
 					    &qcom_pdc_gic_chip, NULL);
 	if (ret)
 		return ret;
-	if (hwirq == GPIO_NO_WAKE_IRQ)
-		return 0;
 	parent_hwirq = get_parent_hwirq(hwirq);
 	if (parent_hwirq == PDC_NO_PARENT_IRQ)
-		return 0;
+		return irq_domain_disconnect_hierarchy(domain->parent, virq);
 	if (type & IRQ_TYPE_EDGE_BOTH)
 		type = IRQ_TYPE_EDGE_RISING;

drivers/mfd/db8500-prcmu.c+1−1

@@ -2364,7 +2364,7 @@ static bool read_mailbox_0(void) · 2363 unmodified lines
2364		2364
2365	for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {	2365	for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
2366	if (ev & prcmu_irq_bit[n])	2366	if (ev & prcmu_irq_bit[n])
2367	generic_handle_irq(irq_find_mapping(db8500_irq_domain, n));	2367	generic_handle_domain_irq(db8500_irq_domain, n);
2368	}	2368	}
2369	r = true;	2369	r = true;
2370	break;	2370	break;

drivers/mfd/fsl-imx25-tsadc.c+2−2

@@ -35,10 +35,10 @@ static void mx25_tsadc_irq_handler(struct irq_desc *desc) · 34 unmodified lines
35	regmap_read(tsadc->regs, MX25_TSC_TGSR, &status);	35	regmap_read(tsadc->regs, MX25_TSC_TGSR, &status);
36		36
37	if (status & MX25_TGSR_GCQ_INT)	37	if (status & MX25_TGSR_GCQ_INT)
38	generic_handle_irq(irq_find_mapping(tsadc->domain, 1));	38	generic_handle_domain_irq(tsadc->domain, 1);
39		39
40	if (status & MX25_TGSR_TCQ_INT)	40	if (status & MX25_TGSR_TCQ_INT)
41	generic_handle_irq(irq_find_mapping(tsadc->domain, 0));	41	generic_handle_domain_irq(tsadc->domain, 0);
42		42
43	chained_irq_exit(chip, desc);	43	chained_irq_exit(chip, desc);
44	}	44	}

drivers/mfd/ioc3.c+3−7

 	struct ioc3_priv_data *ipd = domain->host_data;
 	struct ioc3 __iomem *regs = ipd->regs;
 	u32 pending, mask;
-	unsigned int irq;
 	pending = readl(&regs->sio_ir);
 	mask = readl(&regs->sio_ies);
 	pending &= mask; /* Mask off not enabled interrupts */
-	if (pending) {
+	if (pending)
-		irq = irq_find_mapping(domain, __ffs(pending));
+		generic_handle_domain_irq(domain, __ffs(pending));
-		if (irq)
+	else
-			generic_handle_irq(irq);
-	} else  {
 		spurious_interrupt();
-	}
 }
 /*

drivers/mfd/qcom-pm8xxx.c+4−6

 static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
 {
-	int pmirq, irq, i, ret = 0;
+	int pmirq, i, ret = 0;
 	unsigned int bits;
 	ret = pm8xxx_read_block_irq(chip, block, &bits);
 	for (i = 0; i < 8; i++) {
 		if (bits & (1 << i)) {
 			pmirq = block * 8 + i;
-			irq = irq_find_mapping(chip->irqdomain, pmirq);
+			generic_handle_domain_irq(chip->irqdomain, pmirq);
-			generic_handle_irq(irq);
 		}
 	}
 	return 0;
 static void pm8821_irq_block_handler(struct pm_irq_chip *chip,
 				     int master, int block)
 {
-	int pmirq, irq, i, ret;
+	int pmirq, i, ret;
 	unsigned int bits;
 	ret = regmap_read(chip->regmap,
 	for (i = 0; i < 8; i++) {
 		if (bits & BIT(i)) {
 			pmirq = block * 8 + i;
-			irq = irq_find_mapping(chip->irqdomain, pmirq);
+			generic_handle_domain_irq(chip->irqdomain, pmirq);
-			generic_handle_irq(irq);
 		}
 	}
 }

drivers/pinctrl/actions/pinctrl-owl.c+2−3

 	unsigned int parent = irq_desc_get_irq(desc);
 	const struct owl_gpio_port *port;
 	void __iomem *base;
-	unsigned int pin, irq, offset = 0, i;
+	unsigned int pin, offset = 0, i;
 	unsigned long pending_irq;
 	chained_irq_enter(chip, desc);
 		pending_irq = readl_relaxed(base + port->intc_pd);
 		for_each_set_bit(pin, &pending_irq, port->pins) {
-			irq = irq_find_mapping(domain, offset + pin);
+			generic_handle_domain_irq(domain, offset + pin);
-			generic_handle_irq(irq);
 			/* clear pending interrupt */
 			owl_gpio_update_reg(base + port->intc_pd, pin, true);

drivers/pinctrl/bcm/pinctrl-bcm2835.c+2−2

@@ -395,8 +395,8 @@ static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc, · 394 unmodified lines
395	events &= pc->enabled_irq_map[bank];	395	events &= pc->enabled_irq_map[bank];
396	for_each_set_bit(offset, &events, 32) {	396	for_each_set_bit(offset, &events, 32) {
397	gpio = (32 * bank) + offset;	397	gpio = (32 * bank) + offset;
398	generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.domain,	398	generic_handle_domain_irq(pc->gpio_chip.irq.domain,
399	gpio));	399	gpio);
400	}	400	}
401	}	401	}
402		402

drivers/pinctrl/bcm/pinctrl-iproc-gpio.c+1−2

 		for_each_set_bit(bit, &val, NGPIOS_PER_BANK) {
 			unsigned pin = NGPIOS_PER_BANK * i + bit;
-			int child_irq = irq_find_mapping(gc->irq.domain, pin);
 			/*
 			 * Clear the interrupt before invoking the
 			writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) +
 			       IPROC_GPIO_INT_CLR_OFFSET);
-			generic_handle_irq(child_irq);
+			generic_handle_domain_irq(gc->irq.domain, pin);
 		}
 	}

drivers/pinctrl/bcm/pinctrl-nsp-gpio.c+1−2

@@ -155,8 +155,7 @@ static irqreturn_t nsp_gpio_irq_handler(int irq, void *data) · 154 unmodified lines
155	int_bits = level \| event;	155	int_bits = level \| event;
156		156
157	for_each_set_bit(bit, &int_bits, gc->ngpio)	157	for_each_set_bit(bit, &int_bits, gc->ngpio)
158	generic_handle_irq(	158	generic_handle_domain_irq(gc->irq.domain, bit);
159	irq_linear_revmap(gc->irq.domain, bit));
160	}	159	}
161		160
162	return int_bits ? IRQ_HANDLED : IRQ_NONE;	161	return int_bits ? IRQ_HANDLED : IRQ_NONE;

drivers/pinctrl/intel/pinctrl-baytrail.c+2−5

 	u32 base, pin;
 	void __iomem *reg;
 	unsigned long pending;
-	unsigned int virq;
 	/* check from GPIO controller which pin triggered the interrupt */
 	for (base = 0; base < vg->chip.ngpio; base += 32) {
 		raw_spin_lock(&byt_lock);
 		pending = readl(reg);
 		raw_spin_unlock(&byt_lock);
-		for_each_set_bit(pin, &pending, 32) {
+		for_each_set_bit(pin, &pending, 32)
-			virq = irq_find_mapping(vg->chip.irq.domain, base + pin);
+			generic_handle_domain_irq(vg->chip.irq.domain, base + pin);
-			generic_handle_irq(virq);
-		}
 	}
 	chip->irq_eoi(data);
 }

drivers/pinctrl/intel/pinctrl-cherryview.c+2−3

 	raw_spin_unlock_irqrestore(&chv_lock, flags);
 	for_each_set_bit(intr_line, &pending, community->nirqs) {
-		unsigned int irq, offset;
+		unsigned int offset;
 		offset = cctx->intr_lines[intr_line];
-		irq = irq_find_mapping(gc->irq.domain, offset);
+		generic_handle_domain_irq(gc->irq.domain, offset);
-		generic_handle_irq(irq);
 	}
 	chained_irq_exit(chip, desc);

drivers/pinctrl/intel/pinctrl-lynxpoint.c+2−6

 		/* Only interrupts that are enabled */
 		pending = ioread32(reg) & ioread32(ena);
-		for_each_set_bit(pin, &pending, 32) {
+		for_each_set_bit(pin, &pending, 32)
-			unsigned int irq;
+			generic_handle_domain_irq(lg->chip.irq.domain, base + pin);
-			irq = irq_find_mapping(lg->chip.irq.domain, base + pin);
-			generic_handle_irq(irq);
-		}
 	}
 	chip->irq_eoi(data);
 }

drivers/pinctrl/mediatek/mtk-eint.c+2−3

 	struct irq_chip *chip = irq_desc_get_chip(desc);
 	struct mtk_eint *eint = irq_desc_get_handler_data(desc);
 	unsigned int status, eint_num;
-	int offset, mask_offset, index, virq;
+	int offset, mask_offset, index;
 	void __iomem *reg =  mtk_eint_get_offset(eint, 0, eint->regs->stat);
 	int dual_edge, start_level, curr_level;
 			offset = __ffs(status);
 			mask_offset = eint_num >> 5;
 			index = eint_num + offset;
-			virq = irq_find_mapping(eint->domain, index);
 			status &= ~BIT(offset);
 			/*
 								 index);
 			}
-			generic_handle_irq(virq);
+			generic_handle_domain_irq(eint->domain, index);
 			if (dual_edge) {
 				curr_level = mtk_eint_flip_edge(eint, index);

drivers/pinctrl/nomadik/pinctrl-nomadik.c+1−1

@@ -815,7 +815,7 @@ static void nmk_gpio_irq_handler(struct irq_desc *desc) · 814 unmodified lines
815	while (status) {	815	while (status) {
816	int bit = __ffs(status);	816	int bit = __ffs(status);
817		817
818	generic_handle_irq(irq_find_mapping(chip->irq.domain, bit));	818	generic_handle_domain_irq(chip->irq.domain, bit);
819	status &= ~BIT(bit);	819	status &= ~BIT(bit);
820	}	820	}
821		821

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c+1−1

@@ -231,7 +231,7 @@ static void npcmgpio_irq_handler(struct irq_desc *desc) · 230 unmodified lines
231		231
232	sts &= en;	232	sts &= en;
233	for_each_set_bit(bit, (const void *)&sts, NPCM7XX_GPIO_PER_BANK)	233	for_each_set_bit(bit, (const void *)&sts, NPCM7XX_GPIO_PER_BANK)
234	generic_handle_irq(irq_linear_revmap(gc->irq.domain, bit));	234	generic_handle_domain_irq(gc->irq.domain, bit);
235	chained_irq_exit(chip, desc);	235	chained_irq_exit(chip, desc);
236	}	236	}
237		237

drivers/pinctrl/pinctrl-amd.c+2−4

 			if (!(regval & PIN_IRQ_PENDING) ||
 			    !(regval & BIT(INTERRUPT_MASK_OFF)))
 				continue;
-			irq = irq_find_mapping(gc->irq.domain, irqnr + i);
+			generic_handle_domain_irq(gc->irq.domain, irqnr + i);
-			if (irq != 0)
-				generic_handle_irq(irq);
 			/* Clear interrupt.
 			 * We must read the pin register again, in case the
 			 * value was changed while executing
-			 * generic_handle_irq() above.
+			 * generic_handle_domain_irq() above.
 			 * If we didn't find a mapping for the interrupt,
 			 * disable it in order to avoid a system hang caused
 			 * by an interrupt storm.

drivers/pinctrl/pinctrl-at91.c+2−4

 			continue;
 		}
-		for_each_set_bit(n, &isr, BITS_PER_LONG) {
+		for_each_set_bit(n, &isr, BITS_PER_LONG)
-			generic_handle_irq(irq_find_mapping(
+			generic_handle_domain_irq(gpio_chip->irq.domain, n);
-					   gpio_chip->irq.domain, n));
-		}
 	}
 	chained_irq_exit(chip, desc);
 	/* now it may re-trigger */

drivers/pinctrl/pinctrl-equilibrium.c+1−1

@@ -155,7 +155,7 @@ static void eqbr_irq_handler(struct irq_desc *desc) · 154 unmodified lines
155	pins = readl(gctrl->membase + GPIO_IRNCR);	155	pins = readl(gctrl->membase + GPIO_IRNCR);
156		156
157	for_each_set_bit(offset, &pins, gc->ngpio)	157	for_each_set_bit(offset, &pins, gc->ngpio)
158	generic_handle_irq(irq_find_mapping(gc->irq.domain, offset));	158	generic_handle_domain_irq(gc->irq.domain, offset);
159		159
160	chained_irq_exit(ic, desc);	160	chained_irq_exit(ic, desc);
161	}	161	}

drivers/pinctrl/pinctrl-ingenic.c+1−1

@@ -3080,7 +3080,7 @@ static void ingenic_gpio_irq_handler(struct irq_desc *desc) · 3079 unmodified lines
3080	flag = ingenic_gpio_read_reg(jzgc, JZ4730_GPIO_GPFR);	3080	flag = ingenic_gpio_read_reg(jzgc, JZ4730_GPIO_GPFR);
3081		3081
3082	for_each_set_bit(i, &flag, 32)	3082	for_each_set_bit(i, &flag, 32)
3083	generic_handle_irq(irq_linear_revmap(gc->irq.domain, i));	3083	generic_handle_domain_irq(gc->irq.domain, i);
3084	chained_irq_exit(irq_chip, desc);	3084	chained_irq_exit(irq_chip, desc);
3085	}	3085	}
3086		3086

drivers/pinctrl/pinctrl-microchip-sgpio.c+1−1

@@ -673,7 +673,7 @@ static void sgpio_irq_handler(struct irq_desc *desc) · 672 unmodified lines
673		673
674	for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) {	674	for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) {
675	gpio = sgpio_addr_to_pin(priv, port, bit);	675	gpio = sgpio_addr_to_pin(priv, port, bit);
676	generic_handle_irq(irq_linear_revmap(chip->irq.domain, gpio));	676	generic_handle_domain_irq(chip->irq.domain, gpio);
677	}	677	}
678		678
679	chained_irq_exit(parent_chip, desc);	679	chained_irq_exit(parent_chip, desc);

drivers/pinctrl/pinctrl-ocelot.c+1−2

@@ -1290,8 +1290,7 @@ static void ocelot_irq_handler(struct irq_desc *desc) · 1289 unmodified lines
1290		1290
1291	for_each_set_bit(irq, &irqs,	1291	for_each_set_bit(irq, &irqs,
1292	min(32U, info->desc->npins - 32 * i))	1292	min(32U, info->desc->npins - 32 * i))
1293	generic_handle_irq(irq_linear_revmap(chip->irq.domain,	1293	generic_handle_domain_irq(chip->irq.domain, irq + 32 * i);
1294	irq + 32 * i));
1295		1294
1296	chained_irq_exit(parent_chip, desc);	1295	chained_irq_exit(parent_chip, desc);
1297	}	1296	}

drivers/pinctrl/pinctrl-oxnas.c+1−1

@@ -1055,7 +1055,7 @@ static void oxnas_gpio_irq_handler(struct irq_desc *desc) · 1054 unmodified lines
1055	stat = readl(bank->reg_base + IRQ_PENDING);	1055	stat = readl(bank->reg_base + IRQ_PENDING);
1056		1056
1057	for_each_set_bit(pin, &stat, BITS_PER_LONG)	1057	for_each_set_bit(pin, &stat, BITS_PER_LONG)
1058	generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));	1058	generic_handle_domain_irq(gc->irq.domain, pin);
1059		1059
1060	chained_irq_exit(chip, desc);	1060	chained_irq_exit(chip, desc);
1061	}	1061	}

drivers/pinctrl/pinctrl-pic32.c+1−1

@@ -2101,7 +2101,7 @@ static void pic32_gpio_irq_handler(struct irq_desc *desc) · 2100 unmodified lines
2101	pending = pic32_gpio_get_pending(gc, stat);	2101	pending = pic32_gpio_get_pending(gc, stat);
2102		2102
2103	for_each_set_bit(pin, &pending, BITS_PER_LONG)	2103	for_each_set_bit(pin, &pending, BITS_PER_LONG)
2104	generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));	2104	generic_handle_domain_irq(gc->irq.domain, pin);
2105		2105
2106	chained_irq_exit(chip, desc);	2106	chained_irq_exit(chip, desc);
2107	}	2107	}

drivers/pinctrl/pinctrl-pistachio.c+1−1

@@ -1306,7 +1306,7 @@ static void pistachio_gpio_irq_handler(struct irq_desc *desc) · 1305 unmodified lines
1306	pending = gpio_readl(bank, GPIO_INTERRUPT_STATUS) &	1306	pending = gpio_readl(bank, GPIO_INTERRUPT_STATUS) &
1307	gpio_readl(bank, GPIO_INTERRUPT_EN);	1307	gpio_readl(bank, GPIO_INTERRUPT_EN);
1308	for_each_set_bit(pin, &pending, 16)	1308	for_each_set_bit(pin, &pending, 16)
1309	generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));	1309	generic_handle_domain_irq(gc->irq.domain, pin);
1310	chained_irq_exit(chip, desc);	1310	chained_irq_exit(chip, desc);
1311	}	1311	}
1312		1312

drivers/pinctrl/pinctrl-rockchip.c+18−891

@@ -21,8 +21,8 @@ · 20 unmodified lines
21	#include <linux/io.h>	21	#include <linux/io.h>
22	#include <linux/bitops.h>	22	#include <linux/bitops.h>
23	#include <linux/gpio/driver.h>	23	#include <linux/gpio/driver.h>
24	#include <linux/of_device.h>
25	#include <linux/of_address.h>	24	#include <linux/of_address.h>
		25	#include <linux/of_device.h>
26	#include <linux/of_irq.h>	26	#include <linux/of_irq.h>
27	#include <linux/pinctrl/machine.h>	27	#include <linux/pinctrl/machine.h>
28	#include <linux/pinctrl/pinconf.h>	28	#include <linux/pinctrl/pinconf.h>
@@ -37,35 +37,7 @@ · 8 unmodified lines
37		37
38	#include "core.h"	38	#include "core.h"
39	#include "pinconf.h"	39	#include "pinconf.h"
40		40	#include "pinctrl-rockchip.h"
41	/* GPIO control registers */
42	#define GPIO_SWPORT_DR 0x00
43	#define GPIO_SWPORT_DDR 0x04
44	#define GPIO_INTEN 0x30
45	#define GPIO_INTMASK 0x34
46	#define GPIO_INTTYPE_LEVEL 0x38
47	#define GPIO_INT_POLARITY 0x3c
48	#define GPIO_INT_STATUS 0x40
49	#define GPIO_INT_RAWSTATUS 0x44
50	#define GPIO_DEBOUNCE 0x48
51	#define GPIO_PORTS_EOI 0x4c
52	#define GPIO_EXT_PORT 0x50
53	#define GPIO_LS_SYNC 0x60
54
55	enum rockchip_pinctrl_type {
56	PX30,
57	RV1108,
58	RK2928,
59	RK3066B,
60	RK3128,
61	RK3188,
62	RK3288,
63	RK3308,
64	RK3368,
65	RK3399,
66	RK3568,
67	};
68
69		41
70	/**	42	/**
71	* Generate a bitmask for setting a value (v) with a write mask bit in hiword	43	* Generate a bitmask for setting a value (v) with a write mask bit in hiword
@@ -84,103 +56,6 @@ enum rockchip_pinctrl_type { · 12 unmodified lines
84	#define IOMUX_WIDTH_3BIT BIT(4)	56	#define IOMUX_WIDTH_3BIT BIT(4)
85	#define IOMUX_WIDTH_2BIT BIT(5)	57	#define IOMUX_WIDTH_2BIT BIT(5)
86		58
87	/**
88	* struct rockchip_iomux
89	* @type: iomux variant using IOMUX_* constants
90	* @offset: if initialized to -1 it will be autocalculated, by specifying
91	* an initial offset value the relevant source offset can be reset
92	* to a new value for autocalculating the following iomux registers.
93	*/
94	struct rockchip_iomux {
95	int type;
96	int offset;
97	};
98
99	/*
100	* enum type index corresponding to rockchip_perpin_drv_list arrays index.
101	*/
102	enum rockchip_pin_drv_type {
103	DRV_TYPE_IO_DEFAULT = 0,
104	DRV_TYPE_IO_1V8_OR_3V0,
105	DRV_TYPE_IO_1V8_ONLY,
106	DRV_TYPE_IO_1V8_3V0_AUTO,
107	DRV_TYPE_IO_3V3_ONLY,
108	DRV_TYPE_MAX
109	};
110
111	/*
112	* enum type index corresponding to rockchip_pull_list arrays index.
113	*/
114	enum rockchip_pin_pull_type {
115	PULL_TYPE_IO_DEFAULT = 0,
116	PULL_TYPE_IO_1V8_ONLY,
117	PULL_TYPE_MAX
118	};
119
120	/**
121	* struct rockchip_drv
122	* @drv_type: drive strength variant using rockchip_perpin_drv_type
123	* @offset: if initialized to -1 it will be autocalculated, by specifying
124	* an initial offset value the relevant source offset can be reset
125	* to a new value for autocalculating the following drive strength
126	* registers. if used chips own cal_drv func instead to calculate
127	* registers offset, the variant could be ignored.
128	*/
129	struct rockchip_drv {
130	enum rockchip_pin_drv_type drv_type;
131	int offset;
132	};
133
134	/**
135	* struct rockchip_pin_bank
136	* @reg_base: register base of the gpio bank
137	* @regmap_pull: optional separate register for additional pull settings
138	* @clk: clock of the gpio bank
139	* @irq: interrupt of the gpio bank
140	* @saved_masks: Saved content of GPIO_INTEN at suspend time.
141	* @pin_base: first pin number
142	* @nr_pins: number of pins in this bank
143	* @name: name of the bank
144	* @bank_num: number of the bank, to account for holes
145	* @iomux: array describing the 4 iomux sources of the bank
146	* @drv: array describing the 4 drive strength sources of the bank
147	* @pull_type: array describing the 4 pull type sources of the bank
148	* @valid: is all necessary information present
149	* @of_node: dt node of this bank
150	* @drvdata: common pinctrl basedata
151	* @domain: irqdomain of the gpio bank
152	* @gpio_chip: gpiolib chip
153	* @grange: gpio range
154	* @slock: spinlock for the gpio bank
155	* @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
156	* @recalced_mask: bit mask to indicate a need to recalulate the mask
157	* @route_mask: bits describing the routing pins of per bank
158	*/
159	struct rockchip_pin_bank {
160	void __iomem *reg_base;
161	struct regmap *regmap_pull;
162	struct clk *clk;
163	int irq;
164	u32 saved_masks;
165	u32 pin_base;
166	u8 nr_pins;
167	char *name;
168	u8 bank_num;
169	struct rockchip_iomux iomux[4];
170	struct rockchip_drv drv[4];
171	enum rockchip_pin_pull_type pull_type[4];
172	bool valid;
173	struct device_node *of_node;
174	struct rockchip_pinctrl *drvdata;
175	struct irq_domain *domain;
176	struct gpio_chip gpio_chip;
177	struct pinctrl_gpio_range grange;
178	raw_spinlock_t slock;
179	u32 toggle_edge_mode;
180	u32 recalced_mask;
181	u32 route_mask;
182	};
183
184	#define PIN_BANK(id, pins, label) \	59	#define PIN_BANK(id, pins, label) \
185	{ \	60	{ \
186	.bank_num = id, \	61	.bank_num = id, \
@@ -320,119 +195,6 @@ struct rockchip_pin_bank { · 133 unmodified lines
320	#define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \	195	#define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \
321	PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)	196	PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
322		197
323	/**
324	* struct rockchip_mux_recalced_data: represent a pin iomux data.
325	* @num: bank number.
326	* @pin: pin number.
327	* @bit: index at register.
328	* @reg: register offset.
329	* @mask: mask bit
330	*/
331	struct rockchip_mux_recalced_data {
332	u8 num;
333	u8 pin;
334	u32 reg;
335	u8 bit;
336	u8 mask;
337	};
338
339	enum rockchip_mux_route_location {
340	ROCKCHIP_ROUTE_SAME = 0,
341	ROCKCHIP_ROUTE_PMU,
342	ROCKCHIP_ROUTE_GRF,
343	};
344
345	/**
346	* struct rockchip_mux_recalced_data: represent a pin iomux data.
347	* @bank_num: bank number.
348	* @pin: index at register or used to calc index.
349	* @func: the min pin.
350	* @route_location: the mux route location (same, pmu, grf).
351	* @route_offset: the max pin.
352	* @route_val: the register offset.
353	*/
354	struct rockchip_mux_route_data {
355	u8 bank_num;
356	u8 pin;
357	u8 func;
358	enum rockchip_mux_route_location route_location;
359	u32 route_offset;
360	u32 route_val;
361	};
362
363	struct rockchip_pin_ctrl {
364	struct rockchip_pin_bank *pin_banks;
365	u32 nr_banks;
366	u32 nr_pins;
367	char *label;
368	enum rockchip_pinctrl_type type;
369	int grf_mux_offset;
370	int pmu_mux_offset;
371	int grf_drv_offset;
372	int pmu_drv_offset;
373	struct rockchip_mux_recalced_data *iomux_recalced;
374	u32 niomux_recalced;
375	struct rockchip_mux_route_data *iomux_routes;
376	u32 niomux_routes;
377
378	void (pull_calc_reg)(struct rockchip_pin_bank bank,
379	int pin_num, struct regmap **regmap,
380	int reg, u8 bit);
381	void (drv_calc_reg)(struct rockchip_pin_bank bank,
382	int pin_num, struct regmap **regmap,
383	int reg, u8 bit);
384	int (schmitt_calc_reg)(struct rockchip_pin_bank bank,
385	int pin_num, struct regmap **regmap,
386	int reg, u8 bit);
387	};
388
389	struct rockchip_pin_config {
390	unsigned int func;
391	unsigned long *configs;
392	unsigned int nconfigs;
393	};
394
395	/**
396	* struct rockchip_pin_group: represent group of pins of a pinmux function.
397	* @name: name of the pin group, used to lookup the group.
398	* @pins: the pins included in this group.
399	* @npins: number of pins included in this group.
400	* @data: local pin configuration
401	*/
402	struct rockchip_pin_group {
403	const char *name;
404	unsigned int npins;
405	unsigned int *pins;
406	struct rockchip_pin_config *data;
407	};
408
409	/**
410	* struct rockchip_pmx_func: represent a pin function.
411	* @name: name of the pin function, used to lookup the function.
412	* @groups: one or more names of pin groups that provide this function.
413	* @ngroups: number of groups included in @groups.
414	*/
415	struct rockchip_pmx_func {
416	const char *name;
417	const char **groups;
418	u8 ngroups;
419	};
420
421	struct rockchip_pinctrl {
422	struct regmap *regmap_base;
423	int reg_size;
424	struct regmap *regmap_pull;
425	struct regmap *regmap_pmu;
426	struct device *dev;
427	struct rockchip_pin_ctrl *ctrl;
428	struct pinctrl_desc pctl;
429	struct pinctrl_dev *pctl_dev;
430	struct rockchip_pin_group *groups;
431	unsigned int ngroups;
432	struct rockchip_pmx_func *functions;
433	unsigned int nfunctions;
434	};
435
436	static struct regmap_config rockchip_regmap_config = {	198	static struct regmap_config rockchip_regmap_config = {
437	.reg_bits = 32,	199	.reg_bits = 32,
438	.val_bits = 32,	200	.val_bits = 32,
@@ -2295,86 +2057,11 @@ static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, · 1856 unmodified lines
2295	return 0;	2057	return 0;
2296	}	2058	}
2297		2059
2298	static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
2299	{
2300	struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
2301	u32 data;
2302	int ret;
2303
2304	ret = clk_enable(bank->clk);
2305	if (ret < 0) {
2306	dev_err(bank->drvdata->dev,
2307	"failed to enable clock for bank %s\n", bank->name);
2308	return ret;
2309	}
2310	data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2311	clk_disable(bank->clk);
2312
2313	if (data & BIT(offset))
2314	return GPIO_LINE_DIRECTION_OUT;
2315
2316	return GPIO_LINE_DIRECTION_IN;
2317	}
2318
2319	/*
2320	* The calls to gpio_direction_output() and gpio_direction_input()
2321	* leads to this function call (via the pinctrl_gpio_direction_{input\|output}()
2322	* function called from the gpiolib interface).
2323	*/
2324	static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
2325	int pin, bool input)
2326	{
2327	struct rockchip_pin_bank *bank;
2328	int ret;
2329	unsigned long flags;
2330	u32 data;
2331
2332	bank = gpiochip_get_data(chip);
2333
2334	ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
2335	if (ret < 0)
2336	return ret;
2337
2338	clk_enable(bank->clk);
2339	raw_spin_lock_irqsave(&bank->slock, flags);
2340
2341	data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2342	/* set bit to 1 for output, 0 for input */
2343	if (!input)
2344	data \|= BIT(pin);
2345	else
2346	data &= ~BIT(pin);
2347	writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2348
2349	raw_spin_unlock_irqrestore(&bank->slock, flags);
2350	clk_disable(bank->clk);
2351
2352	return 0;
2353	}
2354
2355	static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2356	struct pinctrl_gpio_range *range,
2357	unsigned offset, bool input)
2358	{
2359	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2360	struct gpio_chip *chip;
2361	int pin;
2362
2363	chip = range->gc;
2364	pin = offset - chip->base;
2365	dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
2366	offset, range->name, pin, input ? "input" : "output");
2367
2368	return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
2369	input);
2370	}
2371
2372	static const struct pinmux_ops rockchip_pmx_ops = {	2060	static const struct pinmux_ops rockchip_pmx_ops = {
2373	.get_functions_count = rockchip_pmx_get_funcs_count,	2061	.get_functions_count = rockchip_pmx_get_funcs_count,
2374	.get_function_name = rockchip_pmx_get_func_name,	2062	.get_function_name = rockchip_pmx_get_func_name,
2375	.get_function_groups = rockchip_pmx_get_groups,	2063	.get_function_groups = rockchip_pmx_get_groups,
2376	.set_mux = rockchip_pmx_set,	2064	.set_mux = rockchip_pmx_set,
2377	.gpio_set_direction = rockchip_pmx_gpio_set_direction,
2378	};	2065	};
2379		2066
2380	/*	2067	/*
@@ -2405,15 +2092,13 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, · 24 unmodified lines
2405	return false;	2092	return false;
2406	}	2093	}
2407		2094
2408	static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2409	static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
2410
2411	/* set the pin config settings for a specified pin */	2095	/* set the pin config settings for a specified pin */
2412	static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,	2096	static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2413	unsigned long *configs, unsigned num_configs)	2097	unsigned long *configs, unsigned num_configs)
2414	{	2098	{
2415	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);	2099	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2416	struct rockchip_pin_bank *bank = pin_to_bank(info, pin);	2100	struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
		2101	struct gpio_chip *gpio = &bank->gpio_chip;
2417	enum pin_config_param param;	2102	enum pin_config_param param;
2418	u32 arg;	2103	u32 arg;
2419	int i;	2104	int i;
@@ -2446,10 +2131,13 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, · 26 unmodified lines
2446	return rc;	2131	return rc;
2447	break;	2132	break;
2448	case PIN_CONFIG_OUTPUT:	2133	case PIN_CONFIG_OUTPUT:
2449	rockchip_gpio_set(&bank->gpio_chip,	2134	rc = rockchip_set_mux(bank, pin - bank->pin_base,
2450	pin - bank->pin_base, arg);	2135	RK_FUNC_GPIO);
2451	rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,	2136	if (rc != RK_FUNC_GPIO)
2452	pin - bank->pin_base, false);	2137	return -EINVAL;
		2138
		2139	rc = gpio->direction_output(gpio, pin - bank->pin_base,
		2140	arg);
2453	if (rc)	2141	if (rc)
2454	return rc;	2142	return rc;
2455	break;	2143	break;
@@ -2487,6 +2175,7 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, · 31 unmodified lines
2487	{	2175	{
2488	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);	2176	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2489	struct rockchip_pin_bank *bank = pin_to_bank(info, pin);	2177	struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
		2178	struct gpio_chip *gpio = &bank->gpio_chip;
2490	enum pin_config_param param = pinconf_to_config_param(*config);	2179	enum pin_config_param param = pinconf_to_config_param(*config);
2491	u16 arg;	2180	u16 arg;
2492	int rc;	2181	int rc;
@@ -2515,7 +2204,7 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, · 22 unmodified lines
2515	if (rc != RK_FUNC_GPIO)	2204	if (rc != RK_FUNC_GPIO)
2516	return -EINVAL;	2205	return -EINVAL;
2517		2206
2518	rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);	2207	rc = gpio->get(gpio, pin - bank->pin_base);
2519	if (rc < 0)	2208	if (rc < 0)
2520	return rc;	2209	return rc;
2521		2210
@@ -2753,7 +2442,7 @@ static int rockchip_pinctrl_register(struct platform_device *pdev, · 231 unmodified lines
2753	ctrldesc->npins = info->ctrl->nr_pins;	2442	ctrldesc->npins = info->ctrl->nr_pins;
2754		2443
2755	pdesc = pindesc;	2444	pdesc = pindesc;
2756	for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {	2445	for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {
2757	pin_bank = &info->ctrl->pin_banks[bank];	2446	pin_bank = &info->ctrl->pin_banks[bank];
2758	for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {	2447	for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2759	pdesc->number = k;	2448	pdesc->number = k;
@@ -2773,553 +2462,9 @@ static int rockchip_pinctrl_register(struct platform_device *pdev, · 13 unmodified lines
2773	return PTR_ERR(info->pctl_dev);	2462	return PTR_ERR(info->pctl_dev);
2774	}	2463	}
2775		2464
2776	for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
2777	pin_bank = &info->ctrl->pin_banks[bank];
2778	pin_bank->grange.name = pin_bank->name;
2779	pin_bank->grange.id = bank;
2780	pin_bank->grange.pin_base = pin_bank->pin_base;
2781	pin_bank->grange.base = pin_bank->gpio_chip.base;
2782	pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
2783	pin_bank->grange.gc = &pin_bank->gpio_chip;
2784	pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
2785	}
2786
2787	return 0;	2465	return 0;
2788	}	2466	}
2789		2467
2790	/*
2791	* GPIO handling
2792	*/
2793
2794	static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2795	{
2796	struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2797	void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2798	unsigned long flags;
2799	u32 data;
2800
2801	clk_enable(bank->clk);
2802	raw_spin_lock_irqsave(&bank->slock, flags);
2803
2804	data = readl(reg);
2805	data &= ~BIT(offset);
2806	if (value)
2807	data \|= BIT(offset);
2808	writel(data, reg);
2809
2810	raw_spin_unlock_irqrestore(&bank->slock, flags);
2811	clk_disable(bank->clk);
2812	}
2813
2814	/*
2815	* Returns the level of the pin for input direction and setting of the DR
2816	* register for output gpios.
2817	*/
2818	static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2819	{
2820	struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2821	u32 data;
2822
2823	clk_enable(bank->clk);
2824	data = readl(bank->reg_base + GPIO_EXT_PORT);
2825	clk_disable(bank->clk);
2826	data >>= offset;
2827	data &= 1;
2828	return data;
2829	}
2830
2831	/*
2832	* gpiolib gpio_direction_input callback function. The setting of the pin
2833	* mux function as 'gpio input' will be handled by the pinctrl subsystem
2834	* interface.
2835	*/
2836	static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2837	{
2838	return pinctrl_gpio_direction_input(gc->base + offset);
2839	}
2840
2841	/*
2842	* gpiolib gpio_direction_output callback function. The setting of the pin
2843	* mux function as 'gpio output' will be handled by the pinctrl subsystem
2844	* interface.
2845	*/
2846	static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2847	unsigned offset, int value)
2848	{
2849	rockchip_gpio_set(gc, offset, value);
2850	return pinctrl_gpio_direction_output(gc->base + offset);
2851	}
2852
2853	static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
2854	unsigned int offset, bool enable)
2855	{
2856	struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2857	void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
2858	unsigned long flags;
2859	u32 data;
2860
2861	clk_enable(bank->clk);
2862	raw_spin_lock_irqsave(&bank->slock, flags);
2863
2864	data = readl(reg);
2865	if (enable)
2866	data \|= BIT(offset);
2867	else
2868	data &= ~BIT(offset);
2869	writel(data, reg);
2870
2871	raw_spin_unlock_irqrestore(&bank->slock, flags);
2872	clk_disable(bank->clk);
2873	}
2874
2875	/*
2876	* gpiolib set_config callback function. The setting of the pin
2877	* mux function as 'gpio output' will be handled by the pinctrl subsystem
2878	* interface.
2879	*/
2880	static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
2881	unsigned long config)
2882	{
2883	enum pin_config_param param = pinconf_to_config_param(config);
2884
2885	switch (param) {
2886	case PIN_CONFIG_INPUT_DEBOUNCE:
2887	rockchip_gpio_set_debounce(gc, offset, true);
2888	/*
2889	* Rockchip's gpio could only support up to one period
2890	* of the debounce clock(pclk), which is far away from
2891	* satisftying the requirement, as pclk is usually near
2892	* 100MHz shared by all peripherals. So the fact is it
2893	* has crippled debounce capability could only be useful
2894	* to prevent any spurious glitches from waking up the system
2895	* if the gpio is conguired as wakeup interrupt source. Let's
2896	* still return -ENOTSUPP as before, to make sure the caller
2897	* of gpiod_set_debounce won't change its behaviour.
2898	*/
2899	return -ENOTSUPP;
2900	default:
2901	return -ENOTSUPP;
2902	}
2903	}
2904
2905	/*
2906	* gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2907	* and a virtual IRQ, if not already present.
2908	*/
2909	static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2910	{
2911	struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2912	unsigned int virq;
2913
2914	if (!bank->domain)
2915	return -ENXIO;
2916
2917	clk_enable(bank->clk);
2918	virq = irq_create_mapping(bank->domain, offset);
2919	clk_disable(bank->clk);
2920
2921	return (virq) ? : -ENXIO;
2922	}
2923
2924	static const struct gpio_chip rockchip_gpiolib_chip = {
2925	.request = gpiochip_generic_request,
2926	.free = gpiochip_generic_free,
2927	.set = rockchip_gpio_set,
2928	.get = rockchip_gpio_get,
2929	.get_direction = rockchip_gpio_get_direction,
2930	.direction_input = rockchip_gpio_direction_input,
2931	.direction_output = rockchip_gpio_direction_output,
2932	.set_config = rockchip_gpio_set_config,
2933	.to_irq = rockchip_gpio_to_irq,
2934	.owner = THIS_MODULE,
2935	};
2936
2937	/*
2938	* Interrupt handling
2939	*/
2940
2941	static void rockchip_irq_demux(struct irq_desc *desc)
2942	{
2943	struct irq_chip *chip = irq_desc_get_chip(desc);
2944	struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
2945	u32 pend;
2946
2947	dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2948
2949	chained_irq_enter(chip, desc);
2950
2951	pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2952
2953	while (pend) {
2954	unsigned int irq, virq;
2955
2956	irq = __ffs(pend);
2957	pend &= ~BIT(irq);
2958	virq = irq_find_mapping(bank->domain, irq);
2959
2960	if (!virq) {
2961	dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2962	continue;
2963	}
2964
2965	dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2966
2967	/*
2968	* Triggering IRQ on both rising and falling edge
2969	* needs manual intervention.
2970	*/
2971	if (bank->toggle_edge_mode & BIT(irq)) {
2972	u32 data, data_old, polarity;
2973	unsigned long flags;
2974
2975	data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2976	do {
2977	raw_spin_lock_irqsave(&bank->slock, flags);
2978
2979	polarity = readl_relaxed(bank->reg_base +
2980	GPIO_INT_POLARITY);
2981	if (data & BIT(irq))
2982	polarity &= ~BIT(irq);
2983	else
2984	polarity \|= BIT(irq);
2985	writel(polarity,
2986	bank->reg_base + GPIO_INT_POLARITY);
2987
2988	raw_spin_unlock_irqrestore(&bank->slock, flags);
2989
2990	data_old = data;
2991	data = readl_relaxed(bank->reg_base +
2992	GPIO_EXT_PORT);
2993	} while ((data & BIT(irq)) != (data_old & BIT(irq)));
2994	}
2995
2996	generic_handle_irq(virq);
2997	}
2998
2999	chained_irq_exit(chip, desc);
3000	}
3001
3002	static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
3003	{
3004	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3005	struct rockchip_pin_bank *bank = gc->private;
3006	u32 mask = BIT(d->hwirq);
3007	u32 polarity;
3008	u32 level;
3009	u32 data;
3010	unsigned long flags;
3011	int ret;
3012
3013	/* make sure the pin is configured as gpio input */
3014	ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
3015	if (ret < 0)
3016	return ret;
3017
3018	clk_enable(bank->clk);
3019	raw_spin_lock_irqsave(&bank->slock, flags);
3020
3021	data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
3022	data &= ~mask;
3023	writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
3024
3025	raw_spin_unlock_irqrestore(&bank->slock, flags);
3026
3027	if (type & IRQ_TYPE_EDGE_BOTH)
3028	irq_set_handler_locked(d, handle_edge_irq);
3029	else
3030	irq_set_handler_locked(d, handle_level_irq);
3031
3032	raw_spin_lock_irqsave(&bank->slock, flags);
3033	irq_gc_lock(gc);
3034
3035	level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
3036	polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
3037
3038	switch (type) {
3039	case IRQ_TYPE_EDGE_BOTH:
3040	bank->toggle_edge_mode \|= mask;
3041	level \|= mask;
3042
3043	/*
3044	* Determine gpio state. If 1 next interrupt should be falling
3045	* otherwise rising.
3046	*/
3047	data = readl(bank->reg_base + GPIO_EXT_PORT);
3048	if (data & mask)
3049	polarity &= ~mask;
3050	else
3051	polarity \|= mask;
3052	break;
3053	case IRQ_TYPE_EDGE_RISING:
3054	bank->toggle_edge_mode &= ~mask;
3055	level \|= mask;
3056	polarity \|= mask;
3057	break;
3058	case IRQ_TYPE_EDGE_FALLING:
3059	bank->toggle_edge_mode &= ~mask;
3060	level \|= mask;
3061	polarity &= ~mask;
3062	break;
3063	case IRQ_TYPE_LEVEL_HIGH:
3064	bank->toggle_edge_mode &= ~mask;
3065	level &= ~mask;
3066	polarity \|= mask;
3067	break;
3068	case IRQ_TYPE_LEVEL_LOW:
3069	bank->toggle_edge_mode &= ~mask;
3070	level &= ~mask;
3071	polarity &= ~mask;
3072	break;
3073	default:
3074	irq_gc_unlock(gc);
3075	raw_spin_unlock_irqrestore(&bank->slock, flags);
3076	clk_disable(bank->clk);
3077	return -EINVAL;
3078	}
3079
3080	writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
3081	writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
3082
3083	irq_gc_unlock(gc);
3084	raw_spin_unlock_irqrestore(&bank->slock, flags);
3085	clk_disable(bank->clk);
3086
3087	return 0;
3088	}
3089
3090	static void rockchip_irq_suspend(struct irq_data *d)
3091	{
3092	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3093	struct rockchip_pin_bank *bank = gc->private;
3094
3095	clk_enable(bank->clk);
3096	bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
3097	irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
3098	clk_disable(bank->clk);
3099	}
3100
3101	static void rockchip_irq_resume(struct irq_data *d)
3102	{
3103	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3104	struct rockchip_pin_bank *bank = gc->private;
3105
3106	clk_enable(bank->clk);
3107	irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
3108	clk_disable(bank->clk);
3109	}
3110
3111	static void rockchip_irq_enable(struct irq_data *d)
3112	{
3113	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3114	struct rockchip_pin_bank *bank = gc->private;
3115
3116	clk_enable(bank->clk);
3117	irq_gc_mask_clr_bit(d);
3118	}
3119
3120	static void rockchip_irq_disable(struct irq_data *d)
3121	{
3122	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3123	struct rockchip_pin_bank *bank = gc->private;
3124
3125	irq_gc_mask_set_bit(d);
3126	clk_disable(bank->clk);
3127	}
3128
3129	static int rockchip_interrupts_register(struct platform_device *pdev,
3130	struct rockchip_pinctrl *info)
3131	{
3132	struct rockchip_pin_ctrl *ctrl = info->ctrl;
3133	struct rockchip_pin_bank *bank = ctrl->pin_banks;
3134	unsigned int clr = IRQ_NOREQUEST \| IRQ_NOPROBE \| IRQ_NOAUTOEN;
3135	struct irq_chip_generic *gc;
3136	int ret;
3137	int i;
3138
3139	for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3140	if (!bank->valid) {
3141	dev_warn(&pdev->dev, "bank %s is not valid\n",
3142	bank->name);
3143	continue;
3144	}
3145
3146	ret = clk_enable(bank->clk);
3147	if (ret) {
3148	dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
3149	bank->name);
3150	continue;
3151	}
3152
3153	bank->domain = irq_domain_add_linear(bank->of_node, 32,
3154	&irq_generic_chip_ops, NULL);
3155	if (!bank->domain) {
3156	dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
3157	bank->name);
3158	clk_disable(bank->clk);
3159	continue;
3160	}
3161
3162	ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
3163	"rockchip_gpio_irq", handle_level_irq,
3164	clr, 0, 0);
3165	if (ret) {
3166	dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
3167	bank->name);
3168	irq_domain_remove(bank->domain);
3169	clk_disable(bank->clk);
3170	continue;
3171	}
3172
3173	gc = irq_get_domain_generic_chip(bank->domain, 0);
3174	gc->reg_base = bank->reg_base;
3175	gc->private = bank;
3176	gc->chip_types[0].regs.mask = GPIO_INTMASK;
3177	gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
3178	gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
3179	gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
3180	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
3181	gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
3182	gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
3183	gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
3184	gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
3185	gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
3186	gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
3187	gc->wake_enabled = IRQ_MSK(bank->nr_pins);
3188
3189	/*
3190	* Linux assumes that all interrupts start out disabled/masked.
3191	* Our driver only uses the concept of masked and always keeps
3192	* things enabled, so for us that's all masked and all enabled.
3193	*/
3194	writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
3195	writel_relaxed(0xffffffff, bank->reg_base + GPIO_PORTS_EOI);
3196	writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
3197	gc->mask_cache = 0xffffffff;
3198
3199	irq_set_chained_handler_and_data(bank->irq,
3200	rockchip_irq_demux, bank);
3201	clk_disable(bank->clk);
3202	}
3203
3204	return 0;
3205	}
3206
3207	static int rockchip_gpiolib_register(struct platform_device *pdev,
3208	struct rockchip_pinctrl *info)
3209	{
3210	struct rockchip_pin_ctrl *ctrl = info->ctrl;
3211	struct rockchip_pin_bank *bank = ctrl->pin_banks;
3212	struct gpio_chip *gc;
3213	int ret;
3214	int i;
3215
3216	for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3217	if (!bank->valid) {
3218	dev_warn(&pdev->dev, "bank %s is not valid\n",
3219	bank->name);
3220	continue;
3221	}
3222
3223	bank->gpio_chip = rockchip_gpiolib_chip;
3224
3225	gc = &bank->gpio_chip;
3226	gc->base = bank->pin_base;
3227	gc->ngpio = bank->nr_pins;
3228	gc->parent = &pdev->dev;
3229	gc->of_node = bank->of_node;
3230	gc->label = bank->name;
3231
3232	ret = gpiochip_add_data(gc, bank);
3233	if (ret) {
3234	dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
3235	gc->label, ret);
3236	goto fail;
3237	}
3238	}
3239
3240	rockchip_interrupts_register(pdev, info);
3241
3242	return 0;
3243
3244	fail:
3245	for (--i, --bank; i >= 0; --i, --bank) {
3246	if (!bank->valid)
3247	continue;
3248	gpiochip_remove(&bank->gpio_chip);
3249	}
3250	return ret;
3251	}
3252
3253	static int rockchip_gpiolib_unregister(struct platform_device *pdev,
3254	struct rockchip_pinctrl *info)
3255	{
3256	struct rockchip_pin_ctrl *ctrl = info->ctrl;
3257	struct rockchip_pin_bank *bank = ctrl->pin_banks;
3258	int i;
3259
3260	for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3261	if (!bank->valid)
3262	continue;
3263	gpiochip_remove(&bank->gpio_chip);
3264	}
3265
3266	return 0;
3267	}
3268
3269	static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
3270	struct rockchip_pinctrl *info)
3271	{
3272	struct resource res;
3273	void __iomem *base;
3274
3275	if (of_address_to_resource(bank->of_node, 0, &res)) {
3276	dev_err(info->dev, "cannot find IO resource for bank\n");
3277	return -ENOENT;
3278	}
3279
3280	bank->reg_base = devm_ioremap_resource(info->dev, &res);
3281	if (IS_ERR(bank->reg_base))
3282	return PTR_ERR(bank->reg_base);
3283
3284	/*
3285	* special case, where parts of the pull setting-registers are
3286	* part of the PMU register space
3287	*/
3288	if (of_device_is_compatible(bank->of_node,
3289	"rockchip,rk3188-gpio-bank0")) {
3290	struct device_node *node;
3291
3292	node = of_parse_phandle(bank->of_node->parent,
3293	"rockchip,pmu", 0);
3294	if (!node) {
3295	if (of_address_to_resource(bank->of_node, 1, &res)) {
3296	dev_err(info->dev, "cannot find IO resource for bank\n");
3297	return -ENOENT;
3298	}
3299
3300	base = devm_ioremap_resource(info->dev, &res);
3301	if (IS_ERR(base))
3302	return PTR_ERR(base);
3303	rockchip_regmap_config.max_register =
3304	resource_size(&res) - 4;
3305	rockchip_regmap_config.name =
3306	"rockchip,rk3188-gpio-bank0-pull";
3307	bank->regmap_pull = devm_regmap_init_mmio(info->dev,
3308	base,
3309	&rockchip_regmap_config);
3310	}
3311	of_node_put(node);
3312	}
3313
3314	bank->irq = irq_of_parse_and_map(bank->of_node, 0);
3315
3316	bank->clk = of_clk_get(bank->of_node, 0);
3317	if (IS_ERR(bank->clk))
3318	return PTR_ERR(bank->clk);
3319
3320	return clk_prepare(bank->clk);
3321	}
3322
3323	static const struct of_device_id rockchip_pinctrl_dt_match[];	2468	static const struct of_device_id rockchip_pinctrl_dt_match[];
3324		2469
3325	/* retrieve the soc specific data */	2470	/* retrieve the soc specific data */
@@ -3329,7 +2474,6 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( · 3 unmodified lines
3329	{	2474	{
3330	const struct of_device_id *match;	2475	const struct of_device_id *match;
3331	struct device_node *node = pdev->dev.of_node;	2476	struct device_node *node = pdev->dev.of_node;
3332	struct device_node *np;
3333	struct rockchip_pin_ctrl *ctrl;	2477	struct rockchip_pin_ctrl *ctrl;
3334	struct rockchip_pin_bank *bank;	2478	struct rockchip_pin_bank *bank;
3335	int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;	2479	int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
@@ -3337,23 +2481,6 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( · 1 unmodified line
3337	match = of_match_node(rockchip_pinctrl_dt_match, node);	2481	match = of_match_node(rockchip_pinctrl_dt_match, node);
3338	ctrl = (struct rockchip_pin_ctrl *)match->data;	2482	ctrl = (struct rockchip_pin_ctrl *)match->data;
3339		2483
3340	for_each_child_of_node(node, np) {
3341	if (!of_find_property(np, "gpio-controller", NULL))
3342	continue;
3343
3344	bank = ctrl->pin_banks;
3345	for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3346	if (!strcmp(bank->name, np->name)) {
3347	bank->of_node = np;
3348
3349	if (!rockchip_get_bank_data(bank, d))
3350	bank->valid = true;
3351
3352	break;
3353	}
3354	}
3355	}
3356
3357	grf_offs = ctrl->grf_mux_offset;	2484	grf_offs = ctrl->grf_mux_offset;
3358	pmu_offs = ctrl->pmu_mux_offset;	2485	pmu_offs = ctrl->pmu_mux_offset;
3359	drv_pmu_offs = ctrl->pmu_drv_offset;	2486	drv_pmu_offs = ctrl->pmu_drv_offset;
@@ -3574,18 +2701,18 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) · 214 unmodified lines
3574	return PTR_ERR(info->regmap_pmu);	2701	return PTR_ERR(info->regmap_pmu);
3575	}	2702	}
3576		2703
3577	ret = rockchip_gpiolib_register(pdev, info);	2704	ret = rockchip_pinctrl_register(pdev, info);
3578	if (ret)	2705	if (ret)
3579	return ret;	2706	return ret;
3580		2707
3581	ret = rockchip_pinctrl_register(pdev, info);	2708	platform_set_drvdata(pdev, info);
		2709
		2710	ret = of_platform_populate(np, rockchip_bank_match, NULL, NULL);
3582	if (ret) {	2711	if (ret) {
3583	rockchip_gpiolib_unregister(pdev, info);	2712	dev_err(&pdev->dev, "failed to register gpio device\n");
3584	return ret;	2713	return ret;
3585	}	2714	}
3586		2715
3587	platform_set_drvdata(pdev, info);
3588
3589	return 0;	2716	return 0;
3590	}	2717	}
3591		2718

drivers/pinctrl/pinctrl-rockchip.h+287−0

@@ -0,0 +1,287 @@
	1	/* SPDX-License-Identifier: GPL-2.0-only */
	2	/*
	3	* Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
	4	*
	5	* Copyright (c) 2013 MundoReader S.L.
	6	* Author: Heiko Stuebner <heiko@sntech.de>
	7	*
	8	* With some ideas taken from pinctrl-samsung:
	9	* Copyright (c) 2012 Samsung Electronics Co., Ltd.
	10	* http://www.samsung.com
	11	* Copyright (c) 2012 Linaro Ltd
	12	* https://www.linaro.org
	13	*
	14	* and pinctrl-at91:
	15	* Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
	16	*/
	17
	18	#ifndef _PINCTRL_ROCKCHIP_H
	19	#define _PINCTRL_ROCKCHIP_H
	20
	21	enum rockchip_pinctrl_type {
	22	PX30,
	23	RV1108,
	24	RK2928,
	25	RK3066B,
	26	RK3128,
	27	RK3188,
	28	RK3288,
	29	RK3308,
	30	RK3368,
	31	RK3399,
	32	RK3568,
	33	};
	34
	35	/**
	36	* struct rockchip_gpio_regs
	37	* @port_dr: data register
	38	* @port_ddr: data direction register
	39	* @int_en: interrupt enable
	40	* @int_mask: interrupt mask
	41	* @int_type: interrupt trigger type, such as high, low, edge trriger type.
	42	* @int_polarity: interrupt polarity enable register
	43	* @int_bothedge: interrupt bothedge enable register
	44	* @int_status: interrupt status register
	45	* @int_rawstatus: int_status = int_rawstatus & int_mask
	46	* @debounce: enable debounce for interrupt signal
	47	* @dbclk_div_en: enable divider for debounce clock
	48	* @dbclk_div_con: setting for divider of debounce clock
	49	* @port_eoi: end of interrupt of the port
	50	* @ext_port: port data from external
	51	* @version_id: controller version register
	52	*/
	53	struct rockchip_gpio_regs {
	54	u32 port_dr;
	55	u32 port_ddr;
	56	u32 int_en;
	57	u32 int_mask;
	58	u32 int_type;
	59	u32 int_polarity;
	60	u32 int_bothedge;
	61	u32 int_status;
	62	u32 int_rawstatus;
	63	u32 debounce;
	64	u32 dbclk_div_en;
	65	u32 dbclk_div_con;
	66	u32 port_eoi;
	67	u32 ext_port;
	68	u32 version_id;
	69	};
	70
	71	/**
	72	* struct rockchip_iomux
	73	* @type: iomux variant using IOMUX_* constants
	74	* @offset: if initialized to -1 it will be autocalculated, by specifying
	75	* an initial offset value the relevant source offset can be reset
	76	* to a new value for autocalculating the following iomux registers.
	77	*/
	78	struct rockchip_iomux {
	79	int type;
	80	int offset;
	81	};
	82
	83	/*
	84	* enum type index corresponding to rockchip_perpin_drv_list arrays index.
	85	*/
	86	enum rockchip_pin_drv_type {
	87	DRV_TYPE_IO_DEFAULT = 0,
	88	DRV_TYPE_IO_1V8_OR_3V0,
	89	DRV_TYPE_IO_1V8_ONLY,
	90	DRV_TYPE_IO_1V8_3V0_AUTO,
	91	DRV_TYPE_IO_3V3_ONLY,
	92	DRV_TYPE_MAX
	93	};
	94
	95	/*
	96	* enum type index corresponding to rockchip_pull_list arrays index.
	97	*/
	98	enum rockchip_pin_pull_type {
	99	PULL_TYPE_IO_DEFAULT = 0,
	100	PULL_TYPE_IO_1V8_ONLY,
	101	PULL_TYPE_MAX
	102	};
	103
	104	/**
	105	* struct rockchip_drv
	106	* @drv_type: drive strength variant using rockchip_perpin_drv_type
	107	* @offset: if initialized to -1 it will be autocalculated, by specifying
	108	* an initial offset value the relevant source offset can be reset
	109	* to a new value for autocalculating the following drive strength
	110	* registers. if used chips own cal_drv func instead to calculate
	111	* registers offset, the variant could be ignored.
	112	*/
	113	struct rockchip_drv {
	114	enum rockchip_pin_drv_type drv_type;
	115	int offset;
	116	};
	117
	118	/**
	119	* struct rockchip_pin_bank
	120	* @dev: the pinctrl device bind to the bank
	121	* @reg_base: register base of the gpio bank
	122	* @regmap_pull: optional separate register for additional pull settings
	123	* @clk: clock of the gpio bank
	124	* @db_clk: clock of the gpio debounce
	125	* @irq: interrupt of the gpio bank
	126	* @saved_masks: Saved content of GPIO_INTEN at suspend time.
	127	* @pin_base: first pin number
	128	* @nr_pins: number of pins in this bank
	129	* @name: name of the bank
	130	* @bank_num: number of the bank, to account for holes
	131	* @iomux: array describing the 4 iomux sources of the bank
	132	* @drv: array describing the 4 drive strength sources of the bank
	133	* @pull_type: array describing the 4 pull type sources of the bank
	134	* @valid: is all necessary information present
	135	* @of_node: dt node of this bank
	136	* @drvdata: common pinctrl basedata
	137	* @domain: irqdomain of the gpio bank
	138	* @gpio_chip: gpiolib chip
	139	* @grange: gpio range
	140	* @slock: spinlock for the gpio bank
	141	* @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
	142	* @recalced_mask: bit mask to indicate a need to recalulate the mask
	143	* @route_mask: bits describing the routing pins of per bank
	144	*/
	145	struct rockchip_pin_bank {
	146	struct device *dev;
	147	void __iomem *reg_base;
	148	struct regmap *regmap_pull;
	149	struct clk *clk;
	150	struct clk *db_clk;
	151	int irq;
	152	u32 saved_masks;
	153	u32 pin_base;
	154	u8 nr_pins;
	155	char *name;
	156	u8 bank_num;
	157	struct rockchip_iomux iomux[4];
	158	struct rockchip_drv drv[4];
	159	enum rockchip_pin_pull_type pull_type[4];
	160	bool valid;
	161	struct device_node *of_node;
	162	struct rockchip_pinctrl *drvdata;
	163	struct irq_domain *domain;
	164	struct gpio_chip gpio_chip;
	165	struct pinctrl_gpio_range grange;
	166	raw_spinlock_t slock;
	167	const struct rockchip_gpio_regs *gpio_regs;
	168	u32 gpio_type;
	169	u32 toggle_edge_mode;
	170	u32 recalced_mask;
	171	u32 route_mask;
	172	};
	173
	174	/**
	175	* struct rockchip_mux_recalced_data: represent a pin iomux data.
	176	* @num: bank number.
	177	* @pin: pin number.
	178	* @bit: index at register.
	179	* @reg: register offset.
	180	* @mask: mask bit
	181	*/
	182	struct rockchip_mux_recalced_data {
	183	u8 num;
	184	u8 pin;
	185	u32 reg;
	186	u8 bit;
	187	u8 mask;
	188	};
	189
	190	enum rockchip_mux_route_location {
	191	ROCKCHIP_ROUTE_SAME = 0,
	192	ROCKCHIP_ROUTE_PMU,
	193	ROCKCHIP_ROUTE_GRF,
	194	};
	195
	196	/**
	197	* struct rockchip_mux_recalced_data: represent a pin iomux data.
	198	* @bank_num: bank number.
	199	* @pin: index at register or used to calc index.
	200	* @func: the min pin.
	201	* @route_location: the mux route location (same, pmu, grf).
	202	* @route_offset: the max pin.
	203	* @route_val: the register offset.
	204	*/
	205	struct rockchip_mux_route_data {
	206	u8 bank_num;
	207	u8 pin;
	208	u8 func;
	209	enum rockchip_mux_route_location route_location;
	210	u32 route_offset;
	211	u32 route_val;
	212	};
	213
	214	struct rockchip_pin_ctrl {
	215	struct rockchip_pin_bank *pin_banks;
	216	u32 nr_banks;
	217	u32 nr_pins;
	218	char *label;
	219	enum rockchip_pinctrl_type type;
	220	int grf_mux_offset;
	221	int pmu_mux_offset;
	222	int grf_drv_offset;
	223	int pmu_drv_offset;
	224	struct rockchip_mux_recalced_data *iomux_recalced;
	225	u32 niomux_recalced;
	226	struct rockchip_mux_route_data *iomux_routes;
	227	u32 niomux_routes;
	228
	229	void (pull_calc_reg)(struct rockchip_pin_bank bank,
	230	int pin_num, struct regmap **regmap,
	231	int reg, u8 bit);
	232	void (drv_calc_reg)(struct rockchip_pin_bank bank,
	233	int pin_num, struct regmap **regmap,
	234	int reg, u8 bit);
	235	int (schmitt_calc_reg)(struct rockchip_pin_bank bank,
	236	int pin_num, struct regmap **regmap,
	237	int reg, u8 bit);
	238	};
	239
	240	struct rockchip_pin_config {
	241	unsigned int func;
	242	unsigned long *configs;
	243	unsigned int nconfigs;
	244	};
	245
	246	/**
	247	* struct rockchip_pin_group: represent group of pins of a pinmux function.
	248	* @name: name of the pin group, used to lookup the group.
	249	* @pins: the pins included in this group.
	250	* @npins: number of pins included in this group.
	251	* @data: local pin configuration
	252	*/
	253	struct rockchip_pin_group {
	254	const char *name;
	255	unsigned int npins;
	256	unsigned int *pins;
	257	struct rockchip_pin_config *data;
	258	};
	259
	260	/**
	261	* struct rockchip_pmx_func: represent a pin function.
	262	* @name: name of the pin function, used to lookup the function.
	263	* @groups: one or more names of pin groups that provide this function.
	264	* @ngroups: number of groups included in @groups.
	265	*/
	266	struct rockchip_pmx_func {
	267	const char *name;
	268	const char **groups;
	269	u8 ngroups;
	270	};
	271
	272	struct rockchip_pinctrl {
	273	struct regmap *regmap_base;
	274	int reg_size;
	275	struct regmap *regmap_pull;
	276	struct regmap *regmap_pmu;
	277	struct device *dev;
	278	struct rockchip_pin_ctrl *ctrl;
	279	struct pinctrl_desc pctl;
	280	struct pinctrl_dev *pctl_dev;
	281	struct rockchip_pin_group *groups;
	282	unsigned int ngroups;
	283	struct rockchip_pmx_func *functions;
	284	unsigned int nfunctions;
	285	};
	286
	287	#endif

drivers/pinctrl/pinctrl-single.c+2−2

@@ -1491,8 +1491,8 @@ static int pcs_irq_handle(struct pcs_soc_data *pcs_soc) · 1490 unmodified lines
1491	mask = pcs->read(pcswi->reg);	1491	mask = pcs->read(pcswi->reg);
1492	raw_spin_unlock(&pcs->lock);	1492	raw_spin_unlock(&pcs->lock);
1493	if (mask & pcs_soc->irq_status_mask) {	1493	if (mask & pcs_soc->irq_status_mask) {
1494	generic_handle_irq(irq_find_mapping(pcs->domain,	1494	generic_handle_domain_irq(pcs->domain,
1495	pcswi->hwirq));	1495	pcswi->hwirq);
1496	count++;	1496	count++;
1497	}	1497	}
1498	}	1498	}

drivers/pinctrl/pinctrl-st.c+1−1

@@ -1420,7 +1420,7 @@ static void __gpio_irq_handler(struct st_gpio_bank *bank) · 1419 unmodified lines
1420	continue;	1420	continue;
1421	}	1421	}
1422		1422
1423	generic_handle_irq(irq_find_mapping(bank->gpio_chip.irq.domain, n));	1423	generic_handle_domain_irq(bank->gpio_chip.irq.domain, n);
1424	}	1424	}
1425	}	1425	}
1426	}	1426	}

drivers/pinctrl/qcom/pinctrl-msm.c+1−3

 	const struct msm_pingroup *g;
 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
 	struct irq_chip *chip = irq_desc_get_chip(desc);
-	int irq_pin;
 	int handled = 0;
 	u32 val;
 	int i;
 		g = &pctrl->soc->groups[i];
 		val = msm_readl_intr_status(pctrl, g);
 		if (val & BIT(g->intr_status_bit)) {
-			irq_pin = irq_find_mapping(gc->irq.domain, i);
+			generic_handle_domain_irq(gc->irq.domain, i);
-			generic_handle_irq(irq_pin);
 			handled++;
 		}
 	}

drivers/pinctrl/samsung/pinctrl-exynos.c+7−8

@@ -246,7 +246,8 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) · 245 unmodified lines
246	{	246	{
247	struct samsung_pinctrl_drv_data *d = data;	247	struct samsung_pinctrl_drv_data *d = data;
248	struct samsung_pin_bank *bank = d->pin_banks;	248	struct samsung_pin_bank *bank = d->pin_banks;
249	unsigned int svc, group, pin, virq;	249	unsigned int svc, group, pin;
		250	int ret;
250		251
251	svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);	252	svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);
252	group = EXYNOS_SVC_GROUP(svc);	253	group = EXYNOS_SVC_GROUP(svc);
@@ -256,10 +257,10 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) · 3 unmodified lines
256	return IRQ_HANDLED;	257	return IRQ_HANDLED;
257	bank += (group - 1);	258	bank += (group - 1);
258		259
259	virq = irq_linear_revmap(bank->irq_domain, pin);	260	ret = generic_handle_domain_irq(bank->irq_domain, pin);
260	if (!virq)	261	if (ret)
261	return IRQ_NONE;	262	return IRQ_NONE;
262	generic_handle_irq(virq);	263
263	return IRQ_HANDLED;	264	return IRQ_HANDLED;
264	}	265	}
265		266
@@ -473,12 +474,10 @@ static void exynos_irq_eint0_15(struct irq_desc *desc) · 207 unmodified lines
473	struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc);	474	struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc);
474	struct samsung_pin_bank *bank = eintd->bank;	475	struct samsung_pin_bank *bank = eintd->bank;
475	struct irq_chip *chip = irq_desc_get_chip(desc);	476	struct irq_chip *chip = irq_desc_get_chip(desc);
476	int eint_irq;
477		477
478	chained_irq_enter(chip, desc);	478	chained_irq_enter(chip, desc);
479		479
480	eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq);	480	generic_handle_domain_irq(bank->irq_domain, eintd->irq);
481	generic_handle_irq(eint_irq);
482		481
483	chained_irq_exit(chip, desc);	482	chained_irq_exit(chip, desc);
484	}	483	}
@@ -490,7 +489,7 @@ static inline void exynos_irq_demux_eint(unsigned int pend, · 5 unmodified lines
490		489
491	while (pend) {	490	while (pend) {
492	irq = fls(pend) - 1;	491	irq = fls(pend) - 1;
493	generic_handle_irq(irq_find_mapping(domain, irq));	492	generic_handle_domain_irq(domain, irq);
494	pend &= ~(1 << irq);	493	pend &= ~(1 << irq);
495	}	494	}
496	}	495	}

drivers/pinctrl/samsung/pinctrl-s3c24xx.c+10−15

 {
 	struct irq_data *data = irq_desc_get_irq_data(desc);
 	struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc);
-	unsigned int virq;
+	int ret;
 	/* the first 4 eints have a simple 1 to 1 mapping */
-	virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq);
+	ret = generic_handle_domain_irq(eint_data->domains[data->hwirq], data->hwirq);
 	/* Something must be really wrong if an unmapped EINT is unmasked */
-	BUG_ON(!virq);
+	BUG_ON(ret);
-	generic_handle_irq(virq);
 }
 /* Handling of EINTs 0-3 on S3C2412 and S3C2413 */
 	struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc);
 	struct irq_data *data = irq_desc_get_irq_data(desc);
 	struct irq_chip *chip = irq_data_get_irq_chip(data);
-	unsigned int virq;
+	int ret;
 	chained_irq_enter(chip, desc);
 	/* the first 4 eints have a simple 1 to 1 mapping */
-	virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq);
+	ret = generic_handle_domain_irq(eint_data->domains[data->hwirq], data->hwirq);
 	/* Something must be really wrong if an unmapped EINT is unmasked */
-	BUG_ON(!virq);
+	BUG_ON(ret);
-	generic_handle_irq(virq);
 	chained_irq_exit(chip, desc);
 }
 	pend &= range;
 	while (pend) {
-		unsigned int virq, irq;
+		unsigned int irq;
+		int ret;
 		irq = __ffs(pend);
 		pend &= ~(1 << irq);
-		virq = irq_linear_revmap(data->domains[irq], irq - offset);
+		ret = generic_handle_domain_irq(data->domains[irq], irq - offset);
 		/* Something is really wrong if an unmapped EINT is unmasked */
-		BUG_ON(!virq);
+		BUG_ON(ret);
-		generic_handle_irq(virq);
 	}
 	chained_irq_exit(chip, desc);

drivers/pinctrl/samsung/pinctrl-s3c64xx.c+7−10

 		unsigned int svc;
 		unsigned int group;
 		unsigned int pin;
-		unsigned int virq;
+		int ret;
 		svc = readl(drvdata->virt_base + SERVICE_REG);
 		group = SVC_GROUP(svc);
 				pin -= 8;
 		}
-		virq = irq_linear_revmap(data->domains[group], pin);
+		ret = generic_handle_domain_irq(data->domains[group], pin);
 		/*
 		 * Something must be really wrong if an unmapped EINT
 		 * was unmasked...
 		 */
-		BUG_ON(!virq);
+		BUG_ON(ret);
-		generic_handle_irq(virq);
 	} while (1);
 	chained_irq_exit(chip, desc);
 	pend &= range;
 	while (pend) {
-		unsigned int virq, irq;
+		unsigned int irq;
+		int ret;
 		irq = fls(pend) - 1;
 		pend &= ~(1 << irq);
-		virq = irq_linear_revmap(data->domains[irq], data->pins[irq]);
+		ret = generic_handle_domain_irq(data->domains[irq], data->pins[irq]);
 		/*
 		 * Something must be really wrong if an unmapped EINT
 		 * was unmasked...
 		 */
-		BUG_ON(!virq);
+		BUG_ON(ret);
-		generic_handle_irq(virq);
 	}
 	chained_irq_exit(chip, desc);

drivers/pinctrl/spear/pinctrl-plgpio.c+1−2

@@ -400,8 +400,7 @@ static void plgpio_irq_handler(struct irq_desc *desc) · 399 unmodified lines
400		400
401	/* get correct irq line number */	401	/* get correct irq line number */
402	pin = i * MAX_GPIO_PER_REG + pin;	402	pin = i * MAX_GPIO_PER_REG + pin;
403	generic_handle_irq(	403	generic_handle_domain_irq(gc->irq.domain, pin);
404	irq_find_mapping(gc->irq.domain, pin));
405	}	404	}
406	}	405	}
407	chained_irq_exit(irqchip, desc);	406	chained_irq_exit(irqchip, desc);

drivers/pinctrl/sunxi/pinctrl-sunxi.c+3−5

 	if (val) {
 		int irqoffset;
-		for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) {
+		for_each_set_bit(irqoffset, &val, IRQ_PER_BANK)
-			int pin_irq = irq_find_mapping(pctl->domain,
+			generic_handle_domain_irq(pctl->domain,
-						       bank * IRQ_PER_BANK + irqoffset);
+						  bank * IRQ_PER_BANK + irqoffset);
-			generic_handle_irq(pin_irq);
-		}
 	}
 	chained_irq_exit(chip, desc);

kernel/irq/irqdomain.c+1−0

@@ -1215,6 +1215,7 @@ int irq_domain_disconnect_hierarchy(struct irq_domain *domain, · 1214 unmodified lines
1215	irqd->chip = ERR_PTR(-ENOTCONN);	1215	irqd->chip = ERR_PTR(-ENOTCONN);
1216	return 0;	1216	return 0;
1217	}	1217	}
		1218	EXPORT_SYMBOL_GPL(irq_domain_disconnect_hierarchy);
1218		1219
1219	static int irq_domain_trim_hierarchy(unsigned int virq)	1220	static int irq_domain_trim_hierarchy(unsigned int virq)
1220	{	1221	{