Pull drm updates from Dave Airlie: "Highlights are usual, more AMD IP blocks for future hw, i915/xe changes, Displayport tunnelling support for i915, msm YUV over DP changes, new tests for ttm, but its mostly a lot of stuff all over the place from lots of people. core: - EDID cleanups - scheduler error handling fixes - managed: add drmm_release_action() with tests - add ratelimited drm debug print - DPCD PSR early transport macro - DP tunneling and bandwidth allocation helpers - remove built-in edids - dp: Avoid AUX transfers on powered-down displays - dp: Add VSC SDP helpers cross drivers: - use new drm print helpers - switch to ->read_edid callback - gem: add stats for shared buffers plus updates to amdgpu, i915, xe syncobj: - fixes to waiting and sleeping ttm: - add tests - fix errno codes - simply busy-placement handling - fix page decryption media: - tc358743: fix v4l device registration video: - move all kernel parameters for video behind CONFIG_VIDEO sound: - remove <drm/drm_edid.h> include from header ci: - add tests for msm - fix apq8016 runner efifb: - use copy of global screen_info state vesafb: - use copy of global screen_info state simplefb: - fix logging bridge: - ite-6505: fix DP link-training bug - samsung-dsim: fix error checking in probe - samsung-dsim: add bsh-smm-s2/pro boards - tc358767: fix regmap usage - imx: add i.MX8MP HDMI PVI plus DT bindings - imx: add i.MX8MP HDMI TX plus DT bindings - sii902x: fix probing and unregistration - tc358767: limit pixel PLL input range - switch to new drm_bridge_read_edid() interface panel: - ltk050h3146w: error-handling fixes - panel-edp: support delay between power-on and enable; use put_sync in unprepare; support Mediatek MT8173 Chromebooks, BOE NV116WHM-N49 V8.0, BOE NV122WUM-N41, CSO MNC207QS1-1 plus DT bindings - panel-lvds: support EDT ETML0700Z9NDHA plus DT bindings - panel-novatek: FRIDA FRD400B25025-A-CTK plus DT bindings - add BOE TH101MB31IG002-28A plus DT bindings - add EDT ETML1010G3DRA plus DT bindings - add Novatek NT36672E LCD DSI plus DT bindings - nt36523: support 120Hz timings, fix includes - simple: fix display timings on RK32FN48H - visionox-vtdr6130: fix initialization - add Powkiddy RGB10MAX3 plus DT bindings - st7703: support panel rotation plus DT bindings - add Himax HX83112A plus DT bindings - ltk500hd1829: add support for ltk101b4029w and admatec 9904370 - simple: add BOE BP082WX1-100 8.2" panel plus DT bindungs panel-orientation-quirks: - GPD Win Mini amdgpu: - Validate DMABuf imports in compute VMs - Add RAS ACA framework - PSP 13 fixes - Misc code cleanups - Replay fixes - Atom interpretor PS, WS bounds checking - DML2 fixes - Audio fixes - DCN 3.5 Z state fixes - Remove deprecated ida_simple usage - UBSAN fixes - RAS fixes - Enable seq64 infrastructure - DC color block enablement - Documentation updates - DC documentation updates - DMCUB updates - ATHUB 4.1 support - LSDMA 7.0 support - JPEG DPG support - IH 7.0 support - HDP 7.0 support - VCN 5.0 support - SMU 13.0.6 updates - NBIO 7.11 updates - SDMA 6.1 updates - MMHUB 3.3 updates - DCN 3.5.1 support - NBIF 6.3.1 support - VPE 6.1.1 support amdkfd: - Validate DMABuf imports in compute VMs - SVM fixes - Trap handler updates and enhancements - Fix cache size reporting - Relocate the trap handler radeon: - Atom interpretor PS, WS bounds checking - Misc code cleanups xe: - new query for GuC submission version - Remove unused persistent exec_queues - Add vram frequency sysfs attributes - Add the flag XE_VM_BIND_FLAG_DUMPABLE - Drop pre-production workarounds - Drop kunit tests for unsupported platforms - Start pumbling SR-IOV support with memory based interrupts for VF - Allow to map BO in GGTT with PAT index corresponding to XE_CACHE_UC to work with memory based interrupts - Add GuC Doorbells Manager as prep work SR-IOV - Implement additional workarounds for xe2 and MTL - Program a few registers according to perfomance guide spec for Xe2 - Fix remaining 32b build issues and enable it back - Fix build with CONFIG_DEBUG_FS=n - Fix warnings from GuC ABI headers - Introduce Relay Communication for SR-IOV for VF <-> GuC <-> PF - Release mmap mappings on rpm suspend - Disable mid-thread preemption when not properly supported by hardware - Fix xe_exec by reserving extra fence slot for CPU bind - Fix xe_exec with full long running exec queue - Canonicalize addresses where needed for Xe2 and add to devcoredum - Toggle USM support for Xe2 - Only allow 1 ufence per exec / bind IOCTL - Add GuC firmware loading for Lunar Lake - Add XE_VMA_PTE_64K VMA flag i915: - Add more ADL-N PCI IDs - Enable fastboot also on older platforms - Early transport for panel replay and PSR - New ARL PCI IDs - DP TPS4 PHY test pattern support - Unify and improve VSC SDP for PSR and non-PSR cases - Refactor memory regions and improve debug logging - Rework global state serialization - Remove unused CDCLK divider fields - Unify HDCP connector logging format - Use display instead of graphics version in display code - Move VBT and opregion debugfs next to the implementation - Abstract opregion interface, use opaque type - MTL fixes - HPD handling fixes - Add GuC submission interface version query - Atomically invalidate userptr on mmu-notifier - Update handling of MMIO triggered reports - Don't make assumptions about intel_wakeref_t type - Extend driver code of Xe_LPG to Xe_LPG+ - Add flex arrays to struct i915_syncmap - Allow for very slow HuC loading - DP tunneling and bandwidth allocation support msm: - Correct bindings for MSM8976 and SM8650 platforms - Start migration of MDP5 platforms to DPU driver - X1E80100 MDSS support - DPU: - Improve DSC allocation, fixing several important corner cases - Add support for SDM630/SDM660 platforms - Simplify dpu_encoder_phys_ops - Apply fixes targeting DSC support with a single DSC encoder - Apply fixes for HCTL_EN timing configuration - X1E80100 support - Add support for YUV420 over DP - GPU: - fix sc7180 UBWC config - fix a7xx LLC config - new gpu support: a305B, a750, a702 - machine support: SM7150 (different power levels than other a618) - a7xx devcoredump support habanalabs: - configure IRQ affinity according to NUMA node - move HBM MMU page tables inside the HBM - improve device reset - check extended PCIe errors ivpu: - updates to firmware API - refactor BO allocation imx: - use devm_ functions during init hisilicon: - fix EDID includes mgag200: - improve ioremap usage - convert to struct drm_edid - Work around PCI write bursts nouveau: - disp: use kmemdup() - fix EDID includes - documentation fixes qaic: - fixes to BO handling - make use of DRM managed release - fix order of remove operations rockchip: - analogix_dp: get encoder port from DT - inno_hdmi: support HDMI for RK3128 - lvds: error-handling fixes ssd130x: - support SSD133x plus DT bindings tegra: - fix error handling tilcdc: - make use of DRM managed release v3d: - show memory stats in debugfs - Support display MMU page size vc4: - fix error handling in plane prepare_fb - fix framebuffer test in plane helpers virtio: - add venus capset defines vkms: - fix OOB access when programming the LUT - Kconfig improvements vmwgfx: - unmap surface before changing plane state - fix memory leak in error handling - documentation fixes - list command SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 as invalid - fix null-pointer deref in execbuf - refactor display-mode probing - fix fencing for creating cursor MOBs - fix cursor-memory lifetime xlnx: - fix live video input for ZynqMP DPSUB lima: - fix memory leak loongson: - fail if no VRAM present meson: - switch to new drm_bridge_read_edid() interface renesas: - add RZ/G2L DU support plus DT bindings mxsfb: - Use managed mode config sun4i: - HDMI: updates to atomic mode setting mediatek: - Add display driver for MT8188 VDOSYS1 - DSI driver cleanups - Filter modes according to hardware capability - Fix a null pointer crash in mtk_drm_crtc_finish_page_flip etnaviv: - enhancements for NPU and MRT support" * tag 'drm-next-2024-03-13' of https://gitlab.freedesktop.org/drm/kernel: (1420 commits) drm/amd/display: Removed redundant @ symbol to fix kernel-doc warnings in -next repo drm/amd/pm: wait for completion of the EnableGfxImu message drm/amdgpu/soc21: add mode2 asic reset for SMU IP v14.0.1 drm/amdgpu: add smu 14.0.1 support drm/amdgpu: add VPE 6.1.1 discovery support drm/amdgpu/vpe: add VPE 6.1.1 support drm/amdgpu/vpe: don't emit cond exec command under collaborate mode drm/amdgpu/vpe: add collaborate mode support for VPE drm/amdgpu/vpe: add PRED_EXE and COLLAB_SYNC OPCODE drm/amdgpu/vpe: add multi instance VPE support drm/amdgpu/discovery: add nbif v6_3_1 ip block drm/amdgpu: Add nbif v6_3_1 ip block support drm/amdgpu: Add pcie v6_1_0 ip headers (v5) drm/amdgpu: Add nbif v6_3_1 ip headers (v5) arch/powerpc: Remove <linux/fb.h> from backlight code macintosh/via-pmu-backlight: Include <linux/backlight.h> fbdev/chipsfb: Include <linux/backlight.h> drm/etnaviv: Restore some id values drm/amdkfd: make kfd_class constant drm/amdgpu: add ring timeout information in devcoredump ...
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| @@ -865,6 +865,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow { · 864 unmodified lines | |||
| 865 | #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa | 865 | #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa |
| 866 | /* Subquery id: Query GPU peak pstate memory clock */ | 866 | /* Subquery id: Query GPU peak pstate memory clock */ |
| 867 | #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb | 867 | #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb |
| 868 | /* Subquery id: Query input GPU power */ | ||
| 869 | #define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc | ||
| 868 | /* Number of VRAM page faults on CPU access. */ | 870 | /* Number of VRAM page faults on CPU access. */ |
| 869 | #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E | 871 | #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E |
| 870 | #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F | 872 | #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F |
| @@ -77,6 +77,11 @@ struct drm_etnaviv_timespec { · 76 unmodified lines | |||
| 77 | #define ETNAVIV_PARAM_GPU_PRODUCT_ID 0x1c | 77 | #define ETNAVIV_PARAM_GPU_PRODUCT_ID 0x1c |
| 78 | #define ETNAVIV_PARAM_GPU_CUSTOMER_ID 0x1d | 78 | #define ETNAVIV_PARAM_GPU_CUSTOMER_ID 0x1d |
| 79 | #define ETNAVIV_PARAM_GPU_ECO_ID 0x1e | 79 | #define ETNAVIV_PARAM_GPU_ECO_ID 0x1e |
| 80 | #define ETNAVIV_PARAM_GPU_NN_CORE_COUNT 0x1f | ||
| 81 | #define ETNAVIV_PARAM_GPU_NN_MAD_PER_CORE 0x20 | ||
| 82 | #define ETNAVIV_PARAM_GPU_TP_CORE_COUNT 0x21 | ||
| 83 | #define ETNAVIV_PARAM_GPU_ON_CHIP_SRAM_SIZE 0x22 | ||
| 84 | #define ETNAVIV_PARAM_GPU_AXI_SRAM_SIZE 0x23 | ||
| 80 | 85 | ||
| 81 | #define ETNA_MAX_PIPES 4 | 86 | #define ETNA_MAX_PIPES 4 |
| 82 | 87 | ||
| @@ -3013,6 +3013,7 @@ struct drm_i915_query_item { · 3012 unmodified lines | |||
| 3013 | * - %DRM_I915_QUERY_MEMORY_REGIONS (see struct drm_i915_query_memory_regions) | 3013 | * - %DRM_I915_QUERY_MEMORY_REGIONS (see struct drm_i915_query_memory_regions) |
| 3014 | * - %DRM_I915_QUERY_HWCONFIG_BLOB (see `GuC HWCONFIG blob uAPI`) | 3014 | * - %DRM_I915_QUERY_HWCONFIG_BLOB (see `GuC HWCONFIG blob uAPI`) |
| 3015 | * - %DRM_I915_QUERY_GEOMETRY_SUBSLICES (see struct drm_i915_query_topology_info) | 3015 | * - %DRM_I915_QUERY_GEOMETRY_SUBSLICES (see struct drm_i915_query_topology_info) |
| 3016 | * - %DRM_I915_QUERY_GUC_SUBMISSION_VERSION (see struct drm_i915_query_guc_submission_version) | ||
| 3016 | */ | 3017 | */ |
| 3017 | __u64 query_id; | 3018 | __u64 query_id; |
| 3018 | #define DRM_I915_QUERY_TOPOLOGY_INFO 1 | 3019 | #define DRM_I915_QUERY_TOPOLOGY_INFO 1 |
| @@ -3021,6 +3022,7 @@ struct drm_i915_query_item { · 2 unmodified lines | |||
| 3021 | #define DRM_I915_QUERY_MEMORY_REGIONS 4 | 3022 | #define DRM_I915_QUERY_MEMORY_REGIONS 4 |
| 3022 | #define DRM_I915_QUERY_HWCONFIG_BLOB 5 | 3023 | #define DRM_I915_QUERY_HWCONFIG_BLOB 5 |
| 3023 | #define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6 | 3024 | #define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6 |
| 3025 | #define DRM_I915_QUERY_GUC_SUBMISSION_VERSION 7 | ||
| 3024 | /* Must be kept compact -- no holes and well documented */ | 3026 | /* Must be kept compact -- no holes and well documented */ |
| 3025 | 3027 | ||
| 3026 | /** | 3028 | /** |
| @@ -3566,6 +3568,20 @@ struct drm_i915_query_memory_regions { · 539 unmodified lines | |||
| 3566 | struct drm_i915_memory_region_info regions[]; | 3568 | struct drm_i915_memory_region_info regions[]; |
| 3567 | }; | 3569 | }; |
| 3568 | 3570 | ||
| 3571 | /** | ||
| 3572 | * struct drm_i915_query_guc_submission_version - query GuC submission interface version | ||
| 3573 | */ | ||
| 3574 | struct drm_i915_query_guc_submission_version { | ||
| 3575 | /** @branch: Firmware branch version. */ | ||
| 3576 | __u32 branch; | ||
| 3577 | /** @major: Firmware major version. */ | ||
| 3578 | __u32 major; | ||
| 3579 | /** @minor: Firmware minor version. */ | ||
| 3580 | __u32 minor; | ||
| 3581 | /** @patch: Firmware patch version. */ | ||
| 3582 | __u32 patch; | ||
| 3583 | }; | ||
| 3584 | |||
| 3569 | /** | 3585 | /** |
| 3570 | * DOC: GuC HWCONFIG blob uAPI | 3586 | * DOC: GuC HWCONFIG blob uAPI |
| 3571 | * | 3587 | * |
| @@ -252,34 +252,32 @@ struct drm_nouveau_vm_init { · 251 unmodified lines | |||
| 252 | struct drm_nouveau_vm_bind_op { | 252 | struct drm_nouveau_vm_bind_op { |
| 253 | /** | 253 | /** |
| 254 | * @op: the operation type | 254 | * @op: the operation type |
| 255 | * | ||
| 256 | * Supported values: | ||
| 257 | * | ||
| 258 | * %DRM_NOUVEAU_VM_BIND_OP_MAP - Map a GEM object to the GPU's VA | ||
| 259 | * space. Optionally, the &DRM_NOUVEAU_VM_BIND_SPARSE flag can be | ||
| 260 | * passed to instruct the kernel to create sparse mappings for the | ||
| 261 | * given range. | ||
| 262 | * | ||
| 263 | * %DRM_NOUVEAU_VM_BIND_OP_UNMAP - Unmap an existing mapping in the | ||
| 264 | * GPU's VA space. If the region the mapping is located in is a | ||
| 265 | * sparse region, new sparse mappings are created where the unmapped | ||
| 266 | * (memory backed) mapping was mapped previously. To remove a sparse | ||
| 267 | * region the &DRM_NOUVEAU_VM_BIND_SPARSE must be set. | ||
| 255 | */ | 268 | */ |
| 256 | __u32 op; | 269 | __u32 op; |
| 257 | /** | ||
| 258 | * @DRM_NOUVEAU_VM_BIND_OP_MAP: | ||
| 259 | * | ||
| 260 | * Map a GEM object to the GPU's VA space. Optionally, the | ||
| 261 | * &DRM_NOUVEAU_VM_BIND_SPARSE flag can be passed to instruct the kernel to | ||
| 262 | * create sparse mappings for the given range. | ||
| 263 | */ | ||
| 264 | #define DRM_NOUVEAU_VM_BIND_OP_MAP 0x0 | 270 | #define DRM_NOUVEAU_VM_BIND_OP_MAP 0x0 |
| 265 | /** | ||
| 266 | * @DRM_NOUVEAU_VM_BIND_OP_UNMAP: | ||
| 267 | * | ||
| 268 | * Unmap an existing mapping in the GPU's VA space. If the region the mapping | ||
| 269 | * is located in is a sparse region, new sparse mappings are created where the | ||
| 270 | * unmapped (memory backed) mapping was mapped previously. To remove a sparse | ||
| 271 | * region the &DRM_NOUVEAU_VM_BIND_SPARSE must be set. | ||
| 272 | */ | ||
| 273 | #define DRM_NOUVEAU_VM_BIND_OP_UNMAP 0x1 | 271 | #define DRM_NOUVEAU_VM_BIND_OP_UNMAP 0x1 |
| 274 | /** | 272 | /** |
| 275 | * @flags: the flags for a &drm_nouveau_vm_bind_op | 273 | * @flags: the flags for a &drm_nouveau_vm_bind_op |
| 274 | * | ||
| 275 | * Supported values: | ||
| 276 | * | ||
| 277 | * %DRM_NOUVEAU_VM_BIND_SPARSE - Indicates that an allocated VA | ||
| 278 | * space region should be sparse. | ||
| 276 | */ | 279 | */ |
| 277 | __u32 flags; | 280 | __u32 flags; |
| 278 | /** | ||
| 279 | * @DRM_NOUVEAU_VM_BIND_SPARSE: | ||
| 280 | * | ||
| 281 | * Indicates that an allocated VA space region should be sparse. | ||
| 282 | */ | ||
| 283 | #define DRM_NOUVEAU_VM_BIND_SPARSE (1 << 8) | 281 | #define DRM_NOUVEAU_VM_BIND_SPARSE (1 << 8) |
| 284 | /** | 282 | /** |
| 285 | * @handle: the handle of the DRM GEM object to map | 283 | * @handle: the handle of the DRM GEM object to map |
| @@ -315,17 +313,17 @@ struct drm_nouveau_vm_bind { · 29 unmodified lines | |||
| 315 | __u32 op_count; | 313 | __u32 op_count; |
| 316 | /** | 314 | /** |
| 317 | * @flags: the flags for a &drm_nouveau_vm_bind ioctl | 315 | * @flags: the flags for a &drm_nouveau_vm_bind ioctl |
| 316 | * | ||
| 317 | * Supported values: | ||
| 318 | * | ||
| 319 | * %DRM_NOUVEAU_VM_BIND_RUN_ASYNC - Indicates that the given VM_BIND | ||
| 320 | * operation should be executed asynchronously by the kernel. | ||
| 321 | * | ||
| 322 | * If this flag is not supplied the kernel executes the associated | ||
| 323 | * operations synchronously and doesn't accept any &drm_nouveau_sync | ||
| 324 | * objects. | ||
| 318 | */ | 325 | */ |
| 319 | __u32 flags; | 326 | __u32 flags; |
| 320 | /** | ||
| 321 | * @DRM_NOUVEAU_VM_BIND_RUN_ASYNC: | ||
| 322 | * | ||
| 323 | * Indicates that the given VM_BIND operation should be executed asynchronously | ||
| 324 | * by the kernel. | ||
| 325 | * | ||
| 326 | * If this flag is not supplied the kernel executes the associated operations | ||
| 327 | * synchronously and doesn't accept any &drm_nouveau_sync objects. | ||
| 328 | */ | ||
| 329 | #define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1 | 327 | #define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1 |
| 330 | /** | 328 | /** |
| 331 | * @wait_count: the number of wait &drm_nouveau_syncs | 329 | * @wait_count: the number of wait &drm_nouveau_syncs |
| @@ -242,18 +242,7 @@ struct qaic_attach_slice_entry { · 241 unmodified lines | |||
| 242 | * @dbc_id: In. Associate the sliced BO with this DBC. | 242 | * @dbc_id: In. Associate the sliced BO with this DBC. |
| 243 | * @handle: In. GEM handle of the BO to slice. | 243 | * @handle: In. GEM handle of the BO to slice. |
| 244 | * @dir: In. Direction of data flow. 1 = DMA_TO_DEVICE, 2 = DMA_FROM_DEVICE | 244 | * @dir: In. Direction of data flow. 1 = DMA_TO_DEVICE, 2 = DMA_FROM_DEVICE |
| 245 | * @size: In. Total length of BO being used. This should not exceed base | 245 | * @size: Deprecated. This value is ignored and size of @handle is used instead. |
| 246 | * size of BO (struct drm_gem_object.base) | ||
| 247 | * For BOs being allocated using DRM_IOCTL_QAIC_CREATE_BO, size of | ||
| 248 | * BO requested is PAGE_SIZE aligned then allocated hence allocated | ||
| 249 | * BO size maybe bigger. This size should not exceed the new | ||
| 250 | * PAGE_SIZE aligned BO size. | ||
| 251 | * @dev_addr: In. Device address this slice pushes to or pulls from. | ||
| 252 | * @db_addr: In. Address of the doorbell to ring. | ||
| 253 | * @db_data: In. Data to write to the doorbell. | ||
| 254 | * @db_len: In. Size of the doorbell data in bits - 32, 16, or 8. 0 is for | ||
| 255 | * inactive doorbells. | ||
| 256 | * @offset: In. Start of this slice as an offset from the start of the BO. | ||
| 257 | */ | 246 | */ |
| 258 | struct qaic_attach_slice_hdr { | 247 | struct qaic_attach_slice_hdr { |
| 259 | __u32 count; | 248 | __u32 count; |
| @@ -1,6 +1,7 @@ | |||
| 1 | /* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR MIT */ | ||
| 1 | /************************************************************************** | 2 | /************************************************************************** |
| 2 | * | 3 | * |
| 3 | * Copyright © 2009-2022 VMware, Inc., Palo Alto, CA., USA | 4 | * Copyright © 2009-2023 VMware, Inc., Palo Alto, CA., USA |
| 4 | * All Rights Reserved. | 5 | * All Rights Reserved. |
| 5 | * | 6 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a | 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
| @@ -902,7 +903,8 @@ struct drm_vmw_shader_arg { · 895 unmodified lines | |||
| 902 | /** | 903 | /** |
| 903 | * enum drm_vmw_surface_flags | 904 | * enum drm_vmw_surface_flags |
| 904 | * | 905 | * |
| 905 | * @drm_vmw_surface_flag_shareable: Whether the surface is shareable | 906 | * @drm_vmw_surface_flag_shareable: Deprecated - all userspace surfaces are |
| 907 | * shareable. | ||
| 906 | * @drm_vmw_surface_flag_scanout: Whether the surface is a scanout | 908 | * @drm_vmw_surface_flag_scanout: Whether the surface is a scanout |
| 907 | * surface. | 909 | * surface. |
| 908 | * @drm_vmw_surface_flag_create_buffer: Create a backup buffer if none is | 910 | * @drm_vmw_surface_flag_create_buffer: Create a backup buffer if none is |
| @@ -574,6 +574,36 @@ struct drm_xe_query_engine_cycles { · 573 unmodified lines | |||
| 574 | __u64 cpu_delta; | 574 | __u64 cpu_delta; |
| 575 | }; | 575 | }; |
| 576 | 576 | ||
| 577 | /** | ||
| 578 | * struct drm_xe_query_uc_fw_version - query a micro-controller firmware version | ||
| 579 | * | ||
| 580 | * Given a uc_type this will return the branch, major, minor and patch version | ||
| 581 | * of the micro-controller firmware. | ||
| 582 | */ | ||
| 583 | struct drm_xe_query_uc_fw_version { | ||
| 584 | /** @uc_type: The micro-controller type to query firmware version */ | ||
| 585 | #define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0 | ||
| 586 | __u16 uc_type; | ||
| 587 | |||
| 588 | /** @pad: MBZ */ | ||
| 589 | __u16 pad; | ||
| 590 | |||
| 591 | /** @branch_ver: branch uc fw version */ | ||
| 592 | __u32 branch_ver; | ||
| 593 | /** @major_ver: major uc fw version */ | ||
| 594 | __u32 major_ver; | ||
| 595 | /** @minor_ver: minor uc fw version */ | ||
| 596 | __u32 minor_ver; | ||
| 597 | /** @patch_ver: patch uc fw version */ | ||
| 598 | __u32 patch_ver; | ||
| 599 | |||
| 600 | /** @pad2: MBZ */ | ||
| 601 | __u32 pad2; | ||
| 602 | |||
| 603 | /** @reserved: Reserved */ | ||
| 604 | __u64 reserved; | ||
| 605 | }; | ||
| 606 | |||
| 577 | /** | 607 | /** |
| 578 | * struct drm_xe_device_query - Input of &DRM_IOCTL_XE_DEVICE_QUERY - main | 608 | * struct drm_xe_device_query - Input of &DRM_IOCTL_XE_DEVICE_QUERY - main |
| 579 | * structure to query device information | 609 | * structure to query device information |
| @@ -643,6 +673,7 @@ struct drm_xe_device_query { · 63 unmodified lines | |||
| 643 | #define DRM_XE_DEVICE_QUERY_HWCONFIG 4 | 673 | #define DRM_XE_DEVICE_QUERY_HWCONFIG 4 |
| 644 | #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5 | 674 | #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5 |
| 645 | #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6 | 675 | #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6 |
| 676 | #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7 | ||
| 646 | /** @query: The type of data to query */ | 677 | /** @query: The type of data to query */ |
| 647 | __u32 query; | 678 | __u32 query; |
| 648 | 679 | ||
| @@ -40,9 +40,10 @@ · 39 unmodified lines | |||
| 40 | * - 1.12 - Add DMA buf export ioctl | 40 | * - 1.12 - Add DMA buf export ioctl |
| 41 | * - 1.13 - Add debugger API | 41 | * - 1.13 - Add debugger API |
| 42 | * - 1.14 - Update kfd_event_data | 42 | * - 1.14 - Update kfd_event_data |
| 43 | * - 1.15 - Enable managing mappings in compute VMs with GEM_VA ioctl | ||
| 43 | */ | 44 | */ |
| 44 | #define KFD_IOCTL_MAJOR_VERSION 1 | 45 | #define KFD_IOCTL_MAJOR_VERSION 1 |
| 45 | #define KFD_IOCTL_MINOR_VERSION 14 | 46 | #define KFD_IOCTL_MINOR_VERSION 15 |
| 46 | 47 | ||
| 47 | struct kfd_ioctl_get_version_args { | 48 | struct kfd_ioctl_get_version_args { |
| 48 | __u32 major_version; /* from KFD */ | 49 | __u32 major_version; /* from KFD */ |
| @@ -309,6 +309,8 @@ struct virtio_gpu_cmd_submit { · 308 unmodified lines | |||
| 309 | 309 | ||
| 310 | #define VIRTIO_GPU_CAPSET_VIRGL 1 | 310 | #define VIRTIO_GPU_CAPSET_VIRGL 1 |
| 311 | #define VIRTIO_GPU_CAPSET_VIRGL2 2 | 311 | #define VIRTIO_GPU_CAPSET_VIRGL2 2 |
| 312 | /* 3 is reserved for gfxstream */ | ||
| 313 | #define VIRTIO_GPU_CAPSET_VENUS 4 | ||
| 312 | 314 | ||
| 313 | /* VIRTIO_GPU_CMD_GET_CAPSET_INFO */ | 315 | /* VIRTIO_GPU_CMD_GET_CAPSET_INFO */ |
| 314 | struct virtio_gpu_get_capset_info { | 316 | struct virtio_gpu_get_capset_info { |