drm-intel-next-2013-09-21: - clock state handling rework from Ville - l3 parity handling fixes for hsw from Ben - some more watermark improvements from Ville - ban badly behaved context from Mika - a few vlv improvements from Jesse - VGA power domain handling from Ville drm-intel-next-2013-09-06: - Basic mipi dsi support from Jani. Not yet converted over to drm_bridge since that was too fresh, but the porting is in progress already. - More vma patches from Ben, this time the code to convert the execbuffer code. Now that the shrinker recursion bug is tracked down we can move ahead here again. Yay! - Optimize hw context switching to not generate needless interrupts (Chris Wilson). Also some shuffling for the oustanding request allocation. - Opregion support for SWSCI, although not yet fully wired up (we need a bit of runtime D3 support for that apparently, due to Windows design deficiencies), from Jani Nikula. - A few smaller changes all over. [airlied: merge conflict fix in i9xx_set_pipeconf] * tag 'drm-intel-next-2013-09-21-merged' of git://people.freedesktop.org/~danvet/drm-intel: (119 commits) drm/i915: assume all GM45 Acer laptops use inverted backlight PWM drm/i915: cleanup a min_t() cast drm/i915: Pull intel_init_power_well() out of intel_modeset_init_hw() drm/i915: Add POWER_DOMAIN_VGA drm/i915: Refactor power well refcount inc/dec operations drm/i915: Add intel_display_power_{get, put} to request power for specific domains drm/i915: Change i915_request power well handling drm/i915: POSTING_READ IPS_CTL before waiting for the vblank drm/i915: don't disable ERR_INT on the IRQ handler drm/i915/vlv: disable rc6p and rc6pp residency reporting on BYT drm/i915/vlv: honor i915_enable_rc6 boot param on VLV drm/i915: s/HAS_L3_GPU_CACHE/HAS_L3_DPF drm/i915: Do remaps for all contexts drm/i915: Keep a list of all contexts drm/i915: Make l3 remapping use the ring drm/i915: Add second slice l3 remapping drm/i915: Fix HSW parity test drm/i915: dump crtc timings from the pipe config drm/i915: register backlight device also when backlight class is a module drm/i915: write D_COMP using the mailbox ...
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| @@ -165,6 +165,7 @@ struct drm_mode_get_plane_res { · 164 unmodified lines | ||
| 165 | 165 | #define DRM_MODE_ENCODER_LVDS 3 |
| 166 | 166 | #define DRM_MODE_ENCODER_TVDAC 4 |
| 167 | 167 | #define DRM_MODE_ENCODER_VIRTUAL 5 |
| 168 | +#define DRM_MODE_ENCODER_DSI 6 | |
| 168 | 169 | |
| 169 | 170 | struct drm_mode_get_encoder { |
| 170 | 171 | __u32 encoder_id; |
| @@ -203,6 +204,7 @@ struct drm_mode_get_encoder { · 32 unmodified lines | ||
| 203 | 204 | #define DRM_MODE_CONNECTOR_TV 13 |
| 204 | 205 | #define DRM_MODE_CONNECTOR_eDP 14 |
| 205 | 206 | #define DRM_MODE_CONNECTOR_VIRTUAL 15 |
| 207 | +#define DRM_MODE_CONNECTOR_DSI 16 | |
| 206 | 208 | |
| 207 | 209 | struct drm_mode_get_connector { |
| 208 | 210 | |
| @@ -38,10 +38,10 @@ · 37 unmodified lines | ||
| 38 | 38 | * |
| 39 | 39 | * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch |
| 40 | 40 | * event from the gpu l3 cache. Additional information supplied is ROW, |
| 41 | − * BANK, SUBBANK of the affected cacheline. Userspace should keep track of | |
| 42 | − * these events and if a specific cache-line seems to have a persistent | |
| 43 | − * error remap it with the l3 remapping tool supplied in intel-gpu-tools. | |
| 44 | − * The value supplied with the event is always 1. | |
| 41 | + * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep | |
| 42 | + * track of these events and if a specific cache-line seems to have a | |
| 43 | + * persistent error remap it with the l3 remapping tool supplied in | |
| 44 | + * intel-gpu-tools. The value supplied with the event is always 1. | |
| 45 | 45 | * |
| 46 | 46 | * I915_ERROR_UEVENT - Generated upon error detection, currently only via |
| 47 | 47 | * hangcheck. The error detection event is a good indicator of when things |