HyperFlash devices are compliant with CFI AMD/Fujitsu Extended Command Set (0x0002) for flash operations, therefore drivers/mtd/chips/cfi_cmdset_0002.c can be used as is. But these devices do not support DQ polling method of determining chip ready/good status. These flashes provide Status Register whose bits can be polled to know status of flash operation. Cypress HyperFlash datasheet here[1], talks about CFI Amd/Fujitsu Extended Query version 1.5. Bit 0 of "Software Features supported" field of CFI Primary Vendor-Specific Extended Query table indicates presence/absence of status register and Bit 1 indicates whether or not DQ polling is supported. Using these bits, its possible to determine whether flash supports DQ polling or need to use Status Register. Add support for polling Status Register to know device ready/status of erase/write operations when DQ polling is not supported. Print error messages on erase/program failure by looking at related Status Register bits. [1] https://www.cypress.com/file/213346/download
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| @@ -233,6 +233,13 @@ struct cfi_pri_amdstd { · 232 unmodified lines | ||
| 233 | 233 | uint8_t VppMin; |
| 234 | 234 | uint8_t VppMax; |
| 235 | 235 | uint8_t TopBottom; |
| 236 | + /* Below field are added from version 1.5 */ | |
| 237 | + uint8_t ProgramSuspend; | |
| 238 | + uint8_t UnlockBypass; | |
| 239 | + uint8_t SecureSiliconSector; | |
| 240 | + uint8_t SoftwareFeatures; | |
| 241 | +#define CFI_POLL_STATUS_REG BIT(0) | |
| 242 | +#define CFI_POLL_DQ BIT(1) | |
| 236 | 243 | } __packed; |
| 237 | 244 | |
| 238 | 245 | /* Vendor-Specific PRI for Atmel chips (command set 0x0002) */ |