History

Merge tag 'mlx5-updates-2017-11-04' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux

Saeed Mahameed says: ==================== mlx5-updates-2017-11-04 This series includes: From Huy: dscp to priority mapping for Ethernet packet. =================================================== First six patches enable differentiated services code point (dscp) to priority mapping for Ethernet packet. Once this feature is enabled, the packet is routed to the corresponding priority based on its dscp. User can combine this feature with priority flow control (pfc) feature to have priority flow control based on the dscp. Firmware interface: Mellanox firmware provides two control knobs for this feature: QPTS register allow changing the trust state between dscp and pcp mode. The default is pcp mode. Once in dscp mode, firmware will route the packet based on its dscp value if the dscp field exists. QPDPM register allow mapping a specific dscp (0 to 63) to a specific priority (0 to 7). By default, all the dscps are mapped to priority zero. Software interface: This feature is controlled via application priority TLV. IEEE specification P802.1Qcd/D2.1 defines priority selector id 5 for application priority TLV. This APP TLV selector defines DSCP to priority map. This APP TLV can be sent by the switch or can be set locally using software such as lldptool. In mlx5 drivers, we add the support for net dcb's getapp and setapp call back. Mlx5 driver only handles the selector id 5 application entry (dscp application priority application entry). If user sends multiple dscp to priority APP TLV entries on the same dscp, the last sent one will take effect. All the previous sent will be deleted. The firmware trust state (in QPTS register) is changed based on the number of dscp to priority application entries. When the first dscp to priority application entry is added by the user, the trust state is changed to dscp. When the last dscp to priority application entry is deleted by the user, the trust state is changed to pcp. When the port is in DSCP trust state, the transmit queue is selected based on the dscp of the skb. When the port is in DSCP trust state and vport inline mode is not NONE, firmware requires mlx5 driver to copy the IP header to the wqe ethernet segment inline header if the skb has it. This is done by changing the transmit queue sq's min inline mode to L3. Note that the min inline mode of sqs that belong to other features such as xdpsq, icosq are not modified. =================================================== Plus to the dscp series, some small misc changes are include as well: From Inbar, Ethtool msglvl support and some debug prints in DCBNL logic From Or Gerlitz, Enlarge the NIC TC offload table size From Rabie, Initialize destination_flow struct to 0 From Feras, Add inner TTC table to IPoIB flow steering From Tal, Enable CQE based moderation on TX CQ ====================

David S. Miller committed 9 years ago

Commit 488e5b32 parents bfe26ba 0088cbb22 files · +696 −53Browse files

Unified · Split

22 files
  1. drivers/net/ethernet/mellanox/mlx5/core/en.h +36 −3
  2. drivers/net/ethernet/mellanox/mlx5/core/en_arfs.c +5 −5
  3. drivers/net/ethernet/mellanox/mlx5/core/en_common.c +12 −0
  4. drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c +264 −1
  5. drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +44 −8
  6. drivers/net/ethernet/mellanox/mlx5/core/en_fs.c +6 −6
  7. drivers/net/ethernet/mellanox/mlx5/core/en_main.c +43 −16
  8. drivers/net/ethernet/mellanox/mlx5/core/en_rx_am.c +6 −2
  9. drivers/net/ethernet/mellanox/mlx5/core/en_tc.c +13 −2
  10. drivers/net/ethernet/mellanox/mlx5/core/en_tx.c +22 −2
  11. drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +1 −1
  12. drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +3 −3
  13. drivers/net/ethernet/mellanox/mlx5/core/fs_core.c +2 −2
  14. drivers/net/ethernet/mellanox/mlx5/core/fw.c +10 −0
  15. drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c +11 −1
  16. drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +2 −0
  17. drivers/net/ethernet/mellanox/mlx5/core/port.c +111 −0
  18. include/linux/mlx5/device.h +31 −0
  19. include/linux/mlx5/driver.h +9 −0
  20. include/linux/mlx5/mlx5_ifc.h +59 −1
  21. include/linux/mlx5/port.h +5 −0
  22. include/uapi/linux/dcbnl.h +1 −0
drivers/net/ethernet/mellanox/mlx5/core/en.h+36−3
@@ -57,6 +57,7 @@ · 56 unmodified lines
5757 #define MLX5E_HW2SW_MTU(priv, hwmtu) ((hwmtu) - ((priv)->hard_mtu))
5858 #define MLX5E_SW2HW_MTU(priv, swmtu) ((swmtu) + ((priv)->hard_mtu))
5959
60+#define MLX5E_MAX_DSCP 64
6061 #define MLX5E_MAX_NUM_TC 8
6162
6263 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
@@ -105,6 +106,7 @@ · 42 unmodified lines
105106 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
106107 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
107108 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
109+#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
108110 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
109111 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
110112 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
@@ -126,6 +128,16 @@ · 15 unmodified lines
126128
127129 #define MLX5E_NUM_MAIN_GROUPS 9
128130
131+#define MLX5E_MSG_LEVEL NETIF_MSG_LINK
132+
133+#define mlx5e_dbg(mlevel, priv, format, ...) \
134+do { \
135+ if (NETIF_MSG_##mlevel & (priv)->msglevel) \
136+ netdev_warn(priv->netdev, format, \
137+ ##__VA_ARGS__); \
138+} while (0)
139+
140+
129141 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
130142 {
131143 switch (wq_type) {
@@ -187,12 +199,14 @@ extern const char mlx5e_self_tests[][ETH_GSTRING_LEN]; · 55 unmodified lines
187199
188200 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
189201 "rx_cqe_moder",
202+ "tx_cqe_moder",
190203 "rx_cqe_compress",
191204 };
192205
193206 enum mlx5e_priv_flag {
194207 MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
195− MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 1),
208+ MLX5E_PFLAG_TX_CQE_BASED_MODER = (1 << 1),
209+ MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 2),
196210 };
197211
198212 #define MLX5E_SET_PFLAG(params, pflag, enable) \
@@ -212,6 +226,7 @@ enum mlx5e_priv_flag { · 13 unmodified lines
212226 struct mlx5e_cq_moder {
213227 u16 usec;
214228 u16 pkts;
229+ u8 cq_period_mode;
215230 };
216231
217232 struct mlx5e_params {
@@ -223,7 +238,6 @@ struct mlx5e_params { · 5 unmodified lines
223238 u8 log_rq_size;
224239 u16 num_channels;
225240 u8 num_tc;
226− u8 rx_cq_period_mode;
227241 bool rx_cqe_compress_def;
228242 struct mlx5e_cq_moder rx_cq_moderation;
229243 struct mlx5e_cq_moder tx_cq_moderation;
@@ -260,11 +274,17 @@ enum { · 30 unmodified lines
260274 struct mlx5e_dcbx {
261275 enum mlx5_dcbx_oper_mode mode;
262276 struct mlx5e_cee_config cee_cfg; /* pending configuration */
277+ u8 dscp_app_cnt;
263278
264279 /* The only setting that cannot be read from FW */
265280 u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
266281 u8 cap;
267282 };
283+
284+struct mlx5e_dcbx_dp {
285+ u8 dscp2prio[MLX5E_MAX_DSCP];
286+ u8 trust_state;
287+};
268288 #endif
269289
270290 enum {
@@ -742,8 +762,12 @@ struct mlx5e_priv { · 471 unmodified lines
742762 /* priv data path fields - start */
743763 struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC];
744764 int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
765+#ifdef CONFIG_MLX5_CORE_EN_DCB
766+ struct mlx5e_dcbx_dp dcbx_dp;
767+#endif
745768 /* priv data path fields - end */
746769
770+ u32 msglevel;
747771 unsigned long state;
748772 struct mutex state_lock; /* Protects Interface state */
749773 struct mlx5e_rq drop_rq;
@@ -800,6 +824,8 @@ struct mlx5e_profile { · 50 unmodified lines
800824 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
801825 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
802826 } rx_handlers;
827+ void (*netdev_registered_init)(struct mlx5e_priv *priv);
828+ void (*netdev_registered_remove)(struct mlx5e_priv *priv);
803829 int max_tc;
804830 };
805831
@@ -903,6 +929,8 @@ void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len, · 97 unmodified lines
903929 int num_channels);
904930 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
905931
932+void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params,
933+ u8 cq_period_mode);
906934 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
907935 u8 cq_period_mode);
908936 void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,
@@ -968,6 +996,8 @@ extern const struct ethtool_ops mlx5e_ethtool_ops; · 59 unmodified lines
968996 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
969997 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
970998 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
999+void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv);
1000+void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv);
9711001 #endif
9721002
9731003 #ifndef CONFIG_RFS_ACCEL
@@ -1020,6 +1050,9 @@ void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt); · 46 unmodified lines
10201050 int mlx5e_create_ttc_table(struct mlx5e_priv *priv);
10211051 void mlx5e_destroy_ttc_table(struct mlx5e_priv *priv);
10221052
1053+int mlx5e_create_inner_ttc_table(struct mlx5e_priv *priv);
1054+void mlx5e_destroy_inner_ttc_table(struct mlx5e_priv *priv);
1055+
10231056 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
10241057 u32 underlay_qpn, u32 *tisn);
10251058 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
@@ -1069,5 +1102,5 @@ void mlx5e_destroy_netdev(struct mlx5e_priv *priv); · 43 unmodified lines
10691102 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
10701103 struct mlx5e_params *params,
10711104 u16 max_channels);
1072−
1105+u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev);
10731106 #endif /* __MLX5_EN_H__ */
drivers/net/ethernet/mellanox/mlx5/core/en_arfs.c+5−5
@@ -92,7 +92,7 @@ static enum mlx5e_traffic_types arfs_get_tt(enum arfs_type type) · 91 unmodified lines
9292
9393 static int arfs_disable(struct mlx5e_priv *priv)
9494 {
95− struct mlx5_flow_destination dest;
95+ struct mlx5_flow_destination dest = {};
9696 struct mlx5e_tir *tir = priv->indir_tir;
9797 int err = 0;
9898 int tt;
@@ -126,7 +126,7 @@ int mlx5e_arfs_disable(struct mlx5e_priv *priv) · 27 unmodified lines
126126
127127 int mlx5e_arfs_enable(struct mlx5e_priv *priv)
128128 {
129− struct mlx5_flow_destination dest;
129+ struct mlx5_flow_destination dest = {};
130130 int err = 0;
131131 int tt;
132132 int i;
@@ -175,7 +175,7 @@ static int arfs_add_default_rule(struct mlx5e_priv *priv, · 42 unmodified lines
175175 {
176176 struct arfs_table *arfs_t = &priv->fs.arfs.arfs_tables[type];
177177 struct mlx5e_tir *tir = priv->indir_tir;
178− struct mlx5_flow_destination dest;
178+ struct mlx5_flow_destination dest = {};
179179 MLX5_DECLARE_FLOW_ACT(flow_act);
180180 struct mlx5_flow_spec *spec;
181181 enum mlx5e_traffic_types tt;
@@ -466,7 +466,7 @@ static struct mlx5_flow_handle *arfs_add_rule(struct mlx5e_priv *priv, · 284 unmodified lines
466466 struct mlx5e_arfs_tables *arfs = &priv->fs.arfs;
467467 struct arfs_tuple *tuple = &arfs_rule->tuple;
468468 struct mlx5_flow_handle *rule = NULL;
469− struct mlx5_flow_destination dest;
469+ struct mlx5_flow_destination dest = {};
470470 MLX5_DECLARE_FLOW_ACT(flow_act);
471471 struct arfs_table *arfs_table;
472472 struct mlx5_flow_spec *spec;
@@ -557,7 +557,7 @@ out: · 84 unmodified lines
557557 static void arfs_modify_rule_rq(struct mlx5e_priv *priv,
558558 struct mlx5_flow_handle *rule, u16 rxq)
559559 {
560− struct mlx5_flow_destination dst;
560+ struct mlx5_flow_destination dst = {};
561561 int err = 0;
562562
563563 dst.type = MLX5_FLOW_DESTINATION_TYPE_TIR;
drivers/net/ethernet/mellanox/mlx5/core/en_common.c+12−0
@@ -171,3 +171,15 @@ out: · 170 unmodified lines
171171
172172 return err;
173173 }
174+
175+u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev)
176+{
177+ u8 min_inline_mode;
178+
179+ mlx5_query_min_inline(mdev, &min_inline_mode);
180+ if (min_inline_mode == MLX5_INLINE_MODE_NONE &&
181+ !MLX5_CAP_ETH(mdev, wqe_vlan_insert))
182+ min_inline_mode = MLX5_INLINE_MODE_L2;
183+
184+ return min_inline_mode;
185+}
drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c+264−1
@@ -46,6 +46,13 @@ enum { · 45 unmodified lines
4646 MLX5E_LOWEST_PRIO_GROUP = 0,
4747 };
4848
49+#define MLX5_DSCP_SUPPORTED(mdev) (MLX5_CAP_GEN(mdev, qcam_reg) && \
50+ MLX5_CAP_QCAM_REG(mdev, qpts) && \
51+ MLX5_CAP_QCAM_REG(mdev, qpdpm))
52+
53+static int mlx5e_set_trust_state(struct mlx5e_priv *priv, u8 trust_state);
54+static int mlx5e_set_dscp2prio(struct mlx5e_priv *priv, u8 dscp, u8 prio);
55+
4956 /* If dcbx mode is non-host set the dcbx mode to host.
5057 */
5158 static int mlx5e_dcbnl_set_dcbx_mode(struct mlx5e_priv *priv,
@@ -234,7 +241,7 @@ int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets) · 182 unmodified lines
234241 u8 tc_tx_bw[IEEE_8021QAZ_MAX_TCS];
235242 u8 tc_group[IEEE_8021QAZ_MAX_TCS];
236243 int max_tc = mlx5_max_tc(mdev);
237− int err;
244+ int err, i;
238245
239246 mlx5e_build_tc_group(ets, tc_group, max_tc);
240247 mlx5e_build_tc_tx_bw(ets, tc_tx_bw, tc_group, max_tc);
@@ -253,6 +260,14 @@ int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets) · 12 unmodified lines
253260 return err;
254261
255262 memcpy(priv->dcbx.tc_tsa, ets->tc_tsa, sizeof(ets->tc_tsa));
263+
264+ for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
265+ mlx5e_dbg(HW, priv, "%s: prio_%d <=> tc_%d\n",
266+ __func__, i, ets->prio_tc[i]);
267+ mlx5e_dbg(HW, priv, "%s: tc_%d <=> tx_bw_%d%%, group_%d\n",
268+ __func__, i, tc_tx_bw[i], tc_group[i]);
269+ }
270+
256271 return err;
257272 }
258273
@@ -338,6 +353,11 @@ static int mlx5e_dcbnl_ieee_setpfc(struct net_device *dev, · 79 unmodified lines
338353 ret = mlx5_set_port_pfc(mdev, pfc->pfc_en, pfc->pfc_en);
339354 mlx5_toggle_port_link(mdev);
340355
356+ if (!ret) {
357+ mlx5e_dbg(HW, priv,
358+ "%s: PFC per priority bit mask: 0x%x\n",
359+ __func__, pfc->pfc_en);
360+ }
341361 return ret;
342362 }
343363
@@ -381,6 +401,113 @@ static u8 mlx5e_dcbnl_setdcbx(struct net_device *dev, u8 mode) · 37 unmodified lines
381401 return 0;
382402 }
383403
404+static int mlx5e_dcbnl_ieee_setapp(struct net_device *dev, struct dcb_app *app)
405+{
406+ struct mlx5e_priv *priv = netdev_priv(dev);
407+ struct dcb_app temp;
408+ bool is_new;
409+ int err;
410+
411+ if (app->selector != IEEE_8021QAZ_APP_SEL_DSCP)
412+ return -EINVAL;
413+
414+ if (!MLX5_CAP_GEN(priv->mdev, vport_group_manager))
415+ return -EINVAL;
416+
417+ if (!MLX5_DSCP_SUPPORTED(priv->mdev))
418+ return -EINVAL;
419+
420+ if (app->protocol >= MLX5E_MAX_DSCP)
421+ return -EINVAL;
422+
423+ /* Save the old entry info */
424+ temp.selector = IEEE_8021QAZ_APP_SEL_DSCP;
425+ temp.protocol = app->protocol;
426+ temp.priority = priv->dcbx_dp.dscp2prio[app->protocol];
427+
428+ /* Check if need to switch to dscp trust state */
429+ if (!priv->dcbx.dscp_app_cnt) {
430+ err = mlx5e_set_trust_state(priv, MLX5_QPTS_TRUST_DSCP);
431+ if (err)
432+ return err;
433+ }
434+
435+ /* Skip the fw command if new and old mapping are the same */
436+ if (app->priority != priv->dcbx_dp.dscp2prio[app->protocol]) {
437+ err = mlx5e_set_dscp2prio(priv, app->protocol, app->priority);
438+ if (err)
439+ goto fw_err;
440+ }
441+
442+ /* Delete the old entry if exists */
443+ is_new = false;
444+ err = dcb_ieee_delapp(dev, &temp);
445+ if (err)
446+ is_new = true;
447+
448+ /* Add new entry and update counter */
449+ err = dcb_ieee_setapp(dev, app);
450+ if (err)
451+ return err;
452+
453+ if (is_new)
454+ priv->dcbx.dscp_app_cnt++;
455+
456+ return err;
457+
458+fw_err:
459+ mlx5e_set_trust_state(priv, MLX5_QPTS_TRUST_PCP);
460+ return err;
461+}
462+
463+static int mlx5e_dcbnl_ieee_delapp(struct net_device *dev, struct dcb_app *app)
464+{
465+ struct mlx5e_priv *priv = netdev_priv(dev);
466+ int err;
467+
468+ if (app->selector != IEEE_8021QAZ_APP_SEL_DSCP)
469+ return -EINVAL;
470+
471+ if (!MLX5_CAP_GEN(priv->mdev, vport_group_manager))
472+ return -EINVAL;
473+
474+ if (!MLX5_DSCP_SUPPORTED(priv->mdev))
475+ return -EINVAL;
476+
477+ if (app->protocol >= MLX5E_MAX_DSCP)
478+ return -EINVAL;
479+
480+ /* Skip if no dscp app entry */
481+ if (!priv->dcbx.dscp_app_cnt)
482+ return -ENOENT;
483+
484+ /* Check if the entry matches fw setting */
485+ if (app->priority != priv->dcbx_dp.dscp2prio[app->protocol])
486+ return -ENOENT;
487+
488+ /* Delete the app entry */
489+ err = dcb_ieee_delapp(dev, app);
490+ if (err)
491+ return err;
492+
493+ /* Reset the priority mapping back to zero */
494+ err = mlx5e_set_dscp2prio(priv, app->protocol, 0);
495+ if (err)
496+ goto fw_err;
497+
498+ priv->dcbx.dscp_app_cnt--;
499+
500+ /* Check if need to switch to pcp trust state */
501+ if (!priv->dcbx.dscp_app_cnt)
502+ err = mlx5e_set_trust_state(priv, MLX5_QPTS_TRUST_PCP);
503+
504+ return err;
505+
506+fw_err:
507+ mlx5e_set_trust_state(priv, MLX5_QPTS_TRUST_PCP);
508+ return err;
509+}
510+
384511 static int mlx5e_dcbnl_ieee_getmaxrate(struct net_device *netdev,
385512 struct ieee_maxrate *maxrate)
386513 {
@@ -446,6 +573,11 @@ static int mlx5e_dcbnl_ieee_setmaxrate(struct net_device *netdev, · 59 unmodified lines
446573 }
447574 }
448575
576+ for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
577+ mlx5e_dbg(HW, priv, "%s: tc_%d <=> max_bw %d Gbps\n",
578+ __func__, i, max_bw_value[i]);
579+ }
580+
449581 return mlx5_modify_port_ets_rate_limit(mdev, max_bw_value, max_bw_unit);
450582 }
451583
@@ -471,6 +603,10 @@ static u8 mlx5e_dcbnl_setall(struct net_device *netdev) · 19 unmodified lines
471603 ets.tc_rx_bw[i] = cee_cfg->pg_bw_pct[i];
472604 ets.tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;
473605 ets.prio_tc[i] = cee_cfg->prio_to_pg_map[i];
606+ mlx5e_dbg(HW, priv,
607+ "%s: Priority group %d: tx_bw %d, rx_bw %d, prio_tc %d\n",
608+ __func__, i, ets.tc_tx_bw[i], ets.tc_rx_bw[i],
609+ ets.prio_tc[i]);
474610 }
475611
476612 err = mlx5e_dbcnl_validate_ets(netdev, &ets);
@@ -740,6 +876,8 @@ const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops = { · 263 unmodified lines
740876 .ieee_setmaxrate = mlx5e_dcbnl_ieee_setmaxrate,
741877 .ieee_getpfc = mlx5e_dcbnl_ieee_getpfc,
742878 .ieee_setpfc = mlx5e_dcbnl_ieee_setpfc,
879+ .ieee_setapp = mlx5e_dcbnl_ieee_setapp,
880+ .ieee_delapp = mlx5e_dcbnl_ieee_delapp,
743881 .getdcbx = mlx5e_dcbnl_getdcbx,
744882 .setdcbx = mlx5e_dcbnl_setdcbx,
745883
@@ -801,10 +939,135 @@ static void mlx5e_ets_init(struct mlx5e_priv *priv) · 55 unmodified lines
801939 mlx5e_dcbnl_ieee_setets_core(priv, &ets);
802940 }
803941
942+enum {
943+ INIT,
944+ DELETE,
945+};
946+
947+static void mlx5e_dcbnl_dscp_app(struct mlx5e_priv *priv, int action)
948+{
949+ struct dcb_app temp;
950+ int i;
951+
952+ if (!MLX5_CAP_GEN(priv->mdev, vport_group_manager))
953+ return;
954+
955+ if (!MLX5_DSCP_SUPPORTED(priv->mdev))
956+ return;
957+
958+ /* No SEL_DSCP entry in non DSCP state */
959+ if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_DSCP)
960+ return;
961+
962+ temp.selector = IEEE_8021QAZ_APP_SEL_DSCP;
963+ for (i = 0; i < MLX5E_MAX_DSCP; i++) {
964+ temp.protocol = i;
965+ temp.priority = priv->dcbx_dp.dscp2prio[i];
966+ if (action == INIT)
967+ dcb_ieee_setapp(priv->netdev, &temp);
968+ else
969+ dcb_ieee_delapp(priv->netdev, &temp);
970+ }
971+
972+ priv->dcbx.dscp_app_cnt = (action == INIT) ? MLX5E_MAX_DSCP : 0;
973+}
974+
975+void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv)
976+{
977+ mlx5e_dcbnl_dscp_app(priv, INIT);
978+}
979+
980+void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv)
981+{
982+ mlx5e_dcbnl_dscp_app(priv, DELETE);
983+}
984+
985+static void mlx5e_trust_update_tx_min_inline_mode(struct mlx5e_priv *priv,
986+ struct mlx5e_params *params)
987+{
988+ params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(priv->mdev);
989+ if (priv->dcbx_dp.trust_state == MLX5_QPTS_TRUST_DSCP &&
990+ params->tx_min_inline_mode == MLX5_INLINE_MODE_L2)
991+ params->tx_min_inline_mode = MLX5_INLINE_MODE_IP;
992+}
993+
994+static void mlx5e_trust_update_sq_inline_mode(struct mlx5e_priv *priv)
995+{
996+ struct mlx5e_channels new_channels = {};
997+
998+ mutex_lock(&priv->state_lock);
999+
1000+ if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1001+ goto out;
1002+
1003+ new_channels.params = priv->channels.params;
1004+ mlx5e_trust_update_tx_min_inline_mode(priv, &new_channels.params);
1005+
1006+ /* Skip if tx_min_inline is the same */
1007+ if (new_channels.params.tx_min_inline_mode ==
1008+ priv->channels.params.tx_min_inline_mode)
1009+ goto out;
1010+
1011+ if (mlx5e_open_channels(priv, &new_channels))
1012+ goto out;
1013+ mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1014+
1015+out:
1016+ mutex_unlock(&priv->state_lock);
1017+}
1018+
1019+static int mlx5e_set_trust_state(struct mlx5e_priv *priv, u8 trust_state)
1020+{
1021+ int err;
1022+
1023+ err = mlx5_set_trust_state(priv->mdev, trust_state);
1024+ if (err)
1025+ return err;
1026+ priv->dcbx_dp.trust_state = trust_state;
1027+ mlx5e_trust_update_sq_inline_mode(priv);
1028+
1029+ return err;
1030+}
1031+
1032+static int mlx5e_set_dscp2prio(struct mlx5e_priv *priv, u8 dscp, u8 prio)
1033+{
1034+ int err;
1035+
1036+ err = mlx5_set_dscp2prio(priv->mdev, dscp, prio);
1037+ if (err)
1038+ return err;
1039+
1040+ priv->dcbx_dp.dscp2prio[dscp] = prio;
1041+ return err;
1042+}
1043+
1044+static int mlx5e_trust_initialize(struct mlx5e_priv *priv)
1045+{
1046+ struct mlx5_core_dev *mdev = priv->mdev;
1047+ int err;
1048+
1049+ if (!MLX5_DSCP_SUPPORTED(mdev))
1050+ return 0;
1051+
1052+ err = mlx5_query_trust_state(priv->mdev, &priv->dcbx_dp.trust_state);
1053+ if (err)
1054+ return err;
1055+
1056+ mlx5e_trust_update_tx_min_inline_mode(priv, &priv->channels.params);
1057+
1058+ err = mlx5_query_dscp2prio(priv->mdev, priv->dcbx_dp.dscp2prio);
1059+ if (err)
1060+ return err;
1061+
1062+ return 0;
1063+}
1064+
8041065 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv)
8051066 {
8061067 struct mlx5e_dcbx *dcbx = &priv->dcbx;
8071068
1069+ mlx5e_trust_initialize(priv);
1070+
8081071 if (!MLX5_CAP_GEN(priv->mdev, qos))
8091072 return;
8101073
drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c+44−8
@@ -1340,6 +1340,16 @@ static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) · 1339 unmodified lines
13401340 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
13411341 }
13421342
1343+static u32 mlx5e_get_msglevel(struct net_device *dev)
1344+{
1345+ return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel;
1346+}
1347+
1348+static void mlx5e_set_msglevel(struct net_device *dev, u32 val)
1349+{
1350+ ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val;
1351+}
1352+
13431353 static int mlx5e_set_phys_id(struct net_device *dev,
13441354 enum ethtool_phys_id_state state)
13451355 {
@@ -1444,29 +1454,36 @@ static int mlx5e_get_module_eeprom(struct net_device *netdev, · 98 unmodified lines
14441454
14451455 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
14461456
1447−static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1457+static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
1458+ bool is_rx_cq)
14481459 {
14491460 struct mlx5e_priv *priv = netdev_priv(netdev);
14501461 struct mlx5_core_dev *mdev = priv->mdev;
14511462 struct mlx5e_channels new_channels = {};
1452− bool rx_mode_changed;
1453− u8 rx_cq_period_mode;
1463+ bool mode_changed;
1464+ u8 cq_period_mode, current_cq_period_mode;
14541465 int err = 0;
14551466
1456− rx_cq_period_mode = enable ?
1467+ cq_period_mode = enable ?
14571468 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
14581469 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1459− rx_mode_changed = rx_cq_period_mode != priv->channels.params.rx_cq_period_mode;
1470+ current_cq_period_mode = is_rx_cq ?
1471+ priv->channels.params.rx_cq_moderation.cq_period_mode :
1472+ priv->channels.params.tx_cq_moderation.cq_period_mode;
1473+ mode_changed = cq_period_mode != current_cq_period_mode;
14601474
1461− if (rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1475+ if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
14621476 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
14631477 return -EOPNOTSUPP;
14641478
1465− if (!rx_mode_changed)
1479+ if (!mode_changed)
14661480 return 0;
14671481
14681482 new_channels.params = priv->channels.params;
1469− mlx5e_set_rx_cq_mode_params(&new_channels.params, rx_cq_period_mode);
1483+ if (is_rx_cq)
1484+ mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode);
1485+ else
1486+ mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode);
14701487
14711488 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
14721489 priv->channels.params = new_channels.params;
@@ -1481,6 +1498,16 @@ static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable) · 8 unmodified lines
14811498 return 0;
14821499 }
14831500
1501+static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
1502+{
1503+ return set_pflag_cqe_based_moder(netdev, enable, false);
1504+}
1505+
1506+static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1507+{
1508+ return set_pflag_cqe_based_moder(netdev, enable, true);
1509+}
1510+
14841511 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
14851512 {
14861513 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
@@ -1568,6 +1595,12 @@ static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags) · 81 unmodified lines
15681595 if (err)
15691596 goto out;
15701597
1598+ err = mlx5e_handle_pflag(netdev, pflags,
1599+ MLX5E_PFLAG_TX_CQE_BASED_MODER,
1600+ set_pflag_tx_cqe_based_moder);
1601+ if (err)
1602+ goto out;
1603+
15711604 err = mlx5e_handle_pflag(netdev, pflags,
15721605 MLX5E_PFLAG_RX_CQE_COMPRESS,
15731606 set_pflag_rx_cqe_compress);
@@ -1672,4 +1705,7 @@ const struct ethtool_ops mlx5e_ethtool_ops = { · 98 unmodified lines
16721705 .get_priv_flags = mlx5e_get_priv_flags,
16731706 .set_priv_flags = mlx5e_set_priv_flags,
16741707 .self_test = mlx5e_self_test,
1708+ .get_msglevel = mlx5e_get_msglevel,
1709+ .set_msglevel = mlx5e_set_msglevel,
1710+
16751711 };
drivers/net/ethernet/mellanox/mlx5/core/en_fs.c+6−6
@@ -162,7 +162,7 @@ static int __mlx5e_add_vlan_rule(struct mlx5e_priv *priv, · 161 unmodified lines
162162 u16 vid, struct mlx5_flow_spec *spec)
163163 {
164164 struct mlx5_flow_table *ft = priv->fs.vlan.ft.t;
165− struct mlx5_flow_destination dest;
165+ struct mlx5_flow_destination dest = {};
166166 struct mlx5_flow_handle **rule_p;
167167 MLX5_DECLARE_FLOW_ACT(flow_act);
168168 int err = 0;
@@ -738,7 +738,7 @@ mlx5e_generate_ttc_rule(struct mlx5e_priv *priv, · 569 unmodified lines
738738
739739 static int mlx5e_generate_ttc_table_rules(struct mlx5e_priv *priv)
740740 {
741− struct mlx5_flow_destination dest;
741+ struct mlx5_flow_destination dest = {};
742742 struct mlx5e_ttc_table *ttc;
743743 struct mlx5_flow_handle **rules;
744744 struct mlx5_flow_table *ft;
@@ -909,7 +909,7 @@ mlx5e_generate_inner_ttc_rule(struct mlx5e_priv *priv, · 164 unmodified lines
909909
910910 static int mlx5e_generate_inner_ttc_table_rules(struct mlx5e_priv *priv)
911911 {
912− struct mlx5_flow_destination dest;
912+ struct mlx5_flow_destination dest = {};
913913 struct mlx5_flow_handle **rules;
914914 struct mlx5e_ttc_table *ttc;
915915 struct mlx5_flow_table *ft;
@@ -1005,7 +1005,7 @@ err: · 89 unmodified lines
10051005 return err;
10061006 }
10071007
1008−static int mlx5e_create_inner_ttc_table(struct mlx5e_priv *priv)
1008+int mlx5e_create_inner_ttc_table(struct mlx5e_priv *priv)
10091009 {
10101010 struct mlx5e_ttc_table *ttc = &priv->fs.inner_ttc;
10111011 struct mlx5_flow_table_attr ft_attr = {};
@@ -1041,7 +1041,7 @@ err: · 29 unmodified lines
10411041 return err;
10421042 }
10431043
1044−static void mlx5e_destroy_inner_ttc_table(struct mlx5e_priv *priv)
1044+void mlx5e_destroy_inner_ttc_table(struct mlx5e_priv *priv)
10451045 {
10461046 struct mlx5e_ttc_table *ttc = &priv->fs.inner_ttc;
10471047
@@ -1106,7 +1106,7 @@ static int mlx5e_add_l2_flow_rule(struct mlx5e_priv *priv, · 58 unmodified lines
11061106 struct mlx5e_l2_rule *ai, int type)
11071107 {
11081108 struct mlx5_flow_table *ft = priv->fs.l2.ft.t;
1109− struct mlx5_flow_destination dest;
1109+ struct mlx5_flow_destination dest = {};
11101110 MLX5_DECLARE_FLOW_ACT(flow_act);
11111111 struct mlx5_flow_spec *spec;
11121112 int err = 0;
drivers/net/ethernet/mellanox/mlx5/core/en_main.c+43−16
@@ -681,7 +681,7 @@ static int mlx5e_alloc_rq(struct mlx5e_channel *c, · 680 unmodified lines
681681 }
682682
683683 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
684− rq->am.mode = params->rx_cq_period_mode;
684+ rq->am.mode = params->rx_cq_moderation.cq_period_mode;
685685 rq->page_cache.head = 0;
686686 rq->page_cache.tail = 0;
687687
@@ -1974,7 +1974,7 @@ static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, · 1286 unmodified lines
19741974 }
19751975
19761976 mlx5e_build_common_cq_param(priv, param);
1977− param->cq_period_mode = params->rx_cq_period_mode;
1977+ param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
19781978 }
19791979
19801980 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
@@ -1986,8 +1986,7 @@ static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, · 5 unmodified lines
19861986 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
19871987
19881988 mlx5e_build_common_cq_param(priv, param);
1989−
1990− param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1989+ param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
19911990 }
19921991
19931992 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
@@ -3987,14 +3986,32 @@ static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw) · 1993 unmodified lines
39873986 (pci_bw <= 16000) && (pci_bw < link_speed));
39883987 }
39893988
3989+void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3990+{
3991+ params->tx_cq_moderation.cq_period_mode = cq_period_mode;
3992+
3993+ params->tx_cq_moderation.pkts =
3994+ MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3995+ params->tx_cq_moderation.usec =
3996+ MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3997+
3998+ if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3999+ params->tx_cq_moderation.usec =
4000+ MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4001+
4002+ MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4003+ params->tx_cq_moderation.cq_period_mode ==
4004+ MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4005+}
4006+
39904007 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
39914008 {
3992− params->rx_cq_period_mode = cq_period_mode;
4009+ params->rx_cq_moderation.cq_period_mode = cq_period_mode;
39934010
39944011 params->rx_cq_moderation.pkts =
39954012 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
39964013 params->rx_cq_moderation.usec =
3997− MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4014+ MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
39984015
39994016 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
40004017 params->rx_cq_moderation.usec =
@@ -4002,10 +4019,11 @@ void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) · 1 unmodified line
40024019
40034020 if (params->rx_am_enabled)
40044021 params->rx_cq_moderation =
4005− mlx5e_am_get_def_profile(params->rx_cq_period_mode);
4022+ mlx5e_am_get_def_profile(cq_period_mode);
40064023
40074024 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4008− params->rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4025+ params->rx_cq_moderation.cq_period_mode ==
4026+ MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
40094027 }
40104028
40114029 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
@@ -4065,16 +4083,11 @@ void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, · 53 unmodified lines
40654083 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
40664084 params->rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
40674085 mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
4068−
4069− params->tx_cq_moderation.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4070− params->tx_cq_moderation.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4086+ mlx5e_set_tx_cq_mode_params(params, cq_period_mode);
40714087
40724088 /* TX inline */
40734089 params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
4074− mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4075− if (params->tx_min_inline_mode == MLX5_INLINE_MODE_NONE &&
4076− !MLX5_CAP_ETH(mdev, wqe_vlan_insert))
4077− params->tx_min_inline_mode = MLX5_INLINE_MODE_L2;
4090+ params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
40784091
40794092 /* RSS */
40804093 params->rss_hfunc = ETH_RSS_HASH_XOR;
@@ -4094,6 +4107,7 @@ static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev, · 13 unmodified lines
40944107 priv->netdev = netdev;
40954108 priv->profile = profile;
40964109 priv->ppriv = ppriv;
4110+ priv->msglevel = MLX5E_MSG_LEVEL;
40974111 priv->hard_mtu = MLX5E_ETH_HARD_MTU;
40984112
40994113 mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
@@ -4374,7 +4388,9 @@ static void mlx5e_nic_enable(struct mlx5e_priv *priv) · 274 unmodified lines
43744388
43754389 if (netdev->reg_state != NETREG_REGISTERED)
43764390 return;
4377−
4391+#ifdef CONFIG_MLX5_CORE_EN_DCB
4392+ mlx5e_dcbnl_init_app(priv);
4393+#endif
43784394 /* Device already registered: sync netdev system state */
43794395 if (mlx5e_vxlan_allowed(mdev)) {
43804396 rtnl_lock();
@@ -4395,6 +4411,11 @@ static void mlx5e_nic_disable(struct mlx5e_priv *priv) · 14 unmodified lines
43954411 {
43964412 struct mlx5_core_dev *mdev = priv->mdev;
43974413
4414+#ifdef CONFIG_MLX5_CORE_EN_DCB
4415+ if (priv->netdev->reg_state == NETREG_REGISTERED)
4416+ mlx5e_dcbnl_delete_app(priv);
4417+#endif
4418+
43984419 rtnl_lock();
43994420 if (netif_running(priv->netdev))
44004421 mlx5e_close(priv->netdev);
@@ -4615,6 +4636,9 @@ static void *mlx5e_add(struct mlx5_core_dev *mdev) · 214 unmodified lines
46154636 goto err_detach;
46164637 }
46174638
4639+#ifdef CONFIG_MLX5_CORE_EN_DCB
4640+ mlx5e_dcbnl_init_app(priv);
4641+#endif
46184642 return priv;
46194643
46204644 err_detach:
@@ -4631,6 +4655,9 @@ static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv) · 10 unmodified lines
46314655 struct mlx5e_priv *priv = vpriv;
46324656 void *ppriv = priv->ppriv;
46334657
4658+#ifdef CONFIG_MLX5_CORE_EN_DCB
4659+ mlx5e_dcbnl_delete_app(priv);
4660+#endif
46344661 unregister_netdev(priv->netdev);
46354662 mlx5e_detach(mdev, vpriv);
46364663 mlx5e_destroy_netdev(priv);
drivers/net/ethernet/mellanox/mlx5/core/en_rx_am.c+6−2
@@ -63,7 +63,11 @@ profile[MLX5_CQ_PERIOD_NUM_MODES][MLX5E_PARAMS_AM_NUM_PROFILES] = { · 62 unmodified lines
6363
6464 static inline struct mlx5e_cq_moder mlx5e_am_get_profile(u8 cq_period_mode, int ix)
6565 {
66− return profile[cq_period_mode][ix];
66+ struct mlx5e_cq_moder cq_moder;
67+
68+ cq_moder = profile[cq_period_mode][ix];
69+ cq_moder.cq_period_mode = cq_period_mode;
70+ return cq_moder;
6771 }
6872
6973 struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode)
@@ -75,7 +79,7 @@ struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode) · 5 unmodified lines
7579 else /* MLX5_CQ_PERIOD_MODE_START_FROM_EQE */
7680 default_profile_ix = MLX5E_RX_AM_DEF_PROFILE_EQE;
7781
78− return profile[rx_cq_period_mode][default_profile_ix];
82+ return mlx5e_am_get_profile(rx_cq_period_mode, default_profile_ix);
7983 }
8084
8185 /* Adaptive moderation logic */
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c+13−2
@@ -90,8 +90,8 @@ enum { · 89 unmodified lines
9090 MLX5_HEADER_TYPE_NVGRE = 0x1,
9191 };
9292
93−#define MLX5E_TC_TABLE_NUM_ENTRIES 1024
9493 #define MLX5E_TC_TABLE_NUM_GROUPS 4
94+#define MLX5E_TC_TABLE_MAX_GROUP_SIZE (1 << 16)
9595
9696 struct mod_hdr_key {
9797 int num_actions;
@@ -263,10 +263,21 @@ mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv, · 165 unmodified lines
263263 }
264264
265265 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
266+ int tc_grp_size, tc_tbl_size;
267+ u32 max_flow_counter;
268+
269+ max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
270+ MLX5_CAP_GEN(dev, max_flow_counter_15_0);
271+
272+ tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
273+
274+ tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
275+ BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
276+
266277 priv->fs.tc.t =
267278 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
268279 MLX5E_TC_PRIO,
269− MLX5E_TC_TABLE_NUM_ENTRIES,
280+ tc_tbl_size,
270281 MLX5E_TC_TABLE_NUM_GROUPS,
271282 0, 0);
272283 if (IS_ERR(priv->fs.tc.t)) {
drivers/net/ethernet/mellanox/mlx5/core/en_tx.c+22−2
@@ -32,6 +32,7 @@ · 31 unmodified lines
3232
3333 #include <linux/tcp.h>
3434 #include <linux/if_vlan.h>
35+#include <net/dsfield.h>
3536 #include "en.h"
3637 #include "ipoib/ipoib.h"
3738 #include "en_accel/ipsec_rxtx.h"
@@ -86,6 +87,20 @@ static void mlx5e_dma_unmap_wqe_err(struct mlx5e_txqsq *sq, u8 num_dma) · 48 unmodified lines
8687 }
8788 }
8889
90+#ifdef CONFIG_MLX5_CORE_EN_DCB
91+static inline int mlx5e_get_dscp_up(struct mlx5e_priv *priv, struct sk_buff *skb)
92+{
93+ int dscp_cp = 0;
94+
95+ if (skb->protocol == htons(ETH_P_IP))
96+ dscp_cp = ipv4_get_dsfield(ip_hdr(skb)) >> 2;
97+ else if (skb->protocol == htons(ETH_P_IPV6))
98+ dscp_cp = ipv6_get_dsfield(ipv6_hdr(skb)) >> 2;
99+
100+ return priv->dcbx_dp.dscp2prio[dscp_cp];
101+}
102+#endif
103+
89104 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
90105 void *accel_priv, select_queue_fallback_t fallback)
91106 {
@@ -97,8 +112,13 @@ u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, · 5 unmodified lines
97112 if (!netdev_get_num_tc(dev))
98113 return channel_ix;
99114
100− if (skb_vlan_tag_present(skb))
101− up = skb->vlan_tci >> VLAN_PRIO_SHIFT;
115+#ifdef CONFIG_MLX5_CORE_EN_DCB
116+ if (priv->dcbx_dp.trust_state == MLX5_QPTS_TRUST_DSCP)
117+ up = mlx5e_get_dscp_up(priv, skb);
118+ else
119+#endif
120+ if (skb_vlan_tag_present(skb))
121+ up = skb->vlan_tci >> VLAN_PRIO_SHIFT;
102122
103123 /* channel_ix can be larger than num_channels since
104124 * dev->num_real_tx_queues = num_channels * num_tc
drivers/net/ethernet/mellanox/mlx5/core/eswitch.c+1−1
@@ -157,7 +157,7 @@ __esw_fdb_set_vport_rule(struct mlx5_eswitch *esw, u32 vport, bool rx_rule, · 156 unmodified lines
157157 MLX5_MATCH_OUTER_HEADERS);
158158 struct mlx5_flow_handle *flow_rule = NULL;
159159 struct mlx5_flow_act flow_act = {0};
160− struct mlx5_flow_destination dest;
160+ struct mlx5_flow_destination dest = {};
161161 struct mlx5_flow_spec *spec;
162162 void *mv_misc = NULL;
163163 void *mc_misc = NULL;
drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c+3−3
@@ -306,7 +306,7 @@ static struct mlx5_flow_handle * · 305 unmodified lines
306306 mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw, int vport, u32 sqn)
307307 {
308308 struct mlx5_flow_act flow_act = {0};
309− struct mlx5_flow_destination dest;
309+ struct mlx5_flow_destination dest = {};
310310 struct mlx5_flow_handle *flow_rule;
311311 struct mlx5_flow_spec *spec;
312312 void *misc;
@@ -395,7 +395,7 @@ out_err: · 82 unmodified lines
395395 static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
396396 {
397397 struct mlx5_flow_act flow_act = {0};
398− struct mlx5_flow_destination dest;
398+ struct mlx5_flow_destination dest = {};
399399 struct mlx5_flow_handle *flow_rule = NULL;
400400 struct mlx5_flow_spec *spec;
401401 int err = 0;
@@ -670,7 +670,7 @@ struct mlx5_flow_handle * · 268 unmodified lines
670670 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport, u32 tirn)
671671 {
672672 struct mlx5_flow_act flow_act = {0};
673− struct mlx5_flow_destination dest;
673+ struct mlx5_flow_destination dest = {};
674674 struct mlx5_flow_handle *flow_rule;
675675 struct mlx5_flow_spec *spec;
676676 void *misc;
drivers/net/ethernet/mellanox/mlx5/core/fs_core.c+2−2
@@ -912,7 +912,7 @@ static int connect_fwd_rules(struct mlx5_core_dev *dev, · 911 unmodified lines
912912 struct mlx5_flow_table *new_next_ft,
913913 struct mlx5_flow_table *old_next_ft)
914914 {
915− struct mlx5_flow_destination dest;
915+ struct mlx5_flow_destination dest = {};
916916 struct mlx5_flow_rule *iter;
917917 int err = 0;
918918
@@ -1820,7 +1820,7 @@ mlx5_add_flow_rules(struct mlx5_flow_table *ft, · 901 unmodified lines
18201820 int dest_num)
18211821 {
18221822 struct mlx5_flow_root_namespace *root = find_root(&ft->node);
1823− struct mlx5_flow_destination gen_dest;
1823+ struct mlx5_flow_destination gen_dest = {};
18241824 struct mlx5_flow_table *next_ft = NULL;
18251825 struct mlx5_flow_handle *handle = NULL;
18261826 u32 sw_action = flow_act->action;
drivers/net/ethernet/mellanox/mlx5/core/fw.c+10−0
@@ -106,6 +106,13 @@ static int mlx5_get_mcam_reg(struct mlx5_core_dev *dev) · 105 unmodified lines
106106 MLX5_MCAM_REGS_FIRST_128);
107107 }
108108
109+static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev)
110+{
111+ return mlx5_query_qcam_reg(dev, dev->caps.qcam,
112+ MLX5_QCAM_FEATURE_ENHANCED_FEATURES,
113+ MLX5_QCAM_REGS_FIRST_128);
114+}
115+
109116 int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
110117 {
111118 int err;
@@ -182,6 +189,9 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev) · 70 unmodified lines
182189 if (MLX5_CAP_GEN(dev, mcam_reg))
183190 mlx5_get_mcam_reg(dev);
184191
192+ if (MLX5_CAP_GEN(dev, qcam_reg))
193+ mlx5_get_qcam_reg(dev);
194+
185195 return 0;
186196 }
187197
drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c+11−1
@@ -255,15 +255,24 @@ static int mlx5i_create_flow_steering(struct mlx5e_priv *priv) · 254 unmodified lines
255255 priv->netdev->hw_features &= ~NETIF_F_NTUPLE;
256256 }
257257
258+ err = mlx5e_create_inner_ttc_table(priv);
259+ if (err) {
260+ netdev_err(priv->netdev, "Failed to create inner ttc table, err=%d\n",
261+ err);
262+ goto err_destroy_arfs_tables;
263+ }
264+
258265 err = mlx5e_create_ttc_table(priv);
259266 if (err) {
260267 netdev_err(priv->netdev, "Failed to create ttc table, err=%d\n",
261268 err);
262− goto err_destroy_arfs_tables;
269+ goto err_destroy_inner_ttc_table;
263270 }
264271
265272 return 0;
266273
274+err_destroy_inner_ttc_table:
275+ mlx5e_destroy_inner_ttc_table(priv);
267276 err_destroy_arfs_tables:
268277 mlx5e_arfs_destroy_tables(priv);
269278
@@ -273,6 +282,7 @@ err_destroy_arfs_tables: · 3 unmodified lines
273282 static void mlx5i_destroy_flow_steering(struct mlx5e_priv *priv)
274283 {
275284 mlx5e_destroy_ttc_table(priv);
285+ mlx5e_destroy_inner_ttc_table(priv);
276286 mlx5e_arfs_destroy_tables(priv);
277287 }
278288
drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h+2−0
@@ -122,6 +122,8 @@ int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group, · 121 unmodified lines
122122 u8 access_reg_group);
123123 int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap, u8 feature_group,
124124 u8 access_reg_group);
125+int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
126+ u8 feature_group, u8 access_reg_group);
125127
126128 void mlx5_lag_add(struct mlx5_core_dev *dev, struct net_device *netdev);
127129 void mlx5_lag_remove(struct mlx5_core_dev *dev);
drivers/net/ethernet/mellanox/mlx5/core/port.c+111−0
@@ -98,6 +98,18 @@ int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcam, u8 feature_group, · 97 unmodified lines
9898 return mlx5_core_access_reg(dev, in, sz, mcam, sz, MLX5_REG_MCAM, 0, 0);
9999 }
100100
101+int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
102+ u8 feature_group, u8 access_reg_group)
103+{
104+ u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {};
105+ int sz = MLX5_ST_SZ_BYTES(qcam_reg);
106+
107+ MLX5_SET(qcam_reg, in, feature_group, feature_group);
108+ MLX5_SET(qcam_reg, in, access_reg_group, access_reg_group);
109+
110+ return mlx5_core_access_reg(mdev, in, sz, qcam, sz, MLX5_REG_QCAM, 0, 0);
111+}
112+
101113 struct mlx5_reg_pcap {
102114 u8 rsvd0;
103115 u8 port_num;
@@ -959,3 +971,102 @@ int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode) · 855 unmodified lines
959971 return mlx5_core_access_reg(mdev, in, sizeof(in), out,
960972 sizeof(out), MLX5_REG_MTPPSE, 0, 1);
961973 }
974+
975+int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state)
976+{
977+ u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {};
978+ u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
979+ int err;
980+
981+ MLX5_SET(qpts_reg, in, local_port, 1);
982+ MLX5_SET(qpts_reg, in, trust_state, trust_state);
983+
984+ err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
985+ sizeof(out), MLX5_REG_QPTS, 0, 1);
986+ return err;
987+}
988+
989+int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state)
990+{
991+ u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {};
992+ u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
993+ int err;
994+
995+ MLX5_SET(qpts_reg, in, local_port, 1);
996+
997+ err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
998+ sizeof(out), MLX5_REG_QPTS, 0, 0);
999+ if (!err)
1000+ *trust_state = MLX5_GET(qpts_reg, out, trust_state);
1001+
1002+ return err;
1003+}
1004+
1005+int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio)
1006+{
1007+ int sz = MLX5_ST_SZ_BYTES(qpdpm_reg);
1008+ void *qpdpm_dscp;
1009+ void *out;
1010+ void *in;
1011+ int err;
1012+
1013+ in = kzalloc(sz, GFP_KERNEL);
1014+ out = kzalloc(sz, GFP_KERNEL);
1015+ if (!in || !out) {
1016+ err = -ENOMEM;
1017+ goto out;
1018+ }
1019+
1020+ MLX5_SET(qpdpm_reg, in, local_port, 1);
1021+ err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0);
1022+ if (err)
1023+ goto out;
1024+
1025+ memcpy(in, out, sz);
1026+ MLX5_SET(qpdpm_reg, in, local_port, 1);
1027+
1028+ /* Update the corresponding dscp entry */
1029+ qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, in, dscp[dscp]);
1030+ MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, prio, prio);
1031+ MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, e, 1);
1032+ err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 1);
1033+
1034+out:
1035+ kfree(in);
1036+ kfree(out);
1037+ return err;
1038+}
1039+
1040+/* dscp2prio[i]: priority that dscp i mapped to */
1041+#define MLX5E_SUPPORTED_DSCP 64
1042+int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio)
1043+{
1044+ int sz = MLX5_ST_SZ_BYTES(qpdpm_reg);
1045+ void *qpdpm_dscp;
1046+ void *out;
1047+ void *in;
1048+ int err;
1049+ int i;
1050+
1051+ in = kzalloc(sz, GFP_KERNEL);
1052+ out = kzalloc(sz, GFP_KERNEL);
1053+ if (!in || !out) {
1054+ err = -ENOMEM;
1055+ goto out;
1056+ }
1057+
1058+ MLX5_SET(qpdpm_reg, in, local_port, 1);
1059+ err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0);
1060+ if (err)
1061+ goto out;
1062+
1063+ for (i = 0; i < (MLX5E_SUPPORTED_DSCP); i++) {
1064+ qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, out, dscp[i]);
1065+ dscp2prio[i] = MLX5_GET16(qpdpm_dscp_reg, qpdpm_dscp, prio);
1066+ }
1067+
1068+out:
1069+ kfree(in);
1070+ kfree(out);
1071+ return err;
1072+}
include/linux/mlx5/device.h+31−0
@@ -49,11 +49,15 @@ · 48 unmodified lines
4949 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
5050 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
5151 #define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld))
52+#define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
5253 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
5354 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
55+#define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
5456 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
5557 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
5658 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
59+#define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
60+#define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
5761 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
5862
5963 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
@@ -116,6 +120,19 @@ __mlx5_mask(typ, fld)) · 56 unmodified lines
116120 ___t; \
117121 })
118122
123+#define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
124+__mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
125+__mlx5_mask16(typ, fld))
126+
127+#define MLX5_SET16(typ, p, fld, v) do { \
128+ u16 _v = v; \
129+ BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \
130+ *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
131+ cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
132+ (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
133+ << __mlx5_16_bit_off(typ, fld))); \
134+} while (0)
135+
119136 /* Big endian getters */
120137 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
121138 __mlx5_64_off(typ, fld)))
@@ -1000,6 +1017,14 @@ enum mlx5_mcam_feature_groups { · 878 unmodified lines
10001017 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
10011018 };
10021019
1020+enum mlx5_qcam_reg_groups {
1021+ MLX5_QCAM_REGS_FIRST_128 = 0x0,
1022+};
1023+
1024+enum mlx5_qcam_feature_groups {
1025+ MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1026+};
1027+
10031028 /* GET Dev Caps macros */
10041029 #define MLX5_CAP_GEN(mdev, cap) \
10051030 MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
@@ -1108,6 +1133,12 @@ enum mlx5_mcam_feature_groups { · 102 unmodified lines
11081133 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
11091134 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
11101135
1136+#define MLX5_CAP_QCAM_REG(mdev, fld) \
1137+ MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1138+
1139+#define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1140+ MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1141+
11111142 #define MLX5_CAP_FPGA(mdev, cap) \
11121143 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
11131144
include/linux/mlx5/driver.h+9−0
@@ -107,8 +107,11 @@ enum { · 106 unmodified lines
107107 };
108108
109109 enum {
110+ MLX5_REG_QPTS = 0x4002,
110111 MLX5_REG_QETCR = 0x4005,
111112 MLX5_REG_QTCT = 0x400a,
113+ MLX5_REG_QPDPM = 0x4013,
114+ MLX5_REG_QCAM = 0x4019,
112115 MLX5_REG_DCBX_PARAM = 0x4020,
113116 MLX5_REG_DCBX_APP = 0x4021,
114117 MLX5_REG_FPGA_CAP = 0x4022,
@@ -141,6 +144,11 @@ enum { · 26 unmodified lines
141144 MLX5_REG_MCAM = 0x907f,
142145 };
143146
147+enum mlx5_qpts_trust_state {
148+ MLX5_QPTS_TRUST_PCP = 1,
149+ MLX5_QPTS_TRUST_DSCP = 2,
150+};
151+
144152 enum mlx5_dcbx_oper_mode {
145153 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
146154 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
@@ -798,6 +806,7 @@ struct mlx5_core_dev { · 651 unmodified lines
798806 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
799807 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
800808 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
809+ u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
801810 } caps;
802811 phys_addr_t iseg_base;
803812 struct mlx5_init_seg __iomem *iseg;
include/linux/mlx5/mlx5_ifc.h+59−1
@@ -838,7 +838,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 837 unmodified lines
838838 u8 cc_modify_allowed[0x1];
839839 u8 start_pad[0x1];
840840 u8 cache_line_128byte[0x1];
841− u8 reserved_at_165[0xb];
841+ u8 reserved_at_165[0xa];
842+ u8 qcam_reg[0x1];
842843 u8 gid_table_size[0x10];
843844
844845 u8 out_of_seq_cnt[0x1];
@@ -7890,6 +7891,43 @@ struct mlx5_ifc_mcam_reg_bits { · 7045 unmodified lines
78907891 u8 reserved_at_1c0[0x80];
78917892 };
78927893
7894+struct mlx5_ifc_qcam_access_reg_cap_mask {
7895+ u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
7896+ u8 qpdpm[0x1];
7897+ u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
7898+ u8 qdpm[0x1];
7899+ u8 qpts[0x1];
7900+ u8 qcap[0x1];
7901+ u8 qcam_access_reg_cap_mask_0[0x1];
7902+};
7903+
7904+struct mlx5_ifc_qcam_qos_feature_cap_mask {
7905+ u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
7906+ u8 qpts_trust_both[0x1];
7907+};
7908+
7909+struct mlx5_ifc_qcam_reg_bits {
7910+ u8 reserved_at_0[0x8];
7911+ u8 feature_group[0x8];
7912+ u8 reserved_at_10[0x8];
7913+ u8 access_reg_group[0x8];
7914+ u8 reserved_at_20[0x20];
7915+
7916+ union {
7917+ struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
7918+ u8 reserved_at_0[0x80];
7919+ } qos_access_reg_cap_mask;
7920+
7921+ u8 reserved_at_c0[0x80];
7922+
7923+ union {
7924+ struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
7925+ u8 reserved_at_0[0x80];
7926+ } qos_feature_cap_mask;
7927+
7928+ u8 reserved_at_1c0[0x80];
7929+};
7930+
78937931 struct mlx5_ifc_pcap_reg_bits {
78947932 u8 reserved_at_0[0x8];
78957933 u8 local_port[0x8];
@@ -8540,6 +8578,26 @@ struct mlx5_ifc_qetc_reg_bits { · 644 unmodified lines
85408578 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
85418579 };
85428580
8581+struct mlx5_ifc_qpdpm_dscp_reg_bits {
8582+ u8 e[0x1];
8583+ u8 reserved_at_01[0x0b];
8584+ u8 prio[0x04];
8585+};
8586+
8587+struct mlx5_ifc_qpdpm_reg_bits {
8588+ u8 reserved_at_0[0x8];
8589+ u8 local_port[0x8];
8590+ u8 reserved_at_10[0x10];
8591+ struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
8592+};
8593+
8594+struct mlx5_ifc_qpts_reg_bits {
8595+ u8 reserved_at_0[0x8];
8596+ u8 local_port[0x8];
8597+ u8 reserved_at_10[0x2d];
8598+ u8 trust_state[0x3];
8599+};
8600+
85438601 struct mlx5_ifc_qtct_reg_bits {
85448602 u8 reserved_at_0[0x8];
85458603 u8 port_number[0x8];
include/linux/mlx5/port.h+5−0
@@ -179,4 +179,9 @@ int mlx5_query_module_eeprom(struct mlx5_core_dev *dev, · 178 unmodified lines
179179
180180 int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out);
181181 int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in);
182+
183+int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state);
184+int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state);
185+int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio);
186+int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio);
182187 #endif /* __MLX5_PORT_H__ */
include/uapi/linux/dcbnl.h+1−0
@@ -206,6 +206,7 @@ struct cee_pfc { · 205 unmodified lines
206206 #define IEEE_8021QAZ_APP_SEL_STREAM 2
207207 #define IEEE_8021QAZ_APP_SEL_DGRAM 3
208208 #define IEEE_8021QAZ_APP_SEL_ANY 4
209+#define IEEE_8021QAZ_APP_SEL_DSCP 5
209210
210211 /* This structure contains the IEEE 802.1Qaz APP managed object. This
211212 * object is also used for the CEE std as well.