Define 200G, 400G and 800G link modes using 200Gbps per lane.
Unified · Split
| @@ -13,7 +13,7 @@ · 12 unmodified lines | ||
| 13 | 13 | */ |
| 14 | 14 | const char *phy_speed_to_str(int speed) |
| 15 | 15 | { |
| 16 | − BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 103, | |
| 16 | + BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 121, | |
| 17 | 17 | "Enum ethtool_link_mode_bit_indices and phylib are out of sync. " |
| 18 | 18 | "If a speed or mode has been added please update phy_speed_to_str " |
| 19 | 19 | "and the PHY settings array.\n"); |
| @@ -169,6 +169,12 @@ static const struct phy_setting settings[] = { · 149 unmodified lines | ||
| 169 | 169 | PHY_SETTING( 800000, FULL, 800000baseDR8_2_Full ), |
| 170 | 170 | PHY_SETTING( 800000, FULL, 800000baseSR8_Full ), |
| 171 | 171 | PHY_SETTING( 800000, FULL, 800000baseVR8_Full ), |
| 172 | + PHY_SETTING( 800000, FULL, 800000baseCR4_Full ), | |
| 173 | + PHY_SETTING( 800000, FULL, 800000baseKR4_Full ), | |
| 174 | + PHY_SETTING( 800000, FULL, 800000baseDR4_Full ), | |
| 175 | + PHY_SETTING( 800000, FULL, 800000baseDR4_2_Full ), | |
| 176 | + PHY_SETTING( 800000, FULL, 800000baseSR4_Full ), | |
| 177 | + PHY_SETTING( 800000, FULL, 800000baseVR4_Full ), | |
| 172 | 178 | /* 400G */ |
| 173 | 179 | PHY_SETTING( 400000, FULL, 400000baseCR8_Full ), |
| 174 | 180 | PHY_SETTING( 400000, FULL, 400000baseKR8_Full ), |
| @@ -180,6 +186,12 @@ static const struct phy_setting settings[] = { · 5 unmodified lines | ||
| 180 | 186 | PHY_SETTING( 400000, FULL, 400000baseLR4_ER4_FR4_Full ), |
| 181 | 187 | PHY_SETTING( 400000, FULL, 400000baseDR4_Full ), |
| 182 | 188 | PHY_SETTING( 400000, FULL, 400000baseSR4_Full ), |
| 189 | + PHY_SETTING( 400000, FULL, 400000baseCR2_Full ), | |
| 190 | + PHY_SETTING( 400000, FULL, 400000baseKR2_Full ), | |
| 191 | + PHY_SETTING( 400000, FULL, 400000baseDR2_Full ), | |
| 192 | + PHY_SETTING( 400000, FULL, 400000baseDR2_2_Full ), | |
| 193 | + PHY_SETTING( 400000, FULL, 400000baseSR2_Full ), | |
| 194 | + PHY_SETTING( 400000, FULL, 400000baseVR2_Full ), | |
| 183 | 195 | /* 200G */ |
| 184 | 196 | PHY_SETTING( 200000, FULL, 200000baseCR4_Full ), |
| 185 | 197 | PHY_SETTING( 200000, FULL, 200000baseKR4_Full ), |
| @@ -191,6 +203,12 @@ static const struct phy_setting settings[] = { · 5 unmodified lines | ||
| 191 | 203 | PHY_SETTING( 200000, FULL, 200000baseLR2_ER2_FR2_Full ), |
| 192 | 204 | PHY_SETTING( 200000, FULL, 200000baseDR2_Full ), |
| 193 | 205 | PHY_SETTING( 200000, FULL, 200000baseSR2_Full ), |
| 206 | + PHY_SETTING( 200000, FULL, 200000baseCR_Full ), | |
| 207 | + PHY_SETTING( 200000, FULL, 200000baseKR_Full ), | |
| 208 | + PHY_SETTING( 200000, FULL, 200000baseDR_Full ), | |
| 209 | + PHY_SETTING( 200000, FULL, 200000baseDR_2_Full ), | |
| 210 | + PHY_SETTING( 200000, FULL, 200000baseSR_Full ), | |
| 211 | + PHY_SETTING( 200000, FULL, 200000baseVR_Full ), | |
| 194 | 212 | /* 100G */ |
| 195 | 213 | PHY_SETTING( 100000, FULL, 100000baseCR4_Full ), |
| 196 | 214 | PHY_SETTING( 100000, FULL, 100000baseKR4_Full ), |
| @@ -2057,6 +2057,24 @@ enum ethtool_link_mode_bit_indices { · 2056 unmodified lines | ||
| 2057 | 2057 | ETHTOOL_LINK_MODE_10baseT1S_Half_BIT = 100, |
| 2058 | 2058 | ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT = 101, |
| 2059 | 2059 | ETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT = 102, |
| 2060 | + ETHTOOL_LINK_MODE_200000baseCR_Full_BIT = 103, | |
| 2061 | + ETHTOOL_LINK_MODE_200000baseKR_Full_BIT = 104, | |
| 2062 | + ETHTOOL_LINK_MODE_200000baseDR_Full_BIT = 105, | |
| 2063 | + ETHTOOL_LINK_MODE_200000baseDR_2_Full_BIT = 106, | |
| 2064 | + ETHTOOL_LINK_MODE_200000baseSR_Full_BIT = 107, | |
| 2065 | + ETHTOOL_LINK_MODE_200000baseVR_Full_BIT = 108, | |
| 2066 | + ETHTOOL_LINK_MODE_400000baseCR2_Full_BIT = 109, | |
| 2067 | + ETHTOOL_LINK_MODE_400000baseKR2_Full_BIT = 110, | |
| 2068 | + ETHTOOL_LINK_MODE_400000baseDR2_Full_BIT = 111, | |
| 2069 | + ETHTOOL_LINK_MODE_400000baseDR2_2_Full_BIT = 112, | |
| 2070 | + ETHTOOL_LINK_MODE_400000baseSR2_Full_BIT = 113, | |
| 2071 | + ETHTOOL_LINK_MODE_400000baseVR2_Full_BIT = 114, | |
| 2072 | + ETHTOOL_LINK_MODE_800000baseCR4_Full_BIT = 115, | |
| 2073 | + ETHTOOL_LINK_MODE_800000baseKR4_Full_BIT = 116, | |
| 2074 | + ETHTOOL_LINK_MODE_800000baseDR4_Full_BIT = 117, | |
| 2075 | + ETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT = 118, | |
| 2076 | + ETHTOOL_LINK_MODE_800000baseSR4_Full_BIT = 119, | |
| 2077 | + ETHTOOL_LINK_MODE_800000baseVR4_Full_BIT = 120, | |
| 2060 | 2078 | |
| 2061 | 2079 | /* must be last entry */ |
| 2062 | 2080 | __ETHTOOL_LINK_MODE_MASK_NBITS |
| @@ -213,6 +213,24 @@ const char link_mode_names[][ETH_GSTRING_LEN] = { · 212 unmodified lines | ||
| 213 | 213 | __DEFINE_LINK_MODE_NAME(10, T1S, Half), |
| 214 | 214 | __DEFINE_LINK_MODE_NAME(10, T1S_P2MP, Half), |
| 215 | 215 | __DEFINE_LINK_MODE_NAME(10, T1BRR, Full), |
| 216 | + __DEFINE_LINK_MODE_NAME(200000, CR, Full), | |
| 217 | + __DEFINE_LINK_MODE_NAME(200000, KR, Full), | |
| 218 | + __DEFINE_LINK_MODE_NAME(200000, DR, Full), | |
| 219 | + __DEFINE_LINK_MODE_NAME(200000, DR_2, Full), | |
| 220 | + __DEFINE_LINK_MODE_NAME(200000, SR, Full), | |
| 221 | + __DEFINE_LINK_MODE_NAME(200000, VR, Full), | |
| 222 | + __DEFINE_LINK_MODE_NAME(400000, CR2, Full), | |
| 223 | + __DEFINE_LINK_MODE_NAME(400000, KR2, Full), | |
| 224 | + __DEFINE_LINK_MODE_NAME(400000, DR2, Full), | |
| 225 | + __DEFINE_LINK_MODE_NAME(400000, DR2_2, Full), | |
| 226 | + __DEFINE_LINK_MODE_NAME(400000, SR2, Full), | |
| 227 | + __DEFINE_LINK_MODE_NAME(400000, VR2, Full), | |
| 228 | + __DEFINE_LINK_MODE_NAME(800000, CR4, Full), | |
| 229 | + __DEFINE_LINK_MODE_NAME(800000, KR4, Full), | |
| 230 | + __DEFINE_LINK_MODE_NAME(800000, DR4, Full), | |
| 231 | + __DEFINE_LINK_MODE_NAME(800000, DR4_2, Full), | |
| 232 | + __DEFINE_LINK_MODE_NAME(800000, SR4, Full), | |
| 233 | + __DEFINE_LINK_MODE_NAME(800000, VR4, Full), | |
| 216 | 234 | }; |
| 217 | 235 | static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS); |
| 218 | 236 | |
| @@ -221,8 +239,11 @@ static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS); · 2 unmodified lines | ||
| 221 | 239 | #define __LINK_MODE_LANES_CR4 4 |
| 222 | 240 | #define __LINK_MODE_LANES_CR8 8 |
| 223 | 241 | #define __LINK_MODE_LANES_DR 1 |
| 242 | +#define __LINK_MODE_LANES_DR_2 1 | |
| 224 | 243 | #define __LINK_MODE_LANES_DR2 2 |
| 244 | +#define __LINK_MODE_LANES_DR2_2 2 | |
| 225 | 245 | #define __LINK_MODE_LANES_DR4 4 |
| 246 | +#define __LINK_MODE_LANES_DR4_2 4 | |
| 226 | 247 | #define __LINK_MODE_LANES_DR8 8 |
| 227 | 248 | #define __LINK_MODE_LANES_KR 1 |
| 228 | 249 | #define __LINK_MODE_LANES_KR2 2 |
| @@ -251,6 +272,9 @@ static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS); · 22 unmodified lines | ||
| 251 | 272 | #define __LINK_MODE_LANES_T1L 1 |
| 252 | 273 | #define __LINK_MODE_LANES_T1S 1 |
| 253 | 274 | #define __LINK_MODE_LANES_T1S_P2MP 1 |
| 275 | +#define __LINK_MODE_LANES_VR 1 | |
| 276 | +#define __LINK_MODE_LANES_VR2 2 | |
| 277 | +#define __LINK_MODE_LANES_VR4 4 | |
| 254 | 278 | #define __LINK_MODE_LANES_VR8 8 |
| 255 | 279 | #define __LINK_MODE_LANES_DR8_2 8 |
| 256 | 280 | #define __LINK_MODE_LANES_T1BRR 1 |
| @@ -378,6 +402,24 @@ const struct link_mode_info link_mode_params[] = { · 121 unmodified lines | ||
| 378 | 402 | __DEFINE_LINK_MODE_PARAMS(10, T1S, Half), |
| 379 | 403 | __DEFINE_LINK_MODE_PARAMS(10, T1S_P2MP, Half), |
| 380 | 404 | __DEFINE_LINK_MODE_PARAMS(10, T1BRR, Full), |
| 405 | + __DEFINE_LINK_MODE_PARAMS(200000, CR, Full), | |
| 406 | + __DEFINE_LINK_MODE_PARAMS(200000, KR, Full), | |
| 407 | + __DEFINE_LINK_MODE_PARAMS(200000, DR, Full), | |
| 408 | + __DEFINE_LINK_MODE_PARAMS(200000, DR_2, Full), | |
| 409 | + __DEFINE_LINK_MODE_PARAMS(200000, SR, Full), | |
| 410 | + __DEFINE_LINK_MODE_PARAMS(200000, VR, Full), | |
| 411 | + __DEFINE_LINK_MODE_PARAMS(400000, CR2, Full), | |
| 412 | + __DEFINE_LINK_MODE_PARAMS(400000, KR2, Full), | |
| 413 | + __DEFINE_LINK_MODE_PARAMS(400000, DR2, Full), | |
| 414 | + __DEFINE_LINK_MODE_PARAMS(400000, DR2_2, Full), | |
| 415 | + __DEFINE_LINK_MODE_PARAMS(400000, SR2, Full), | |
| 416 | + __DEFINE_LINK_MODE_PARAMS(400000, VR2, Full), | |
| 417 | + __DEFINE_LINK_MODE_PARAMS(800000, CR4, Full), | |
| 418 | + __DEFINE_LINK_MODE_PARAMS(800000, KR4, Full), | |
| 419 | + __DEFINE_LINK_MODE_PARAMS(800000, DR4, Full), | |
| 420 | + __DEFINE_LINK_MODE_PARAMS(800000, DR4_2, Full), | |
| 421 | + __DEFINE_LINK_MODE_PARAMS(800000, SR4, Full), | |
| 422 | + __DEFINE_LINK_MODE_PARAMS(800000, VR4, Full), | |
| 381 | 423 | }; |
| 382 | 424 | static_assert(ARRAY_SIZE(link_mode_params) == __ETHTOOL_LINK_MODE_MASK_NBITS); |
| 383 | 425 | |