History

Merge tag 'riscv-for-linus-6.5-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Palmer Dabbelt: "This is obviously not ideal, particularly for something this late in the cycle. Unfortunately we found some uABI issues in the vector support while reviewing the GDB port, which has triggered a revert -- probably a good sign we should have reviewed GDB before merging this, I guess I just dropped the ball because I was so worried about the context extension and libc suff I forgot. Hence the late revert. There's some risk here as we're still exposing the vector context for signal handlers, but changing that would have meant reverting all of the vector support. The issues we've found so far have been fixed already and they weren't absolute showstoppers, so we're essentially just playing it safe by holding ptrace support for another release (or until we get through a proper userspace code review). Summary: - The vector ucontext extension has been extended with vlenb - The vector registers ELF core dump note type has been changed to avoid aliasing with the CSR type used in embedded systems - Support for accessing vector registers via ptrace() has been reverted - Another build fix for the ISA spec changes around Zifencei/Zicsr that manifests on some systems built with binutils-2.37 and gcc-11.2" * tag 'riscv-for-linus-6.5-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: Fix build errors using binutils2.37 toolchains RISC-V: vector: export VLENB csr in __sc_riscv_v_state RISC-V: Remove ptrace support for vectors

Linus Torvalds committed 3 years ago

Commit 4942fed2 parents 98c6b8a ef21fa75 files · +7 −75Browse files

Unified · Split

5 files
  1. arch/riscv/Kconfig +4 −4
  2. arch/riscv/include/asm/vector.h +2 −1
  3. arch/riscv/include/uapi/asm/ptrace.h +1 −0
  4. arch/riscv/kernel/ptrace.c +0 −69
  5. include/uapi/linux/elf.h +0 −1
arch/riscv/Kconfig+4−4
@@ -580,15 +580,15 @@ config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI · 579 unmodified lines
580 and Zifencei are supported in binutils from version 2.36 onwards.580 and Zifencei are supported in binutils from version 2.36 onwards.
581 To make life easier, and avoid forcing toolchains that default to a581 To make life easier, and avoid forcing toolchains that default to a
582 newer ISA spec to version 2.2, relax the check to binutils >= 2.36.582 newer ISA spec to version 2.2, relax the check to binutils >= 2.36.
583 For clang < 17 or GCC < 11.1.0, for which this is not possible, this is583 For clang < 17 or GCC < 11.3.0, for which this is not possible or need
584 dealt with in CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC.584 special treatment, this is dealt with in TOOLCHAIN_NEEDS_OLD_ISA_SPEC.
585 585
586config TOOLCHAIN_NEEDS_OLD_ISA_SPEC586config TOOLCHAIN_NEEDS_OLD_ISA_SPEC
587 def_bool y587 def_bool y
588 depends on TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI588 depends on TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
589 # https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d4498694e15bf8a16589 # https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d4498694e15bf8a16
590 # https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=b03be74bad08c382da47e048007a78fa3fb4ef49590 # https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=d29f5d6ab513c52fd872f532c492e35ae9fd6671
591 depends on (CC_IS_CLANG && CLANG_VERSION < 170000) || (CC_IS_GCC && GCC_VERSION < 110100)591 depends on (CC_IS_CLANG && CLANG_VERSION < 170000) || (CC_IS_GCC && GCC_VERSION < 110300)
592 help592 help
593 Certain versions of clang and GCC do not support zicsr and zifencei via593 Certain versions of clang and GCC do not support zicsr and zifencei via
594 -march. This option causes an older ISA spec compatible with these older594 -march. This option causes an older ISA spec compatible with these older
arch/riscv/include/asm/vector.h+2−1
@@ -70,8 +70,9 @@ static __always_inline void __vstate_csr_save(struct __riscv_v_ext_state *dest) · 69 unmodified lines
70 "csrr %1, " __stringify(CSR_VTYPE) "\n\t"70 "csrr %1, " __stringify(CSR_VTYPE) "\n\t"
71 "csrr %2, " __stringify(CSR_VL) "\n\t"71 "csrr %2, " __stringify(CSR_VL) "\n\t"
72 "csrr %3, " __stringify(CSR_VCSR) "\n\t"72 "csrr %3, " __stringify(CSR_VCSR) "\n\t"
73 "csrr %4, " __stringify(CSR_VLENB) "\n\t"
73 : "=r" (dest->vstart), "=r" (dest->vtype), "=r" (dest->vl),74 : "=r" (dest->vstart), "=r" (dest->vtype), "=r" (dest->vl),
74 "=r" (dest->vcsr) : :);75 "=r" (dest->vcsr), "=r" (dest->vlenb) : :);
75}76}
76 77
77static __always_inline void __vstate_csr_restore(struct __riscv_v_ext_state *src)78static __always_inline void __vstate_csr_restore(struct __riscv_v_ext_state *src)
arch/riscv/include/uapi/asm/ptrace.h+1−0
@@ -97,6 +97,7 @@ struct __riscv_v_ext_state { · 96 unmodified lines
97 unsigned long vl;97 unsigned long vl;
98 unsigned long vtype;98 unsigned long vtype;
99 unsigned long vcsr;99 unsigned long vcsr;
100 unsigned long vlenb;
100 void *datap;101 void *datap;
101 /*102 /*
102 * In signal handler, datap will be set a correct user stack offset103 * In signal handler, datap will be set a correct user stack offset
arch/riscv/kernel/ptrace.c+0−69
@@ -25,9 +25,6 @@ enum riscv_regset { · 24 unmodified lines
25#ifdef CONFIG_FPU25#ifdef CONFIG_FPU
26 REGSET_F,26 REGSET_F,
27#endif27#endif
28#ifdef CONFIG_RISCV_ISA_V
29 REGSET_V,
30#endif
31};28};
32 29
33static int riscv_gpr_get(struct task_struct *target,30static int riscv_gpr_get(struct task_struct *target,
@@ -84,61 +81,6 @@ static int riscv_fpr_set(struct task_struct *target, · 50 unmodified lines
84}81}
85#endif82#endif
86 83
87#ifdef CONFIG_RISCV_ISA_V
88static int riscv_vr_get(struct task_struct *target,
89 const struct user_regset *regset,
90 struct membuf to)
91{
92 struct __riscv_v_ext_state *vstate = &target->thread.vstate;
93
94 if (!riscv_v_vstate_query(task_pt_regs(target)))
95 return -EINVAL;
96
97 /*
98 * Ensure the vector registers have been saved to the memory before
99 * copying them to membuf.
100 */
101 if (target == current)
102 riscv_v_vstate_save(current, task_pt_regs(current));
103
104 /* Copy vector header from vstate. */
105 membuf_write(&to, vstate, offsetof(struct __riscv_v_ext_state, datap));
106 membuf_zero(&to, sizeof(vstate->datap));
107
108 /* Copy all the vector registers from vstate. */
109 return membuf_write(&to, vstate->datap, riscv_v_vsize);
110}
111
112static int riscv_vr_set(struct task_struct *target,
113 const struct user_regset *regset,
114 unsigned int pos, unsigned int count,
115 const void *kbuf, const void __user *ubuf)
116{
117 int ret, size;
118 struct __riscv_v_ext_state *vstate = &target->thread.vstate;
119
120 if (!riscv_v_vstate_query(task_pt_regs(target)))
121 return -EINVAL;
122
123 /* Copy rest of the vstate except datap */
124 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate, 0,
125 offsetof(struct __riscv_v_ext_state, datap));
126 if (unlikely(ret))
127 return ret;
128
129 /* Skip copy datap. */
130 size = sizeof(vstate->datap);
131 count -= size;
132 ubuf += size;
133
134 /* Copy all the vector registers. */
135 pos = 0;
136 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate->datap,
137 0, riscv_v_vsize);
138 return ret;
139}
140#endif
141
142static const struct user_regset riscv_user_regset[] = {84static const struct user_regset riscv_user_regset[] = {
143 [REGSET_X] = {85 [REGSET_X] = {
144 .core_note_type = NT_PRSTATUS,86 .core_note_type = NT_PRSTATUS,
@@ -158,17 +100,6 @@ static const struct user_regset riscv_user_regset[] = { · 13 unmodified lines
158 .set = riscv_fpr_set,100 .set = riscv_fpr_set,
159 },101 },
160#endif102#endif
161#ifdef CONFIG_RISCV_ISA_V
162 [REGSET_V] = {
163 .core_note_type = NT_RISCV_VECTOR,
164 .align = 16,
165 .n = ((32 * RISCV_MAX_VLENB) +
166 sizeof(struct __riscv_v_ext_state)) / sizeof(__u32),
167 .size = sizeof(__u32),
168 .regset_get = riscv_vr_get,
169 .set = riscv_vr_set,
170 },
171#endif
172};103};
173 104
174static const struct user_regset_view riscv_user_native_view = {105static const struct user_regset_view riscv_user_native_view = {
include/uapi/linux/elf.h+0−1
@@ -443,7 +443,6 @@ typedef struct elf64_shdr { · 442 unmodified lines
443#define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers */443#define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers */
444#define NT_MIPS_FP_MODE 0x801 /* MIPS floating-point mode */444#define NT_MIPS_FP_MODE 0x801 /* MIPS floating-point mode */
445#define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */445#define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */
446#define NT_RISCV_VECTOR 0x900 /* RISC-V vector registers */
447#define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */446#define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */
448#define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */447#define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */
449#define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension registers */448#define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension registers */