Merge tag 'drm-next-2018-12-14' of git://anongit.freedesktop.org/drm/drm

Pull drm updates from Dave Airlie: "Core: - shared fencing staging removal - drop transactional atomic helpers and move helpers to new location - DP/MST atomic cleanup - Leasing cleanups and drop EXPORT_SYMBOL - Convert drivers to atomic helpers and generic fbdev. - removed deprecated obj_ref/unref in favour of get/put - Improve dumb callback documentation - MODESET_LOCK_BEGIN/END helpers panels: - CDTech panels, Banana Pi Panel, DLC1010GIG, - Olimex LCD-O-LinuXino, Samsung S6D16D0, Truly NT35597 WQXGA, - Himax HX8357D, simulated RTSM AEMv8. - GPD Win2 panel - AUO G101EVN010 vgem: - render node support ttm: - move global init out of drivers - fix LRU handling for ghost objects - Support for simultaneous submissions to multiple engines scheduler: - timeout/fault handling changes to help GPU recovery - helpers for hw with preemption support i915: - Scaler/Watermark fixes - DP MST + powerwell fixes - PSR fixes - Break long get/put shmemfs pages - Icelake fixes - Icelake DSI video mode enablement - Engine workaround improvements amdgpu: - freesync support - GPU reset enabled on CI, VI, SOC15 dGPUs - ABM support in DC - KFD support for vega12/polaris12 - SDMA paging queue on vega - More amdkfd code sharing - DCC scanout on GFX9 - DC kerneldoc - Updated SMU firmware for GFX8 chips - XGMI PSP + hive reset support - GPU reset - DC trace support - Powerplay updates for newer Polaris - Cursor plane update fast path - kfd dma-buf support virtio-gpu: - add EDID support vmwgfx: - pageflip with damage support nouveau: - Initial Turing TU104/TU106 modesetting support msm: - a2xx gpu support for apq8060 and imx5 - a2xx gpummu support - mdp4 display support for apq8060 - DPU fixes and cleanups - enhanced profiling support - debug object naming interface - get_iova/page pinning decoupling tegra: - Tegra194 host1x, VIC and display support enabled - Audio over HDMI for Tegra186 and Tegra194 exynos: - DMA/IOMMU refactoring - plane alpha + blend mode support - Color format fixes for mixer driver rcar-du: - R8A7744 and R8A77470 support - R8A77965 LVDS support imx: - fbdev emulation fix - multi-tiled scalling fixes - SPDX identifiers rockchip - dw_hdmi support - dw-mipi-dsi + dual dsi support - mailbox read size fix qxl: - fix cursor pinning vc4: - YUV support (scaling + cursor) v3d: - enable TFU (Texture Formatting Unit) mali-dp: - add support for linear tiled formats sun4i: - Display Engine 3 support - H6 DE3 mixer 0 support - H6 display engine support - dw-hdmi support - H6 HDMI phy support - implicit fence waiting - BGRX8888 support meson: - Overlay plane support - implicit fence waiting - HDMI 1.4 4k modes bridge: - i2c fixes for sii902x" * tag 'drm-next-2018-12-14' of git://anongit.freedesktop.org/drm/drm: (1403 commits) drm/amd/display: Add fast path for cursor plane updates drm/amdgpu: Enable GPU recovery by default for CI drm/amd/display: Fix duplicating scaling/underscan connector state drm/amd/display: Fix unintialized max_bpc state values Revert "drm/amd/display: Set RMX_ASPECT as default" drm/amdgpu: Fix stub function name drm/msm/dpu: Fix clock issue after bind failure drm/msm/dpu: Clean up dpu_media_info.h static inline functions drm/msm/dpu: Further cleanups for static inline functions drm/msm/dpu: Cleanup the debugfs functions drm/msm/dpu: Remove dpu_irq and unused functions drm/msm: Make irq_postinstall optional drm/msm/dpu: Cleanup callers of dpu_hw_blk_init drm/msm/dpu: Remove unused functions drm/msm/dpu: Remove dpu_crtc_is_enabled() drm/msm/dpu: Remove dpu_crtc_get_mixer_height drm/msm/dpu: Remove dpu_dbg drm/msm: dpu: Remove crtc_lock drm/msm: dpu: Remove vblank_requested flag from dpu_crtc drm/msm: dpu: Separate crtc assignment from vblank enable ...

Linus Torvalds committed 7 years ago

Commit 4971f092 parents c76cd63 2a3c83f1030 files · +47033 −26462Browse files

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include/uapi/drm/amdgpu_drm.h +6 −0
include/uapi/drm/drm_fourcc.h +15 −0
include/uapi/drm/drm_mode.h +19 −0
include/uapi/drm/i915_drm.h +8 −0
include/uapi/drm/msm_drm.h +19 −6
include/uapi/drm/v3d_drm.h +37 −2
include/uapi/drm/virtgpu_drm.h +10 −3
include/uapi/linux/kfd_ioctl.h +25 −1
include/uapi/linux/virtio_gpu.h +18 −0

include/uapi/drm/amdgpu_drm.h+6−0

 /* GFX9 and later: */
 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT		0
 #define AMDGPU_TILING_SWIZZLE_MODE_MASK			0x1f
+#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT		5
+#define AMDGPU_TILING_DCC_OFFSET_256B_MASK		0xFFFFFF
+#define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT		29
+#define AMDGPU_TILING_DCC_PITCH_MAX_MASK		0x3FFF
+#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT		43
+#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK		0x1
 /* Set/Get helpers for tiling flags. */
 #define AMDGPU_TILING_SET(field, value) \

include/uapi/drm/drm_fourcc.h+15−0

@@ -151,6 +151,21 @@ extern "C" { · 150 unmodified lines
151	#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */	151	#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
152		152
153	#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */	153	#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
		154	#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
		155
		156	/*
		157	* packed YCbCr420 2x2 tiled formats
		158	* first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
		159	*/
		160	/* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
		161	#define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0')
		162	/* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
		163	#define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0')
		164
		165	/* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
		166	#define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')
		167	/* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
		168	#define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')
154		169
155	/*	170	/*
156	* 2 plane RGB + A	171	* 2 plane RGB + A

include/uapi/drm/drm_mode.h+19−0

@@ -888,6 +888,25 @@ struct drm_mode_revoke_lease { · 887 unmodified lines
888	__u32 lessee_id;	888	__u32 lessee_id;
889	};	889	};
890		890
		891	/**
		892	* struct drm_mode_rect - Two dimensional rectangle.
		893	* @x1: Horizontal starting coordinate (inclusive).
		894	* @y1: Vertical starting coordinate (inclusive).
		895	* @x2: Horizontal ending coordinate (exclusive).
		896	* @y2: Vertical ending coordinate (exclusive).
		897	*
		898	* With drm subsystem using struct drm_rect to manage rectangular area this
		899	* export it to user-space.
		900	*
		901	* Currently used by drm_mode_atomic blob property FB_DAMAGE_CLIPS.
		902	*/
		903	struct drm_mode_rect {
		904	__s32 x1;
		905	__s32 y1;
		906	__s32 x2;
		907	__s32 y2;
		908	};
		909
891	#if defined(__cplusplus)	910	#if defined(__cplusplus)
892	}	911	}
893	#endif	912	#endif

include/uapi/drm/i915_drm.h+8−0

@@ -412,6 +412,14 @@ typedef struct drm_i915_irq_wait { · 411 unmodified lines
412	int irq_seq;	412	int irq_seq;
413	} drm_i915_irq_wait_t;	413	} drm_i915_irq_wait_t;
414		414
		415	/*
		416	* Different modes of per-process Graphics Translation Table,
		417	* see I915_PARAM_HAS_ALIASING_PPGTT
		418	*/
		419	#define I915_GEM_PPGTT_NONE 0
		420	#define I915_GEM_PPGTT_ALIASING 1
		421	#define I915_GEM_PPGTT_FULL 2
		422
415	/* Ioctl to query kernel params:	423	/* Ioctl to query kernel params:
416	*/	424	*/
417	#define I915_PARAM_IRQ_ACTIVE 1	425	#define I915_PARAM_IRQ_ACTIVE 1

include/uapi/drm/msm_drm.h+19−6

@@ -105,14 +105,24 @@ struct drm_msm_gem_new { · 104 unmodified lines
105	__u32 handle; /* out */	105	__u32 handle; /* out */
106	};	106	};
107		107
108	#define MSM_INFO_IOVA 0x01	108	/* Get or set GEM buffer info. The requested value can be passed
109		109	* directly in 'value', or for data larger than 64b 'value' is a
110	#define MSM_INFO_FLAGS (MSM_INFO_IOVA)	110	* pointer to userspace buffer, with 'len' specifying the number of
		111	* bytes copied into that buffer. For info returned by pointer,
		112	* calling the GEM_INFO ioctl with null 'value' will return the
		113	* required buffer size in 'len'
		114	*/
		115	#define MSM_INFO_GET_OFFSET 0x00 /* get mmap() offset, returned by value */
		116	#define MSM_INFO_GET_IOVA 0x01 /* get iova, returned by value */
		117	#define MSM_INFO_SET_NAME 0x02 /* set the debug name (by pointer) */
		118	#define MSM_INFO_GET_NAME 0x03 /* get debug name, returned by pointer */
111		119
112	struct drm_msm_gem_info {	120	struct drm_msm_gem_info {
113	__u32 handle; /* in */	121	__u32 handle; /* in */
114	__u32 flags; /* in - combination of MSM_INFO_* flags */	122	__u32 info; /* in - one of MSM_INFO_* */
115	__u64 offset; /* out, mmap() offset or iova */	123	__u64 value; /* in or out */
		124	__u32 len; /* in or out */
		125	__u32 pad;
116	};	126	};
117		127
118	#define MSM_PREP_READ 0x01	128	#define MSM_PREP_READ 0x01
@@ -188,8 +198,11 @@ struct drm_msm_gem_submit_cmd { · 69 unmodified lines
188	*/	198	*/
189	#define MSM_SUBMIT_BO_READ 0x0001	199	#define MSM_SUBMIT_BO_READ 0x0001
190	#define MSM_SUBMIT_BO_WRITE 0x0002	200	#define MSM_SUBMIT_BO_WRITE 0x0002
		201	#define MSM_SUBMIT_BO_DUMP 0x0004
191		202
192	#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ \| MSM_SUBMIT_BO_WRITE)	203	#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ \| \
		204	MSM_SUBMIT_BO_WRITE \| \
		205	MSM_SUBMIT_BO_DUMP)
193		206
194	struct drm_msm_gem_submit_bo {	207	struct drm_msm_gem_submit_bo {
195	__u32 flags; /* in, mask of MSM_SUBMIT_BO_x */	208	__u32 flags; /* in, mask of MSM_SUBMIT_BO_x */

include/uapi/drm/v3d_drm.h+37−2

 #define DRM_V3D_MMAP_BO                           0x03
 #define DRM_V3D_GET_PARAM                         0x04
 #define DRM_V3D_GET_BO_OFFSET                     0x05
+#define DRM_V3D_SUBMIT_TFU                        0x06
 #define DRM_IOCTL_V3D_SUBMIT_CL           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
 #define DRM_IOCTL_V3D_WAIT_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
 #define DRM_IOCTL_V3D_MMAP_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
 #define DRM_IOCTL_V3D_GET_PARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
 #define DRM_IOCTL_V3D_GET_BO_OFFSET       DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
+#define DRM_IOCTL_V3D_SUBMIT_TFU          DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
 /**
  * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
 	 * coordinate shader to determine where primitives land on the screen,
 	 * then writes out the state updates and draw calls necessary per tile
 	 * to the tile allocation BO.
+	 *
+	 * This BCL will block on any previous BCL submitted on the
+	 * same FD, but not on any RCL or BCLs submitted by other
+	 * clients -- that is left up to the submitter to control
+	 * using in_sync_bcl if necessary.
 	 */
 	__u32 bcl_start;
-	 /** End address of the BCL (first byte after the BCL) */
+	/** End address of the BCL (first byte after the BCL) */
 	__u32 bcl_end;
 	/* Offset of the render command list.
 	 * This is the second set of commands executed, which will either
 	 * execute the tiles that have been set up by the BCL, or a fixed set
 	 * of tiles (in the case of RCL-only blits).
+	 *
+	 * This RCL will block on this submit's BCL, and any previous
+	 * RCL submitted on the same FD, but not on any RCL or BCLs
+	 * submitted by other clients -- that is left up to the
+	 * submitter to control using in_sync_rcl if necessary.
 	 */
 	__u32 rcl_start;
-	 /** End address of the RCL (first byte after the RCL) */
+	/** End address of the RCL (first byte after the RCL) */
 	__u32 rcl_end;
 	/** An optional sync object to wait on before starting the BCL. */
 	DRM_V3D_PARAM_V3D_CORE0_IDENT0,
 	DRM_V3D_PARAM_V3D_CORE0_IDENT1,
 	DRM_V3D_PARAM_V3D_CORE0_IDENT2,
+	DRM_V3D_PARAM_SUPPORTS_TFU,
 };
 struct drm_v3d_get_param {
 	__u32 offset;
 };
+struct drm_v3d_submit_tfu {
+	__u32 icfg;
+	__u32 iia;
+	__u32 iis;
+	__u32 ica;
+	__u32 iua;
+	__u32 ioa;
+	__u32 ios;
+	__u32 coef[4];
+	/* First handle is the output BO, following are other inputs.
+	 * 0 for unused.
+	 */
+	__u32 bo_handles[4];
+	/* sync object to block on before running the TFU job.  Each TFU
+	 * job will execute in the order submitted to its FD.  Synchronization
+	 * against rendering jobs requires using sync objects.
+	 */
+	__u32 in_sync;
+	/* Sync object to signal when the TFU job is done. */
+	__u32 out_sync;
+};
 #if defined(__cplusplus)
 }
 #endif

include/uapi/drm/virtgpu_drm.h+10−3

 #define DRM_VIRTGPU_WAIT     0x08
 #define DRM_VIRTGPU_GET_CAPS  0x09
+#define VIRTGPU_EXECBUF_FENCE_FD_IN	0x01
+#define VIRTGPU_EXECBUF_FENCE_FD_OUT	0x02
+#define VIRTGPU_EXECBUF_FLAGS  (\
+		VIRTGPU_EXECBUF_FENCE_FD_IN |\
+		VIRTGPU_EXECBUF_FENCE_FD_OUT |\
+		0)
 struct drm_virtgpu_map {
 	__u64 offset; /* use for mmap system call */
 	__u32 handle;
 };
 struct drm_virtgpu_execbuffer {
-	__u32		flags;		/* for future use */
+	__u32 flags;
 	__u32 size;
 	__u64 command; /* void* */
 	__u64 bo_handles;
 	__u32 num_bo_handles;
-	__u32 pad;
+	__s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */
 };
 #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
 #define DRM_IOCTL_VIRTGPU_EXECBUFFER \
-	DRM_IOW(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\
+	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\
 		struct drm_virtgpu_execbuffer)
 #define DRM_IOCTL_VIRTGPU_GETPARAM \

include/uapi/linux/kfd_ioctl.h+25−1

@@ -398,6 +398,24 @@ struct kfd_ioctl_unmap_memory_from_gpu_args { · 397 unmodified lines
398	__u32 n_success; /* to/from KFD */	398	__u32 n_success; /* to/from KFD */
399	};	399	};
400		400
		401	struct kfd_ioctl_get_dmabuf_info_args {
		402	__u64 size; /* from KFD */
		403	__u64 metadata_ptr; /* to KFD */
		404	__u32 metadata_size; /* to KFD (space allocated by user)
		405	* from KFD (actual metadata size)
		406	*/
		407	__u32 gpu_id; /* from KFD */
		408	__u32 flags; /* from KFD (KFD_IOC_ALLOC_MEM_FLAGS) */
		409	__u32 dmabuf_fd; /* to KFD */
		410	};
		411
		412	struct kfd_ioctl_import_dmabuf_args {
		413	__u64 va_addr; /* to KFD */
		414	__u64 handle; /* from KFD */
		415	__u32 gpu_id; /* to KFD */
		416	__u32 dmabuf_fd; /* to KFD */
		417	};
		418
401	#define AMDKFD_IOCTL_BASE 'K'	419	#define AMDKFD_IOCTL_BASE 'K'
402	#define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr)	420	#define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr)
403	#define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type)	421	#define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type)
@@ -486,7 +504,13 @@ struct kfd_ioctl_unmap_memory_from_gpu_args { · 82 unmodified lines
486	#define AMDKFD_IOC_GET_QUEUE_WAVE_STATE \	504	#define AMDKFD_IOC_GET_QUEUE_WAVE_STATE \
487	AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args)	505	AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args)
488		506
		507	#define AMDKFD_IOC_GET_DMABUF_INFO \
		508	AMDKFD_IOWR(0x1C, struct kfd_ioctl_get_dmabuf_info_args)
		509
		510	#define AMDKFD_IOC_IMPORT_DMABUF \
		511	AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args)
		512
489	#define AMDKFD_COMMAND_START 0x01	513	#define AMDKFD_COMMAND_START 0x01
490	#define AMDKFD_COMMAND_END 0x1C	514	#define AMDKFD_COMMAND_END 0x1E
491		515
492	#endif	516	#endif

include/uapi/linux/virtio_gpu.h+18−0

 #include <linux/types.h>
 #define VIRTIO_GPU_F_VIRGL 0
+#define VIRTIO_GPU_F_EDID  1
 enum virtio_gpu_ctrl_type {
 	VIRTIO_GPU_UNDEFINED = 0,
 	VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
 	VIRTIO_GPU_CMD_GET_CAPSET_INFO,
 	VIRTIO_GPU_CMD_GET_CAPSET,
+	VIRTIO_GPU_CMD_GET_EDID,
 	/* 3d commands */
 	VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
 	VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
 	VIRTIO_GPU_RESP_OK_CAPSET_INFO,
 	VIRTIO_GPU_RESP_OK_CAPSET,
+	VIRTIO_GPU_RESP_OK_EDID,
 	/* error responses */
 	VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
 	__u8 capset_data[];
 };
+/* VIRTIO_GPU_CMD_GET_EDID */
+struct virtio_gpu_cmd_get_edid {
+	struct virtio_gpu_ctrl_hdr hdr;
+	__le32 scanout;
+	__le32 padding;
+};
+/* VIRTIO_GPU_RESP_OK_EDID */
+struct virtio_gpu_resp_edid {
+	struct virtio_gpu_ctrl_hdr hdr;
+	__le32 size;
+	__le32 padding;
+	__u8 edid[1024];
+};
 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
 struct virtio_gpu_config {

Merge tag 'drm-next-2018-12-14' of git://anongit.freedesktop.org/drm/drm

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