Pull drm updates from Dave Airlie: "Core: - shared fencing staging removal - drop transactional atomic helpers and move helpers to new location - DP/MST atomic cleanup - Leasing cleanups and drop EXPORT_SYMBOL - Convert drivers to atomic helpers and generic fbdev. - removed deprecated obj_ref/unref in favour of get/put - Improve dumb callback documentation - MODESET_LOCK_BEGIN/END helpers panels: - CDTech panels, Banana Pi Panel, DLC1010GIG, - Olimex LCD-O-LinuXino, Samsung S6D16D0, Truly NT35597 WQXGA, - Himax HX8357D, simulated RTSM AEMv8. - GPD Win2 panel - AUO G101EVN010 vgem: - render node support ttm: - move global init out of drivers - fix LRU handling for ghost objects - Support for simultaneous submissions to multiple engines scheduler: - timeout/fault handling changes to help GPU recovery - helpers for hw with preemption support i915: - Scaler/Watermark fixes - DP MST + powerwell fixes - PSR fixes - Break long get/put shmemfs pages - Icelake fixes - Icelake DSI video mode enablement - Engine workaround improvements amdgpu: - freesync support - GPU reset enabled on CI, VI, SOC15 dGPUs - ABM support in DC - KFD support for vega12/polaris12 - SDMA paging queue on vega - More amdkfd code sharing - DCC scanout on GFX9 - DC kerneldoc - Updated SMU firmware for GFX8 chips - XGMI PSP + hive reset support - GPU reset - DC trace support - Powerplay updates for newer Polaris - Cursor plane update fast path - kfd dma-buf support virtio-gpu: - add EDID support vmwgfx: - pageflip with damage support nouveau: - Initial Turing TU104/TU106 modesetting support msm: - a2xx gpu support for apq8060 and imx5 - a2xx gpummu support - mdp4 display support for apq8060 - DPU fixes and cleanups - enhanced profiling support - debug object naming interface - get_iova/page pinning decoupling tegra: - Tegra194 host1x, VIC and display support enabled - Audio over HDMI for Tegra186 and Tegra194 exynos: - DMA/IOMMU refactoring - plane alpha + blend mode support - Color format fixes for mixer driver rcar-du: - R8A7744 and R8A77470 support - R8A77965 LVDS support imx: - fbdev emulation fix - multi-tiled scalling fixes - SPDX identifiers rockchip - dw_hdmi support - dw-mipi-dsi + dual dsi support - mailbox read size fix qxl: - fix cursor pinning vc4: - YUV support (scaling + cursor) v3d: - enable TFU (Texture Formatting Unit) mali-dp: - add support for linear tiled formats sun4i: - Display Engine 3 support - H6 DE3 mixer 0 support - H6 display engine support - dw-hdmi support - H6 HDMI phy support - implicit fence waiting - BGRX8888 support meson: - Overlay plane support - implicit fence waiting - HDMI 1.4 4k modes bridge: - i2c fixes for sii902x" * tag 'drm-next-2018-12-14' of git://anongit.freedesktop.org/drm/drm: (1403 commits) drm/amd/display: Add fast path for cursor plane updates drm/amdgpu: Enable GPU recovery by default for CI drm/amd/display: Fix duplicating scaling/underscan connector state drm/amd/display: Fix unintialized max_bpc state values Revert "drm/amd/display: Set RMX_ASPECT as default" drm/amdgpu: Fix stub function name drm/msm/dpu: Fix clock issue after bind failure drm/msm/dpu: Clean up dpu_media_info.h static inline functions drm/msm/dpu: Further cleanups for static inline functions drm/msm/dpu: Cleanup the debugfs functions drm/msm/dpu: Remove dpu_irq and unused functions drm/msm: Make irq_postinstall optional drm/msm/dpu: Cleanup callers of dpu_hw_blk_init drm/msm/dpu: Remove unused functions drm/msm/dpu: Remove dpu_crtc_is_enabled() drm/msm/dpu: Remove dpu_crtc_get_mixer_height drm/msm/dpu: Remove dpu_dbg drm/msm: dpu: Remove crtc_lock drm/msm: dpu: Remove vblank_requested flag from dpu_crtc drm/msm: dpu: Separate crtc assignment from vblank enable ...
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| @@ -326,6 +326,12 @@ struct drm_amdgpu_gem_userptr { · 325 unmodified lines | ||
| 326 | 326 | /* GFX9 and later: */ |
| 327 | 327 | #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 |
| 328 | 328 | #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f |
| 329 | +#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 | |
| 330 | +#define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF | |
| 331 | +#define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 | |
| 332 | +#define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF | |
| 333 | +#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 | |
| 334 | +#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 | |
| 329 | 335 | |
| 330 | 336 | /* Set/Get helpers for tiling flags. */ |
| 331 | 337 | #define AMDGPU_TILING_SET(field, value) \ |
| @@ -151,6 +151,21 @@ extern "C" { · 150 unmodified lines | ||
| 151 | 151 | #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ |
| 152 | 152 | |
| 153 | 153 | #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ |
| 154 | +#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ | |
| 155 | + | |
| 156 | +/* | |
| 157 | + * packed YCbCr420 2x2 tiled formats | |
| 158 | + * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile | |
| 159 | + */ | |
| 160 | +/* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ | |
| 161 | +#define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0') | |
| 162 | +/* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ | |
| 163 | +#define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0') | |
| 164 | + | |
| 165 | +/* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ | |
| 166 | +#define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2') | |
| 167 | +/* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ | |
| 168 | +#define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2') | |
| 154 | 169 | |
| 155 | 170 | /* |
| 156 | 171 | * 2 plane RGB + A |
| @@ -888,6 +888,25 @@ struct drm_mode_revoke_lease { · 887 unmodified lines | ||
| 888 | 888 | __u32 lessee_id; |
| 889 | 889 | }; |
| 890 | 890 | |
| 891 | +/** | |
| 892 | + * struct drm_mode_rect - Two dimensional rectangle. | |
| 893 | + * @x1: Horizontal starting coordinate (inclusive). | |
| 894 | + * @y1: Vertical starting coordinate (inclusive). | |
| 895 | + * @x2: Horizontal ending coordinate (exclusive). | |
| 896 | + * @y2: Vertical ending coordinate (exclusive). | |
| 897 | + * | |
| 898 | + * With drm subsystem using struct drm_rect to manage rectangular area this | |
| 899 | + * export it to user-space. | |
| 900 | + * | |
| 901 | + * Currently used by drm_mode_atomic blob property FB_DAMAGE_CLIPS. | |
| 902 | + */ | |
| 903 | +struct drm_mode_rect { | |
| 904 | + __s32 x1; | |
| 905 | + __s32 y1; | |
| 906 | + __s32 x2; | |
| 907 | + __s32 y2; | |
| 908 | +}; | |
| 909 | + | |
| 891 | 910 | #if defined(__cplusplus) |
| 892 | 911 | } |
| 893 | 912 | #endif |
| @@ -412,6 +412,14 @@ typedef struct drm_i915_irq_wait { · 411 unmodified lines | ||
| 412 | 412 | int irq_seq; |
| 413 | 413 | } drm_i915_irq_wait_t; |
| 414 | 414 | |
| 415 | +/* | |
| 416 | + * Different modes of per-process Graphics Translation Table, | |
| 417 | + * see I915_PARAM_HAS_ALIASING_PPGTT | |
| 418 | + */ | |
| 419 | +#define I915_GEM_PPGTT_NONE 0 | |
| 420 | +#define I915_GEM_PPGTT_ALIASING 1 | |
| 421 | +#define I915_GEM_PPGTT_FULL 2 | |
| 422 | + | |
| 415 | 423 | /* Ioctl to query kernel params: |
| 416 | 424 | */ |
| 417 | 425 | #define I915_PARAM_IRQ_ACTIVE 1 |
| @@ -105,14 +105,24 @@ struct drm_msm_gem_new { · 104 unmodified lines | ||
| 105 | 105 | __u32 handle; /* out */ |
| 106 | 106 | }; |
| 107 | 107 | |
| 108 | −#define MSM_INFO_IOVA 0x01 | |
| 109 | − | |
| 110 | −#define MSM_INFO_FLAGS (MSM_INFO_IOVA) | |
| 108 | +/* Get or set GEM buffer info. The requested value can be passed | |
| 109 | + * directly in 'value', or for data larger than 64b 'value' is a | |
| 110 | + * pointer to userspace buffer, with 'len' specifying the number of | |
| 111 | + * bytes copied into that buffer. For info returned by pointer, | |
| 112 | + * calling the GEM_INFO ioctl with null 'value' will return the | |
| 113 | + * required buffer size in 'len' | |
| 114 | + */ | |
| 115 | +#define MSM_INFO_GET_OFFSET 0x00 /* get mmap() offset, returned by value */ | |
| 116 | +#define MSM_INFO_GET_IOVA 0x01 /* get iova, returned by value */ | |
| 117 | +#define MSM_INFO_SET_NAME 0x02 /* set the debug name (by pointer) */ | |
| 118 | +#define MSM_INFO_GET_NAME 0x03 /* get debug name, returned by pointer */ | |
| 111 | 119 | |
| 112 | 120 | struct drm_msm_gem_info { |
| 113 | 121 | __u32 handle; /* in */ |
| 114 | − __u32 flags; /* in - combination of MSM_INFO_* flags */ | |
| 115 | − __u64 offset; /* out, mmap() offset or iova */ | |
| 122 | + __u32 info; /* in - one of MSM_INFO_* */ | |
| 123 | + __u64 value; /* in or out */ | |
| 124 | + __u32 len; /* in or out */ | |
| 125 | + __u32 pad; | |
| 116 | 126 | }; |
| 117 | 127 | |
| 118 | 128 | #define MSM_PREP_READ 0x01 |
| @@ -188,8 +198,11 @@ struct drm_msm_gem_submit_cmd { · 69 unmodified lines | ||
| 188 | 198 | */ |
| 189 | 199 | #define MSM_SUBMIT_BO_READ 0x0001 |
| 190 | 200 | #define MSM_SUBMIT_BO_WRITE 0x0002 |
| 201 | +#define MSM_SUBMIT_BO_DUMP 0x0004 | |
| 191 | 202 | |
| 192 | −#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE) | |
| 203 | +#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | \ | |
| 204 | + MSM_SUBMIT_BO_WRITE | \ | |
| 205 | + MSM_SUBMIT_BO_DUMP) | |
| 193 | 206 | |
| 194 | 207 | struct drm_msm_gem_submit_bo { |
| 195 | 208 | __u32 flags; /* in, mask of MSM_SUBMIT_BO_x */ |
| @@ -36,6 +36,7 @@ extern "C" { · 35 unmodified lines | ||
| 36 | 36 | #define DRM_V3D_MMAP_BO 0x03 |
| 37 | 37 | #define DRM_V3D_GET_PARAM 0x04 |
| 38 | 38 | #define DRM_V3D_GET_BO_OFFSET 0x05 |
| 39 | +#define DRM_V3D_SUBMIT_TFU 0x06 | |
| 39 | 40 | |
| 40 | 41 | #define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl) |
| 41 | 42 | #define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo) |
| @@ -43,6 +44,7 @@ extern "C" { · 1 unmodified line | ||
| 43 | 44 | #define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo) |
| 44 | 45 | #define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param) |
| 45 | 46 | #define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset) |
| 47 | +#define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu) | |
| 46 | 48 | |
| 47 | 49 | /** |
| 48 | 50 | * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D |
| @@ -58,10 +60,15 @@ struct drm_v3d_submit_cl { · 9 unmodified lines | ||
| 58 | 60 | * coordinate shader to determine where primitives land on the screen, |
| 59 | 61 | * then writes out the state updates and draw calls necessary per tile |
| 60 | 62 | * to the tile allocation BO. |
| 63 | + * | |
| 64 | + * This BCL will block on any previous BCL submitted on the | |
| 65 | + * same FD, but not on any RCL or BCLs submitted by other | |
| 66 | + * clients -- that is left up to the submitter to control | |
| 67 | + * using in_sync_bcl if necessary. | |
| 61 | 68 | */ |
| 62 | 69 | __u32 bcl_start; |
| 63 | 70 | |
| 64 | − /** End address of the BCL (first byte after the BCL) */ | |
| 71 | + /** End address of the BCL (first byte after the BCL) */ | |
| 65 | 72 | __u32 bcl_end; |
| 66 | 73 | |
| 67 | 74 | /* Offset of the render command list. |
| @@ -69,10 +76,15 @@ struct drm_v3d_submit_cl { · 1 unmodified line | ||
| 69 | 76 | * This is the second set of commands executed, which will either |
| 70 | 77 | * execute the tiles that have been set up by the BCL, or a fixed set |
| 71 | 78 | * of tiles (in the case of RCL-only blits). |
| 79 | + * | |
| 80 | + * This RCL will block on this submit's BCL, and any previous | |
| 81 | + * RCL submitted on the same FD, but not on any RCL or BCLs | |
| 82 | + * submitted by other clients -- that is left up to the | |
| 83 | + * submitter to control using in_sync_rcl if necessary. | |
| 72 | 84 | */ |
| 73 | 85 | __u32 rcl_start; |
| 74 | 86 | |
| 75 | − /** End address of the RCL (first byte after the RCL) */ | |
| 87 | + /** End address of the RCL (first byte after the RCL) */ | |
| 76 | 88 | __u32 rcl_end; |
| 77 | 89 | |
| 78 | 90 | /** An optional sync object to wait on before starting the BCL. */ |
| @@ -169,6 +181,7 @@ enum drm_v3d_param { · 90 unmodified lines | ||
| 169 | 181 | DRM_V3D_PARAM_V3D_CORE0_IDENT0, |
| 170 | 182 | DRM_V3D_PARAM_V3D_CORE0_IDENT1, |
| 171 | 183 | DRM_V3D_PARAM_V3D_CORE0_IDENT2, |
| 184 | + DRM_V3D_PARAM_SUPPORTS_TFU, | |
| 172 | 185 | }; |
| 173 | 186 | |
| 174 | 187 | struct drm_v3d_get_param { |
| @@ -187,6 +200,28 @@ struct drm_v3d_get_bo_offset { · 12 unmodified lines | ||
| 187 | 200 | __u32 offset; |
| 188 | 201 | }; |
| 189 | 202 | |
| 203 | +struct drm_v3d_submit_tfu { | |
| 204 | + __u32 icfg; | |
| 205 | + __u32 iia; | |
| 206 | + __u32 iis; | |
| 207 | + __u32 ica; | |
| 208 | + __u32 iua; | |
| 209 | + __u32 ioa; | |
| 210 | + __u32 ios; | |
| 211 | + __u32 coef[4]; | |
| 212 | + /* First handle is the output BO, following are other inputs. | |
| 213 | + * 0 for unused. | |
| 214 | + */ | |
| 215 | + __u32 bo_handles[4]; | |
| 216 | + /* sync object to block on before running the TFU job. Each TFU | |
| 217 | + * job will execute in the order submitted to its FD. Synchronization | |
| 218 | + * against rendering jobs requires using sync objects. | |
| 219 | + */ | |
| 220 | + __u32 in_sync; | |
| 221 | + /* Sync object to signal when the TFU job is done. */ | |
| 222 | + __u32 out_sync; | |
| 223 | +}; | |
| 224 | + | |
| 190 | 225 | #if defined(__cplusplus) |
| 191 | 226 | } |
| 192 | 227 | #endif |
| @@ -47,6 +47,13 @@ extern "C" { · 46 unmodified lines | ||
| 47 | 47 | #define DRM_VIRTGPU_WAIT 0x08 |
| 48 | 48 | #define DRM_VIRTGPU_GET_CAPS 0x09 |
| 49 | 49 | |
| 50 | +#define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01 | |
| 51 | +#define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02 | |
| 52 | +#define VIRTGPU_EXECBUF_FLAGS (\ | |
| 53 | + VIRTGPU_EXECBUF_FENCE_FD_IN |\ | |
| 54 | + VIRTGPU_EXECBUF_FENCE_FD_OUT |\ | |
| 55 | + 0) | |
| 56 | + | |
| 50 | 57 | struct drm_virtgpu_map { |
| 51 | 58 | __u64 offset; /* use for mmap system call */ |
| 52 | 59 | __u32 handle; |
| @@ -54,12 +61,12 @@ struct drm_virtgpu_map { · 1 unmodified line | ||
| 54 | 61 | }; |
| 55 | 62 | |
| 56 | 63 | struct drm_virtgpu_execbuffer { |
| 57 | − __u32 flags; /* for future use */ | |
| 64 | + __u32 flags; | |
| 58 | 65 | __u32 size; |
| 59 | 66 | __u64 command; /* void* */ |
| 60 | 67 | __u64 bo_handles; |
| 61 | 68 | __u32 num_bo_handles; |
| 62 | − __u32 pad; | |
| 69 | + __s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */ | |
| 63 | 70 | }; |
| 64 | 71 | |
| 65 | 72 | #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */ |
| @@ -137,7 +144,7 @@ struct drm_virtgpu_get_caps { · 71 unmodified lines | ||
| 137 | 144 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map) |
| 138 | 145 | |
| 139 | 146 | #define DRM_IOCTL_VIRTGPU_EXECBUFFER \ |
| 140 | − DRM_IOW(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\ | |
| 147 | + DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\ | |
| 141 | 148 | struct drm_virtgpu_execbuffer) |
| 142 | 149 | |
| 143 | 150 | #define DRM_IOCTL_VIRTGPU_GETPARAM \ |
| @@ -398,6 +398,24 @@ struct kfd_ioctl_unmap_memory_from_gpu_args { · 397 unmodified lines | ||
| 398 | 398 | __u32 n_success; /* to/from KFD */ |
| 399 | 399 | }; |
| 400 | 400 | |
| 401 | +struct kfd_ioctl_get_dmabuf_info_args { | |
| 402 | + __u64 size; /* from KFD */ | |
| 403 | + __u64 metadata_ptr; /* to KFD */ | |
| 404 | + __u32 metadata_size; /* to KFD (space allocated by user) | |
| 405 | + * from KFD (actual metadata size) | |
| 406 | + */ | |
| 407 | + __u32 gpu_id; /* from KFD */ | |
| 408 | + __u32 flags; /* from KFD (KFD_IOC_ALLOC_MEM_FLAGS) */ | |
| 409 | + __u32 dmabuf_fd; /* to KFD */ | |
| 410 | +}; | |
| 411 | + | |
| 412 | +struct kfd_ioctl_import_dmabuf_args { | |
| 413 | + __u64 va_addr; /* to KFD */ | |
| 414 | + __u64 handle; /* from KFD */ | |
| 415 | + __u32 gpu_id; /* to KFD */ | |
| 416 | + __u32 dmabuf_fd; /* to KFD */ | |
| 417 | +}; | |
| 418 | + | |
| 401 | 419 | #define AMDKFD_IOCTL_BASE 'K' |
| 402 | 420 | #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) |
| 403 | 421 | #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) |
| @@ -486,7 +504,13 @@ struct kfd_ioctl_unmap_memory_from_gpu_args { · 82 unmodified lines | ||
| 486 | 504 | #define AMDKFD_IOC_GET_QUEUE_WAVE_STATE \ |
| 487 | 505 | AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args) |
| 488 | 506 | |
| 507 | +#define AMDKFD_IOC_GET_DMABUF_INFO \ | |
| 508 | + AMDKFD_IOWR(0x1C, struct kfd_ioctl_get_dmabuf_info_args) | |
| 509 | + | |
| 510 | +#define AMDKFD_IOC_IMPORT_DMABUF \ | |
| 511 | + AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args) | |
| 512 | + | |
| 489 | 513 | #define AMDKFD_COMMAND_START 0x01 |
| 490 | −#define AMDKFD_COMMAND_END 0x1C | |
| 514 | +#define AMDKFD_COMMAND_END 0x1E | |
| 491 | 515 | |
| 492 | 516 | #endif |
| @@ -41,6 +41,7 @@ · 40 unmodified lines | ||
| 41 | 41 | #include <linux/types.h> |
| 42 | 42 | |
| 43 | 43 | #define VIRTIO_GPU_F_VIRGL 0 |
| 44 | +#define VIRTIO_GPU_F_EDID 1 | |
| 44 | 45 | |
| 45 | 46 | enum virtio_gpu_ctrl_type { |
| 46 | 47 | VIRTIO_GPU_UNDEFINED = 0, |
| @@ -56,6 +57,7 @@ enum virtio_gpu_ctrl_type { · 9 unmodified lines | ||
| 56 | 57 | VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING, |
| 57 | 58 | VIRTIO_GPU_CMD_GET_CAPSET_INFO, |
| 58 | 59 | VIRTIO_GPU_CMD_GET_CAPSET, |
| 60 | + VIRTIO_GPU_CMD_GET_EDID, | |
| 59 | 61 | |
| 60 | 62 | /* 3d commands */ |
| 61 | 63 | VIRTIO_GPU_CMD_CTX_CREATE = 0x0200, |
| @@ -76,6 +78,7 @@ enum virtio_gpu_ctrl_type { · 14 unmodified lines | ||
| 76 | 78 | VIRTIO_GPU_RESP_OK_DISPLAY_INFO, |
| 77 | 79 | VIRTIO_GPU_RESP_OK_CAPSET_INFO, |
| 78 | 80 | VIRTIO_GPU_RESP_OK_CAPSET, |
| 81 | + VIRTIO_GPU_RESP_OK_EDID, | |
| 79 | 82 | |
| 80 | 83 | /* error responses */ |
| 81 | 84 | VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200, |
| @@ -291,6 +294,21 @@ struct virtio_gpu_resp_capset { · 209 unmodified lines | ||
| 291 | 294 | __u8 capset_data[]; |
| 292 | 295 | }; |
| 293 | 296 | |
| 297 | +/* VIRTIO_GPU_CMD_GET_EDID */ | |
| 298 | +struct virtio_gpu_cmd_get_edid { | |
| 299 | + struct virtio_gpu_ctrl_hdr hdr; | |
| 300 | + __le32 scanout; | |
| 301 | + __le32 padding; | |
| 302 | +}; | |
| 303 | + | |
| 304 | +/* VIRTIO_GPU_RESP_OK_EDID */ | |
| 305 | +struct virtio_gpu_resp_edid { | |
| 306 | + struct virtio_gpu_ctrl_hdr hdr; | |
| 307 | + __le32 size; | |
| 308 | + __le32 padding; | |
| 309 | + __u8 edid[1024]; | |
| 310 | +}; | |
| 311 | + | |
| 294 | 312 | #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0) |
| 295 | 313 | |
| 296 | 314 | struct virtio_gpu_config { |