Both RIF and ACL flow counters use a 24-bit SW-managed counter address to communicate which counter they want to bind. In a number of Spectrum FW releases, binding a RIF counter is broken and slices the counter index to 16 bits. As a result, on Spectrum-2 and above, no more than about 410 RIF counters can be effectively used. This translates to 205 netdevices for which L3 HW stats can be enabled. (This does not happen on Spectrum-1, because there are fewer counters available overall and the counter index never exceeds 16 bits.) Binding counters to ACLs does not have this issue. Therefore reorder the counter allocation scheme so that RIF counters come first and therefore get lower indices that are below the 16-bit barrier.
Unified · Split
| @@ -8,8 +8,8 @@ · 7 unmodified lines | |||
| 8 | #include "spectrum.h" | 8 | #include "spectrum.h" |
| 9 | 9 | ||
| 10 | enum mlxsw_sp_counter_sub_pool_id { | 10 | enum mlxsw_sp_counter_sub_pool_id { |
| 11 | MLXSW_SP_COUNTER_SUB_POOL_FLOW, | ||
| 12 | MLXSW_SP_COUNTER_SUB_POOL_RIF, | 11 | MLXSW_SP_COUNTER_SUB_POOL_RIF, |
| 12 | MLXSW_SP_COUNTER_SUB_POOL_FLOW, | ||
| 13 | }; | 13 | }; |
| 14 | 14 | ||
| 15 | int mlxsw_sp_counter_alloc(struct mlxsw_sp *mlxsw_sp, | 15 | int mlxsw_sp_counter_alloc(struct mlxsw_sp *mlxsw_sp, |