Flash update routine was improperly checking register read API return value. Modify register read API and perform proper error check.
Unified · Split
| @@ -1400,8 +1400,8 @@ void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64); · 1399 unmodified lines | ||
| 1400 | 1400 | #define ADDR_IN_RANGE(addr, low, high) \ |
| 1401 | 1401 | (((addr) < (high)) && ((addr) >= (low))) |
| 1402 | 1402 | |
| 1403 | −#define QLCRD32(adapter, off) \ | |
| 1404 | − (adapter->ahw->hw_ops->read_reg)(adapter, off) | |
| 1403 | +#define QLCRD32(adapter, off, err) \ | |
| 1404 | + (adapter->ahw->hw_ops->read_reg)(adapter, off, err) | |
| 1405 | 1405 | |
| 1406 | 1406 | #define QLCWR32(adapter, off, val) \ |
| 1407 | 1407 | adapter->ahw->hw_ops->write_reg(adapter, off, val) |
| @@ -1604,7 +1604,7 @@ struct qlcnic_nic_template { · 196 unmodified lines | ||
| 1604 | 1604 | struct qlcnic_hardware_ops { |
| 1605 | 1605 | void (*read_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); |
| 1606 | 1606 | void (*write_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); |
| 1607 | − int (*read_reg) (struct qlcnic_adapter *, ulong); | |
| 1607 | + int (*read_reg) (struct qlcnic_adapter *, ulong, int *); | |
| 1608 | 1608 | int (*write_reg) (struct qlcnic_adapter *, ulong, u32); |
| 1609 | 1609 | void (*get_ocm_win) (struct qlcnic_hardware_context *); |
| 1610 | 1610 | int (*get_mac_address) (struct qlcnic_adapter *, u8 *); |
| @@ -1662,12 +1662,6 @@ static inline void qlcnic_write_crb(struct qlcnic_adapter *adapter, char *buf, · 51 unmodified lines | ||
| 1662 | 1662 | adapter->ahw->hw_ops->write_crb(adapter, buf, offset, size); |
| 1663 | 1663 | } |
| 1664 | 1664 | |
| 1665 | −static inline int qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, | |
| 1666 | − ulong off) | |
| 1667 | −{ | |
| 1668 | − return adapter->ahw->hw_ops->read_reg(adapter, off); | |
| 1669 | −} | |
| 1670 | − | |
| 1671 | 1665 | static inline int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, |
| 1672 | 1666 | ulong off, u32 data) |
| 1673 | 1667 | { |
| @@ -228,17 +228,17 @@ static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr) · 227 unmodified lines | ||
| 228 | 228 | return 0; |
| 229 | 229 | } |
| 230 | 230 | |
| 231 | −int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr) | |
| 231 | +int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr, | |
| 232 | + int *err) | |
| 232 | 233 | { |
| 233 | − int ret; | |
| 234 | 234 | struct qlcnic_hardware_context *ahw = adapter->ahw; |
| 235 | 235 | |
| 236 | − ret = __qlcnic_set_win_base(adapter, (u32) addr); | |
| 237 | − if (!ret) { | |
| 236 | + *err = __qlcnic_set_win_base(adapter, (u32) addr); | |
| 237 | + if (!*err) { | |
| 238 | 238 | return QLCRDX(ahw, QLCNIC_WILDCARD); |
| 239 | 239 | } else { |
| 240 | 240 | dev_err(&adapter->pdev->dev, |
| 241 | − "%s failed, addr = 0x%x\n", __func__, (int)addr); | |
| 241 | + "%s failed, addr = 0x%lx\n", __func__, addr); | |
| 242 | 242 | return -EIO; |
| 243 | 243 | } |
| 244 | 244 | } |
| @@ -561,7 +561,7 @@ void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter) · 316 unmodified lines | ||
| 561 | 561 | void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf, |
| 562 | 562 | loff_t offset, size_t size) |
| 563 | 563 | { |
| 564 | − int ret; | |
| 564 | + int ret = 0; | |
| 565 | 565 | u32 data; |
| 566 | 566 | |
| 567 | 567 | if (qlcnic_api_lock(adapter)) { |
| @@ -571,7 +571,7 @@ void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf, · 3 unmodified lines | ||
| 571 | 571 | return; |
| 572 | 572 | } |
| 573 | 573 | |
| 574 | − ret = qlcnic_83xx_rd_reg_indirect(adapter, (u32) offset); | |
| 574 | + data = QLCRD32(adapter, (u32) offset, &ret); | |
| 575 | 575 | qlcnic_api_unlock(adapter); |
| 576 | 576 | |
| 577 | 577 | if (ret == -EIO) { |
| @@ -580,7 +580,6 @@ void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf, · 2 unmodified lines | ||
| 580 | 580 | __func__, (u32)offset); |
| 581 | 581 | return; |
| 582 | 582 | } |
| 583 | − data = ret; | |
| 584 | 583 | memcpy(buf, &data, size); |
| 585 | 584 | } |
| 586 | 585 | |
| @@ -2391,9 +2390,9 @@ int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter, · 1804 unmodified lines | ||
| 2391 | 2390 | u32 flash_addr, u8 *p_data, |
| 2392 | 2391 | int count) |
| 2393 | 2392 | { |
| 2394 | − int i, ret; | |
| 2395 | − u32 word, range, flash_offset, addr = flash_addr; | |
| 2393 | + u32 word, range, flash_offset, addr = flash_addr, ret; | |
| 2396 | 2394 | ulong indirect_add, direct_window; |
| 2395 | + int i, err = 0; | |
| 2397 | 2396 | |
| 2398 | 2397 | flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1); |
| 2399 | 2398 | if (addr & 0x3) { |
| @@ -2411,10 +2410,9 @@ int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter, · 11 unmodified lines | ||
| 2411 | 2410 | /* Multi sector read */ |
| 2412 | 2411 | for (i = 0; i < count; i++) { |
| 2413 | 2412 | indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr); |
| 2414 | − ret = qlcnic_83xx_rd_reg_indirect(adapter, | |
| 2415 | − indirect_add); | |
| 2416 | − if (ret == -EIO) | |
| 2417 | − return -EIO; | |
| 2413 | + ret = QLCRD32(adapter, indirect_add, &err); | |
| 2414 | + if (err == -EIO) | |
| 2415 | + return err; | |
| 2418 | 2416 | |
| 2419 | 2417 | word = ret; |
| 2420 | 2418 | *(u32 *)p_data = word; |
| @@ -2435,10 +2433,9 @@ int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter, · 14 unmodified lines | ||
| 2435 | 2433 | /* Single sector read */ |
| 2436 | 2434 | for (i = 0; i < count; i++) { |
| 2437 | 2435 | indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr); |
| 2438 | − ret = qlcnic_83xx_rd_reg_indirect(adapter, | |
| 2439 | − indirect_add); | |
| 2440 | − if (ret == -EIO) | |
| 2441 | − return -EIO; | |
| 2436 | + ret = QLCRD32(adapter, indirect_add, &err); | |
| 2437 | + if (err == -EIO) | |
| 2438 | + return err; | |
| 2442 | 2439 | |
| 2443 | 2440 | word = ret; |
| 2444 | 2441 | *(u32 *)p_data = word; |
| @@ -2454,10 +2451,13 @@ static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter) · 9 unmodified lines | ||
| 2454 | 2451 | { |
| 2455 | 2452 | u32 status; |
| 2456 | 2453 | int retries = QLC_83XX_FLASH_READ_RETRY_COUNT; |
| 2454 | + int err = 0; | |
| 2457 | 2455 | |
| 2458 | 2456 | do { |
| 2459 | − status = qlcnic_83xx_rd_reg_indirect(adapter, | |
| 2460 | − QLC_83XX_FLASH_STATUS); | |
| 2457 | + status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err); | |
| 2458 | + if (err == -EIO) | |
| 2459 | + return err; | |
| 2460 | + | |
| 2461 | 2461 | if ((status & QLC_83XX_FLASH_STATUS_READY) == |
| 2462 | 2462 | QLC_83XX_FLASH_STATUS_READY) |
| 2463 | 2463 | break; |
| @@ -2509,7 +2509,8 @@ int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter) · 45 unmodified lines | ||
| 2509 | 2509 | |
| 2510 | 2510 | int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter) |
| 2511 | 2511 | { |
| 2512 | − int ret, mfg_id; | |
| 2512 | + int ret, err = 0; | |
| 2513 | + u32 mfg_id; | |
| 2513 | 2514 | |
| 2514 | 2515 | if (qlcnic_83xx_lock_flash(adapter)) |
| 2515 | 2516 | return -EIO; |
| @@ -2524,9 +2525,11 @@ int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter) · 8 unmodified lines | ||
| 2524 | 2525 | return -EIO; |
| 2525 | 2526 | } |
| 2526 | 2527 | |
| 2527 | − mfg_id = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_RDDATA); | |
| 2528 | − if (mfg_id == -EIO) | |
| 2529 | − return -EIO; | |
| 2528 | + mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err); | |
| 2529 | + if (err == -EIO) { | |
| 2530 | + qlcnic_83xx_unlock_flash(adapter); | |
| 2531 | + return err; | |
| 2532 | + } | |
| 2530 | 2533 | |
| 2531 | 2534 | adapter->flash_mfg_id = (mfg_id & 0xFF); |
| 2532 | 2535 | qlcnic_83xx_unlock_flash(adapter); |
| @@ -2643,7 +2646,7 @@ int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr, · 110 unmodified lines | ||
| 2643 | 2646 | u32 *p_data, int count) |
| 2644 | 2647 | { |
| 2645 | 2648 | u32 temp; |
| 2646 | − int ret = -EIO; | |
| 2649 | + int ret = -EIO, err = 0; | |
| 2647 | 2650 | |
| 2648 | 2651 | if ((count < QLC_83XX_FLASH_WRITE_MIN) || |
| 2649 | 2652 | (count > QLC_83XX_FLASH_WRITE_MAX)) { |
| @@ -2652,8 +2655,10 @@ int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr, · 2 unmodified lines | ||
| 2652 | 2655 | return -EIO; |
| 2653 | 2656 | } |
| 2654 | 2657 | |
| 2655 | − temp = qlcnic_83xx_rd_reg_indirect(adapter, | |
| 2656 | − QLC_83XX_FLASH_SPI_CONTROL); | |
| 2658 | + temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err); | |
| 2659 | + if (err == -EIO) | |
| 2660 | + return err; | |
| 2661 | + | |
| 2657 | 2662 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL, |
| 2658 | 2663 | (temp | QLC_83XX_FLASH_SPI_CTRL)); |
| 2659 | 2664 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, |
| @@ -2702,13 +2707,18 @@ int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr, · 42 unmodified lines | ||
| 2702 | 2707 | return -EIO; |
| 2703 | 2708 | } |
| 2704 | 2709 | |
| 2705 | − ret = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_SPI_STATUS); | |
| 2710 | + ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err); | |
| 2711 | + if (err == -EIO) | |
| 2712 | + return err; | |
| 2713 | + | |
| 2706 | 2714 | if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) { |
| 2707 | 2715 | dev_err(&adapter->pdev->dev, "%s: failed at %d\n", |
| 2708 | 2716 | __func__, __LINE__); |
| 2709 | 2717 | /* Operation failed, clear error bit */ |
| 2710 | − temp = qlcnic_83xx_rd_reg_indirect(adapter, | |
| 2711 | − QLC_83XX_FLASH_SPI_CONTROL); | |
| 2718 | + temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err); | |
| 2719 | + if (err == -EIO) | |
| 2720 | + return err; | |
| 2721 | + | |
| 2712 | 2722 | qlcnic_83xx_wrt_reg_indirect(adapter, |
| 2713 | 2723 | QLC_83XX_FLASH_SPI_CONTROL, |
| 2714 | 2724 | (temp | QLC_83XX_FLASH_SPI_CTRL)); |
| @@ -2830,6 +2840,7 @@ int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr, · 115 unmodified lines | ||
| 2830 | 2840 | { |
| 2831 | 2841 | int i, j, ret = 0; |
| 2832 | 2842 | u32 temp; |
| 2843 | + int err = 0; | |
| 2833 | 2844 | |
| 2834 | 2845 | /* Check alignment */ |
| 2835 | 2846 | if (addr & 0xF) |
| @@ -2862,8 +2873,12 @@ int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr, · 26 unmodified lines | ||
| 2862 | 2873 | QLCNIC_TA_WRITE_START); |
| 2863 | 2874 | |
| 2864 | 2875 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
| 2865 | − temp = qlcnic_83xx_rd_reg_indirect(adapter, | |
| 2866 | − QLCNIC_MS_CTRL); | |
| 2876 | + temp = QLCRD32(adapter, QLCNIC_MS_CTRL, &err); | |
| 2877 | + if (err == -EIO) { | |
| 2878 | + mutex_unlock(&adapter->ahw->mem_lock); | |
| 2879 | + return err; | |
| 2880 | + } | |
| 2881 | + | |
| 2867 | 2882 | if ((temp & TA_CTL_BUSY) == 0) |
| 2868 | 2883 | break; |
| 2869 | 2884 | } |
| @@ -2885,9 +2900,9 @@ int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr, · 15 unmodified lines | ||
| 2885 | 2900 | int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr, |
| 2886 | 2901 | u8 *p_data, int count) |
| 2887 | 2902 | { |
| 2888 | − int i, ret; | |
| 2889 | − u32 word, addr = flash_addr; | |
| 2903 | + u32 word, addr = flash_addr, ret; | |
| 2890 | 2904 | ulong indirect_addr; |
| 2905 | + int i, err = 0; | |
| 2891 | 2906 | |
| 2892 | 2907 | if (qlcnic_83xx_lock_flash(adapter) != 0) |
| 2893 | 2908 | return -EIO; |
| @@ -2907,10 +2922,10 @@ int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr, · 13 unmodified lines | ||
| 2907 | 2922 | } |
| 2908 | 2923 | |
| 2909 | 2924 | indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr); |
| 2910 | − ret = qlcnic_83xx_rd_reg_indirect(adapter, | |
| 2911 | − indirect_addr); | |
| 2912 | − if (ret == -EIO) | |
| 2913 | − return -EIO; | |
| 2925 | + ret = QLCRD32(adapter, indirect_addr, &err); | |
| 2926 | + if (err == -EIO) | |
| 2927 | + return err; | |
| 2928 | + | |
| 2914 | 2929 | word = ret; |
| 2915 | 2930 | *(u32 *)p_data = word; |
| 2916 | 2931 | p_data = p_data + 4; |
| @@ -3376,7 +3391,8 @@ int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter, · 459 unmodified lines | ||
| 3376 | 3391 | |
| 3377 | 3392 | static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter) |
| 3378 | 3393 | { |
| 3379 | − int ret; | |
| 3394 | + int ret, err = 0; | |
| 3395 | + u32 temp; | |
| 3380 | 3396 | |
| 3381 | 3397 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, |
| 3382 | 3398 | QLC_83XX_FLASH_OEM_READ_SIG); |
| @@ -3386,8 +3402,11 @@ static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter) · 3 unmodified lines | ||
| 3386 | 3402 | if (ret) |
| 3387 | 3403 | return -EIO; |
| 3388 | 3404 | |
| 3389 | − ret = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_RDDATA); | |
| 3390 | − return ret & 0xFF; | |
| 3405 | + temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err); | |
| 3406 | + if (err == -EIO) | |
| 3407 | + return err; | |
| 3408 | + | |
| 3409 | + return temp & 0xFF; | |
| 3391 | 3410 | } |
| 3392 | 3411 | |
| 3393 | 3412 | int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter) |
| @@ -508,7 +508,7 @@ void qlcnic_83xx_add_sysfs(struct qlcnic_adapter *); · 507 unmodified lines | ||
| 508 | 508 | void qlcnic_83xx_remove_sysfs(struct qlcnic_adapter *); |
| 509 | 509 | void qlcnic_83xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t); |
| 510 | 510 | void qlcnic_83xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t); |
| 511 | −int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *, ulong); | |
| 511 | +int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *, ulong, int *); | |
| 512 | 512 | int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *, ulong, u32); |
| 513 | 513 | void qlcnic_83xx_process_rcv_diag(struct qlcnic_adapter *, int, u64 []); |
| 514 | 514 | int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *, u32); |
| @@ -1303,8 +1303,11 @@ static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter) · 1302 unmodified lines | ||
| 1303 | 1303 | { |
| 1304 | 1304 | int i, j; |
| 1305 | 1305 | u32 val = 0, val1 = 0, reg = 0; |
| 1306 | + int err = 0; | |
| 1306 | 1307 | |
| 1307 | − val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG); | |
| 1308 | + val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG, &err); | |
| 1309 | + if (err == -EIO) | |
| 1310 | + return; | |
| 1308 | 1311 | dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val); |
| 1309 | 1312 | |
| 1310 | 1313 | for (j = 0; j < 2; j++) { |
| @@ -1318,7 +1321,9 @@ static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter) · 7 unmodified lines | ||
| 1318 | 1321 | reg = QLC_83XX_PORT1_THRESHOLD; |
| 1319 | 1322 | } |
| 1320 | 1323 | for (i = 0; i < 8; i++) { |
| 1321 | − val = QLCRD32(adapter, reg + (i * 0x4)); | |
| 1324 | + val = QLCRD32(adapter, reg + (i * 0x4), &err); | |
| 1325 | + if (err == -EIO) | |
| 1326 | + return; | |
| 1322 | 1327 | dev_info(&adapter->pdev->dev, "0x%x ", val); |
| 1323 | 1328 | } |
| 1324 | 1329 | dev_info(&adapter->pdev->dev, "\n"); |
| @@ -1335,8 +1340,10 @@ static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter) · 10 unmodified lines | ||
| 1335 | 1340 | reg = QLC_83XX_PORT1_TC_MC_REG; |
| 1336 | 1341 | } |
| 1337 | 1342 | for (i = 0; i < 4; i++) { |
| 1338 | − val = QLCRD32(adapter, reg + (i * 0x4)); | |
| 1339 | − dev_info(&adapter->pdev->dev, "0x%x ", val); | |
| 1343 | + val = QLCRD32(adapter, reg + (i * 0x4), &err); | |
| 1344 | + if (err == -EIO) | |
| 1345 | + return; | |
| 1346 | + dev_info(&adapter->pdev->dev, "0x%x ", val); | |
| 1340 | 1347 | } |
| 1341 | 1348 | dev_info(&adapter->pdev->dev, "\n"); |
| 1342 | 1349 | } |
| @@ -1352,17 +1359,25 @@ static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter) · 9 unmodified lines | ||
| 1352 | 1359 | reg = QLC_83XX_PORT1_TC_STATS; |
| 1353 | 1360 | } |
| 1354 | 1361 | for (i = 7; i >= 0; i--) { |
| 1355 | − val = QLCRD32(adapter, reg); | |
| 1362 | + val = QLCRD32(adapter, reg, &err); | |
| 1363 | + if (err == -EIO) | |
| 1364 | + return; | |
| 1356 | 1365 | val &= ~(0x7 << 29); /* Reset bits 29 to 31 */ |
| 1357 | 1366 | QLCWR32(adapter, reg, (val | (i << 29))); |
| 1358 | − val = QLCRD32(adapter, reg); | |
| 1367 | + val = QLCRD32(adapter, reg, &err); | |
| 1368 | + if (err == -EIO) | |
| 1369 | + return; | |
| 1359 | 1370 | dev_info(&adapter->pdev->dev, "0x%x ", val); |
| 1360 | 1371 | } |
| 1361 | 1372 | dev_info(&adapter->pdev->dev, "\n"); |
| 1362 | 1373 | } |
| 1363 | 1374 | |
| 1364 | − val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD); | |
| 1365 | − val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD); | |
| 1375 | + val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, &err); | |
| 1376 | + if (err == -EIO) | |
| 1377 | + return; | |
| 1378 | + val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, &err); | |
| 1379 | + if (err == -EIO) | |
| 1380 | + return; | |
| 1366 | 1381 | dev_info(&adapter->pdev->dev, |
| 1367 | 1382 | "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n", |
| 1368 | 1383 | val, val1); |
| @@ -1425,7 +1440,7 @@ static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter) · 56 unmodified lines | ||
| 1425 | 1440 | static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev) |
| 1426 | 1441 | { |
| 1427 | 1442 | u32 heartbeat, peg_status; |
| 1428 | − int retries, ret = -EIO; | |
| 1443 | + int retries, ret = -EIO, err = 0; | |
| 1429 | 1444 | |
| 1430 | 1445 | retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT; |
| 1431 | 1446 | p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev, |
| @@ -1453,11 +1468,11 @@ static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev) · 21 unmodified lines | ||
| 1453 | 1468 | "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n" |
| 1454 | 1469 | "PEG_NET_4_PC: 0x%x\n", peg_status, |
| 1455 | 1470 | QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2), |
| 1456 | − QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0), | |
| 1457 | − QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1), | |
| 1458 | − QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2), | |
| 1459 | − QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3), | |
| 1460 | − QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4)); | |
| 1471 | + QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0, &err), | |
| 1472 | + QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1, &err), | |
| 1473 | + QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2, &err), | |
| 1474 | + QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3, &err), | |
| 1475 | + QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4, &err)); | |
| 1461 | 1476 | |
| 1462 | 1477 | if (QLCNIC_FWERROR_CODE(peg_status) == 0x67) |
| 1463 | 1478 | dev_err(&p_dev->pdev->dev, |
| @@ -1501,18 +1516,22 @@ int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev) · 37 unmodified lines | ||
| 1501 | 1516 | static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr, |
| 1502 | 1517 | int duration, u32 mask, u32 status) |
| 1503 | 1518 | { |
| 1519 | + int timeout_error, err = 0; | |
| 1504 | 1520 | u32 value; |
| 1505 | − int timeout_error; | |
| 1506 | 1521 | u8 retries; |
| 1507 | 1522 | |
| 1508 | − value = qlcnic_83xx_rd_reg_indirect(p_dev, addr); | |
| 1523 | + value = QLCRD32(p_dev, addr, &err); | |
| 1524 | + if (err == -EIO) | |
| 1525 | + return err; | |
| 1509 | 1526 | retries = duration / 10; |
| 1510 | 1527 | |
| 1511 | 1528 | do { |
| 1512 | 1529 | if ((value & mask) != status) { |
| 1513 | 1530 | timeout_error = 1; |
| 1514 | 1531 | msleep(duration / 10); |
| 1515 | − value = qlcnic_83xx_rd_reg_indirect(p_dev, addr); | |
| 1532 | + value = QLCRD32(p_dev, addr, &err); | |
| 1533 | + if (err == -EIO) | |
| 1534 | + return err; | |
| 1516 | 1535 | } else { |
| 1517 | 1536 | timeout_error = 0; |
| 1518 | 1537 | break; |
| @@ -1606,9 +1625,12 @@ int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev) · 87 unmodified lines | ||
| 1606 | 1625 | static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev, |
| 1607 | 1626 | u32 raddr, u32 waddr) |
| 1608 | 1627 | { |
| 1609 | − int value; | |
| 1628 | + int err = 0; | |
| 1629 | + u32 value; | |
| 1610 | 1630 | |
| 1611 | − value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr); | |
| 1631 | + value = QLCRD32(p_dev, raddr, &err); | |
| 1632 | + if (err == -EIO) | |
| 1633 | + return; | |
| 1612 | 1634 | qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value); |
| 1613 | 1635 | } |
| 1614 | 1636 | |
| @@ -1617,12 +1639,16 @@ static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev, · 2 unmodified lines | ||
| 1617 | 1639 | u32 raddr, u32 waddr, |
| 1618 | 1640 | struct qlc_83xx_rmw *p_rmw_hdr) |
| 1619 | 1641 | { |
| 1620 | − int value; | |
| 1642 | + int err = 0; | |
| 1643 | + u32 value; | |
| 1621 | 1644 | |
| 1622 | − if (p_rmw_hdr->index_a) | |
| 1645 | + if (p_rmw_hdr->index_a) { | |
| 1623 | 1646 | value = p_dev->ahw->reset.array[p_rmw_hdr->index_a]; |
| 1624 | − else | |
| 1625 | − value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr); | |
| 1647 | + } else { | |
| 1648 | + value = QLCRD32(p_dev, raddr, &err); | |
| 1649 | + if (err == -EIO) | |
| 1650 | + return; | |
| 1651 | + } | |
| 1626 | 1652 | |
| 1627 | 1653 | value &= p_rmw_hdr->mask; |
| 1628 | 1654 | value <<= p_rmw_hdr->shl; |
| @@ -1675,7 +1701,7 @@ static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev, · 46 unmodified lines | ||
| 1675 | 1701 | long delay; |
| 1676 | 1702 | struct qlc_83xx_entry *entry; |
| 1677 | 1703 | struct qlc_83xx_poll *poll; |
| 1678 | − int i; | |
| 1704 | + int i, err = 0; | |
| 1679 | 1705 | unsigned long arg1, arg2; |
| 1680 | 1706 | |
| 1681 | 1707 | poll = (struct qlc_83xx_poll *)((char *)p_hdr + |
| @@ -1699,10 +1725,12 @@ static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev, · 17 unmodified lines | ||
| 1699 | 1725 | arg1, delay, |
| 1700 | 1726 | poll->mask, |
| 1701 | 1727 | poll->status)){ |
| 1702 | − qlcnic_83xx_rd_reg_indirect(p_dev, | |
| 1703 | − arg1); | |
| 1704 | − qlcnic_83xx_rd_reg_indirect(p_dev, | |
| 1705 | − arg2); | |
| 1728 | + QLCRD32(p_dev, arg1, &err); | |
| 1729 | + if (err == -EIO) | |
| 1730 | + return; | |
| 1731 | + QLCRD32(p_dev, arg2, &err); | |
| 1732 | + if (err == -EIO) | |
| 1733 | + return; | |
| 1706 | 1734 | } |
| 1707 | 1735 | } |
| 1708 | 1736 | } |
| @@ -1768,7 +1796,7 @@ static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev, · 59 unmodified lines | ||
| 1768 | 1796 | struct qlc_83xx_entry_hdr *p_hdr) |
| 1769 | 1797 | { |
| 1770 | 1798 | long delay; |
| 1771 | − int index, i, j; | |
| 1799 | + int index, i, j, err; | |
| 1772 | 1800 | struct qlc_83xx_quad_entry *entry; |
| 1773 | 1801 | struct qlc_83xx_poll *poll; |
| 1774 | 1802 | unsigned long addr; |
| @@ -1788,7 +1816,10 @@ static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev, · 13 unmodified lines | ||
| 1788 | 1816 | poll->mask, poll->status)){ |
| 1789 | 1817 | index = p_dev->ahw->reset.array_index; |
| 1790 | 1818 | addr = entry->dr_addr; |
| 1791 | − j = qlcnic_83xx_rd_reg_indirect(p_dev, addr); | |
| 1819 | + j = QLCRD32(p_dev, addr, &err); | |
| 1820 | + if (err == -EIO) | |
| 1821 | + return; | |
| 1822 | + | |
| 1792 | 1823 | p_dev->ahw->reset.array[index++] = j; |
| 1793 | 1824 | |
| 1794 | 1825 | if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES) |
| @@ -104,7 +104,7 @@ static u32 · 103 unmodified lines | ||
| 104 | 104 | qlcnic_poll_rsp(struct qlcnic_adapter *adapter) |
| 105 | 105 | { |
| 106 | 106 | u32 rsp; |
| 107 | − int timeout = 0; | |
| 107 | + int timeout = 0, err = 0; | |
| 108 | 108 | |
| 109 | 109 | do { |
| 110 | 110 | /* give atleast 1ms for firmware to respond */ |
| @@ -113,7 +113,7 @@ qlcnic_poll_rsp(struct qlcnic_adapter *adapter) · 2 unmodified lines | ||
| 113 | 113 | if (++timeout > QLCNIC_OS_CRB_RETRY_COUNT) |
| 114 | 114 | return QLCNIC_CDRP_RSP_TIMEOUT; |
| 115 | 115 | |
| 116 | − rsp = QLCRD32(adapter, QLCNIC_CDRP_CRB_OFFSET); | |
| 116 | + rsp = QLCRD32(adapter, QLCNIC_CDRP_CRB_OFFSET, &err); | |
| 117 | 117 | } while (!QLCNIC_CDRP_IS_RSP(rsp)); |
| 118 | 118 | |
| 119 | 119 | return rsp; |
| @@ -122,7 +122,7 @@ qlcnic_poll_rsp(struct qlcnic_adapter *adapter) · 2 unmodified lines | ||
| 122 | 122 | int qlcnic_82xx_issue_cmd(struct qlcnic_adapter *adapter, |
| 123 | 123 | struct qlcnic_cmd_args *cmd) |
| 124 | 124 | { |
| 125 | − int i; | |
| 125 | + int i, err = 0; | |
| 126 | 126 | u32 rsp; |
| 127 | 127 | u32 signature; |
| 128 | 128 | struct pci_dev *pdev = adapter->pdev; |
| @@ -148,7 +148,7 @@ int qlcnic_82xx_issue_cmd(struct qlcnic_adapter *adapter, · 19 unmodified lines | ||
| 148 | 148 | dev_err(&pdev->dev, "card response timeout.\n"); |
| 149 | 149 | cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT; |
| 150 | 150 | } else if (rsp == QLCNIC_CDRP_RSP_FAIL) { |
| 151 | − cmd->rsp.arg[0] = QLCRD32(adapter, QLCNIC_CDRP_ARG(1)); | |
| 151 | + cmd->rsp.arg[0] = QLCRD32(adapter, QLCNIC_CDRP_ARG(1), &err); | |
| 152 | 152 | switch (cmd->rsp.arg[0]) { |
| 153 | 153 | case QLCNIC_RCODE_INVALID_ARGS: |
| 154 | 154 | fmt = "CDRP invalid args: [%d]\n"; |
| @@ -175,7 +175,7 @@ int qlcnic_82xx_issue_cmd(struct qlcnic_adapter *adapter, · 20 unmodified lines | ||
| 175 | 175 | cmd->rsp.arg[0] = QLCNIC_RCODE_SUCCESS; |
| 176 | 176 | |
| 177 | 177 | for (i = 1; i < cmd->rsp.num; i++) |
| 178 | − cmd->rsp.arg[i] = QLCRD32(adapter, QLCNIC_CDRP_ARG(i)); | |
| 178 | + cmd->rsp.arg[i] = QLCRD32(adapter, QLCNIC_CDRP_ARG(i), &err); | |
| 179 | 179 | |
| 180 | 180 | /* Release semaphore */ |
| 181 | 181 | qlcnic_api_unlock(adapter); |
| @@ -267,7 +267,7 @@ int qlcnic_82xx_get_settings(struct qlcnic_adapter *adapter, · 266 unmodified lines | ||
| 267 | 267 | { |
| 268 | 268 | struct qlcnic_hardware_context *ahw = adapter->ahw; |
| 269 | 269 | u32 speed, reg; |
| 270 | − int check_sfp_module = 0; | |
| 270 | + int check_sfp_module = 0, err = 0; | |
| 271 | 271 | u16 pcifn = ahw->pci_func; |
| 272 | 272 | |
| 273 | 273 | /* read which mode */ |
| @@ -290,7 +290,7 @@ int qlcnic_82xx_get_settings(struct qlcnic_adapter *adapter, · 16 unmodified lines | ||
| 290 | 290 | |
| 291 | 291 | } else if (adapter->ahw->port_type == QLCNIC_XGBE) { |
| 292 | 292 | u32 val = 0; |
| 293 | − val = QLCRD32(adapter, QLCNIC_PORT_MODE_ADDR); | |
| 293 | + val = QLCRD32(adapter, QLCNIC_PORT_MODE_ADDR, &err); | |
| 294 | 294 | |
| 295 | 295 | if (val == QLCNIC_PORT_MODE_802_3_AP) { |
| 296 | 296 | ecmd->supported = SUPPORTED_1000baseT_Full; |
| @@ -303,7 +303,7 @@ int qlcnic_82xx_get_settings(struct qlcnic_adapter *adapter, · 6 unmodified lines | ||
| 303 | 303 | if (netif_running(adapter->netdev) && ahw->has_link_events) { |
| 304 | 304 | if (ahw->linkup) { |
| 305 | 305 | reg = QLCRD32(adapter, |
| 306 | − P3P_LINK_SPEED_REG(pcifn)); | |
| 306 | + P3P_LINK_SPEED_REG(pcifn), &err); | |
| 307 | 307 | speed = P3P_LINK_SPEED_VAL(pcifn, reg); |
| 308 | 308 | ahw->link_speed = speed * P3P_LINK_SPEED_MHZ; |
| 309 | 309 | } |
| @@ -468,13 +468,14 @@ static int qlcnic_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) · 158 unmodified lines | ||
| 468 | 468 | static int qlcnic_82xx_get_registers(struct qlcnic_adapter *adapter, |
| 469 | 469 | u32 *regs_buff) |
| 470 | 470 | { |
| 471 | − int i, j = 0; | |
| 471 | + int i, j = 0, err = 0; | |
| 472 | 472 | |
| 473 | 473 | for (i = QLCNIC_DEV_INFO_SIZE + 1; diag_registers[j] != -1; j++, i++) |
| 474 | 474 | regs_buff[i] = QLC_SHARED_REG_RD32(adapter, diag_registers[j]); |
| 475 | 475 | j = 0; |
| 476 | 476 | while (ext_diag_registers[j] != -1) |
| 477 | − regs_buff[i++] = QLCRD32(adapter, ext_diag_registers[j++]); | |
| 477 | + regs_buff[i++] = QLCRD32(adapter, ext_diag_registers[j++], | |
| 478 | + &err); | |
| 478 | 479 | return i; |
| 479 | 480 | } |
| 480 | 481 | |
| @@ -524,13 +525,16 @@ qlcnic_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p) · 43 unmodified lines | ||
| 524 | 525 | static u32 qlcnic_test_link(struct net_device *dev) |
| 525 | 526 | { |
| 526 | 527 | struct qlcnic_adapter *adapter = netdev_priv(dev); |
| 528 | + int err = 0; | |
| 527 | 529 | u32 val; |
| 528 | 530 | |
| 529 | 531 | if (qlcnic_83xx_check(adapter)) { |
| 530 | 532 | val = qlcnic_83xx_test_link(adapter); |
| 531 | 533 | return (val & 1) ? 0 : 1; |
| 532 | 534 | } |
| 533 | − val = QLCRD32(adapter, CRB_XG_STATE_P3P); | |
| 535 | + val = QLCRD32(adapter, CRB_XG_STATE_P3P, &err); | |
| 536 | + if (err == -EIO) | |
| 537 | + return err; | |
| 534 | 538 | val = XG_LINK_STATE_P3P(adapter->ahw->pci_func, val); |
| 535 | 539 | return (val == XG_LINK_UP_P3P) ? 0 : 1; |
| 536 | 540 | } |
| @@ -663,6 +667,7 @@ qlcnic_get_pauseparam(struct net_device *netdev, · 126 unmodified lines | ||
| 663 | 667 | { |
| 664 | 668 | struct qlcnic_adapter *adapter = netdev_priv(netdev); |
| 665 | 669 | int port = adapter->ahw->physical_port; |
| 670 | + int err = 0; | |
| 666 | 671 | __u32 val; |
| 667 | 672 | |
| 668 | 673 | if (qlcnic_83xx_check(adapter)) { |
| @@ -673,9 +678,13 @@ qlcnic_get_pauseparam(struct net_device *netdev, · 4 unmodified lines | ||
| 673 | 678 | if ((port < 0) || (port > QLCNIC_NIU_MAX_GBE_PORTS)) |
| 674 | 679 | return; |
| 675 | 680 | /* get flow control settings */ |
| 676 | − val = QLCRD32(adapter, QLCNIC_NIU_GB_MAC_CONFIG_0(port)); | |
| 681 | + val = QLCRD32(adapter, QLCNIC_NIU_GB_MAC_CONFIG_0(port), &err); | |
| 682 | + if (err == -EIO) | |
| 683 | + return; | |
| 677 | 684 | pause->rx_pause = qlcnic_gb_get_rx_flowctl(val); |
| 678 | − val = QLCRD32(adapter, QLCNIC_NIU_GB_PAUSE_CTL); | |
| 685 | + val = QLCRD32(adapter, QLCNIC_NIU_GB_PAUSE_CTL, &err); | |
| 686 | + if (err == -EIO) | |
| 687 | + return; | |
| 679 | 688 | switch (port) { |
| 680 | 689 | case 0: |
| 681 | 690 | pause->tx_pause = !(qlcnic_gb_get_gb0_mask(val)); |
| @@ -695,7 +704,9 @@ qlcnic_get_pauseparam(struct net_device *netdev, · 13 unmodified lines | ||
| 695 | 704 | if ((port < 0) || (port > QLCNIC_NIU_MAX_XG_PORTS)) |
| 696 | 705 | return; |
| 697 | 706 | pause->rx_pause = 1; |
| 698 | − val = QLCRD32(adapter, QLCNIC_NIU_XG_PAUSE_CTL); | |
| 707 | + val = QLCRD32(adapter, QLCNIC_NIU_XG_PAUSE_CTL, &err); | |
| 708 | + if (err == -EIO) | |
| 709 | + return; | |
| 699 | 710 | if (port == 0) |
| 700 | 711 | pause->tx_pause = !(qlcnic_xg_get_xg0_mask(val)); |
| 701 | 712 | else |
| @@ -712,6 +723,7 @@ qlcnic_set_pauseparam(struct net_device *netdev, · 10 unmodified lines | ||
| 712 | 723 | { |
| 713 | 724 | struct qlcnic_adapter *adapter = netdev_priv(netdev); |
| 714 | 725 | int port = adapter->ahw->physical_port; |
| 726 | + int err = 0; | |
| 715 | 727 | __u32 val; |
| 716 | 728 | |
| 717 | 729 | if (qlcnic_83xx_check(adapter)) |
| @@ -722,7 +734,9 @@ qlcnic_set_pauseparam(struct net_device *netdev, · 4 unmodified lines | ||
| 722 | 734 | if ((port < 0) || (port > QLCNIC_NIU_MAX_GBE_PORTS)) |
| 723 | 735 | return -EIO; |
| 724 | 736 | /* set flow control */ |
| 725 | − val = QLCRD32(adapter, QLCNIC_NIU_GB_MAC_CONFIG_0(port)); | |
| 737 | + val = QLCRD32(adapter, QLCNIC_NIU_GB_MAC_CONFIG_0(port), &err); | |
| 738 | + if (err == -EIO) | |
| 739 | + return err; | |
| 726 | 740 | |
| 727 | 741 | if (pause->rx_pause) |
| 728 | 742 | qlcnic_gb_rx_flowctl(val); |
| @@ -733,7 +747,9 @@ qlcnic_set_pauseparam(struct net_device *netdev, · 4 unmodified lines | ||
| 733 | 747 | val); |
| 734 | 748 | QLCWR32(adapter, QLCNIC_NIU_GB_MAC_CONFIG_0(port), val); |
| 735 | 749 | /* set autoneg */ |
| 736 | − val = QLCRD32(adapter, QLCNIC_NIU_GB_PAUSE_CTL); | |
| 750 | + val = QLCRD32(adapter, QLCNIC_NIU_GB_PAUSE_CTL, &err); | |
| 751 | + if (err == -EIO) | |
| 752 | + return err; | |
| 737 | 753 | switch (port) { |
| 738 | 754 | case 0: |
| 739 | 755 | if (pause->tx_pause) |
| @@ -769,7 +785,9 @@ qlcnic_set_pauseparam(struct net_device *netdev, · 29 unmodified lines | ||
| 769 | 785 | if ((port < 0) || (port > QLCNIC_NIU_MAX_XG_PORTS)) |
| 770 | 786 | return -EIO; |
| 771 | 787 | |
| 772 | − val = QLCRD32(adapter, QLCNIC_NIU_XG_PAUSE_CTL); | |
| 788 | + val = QLCRD32(adapter, QLCNIC_NIU_XG_PAUSE_CTL, &err); | |
| 789 | + if (err == -EIO) | |
| 790 | + return err; | |
| 773 | 791 | if (port == 0) { |
| 774 | 792 | if (pause->tx_pause) |
| 775 | 793 | qlcnic_xg_unset_xg0_mask(val); |
| @@ -793,11 +811,14 @@ static int qlcnic_reg_test(struct net_device *dev) · 17 unmodified lines | ||
| 793 | 811 | { |
| 794 | 812 | struct qlcnic_adapter *adapter = netdev_priv(dev); |
| 795 | 813 | u32 data_read; |
| 814 | + int err = 0; | |
| 796 | 815 | |
| 797 | 816 | if (qlcnic_83xx_check(adapter)) |
| 798 | 817 | return qlcnic_83xx_reg_test(adapter); |
| 799 | 818 | |
| 800 | − data_read = QLCRD32(adapter, QLCNIC_PCIX_PH_REG(0)); | |
| 819 | + data_read = QLCRD32(adapter, QLCNIC_PCIX_PH_REG(0), &err); | |
| 820 | + if (err == -EIO) | |
| 821 | + return err; | |
| 801 | 822 | if ((data_read & 0xffff) != adapter->pdev->vendor) |
| 802 | 823 | return 1; |
| 803 | 824 | |
| @@ -1269,17 +1290,20 @@ qlcnic_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) · 465 unmodified lines | ||
| 1269 | 1290 | { |
| 1270 | 1291 | struct qlcnic_adapter *adapter = netdev_priv(dev); |
| 1271 | 1292 | u32 wol_cfg; |
| 1293 | + int err = 0; | |
| 1272 | 1294 | |
| 1273 | 1295 | if (qlcnic_83xx_check(adapter)) |
| 1274 | 1296 | return; |
| 1275 | 1297 | wol->supported = 0; |
| 1276 | 1298 | wol->wolopts = 0; |
| 1277 | 1299 | |
| 1278 | − wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV); | |
| 1300 | + wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV, &err); | |
| 1301 | + if (err == -EIO) | |
| 1302 | + return; | |
| 1279 | 1303 | if (wol_cfg & (1UL << adapter->portnum)) |
| 1280 | 1304 | wol->supported |= WAKE_MAGIC; |
| 1281 | 1305 | |
| 1282 | − wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG); | |
| 1306 | + wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG, &err); | |
| 1283 | 1307 | if (wol_cfg & (1UL << adapter->portnum)) |
| 1284 | 1308 | wol->wolopts |= WAKE_MAGIC; |
| 1285 | 1309 | } |
| @@ -1289,17 +1313,22 @@ qlcnic_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) · 3 unmodified lines | ||
| 1289 | 1313 | { |
| 1290 | 1314 | struct qlcnic_adapter *adapter = netdev_priv(dev); |
| 1291 | 1315 | u32 wol_cfg; |
| 1316 | + int err = 0; | |
| 1292 | 1317 | |
| 1293 | 1318 | if (qlcnic_83xx_check(adapter)) |
| 1294 | 1319 | return -EOPNOTSUPP; |
| 1295 | 1320 | if (wol->wolopts & ~WAKE_MAGIC) |
| 1296 | 1321 | return -EINVAL; |
| 1297 | 1322 | |
| 1298 | − wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV); | |
| 1323 | + wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV, &err); | |
| 1324 | + if (err == -EIO) | |
| 1325 | + return err; | |
| 1299 | 1326 | if (!(wol_cfg & (1 << adapter->portnum))) |
| 1300 | 1327 | return -EOPNOTSUPP; |
| 1301 | 1328 | |
| 1302 | − wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG); | |
| 1329 | + wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG, &err); | |
| 1330 | + if (err == -EIO) | |
| 1331 | + return err; | |
| 1303 | 1332 | if (wol->wolopts & WAKE_MAGIC) |
| 1304 | 1333 | wol_cfg |= 1UL << adapter->portnum; |
| 1305 | 1334 | else |
| @@ -317,16 +317,20 @@ static void qlcnic_write_window_reg(u32 addr, void __iomem *bar0, u32 data) · 316 unmodified lines | ||
| 317 | 317 | int |
| 318 | 318 | qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg) |
| 319 | 319 | { |
| 320 | − int done = 0, timeout = 0; | |
| 320 | + int timeout = 0; | |
| 321 | + int err = 0; | |
| 322 | + u32 done = 0; | |
| 321 | 323 | |
| 322 | 324 | while (!done) { |
| 323 | − done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem))); | |
| 325 | + done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)), | |
| 326 | + &err); | |
| 324 | 327 | if (done == 1) |
| 325 | 328 | break; |
| 326 | 329 | if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) { |
| 327 | 330 | dev_err(&adapter->pdev->dev, |
| 328 | 331 | "Failed to acquire sem=%d lock; holdby=%d\n", |
| 329 | − sem, id_reg ? QLCRD32(adapter, id_reg) : -1); | |
| 332 | + sem, | |
| 333 | + id_reg ? QLCRD32(adapter, id_reg, &err) : -1); | |
| 330 | 334 | return -EIO; |
| 331 | 335 | } |
| 332 | 336 | msleep(1); |
| @@ -341,19 +345,22 @@ qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg) · 8 unmodified lines | ||
| 341 | 345 | void |
| 342 | 346 | qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem) |
| 343 | 347 | { |
| 344 | − QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem))); | |
| 348 | + int err = 0; | |
| 349 | + | |
| 350 | + QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)), &err); | |
| 345 | 351 | } |
| 346 | 352 | |
| 347 | 353 | int qlcnic_ind_rd(struct qlcnic_adapter *adapter, u32 addr) |
| 348 | 354 | { |
| 355 | + int err = 0; | |
| 349 | 356 | u32 data; |
| 350 | 357 | |
| 351 | 358 | if (qlcnic_82xx_check(adapter)) |
| 352 | 359 | qlcnic_read_window_reg(addr, adapter->ahw->pci_base0, &data); |
| 353 | 360 | else { |
| 354 | − data = qlcnic_83xx_rd_reg_indirect(adapter, addr); | |
| 355 | − if (data == -EIO) | |
| 356 | − return -EIO; | |
| 361 | + data = QLCRD32(adapter, addr, &err); | |
| 362 | + if (err == -EIO) | |
| 363 | + return err; | |
| 357 | 364 | } |
| 358 | 365 | return data; |
| 359 | 366 | } |
| @@ -1159,7 +1166,8 @@ int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, · 799 unmodified lines | ||
| 1159 | 1166 | return -EIO; |
| 1160 | 1167 | } |
| 1161 | 1168 | |
| 1162 | −int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off) | |
| 1169 | +int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off, | |
| 1170 | + int *err) | |
| 1163 | 1171 | { |
| 1164 | 1172 | unsigned long flags; |
| 1165 | 1173 | int rv; |
| @@ -1415,7 +1423,7 @@ int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data) · 249 unmodified lines | ||
| 1415 | 1423 | |
| 1416 | 1424 | int qlcnic_82xx_get_board_info(struct qlcnic_adapter *adapter) |
| 1417 | 1425 | { |
| 1418 | − int offset, board_type, magic; | |
| 1426 | + int offset, board_type, magic, err = 0; | |
| 1419 | 1427 | struct pci_dev *pdev = adapter->pdev; |
| 1420 | 1428 | |
| 1421 | 1429 | offset = QLCNIC_FW_MAGIC_OFFSET; |
| @@ -1435,7 +1443,9 @@ int qlcnic_82xx_get_board_info(struct qlcnic_adapter *adapter) · 13 unmodified lines | ||
| 1435 | 1443 | adapter->ahw->board_type = board_type; |
| 1436 | 1444 | |
| 1437 | 1445 | if (board_type == QLCNIC_BRDTYPE_P3P_4_GB_MM) { |
| 1438 | − u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I); | |
| 1446 | + u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I, &err); | |
| 1447 | + if (err == -EIO) | |
| 1448 | + return err; | |
| 1439 | 1449 | if ((gpio & 0x8000) == 0) |
| 1440 | 1450 | board_type = QLCNIC_BRDTYPE_P3P_10G_TP; |
| 1441 | 1451 | } |
| @@ -1475,10 +1485,13 @@ int · 33 unmodified lines | ||
| 1475 | 1485 | qlcnic_wol_supported(struct qlcnic_adapter *adapter) |
| 1476 | 1486 | { |
| 1477 | 1487 | u32 wol_cfg; |
| 1488 | + int err = 0; | |
| 1478 | 1489 | |
| 1479 | − wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV); | |
| 1490 | + wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV, &err); | |
| 1480 | 1491 | if (wol_cfg & (1UL << adapter->portnum)) { |
| 1481 | − wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG); | |
| 1492 | + wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG, &err); | |
| 1493 | + if (err == -EIO) | |
| 1494 | + return err; | |
| 1482 | 1495 | if (wol_cfg & (1 << adapter->portnum)) |
| 1483 | 1496 | return 1; |
| 1484 | 1497 | } |
| @@ -1539,6 +1552,7 @@ void qlcnic_82xx_get_func_no(struct qlcnic_adapter *adapter) · 54 unmodified lines | ||
| 1539 | 1552 | void qlcnic_82xx_read_crb(struct qlcnic_adapter *adapter, char *buf, |
| 1540 | 1553 | loff_t offset, size_t size) |
| 1541 | 1554 | { |
| 1555 | + int err = 0; | |
| 1542 | 1556 | u32 data; |
| 1543 | 1557 | u64 qmdata; |
| 1544 | 1558 | |
| @@ -1546,7 +1560,7 @@ void qlcnic_82xx_read_crb(struct qlcnic_adapter *adapter, char *buf, · 1 unmodified line | ||
| 1546 | 1560 | qlcnic_pci_camqm_read_2M(adapter, offset, &qmdata); |
| 1547 | 1561 | memcpy(buf, &qmdata, size); |
| 1548 | 1562 | } else { |
| 1549 | − data = QLCRD32(adapter, offset); | |
| 1563 | + data = QLCRD32(adapter, offset, &err); | |
| 1550 | 1564 | memcpy(buf, &data, size); |
| 1551 | 1565 | } |
| 1552 | 1566 | } |
| @@ -154,7 +154,7 @@ struct qlcnic_hardware_context; · 153 unmodified lines | ||
| 154 | 154 | struct qlcnic_adapter; |
| 155 | 155 | |
| 156 | 156 | int qlcnic_82xx_start_firmware(struct qlcnic_adapter *); |
| 157 | −int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong); | |
| 157 | +int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong, int *); | |
| 158 | 158 | int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *, ulong, u32); |
| 159 | 159 | int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter *adapter, int); |
| 160 | 160 | int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32); |
| @@ -286,10 +286,11 @@ static int qlcnic_wait_rom_done(struct qlcnic_adapter *adapter) · 285 unmodified lines | ||
| 286 | 286 | { |
| 287 | 287 | long timeout = 0; |
| 288 | 288 | long done = 0; |
| 289 | + int err = 0; | |
| 289 | 290 | |
| 290 | 291 | cond_resched(); |
| 291 | 292 | while (done == 0) { |
| 292 | − done = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_STATUS); | |
| 293 | + done = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_STATUS, &err); | |
| 293 | 294 | done &= 2; |
| 294 | 295 | if (++timeout >= QLCNIC_MAX_ROM_WAIT_USEC) { |
| 295 | 296 | dev_err(&adapter->pdev->dev, |
| @@ -304,6 +305,8 @@ static int qlcnic_wait_rom_done(struct qlcnic_adapter *adapter) · 8 unmodified lines | ||
| 304 | 305 | static int do_rom_fast_read(struct qlcnic_adapter *adapter, |
| 305 | 306 | u32 addr, u32 *valp) |
| 306 | 307 | { |
| 308 | + int err = 0; | |
| 309 | + | |
| 307 | 310 | QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ADDRESS, addr); |
| 308 | 311 | QLCWR32(adapter, QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); |
| 309 | 312 | QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ABYTE_CNT, 3); |
| @@ -317,7 +320,9 @@ static int do_rom_fast_read(struct qlcnic_adapter *adapter, · 7 unmodified lines | ||
| 317 | 320 | udelay(10); |
| 318 | 321 | QLCWR32(adapter, QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); |
| 319 | 322 | |
| 320 | − *valp = QLCRD32(adapter, QLCNIC_ROMUSB_ROM_RDATA); | |
| 323 | + *valp = QLCRD32(adapter, QLCNIC_ROMUSB_ROM_RDATA, &err); | |
| 324 | + if (err == -EIO) | |
| 325 | + return err; | |
| 321 | 326 | return 0; |
| 322 | 327 | } |
| 323 | 328 | |
| @@ -369,11 +374,11 @@ int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp) · 45 unmodified lines | ||
| 369 | 374 | |
| 370 | 375 | int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter) |
| 371 | 376 | { |
| 372 | − int addr, val; | |
| 377 | + int addr, err = 0; | |
| 373 | 378 | int i, n, init_delay; |
| 374 | 379 | struct crb_addr_pair *buf; |
| 375 | 380 | unsigned offset; |
| 376 | − u32 off; | |
| 381 | + u32 off, val; | |
| 377 | 382 | struct pci_dev *pdev = adapter->pdev; |
| 378 | 383 | |
| 379 | 384 | QLC_SHARED_REG_WR32(adapter, QLCNIC_CMDPEG_STATE, 0); |
| @@ -402,7 +407,9 @@ int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter) · 22 unmodified lines | ||
| 402 | 407 | QLCWR32(adapter, QLCNIC_CRB_NIU + 0xb0000, 0x00); |
| 403 | 408 | |
| 404 | 409 | /* halt sre */ |
| 405 | − val = QLCRD32(adapter, QLCNIC_CRB_SRE + 0x1000); | |
| 410 | + val = QLCRD32(adapter, QLCNIC_CRB_SRE + 0x1000, &err); | |
| 411 | + if (err == -EIO) | |
| 412 | + return err; | |
| 406 | 413 | QLCWR32(adapter, QLCNIC_CRB_SRE + 0x1000, val & (~(0x1))); |
| 407 | 414 | |
| 408 | 415 | /* halt epg */ |
| @@ -719,10 +726,12 @@ qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter) · 310 unmodified lines | ||
| 719 | 726 | static int |
| 720 | 727 | qlcnic_has_mn(struct qlcnic_adapter *adapter) |
| 721 | 728 | { |
| 722 | − u32 capability; | |
| 723 | − capability = 0; | |
| 729 | + u32 capability = 0; | |
| 730 | + int err = 0; | |
| 724 | 731 | |
| 725 | − capability = QLCRD32(adapter, QLCNIC_PEG_TUNE_CAPABILITY); | |
| 732 | + capability = QLCRD32(adapter, QLCNIC_PEG_TUNE_CAPABILITY, &err); | |
| 733 | + if (err == -EIO) | |
| 734 | + return err; | |
| 726 | 735 | if (capability & QLCNIC_PEG_TUNE_MN_PRESENT) |
| 727 | 736 | return 1; |
| 728 | 737 | |
| @@ -977,8 +977,8 @@ qlcnic_check_options(struct qlcnic_adapter *adapter) · 976 unmodified lines | ||
| 977 | 977 | static int |
| 978 | 978 | qlcnic_initialize_nic(struct qlcnic_adapter *adapter) |
| 979 | 979 | { |
| 980 | − int err; | |
| 981 | 980 | struct qlcnic_info nic_info; |
| 981 | + int err = 0; | |
| 982 | 982 | |
| 983 | 983 | memset(&nic_info, 0, sizeof(struct qlcnic_info)); |
| 984 | 984 | err = qlcnic_get_nic_info(adapter, &nic_info, adapter->ahw->pci_func); |
| @@ -993,7 +993,9 @@ qlcnic_initialize_nic(struct qlcnic_adapter *adapter) · 8 unmodified lines | ||
| 993 | 993 | |
| 994 | 994 | if (adapter->ahw->capabilities & QLCNIC_FW_CAPABILITY_MORE_CAPS) { |
| 995 | 995 | u32 temp; |
| 996 | − temp = QLCRD32(adapter, CRB_FW_CAPABILITIES_2); | |
| 996 | + temp = QLCRD32(adapter, CRB_FW_CAPABILITIES_2, &err); | |
| 997 | + if (err == -EIO) | |
| 998 | + return err; | |
| 997 | 999 | adapter->ahw->extra_capability[0] = temp; |
| 998 | 1000 | } |
| 999 | 1001 | adapter->ahw->max_mac_filters = nic_info.max_mac_filters; |
| @@ -3095,6 +3097,7 @@ qlcnic_check_health(struct qlcnic_adapter *adapter) · 2095 unmodified lines | ||
| 3095 | 3097 | { |
| 3096 | 3098 | u32 state = 0, heartbeat; |
| 3097 | 3099 | u32 peg_status; |
| 3100 | + int err = 0; | |
| 3098 | 3101 | |
| 3099 | 3102 | if (qlcnic_check_temp(adapter)) |
| 3100 | 3103 | goto detach; |
| @@ -3141,11 +3144,11 @@ qlcnic_check_health(struct qlcnic_adapter *adapter) · 40 unmodified lines | ||
| 3141 | 3144 | "PEG_NET_4_PC: 0x%x\n", |
| 3142 | 3145 | peg_status, |
| 3143 | 3146 | QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS2), |
| 3144 | − QLCRD32(adapter, QLCNIC_CRB_PEG_NET_0 + 0x3c), | |
| 3145 | − QLCRD32(adapter, QLCNIC_CRB_PEG_NET_1 + 0x3c), | |
| 3146 | − QLCRD32(adapter, QLCNIC_CRB_PEG_NET_2 + 0x3c), | |
| 3147 | − QLCRD32(adapter, QLCNIC_CRB_PEG_NET_3 + 0x3c), | |
| 3148 | − QLCRD32(adapter, QLCNIC_CRB_PEG_NET_4 + 0x3c)); | |
| 3147 | + QLCRD32(adapter, QLCNIC_CRB_PEG_NET_0 + 0x3c, &err), | |
| 3148 | + QLCRD32(adapter, QLCNIC_CRB_PEG_NET_1 + 0x3c, &err), | |
| 3149 | + QLCRD32(adapter, QLCNIC_CRB_PEG_NET_2 + 0x3c, &err), | |
| 3150 | + QLCRD32(adapter, QLCNIC_CRB_PEG_NET_3 + 0x3c, &err), | |
| 3151 | + QLCRD32(adapter, QLCNIC_CRB_PEG_NET_4 + 0x3c, &err)); | |
| 3149 | 3152 | if (QLCNIC_FWERROR_CODE(peg_status) == 0x67) |
| 3150 | 3153 | dev_err(&adapter->pdev->dev, |
| 3151 | 3154 | "Firmware aborted with error code 0x00006700. " |