Merge tag 'mfd-next-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

Pull MFD updates from Lee Jones: "New Drivers: - Add support for Merrifield Basin Cove PMIC New Device Support: - Add support for Intel Tiger Lake to Intel LPSS PCI - Add support for Intel Sky Lake to Intel LPSS PCI - Add support for ST-Ericsson DB8520 to DB8500 PRCMU New Functionality: - Add RTC and PWRC support to MT6323 Fix-ups: - Clean-up include files; davinci_voicecodec, asic3, sm501, mt6397 - Ignore return values from debugfs_create*(); ab3100-*, ab8500-debugfs, aat2870-core - Device Tree changes; rn5t618, mt6397 - Use new I2C API; tps80031, 88pm860x-core, ab3100-core, bcm590xx, da9150-core, max14577, max77693, max77843, max8907, max8925-i2c, max8997, max8998, palmas, twl-core, - Remove obsolete code; da9063, jz4740-adc - Simplify semantics; timberdale, htc-i2cpld - Add 'fall-through' tags; omap-usb-host, db8500-prcmu - Remove superfluous prints; ab8500-debugfs, db8500-prcmu, fsl-imx25-tsadc, intel_soc_pmic_bxtwc, qcom_rpm, sm501 - Trivial rename/whitespace/typo fixes; mt6397-core, MAINTAINERS - Reorganise code structure; mt6397-* - Improve code consistency; intel-lpss - Use MODULE_SOFTDEP() helper; intel-lpss - Use DEFINE_RES_*() helpers; mt6397-core Bug Fixes: - Clean-up resources; max77620 - Prevent input events being dropped on resume; intel-lpss-pci - Prevent sleeping in IRQ context; ezx-pcap" * tag 'mfd-next-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (48 commits) mfd: mt6323: Add MT6323 RTC and PWRC mfd: mt6323: Replace boilerplate resource code with DEFINE_RES_* macros mfd: mt6397: Add mutex include dt-bindings: mfd: mediatek: Add MT6323 Power Controller dt-bindings: mfd: mediatek: Update RTC to include MT6323 dt-bindings: mfd: mediatek: mt6397: Change to relative paths mfd: db8500-prcmu: Support the higher DB8520 ARMSS mfd: intel-lpss: Use MODULE_SOFTDEP() instead of implicit request mfd: htc-i2cpld: Drop check because i2c_unregister_device() is NULL safe mfd: sm501: Include the GPIO driver header mfd: intel-lpss: Add Intel Skylake ACPI IDs mfd: intel-lpss: Consistently use GENMASK() mfd: Add support for Merrifield Basin Cove PMIC mfd: ezx-pcap: Replace mutex_lock with spin_lock mfd: asic3: Include the right header MAINTAINERS: altera-sysmgr: Fix typo in a filepath mfd: mt6397: Extract IRQ related code from core driver mfd: mt6397: Rename macros to something more readable mfd: Remove dev_err() usage after platform_get_irq() mfd: db8500-prcmu: Mark expected switch fall-throughs ...

Linus Torvalds committed 7 years ago

Commit 4c07e2d2 parents d0b3cfe 8391c6c45 files · +742 −727Browse files

Unified · Split

45 files

Documentation/devicetree/bindings/mfd/mt6397.txt +14 −6
Documentation/devicetree/bindings/mfd/rn5t618.txt +5 −0
Documentation/devicetree/bindings/power/reset/mt6323-poweroff.txt +20 −0
MAINTAINERS +1 −1
drivers/mfd/88pm800.c +6 −6
drivers/mfd/88pm860x-core.c +3 −3
drivers/mfd/Kconfig +11 −9
drivers/mfd/Makefile +3 −2
drivers/mfd/ab3100-core.c +3 −3
drivers/mfd/ab8500-debugfs.c +2 −6
drivers/mfd/asic3.c +1 −1
drivers/mfd/bcm590xx.c +3 −3
drivers/mfd/da9150-core.c +3 −3
drivers/mfd/davinci_voicecodec.c +4 −5
drivers/mfd/db8500-prcmu.c +36 −8
drivers/mfd/ezx-pcap.c +30 −23
drivers/mfd/fsl-imx25-tsadc.c +1 −3
drivers/mfd/htc-i2cpld.c +1 −2
drivers/mfd/intel-lpss-acpi.c +26 −0
drivers/mfd/intel-lpss-pci.c +25 −0
drivers/mfd/intel-lpss.c +13 −26
drivers/mfd/intel_soc_pmic_bxtwc.c +1 −3
drivers/mfd/intel_soc_pmic_mrfld.c +157 −0
drivers/mfd/jz4740-adc.c +0 −324
drivers/mfd/max14577.c +3 −3
drivers/mfd/max77620.c +3 −1
drivers/mfd/max77693.c +6 −6
drivers/mfd/max77843.c +3 −3
drivers/mfd/max8907.c +3 −3
drivers/mfd/max8925-i2c.c +6 −6
drivers/mfd/max8997.c +9 −9
drivers/mfd/max8998.c +3 −3
drivers/mfd/mt6397-core.c +32 −160
drivers/mfd/mt6397-irq.c +181 −0
drivers/mfd/palmas.c +3 −3
drivers/mfd/qcom_rpm.c +3 −9
drivers/mfd/sm501.c +2 −3
drivers/mfd/timberdale.c +1 −2
drivers/mfd/tps80031.c +8 −15
drivers/mfd/twl-core.c +3 −3
include/Kbuild +0 −1
include/linux/mfd/da9063/pdata.h +0 −60
include/linux/mfd/intel_soc_pmic_mrfld.h +81 −0
include/linux/mfd/mt6397/core.h +11 −0
include/linux/platform_data/cros_ec_commands.h +12 −0

Documentation/devicetree/bindings/mfd/mt6397.txt+14−6

@@ -8,11 +8,12 @@ MT6397/MT6323 is a multifunction device with the following sub modules: · 7 unmodified lines
8	8	- Clock
9	9	- LED
10	10	- Keys
	11	+- Power controller
11	12
12	13	It is interfaced to host controller using SPI interface by a proprietary hardware
13	14	called PMIC wrapper or pwrap. MT6397/MT6323 MFD is a child device of pwrap.
14	15	See the following for pwarp node definitions:
15		−Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
	16	+../soc/mediatek/pwrap.txt
16	17
17	18	This document describes the binding for MFD device and its sub module.
18	19
@@ -22,14 +23,16 @@ compatible: "mediatek,mt6397" or "mediatek,mt6323" · 3 unmodified lines
22	23	Optional subnodes:
23	24
24	25	- rtc
25		− Required properties:
	26	+ Required properties: Should be one of follows
	27	+ - compatible: "mediatek,mt6323-rtc"
26	28	- compatible: "mediatek,mt6397-rtc"
	29	+ For details, see ../rtc/rtc-mt6397.txt
27	30	- regulators
28	31	Required properties:
29	32	- compatible: "mediatek,mt6397-regulator"
30		− see Documentation/devicetree/bindings/regulator/mt6397-regulator.txt
	33	+ see ../regulator/mt6397-regulator.txt
31	34	- compatible: "mediatek,mt6323-regulator"
32		− see Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
	35	+ see ../regulator/mt6323-regulator.txt
33	36	- codec
34	37	Required properties:
35	38	- compatible: "mediatek,mt6397-codec"
@@ -39,12 +42,17 @@ Optional subnodes: · 3 unmodified lines
39	42	- led
40	43	Required properties:
41	44	- compatible: "mediatek,mt6323-led"
42		− see Documentation/devicetree/bindings/leds/leds-mt6323.txt
	45	+ see ../leds/leds-mt6323.txt
43	46
44	47	- keys
45	48	Required properties:
46	49	- compatible: "mediatek,mt6397-keys" or "mediatek,mt6323-keys"
47		− see Documentation/devicetree/bindings/input/mtk-pmic-keys.txt
	50	+ see ../input/mtk-pmic-keys.txt
	51	+
	52	+- power-controller
	53	+ Required properties:
	54	+ - compatible: "mediatek,mt6323-pwrc"
	55	+ For details, see ../power/reset/mt6323-poweroff.txt
48	56
49	57	Example:
50	58	pwrap: pwrap@1000f000 {

Documentation/devicetree/bindings/mfd/rn5t618.txt+5−0

@@ -14,6 +14,10 @@ Required properties: · 13 unmodified lines
14	14	"ricoh,rc5t619"
15	15	- reg: the I2C slave address of the device
16	16
	17	+Optional properties:
	18	+ - system-power-controller:
	19	+ See Documentation/devicetree/bindings/power/power-controller.txt
	20	+
17	21	Sub-nodes:
18	22	- regulators: the node is required if the regulator functionality is
19	23	needed. The valid regulator names are: DCDC1, DCDC2, DCDC3, DCDC4
@@ -28,6 +32,7 @@ Example: · 8 unmodified lines
28	32	pmic@32 {
29	33	compatible = "ricoh,rn5t618";
30	34	reg = <0x32>;
	35	+ system-power-controller;
31	36
32	37	regulators {
33	38	DCDC1 {

Documentation/devicetree/bindings/power/reset/mt6323-poweroff.txt+20−0

@@ -0,0 +1,20 @@
	1	+Device Tree Bindings for Power Controller on MediaTek PMIC
	2	+
	3	+The power controller which could be found on PMIC is responsible for externally
	4	+powering off or on the remote MediaTek SoC through the circuit BBPU.
	5	+
	6	+Required properties:
	7	+- compatible: Should be one of follows
	8	+ "mediatek,mt6323-pwrc": for MT6323 PMIC
	9	+
	10	+Example:
	11	+
	12	+ pmic {
	13	+ compatible = "mediatek,mt6323";
	14	+
	15	+ ...
	16	+
	17	+ power-controller {
	18	+ compatible = "mediatek,mt6323-pwrc";
	19	+ };
	20	+ }

MAINTAINERS+1−1

@@ -728,7 +728,7 @@ ALTERA SYSTEM MANAGER DRIVER · 727 unmodified lines
728	728	M: Thor Thayer <thor.thayer@linux.intel.com>
729	729	S: Maintained
730	730	F: drivers/mfd/altera-sysmgr.c
731		−F: include/linux/mfd/altera-sysgmr.h
	731	+F: include/linux/mfd/altera-sysmgr.h
732	732
733	733	ALTERA SYSTEM RESOURCE DRIVER FOR ARRIA10 DEVKIT
734	734	M: Thor Thayer <thor.thayer@linux.intel.com>

drivers/mfd/88pm800.c+6−6

@@ -425,10 +425,10 @@ static int pm800_pages_init(struct pm80x_chip *chip) · 424 unmodified lines
425	425	return -ENODEV;
426	426
427	427	/* PM800 block power page */
428		− subchip->power_page = i2c_new_dummy(client->adapter,
	428	+ subchip->power_page = i2c_new_dummy_device(client->adapter,
429	429	subchip->power_page_addr);
430		− if (subchip->power_page == NULL) {
431		− ret = -ENODEV;
	430	+ if (IS_ERR(subchip->power_page)) {
	431	+ ret = PTR_ERR(subchip->power_page);
432	432	goto out;
433	433	}
434	434
@@ -444,10 +444,10 @@ static int pm800_pages_init(struct pm80x_chip *chip) · 9 unmodified lines
444	444	i2c_set_clientdata(subchip->power_page, chip);
445	445
446	446	/* PM800 block GPADC */
447		− subchip->gpadc_page = i2c_new_dummy(client->adapter,
	447	+ subchip->gpadc_page = i2c_new_dummy_device(client->adapter,
448	448	subchip->gpadc_page_addr);
449		− if (subchip->gpadc_page == NULL) {
450		− ret = -ENODEV;
	449	+ if (IS_ERR(subchip->gpadc_page)) {
	450	+ ret = PTR_ERR(subchip->gpadc_page);
451	451	goto out;
452	452	}
453	453

drivers/mfd/88pm860x-core.c+3−3

@@ -1178,12 +1178,12 @@ static int pm860x_probe(struct i2c_client *client) · 1177 unmodified lines
1178	1178	*/
1179	1179	if (pdata->companion_addr && (pdata->companion_addr != client->addr)) {
1180	1180	chip->companion_addr = pdata->companion_addr;
1181		− chip->companion = i2c_new_dummy(chip->client->adapter,
	1181	+ chip->companion = i2c_new_dummy_device(chip->client->adapter,
1182	1182	chip->companion_addr);
1183		− if (!chip->companion) {
	1183	+ if (IS_ERR(chip->companion)) {
1184	1184	dev_err(&client->dev,
1185	1185	"Failed to allocate I2C companion device\n");
1186		− return -ENODEV;
	1186	+ return PTR_ERR(chip->companion);
1187	1187	}
1188	1188	chip->regmap_companion = regmap_init_i2c(chip->companion,
1189	1189	&pm860x_regmap_config);

drivers/mfd/Kconfig+11−9

@@ -589,6 +589,17 @@ config INTEL_SOC_PMIC_CHTDC_TI · 588 unmodified lines
589	589	Select this option for supporting Dollar Cove (TI version) PMIC
590	590	device that is found on some Intel Cherry Trail systems.
591	591
	592	+config INTEL_SOC_PMIC_MRFLD
	593	+ tristate "Support for Intel Merrifield Basin Cove PMIC"
	594	+ depends on GPIOLIB
	595	+ depends on ACPI
	596	+ depends on INTEL_SCU_IPC
	597	+ select MFD_CORE
	598	+ select REGMAP_IRQ
	599	+ help
	600	+ Select this option for supporting Basin Cove PMIC device
	601	+ that is found on Intel Merrifield systems.
	602	+
592	603	config MFD_INTEL_LPSS
593	604	tristate
594	605	select COMMON_CLK
@@ -641,15 +652,6 @@ config MFD_JANZ_CMODIO · 46 unmodified lines
641	652	host many different types of MODULbus daughterboards, including
642	653	CAN and GPIO controllers.
643	654
644		−config MFD_JZ4740_ADC
645		− bool "Janz JZ4740 ADC core"
646		− select MFD_CORE
647		− select GENERIC_IRQ_CHIP
648		− depends on MACH_JZ4740
649		− help
650		− Say yes here if you want support for the ADC unit in the JZ4740 SoC.
651		− This driver is necessary for jz4740-battery and jz4740-hwmon driver.
652		−
653	655	config MFD_KEMPLD
654	656	tristate "Kontron module PLD device"
655	657	select MFD_CORE

drivers/mfd/Makefile+3−2

@@ -189,7 +189,6 @@ obj-$(CONFIG_LPC_SCH) += lpc_sch.o · 188 unmodified lines
189	189	obj-$(CONFIG_LPC_ICH) += lpc_ich.o
190	190	obj-$(CONFIG_MFD_RDC321X) += rdc321x-southbridge.o
191	191	obj-$(CONFIG_MFD_JANZ_CMODIO) += janz-cmodio.o
192		−obj-$(CONFIG_MFD_JZ4740_ADC) += jz4740-adc.o
193	192	obj-$(CONFIG_MFD_TPS6586X) += tps6586x.o
194	193	obj-$(CONFIG_MFD_VX855) += vx855.o
195	194	obj-$(CONFIG_MFD_WL1273_CORE) += wl1273-core.o
@@ -239,7 +238,9 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o · 43 unmodified lines
239	238	obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC) += intel_soc_pmic_bxtwc.o
240	239	obj-$(CONFIG_INTEL_SOC_PMIC_CHTWC) += intel_soc_pmic_chtwc.o
241	240	obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI) += intel_soc_pmic_chtdc_ti.o
242		−obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
	241	+mt6397-objs := mt6397-core.o mt6397-irq.o
	242	+obj-$(CONFIG_MFD_MT6397) += mt6397.o
	243	+obj-$(CONFIG_INTEL_SOC_PMIC_MRFLD) += intel_soc_pmic_mrfld.o
243	244
244	245	obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
245	246	obj-$(CONFIG_MFD_ALTERA_SYSMGR) += altera-sysmgr.o

drivers/mfd/ab3100-core.c+3−3

@@ -865,10 +865,10 @@ static int ab3100_probe(struct i2c_client *client, · 864 unmodified lines
865	865	&ab3100->chip_name[0]);
866	866
867	867	/* Attach a second dummy i2c_client to the test register address */
868		− ab3100->testreg_client = i2c_new_dummy(client->adapter,
	868	+ ab3100->testreg_client = i2c_new_dummy_device(client->adapter,
869	869	client->addr + 1);
870		− if (!ab3100->testreg_client) {
871		− err = -ENOMEM;
	870	+ if (IS_ERR(ab3100->testreg_client)) {
	871	+ err = PTR_ERR(ab3100->testreg_client);
872	872	goto exit_no_testreg_client;
873	873	}
874	874

drivers/mfd/ab8500-debugfs.c+2−6

@@ -2680,16 +2680,12 @@ static int ab8500_debug_probe(struct platform_device *plf) · 2679 unmodified lines
2680	2680	irq_ab8500 = res->start;
2681	2681
2682	2682	irq_first = platform_get_irq_byname(plf, "IRQ_FIRST");
2683		− if (irq_first < 0) {
2684		− dev_err(&plf->dev, "First irq not found, err %d\n", irq_first);
	2683	+ if (irq_first < 0)
2685	2684	return irq_first;
2686		− }
2687	2685
2688	2686	irq_last = platform_get_irq_byname(plf, "IRQ_LAST");
2689		− if (irq_last < 0) {
2690		− dev_err(&plf->dev, "Last irq not found, err %d\n", irq_last);
	2687	+ if (irq_last < 0)
2691	2688	return irq_last;
2692		− }
2693	2689
2694	2690	ab8500_dir = debugfs_create_dir(AB8500_NAME_STRING, NULL);
2695	2691

drivers/mfd/asic3.c+1−1

@@ -15,7 +15,7 @@ · 14 unmodified lines
15	15	#include <linux/kernel.h>
16	16	#include <linux/delay.h>
17	17	#include <linux/irq.h>
18		−#include <linux/gpio.h>
	18	+#include <linux/gpio/driver.h>
19	19	#include <linux/export.h>
20	20	#include <linux/io.h>
21	21	#include <linux/slab.h>

drivers/mfd/bcm590xx.c+3−3

@@ -61,11 +61,11 @@ static int bcm590xx_i2c_probe(struct i2c_client *i2c_pri, · 60 unmodified lines
61	61	}
62	62
63	63	/* Secondary I2C slave address is the base address with A(2) asserted */
64		− bcm590xx->i2c_sec = i2c_new_dummy(i2c_pri->adapter,
	64	+ bcm590xx->i2c_sec = i2c_new_dummy_device(i2c_pri->adapter,
65	65	i2c_pri->addr \| BIT(2));
66		− if (!bcm590xx->i2c_sec) {
	66	+ if (IS_ERR(bcm590xx->i2c_sec)) {
67	67	dev_err(&i2c_pri->dev, "failed to add secondary I2C device\n");
68		− return -ENODEV;
	68	+ return PTR_ERR(bcm590xx->i2c_sec);
69	69	}
70	70	i2c_set_clientdata(bcm590xx->i2c_sec, bcm590xx);
71	71

drivers/mfd/da9150-core.c+3−3

@@ -420,10 +420,10 @@ static int da9150_probe(struct i2c_client *client, · 419 unmodified lines
420	420	qif_addr = da9150_reg_read(da9150, DA9150_CORE2WIRE_CTRL_A);
421	421	qif_addr = (qif_addr & DA9150_CORE_BASE_ADDR_MASK) >> 1;
422	422	qif_addr \|= DA9150_QIF_I2C_ADDR_LSB;
423		− da9150->core_qif = i2c_new_dummy(client->adapter, qif_addr);
424		− if (!da9150->core_qif) {
	423	+ da9150->core_qif = i2c_new_dummy_device(client->adapter, qif_addr);
	424	+ if (IS_ERR(da9150->core_qif)) {
425	425	dev_err(da9150->dev, "Failed to attach QIF client\n");
426		− return -ENODEV;
	426	+ return PTR_ERR(da9150->core_qif);
427	427	}
428	428
429	429	i2c_set_clientdata(da9150->core_qif, da9150);

drivers/mfd/davinci_voicecodec.c+4−5

@@ -19,7 +19,6 @@ · 18 unmodified lines
19	19	#include <sound/pcm.h>
20	20
21	21	#include <linux/mfd/davinci_voicecodec.h>
22		−#include <mach/hardware.h>
23	22
24	23	static const struct regmap_config davinci_vc_regmap = {
25	24	.reg_bits = 32,
@@ -31,6 +30,7 @@ static int __init davinci_vc_probe(struct platform_device *pdev) · 5 unmodified lines
31	30	struct davinci_vc *davinci_vc;
32	31	struct resource *res;
33	32	struct mfd_cell *cell = NULL;
	33	+ dma_addr_t fifo_base;
34	34	int ret;
35	35
36	36	davinci_vc = devm_kzalloc(&pdev->dev,
@@ -48,6 +48,7 @@ static int __init davinci_vc_probe(struct platform_device *pdev) · 11 unmodified lines
48	48
49	49	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
50	50
	51	+ fifo_base = (dma_addr_t)res->start;
51	52	davinci_vc->base = devm_ioremap_resource(&pdev->dev, res);
52	53	if (IS_ERR(davinci_vc->base)) {
53	54	ret = PTR_ERR(davinci_vc->base);
@@ -70,8 +71,7 @@ static int __init davinci_vc_probe(struct platform_device *pdev) · 16 unmodified lines
70	71	}
71	72
72	73	davinci_vc->davinci_vcif.dma_tx_channel = res->start;
73		− davinci_vc->davinci_vcif.dma_tx_addr =
74		− (dma_addr_t)(io_v2p(davinci_vc->base) + DAVINCI_VC_WFIFO);
	74	+ davinci_vc->davinci_vcif.dma_tx_addr = fifo_base + DAVINCI_VC_WFIFO;
75	75
76	76	res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
77	77	if (!res) {
@@ -81,8 +81,7 @@ static int __init davinci_vc_probe(struct platform_device *pdev) · 3 unmodified lines
81	81	}
82	82
83	83	davinci_vc->davinci_vcif.dma_rx_channel = res->start;
84		− davinci_vc->davinci_vcif.dma_rx_addr =
85		− (dma_addr_t)(io_v2p(davinci_vc->base) + DAVINCI_VC_RFIFO);
	84	+ davinci_vc->davinci_vcif.dma_rx_addr = fifo_base + DAVINCI_VC_RFIFO;
86	85
87	86	davinci_vc->dev = &pdev->dev;
88	87	davinci_vc->pdev = pdev;

drivers/mfd/db8500-prcmu.c+36−8

@@ -1695,21 +1695,41 @@ static long round_clock_rate(u8 clock, unsigned long rate) · 1694 unmodified lines
1695	1695	return rounded_rate;
1696	1696	}
1697	1697
1698		−static const unsigned long armss_freqs[] = {
	1698	+static const unsigned long db8500_armss_freqs[] = {
1699	1699	200000000,
1700	1700	400000000,
1701	1701	800000000,
1702	1702	998400000
1703	1703	};
1704	1704
	1705	+/* The DB8520 has slightly higher ARMSS max frequency */
	1706	+static const unsigned long db8520_armss_freqs[] = {
	1707	+ 200000000,
	1708	+ 400000000,
	1709	+ 800000000,
	1710	+ 1152000000
	1711	+};
	1712	+
	1713	+
	1714	+
1705	1715	static long round_armss_rate(unsigned long rate)
1706	1716	{
1707	1717	unsigned long freq = 0;
	1718	+ const unsigned long *freqs;
	1719	+ int nfreqs;
1708	1720	int i;
1709	1721
	1722	+ if (fw_info.version.project == PRCMU_FW_PROJECT_U8520) {
	1723	+ freqs = db8520_armss_freqs;
	1724	+ nfreqs = ARRAY_SIZE(db8520_armss_freqs);
	1725	+ } else {
	1726	+ freqs = db8500_armss_freqs;
	1727	+ nfreqs = ARRAY_SIZE(db8500_armss_freqs);
	1728	+ }
	1729	+
1710	1730	/* Find the corresponding arm opp from the cpufreq table. */
1711		− for (i = 0; i < ARRAY_SIZE(armss_freqs); i++) {
1712		− freq = armss_freqs[i];
	1731	+ for (i = 0; i < nfreqs; i++) {
	1732	+ freq = freqs[i];
1713	1733	if (rate <= freq)
1714	1734	break;
1715	1735	}
@@ -1854,11 +1874,21 @@ static int set_armss_rate(unsigned long rate) · 138 unmodified lines
1854	1874	{
1855	1875	unsigned long freq;
1856	1876	u8 opps[] = { ARM_EXTCLK, ARM_50_OPP, ARM_100_OPP, ARM_MAX_OPP };
	1877	+ const unsigned long *freqs;
	1878	+ int nfreqs;
1857	1879	int i;
1858	1880
	1881	+ if (fw_info.version.project == PRCMU_FW_PROJECT_U8520) {
	1882	+ freqs = db8520_armss_freqs;
	1883	+ nfreqs = ARRAY_SIZE(db8520_armss_freqs);
	1884	+ } else {
	1885	+ freqs = db8500_armss_freqs;
	1886	+ nfreqs = ARRAY_SIZE(db8500_armss_freqs);
	1887	+ }
	1888	+
1859	1889	/* Find the corresponding arm opp from the cpufreq table. */
1860		− for (i = 0; i < ARRAY_SIZE(armss_freqs); i++) {
1861		− freq = armss_freqs[i];
	1890	+ for (i = 0; i < nfreqs; i++) {
	1891	+ freq = freqs[i];
1862	1892	if (rate == freq)
1863	1893	break;
1864	1894	}
@@ -3130,10 +3160,8 @@ static int db8500_prcmu_probe(struct platform_device *pdev) · 1265 unmodified lines
3130	3160	writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
3131	3161
3132	3162	irq = platform_get_irq(pdev, 0);
3133		− if (irq <= 0) {
3134		− dev_err(&pdev->dev, "no prcmu irq provided\n");
	3163	+ if (irq <= 0)
3135	3164	return irq;
3136		− }
3137	3165
3138	3166	err = request_threaded_irq(irq, prcmu_irq_handler,
3139	3167	prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);

drivers/mfd/ezx-pcap.c+30−23

@@ -35,7 +35,7 @@ struct pcap_chip { · 34 unmodified lines
35	35
36	36	/* IO */
37	37	u32 buf;
38		− struct mutex io_mutex;
	38	+ spinlock_t io_lock;
39	39
40	40	/* IRQ */
41	41	unsigned int irq_base;
@@ -48,7 +48,7 @@ struct pcap_chip { · 6 unmodified lines
48	48	struct pcap_adc_request *adc_queue[PCAP_ADC_MAXQ];
49	49	u8 adc_head;
50	50	u8 adc_tail;
51		− struct mutex adc_mutex;
	51	+ spinlock_t adc_lock;
52	52	};
53	53
54	54	/* IO */
@@ -76,14 +76,15 @@ static int ezx_pcap_putget(struct pcap_chip pcap, u32 data) · 21 unmodified lines
76	76
77	77	int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value)
78	78	{
	79	+ unsigned long flags;
79	80	int ret;
80	81
81		− mutex_lock(&pcap->io_mutex);
	82	+ spin_lock_irqsave(&pcap->io_lock, flags);
82	83	value &= PCAP_REGISTER_VALUE_MASK;
83	84	value \|= PCAP_REGISTER_WRITE_OP_BIT
84	85	\| (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
85	86	ret = ezx_pcap_putget(pcap, &value);
86		− mutex_unlock(&pcap->io_mutex);
	87	+ spin_unlock_irqrestore(&pcap->io_lock, flags);
87	88
88	89	return ret;
89	90	}
@@ -91,14 +92,15 @@ EXPORT_SYMBOL_GPL(ezx_pcap_write); · 1 unmodified line
91	92
92	93	int ezx_pcap_read(struct pcap_chip pcap, u8 reg_num, u32 value)
93	94	{
	95	+ unsigned long flags;
94	96	int ret;
95	97
96		− mutex_lock(&pcap->io_mutex);
	98	+ spin_lock_irqsave(&pcap->io_lock, flags);
97	99	*value = PCAP_REGISTER_READ_OP_BIT
98	100	\| (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
99	101
100	102	ret = ezx_pcap_putget(pcap, value);
101		− mutex_unlock(&pcap->io_mutex);
	103	+ spin_unlock_irqrestore(&pcap->io_lock, flags);
102	104
103	105	return ret;
104	106	}
@@ -106,11 +108,12 @@ EXPORT_SYMBOL_GPL(ezx_pcap_read); · 1 unmodified line
106	108
107	109	int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val)
108	110	{
	111	+ unsigned long flags;
109	112	int ret;
110	113	u32 tmp = PCAP_REGISTER_READ_OP_BIT \|
111	114	(reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
112	115
113		− mutex_lock(&pcap->io_mutex);
	116	+ spin_lock_irqsave(&pcap->io_lock, flags);
114	117	ret = ezx_pcap_putget(pcap, &tmp);
115	118	if (ret)
116	119	goto out_unlock;
@@ -121,7 +124,7 @@ int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val) · 4 unmodified lines
121	124
122	125	ret = ezx_pcap_putget(pcap, &tmp);
123	126	out_unlock:
124		− mutex_unlock(&pcap->io_mutex);
	127	+ spin_unlock_irqrestore(&pcap->io_lock, flags);
125	128
126	129	return ret;
127	130	}
@@ -212,14 +215,15 @@ static void pcap_irq_handler(struct irq_desc *desc) · 84 unmodified lines
212	215	/* ADC */
213	216	void pcap_set_ts_bits(struct pcap_chip *pcap, u32 bits)
214	217	{
	218	+ unsigned long flags;
215	219	u32 tmp;
216	220
217		− mutex_lock(&pcap->adc_mutex);
	221	+ spin_lock_irqsave(&pcap->adc_lock, flags);
218	222	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
219	223	tmp &= ~(PCAP_ADC_TS_M_MASK \| PCAP_ADC_TS_REF_LOWPWR);
220	224	tmp \|= bits & (PCAP_ADC_TS_M_MASK \| PCAP_ADC_TS_REF_LOWPWR);
221	225	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
222		− mutex_unlock(&pcap->adc_mutex);
	226	+ spin_unlock_irqrestore(&pcap->adc_lock, flags);
223	227	}
224	228	EXPORT_SYMBOL_GPL(pcap_set_ts_bits);
225	229
@@ -234,15 +238,16 @@ static void pcap_disable_adc(struct pcap_chip *pcap) · 8 unmodified lines
234	238
235	239	static void pcap_adc_trigger(struct pcap_chip *pcap)
236	240	{
	241	+ unsigned long flags;
237	242	u32 tmp;
238	243	u8 head;
239	244
240		− mutex_lock(&pcap->adc_mutex);
	245	+ spin_lock_irqsave(&pcap->adc_lock, flags);
241	246	head = pcap->adc_head;
242	247	if (!pcap->adc_queue[head]) {
243	248	/* queue is empty, save power */
244	249	pcap_disable_adc(pcap);
245		− mutex_unlock(&pcap->adc_mutex);
	250	+ spin_unlock_irqrestore(&pcap->adc_lock, flags);
246	251	return;
247	252	}
248	253	/* start conversion on requested bank, save TS_M bits */
@@ -254,7 +259,7 @@ static void pcap_adc_trigger(struct pcap_chip *pcap) · 5 unmodified lines
254	259	tmp \|= PCAP_ADC_AD_SEL1;
255	260
256	261	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
257		− mutex_unlock(&pcap->adc_mutex);
	262	+ spin_unlock_irqrestore(&pcap->adc_lock, flags);
258	263	ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC);
259	264	}
260	265
@@ -265,11 +270,11 @@ static irqreturn_t pcap_adc_irq(int irq, void *_pcap) · 4 unmodified lines
265	270	u16 res[2];
266	271	u32 tmp;
267	272
268		− mutex_lock(&pcap->adc_mutex);
	273	+ spin_lock(&pcap->adc_lock);
269	274	req = pcap->adc_queue[pcap->adc_head];
270	275
271	276	if (WARN(!req, "adc irq without pending request\n")) {
272		− mutex_unlock(&pcap->adc_mutex);
	277	+ spin_unlock(&pcap->adc_lock);
273	278	return IRQ_HANDLED;
274	279	}
275	280
@@ -285,7 +290,7 @@ static irqreturn_t pcap_adc_irq(int irq, void *_pcap) · 9 unmodified lines
285	290
286	291	pcap->adc_queue[pcap->adc_head] = NULL;
287	292	pcap->adc_head = (pcap->adc_head + 1) & (PCAP_ADC_MAXQ - 1);
288		− mutex_unlock(&pcap->adc_mutex);
	293	+ spin_unlock(&pcap->adc_lock);
289	294
290	295	/* pass the results and release memory */
291	296	req->callback(req->data, res);
@@ -301,6 +306,7 @@ int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[], · 9 unmodified lines
301	306	void callback, void data)
302	307	{
303	308	struct pcap_adc_request *req;
	309	+ unsigned long irq_flags;
304	310
305	311	/* This will be freed after we have a result */
306	312	req = kmalloc(sizeof(struct pcap_adc_request), GFP_KERNEL);
@@ -314,15 +320,15 @@ int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[], · 7 unmodified lines
314	320	req->callback = callback;
315	321	req->data = data;
316	322
317		− mutex_lock(&pcap->adc_mutex);
	323	+ spin_lock_irqsave(&pcap->adc_lock, irq_flags);
318	324	if (pcap->adc_queue[pcap->adc_tail]) {
319		− mutex_unlock(&pcap->adc_mutex);
	325	+ spin_unlock_irqrestore(&pcap->adc_lock, irq_flags);
320	326	kfree(req);
321	327	return -EBUSY;
322	328	}
323	329	pcap->adc_queue[pcap->adc_tail] = req;
324	330	pcap->adc_tail = (pcap->adc_tail + 1) & (PCAP_ADC_MAXQ - 1);
325		− mutex_unlock(&pcap->adc_mutex);
	331	+ spin_unlock_irqrestore(&pcap->adc_lock, irq_flags);
326	332
327	333	/* start conversion */
328	334	pcap_adc_trigger(pcap);
@@ -389,16 +395,17 @@ static int pcap_add_subdev(struct pcap_chip *pcap, · 60 unmodified lines
389	395	static int ezx_pcap_remove(struct spi_device *spi)
390	396	{
391	397	struct pcap_chip *pcap = spi_get_drvdata(spi);
	398	+ unsigned long flags;
392	399	int i;
393	400
394	401	/* remove all registered subdevs */
395	402	device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
396	403
397	404	/* cleanup ADC */
398		− mutex_lock(&pcap->adc_mutex);
	405	+ spin_lock_irqsave(&pcap->adc_lock, flags);
399	406	for (i = 0; i < PCAP_ADC_MAXQ; i++)
400	407	kfree(pcap->adc_queue[i]);
401		− mutex_unlock(&pcap->adc_mutex);
	408	+ spin_unlock_irqrestore(&pcap->adc_lock, flags);
402	409
403	410	/* cleanup irqchip */
404	411	for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
@@ -426,8 +433,8 @@ static int ezx_pcap_probe(struct spi_device *spi) · 21 unmodified lines
426	433	goto ret;
427	434	}
428	435
429		− mutex_init(&pcap->io_mutex);
430		− mutex_init(&pcap->adc_mutex);
	436	+ spin_lock_init(&pcap->io_lock);
	437	+ spin_lock_init(&pcap->adc_lock);
431	438	INIT_WORK(&pcap->isr_work, pcap_isr_work);
432	439	INIT_WORK(&pcap->msr_work, pcap_msr_work);
433	440	spi_set_drvdata(spi, pcap);

drivers/mfd/fsl-imx25-tsadc.c+1−3

@@ -69,10 +69,8 @@ static int mx25_tsadc_setup_irq(struct platform_device *pdev, · 68 unmodified lines
69	69	int irq;
70	70
71	71	irq = platform_get_irq(pdev, 0);
72		− if (irq <= 0) {
73		− dev_err(dev, "Failed to get irq\n");
	72	+ if (irq <= 0)
74	73	return irq;
75		− }
76	74
77	75	tsadc->domain = irq_domain_add_simple(np, 2, 0, &mx25_tsadc_domain_ops,
78	76	tsadc);

drivers/mfd/htc-i2cpld.c+1−2

@@ -385,8 +385,7 @@ static void htcpld_unregister_chip_i2c( · 384 unmodified lines
385	385	htcpld = platform_get_drvdata(pdev);
386	386	chip = &htcpld->chip[chip_index];
387	387
388		− if (chip->client)
389		− i2c_unregister_device(chip->client);
	388	+ i2c_unregister_device(chip->client);
390	389	}
391	390
392	391	static int htcpld_register_chip_gpio(

drivers/mfd/intel-lpss-acpi.c+26−0

@@ -18,6 +18,10 @@ · 17 unmodified lines
18	18
19	19	#include "intel-lpss.h"
20	20
	21	+static const struct intel_lpss_platform_info spt_info = {
	22	+ .clk_rate = 120000000,
	23	+};
	24	+
21	25	static struct property_entry spt_i2c_properties[] = {
22	26	PROPERTY_ENTRY_U32("i2c-sda-hold-time-ns", 230),
23	27	{ },
@@ -28,6 +32,19 @@ static const struct intel_lpss_platform_info spt_i2c_info = { · 4 unmodified lines
28	32	.properties = spt_i2c_properties,
29	33	};
30	34
	35	+static struct property_entry uart_properties[] = {
	36	+ PROPERTY_ENTRY_U32("reg-io-width", 4),
	37	+ PROPERTY_ENTRY_U32("reg-shift", 2),
	38	+ PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
	39	+ { },
	40	+};
	41	+
	42	+static const struct intel_lpss_platform_info spt_uart_info = {
	43	+ .clk_rate = 120000000,
	44	+ .clk_con_id = "baudclk",
	45	+ .properties = uart_properties,
	46	+};
	47	+
31	48	static const struct intel_lpss_platform_info bxt_info = {
32	49	.clk_rate = 100000000,
33	50	};
@@ -58,8 +75,17 @@ static const struct intel_lpss_platform_info apl_i2c_info = { · 24 unmodified lines
58	75
59	76	static const struct acpi_device_id intel_lpss_acpi_ids[] = {
60	77	/* SPT */
	78	+ { "INT3440", (kernel_ulong_t)&spt_info },
	79	+ { "INT3441", (kernel_ulong_t)&spt_info },
	80	+ { "INT3442", (kernel_ulong_t)&spt_i2c_info },
	81	+ { "INT3443", (kernel_ulong_t)&spt_i2c_info },
	82	+ { "INT3444", (kernel_ulong_t)&spt_i2c_info },
	83	+ { "INT3445", (kernel_ulong_t)&spt_i2c_info },
61	84	{ "INT3446", (kernel_ulong_t)&spt_i2c_info },
62	85	{ "INT3447", (kernel_ulong_t)&spt_i2c_info },
	86	+ { "INT3448", (kernel_ulong_t)&spt_uart_info },
	87	+ { "INT3449", (kernel_ulong_t)&spt_uart_info },
	88	+ { "INT344A", (kernel_ulong_t)&spt_uart_info },
63	89	/* BXT */
64	90	{ "80860AAC", (kernel_ulong_t)&bxt_i2c_info },
65	91	{ "80860ABC", (kernel_ulong_t)&bxt_info },

drivers/mfd/intel-lpss-pci.c+25−0

@@ -35,6 +35,8 @@ static int intel_lpss_pci_probe(struct pci_dev *pdev, · 34 unmodified lines
35	35	info->mem = &pdev->resource[0];
36	36	info->irq = pdev->irq;
37	37
	38	+ pdev->d3cold_delay = 0;
	39	+
38	40	/* Probably it is enough to set this for iDMA capable devices only */
39	41	pci_set_master(pdev);
40	42	pci_try_set_mwi(pdev);
@@ -256,6 +258,29 @@ static const struct pci_device_id intel_lpss_pci_ids[] = { · 215 unmodified lines
256	258	{ PCI_VDEVICE(INTEL, 0x9dea), (kernel_ulong_t)&cnl_i2c_info },
257	259	{ PCI_VDEVICE(INTEL, 0x9deb), (kernel_ulong_t)&cnl_i2c_info },
258	260	{ PCI_VDEVICE(INTEL, 0x9dfb), (kernel_ulong_t)&spt_info },
	261	+ /* TGL-LP */
	262	+ { PCI_VDEVICE(INTEL, 0xa0a8), (kernel_ulong_t)&bxt_uart_info },
	263	+ { PCI_VDEVICE(INTEL, 0xa0a9), (kernel_ulong_t)&bxt_uart_info },
	264	+ { PCI_VDEVICE(INTEL, 0xa0aa), (kernel_ulong_t)&spt_info },
	265	+ { PCI_VDEVICE(INTEL, 0xa0ab), (kernel_ulong_t)&spt_info },
	266	+ { PCI_VDEVICE(INTEL, 0xa0c5), (kernel_ulong_t)&spt_i2c_info },
	267	+ { PCI_VDEVICE(INTEL, 0xa0c6), (kernel_ulong_t)&spt_i2c_info },
	268	+ { PCI_VDEVICE(INTEL, 0xa0c7), (kernel_ulong_t)&bxt_uart_info },
	269	+ { PCI_VDEVICE(INTEL, 0xa0d8), (kernel_ulong_t)&spt_i2c_info },
	270	+ { PCI_VDEVICE(INTEL, 0xa0d9), (kernel_ulong_t)&spt_i2c_info },
	271	+ { PCI_VDEVICE(INTEL, 0xa0da), (kernel_ulong_t)&bxt_uart_info },
	272	+ { PCI_VDEVICE(INTEL, 0xa0db), (kernel_ulong_t)&bxt_uart_info },
	273	+ { PCI_VDEVICE(INTEL, 0xa0dc), (kernel_ulong_t)&bxt_uart_info },
	274	+ { PCI_VDEVICE(INTEL, 0xa0dd), (kernel_ulong_t)&bxt_uart_info },
	275	+ { PCI_VDEVICE(INTEL, 0xa0de), (kernel_ulong_t)&spt_info },
	276	+ { PCI_VDEVICE(INTEL, 0xa0df), (kernel_ulong_t)&spt_info },
	277	+ { PCI_VDEVICE(INTEL, 0xa0e8), (kernel_ulong_t)&spt_i2c_info },
	278	+ { PCI_VDEVICE(INTEL, 0xa0e9), (kernel_ulong_t)&spt_i2c_info },
	279	+ { PCI_VDEVICE(INTEL, 0xa0ea), (kernel_ulong_t)&spt_i2c_info },
	280	+ { PCI_VDEVICE(INTEL, 0xa0eb), (kernel_ulong_t)&spt_i2c_info },
	281	+ { PCI_VDEVICE(INTEL, 0xa0fb), (kernel_ulong_t)&spt_info },
	282	+ { PCI_VDEVICE(INTEL, 0xa0fd), (kernel_ulong_t)&spt_info },
	283	+ { PCI_VDEVICE(INTEL, 0xa0fe), (kernel_ulong_t)&spt_info },
259	284	/* SPT-H */
260	285	{ PCI_VDEVICE(INTEL, 0xa127), (kernel_ulong_t)&spt_uart_info },
261	286	{ PCI_VDEVICE(INTEL, 0xa128), (kernel_ulong_t)&spt_uart_info },

drivers/mfd/intel-lpss.c+13−26

@@ -47,10 +47,10 @@ · 46 unmodified lines
47	47	#define LPSS_PRIV_IDLELTR 0x14
48	48
49	49	#define LPSS_PRIV_LTR_REQ BIT(15)
50		−#define LPSS_PRIV_LTR_SCALE_MASK 0xc00
51		−#define LPSS_PRIV_LTR_SCALE_1US 0x800
52		−#define LPSS_PRIV_LTR_SCALE_32US 0xc00
53		−#define LPSS_PRIV_LTR_VALUE_MASK 0x3ff
	50	+#define LPSS_PRIV_LTR_SCALE_MASK GENMASK(11, 10)
	51	+#define LPSS_PRIV_LTR_SCALE_1US (2 << 10)
	52	+#define LPSS_PRIV_LTR_SCALE_32US (3 << 10)
	53	+#define LPSS_PRIV_LTR_VALUE_MASK GENMASK(9, 0)
54	54
55	55	#define LPSS_PRIV_SSP_REG 0x20
56	56	#define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0)
@@ -59,8 +59,8 @@ · 2 unmodified lines
59	59
60	60	#define LPSS_PRIV_CAPS 0xfc
61	61	#define LPSS_PRIV_CAPS_NO_IDMA BIT(8)
	62	+#define LPSS_PRIV_CAPS_TYPE_MASK GENMASK(7, 4)
62	63	#define LPSS_PRIV_CAPS_TYPE_SHIFT 4
63		−#define LPSS_PRIV_CAPS_TYPE_MASK (0xf << LPSS_PRIV_CAPS_TYPE_SHIFT)
64	64
65	65	/* This matches the type field in CAPS register */
66	66	enum intel_lpss_dev_type {
@@ -128,17 +128,6 @@ static const struct mfd_cell intel_lpss_spi_cell = { · 61 unmodified lines
128	128	static DEFINE_IDA(intel_lpss_devid_ida);
129	129	static struct dentry *intel_lpss_debugfs;
130	130
131		−static int intel_lpss_request_dma_module(const char *name)
132		−{
133		− static bool intel_lpss_dma_requested;
134		−
135		− if (intel_lpss_dma_requested)
136		− return 0;
137		−
138		− intel_lpss_dma_requested = true;
139		− return request_module("%s", name);
140		−}
141		−
142	131	static void intel_lpss_cache_ltr(struct intel_lpss *lpss)
143	132	{
144	133	lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
@@ -429,16 +418,6 @@ int intel_lpss_probe(struct device *dev, · 284 unmodified lines
429	418	dev_warn(dev, "Failed to create debugfs entries\n");
430	419
431	420	if (intel_lpss_has_idma(lpss)) {
432		− /*
433		− * Ensure the DMA driver is loaded before the host
434		− * controller device appears, so that the host controller
435		− * driver can request its DMA channels as early as
436		− * possible.
437		− *
438		− * If the DMA module is not there that's OK as well.
439		− */
440		− intel_lpss_request_dma_module(LPSS_IDMA64_DRIVER_NAME);
441		−
442	421	ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,
443	422	1, info->mem, info->irq, NULL);
444	423	if (ret)
@@ -554,3 +533,11 @@ MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>"); · 109 unmodified lines
554	533	MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
555	534	MODULE_DESCRIPTION("Intel LPSS core driver");
556	535	MODULE_LICENSE("GPL v2");
	536	+/*
	537	+ * Ensure the DMA driver is loaded before the host controller device appears,
	538	+ * so that the host controller driver can request its DMA channels as early
	539	+ * as possible.
	540	+ *
	541	+ * If the DMA module is not there that's OK as well.
	542	+ */
	543	+MODULE_SOFTDEP("pre: platform:" LPSS_IDMA64_DRIVER_NAME);

drivers/mfd/intel_soc_pmic_bxtwc.c+1−3

@@ -450,10 +450,8 @@ static int bxtwc_probe(struct platform_device *pdev) · 449 unmodified lines
450	450	return -ENOMEM;
451	451
452	452	ret = platform_get_irq(pdev, 0);
453		− if (ret < 0) {
454		− dev_err(&pdev->dev, "Invalid IRQ\n");
	453	+ if (ret < 0)
455	454	return ret;
456		− }
457	455	pmic->irq = ret;
458	456
459	457	dev_set_drvdata(&pdev->dev, pmic);

drivers/mfd/intel_soc_pmic_mrfld.c+157−0

@@ -0,0 +1,157 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+/*
	3	+ * Device access for Basin Cove PMIC
	4	+ *
	5	+ * Copyright (c) 2019, Intel Corporation.
	6	+ * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
	7	+ */
	8	+
	9	+#include <linux/acpi.h>
	10	+#include <linux/interrupt.h>
	11	+#include <linux/mfd/core.h>
	12	+#include <linux/mfd/intel_soc_pmic.h>
	13	+#include <linux/mfd/intel_soc_pmic_mrfld.h>
	14	+#include <linux/module.h>
	15	+#include <linux/platform_device.h>
	16	+#include <linux/regmap.h>
	17	+
	18	+#include <asm/intel_scu_ipc.h>
	19	+
	20	+/*
	21	+ * Level 2 IRQs
	22	+ *
	23	+ * Firmware on the systems with Basin Cove PMIC services Level 1 IRQs
	24	+ * without an assistance. Thus, each of the Level 1 IRQ is represented
	25	+ * as a separate RTE in IOAPIC.
	26	+ */
	27	+static struct resource irq_level2_resources[] = {
	28	+ DEFINE_RES_IRQ(0), /* power button */
	29	+ DEFINE_RES_IRQ(0), /* TMU */
	30	+ DEFINE_RES_IRQ(0), /* thermal */
	31	+ DEFINE_RES_IRQ(0), /* BCU */
	32	+ DEFINE_RES_IRQ(0), /* ADC */
	33	+ DEFINE_RES_IRQ(0), /* charger */
	34	+ DEFINE_RES_IRQ(0), /* GPIO */
	35	+};
	36	+
	37	+static const struct mfd_cell bcove_dev[] = {
	38	+ {
	39	+ .name = "mrfld_bcove_pwrbtn",
	40	+ .num_resources = 1,
	41	+ .resources = &irq_level2_resources[0],
	42	+ }, {
	43	+ .name = "mrfld_bcove_tmu",
	44	+ .num_resources = 1,
	45	+ .resources = &irq_level2_resources[1],
	46	+ }, {
	47	+ .name = "mrfld_bcove_thermal",
	48	+ .num_resources = 1,
	49	+ .resources = &irq_level2_resources[2],
	50	+ }, {
	51	+ .name = "mrfld_bcove_bcu",
	52	+ .num_resources = 1,
	53	+ .resources = &irq_level2_resources[3],
	54	+ }, {
	55	+ .name = "mrfld_bcove_adc",
	56	+ .num_resources = 1,
	57	+ .resources = &irq_level2_resources[4],
	58	+ }, {
	59	+ .name = "mrfld_bcove_charger",
	60	+ .num_resources = 1,
	61	+ .resources = &irq_level2_resources[5],
	62	+ }, {
	63	+ .name = "mrfld_bcove_pwrsrc",
	64	+ .num_resources = 1,
	65	+ .resources = &irq_level2_resources[5],
	66	+ }, {
	67	+ .name = "mrfld_bcove_gpio",
	68	+ .num_resources = 1,
	69	+ .resources = &irq_level2_resources[6],
	70	+ },
	71	+ { .name = "mrfld_bcove_region", },
	72	+};
	73	+
	74	+static int bcove_ipc_byte_reg_read(void *context, unsigned int reg,
	75	+ unsigned int *val)
	76	+{
	77	+ u8 ipc_out;
	78	+ int ret;
	79	+
	80	+ ret = intel_scu_ipc_ioread8(reg, &ipc_out);
	81	+ if (ret)
	82	+ return ret;
	83	+
	84	+ *val = ipc_out;
	85	+ return 0;
	86	+}
	87	+
	88	+static int bcove_ipc_byte_reg_write(void *context, unsigned int reg,
	89	+ unsigned int val)
	90	+{
	91	+ u8 ipc_in = val;
	92	+ int ret;
	93	+
	94	+ ret = intel_scu_ipc_iowrite8(reg, ipc_in);
	95	+ if (ret)
	96	+ return ret;
	97	+
	98	+ return 0;
	99	+}
	100	+
	101	+static const struct regmap_config bcove_regmap_config = {
	102	+ .reg_bits = 16,
	103	+ .val_bits = 8,
	104	+ .max_register = 0xff,
	105	+ .reg_write = bcove_ipc_byte_reg_write,
	106	+ .reg_read = bcove_ipc_byte_reg_read,
	107	+};
	108	+
	109	+static int bcove_probe(struct platform_device *pdev)
	110	+{
	111	+ struct device *dev = &pdev->dev;
	112	+ struct intel_soc_pmic *pmic;
	113	+ unsigned int i;
	114	+ int ret;
	115	+
	116	+ pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
	117	+ if (!pmic)
	118	+ return -ENOMEM;
	119	+
	120	+ platform_set_drvdata(pdev, pmic);
	121	+ pmic->dev = &pdev->dev;
	122	+
	123	+ pmic->regmap = devm_regmap_init(dev, NULL, pmic, &bcove_regmap_config);
	124	+ if (IS_ERR(pmic->regmap))
	125	+ return PTR_ERR(pmic->regmap);
	126	+
	127	+ for (i = 0; i < ARRAY_SIZE(irq_level2_resources); i++) {
	128	+ ret = platform_get_irq(pdev, i);
	129	+ if (ret < 0)
	130	+ return ret;
	131	+
	132	+ irq_level2_resources[i].start = ret;
	133	+ irq_level2_resources[i].end = ret;
	134	+ }
	135	+
	136	+ return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
	137	+ bcove_dev, ARRAY_SIZE(bcove_dev),
	138	+ NULL, 0, NULL);
	139	+}
	140	+
	141	+static const struct acpi_device_id bcove_acpi_ids[] = {
	142	+ { "INTC100E" },
	143	+ {}
	144	+};
	145	+MODULE_DEVICE_TABLE(acpi, bcove_acpi_ids);
	146	+
	147	+static struct platform_driver bcove_driver = {
	148	+ .driver = {
	149	+ .name = "intel_soc_pmic_mrfld",
	150	+ .acpi_match_table = bcove_acpi_ids,
	151	+ },
	152	+ .probe = bcove_probe,
	153	+};
	154	+module_platform_driver(bcove_driver);
	155	+
	156	+MODULE_DESCRIPTION("IPC driver for Intel SoC Basin Cove PMIC");
	157	+MODULE_LICENSE("GPL v2");

drivers/mfd/jz4740-adc.c+0−324

@@ -1,324 +0,0 @@
1		−// SPDX-License-Identifier: GPL-2.0-or-later
2		−/*
3		− * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
4		− * JZ4740 SoC ADC driver
5		− *
6		− * This driver synchronizes access to the JZ4740 ADC core between the
7		− * JZ4740 battery and hwmon drivers.
8		− */
9		−
10		−#include <linux/err.h>
11		−#include <linux/io.h>
12		−#include <linux/irq.h>
13		−#include <linux/interrupt.h>
14		−#include <linux/kernel.h>
15		−#include <linux/module.h>
16		−#include <linux/platform_device.h>
17		−#include <linux/slab.h>
18		−#include <linux/spinlock.h>
19		−
20		−#include <linux/clk.h>
21		−#include <linux/mfd/core.h>
22		−
23		−#include <linux/jz4740-adc.h>
24		−
25		−
26		−#define JZ_REG_ADC_ENABLE 0x00
27		−#define JZ_REG_ADC_CFG 0x04
28		−#define JZ_REG_ADC_CTRL 0x08
29		−#define JZ_REG_ADC_STATUS 0x0c
30		−
31		−#define JZ_REG_ADC_TOUCHSCREEN_BASE 0x10
32		−#define JZ_REG_ADC_BATTERY_BASE 0x1c
33		−#define JZ_REG_ADC_HWMON_BASE 0x20
34		−
35		−#define JZ_ADC_ENABLE_TOUCH BIT(2)
36		−#define JZ_ADC_ENABLE_BATTERY BIT(1)
37		−#define JZ_ADC_ENABLE_ADCIN BIT(0)
38		−
39		−enum {
40		− JZ_ADC_IRQ_ADCIN = 0,
41		− JZ_ADC_IRQ_BATTERY,
42		− JZ_ADC_IRQ_TOUCH,
43		− JZ_ADC_IRQ_PENUP,
44		− JZ_ADC_IRQ_PENDOWN,
45		−};
46		−
47		−struct jz4740_adc {
48		− struct resource *mem;
49		− void __iomem *base;
50		−
51		− int irq;
52		− struct irq_chip_generic *gc;
53		−
54		− struct clk *clk;
55		− atomic_t clk_ref;
56		−
57		− spinlock_t lock;
58		−};
59		−
60		−static void jz4740_adc_irq_demux(struct irq_desc *desc)
61		−{
62		− struct irq_chip_generic *gc = irq_desc_get_handler_data(desc);
63		− uint8_t status;
64		− unsigned int i;
65		−
66		− status = readb(gc->reg_base + JZ_REG_ADC_STATUS);
67		−
68		− for (i = 0; i < 5; ++i) {
69		− if (status & BIT(i))
70		− generic_handle_irq(gc->irq_base + i);
71		− }
72		−}
73		−
74		−
75		−/* Refcounting for the ADC clock is done in here instead of in the clock
76		− * framework, because it is the only clock which is shared between multiple
77		− * devices and thus is the only clock which needs refcounting */
78		−static inline void jz4740_adc_clk_enable(struct jz4740_adc *adc)
79		−{
80		− if (atomic_inc_return(&adc->clk_ref) == 1)
81		− clk_prepare_enable(adc->clk);
82		−}
83		−
84		−static inline void jz4740_adc_clk_disable(struct jz4740_adc *adc)
85		−{
86		− if (atomic_dec_return(&adc->clk_ref) == 0)
87		− clk_disable_unprepare(adc->clk);
88		−}
89		−
90		−static inline void jz4740_adc_set_enabled(struct jz4740_adc *adc, int engine,
91		− bool enabled)
92		−{
93		− unsigned long flags;
94		− uint8_t val;
95		−
96		− spin_lock_irqsave(&adc->lock, flags);
97		−
98		− val = readb(adc->base + JZ_REG_ADC_ENABLE);
99		− if (enabled)
100		− val \|= BIT(engine);
101		− else
102		− val &= ~BIT(engine);
103		− writeb(val, adc->base + JZ_REG_ADC_ENABLE);
104		−
105		− spin_unlock_irqrestore(&adc->lock, flags);
106		−}
107		−
108		−static int jz4740_adc_cell_enable(struct platform_device *pdev)
109		−{
110		− struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent);
111		−
112		− jz4740_adc_clk_enable(adc);
113		− jz4740_adc_set_enabled(adc, pdev->id, true);
114		−
115		− return 0;
116		−}
117		−
118		−static int jz4740_adc_cell_disable(struct platform_device *pdev)
119		−{
120		− struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent);
121		−
122		− jz4740_adc_set_enabled(adc, pdev->id, false);
123		− jz4740_adc_clk_disable(adc);
124		−
125		− return 0;
126		−}
127		−
128		−int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val)
129		−{
130		− struct jz4740_adc *adc = dev_get_drvdata(dev);
131		− unsigned long flags;
132		− uint32_t cfg;
133		−
134		− if (!adc)
135		− return -ENODEV;
136		−
137		− spin_lock_irqsave(&adc->lock, flags);
138		−
139		− cfg = readl(adc->base + JZ_REG_ADC_CFG);
140		−
141		− cfg &= ~mask;
142		− cfg \|= val;
143		−
144		− writel(cfg, adc->base + JZ_REG_ADC_CFG);
145		−
146		− spin_unlock_irqrestore(&adc->lock, flags);
147		−
148		− return 0;
149		−}
150		−EXPORT_SYMBOL_GPL(jz4740_adc_set_config);
151		−
152		−static struct resource jz4740_hwmon_resources[] = {
153		− {
154		− .start = JZ_ADC_IRQ_ADCIN,
155		− .flags = IORESOURCE_IRQ,
156		− },
157		− {
158		− .start = JZ_REG_ADC_HWMON_BASE,
159		− .end = JZ_REG_ADC_HWMON_BASE + 3,
160		− .flags = IORESOURCE_MEM,
161		− },
162		−};
163		−
164		−static struct resource jz4740_battery_resources[] = {
165		− {
166		− .start = JZ_ADC_IRQ_BATTERY,
167		− .flags = IORESOURCE_IRQ,
168		− },
169		− {
170		− .start = JZ_REG_ADC_BATTERY_BASE,
171		− .end = JZ_REG_ADC_BATTERY_BASE + 3,
172		− .flags = IORESOURCE_MEM,
173		− },
174		−};
175		−
176		−static const struct mfd_cell jz4740_adc_cells[] = {
177		− {
178		− .id = 0,
179		− .name = "jz4740-hwmon",
180		− .num_resources = ARRAY_SIZE(jz4740_hwmon_resources),
181		− .resources = jz4740_hwmon_resources,
182		−
183		− .enable = jz4740_adc_cell_enable,
184		− .disable = jz4740_adc_cell_disable,
185		− },
186		− {
187		− .id = 1,
188		− .name = "jz4740-battery",
189		− .num_resources = ARRAY_SIZE(jz4740_battery_resources),
190		− .resources = jz4740_battery_resources,
191		−
192		− .enable = jz4740_adc_cell_enable,
193		− .disable = jz4740_adc_cell_disable,
194		− },
195		−};
196		−
197		−static int jz4740_adc_probe(struct platform_device *pdev)
198		−{
199		− struct irq_chip_generic *gc;
200		− struct irq_chip_type *ct;
201		− struct jz4740_adc *adc;
202		− struct resource *mem_base;
203		− int ret;
204		− int irq_base;
205		−
206		− adc = devm_kzalloc(&pdev->dev, sizeof(*adc), GFP_KERNEL);
207		− if (!adc)
208		− return -ENOMEM;
209		−
210		− adc->irq = platform_get_irq(pdev, 0);
211		− if (adc->irq < 0) {
212		− ret = adc->irq;
213		− dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
214		− return ret;
215		− }
216		−
217		− irq_base = platform_get_irq(pdev, 1);
218		− if (irq_base < 0) {
219		− dev_err(&pdev->dev, "Failed to get irq base: %d\n", irq_base);
220		− return irq_base;
221		− }
222		−
223		− mem_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
224		− if (!mem_base) {
225		− dev_err(&pdev->dev, "Failed to get platform mmio resource\n");
226		− return -ENOENT;
227		− }
228		−
229		− /* Only request the shared registers for the MFD driver */
230		− adc->mem = request_mem_region(mem_base->start, JZ_REG_ADC_STATUS,
231		− pdev->name);
232		− if (!adc->mem) {
233		− dev_err(&pdev->dev, "Failed to request mmio memory region\n");
234		− return -EBUSY;
235		− }
236		−
237		− adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem));
238		− if (!adc->base) {
239		− ret = -EBUSY;
240		− dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
241		− goto err_release_mem_region;
242		− }
243		−
244		− adc->clk = clk_get(&pdev->dev, "adc");
245		− if (IS_ERR(adc->clk)) {
246		− ret = PTR_ERR(adc->clk);
247		− dev_err(&pdev->dev, "Failed to get clock: %d\n", ret);
248		− goto err_iounmap;
249		− }
250		−
251		− spin_lock_init(&adc->lock);
252		− atomic_set(&adc->clk_ref, 0);
253		−
254		− platform_set_drvdata(pdev, adc);
255		−
256		− gc = irq_alloc_generic_chip("INTC", 1, irq_base, adc->base,
257		− handle_level_irq);
258		−
259		− ct = gc->chip_types;
260		− ct->regs.mask = JZ_REG_ADC_CTRL;
261		− ct->regs.ack = JZ_REG_ADC_STATUS;
262		− ct->chip.irq_mask = irq_gc_mask_set_bit;
263		− ct->chip.irq_unmask = irq_gc_mask_clr_bit;
264		− ct->chip.irq_ack = irq_gc_ack_set_bit;
265		−
266		− irq_setup_generic_chip(gc, IRQ_MSK(5), IRQ_GC_INIT_MASK_CACHE, 0,
267		− IRQ_NOPROBE \| IRQ_LEVEL);
268		−
269		− adc->gc = gc;
270		−
271		− irq_set_chained_handler_and_data(adc->irq, jz4740_adc_irq_demux, gc);
272		−
273		− writeb(0x00, adc->base + JZ_REG_ADC_ENABLE);
274		− writeb(0xff, adc->base + JZ_REG_ADC_CTRL);
275		−
276		− ret = mfd_add_devices(&pdev->dev, 0, jz4740_adc_cells,
277		− ARRAY_SIZE(jz4740_adc_cells), mem_base,
278		− irq_base, NULL);
279		− if (ret < 0)
280		− goto err_clk_put;
281		−
282		− return 0;
283		−
284		−err_clk_put:
285		− clk_put(adc->clk);
286		−err_iounmap:
287		− iounmap(adc->base);
288		−err_release_mem_region:
289		− release_mem_region(adc->mem->start, resource_size(adc->mem));
290		− return ret;
291		−}
292		−
293		−static int jz4740_adc_remove(struct platform_device *pdev)
294		−{
295		− struct jz4740_adc *adc = platform_get_drvdata(pdev);
296		−
297		− mfd_remove_devices(&pdev->dev);
298		−
299		− irq_remove_generic_chip(adc->gc, IRQ_MSK(5), IRQ_NOPROBE \| IRQ_LEVEL, 0);
300		− kfree(adc->gc);
301		− irq_set_chained_handler_and_data(adc->irq, NULL, NULL);
302		−
303		− iounmap(adc->base);
304		− release_mem_region(adc->mem->start, resource_size(adc->mem));
305		−
306		− clk_put(adc->clk);
307		−
308		− return 0;
309		−}
310		−
311		−static struct platform_driver jz4740_adc_driver = {
312		− .probe = jz4740_adc_probe,
313		− .remove = jz4740_adc_remove,
314		− .driver = {
315		− .name = "jz4740-adc",
316		− },
317		−};
318		−
319		−module_platform_driver(jz4740_adc_driver);
320		−
321		−MODULE_DESCRIPTION("JZ4740 SoC ADC driver");
322		−MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
323		−MODULE_LICENSE("GPL");
324		−MODULE_ALIAS("platform:jz4740-adc");

drivers/mfd/max14577.c+3−3

@@ -297,11 +297,11 @@ static int max77836_init(struct max14577 *max14577) · 296 unmodified lines
297	297	int ret;
298	298	u8 intsrc_mask;
299	299
300		− max14577->i2c_pmic = i2c_new_dummy(max14577->i2c->adapter,
	300	+ max14577->i2c_pmic = i2c_new_dummy_device(max14577->i2c->adapter,
301	301	I2C_ADDR_PMIC);
302		− if (!max14577->i2c_pmic) {
	302	+ if (IS_ERR(max14577->i2c_pmic)) {
303	303	dev_err(max14577->dev, "Failed to register PMIC I2C device\n");
304		− return -ENODEV;
	304	+ return PTR_ERR(max14577->i2c_pmic);
305	305	}
306	306	i2c_set_clientdata(max14577->i2c_pmic, max14577);
307	307

drivers/mfd/max77620.c+3−1

@@ -416,8 +416,10 @@ static int max77620_initialise_fps(struct max77620_chip *chip) · 415 unmodified lines
416	416
417	417	for_each_child_of_node(fps_np, fps_child) {
418	418	ret = max77620_config_fps(chip, fps_child);
419		− if (ret < 0)
	419	+ if (ret < 0) {
	420	+ of_node_put(fps_child);
420	421	return ret;
	422	+ }
421	423	}
422	424
423	425	config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0;

drivers/mfd/max77693.c+6−6

@@ -183,17 +183,17 @@ static int max77693_i2c_probe(struct i2c_client *i2c, · 182 unmodified lines
183	183	} else
184	184	dev_info(max77693->dev, "device ID: 0x%x\n", reg_data);
185	185
186		− max77693->i2c_muic = i2c_new_dummy(i2c->adapter, I2C_ADDR_MUIC);
187		− if (!max77693->i2c_muic) {
	186	+ max77693->i2c_muic = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_MUIC);
	187	+ if (IS_ERR(max77693->i2c_muic)) {
188	188	dev_err(max77693->dev, "Failed to allocate I2C device for MUIC\n");
189		− return -ENODEV;
	189	+ return PTR_ERR(max77693->i2c_muic);
190	190	}
191	191	i2c_set_clientdata(max77693->i2c_muic, max77693);
192	192
193		− max77693->i2c_haptic = i2c_new_dummy(i2c->adapter, I2C_ADDR_HAPTIC);
194		− if (!max77693->i2c_haptic) {
	193	+ max77693->i2c_haptic = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_HAPTIC);
	194	+ if (IS_ERR(max77693->i2c_haptic)) {
195	195	dev_err(max77693->dev, "Failed to allocate I2C device for Haptic\n");
196		− ret = -ENODEV;
	196	+ ret = PTR_ERR(max77693->i2c_haptic);
197	197	goto err_i2c_haptic;
198	198	}
199	199	i2c_set_clientdata(max77693->i2c_haptic, max77693);

drivers/mfd/max77843.c+3−3

@@ -70,11 +70,11 @@ static int max77843_chg_init(struct max77693_dev *max77843) · 69 unmodified lines
70	70	{
71	71	int ret;
72	72
73		− max77843->i2c_chg = i2c_new_dummy(max77843->i2c->adapter, I2C_ADDR_CHG);
74		− if (!max77843->i2c_chg) {
	73	+ max77843->i2c_chg = i2c_new_dummy_device(max77843->i2c->adapter, I2C_ADDR_CHG);
	74	+ if (IS_ERR(max77843->i2c_chg)) {
75	75	dev_err(&max77843->i2c->dev,
76	76	"Cannot allocate I2C device for Charger\n");
77		− return -ENODEV;
	77	+ return PTR_ERR(max77843->i2c_chg);
78	78	}
79	79	i2c_set_clientdata(max77843->i2c_chg, max77843);
80	80

drivers/mfd/max8907.c+3−3

@@ -214,9 +214,9 @@ static int max8907_i2c_probe(struct i2c_client *i2c, · 213 unmodified lines
214	214	goto err_regmap_gen;
215	215	}
216	216
217		− max8907->i2c_rtc = i2c_new_dummy(i2c->adapter, MAX8907_RTC_I2C_ADDR);
218		− if (!max8907->i2c_rtc) {
219		− ret = -ENOMEM;
	217	+ max8907->i2c_rtc = i2c_new_dummy_device(i2c->adapter, MAX8907_RTC_I2C_ADDR);
	218	+ if (IS_ERR(max8907->i2c_rtc)) {
	219	+ ret = PTR_ERR(max8907->i2c_rtc);
220	220	goto err_dummy_rtc;
221	221	}
222	222	i2c_set_clientdata(max8907->i2c_rtc, max8907);

drivers/mfd/max8925-i2c.c+6−6

@@ -176,18 +176,18 @@ static int max8925_probe(struct i2c_client *client, · 175 unmodified lines
176	176	dev_set_drvdata(chip->dev, chip);
177	177	mutex_init(&chip->io_lock);
178	178
179		− chip->rtc = i2c_new_dummy(chip->i2c->adapter, RTC_I2C_ADDR);
180		− if (!chip->rtc) {
	179	+ chip->rtc = i2c_new_dummy_device(chip->i2c->adapter, RTC_I2C_ADDR);
	180	+ if (IS_ERR(chip->rtc)) {
181	181	dev_err(chip->dev, "Failed to allocate I2C device for RTC\n");
182		− return -ENODEV;
	182	+ return PTR_ERR(chip->rtc);
183	183	}
184	184	i2c_set_clientdata(chip->rtc, chip);
185	185
186		− chip->adc = i2c_new_dummy(chip->i2c->adapter, ADC_I2C_ADDR);
187		− if (!chip->adc) {
	186	+ chip->adc = i2c_new_dummy_device(chip->i2c->adapter, ADC_I2C_ADDR);
	187	+ if (IS_ERR(chip->adc)) {
188	188	dev_err(chip->dev, "Failed to allocate I2C device for ADC\n");
189	189	i2c_unregister_device(chip->rtc);
190		− return -ENODEV;
	190	+ return PTR_ERR(chip->adc);
191	191	}
192	192	i2c_set_clientdata(chip->adc, chip);
193	193

drivers/mfd/max8997.c+9−9

@@ -185,25 +185,25 @@ static int max8997_i2c_probe(struct i2c_client *i2c, · 184 unmodified lines
185	185
186	186	mutex_init(&max8997->iolock);
187	187
188		− max8997->rtc = i2c_new_dummy(i2c->adapter, I2C_ADDR_RTC);
189		− if (!max8997->rtc) {
	188	+ max8997->rtc = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_RTC);
	189	+ if (IS_ERR(max8997->rtc)) {
190	190	dev_err(max8997->dev, "Failed to allocate I2C device for RTC\n");
191		− return -ENODEV;
	191	+ return PTR_ERR(max8997->rtc);
192	192	}
193	193	i2c_set_clientdata(max8997->rtc, max8997);
194	194
195		− max8997->haptic = i2c_new_dummy(i2c->adapter, I2C_ADDR_HAPTIC);
196		− if (!max8997->haptic) {
	195	+ max8997->haptic = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_HAPTIC);
	196	+ if (IS_ERR(max8997->haptic)) {
197	197	dev_err(max8997->dev, "Failed to allocate I2C device for Haptic\n");
198		− ret = -ENODEV;
	198	+ ret = PTR_ERR(max8997->haptic);
199	199	goto err_i2c_haptic;
200	200	}
201	201	i2c_set_clientdata(max8997->haptic, max8997);
202	202
203		− max8997->muic = i2c_new_dummy(i2c->adapter, I2C_ADDR_MUIC);
204		− if (!max8997->muic) {
	203	+ max8997->muic = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_MUIC);
	204	+ if (IS_ERR(max8997->muic)) {
205	205	dev_err(max8997->dev, "Failed to allocate I2C device for MUIC\n");
206		− ret = -ENODEV;
	206	+ ret = PTR_ERR(max8997->muic);
207	207	goto err_i2c_muic;
208	208	}
209	209	i2c_set_clientdata(max8997->muic, max8997);

drivers/mfd/max8998.c+3−3

@@ -195,10 +195,10 @@ static int max8998_i2c_probe(struct i2c_client *i2c, · 194 unmodified lines
195	195	}
196	196	mutex_init(&max8998->iolock);
197	197
198		− max8998->rtc = i2c_new_dummy(i2c->adapter, RTC_I2C_ADDR);
199		− if (!max8998->rtc) {
	198	+ max8998->rtc = i2c_new_dummy_device(i2c->adapter, RTC_I2C_ADDR);
	199	+ if (IS_ERR(max8998->rtc)) {
200	200	dev_err(&i2c->dev, "Failed to allocate I2C device for RTC\n");
201		− return -ENODEV;
	201	+ return PTR_ERR(max8998->rtc);
202	202	}
203	203	i2c_set_clientdata(max8998->rtc, max8998);
204	204

drivers/mfd/mt6397-core.c+32−160

@@ -5,34 +5,34 @@ · 4 unmodified lines
5	5	*/
6	6
7	7	#include <linux/interrupt.h>
	8	+#include <linux/ioport.h>
8	9	#include <linux/module.h>
9	10	#include <linux/of_device.h>
10	11	#include <linux/of_irq.h>
11	12	#include <linux/regmap.h>
12	13	#include <linux/mfd/core.h>
13		−#include <linux/mfd/mt6397/core.h>
14	14	#include <linux/mfd/mt6323/core.h>
15		−#include <linux/mfd/mt6397/registers.h>
	15	+#include <linux/mfd/mt6397/core.h>
16	16	#include <linux/mfd/mt6323/registers.h>
	17	+#include <linux/mfd/mt6397/registers.h>
	18	+
	19	+#define MT6323_RTC_BASE 0x8000
	20	+#define MT6323_RTC_SIZE 0x40
17	21
18	22	#define MT6397_RTC_BASE 0xe000
19	23	#define MT6397_RTC_SIZE 0x3e
20	24
21		−#define MT6323_CID_CODE 0x23
22		−#define MT6391_CID_CODE 0x91
23		−#define MT6397_CID_CODE 0x97
	25	+#define MT6323_PWRC_BASE 0x8000
	26	+#define MT6323_PWRC_SIZE 0x40
	27	+
	28	+static const struct resource mt6323_rtc_resources[] = {
	29	+ DEFINE_RES_MEM(MT6323_RTC_BASE, MT6323_RTC_SIZE),
	30	+ DEFINE_RES_IRQ(MT6323_IRQ_STATUS_RTC),
	31	+};
24	32
25	33	static const struct resource mt6397_rtc_resources[] = {
26		− {
27		− .start = MT6397_RTC_BASE,
28		− .end = MT6397_RTC_BASE + MT6397_RTC_SIZE,
29		− .flags = IORESOURCE_MEM,
30		− },
31		− {
32		− .start = MT6397_IRQ_RTC,
33		− .end = MT6397_IRQ_RTC,
34		− .flags = IORESOURCE_IRQ,
35		− },
	34	+ DEFINE_RES_MEM(MT6397_RTC_BASE, MT6397_RTC_SIZE),
	35	+ DEFINE_RES_IRQ(MT6397_IRQ_RTC),
36	36	};
37	37
38	38	static const struct resource mt6323_keys_resources[] = {
@@ -45,8 +45,17 @@ static const struct resource mt6397_keys_resources[] = { · 6 unmodified lines
45	45	DEFINE_RES_IRQ(MT6397_IRQ_HOMEKEY),
46	46	};
47	47
	48	+static const struct resource mt6323_pwrc_resources[] = {
	49	+ DEFINE_RES_MEM(MT6323_PWRC_BASE, MT6323_PWRC_SIZE),
	50	+};
	51	+
48	52	static const struct mfd_cell mt6323_devs[] = {
49	53	{
	54	+ .name = "mt6323-rtc",
	55	+ .num_resources = ARRAY_SIZE(mt6323_rtc_resources),
	56	+ .resources = mt6323_rtc_resources,
	57	+ .of_compatible = "mediatek,mt6323-rtc",
	58	+ }, {
50	59	.name = "mt6323-regulator",
51	60	.of_compatible = "mediatek,mt6323-regulator"
52	61	}, {
@@ -57,6 +66,11 @@ static const struct mfd_cell mt6323_devs[] = { · 4 unmodified lines
57	66	.num_resources = ARRAY_SIZE(mt6323_keys_resources),
58	67	.resources = mt6323_keys_resources,
59	68	.of_compatible = "mediatek,mt6323-keys"
	69	+ }, {
	70	+ .name = "mt6323-pwrc",
	71	+ .num_resources = ARRAY_SIZE(mt6323_pwrc_resources),
	72	+ .resources = mt6323_pwrc_resources,
	73	+ .of_compatible = "mediatek,mt6323-pwrc"
60	74	},
61	75	};
62	76
@@ -86,148 +100,6 @@ static const struct mfd_cell mt6397_devs[] = { · 23 unmodified lines
86	100	}
87	101	};
88	102
89		−static void mt6397_irq_lock(struct irq_data *data)
90		−{
91		− struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
92		−
93		− mutex_lock(&mt6397->irqlock);
94		−}
95		−
96		−static void mt6397_irq_sync_unlock(struct irq_data *data)
97		−{
98		− struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
99		−
100		− regmap_write(mt6397->regmap, mt6397->int_con[0],
101		− mt6397->irq_masks_cur[0]);
102		− regmap_write(mt6397->regmap, mt6397->int_con[1],
103		− mt6397->irq_masks_cur[1]);
104		−
105		− mutex_unlock(&mt6397->irqlock);
106		−}
107		−
108		−static void mt6397_irq_disable(struct irq_data *data)
109		−{
110		− struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
111		− int shift = data->hwirq & 0xf;
112		− int reg = data->hwirq >> 4;
113		−
114		− mt6397->irq_masks_cur[reg] &= ~BIT(shift);
115		−}
116		−
117		−static void mt6397_irq_enable(struct irq_data *data)
118		−{
119		− struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
120		− int shift = data->hwirq & 0xf;
121		− int reg = data->hwirq >> 4;
122		−
123		− mt6397->irq_masks_cur[reg] \|= BIT(shift);
124		−}
125		−
126		−#ifdef CONFIG_PM_SLEEP
127		−static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
128		−{
129		− struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
130		− int shift = irq_data->hwirq & 0xf;
131		− int reg = irq_data->hwirq >> 4;
132		−
133		− if (on)
134		− mt6397->wake_mask[reg] \|= BIT(shift);
135		− else
136		− mt6397->wake_mask[reg] &= ~BIT(shift);
137		−
138		− return 0;
139		−}
140		−#else
141		−#define mt6397_irq_set_wake NULL
142		−#endif
143		−
144		−static struct irq_chip mt6397_irq_chip = {
145		− .name = "mt6397-irq",
146		− .irq_bus_lock = mt6397_irq_lock,
147		− .irq_bus_sync_unlock = mt6397_irq_sync_unlock,
148		− .irq_enable = mt6397_irq_enable,
149		− .irq_disable = mt6397_irq_disable,
150		− .irq_set_wake = mt6397_irq_set_wake,
151		−};
152		−
153		−static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
154		− int irqbase)
155		−{
156		− unsigned int status;
157		− int i, irq, ret;
158		−
159		− ret = regmap_read(mt6397->regmap, reg, &status);
160		− if (ret) {
161		− dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
162		− return;
163		− }
164		−
165		− for (i = 0; i < 16; i++) {
166		− if (status & BIT(i)) {
167		− irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
168		− if (irq)
169		− handle_nested_irq(irq);
170		− }
171		− }
172		−
173		− regmap_write(mt6397->regmap, reg, status);
174		−}
175		−
176		−static irqreturn_t mt6397_irq_thread(int irq, void *data)
177		−{
178		− struct mt6397_chip *mt6397 = data;
179		−
180		− mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
181		− mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
182		−
183		− return IRQ_HANDLED;
184		−}
185		−
186		−static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
187		− irq_hw_number_t hw)
188		−{
189		− struct mt6397_chip *mt6397 = d->host_data;
190		−
191		− irq_set_chip_data(irq, mt6397);
192		− irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
193		− irq_set_nested_thread(irq, 1);
194		− irq_set_noprobe(irq);
195		−
196		− return 0;
197		−}
198		−
199		−static const struct irq_domain_ops mt6397_irq_domain_ops = {
200		− .map = mt6397_irq_domain_map,
201		−};
202		−
203		−static int mt6397_irq_init(struct mt6397_chip *mt6397)
204		−{
205		− int ret;
206		−
207		− mutex_init(&mt6397->irqlock);
208		−
209		− /* Mask all interrupt sources */
210		− regmap_write(mt6397->regmap, mt6397->int_con[0], 0x0);
211		− regmap_write(mt6397->regmap, mt6397->int_con[1], 0x0);
212		−
213		− mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
214		− MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
215		− if (!mt6397->irq_domain) {
216		− dev_err(mt6397->dev, "could not create irq domain\n");
217		− return -ENOMEM;
218		− }
219		−
220		− ret = devm_request_threaded_irq(mt6397->dev, mt6397->irq, NULL,
221		− mt6397_irq_thread, IRQF_ONESHOT, "mt6397-pmic", mt6397);
222		− if (ret) {
223		− dev_err(mt6397->dev, "failed to register irq=%d; err: %d\n",
224		− mt6397->irq, ret);
225		− return ret;
226		− }
227		−
228		− return 0;
229		−}
230		−
231	103	#ifdef CONFIG_PM_SLEEP
232	104	static int mt6397_irq_suspend(struct device *dev)
233	105	{
@@ -290,7 +162,7 @@ static int mt6397_probe(struct platform_device *pdev) · 56 unmodified lines
290	162	return pmic->irq;
291	163
292	164	switch (id & 0xff) {
293		− case MT6323_CID_CODE:
	165	+ case MT6323_CHIP_ID:
294	166	pmic->int_con[0] = MT6323_INT_CON0;
295	167	pmic->int_con[1] = MT6323_INT_CON1;
296	168	pmic->int_status[0] = MT6323_INT_STATUS0;
@@ -304,8 +176,8 @@ static int mt6397_probe(struct platform_device *pdev) · 7 unmodified lines
304	176	0, pmic->irq_domain);
305	177	break;
306	178
307		− case MT6397_CID_CODE:
308		− case MT6391_CID_CODE:
	179	+ case MT6391_CHIP_ID:
	180	+ case MT6397_CHIP_ID:
309	181	pmic->int_con[0] = MT6397_INT_CON0;
310	182	pmic->int_con[1] = MT6397_INT_CON1;
311	183	pmic->int_status[0] = MT6397_INT_STATUS0;

drivers/mfd/mt6397-irq.c+181−0

@@ -0,0 +1,181 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+//
	3	+// Copyright (c) 2019 MediaTek Inc.
	4	+
	5	+#include <linux/interrupt.h>
	6	+#include <linux/module.h>
	7	+#include <linux/of.h>
	8	+#include <linux/of_device.h>
	9	+#include <linux/of_irq.h>
	10	+#include <linux/platform_device.h>
	11	+#include <linux/regmap.h>
	12	+#include <linux/mfd/mt6323/core.h>
	13	+#include <linux/mfd/mt6323/registers.h>
	14	+#include <linux/mfd/mt6397/core.h>
	15	+#include <linux/mfd/mt6397/registers.h>
	16	+
	17	+static void mt6397_irq_lock(struct irq_data *data)
	18	+{
	19	+ struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
	20	+
	21	+ mutex_lock(&mt6397->irqlock);
	22	+}
	23	+
	24	+static void mt6397_irq_sync_unlock(struct irq_data *data)
	25	+{
	26	+ struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
	27	+
	28	+ regmap_write(mt6397->regmap, mt6397->int_con[0],
	29	+ mt6397->irq_masks_cur[0]);
	30	+ regmap_write(mt6397->regmap, mt6397->int_con[1],
	31	+ mt6397->irq_masks_cur[1]);
	32	+
	33	+ mutex_unlock(&mt6397->irqlock);
	34	+}
	35	+
	36	+static void mt6397_irq_disable(struct irq_data *data)
	37	+{
	38	+ struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
	39	+ int shift = data->hwirq & 0xf;
	40	+ int reg = data->hwirq >> 4;
	41	+
	42	+ mt6397->irq_masks_cur[reg] &= ~BIT(shift);
	43	+}
	44	+
	45	+static void mt6397_irq_enable(struct irq_data *data)
	46	+{
	47	+ struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
	48	+ int shift = data->hwirq & 0xf;
	49	+ int reg = data->hwirq >> 4;
	50	+
	51	+ mt6397->irq_masks_cur[reg] \|= BIT(shift);
	52	+}
	53	+
	54	+#ifdef CONFIG_PM_SLEEP
	55	+static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
	56	+{
	57	+ struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
	58	+ int shift = irq_data->hwirq & 0xf;
	59	+ int reg = irq_data->hwirq >> 4;
	60	+
	61	+ if (on)
	62	+ mt6397->wake_mask[reg] \|= BIT(shift);
	63	+ else
	64	+ mt6397->wake_mask[reg] &= ~BIT(shift);
	65	+
	66	+ return 0;
	67	+}
	68	+#else
	69	+#define mt6397_irq_set_wake NULL
	70	+#endif
	71	+
	72	+static struct irq_chip mt6397_irq_chip = {
	73	+ .name = "mt6397-irq",
	74	+ .irq_bus_lock = mt6397_irq_lock,
	75	+ .irq_bus_sync_unlock = mt6397_irq_sync_unlock,
	76	+ .irq_enable = mt6397_irq_enable,
	77	+ .irq_disable = mt6397_irq_disable,
	78	+ .irq_set_wake = mt6397_irq_set_wake,
	79	+};
	80	+
	81	+static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
	82	+ int irqbase)
	83	+{
	84	+ unsigned int status;
	85	+ int i, irq, ret;
	86	+
	87	+ ret = regmap_read(mt6397->regmap, reg, &status);
	88	+ if (ret) {
	89	+ dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
	90	+ return;
	91	+ }
	92	+
	93	+ for (i = 0; i < 16; i++) {
	94	+ if (status & BIT(i)) {
	95	+ irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
	96	+ if (irq)
	97	+ handle_nested_irq(irq);
	98	+ }
	99	+ }
	100	+
	101	+ regmap_write(mt6397->regmap, reg, status);
	102	+}
	103	+
	104	+static irqreturn_t mt6397_irq_thread(int irq, void *data)
	105	+{
	106	+ struct mt6397_chip *mt6397 = data;
	107	+
	108	+ mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
	109	+ mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
	110	+
	111	+ return IRQ_HANDLED;
	112	+}
	113	+
	114	+static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
	115	+ irq_hw_number_t hw)
	116	+{
	117	+ struct mt6397_chip *mt6397 = d->host_data;
	118	+
	119	+ irq_set_chip_data(irq, mt6397);
	120	+ irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
	121	+ irq_set_nested_thread(irq, 1);
	122	+ irq_set_noprobe(irq);
	123	+
	124	+ return 0;
	125	+}
	126	+
	127	+static const struct irq_domain_ops mt6397_irq_domain_ops = {
	128	+ .map = mt6397_irq_domain_map,
	129	+};
	130	+
	131	+int mt6397_irq_init(struct mt6397_chip *chip)
	132	+{
	133	+ int ret;
	134	+
	135	+ mutex_init(&chip->irqlock);
	136	+
	137	+ switch (chip->chip_id) {
	138	+ case MT6323_CHIP_ID:
	139	+ chip->int_con[0] = MT6323_INT_CON0;
	140	+ chip->int_con[1] = MT6323_INT_CON1;
	141	+ chip->int_status[0] = MT6323_INT_STATUS0;
	142	+ chip->int_status[1] = MT6323_INT_STATUS1;
	143	+ break;
	144	+
	145	+ case MT6391_CHIP_ID:
	146	+ case MT6397_CHIP_ID:
	147	+ chip->int_con[0] = MT6397_INT_CON0;
	148	+ chip->int_con[1] = MT6397_INT_CON1;
	149	+ chip->int_status[0] = MT6397_INT_STATUS0;
	150	+ chip->int_status[1] = MT6397_INT_STATUS1;
	151	+ break;
	152	+
	153	+ default:
	154	+ dev_err(chip->dev, "unsupported chip: 0x%x\n", chip->chip_id);
	155	+ return -ENODEV;
	156	+ }
	157	+
	158	+ /* Mask all interrupt sources */
	159	+ regmap_write(chip->regmap, chip->int_con[0], 0x0);
	160	+ regmap_write(chip->regmap, chip->int_con[1], 0x0);
	161	+
	162	+ chip->irq_domain = irq_domain_add_linear(chip->dev->of_node,
	163	+ MT6397_IRQ_NR,
	164	+ &mt6397_irq_domain_ops,
	165	+ chip);
	166	+ if (!chip->irq_domain) {
	167	+ dev_err(chip->dev, "could not create irq domain\n");
	168	+ return -ENOMEM;
	169	+ }
	170	+
	171	+ ret = devm_request_threaded_irq(chip->dev, chip->irq, NULL,
	172	+ mt6397_irq_thread, IRQF_ONESHOT,
	173	+ "mt6397-pmic", chip);
	174	+ if (ret) {
	175	+ dev_err(chip->dev, "failed to register irq=%d; err: %d\n",
	176	+ chip->irq, ret);
	177	+ return ret;
	178	+ }
	179	+
	180	+ return 0;
	181	+}

drivers/mfd/palmas.c+3−3

@@ -549,12 +549,12 @@ static int palmas_i2c_probe(struct i2c_client *i2c, · 548 unmodified lines
549	549	palmas->i2c_clients[i] = i2c;
550	550	else {
551	551	palmas->i2c_clients[i] =
552		− i2c_new_dummy(i2c->adapter,
	552	+ i2c_new_dummy_device(i2c->adapter,
553	553	i2c->addr + i);
554		− if (!palmas->i2c_clients[i]) {
	554	+ if (IS_ERR(palmas->i2c_clients[i])) {
555	555	dev_err(palmas->dev,
556	556	"can't attach client %d\n", i);
557		− ret = -ENOMEM;
	557	+ ret = PTR_ERR(palmas->i2c_clients[i]);
558	558	goto err_i2c;
559	559	}
560	560	palmas->i2c_clients[i]->dev.of_node = of_node_get(node);

drivers/mfd/qcom_rpm.c+3−9

@@ -561,22 +561,16 @@ static int qcom_rpm_probe(struct platform_device *pdev) · 560 unmodified lines
561	561	clk_prepare_enable(rpm->ramclk); /* Accepts NULL */
562	562
563	563	irq_ack = platform_get_irq_byname(pdev, "ack");
564		− if (irq_ack < 0) {
565		− dev_err(&pdev->dev, "required ack interrupt missing\n");
	564	+ if (irq_ack < 0)
566	565	return irq_ack;
567		− }
568	566
569	567	irq_err = platform_get_irq_byname(pdev, "err");
570		− if (irq_err < 0) {
571		− dev_err(&pdev->dev, "required err interrupt missing\n");
	568	+ if (irq_err < 0)
572	569	return irq_err;
573		− }
574	570
575	571	irq_wakeup = platform_get_irq_byname(pdev, "wakeup");
576		− if (irq_wakeup < 0) {
577		− dev_err(&pdev->dev, "required wakeup interrupt missing\n");
	572	+ if (irq_wakeup < 0)
578	573	return irq_wakeup;
579		− }
580	574
581	575	match = of_match_device(qcom_rpm_of_match, &pdev->dev);
582	576	if (!match)

drivers/mfd/sm501.c+2−3

@@ -17,6 +17,7 @@ · 16 unmodified lines
17	17	#include <linux/platform_device.h>
18	18	#include <linux/pci.h>
19	19	#include <linux/platform_data/i2c-gpio.h>
	20	+#include <linux/gpio/driver.h>
20	21	#include <linux/gpio/machine.h>
21	22	#include <linux/slab.h>
22	23
@@ -1394,10 +1395,8 @@ static int sm501_plat_probe(struct platform_device *dev) · 1371 unmodified lines
1394	1395	sm->platdata = dev_get_platdata(&dev->dev);
1395	1396
1396	1397	ret = platform_get_irq(dev, 0);
1397		− if (ret < 0) {
1398		− dev_err(&dev->dev, "failed to get irq resource\n");
	1398	+ if (ret < 0)
1399	1399	goto err_res;
1400		− }
1401	1400	sm->irq = ret;
1402	1401
1403	1402	sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);

drivers/mfd/timberdale.c+1−2

@@ -626,8 +626,7 @@ static const struct mfd_cell timberdale_cells_bar2[] = { · 625 unmodified lines
626	626	static ssize_t show_fw_ver(struct device dev, struct device_attribute attr,
627	627	char *buf)
628	628	{
629		− struct pci_dev *pdev = to_pci_dev(dev);
630		− struct timberdale_device *priv = pci_get_drvdata(pdev);
	629	+ struct timberdale_device *priv = dev_get_drvdata(dev);
631	630
632	631	return sprintf(buf, "%d.%d.%d\n", priv->fw.major, priv->fw.minor,
633	632	priv->fw.config);

drivers/mfd/tps80031.c+8−15

@@ -437,12 +437,11 @@ static int tps80031_probe(struct i2c_client *client, · 436 unmodified lines
437	437	if (tps80031_slave_address[i] == client->addr)
438	438	tps80031->clients[i] = client;
439	439	else
440		− tps80031->clients[i] = i2c_new_dummy(client->adapter,
441		− tps80031_slave_address[i]);
442		− if (!tps80031->clients[i]) {
	440	+ tps80031->clients[i] = devm_i2c_new_dummy_device(&client->dev,
	441	+ client->adapter, tps80031_slave_address[i]);
	442	+ if (IS_ERR(tps80031->clients[i])) {
443	443	dev_err(&client->dev, "can't attach client %d\n", i);
444		− ret = -ENOMEM;
445		− goto fail_client_reg;
	444	+ return PTR_ERR(tps80031->clients[i]);
446	445	}
447	446
448	447	i2c_set_clientdata(tps80031->clients[i], tps80031);
@@ -452,7 +451,7 @@ static int tps80031_probe(struct i2c_client *client, · 3 unmodified lines
452	451	ret = PTR_ERR(tps80031->regmap[i]);
453	452	dev_err(&client->dev,
454	453	"regmap %d init failed, err %d\n", i, ret);
455		− goto fail_client_reg;
	454	+ return ret;
456	455	}
457	456	}
458	457
@@ -461,7 +460,7 @@ static int tps80031_probe(struct i2c_client *client, · 2 unmodified lines
461	460	if (ret < 0) {
462	461	dev_err(&client->dev,
463	462	"Silicon version number read failed: %d\n", ret);
464		− goto fail_client_reg;
	463	+ return ret;
465	464	}
466	465
467	466	ret = tps80031_read(&client->dev, TPS80031_SLAVE_ID3,
@@ -469,7 +468,7 @@ static int tps80031_probe(struct i2c_client *client, · 1 unmodified line
469	468	if (ret < 0) {
470	469	dev_err(&client->dev,
471	470	"Silicon eeprom version read failed: %d\n", ret);
472		− goto fail_client_reg;
	471	+ return ret;
473	472	}
474	473
475	474	dev_info(&client->dev, "ES version 0x%02x and EPROM version 0x%02x\n",
@@ -482,7 +481,7 @@ static int tps80031_probe(struct i2c_client *client, · 6 unmodified lines
482	481	ret = tps80031_irq_init(tps80031, client->irq, pdata->irq_base);
483	482	if (ret) {
484	483	dev_err(&client->dev, "IRQ init failed: %d\n", ret);
485		− goto fail_client_reg;
	484	+ return ret;
486	485	}
487	486
488	487	tps80031_pupd_init(tps80031, pdata);
@@ -506,12 +505,6 @@ static int tps80031_probe(struct i2c_client *client, · 17 unmodified lines
506	505
507	506	fail_mfd_add:
508	507	regmap_del_irq_chip(client->irq, tps80031->irq_data);
509		−
510		−fail_client_reg:
511		− for (i = 0; i < TPS80031_NUM_SLAVES; i++) {
512		− if (tps80031->clients[i] && (tps80031->clients[i] != client))
513		− i2c_unregister_device(tps80031->clients[i]);
514		− }
515	508	return ret;
516	509	}
517	510

drivers/mfd/twl-core.c+3−3

@@ -1141,12 +1141,12 @@ twl_probe(struct i2c_client client, const struct i2c_device_id id) · 1140 unmodified lines
1141	1141	if (i == 0) {
1142	1142	twl->client = client;
1143	1143	} else {
1144		− twl->client = i2c_new_dummy(client->adapter,
	1144	+ twl->client = i2c_new_dummy_device(client->adapter,
1145	1145	client->addr + i);
1146		− if (!twl->client) {
	1146	+ if (IS_ERR(twl->client)) {
1147	1147	dev_err(&client->dev,
1148	1148	"can't attach client %d\n", i);
1149		− status = -ENOMEM;
	1149	+ status = PTR_ERR(twl->client);
1150	1150	goto fail;
1151	1151	}
1152	1152	}

include/Kbuild+0−1

@@ -312,7 +312,6 @@ header-test- += linux/mfd/as3711.h · 311 unmodified lines
312	312	header-test- += linux/mfd/as3722.h
313	313	header-test- += linux/mfd/da903x.h
314	314	header-test- += linux/mfd/da9055/pdata.h
315		−header-test- += linux/mfd/da9063/pdata.h
316	315	header-test- += linux/mfd/db8500-prcmu.h
317	316	header-test- += linux/mfd/dbx500-prcmu.h
318	317	header-test- += linux/mfd/dln2.h

include/linux/mfd/da9063/pdata.h+0−60

@@ -1,60 +0,0 @@
1		−/* SPDX-License-Identifier: GPL-2.0-or-later */
2		−/*
3		− * Platform configuration options for DA9063
4		− *
5		− * Copyright 2012 Dialog Semiconductor Ltd.
6		− *
7		− * Author: Michal Hajduk, Dialog Semiconductor
8		− * Author: Krystian Garbaciak, Dialog Semiconductor
9		− */
10		−
11		−#ifndef __MFD_DA9063_PDATA_H__
12		−#define __MFD_DA9063_PDATA_H__
13		−
14		−/*
15		− * RGB LED configuration
16		− */
17		−/* LED IDs for flags in struct led_info. */
18		−enum {
19		− DA9063_GPIO11_LED,
20		− DA9063_GPIO14_LED,
21		− DA9063_GPIO15_LED,
22		−
23		− DA9063_LED_NUM
24		−};
25		−#define DA9063_LED_ID_MASK 0x3
26		−
27		−/* LED polarity for flags in struct led_info. */
28		−#define DA9063_LED_HIGH_LEVEL_ACTIVE 0x0
29		−#define DA9063_LED_LOW_LEVEL_ACTIVE 0x4
30		−
31		−
32		−/*
33		− * General PMIC configuration
34		− */
35		−/* HWMON ADC channels configuration */
36		−#define DA9063_FLG_FORCE_IN0_MANUAL_MODE 0x0010
37		−#define DA9063_FLG_FORCE_IN0_AUTO_MODE 0x0020
38		−#define DA9063_FLG_FORCE_IN1_MANUAL_MODE 0x0040
39		−#define DA9063_FLG_FORCE_IN1_AUTO_MODE 0x0080
40		−#define DA9063_FLG_FORCE_IN2_MANUAL_MODE 0x0100
41		−#define DA9063_FLG_FORCE_IN2_AUTO_MODE 0x0200
42		−#define DA9063_FLG_FORCE_IN3_MANUAL_MODE 0x0400
43		−#define DA9063_FLG_FORCE_IN3_AUTO_MODE 0x0800
44		−
45		−/* Disable register caching. */
46		−#define DA9063_FLG_NO_CACHE 0x0008
47		−
48		−struct da9063;
49		−
50		−/* DA9063 platform data */
51		−struct da9063_pdata {
52		− int (init)(struct da9063 da9063);
53		− int irq_base;
54		− bool key_power;
55		− unsigned flags;
56		− struct da9063_regulators_pdata *regulators_pdata;
57		− struct led_platform_data *leds_pdata;
58		−};
59		−
60		−#endif /* __MFD_DA9063_PDATA_H__ */

include/linux/mfd/intel_soc_pmic_mrfld.h+81−0

@@ -0,0 +1,81 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 */
	2	+/*
	3	+ * Header file for Intel Merrifield Basin Cove PMIC
	4	+ *
	5	+ * Copyright (C) 2019 Intel Corporation. All rights reserved.
	6	+ */
	7	+
	8	+#ifndef __INTEL_SOC_PMIC_MRFLD_H__
	9	+#define __INTEL_SOC_PMIC_MRFLD_H__
	10	+
	11	+#include <linux/bits.h>
	12	+
	13	+#define BCOVE_ID 0x00
	14	+
	15	+#define BCOVE_ID_MINREV0 GENMASK(2, 0)
	16	+#define BCOVE_ID_MAJREV0 GENMASK(5, 3)
	17	+#define BCOVE_ID_VENDID0 GENMASK(7, 6)
	18	+
	19	+#define BCOVE_MINOR(x) (unsigned int)(((x) & BCOVE_ID_MINREV0) >> 0)
	20	+#define BCOVE_MAJOR(x) (unsigned int)(((x) & BCOVE_ID_MAJREV0) >> 3)
	21	+#define BCOVE_VENDOR(x) (unsigned int)(((x) & BCOVE_ID_VENDID0) >> 6)
	22	+
	23	+#define BCOVE_IRQLVL1 0x01
	24	+
	25	+#define BCOVE_PBIRQ 0x02
	26	+#define BCOVE_TMUIRQ 0x03
	27	+#define BCOVE_THRMIRQ 0x04
	28	+#define BCOVE_BCUIRQ 0x05
	29	+#define BCOVE_ADCIRQ 0x06
	30	+#define BCOVE_CHGRIRQ0 0x07
	31	+#define BCOVE_CHGRIRQ1 0x08
	32	+#define BCOVE_GPIOIRQ 0x09
	33	+#define BCOVE_CRITIRQ 0x0B
	34	+
	35	+#define BCOVE_MIRQLVL1 0x0C
	36	+
	37	+#define BCOVE_MPBIRQ 0x0D
	38	+#define BCOVE_MTMUIRQ 0x0E
	39	+#define BCOVE_MTHRMIRQ 0x0F
	40	+#define BCOVE_MBCUIRQ 0x10
	41	+#define BCOVE_MADCIRQ 0x11
	42	+#define BCOVE_MCHGRIRQ0 0x12
	43	+#define BCOVE_MCHGRIRQ1 0x13
	44	+#define BCOVE_MGPIOIRQ 0x14
	45	+#define BCOVE_MCRITIRQ 0x16
	46	+
	47	+#define BCOVE_SCHGRIRQ0 0x4E
	48	+#define BCOVE_SCHGRIRQ1 0x4F
	49	+
	50	+/* Level 1 IRQs */
	51	+#define BCOVE_LVL1_PWRBTN BIT(0) /* power button */
	52	+#define BCOVE_LVL1_TMU BIT(1) /* time management unit */
	53	+#define BCOVE_LVL1_THRM BIT(2) /* thermal */
	54	+#define BCOVE_LVL1_BCU BIT(3) /* burst control unit */
	55	+#define BCOVE_LVL1_ADC BIT(4) /* ADC */
	56	+#define BCOVE_LVL1_CHGR BIT(5) /* charger */
	57	+#define BCOVE_LVL1_GPIO BIT(6) /* GPIO */
	58	+#define BCOVE_LVL1_CRIT BIT(7) /* critical event */
	59	+
	60	+/* Level 2 IRQs: power button */
	61	+#define BCOVE_PBIRQ_PBTN BIT(0)
	62	+#define BCOVE_PBIRQ_UBTN BIT(1)
	63	+
	64	+/* Level 2 IRQs: ADC */
	65	+#define BCOVE_ADCIRQ_BATTEMP BIT(2)
	66	+#define BCOVE_ADCIRQ_SYSTEMP BIT(3)
	67	+#define BCOVE_ADCIRQ_BATTID BIT(4)
	68	+#define BCOVE_ADCIRQ_VIBATT BIT(5)
	69	+#define BCOVE_ADCIRQ_CCTICK BIT(7)
	70	+
	71	+/* Level 2 IRQs: charger */
	72	+#define BCOVE_CHGRIRQ_BAT0ALRT BIT(4)
	73	+#define BCOVE_CHGRIRQ_BAT1ALRT BIT(5)
	74	+#define BCOVE_CHGRIRQ_BATCRIT BIT(6)
	75	+
	76	+#define BCOVE_CHGRIRQ_VBUSDET BIT(0)
	77	+#define BCOVE_CHGRIRQ_DCDET BIT(1)
	78	+#define BCOVE_CHGRIRQ_BATTDET BIT(2)
	79	+#define BCOVE_CHGRIRQ_USBIDDET BIT(3)
	80	+
	81	+#endif /* __INTEL_SOC_PMIC_MRFLD_H__ */

include/linux/mfd/mt6397/core.h+11−0

@@ -7,6 +7,14 @@ · 6 unmodified lines
7	7	#ifndef __MFD_MT6397_CORE_H__
8	8	#define __MFD_MT6397_CORE_H__
9	9
	10	+#include <linux/mutex.h>
	11	+
	12	+enum chip_id {
	13	+ MT6323_CHIP_ID = 0x23,
	14	+ MT6391_CHIP_ID = 0x91,
	15	+ MT6397_CHIP_ID = 0x97,
	16	+};
	17	+
10	18	enum mt6397_irq_numbers {
11	19	MT6397_IRQ_SPKL_AB = 0,
12	20	MT6397_IRQ_SPKR_AB,
@@ -54,6 +62,9 @@ struct mt6397_chip { · 41 unmodified lines
54	62	u16 irq_masks_cache[2];
55	63	u16 int_con[2];
56	64	u16 int_status[2];
	65	+ u16 chip_id;
57	66	};
58	67
	68	+int mt6397_irq_init(struct mt6397_chip *chip);
	69	+
59	70	#endif /* __MFD_MT6397_CORE_H__ */

include/linux/platform_data/cros_ec_commands.h+12−0

@@ -5513,6 +5513,18 @@ struct ec_params_fp_seed { · 5512 unmodified lines
5513	5513	uint8_t seed[FP_CONTEXT_TPM_BYTES];
5514	5514	} __ec_align4;
5515	5515
	5516	+#define EC_CMD_FP_ENC_STATUS 0x0409
	5517	+
	5518	+/* FP TPM seed has been set or not */
	5519	+#define FP_ENC_STATUS_SEED_SET BIT(0)
	5520	+
	5521	+struct ec_response_fp_encryption_status {
	5522	+ /* Used bits in encryption engine status */
	5523	+ uint32_t valid_flags;
	5524	+ /* Encryption engine status */
	5525	+ uint32_t status;
	5526	+} __ec_align4;
	5527	+
5516	5528	/*****************************************************************************/
5517	5529	/* Touchpad MCU commands: range 0x0500-0x05FF */
5518	5530

Merge tag 'mfd-next-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

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