perf vendor events s390: Add metric for TLB and cache

Add metrics for tlb and cache statistics: - finite_cpi: Cycles per Instructions from Finite cache/memory - est_cpi: Estimated Instruction Complexity CPI infinite Level 1 - scpl1m: Estimated Sourcing Cycles per Level 1 Miss - tlb_percent: Estimated TLB CPU percentage of Total CPU - tlb_miss: Estimated Cycles per TLB Miss For details about the formulas see this documentation: https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf Output after: # ./perf stat -M tlb_miss -- dd if=/dev/zero of=/dev/null bs=1M count=10K ... dd output removed Performance counter stats for 'dd if=/dev/zero of=/dev/null bs=1M count=10K': 667,726 DTLB2_MISSES # 440.96 tlb_miss 198 ITLB2_WRITES 795,170,260 L1C_TLB2_MISSES 9,478 ITLB2_MISSES 820 DTLB2_WRITES 1,197,126,869 L1D_PENALTY_CYCLES 2,457,447 L1I_PENALTY_CYCLES 1.249342187 seconds time elapsed 0.001030000 seconds user 1.248105000 seconds sys #

Thomas Richter committed 3 years ago

Commit 4c290d41 parent 850eea24 files · +105 −0Browse files

Unified · Split

4 files

tools/perf/pmu-events/arch/s390/cf_z13/transaction.json +30 −0
tools/perf/pmu-events/arch/s390/cf_z14/transaction.json +25 −0
tools/perf/pmu-events/arch/s390/cf_z15/transaction.json +25 −0
tools/perf/pmu-events/arch/s390/cf_z16/transaction.json +25 −0

tools/perf/pmu-events/arch/s390/cf_z13/transaction.json+30−0

@@ -43,5 +43,35 @@ · 42 unmodified lines
43	43	"BriefDescription": "Percentage sourced from memory",
44	44	"MetricName": "memp",
45	45	"MetricExpr": "((L1D_ONNODE_MEM_SOURCED_WRITES + L1D_ONDRAWER_MEM_SOURCED_WRITES + L1D_OFFDRAWER_MEM_SOURCED_WRITES + L1D_ONCHIP_MEM_SOURCED_WRITES + L1I_ONNODE_MEM_SOURCED_WRITES + L1I_ONDRAWER_MEM_SOURCED_WRITES + L1I_OFFDRAWER_MEM_SOURCED_WRITES + L1I_ONCHIP_MEM_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
	46	+ },
	47	+ {
	48	+ "BriefDescription": "Cycles per Instructions from Finite cache/memory",
	49	+ "MetricName": "finite_cpi",
	50	+ "MetricExpr": "L1C_TLB1_MISSES / INSTRUCTIONS"
	51	+ },
	52	+ {
	53	+ "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1",
	54	+ "MetricName": "est_cpi",
	55	+ "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB1_MISSES / INSTRUCTIONS)"
	56	+ },
	57	+ {
	58	+ "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss",
	59	+ "MetricName": "scpl1m",
	60	+ "MetricExpr": "L1C_TLB1_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)"
	61	+ },
	62	+ {
	63	+ "BriefDescription": "Estimated TLB CPU percentage of Total CPU",
	64	+ "MetricName": "tlb_percent",
	65	+ "MetricExpr": "((DTLB1_MISSES + ITLB1_MISSES) / CPU_CYCLES) * (L1C_TLB1_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100"
	66	+ },
	67	+ {
	68	+ "BriefDescription": "Estimated Cycles per TLB Miss",
	69	+ "MetricName": "tlb_miss",
	70	+ "MetricExpr": "((DTLB1_MISSES + ITLB1_MISSES) / (DTLB1_WRITES + ITLB1_WRITES)) * (L1C_TLB1_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))"
	71	+ },
	72	+ {
	73	+ "BriefDescription": "Page Table Entry misses",
	74	+ "MetricName": "pte_miss",
	75	+ "MetricExpr": "(TLB2_PTE_WRITES / (DTLB1_WRITES + ITLB1_WRITES)) * 100"
46	76	}
47	77	]

tools/perf/pmu-events/arch/s390/cf_z14/transaction.json+25−0

@@ -43,5 +43,30 @@ · 42 unmodified lines
43	43	"BriefDescription": "Percentage sourced from memory",
44	44	"MetricName": "memp",
45	45	"MetricExpr": "((L1D_ONCHIP_MEMORY_SOURCED_WRITES + L1D_ONCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFDRAWER_MEMORY_SOURCED_WRITES + L1I_ONCHIP_MEMORY_SOURCED_WRITES + L1I_ONCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFDRAWER_MEMORY_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
	46	+ },
	47	+ {
	48	+ "BriefDescription": "Cycles per Instructions from Finite cache/memory",
	49	+ "MetricName": "finite_cpi",
	50	+ "MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS"
	51	+ },
	52	+ {
	53	+ "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1",
	54	+ "MetricName": "est_cpi",
	55	+ "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)"
	56	+ },
	57	+ {
	58	+ "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss",
	59	+ "MetricName": "scpl1m",
	60	+ "MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)"
	61	+ },
	62	+ {
	63	+ "BriefDescription": "Estimated TLB CPU percentage of Total CPU",
	64	+ "MetricName": "tlb_percent",
	65	+ "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100"
	66	+ },
	67	+ {
	68	+ "BriefDescription": "Estimated Cycles per TLB Miss",
	69	+ "MetricName": "tlb_miss",
	70	+ "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))"
46	71	}
47	72	]

tools/perf/pmu-events/arch/s390/cf_z15/transaction.json+25−0

@@ -43,5 +43,30 @@ · 42 unmodified lines
43	43	"BriefDescription": "Percentage sourced from memory",
44	44	"MetricName": "memp",
45	45	"MetricExpr": "((L1D_ONCHIP_MEMORY_SOURCED_WRITES + L1D_ONCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFDRAWER_MEMORY_SOURCED_WRITES + L1I_ONCHIP_MEMORY_SOURCED_WRITES + L1I_ONCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFDRAWER_MEMORY_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
	46	+ },
	47	+ {
	48	+ "BriefDescription": "Cycles per Instructions from Finite cache/memory",
	49	+ "MetricName": "finite_cpi",
	50	+ "MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS"
	51	+ },
	52	+ {
	53	+ "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1",
	54	+ "MetricName": "est_cpi",
	55	+ "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)"
	56	+ },
	57	+ {
	58	+ "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss",
	59	+ "MetricName": "scpl1m",
	60	+ "MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)"
	61	+ },
	62	+ {
	63	+ "BriefDescription": "Estimated TLB CPU percentage of Total CPU",
	64	+ "MetricName": "tlb_percent",
	65	+ "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100"
	66	+ },
	67	+ {
	68	+ "BriefDescription": "Estimated Cycles per TLB Miss",
	69	+ "MetricName": "tlb_miss",
	70	+ "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))"
46	71	}
47	72	]

tools/perf/pmu-events/arch/s390/cf_z16/transaction.json+25−0

@@ -43,5 +43,30 @@ · 42 unmodified lines
43	43	"BriefDescription": "Percentage sourced from memory",
44	44	"MetricName": "memp",
45	45	"MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
	46	+ },
	47	+ {
	48	+ "BriefDescription": "Cycles per Instructions from Finite cache/memory",
	49	+ "MetricName": "finite_cpi",
	50	+ "MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS"
	51	+ },
	52	+ {
	53	+ "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1",
	54	+ "MetricName": "est_cpi",
	55	+ "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)"
	56	+ },
	57	+ {
	58	+ "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss",
	59	+ "MetricName": "scpl1m",
	60	+ "MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)"
	61	+ },
	62	+ {
	63	+ "BriefDescription": "Estimated TLB CPU percentage of Total CPU",
	64	+ "MetricName": "tlb_percent",
	65	+ "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100"
	66	+ },
	67	+ {
	68	+ "BriefDescription": "Estimated Cycles per TLB Miss",
	69	+ "MetricName": "tlb_miss",
	70	+ "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))"
46	71	}
47	72	]

perf vendor events s390: Add metric for TLB and cache

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