- Add intel-gw driver for PCIe host controller on Intel Gateway SoC (Dilip Kota) - Use shared DesignWare helpers to configure Fast Training Sequence (FTS) in artpec6 (Dilip Kota) * remotes/lorenzo/pci/dwc: PCI: artpec6: Configure FTS with dwc helper function PCI: dwc: intel: PCIe RC controller driver dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
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| @@ -676,6 +676,7 @@ · 675 unmodified lines | |||
| 676 | #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ | 676 | #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ |
| 677 | #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ | 677 | #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ |
| 678 | #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ | 678 | #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ |
| 679 | #define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */ | ||
| 679 | #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ | 680 | #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ |
| 680 | #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ | 681 | #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ |
| 681 | #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ | 682 | #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ |