VMX encodes access rights differently from LAR, and the latter is most likely what x86 people think of when they think of "access rights". Rename them to avoid confusion.
Unified · Split
| @@ -368,29 +368,29 @@ enum vmcs_field { · 367 unmodified lines | ||
| 368 | 368 | #define TYPE_PHYSICAL_APIC_EVENT (10 << 12) |
| 369 | 369 | #define TYPE_PHYSICAL_APIC_INST (15 << 12) |
| 370 | 370 | |
| 371 | −/* segment AR */ | |
| 372 | −#define SEGMENT_AR_L_MASK (1 << 13) | |
| 373 | − | |
| 374 | −#define AR_TYPE_ACCESSES_MASK 1 | |
| 375 | −#define AR_TYPE_READABLE_MASK (1 << 1) | |
| 376 | −#define AR_TYPE_WRITEABLE_MASK (1 << 2) | |
| 377 | −#define AR_TYPE_CODE_MASK (1 << 3) | |
| 378 | −#define AR_TYPE_MASK 0x0f | |
| 379 | −#define AR_TYPE_BUSY_64_TSS 11 | |
| 380 | −#define AR_TYPE_BUSY_32_TSS 11 | |
| 381 | −#define AR_TYPE_BUSY_16_TSS 3 | |
| 382 | −#define AR_TYPE_LDT 2 | |
| 383 | − | |
| 384 | −#define AR_UNUSABLE_MASK (1 << 16) | |
| 385 | −#define AR_S_MASK (1 << 4) | |
| 386 | −#define AR_P_MASK (1 << 7) | |
| 387 | −#define AR_L_MASK (1 << 13) | |
| 388 | −#define AR_DB_MASK (1 << 14) | |
| 389 | −#define AR_G_MASK (1 << 15) | |
| 390 | −#define AR_DPL_SHIFT 5 | |
| 391 | −#define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3) | |
| 392 | − | |
| 393 | −#define AR_RESERVD_MASK 0xfffe0f00 | |
| 371 | +/* segment AR in VMCS -- these are different from what LAR reports */ | |
| 372 | +#define VMX_SEGMENT_AR_L_MASK (1 << 13) | |
| 373 | + | |
| 374 | +#define VMX_AR_TYPE_ACCESSES_MASK 1 | |
| 375 | +#define VMX_AR_TYPE_READABLE_MASK (1 << 1) | |
| 376 | +#define VMX_AR_TYPE_WRITEABLE_MASK (1 << 2) | |
| 377 | +#define VMX_AR_TYPE_CODE_MASK (1 << 3) | |
| 378 | +#define VMX_AR_TYPE_MASK 0x0f | |
| 379 | +#define VMX_AR_TYPE_BUSY_64_TSS 11 | |
| 380 | +#define VMX_AR_TYPE_BUSY_32_TSS 11 | |
| 381 | +#define VMX_AR_TYPE_BUSY_16_TSS 3 | |
| 382 | +#define VMX_AR_TYPE_LDT 2 | |
| 383 | + | |
| 384 | +#define VMX_AR_UNUSABLE_MASK (1 << 16) | |
| 385 | +#define VMX_AR_S_MASK (1 << 4) | |
| 386 | +#define VMX_AR_P_MASK (1 << 7) | |
| 387 | +#define VMX_AR_L_MASK (1 << 13) | |
| 388 | +#define VMX_AR_DB_MASK (1 << 14) | |
| 389 | +#define VMX_AR_G_MASK (1 << 15) | |
| 390 | +#define VMX_AR_DPL_SHIFT 5 | |
| 391 | +#define VMX_AR_DPL(ar) (((ar) >> VMX_AR_DPL_SHIFT) & 3) | |
| 392 | + | |
| 393 | +#define VMX_AR_RESERVD_MASK 0xfffe0f00 | |
| 394 | 394 | |
| 395 | 395 | #define TSS_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 0) |
| 396 | 396 | #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 1) |
| @@ -3423,12 +3423,12 @@ static void enter_lmode(struct kvm_vcpu *vcpu) · 3422 unmodified lines | ||
| 3423 | 3423 | vmx_segment_cache_clear(to_vmx(vcpu)); |
| 3424 | 3424 | |
| 3425 | 3425 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); |
| 3426 | − if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { | |
| 3426 | + if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { | |
| 3427 | 3427 | pr_debug_ratelimited("%s: tss fixup for long mode. \n", |
| 3428 | 3428 | __func__); |
| 3429 | 3429 | vmcs_write32(GUEST_TR_AR_BYTES, |
| 3430 | − (guest_tr_ar & ~AR_TYPE_MASK) | |
| 3431 | − | AR_TYPE_BUSY_64_TSS); | |
| 3430 | + (guest_tr_ar & ~VMX_AR_TYPE_MASK) | |
| 3431 | + | VMX_AR_TYPE_BUSY_64_TSS); | |
| 3432 | 3432 | } |
| 3433 | 3433 | vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); |
| 3434 | 3434 | } |
| @@ -3719,7 +3719,7 @@ static int vmx_get_cpl(struct kvm_vcpu *vcpu) · 284 unmodified lines | ||
| 3719 | 3719 | return 0; |
| 3720 | 3720 | else { |
| 3721 | 3721 | int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); |
| 3722 | − return AR_DPL(ar); | |
| 3722 | + return VMX_AR_DPL(ar); | |
| 3723 | 3723 | } |
| 3724 | 3724 | } |
| 3725 | 3725 | |
| @@ -3847,11 +3847,11 @@ static bool code_segment_valid(struct kvm_vcpu *vcpu) · 121 unmodified lines | ||
| 3847 | 3847 | |
| 3848 | 3848 | if (cs.unusable) |
| 3849 | 3849 | return false; |
| 3850 | − if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK)) | |
| 3850 | + if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) | |
| 3851 | 3851 | return false; |
| 3852 | 3852 | if (!cs.s) |
| 3853 | 3853 | return false; |
| 3854 | − if (cs.type & AR_TYPE_WRITEABLE_MASK) { | |
| 3854 | + if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { | |
| 3855 | 3855 | if (cs.dpl > cs_rpl) |
| 3856 | 3856 | return false; |
| 3857 | 3857 | } else { |
| @@ -3901,7 +3901,7 @@ static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) · 43 unmodified lines | ||
| 3901 | 3901 | return false; |
| 3902 | 3902 | if (!var.present) |
| 3903 | 3903 | return false; |
| 3904 | − if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) { | |
| 3904 | + if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { | |
| 3905 | 3905 | if (var.dpl < rpl) /* DPL < RPL */ |
| 3906 | 3906 | return false; |
| 3907 | 3907 | } |