Pull performance event updates from Ingo Molnar: "x86 PMU driver updates: - Add support for the core PMU for Intel Diamond Rapids (DMR) CPUs (Dapeng Mi) Compared to previous iterations of the Intel PMU code, there's been a lot of changes, which center around three main areas: - Introduce the OFF-MODULE RESPONSE (OMR) facility to replace the Off-Core Response (OCR) facility - New PEBS data source encoding layout - Support the new "RDPMC user disable" feature - Likewise, a large series adds uncore PMU support for Intel Diamond Rapids (DMR) CPUs (Zide Chen) This centers around these four main areas: - DMR may have two Integrated I/O and Memory Hub (IMH) dies, separate from the compute tile (CBB) dies. Each CBB and each IMH die has its own discovery domain. - Unlike prior CPUs that retrieve the global discovery table portal exclusively via PCI or MSR, DMR uses PCI for IMH PMON discovery and MSR for CBB PMON discovery. - DMR introduces several new PMON types: SCA, HAMVF, D2D_ULA, UBR, PCIE4, CRS, CPC, ITC, OTC, CMS, and PCIE6. - IIO free-running counters in DMR are MMIO-based, unlike SPR. - Also add support for Add missing PMON units for Intel Panther Lake, and support Nova Lake (NVL), which largely maps to Panther Lake. (Zide Chen) - KVM integration: Add support for mediated vPMUs (by Kan Liang and Sean Christopherson, with fixes and cleanups by Peter Zijlstra, Sandipan Das and Mingwei Zhang) - Add Intel cstate driver to support for Wildcat Lake (WCL) CPUs, which are a low-power variant of Panther Lake (Zide Chen) - Add core, cstate and MSR PMU support for the Airmont NP Intel CPU (aka MaxLinear Lightning Mountain), which maps to the existing Airmont code (Martin Schiller) Performance enhancements: - Speed up kexec shutdown by avoiding unnecessary cross CPU calls (Jan H. Schönherr) - Fix slow perf_event_task_exit() with LBR callstacks (Namhyung Kim) User-space stack unwinding support: - Various cleanups and refactorings in preparation to generalize the unwinding code for other architectures (Jens Remus) Uprobes updates: - Transition from kmap_atomic to kmap_local_page (Keke Ming) - Fix incorrect lockdep condition in filter_chain() (Breno Leitao) - Fix XOL allocation failure for 32-bit tasks (Oleg Nesterov) Misc fixes and cleanups: - s390: Remove kvm_types.h from Kbuild (Randy Dunlap) - x86/intel/uncore: Convert comma to semicolon (Chen Ni) - x86/uncore: Clean up const mismatch (Greg Kroah-Hartman) - x86/ibs: Fix typo in dc_l2tlb_miss comment (Xiang-Bin Shi)" * tag 'perf-core-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (58 commits) s390: remove kvm_types.h from Kbuild uprobes: Fix incorrect lockdep condition in filter_chain() x86/ibs: Fix typo in dc_l2tlb_miss comment x86/uprobes: Fix XOL allocation failure for 32-bit tasks perf/x86/intel/uncore: Convert comma to semicolon perf/x86/intel: Add support for rdpmc user disable feature perf/x86: Use macros to replace magic numbers in attr_rdpmc perf/x86/intel: Add core PMU support for Novalake perf/x86/intel: Add support for PEBS memory auxiliary info field in NVL perf/x86/intel: Add core PMU support for DMR perf/x86/intel: Add support for PEBS memory auxiliary info field in DMR perf/x86/intel: Support the 4 new OMR MSRs introduced in DMR and NVL perf/core: Fix slow perf_event_task_exit() with LBR callstacks perf/core: Speed up kexec shutdown by avoiding unnecessary cross CPU calls uprobes: use kmap_local_page() for temporary page mappings arm/uprobes: use kmap_local_page() in arch_uprobe_copy_ixol() mips/uprobes: use kmap_local_page() in arch_uprobe_copy_ixol() arm64/uprobes: use kmap_local_page() in arch_uprobe_copy_ixol() riscv/uprobes: use kmap_local_page() in arch_uprobe_copy_ixol() perf/x86/intel/uncore: Add Nova Lake support ...
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| @@ -1330,14 +1330,16 @@ union perf_mem_data_src { · 1329 unmodified lines | ||
| 1330 | 1330 | mem_snoopx : 2, /* Snoop mode, ext */ |
| 1331 | 1331 | mem_blk : 3, /* Access blocked */ |
| 1332 | 1332 | mem_hops : 3, /* Hop level */ |
| 1333 | − mem_rsvd : 18; | |
| 1333 | + mem_region : 5, /* cache/memory regions */ | |
| 1334 | + mem_rsvd : 13; | |
| 1334 | 1335 | }; |
| 1335 | 1336 | }; |
| 1336 | 1337 | #elif defined(__BIG_ENDIAN_BITFIELD) |
| 1337 | 1338 | union perf_mem_data_src { |
| 1338 | 1339 | __u64 val; |
| 1339 | 1340 | struct { |
| 1340 | − __u64 mem_rsvd : 18, | |
| 1341 | + __u64 mem_rsvd : 13, | |
| 1342 | + mem_region : 5, /* cache/memory regions */ | |
| 1341 | 1343 | mem_hops : 3, /* Hop level */ |
| 1342 | 1344 | mem_blk : 3, /* Access blocked */ |
| 1343 | 1345 | mem_snoopx : 2, /* Snoop mode, ext */ |
| @@ -1394,7 +1396,7 @@ union perf_mem_data_src { · 50 unmodified lines | ||
| 1394 | 1396 | #define PERF_MEM_LVLNUM_L4 0x0004 /* L4 */ |
| 1395 | 1397 | #define PERF_MEM_LVLNUM_L2_MHB 0x0005 /* L2 Miss Handling Buffer */ |
| 1396 | 1398 | #define PERF_MEM_LVLNUM_MSC 0x0006 /* Memory-side Cache */ |
| 1397 | −/* 0x007 available */ | |
| 1399 | +#define PERF_MEM_LVLNUM_L0 0x0007 /* L0 */ | |
| 1398 | 1400 | #define PERF_MEM_LVLNUM_UNC 0x0008 /* Uncached */ |
| 1399 | 1401 | #define PERF_MEM_LVLNUM_CXL 0x0009 /* CXL */ |
| 1400 | 1402 | #define PERF_MEM_LVLNUM_IO 0x000a /* I/O */ |
| @@ -1447,6 +1449,25 @@ union perf_mem_data_src { · 46 unmodified lines | ||
| 1447 | 1449 | /* 5-7 available */ |
| 1448 | 1450 | #define PERF_MEM_HOPS_SHIFT 43 |
| 1449 | 1451 | |
| 1452 | +/* Cache/Memory region */ | |
| 1453 | +#define PERF_MEM_REGION_NA 0x0 /* Invalid */ | |
| 1454 | +#define PERF_MEM_REGION_RSVD 0x01 /* Reserved */ | |
| 1455 | +#define PERF_MEM_REGION_L_SHARE 0x02 /* Local CA shared cache */ | |
| 1456 | +#define PERF_MEM_REGION_L_NON_SHARE 0x03 /* Local CA non-shared cache */ | |
| 1457 | +#define PERF_MEM_REGION_O_IO 0x04 /* Other CA IO agent */ | |
| 1458 | +#define PERF_MEM_REGION_O_SHARE 0x05 /* Other CA shared cache */ | |
| 1459 | +#define PERF_MEM_REGION_O_NON_SHARE 0x06 /* Other CA non-shared cache */ | |
| 1460 | +#define PERF_MEM_REGION_MMIO 0x07 /* MMIO */ | |
| 1461 | +#define PERF_MEM_REGION_MEM0 0x08 /* Memory region 0 */ | |
| 1462 | +#define PERF_MEM_REGION_MEM1 0x09 /* Memory region 1 */ | |
| 1463 | +#define PERF_MEM_REGION_MEM2 0x0a /* Memory region 2 */ | |
| 1464 | +#define PERF_MEM_REGION_MEM3 0x0b /* Memory region 3 */ | |
| 1465 | +#define PERF_MEM_REGION_MEM4 0x0c /* Memory region 4 */ | |
| 1466 | +#define PERF_MEM_REGION_MEM5 0x0d /* Memory region 5 */ | |
| 1467 | +#define PERF_MEM_REGION_MEM6 0x0e /* Memory region 6 */ | |
| 1468 | +#define PERF_MEM_REGION_MEM7 0x0f /* Memory region 7 */ | |
| 1469 | +#define PERF_MEM_REGION_SHIFT 46 | |
| 1470 | + | |
| 1450 | 1471 | #define PERF_MEM_S(a, s) \ |
| 1451 | 1472 | (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) |
| 1452 | 1473 | |