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Merge tag 'perf-urgent-for-mingo-4.17-20180602' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/urgent

Pull perf/urgent fixes from Carvalho de Melo: - Update prctl and cpufeatures.h tools/ copies with the kernel sources originals, which makes 'perf trace' know about the new prctl options for speculation control and silences the build warnings (Arnaldo Carvalho de Melo) - Update insn.h in Intel-PT instruction decoder with its original from from the kernel sources, to silence build warnings, no effect on the actual tools this time around (Arnaldo Carvalho de Melo)

Ingo Molnar committed 8 years ago

Commit 4e9ae0d2 parents 874cd33 0b3a1834 files · +45 −7Browse files

Unified · Split

4 files
  1. tools/arch/x86/include/asm/cpufeatures.h +14 −6
  2. tools/include/uapi/linux/prctl.h +12 −0
  3. tools/perf/trace/beauty/prctl_option.sh +1 −1
  4. tools/perf/util/intel-pt-decoder/insn.h +18 −0
tools/arch/x86/include/asm/cpufeatures.h+14−6
@@ -198,7 +198,6 @@ · 197 unmodified lines
198198 #define X86_FEATURE_CAT_L2 ( 7*32+ 5) /* Cache Allocation Technology L2 */
199199 #define X86_FEATURE_CDP_L3 ( 7*32+ 6) /* Code and Data Prioritization L3 */
200200 #define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 7) /* Effectively INVPCID && CR4.PCIDE=1 */
201−
202201 #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */
203202 #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
204203 #define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */
@@ -207,13 +206,19 @@ · 2 unmodified lines
207206 #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */
208207 #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */
209208 #define X86_FEATURE_CDP_L2 ( 7*32+15) /* Code and Data Prioritization L2 */
210−
209+#define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16) /* "" MSR SPEC_CTRL is implemented */
210+#define X86_FEATURE_SSBD ( 7*32+17) /* Speculative Store Bypass Disable */
211211 #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */
212212 #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* "" Fill RSB on context switches */
213213 #define X86_FEATURE_SEV ( 7*32+20) /* AMD Secure Encrypted Virtualization */
214−
215214 #define X86_FEATURE_USE_IBPB ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */
216215 #define X86_FEATURE_USE_IBRS_FW ( 7*32+22) /* "" Use IBRS during runtime firmware calls */
216+#define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */
217+#define X86_FEATURE_LS_CFG_SSBD ( 7*32+24) /* "" AMD SSBD implementation via LS_CFG MSR */
218+#define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */
219+#define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */
220+#define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */
221+#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */
217222
218223 /* Virtualization flags: Linux defined, word 8 */
219224 #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
@@ -274,9 +279,10 @@ · 54 unmodified lines
274279 #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
275280 #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */
276281 #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */
277−#define X86_FEATURE_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */
278−#define X86_FEATURE_IBRS (13*32+14) /* Indirect Branch Restricted Speculation */
279−#define X86_FEATURE_STIBP (13*32+15) /* Single Thread Indirect Branch Predictors */
282+#define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */
283+#define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */
284+#define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */
285+#define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */
280286
281287 /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
282288 #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
@@ -334,6 +340,7 @@ · 51 unmodified lines
334340 #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
335341 #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
336342 #define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
343+#define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */
337344
338345 /*
339346 * BUG word(s)
@@ -363,5 +370,6 @@ · 23 unmodified lines
363370 #define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel page table isolation */
364371 #define X86_BUG_SPECTRE_V1 X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditional branches */
365372 #define X86_BUG_SPECTRE_V2 X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */
373+#define X86_BUG_SPEC_STORE_BYPASS X86_BUG(17) /* CPU is affected by speculative store bypass attack */
366374
367375 #endif /* _ASM_X86_CPUFEATURES_H */
tools/include/uapi/linux/prctl.h+12−0
@@ -207,4 +207,16 @@ struct prctl_mm_map { · 206 unmodified lines
207207 # define PR_SVE_VL_LEN_MASK 0xffff
208208 # define PR_SVE_VL_INHERIT (1 << 17) /* inherit across exec */
209209
210+/* Per task speculation control */
211+#define PR_GET_SPECULATION_CTRL 52
212+#define PR_SET_SPECULATION_CTRL 53
213+/* Speculation control variants */
214+# define PR_SPEC_STORE_BYPASS 0
215+/* Return and control values for PR_SET/GET_SPECULATION_CTRL */
216+# define PR_SPEC_NOT_AFFECTED 0
217+# define PR_SPEC_PRCTL (1UL << 0)
218+# define PR_SPEC_ENABLE (1UL << 1)
219+# define PR_SPEC_DISABLE (1UL << 2)
220+# define PR_SPEC_FORCE_DISABLE (1UL << 3)
221+
210222 #endif /* _LINUX_PRCTL_H */
tools/perf/trace/beauty/prctl_option.sh+1−1
@@ -1,6 +1,6 @@
11 #!/bin/sh
22
3−header_dir=$1
3+[ $# -eq 1 ] && header_dir=$1 || header_dir=tools/include/uapi/linux/
44
55 printf "static const char *prctl_options[] = {\n"
66 regex='^#define[[:space:]]+PR_([GS]ET\w+)[[:space:]]*([[:xdigit:]]+).*'
tools/perf/util/intel-pt-decoder/insn.h+18−0
@@ -208,4 +208,22 @@ static inline int insn_offset_immediate(struct insn *insn) · 207 unmodified lines
208208 return insn_offset_displacement(insn) + insn->displacement.nbytes;
209209 }
210210
211+#define POP_SS_OPCODE 0x1f
212+#define MOV_SREG_OPCODE 0x8e
213+
214+/*
215+ * Intel SDM Vol.3A 6.8.3 states;
216+ * "Any single-step trap that would be delivered following the MOV to SS
217+ * instruction or POP to SS instruction (because EFLAGS.TF is 1) is
218+ * suppressed."
219+ * This function returns true if @insn is MOV SS or POP SS. On these
220+ * instructions, single stepping is suppressed.
221+ */
222+static inline int insn_masking_exception(struct insn *insn)
223+{
224+ return insn->opcode.bytes[0] == POP_SS_OPCODE ||
225+ (insn->opcode.bytes[0] == MOV_SREG_OPCODE &&
226+ X86_MODRM_REG(insn->modrm.bytes[0]) == 2);
227+}
228+
211229 #endif /* _ASM_X86_INSN_H */