Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd: "We've finally gotten rid of the struct clk_ops::round_rate() code after months of effort from Brian Masney. Now the only option is to use determine_rate(), which is good because that takes a struct argument instead of just a couple unsigned longs, allowing us to easily modify the way we determine and set rates in the clk tree. Beyond that core framework change we've got the typical pile of new SoC clk driver additions, fixes for clk data and/or adding missing clks because the consumer driver using those clks wasn't ready, etc. The usual suspects are all here: Qualcomm, Samsung, Mediatek, and Rockchip along with some newcomers making RISC-V SoCs like ESWIN's eic700 and Tenstorrent's Atlantis. The clk driver side of this looks pretty normal. Core: - Remove the round_rate() clk op (yay!) New Drivers: - ESWIN eic700 SoC clk support - Econet EN751221 SoC clock/reset support - Global TCSR, RPMh, and display clock controller support for the Qualcomm Eliza platform - TCSR, the multiple global, and the RPMh clock controller support for the Qualcomm Nord platform - GPU clock controller support for Qualcomm SM8750 - Video and GPU clock controller support for Qualcomm Glymur - Global clock controller support for Qualcomm IPQ5210 - Axis ARTPEC-9: Add new PLL clocks and new drivers for eight clock controllers on the SoC - ExynosAutov920: Add G3D (GPU) clock controller - Clock driver for the Rockchip RV1103B SoC - Initial support for the Renesas RZ/G3L (R9A08G046) SoC - Clock and reset controllers (e.g. PRCM) in the Tenstorrent Atlantis SoC" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (132 commits) clk: visconti: pll: initialize clk_init_data to zero clk: fsl-sai: Add MCLK generation support clk: fsl-sai: Extract clock setup into fsl_sai_clk_register() dt-bindings: clock: fsl-sai: Document clock-cells = <1> support clk: fsl-sai: Add i.MX8M support with 8 byte register offset clk: fsl-sai: Sort the headers dt-bindings: clock: fsl-sai: Document i.MX8M support clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC clk: qcom: rpmh: Add support for Nord rpmh clocks clk: qcom: Add TCSR clock driver for Nord SoC dt-bindings: clock: qcom: Add Nord Global Clock Controller dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller clk: qcom: gcc-x1e80100: Keep GCC USB QTB clock always ON clk: qcom: Constify list of critical CBCR registers clk: qcom: Constify qcom_cc_driver_data clk: qcom: videocc-glymur: Constify qcom_cc_desc clk: qcom: Add a driver for SM8750 GPU clocks dt-bindings: clock: qcom: Add SM8750 GPU clocks clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support ...

Linus Torvalds committed 6 months ago

Commit 4ee64202 parents a85d6ff 6b701fd179 files · +24821 −3464Browse files

Unified · Split

179 files

Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml +5 −1
Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml +0 −196
Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml +0 −131
Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml +46 −0
Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml +36 −7
Documentation/devicetree/bindings/clock/imx6q-clock.yaml +4 −0
Documentation/devicetree/bindings/clock/imx6ul-clock.yaml +4 −0
Documentation/devicetree/bindings/clock/qcom,eliza-dispcc.yaml +96 −0
Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml +2 −2
Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml +2 −0
Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml +2 −0
Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml +7 −0
Documentation/devicetree/bindings/clock/qcom,nord-gcc.yaml +58 −0
Documentation/devicetree/bindings/clock/qcom,nord-negcc.yaml +60 −0
Documentation/devicetree/bindings/clock/qcom,nord-nwgcc.yaml +55 −0
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +1 −0
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +26 −1
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +3 −0
Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml +2 −0
Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml +21 −0
Documentation/devicetree/bindings/clock/tenstorrent,atlantis-prcm-rcpu.yaml +54 −0
Documentation/devicetree/bindings/mfd/syscon.yaml +2 −0
Documentation/driver-api/clk.rst +1 −8
MAINTAINERS +14 −0
drivers/clk/Kconfig +6 −5
drivers/clk/Makefile +2 −1
drivers/clk/baikal-t1/Kconfig +0 −52
drivers/clk/baikal-t1/Makefile +0 −4
drivers/clk/baikal-t1/ccu-div.c +0 −653
drivers/clk/baikal-t1/ccu-div.h +0 −121
drivers/clk/baikal-t1/ccu-pll.c +0 −560
drivers/clk/baikal-t1/ccu-pll.h +0 −72
drivers/clk/baikal-t1/ccu-rst.c +0 −217
drivers/clk/baikal-t1/ccu-rst.h +0 −67
drivers/clk/baikal-t1/clk-ccu-div.c +0 −520
drivers/clk/baikal-t1/clk-ccu-pll.c +0 −277
drivers/clk/bcm/clk-raspberrypi.c +34 −4
drivers/clk/clk-composite.c +5 −33
drivers/clk/clk-divider.c +0 −44
drivers/clk/clk-en7523.c +218 −5
drivers/clk/clk-fsl-sai.c +118 −30
drivers/clk/clk-qoriq.c +9 −8
drivers/clk/clk-xgene.c +2 −0
drivers/clk/clk.c +17 −29
drivers/clk/clk_test.c +8 −8
drivers/clk/eswin/Kconfig +15 −0
drivers/clk/eswin/Makefile +8 −0
drivers/clk/eswin/clk-eic7700.c +1376 −0
drivers/clk/eswin/clk.c +586 −0
drivers/clk/eswin/common.h +340 −0
drivers/clk/imx/clk-fracn-gppll.c +2 −0
drivers/clk/imx/clk-imx6q.c +11 −1
drivers/clk/imx/clk-imx8-acm.c +2 −1
drivers/clk/imx/clk-imx8mq.c +2 −2
drivers/clk/imx/clk-pll14xx.c +3 −3
drivers/clk/imx/clk-vf610.c +12 −0
drivers/clk/microchip/clk-mpfs-ccc.c +5 −1
drivers/clk/mvebu/armada-37xx-periph.c +9 −7
drivers/clk/qcom/Kconfig +86 −8
drivers/clk/qcom/Makefile +9 −0
drivers/clk/qcom/apss-ipq5424.c +1 −1
drivers/clk/qcom/cambistmclkcc-kaanapali.c +2 −4
drivers/clk/qcom/cambistmclkcc-sm8750.c +2 −2
drivers/clk/qcom/camcc-kaanapali.c +2 −4
drivers/clk/qcom/camcc-milos.c +2 −2
drivers/clk/qcom/camcc-qcs615.c +1 −1
drivers/clk/qcom/camcc-sc8180x.c +32 −35
drivers/clk/qcom/camcc-sm8450.c +2 −2
drivers/clk/qcom/camcc-sm8550.c +2 −2
drivers/clk/qcom/camcc-sm8650.c +2 −2
drivers/clk/qcom/camcc-sm8750.c +2 −2
drivers/clk/qcom/camcc-x1e80100.c +2 −2
drivers/clk/qcom/clk-rcg2.c +2 −0
drivers/clk/qcom/clk-rpmh.c +46 −0
drivers/clk/qcom/common.h +2 −2
drivers/clk/qcom/dispcc-eliza.c +2121 −0
drivers/clk/qcom/dispcc-glymur.c +4 −8
drivers/clk/qcom/dispcc-kaanapali.c +2 −6
drivers/clk/qcom/dispcc-milos.c +3 −6
drivers/clk/qcom/dispcc-qcs615.c +2 −2
drivers/clk/qcom/dispcc-sc7180.c +8 −0
drivers/clk/qcom/dispcc-sc8280xp.c +0 −4
drivers/clk/qcom/dispcc-sm4450.c +0 −1
drivers/clk/qcom/dispcc-sm6115.c +7 −0
drivers/clk/qcom/dispcc-sm6125.c +7 −0
drivers/clk/qcom/dispcc-sm8250.c +3 −3
drivers/clk/qcom/dispcc-sm8450.c +1 −1
drivers/clk/qcom/dispcc0-sa8775p.c +0 −2
drivers/clk/qcom/dispcc1-sa8775p.c +0 −2
drivers/clk/qcom/gcc-eliza.c +3105 −0
drivers/clk/qcom/gcc-glymur.c +4 −4
drivers/clk/qcom/gcc-ipq5210.c +2661 −0
drivers/clk/qcom/gcc-ipq6018.c +1 −1
drivers/clk/qcom/gcc-kaanapali.c +2 −3
drivers/clk/qcom/gcc-milos.c +2 −2
drivers/clk/qcom/gcc-nord.c +1902 −0
drivers/clk/qcom/gcc-sc8180x.c +89 −37
drivers/clk/qcom/gcc-x1e80100.c +1 −0
drivers/clk/qcom/gdsc.c +11 −1
drivers/clk/qcom/gpucc-glymur.c +618 −0
drivers/clk/qcom/gpucc-kaanapali.c +2 −3
drivers/clk/qcom/gpucc-milos.c +2 −2
drivers/clk/qcom/gpucc-qcs615.c +2 −2
drivers/clk/qcom/gpucc-sm8750.c +473 −0
drivers/clk/qcom/gxclkctl-kaanapali.c +2 −1
drivers/clk/qcom/ipq-cmn-pll.c +16 −0
drivers/clk/qcom/negcc-nord.c +1987 −0
drivers/clk/qcom/nwgcc-nord.c +688 −0
drivers/clk/qcom/segcc-nord.c +1609 −0
drivers/clk/qcom/tcsrcc-eliza.c +179 −0
drivers/clk/qcom/tcsrcc-glymur.c +1 −2
drivers/clk/qcom/tcsrcc-kaanapali.c +0 −1
drivers/clk/qcom/tcsrcc-nord.c +337 −0
drivers/clk/qcom/tcsrcc-sm8750.c +1 −1
drivers/clk/qcom/videocc-glymur.c +532 −0
drivers/clk/qcom/videocc-kaanapali.c +2 −2
drivers/clk/qcom/videocc-milos.c +2 −2
drivers/clk/qcom/videocc-qcs615.c +2 −2
drivers/clk/qcom/videocc-sm8450.c +2 −2
drivers/clk/qcom/videocc-sm8550.c +2 −2
drivers/clk/qcom/videocc-sm8750.c +2 −3
drivers/clk/renesas/Kconfig +6 −1
drivers/clk/renesas/Makefile +1 −0
drivers/clk/renesas/r9a06g032-clocks.c +3 −2
drivers/clk/renesas/r9a07g043-cpg.c +9 −0
drivers/clk/renesas/r9a07g044-cpg.c +13 −0
drivers/clk/renesas/r9a08g045-cpg.c +9 −0
drivers/clk/renesas/r9a08g046-cpg.c +153 −0
drivers/clk/renesas/r9a09g047-cpg.c +29 −0
drivers/clk/renesas/r9a09g056-cpg.c +27 −33
drivers/clk/renesas/r9a09g057-cpg.c +25 −35
drivers/clk/renesas/renesas-cpg-mssr.c +2 −2
drivers/clk/renesas/rzg2l-cpg.c +78 −13
drivers/clk/renesas/rzg2l-cpg.h +8 −0
drivers/clk/rockchip/Kconfig +7 −0
drivers/clk/rockchip/Makefile +1 −0
drivers/clk/rockchip/clk-rk3568.c +6 −0
drivers/clk/rockchip/clk-rv1103b.c +658 −0
drivers/clk/rockchip/clk.h +49 −0
drivers/clk/samsung/Makefile +1 −0
drivers/clk/samsung/clk-artpec9.c +1224 −0
drivers/clk/samsung/clk-exynos850.c +6 −1
drivers/clk/samsung/clk-exynosautov920.c +52 −0
drivers/clk/samsung/clk-gs101.c +26 −26
drivers/clk/samsung/clk-pll.c +177 −8
drivers/clk/samsung/clk-pll.h +17 −0
drivers/clk/samsung/clk.c +2 −2
drivers/clk/spacemit/ccu_mix.c +1 −1
drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c +16 −1
drivers/clk/tenstorrent/Kconfig +14 −0
drivers/clk/tenstorrent/Makefile +3 −0
drivers/clk/tenstorrent/atlantis-prcm.c +870 −0
drivers/clk/visconti/pll.c +1 −1
drivers/reset/Kconfig +11 −0
drivers/reset/Makefile +1 −0
drivers/reset/reset-tenstorrent-atlantis.c +173 −0
include/dt-bindings/clock/bt1-ccu.h +0 −48
include/dt-bindings/clock/econet,en751221-scu.h +12 −0
include/dt-bindings/clock/eswin,eic7700-clock.h +285 −0
include/dt-bindings/clock/exynos850.h +1 −0
include/dt-bindings/clock/qcom,dispcc-sc7180.h +6 −1
include/dt-bindings/clock/qcom,eliza-dispcc.h +118 −0
include/dt-bindings/clock/qcom,gcc-sc8180x.h +5 −0
include/dt-bindings/clock/qcom,glymur-gcc.h +1 −0
include/dt-bindings/clock/qcom,glymur-gpucc.h +51 −0
include/dt-bindings/clock/qcom,glymur-videocc.h +45 −0
include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h +15 −0
include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h +15 −0
include/dt-bindings/clock/qcom,nord-gcc.h +147 −0
include/dt-bindings/clock/qcom,nord-negcc.h +124 −0
include/dt-bindings/clock/qcom,nord-nwgcc.h +69 −0
include/dt-bindings/clock/qcom,nord-segcc.h +98 −0
include/dt-bindings/clock/qcom,nord-tcsrcc.h +26 −0
include/dt-bindings/clock/qcom,sm8750-gpucc.h +50 −0
include/dt-bindings/clock/samsung,exynosautov920.h +6 −0
include/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h +103 −0
include/dt-bindings/clock/vf610-clock.h +5 −1
include/dt-bindings/reset/econet,en751221-scu.h +49 −0
include/linux/clk-provider.h +26 −40

Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml+5−1

@@ -32,6 +32,7 @@ properties: · 31 unmodified lines
32	32	- enum:
33	33	- airoha,en7523-scu
34	34	- airoha,en7581-scu
	35	+ - econet,en751221-scu
35	36
36	37	reg:
37	38	items:
@@ -67,7 +68,9 @@ allOf: · 29 unmodified lines
67	68	- if:
68	69	properties:
69	70	compatible:
70		− const: airoha,en7581-scu
	71	+ enum:
	72	+ - airoha,en7581-scu
	73	+ - econet,en751221-scu
71	74	then:
72	75	properties:
73	76	reg:
@@ -98,3 +101,4 @@ examples: · 24 unmodified lines
98	101	#reset-cells = <1>;
99	102	};
100	103	};
	104	+

Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml+0−196

@@ -1,196 +0,0 @@
1		−# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2		−# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
3		−%YAML 1.2
4		−---
5		−$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6		−$schema: http://devicetree.org/meta-schemas/core.yaml#
7		−
8		−title: Baikal-T1 Clock Control Unit Dividers
9		−
10		−maintainers:
11		− - Serge Semin <fancer.lancer@gmail.com>
12		−
13		−description: \|
14		− Clocks Control Unit is the core of Baikal-T1 SoC System Controller
15		− responsible for the chip subsystems clocking and resetting. The CCU is
16		− connected with an external fixed rate oscillator, which signal is transformed
17		− into clocks of various frequencies and then propagated to either individual
18		− IP-blocks or to groups of blocks (clock domains). The transformation is done
19		− by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
20		− later ones are described in this binding. Each clock domain can be also
21		− individually reset by using the domain clocks divider configuration
22		− registers. Baikal-T1 CCU is logically divided into the next components:
23		− 1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
24		− in general can provide any frequency supported by the CCU PLLs).
25		− 2) PLLs clocks generators (PLLs).
26		− 3) AXI-bus clock dividers (AXI) - described in this binding file.
27		− 4) System devices reference clock dividers (SYS) - described in this binding
28		− file.
29		− which are connected with each other as shown on the next figure:
30		−
31		− +---------------+
32		− \| Baikal-T1 CCU \|
33		− \| +----+------\|- MIPS P5600 cores
34		− \| +-\|PLLs\|------\|- DDR controller
35		− \| \| +----+ \|
36		− +----+ \| \| \| \| \|
37		− \|XTAL\|--\|-+ \| \| +---+-\|
38		− +----+ \| \| \| +-\|AXI\|-\|- AXI-bus
39		− \| \| \| +---+-\|
40		− \| \| \| \|
41		− \| \| +----+---+-\|- APB-bus
42		− \| +-------\|SYS\|-\|- Low-speed Devices
43		− \| +---+-\|- High-speed Devices
44		− +---------------+
45		−
46		− Each sub-block is represented as a separate DT node and has an individual
47		− driver to be bound with.
48		−
49		− In order to create signals of wide range frequencies the external oscillator
50		− output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are
51		− then passed over CCU dividers to create signals required for the target clock
52		− domain (like AXI-bus or System Device consumers). The dividers have the
53		− following structure:
54		−
55		− +--------------+
56		− CLKIN --\|->+----+ 1\|\ \|
57		− SETCLK--\|--\|/DIV\|->\| \| \|
58		− CLKDIV--\|--\| \| \| \|-\|->CLKLOUT
59		− LOCK----\|--+----+ \| \| \|
60		− \| \|/ \|
61		− \| \| \|
62		− EN------\|-----------+ \|
63		− RST-----\|--------------\|->RSTOUT
64		− +--------------+
65		−
66		− where CLKIN is the reference clock coming either from CCU PLLs or from an
67		− external clock oscillator, SETCLK - a command to update the output clock in
68		− accordance with a set divider, CLKDIV - clocks divider, LOCK - a signal of
69		− the output clock stabilization, EN - enable/disable the divider block,
70		− RST/RSTOUT - reset clocks domain signal. Depending on the consumer IP-core
71		− peculiarities the dividers may lack of some functionality depicted on the
72		− figure above (like EN, CLKDIV/LOCK/SETCLK). In this case the corresponding
73		− clock provider just doesn't expose either switching functions, or the rate
74		− configuration, or both of them.
75		−
76		− The clock dividers, which output clock is then consumed by the SoC individual
77		− devices, are united into a single clocks provider called System Devices CCU.
78		− Similarly the dividers with output clocks utilized as AXI-bus reference clocks
79		− are called AXI-bus CCU. Both of them use the common clock bindings with no
80		− custom properties. The list of exported clocks and reset signals can be found
81		− in the files: 'include/dt-bindings/clock/bt1-ccu.h' and
82		− 'include/dt-bindings/reset/bt1-ccu.h'. Since System Devices and AXI-bus CCU
83		− are a part of the Baikal-T1 SoC System Controller their DT nodes are supposed
84		− to be a children of later one.
85		−
86		−if:
87		− properties:
88		− compatible:
89		− contains:
90		− const: baikal,bt1-ccu-axi
91		−
92		−then:
93		− properties:
94		− clocks:
95		− items:
96		− - description: CCU SATA PLL output clock
97		− - description: CCU PCIe PLL output clock
98		− - description: CCU Ethernet PLL output clock
99		−
100		− clock-names:
101		− items:
102		− - const: sata_clk
103		− - const: pcie_clk
104		− - const: eth_clk
105		−
106		−else:
107		− properties:
108		− clocks:
109		− items:
110		− - description: External reference clock
111		− - description: CCU SATA PLL output clock
112		− - description: CCU PCIe PLL output clock
113		− - description: CCU Ethernet PLL output clock
114		−
115		− clock-names:
116		− items:
117		− - const: ref_clk
118		− - const: sata_clk
119		− - const: pcie_clk
120		− - const: eth_clk
121		−
122		−properties:
123		− compatible:
124		− enum:
125		− - baikal,bt1-ccu-axi
126		− - baikal,bt1-ccu-sys
127		−
128		− reg:
129		− maxItems: 1
130		−
131		− "#clock-cells":
132		− const: 1
133		−
134		− "#reset-cells":
135		− const: 1
136		−
137		− clocks:
138		− minItems: 3
139		− maxItems: 4
140		−
141		− clock-names:
142		− minItems: 3
143		− maxItems: 4
144		−
145		−additionalProperties: false
146		−
147		−required:
148		− - compatible
149		− - "#clock-cells"
150		− - clocks
151		− - clock-names
152		−
153		−examples:
154		− # AXI-bus Clock Control Unit node:
155		− - \|
156		− #include <dt-bindings/clock/bt1-ccu.h>
157		−
158		− clock-controller@1f04d030 {
159		− compatible = "baikal,bt1-ccu-axi";
160		− reg = <0x1f04d030 0x030>;
161		− #clock-cells = <1>;
162		− #reset-cells = <1>;
163		−
164		− clocks = <&ccu_pll CCU_SATA_PLL>,
165		− <&ccu_pll CCU_PCIE_PLL>,
166		− <&ccu_pll CCU_ETH_PLL>;
167		− clock-names = "sata_clk", "pcie_clk", "eth_clk";
168		− };
169		− # System Devices Clock Control Unit node:
170		− - \|
171		− #include <dt-bindings/clock/bt1-ccu.h>
172		−
173		− clock-controller@1f04d060 {
174		− compatible = "baikal,bt1-ccu-sys";
175		− reg = <0x1f04d060 0x0a0>;
176		− #clock-cells = <1>;
177		− #reset-cells = <1>;
178		−
179		− clocks = <&clk25m>,
180		− <&ccu_pll CCU_SATA_PLL>,
181		− <&ccu_pll CCU_PCIE_PLL>,
182		− <&ccu_pll CCU_ETH_PLL>;
183		− clock-names = "ref_clk", "sata_clk", "pcie_clk",
184		− "eth_clk";
185		− };
186		− # Required Clock Control Unit PLL node:
187		− - \|
188		− ccu_pll: clock-controller@1f04d000 {
189		− compatible = "baikal,bt1-ccu-pll";
190		− reg = <0x1f04d000 0x028>;
191		− #clock-cells = <1>;
192		−
193		− clocks = <&clk25m>;
194		− clock-names = "ref_clk";
195		− };
196		−...

Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml+0−131

@@ -1,131 +0,0 @@
1		−# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2		−# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
3		−%YAML 1.2
4		−---
5		−$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6		−$schema: http://devicetree.org/meta-schemas/core.yaml#
7		−
8		−title: Baikal-T1 Clock Control Unit PLL
9		−
10		−maintainers:
11		− - Serge Semin <fancer.lancer@gmail.com>
12		−
13		−description: \|
14		− Clocks Control Unit is the core of Baikal-T1 SoC System Controller
15		− responsible for the chip subsystems clocking and resetting. The CCU is
16		− connected with an external fixed rate oscillator, which signal is transformed
17		− into clocks of various frequencies and then propagated to either individual
18		− IP-blocks or to groups of blocks (clock domains). The transformation is done
19		− by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
20		− It's logically divided into the next components:
21		− 1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
22		− in general can provide any frequency supported by the CCU PLLs).
23		− 2) PLLs clocks generators (PLLs) - described in this binding file.
24		− 3) AXI-bus clock dividers (AXI).
25		− 4) System devices reference clock dividers (SYS).
26		− which are connected with each other as shown on the next figure:
27		−
28		− +---------------+
29		− \| Baikal-T1 CCU \|
30		− \| +----+------\|- MIPS P5600 cores
31		− \| +-\|PLLs\|------\|- DDR controller
32		− \| \| +----+ \|
33		− +----+ \| \| \| \| \|
34		− \|XTAL\|--\|-+ \| \| +---+-\|
35		− +----+ \| \| \| +-\|AXI\|-\|- AXI-bus
36		− \| \| \| +---+-\|
37		− \| \| \| \|
38		− \| \| +----+---+-\|- APB-bus
39		− \| +-------\|SYS\|-\|- Low-speed Devices
40		− \| +---+-\|- High-speed Devices
41		− +---------------+
42		−
43		− Each CCU sub-block is represented as a separate dts-node and has an
44		− individual driver to be bound with.
45		−
46		− In order to create signals of wide range frequencies the external oscillator
47		− output is primarily connected to a set of CCU PLLs. There are five PLLs
48		− to create a clock for the MIPS P5600 cores, the embedded DDR controller,
49		− SATA, Ethernet and PCIe domains. The last three domains though named by the
50		− biggest system interfaces in fact include nearly all of the rest SoC
51		− peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core
52		− with an interface wrapper (so called safe PLL' clocks switcher) to simplify
53		− the PLL configuration procedure. The PLLs work as depicted on the next
54		− diagram:
55		−
56		− +--------------------------+
57		− \| \|
58		− +-->+---+ +---+ +---+ \| +---+ 0\|\
59		− CLKF--->\|/NF\|--->\|PFD\|...\|VCO\|-+->\|/OD\|--->\| \|
60		− +---+ +->+---+ +---+ /->+---+ \| \|--->CLKOUT
61		− CLKOD---------C----------------+ 1\| \|
62		− +--------C--------------------------->\|/
63		− \| \| ^
64		− Rclk-+->+---+ \| \|
65		− CLKR--->\|/NR\|-+ \|
66		− +---+ \|
67		− BYPASS--------------------------------------+
68		− BWADJ--->
69		−
70		− where Rclk is the reference clock coming from XTAL, NR - reference clock
71		− divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -
72		− output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment
73		− the binding supports the PLL dividers configuration in accordance with a
74		− requested rate, while bypassing and bandwidth adjustment settings can be
75		− added in future if it gets to be necessary.
76		−
77		− The PLLs CLKOUT is then either directly connected with the corresponding
78		− clocks consumer (like P5600 cores or DDR controller) or passed over a CCU
79		− divider to create a signal required for the clock domain.
80		−
81		− The CCU PLL dts-node uses the common clock bindings with no custom
82		− parameters. The list of exported clocks can be found in
83		− 'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the
84		− Baikal-T1 SoC System Controller its DT node is supposed to be a child of
85		− later one.
86		−
87		−properties:
88		− compatible:
89		− const: baikal,bt1-ccu-pll
90		−
91		− reg:
92		− maxItems: 1
93		−
94		− "#clock-cells":
95		− const: 1
96		−
97		− clocks:
98		− description: External reference clock
99		− maxItems: 1
100		−
101		− clock-names:
102		− const: ref_clk
103		−
104		−additionalProperties: false
105		−
106		−required:
107		− - compatible
108		− - "#clock-cells"
109		− - clocks
110		− - clock-names
111		−
112		−examples:
113		− # Clock Control Unit PLL node:
114		− - \|
115		− clock-controller@1f04d000 {
116		− compatible = "baikal,bt1-ccu-pll";
117		− reg = <0x1f04d000 0x028>;
118		− #clock-cells = <1>;
119		−
120		− clocks = <&clk25m>;
121		− clock-names = "ref_clk";
122		− };
123		− # Required external oscillator:
124		− - \|
125		− clk25m: clock-oscillator-25m {
126		− compatible = "fixed-clock";
127		− #clock-cells = <0>;
128		− clock-frequency = <25000000>;
129		− clock-output-names = "clk25m";
130		− };
131		−...

Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml+46−0

@@ -0,0 +1,46 @@
	1	+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	+%YAML 1.2
	3	+---
	4	+$id: http://devicetree.org/schemas/clock/eswin,eic7700-clock.yaml#
	5	+$schema: http://devicetree.org/meta-schemas/core.yaml#
	6	+
	7	+title: Eswin EIC7700 SoC clock controller
	8	+
	9	+maintainers:
	10	+ - Yifeng Huang <huangyifeng@eswincomputing.com>
	11	+ - Xuyang Dong <dongxuyang@eswincomputing.com>
	12	+
	13	+description:
	14	+ The clock controller generates and supplies clock to all the modules
	15	+ for eic7700 SoC.
	16	+
	17	+properties:
	18	+ compatible:
	19	+ const: eswin,eic7700-clock
	20	+
	21	+ reg:
	22	+ maxItems: 1
	23	+
	24	+ clocks:
	25	+ items:
	26	+ - description: External 24MHz oscillator clock
	27	+
	28	+ '#clock-cells':
	29	+ const: 1
	30	+
	31	+required:
	32	+ - compatible
	33	+ - reg
	34	+ - clocks
	35	+ - '#clock-cells'
	36	+
	37	+additionalProperties: false
	38	+
	39	+examples:
	40	+ - \|
	41	+ clock-controller@51828000 {
	42	+ compatible = "eswin,eic7700-clock";
	43	+ reg = <0x51828000 0x300>;
	44	+ clocks = <&xtal24m>;
	45	+ #clock-cells = <1>;
	46	+ };

Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml+36−7

@@ -10,10 +10,10 @@ maintainers: · 9 unmodified lines
10	10	- Michael Walle <michael@walle.cc>
11	11
12	12	description: \|
13		− It is possible to use the BCLK pin of a SAI module as a generic clock
14		− output. Some SoC are very constrained in their pin multiplexer
15		− configuration. Eg. pins can only be changed groups. For example, on the
16		− LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
	13	+ It is possible to use the BCLK or MCLK pin of a SAI module as a generic
	14	+ clock output. Some SoC are very constrained in their pin multiplexer
	15	+ configuration. E.g. pins can only be changed in groups. For example, on
	16	+ the LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
17	17	the second pins are wasted. Using this binding it is possible to use the
18	18	clock of the second SAI as a MCLK clock for an audio codec, for example.
19	19
@@ -21,16 +21,45 @@ description: \| · 1 unmodified line
21	21
22	22	properties:
23	23	compatible:
24		− const: fsl,vf610-sai-clock
	24	+ oneOf:
	25	+ - items:
	26	+ - enum:
	27	+ - fsl,imx8mm-sai-clock
	28	+ - fsl,imx8mn-sai-clock
	29	+ - fsl,imx8mp-sai-clock
	30	+ - const: fsl,imx8mq-sai-clock
	31	+ - items:
	32	+ - enum:
	33	+ - fsl,imx8mq-sai-clock
	34	+ - fsl,vf610-sai-clock
25	35
26	36	reg:
27	37	maxItems: 1
28	38
29	39	clocks:
30		− maxItems: 1
	40	+ minItems: 1
	41	+ maxItems: 2
	42	+
	43	+ clock-names:
	44	+ minItems: 1
	45	+ items:
	46	+ - const: bus
	47	+ - const: mclk1
31	48
32	49	'#clock-cells':
33		− const: 0
	50	+ maximum: 1
	51	+
	52	+allOf:
	53	+ - if:
	54	+ properties:
	55	+ compatible:
	56	+ contains:
	57	+ const: fsl,vf610-sai-clock
	58	+ then:
	59	+ properties:
	60	+ clocks:
	61	+ maxItems: 1
	62	+ clock-names: false
34	63
35	64	required:
36	65	- compatible

Documentation/devicetree/bindings/clock/imx6q-clock.yaml+4−0

@@ -29,20 +29,24 @@ properties: · 28 unmodified lines
29	29	const: 1
30	30
31	31	clocks:
	32	+ minItems: 5
32	33	items:
33	34	- description: 24m osc
34	35	- description: 32k osc
35	36	- description: ckih1 clock input
36	37	- description: anaclk1 clock input
37	38	- description: anaclk2 clock input
	39	+ - description: clock input from enet ref pad
38	40
39	41	clock-names:
	42	+ minItems: 5
40	43	items:
41	44	- const: osc
42	45	- const: ckil
43	46	- const: ckih1
44	47	- const: anaclk1
45	48	- const: anaclk2
	49	+ - const: enet_ref_pad
46	50
47	51	fsl,pmic-stby-poweroff:
48	52	$ref: /schemas/types.yaml#/definitions/flag

Documentation/devicetree/bindings/clock/imx6ul-clock.yaml+4−0

@@ -29,18 +29,22 @@ properties: · 28 unmodified lines
29	29	const: 1
30	30
31	31	clocks:
	32	+ minItems: 4
32	33	items:
33	34	- description: 32k osc
34	35	- description: 24m osc
35	36	- description: ipp_di0 clock input
36	37	- description: ipp_di1 clock input
	38	+ - description: clock input from enet1 ref pad
37	39
38	40	clock-names:
	41	+ minItems: 4
39	42	items:
40	43	- const: ckil
41	44	- const: osc
42	45	- const: ipp_di0
43	46	- const: ipp_di1
	47	+ - const: enet1_ref_pad
44	48
45	49	required:
46	50	- compatible

Documentation/devicetree/bindings/clock/qcom,eliza-dispcc.yaml+96−0

@@ -0,0 +1,96 @@
	1	+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	+%YAML 1.2
	3	+---
	4	+$id: http://devicetree.org/schemas/clock/qcom,eliza-dispcc.yaml#
	5	+$schema: http://devicetree.org/meta-schemas/core.yaml#
	6	+
	7	+title: Display Clock & Reset Controller for Qualcomm Eliza SoC
	8	+
	9	+maintainers:
	10	+ - Bjorn Andersson <andersson@kernel.org>
	11	+ - Konrad Dybcio <konradybcio@kernel.org>
	12	+ - Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
	13	+
	14	+description: \|
	15	+ Display clock control module provides the clocks, resets and power
	16	+ domains on Qualcomm Eliza SoC platform.
	17	+
	18	+ See also:
	19	+ - include/dt-bindings/clock/qcom,eliza-dispcc.h
	20	+
	21	+properties:
	22	+ compatible:
	23	+ enum:
	24	+ - qcom,eliza-dispcc
	25	+
	26	+ clocks:
	27	+ items:
	28	+ - description: Board XO source
	29	+ - description: Board Always On XO source
	30	+ - description: Display's AHB clock
	31	+ - description: sleep clock
	32	+ - description: Byte clock from DSI PHY0
	33	+ - description: Pixel clock from DSI PHY0
	34	+ - description: Byte clock from DSI PHY1
	35	+ - description: Pixel clock from DSI PHY1
	36	+ - description: Link clock from DP PHY0
	37	+ - description: VCO DIV clock from DP PHY0
	38	+ - description: Link clock from DP PHY1
	39	+ - description: VCO DIV clock from DP PHY1
	40	+ - description: Link clock from DP PHY2
	41	+ - description: VCO DIV clock from DP PHY2
	42	+ - description: Link clock from DP PHY3
	43	+ - description: VCO DIV clock from DP PHY3
	44	+ - description: HDMI link clock from HDMI PHY
	45	+
	46	+ power-domains:
	47	+ maxItems: 1
	48	+
	49	+ required-opps:
	50	+ maxItems: 1
	51	+
	52	+required:
	53	+ - compatible
	54	+ - clocks
	55	+ - '#power-domain-cells'
	56	+
	57	+allOf:
	58	+ - $ref: qcom,gcc.yaml#
	59	+
	60	+unevaluatedProperties: false
	61	+
	62	+examples:
	63	+ - \|
	64	+ #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
	65	+ #include <dt-bindings/clock/qcom,eliza-gcc.h>
	66	+ #include <dt-bindings/clock/qcom,rpmh.h>
	67	+ #include <dt-bindings/power/qcom,rpmhpd.h>
	68	+ clock-controller@af00000 {
	69	+ compatible = "qcom,eliza-dispcc";
	70	+ reg = <0x0af00000 0x20000>;
	71	+ clocks = <&bi_tcxo_div2>,
	72	+ <&bi_tcxo_ao_div2>,
	73	+ <&gcc GCC_DISP_AHB_CLK>,
	74	+ <&sleep_clk>,
	75	+ <&dsi0_phy DSI_BYTE_PLL_CLK>,
	76	+ <&dsi0_phy DSI_PIXEL_PLL_CLK>,
	77	+ <&dsi1_phy DSI_BYTE_PLL_CLK>,
	78	+ <&dsi1_phy DSI_PIXEL_PLL_CLK>,
	79	+ <&dp0_phy 0>,
	80	+ <&dp0_phy 1>,
	81	+ <&dp1_phy 0>,
	82	+ <&dp1_phy 1>,
	83	+ <&dp2_phy 0>,
	84	+ <&dp2_phy 1>,
	85	+ <&dp3_phy 0>,
	86	+ <&dp3_phy 1>,
	87	+ <&hdmi_phy>;
	88	+
	89	+ #clock-cells = <1>;
	90	+ #power-domain-cells = <1>;
	91	+ #reset-cells = <1>;
	92	+
	93	+ power-domains = <&rpmhpd RPMHPD_MMCX>;
	94	+ required-opps = <&rpmhpd_opp_low_svs>;
	95	+ };
	96	+...

Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml+2−2

@@ -4,14 +4,14 @@ · 3 unmodified lines
4	4	$id: http://devicetree.org/schemas/clock/qcom,glymur-dispcc.yaml#
5	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
6	6
7		−title: Qualcomm Display Clock & Reset Controller on GLYMUR
	7	+title: Qualcomm Display Clock & Reset Controller on Glymur SoC
8	8
9	9	maintainers:
10	10	- Taniya Das <taniya.das@oss.qualcomm.com>
11	11
12	12	description: \|
13	13	Qualcomm display clock control module which supports the clocks, resets and
14		− power domains for the MDSS instances on GLYMUR SoC.
	14	+ power domains for the MDSS instances on Glymur SoC.
15	15
16	16	See also:
17	17	include/dt-bindings/clock/qcom,dispcc-glymur.h

Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml+2−0

@@ -26,6 +26,8 @@ properties: · 25 unmodified lines
26	26	enum:
27	27	- qcom,ipq5018-cmn-pll
28	28	- qcom,ipq5424-cmn-pll
	29	+ - qcom,ipq6018-cmn-pll
	30	+ - qcom,ipq8074-cmn-pll
29	31	- qcom,ipq9574-cmn-pll
30	32
31	33	reg:

Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml+2−0

@@ -20,7 +20,9 @@ description: \| · 19 unmodified lines
20	20	properties:
21	21	compatible:
22	22	enum:
	23	+ - qcom,glymur-gxclkctl
23	24	- qcom,kaanapali-gxclkctl
	25	+ - qcom,sm8750-gxclkctl
24	26
25	27	power-domains:
26	28	description:

Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml+7−0

@@ -35,9 +35,14 @@ properties: · 34 unmodified lines
35	35	- description: UFS Phy Tx symbol 0 clock source
36	36	- description: USB3 Phy wrapper pipe clock source
37	37
	38	+ power-domains:
	39	+ items:
	40	+ - description: CX domain
	41	+
38	42	required:
39	43	- compatible
40	44	- clocks
	45	+ - power-domains
41	46	- '#power-domain-cells'
42	47
43	48	allOf:
@@ -48,6 +53,7 @@ unevaluatedProperties: false · 4 unmodified lines
48	53	examples:
49	54	- \|
50	55	#include <dt-bindings/clock/qcom,rpmh.h>
	56	+ #include <dt-bindings/power/qcom,rpmhpd.h>
51	57	clock-controller@100000 {
52	58	compatible = "qcom,milos-gcc";
53	59	reg = <0x00100000 0x1f4200>;
@@ -59,6 +65,7 @@ examples: · 5 unmodified lines
59	65	<&ufs_mem_phy 1>,
60	66	<&ufs_mem_phy 2>,
61	67	<&usb_1_qmpphy>;
	68	+ power-domains = <&rpmhpd RPMHPD_CX>;
62	69	#clock-cells = <1>;
63	70	#reset-cells = <1>;
64	71	#power-domain-cells = <1>;

Documentation/devicetree/bindings/clock/qcom,nord-gcc.yaml+58−0

@@ -0,0 +1,58 @@
	1	+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	+%YAML 1.2
	3	+---
	4	+$id: http://devicetree.org/schemas/clock/qcom,nord-gcc.yaml#
	5	+$schema: http://devicetree.org/meta-schemas/core.yaml#
	6	+
	7	+title: Qualcomm Global Clock & Reset Controller on Nord SoC
	8	+
	9	+maintainers:
	10	+ - Taniya Das <taniya.das@oss.qualcomm.com>
	11	+
	12	+description: \|
	13	+ Qualcomm global clock control module provides the clocks, resets and power
	14	+ domains on Nord SoC.
	15	+
	16	+ See also: include/dt-bindings/clock/qcom,nord-gcc.h
	17	+
	18	+properties:
	19	+ compatible:
	20	+ const: qcom,nord-gcc
	21	+
	22	+ clocks:
	23	+ items:
	24	+ - description: Board XO source
	25	+ - description: Sleep clock source
	26	+ - description: PCIE A Pipe clock source
	27	+ - description: PCIE B Pipe clock source
	28	+ - description: PCIE C Pipe clock source
	29	+ - description: PCIE D Pipe clock source
	30	+
	31	+required:
	32	+ - compatible
	33	+ - clocks
	34	+ - '#power-domain-cells'
	35	+
	36	+allOf:
	37	+ - $ref: qcom,gcc.yaml#
	38	+
	39	+unevaluatedProperties: false
	40	+
	41	+examples:
	42	+ - \|
	43	+ #include <dt-bindings/clock/qcom,rpmh.h>
	44	+ clock-controller@100000 {
	45	+ compatible = "qcom,nord-gcc";
	46	+ reg = <0x00100000 0x1f4200>;
	47	+ clocks = <&rpmhcc RPMH_CXO_CLK>,
	48	+ <&sleep_clk>,
	49	+ <&pcie_a_pipe_clk>,
	50	+ <&pcie_b_pipe_clk>,
	51	+ <&pcie_c_pipe_clk>,
	52	+ <&pcie_d_pipe_clk>;
	53	+ #clock-cells = <1>;
	54	+ #reset-cells = <1>;
	55	+ #power-domain-cells = <1>;
	56	+ };
	57	+
	58	+...

Documentation/devicetree/bindings/clock/qcom,nord-negcc.yaml+60−0

@@ -0,0 +1,60 @@
	1	+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	+%YAML 1.2
	3	+---
	4	+$id: http://devicetree.org/schemas/clock/qcom,nord-negcc.yaml#
	5	+$schema: http://devicetree.org/meta-schemas/core.yaml#
	6	+
	7	+title: Qualcomm Global North East Clock & Reset Controller on Nord SoC
	8	+
	9	+maintainers:
	10	+ - Taniya Das <taniya.das@oss.qualcomm.com>
	11	+
	12	+description: \|
	13	+ Qualcomm global clock control (NE) module provides the clocks, resets
	14	+ and power domains on Nord SoC.
	15	+
	16	+ See also: include/dt-bindings/clock/qcom,nord-negcc.h
	17	+
	18	+properties:
	19	+ compatible:
	20	+ const: qcom,nord-negcc
	21	+
	22	+ clocks:
	23	+ items:
	24	+ - description: Board XO source
	25	+ - description: Sleep clock source
	26	+ - description: UFS Phy Rx symbol 0 clock source
	27	+ - description: UFS Phy Rx symbol 1 clock source
	28	+ - description: UFS Phy Tx symbol 0 clock source
	29	+ - description: USB3 Phy sec wrapper pipe clock source
	30	+ - description: USB3 Phy wrapper pipe clock source
	31	+
	32	+required:
	33	+ - compatible
	34	+ - clocks
	35	+ - '#power-domain-cells'
	36	+
	37	+allOf:
	38	+ - $ref: qcom,gcc.yaml#
	39	+
	40	+unevaluatedProperties: false
	41	+
	42	+examples:
	43	+ - \|
	44	+ #include <dt-bindings/clock/qcom,rpmh.h>
	45	+ clock-controller@8900000 {
	46	+ compatible = "qcom,nord-negcc";
	47	+ reg = <0x08900000 0xf4200>;
	48	+ clocks = <&rpmhcc RPMH_CXO_CLK>,
	49	+ <&sleep_clk>,
	50	+ <&ufs_phy_rx_symbol_0_clk>,
	51	+ <&ufs_phy_rx_symbol_1_clk>,
	52	+ <&ufs_phy_tx_symbol_0_clk>,
	53	+ <&usb3_phy_sec_pipe_clk>,
	54	+ <&usb3_phy_pipe_clk>;
	55	+ #clock-cells = <1>;
	56	+ #reset-cells = <1>;
	57	+ #power-domain-cells = <1>;
	58	+ };
	59	+
	60	+...

Documentation/devicetree/bindings/clock/qcom,nord-nwgcc.yaml+55−0

@@ -0,0 +1,55 @@
	1	+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	+%YAML 1.2
	3	+---
	4	+$id: http://devicetree.org/schemas/clock/qcom,nord-nwgcc.yaml#
	5	+$schema: http://devicetree.org/meta-schemas/core.yaml#
	6	+
	7	+title: Qualcomm Global North West and South East Clock & Reset Controller
	8	+ on Nord SoC
	9	+
	10	+maintainers:
	11	+ - Taniya Das <taniya.das@oss.qualcomm.com>
	12	+
	13	+description: \|
	14	+ Qualcomm global clock control (NW, SE) module provides the clocks, resets
	15	+ and power domains on Nord SoC.
	16	+
	17	+ See also:
	18	+ include/dt-bindings/clock/qcom,nord-nwgcc.h
	19	+ include/dt-bindings/clock/qcom,nord-segcc.h
	20	+
	21	+properties:
	22	+ compatible:
	23	+ enum:
	24	+ - qcom,nord-nwgcc
	25	+ - qcom,nord-segcc
	26	+
	27	+ clocks:
	28	+ items:
	29	+ - description: Board XO source
	30	+ - description: Sleep clock source
	31	+
	32	+required:
	33	+ - compatible
	34	+ - clocks
	35	+ - '#power-domain-cells'
	36	+
	37	+allOf:
	38	+ - $ref: qcom,gcc.yaml#
	39	+
	40	+unevaluatedProperties: false
	41	+
	42	+examples:
	43	+ - \|
	44	+ #include <dt-bindings/clock/qcom,rpmh.h>
	45	+ clock-controller@8b00000 {
	46	+ compatible = "qcom,nord-nwgcc";
	47	+ reg = <0x08b00000 0xf4200>;
	48	+ clocks = <&rpmhcc RPMH_CXO_CLK>,
	49	+ <&sleep_clk>;
	50	+ #clock-cells = <1>;
	51	+ #reset-cells = <1>;
	52	+ #power-domain-cells = <1>;
	53	+ };
	54	+
	55	+...

Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml+1−0

@@ -21,6 +21,7 @@ properties: · 20 unmodified lines
21	21	- qcom,glymur-rpmh-clk
22	22	- qcom,kaanapali-rpmh-clk
23	23	- qcom,milos-rpmh-clk
	24	+ - qcom,nord-rpmh-clk
24	25	- qcom,qcs615-rpmh-clk
25	26	- qcom,qdu1000-rpmh-clk
26	27	- qcom,sa8775p-rpmh-clk

Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml+26−1

@@ -8,12 +8,14 @@ title: Qualcomm Graphics Clock & Reset Controller on SM8450 · 7 unmodified lines
8	8
9	9	maintainers:
10	10	- Konrad Dybcio <konradybcio@kernel.org>
	11	+ - Taniya Das <taniya.das@oss.qualcomm.com>
11	12
12	13	description: \|
13	14	Qualcomm graphics clock control module provides the clocks, resets and power
14	15	domains on Qualcomm SoCs.
15	16
16		− See also::
	17	+ See also:
	18	+ include/dt-bindings/clock/qcom,glymur-gpucc.h
17	19	include/dt-bindings/clock/qcom,kaanapali-gpucc.h
18	20	include/dt-bindings/clock/qcom,milos-gpucc.h
19	21	include/dt-bindings/clock/qcom,sar2130p-gpucc.h
@@ -22,11 +24,13 @@ description: \| · 2 unmodified lines
22	24	include/dt-bindings/clock/qcom,sm8550-gpucc.h
23	25	include/dt-bindings/reset/qcom,sm8450-gpucc.h
24	26	include/dt-bindings/reset/qcom,sm8650-gpucc.h
	27	+ include/dt-bindings/reset/qcom,sm8750-gpucc.h
25	28	include/dt-bindings/reset/qcom,x1e80100-gpucc.h
26	29
27	30	properties:
28	31	compatible:
29	32	enum:
	33	+ - qcom,glymur-gpucc
30	34	- qcom,kaanapali-gpucc
31	35	- qcom,milos-gpucc
32	36	- qcom,sar2130p-gpucc
@@ -35,6 +39,7 @@ properties: · 2 unmodified lines
35	39	- qcom,sm8475-gpucc
36	40	- qcom,sm8550-gpucc
37	41	- qcom,sm8650-gpucc
	42	+ - qcom,sm8750-gpucc
38	43	- qcom,x1e80100-gpucc
39	44	- qcom,x1p42100-gpucc
40	45
@@ -44,6 +49,16 @@ properties: · 3 unmodified lines
44	49	- description: GPLL0 main branch source
45	50	- description: GPLL0 div branch source
46	51
	52	+ power-domains:
	53	+ items:
	54	+ - description: A phandle to the MX power-domain
	55	+ - description: A phandle to the CX power-domain
	56	+
	57	+ required-opps:
	58	+ items:
	59	+ - description: A phandle to an OPP node describing MX performance points
	60	+ - description: A phandle to an OPP node describing CX performance points
	61	+
47	62	required:
48	63	- compatible
49	64	- clocks
@@ -51,6 +66,16 @@ required: · 1 unmodified line
51	66
52	67	allOf:
53	68	- $ref: qcom,gcc.yaml#
	69	+ - if:
	70	+ properties:
	71	+ compatible:
	72	+ contains:
	73	+ enum:
	74	+ - qcom,sm8750-gpucc
	75	+ then:
	76	+ required:
	77	+ - power-domains
	78	+ - required-opps
54	79
55	80	unevaluatedProperties: false
56	81

Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml+3−0

@@ -15,6 +15,7 @@ description: \| · 14 unmodified lines
15	15	domains on SM8450.
16	16
17	17	See also:
	18	+ include/dt-bindings/clock/qcom,glymur-videocc.h
18	19	include/dt-bindings/clock/qcom,kaanapali-videocc.h
19	20	include/dt-bindings/clock/qcom,sm8450-videocc.h
20	21	include/dt-bindings/clock/qcom,sm8650-videocc.h
@@ -23,6 +24,7 @@ description: \| · 2 unmodified lines
23	24	properties:
24	25	compatible:
25	26	enum:
	27	+ - qcom,glymur-videocc
26	28	- qcom,kaanapali-videocc
27	29	- qcom,sm8450-videocc
28	30	- qcom,sm8475-videocc
@@ -63,6 +65,7 @@ allOf: · 34 unmodified lines
63	65	compatible:
64	66	contains:
65	67	enum:
	68	+ - qcom,glymur-videocc
66	69	- qcom,kaanapali-videocc
67	70	- qcom,sm8450-videocc
68	71	- qcom,sm8550-videocc

Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml+2−0

@@ -17,6 +17,7 @@ description: \| · 16 unmodified lines
17	17	See also:
18	18	- include/dt-bindings/clock/qcom,eliza-tcsr.h
19	19	- include/dt-bindings/clock/qcom,glymur-tcsr.h
	20	+ - include/dt-bindings/clock/qcom,nord-tcsrcc.h
20	21	- include/dt-bindings/clock/qcom,sm8550-tcsr.h
21	22	- include/dt-bindings/clock/qcom,sm8650-tcsr.h
22	23	- include/dt-bindings/clock/qcom,sm8750-tcsr.h
@@ -29,6 +30,7 @@ properties: · 6 unmodified lines
29	30	- qcom,glymur-tcsr
30	31	- qcom,kaanapali-tcsr
31	32	- qcom,milos-tcsr
	33	+ - qcom,nord-tcsrcc
32	34	- qcom,sar2130p-tcsr
33	35	- qcom,sm8550-tcsr
34	36	- qcom,sm8650-tcsr

Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml+21−0

@@ -35,6 +35,7 @@ properties: · 34 unmodified lines
35	35	- samsung,exynosautov920-cmu-cpucl0
36	36	- samsung,exynosautov920-cmu-cpucl1
37	37	- samsung,exynosautov920-cmu-cpucl2
	38	+ - samsung,exynosautov920-cmu-g3d
38	39	- samsung,exynosautov920-cmu-hsi0
39	40	- samsung,exynosautov920-cmu-hsi1
40	41	- samsung,exynosautov920-cmu-hsi2
@@ -287,6 +288,26 @@ allOf: · 246 unmodified lines
287	288	- const: oscclk
288	289	- const: noc
289	290
	291	+ - if:
	292	+ properties:
	293	+ compatible:
	294	+ contains:
	295	+ const: samsung,exynosautov920-cmu-g3d
	296	+
	297	+ then:
	298	+ properties:
	299	+ clocks:
	300	+ items:
	301	+ - description: External reference clock (38.4 MHz)
	302	+ - description: CMU_G3D SWITCH clock (from CMU_TOP)
	303	+ - description: CMU_G3D NOCP clock (from CMU_TOP)
	304	+
	305	+ clock-names:
	306	+ items:
	307	+ - const: oscclk
	308	+ - const: switch
	309	+ - const: nocp
	310	+
290	311	required:
291	312	- compatible
292	313	- "#clock-cells"

Documentation/devicetree/bindings/clock/tenstorrent,atlantis-prcm-rcpu.yaml+54−0

@@ -0,0 +1,54 @@
	1	+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	+%YAML 1.2
	3	+---
	4	+$id: http://devicetree.org/schemas/clock/tenstorrent,atlantis-prcm-rcpu.yaml#
	5	+$schema: http://devicetree.org/meta-schemas/core.yaml#
	6	+
	7	+title: Tenstorrent Atlantis PRCM (Power, Reset, Clock Management) Module
	8	+
	9	+maintainers:
	10	+ - Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
	11	+
	12	+description:
	13	+ Multifunctional register block found in Tenstorrent Atlantis SoC whose main
	14	+ function is to control clocks and resets. This block is instantiated multiple
	15	+ times in the SoC, each block controls clock and resets for a different
	16	+ subsystem. RCPU prcm serves low speed IO interfaces.
	17	+
	18	+properties:
	19	+ compatible:
	20	+ enum:
	21	+ - tenstorrent,atlantis-prcm-rcpu
	22	+
	23	+ reg:
	24	+ maxItems: 1
	25	+
	26	+ clocks:
	27	+ maxItems: 1
	28	+
	29	+ "#clock-cells":
	30	+ const: 1
	31	+ description:
	32	+ See <dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h> for valid indices.
	33	+
	34	+ "#reset-cells":
	35	+ const: 1
	36	+
	37	+required:
	38	+ - compatible
	39	+ - reg
	40	+ - clocks
	41	+ - "#clock-cells"
	42	+ - "#reset-cells"
	43	+
	44	+additionalProperties: false
	45	+
	46	+examples:
	47	+ - \|
	48	+ clock-controller@a8000000 {
	49	+ compatible = "tenstorrent,atlantis-prcm-rcpu";
	50	+ reg = <0xa8000000 0x10000>;
	51	+ clocks = <&osc_24m>;
	52	+ #clock-cells = <1>;
	53	+ #reset-cells = <1>;
	54	+ };

Documentation/devicetree/bindings/mfd/syscon.yaml+2−0

@@ -61,6 +61,7 @@ select: · 60 unmodified lines
61	61	- cirrus,ep7209-syscon2
62	62	- cirrus,ep7209-syscon3
63	63	- cnxt,cx92755-uc
	64	+ - econet,en751221-chip-scu
64	65	- freecom,fsg-cs2-system-controller
65	66	- fsl,imx93-aonmix-ns-syscfg
66	67	- fsl,imx93-wakeupmix-syscfg
@@ -173,6 +174,7 @@ properties: · 106 unmodified lines
173	174	- cirrus,ep7209-syscon2
174	175	- cirrus,ep7209-syscon3
175	176	- cnxt,cx92755-uc
	177	+ - econet,en751221-chip-scu
176	178	- freecom,fsg-cs2-system-controller
177	179	- fsl,imx93-aonmix-ns-syscfg
178	180	- fsl,imx93-wakeupmix-syscfg

Documentation/driver-api/clk.rst+1−8

@@ -77,9 +77,6 @@ the operations defined in clk-provider.h:: · 76 unmodified lines
77	77	void (disable_unused)(struct clk_hw hw);
78	78	unsigned long (recalc_rate)(struct clk_hw hw,
79	79	unsigned long parent_rate);
80		− long (round_rate)(struct clk_hw hw,
81		− unsigned long rate,
82		− unsigned long *parent_rate);
83	80	int (determine_rate)(struct clk_hw hw,
84	81	struct clk_rate_request *req);
85	82	int (set_parent)(struct clk_hw hw, u8 index);
@@ -220,9 +217,7 @@ optional or must be evaluated on a case-by-case basis. · 134 unmodified lines
220	217	+----------------+------+-------------+---------------+-------------+------+
221	218	\|.recalc_rate \| \| y \| \| \| \|
222	219	+----------------+------+-------------+---------------+-------------+------+
223		− \|.round_rate \| \| y [1]_ \| \| \| \|
224		− +----------------+------+-------------+---------------+-------------+------+
225		− \|.determine_rate \| \| y [1]_ \| \| \| \|
	220	+ \|.determine_rate \| \| y \| \| \| \|
226	221	+----------------+------+-------------+---------------+-------------+------+
227	222	\|.set_rate \| \| y \| \| \| \|
228	223	+----------------+------+-------------+---------------+-------------+------+
@@ -238,8 +233,6 @@ optional or must be evaluated on a case-by-case basis. · 9 unmodified lines
238	233	\|.init \| \| \| \| \| \|
239	234	+----------------+------+-------------+---------------+-------------+------+
240	235
241		−.. [1] either one of round_rate or determine_rate is required.
242		−
243	236	Finally, register your clock at run-time with a hardware-specific
244	237	registration function. This function simply populates struct clk_foo's
245	238	data and then passes the common struct clk parameters to the framework

MAINTAINERS+14−0

@@ -9139,6 +9139,8 @@ F: arch/mips/boot/dts/econet/ · 9138 unmodified lines
9139	9139	F: arch/mips/econet/
9140	9140	F: drivers/clocksource/timer-econet-en751221.c
9141	9141	F: drivers/irqchip/irq-econet-en751221.c
	9142	+F: include/dt-bindings/clock/econet,en751221-scu.h
	9143	+F: include/dt-bindings/reset/econet,en751221-scu.h
9142	9144
9143	9145	ECRYPT FILE SYSTEM
9144	9146	M: Tyler Hicks <code@tyhicks.com>
@@ -9538,6 +9540,14 @@ T: git https://github.com/eswincomputing/linux-next.git · 393 unmodified lines
9538	9540	F: Documentation/devicetree/bindings/riscv/eswin.yaml
9539	9541	F: arch/riscv/boot/dts/eswin/
9540	9542
	9543	+ESWIN EIC7700 CLOCK DRIVER
	9544	+M: Yifeng Huang <huangyifeng@eswincomputing.com>
	9545	+M: Xuyang Dong <dongxuyang@eswincomputing.com>
	9546	+S: Maintained
	9547	+F: Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
	9548	+F: drivers/clk/eswin/
	9549	+F: include/dt-bindings/clock/eswin,eic7700-clock.h
	9550	+
9541	9551	ET131X NETWORK DRIVER
9542	9552	M: Mark Einon <mark.einon@gmail.com>
9543	9553	S: Odd Fixes
@@ -23012,8 +23022,12 @@ M: Joel Stanley <jms@oss.tenstorrent.com> · 13468 unmodified lines
23012	23022	L: linux-riscv@lists.infradead.org
23013	23023	S: Maintained
23014	23024	T: git https://github.com/tenstorrent/linux.git
	23025	+F: Documentation/devicetree/bindings/clock/tenstorrent,atlantis-prcm-rcpu.yaml
23015	23026	F: Documentation/devicetree/bindings/riscv/tenstorrent.yaml
23016	23027	F: arch/riscv/boot/dts/tenstorrent/
	23028	+F: drivers/clk/tenstorrent/
	23029	+F: drivers/reset/reset-tenstorrent-atlantis.c
	23030	+F: include/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h
23017	23031
23018	23032	RISC-V THEAD SoC SUPPORT
23019	23033	M: Drew Fustini <fustini@kernel.org>

drivers/clk/Kconfig+6−5

@@ -218,13 +218,13 @@ config COMMON_CLK_CS2000_CP · 217 unmodified lines
218	218	If you say yes here you get support for the CS2000 clock multiplier.
219	219
220	220	config COMMON_CLK_EN7523
221		− bool "Clock driver for Airoha EN7523 SoC system clocks"
	221	+ bool "Clock driver for Airoha/EcoNet SoC system clocks"
222	222	depends on OF
223		− depends on ARCH_AIROHA \|\| COMPILE_TEST
	223	+ depends on ARCH_AIROHA \|\| ECONET \|\| COMPILE_TEST
224	224	default ARCH_AIROHA
225	225	help
226	226	This driver provides the fixed clocks and gates present on Airoha
227		− ARM silicon.
	227	+ and EcoNet silicon.
228	228
229	229	config COMMON_CLK_EP93XX
230	230	tristate "Clock driver for Cirrus Logic ep93xx SoC"
@@ -255,7 +255,7 @@ config COMMON_CLK_FSL_FLEXSPI · 24 unmodified lines
255	255
256	256	config COMMON_CLK_FSL_SAI
257	257	bool "Clock driver for BCLK of Freescale SAI cores"
258		− depends on ARCH_LAYERSCAPE \|\| COMPILE_TEST
	258	+ depends on ARCH_LAYERSCAPE \|\| ARCH_MXC \|\| COMPILE_TEST
259	259	help
260	260	This driver supports the Freescale SAI (Synchronous Audio Interface)
261	261	to be used as a generic clock output. Some SoCs have restrictions
@@ -502,8 +502,8 @@ config COMMON_CLK_RPMI · 240 unmodified lines
502	502	source "drivers/clk/actions/Kconfig"
503	503	source "drivers/clk/analogbits/Kconfig"
504	504	source "drivers/clk/aspeed/Kconfig"
505		−source "drivers/clk/baikal-t1/Kconfig"
506	505	source "drivers/clk/bcm/Kconfig"
	506	+source "drivers/clk/eswin/Kconfig"
507	507	source "drivers/clk/hisilicon/Kconfig"
508	508	source "drivers/clk/imgtec/Kconfig"
509	509	source "drivers/clk/imx/Kconfig"
@@ -531,6 +531,7 @@ source "drivers/clk/starfive/Kconfig" · 21 unmodified lines
531	531	source "drivers/clk/sunxi/Kconfig"
532	532	source "drivers/clk/sunxi-ng/Kconfig"
533	533	source "drivers/clk/tegra/Kconfig"
	534	+source "drivers/clk/tenstorrent/Kconfig"
534	535	source "drivers/clk/thead/Kconfig"
535	536	source "drivers/clk/stm32/Kconfig"
536	537	source "drivers/clk/ti/Kconfig"

drivers/clk/Makefile+2−1

@@ -116,10 +116,10 @@ obj-y += aspeed/ · 115 unmodified lines
116	116	obj-$(CONFIG_COMMON_CLK_AT91) += at91/
117	117	obj-$(CONFIG_ARCH_ARTPEC) += axis/
118	118	obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/
119		−obj-$(CONFIG_CLK_BAIKAL_T1) += baikal-t1/
120	119	obj-y += bcm/
121	120	obj-$(CONFIG_ARCH_BERLIN) += berlin/
122	121	obj-$(CONFIG_ARCH_DAVINCI) += davinci/
	122	+obj-$(CONFIG_COMMON_CLK_ESWIN) += eswin/
123	123	obj-$(CONFIG_ARCH_HISI) += hisilicon/
124	124	obj-y += imgtec/
125	125	obj-y += imx/
@@ -155,6 +155,7 @@ obj-y += starfive/ · 29 unmodified lines
155	155	obj-$(CONFIG_ARCH_SUNXI) += sunxi/
156	156	obj-y += sunxi-ng/
157	157	obj-$(CONFIG_ARCH_TEGRA) += tegra/
	158	+obj-y += tenstorrent/
158	159	obj-$(CONFIG_ARCH_THEAD) += thead/
159	160	obj-y += ti/
160	161	obj-$(CONFIG_CLK_UNIPHIER) += uniphier/

drivers/clk/baikal-t1/Kconfig+0−52

@@ -1,52 +0,0 @@
1		−# SPDX-License-Identifier: GPL-2.0-only
2		−config CLK_BAIKAL_T1
3		− bool "Baikal-T1 Clocks Control Unit interface"
4		− depends on (MIPS_BAIKAL_T1 && OF) \|\| COMPILE_TEST
5		− default MIPS_BAIKAL_T1
6		− help
7		− Clocks Control Unit is the core of Baikal-T1 SoC System Controller
8		− responsible for the chip subsystems clocking and resetting. It
9		− consists of multiple global clock domains, which can be reset by
10		− means of the CCU control registers. These domains and devices placed
11		− in them are fed with clocks generated by a hierarchy of PLLs,
12		− configurable and fixed clock dividers. Enable this option to be able
13		− to select Baikal-T1 CCU PLLs and Dividers drivers.
14		−
15		−if CLK_BAIKAL_T1
16		−
17		−config CLK_BT1_CCU_PLL
18		− bool "Baikal-T1 CCU PLLs support"
19		− select MFD_SYSCON
20		− default MIPS_BAIKAL_T1
21		− help
22		− Enable this to support the PLLs embedded into the Baikal-T1 SoC
23		− System Controller. These are five PLLs placed at the root of the
24		− clocks hierarchy, right after an external reference oscillator
25		− (normally of 25MHz). They are used to generate high frequency
26		− signals, which are either directly wired to the consumers (like
27		− CPUs, DDR, etc.) or passed over the clock dividers to be only
28		− then used as an individual reference clock of a target device.
29		−
30		−config CLK_BT1_CCU_DIV
31		− bool "Baikal-T1 CCU Dividers support"
32		− select MFD_SYSCON
33		− default MIPS_BAIKAL_T1
34		− help
35		− Enable this to support the CCU dividers used to distribute clocks
36		− between AXI-bus and system devices coming from CCU PLLs of Baikal-T1
37		− SoC. CCU dividers can be either configurable or with fixed divider,
38		− either gateable or ungateable. Some of the CCU dividers can be as well
39		− used to reset the domains they're supplying clock to.
40		−
41		−config CLK_BT1_CCU_RST
42		− bool "Baikal-T1 CCU Resets support"
43		− select RESET_CONTROLLER
44		− select MFD_SYSCON
45		− default MIPS_BAIKAL_T1
46		− help
47		− Enable this to support the CCU reset blocks responsible for the
48		− AXI-bus and some subsystems reset. These are mainly the
49		− self-deasserted reset controls but there are several lines which
50		− can be directly asserted/de-asserted (PCIe and DDR sub-domains).
51		−
52		−endif

drivers/clk/baikal-t1/Makefile+0−4

@@ -1,4 +0,0 @@
1		−# SPDX-License-Identifier: GPL-2.0-only
2		−obj-$(CONFIG_CLK_BT1_CCU_PLL) += ccu-pll.o clk-ccu-pll.o
3		−obj-$(CONFIG_CLK_BT1_CCU_DIV) += ccu-div.o clk-ccu-div.o
4		−obj-$(CONFIG_CLK_BT1_CCU_RST) += ccu-rst.o

drivers/clk/baikal-t1/ccu-div.c+0−653

@@ -1,653 +0,0 @@
1		−// SPDX-License-Identifier: GPL-2.0-only
2		−/*
3		− * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
4		− *
5		− * Authors:
6		− * Serge Semin <Sergey.Semin@baikalelectronics.ru>
7		− * Dmitry Dunaev <dmitry.dunaev@baikalelectronics.ru>
8		− *
9		− * Baikal-T1 CCU Dividers interface driver
10		− */
11		−
12		−#define pr_fmt(fmt) "bt1-ccu-div: " fmt
13		−
14		−#include <linux/kernel.h>
15		−#include <linux/printk.h>
16		−#include <linux/bits.h>
17		−#include <linux/bitfield.h>
18		−#include <linux/slab.h>
19		−#include <linux/clk-provider.h>
20		−#include <linux/of.h>
21		−#include <linux/spinlock.h>
22		−#include <linux/regmap.h>
23		−#include <linux/delay.h>
24		−#include <linux/time64.h>
25		−#include <linux/debugfs.h>
26		−
27		−#include "ccu-div.h"
28		−
29		−#define CCU_DIV_CTL 0x00
30		−#define CCU_DIV_CTL_EN BIT(0)
31		−#define CCU_DIV_CTL_RST BIT(1)
32		−#define CCU_DIV_CTL_SET_CLKDIV BIT(2)
33		−#define CCU_DIV_CTL_CLKDIV_FLD 4
34		−#define CCU_DIV_CTL_CLKDIV_MASK(_width) \
35		− GENMASK((_width) + CCU_DIV_CTL_CLKDIV_FLD - 1, CCU_DIV_CTL_CLKDIV_FLD)
36		−#define CCU_DIV_CTL_LOCK_SHIFTED BIT(27)
37		−#define CCU_DIV_CTL_GATE_REF_BUF BIT(28)
38		−#define CCU_DIV_CTL_LOCK_NORMAL BIT(31)
39		−
40		−#define CCU_DIV_LOCK_CHECK_RETRIES 50
41		−
42		−#define CCU_DIV_CLKDIV_MIN 0
43		−#define CCU_DIV_CLKDIV_MAX(_mask) \
44		− ((_mask) >> CCU_DIV_CTL_CLKDIV_FLD)
45		−
46		−/*
47		− * Use the next two methods until there are generic field setter and
48		− * getter available with non-constant mask support.
49		− */
50		−static inline u32 ccu_div_get(u32 mask, u32 val)
51		−{
52		− return (val & mask) >> CCU_DIV_CTL_CLKDIV_FLD;
53		−}
54		−
55		−static inline u32 ccu_div_prep(u32 mask, u32 val)
56		−{
57		− return (val << CCU_DIV_CTL_CLKDIV_FLD) & mask;
58		−}
59		−
60		−static inline unsigned long ccu_div_lock_delay_ns(unsigned long ref_clk,
61		− unsigned long div)
62		−{
63		− u64 ns = 4ULL * (div ?: 1) * NSEC_PER_SEC;
64		−
65		− do_div(ns, ref_clk);
66		−
67		− return ns;
68		−}
69		−
70		−static inline unsigned long ccu_div_calc_freq(unsigned long ref_clk,
71		− unsigned long div)
72		−{
73		− return ref_clk / (div ?: 1);
74		−}
75		−
76		−static int ccu_div_var_update_clkdiv(struct ccu_div *div,
77		− unsigned long parent_rate,
78		− unsigned long divider)
79		−{
80		− unsigned long nd;
81		− u32 val = 0;
82		− u32 lock;
83		− int count;
84		−
85		− nd = ccu_div_lock_delay_ns(parent_rate, divider);
86		−
87		− if (div->features & CCU_DIV_LOCK_SHIFTED)
88		− lock = CCU_DIV_CTL_LOCK_SHIFTED;
89		− else
90		− lock = CCU_DIV_CTL_LOCK_NORMAL;
91		−
92		− regmap_update_bits(div->sys_regs, div->reg_ctl,
93		− CCU_DIV_CTL_SET_CLKDIV, CCU_DIV_CTL_SET_CLKDIV);
94		−
95		− /*
96		− * Until there is nsec-version of readl_poll_timeout() is available
97		− * we have to implement the next polling loop.
98		− */
99		− count = CCU_DIV_LOCK_CHECK_RETRIES;
100		− do {
101		− ndelay(nd);
102		− regmap_read(div->sys_regs, div->reg_ctl, &val);
103		− if (val & lock)
104		− return 0;
105		− } while (--count);
106		−
107		− return -ETIMEDOUT;
108		−}
109		−
110		−static int ccu_div_var_enable(struct clk_hw *hw)
111		−{
112		− struct clk_hw *parent_hw = clk_hw_get_parent(hw);
113		− struct ccu_div *div = to_ccu_div(hw);
114		− unsigned long flags;
115		− u32 val = 0;
116		− int ret;
117		−
118		− if (!parent_hw) {
119		− pr_err("Can't enable '%s' with no parent", clk_hw_get_name(hw));
120		− return -EINVAL;
121		− }
122		−
123		− regmap_read(div->sys_regs, div->reg_ctl, &val);
124		− if (val & CCU_DIV_CTL_EN)
125		− return 0;
126		−
127		− spin_lock_irqsave(&div->lock, flags);
128		− ret = ccu_div_var_update_clkdiv(div, clk_hw_get_rate(parent_hw),
129		− ccu_div_get(div->mask, val));
130		− if (!ret)
131		− regmap_update_bits(div->sys_regs, div->reg_ctl,
132		− CCU_DIV_CTL_EN, CCU_DIV_CTL_EN);
133		− spin_unlock_irqrestore(&div->lock, flags);
134		− if (ret)
135		− pr_err("Divider '%s' lock timed out\n", clk_hw_get_name(hw));
136		−
137		− return ret;
138		−}
139		−
140		−static int ccu_div_gate_enable(struct clk_hw *hw)
141		−{
142		− struct ccu_div *div = to_ccu_div(hw);
143		− unsigned long flags;
144		−
145		− spin_lock_irqsave(&div->lock, flags);
146		− regmap_update_bits(div->sys_regs, div->reg_ctl,
147		− CCU_DIV_CTL_EN, CCU_DIV_CTL_EN);
148		− spin_unlock_irqrestore(&div->lock, flags);
149		−
150		− return 0;
151		−}
152		−
153		−static void ccu_div_gate_disable(struct clk_hw *hw)
154		−{
155		− struct ccu_div *div = to_ccu_div(hw);
156		− unsigned long flags;
157		−
158		− spin_lock_irqsave(&div->lock, flags);
159		− regmap_update_bits(div->sys_regs, div->reg_ctl, CCU_DIV_CTL_EN, 0);
160		− spin_unlock_irqrestore(&div->lock, flags);
161		−}
162		−
163		−static int ccu_div_gate_is_enabled(struct clk_hw *hw)
164		−{
165		− struct ccu_div *div = to_ccu_div(hw);
166		− u32 val = 0;
167		−
168		− regmap_read(div->sys_regs, div->reg_ctl, &val);
169		−
170		− return !!(val & CCU_DIV_CTL_EN);
171		−}
172		−
173		−static int ccu_div_buf_enable(struct clk_hw *hw)
174		−{
175		− struct ccu_div *div = to_ccu_div(hw);
176		− unsigned long flags;
177		−
178		− spin_lock_irqsave(&div->lock, flags);
179		− regmap_update_bits(div->sys_regs, div->reg_ctl,
180		− CCU_DIV_CTL_GATE_REF_BUF, 0);
181		− spin_unlock_irqrestore(&div->lock, flags);
182		−
183		− return 0;
184		−}
185		−
186		−static void ccu_div_buf_disable(struct clk_hw *hw)
187		−{
188		− struct ccu_div *div = to_ccu_div(hw);
189		− unsigned long flags;
190		−
191		− spin_lock_irqsave(&div->lock, flags);
192		− regmap_update_bits(div->sys_regs, div->reg_ctl,
193		− CCU_DIV_CTL_GATE_REF_BUF, CCU_DIV_CTL_GATE_REF_BUF);
194		− spin_unlock_irqrestore(&div->lock, flags);
195		−}
196		−
197		−static int ccu_div_buf_is_enabled(struct clk_hw *hw)
198		−{
199		− struct ccu_div *div = to_ccu_div(hw);
200		− u32 val = 0;
201		−
202		− regmap_read(div->sys_regs, div->reg_ctl, &val);
203		−
204		− return !(val & CCU_DIV_CTL_GATE_REF_BUF);
205		−}
206		−
207		−static unsigned long ccu_div_var_recalc_rate(struct clk_hw *hw,
208		− unsigned long parent_rate)
209		−{
210		− struct ccu_div *div = to_ccu_div(hw);
211		− unsigned long divider;
212		− u32 val = 0;
213		−
214		− regmap_read(div->sys_regs, div->reg_ctl, &val);
215		− divider = ccu_div_get(div->mask, val);
216		−
217		− return ccu_div_calc_freq(parent_rate, divider);
218		−}
219		−
220		−static inline unsigned long ccu_div_var_calc_divider(unsigned long rate,
221		− unsigned long parent_rate,
222		− unsigned int mask)
223		−{
224		− unsigned long divider;
225		−
226		− divider = parent_rate / rate;
227		− return clamp_t(unsigned long, divider, CCU_DIV_CLKDIV_MIN,
228		− CCU_DIV_CLKDIV_MAX(mask));
229		−}
230		−
231		−static int ccu_div_var_determine_rate(struct clk_hw *hw,
232		− struct clk_rate_request *req)
233		−{
234		− struct ccu_div *div = to_ccu_div(hw);
235		− unsigned long divider;
236		−
237		− divider = ccu_div_var_calc_divider(req->rate, req->best_parent_rate,
238		− div->mask);
239		−
240		− req->rate = ccu_div_calc_freq(req->best_parent_rate, divider);
241		−
242		− return 0;
243		−}
244		−
245		−/*
246		− * This method is used for the clock divider blocks, which support the
247		− * on-the-fly rate change. So due to lacking the EN bit functionality
248		− * they can't be gated before the rate adjustment.
249		− */
250		−static int ccu_div_var_set_rate_slow(struct clk_hw *hw, unsigned long rate,
251		− unsigned long parent_rate)
252		−{
253		− struct ccu_div *div = to_ccu_div(hw);
254		− unsigned long flags, divider;
255		− u32 val;
256		− int ret;
257		−
258		− divider = ccu_div_var_calc_divider(rate, parent_rate, div->mask);
259		− if (divider == 1 && div->features & CCU_DIV_SKIP_ONE) {
260		− divider = 0;
261		− } else if (div->features & CCU_DIV_SKIP_ONE_TO_THREE) {
262		− if (divider == 1 \|\| divider == 2)
263		− divider = 0;
264		− else if (divider == 3)
265		− divider = 4;
266		− }
267		−
268		− val = ccu_div_prep(div->mask, divider);
269		−
270		− spin_lock_irqsave(&div->lock, flags);
271		− regmap_update_bits(div->sys_regs, div->reg_ctl, div->mask, val);
272		− ret = ccu_div_var_update_clkdiv(div, parent_rate, divider);
273		− spin_unlock_irqrestore(&div->lock, flags);
274		− if (ret)
275		− pr_err("Divider '%s' lock timed out\n", clk_hw_get_name(hw));
276		−
277		− return ret;
278		−}
279		−
280		−/*
281		− * This method is used for the clock divider blocks, which don't support
282		− * the on-the-fly rate change.
283		− */
284		−static int ccu_div_var_set_rate_fast(struct clk_hw *hw, unsigned long rate,
285		− unsigned long parent_rate)
286		−{
287		− struct ccu_div *div = to_ccu_div(hw);
288		− unsigned long flags, divider;
289		− u32 val;
290		−
291		− divider = ccu_div_var_calc_divider(rate, parent_rate, div->mask);
292		− val = ccu_div_prep(div->mask, divider);
293		−
294		− /*
295		− * Also disable the clock divider block if it was enabled by default
296		− * or by the bootloader.
297		− */
298		− spin_lock_irqsave(&div->lock, flags);
299		− regmap_update_bits(div->sys_regs, div->reg_ctl,
300		− div->mask \| CCU_DIV_CTL_EN, val);
301		− spin_unlock_irqrestore(&div->lock, flags);
302		−
303		− return 0;
304		−}
305		−
306		−static unsigned long ccu_div_fixed_recalc_rate(struct clk_hw *hw,
307		− unsigned long parent_rate)
308		−{
309		− struct ccu_div *div = to_ccu_div(hw);
310		−
311		− return ccu_div_calc_freq(parent_rate, div->divider);
312		−}
313		−
314		−static int ccu_div_fixed_determine_rate(struct clk_hw *hw,
315		− struct clk_rate_request *req)
316		−{
317		− struct ccu_div *div = to_ccu_div(hw);
318		−
319		− req->rate = ccu_div_calc_freq(req->best_parent_rate, div->divider);
320		−
321		− return 0;
322		−}
323		−
324		−static int ccu_div_fixed_set_rate(struct clk_hw *hw, unsigned long rate,
325		− unsigned long parent_rate)
326		−{
327		− return 0;
328		−}
329		−
330		−#ifdef CONFIG_DEBUG_FS
331		−
332		−struct ccu_div_dbgfs_bit {
333		− struct ccu_div *div;
334		− const char *name;
335		− u32 mask;
336		−};
337		−
338		−#define CCU_DIV_DBGFS_BIT_ATTR(_name, _mask) { \
339		− .name = _name, \
340		− .mask = _mask \
341		− }
342		−
343		−static const struct ccu_div_dbgfs_bit ccu_div_bits[] = {
344		− CCU_DIV_DBGFS_BIT_ATTR("div_en", CCU_DIV_CTL_EN),
345		− CCU_DIV_DBGFS_BIT_ATTR("div_rst", CCU_DIV_CTL_RST),
346		− CCU_DIV_DBGFS_BIT_ATTR("div_bypass", CCU_DIV_CTL_SET_CLKDIV),
347		− CCU_DIV_DBGFS_BIT_ATTR("div_buf", CCU_DIV_CTL_GATE_REF_BUF),
348		− CCU_DIV_DBGFS_BIT_ATTR("div_lock", CCU_DIV_CTL_LOCK_NORMAL)
349		−};
350		−
351		−#define CCU_DIV_DBGFS_BIT_NUM ARRAY_SIZE(ccu_div_bits)
352		−
353		−/*
354		− * It can be dangerous to change the Divider settings behind clock framework
355		− * back, therefore we don't provide any kernel config based compile time option
356		− * for this feature to enable.
357		− */
358		−#undef CCU_DIV_ALLOW_WRITE_DEBUGFS
359		−#ifdef CCU_DIV_ALLOW_WRITE_DEBUGFS
360		−
361		−static int ccu_div_dbgfs_bit_set(void *priv, u64 val)
362		−{
363		− const struct ccu_div_dbgfs_bit *bit = priv;
364		− struct ccu_div *div = bit->div;
365		− unsigned long flags;
366		−
367		− spin_lock_irqsave(&div->lock, flags);
368		− regmap_update_bits(div->sys_regs, div->reg_ctl,
369		− bit->mask, val ? bit->mask : 0);
370		− spin_unlock_irqrestore(&div->lock, flags);
371		−
372		− return 0;
373		−}
374		−
375		−static int ccu_div_dbgfs_var_clkdiv_set(void *priv, u64 val)
376		−{
377		− struct ccu_div *div = priv;
378		− unsigned long flags;
379		− u32 data;
380		−
381		− val = clamp_t(u64, val, CCU_DIV_CLKDIV_MIN,
382		− CCU_DIV_CLKDIV_MAX(div->mask));
383		− data = ccu_div_prep(div->mask, val);
384		−
385		− spin_lock_irqsave(&div->lock, flags);
386		− regmap_update_bits(div->sys_regs, div->reg_ctl, div->mask, data);
387		− spin_unlock_irqrestore(&div->lock, flags);
388		−
389		− return 0;
390		−}
391		−
392		−#define ccu_div_dbgfs_mode 0644
393		−
394		−#else /* !CCU_DIV_ALLOW_WRITE_DEBUGFS */
395		−
396		−#define ccu_div_dbgfs_bit_set NULL
397		−#define ccu_div_dbgfs_var_clkdiv_set NULL
398		−#define ccu_div_dbgfs_mode 0444
399		−
400		−#endif /* !CCU_DIV_ALLOW_WRITE_DEBUGFS */
401		−
402		−static int ccu_div_dbgfs_bit_get(void priv, u64 val)
403		−{
404		− const struct ccu_div_dbgfs_bit *bit = priv;
405		− struct ccu_div *div = bit->div;
406		− u32 data = 0;
407		−
408		− regmap_read(div->sys_regs, div->reg_ctl, &data);
409		− *val = !!(data & bit->mask);
410		−
411		− return 0;
412		−}
413		−DEFINE_DEBUGFS_ATTRIBUTE(ccu_div_dbgfs_bit_fops,
414		− ccu_div_dbgfs_bit_get, ccu_div_dbgfs_bit_set, "%llu\n");
415		−
416		−static int ccu_div_dbgfs_var_clkdiv_get(void priv, u64 val)
417		−{
418		− struct ccu_div *div = priv;
419		− u32 data = 0;
420		−
421		− regmap_read(div->sys_regs, div->reg_ctl, &data);
422		− *val = ccu_div_get(div->mask, data);
423		−
424		− return 0;
425		−}
426		−DEFINE_DEBUGFS_ATTRIBUTE(ccu_div_dbgfs_var_clkdiv_fops,
427		− ccu_div_dbgfs_var_clkdiv_get, ccu_div_dbgfs_var_clkdiv_set, "%llu\n");
428		−
429		−static int ccu_div_dbgfs_fixed_clkdiv_get(void priv, u64 val)
430		−{
431		− struct ccu_div *div = priv;
432		−
433		− *val = div->divider;
434		−
435		− return 0;
436		−}
437		−DEFINE_DEBUGFS_ATTRIBUTE(ccu_div_dbgfs_fixed_clkdiv_fops,
438		− ccu_div_dbgfs_fixed_clkdiv_get, NULL, "%llu\n");
439		−
440		−static void ccu_div_var_debug_init(struct clk_hw hw, struct dentry dentry)
441		−{
442		− struct ccu_div *div = to_ccu_div(hw);
443		− struct ccu_div_dbgfs_bit *bits;
444		− int didx, bidx, num = 2;
445		− const char *name;
446		−
447		− num += !!(div->flags & CLK_SET_RATE_GATE) +
448		− !!(div->features & CCU_DIV_RESET_DOMAIN);
449		−
450		− bits = kzalloc_objs(*bits, num);
451		− if (!bits)
452		− return;
453		−
454		− for (didx = 0, bidx = 0; bidx < CCU_DIV_DBGFS_BIT_NUM; ++bidx) {
455		− name = ccu_div_bits[bidx].name;
456		− if (!(div->flags & CLK_SET_RATE_GATE) &&
457		− !strcmp("div_en", name)) {
458		− continue;
459		− }
460		−
461		− if (!(div->features & CCU_DIV_RESET_DOMAIN) &&
462		− !strcmp("div_rst", name)) {
463		− continue;
464		− }
465		−
466		− if (!strcmp("div_buf", name))
467		− continue;
468		−
469		− bits[didx] = ccu_div_bits[bidx];
470		− bits[didx].div = div;
471		−
472		− if (div->features & CCU_DIV_LOCK_SHIFTED &&
473		− !strcmp("div_lock", name)) {
474		− bits[didx].mask = CCU_DIV_CTL_LOCK_SHIFTED;
475		− }
476		−
477		− debugfs_create_file_unsafe(bits[didx].name, ccu_div_dbgfs_mode,
478		− dentry, &bits[didx],
479		− &ccu_div_dbgfs_bit_fops);
480		− ++didx;
481		− }
482		−
483		− debugfs_create_file_unsafe("div_clkdiv", ccu_div_dbgfs_mode, dentry,
484		− div, &ccu_div_dbgfs_var_clkdiv_fops);
485		−}
486		−
487		−static void ccu_div_gate_debug_init(struct clk_hw hw, struct dentry dentry)
488		−{
489		− struct ccu_div *div = to_ccu_div(hw);
490		− struct ccu_div_dbgfs_bit *bit;
491		−
492		− bit = kmalloc_obj(*bit);
493		− if (!bit)
494		− return;
495		−
496		− *bit = ccu_div_bits[0];
497		− bit->div = div;
498		− debugfs_create_file_unsafe(bit->name, ccu_div_dbgfs_mode, dentry, bit,
499		− &ccu_div_dbgfs_bit_fops);
500		−
501		− debugfs_create_file_unsafe("div_clkdiv", 0400, dentry, div,
502		− &ccu_div_dbgfs_fixed_clkdiv_fops);
503		−}
504		−
505		−static void ccu_div_buf_debug_init(struct clk_hw hw, struct dentry dentry)
506		−{
507		− struct ccu_div *div = to_ccu_div(hw);
508		− struct ccu_div_dbgfs_bit *bit;
509		−
510		− bit = kmalloc_obj(*bit);
511		− if (!bit)
512		− return;
513		−
514		− *bit = ccu_div_bits[3];
515		− bit->div = div;
516		− debugfs_create_file_unsafe(bit->name, ccu_div_dbgfs_mode, dentry, bit,
517		− &ccu_div_dbgfs_bit_fops);
518		−}
519		−
520		−static void ccu_div_fixed_debug_init(struct clk_hw hw, struct dentry dentry)
521		−{
522		− struct ccu_div *div = to_ccu_div(hw);
523		−
524		− debugfs_create_file_unsafe("div_clkdiv", 0400, dentry, div,
525		− &ccu_div_dbgfs_fixed_clkdiv_fops);
526		−}
527		−
528		−#else /* !CONFIG_DEBUG_FS */
529		−
530		−#define ccu_div_var_debug_init NULL
531		−#define ccu_div_gate_debug_init NULL
532		−#define ccu_div_buf_debug_init NULL
533		−#define ccu_div_fixed_debug_init NULL
534		−
535		−#endif /* !CONFIG_DEBUG_FS */
536		−
537		−static const struct clk_ops ccu_div_var_gate_to_set_ops = {
538		− .enable = ccu_div_var_enable,
539		− .disable = ccu_div_gate_disable,
540		− .is_enabled = ccu_div_gate_is_enabled,
541		− .recalc_rate = ccu_div_var_recalc_rate,
542		− .determine_rate = ccu_div_var_determine_rate,
543		− .set_rate = ccu_div_var_set_rate_fast,
544		− .debug_init = ccu_div_var_debug_init
545		−};
546		−
547		−static const struct clk_ops ccu_div_var_nogate_ops = {
548		− .recalc_rate = ccu_div_var_recalc_rate,
549		− .determine_rate = ccu_div_var_determine_rate,
550		− .set_rate = ccu_div_var_set_rate_slow,
551		− .debug_init = ccu_div_var_debug_init
552		−};
553		−
554		−static const struct clk_ops ccu_div_gate_ops = {
555		− .enable = ccu_div_gate_enable,
556		− .disable = ccu_div_gate_disable,
557		− .is_enabled = ccu_div_gate_is_enabled,
558		− .recalc_rate = ccu_div_fixed_recalc_rate,
559		− .determine_rate = ccu_div_fixed_determine_rate,
560		− .set_rate = ccu_div_fixed_set_rate,
561		− .debug_init = ccu_div_gate_debug_init
562		−};
563		−
564		−static const struct clk_ops ccu_div_buf_ops = {
565		− .enable = ccu_div_buf_enable,
566		− .disable = ccu_div_buf_disable,
567		− .is_enabled = ccu_div_buf_is_enabled,
568		− .debug_init = ccu_div_buf_debug_init
569		−};
570		−
571		−static const struct clk_ops ccu_div_fixed_ops = {
572		− .recalc_rate = ccu_div_fixed_recalc_rate,
573		− .determine_rate = ccu_div_fixed_determine_rate,
574		− .set_rate = ccu_div_fixed_set_rate,
575		− .debug_init = ccu_div_fixed_debug_init
576		−};
577		−
578		−struct ccu_div ccu_div_hw_register(const struct ccu_div_init_data div_init)
579		−{
580		− struct clk_parent_data parent_data = { };
581		− struct clk_init_data hw_init = { };
582		− struct ccu_div *div;
583		− int ret;
584		−
585		− if (!div_init)
586		− return ERR_PTR(-EINVAL);
587		−
588		− div = kzalloc_obj(*div);
589		− if (!div)
590		− return ERR_PTR(-ENOMEM);
591		−
592		− /*
593		− * Note since Baikal-T1 System Controller registers are MMIO-backed
594		− * we won't check the regmap IO operations return status, because it
595		− * must be zero anyway.
596		− */
597		− div->hw.init = &hw_init;
598		− div->id = div_init->id;
599		− div->reg_ctl = div_init->base + CCU_DIV_CTL;
600		− div->sys_regs = div_init->sys_regs;
601		− div->flags = div_init->flags;
602		− div->features = div_init->features;
603		− spin_lock_init(&div->lock);
604		−
605		− hw_init.name = div_init->name;
606		− hw_init.flags = div_init->flags;
607		−
608		− if (div_init->type == CCU_DIV_VAR) {
609		− if (hw_init.flags & CLK_SET_RATE_GATE)
610		− hw_init.ops = &ccu_div_var_gate_to_set_ops;
611		− else
612		− hw_init.ops = &ccu_div_var_nogate_ops;
613		− div->mask = CCU_DIV_CTL_CLKDIV_MASK(div_init->width);
614		− } else if (div_init->type == CCU_DIV_GATE) {
615		− hw_init.ops = &ccu_div_gate_ops;
616		− div->divider = div_init->divider;
617		− } else if (div_init->type == CCU_DIV_BUF) {
618		− hw_init.ops = &ccu_div_buf_ops;
619		− } else if (div_init->type == CCU_DIV_FIXED) {
620		− hw_init.ops = &ccu_div_fixed_ops;
621		− div->divider = div_init->divider;
622		− } else {
623		− ret = -EINVAL;
624		− goto err_free_div;
625		− }
626		−
627		− if (!div_init->parent_name) {
628		− ret = -EINVAL;
629		− goto err_free_div;
630		− }
631		− parent_data.fw_name = div_init->parent_name;
632		− parent_data.name = div_init->parent_name;
633		− hw_init.parent_data = &parent_data;
634		− hw_init.num_parents = 1;
635		−
636		− ret = of_clk_hw_register(div_init->np, &div->hw);
637		− if (ret)
638		− goto err_free_div;
639		−
640		− return div;
641		−
642		−err_free_div:
643		− kfree(div);
644		−
645		− return ERR_PTR(ret);
646		−}
647		−
648		−void ccu_div_hw_unregister(struct ccu_div *div)
649		−{
650		− clk_hw_unregister(&div->hw);
651		−
652		− kfree(div);
653		−}

drivers/clk/baikal-t1/ccu-div.h+0−121

@@ -1,121 +0,0 @@
1		−/* SPDX-License-Identifier: GPL-2.0-only */
2		−/*
3		− * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
4		− *
5		− * Baikal-T1 CCU Dividers interface driver
6		− */
7		−#ifndef __CLK_BT1_CCU_DIV_H__
8		−#define __CLK_BT1_CCU_DIV_H__
9		−
10		−#include <linux/clk-provider.h>
11		−#include <linux/spinlock.h>
12		−#include <linux/regmap.h>
13		−#include <linux/bits.h>
14		−#include <linux/of.h>
15		−
16		−/*
17		− * CCU Divider private clock IDs
18		− * @CCU_SYS_SATA_CLK: CCU SATA internal clock
19		− * @CCU_SYS_XGMAC_CLK: CCU XGMAC internal clock
20		− */
21		−#define CCU_SYS_SATA_CLK -1
22		−#define CCU_SYS_XGMAC_CLK -2
23		−
24		−/*
25		− * CCU Divider private flags
26		− * @CCU_DIV_BASIC: Basic divider clock required by the kernel as early as
27		− * possible.
28		− * @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1.
29		− * It can be 0 though, which is functionally the same.
30		− * @CCU_DIV_SKIP_ONE_TO_THREE: For some reason divider can't be within [1,3].
31		− * It can be either 0 or greater than 3.
32		− * @CCU_DIV_LOCK_SHIFTED: Find lock-bit at non-standard position.
33		− * @CCU_DIV_RESET_DOMAIN: There is a clock domain reset handle.
34		− */
35		−#define CCU_DIV_BASIC BIT(0)
36		−#define CCU_DIV_SKIP_ONE BIT(1)
37		−#define CCU_DIV_SKIP_ONE_TO_THREE BIT(2)
38		−#define CCU_DIV_LOCK_SHIFTED BIT(3)
39		−#define CCU_DIV_RESET_DOMAIN BIT(4)
40		−
41		−/*
42		− * enum ccu_div_type - CCU Divider types
43		− * @CCU_DIV_VAR: Clocks gate with variable divider.
44		− * @CCU_DIV_GATE: Clocks gate with fixed divider.
45		− * @CCU_DIV_BUF: Clock gate with no divider.
46		− * @CCU_DIV_FIXED: Ungateable clock with fixed divider.
47		− */
48		−enum ccu_div_type {
49		− CCU_DIV_VAR,
50		− CCU_DIV_GATE,
51		− CCU_DIV_BUF,
52		− CCU_DIV_FIXED
53		−};
54		−
55		−/*
56		− * struct ccu_div_init_data - CCU Divider initialization data
57		− * @id: Clocks private identifier.
58		− * @name: Clocks name.
59		− * @parent_name: Parent clocks name in a fw node.
60		− * @base: Divider register base address with respect to the sys_regs base.
61		− * @sys_regs: Baikal-T1 System Controller registers map.
62		− * @np: Pointer to the node describing the CCU Dividers.
63		− * @type: CCU divider type (variable, fixed with and without gate).
64		− * @width: Divider width if it's variable.
65		− * @divider: Divider fixed value.
66		− * @flags: CCU Divider clock flags.
67		− * @features: CCU Divider private features.
68		− */
69		−struct ccu_div_init_data {
70		− unsigned int id;
71		− const char *name;
72		− const char *parent_name;
73		− unsigned int base;
74		− struct regmap *sys_regs;
75		− struct device_node *np;
76		− enum ccu_div_type type;
77		− union {
78		− unsigned int width;
79		− unsigned int divider;
80		− };
81		− unsigned long flags;
82		− unsigned long features;
83		−};
84		−
85		−/*
86		− * struct ccu_div - CCU Divider descriptor
87		− * @hw: clk_hw of the divider.
88		− * @id: Clock private identifier.
89		− * @reg_ctl: Divider control register base address.
90		− * @sys_regs: Baikal-T1 System Controller registers map.
91		− * @lock: Divider state change spin-lock.
92		− * @mask: Divider field mask.
93		− * @divider: Divider fixed value.
94		− * @flags: Divider clock flags.
95		− * @features: CCU Divider private features.
96		− */
97		−struct ccu_div {
98		− struct clk_hw hw;
99		− unsigned int id;
100		− unsigned int reg_ctl;
101		− struct regmap *sys_regs;
102		− spinlock_t lock;
103		− union {
104		− u32 mask;
105		− unsigned int divider;
106		− };
107		− unsigned long flags;
108		− unsigned long features;
109		−};
110		−#define to_ccu_div(_hw) container_of(_hw, struct ccu_div, hw)
111		−
112		−static inline struct clk_hw ccu_div_get_clk_hw(struct ccu_div div)
113		−{
114		− return div ? &div->hw : NULL;
115		−}
116		−
117		−struct ccu_div ccu_div_hw_register(const struct ccu_div_init_data init);
118		−
119		−void ccu_div_hw_unregister(struct ccu_div *div);
120		−
121		−#endif /* __CLK_BT1_CCU_DIV_H__ */

drivers/clk/baikal-t1/ccu-pll.c+0−560

@@ -1,560 +0,0 @@
1		−// SPDX-License-Identifier: GPL-2.0-only
2		−/*
3		− * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
4		− *
5		− * Authors:
6		− * Serge Semin <Sergey.Semin@baikalelectronics.ru>
7		− * Dmitry Dunaev <dmitry.dunaev@baikalelectronics.ru>
8		− *
9		− * Baikal-T1 CCU PLL interface driver
10		− */
11		−
12		−#define pr_fmt(fmt) "bt1-ccu-pll: " fmt
13		−
14		−#include <linux/kernel.h>
15		−#include <linux/printk.h>
16		−#include <linux/limits.h>
17		−#include <linux/bits.h>
18		−#include <linux/bitfield.h>
19		−#include <linux/slab.h>
20		−#include <linux/clk-provider.h>
21		−#include <linux/of.h>
22		−#include <linux/spinlock.h>
23		−#include <linux/regmap.h>
24		−#include <linux/iopoll.h>
25		−#include <linux/time64.h>
26		−#include <linux/rational.h>
27		−#include <linux/debugfs.h>
28		−
29		−#include "ccu-pll.h"
30		−
31		−#define CCU_PLL_CTL 0x000
32		−#define CCU_PLL_CTL_EN BIT(0)
33		−#define CCU_PLL_CTL_RST BIT(1)
34		−#define CCU_PLL_CTL_CLKR_FLD 2
35		−#define CCU_PLL_CTL_CLKR_MASK GENMASK(7, CCU_PLL_CTL_CLKR_FLD)
36		−#define CCU_PLL_CTL_CLKF_FLD 8
37		−#define CCU_PLL_CTL_CLKF_MASK GENMASK(20, CCU_PLL_CTL_CLKF_FLD)
38		−#define CCU_PLL_CTL_CLKOD_FLD 21
39		−#define CCU_PLL_CTL_CLKOD_MASK GENMASK(24, CCU_PLL_CTL_CLKOD_FLD)
40		−#define CCU_PLL_CTL_BYPASS BIT(30)
41		−#define CCU_PLL_CTL_LOCK BIT(31)
42		−#define CCU_PLL_CTL1 0x004
43		−#define CCU_PLL_CTL1_BWADJ_FLD 3
44		−#define CCU_PLL_CTL1_BWADJ_MASK GENMASK(14, CCU_PLL_CTL1_BWADJ_FLD)
45		−
46		−#define CCU_PLL_LOCK_CHECK_RETRIES 50
47		−
48		−#define CCU_PLL_NR_MAX \
49		− ((CCU_PLL_CTL_CLKR_MASK >> CCU_PLL_CTL_CLKR_FLD) + 1)
50		−#define CCU_PLL_NF_MAX \
51		− ((CCU_PLL_CTL_CLKF_MASK >> (CCU_PLL_CTL_CLKF_FLD + 1)) + 1)
52		−#define CCU_PLL_OD_MAX \
53		− ((CCU_PLL_CTL_CLKOD_MASK >> CCU_PLL_CTL_CLKOD_FLD) + 1)
54		−#define CCU_PLL_NB_MAX \
55		− ((CCU_PLL_CTL1_BWADJ_MASK >> CCU_PLL_CTL1_BWADJ_FLD) + 1)
56		−#define CCU_PLL_FDIV_MIN 427000UL
57		−#define CCU_PLL_FDIV_MAX 3500000000UL
58		−#define CCU_PLL_FOUT_MIN 200000000UL
59		−#define CCU_PLL_FOUT_MAX 2500000000UL
60		−#define CCU_PLL_FVCO_MIN 700000000UL
61		−#define CCU_PLL_FVCO_MAX 3500000000UL
62		−#define CCU_PLL_CLKOD_FACTOR 2
63		−
64		−static inline unsigned long ccu_pll_lock_delay_us(unsigned long ref_clk,
65		− unsigned long nr)
66		−{
67		− u64 us = 500ULL * nr * USEC_PER_SEC;
68		−
69		− do_div(us, ref_clk);
70		−
71		− return us;
72		−}
73		−
74		−static inline unsigned long ccu_pll_calc_freq(unsigned long ref_clk,
75		− unsigned long nr,
76		− unsigned long nf,
77		− unsigned long od)
78		−{
79		− u64 tmp = ref_clk;
80		−
81		− do_div(tmp, nr);
82		− tmp *= nf;
83		− do_div(tmp, od);
84		−
85		− return tmp;
86		−}
87		−
88		−static int ccu_pll_reset(struct ccu_pll *pll, unsigned long ref_clk,
89		− unsigned long nr)
90		−{
91		− unsigned long ud, ut;
92		− u32 val;
93		−
94		− ud = ccu_pll_lock_delay_us(ref_clk, nr);
95		− ut = ud * CCU_PLL_LOCK_CHECK_RETRIES;
96		−
97		− regmap_update_bits(pll->sys_regs, pll->reg_ctl,
98		− CCU_PLL_CTL_RST, CCU_PLL_CTL_RST);
99		−
100		− return regmap_read_poll_timeout_atomic(pll->sys_regs, pll->reg_ctl, val,
101		− val & CCU_PLL_CTL_LOCK, ud, ut);
102		−}
103		−
104		−static int ccu_pll_enable(struct clk_hw *hw)
105		−{
106		− struct clk_hw *parent_hw = clk_hw_get_parent(hw);
107		− struct ccu_pll *pll = to_ccu_pll(hw);
108		− unsigned long flags;
109		− u32 val = 0;
110		− int ret;
111		−
112		− if (!parent_hw) {
113		− pr_err("Can't enable '%s' with no parent", clk_hw_get_name(hw));
114		− return -EINVAL;
115		− }
116		−
117		− regmap_read(pll->sys_regs, pll->reg_ctl, &val);
118		− if (val & CCU_PLL_CTL_EN)
119		− return 0;
120		−
121		− spin_lock_irqsave(&pll->lock, flags);
122		− regmap_write(pll->sys_regs, pll->reg_ctl, val \| CCU_PLL_CTL_EN);
123		− ret = ccu_pll_reset(pll, clk_hw_get_rate(parent_hw),
124		− FIELD_GET(CCU_PLL_CTL_CLKR_MASK, val) + 1);
125		− spin_unlock_irqrestore(&pll->lock, flags);
126		− if (ret)
127		− pr_err("PLL '%s' reset timed out\n", clk_hw_get_name(hw));
128		−
129		− return ret;
130		−}
131		−
132		−static void ccu_pll_disable(struct clk_hw *hw)
133		−{
134		− struct ccu_pll *pll = to_ccu_pll(hw);
135		− unsigned long flags;
136		−
137		− spin_lock_irqsave(&pll->lock, flags);
138		− regmap_update_bits(pll->sys_regs, pll->reg_ctl, CCU_PLL_CTL_EN, 0);
139		− spin_unlock_irqrestore(&pll->lock, flags);
140		−}
141		−
142		−static int ccu_pll_is_enabled(struct clk_hw *hw)
143		−{
144		− struct ccu_pll *pll = to_ccu_pll(hw);
145		− u32 val = 0;
146		−
147		− regmap_read(pll->sys_regs, pll->reg_ctl, &val);
148		−
149		− return !!(val & CCU_PLL_CTL_EN);
150		−}
151		−
152		−static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw,
153		− unsigned long parent_rate)
154		−{
155		− struct ccu_pll *pll = to_ccu_pll(hw);
156		− unsigned long nr, nf, od;
157		− u32 val = 0;
158		−
159		− regmap_read(pll->sys_regs, pll->reg_ctl, &val);
160		− nr = FIELD_GET(CCU_PLL_CTL_CLKR_MASK, val) + 1;
161		− nf = FIELD_GET(CCU_PLL_CTL_CLKF_MASK, val) + 1;
162		− od = FIELD_GET(CCU_PLL_CTL_CLKOD_MASK, val) + 1;
163		−
164		− return ccu_pll_calc_freq(parent_rate, nr, nf, od);
165		−}
166		−
167		−static void ccu_pll_calc_factors(unsigned long rate, unsigned long parent_rate,
168		− unsigned long nr, unsigned long nf,
169		− unsigned long *od)
170		−{
171		− unsigned long err, freq, min_err = ULONG_MAX;
172		− unsigned long num, denom, n1, d1, nri;
173		− unsigned long nr_max, nf_max, od_max;
174		−
175		− /*
176		− * Make sure PLL is working with valid input signal (Fdiv). If
177		− * you want to speed the function up just reduce CCU_PLL_NR_MAX.
178		− * This will cause a worse approximation though.
179		− */
180		− nri = (parent_rate / CCU_PLL_FDIV_MAX) + 1;
181		− nr_max = min(parent_rate / CCU_PLL_FDIV_MIN, CCU_PLL_NR_MAX);
182		−
183		− /*
184		− * Find a closest [nr;nf;od] vector taking into account the
185		− * limitations like: 1) 700MHz <= Fvco <= 3.5GHz, 2) PLL Od is
186		− * either 1 or even number within the acceptable range (alas 1s
187		− * is also excluded by the next loop).
188		− */
189		− for (; nri <= nr_max; ++nri) {
190		− /* Use Od factor to fulfill the limitation 2). */
191		− num = CCU_PLL_CLKOD_FACTOR * rate;
192		− denom = parent_rate / nri;
193		−
194		− /*
195		− * Make sure Fvco is within the acceptable range to fulfill
196		− * the condition 1). Note due to the CCU_PLL_CLKOD_FACTOR value
197		− * the actual upper limit is also divided by that factor.
198		− * It's not big problem for us since practically there is no
199		− * need in clocks with that high frequency.
200		− */
201		− nf_max = min(CCU_PLL_FVCO_MAX / denom, CCU_PLL_NF_MAX);
202		− od_max = CCU_PLL_OD_MAX / CCU_PLL_CLKOD_FACTOR;
203		−
204		− /*
205		− * Bypass the out-of-bound values, which can't be properly
206		− * handled by the rational fraction approximation algorithm.
207		− */
208		− if (num / denom >= nf_max) {
209		− n1 = nf_max;
210		− d1 = 1;
211		− } else if (denom / num >= od_max) {
212		− n1 = 1;
213		− d1 = od_max;
214		− } else {
215		− rational_best_approximation(num, denom, nf_max, od_max,
216		− &n1, &d1);
217		− }
218		−
219		− /* Select the best approximation of the target rate. */
220		− freq = ccu_pll_calc_freq(parent_rate, nri, n1, d1);
221		− err = abs((int64_t)freq - num);
222		− if (err < min_err) {
223		− min_err = err;
224		− *nr = nri;
225		− *nf = n1;
226		− od = CCU_PLL_CLKOD_FACTOR d1;
227		− }
228		− }
229		−}
230		−
231		−static int ccu_pll_determine_rate(struct clk_hw *hw,
232		− struct clk_rate_request *req)
233		−{
234		− unsigned long nr = 1, nf = 1, od = 1;
235		−
236		− ccu_pll_calc_factors(req->rate, req->best_parent_rate, &nr, &nf, &od);
237		−
238		− req->rate = ccu_pll_calc_freq(req->best_parent_rate, nr, nf, od);
239		−
240		− return 0;
241		−}
242		−
243		−/*
244		− * This method is used for PLLs, which support the on-the-fly dividers
245		− * adjustment. So there is no need in gating such clocks.
246		− */
247		−static int ccu_pll_set_rate_reset(struct clk_hw *hw, unsigned long rate,
248		− unsigned long parent_rate)
249		−{
250		− struct ccu_pll *pll = to_ccu_pll(hw);
251		− unsigned long nr, nf, od;
252		− unsigned long flags;
253		− u32 mask, val;
254		− int ret;
255		−
256		− ccu_pll_calc_factors(rate, parent_rate, &nr, &nf, &od);
257		−
258		− mask = CCU_PLL_CTL_CLKR_MASK \| CCU_PLL_CTL_CLKF_MASK \|
259		− CCU_PLL_CTL_CLKOD_MASK;
260		− val = FIELD_PREP(CCU_PLL_CTL_CLKR_MASK, nr - 1) \|
261		− FIELD_PREP(CCU_PLL_CTL_CLKF_MASK, nf - 1) \|
262		− FIELD_PREP(CCU_PLL_CTL_CLKOD_MASK, od - 1);
263		−
264		− spin_lock_irqsave(&pll->lock, flags);
265		− regmap_update_bits(pll->sys_regs, pll->reg_ctl, mask, val);
266		− ret = ccu_pll_reset(pll, parent_rate, nr);
267		− spin_unlock_irqrestore(&pll->lock, flags);
268		− if (ret)
269		− pr_err("PLL '%s' reset timed out\n", clk_hw_get_name(hw));
270		−
271		− return ret;
272		−}
273		−
274		−/*
275		− * This method is used for PLLs, which don't support the on-the-fly dividers
276		− * adjustment. So the corresponding clocks are supposed to be gated first.
277		− */
278		−static int ccu_pll_set_rate_norst(struct clk_hw *hw, unsigned long rate,
279		− unsigned long parent_rate)
280		−{
281		− struct ccu_pll *pll = to_ccu_pll(hw);
282		− unsigned long nr, nf, od;
283		− unsigned long flags;
284		− u32 mask, val;
285		−
286		− ccu_pll_calc_factors(rate, parent_rate, &nr, &nf, &od);
287		−
288		− /*
289		− * Disable PLL if it was enabled by default or left enabled by the
290		− * system bootloader.
291		− */
292		− mask = CCU_PLL_CTL_CLKR_MASK \| CCU_PLL_CTL_CLKF_MASK \|
293		− CCU_PLL_CTL_CLKOD_MASK \| CCU_PLL_CTL_EN;
294		− val = FIELD_PREP(CCU_PLL_CTL_CLKR_MASK, nr - 1) \|
295		− FIELD_PREP(CCU_PLL_CTL_CLKF_MASK, nf - 1) \|
296		− FIELD_PREP(CCU_PLL_CTL_CLKOD_MASK, od - 1);
297		−
298		− spin_lock_irqsave(&pll->lock, flags);
299		− regmap_update_bits(pll->sys_regs, pll->reg_ctl, mask, val);
300		− spin_unlock_irqrestore(&pll->lock, flags);
301		−
302		− return 0;
303		−}
304		−
305		−#ifdef CONFIG_DEBUG_FS
306		−
307		−struct ccu_pll_dbgfs_bit {
308		− struct ccu_pll *pll;
309		− const char *name;
310		− unsigned int reg;
311		− u32 mask;
312		−};
313		−
314		−struct ccu_pll_dbgfs_fld {
315		− struct ccu_pll *pll;
316		− const char *name;
317		− unsigned int reg;
318		− unsigned int lsb;
319		− u32 mask;
320		− u32 min;
321		− u32 max;
322		−};
323		−
324		−#define CCU_PLL_DBGFS_BIT_ATTR(_name, _reg, _mask) \
325		− { \
326		− .name = _name, \
327		− .reg = _reg, \
328		− .mask = _mask \
329		− }
330		−
331		−#define CCU_PLL_DBGFS_FLD_ATTR(_name, _reg, _lsb, _mask, _min, _max) \
332		− { \
333		− .name = _name, \
334		− .reg = _reg, \
335		− .lsb = _lsb, \
336		− .mask = _mask, \
337		− .min = _min, \
338		− .max = _max \
339		− }
340		−
341		−static const struct ccu_pll_dbgfs_bit ccu_pll_bits[] = {
342		− CCU_PLL_DBGFS_BIT_ATTR("pll_en", CCU_PLL_CTL, CCU_PLL_CTL_EN),
343		− CCU_PLL_DBGFS_BIT_ATTR("pll_rst", CCU_PLL_CTL, CCU_PLL_CTL_RST),
344		− CCU_PLL_DBGFS_BIT_ATTR("pll_bypass", CCU_PLL_CTL, CCU_PLL_CTL_BYPASS),
345		− CCU_PLL_DBGFS_BIT_ATTR("pll_lock", CCU_PLL_CTL, CCU_PLL_CTL_LOCK)
346		−};
347		−
348		−#define CCU_PLL_DBGFS_BIT_NUM ARRAY_SIZE(ccu_pll_bits)
349		−
350		−static const struct ccu_pll_dbgfs_fld ccu_pll_flds[] = {
351		− CCU_PLL_DBGFS_FLD_ATTR("pll_nr", CCU_PLL_CTL, CCU_PLL_CTL_CLKR_FLD,
352		− CCU_PLL_CTL_CLKR_MASK, 1, CCU_PLL_NR_MAX),
353		− CCU_PLL_DBGFS_FLD_ATTR("pll_nf", CCU_PLL_CTL, CCU_PLL_CTL_CLKF_FLD,
354		− CCU_PLL_CTL_CLKF_MASK, 1, CCU_PLL_NF_MAX),
355		− CCU_PLL_DBGFS_FLD_ATTR("pll_od", CCU_PLL_CTL, CCU_PLL_CTL_CLKOD_FLD,
356		− CCU_PLL_CTL_CLKOD_MASK, 1, CCU_PLL_OD_MAX),
357		− CCU_PLL_DBGFS_FLD_ATTR("pll_nb", CCU_PLL_CTL1, CCU_PLL_CTL1_BWADJ_FLD,
358		− CCU_PLL_CTL1_BWADJ_MASK, 1, CCU_PLL_NB_MAX)
359		−};
360		−
361		−#define CCU_PLL_DBGFS_FLD_NUM ARRAY_SIZE(ccu_pll_flds)
362		−
363		−/*
364		− * It can be dangerous to change the PLL settings behind clock framework back,
365		− * therefore we don't provide any kernel config based compile time option for
366		− * this feature to enable.
367		− */
368		−#undef CCU_PLL_ALLOW_WRITE_DEBUGFS
369		−#ifdef CCU_PLL_ALLOW_WRITE_DEBUGFS
370		−
371		−static int ccu_pll_dbgfs_bit_set(void *priv, u64 val)
372		−{
373		− const struct ccu_pll_dbgfs_bit *bit = priv;
374		− struct ccu_pll *pll = bit->pll;
375		− unsigned long flags;
376		−
377		− spin_lock_irqsave(&pll->lock, flags);
378		− regmap_update_bits(pll->sys_regs, pll->reg_ctl + bit->reg,
379		− bit->mask, val ? bit->mask : 0);
380		− spin_unlock_irqrestore(&pll->lock, flags);
381		−
382		− return 0;
383		−}
384		−
385		−static int ccu_pll_dbgfs_fld_set(void *priv, u64 val)
386		−{
387		− struct ccu_pll_dbgfs_fld *fld = priv;
388		− struct ccu_pll *pll = fld->pll;
389		− unsigned long flags;
390		− u32 data;
391		−
392		− val = clamp_t(u64, val, fld->min, fld->max);
393		− data = ((val - 1) << fld->lsb) & fld->mask;
394		−
395		− spin_lock_irqsave(&pll->lock, flags);
396		− regmap_update_bits(pll->sys_regs, pll->reg_ctl + fld->reg, fld->mask,
397		− data);
398		− spin_unlock_irqrestore(&pll->lock, flags);
399		−
400		− return 0;
401		−}
402		−
403		−#define ccu_pll_dbgfs_mode 0644
404		−
405		−#else /* !CCU_PLL_ALLOW_WRITE_DEBUGFS */
406		−
407		−#define ccu_pll_dbgfs_bit_set NULL
408		−#define ccu_pll_dbgfs_fld_set NULL
409		−#define ccu_pll_dbgfs_mode 0444
410		−
411		−#endif /* !CCU_PLL_ALLOW_WRITE_DEBUGFS */
412		−
413		−static int ccu_pll_dbgfs_bit_get(void priv, u64 val)
414		−{
415		− struct ccu_pll_dbgfs_bit *bit = priv;
416		− struct ccu_pll *pll = bit->pll;
417		− u32 data = 0;
418		−
419		− regmap_read(pll->sys_regs, pll->reg_ctl + bit->reg, &data);
420		− *val = !!(data & bit->mask);
421		−
422		− return 0;
423		−}
424		−DEFINE_DEBUGFS_ATTRIBUTE(ccu_pll_dbgfs_bit_fops,
425		− ccu_pll_dbgfs_bit_get, ccu_pll_dbgfs_bit_set, "%llu\n");
426		−
427		−static int ccu_pll_dbgfs_fld_get(void priv, u64 val)
428		−{
429		− struct ccu_pll_dbgfs_fld *fld = priv;
430		− struct ccu_pll *pll = fld->pll;
431		− u32 data = 0;
432		−
433		− regmap_read(pll->sys_regs, pll->reg_ctl + fld->reg, &data);
434		− *val = ((data & fld->mask) >> fld->lsb) + 1;
435		−
436		− return 0;
437		−}
438		−DEFINE_DEBUGFS_ATTRIBUTE(ccu_pll_dbgfs_fld_fops,
439		− ccu_pll_dbgfs_fld_get, ccu_pll_dbgfs_fld_set, "%llu\n");
440		−
441		−static void ccu_pll_debug_init(struct clk_hw hw, struct dentry dentry)
442		−{
443		− struct ccu_pll *pll = to_ccu_pll(hw);
444		− struct ccu_pll_dbgfs_bit *bits;
445		− struct ccu_pll_dbgfs_fld *flds;
446		− int idx;
447		−
448		− bits = kzalloc_objs(*bits, CCU_PLL_DBGFS_BIT_NUM);
449		− if (!bits)
450		− return;
451		−
452		− for (idx = 0; idx < CCU_PLL_DBGFS_BIT_NUM; ++idx) {
453		− bits[idx] = ccu_pll_bits[idx];
454		− bits[idx].pll = pll;
455		−
456		− debugfs_create_file_unsafe(bits[idx].name, ccu_pll_dbgfs_mode,
457		− dentry, &bits[idx],
458		− &ccu_pll_dbgfs_bit_fops);
459		− }
460		−
461		− flds = kzalloc_objs(*flds, CCU_PLL_DBGFS_FLD_NUM);
462		− if (!flds)
463		− return;
464		−
465		− for (idx = 0; idx < CCU_PLL_DBGFS_FLD_NUM; ++idx) {
466		− flds[idx] = ccu_pll_flds[idx];
467		− flds[idx].pll = pll;
468		−
469		− debugfs_create_file_unsafe(flds[idx].name, ccu_pll_dbgfs_mode,
470		− dentry, &flds[idx],
471		− &ccu_pll_dbgfs_fld_fops);
472		− }
473		−}
474		−
475		−#else /* !CONFIG_DEBUG_FS */
476		−
477		−#define ccu_pll_debug_init NULL
478		−
479		−#endif /* !CONFIG_DEBUG_FS */
480		−
481		−static const struct clk_ops ccu_pll_gate_to_set_ops = {
482		− .enable = ccu_pll_enable,
483		− .disable = ccu_pll_disable,
484		− .is_enabled = ccu_pll_is_enabled,
485		− .recalc_rate = ccu_pll_recalc_rate,
486		− .determine_rate = ccu_pll_determine_rate,
487		− .set_rate = ccu_pll_set_rate_norst,
488		− .debug_init = ccu_pll_debug_init
489		−};
490		−
491		−static const struct clk_ops ccu_pll_straight_set_ops = {
492		− .enable = ccu_pll_enable,
493		− .disable = ccu_pll_disable,
494		− .is_enabled = ccu_pll_is_enabled,
495		− .recalc_rate = ccu_pll_recalc_rate,
496		− .determine_rate = ccu_pll_determine_rate,
497		− .set_rate = ccu_pll_set_rate_reset,
498		− .debug_init = ccu_pll_debug_init
499		−};
500		−
501		−struct ccu_pll ccu_pll_hw_register(const struct ccu_pll_init_data pll_init)
502		−{
503		− struct clk_parent_data parent_data = { };
504		− struct clk_init_data hw_init = { };
505		− struct ccu_pll *pll;
506		− int ret;
507		−
508		− if (!pll_init)
509		− return ERR_PTR(-EINVAL);
510		−
511		− pll = kzalloc_obj(*pll);
512		− if (!pll)
513		− return ERR_PTR(-ENOMEM);
514		−
515		− /*
516		− * Note since Baikal-T1 System Controller registers are MMIO-backed
517		− * we won't check the regmap IO operations return status, because it
518		− * must be zero anyway.
519		− */
520		− pll->hw.init = &hw_init;
521		− pll->reg_ctl = pll_init->base + CCU_PLL_CTL;
522		− pll->reg_ctl1 = pll_init->base + CCU_PLL_CTL1;
523		− pll->sys_regs = pll_init->sys_regs;
524		− pll->id = pll_init->id;
525		− spin_lock_init(&pll->lock);
526		−
527		− hw_init.name = pll_init->name;
528		− hw_init.flags = pll_init->flags;
529		−
530		− if (hw_init.flags & CLK_SET_RATE_GATE)
531		− hw_init.ops = &ccu_pll_gate_to_set_ops;
532		− else
533		− hw_init.ops = &ccu_pll_straight_set_ops;
534		−
535		− if (!pll_init->parent_name) {
536		− ret = -EINVAL;
537		− goto err_free_pll;
538		− }
539		− parent_data.fw_name = pll_init->parent_name;
540		− hw_init.parent_data = &parent_data;
541		− hw_init.num_parents = 1;
542		−
543		− ret = of_clk_hw_register(pll_init->np, &pll->hw);
544		− if (ret)
545		− goto err_free_pll;
546		−
547		− return pll;
548		−
549		−err_free_pll:
550		− kfree(pll);
551		−
552		− return ERR_PTR(ret);
553		−}
554		−
555		−void ccu_pll_hw_unregister(struct ccu_pll *pll)
556		−{
557		− clk_hw_unregister(&pll->hw);
558		−
559		− kfree(pll);
560		−}

drivers/clk/baikal-t1/ccu-pll.h+0−72

@@ -1,72 +0,0 @@
1		−/* SPDX-License-Identifier: GPL-2.0-only */
2		−/*
3		− * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
4		− *
5		− * Baikal-T1 CCU PLL interface driver
6		− */
7		−#ifndef __CLK_BT1_CCU_PLL_H__
8		−#define __CLK_BT1_CCU_PLL_H__
9		−
10		−#include <linux/clk-provider.h>
11		−#include <linux/spinlock.h>
12		−#include <linux/regmap.h>
13		−#include <linux/bits.h>
14		−#include <linux/of.h>
15		−
16		−/*
17		− * CCU PLL private flags
18		− * @CCU_PLL_BASIC: Basic PLL required by the kernel as early as possible.
19		− */
20		−#define CCU_PLL_BASIC BIT(0)
21		−
22		−/*
23		− * struct ccu_pll_init_data - CCU PLL initialization data
24		− * @id: Clock private identifier.
25		− * @name: Clocks name.
26		− * @parent_name: Clocks parent name in a fw node.
27		− * @base: PLL registers base address with respect to the sys_regs base.
28		− * @sys_regs: Baikal-T1 System Controller registers map.
29		− * @np: Pointer to the node describing the CCU PLLs.
30		− * @flags: PLL clock flags.
31		− * @features: PLL private features.
32		− */
33		−struct ccu_pll_init_data {
34		− unsigned int id;
35		− const char *name;
36		− const char *parent_name;
37		− unsigned int base;
38		− struct regmap *sys_regs;
39		− struct device_node *np;
40		− unsigned long flags;
41		− unsigned long features;
42		−};
43		−
44		−/*
45		− * struct ccu_pll - CCU PLL descriptor
46		− * @hw: clk_hw of the PLL.
47		− * @id: Clock private identifier.
48		− * @reg_ctl: PLL control register base.
49		− * @reg_ctl1: PLL control1 register base.
50		− * @sys_regs: Baikal-T1 System Controller registers map.
51		− * @lock: PLL state change spin-lock.
52		− */
53		−struct ccu_pll {
54		− struct clk_hw hw;
55		− unsigned int id;
56		− unsigned int reg_ctl;
57		− unsigned int reg_ctl1;
58		− struct regmap *sys_regs;
59		− spinlock_t lock;
60		−};
61		−#define to_ccu_pll(_hw) container_of(_hw, struct ccu_pll, hw)
62		−
63		−static inline struct clk_hw ccu_pll_get_clk_hw(struct ccu_pll pll)
64		−{
65		− return pll ? &pll->hw : NULL;
66		−}
67		−
68		−struct ccu_pll ccu_pll_hw_register(const struct ccu_pll_init_data init);
69		−
70		−void ccu_pll_hw_unregister(struct ccu_pll *pll);
71		−
72		−#endif /* __CLK_BT1_CCU_PLL_H__ */

drivers/clk/baikal-t1/ccu-rst.c+0−217

@@ -1,217 +0,0 @@
1		−// SPDX-License-Identifier: GPL-2.0-only
2		−/*
3		− * Copyright (C) 2021 BAIKAL ELECTRONICS, JSC
4		− *
5		− * Authors:
6		− * Serge Semin <Sergey.Semin@baikalelectronics.ru>
7		− *
8		− * Baikal-T1 CCU Resets interface driver
9		− */
10		−
11		−#define pr_fmt(fmt) "bt1-ccu-rst: " fmt
12		−
13		−#include <linux/bits.h>
14		−#include <linux/delay.h>
15		−#include <linux/kernel.h>
16		−#include <linux/of.h>
17		−#include <linux/printk.h>
18		−#include <linux/regmap.h>
19		−#include <linux/reset-controller.h>
20		−#include <linux/slab.h>
21		−
22		−#include <dt-bindings/reset/bt1-ccu.h>
23		−
24		−#include "ccu-rst.h"
25		−
26		−#define CCU_AXI_MAIN_BASE 0x030
27		−#define CCU_AXI_DDR_BASE 0x034
28		−#define CCU_AXI_SATA_BASE 0x038
29		−#define CCU_AXI_GMAC0_BASE 0x03C
30		−#define CCU_AXI_GMAC1_BASE 0x040
31		−#define CCU_AXI_XGMAC_BASE 0x044
32		−#define CCU_AXI_PCIE_M_BASE 0x048
33		−#define CCU_AXI_PCIE_S_BASE 0x04C
34		−#define CCU_AXI_USB_BASE 0x050
35		−#define CCU_AXI_HWA_BASE 0x054
36		−#define CCU_AXI_SRAM_BASE 0x058
37		−
38		−#define CCU_SYS_DDR_BASE 0x02c
39		−#define CCU_SYS_SATA_REF_BASE 0x060
40		−#define CCU_SYS_APB_BASE 0x064
41		−#define CCU_SYS_PCIE_BASE 0x144
42		−
43		−#define CCU_RST_DELAY_US 1
44		−
45		−#define CCU_RST_TRIG(_base, _ofs) \
46		− { \
47		− .type = CCU_RST_TRIG, \
48		− .base = _base, \
49		− .mask = BIT(_ofs), \
50		− }
51		−
52		−#define CCU_RST_DIR(_base, _ofs) \
53		− { \
54		− .type = CCU_RST_DIR, \
55		− .base = _base, \
56		− .mask = BIT(_ofs), \
57		− }
58		−
59		−struct ccu_rst_info {
60		− enum ccu_rst_type type;
61		− unsigned int base;
62		− unsigned int mask;
63		−};
64		−
65		−/*
66		− * Each AXI-bus clock divider is equipped with the corresponding clock-consumer
67		− * domain reset (it's self-deasserted reset control).
68		− */
69		−static const struct ccu_rst_info axi_rst_info[] = {
70		− [CCU_AXI_MAIN_RST] = CCU_RST_TRIG(CCU_AXI_MAIN_BASE, 1),
71		− [CCU_AXI_DDR_RST] = CCU_RST_TRIG(CCU_AXI_DDR_BASE, 1),
72		− [CCU_AXI_SATA_RST] = CCU_RST_TRIG(CCU_AXI_SATA_BASE, 1),
73		− [CCU_AXI_GMAC0_RST] = CCU_RST_TRIG(CCU_AXI_GMAC0_BASE, 1),
74		− [CCU_AXI_GMAC1_RST] = CCU_RST_TRIG(CCU_AXI_GMAC1_BASE, 1),
75		− [CCU_AXI_XGMAC_RST] = CCU_RST_TRIG(CCU_AXI_XGMAC_BASE, 1),
76		− [CCU_AXI_PCIE_M_RST] = CCU_RST_TRIG(CCU_AXI_PCIE_M_BASE, 1),
77		− [CCU_AXI_PCIE_S_RST] = CCU_RST_TRIG(CCU_AXI_PCIE_S_BASE, 1),
78		− [CCU_AXI_USB_RST] = CCU_RST_TRIG(CCU_AXI_USB_BASE, 1),
79		− [CCU_AXI_HWA_RST] = CCU_RST_TRIG(CCU_AXI_HWA_BASE, 1),
80		− [CCU_AXI_SRAM_RST] = CCU_RST_TRIG(CCU_AXI_SRAM_BASE, 1),
81		−};
82		−
83		−/*
84		− * SATA reference clock domain and APB-bus domain are connected with the
85		− * sefl-deasserted reset control, which can be activated via the corresponding
86		− * clock divider register. DDR and PCIe sub-domains can be reset with directly
87		− * controlled reset signals. Resetting the DDR controller though won't end up
88		− * well while the Linux kernel is working.
89		− */
90		−static const struct ccu_rst_info sys_rst_info[] = {
91		− [CCU_SYS_SATA_REF_RST] = CCU_RST_TRIG(CCU_SYS_SATA_REF_BASE, 1),
92		− [CCU_SYS_APB_RST] = CCU_RST_TRIG(CCU_SYS_APB_BASE, 1),
93		− [CCU_SYS_DDR_FULL_RST] = CCU_RST_DIR(CCU_SYS_DDR_BASE, 1),
94		− [CCU_SYS_DDR_INIT_RST] = CCU_RST_DIR(CCU_SYS_DDR_BASE, 2),
95		− [CCU_SYS_PCIE_PCS_PHY_RST] = CCU_RST_DIR(CCU_SYS_PCIE_BASE, 0),
96		− [CCU_SYS_PCIE_PIPE0_RST] = CCU_RST_DIR(CCU_SYS_PCIE_BASE, 4),
97		− [CCU_SYS_PCIE_CORE_RST] = CCU_RST_DIR(CCU_SYS_PCIE_BASE, 8),
98		− [CCU_SYS_PCIE_PWR_RST] = CCU_RST_DIR(CCU_SYS_PCIE_BASE, 9),
99		− [CCU_SYS_PCIE_STICKY_RST] = CCU_RST_DIR(CCU_SYS_PCIE_BASE, 10),
100		− [CCU_SYS_PCIE_NSTICKY_RST] = CCU_RST_DIR(CCU_SYS_PCIE_BASE, 11),
101		− [CCU_SYS_PCIE_HOT_RST] = CCU_RST_DIR(CCU_SYS_PCIE_BASE, 12),
102		−};
103		−
104		−static int ccu_rst_reset(struct reset_controller_dev *rcdev, unsigned long idx)
105		−{
106		− struct ccu_rst *rst = to_ccu_rst(rcdev);
107		− const struct ccu_rst_info *info = &rst->rsts_info[idx];
108		−
109		− if (info->type != CCU_RST_TRIG)
110		− return -EOPNOTSUPP;
111		−
112		− regmap_update_bits(rst->sys_regs, info->base, info->mask, info->mask);
113		−
114		− /* The next delay must be enough to cover all the resets. */
115		− udelay(CCU_RST_DELAY_US);
116		−
117		− return 0;
118		−}
119		−
120		−static int ccu_rst_set(struct reset_controller_dev *rcdev,
121		− unsigned long idx, bool high)
122		−{
123		− struct ccu_rst *rst = to_ccu_rst(rcdev);
124		− const struct ccu_rst_info *info = &rst->rsts_info[idx];
125		−
126		− if (info->type != CCU_RST_DIR)
127		− return high ? -EOPNOTSUPP : 0;
128		−
129		− return regmap_update_bits(rst->sys_regs, info->base,
130		− info->mask, high ? info->mask : 0);
131		−}
132		−
133		−static int ccu_rst_assert(struct reset_controller_dev *rcdev,
134		− unsigned long idx)
135		−{
136		− return ccu_rst_set(rcdev, idx, true);
137		−}
138		−
139		−static int ccu_rst_deassert(struct reset_controller_dev *rcdev,
140		− unsigned long idx)
141		−{
142		− return ccu_rst_set(rcdev, idx, false);
143		−}
144		−
145		−static int ccu_rst_status(struct reset_controller_dev *rcdev,
146		− unsigned long idx)
147		−{
148		− struct ccu_rst *rst = to_ccu_rst(rcdev);
149		− const struct ccu_rst_info *info = &rst->rsts_info[idx];
150		− u32 val;
151		−
152		− if (info->type != CCU_RST_DIR)
153		− return -EOPNOTSUPP;
154		−
155		− regmap_read(rst->sys_regs, info->base, &val);
156		−
157		− return !!(val & info->mask);
158		−}
159		−
160		−static const struct reset_control_ops ccu_rst_ops = {
161		− .reset = ccu_rst_reset,
162		− .assert = ccu_rst_assert,
163		− .deassert = ccu_rst_deassert,
164		− .status = ccu_rst_status,
165		−};
166		−
167		−struct ccu_rst ccu_rst_hw_register(const struct ccu_rst_init_data rst_init)
168		−{
169		− struct ccu_rst *rst;
170		− int ret;
171		−
172		− if (!rst_init)
173		− return ERR_PTR(-EINVAL);
174		−
175		− rst = kzalloc_obj(*rst);
176		− if (!rst)
177		− return ERR_PTR(-ENOMEM);
178		−
179		− rst->sys_regs = rst_init->sys_regs;
180		− if (of_device_is_compatible(rst_init->np, "baikal,bt1-ccu-axi")) {
181		− rst->rcdev.nr_resets = ARRAY_SIZE(axi_rst_info);
182		− rst->rsts_info = axi_rst_info;
183		− } else if (of_device_is_compatible(rst_init->np, "baikal,bt1-ccu-sys")) {
184		− rst->rcdev.nr_resets = ARRAY_SIZE(sys_rst_info);
185		− rst->rsts_info = sys_rst_info;
186		− } else {
187		− pr_err("Incompatible DT node '%s' specified\n",
188		− of_node_full_name(rst_init->np));
189		− ret = -EINVAL;
190		− goto err_kfree_rst;
191		− }
192		−
193		− rst->rcdev.owner = THIS_MODULE;
194		− rst->rcdev.ops = &ccu_rst_ops;
195		− rst->rcdev.of_node = rst_init->np;
196		−
197		− ret = reset_controller_register(&rst->rcdev);
198		− if (ret) {
199		− pr_err("Couldn't register '%s' reset controller\n",
200		− of_node_full_name(rst_init->np));
201		− goto err_kfree_rst;
202		− }
203		−
204		− return rst;
205		−
206		−err_kfree_rst:
207		− kfree(rst);
208		−
209		− return ERR_PTR(ret);
210		−}
211		−
212		−void ccu_rst_hw_unregister(struct ccu_rst *rst)
213		−{
214		− reset_controller_unregister(&rst->rcdev);
215		−
216		− kfree(rst);
217		−}

drivers/clk/baikal-t1/ccu-rst.h+0−67

@@ -1,67 +0,0 @@
1		−/* SPDX-License-Identifier: GPL-2.0-only */
2		−/*
3		− * Copyright (C) 2021 BAIKAL ELECTRONICS, JSC
4		− *
5		− * Baikal-T1 CCU Resets interface driver
6		− */
7		−#ifndef __CLK_BT1_CCU_RST_H__
8		−#define __CLK_BT1_CCU_RST_H__
9		−
10		−#include <linux/of.h>
11		−#include <linux/regmap.h>
12		−#include <linux/reset-controller.h>
13		−
14		−struct ccu_rst_info;
15		−
16		−/*
17		− * enum ccu_rst_type - CCU Reset types
18		− * @CCU_RST_TRIG: Self-deasserted reset signal.
19		− * @CCU_RST_DIR: Directly controlled reset signal.
20		− */
21		−enum ccu_rst_type {
22		− CCU_RST_TRIG,
23		− CCU_RST_DIR,
24		−};
25		−
26		−/*
27		− * struct ccu_rst_init_data - CCU Resets initialization data
28		− * @sys_regs: Baikal-T1 System Controller registers map.
29		− * @np: Pointer to the node with the System CCU block.
30		− */
31		−struct ccu_rst_init_data {
32		− struct regmap *sys_regs;
33		− struct device_node *np;
34		−};
35		−
36		−/*
37		− * struct ccu_rst - CCU Reset descriptor
38		− * @rcdev: Reset controller descriptor.
39		− * @sys_regs: Baikal-T1 System Controller registers map.
40		− * @rsts_info: Reset flag info (base address and mask).
41		− */
42		−struct ccu_rst {
43		− struct reset_controller_dev rcdev;
44		− struct regmap *sys_regs;
45		− const struct ccu_rst_info *rsts_info;
46		−};
47		−#define to_ccu_rst(_rcdev) container_of(_rcdev, struct ccu_rst, rcdev)
48		−
49		−#ifdef CONFIG_CLK_BT1_CCU_RST
50		−
51		−struct ccu_rst ccu_rst_hw_register(const struct ccu_rst_init_data init);
52		−
53		−void ccu_rst_hw_unregister(struct ccu_rst *rst);
54		−
55		−#else
56		−
57		−static inline
58		−struct ccu_rst ccu_rst_hw_register(const struct ccu_rst_init_data init)
59		−{
60		− return NULL;
61		−}
62		−
63		−static inline void ccu_rst_hw_unregister(struct ccu_rst *rst) {}
64		−
65		−#endif
66		−
67		−#endif /* __CLK_BT1_CCU_RST_H__ */

drivers/clk/baikal-t1/clk-ccu-div.c+0−520

@@ -1,520 +0,0 @@
1		−// SPDX-License-Identifier: GPL-2.0-only
2		−/*
3		− * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
4		− *
5		− * Authors:
6		− * Serge Semin <Sergey.Semin@baikalelectronics.ru>
7		− * Dmitry Dunaev <dmitry.dunaev@baikalelectronics.ru>
8		− *
9		− * Baikal-T1 CCU Dividers clock driver
10		− */
11		−
12		−#define pr_fmt(fmt) "bt1-ccu-div: " fmt
13		−
14		−#include <linux/kernel.h>
15		−#include <linux/platform_device.h>
16		−#include <linux/printk.h>
17		−#include <linux/slab.h>
18		−#include <linux/clk-provider.h>
19		−#include <linux/reset-controller.h>
20		−#include <linux/mfd/syscon.h>
21		−#include <linux/of.h>
22		−#include <linux/of_address.h>
23		−#include <linux/ioport.h>
24		−#include <linux/regmap.h>
25		−
26		−#include <dt-bindings/clock/bt1-ccu.h>
27		−
28		−#include "ccu-div.h"
29		−#include "ccu-rst.h"
30		−
31		−#define CCU_AXI_MAIN_BASE 0x030
32		−#define CCU_AXI_DDR_BASE 0x034
33		−#define CCU_AXI_SATA_BASE 0x038
34		−#define CCU_AXI_GMAC0_BASE 0x03C
35		−#define CCU_AXI_GMAC1_BASE 0x040
36		−#define CCU_AXI_XGMAC_BASE 0x044
37		−#define CCU_AXI_PCIE_M_BASE 0x048
38		−#define CCU_AXI_PCIE_S_BASE 0x04C
39		−#define CCU_AXI_USB_BASE 0x050
40		−#define CCU_AXI_HWA_BASE 0x054
41		−#define CCU_AXI_SRAM_BASE 0x058
42		−
43		−#define CCU_SYS_SATA_REF_BASE 0x060
44		−#define CCU_SYS_APB_BASE 0x064
45		−#define CCU_SYS_GMAC0_BASE 0x068
46		−#define CCU_SYS_GMAC1_BASE 0x06C
47		−#define CCU_SYS_XGMAC_BASE 0x070
48		−#define CCU_SYS_USB_BASE 0x074
49		−#define CCU_SYS_PVT_BASE 0x078
50		−#define CCU_SYS_HWA_BASE 0x07C
51		−#define CCU_SYS_UART_BASE 0x084
52		−#define CCU_SYS_TIMER0_BASE 0x088
53		−#define CCU_SYS_TIMER1_BASE 0x08C
54		−#define CCU_SYS_TIMER2_BASE 0x090
55		−#define CCU_SYS_WDT_BASE 0x150
56		−
57		−#define CCU_DIV_VAR_INFO(_id, _name, _pname, _base, _width, _flags, _features) \
58		− { \
59		− .id = _id, \
60		− .name = _name, \
61		− .parent_name = _pname, \
62		− .base = _base, \
63		− .type = CCU_DIV_VAR, \
64		− .width = _width, \
65		− .flags = _flags, \
66		− .features = _features \
67		− }
68		−
69		−#define CCU_DIV_GATE_INFO(_id, _name, _pname, _base, _divider) \
70		− { \
71		− .id = _id, \
72		− .name = _name, \
73		− .parent_name = _pname, \
74		− .base = _base, \
75		− .type = CCU_DIV_GATE, \
76		− .divider = _divider \
77		− }
78		−
79		−#define CCU_DIV_BUF_INFO(_id, _name, _pname, _base, _flags) \
80		− { \
81		− .id = _id, \
82		− .name = _name, \
83		− .parent_name = _pname, \
84		− .base = _base, \
85		− .type = CCU_DIV_BUF, \
86		− .flags = _flags \
87		− }
88		−
89		−#define CCU_DIV_FIXED_INFO(_id, _name, _pname, _divider) \
90		− { \
91		− .id = _id, \
92		− .name = _name, \
93		− .parent_name = _pname, \
94		− .type = CCU_DIV_FIXED, \
95		− .divider = _divider \
96		− }
97		−
98		−struct ccu_div_info {
99		− unsigned int id;
100		− const char *name;
101		− const char *parent_name;
102		− unsigned int base;
103		− enum ccu_div_type type;
104		− union {
105		− unsigned int width;
106		− unsigned int divider;
107		− };
108		− unsigned long flags;
109		− unsigned long features;
110		−};
111		−
112		−struct ccu_div_data {
113		− struct device_node *np;
114		− struct regmap *sys_regs;
115		−
116		− unsigned int divs_num;
117		− const struct ccu_div_info *divs_info;
118		− struct ccu_div **divs;
119		−
120		− struct ccu_rst *rsts;
121		−};
122		−
123		−/*
124		− * AXI Main Interconnect (axi_main_clk) and DDR AXI-bus (axi_ddr_clk) clocks
125		− * must be left enabled in any case, since former one is responsible for
126		− * clocking a bus between CPU cores and the rest of the SoC components, while
127		− * the later is clocking the AXI-bus between DDR controller and the Main
128		− * Interconnect. So should any of these clocks get to be disabled, the system
129		− * will literally stop working. That's why we marked them as critical.
130		− */
131		−static const struct ccu_div_info axi_info[] = {
132		− CCU_DIV_VAR_INFO(CCU_AXI_MAIN_CLK, "axi_main_clk", "pcie_clk",
133		− CCU_AXI_MAIN_BASE, 4,
134		− CLK_IS_CRITICAL, CCU_DIV_RESET_DOMAIN),
135		− CCU_DIV_VAR_INFO(CCU_AXI_DDR_CLK, "axi_ddr_clk", "sata_clk",
136		− CCU_AXI_DDR_BASE, 4,
137		− CLK_IS_CRITICAL \| CLK_SET_RATE_GATE,
138		− CCU_DIV_RESET_DOMAIN),
139		− CCU_DIV_VAR_INFO(CCU_AXI_SATA_CLK, "axi_sata_clk", "sata_clk",
140		− CCU_AXI_SATA_BASE, 4,
141		− CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
142		− CCU_DIV_VAR_INFO(CCU_AXI_GMAC0_CLK, "axi_gmac0_clk", "eth_clk",
143		− CCU_AXI_GMAC0_BASE, 4,
144		− CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
145		− CCU_DIV_VAR_INFO(CCU_AXI_GMAC1_CLK, "axi_gmac1_clk", "eth_clk",
146		− CCU_AXI_GMAC1_BASE, 4,
147		− CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
148		− CCU_DIV_VAR_INFO(CCU_AXI_XGMAC_CLK, "axi_xgmac_clk", "eth_clk",
149		− CCU_AXI_XGMAC_BASE, 4,
150		− CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
151		− CCU_DIV_VAR_INFO(CCU_AXI_PCIE_M_CLK, "axi_pcie_m_clk", "pcie_clk",
152		− CCU_AXI_PCIE_M_BASE, 4,
153		− CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
154		− CCU_DIV_VAR_INFO(CCU_AXI_PCIE_S_CLK, "axi_pcie_s_clk", "pcie_clk",
155		− CCU_AXI_PCIE_S_BASE, 4,
156		− CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
157		− CCU_DIV_VAR_INFO(CCU_AXI_USB_CLK, "axi_usb_clk", "sata_clk",
158		− CCU_AXI_USB_BASE, 4,
159		− CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
160		− CCU_DIV_VAR_INFO(CCU_AXI_HWA_CLK, "axi_hwa_clk", "sata_clk",
161		− CCU_AXI_HWA_BASE, 4,
162		− CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
163		− CCU_DIV_VAR_INFO(CCU_AXI_SRAM_CLK, "axi_sram_clk", "eth_clk",
164		− CCU_AXI_SRAM_BASE, 4,
165		− CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN)
166		−};
167		−
168		−/*
169		− * APB-bus clock is marked as critical since it's a main communication bus
170		− * for the SoC devices registers IO-operations.
171		− */
172		−static const struct ccu_div_info sys_info[] = {
173		− CCU_DIV_VAR_INFO(CCU_SYS_SATA_CLK, "sys_sata_clk",
174		− "sata_clk", CCU_SYS_SATA_REF_BASE, 4,
175		− CLK_SET_RATE_GATE,
176		− CCU_DIV_SKIP_ONE \| CCU_DIV_LOCK_SHIFTED \|
177		− CCU_DIV_RESET_DOMAIN),
178		− CCU_DIV_BUF_INFO(CCU_SYS_SATA_REF_CLK, "sys_sata_ref_clk",
179		− "sys_sata_clk", CCU_SYS_SATA_REF_BASE,
180		− CLK_SET_RATE_PARENT),
181		− CCU_DIV_VAR_INFO(CCU_SYS_APB_CLK, "sys_apb_clk",
182		− "pcie_clk", CCU_SYS_APB_BASE, 5,
183		− CLK_IS_CRITICAL, CCU_DIV_BASIC \| CCU_DIV_RESET_DOMAIN),
184		− CCU_DIV_GATE_INFO(CCU_SYS_GMAC0_TX_CLK, "sys_gmac0_tx_clk",
185		− "eth_clk", CCU_SYS_GMAC0_BASE, 5),
186		− CCU_DIV_FIXED_INFO(CCU_SYS_GMAC0_PTP_CLK, "sys_gmac0_ptp_clk",
187		− "eth_clk", 10),
188		− CCU_DIV_GATE_INFO(CCU_SYS_GMAC1_TX_CLK, "sys_gmac1_tx_clk",
189		− "eth_clk", CCU_SYS_GMAC1_BASE, 5),
190		− CCU_DIV_FIXED_INFO(CCU_SYS_GMAC1_PTP_CLK, "sys_gmac1_ptp_clk",
191		− "eth_clk", 10),
192		− CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_CLK, "sys_xgmac_clk",
193		− "eth_clk", CCU_SYS_XGMAC_BASE, 1),
194		− CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",
195		− "sys_xgmac_clk", 8),
196		− CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_PTP_CLK, "sys_xgmac_ptp_clk",
197		− "sys_xgmac_clk", 8),
198		− CCU_DIV_GATE_INFO(CCU_SYS_USB_CLK, "sys_usb_clk",
199		− "eth_clk", CCU_SYS_USB_BASE, 10),
200		− CCU_DIV_VAR_INFO(CCU_SYS_PVT_CLK, "sys_pvt_clk",
201		− "ref_clk", CCU_SYS_PVT_BASE, 5,
202		− CLK_SET_RATE_GATE, 0),
203		− CCU_DIV_VAR_INFO(CCU_SYS_HWA_CLK, "sys_hwa_clk",
204		− "sata_clk", CCU_SYS_HWA_BASE, 4,
205		− CLK_SET_RATE_GATE, 0),
206		− CCU_DIV_VAR_INFO(CCU_SYS_UART_CLK, "sys_uart_clk",
207		− "eth_clk", CCU_SYS_UART_BASE, 17,
208		− CLK_SET_RATE_GATE, 0),
209		− CCU_DIV_FIXED_INFO(CCU_SYS_I2C1_CLK, "sys_i2c1_clk",
210		− "eth_clk", 10),
211		− CCU_DIV_FIXED_INFO(CCU_SYS_I2C2_CLK, "sys_i2c2_clk",
212		− "eth_clk", 10),
213		− CCU_DIV_FIXED_INFO(CCU_SYS_GPIO_CLK, "sys_gpio_clk",
214		− "ref_clk", 25),
215		− CCU_DIV_VAR_INFO(CCU_SYS_TIMER0_CLK, "sys_timer0_clk",
216		− "ref_clk", CCU_SYS_TIMER0_BASE, 17,
217		− CLK_SET_RATE_GATE, CCU_DIV_BASIC),
218		− CCU_DIV_VAR_INFO(CCU_SYS_TIMER1_CLK, "sys_timer1_clk",
219		− "ref_clk", CCU_SYS_TIMER1_BASE, 17,
220		− CLK_SET_RATE_GATE, CCU_DIV_BASIC),
221		− CCU_DIV_VAR_INFO(CCU_SYS_TIMER2_CLK, "sys_timer2_clk",
222		− "ref_clk", CCU_SYS_TIMER2_BASE, 17,
223		− CLK_SET_RATE_GATE, CCU_DIV_BASIC),
224		− CCU_DIV_VAR_INFO(CCU_SYS_WDT_CLK, "sys_wdt_clk",
225		− "eth_clk", CCU_SYS_WDT_BASE, 17,
226		− CLK_SET_RATE_GATE, CCU_DIV_SKIP_ONE_TO_THREE)
227		−};
228		−
229		−static struct ccu_div_data *axi_data;
230		−static struct ccu_div_data *sys_data;
231		−
232		−static void ccu_div_set_data(struct ccu_div_data *data)
233		−{
234		− struct device_node *np = data->np;
235		−
236		− if (of_device_is_compatible(np, "baikal,bt1-ccu-axi"))
237		− axi_data = data;
238		− else if (of_device_is_compatible(np, "baikal,bt1-ccu-sys"))
239		− sys_data = data;
240		− else
241		− pr_err("Invalid DT node '%s' specified\n", of_node_full_name(np));
242		−}
243		−
244		−static struct ccu_div_data ccu_div_get_data(struct device_node np)
245		−{
246		− if (of_device_is_compatible(np, "baikal,bt1-ccu-axi"))
247		− return axi_data;
248		− else if (of_device_is_compatible(np, "baikal,bt1-ccu-sys"))
249		− return sys_data;
250		−
251		− pr_err("Invalid DT node '%s' specified\n", of_node_full_name(np));
252		−
253		− return NULL;
254		−}
255		−
256		−static struct ccu_div ccu_div_find_desc(struct ccu_div_data data,
257		− unsigned int clk_id)
258		−{
259		− int idx;
260		−
261		− for (idx = 0; idx < data->divs_num; ++idx) {
262		− if (data->divs_info[idx].id == clk_id)
263		− return data->divs[idx];
264		− }
265		−
266		− return ERR_PTR(-EINVAL);
267		−}
268		−
269		−static struct ccu_div_data ccu_div_create_data(struct device_node np)
270		−{
271		− struct ccu_div_data *data;
272		− int ret;
273		−
274		− data = kzalloc_obj(*data);
275		− if (!data)
276		− return ERR_PTR(-ENOMEM);
277		−
278		− data->np = np;
279		− if (of_device_is_compatible(np, "baikal,bt1-ccu-axi")) {
280		− data->divs_num = ARRAY_SIZE(axi_info);
281		− data->divs_info = axi_info;
282		− } else if (of_device_is_compatible(np, "baikal,bt1-ccu-sys")) {
283		− data->divs_num = ARRAY_SIZE(sys_info);
284		− data->divs_info = sys_info;
285		− } else {
286		− pr_err("Incompatible DT node '%s' specified\n",
287		− of_node_full_name(np));
288		− ret = -EINVAL;
289		− goto err_kfree_data;
290		− }
291		−
292		− data->divs = kzalloc_objs(*data->divs, data->divs_num);
293		− if (!data->divs) {
294		− ret = -ENOMEM;
295		− goto err_kfree_data;
296		− }
297		−
298		− return data;
299		−
300		−err_kfree_data:
301		− kfree(data);
302		−
303		− return ERR_PTR(ret);
304		−}
305		−
306		−static void ccu_div_free_data(struct ccu_div_data *data)
307		−{
308		− kfree(data->divs);
309		−
310		− kfree(data);
311		−}
312		−
313		−static int ccu_div_find_sys_regs(struct ccu_div_data *data)
314		−{
315		− data->sys_regs = syscon_node_to_regmap(data->np->parent);
316		− if (IS_ERR(data->sys_regs)) {
317		− pr_err("Failed to find syscon regs for '%s'\n",
318		− of_node_full_name(data->np));
319		− return PTR_ERR(data->sys_regs);
320		− }
321		−
322		− return 0;
323		−}
324		−
325		−static struct clk_hw ccu_div_of_clk_hw_get(struct of_phandle_args clkspec,
326		− void *priv)
327		−{
328		− struct ccu_div_data *data = priv;
329		− struct ccu_div *div;
330		− unsigned int clk_id;
331		−
332		− clk_id = clkspec->args[0];
333		− div = ccu_div_find_desc(data, clk_id);
334		− if (IS_ERR(div)) {
335		− if (div != ERR_PTR(-EPROBE_DEFER))
336		− pr_info("Invalid clock ID %d specified\n", clk_id);
337		−
338		− return ERR_CAST(div);
339		− }
340		−
341		− return ccu_div_get_clk_hw(div);
342		−}
343		−
344		−static int ccu_div_clk_register(struct ccu_div_data *data, bool defer)
345		−{
346		− int idx, ret;
347		−
348		− for (idx = 0; idx < data->divs_num; ++idx) {
349		− const struct ccu_div_info *info = &data->divs_info[idx];
350		− struct ccu_div_init_data init = {0};
351		−
352		− if (!!(info->features & CCU_DIV_BASIC) ^ defer) {
353		− if (!data->divs[idx])
354		− data->divs[idx] = ERR_PTR(-EPROBE_DEFER);
355		−
356		− continue;
357		− }
358		−
359		− init.id = info->id;
360		− init.name = info->name;
361		− init.parent_name = info->parent_name;
362		− init.np = data->np;
363		− init.type = info->type;
364		− init.flags = info->flags;
365		− init.features = info->features;
366		−
367		− if (init.type == CCU_DIV_VAR) {
368		− init.base = info->base;
369		− init.sys_regs = data->sys_regs;
370		− init.width = info->width;
371		− } else if (init.type == CCU_DIV_GATE) {
372		− init.base = info->base;
373		− init.sys_regs = data->sys_regs;
374		− init.divider = info->divider;
375		− } else if (init.type == CCU_DIV_BUF) {
376		− init.base = info->base;
377		− init.sys_regs = data->sys_regs;
378		− } else {
379		− init.divider = info->divider;
380		− }
381		−
382		− data->divs[idx] = ccu_div_hw_register(&init);
383		− if (IS_ERR(data->divs[idx])) {
384		− ret = PTR_ERR(data->divs[idx]);
385		− pr_err("Couldn't register divider '%s' hw\n",
386		− init.name);
387		− goto err_hw_unregister;
388		− }
389		− }
390		−
391		− return 0;
392		−
393		−err_hw_unregister:
394		− for (--idx; idx >= 0; --idx) {
395		− if (!!(data->divs_info[idx].features & CCU_DIV_BASIC) ^ defer)
396		− continue;
397		−
398		− ccu_div_hw_unregister(data->divs[idx]);
399		− }
400		−
401		− return ret;
402		−}
403		−
404		−static void ccu_div_clk_unregister(struct ccu_div_data *data, bool defer)
405		−{
406		− int idx;
407		−
408		− /* Uninstall only the clocks registered on the specified stage */
409		− for (idx = 0; idx < data->divs_num; ++idx) {
410		− if (!!(data->divs_info[idx].features & CCU_DIV_BASIC) ^ defer)
411		− continue;
412		−
413		− ccu_div_hw_unregister(data->divs[idx]);
414		− }
415		−}
416		−
417		−static int ccu_div_of_register(struct ccu_div_data *data)
418		−{
419		− int ret;
420		−
421		− ret = of_clk_add_hw_provider(data->np, ccu_div_of_clk_hw_get, data);
422		− if (ret) {
423		− pr_err("Couldn't register dividers '%s' clock provider\n",
424		− of_node_full_name(data->np));
425		− }
426		−
427		− return ret;
428		−}
429		−
430		−static int ccu_div_rst_register(struct ccu_div_data *data)
431		−{
432		− struct ccu_rst_init_data init = {0};
433		−
434		− init.sys_regs = data->sys_regs;
435		− init.np = data->np;
436		−
437		− data->rsts = ccu_rst_hw_register(&init);
438		− if (IS_ERR(data->rsts)) {
439		− pr_err("Couldn't register divider '%s' reset controller\n",
440		− of_node_full_name(data->np));
441		− return PTR_ERR(data->rsts);
442		− }
443		−
444		− return 0;
445		−}
446		−
447		−static int ccu_div_probe(struct platform_device *pdev)
448		−{
449		− struct ccu_div_data *data;
450		− int ret;
451		−
452		− data = ccu_div_get_data(dev_of_node(&pdev->dev));
453		− if (!data)
454		− return -EINVAL;
455		−
456		− ret = ccu_div_clk_register(data, false);
457		− if (ret)
458		− return ret;
459		−
460		− ret = ccu_div_rst_register(data);
461		− if (ret)
462		− goto err_clk_unregister;
463		−
464		− return 0;
465		−
466		−err_clk_unregister:
467		− ccu_div_clk_unregister(data, false);
468		−
469		− return ret;
470		−}
471		−
472		−static const struct of_device_id ccu_div_of_match[] = {
473		− { .compatible = "baikal,bt1-ccu-axi" },
474		− { .compatible = "baikal,bt1-ccu-sys" },
475		− { }
476		−};
477		−
478		−static struct platform_driver ccu_div_driver = {
479		− .probe = ccu_div_probe,
480		− .driver = {
481		− .name = "clk-ccu-div",
482		− .of_match_table = ccu_div_of_match,
483		− .suppress_bind_attrs = true,
484		− },
485		−};
486		−builtin_platform_driver(ccu_div_driver);
487		−
488		−static __init void ccu_div_init(struct device_node *np)
489		−{
490		− struct ccu_div_data *data;
491		− int ret;
492		−
493		− data = ccu_div_create_data(np);
494		− if (IS_ERR(data))
495		− return;
496		−
497		− ret = ccu_div_find_sys_regs(data);
498		− if (ret)
499		− goto err_free_data;
500		−
501		− ret = ccu_div_clk_register(data, true);
502		− if (ret)
503		− goto err_free_data;
504		−
505		− ret = ccu_div_of_register(data);
506		− if (ret)
507		− goto err_clk_unregister;
508		−
509		− ccu_div_set_data(data);
510		−
511		− return;
512		−
513		−err_clk_unregister:
514		− ccu_div_clk_unregister(data, true);
515		−
516		−err_free_data:
517		− ccu_div_free_data(data);
518		−}
519		−CLK_OF_DECLARE_DRIVER(ccu_axi, "baikal,bt1-ccu-axi", ccu_div_init);
520		−CLK_OF_DECLARE_DRIVER(ccu_sys, "baikal,bt1-ccu-sys", ccu_div_init);

drivers/clk/baikal-t1/clk-ccu-pll.c+0−277

@@ -1,277 +0,0 @@
1		−// SPDX-License-Identifier: GPL-2.0-only
2		−/*
3		− * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
4		− *
5		− * Authors:
6		− * Serge Semin <Sergey.Semin@baikalelectronics.ru>
7		− * Dmitry Dunaev <dmitry.dunaev@baikalelectronics.ru>
8		− *
9		− * Baikal-T1 CCU PLL clocks driver
10		− */
11		−
12		−#define pr_fmt(fmt) "bt1-ccu-pll: " fmt
13		−
14		−#include <linux/kernel.h>
15		−#include <linux/platform_device.h>
16		−#include <linux/printk.h>
17		−#include <linux/slab.h>
18		−#include <linux/clk-provider.h>
19		−#include <linux/mfd/syscon.h>
20		−#include <linux/of.h>
21		−#include <linux/of_address.h>
22		−#include <linux/ioport.h>
23		−#include <linux/regmap.h>
24		−
25		−#include <dt-bindings/clock/bt1-ccu.h>
26		−
27		−#include "ccu-pll.h"
28		−
29		−#define CCU_CPU_PLL_BASE 0x000
30		−#define CCU_SATA_PLL_BASE 0x008
31		−#define CCU_DDR_PLL_BASE 0x010
32		−#define CCU_PCIE_PLL_BASE 0x018
33		−#define CCU_ETH_PLL_BASE 0x020
34		−
35		−#define CCU_PLL_INFO(_id, _name, _pname, _base, _flags, _features) \
36		− { \
37		− .id = _id, \
38		− .name = _name, \
39		− .parent_name = _pname, \
40		− .base = _base, \
41		− .flags = _flags, \
42		− .features = _features, \
43		− }
44		−
45		−#define CCU_PLL_NUM ARRAY_SIZE(pll_info)
46		−
47		−struct ccu_pll_info {
48		− unsigned int id;
49		− const char *name;
50		− const char *parent_name;
51		− unsigned int base;
52		− unsigned long flags;
53		− unsigned long features;
54		−};
55		−
56		−/*
57		− * Alas we have to mark all PLLs as critical. CPU and DDR PLLs are sources of
58		− * CPU cores and DDR controller reference clocks, due to which they obviously
59		− * shouldn't be ever gated. SATA and PCIe PLLs are the parents of APB-bus and
60		− * DDR controller AXI-bus clocks. If they are gated the system will be
61		− * unusable. Moreover disabling SATA and Ethernet PLLs causes automatic reset
62		− * of the corresponding subsystems. So until we aren't ready to re-initialize
63		− * all the devices consuming those PLLs, they will be marked as critical too.
64		− */
65		−static const struct ccu_pll_info pll_info[] = {
66		− CCU_PLL_INFO(CCU_CPU_PLL, "cpu_pll", "ref_clk", CCU_CPU_PLL_BASE,
67		− CLK_IS_CRITICAL, CCU_PLL_BASIC),
68		− CCU_PLL_INFO(CCU_SATA_PLL, "sata_pll", "ref_clk", CCU_SATA_PLL_BASE,
69		− CLK_IS_CRITICAL \| CLK_SET_RATE_GATE, 0),
70		− CCU_PLL_INFO(CCU_DDR_PLL, "ddr_pll", "ref_clk", CCU_DDR_PLL_BASE,
71		− CLK_IS_CRITICAL \| CLK_SET_RATE_GATE, 0),
72		− CCU_PLL_INFO(CCU_PCIE_PLL, "pcie_pll", "ref_clk", CCU_PCIE_PLL_BASE,
73		− CLK_IS_CRITICAL, CCU_PLL_BASIC),
74		− CCU_PLL_INFO(CCU_ETH_PLL, "eth_pll", "ref_clk", CCU_ETH_PLL_BASE,
75		− CLK_IS_CRITICAL \| CLK_SET_RATE_GATE, 0)
76		−};
77		−
78		−struct ccu_pll_data {
79		− struct device_node *np;
80		− struct regmap *sys_regs;
81		− struct ccu_pll *plls[CCU_PLL_NUM];
82		−};
83		−
84		−static struct ccu_pll_data *pll_data;
85		−
86		−static struct ccu_pll ccu_pll_find_desc(struct ccu_pll_data data,
87		− unsigned int clk_id)
88		−{
89		− int idx;
90		−
91		− for (idx = 0; idx < CCU_PLL_NUM; ++idx) {
92		− if (pll_info[idx].id == clk_id)
93		− return data->plls[idx];
94		− }
95		−
96		− return ERR_PTR(-EINVAL);
97		−}
98		−
99		−static struct ccu_pll_data ccu_pll_create_data(struct device_node np)
100		−{
101		− struct ccu_pll_data *data;
102		−
103		− data = kzalloc_obj(*data);
104		− if (!data)
105		− return ERR_PTR(-ENOMEM);
106		−
107		− data->np = np;
108		−
109		− return data;
110		−}
111		−
112		−static void ccu_pll_free_data(struct ccu_pll_data *data)
113		−{
114		− kfree(data);
115		−}
116		−
117		−static int ccu_pll_find_sys_regs(struct ccu_pll_data *data)
118		−{
119		− data->sys_regs = syscon_node_to_regmap(data->np->parent);
120		− if (IS_ERR(data->sys_regs)) {
121		− pr_err("Failed to find syscon regs for '%s'\n",
122		− of_node_full_name(data->np));
123		− return PTR_ERR(data->sys_regs);
124		− }
125		−
126		− return 0;
127		−}
128		−
129		−static struct clk_hw ccu_pll_of_clk_hw_get(struct of_phandle_args clkspec,
130		− void *priv)
131		−{
132		− struct ccu_pll_data *data = priv;
133		− struct ccu_pll *pll;
134		− unsigned int clk_id;
135		−
136		− clk_id = clkspec->args[0];
137		− pll = ccu_pll_find_desc(data, clk_id);
138		− if (IS_ERR(pll)) {
139		− if (pll != ERR_PTR(-EPROBE_DEFER))
140		− pr_info("Invalid PLL clock ID %d specified\n", clk_id);
141		−
142		− return ERR_CAST(pll);
143		− }
144		−
145		− return ccu_pll_get_clk_hw(pll);
146		−}
147		−
148		−static int ccu_pll_clk_register(struct ccu_pll_data *data, bool defer)
149		−{
150		− int idx, ret;
151		−
152		− for (idx = 0; idx < CCU_PLL_NUM; ++idx) {
153		− const struct ccu_pll_info *info = &pll_info[idx];
154		− struct ccu_pll_init_data init = {0};
155		−
156		− /* Defer non-basic PLLs allocation for the probe stage */
157		− if (!!(info->features & CCU_PLL_BASIC) ^ defer) {
158		− if (!data->plls[idx])
159		− data->plls[idx] = ERR_PTR(-EPROBE_DEFER);
160		−
161		− continue;
162		− }
163		−
164		− init.id = info->id;
165		− init.name = info->name;
166		− init.parent_name = info->parent_name;
167		− init.base = info->base;
168		− init.sys_regs = data->sys_regs;
169		− init.np = data->np;
170		− init.flags = info->flags;
171		− init.features = info->features;
172		−
173		− data->plls[idx] = ccu_pll_hw_register(&init);
174		− if (IS_ERR(data->plls[idx])) {
175		− ret = PTR_ERR(data->plls[idx]);
176		− pr_err("Couldn't register PLL hw '%s'\n",
177		− init.name);
178		− goto err_hw_unregister;
179		− }
180		− }
181		−
182		− return 0;
183		−
184		−err_hw_unregister:
185		− for (--idx; idx >= 0; --idx) {
186		− if (!!(pll_info[idx].features & CCU_PLL_BASIC) ^ defer)
187		− continue;
188		−
189		− ccu_pll_hw_unregister(data->plls[idx]);
190		− }
191		−
192		− return ret;
193		−}
194		−
195		−static void ccu_pll_clk_unregister(struct ccu_pll_data *data, bool defer)
196		−{
197		− int idx;
198		−
199		− /* Uninstall only the clocks registered on the specified stage */
200		− for (idx = 0; idx < CCU_PLL_NUM; ++idx) {
201		− if (!!(pll_info[idx].features & CCU_PLL_BASIC) ^ defer)
202		− continue;
203		−
204		− ccu_pll_hw_unregister(data->plls[idx]);
205		− }
206		−}
207		−
208		−static int ccu_pll_of_register(struct ccu_pll_data *data)
209		−{
210		− int ret;
211		−
212		− ret = of_clk_add_hw_provider(data->np, ccu_pll_of_clk_hw_get, data);
213		− if (ret) {
214		− pr_err("Couldn't register PLL provider of '%s'\n",
215		− of_node_full_name(data->np));
216		− }
217		−
218		− return ret;
219		−}
220		−
221		−static int ccu_pll_probe(struct platform_device *pdev)
222		−{
223		− struct ccu_pll_data *data = pll_data;
224		−
225		− if (!data)
226		− return -EINVAL;
227		−
228		− return ccu_pll_clk_register(data, false);
229		−}
230		−
231		−static const struct of_device_id ccu_pll_of_match[] = {
232		− { .compatible = "baikal,bt1-ccu-pll" },
233		− { }
234		−};
235		−
236		−static struct platform_driver ccu_pll_driver = {
237		− .probe = ccu_pll_probe,
238		− .driver = {
239		− .name = "clk-ccu-pll",
240		− .of_match_table = ccu_pll_of_match,
241		− .suppress_bind_attrs = true,
242		− },
243		−};
244		−builtin_platform_driver(ccu_pll_driver);
245		−
246		−static __init void ccu_pll_init(struct device_node *np)
247		−{
248		− struct ccu_pll_data *data;
249		− int ret;
250		−
251		− data = ccu_pll_create_data(np);
252		− if (IS_ERR(data))
253		− return;
254		−
255		− ret = ccu_pll_find_sys_regs(data);
256		− if (ret)
257		− goto err_free_data;
258		−
259		− ret = ccu_pll_clk_register(data, true);
260		− if (ret)
261		− goto err_free_data;
262		−
263		− ret = ccu_pll_of_register(data);
264		− if (ret)
265		− goto err_clk_unregister;
266		−
267		− pll_data = data;
268		−
269		− return;
270		−
271		−err_clk_unregister:
272		− ccu_pll_clk_unregister(data, true);
273		−
274		−err_free_data:
275		− ccu_pll_free_data(data);
276		−}
277		−CLK_OF_DECLARE_DRIVER(ccu_pll, "baikal,bt1-ccu-pll", ccu_pll_init);

drivers/clk/bcm/clk-raspberrypi.c+34−4

@@ -289,16 +289,31 @@ static int raspberrypi_fw_dumb_determine_rate(struct clk_hw *hw, · 288 unmodified lines
289	289	static int raspberrypi_fw_prepare(struct clk_hw *hw)
290	290	{
291	291	const struct raspberrypi_clk_data *data = clk_hw_to_data(hw);
	292	+ struct raspberrypi_clk_variant *variant = data->variant;
292	293	struct raspberrypi_clk *rpi = data->rpi;
293	294	u32 state = RPI_FIRMWARE_STATE_ENABLE_BIT;
294	295	int ret;
295	296
296	297	ret = raspberrypi_clock_property(rpi->firmware, data,
297	298	RPI_FIRMWARE_SET_CLOCK_STATE, &state);
298		− if (ret)
	299	+ if (ret) {
299	300	dev_err_ratelimited(rpi->dev,
300	301	"Failed to set clock %s state to on: %d\n",
301	302	clk_hw_get_name(hw), ret);
	303	+ return ret;
	304	+ }
	305	+
	306	+ /*
	307	+ * For clocks marked with 'maximize', restore the rate to the
	308	+ * maximum after enabling. This compensates for the rate being
	309	+ * set to minimum during unprepare (see raspberrypi_fw_unprepare).
	310	+ */
	311	+ if (variant->maximize) {
	312	+ unsigned long min_rate, max_rate;
	313	+
	314	+ clk_hw_get_rate_range(hw, &min_rate, &max_rate);
	315	+ ret = raspberrypi_fw_set_rate(hw, max_rate, 0);
	316	+ }
302	317
303	318	return ret;
304	319	}
@@ -307,9 +322,27 @@ static void raspberrypi_fw_unprepare(struct clk_hw *hw) · 2 unmodified lines
307	322	{
308	323	const struct raspberrypi_clk_data *data = clk_hw_to_data(hw);
309	324	struct raspberrypi_clk *rpi = data->rpi;
	325	+ unsigned long min_rate, max_rate;
310	326	u32 state = 0;
311	327	int ret;
312	328
	329	+ clk_hw_get_rate_range(hw, &min_rate, &max_rate);
	330	+
	331	+ /*
	332	+ * Setting the rate in unprepare is a deviation from the usual CCF
	333	+ * behavior, where unprepare only gates the clock. However, this is
	334	+ * needed, as RPI_FIRMWARE_SET_CLOCK_STATE doesn't actually power off
	335	+ * the clock on current firmware versions. Setting the rate to minimum
	336	+ * before disabling the clock is the only way to achieve meaningful
	337	+ * power savings.
	338	+ *
	339	+ * This is safe because no consumer should rely on the rate of an
	340	+ * unprepared clock. Any consumer must call clk_prepare() before use,
	341	+ * at which point the rate is either restored to maximum (for clocks
	342	+ * with the 'maximize' flag) or re-established by the consumer.
	343	+ */
	344	+ raspberrypi_fw_set_rate(hw, min_rate, 0);
	345	+
313	346	ret = raspberrypi_clock_property(rpi->firmware, data,
314	347	RPI_FIRMWARE_SET_CLOCK_STATE, &state);
315	348	if (ret)
@@ -387,9 +420,6 @@ static struct clk_hw raspberrypi_clk_register(struct raspberrypi_clk rpi, · 71 unmodified lines
387	420	}
388	421	}
389	422
390		− if (variant->maximize)
391		− variant->min_rate = max_rate;
392		−
393	423	if (variant->min_rate) {
394	424	unsigned long rate;
395	425

drivers/clk/clk-composite.c+5−33

@@ -47,22 +47,10 @@ static int clk_composite_determine_rate_for_parent(struct clk_hw *rate_hw, · 46 unmodified lines
47	47	struct clk_hw *parent_hw,
48	48	const struct clk_ops *rate_ops)
49	49	{
50		− long rate;
51		−
52	50	req->best_parent_hw = parent_hw;
53	51	req->best_parent_rate = clk_hw_get_rate(parent_hw);
54	52
55		− if (rate_ops->determine_rate)
56		− return rate_ops->determine_rate(rate_hw, req);
57		−
58		− rate = rate_ops->round_rate(rate_hw, req->rate,
59		− &req->best_parent_rate);
60		− if (rate < 0)
61		− return rate;
62		−
63		− req->rate = rate;
64		−
65		− return 0;
	53	+ return rate_ops->determine_rate(rate_hw, req);
66	54	}
67	55
68	56	static int clk_composite_determine_rate(struct clk_hw *hw,
@@ -79,8 +67,7 @@ static int clk_composite_determine_rate(struct clk_hw *hw, · 10 unmodified lines
79	67	unsigned long best_rate = 0;
80	68	int i, ret;
81	69
82		− if (rate_hw && rate_ops &&
83		− (rate_ops->determine_rate \|\| rate_ops->round_rate) &&
	70	+ if (rate_hw && rate_ops && rate_ops->determine_rate &&
84	71	mux_hw && mux_ops && mux_ops->set_parent) {
85	72	req->best_parent_hw = NULL;
86	73
@@ -150,18 +137,6 @@ static int clk_composite_determine_rate(struct clk_hw *hw, · 63 unmodified lines
150	137	}
151	138	}
152	139
153		−static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
154		− unsigned long *prate)
155		−{
156		− struct clk_composite *composite = to_clk_composite(hw);
157		− const struct clk_ops *rate_ops = composite->rate_ops;
158		− struct clk_hw *rate_hw = composite->rate_hw;
159		−
160		− __clk_hw_set_clk(rate_hw, hw);
161		−
162		− return rate_ops->round_rate(rate_hw, rate, prate);
163		−}
164		−
165	140	static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
166	141	unsigned long parent_rate)
167	142	{
@@ -288,17 +263,14 @@ static struct clk_hw __clk_hw_register_composite(struct device dev, · 120 unmodified lines
288	263	if (rate_ops->determine_rate)
289	264	clk_composite_ops->determine_rate =
290	265	clk_composite_determine_rate;
291		− else if (rate_ops->round_rate)
292		− clk_composite_ops->round_rate =
293		− clk_composite_round_rate;
294	266
295		− /* .set_rate requires either .round_rate or .determine_rate */
	267	+ /* .set_rate requires .determine_rate */
296	268	if (rate_ops->set_rate) {
297		− if (rate_ops->determine_rate \|\| rate_ops->round_rate)
	269	+ if (rate_ops->determine_rate)
298	270	clk_composite_ops->set_rate =
299	271	clk_composite_set_rate;
300	272	else
301		− WARN(1, "%s: missing round_rate op is required\n",
	273	+ WARN(1, "%s: missing determine_rate op is required\n",
302	274	__func__);
303	275	}
304	276

drivers/clk/clk-divider.c+0−44

@@ -387,50 +387,6 @@ int divider_ro_determine_rate(struct clk_hw hw, struct clk_rate_request req, · 386 unmodified lines
387	387	}
388	388	EXPORT_SYMBOL_GPL(divider_ro_determine_rate);
389	389
390		−long divider_round_rate_parent(struct clk_hw hw, struct clk_hw parent,
391		− unsigned long rate, unsigned long *prate,
392		− const struct clk_div_table *table,
393		− u8 width, unsigned long flags)
394		−{
395		− struct clk_rate_request req;
396		− int ret;
397		−
398		− clk_hw_init_rate_request(hw, &req, rate);
399		− req.best_parent_rate = *prate;
400		− req.best_parent_hw = parent;
401		−
402		− ret = divider_determine_rate(hw, &req, table, width, flags);
403		− if (ret)
404		− return ret;
405		−
406		− *prate = req.best_parent_rate;
407		−
408		− return req.rate;
409		−}
410		−EXPORT_SYMBOL_GPL(divider_round_rate_parent);
411		−
412		−long divider_ro_round_rate_parent(struct clk_hw hw, struct clk_hw parent,
413		− unsigned long rate, unsigned long *prate,
414		− const struct clk_div_table *table, u8 width,
415		− unsigned long flags, unsigned int val)
416		−{
417		− struct clk_rate_request req;
418		− int ret;
419		−
420		− clk_hw_init_rate_request(hw, &req, rate);
421		− req.best_parent_rate = *prate;
422		− req.best_parent_hw = parent;
423		−
424		− ret = divider_ro_determine_rate(hw, &req, table, width, flags, val);
425		− if (ret)
426		− return ret;
427		−
428		− *prate = req.best_parent_rate;
429		−
430		− return req.rate;
431		−}
432		−EXPORT_SYMBOL_GPL(divider_ro_round_rate_parent);
433		−
434	390	static int clk_divider_determine_rate(struct clk_hw *hw,
435	391	struct clk_rate_request *req)
436	392	{

drivers/clk/clk-en7523.c+218−5

@@ -1,5 +1,6 @@
1	1	// SPDX-License-Identifier: GPL-2.0-only
2	2
	3	+#include <linux/bitfield.h>
3	4	#include <linux/delay.h>
4	5	#include <linux/clk-provider.h>
5	6	#include <linux/io.h>
@@ -11,6 +12,8 @@ · 5 unmodified lines
11	12	#include <dt-bindings/clock/en7523-clk.h>
12	13	#include <dt-bindings/reset/airoha,en7523-reset.h>
13	14	#include <dt-bindings/reset/airoha,en7581-reset.h>
	15	+#include <dt-bindings/clock/econet,en751221-scu.h>
	16	+#include <dt-bindings/reset/econet,en751221-scu.h>
14	17
15	18	#define RST_NR_PER_BANK 32
16	19
@@ -33,15 +36,50 @@ · 16 unmodified lines
33	36	#define REG_RESET_CONTROL_PCIEHB BIT(29)
34	37	#define REG_RESET_CONTROL_PCIE1 BIT(27)
35	38	#define REG_RESET_CONTROL_PCIE2 BIT(26)
	39	+#define REG_HIR 0x064
	40	+#define REG_HIR_MASK GENMASK(31, 16)
36	41	/* EN7581 */
37	42	#define REG_NP_SCU_PCIC 0x88
38	43	#define REG_NP_SCU_SSTR 0x9c
39	44	#define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13)
40	45	#define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11)
41	46	#define REG_CRYPTO_CLKSRC2 0x20c
	47	+/* EN751221 */
	48	+#define EN751221_REG_SPI_DIV 0x0cc
	49	+#define EN751221_REG_SPI_DIV_MASK GENMASK(31, 8)
	50	+#define EN751221_SPI_BASE 500000000
	51	+#define EN751221_SPI_BASE_EN7526C 400000000
	52	+#define EN751221_SPI_DIV_DEFAULT 40
	53	+#define EN751221_REG_BUS 0x284
	54	+#define EN751221_REG_BUS_MASK GENMASK(21, 12)
	55	+#define EN751221_REG_SSR3 0x094
	56	+#define EN751221_REG_SSR3_GSW_MASK GENMASK(9, 8)
42	57
43	58	#define REG_RST_CTRL2 0x830
44	59	#define REG_RST_CTRL1 0x834
	60	+#define EN751221_REG_RST_DMT 0x84
	61	+#define EN751221_REG_RST_USB 0xec
	62	+
	63	+#define EN751221_MAX_CLKS 5
	64	+
	65	+enum en_hir {
	66	+ HIR_UNKNOWN = -1,
	67	+ HIR_TC3169 = 0,
	68	+ HIR_TC3182 = 1,
	69	+ HIR_RT65168 = 2,
	70	+ HIR_RT63165 = 3,
	71	+ HIR_RT63365 = 4,
	72	+ HIR_MT751020 = 5,
	73	+ HIR_MT7505 = 6,
	74	+ HIR_EN751221 = 7,
	75	+ HIR_EN7526C = 8,
	76	+ HIR_EN751627 = 9,
	77	+ HIR_EN7580 = 10,
	78	+ HIR_EN7528 = 11,
	79	+ HIR_EN7523 = 12,
	80	+ HIR_EN7581 = 13,
	81	+ HIR_MAX = 14,
	82	+};
45	83
46	84	struct en_clk_desc {
47	85	int id;
@@ -93,6 +131,8 @@ static const u32 bus7581_base[] = { 600000000, 540000000 }; · 45 unmodified lines
93	131	static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 };
94	132	static const u32 crypto_base[] = { 540000000, 480000000 };
95	133	static const u32 emmc7581_base[] = { 200000000, 150000000 };
	134	+/* EN751221 */
	135	+static const u32 gsw751221_base[] = { 500000000, 250000000, 400000000, 200000000 };
96	136
97	137	static const struct en_clk_desc en7523_base_clks[] = {
98	138	{
@@ -300,6 +340,13 @@ static const u16 en7581_rst_ofs[] = { · 201 unmodified lines
300	340	REG_RST_CTRL1,
301	341	};
302	342
	343	+static const u16 en751221_rst_ofs[] = {
	344	+ REG_RST_CTRL2,
	345	+ REG_RST_CTRL1,
	346	+ EN751221_REG_RST_DMT,
	347	+ EN751221_REG_RST_USB,
	348	+};
	349	+
303	350	static const u16 en7523_rst_map[] = {
304	351	/* RST_CTRL2 */
305	352	[EN7523_XPON_PHY_RST] = 0,
@@ -405,8 +452,61 @@ static const u16 en7581_rst_map[] = { · 99 unmodified lines
405	452	[EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
406	453	};
407	454
	455	+static const u16 en751221_rst_map[] = {
	456	+ /* RST_CTRL2 */
	457	+ [EN751221_XPON_PHY_RST] = 0,
	458	+ [EN751221_GFAST_RST] = 1,
	459	+ [EN751221_CPU_TIMER2_RST] = 2,
	460	+ [EN751221_UART3_RST] = 3,
	461	+ [EN751221_UART4_RST] = 4,
	462	+ [EN751221_UART5_RST] = 5,
	463	+ [EN751221_I2C2_RST] = 6,
	464	+ [EN751221_XSI_MAC_RST] = 7,
	465	+ [EN751221_XSI_PHY_RST] = 8,
	466	+
	467	+ /* RST_CTRL1 */
	468	+ [EN751221_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0,
	469	+ [EN751221_FE_QDMA1_RST] = RST_NR_PER_BANK + 1,
	470	+ [EN751221_FE_QDMA2_RST] = RST_NR_PER_BANK + 2,
	471	+ [EN751221_FE_UNZIP_RST] = RST_NR_PER_BANK + 3,
	472	+ [EN751221_PCM2_RST] = RST_NR_PER_BANK + 4,
	473	+ [EN751221_PTM_MAC_RST] = RST_NR_PER_BANK + 5,
	474	+ [EN751221_CRYPTO_RST] = RST_NR_PER_BANK + 6,
	475	+ [EN751221_SAR_RST] = RST_NR_PER_BANK + 7,
	476	+ [EN751221_TIMER_RST] = RST_NR_PER_BANK + 8,
	477	+ [EN751221_INTC_RST] = RST_NR_PER_BANK + 9,
	478	+ [EN751221_BONDING_RST] = RST_NR_PER_BANK + 10,
	479	+ [EN751221_PCM1_RST] = RST_NR_PER_BANK + 11,
	480	+ [EN751221_UART_RST] = RST_NR_PER_BANK + 12,
	481	+ [EN751221_GPIO_RST] = RST_NR_PER_BANK + 13,
	482	+ [EN751221_GDMA_RST] = RST_NR_PER_BANK + 14,
	483	+ [EN751221_I2C_MASTER_RST] = RST_NR_PER_BANK + 16,
	484	+ [EN751221_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17,
	485	+ [EN751221_SFC_RST] = RST_NR_PER_BANK + 18,
	486	+ [EN751221_UART2_RST] = RST_NR_PER_BANK + 19,
	487	+ [EN751221_GDMP_RST] = RST_NR_PER_BANK + 20,
	488	+ [EN751221_FE_RST] = RST_NR_PER_BANK + 21,
	489	+ [EN751221_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22,
	490	+ [EN751221_GSW_RST] = RST_NR_PER_BANK + 23,
	491	+ [EN751221_SFC2_PCM_RST] = RST_NR_PER_BANK + 25,
	492	+ [EN751221_PCIE0_RST] = RST_NR_PER_BANK + 26,
	493	+ [EN751221_PCIE1_RST] = RST_NR_PER_BANK + 27,
	494	+ [EN751221_CPU_TIMER_RST] = RST_NR_PER_BANK + 28,
	495	+ [EN751221_PCIE_HB_RST] = RST_NR_PER_BANK + 29,
	496	+ [EN751221_SIMIF_RST] = RST_NR_PER_BANK + 30,
	497	+ [EN751221_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
	498	+
	499	+ /* RST_DMT */
	500	+ [EN751221_DMT_RST] = 2 * RST_NR_PER_BANK + 0,
	501	+
	502	+ /* RST_USB */
	503	+ [EN751221_USB_PHY_P0_RST] = 3 * RST_NR_PER_BANK + 6,
	504	+ [EN751221_USB_PHY_P1_RST] = 3 * RST_NR_PER_BANK + 7,
	505	+};
	506	+
408	507	static int en7581_reset_register(struct device dev, void __iomem base,
409		− const u16 *rst_map, int nr_resets);
	508	+ const u16 *rst_map, int nr_resets,
	509	+ const u16 *rst_reg_ofs);
410	510
411	511	static u32 en7523_get_base_rate(const struct en_clk_desc *desc, u32 val)
412	512	{
@@ -604,7 +704,8 @@ static int en7523_clk_hw_init(struct platform_device *pdev, · 191 unmodified lines
604	704	en7523_register_clocks(&pdev->dev, clk_data, base, np_base);
605	705
606	706	return en7581_reset_register(&pdev->dev, np_base, en7523_rst_map,
607		− ARRAY_SIZE(en7523_rst_map));
	707	+ ARRAY_SIZE(en7523_rst_map),
	708	+ en7581_rst_ofs);
608	709	}
609	710
610	711	static void en7581_register_clocks(struct device dev, struct clk_hw_onecell_data clk_data,
@@ -705,7 +806,8 @@ static const struct reset_control_ops en7581_reset_ops = { · 94 unmodified lines
705	806	};
706	807
707	808	static int en7581_reset_register(struct device dev, void __iomem base,
708		− const u16 *rst_map, int nr_resets)
	809	+ const u16 *rst_map, int nr_resets,
	810	+ const u16 *rst_reg_ofs)
709	811	{
710	812	struct en_rst_data *rst_data;
711	813
@@ -713,7 +815,7 @@ static int en7581_reset_register(struct device dev, void __iomem base, · 1 unmodified line
713	815	if (!rst_data)
714	816	return -ENOMEM;
715	817
716		− rst_data->bank_ofs = en7581_rst_ofs;
	818	+ rst_data->bank_ofs = rst_reg_ofs;
717	819	rst_data->idx_map = rst_map;
718	820	rst_data->base = base;
719	821
@@ -752,7 +854,107 @@ static int en7581_clk_hw_init(struct platform_device *pdev, · 32 unmodified lines
752	854	writel(val \| 3, base + REG_NP_SCU_PCIC);
753	855
754	856	return en7581_reset_register(&pdev->dev, base, en7581_rst_map,
755		− ARRAY_SIZE(en7581_rst_map));
	857	+ ARRAY_SIZE(en7581_rst_map),
	858	+ en7581_rst_ofs);
	859	+}
	860	+
	861	+static enum en_hir get_hw_id(void __iomem *np_base)
	862	+{
	863	+ u32 val = FIELD_GET(REG_HIR_MASK, readl(np_base + REG_HIR));
	864	+
	865	+ if (val < HIR_MAX)
	866	+ return (enum en_hir)val;
	867	+
	868	+ pr_warn("Unable to determine EcoNet SoC\n");
	869	+
	870	+ return HIR_UNKNOWN;
	871	+}
	872	+
	873	+static void en751221_try_register_clk(struct device *dev, int key,
	874	+ struct clk_hw_onecell_data *clk_data,
	875	+ const char *name, u32 rate)
	876	+{
	877	+ struct clk_hw *hw;
	878	+
	879	+ if (WARN_ON_ONCE(key >= EN751221_MAX_CLKS))
	880	+ return;
	881	+
	882	+ hw = clk_hw_register_fixed_rate(dev, name, NULL, 0, rate);
	883	+ if (IS_ERR(hw))
	884	+ pr_err("Failed to register clk %s: %pe\n", name, hw);
	885	+ else
	886	+ clk_data->hws[key] = hw;
	887	+}
	888	+
	889	+static void en751221_register_clocks(struct device *dev,
	890	+ struct clk_hw_onecell_data *clk_data,
	891	+ struct regmap map, void __iomem np_base)
	892	+{
	893	+ enum en_hir hid = get_hw_id(np_base);
	894	+ struct clk_hw *hw;
	895	+ u32 rate;
	896	+ u32 div;
	897	+ int err;
	898	+
	899	+ /* PCI */
	900	+ hw = en7523_register_pcie_clk(dev, np_base);
	901	+ clk_data->hws[EN751221_CLK_PCIE] = hw;
	902	+
	903	+ /* SPI */
	904	+ rate = EN751221_SPI_BASE;
	905	+ if (hid == HIR_EN7526C)
	906	+ rate = EN751221_SPI_BASE_EN7526C;
	907	+
	908	+ err = regmap_read(map, EN751221_REG_SPI_DIV, &div);
	909	+ if (err) {
	910	+ pr_err("Failed reading fixed clk div %s: %d\n",
	911	+ "spi", err);
	912	+ } else {
	913	+ div = FIELD_GET(EN751221_REG_SPI_DIV_MASK, div) * 2;
	914	+ if (!div)
	915	+ div = EN751221_SPI_DIV_DEFAULT;
	916	+
	917	+ en751221_try_register_clk(dev, EN751221_CLK_SPI, clk_data,
	918	+ "spi", rate / div);
	919	+ }
	920	+
	921	+ /* BUS */
	922	+ rate = FIELD_GET(EN751221_REG_BUS_MASK,
	923	+ readl(np_base + EN751221_REG_BUS));
	924	+ rate *= 1000000;
	925	+ en751221_try_register_clk(dev, EN751221_CLK_BUS, clk_data, "bus",
	926	+ rate);
	927	+
	928	+ /* CPU */
	929	+ en751221_try_register_clk(dev, EN751221_CLK_CPU, clk_data, "cpu",
	930	+ rate * 4);
	931	+
	932	+ /* GSW */
	933	+ rate = FIELD_GET(EN751221_REG_SSR3_GSW_MASK,
	934	+ readl(np_base + EN751221_REG_SSR3));
	935	+ en751221_try_register_clk(dev, EN751221_CLK_GSW, clk_data, "gsw",
	936	+ gsw751221_base[rate]);
	937	+}
	938	+
	939	+static int en751221_clk_hw_init(struct platform_device *pdev,
	940	+ struct clk_hw_onecell_data *clk_data)
	941	+{
	942	+ struct regmap *map;
	943	+ void __iomem *base;
	944	+
	945	+ map = syscon_regmap_lookup_by_compatible("econet,en751221-chip-scu");
	946	+ if (IS_ERR(map))
	947	+ return PTR_ERR(map);
	948	+
	949	+ base = devm_platform_ioremap_resource(pdev, 0);
	950	+ if (IS_ERR(base))
	951	+ return PTR_ERR(base);
	952	+
	953	+ en751221_register_clocks(&pdev->dev, clk_data, map, base);
	954	+
	955	+ return en7581_reset_register(&pdev->dev, base, en751221_rst_map,
	956	+ ARRAY_SIZE(en751221_rst_map),
	957	+ en751221_rst_ofs);
756	958	}
757	959
758	960	static int en7523_clk_probe(struct platform_device *pdev)
@@ -799,9 +1001,20 @@ static const struct en_clk_soc_data en7581_data = { · 40 unmodified lines
799	1001	.hw_init = en7581_clk_hw_init,
800	1002	};
801	1003
	1004	+static const struct en_clk_soc_data en751221_data = {
	1005	+ .num_clocks = EN751221_MAX_CLKS,
	1006	+ .pcie_ops = {
	1007	+ .is_enabled = en7523_pci_is_enabled,
	1008	+ .prepare = en7523_pci_prepare,
	1009	+ .unprepare = en7523_pci_unprepare,
	1010	+ },
	1011	+ .hw_init = en751221_clk_hw_init,
	1012	+};
	1013	+
802	1014	static const struct of_device_id of_match_clk_en7523[] = {
803	1015	{ .compatible = "airoha,en7523-scu", .data = &en7523_data },
804	1016	{ .compatible = "airoha,en7581-scu", .data = &en7581_data },
	1017	+ { .compatible = "econet,en751221-scu", .data = &en751221_data },
805	1018	{ /* sentinel */ }
806	1019	};
807	1020

drivers/clk/clk-fsl-sai.c+118−30

@@ -5,34 +5,110 @@ · 4 unmodified lines
5	5	* Copyright 2020 Michael Walle <michael@walle.cc>
6	6	*/
7	7
8		−#include <linux/module.h>
9		−#include <linux/platform_device.h>
10	8	#include <linux/clk-provider.h>
	9	+#include <linux/clk.h>
11	10	#include <linux/err.h>
	11	+#include <linux/module.h>
12	12	#include <linux/of.h>
13	13	#include <linux/of_address.h>
	14	+#include <linux/platform_device.h>
14	15	#include <linux/slab.h>
15	16
16	17	#define I2S_CSR 0x00
17	18	#define I2S_CR2 0x08
	19	+#define I2S_MCR 0x100
18	20	#define CSR_BCE_BIT 28
	21	+#define CSR_TE_BIT 31
19	22	#define CR2_BCD BIT(24)
20	23	#define CR2_DIV_SHIFT 0
21	24	#define CR2_DIV_WIDTH 8
	25	+#define MCR_MOE BIT(30)
	26	+
	27	+struct fsl_sai_data {
	28	+ unsigned int offset; /* Register offset */
	29	+ bool have_mclk; /* Have MCLK control */
	30	+};
22	31
23	32	struct fsl_sai_clk {
24		− struct clk_divider div;
25		− struct clk_gate gate;
	33	+ const struct fsl_sai_data *data;
	34	+ struct clk_divider bclk_div;
	35	+ struct clk_divider mclk_div;
	36	+ struct clk_gate bclk_gate;
	37	+ struct clk_gate mclk_gate;
	38	+ struct clk_hw *bclk_hw;
	39	+ struct clk_hw *mclk_hw;
26	40	spinlock_t lock;
27	41	};
28	42
	43	+static struct clk_hw *
	44	+fsl_sai_of_clk_get(struct of_phandle_args clkspec, void data)
	45	+{
	46	+ struct fsl_sai_clk *sai_clk = data;
	47	+
	48	+ if (clkspec->args_count == 0)
	49	+ return sai_clk->bclk_hw;
	50	+
	51	+ if (clkspec->args_count == 1) {
	52	+ if (clkspec->args[0] == 0)
	53	+ return sai_clk->bclk_hw;
	54	+ if (sai_clk->data->have_mclk && clkspec->args[0] == 1)
	55	+ return sai_clk->mclk_hw;
	56	+ }
	57	+
	58	+ return ERR_PTR(-EINVAL);
	59	+}
	60	+
	61	+static int fsl_sai_clk_register(struct device dev, void __iomem base,
	62	+ spinlock_t lock, struct clk_divider div,
	63	+ struct clk_gate gate, struct clk_hw *hw,
	64	+ const int gate_bit, const int dir_bit,
	65	+ const int div_reg, char *name)
	66	+{
	67	+ const struct fsl_sai_data *data = device_get_match_data(dev);
	68	+ struct clk_parent_data pdata = { .index = 0 };
	69	+ struct clk_hw *chw;
	70	+ char *cname;
	71	+
	72	+ gate->reg = base + data->offset + I2S_CSR;
	73	+ gate->bit_idx = gate_bit;
	74	+ gate->lock = lock;
	75	+
	76	+ div->reg = base + div_reg;
	77	+ div->shift = CR2_DIV_SHIFT;
	78	+ div->width = CR2_DIV_WIDTH;
	79	+ div->lock = lock;
	80	+
	81	+ cname = devm_kasprintf(dev, GFP_KERNEL, "%s.%s",
	82	+ of_node_full_name(dev->of_node), name);
	83	+ if (!cname)
	84	+ return -ENOMEM;
	85	+
	86	+ /* Set clock direction */
	87	+ writel(dir_bit, base + div_reg);
	88	+
	89	+ chw = devm_clk_hw_register_composite_pdata(dev, cname,
	90	+ &pdata, 1, NULL, NULL,
	91	+ &div->hw,
	92	+ &clk_divider_ops,
	93	+ &gate->hw,
	94	+ &clk_gate_ops,
	95	+ CLK_SET_RATE_GATE);
	96	+ if (IS_ERR(chw))
	97	+ return PTR_ERR(chw);
	98	+
	99	+ *hw = chw;
	100	+
	101	+ return 0;
	102	+}
	103	+
29	104	static int fsl_sai_clk_probe(struct platform_device *pdev)
30	105	{
31	106	struct device *dev = &pdev->dev;
	107	+ const struct fsl_sai_data *data = device_get_match_data(dev);
32	108	struct fsl_sai_clk *sai_clk;
33		− struct clk_parent_data pdata = { .index = 0 };
	109	+ struct clk *clk_bus;
34	110	void __iomem *base;
35		− struct clk_hw *hw;
	111	+ int ret;
36	112
37	113	sai_clk = devm_kzalloc(dev, sizeof(*sai_clk), GFP_KERNEL);
38	114	if (!sai_clk)
@@ -42,35 +118,47 @@ static int fsl_sai_clk_probe(struct platform_device *pdev) · 3 unmodified lines
42	118	if (IS_ERR(base))
43	119	return PTR_ERR(base);
44	120
	121	+ clk_bus = devm_clk_get_optional_enabled(dev, "bus");
	122	+ if (IS_ERR(clk_bus))
	123	+ return PTR_ERR(clk_bus);
	124	+
	125	+ sai_clk->data = data;
45	126	spin_lock_init(&sai_clk->lock);
46	127
47		− sai_clk->gate.reg = base + I2S_CSR;
48		− sai_clk->gate.bit_idx = CSR_BCE_BIT;
49		− sai_clk->gate.lock = &sai_clk->lock;
50		−
51		− sai_clk->div.reg = base + I2S_CR2;
52		− sai_clk->div.shift = CR2_DIV_SHIFT;
53		− sai_clk->div.width = CR2_DIV_WIDTH;
54		− sai_clk->div.lock = &sai_clk->lock;
55		−
56		− /* set clock direction, we are the BCLK master */
57		− writel(CR2_BCD, base + I2S_CR2);
58		−
59		− hw = devm_clk_hw_register_composite_pdata(dev, dev->of_node->name,
60		− &pdata, 1, NULL, NULL,
61		− &sai_clk->div.hw,
62		− &clk_divider_ops,
63		− &sai_clk->gate.hw,
64		− &clk_gate_ops,
65		− CLK_SET_RATE_GATE);
66		− if (IS_ERR(hw))
67		− return PTR_ERR(hw);
68		−
69		− return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
	128	+ ret = fsl_sai_clk_register(dev, base, &sai_clk->lock,
	129	+ &sai_clk->bclk_div, &sai_clk->bclk_gate,
	130	+ &sai_clk->bclk_hw, CSR_BCE_BIT, CR2_BCD,
	131	+ data->offset + I2S_CR2, "BCLK");
	132	+ if (ret)
	133	+ return ret;
	134	+
	135	+ if (data->have_mclk) {
	136	+ ret = fsl_sai_clk_register(dev, base, &sai_clk->lock,
	137	+ &sai_clk->mclk_div,
	138	+ &sai_clk->mclk_gate,
	139	+ &sai_clk->mclk_hw,
	140	+ CSR_TE_BIT, MCR_MOE, I2S_MCR,
	141	+ "MCLK");
	142	+ if (ret)
	143	+ return ret;
	144	+ }
	145	+
	146	+ return devm_of_clk_add_hw_provider(dev, fsl_sai_of_clk_get, sai_clk);
70	147	}
71	148
	149	+static const struct fsl_sai_data fsl_sai_vf610_data = {
	150	+ .offset = 0,
	151	+ .have_mclk = false,
	152	+};
	153	+
	154	+static const struct fsl_sai_data fsl_sai_imx8mq_data = {
	155	+ .offset = 8,
	156	+ .have_mclk = true,
	157	+};
	158	+
72	159	static const struct of_device_id of_fsl_sai_clk_ids[] = {
73		− { .compatible = "fsl,vf610-sai-clock" },
	160	+ { .compatible = "fsl,vf610-sai-clock", .data = &fsl_sai_vf610_data },
	161	+ { .compatible = "fsl,imx8mq-sai-clock", .data = &fsl_sai_imx8mq_data },
74	162	{ }
75	163	};
76	164	MODULE_DEVICE_TABLE(of, of_fsl_sai_clk_ids);

drivers/clk/clk-qoriq.c+9−8

@@ -907,13 +907,11 @@ static const struct clockgen_pll_div get_pll_div(struct clockgen cg, · 906 unmodified lines
907	907	return &cg->pll[pll].div[div];
908	908	}
909	909
910		−static struct clk * __init create_mux_common(struct clockgen *cg,
911		− struct mux_hwclock *hwc,
912		− const struct clk_ops *ops,
913		− unsigned long min_rate,
914		− unsigned long max_rate,
915		− unsigned long pct80_rate,
916		− const char *fmt, int idx)
	910	+static struct clk * __init __printf(7, 8)
	911	+create_mux_common(struct clockgen cg, struct mux_hwclock hwc,
	912	+ const struct clk_ops *ops, unsigned long min_rate,
	913	+ unsigned long max_rate, unsigned long pct80_rate,
	914	+ const char *fmt, ...)
917	915	{
918	916	struct clk_init_data init = {};
919	917	struct clk *clk;
@@ -921,8 +919,11 @@ static struct clk * __init create_mux_common(struct clockgen *cg, · 1 unmodified line
921	919	const char *parent_names[NUM_MUX_PARENTS];
922	920	char name[32];
923	921	int i, j;
	922	+ va_list args;
924	923
925		− snprintf(name, sizeof(name), fmt, idx);
	924	+ va_start(args, fmt);
	925	+ vsnprintf(name, sizeof(name), fmt, args);
	926	+ va_end(args);
926	927
927	928	for (i = 0, j = 0; i < NUM_MUX_PARENTS; i++) {
928	929	unsigned long rate;

drivers/clk/clk-xgene.c+2−0

@@ -188,6 +188,8 @@ static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_ty · 187 unmodified lines
188	188	of_clk_add_provider(np, of_clk_src_simple_get, clk);
189	189	clk_register_clkdev(clk, clk_name, NULL);
190	190	pr_debug("Add %s clock PLL\n", clk_name);
	191	+ } else {
	192	+ iounmap(reg);
191	193	}
192	194	}
193	195

drivers/clk/clk.c+17−29

@@ -1560,8 +1560,6 @@ late_initcall_sync(clk_disable_unused); · 1559 unmodified lines
1560	1560	static int clk_core_determine_round_nolock(struct clk_core *core,
1561	1561	struct clk_rate_request *req)
1562	1562	{
1563		− long rate;
1564		−
1565	1563	lockdep_assert_held(&prepare_lock);
1566	1564
1567	1565	if (!core)
@@ -1591,13 +1589,6 @@ static int clk_core_determine_round_nolock(struct clk_core *core, · 23 unmodified lines
1591	1589	req->rate = core->rate;
1592	1590	} else if (core->ops->determine_rate) {
1593	1591	return core->ops->determine_rate(core->hw, req);
1594		− } else if (core->ops->round_rate) {
1595		− rate = core->ops->round_rate(core->hw, req->rate,
1596		− &req->best_parent_rate);
1597		− if (rate < 0)
1598		− return rate;
1599		−
1600		− req->rate = rate;
1601	1592	} else {
1602	1593	return -EINVAL;
1603	1594	}
@@ -1682,7 +1673,7 @@ EXPORT_SYMBOL_GPL(clk_hw_forward_rate_request); · 78 unmodified lines
1682	1673
1683	1674	static bool clk_core_can_round(struct clk_core * const core)
1684	1675	{
1685		− return core->ops->determine_rate \|\| core->ops->round_rate;
	1676	+ return core->ops->determine_rate;
1686	1677	}
1687	1678
1688	1679	static int clk_core_round_rate_nolock(struct clk_core *core,
@@ -1750,11 +1741,11 @@ EXPORT_SYMBOL_GPL(__clk_determine_rate); · 61 unmodified lines
1750	1741	* use.
1751	1742	*
1752	1743	* Context: prepare_lock must be held.
1753		− * For clk providers to call from within clk_ops such as .round_rate,
	1744	+ * For clk providers to call from within clk_ops such as
1754	1745	* .determine_rate.
1755	1746	*
1756		− * Return: returns rounded rate of hw clk if clk supports round_rate operation
1757		− * else returns the parent rate.
	1747	+ * Return: returns rounded rate of hw clk if clk supports determine_rate
	1748	+ * operation; else returns the parent rate.
1758	1749	*/
1759	1750	unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate)
1760	1751	{
@@ -2569,12 +2560,13 @@ err: · 808 unmodified lines
2569	2560	*
2570	2561	* Setting the CLK_SET_RATE_PARENT flag allows the rate change operation to
2571	2562	* propagate up to clk's parent; whether or not this happens depends on the
2572		− * outcome of clk's .round_rate implementation. If *parent_rate is unchanged
2573		− * after calling .round_rate then upstream parent propagation is ignored. If
2574		− * *parent_rate comes back with a new rate for clk's parent then we propagate
2575		− * up to clk's parent and set its rate. Upward propagation will continue
2576		− * until either a clk does not support the CLK_SET_RATE_PARENT flag or
2577		− * .round_rate stops requesting changes to clk's parent_rate.
	2563	+ * outcome of clk's .determine_rate implementation. If req->best_parent_rate
	2564	+ * is unchanged after calling .determine_rate then upstream parent propagation
	2565	+ * is ignored. If req->best_parent_rate comes back with a new rate for clk's
	2566	+ * parent then we propagate up to clk's parent and set its rate. Upward
	2567	+ * propagation will continue until either a clk does not support the
	2568	+ * CLK_SET_RATE_PARENT flag or .determine_rate stops requesting changes to
	2569	+ * clk's parent_rate.
2578	2570	*
2579	2571	* Rate changes are accomplished via tree traversal that also recalculates the
2580	2572	* rates for the clocks and fires off POST_RATE_CHANGE notifiers.
@@ -2703,8 +2695,6 @@ static int clk_set_rate_range_nolock(struct clk *clk, · 122 unmodified lines
2703	2695	* FIXME:
2704	2696	* There is a catch. It may fail for the usual reason (clock
2705	2697	* broken, clock protected, etc) but also because:
2706		− * - round_rate() was not favorable and fell on the wrong
2707		− * side of the boundary
2708	2698	* - the determine_rate() callback does not really check for
2709	2699	* this corner case when determining the rate
2710	2700	*/
@@ -3259,11 +3249,10 @@ bool clk_is_match(const struct clk p, const struct clk q) · 548 unmodified lines
3259	3249	return true;
3260	3250
3261	3251	/* true if clk->core pointers match. Avoid dereferencing garbage */
3262		− if (!IS_ERR_OR_NULL(p) && !IS_ERR_OR_NULL(q))
3263		− if (p->core == q->core)
3264		− return true;
	3252	+ if (IS_ERR_OR_NULL(p) \|\| IS_ERR_OR_NULL(q))
	3253	+ return false;
3265	3254
3266		− return false;
	3255	+ return p->core == q->core;
3267	3256	}
3268	3257	EXPORT_SYMBOL_GPL(clk_is_match);
3269	3258
@@ -3915,10 +3904,9 @@ static int __clk_core_init(struct clk_core *core) · 645 unmodified lines
3915	3904	}
3916	3905
3917	3906	/* check that clk_ops are sane. See Documentation/driver-api/clk.rst */
3918		− if (core->ops->set_rate &&
3919		− !((core->ops->round_rate \|\| core->ops->determine_rate) &&
3920		− core->ops->recalc_rate)) {
3921		− pr_err("%s: %s must implement .round_rate or .determine_rate in addition to .recalc_rate\n",
	3907	+ if (core->ops->set_rate && !core->ops->determine_rate &&
	3908	+ core->ops->recalc_rate) {
	3909	+ pr_err("%s: %s must implement .determine_rate in addition to .recalc_rate\n",
3922	3910	__func__, core->name);
3923	3911	ret = -EINVAL;
3924	3912	goto out;

drivers/clk/clk_test.c+8−8

@@ -241,8 +241,8 @@ static void clk_test_get_rate(struct kunit *test) · 240 unmodified lines
241	241	* Test that, after a call to clk_set_rate(), the rate returned by
242	242	* clk_get_rate() matches.
243	243	*
244		− * This assumes that clk_ops.determine_rate or clk_ops.round_rate won't
245		− * modify the requested rate, which is our case in clk_dummy_rate_ops.
	244	+ * This assumes that clk_ops.determine_rate won't modify the requested rate,
	245	+ * which is our case in clk_dummy_rate_ops.
246	246	*/
247	247	static void clk_test_set_get_rate(struct kunit *test)
248	248	{
@@ -266,8 +266,8 @@ static void clk_test_set_get_rate(struct kunit *test) · 17 unmodified lines
266	266	* Test that, after several calls to clk_set_rate(), the rate returned
267	267	* by clk_get_rate() matches the last one.
268	268	*
269		− * This assumes that clk_ops.determine_rate or clk_ops.round_rate won't
270		− * modify the requested rate, which is our case in clk_dummy_rate_ops.
	269	+ * This assumes that clk_ops.determine_rate won't modify the requested rate,
	270	+ * which is our case in clk_dummy_rate_ops.
271	271	*/
272	272	static void clk_test_set_set_get_rate(struct kunit *test)
273	273	{
@@ -1675,8 +1675,8 @@ static void clk_range_test_set_range_set_round_rate_consistent_higher(struct kun · 1401 unmodified lines
1675	1675	* call to clk_set_rate_range(), the rate will be raised to match the
1676	1676	* new minimum.
1677	1677	*
1678		− * This assumes that clk_ops.determine_rate or clk_ops.round_rate won't
1679		− * modify the requested rate, which is our case in clk_dummy_rate_ops.
	1678	+ * This assumes that clk_ops.determine_rate won't modify the requested rate,
	1679	+ * which is our case in clk_dummy_rate_ops.
1680	1680	*/
1681	1681	static void clk_range_test_set_range_get_rate_raised(struct kunit *test)
1682	1682	{
@@ -1707,8 +1707,8 @@ static void clk_range_test_set_range_get_rate_raised(struct kunit *test) · 24 unmodified lines
1707	1707	* call to clk_set_rate_range(), the rate will be lowered to match the
1708	1708	* new maximum.
1709	1709	*
1710		− * This assumes that clk_ops.determine_rate or clk_ops.round_rate won't
1711		− * modify the requested rate, which is our case in clk_dummy_rate_ops.
	1710	+ * This assumes that clk_ops.determine_rate won't modify the requested rate,
	1711	+ * which is our case in clk_dummy_rate_ops.
1712	1712	*/
1713	1713	static void clk_range_test_set_range_get_rate_lowered(struct kunit *test)
1714	1714	{

drivers/clk/eswin/Kconfig+15−0

@@ -0,0 +1,15 @@
	1	+# SPDX-License-Identifier: GPL-2.0
	2	+
	3	+config COMMON_CLK_ESWIN
	4	+ bool
	5	+
	6	+config COMMON_CLK_EIC7700
	7	+ tristate "EIC7700 Clock Driver"
	8	+ depends on ARCH_ESWIN \|\| COMPILE_TEST
	9	+ select COMMON_CLK_ESWIN
	10	+ default ARCH_ESWIN
	11	+ help
	12	+ This driver provides support for clock controller on ESWIN EIC7700
	13	+ SoC. The clock controller generates and supplies clocks to various
	14	+ peripherals within the SoC.
	15	+ Say yes here to support the clock controller on the EIC7700 SoC.

drivers/clk/eswin/Makefile+8−0

@@ -0,0 +1,8 @@
	1	+# SPDX-License-Identifier: GPL-2.0
	2	+#
	3	+# Eswin Clock specific Makefile
	4	+#
	5	+
	6	+obj-$(CONFIG_COMMON_CLK_ESWIN) += clk.o
	7	+
	8	+obj-$(CONFIG_COMMON_CLK_EIC7700) += clk-eic7700.o

drivers/clk/eswin/clk-eic7700.c+1376−0

@@ -0,0 +1,1376 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+/*
	3	+ * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
	4	+ * All rights reserved.
	5	+ *
	6	+ * ESWIN EIC7700 Clk Provider Driver
	7	+ *
	8	+ * Authors:
	9	+ * Yifeng Huang <huangyifeng@eswincomputing.com>
	10	+ * Xuyang Dong <dongxuyang@eswincomputing.com>
	11	+ */
	12	+
	13	+#include <linux/clk.h>
	14	+#include <linux/clk-provider.h>
	15	+#include <linux/platform_device.h>
	16	+
	17	+#include <dt-bindings/clock/eswin,eic7700-clock.h>
	18	+
	19	+#include "common.h"
	20	+
	21	+/* REG OFFSET OF SYS-CRG */
	22	+#define EIC7700_REG_OFFSET_SPLL0_CFG_0 0x0
	23	+#define EIC7700_REG_OFFSET_SPLL0_CFG_1 0x4
	24	+#define EIC7700_REG_OFFSET_SPLL0_CFG_2 0x8
	25	+#define EIC7700_REG_OFFSET_SPLL0_DSKEWCAL 0xC
	26	+#define EIC7700_REG_OFFSET_SPLL0_SSC 0x10
	27	+#define EIC7700_REG_OFFSET_SPLL1_CFG_0 0x14
	28	+#define EIC7700_REG_OFFSET_SPLL1_CFG_1 0x18
	29	+#define EIC7700_REG_OFFSET_SPLL1_CFG_2 0x1C
	30	+#define EIC7700_REG_OFFSET_SPLL1_DSKEWCAL 0x20
	31	+#define EIC7700_REG_OFFSET_SPLL1_SSC 0x24
	32	+#define EIC7700_REG_OFFSET_SPLL2_CFG_0 0x28
	33	+#define EIC7700_REG_OFFSET_SPLL2_CFG_1 0x2C
	34	+#define EIC7700_REG_OFFSET_SPLL2_CFG_2 0x30
	35	+#define EIC7700_REG_OFFSET_SPLL2_DSKEWCAL 0x34
	36	+#define EIC7700_REG_OFFSET_SPLL2_SSC 0x38
	37	+#define EIC7700_REG_OFFSET_VPLL_CFG_0 0x3C
	38	+#define EIC7700_REG_OFFSET_VPLL_CFG_1 0x40
	39	+#define EIC7700_REG_OFFSET_VPLL_CFG_2 0x44
	40	+#define EIC7700_REG_OFFSET_VPLL_DSKEWCAL 0x48
	41	+#define EIC7700_REG_OFFSET_VPLL_SSC 0x4C
	42	+#define EIC7700_REG_OFFSET_APLL_CFG_0 0x50
	43	+#define EIC7700_REG_OFFSET_APLL_CFG_1 0x54
	44	+#define EIC7700_REG_OFFSET_APLL_CFG_2 0x58
	45	+#define EIC7700_REG_OFFSET_APLL_DSKEWCAL 0x5C
	46	+#define EIC7700_REG_OFFSET_APLL_SSC 0x60
	47	+#define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_0 0x64
	48	+#define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_1 0x68
	49	+#define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_2 0x6C
	50	+#define EIC7700_REG_OFFSET_MCPUT_PLL_DSKEWCAL 0x70
	51	+#define EIC7700_REG_OFFSET_MCPUT_PLL_SSC 0x74
	52	+#define EIC7700_REG_OFFSET_DDRT_PLL_CFG_0 0x78
	53	+#define EIC7700_REG_OFFSET_DDRT_PLL_CFG_1 0x7C
	54	+#define EIC7700_REG_OFFSET_DDRT_PLL_CFG_2 0x80
	55	+#define EIC7700_REG_OFFSET_DDRT_PLL_DSKEWCAL 0x84
	56	+#define EIC7700_REG_OFFSET_DDRT_PLL_SSC 0x88
	57	+#define EIC7700_REG_OFFSET_PLL_STATUS 0xA4
	58	+#define EIC7700_REG_OFFSET_NOC 0x100
	59	+#define EIC7700_REG_OFFSET_BOOTSPI 0x104
	60	+#define EIC7700_REG_OFFSET_BOOTSPI_CFGCLK 0x108
	61	+#define EIC7700_REG_OFFSET_SCPU_CORE 0x10C
	62	+#define EIC7700_REG_OFFSET_SCPU_BUSCLK 0x110
	63	+#define EIC7700_REG_OFFSET_LPCPU_CORE 0x114
	64	+#define EIC7700_REG_OFFSET_LPCPU_BUSCLK 0x118
	65	+#define EIC7700_REG_OFFSET_TCU_ACLK 0x11C
	66	+#define EIC7700_REG_OFFSET_TCU_CFG 0x120
	67	+#define EIC7700_REG_OFFSET_DDR 0x124
	68	+#define EIC7700_REG_OFFSET_DDR1 0x128
	69	+#define EIC7700_REG_OFFSET_GPU_ACLK 0x12C
	70	+#define EIC7700_REG_OFFSET_GPU_CFG 0x130
	71	+#define EIC7700_REG_OFFSET_GPU_GRAY 0x134
	72	+#define EIC7700_REG_OFFSET_DSP_ACLK 0x138
	73	+#define EIC7700_REG_OFFSET_DSP_CFG 0x13C
	74	+#define EIC7700_REG_OFFSET_D2D_ACLK 0x140
	75	+#define EIC7700_REG_OFFSET_D2D_CFG 0x144
	76	+#define EIC7700_REG_OFFSET_HSP_ACLK 0x148
	77	+#define EIC7700_REG_OFFSET_HSP_CFG 0x14C
	78	+#define EIC7700_REG_OFFSET_SATA_RBC 0x150
	79	+#define EIC7700_REG_OFFSET_SATA_OOB 0x154
	80	+#define EIC7700_REG_OFFSET_ETH0 0x158
	81	+#define EIC7700_REG_OFFSET_ETH1 0x15C
	82	+#define EIC7700_REG_OFFSET_MSHC0_CORE 0x160
	83	+#define EIC7700_REG_OFFSET_MSHC1_CORE 0x164
	84	+#define EIC7700_REG_OFFSET_MSHC2_CORE 0x168
	85	+#define EIC7700_REG_OFFSET_MSHC_USB_SLWCLK 0x16C
	86	+#define EIC7700_REG_OFFSET_PCIE_ACLK 0x170
	87	+#define EIC7700_REG_OFFSET_PCIE_CFG 0x174
	88	+#define EIC7700_REG_OFFSET_NPU_ACLK 0x178
	89	+#define EIC7700_REG_OFFSET_NPU_LLC 0x17C
	90	+#define EIC7700_REG_OFFSET_NPU_CORE 0x180
	91	+#define EIC7700_REG_OFFSET_VI_DWCLK 0x184
	92	+#define EIC7700_REG_OFFSET_VI_ACLK 0x188
	93	+#define EIC7700_REG_OFFSET_VI_DIG_ISP 0x18C
	94	+#define EIC7700_REG_OFFSET_VI_DVP 0x190
	95	+#define EIC7700_REG_OFFSET_VI_SHUTTER0 0x194
	96	+#define EIC7700_REG_OFFSET_VI_SHUTTER1 0x198
	97	+#define EIC7700_REG_OFFSET_VI_SHUTTER2 0x19C
	98	+#define EIC7700_REG_OFFSET_VI_SHUTTER3 0x1A0
	99	+#define EIC7700_REG_OFFSET_VI_SHUTTER4 0x1A4
	100	+#define EIC7700_REG_OFFSET_VI_SHUTTER5 0x1A8
	101	+#define EIC7700_REG_OFFSET_VI_PHY 0x1AC
	102	+#define EIC7700_REG_OFFSET_VO_ACLK 0x1B0
	103	+#define EIC7700_REG_OFFSET_VO_IESMCLK 0x1B4
	104	+#define EIC7700_REG_OFFSET_VO_PIXEL 0x1B8
	105	+#define EIC7700_REG_OFFSET_VO_MCLK 0x1BC
	106	+#define EIC7700_REG_OFFSET_VO_PHY_CLK 0x1C0
	107	+#define EIC7700_REG_OFFSET_VC_ACLK 0x1C4
	108	+#define EIC7700_REG_OFFSET_VCDEC_ROOT 0x1C8
	109	+#define EIC7700_REG_OFFSET_G2D 0x1CC
	110	+#define EIC7700_REG_OFFSET_VC_CLKEN 0x1D0
	111	+#define EIC7700_REG_OFFSET_JE 0x1D4
	112	+#define EIC7700_REG_OFFSET_JD 0x1D8
	113	+#define EIC7700_REG_OFFSET_VD 0x1DC
	114	+#define EIC7700_REG_OFFSET_VE 0x1E0
	115	+#define EIC7700_REG_OFFSET_AON_DMA 0x1E4
	116	+#define EIC7700_REG_OFFSET_TIMER 0x1E8
	117	+#define EIC7700_REG_OFFSET_RTC 0x1EC
	118	+#define EIC7700_REG_OFFSET_PKA 0x1F0
	119	+#define EIC7700_REG_OFFSET_SPACC 0x1F4
	120	+#define EIC7700_REG_OFFSET_TRNG 0x1F8
	121	+#define EIC7700_REG_OFFSET_OTP 0x1FC
	122	+#define EIC7700_REG_OFFSET_LSP_EN0 0x200
	123	+#define EIC7700_REG_OFFSET_LSP_EN1 0x204
	124	+#define EIC7700_REG_OFFSET_U84 0x208
	125	+#define EIC7700_REG_OFFSET_SYSCFG 0x20C
	126	+#define EIC7700_REG_OFFSET_I2C0 0x210
	127	+#define EIC7700_REG_OFFSET_I2C1 0x214
	128	+
	129	+#define EIC7700_NR_CLKS (EIC7700_CLK_GATE_NOC_WDREF + 1)
	130	+
	131	+/*
	132	+ * The 24 MHz oscillator, the root of most of the clock tree.
	133	+ */
	134	+static const struct clk_parent_data xtal24M[] = {
	135	+ { .index = 0, }
	136	+};
	137	+
	138	+/* fixed rate clocks */
	139	+static struct eswin_fixed_rate_clock eic7700_fixed_rate_clks[] = {
	140	+ ESWIN_FIXED(EIC7700_CLK_XTAL_32K, "fixed_rate_clk_xtal_32k", 0, 32768),
	141	+ ESWIN_FIXED(EIC7700_CLK_SPLL0_FOUT1, "fixed_rate_clk_spll0_fout1", 0,
	142	+ 1600000000),
	143	+ ESWIN_FIXED(EIC7700_CLK_SPLL0_FOUT2, "fixed_rate_clk_spll0_fout2", 0,
	144	+ 800000000),
	145	+ ESWIN_FIXED(EIC7700_CLK_SPLL0_FOUT3, "fixed_rate_clk_spll0_fout3", 0,
	146	+ 400000000),
	147	+ ESWIN_FIXED(EIC7700_CLK_SPLL1_FOUT1, "fixed_rate_clk_spll1_fout1", 0,
	148	+ 1500000000),
	149	+ ESWIN_FIXED(EIC7700_CLK_SPLL1_FOUT2, "fixed_rate_clk_spll1_fout2", 0,
	150	+ 300000000),
	151	+ ESWIN_FIXED(EIC7700_CLK_SPLL1_FOUT3, "fixed_rate_clk_spll1_fout3", 0,
	152	+ 250000000),
	153	+ ESWIN_FIXED(EIC7700_CLK_SPLL2_FOUT1, "fixed_rate_clk_spll2_fout1", 0,
	154	+ 2080000000),
	155	+ ESWIN_FIXED(EIC7700_CLK_SPLL2_FOUT2, "fixed_rate_clk_spll2_fout2", 0,
	156	+ 1040000000),
	157	+ ESWIN_FIXED(EIC7700_CLK_SPLL2_FOUT3, "fixed_rate_clk_spll2_fout3", 0,
	158	+ 416000000),
	159	+ ESWIN_FIXED(EIC7700_CLK_VPLL_FOUT1, "fixed_rate_clk_vpll_fout1", 0,
	160	+ 1188000000),
	161	+ ESWIN_FIXED(EIC7700_CLK_VPLL_FOUT2, "fixed_rate_clk_vpll_fout2", 0,
	162	+ 594000000),
	163	+ ESWIN_FIXED(EIC7700_CLK_VPLL_FOUT3, "fixed_rate_clk_vpll_fout3", 0,
	164	+ 49500000),
	165	+ ESWIN_FIXED(EIC7700_CLK_APLL_FOUT2, "fixed_rate_clk_apll_fout2", 0, 0),
	166	+ ESWIN_FIXED(EIC7700_CLK_APLL_FOUT3, "fixed_rate_clk_apll_fout3", 0, 0),
	167	+ ESWIN_FIXED(EIC7700_CLK_EXT_MCLK, "fixed_rate_ext_mclk", 0, 0),
	168	+ ESWIN_FIXED(EIC7700_CLK_LPDDR_REF_BAK, "fixed_rate_lpddr_ref_bak", 0,
	169	+ 50000000),
	170	+};
	171	+
	172	+/* pll clocks */
	173	+static struct eswin_pll_clock eic7700_pll_clks[] = {
	174	+ ESWIN_PLL(EIC7700_CLK_APLL_FOUT1, "clk_apll_fout1", xtal24M,
	175	+ EIC7700_REG_OFFSET_APLL_CFG_0, 20,
	176	+ EIC7700_REG_OFFSET_APLL_CFG_1, 4,
	177	+ EIC7700_REG_OFFSET_APLL_CFG_2, EIC7700_REG_OFFSET_PLL_STATUS,
	178	+ 4, 1, APLL_HIGH_FREQ, APLL_LOW_FREQ),
	179	+ ESWIN_PLL(EIC7700_CLK_PLL_CPU, "clk_pll_cpu", xtal24M,
	180	+ EIC7700_REG_OFFSET_MCPUT_PLL_CFG_0, 20,
	181	+ EIC7700_REG_OFFSET_MCPUT_PLL_CFG_1, 4,
	182	+ EIC7700_REG_OFFSET_MCPUT_PLL_CFG_2,
	183	+ EIC7700_REG_OFFSET_PLL_STATUS, 5, 1, PLL_HIGH_FREQ,
	184	+ PLL_LOW_FREQ),
	185	+};
	186	+
	187	+/* fixed factor clocks */
	188	+static struct eswin_fixed_factor_clock eic7700_factor_clks[] = {
	189	+ ESWIN_FACTOR(EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24,
	190	+ "fixed_factor_clk_1m_div24", xtal24M, 1, 24, 0),
	191	+ ESWIN_FACTOR(EIC7700_CLK_FIXED_FACTOR_PVT_DIV20,
	192	+ "fixed_factor_pvt_div20", xtal24M, 1, 20, 0),
	193	+};
	194	+
	195	+/* divider clocks */
	196	+static struct eswin_divider_clock eic7700_div_clks[] = {
	197	+ ESWIN_DIV(EIC7700_CLK_DIV_U84_RTC_TOGGLE_DYNM,
	198	+ "divider_u84_rtc_toggle_dynm", xtal24M, 0,
	199	+ EIC7700_REG_OFFSET_RTC, 16, 5,
	200	+ CLK_DIVIDER_ONE_BASED \| CLK_DIVIDER_ALLOW_ZERO, 0),
	201	+ ESWIN_DIV(EIC7700_CLK_DIV_NOC_WDREF_DYNM, "divider_noc_wdref_dynm",
	202	+ xtal24M, 0, EIC7700_REG_OFFSET_NOC, 4, 16,
	203	+ CLK_DIVIDER_ONE_BASED \| CLK_DIVIDER_ALLOW_ZERO, 0),
	204	+};
	205	+
	206	+/* gate clocks */
	207	+static struct eswin_gate_clock eic7700_gate_clks[] = {
	208	+ ESWIN_GATE(EIC7700_CLK_GATE_GPU_GRAY_CLK, "gate_gpu_gray_clk", xtal24M,
	209	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_GPU_GRAY, 31, 0),
	210	+ ESWIN_GATE(EIC7700_CLK_GATE_VI_PHY_CFG, "gate_vi_phy_cfg", xtal24M,
	211	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_PHY, 1, 0),
	212	+ ESWIN_GATE(EIC7700_CLK_GATE_TIMER_CLK_0, "gate_time_clk_0", xtal24M,
	213	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 0, 0),
	214	+ ESWIN_GATE(EIC7700_CLK_GATE_TIMER_CLK_1, "gate_time_clk_1", xtal24M,
	215	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 1, 0),
	216	+ ESWIN_GATE(EIC7700_CLK_GATE_TIMER_CLK_2, "gate_time_clk_2", xtal24M,
	217	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 2, 0),
	218	+ ESWIN_GATE(EIC7700_CLK_GATE_TIMER_CLK_3, "gate_time_clk_3", xtal24M,
	219	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 3, 0),
	220	+};
	221	+
	222	+/* Define the early clocks as the parent clocks of the mux clocks. */
	223	+static struct eswin_clk_info eic7700_early_clks[] = {
	224	+ ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_HSP_RMII_REF_DIV6,
	225	+ "fixed_factor_hsp_rmii_ref_div6",
	226	+ EIC7700_CLK_SPLL1_FOUT2, 1, 6, 0),
	227	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_LLC_SRC0_DYNM,
	228	+ "divider_npu_llc_src0_div_dynm",
	229	+ EIC7700_CLK_SPLL0_FOUT1, 0, EIC7700_REG_OFFSET_NPU_LLC,
	230	+ 4, 4, 0, ESWIN_PRIV_DIV_MIN_2),
	231	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_LLC_SRC1_DYNM,
	232	+ "divider_npu_llc_src1_div_dynm",
	233	+ EIC7700_CLK_SPLL2_FOUT1, 0, EIC7700_REG_OFFSET_NPU_LLC,
	234	+ 8, 4, 0, ESWIN_PRIV_DIV_MIN_2),
	235	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_SPLL0_FOUT2, "gate_clk_spll0_fout2",
	236	+ EIC7700_CLK_SPLL0_FOUT2,
	237	+ CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	238	+ EIC7700_REG_OFFSET_SPLL0_CFG_2, 31, 0),
	239	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_BOOTSPI_DYNM, "divider_bootspi_div_dynm",
	240	+ EIC7700_CLK_GATE_SPLL0_FOUT2, 0,
	241	+ EIC7700_REG_OFFSET_BOOTSPI, 4, 6, 0,
	242	+ ESWIN_PRIV_DIV_MIN_2),
	243	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_SCPU_CORE_DYNM,
	244	+ "divider_scpu_core_div_dynm", EIC7700_CLK_SPLL0_FOUT1, 0,
	245	+ EIC7700_REG_OFFSET_SCPU_CORE, 4, 4, 0,
	246	+ ESWIN_PRIV_DIV_MIN_2),
	247	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_LPCPU_CORE_DYNM,
	248	+ "divider_lpcpu_core_div_dynm", EIC7700_CLK_SPLL0_FOUT1,
	249	+ 0, EIC7700_REG_OFFSET_LPCPU_CORE, 4, 4, 0,
	250	+ ESWIN_PRIV_DIV_MIN_2),
	251	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VO_MCLK_DYNM, "divider_vo_mclk_div_dynm",
	252	+ EIC7700_CLK_APLL_FOUT1, 0, EIC7700_REG_OFFSET_VO_MCLK, 4,
	253	+ 8, 0, ESWIN_PRIV_DIV_MIN_2),
	254	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_AONDMA_AXI_DYNM,
	255	+ "divider_aondma_axi_div_dynm", EIC7700_CLK_SPLL0_FOUT1,
	256	+ 0, EIC7700_REG_OFFSET_AON_DMA, 4, 4, 0,
	257	+ ESWIN_PRIV_DIV_MIN_2),
	258	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_SATA_PHY_REF_DYNM,
	259	+ "divider_sata_phy_ref_div_dynm",
	260	+ EIC7700_CLK_SPLL1_FOUT2, 0, EIC7700_REG_OFFSET_SATA_OOB,
	261	+ 0, 4, 0, ESWIN_PRIV_DIV_MIN_2),
	262	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_SYS_CFG_DYNM, "divider_sys_cfg_div_dynm",
	263	+ EIC7700_CLK_SPLL0_FOUT3, 0, EIC7700_REG_OFFSET_SYSCFG, 4,
	264	+ 3, 0, ESWIN_PRIV_DIV_MIN_2),
	265	+ ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_U84_CORE_LP_DIV2,
	266	+ "fixed_factor_u84_core_lp_div2",
	267	+ EIC7700_CLK_GATE_SPLL0_FOUT2, 1, 2, 0),
	268	+};
	269	+
	270	+static const struct clk_parent_data dsp_aclk_root_2mux1_gfree_mux_p[] = {
	271	+ { .hw = &eic7700_fixed_rate_clks[7].hw },
	272	+ { .hw = &eic7700_fixed_rate_clks[1].hw },
	273	+};
	274	+
	275	+static const struct clk_parent_data d2d_aclk_root_2mux1_gfree_mux_p[] = {
	276	+ { .hw = &eic7700_fixed_rate_clks[7].hw },
	277	+ { .hw = &eic7700_fixed_rate_clks[1].hw },
	278	+};
	279	+
	280	+static const struct clk_parent_data ddr_aclk_root_2mux1_gfree_mux_p[] = {
	281	+ { .hw = &eic7700_fixed_rate_clks[7].hw },
	282	+ { .hw = &eic7700_fixed_rate_clks[1].hw },
	283	+};
	284	+
	285	+static const struct clk_parent_data mshcore_root_3mux1_0_mux_p[] = {
	286	+ { .hw = &eic7700_fixed_rate_clks[3].hw },
	287	+ { .hw = &eic7700_fixed_rate_clks[9].hw },
	288	+};
	289	+
	290	+static const struct clk_parent_data mshcore_root_3mux1_1_mux_p[] = {
	291	+ { .hw = &eic7700_fixed_rate_clks[3].hw },
	292	+ { .hw = &eic7700_fixed_rate_clks[9].hw },
	293	+};
	294	+
	295	+static const struct clk_parent_data mshcore_root_3mux1_2_mux_p[] = {
	296	+ { .hw = &eic7700_fixed_rate_clks[3].hw },
	297	+ { .hw = &eic7700_fixed_rate_clks[9].hw },
	298	+};
	299	+
	300	+static const struct clk_parent_data npu_core_3mux1_gfree_mux_p[] = {
	301	+ { .hw = &eic7700_fixed_rate_clks[4].hw },
	302	+ { .hw = &eic7700_fixed_rate_clks[10].hw },
	303	+ { .hw = &eic7700_fixed_rate_clks[8].hw },
	304	+};
	305	+
	306	+static const struct clk_parent_data npu_e31_3mux1_gfree_mux_p[] = {
	307	+ { .hw = &eic7700_fixed_rate_clks[4].hw },
	308	+ { .hw = &eic7700_fixed_rate_clks[10].hw },
	309	+ { .hw = &eic7700_fixed_rate_clks[8].hw },
	310	+};
	311	+
	312	+static const struct clk_parent_data vi_aclk_root_2mux1_gfree_mux_p[] = {
	313	+ { .hw = &eic7700_fixed_rate_clks[1].hw },
	314	+ { .hw = &eic7700_fixed_rate_clks[7].hw },
	315	+};
	316	+
	317	+static const struct clk_parent_data mux_vi_dw_root_2mux1_p[] = {
	318	+ { .hw = &eic7700_fixed_rate_clks[10].hw },
	319	+ { .hw = &eic7700_fixed_rate_clks[1].hw },
	320	+};
	321	+
	322	+static const struct clk_parent_data mux_vi_dvp_root_2mux1_gfree_p[] = {
	323	+ { .hw = &eic7700_fixed_rate_clks[10].hw },
	324	+ { .hw = &eic7700_fixed_rate_clks[1].hw },
	325	+};
	326	+
	327	+static const struct clk_parent_data mux_vi_dig_isp_root_2mux1_gfree_p[] = {
	328	+ { .hw = &eic7700_fixed_rate_clks[10].hw },
	329	+ { .hw = &eic7700_fixed_rate_clks[1].hw },
	330	+};
	331	+
	332	+static const struct clk_parent_data mux_vo_aclk_root_2mux1_gfree_p[] = {
	333	+ { .hw = &eic7700_fixed_rate_clks[1].hw },
	334	+ { .hw = &eic7700_fixed_rate_clks[7].hw },
	335	+};
	336	+
	337	+static const struct clk_parent_data mux_vo_pixel_root_2mux1_p[] = {
	338	+ { .hw = &eic7700_fixed_rate_clks[10].hw },
	339	+ { .hw = &eic7700_fixed_rate_clks[8].hw },
	340	+};
	341	+
	342	+static const struct clk_parent_data mux_vcdec_root_2mux1_gfree_p[] = {
	343	+ { .hw = &eic7700_fixed_rate_clks[1].hw },
	344	+ { .hw = &eic7700_fixed_rate_clks[7].hw },
	345	+};
	346	+
	347	+static const struct clk_parent_data mux_vcaclk_root_2mux1_gfree_p[] = {
	348	+ { .hw = &eic7700_fixed_rate_clks[1].hw },
	349	+ { .hw = &eic7700_fixed_rate_clks[7].hw },
	350	+};
	351	+
	352	+static const struct clk_parent_data npu_llclk_3mux1_gfree_mux_p[] = {
	353	+ { .hw = &eic7700_early_clks[1].hw },
	354	+ { .hw = &eic7700_early_clks[2].hw },
	355	+ { .hw = &eic7700_fixed_rate_clks[10].hw },
	356	+};
	357	+
	358	+static const struct clk_parent_data mux_bootspi_clk_2mux1_gfree_p[] = {
	359	+ { .hw = &eic7700_early_clks[4].hw },
	360	+ { .index = 0 },
	361	+};
	362	+
	363	+static const struct clk_parent_data mux_scpu_core_clk_2mux1_gfree_p[] = {
	364	+ { .hw = &eic7700_early_clks[5].hw },
	365	+ { .index = 0 },
	366	+};
	367	+
	368	+static const struct clk_parent_data mux_lpcpu_core_clk_2mux1_gfree_p[] = {
	369	+ { .hw = &eic7700_early_clks[6].hw },
	370	+ { .index = 0 },
	371	+};
	372	+
	373	+static const struct clk_parent_data mux_vo_mclk_2mux_ext_mclk_p[] = {
	374	+ { .hw = &eic7700_early_clks[7].hw },
	375	+ { .hw = &eic7700_fixed_rate_clks[15].hw },
	376	+};
	377	+
	378	+static const struct clk_parent_data mux_aondma_axi2mux1_gfree_p[] = {
	379	+ { .hw = &eic7700_early_clks[8].hw },
	380	+ { .index = 0 },
	381	+};
	382	+
	383	+static const struct clk_parent_data mux_rmii_ref_2mux1_p[] = {
	384	+ { .hw = &eic7700_early_clks[0].hw },
	385	+ { .hw = &eic7700_fixed_rate_clks[16].hw },
	386	+};
	387	+
	388	+static const struct clk_parent_data mux_eth_core_2mux1_p[] = {
	389	+ { .hw = &eic7700_fixed_rate_clks[6].hw },
	390	+ { .hw = &eic7700_fixed_rate_clks[16].hw },
	391	+};
	392	+
	393	+static const struct clk_parent_data mux_sata_phy_2mux1_p[] = {
	394	+ { .hw = &eic7700_early_clks[9].hw },
	395	+ { .hw = &eic7700_fixed_rate_clks[16].hw },
	396	+};
	397	+
	398	+static const struct clk_parent_data mux_syscfg_clk_root_2mux1_gfree_p[] = {
	399	+ { .hw = &eic7700_early_clks[10].hw },
	400	+ { .index = 0 },
	401	+};
	402	+
	403	+static const struct clk_parent_data mux_cpu_root_3mux1_gfree_p[] = {
	404	+ { .hw = &eic7700_pll_clks[1].hw },
	405	+ { .hw = &eic7700_early_clks[11].hw },
	406	+ { .index = 0 },
	407	+};
	408	+
	409	+static struct eswin_mux_clock eic7700_mux_clks[] = {
	410	+ ESWIN_MUX(EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
	411	+ "mux_cpu_root_3mux1_gfree", mux_cpu_root_3mux1_gfree_p,
	412	+ ARRAY_SIZE(mux_cpu_root_3mux1_gfree_p),
	413	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 0, 2,
	414	+ CLK_MUX_ROUND_CLOSEST),
	415	+ ESWIN_MUX(EIC7700_CLK_MUX_RMII_REF_2MUX, "mux_rmii_ref_2mux1",
	416	+ mux_rmii_ref_2mux1_p, ARRAY_SIZE(mux_rmii_ref_2mux1_p),
	417	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_ETH0, 2, 1,
	418	+ CLK_MUX_ROUND_CLOSEST),
	419	+ ESWIN_MUX(EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE,
	420	+ "mux_dsp_aclk_root_2mux1_gfree",
	421	+ dsp_aclk_root_2mux1_gfree_mux_p,
	422	+ ARRAY_SIZE(dsp_aclk_root_2mux1_gfree_mux_p),
	423	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DSP_ACLK, 0, 1,
	424	+ CLK_MUX_ROUND_CLOSEST),
	425	+ ESWIN_MUX(EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE,
	426	+ "mux_d2d_aclk_root_2mux1_gfree",
	427	+ d2d_aclk_root_2mux1_gfree_mux_p,
	428	+ ARRAY_SIZE(d2d_aclk_root_2mux1_gfree_mux_p),
	429	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_D2D_ACLK, 0, 1,
	430	+ CLK_MUX_ROUND_CLOSEST),
	431	+ ESWIN_MUX(EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE,
	432	+ "mux_ddr_aclk_root_2mux1_gfree",
	433	+ ddr_aclk_root_2mux1_gfree_mux_p,
	434	+ ARRAY_SIZE(ddr_aclk_root_2mux1_gfree_mux_p),
	435	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DDR, 16, 1,
	436	+ CLK_MUX_ROUND_CLOSEST),
	437	+ ESWIN_MUX(EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0,
	438	+ "mux_mshcore_root_3mux1_0", mshcore_root_3mux1_0_mux_p,
	439	+ ARRAY_SIZE(mshcore_root_3mux1_0_mux_p), CLK_SET_RATE_PARENT,
	440	+ EIC7700_REG_OFFSET_MSHC0_CORE, 0, 1, CLK_MUX_ROUND_CLOSEST),
	441	+ ESWIN_MUX(EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1,
	442	+ "mux_mshcore_root_3mux1_1", mshcore_root_3mux1_1_mux_p,
	443	+ ARRAY_SIZE(mshcore_root_3mux1_1_mux_p), CLK_SET_RATE_PARENT,
	444	+ EIC7700_REG_OFFSET_MSHC1_CORE, 0, 1, CLK_MUX_ROUND_CLOSEST),
	445	+ ESWIN_MUX(EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2,
	446	+ "mux_mshcore_root_3mux1_2", mshcore_root_3mux1_2_mux_p,
	447	+ ARRAY_SIZE(mshcore_root_3mux1_2_mux_p), CLK_SET_RATE_PARENT,
	448	+ EIC7700_REG_OFFSET_MSHC2_CORE, 0, 1, CLK_MUX_ROUND_CLOSEST),
	449	+ ESWIN_MUX(EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE,
	450	+ "mux_npu_llclk_3mux1_gfree", npu_llclk_3mux1_gfree_mux_p,
	451	+ ARRAY_SIZE(npu_llclk_3mux1_gfree_mux_p),
	452	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_NPU_LLC, 0, 2,
	453	+ CLK_MUX_ROUND_CLOSEST),
	454	+ ESWIN_MUX(EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE,
	455	+ "mux_npu_core_3mux1_gfree", npu_core_3mux1_gfree_mux_p,
	456	+ ARRAY_SIZE(npu_core_3mux1_gfree_mux_p), CLK_SET_RATE_PARENT,
	457	+ EIC7700_REG_OFFSET_NPU_CORE, 0, 2, CLK_MUX_ROUND_CLOSEST),
	458	+ ESWIN_MUX(EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE,
	459	+ "mux_npu_e31_3mux1_gfree", npu_e31_3mux1_gfree_mux_p,
	460	+ ARRAY_SIZE(npu_e31_3mux1_gfree_mux_p), CLK_SET_RATE_PARENT,
	461	+ EIC7700_REG_OFFSET_NPU_CORE, 8, 2, CLK_MUX_ROUND_CLOSEST),
	462	+ ESWIN_MUX(EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE,
	463	+ "mux_vi_aclk_root_2mux1_gfree",
	464	+ vi_aclk_root_2mux1_gfree_mux_p,
	465	+ ARRAY_SIZE(vi_aclk_root_2mux1_gfree_mux_p),
	466	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_ACLK, 0, 1,
	467	+ CLK_MUX_ROUND_CLOSEST),
	468	+ ESWIN_MUX(EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1, "mux_vi_dw_root_2mux1",
	469	+ mux_vi_dw_root_2mux1_p, ARRAY_SIZE(mux_vi_dw_root_2mux1_p),
	470	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DWCLK, 0, 1,
	471	+ CLK_MUX_ROUND_CLOSEST),
	472	+ ESWIN_MUX(EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE,
	473	+ "mux_vi_dvp_root_2mux1_gfree",
	474	+ mux_vi_dvp_root_2mux1_gfree_p,
	475	+ ARRAY_SIZE(mux_vi_dvp_root_2mux1_gfree_p),
	476	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DVP, 0, 1,
	477	+ CLK_MUX_ROUND_CLOSEST),
	478	+ ESWIN_MUX(EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE,
	479	+ "mux_vi_dig_isp_root_2mux1_gfree",
	480	+ mux_vi_dig_isp_root_2mux1_gfree_p,
	481	+ ARRAY_SIZE(mux_vi_dig_isp_root_2mux1_gfree_p),
	482	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DIG_ISP, 0, 1,
	483	+ CLK_MUX_ROUND_CLOSEST),
	484	+ ESWIN_MUX(EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE,
	485	+ "mux_vo_aclk_root_2mux1_gfree",
	486	+ mux_vo_aclk_root_2mux1_gfree_p,
	487	+ ARRAY_SIZE(mux_vo_aclk_root_2mux1_gfree_p),
	488	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_ACLK, 0, 1,
	489	+ CLK_MUX_ROUND_CLOSEST),
	490	+ ESWIN_MUX(EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1,
	491	+ "mux_vo_pixel_root_2mux1", mux_vo_pixel_root_2mux1_p,
	492	+ ARRAY_SIZE(mux_vo_pixel_root_2mux1_p), CLK_SET_RATE_PARENT,
	493	+ EIC7700_REG_OFFSET_VO_PIXEL, 0, 1, CLK_MUX_ROUND_CLOSEST),
	494	+ ESWIN_MUX(EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE,
	495	+ "mux_vcdec_root_2mux1_gfree", mux_vcdec_root_2mux1_gfree_p,
	496	+ ARRAY_SIZE(mux_vcdec_root_2mux1_gfree_p),
	497	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VCDEC_ROOT, 0, 1,
	498	+ CLK_MUX_ROUND_CLOSEST),
	499	+ ESWIN_MUX(EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE,
	500	+ "mux_vcaclk_root_2mux1_gfree",
	501	+ mux_vcaclk_root_2mux1_gfree_p,
	502	+ ARRAY_SIZE(mux_vcaclk_root_2mux1_gfree_p),
	503	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_ACLK, 0, 1,
	504	+ CLK_MUX_ROUND_CLOSEST),
	505	+ ESWIN_MUX(EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	506	+ "mux_syscfg_clk_root_2mux1_gfree",
	507	+ mux_syscfg_clk_root_2mux1_gfree_p,
	508	+ ARRAY_SIZE(mux_syscfg_clk_root_2mux1_gfree_p),
	509	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SYSCFG, 0, 1,
	510	+ CLK_MUX_ROUND_CLOSEST),
	511	+ ESWIN_MUX(EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE,
	512	+ "mux_bootspi_clk_2mux1_gfree",
	513	+ mux_bootspi_clk_2mux1_gfree_p,
	514	+ ARRAY_SIZE(mux_bootspi_clk_2mux1_gfree_p),
	515	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_BOOTSPI, 0, 1,
	516	+ CLK_MUX_ROUND_CLOSEST),
	517	+ ESWIN_MUX(EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE,
	518	+ "mux_scpu_core_clk_2mux1_gfree",
	519	+ mux_scpu_core_clk_2mux1_gfree_p,
	520	+ ARRAY_SIZE(mux_scpu_core_clk_2mux1_gfree_p),
	521	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SCPU_CORE, 0, 1,
	522	+ CLK_MUX_ROUND_CLOSEST),
	523	+ ESWIN_MUX(EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE,
	524	+ "mux_lpcpu_core_clk_2mux1_gfree",
	525	+ mux_lpcpu_core_clk_2mux1_gfree_p,
	526	+ ARRAY_SIZE(mux_lpcpu_core_clk_2mux1_gfree_p),
	527	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LPCPU_CORE, 0, 1,
	528	+ CLK_MUX_ROUND_CLOSEST),
	529	+ ESWIN_MUX(EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK,
	530	+ "mux_vo_mclk_2mux_ext_mclk", mux_vo_mclk_2mux_ext_mclk_p,
	531	+ ARRAY_SIZE(mux_vo_mclk_2mux_ext_mclk_p),
	532	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_MCLK, 0, 1,
	533	+ CLK_MUX_ROUND_CLOSEST),
	534	+ ESWIN_MUX(EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE,
	535	+ "mux_aondma_axi2mux1_gfree", mux_aondma_axi2mux1_gfree_p,
	536	+ ARRAY_SIZE(mux_aondma_axi2mux1_gfree_p),
	537	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA, 0, 1,
	538	+ CLK_MUX_ROUND_CLOSEST),
	539	+ ESWIN_MUX(EIC7700_CLK_MUX_ETH_CORE_2MUX1, "mux_eth_core_2mux1",
	540	+ mux_eth_core_2mux1_p, ARRAY_SIZE(mux_eth_core_2mux1_p),
	541	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_ETH0, 1, 1,
	542	+ CLK_MUX_ROUND_CLOSEST),
	543	+ ESWIN_MUX(EIC7700_CLK_MUX_SATA_PHY_2MUX1, "mux_sata_phy_2mux1",
	544	+ mux_sata_phy_2mux1_p, ARRAY_SIZE(mux_sata_phy_2mux1_p),
	545	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SATA_OOB, 9, 1,
	546	+ CLK_MUX_ROUND_CLOSEST),
	547	+};
	548	+
	549	+static const struct clk_parent_data mux_cpu_aclk_2mux1_gfree_p[] = {
	550	+ { .hw = &eic7700_mux_clks[1].hw },
	551	+ { .hw = &eic7700_mux_clks[0].hw },
	552	+};
	553	+
	554	+static struct eswin_clk_info eic7700_clks[] = {
	555	+ ESWIN_MUX_TYPE(EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE,
	556	+ "mux_cpu_aclk_2mux1_gfree", mux_cpu_aclk_2mux1_gfree_p,
	557	+ ARRAY_SIZE(mux_cpu_aclk_2mux1_gfree_p),
	558	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 20, 1,
	559	+ CLK_MUX_ROUND_CLOSEST, NULL),
	560	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_COM_CLK,
	561	+ "gate_clk_cpu_trace_com_clk",
	562	+ EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE,
	563	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 23, 0),
	564	+ ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_CPU_DIV2,
	565	+ "fixed_factor_cpu_div2",
	566	+ EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, 1, 2, 0),
	567	+ ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10,
	568	+ "fixed_factor_mipi_txesc_div10",
	569	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1, 10,
	570	+ 0),
	571	+ ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2,
	572	+ "fixed_factor_scpu_bus_div2",
	573	+ EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE, 1, 2, 0),
	574	+ ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2,
	575	+ "fixed_factor_lpcpu_bus_div2",
	576	+ EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE, 1, 2, 0),
	577	+ ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2,
	578	+ "fixed_factor_pcie_cr_div2",
	579	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1, 2, 0),
	580	+ ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4,
	581	+ "fixed_factor_pcie_aux_div4",
	582	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1, 4, 0),
	583	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_D2D_ACLK_DYNM,
	584	+ "divider_d2d_aclk_div_dynm",
	585	+ EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE, 0,
	586	+ EIC7700_REG_OFFSET_D2D_ACLK, 4, 4, 0,
	587	+ ESWIN_PRIV_DIV_MIN_2),
	588	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_ACLK_DYNM,
	589	+ "divider_dsp_aclk_div_dynm",
	590	+ EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE, 0,
	591	+ EIC7700_REG_OFFSET_DSP_ACLK, 4, 4, 0,
	592	+ ESWIN_PRIV_DIV_MIN_2),
	593	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DDR_ACLK_DYNM,
	594	+ "divider_ddr_aclk_div_dynm",
	595	+ EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE, 0,
	596	+ EIC7700_REG_OFFSET_DDR, 20, 4, 0, ESWIN_PRIV_DIV_MIN_2),
	597	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0,
	598	+ "divider_eth_txclk_div_dynm_0",
	599	+ EIC7700_CLK_MUX_ETH_CORE_2MUX1, 0,
	600	+ EIC7700_REG_OFFSET_ETH0, 4, 7, 0, ESWIN_PRIV_DIV_MIN_2),
	601	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1,
	602	+ "divider_eth_txclk_div_dynm_1",
	603	+ EIC7700_CLK_MUX_ETH_CORE_2MUX1, 0,
	604	+ EIC7700_REG_OFFSET_ETH1, 4, 7, 0, ESWIN_PRIV_DIV_MIN_2),
	605	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_MSHC_CORE_DYNM_0,
	606	+ "divider_mshc_core_div_dynm_0",
	607	+ EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0,
	608	+ 0, EIC7700_REG_OFFSET_MSHC0_CORE, 4, 12,
	609	+ CLK_DIVIDER_ONE_BASED \| CLK_DIVIDER_ALLOW_ZERO, 0),
	610	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_MSHC_CORE_DYNM_1,
	611	+ "divider_mshc_core_div_dynm_1",
	612	+ EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1,
	613	+ 0, EIC7700_REG_OFFSET_MSHC1_CORE, 4, 12,
	614	+ CLK_DIVIDER_ONE_BASED \| CLK_DIVIDER_ALLOW_ZERO, 0),
	615	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_MSHC_CORE_DYNM_2,
	616	+ "divider_mshc_core_div_dynm_2",
	617	+ EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2,
	618	+ 0, EIC7700_REG_OFFSET_MSHC2_CORE, 4, 12,
	619	+ CLK_DIVIDER_ONE_BASED \| CLK_DIVIDER_ALLOW_ZERO, 0),
	620	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_CORECLK_DYNM,
	621	+ "divider_npu_coreclk_div_dynm",
	622	+ EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE,
	623	+ 0, EIC7700_REG_OFFSET_NPU_CORE, 4, 4,
	624	+ CLK_DIVIDER_ONE_BASED \| CLK_DIVIDER_ALLOW_ZERO, 0),
	625	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_E31_DYNM, "divider_npu_e31_div_dynm",
	626	+ EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE, 0,
	627	+ EIC7700_REG_OFFSET_NPU_CORE, 12, 4,
	628	+ CLK_DIVIDER_ONE_BASED \| CLK_DIVIDER_ALLOW_ZERO, 0),
	629	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_ACLK_DYNM, "divider_vi_aclk_div_dynm",
	630	+ EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE, 0,
	631	+ EIC7700_REG_OFFSET_VI_ACLK, 4, 4, 0,
	632	+ ESWIN_PRIV_DIV_MIN_2),
	633	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_DW_DYNM, "divider_vi_dw_div_dynm",
	634	+ EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1, 0,
	635	+ EIC7700_REG_OFFSET_VI_DWCLK, 4, 4, 0,
	636	+ ESWIN_PRIV_DIV_MIN_2),
	637	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_DVP_DYNM, "divider_vi_dvp_div_dynm",
	638	+ EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE, 0,
	639	+ EIC7700_REG_OFFSET_VI_DVP, 4, 4, 0,
	640	+ ESWIN_PRIV_DIV_MIN_2),
	641	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_DIG_ISP_DYNM,
	642	+ "divider_vi_dig_isp_div_dynm",
	643	+ EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE, 0,
	644	+ EIC7700_REG_OFFSET_VI_DIG_ISP, 4, 4, 0,
	645	+ ESWIN_PRIV_DIV_MIN_2),
	646	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VO_ACLK_DYNM, "divider_vo_aclk_div_dynm",
	647	+ EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE, 0,
	648	+ EIC7700_REG_OFFSET_VO_ACLK, 4, 4, 0,
	649	+ ESWIN_PRIV_DIV_MIN_2),
	650	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VO_PIXEL_DYNM,
	651	+ "divider_vo_pixel_div_dynm",
	652	+ EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1, 0,
	653	+ EIC7700_REG_OFFSET_VO_PIXEL, 4, 6, 0,
	654	+ ESWIN_PRIV_DIV_MIN_2),
	655	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VC_ACLK_DYNM, "divider_vc_aclk_div_dynm",
	656	+ EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE, 0,
	657	+ EIC7700_REG_OFFSET_VC_ACLK, 4, 4, 0,
	658	+ ESWIN_PRIV_DIV_MIN_2),
	659	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_JD_DYNM, "divider_jd_div_dynm",
	660	+ EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, 0,
	661	+ EIC7700_REG_OFFSET_JD, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2),
	662	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_JE_DYNM, "divider_je_div_dynm",
	663	+ EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, 0,
	664	+ EIC7700_REG_OFFSET_JE, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2),
	665	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VE_DYNM, "divider_ve_div_dynm",
	666	+ EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, 0,
	667	+ EIC7700_REG_OFFSET_VE, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2),
	668	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VD_DYNM, "divider_vd_div_dynm",
	669	+ EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, 0,
	670	+ EIC7700_REG_OFFSET_VD, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2),
	671	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_G2D_DYNM, "divider_g2d_div_dynm",
	672	+ EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE, 0,
	673	+ EIC7700_REG_OFFSET_G2D, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2),
	674	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NOC_NSP_DYNM, "divider_noc_nsp_div_dynm",
	675	+ EIC7700_CLK_SPLL2_FOUT1, 0, EIC7700_REG_OFFSET_NOC, 0, 3,
	676	+ 0, ESWIN_PRIV_DIV_MIN_2),
	677	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_GPU_ACLK_DYNM,
	678	+ "divider_gpu_aclk_div_dynm", EIC7700_CLK_SPLL0_FOUT1, 0,
	679	+ EIC7700_REG_OFFSET_GPU_ACLK, 4, 4, 0,
	680	+ ESWIN_PRIV_DIV_MIN_2),
	681	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_HSP_ACLK_DYNM,
	682	+ "divider_hsp_aclk_div_dynm", EIC7700_CLK_SPLL0_FOUT1, 0,
	683	+ EIC7700_REG_OFFSET_HSP_ACLK, 4, 4, 0,
	684	+ ESWIN_PRIV_DIV_MIN_2),
	685	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_PCIE_ACLK_DYNM,
	686	+ "divider_pcie_aclk_div_dynm", EIC7700_CLK_SPLL2_FOUT2, 0,
	687	+ EIC7700_REG_OFFSET_PCIE_ACLK, 4, 4, 0,
	688	+ ESWIN_PRIV_DIV_MIN_2),
	689	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_ACLK_DYNM,
	690	+ "divider_npu_aclk_div_dynm", EIC7700_CLK_SPLL0_FOUT1, 0,
	691	+ EIC7700_REG_OFFSET_NPU_ACLK, 4, 4, 0,
	692	+ ESWIN_PRIV_DIV_MIN_2),
	693	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0,
	694	+ "divider_vi_shutter_div_dynm_0",
	695	+ EIC7700_CLK_VPLL_FOUT2, 0,
	696	+ EIC7700_REG_OFFSET_VI_SHUTTER0, 4, 7, 0,
	697	+ ESWIN_PRIV_DIV_MIN_2),
	698	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1,
	699	+ "divider_vi_shutter_div_dynm_1",
	700	+ EIC7700_CLK_VPLL_FOUT2, 0,
	701	+ EIC7700_REG_OFFSET_VI_SHUTTER1, 4, 7, 0,
	702	+ ESWIN_PRIV_DIV_MIN_2),
	703	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2,
	704	+ "divider_vi_shutter_div_dynm_2",
	705	+ EIC7700_CLK_VPLL_FOUT2, 0,
	706	+ EIC7700_REG_OFFSET_VI_SHUTTER2, 4, 7, 0,
	707	+ ESWIN_PRIV_DIV_MIN_2),
	708	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3,
	709	+ "divider_vi_shutter_div_dynm_3",
	710	+ EIC7700_CLK_VPLL_FOUT2, 0,
	711	+ EIC7700_REG_OFFSET_VI_SHUTTER3, 4, 7, 0,
	712	+ ESWIN_PRIV_DIV_MIN_2),
	713	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4,
	714	+ "divider_vi_shutter_div_dynm_4",
	715	+ EIC7700_CLK_VPLL_FOUT2, 0,
	716	+ EIC7700_REG_OFFSET_VI_SHUTTER4, 4, 7, 0,
	717	+ ESWIN_PRIV_DIV_MIN_2),
	718	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5,
	719	+ "divider_vi_shutter_div_dynm_5",
	720	+ EIC7700_CLK_VPLL_FOUT2, 0,
	721	+ EIC7700_REG_OFFSET_VI_SHUTTER5, 4, 7, 0,
	722	+ ESWIN_PRIV_DIV_MIN_2),
	723	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_IESMCLK_DYNM, "divider_iesmclk_div_dynm",
	724	+ EIC7700_CLK_SPLL0_FOUT3, 0,
	725	+ EIC7700_REG_OFFSET_VO_IESMCLK, 4, 4, 0,
	726	+ ESWIN_PRIV_DIV_MIN_2),
	727	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VO_CEC_DYNM, "divider_vo_cec_div_dynm",
	728	+ EIC7700_CLK_VPLL_FOUT2, 0,
	729	+ EIC7700_REG_OFFSET_VO_PHY_CLK, 16, 16, 0,
	730	+ ESWIN_PRIV_DIV_MIN_2),
	731	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_CRYPTO_DYNM, "divider_crypto_div_dynm",
	732	+ EIC7700_CLK_SPLL0_FOUT1, 0,
	733	+ EIC7700_REG_OFFSET_SPACC, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2),
	734	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_AON_RTC_DYNM, "divider_aon_rtc_div_dynm",
	735	+ EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24, 0,
	736	+ EIC7700_REG_OFFSET_RTC, 21, 11, 0,
	737	+ ESWIN_PRIV_DIV_MIN_2),
	738	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DSPT_ACLK, "gate_dspt_aclk",
	739	+ EIC7700_CLK_DIV_DSP_ACLK_DYNM, CLK_SET_RATE_PARENT,
	740	+ EIC7700_REG_OFFSET_DSP_ACLK, 31, 0),
	741	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_0_ACLK_DYNM,
	742	+ "divider_dsp_0_aclk_div_dynm",
	743	+ EIC7700_CLK_GATE_DSPT_ACLK, 0,
	744	+ EIC7700_REG_OFFSET_DSP_CFG, 19, 1, 0, 0),
	745	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_1_ACLK_DYNM,
	746	+ "divider_dsp_1_aclk_div_dynm",
	747	+ EIC7700_CLK_GATE_DSPT_ACLK, 0,
	748	+ EIC7700_REG_OFFSET_DSP_CFG, 20, 1, 0, 0),
	749	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_2_ACLK_DYNM,
	750	+ "divider_dsp_2_aclk_div_dynm",
	751	+ EIC7700_CLK_GATE_DSPT_ACLK, 0,
	752	+ EIC7700_REG_OFFSET_DSP_CFG, 21, 1, 0, 0),
	753	+ ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_3_ACLK_DYNM,
	754	+ "divider_dsp_3_aclk_div_dynm",
	755	+ EIC7700_CLK_GATE_DSPT_ACLK, 0,
	756	+ EIC7700_REG_OFFSET_DSP_CFG, 22, 1, 0, 0),
	757	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_0,
	758	+ "gate_clk_cpu_ext_src_core_clk_0",
	759	+ EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
	760	+ CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	761	+ EIC7700_REG_OFFSET_U84, 28, 0),
	762	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_1,
	763	+ "gate_clk_cpu_ext_src_core_clk_1",
	764	+ EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
	765	+ CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	766	+ EIC7700_REG_OFFSET_U84, 29, 0),
	767	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_2,
	768	+ "gate_clk_cpu_ext_src_core_clk_2",
	769	+ EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
	770	+ CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	771	+ EIC7700_REG_OFFSET_U84, 30, 0),
	772	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_3,
	773	+ "gate_clk_cpu_ext_src_core_clk_3",
	774	+ EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
	775	+ CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	776	+ EIC7700_REG_OFFSET_U84, 31, 0),
	777	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_CLK_0,
	778	+ "gate_clk_cpu_trace_clk_0",
	779	+ EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
	780	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 24, 0),
	781	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_CLK_1,
	782	+ "gate_clk_cpu_trace_clk_1",
	783	+ EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
	784	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 25, 0),
	785	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_CLK_2,
	786	+ "gate_clk_cpu_trace_clk_2",
	787	+ EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
	788	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 26, 0),
	789	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_CLK_3,
	790	+ "gate_clk_cpu_trace_clk_3",
	791	+ EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE,
	792	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 27, 0),
	793	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NOC_NSP_CLK, "gate_noc_nsp_clk",
	794	+ EIC7700_CLK_DIV_NOC_NSP_DYNM, CLK_SET_RATE_PARENT,
	795	+ EIC7700_REG_OFFSET_NOC, 31, 0),
	796	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_BOOTSPI, "gate_clk_bootspi",
	797	+ EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE,
	798	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_BOOTSPI, 31, 0),
	799	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_BOOTSPI_CFG, "gate_clk_bootspi_cfg",
	800	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	801	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_BOOTSPI_CFGCLK,
	802	+ 31, 0),
	803	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_SCPU_CORE, "gate_clk_scpu_core",
	804	+ EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE,
	805	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SCPU_CORE, 31,
	806	+ 0),
	807	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_SCPU_BUS, "gate_clk_scpu_bus",
	808	+ EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2,
	809	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SCPU_BUSCLK, 31,
	810	+ 0),
	811	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LPCPU_CORE, "gate_clk_lpcpu_core",
	812	+ EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE,
	813	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LPCPU_CORE, 31,
	814	+ 0),
	815	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LPCPU_BUS, "gate_clk_lpcpu_bus",
	816	+ EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2,
	817	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LPCPU_BUSCLK,
	818	+ 31, 0),
	819	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_GPU_ACLK, "gate_gpu_aclk",
	820	+ EIC7700_CLK_DIV_GPU_ACLK_DYNM, CLK_SET_RATE_PARENT,
	821	+ EIC7700_REG_OFFSET_GPU_ACLK, 31, 0),
	822	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_GPU_CFG_CLK, "gate_gpu_cfg_clk",
	823	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	824	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_GPU_CFG, 31, 0),
	825	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DSPT_CFG_CLK, "gate_dspt_cfg_clk",
	826	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	827	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DSP_CFG, 31, 0),
	828	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_D2D_ACLK, "gate_d2d_aclk",
	829	+ EIC7700_CLK_DIV_D2D_ACLK_DYNM, CLK_SET_RATE_PARENT,
	830	+ EIC7700_REG_OFFSET_D2D_ACLK, 31, 0),
	831	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_D2D_CFG_CLK, "gate_d2d_cfg_clk",
	832	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	833	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_D2D_CFG, 31, 0),
	834	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TCU_ACLK, "gate_tcu_aclk",
	835	+ EIC7700_CLK_DIV_DDR_ACLK_DYNM, CLK_SET_RATE_PARENT,
	836	+ EIC7700_REG_OFFSET_TCU_ACLK, 31, 0),
	837	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TCU_CFG_CLK, "gate_tcu_cfg_clk",
	838	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	839	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TCU_CFG, 31, 0),
	840	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT_CFG_CLK, "gate_ddrt_cfg_clk",
	841	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	842	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DDR, 9, 0),
	843	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P0_ACLK, "gate_ddrt0_p0_aclk",
	844	+ EIC7700_CLK_DIV_DDR_ACLK_DYNM,
	845	+ CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	846	+ EIC7700_REG_OFFSET_DDR, 4, 0),
	847	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P1_ACLK, "gate_ddrt0_p1_aclk",
	848	+ EIC7700_CLK_DIV_DDR_ACLK_DYNM,
	849	+ CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	850	+ EIC7700_REG_OFFSET_DDR, 5, 0),
	851	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P2_ACLK, "gate_ddrt0_p2_aclk",
	852	+ EIC7700_CLK_DIV_DDR_ACLK_DYNM,
	853	+ CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	854	+ EIC7700_REG_OFFSET_DDR, 6, 0),
	855	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P3_ACLK, "gate_ddrt0_p3_aclk",
	856	+ EIC7700_CLK_DIV_DDR_ACLK_DYNM,
	857	+ CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	858	+ EIC7700_REG_OFFSET_DDR, 7, 0),
	859	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P4_ACLK, "gate_ddrt0_p4_aclk",
	860	+ EIC7700_CLK_DIV_DDR_ACLK_DYNM,
	861	+ CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	862	+ EIC7700_REG_OFFSET_DDR, 8, 0),
	863	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P0_ACLK, "gate_ddrt1_p0_aclk",
	864	+ EIC7700_CLK_DIV_DDR_ACLK_DYNM,
	865	+ CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	866	+ EIC7700_REG_OFFSET_DDR1, 4, 0),
	867	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P1_ACLK, "gate_ddrt1_p1_aclk",
	868	+ EIC7700_CLK_DIV_DDR_ACLK_DYNM,
	869	+ CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	870	+ EIC7700_REG_OFFSET_DDR1, 5, 0),
	871	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P2_ACLK, "gate_ddrt1_p2_aclk",
	872	+ EIC7700_CLK_DIV_DDR_ACLK_DYNM,
	873	+ CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	874	+ EIC7700_REG_OFFSET_DDR1, 6, 0),
	875	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P3_ACLK, "gate_ddrt1_p3_aclk",
	876	+ EIC7700_CLK_DIV_DDR_ACLK_DYNM,
	877	+ CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	878	+ EIC7700_REG_OFFSET_DDR1, 7, 0),
	879	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P4_ACLK, "gate_ddrt1_p4_aclk",
	880	+ EIC7700_CLK_DIV_DDR_ACLK_DYNM,
	881	+ CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	882	+ EIC7700_REG_OFFSET_DDR1, 8, 0),
	883	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_ACLK, "gate_clk_hsp_aclk",
	884	+ EIC7700_CLK_DIV_HSP_ACLK_DYNM, CLK_SET_RATE_PARENT,
	885	+ EIC7700_REG_OFFSET_HSP_ACLK, 31, 0),
	886	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_CFG_CLK, "gate_clk_hsp_cfg_clk",
	887	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	888	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_HSP_CFG, 31, 0),
	889	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PCIET_ACLK, "gate_pciet_aclk",
	890	+ EIC7700_CLK_DIV_PCIE_ACLK_DYNM, CLK_SET_RATE_PARENT,
	891	+ EIC7700_REG_OFFSET_PCIE_ACLK, 31, 0),
	892	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PCIET_CFG_CLK, "gate_pciet_cfg_clk",
	893	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	894	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_PCIE_CFG, 31,
	895	+ 0),
	896	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PCIET_CR_CLK, "gate_pciet_cr_clk",
	897	+ EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2,
	898	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_PCIE_CFG, 0, 0),
	899	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PCIET_AUX_CLK, "gate_pciet_aux_clk",
	900	+ EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4,
	901	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_PCIE_CFG, 1, 0),
	902	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_ACLK, "gate_npu_aclk",
	903	+ EIC7700_CLK_DIV_NPU_ACLK_DYNM, CLK_SET_RATE_PARENT,
	904	+ EIC7700_REG_OFFSET_NPU_ACLK, 31, 0),
	905	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_CFG_CLK, "gate_npu_cfg_clk",
	906	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	907	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_NPU_ACLK, 30,
	908	+ 0),
	909	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_LLC_ACLK, "gate_npu_llc_aclk",
	910	+ EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE,
	911	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_NPU_LLC, 31, 0),
	912	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_CLK, "gate_npu_clk",
	913	+ EIC7700_CLK_DIV_NPU_CORECLK_DYNM, CLK_SET_RATE_PARENT,
	914	+ EIC7700_REG_OFFSET_NPU_CORE, 31, 0),
	915	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_E31_CLK, "gate_npu_e31_clk",
	916	+ EIC7700_CLK_DIV_NPU_E31_DYNM, CLK_SET_RATE_PARENT,
	917	+ EIC7700_REG_OFFSET_NPU_CORE, 30, 0),
	918	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_ACLK, "gate_vi_aclk",
	919	+ EIC7700_CLK_DIV_VI_ACLK_DYNM, CLK_SET_RATE_PARENT,
	920	+ EIC7700_REG_OFFSET_VI_ACLK, 31, 0),
	921	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_CFG_CLK, "gate_vi_cfg_clk",
	922	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	923	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_ACLK, 30, 0),
	924	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_DIG_DW_CLK, "gate_vi_dig_dw_clk",
	925	+ EIC7700_CLK_DIV_VI_DW_DYNM, CLK_SET_RATE_PARENT,
	926	+ EIC7700_REG_OFFSET_VI_DWCLK, 31, 0),
	927	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_DVP_CLK, "gate_vi_dvp_clk",
	928	+ EIC7700_CLK_DIV_VI_DVP_DYNM, CLK_SET_RATE_PARENT,
	929	+ EIC7700_REG_OFFSET_VI_DVP, 31, 0),
	930	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_DIG_ISP_CLK, "gate_vi_dig_isp_clk",
	931	+ EIC7700_CLK_DIV_VI_DIG_ISP_DYNM, CLK_SET_RATE_PARENT,
	932	+ EIC7700_REG_OFFSET_VI_DIG_ISP, 31, 0),
	933	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_0, "gate_vi_shutter_0",
	934	+ EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0, CLK_SET_RATE_PARENT,
	935	+ EIC7700_REG_OFFSET_VI_SHUTTER0, 31, 0),
	936	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_1, "gate_vi_shutter_1",
	937	+ EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1, CLK_SET_RATE_PARENT,
	938	+ EIC7700_REG_OFFSET_VI_SHUTTER1, 31, 0),
	939	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_2, "gate_vi_shutter_2",
	940	+ EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2, CLK_SET_RATE_PARENT,
	941	+ EIC7700_REG_OFFSET_VI_SHUTTER2, 31, 0),
	942	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_3, "gate_vi_shutter_3",
	943	+ EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3, CLK_SET_RATE_PARENT,
	944	+ EIC7700_REG_OFFSET_VI_SHUTTER3, 31, 0),
	945	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_4, "gate_vi_shutter_4",
	946	+ EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4, CLK_SET_RATE_PARENT,
	947	+ EIC7700_REG_OFFSET_VI_SHUTTER4, 31, 0),
	948	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_5, "gate_vi_shutter_5",
	949	+ EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5, CLK_SET_RATE_PARENT,
	950	+ EIC7700_REG_OFFSET_VI_SHUTTER5, 31, 0),
	951	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_PHY_TXCLKESC,
	952	+ "gate_vi_phy_txclkesc",
	953	+ EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10,
	954	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_PHY, 0, 0),
	955	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_ACLK, "gate_vo_aclk",
	956	+ EIC7700_CLK_DIV_VO_ACLK_DYNM, CLK_SET_RATE_PARENT,
	957	+ EIC7700_REG_OFFSET_VO_ACLK, 31, 0),
	958	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_CFG_CLK, "gate_vo_cfg_clk",
	959	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	960	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_ACLK, 30, 0),
	961	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_HDMI_IESMCLK,
	962	+ "gate_vo_hdmi_iesmclk", EIC7700_CLK_DIV_IESMCLK_DYNM,
	963	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_IESMCLK, 31,
	964	+ 0),
	965	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_PIXEL_CLK, "gate_vo_pixel_clk",
	966	+ EIC7700_CLK_DIV_VO_PIXEL_DYNM, CLK_SET_RATE_PARENT,
	967	+ EIC7700_REG_OFFSET_VO_PIXEL, 31, 0),
	968	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_I2S_MCLK, "gate_vo_i2s_mclk",
	969	+ EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK,
	970	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_MCLK, 31, 0),
	971	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_CR_CLK, "gate_vo_cr_clk",
	972	+ EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10,
	973	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_PHY_CLK, 1,
	974	+ 0),
	975	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_ACLK, "gate_vc_aclk",
	976	+ EIC7700_CLK_DIV_VC_ACLK_DYNM, CLK_SET_RATE_PARENT,
	977	+ EIC7700_REG_OFFSET_VC_ACLK, 31, 0),
	978	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_CFG_CLK, "gate_vc_cfg_clk",
	979	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	980	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 0, 0),
	981	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_JE_CLK, "gate_vc_je_clk",
	982	+ EIC7700_CLK_DIV_JE_DYNM, CLK_SET_RATE_PARENT,
	983	+ EIC7700_REG_OFFSET_JE, 31, 0),
	984	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_JD_CLK, "gate_vc_jd_clk",
	985	+ EIC7700_CLK_DIV_JD_DYNM, CLK_SET_RATE_PARENT,
	986	+ EIC7700_REG_OFFSET_JD, 31, 0),
	987	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_VE_CLK, "gate_vc_ve_clk",
	988	+ EIC7700_CLK_DIV_VE_DYNM, CLK_SET_RATE_PARENT,
	989	+ EIC7700_REG_OFFSET_VE, 31, 0),
	990	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_VD_CLK, "gate_vc_vd_clk",
	991	+ EIC7700_CLK_DIV_VD_DYNM, CLK_SET_RATE_PARENT,
	992	+ EIC7700_REG_OFFSET_VD, 31, 0),
	993	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_G2D_CFG_CLK, "gate_g2d_cfg_clk",
	994	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	995	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_G2D, 28, 0),
	996	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_G2D_CLK, "gate_g2d_clk",
	997	+ EIC7700_CLK_DIV_G2D_DYNM, CLK_SET_RATE_PARENT,
	998	+ EIC7700_REG_OFFSET_G2D, 30, 0),
	999	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_G2D_ACLK, "gate_g2d_aclk",
	1000	+ EIC7700_CLK_DIV_G2D_DYNM, CLK_SET_RATE_PARENT,
	1001	+ EIC7700_REG_OFFSET_G2D, 31, 0),
	1002	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AONDMA_CFG, "gate_clk_aondma_cfg",
	1003	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1004	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA, 30, 0),
	1005	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AONDMA_ACLK, "gate_aondma_aclk",
	1006	+ EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE,
	1007	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA, 31, 0),
	1008	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AON_ACLK, "gate_aon_aclk",
	1009	+ EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE,
	1010	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA, 29, 0),
	1011	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER_PCLK_0, "gate_timer_pclk_0",
	1012	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1013	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 4, 0),
	1014	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER_PCLK_1, "gate_timer_pclk_1",
	1015	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1016	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 5, 0),
	1017	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER_PCLK_2, "gate_timer_pclk_2",
	1018	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1019	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 6, 0),
	1020	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER_PCLK_3, "gate_timer_pclk_3",
	1021	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1022	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 7, 0),
	1023	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER3_CLK8, "gate_timer3_clk8",
	1024	+ EIC7700_CLK_VPLL_FOUT3, CLK_SET_RATE_PARENT,
	1025	+ EIC7700_REG_OFFSET_TIMER, 8, 0),
	1026	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_RTC_CFG, "gate_clk_rtc_cfg",
	1027	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1028	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_RTC, 2, 0),
	1029	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_RTC, "gate_clk_rtc",
	1030	+ EIC7700_CLK_DIV_AON_RTC_DYNM, CLK_SET_RATE_PARENT,
	1031	+ EIC7700_REG_OFFSET_RTC, 1, 0),
	1032	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_RMII_REF_0, "gate_hsp_rmii_ref_0",
	1033	+ EIC7700_CLK_MUX_RMII_REF_2MUX, CLK_SET_RATE_PARENT,
	1034	+ EIC7700_REG_OFFSET_ETH0, 31, 0),
	1035	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_RMII_REF_1, "gate_hsp_rmii_ref_1",
	1036	+ EIC7700_CLK_MUX_RMII_REF_2MUX, CLK_SET_RATE_PARENT,
	1037	+ EIC7700_REG_OFFSET_ETH1, 31, 0),
	1038	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PKA_CFG, "gate_clk_pka_cfg",
	1039	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1040	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_PKA, 31, 0),
	1041	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_SPACC_CFG, "gate_clk_spacc_cfg",
	1042	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1043	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SPACC, 31, 0),
	1044	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CRYPTO, "gate_clk_crypto",
	1045	+ EIC7700_CLK_DIV_CRYPTO_DYNM, CLK_SET_RATE_PARENT,
	1046	+ EIC7700_REG_OFFSET_SPACC, 30, 0),
	1047	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TRNG_CFG, "gate_clk_trng_cfg",
	1048	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1049	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TRNG, 31, 0),
	1050	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_OTP_CFG, "gate_clk_otp_cfg",
	1051	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1052	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_OTP, 31, 0),
	1053	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_0, "gate_clk_mailbox_0",
	1054	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1055	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 0, 0),
	1056	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_1, "gate_clk_mailbox_1",
	1057	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1058	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 1, 0),
	1059	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_2, "gate_clk_mailbox_2",
	1060	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1061	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 2, 0),
	1062	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_3, "gate_clk_mailbox_3",
	1063	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1064	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 3, 0),
	1065	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_4, "gate_clk_mailbox_4",
	1066	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1067	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 4, 0),
	1068	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_5, "gate_clk_mailbox_5",
	1069	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1070	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 5, 0),
	1071	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_6, "gate_clk_mailbox_6",
	1072	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1073	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 6, 0),
	1074	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_7, "gate_clk_mailbox_7",
	1075	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1076	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 7, 0),
	1077	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_8, "gate_clk_mailbox_8",
	1078	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1079	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 8, 0),
	1080	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_9, "gate_clk_mailbox_9",
	1081	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1082	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 9, 0),
	1083	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_10, "gate_clk_mailbox_10",
	1084	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1085	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 10, 0),
	1086	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_11, "gate_clk_mailbox_11",
	1087	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1088	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 11, 0),
	1089	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_12, "gate_clk_mailbox_12",
	1090	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1091	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 12, 0),
	1092	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_13, "gate_clk_mailbox_13",
	1093	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1094	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 13, 0),
	1095	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_14, "gate_clk_mailbox_14",
	1096	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1097	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 14, 0),
	1098	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_15, "gate_clk_mailbox_15",
	1099	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1100	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 15, 0),
	1101	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C0_PCLK, "gate_i2c0_pclk",
	1102	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1103	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 7, 0),
	1104	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C1_PCLK, "gate_i2c1_pclk",
	1105	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1106	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 8, 0),
	1107	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C2_PCLK, "gate_i2c2_pclk",
	1108	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1109	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 9, 0),
	1110	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C3_PCLK, "gate_i2c3_pclk",
	1111	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1112	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 10, 0),
	1113	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C4_PCLK, "gate_i2c4_pclk",
	1114	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1115	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 11, 0),
	1116	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C5_PCLK, "gate_i2c5_pclk",
	1117	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1118	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 12, 0),
	1119	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C6_PCLK, "gate_i2c6_pclk",
	1120	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1121	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 13, 0),
	1122	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C7_PCLK, "gate_i2c7_pclk",
	1123	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1124	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 14, 0),
	1125	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C8_PCLK, "gate_i2c8_pclk",
	1126	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1127	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 15, 0),
	1128	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C9_PCLK, "gate_i2c9_pclk",
	1129	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1130	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 16, 0),
	1131	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_WDT0_PCLK, "gate_lsp_wdt0_pclk",
	1132	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1133	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 28, 0),
	1134	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_WDT1_PCLK, "gate_lsp_wdt1_pclk",
	1135	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1136	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 29, 0),
	1137	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_WDT2_PCLK, "gate_lsp_wdt2_pclk",
	1138	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1139	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 30, 0),
	1140	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_WDT3_PCLK, "gate_lsp_wdt3_pclk",
	1141	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1142	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 31, 0),
	1143	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_SSI0_PCLK, "gate_lsp_ssi0_pclk",
	1144	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1145	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 26, 0),
	1146	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_SSI1_PCLK, "gate_lsp_ssi1_pclk",
	1147	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1148	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 27, 0),
	1149	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART0_PCLK, "gate_lsp_uart0_pclk",
	1150	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1151	+ CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	1152	+ EIC7700_REG_OFFSET_LSP_EN0, 17, 0),
	1153	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART1_PCLK, "gate_lsp_uart1_pclk",
	1154	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1155	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 18, 0),
	1156	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART2_PCLK, "gate_lsp_uart2_pclk",
	1157	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1158	+ CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	1159	+ EIC7700_REG_OFFSET_LSP_EN0, 19, 0),
	1160	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART3_PCLK, "gate_lsp_uart3_pclk",
	1161	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1162	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 20, 0),
	1163	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART4_PCLK, "gate_lsp_uart4_pclk",
	1164	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1165	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 21, 0),
	1166	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_TIMER_PCLK, "gate_lsp_timer_pclk",
	1167	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1168	+ CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	1169	+ EIC7700_REG_OFFSET_LSP_EN0, 25, 0),
	1170	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_FAN_PCLK, "gate_lsp_fan_pclk",
	1171	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1172	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 0, 0),
	1173	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_PVT_PCLK, "gate_lsp_pvt_pclk",
	1174	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1175	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 1, 0),
	1176	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_PVT0_CLK, "gate_pvt0_clk",
	1177	+ EIC7700_CLK_FIXED_FACTOR_PVT_DIV20, CLK_SET_RATE_PARENT,
	1178	+ EIC7700_REG_OFFSET_LSP_EN1, 16, 0),
	1179	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_PVT1_CLK, "gate_pvt1_clk",
	1180	+ EIC7700_CLK_FIXED_FACTOR_PVT_DIV20, CLK_SET_RATE_PARENT,
	1181	+ EIC7700_REG_OFFSET_LSP_EN1, 17, 0),
	1182	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_JE_PCLK, "gate_vc_je_pclk",
	1183	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1184	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 2, 0),
	1185	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_JD_PCLK, "gate_vc_jd_pclk",
	1186	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1187	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 1, 0),
	1188	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_VE_PCLK, "gate_vc_ve_pclk",
	1189	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1190	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 5, 0),
	1191	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_VD_PCLK, "gate_vc_vd_pclk",
	1192	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1193	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 4, 0),
	1194	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_MON_PCLK, "gate_vc_mon_pclk",
	1195	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1196	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 3, 0),
	1197	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_MSHC0_CORE_CLK,
	1198	+ "gate_hsp_mshc0_core_clk",
	1199	+ EIC7700_CLK_DIV_MSHC_CORE_DYNM_0, CLK_SET_RATE_PARENT,
	1200	+ EIC7700_REG_OFFSET_MSHC0_CORE, 16, 0),
	1201	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_MSHC1_CORE_CLK,
	1202	+ "gate_hsp_mshc1_core_clk",
	1203	+ EIC7700_CLK_DIV_MSHC_CORE_DYNM_1, CLK_SET_RATE_PARENT,
	1204	+ EIC7700_REG_OFFSET_MSHC1_CORE, 16, 0),
	1205	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_MSHC2_CORE_CLK,
	1206	+ "gate_hsp_mshc2_core_clk",
	1207	+ EIC7700_CLK_DIV_MSHC_CORE_DYNM_2, CLK_SET_RATE_PARENT,
	1208	+ EIC7700_REG_OFFSET_MSHC2_CORE, 16, 0),
	1209	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_SATA_RBC_CLK,
	1210	+ "gate_hsp_sata_rbc_clk", EIC7700_CLK_SPLL1_FOUT2,
	1211	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SATA_RBC,
	1212	+ 0, 0),
	1213	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_SATA_OOB_CLK,
	1214	+ "gate_hsp_sata_oob_clk", EIC7700_CLK_MUX_SATA_PHY_2MUX1,
	1215	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SATA_OOB, 31,
	1216	+ 0),
	1217	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_DMA0_CLK_TEST,
	1218	+ "gate_hsp_dma0_clk_test", EIC7700_CLK_GATE_HSP_ACLK,
	1219	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_HSP_ACLK, 1, 0),
	1220	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_DMA0_CLK, "gate_hsp_dma0_clk",
	1221	+ EIC7700_CLK_GATE_HSP_ACLK, CLK_SET_RATE_PARENT,
	1222	+ EIC7700_REG_OFFSET_HSP_ACLK, 0, 0),
	1223	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_ETH0_CORE_CLK,
	1224	+ "gate_hsp_eth0_core_clk",
	1225	+ EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0, CLK_SET_RATE_PARENT,
	1226	+ EIC7700_REG_OFFSET_ETH0, 0, 0),
	1227	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_ETH1_CORE_CLK,
	1228	+ "gate_hsp_eth1_core_clk",
	1229	+ EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1, CLK_SET_RATE_PARENT,
	1230	+ EIC7700_REG_OFFSET_ETH1, 0, 0),
	1231	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AON_I2C0_PCLK, "gate_aon_i2c0_pclk",
	1232	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1233	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_I2C0, 31, 0),
	1234	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AON_I2C1_PCLK, "gate_aon_i2c1_pclk",
	1235	+ EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
	1236	+ CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_I2C1, 31, 0),
	1237	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDR0_TRACE, "gate_ddr0_trace",
	1238	+ EIC7700_CLK_DIV_DDR_ACLK_DYNM, CLK_SET_RATE_PARENT,
	1239	+ EIC7700_REG_OFFSET_DDR, 0, 0),
	1240	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDR1_TRACE, "gate_ddr1_trace",
	1241	+ EIC7700_CLK_DIV_DDR_ACLK_DYNM, CLK_SET_RATE_PARENT,
	1242	+ EIC7700_REG_OFFSET_DDR1, 0, 0),
	1243	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_RNOC_NSP, "gate_rnoc_nsp",
	1244	+ EIC7700_CLK_DIV_NOC_NSP_DYNM, CLK_SET_RATE_PARENT,
	1245	+ EIC7700_REG_OFFSET_NOC, 29, 0),
	1246	+ ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NOC_WDREF, "gate_noc_wdref",
	1247	+ EIC7700_CLK_DIV_NOC_WDREF_DYNM, CLK_SET_RATE_PARENT,
	1248	+ EIC7700_REG_OFFSET_NOC, 30, 0),
	1249	+};
	1250	+
	1251	+/*
	1252	+ * This clock notifier is called when the rate of clk_pll_cpu clock is to be
	1253	+ * changed. The mux_cpu_root_3mux1_gfree clock should save the current parent
	1254	+ * clock and switch its parent clock to fixed_factor_u84_core_lp_div2 before
	1255	+ * clk_pll_cpu rate will be changed. Then switch its parent clock back after
	1256	+ * the clk_pll_cpu rate is completed.
	1257	+ */
	1258	+static int eic7700_clk_pll_cpu_notifier_cb(struct notifier_block *nb,
	1259	+ unsigned long action, void *data)
	1260	+{
	1261	+ struct eswin_clock_data *pdata;
	1262	+ struct clk_hw *mux_clk;
	1263	+ struct clk_hw *lp_clk;
	1264	+ int ret = 0;
	1265	+
	1266	+ pdata = container_of(nb, struct eswin_clock_data, pll_nb);
	1267	+
	1268	+ mux_clk = &eic7700_mux_clks[0].hw;
	1269	+ lp_clk = &eic7700_early_clks[11].hw;
	1270	+
	1271	+ if (action == PRE_RATE_CHANGE) {
	1272	+ pdata->original_clk = clk_hw_get_parent(mux_clk);
	1273	+ ret = clk_hw_set_parent(mux_clk, lp_clk);
	1274	+ } else if (action == POST_RATE_CHANGE) {
	1275	+ ret = clk_hw_set_parent(mux_clk, pdata->original_clk);
	1276	+ }
	1277	+
	1278	+ return notifier_from_errno(ret);
	1279	+}
	1280	+
	1281	+static int eic7700_clk_probe(struct platform_device *pdev)
	1282	+{
	1283	+ struct eswin_clock_data *clk_data;
	1284	+ struct device *dev = &pdev->dev;
	1285	+ struct clk *pll_clk;
	1286	+ int ret;
	1287	+
	1288	+ clk_data = eswin_clk_init(pdev, EIC7700_NR_CLKS);
	1289	+ if (IS_ERR(clk_data))
	1290	+ return dev_err_probe(dev, PTR_ERR(clk_data),
	1291	+ "failed to get clk data!\n");
	1292	+
	1293	+ ret = eswin_clk_register_fixed_rate(dev, eic7700_fixed_rate_clks,
	1294	+ ARRAY_SIZE(eic7700_fixed_rate_clks),
	1295	+ clk_data);
	1296	+ if (ret)
	1297	+ return dev_err_probe(dev, ret,
	1298	+ "failed to register fixed rate clock\n");
	1299	+
	1300	+ ret = eswin_clk_register_pll(dev, eic7700_pll_clks,
	1301	+ ARRAY_SIZE(eic7700_pll_clks),
	1302	+ clk_data);
	1303	+ if (ret)
	1304	+ return dev_err_probe(dev, ret,
	1305	+ "failed to register pll clock\n");
	1306	+
	1307	+ pll_clk = devm_clk_hw_get_clk(dev, &eic7700_pll_clks[1].hw,
	1308	+ "clk_pll_cpu");
	1309	+ if (IS_ERR(pll_clk))
	1310	+ return dev_err_probe(dev, PTR_ERR(pll_clk),
	1311	+ "failed to get clk_pll_cpu\n");
	1312	+
	1313	+ clk_data->pll_nb.notifier_call = eic7700_clk_pll_cpu_notifier_cb;
	1314	+ ret = devm_clk_notifier_register(dev, pll_clk, &clk_data->pll_nb);
	1315	+ if (ret)
	1316	+ return ret;
	1317	+
	1318	+ ret = eswin_clk_register_fixed_factor(dev, eic7700_factor_clks,
	1319	+ ARRAY_SIZE(eic7700_factor_clks),
	1320	+ clk_data);
	1321	+ if (ret)
	1322	+ return dev_err_probe(dev, ret,
	1323	+ "failed to register fixed factor clock\n");
	1324	+
	1325	+ ret = eswin_clk_register_divider(dev, eic7700_div_clks,
	1326	+ ARRAY_SIZE(eic7700_div_clks),
	1327	+ clk_data);
	1328	+ if (ret)
	1329	+ return dev_err_probe(dev, ret,
	1330	+ "failed to register divider clock\n");
	1331	+
	1332	+ ret = eswin_clk_register_gate(dev, eic7700_gate_clks,
	1333	+ ARRAY_SIZE(eic7700_gate_clks), clk_data);
	1334	+ if (ret)
	1335	+ return dev_err_probe(dev, ret,
	1336	+ "failed to register gate clock\n");
	1337	+
	1338	+ ret = eswin_clk_register_clks(dev, eic7700_early_clks,
	1339	+ ARRAY_SIZE(eic7700_early_clks), clk_data);
	1340	+ if (ret)
	1341	+ return dev_err_probe(dev, ret, "failed to register clock\n");
	1342	+
	1343	+ ret = eswin_clk_register_mux(dev, eic7700_mux_clks,
	1344	+ ARRAY_SIZE(eic7700_mux_clks), clk_data);
	1345	+ if (ret)
	1346	+ return dev_err_probe(dev, ret,
	1347	+ "failed to register mux clock\n");
	1348	+
	1349	+ ret = eswin_clk_register_clks(dev, eic7700_clks,
	1350	+ ARRAY_SIZE(eic7700_clks), clk_data);
	1351	+ if (ret)
	1352	+ return dev_err_probe(dev, ret, "failed to register clock\n");
	1353	+
	1354	+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
	1355	+ &clk_data->clk_data);
	1356	+}
	1357	+
	1358	+static const struct of_device_id eic7700_clock_dt_ids[] = {
	1359	+ { .compatible = "eswin,eic7700-clock", },
	1360	+ { /* sentinel */ }
	1361	+};
	1362	+MODULE_DEVICE_TABLE(of, eic7700_clock_dt_ids);
	1363	+
	1364	+static struct platform_driver eic7700_clock_driver = {
	1365	+ .probe = eic7700_clk_probe,
	1366	+ .driver = {
	1367	+ .name = "eic7700-clock",
	1368	+ .of_match_table = eic7700_clock_dt_ids,
	1369	+ },
	1370	+};
	1371	+module_platform_driver(eic7700_clock_driver);
	1372	+
	1373	+MODULE_LICENSE("GPL");
	1374	+MODULE_AUTHOR("Yifeng Huang <huangyifeng@eswincomputing.com>");
	1375	+MODULE_AUTHOR("Xuyang Dong <dongxuyang@eswincomputing.com>");
	1376	+MODULE_DESCRIPTION("ESWIN EIC7700 clock controller driver");

drivers/clk/eswin/clk.c+586−0

@@ -0,0 +1,586 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+/*
	3	+ * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
	4	+ * All rights reserved.
	5	+ *
	6	+ * Authors:
	7	+ * Yifeng Huang <huangyifeng@eswincomputing.com>
	8	+ * Xuyang Dong <dongxuyang@eswincomputing.com>
	9	+ */
	10	+
	11	+#include <linux/bitfield.h>
	12	+#include <linux/clk-provider.h>
	13	+#include <linux/iopoll.h>
	14	+#include <linux/math.h>
	15	+#include <linux/platform_device.h>
	16	+#include <linux/slab.h>
	17	+
	18	+#include "common.h"
	19	+
	20	+#define PLL_EN_MASK GENMASK(1, 0)
	21	+#define PLL_REFDIV_MASK GENMASK(17, 12)
	22	+#define PLL_FBDIV_MASK GENMASK(31, 20)
	23	+#define PLL_FRAC_MASK GENMASK(27, 4)
	24	+#define PLL_POSTDIV1_MASK GENMASK(10, 8)
	25	+#define PLL_POSTDIV2_MASK GENMASK(18, 16)
	26	+
	27	+struct eswin_clock_data eswin_clk_init(struct platform_device pdev,
	28	+ size_t nr_clks)
	29	+{
	30	+ struct eswin_clock_data *eclk_data;
	31	+
	32	+ eclk_data = devm_kzalloc(&pdev->dev,
	33	+ struct_size(eclk_data, clk_data.hws, nr_clks),
	34	+ GFP_KERNEL);
	35	+ if (!eclk_data)
	36	+ return ERR_PTR(-ENOMEM);
	37	+
	38	+ eclk_data->base = devm_platform_ioremap_resource(pdev, 0);
	39	+ if (IS_ERR(eclk_data->base))
	40	+ return ERR_PTR(-EINVAL);
	41	+
	42	+ eclk_data->clk_data.num = nr_clks;
	43	+ spin_lock_init(&eclk_data->lock);
	44	+
	45	+ return eclk_data;
	46	+}
	47	+EXPORT_SYMBOL_GPL(eswin_clk_init);
	48	+
	49	+/**
	50	+ * eswin_calc_pll - calculate PLL values
	51	+ * @frac_val: fractional divider
	52	+ * @fbdiv_val: feedback divider
	53	+ * @rate: reference rate
	54	+ * @parent_rate: parent rate
	55	+ *
	56	+ * Calculate PLL values for frac and fbdiv:
	57	+ * fbdiv = rate * 4 / parent_rate
	58	+ * frac = (rate * 4 % parent_rate * (2 ^ 24)) / parent_rate
	59	+ */
	60	+static void eswin_calc_pll(u32 frac_val, u32 fbdiv_val, unsigned long rate,
	61	+ unsigned long parent_rate)
	62	+{
	63	+ u32 rem;
	64	+ u64 tmp;
	65	+
	66	+ /* step 1: rate * 4 */
	67	+ tmp = rate * 4;
	68	+ /* step 2: use do_div() to get the quotient(tmp) and remainder(rem) */
	69	+ rem = do_div(tmp, (u32)parent_rate);
	70	+ /* fbdiv = rate * 4 / parent_rate */
	71	+ *fbdiv_val = (u32)tmp;
	72	+ /*
	73	+ * step 3: rem << 24
	74	+ * 24: 24-bit fractional accuracy
	75	+ */
	76	+ tmp = (u64)rem << 24;
	77	+ /* step 4: use do_div() to get the quotient(tmp) */
	78	+ do_div(tmp, (u32)parent_rate);
	79	+ /* frac = (rate * 4 % parent_rate * (2 ^ 24)) / parent_rate */
	80	+ *frac_val = (u32)tmp;
	81	+}
	82	+
	83	+static inline struct eswin_clk_pll to_pll_clk(struct clk_hw hw)
	84	+{
	85	+ return container_of(hw, struct eswin_clk_pll, hw);
	86	+}
	87	+
	88	+static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
	89	+ unsigned long parent_rate)
	90	+{
	91	+ struct eswin_clk_pll *clk = to_pll_clk(hw);
	92	+ u32 frac_val, fbdiv_val, val, mask;
	93	+ int ret;
	94	+
	95	+ eswin_calc_pll(&frac_val, &fbdiv_val, rate, parent_rate);
	96	+
	97	+ /* First, disable pll */
	98	+ val = readl_relaxed(clk->ctrl_reg0);
	99	+ val &= ~PLL_EN_MASK;
	100	+ val \|= FIELD_PREP(PLL_EN_MASK, 0);
	101	+ writel_relaxed(val, clk->ctrl_reg0);
	102	+
	103	+ val = readl_relaxed(clk->ctrl_reg0);
	104	+ val &= ~(PLL_REFDIV_MASK \| PLL_FBDIV_MASK);
	105	+ val \|= FIELD_PREP(PLL_FBDIV_MASK, fbdiv_val);
	106	+ val \|= FIELD_PREP(PLL_REFDIV_MASK, 1);
	107	+ writel_relaxed(val, clk->ctrl_reg0);
	108	+
	109	+ val = readl_relaxed(clk->ctrl_reg1);
	110	+ val &= ~PLL_FRAC_MASK;
	111	+ val \|= FIELD_PREP(PLL_FRAC_MASK, frac_val);
	112	+ writel_relaxed(val, clk->ctrl_reg1);
	113	+
	114	+ val = readl_relaxed(clk->ctrl_reg2);
	115	+ val &= ~(PLL_POSTDIV1_MASK \| PLL_POSTDIV2_MASK);
	116	+ val \|= FIELD_PREP(PLL_POSTDIV1_MASK, 1);
	117	+ val \|= FIELD_PREP(PLL_POSTDIV2_MASK, 1);
	118	+ writel_relaxed(val, clk->ctrl_reg2);
	119	+
	120	+ /* Last, enable pll */
	121	+ val = readl_relaxed(clk->ctrl_reg0);
	122	+ val &= ~PLL_EN_MASK;
	123	+ val \|= FIELD_PREP(PLL_EN_MASK, 1);
	124	+ writel_relaxed(val, clk->ctrl_reg0);
	125	+
	126	+ /* Usually the pll will lock in 50us */
	127	+ mask = GENMASK(clk->lock_shift + clk->lock_width - 1, clk->lock_shift);
	128	+ ret = readl_poll_timeout(clk->status_reg, val, val & mask, 1, 50 * 2);
	129	+ if (ret)
	130	+ pr_err("failed to lock the pll!\n");
	131	+
	132	+ return ret;
	133	+}
	134	+
	135	+static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
	136	+ unsigned long parent_rate)
	137	+{
	138	+ struct eswin_clk_pll *clk = to_pll_clk(hw);
	139	+ u64 fbdiv_val, frac_val, tmp;
	140	+ u32 rem, val;
	141	+
	142	+ val = readl_relaxed(clk->ctrl_reg0);
	143	+ val &= PLL_FBDIV_MASK;
	144	+ fbdiv_val = (val >> clk->fbdiv_shift);
	145	+
	146	+ val = readl_relaxed(clk->ctrl_reg1);
	147	+ val &= PLL_FRAC_MASK;
	148	+ frac_val = (val >> clk->frac_shift);
	149	+
	150	+ /* rate = 24000000 * (fbdiv + frac / (2 ^ 24)) / 4 */
	151	+ tmp = parent_rate * frac_val;
	152	+ rem = do_div(tmp, BIT(24));
	153	+ if (rem)
	154	+ tmp = parent_rate * fbdiv_val + tmp + 1;
	155	+ else
	156	+ tmp = parent_rate * fbdiv_val + tmp;
	157	+
	158	+ do_div(tmp, 4);
	159	+
	160	+ return tmp;
	161	+}
	162	+
	163	+static int clk_pll_determine_rate(struct clk_hw *hw,
	164	+ struct clk_rate_request *req)
	165	+{
	166	+ struct eswin_clk_pll *clk = to_pll_clk(hw);
	167	+
	168	+ req->rate = clamp(req->rate, clk->min_rate, clk->max_rate);
	169	+ req->min_rate = clk->min_rate;
	170	+ req->max_rate = clk->max_rate;
	171	+
	172	+ return 0;
	173	+}
	174	+
	175	+int eswin_clk_register_fixed_rate(struct device *dev,
	176	+ struct eswin_fixed_rate_clock *clks,
	177	+ int nums, struct eswin_clock_data *data)
	178	+{
	179	+ struct clk_hw *clk_hw;
	180	+ int i;
	181	+
	182	+ for (i = 0; i < nums; i++) {
	183	+ clk_hw = devm_clk_hw_register_fixed_rate(dev, clks[i].name,
	184	+ NULL, clks[i].flags,
	185	+ clks[i].rate);
	186	+ if (IS_ERR(clk_hw))
	187	+ return PTR_ERR(clk_hw);
	188	+
	189	+ clks[i].hw = *clk_hw;
	190	+ data->clk_data.hws[clks[i].id] = clk_hw;
	191	+ }
	192	+
	193	+ return 0;
	194	+}
	195	+EXPORT_SYMBOL_GPL(eswin_clk_register_fixed_rate);
	196	+
	197	+static const struct clk_ops eswin_clk_pll_ops = {
	198	+ .set_rate = clk_pll_set_rate,
	199	+ .recalc_rate = clk_pll_recalc_rate,
	200	+ .determine_rate = clk_pll_determine_rate,
	201	+};
	202	+
	203	+int eswin_clk_register_pll(struct device dev, struct eswin_pll_clock clks,
	204	+ int nums, struct eswin_clock_data *data)
	205	+{
	206	+ struct eswin_clk_pll *p_clk = NULL;
	207	+ struct clk_init_data init;
	208	+ struct clk_hw *clk_hw;
	209	+ int i, ret;
	210	+
	211	+ p_clk = devm_kzalloc(dev, sizeof(p_clk) nums, GFP_KERNEL);
	212	+ if (!p_clk)
	213	+ return -ENOMEM;
	214	+
	215	+ for (i = 0; i < nums; i++) {
	216	+ p_clk->id = clks[i].id;
	217	+ p_clk->ctrl_reg0 = data->base + clks[i].ctrl_reg0;
	218	+ p_clk->fbdiv_shift = clks[i].fbdiv_shift;
	219	+
	220	+ p_clk->ctrl_reg1 = data->base + clks[i].ctrl_reg1;
	221	+ p_clk->frac_shift = clks[i].frac_shift;
	222	+
	223	+ p_clk->ctrl_reg2 = data->base + clks[i].ctrl_reg2;
	224	+
	225	+ p_clk->status_reg = data->base + clks[i].status_reg;
	226	+ p_clk->lock_shift = clks[i].lock_shift;
	227	+ p_clk->lock_width = clks[i].lock_width;
	228	+
	229	+ p_clk->max_rate = clks[i].max_rate;
	230	+ p_clk->min_rate = clks[i].min_rate;
	231	+
	232	+ init.name = clks[i].name;
	233	+ init.flags = 0;
	234	+ init.parent_data = clks[i].parent_data;
	235	+ init.num_parents = 1;
	236	+ init.ops = &eswin_clk_pll_ops;
	237	+ p_clk->hw.init = &init;
	238	+
	239	+ clk_hw = &p_clk->hw;
	240	+
	241	+ ret = devm_clk_hw_register(dev, clk_hw);
	242	+ if (ret)
	243	+ return ret;
	244	+
	245	+ clks[i].hw = *clk_hw;
	246	+ data->clk_data.hws[clks[i].id] = clk_hw;
	247	+ p_clk++;
	248	+ }
	249	+
	250	+ return 0;
	251	+}
	252	+EXPORT_SYMBOL_GPL(eswin_clk_register_pll);
	253	+
	254	+int eswin_clk_register_fixed_factor(struct device *dev,
	255	+ struct eswin_fixed_factor_clock *clks,
	256	+ int nums, struct eswin_clock_data *data)
	257	+{
	258	+ struct clk_hw *clk_hw;
	259	+ int i;
	260	+
	261	+ for (i = 0; i < nums; i++) {
	262	+ clk_hw = devm_clk_hw_register_fixed_factor_index(dev, clks[i].name,
	263	+ clks[i].parent_data->index,
	264	+ clks[i].flags, clks[i].mult,
	265	+ clks[i].div);
	266	+
	267	+ if (IS_ERR(clk_hw))
	268	+ return PTR_ERR(clk_hw);
	269	+
	270	+ clks[i].hw = *clk_hw;
	271	+ data->clk_data.hws[clks[i].id] = clk_hw;
	272	+ }
	273	+
	274	+ return 0;
	275	+}
	276	+EXPORT_SYMBOL_GPL(eswin_clk_register_fixed_factor);
	277	+
	278	+int eswin_clk_register_mux(struct device dev, struct eswin_mux_clock clks,
	279	+ int nums, struct eswin_clock_data *data)
	280	+{
	281	+ struct clk_hw *clk_hw;
	282	+ int i;
	283	+
	284	+ for (i = 0; i < nums; i++) {
	285	+ clk_hw = devm_clk_hw_register_mux_parent_data_table(dev, clks[i].name,
	286	+ clks[i].parent_data,
	287	+ clks[i].num_parents,
	288	+ clks[i].flags,
	289	+ data->base + clks[i].reg,
	290	+ clks[i].shift, clks[i].width,
	291	+ clks[i].mux_flags,
	292	+ clks[i].table, &data->lock);
	293	+
	294	+ if (IS_ERR(clk_hw))
	295	+ return PTR_ERR(clk_hw);
	296	+
	297	+ clks[i].hw = *clk_hw;
	298	+ data->clk_data.hws[clks[i].id] = clk_hw;
	299	+ }
	300	+
	301	+ return 0;
	302	+}
	303	+EXPORT_SYMBOL_GPL(eswin_clk_register_mux);
	304	+
	305	+static unsigned int _eswin_get_val(unsigned int div, unsigned long flags,
	306	+ u8 width)
	307	+{
	308	+ unsigned int maxdiv;
	309	+
	310	+ maxdiv = clk_div_mask(width);
	311	+ div = div > maxdiv ? maxdiv : div;
	312	+
	313	+ if (flags & ESWIN_PRIV_DIV_MIN_2)
	314	+ return (div < 2) ? 2 : div;
	315	+
	316	+ return div;
	317	+}
	318	+
	319	+static unsigned int eswin_div_get_val(unsigned long rate,
	320	+ unsigned long parent_rate, u8 width,
	321	+ unsigned long flags)
	322	+{
	323	+ unsigned int div;
	324	+
	325	+ div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
	326	+
	327	+ return _eswin_get_val(div, flags, width);
	328	+}
	329	+
	330	+static inline struct eswin_divider_clock to_div_clk(struct clk_hw hw)
	331	+{
	332	+ return container_of(hw, struct eswin_divider_clock, hw);
	333	+}
	334	+
	335	+static int clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
	336	+ unsigned long parent_rate)
	337	+{
	338	+ struct eswin_divider_clock *dclk = to_div_clk(hw);
	339	+ unsigned long flags;
	340	+ unsigned int value;
	341	+ u32 val;
	342	+
	343	+ value = eswin_div_get_val(rate, parent_rate, dclk->width,
	344	+ dclk->priv_flag);
	345	+
	346	+ spin_lock_irqsave(dclk->lock, flags);
	347	+
	348	+ val = readl_relaxed(dclk->ctrl_reg);
	349	+ val &= ~(clk_div_mask(dclk->width) << dclk->shift);
	350	+ val \|= (u32)value << dclk->shift;
	351	+ writel_relaxed(val, dclk->ctrl_reg);
	352	+
	353	+ spin_unlock_irqrestore(dclk->lock, flags);
	354	+
	355	+ return 0;
	356	+}
	357	+
	358	+static unsigned long clk_div_recalc_rate(struct clk_hw *hw,
	359	+ unsigned long parent_rate)
	360	+{
	361	+ struct eswin_divider_clock *dclk = to_div_clk(hw);
	362	+ unsigned int div, val;
	363	+
	364	+ val = readl_relaxed(dclk->ctrl_reg) >> dclk->shift;
	365	+ val &= clk_div_mask(dclk->width);
	366	+ div = _eswin_get_val(val, dclk->priv_flag, dclk->width);
	367	+
	368	+ return DIV_ROUND_UP_ULL((u64)parent_rate, div);
	369	+}
	370	+
	371	+static int eswin_clk_bestdiv(unsigned long rate,
	372	+ unsigned long best_parent_rate, u8 width,
	373	+ unsigned long flags)
	374	+{
	375	+ unsigned long bestdiv, up_rate, down_rate;
	376	+ int up, down;
	377	+
	378	+ if (!rate)
	379	+ rate = 1;
	380	+
	381	+ /* closest round */
	382	+ up = DIV_ROUND_UP_ULL((u64)best_parent_rate, rate);
	383	+ down = best_parent_rate / rate;
	384	+
	385	+ up_rate = DIV_ROUND_UP_ULL((u64)best_parent_rate, up);
	386	+ down_rate = DIV_ROUND_UP_ULL((u64)best_parent_rate, down);
	387	+
	388	+ bestdiv = (rate - up_rate) <= (down_rate - rate) ? up : down;
	389	+
	390	+ return bestdiv;
	391	+}
	392	+
	393	+static int clk_div_determine_rate(struct clk_hw *hw,
	394	+ struct clk_rate_request *req)
	395	+{
	396	+ struct eswin_divider_clock *dclk = to_div_clk(hw);
	397	+ int div;
	398	+
	399	+ div = eswin_clk_bestdiv(req->rate, req->best_parent_rate, dclk->width,
	400	+ dclk->priv_flag);
	401	+ div = _eswin_get_val(div, dclk->priv_flag, dclk->width);
	402	+ req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);
	403	+
	404	+ return 0;
	405	+}
	406	+
	407	+static const struct clk_ops eswin_clk_div_ops = {
	408	+ .set_rate = clk_div_set_rate,
	409	+ .recalc_rate = clk_div_recalc_rate,
	410	+ .determine_rate = clk_div_determine_rate,
	411	+};
	412	+
	413	+struct clk_hw eswin_register_clkdiv(struct device dev, unsigned int id,
	414	+ const char *name,
	415	+ const struct clk_hw *parent_hw,
	416	+ unsigned long flags, void __iomem *reg,
	417	+ u8 shift, u8 width,
	418	+ unsigned long clk_divider_flags,
	419	+ unsigned long priv_flag, spinlock_t *lock)
	420	+{
	421	+ struct eswin_divider_clock *dclk;
	422	+ struct clk_init_data init;
	423	+ struct clk_hw *clk_hw;
	424	+ int ret;
	425	+
	426	+ dclk = devm_kzalloc(dev, sizeof(*dclk), GFP_KERNEL);
	427	+ if (!dclk)
	428	+ return ERR_PTR(-ENOMEM);
	429	+
	430	+ init.name = name;
	431	+ init.ops = &eswin_clk_div_ops;
	432	+ init.flags = flags;
	433	+ init.parent_hws = &parent_hw;
	434	+ init.num_parents = 1;
	435	+
	436	+ /* struct clk_divider assignments */
	437	+ dclk->id = id;
	438	+ dclk->ctrl_reg = reg;
	439	+ dclk->shift = shift;
	440	+ dclk->width = width;
	441	+ dclk->div_flags = clk_divider_flags;
	442	+ dclk->priv_flag = priv_flag;
	443	+ dclk->lock = lock;
	444	+ dclk->hw.init = &init;
	445	+
	446	+ /* register the clock */
	447	+ clk_hw = &dclk->hw;
	448	+ ret = devm_clk_hw_register(dev, clk_hw);
	449	+ if (ret) {
	450	+ dev_err(dev, "failed to register divider clock!\n");
	451	+ return ERR_PTR(ret);
	452	+ }
	453	+
	454	+ return clk_hw;
	455	+}
	456	+EXPORT_SYMBOL_GPL(eswin_register_clkdiv);
	457	+
	458	+int eswin_clk_register_divider(struct device *dev,
	459	+ struct eswin_divider_clock *clks,
	460	+ int nums, struct eswin_clock_data *data)
	461	+{
	462	+ struct clk_hw *clk_hw;
	463	+ int i;
	464	+
	465	+ for (i = 0; i < nums; i++) {
	466	+ clk_hw = devm_clk_hw_register_divider_parent_data(dev, clks[i].name,
	467	+ clks[i].parent_data,
	468	+ clks[i].flags,
	469	+ data->base + clks[i].reg,
	470	+ clks[i].shift, clks[i].width,
	471	+ clks[i].div_flags, &data->lock);
	472	+
	473	+ if (IS_ERR(clk_hw))
	474	+ return PTR_ERR(clk_hw);
	475	+
	476	+ clks[i].hw = *clk_hw;
	477	+ data->clk_data.hws[clks[i].id] = clk_hw;
	478	+ }
	479	+
	480	+ return 0;
	481	+}
	482	+EXPORT_SYMBOL_GPL(eswin_clk_register_divider);
	483	+
	484	+int eswin_clk_register_gate(struct device dev, struct eswin_gate_clock clks,
	485	+ int nums, struct eswin_clock_data *data)
	486	+{
	487	+ struct clk_hw *clk_hw;
	488	+ int i;
	489	+
	490	+ for (i = 0; i < nums; i++) {
	491	+ clk_hw = devm_clk_hw_register_gate_parent_data(dev, clks[i].name,
	492	+ clks[i].parent_data,
	493	+ clks[i].flags,
	494	+ data->base + clks[i].reg,
	495	+ clks[i].bit_idx, clks[i].gate_flags,
	496	+ &data->lock);
	497	+
	498	+ if (IS_ERR(clk_hw))
	499	+ return PTR_ERR(clk_hw);
	500	+
	501	+ clks[i].hw = *clk_hw;
	502	+ data->clk_data.hws[clks[i].id] = clk_hw;
	503	+ }
	504	+
	505	+ return 0;
	506	+}
	507	+EXPORT_SYMBOL_GPL(eswin_clk_register_gate);
	508	+
	509	+int eswin_clk_register_clks(struct device dev, struct eswin_clk_info clks,
	510	+ int nums, struct eswin_clock_data *data)
	511	+{
	512	+ struct eswin_clk_info *info;
	513	+ const struct clk_hw *phw = NULL;
	514	+ struct clk_hw *hw;
	515	+ int i;
	516	+
	517	+ for (i = 0; i < nums; i++) {
	518	+ info = &clks[i];
	519	+ switch (info->type) {
	520	+ case CLK_FIXED_FACTOR: {
	521	+ const struct eswin_fixed_factor_clock *factor;
	522	+
	523	+ factor = &info->data.factor;
	524	+ phw = data->clk_data.hws[info->pid];
	525	+ hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, factor->name, phw,
	526	+ factor->flags,
	527	+ factor->mult,
	528	+ factor->div);
	529	+ break;
	530	+ }
	531	+ case CLK_MUX: {
	532	+ const struct eswin_mux_clock *mux = &info->data.mux;
	533	+
	534	+ hw = devm_clk_hw_register_mux_parent_data_table(dev, mux->name,
	535	+ mux->parent_data,
	536	+ mux->num_parents,
	537	+ mux->flags,
	538	+ data->base + mux->reg,
	539	+ mux->shift, mux->width,
	540	+ mux->mux_flags,
	541	+ mux->table, &data->lock);
	542	+ break;
	543	+ }
	544	+ case CLK_DIVIDER: {
	545	+ const struct eswin_divider_clock *div = &info->data.div;
	546	+
	547	+ phw = data->clk_data.hws[info->pid];
	548	+ if (div->priv_flag)
	549	+ hw = eswin_register_clkdiv(dev, div->id, div->name, phw,
	550	+ div->flags, data->base + div->reg,
	551	+ div->shift, div->width, div->div_flags,
	552	+ div->priv_flag, &data->lock);
	553	+ else
	554	+ hw = devm_clk_hw_register_divider_parent_hw(dev, div->name, phw,
	555	+ div->flags,
	556	+ data->base + div->reg,
	557	+ div->shift, div->width,
	558	+ div->div_flags,
	559	+ &data->lock);
	560	+ break;
	561	+ }
	562	+ case CLK_GATE: {
	563	+ const struct eswin_gate_clock *gate = &info->data.gate;
	564	+
	565	+ phw = data->clk_data.hws[info->pid];
	566	+ hw = devm_clk_hw_register_gate_parent_hw(dev, gate->name, phw,
	567	+ gate->flags,
	568	+ data->base + gate->reg,
	569	+ gate->bit_idx, gate->gate_flags,
	570	+ &data->lock);
	571	+ break;
	572	+ }
	573	+ default:
	574	+ dev_err(dev, "Unidentifiable clock type!\n");
	575	+ return -EINVAL;
	576	+ }
	577	+ if (IS_ERR(hw))
	578	+ return PTR_ERR(hw);
	579	+
	580	+ info->hw = *hw;
	581	+ data->clk_data.hws[info->id] = hw;
	582	+ }
	583	+
	584	+ return 0;
	585	+}
	586	+EXPORT_SYMBOL_GPL(eswin_clk_register_clks);

drivers/clk/eswin/common.h+340−0

@@ -0,0 +1,340 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 */
	2	+/*
	3	+ * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
	4	+ * All rights reserved.
	5	+ *
	6	+ * Authors:
	7	+ * Yifeng Huang <huangyifeng@eswincomputing.com>
	8	+ * Xuyang Dong <dongxuyang@eswincomputing.com>
	9	+ */
	10	+
	11	+#ifndef __ESWIN_COMMON_H__
	12	+#define __ESWIN_COMMON_H__
	13	+
	14	+#define APLL_HIGH_FREQ 983040000
	15	+#define APLL_LOW_FREQ 225792000
	16	+#define PLL_HIGH_FREQ 1800000000
	17	+#define PLL_LOW_FREQ 24000000
	18	+
	19	+/*
	20	+ * ESWIN_PRIV_DIV_MIN_2: If ESWIN_PRIV_DIV_MIN_2 is set, the minimum value of
	21	+ * the register is 2, i.e. the minimum division ratio is 2.
	22	+ */
	23	+#define ESWIN_PRIV_DIV_MIN_2 BIT(0)
	24	+
	25	+enum eswin_clk_type {
	26	+ CLK_FIXED_FACTOR,
	27	+ CLK_MUX,
	28	+ CLK_DIVIDER,
	29	+ CLK_GATE,
	30	+};
	31	+
	32	+struct eswin_clock_data {
	33	+ void __iomem *base;
	34	+ struct clk_hw *original_clk;
	35	+ struct notifier_block pll_nb;
	36	+ spinlock_t lock; /* protect register read-modify-write cycle */
	37	+ struct clk_hw_onecell_data clk_data;
	38	+};
	39	+
	40	+struct eswin_divider_clock {
	41	+ struct clk_hw hw;
	42	+ unsigned int id;
	43	+ const char *name;
	44	+ const struct clk_parent_data *parent_data;
	45	+ void __iomem ctrl_reg; / register address of the divider clock */
	46	+ unsigned long flags;
	47	+ unsigned long reg; /* register offset */
	48	+ u8 shift;
	49	+ u8 width;
	50	+ unsigned long div_flags;
	51	+ unsigned long priv_flag;
	52	+ spinlock_t lock; / protect register read-modify-write cycle */
	53	+};
	54	+
	55	+struct eswin_fixed_rate_clock {
	56	+ struct clk_hw hw;
	57	+ unsigned int id;
	58	+ const char *name;
	59	+ unsigned long flags;
	60	+ unsigned long rate;
	61	+};
	62	+
	63	+struct eswin_fixed_factor_clock {
	64	+ struct clk_hw hw;
	65	+ unsigned int id;
	66	+ const char *name;
	67	+ const struct clk_parent_data *parent_data;
	68	+ unsigned long mult;
	69	+ unsigned long div;
	70	+ unsigned long flags;
	71	+};
	72	+
	73	+struct eswin_gate_clock {
	74	+ struct clk_hw hw;
	75	+ unsigned int id;
	76	+ const char *name;
	77	+ const struct clk_parent_data *parent_data;
	78	+ unsigned long flags;
	79	+ unsigned long reg;
	80	+ u8 bit_idx;
	81	+ u8 gate_flags;
	82	+};
	83	+
	84	+struct eswin_mux_clock {
	85	+ struct clk_hw hw;
	86	+ unsigned int id;
	87	+ const char *name;
	88	+ const struct clk_parent_data *parent_data;
	89	+ u8 num_parents;
	90	+ unsigned long flags;
	91	+ unsigned long reg;
	92	+ u8 shift;
	93	+ u8 width;
	94	+ u8 mux_flags;
	95	+ u32 *table;
	96	+};
	97	+
	98	+struct eswin_pll_clock {
	99	+ struct clk_hw hw;
	100	+ u32 id;
	101	+ const char *name;
	102	+ const struct clk_parent_data *parent_data;
	103	+ const u32 ctrl_reg0;
	104	+ const u8 fbdiv_shift;
	105	+
	106	+ const u32 ctrl_reg1;
	107	+ const u8 frac_shift;
	108	+
	109	+ const u32 ctrl_reg2;
	110	+
	111	+ const u32 status_reg;
	112	+ const u8 lock_shift;
	113	+ const u8 lock_width;
	114	+
	115	+ const u64 max_rate;
	116	+ const u64 min_rate;
	117	+};
	118	+
	119	+struct eswin_clk_pll {
	120	+ struct clk_hw hw;
	121	+ u32 id;
	122	+ void __iomem *ctrl_reg0;
	123	+ u8 fbdiv_shift;
	124	+
	125	+ void __iomem *ctrl_reg1;
	126	+ u8 frac_shift;
	127	+
	128	+ void __iomem *ctrl_reg2;
	129	+
	130	+ void __iomem *status_reg;
	131	+ u8 lock_shift;
	132	+ u8 lock_width;
	133	+
	134	+ u64 max_rate;
	135	+ u64 min_rate;
	136	+};
	137	+
	138	+struct eswin_clk_info {
	139	+ unsigned int type;
	140	+ unsigned int pid;
	141	+ unsigned int id;
	142	+ struct clk_hw hw;
	143	+ union {
	144	+ struct eswin_divider_clock div;
	145	+ struct eswin_fixed_factor_clock factor;
	146	+ struct eswin_gate_clock gate;
	147	+ struct eswin_mux_clock mux;
	148	+ } data;
	149	+};
	150	+
	151	+struct eswin_clock_data eswin_clk_init(struct platform_device pdev,
	152	+ size_t nr_clks);
	153	+int eswin_clk_register_fixed_rate(struct device *dev,
	154	+ struct eswin_fixed_rate_clock *clks,
	155	+ int nums, struct eswin_clock_data *data);
	156	+int eswin_clk_register_pll(struct device dev, struct eswin_pll_clock clks,
	157	+ int nums, struct eswin_clock_data *data);
	158	+int eswin_clk_register_fixed_factor(struct device *dev,
	159	+ struct eswin_fixed_factor_clock *clks,
	160	+ int nums, struct eswin_clock_data *data);
	161	+int eswin_clk_register_mux(struct device dev, struct eswin_mux_clock clks,
	162	+ int nums, struct eswin_clock_data *data);
	163	+int eswin_clk_register_divider(struct device *dev,
	164	+ struct eswin_divider_clock *clks,
	165	+ int nums, struct eswin_clock_data *data);
	166	+int eswin_clk_register_gate(struct device dev, struct eswin_gate_clock clks,
	167	+ int nums, struct eswin_clock_data *data);
	168	+int eswin_clk_register_clks(struct device dev, struct eswin_clk_info clks,
	169	+ int nums, struct eswin_clock_data *data);
	170	+struct clk_hw eswin_register_clkdiv(struct device dev, unsigned int id,
	171	+ const char *name,
	172	+ const struct clk_hw *parent_hw,
	173	+ unsigned long flags, void __iomem *reg,
	174	+ u8 shift, u8 width,
	175	+ unsigned long clk_divider_flags,
	176	+ unsigned long priv_flag, spinlock_t *lock);
	177	+
	178	+#define ESWIN_DIV(_id, _name, _pdata, _flags, _reg, _shift, _width, \
	179	+ _dflags, _pflag) \
	180	+ { \
	181	+ .id = _id, \
	182	+ .name = _name, \
	183	+ .parent_data = _pdata, \
	184	+ .flags = _flags, \
	185	+ .reg = _reg, \
	186	+ .shift = _shift, \
	187	+ .width = _width, \
	188	+ .div_flags = _dflags, \
	189	+ .priv_flag = _pflag, \
	190	+ }
	191	+
	192	+#define ESWIN_DIV_TYPE(_id, _name, _pid, _flags, _reg, _shift, _width, \
	193	+ _dflags, _pflag) \
	194	+ { \
	195	+ .type = CLK_DIVIDER, \
	196	+ .pid = _pid, \
	197	+ .id = _id, \
	198	+ .data = { \
	199	+ .div = { \
	200	+ .name = _name, \
	201	+ .flags = _flags, \
	202	+ .reg = _reg, \
	203	+ .shift = _shift, \
	204	+ .width = _width, \
	205	+ .div_flags = _dflags, \
	206	+ .priv_flag = _pflag, \
	207	+ }, \
	208	+ }, \
	209	+ }
	210	+
	211	+#define ESWIN_FACTOR(_id, _name, _pdata, _mult, _div, _flags) \
	212	+ { \
	213	+ .id = _id, \
	214	+ .name = _name, \
	215	+ .parent_data = _pdata, \
	216	+ .mult = _mult, \
	217	+ .div = _div, \
	218	+ .flags = _flags, \
	219	+ }
	220	+
	221	+#define ESWIN_FACTOR_TYPE(_id, _name, _pid, _mult, _div, _flags) \
	222	+ { \
	223	+ .type = CLK_FIXED_FACTOR, \
	224	+ .pid = _pid, \
	225	+ .id = _id, \
	226	+ .data = { \
	227	+ .factor = { \
	228	+ .name = _name, \
	229	+ .mult = _mult, \
	230	+ .div = _div, \
	231	+ .flags = _flags, \
	232	+ }, \
	233	+ }, \
	234	+ }
	235	+
	236	+#define ESWIN_FIXED(_id, _name, _flags, _rate) \
	237	+ { \
	238	+ .id = _id, \
	239	+ .name = _name, \
	240	+ .flags = _flags, \
	241	+ .rate = _rate, \
	242	+ }
	243	+
	244	+#define ESWIN_GATE(_id, _name, _pdata, _flags, _reg, _idx, _gflags) \
	245	+ { \
	246	+ .id = _id, \
	247	+ .name = _name, \
	248	+ .parent_data = _pdata, \
	249	+ .flags = _flags, \
	250	+ .reg = _reg, \
	251	+ .bit_idx = _idx, \
	252	+ .gate_flags = _gflags, \
	253	+ }
	254	+
	255	+#define ESWIN_GATE_TYPE(_id, _name, _pid, _flags, _reg, _idx, _gflags) \
	256	+ { \
	257	+ .type = CLK_GATE, \
	258	+ .pid = _pid, \
	259	+ .id = _id, \
	260	+ .data = { \
	261	+ .gate = { \
	262	+ .name = _name, \
	263	+ .flags = _flags, \
	264	+ .reg = _reg, \
	265	+ .bit_idx = _idx, \
	266	+ .gate_flags = _gflags, \
	267	+ }, \
	268	+ }, \
	269	+ }
	270	+
	271	+#define ESWIN_MUX(_id, _name, _pdata, _num_parents, _flags, _reg, \
	272	+ _shift, _width, _mflags) \
	273	+ { \
	274	+ .id = _id, \
	275	+ .name = _name, \
	276	+ .parent_data = _pdata, \
	277	+ .num_parents = _num_parents, \
	278	+ .flags = _flags, \
	279	+ .reg = _reg, \
	280	+ .shift = _shift, \
	281	+ .width = _width, \
	282	+ .mux_flags = _mflags, \
	283	+ .table = NULL, \
	284	+ }
	285	+
	286	+#define ESWIN_MUX_TBL(_id, _name, _pdata, _num_parents, _flags, _reg, \
	287	+ _shift, _width, _mflags, _table) \
	288	+ { \
	289	+ .id = _id, \
	290	+ .name = _name, \
	291	+ .parent_data = _pdata, \
	292	+ .num_parents = _num_parents, \
	293	+ .flags = _flags, \
	294	+ .reg = _reg, \
	295	+ .shift = _shift, \
	296	+ .width = _width, \
	297	+ .mux_flags = _mflags, \
	298	+ .table = _table, \
	299	+ }
	300	+
	301	+#define ESWIN_MUX_TYPE(_id, _name, _pdata, _num_parents, _flags, _reg, \
	302	+ _shift, _width, _mflags, _table) \
	303	+ { \
	304	+ .type = CLK_MUX, \
	305	+ .id = _id, \
	306	+ .data = { \
	307	+ .mux = { \
	308	+ .name = _name, \
	309	+ .parent_data = _pdata, \
	310	+ .num_parents = _num_parents, \
	311	+ .flags = _flags, \
	312	+ .reg = _reg, \
	313	+ .shift = _shift, \
	314	+ .width = _width, \
	315	+ .mux_flags = _mflags, \
	316	+ .table = _table, \
	317	+ }, \
	318	+ }, \
	319	+ }
	320	+
	321	+#define ESWIN_PLL(_id, _name, _pdata, _reg0, _fb_shift, _reg1, \
	322	+ _frac_shift, _reg2, _reg, _lock_shift, _lock_width, \
	323	+ _max_rate, _min_rate) \
	324	+ { \
	325	+ .id = _id, \
	326	+ .name = _name, \
	327	+ .parent_data = _pdata, \
	328	+ .ctrl_reg0 = _reg0, \
	329	+ .fbdiv_shift = _fb_shift, \
	330	+ .ctrl_reg1 = _reg1, \
	331	+ .frac_shift = _frac_shift, \
	332	+ .ctrl_reg2 = _reg2, \
	333	+ .status_reg = _reg, \
	334	+ .lock_shift = _lock_shift, \
	335	+ .lock_width = _lock_width, \
	336	+ .max_rate = _max_rate, \
	337	+ .min_rate = _min_rate, \
	338	+ }
	339	+
	340	+#endif /* __ESWIN_COMMON_H__ */

drivers/clk/imx/clk-fracn-gppll.c+2−0

@@ -85,9 +85,11 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { · 84 unmodified lines
85	85	PLL_FRACN_GP(519750000U, 173, 25, 100, 1, 8),
86	86	PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
87	87	PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
	88	+ PLL_FRACN_GP(477400000U, 119, 35, 100, 0, 6),
88	89	PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
89	90	PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
90	91	PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
	92	+ PLL_FRACN_GP(333333333U, 125, 0, 1, 1, 9),
91	93	PLL_FRACN_GP(332600000U, 138, 584, 1000, 0, 10),
92	94	PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12),
93	95	PLL_FRACN_GP(241900000U, 201, 584, 1000, 0, 20),

drivers/clk/imx/clk-imx6q.c+11−1

@@ -188,9 +188,11 @@ static void of_assigned_ldb_sels(struct device_node *node, · 187 unmodified lines
188	188	}
189	189	if (clkspec.np != node \|\| clkspec.args[0] >= IMX6QDL_CLK_END) {
190	190	pr_err("ccm: parent clock %d not in ccm\n", index);
	191	+ of_node_put(clkspec.np);
191	192	return;
192	193	}
193	194	parent = clkspec.args[0];
	195	+ of_node_put(clkspec.np);
194	196
195	197	rc = of_parse_phandle_with_args(node, "assigned-clocks",
196	198	"#clock-cells", index, &clkspec);
@@ -198,9 +200,11 @@ static void of_assigned_ldb_sels(struct device_node *node, · 1 unmodified line
198	200	return;
199	201	if (clkspec.np != node \|\| clkspec.args[0] >= IMX6QDL_CLK_END) {
200	202	pr_err("ccm: child clock %d not in ccm\n", index);
	203	+ of_node_put(clkspec.np);
201	204	return;
202	205	}
203	206	child = clkspec.args[0];
	207	+ of_node_put(clkspec.np);
204	208
205	209	if (child != IMX6QDL_CLK_LDB_DI0_SEL &&
206	210	child != IMX6QDL_CLK_LDB_DI1_SEL)
@@ -238,8 +242,11 @@ static bool pll6_bypassed(struct device_node *node) · 31 unmodified lines
238	242	return false;
239	243
240	244	if (clkspec.np == node &&
241		− clkspec.args[0] == IMX6QDL_PLL6_BYPASS)
	245	+ clkspec.args[0] == IMX6QDL_PLL6_BYPASS) {
	246	+ of_node_put(clkspec.np);
242	247	break;
	248	+ }
	249	+ of_node_put(clkspec.np);
243	250	}
244	251
245	252	/* PLL6 bypass is not part of the assigned clock list */
@@ -249,6 +256,9 @@ static bool pll6_bypassed(struct device_node *node) · 3 unmodified lines
249	256	ret = of_parse_phandle_with_args(node, "assigned-clock-parents",
250	257	"#clock-cells", index, &clkspec);
251	258
	259	+ if (!ret)
	260	+ of_node_put(clkspec.np);
	261	+
252	262	if (clkspec.args[0] != IMX6QDL_CLK_PLL6)
253	263	return true;
254	264

drivers/clk/imx/clk-imx8-acm.c+2−1

@@ -371,7 +371,8 @@ static int imx8_acm_clk_probe(struct platform_device *pdev) · 370 unmodified lines
371	371	for (i = 0; i < priv->soc_data->num_sels; i++) {
372	372	hws[sels[i].clkid] = devm_clk_hw_register_mux_parent_data_table(dev,
373	373	sels[i].name, sels[i].parents,
374		− sels[i].num_parents, 0,
	374	+ sels[i].num_parents,
	375	+ CLK_SET_RATE_NO_REPARENT,
375	376	base + sels[i].reg,
376	377	sels[i].shift, sels[i].width,
377	378	0, NULL, NULL);

drivers/clk/imx/clk-imx8mq.c+2−2

@@ -237,7 +237,7 @@ static const char * const imx8mq_dsi_esc_sels[] = {"osc_25m", "sys2_pll_100m", " · 236 unmodified lines
237	237	static const char * const imx8mq_csi1_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
238	238	"sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
239	239
240		−static const char * const imx8mq_csi1_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
	240	+static const char * const imx8mq_csi1_phy_sels[] = {"osc_25m", "sys2_pll_333m", "sys2_pll_100m", "sys1_pll_800m",
241	241	"sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
242	242
243	243	static const char * const imx8mq_csi1_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
@@ -246,7 +246,7 @@ static const char * const imx8mq_csi1_esc_sels[] = {"osc_25m", "sys2_pll_100m", · 2 unmodified lines
246	246	static const char * const imx8mq_csi2_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
247	247	"sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
248	248
249		−static const char * const imx8mq_csi2_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
	249	+static const char * const imx8mq_csi2_phy_sels[] = {"osc_25m", "sys2_pll_333m", "sys2_pll_100m", "sys1_pll_800m",
250	250	"sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
251	251
252	252	static const char * const imx8mq_csi2_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",

drivers/clk/imx/clk-pll14xx.c+3−3

@@ -151,7 +151,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat · 150 unmodified lines
151	151	/* First try if we can get the desired rate from one of the static entries */
152	152	tt = imx_get_pll_settings(pll, rate);
153	153	if (tt) {
154		− pr_debug("%s: in=%ld, want=%ld, Using PLL setting from table\n",
	154	+ pr_debug("%s: in=%lu, want=%lu, Using PLL setting from table\n",
155	155	clk_hw_get_name(&pll->hw), prate, rate);
156	156	t->rate = tt->rate;
157	157	t->mdiv = tt->mdiv;
@@ -173,7 +173,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat · 15 unmodified lines
173	173
174	174	if (rate >= rate_min && rate <= rate_max) {
175	175	kdiv = pll1443x_calc_kdiv(mdiv, pdiv, sdiv, rate, prate);
176		− pr_debug("%s: in=%ld, want=%ld Only adjust kdiv %ld -> %d\n",
	176	+ pr_debug("%s: in=%lu, want=%lu Only adjust kdiv %ld -> %d\n",
177	177	clk_hw_get_name(&pll->hw), prate, rate,
178	178	FIELD_GET(KDIV_MASK, pll_div_ctl1), kdiv);
179	179	fout = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate);
@@ -211,7 +211,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat · 31 unmodified lines
211	211	}
212	212	}
213	213	found:
214		− pr_debug("%s: in=%ld, want=%ld got=%d (pdiv=%d sdiv=%d mdiv=%d kdiv=%d)\n",
	214	+ pr_debug("%s: in=%lu, want=%lu got=%u (pdiv=%d sdiv=%d mdiv=%d kdiv=%d)\n",
215	215	clk_hw_get_name(&pll->hw), prate, rate, t->rate, t->pdiv, t->sdiv,
216	216	t->mdiv, t->kdiv);
217	217	}

drivers/clk/imx/clk-vf610.c+12−0

@@ -11,6 +11,13 @@ · 10 unmodified lines
11	11
12	12	#include "clk.h"
13	13
	14	+/*
	15	+ * The VF610_CLK_END corresponds to ones defined in
	16	+ * include/dt-bindings/clock/vf610-clock.h
	17	+ * It shall be the value of the last defined clock +1
	18	+ */
	19	+#define VF610_CLK_END 196
	20	+
14	21	#define CCM_CCR (ccm_base + 0x00)
15	22	#define CCM_CSR (ccm_base + 0x04)
16	23	#define CCM_CCSR (ccm_base + 0x08)
@@ -313,6 +320,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) · 296 unmodified lines
313	320	clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23);
314	321	clk[VF610_CLK_ENET0] = imx_clk_gate2("enet0", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(0));
315	322	clk[VF610_CLK_ENET1] = imx_clk_gate2("enet1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(1));
	323	+ clk[VF610_CLK_ESW] = imx_clk_gate2("esw", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(8));
	324	+ clk[VF610_CLK_ESW_MAC_TAB0] = imx_clk_gate2("esw_tab0", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(12));
	325	+ clk[VF610_CLK_ESW_MAC_TAB1] = imx_clk_gate2("esw_tab1", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(13));
	326	+ clk[VF610_CLK_ESW_MAC_TAB2] = imx_clk_gate2("esw_tab2", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(14));
	327	+ clk[VF610_CLK_ESW_MAC_TAB3] = imx_clk_gate2("esw_tab3", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(15));
316	328
317	329	clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
318	330

drivers/clk/microchip/clk-mpfs-ccc.c+5−1

@@ -178,7 +178,7 @@ static int mpfs_ccc_register_outputs(struct device *dev, struct mpfs_ccc_out_hw_ · 177 unmodified lines
178	178	return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
179	179	out_hw->id);
180	180
181		− data->hw_data.hws[out_hw->id] = &out_hw->divider.hw;
	181	+ data->hw_data.hws[out_hw->id - 2] = &out_hw->divider.hw;
182	182	}
183	183
184	184	return 0;
@@ -234,6 +234,10 @@ static int mpfs_ccc_probe(struct platform_device *pdev) · 49 unmodified lines
234	234	unsigned int num_clks;
235	235	int ret;
236	236
	237	+ /*
	238	+ * If DLLs get added here, mpfs_ccc_register_outputs() currently packs
	239	+ * sparse clock IDs in the hws array
	240	+ */
237	241	num_clks = ARRAY_SIZE(mpfs_ccc_pll_clks) + ARRAY_SIZE(mpfs_ccc_pll0out_clks) +
238	242	ARRAY_SIZE(mpfs_ccc_pll1out_clks);
239	243

drivers/clk/mvebu/armada-37xx-periph.c+9−7

@@ -126,9 +126,11 @@ static const struct clk_div_table clk_table2[] = { · 125 unmodified lines
126	126	static const struct clk_ops clk_double_div_ops;
127	127	static const struct clk_ops clk_pm_cpu_ops;
128	128
	129	+#define __reg(__x) ((void __iomem __force *)(__x))
	130	+
129	131	#define PERIPH_GATE(_name, _bit) \
130	132	struct clk_gate gate_##_name = { \
131		− .reg = (void *)CLK_DIS, \
	133	+ .reg = __reg(CLK_DIS), \
132	134	.bit_idx = _bit, \
133	135	.hw.init = &(struct clk_init_data){ \
134	136	.ops = &clk_gate_ops, \
@@ -137,7 +139,7 @@ struct clk_gate gate_##_name = { \ · 2 unmodified lines
137	139
138	140	#define PERIPH_MUX(_name, _shift) \
139	141	struct clk_mux mux_##_name = { \
140		− .reg = (void *)TBG_SEL, \
	142	+ .reg = __reg(TBG_SEL), \
141	143	.shift = _shift, \
142	144	.mask = 3, \
143	145	.hw.init = &(struct clk_init_data){ \
@@ -147,8 +149,8 @@ struct clk_mux mux_##_name = { \ · 3 unmodified lines
147	149
148	150	#define PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2) \
149	151	struct clk_double_div rate_##_name = { \
150		− .reg1 = (void *)_reg1, \
151		− .reg2 = (void *)_reg2, \
	152	+ .reg1 = __reg(_reg1), \
	153	+ .reg2 = __reg(_reg2), \
152	154	.shift1 = _shift1, \
153	155	.shift2 = _shift2, \
154	156	.hw.init = &(struct clk_init_data){ \
@@ -158,7 +160,7 @@ struct clk_double_div rate_##_name = { \ · 3 unmodified lines
158	160
159	161	#define PERIPH_DIV(_name, _reg, _shift, _table) \
160	162	struct clk_divider rate_##_name = { \
161		− .reg = (void *)_reg, \
	163	+ .reg = __reg(_reg), \
162	164	.table = _table, \
163	165	.shift = _shift, \
164	166	.hw.init = &(struct clk_init_data){ \
@@ -168,10 +170,10 @@ struct clk_divider rate_##_name = { \ · 3 unmodified lines
168	170
169	171	#define PERIPH_PM_CPU(_name, _shift1, _reg, _shift2) \
170	172	struct clk_pm_cpu muxrate_##_name = { \
171		− .reg_mux = (void *)TBG_SEL, \
	173	+ .reg_mux = __reg(TBG_SEL), \
172	174	.mask_mux = 3, \
173	175	.shift_mux = _shift1, \
174		− .reg_div = (void *)_reg, \
	176	+ .reg_div = __reg(_reg), \
175	177	.shift_div = _shift2, \
176	178	.hw.init = &(struct clk_init_data){ \
177	179	.ops = &clk_pm_cpu_ops, \

drivers/clk/qcom/Kconfig+86−8

@@ -19,33 +19,77 @@ menuconfig COMMON_CLK_QCOM · 18 unmodified lines
19	19
20	20	if COMMON_CLK_QCOM
21	21
	22	+config CLK_ELIZA_DISPCC
	23	+ tristate "Eliza Display Clock Controller"
	24	+ depends on ARM64 \|\| COMPILE_TEST
	25	+ select CLK_ELIZA_GCC
	26	+ help
	27	+ Support for the display clock controllers on Eliza SoCs.
	28	+ Say Y if you want to support display devices and functionality such as
	29	+ splash screen.
	30	+
	31	+config CLK_ELIZA_GCC
	32	+ tristate "Eliza Global Clock Controller"
	33	+ depends on ARM64 \|\| COMPILE_TEST
	34	+ select QCOM_GDSC
	35	+ help
	36	+ Support for the global clock controller on Eliza devices.
	37	+ Say Y if you want to use peripheral devices such as UART, SPI,
	38	+ I2C, USB, UFS, SDCC, etc.
	39	+
	40	+config CLK_ELIZA_TCSRCC
	41	+ tristate "Eliza TCSR Clock Controller"
	42	+ depends on ARM64 \|\| COMPILE_TEST
	43	+ select QCOM_GDSC
	44	+ help
	45	+ Support for the TCSR clock controller on Eliza devices.
	46	+ Say Y if you want to use peripheral devices such as USB/PCIe/UFS.
	47	+
22	48	config CLK_GLYMUR_DISPCC
23		− tristate "GLYMUR Display Clock Controller"
	49	+ tristate "Glymur Display Clock Controller"
24	50	depends on ARM64 \|\| COMPILE_TEST
25	51	select CLK_GLYMUR_GCC
26	52	help
27	53	Support for the display clock controllers on Qualcomm
28		− Technologies, Inc. GLYMUR devices.
	54	+ Technologies, Inc. Glymur devices.
29	55	Say Y if you want to support display devices and functionality such as
30	56	splash screen.
31	57
32	58	config CLK_GLYMUR_GCC
33		− tristate "GLYMUR Global Clock Controller"
	59	+ tristate "Glymur Global Clock Controller"
34	60	depends on ARM64 \|\| COMPILE_TEST
35	61	select QCOM_GDSC
36	62	help
37		− Support for the global clock controller on GLYMUR devices.
	63	+ Support for the global clock controller on Glymur devices.
38	64	Say Y if you want to use peripheral devices such as UART, SPI,
39	65	I2C, USB, UFS, SDCC, etc.
40	66
	67	+config CLK_GLYMUR_GPUCC
	68	+ tristate "GLYMUR Graphics Clock Controller"
	69	+ depends on ARM64 \|\| COMPILE_TEST
	70	+ select CLK_GLYMUR_GCC
	71	+ help
	72	+ Support for the graphics clock controller on GLYMUR devices.
	73	+ Say Y if you want to support graphics controller devices and
	74	+ functionality such as 3D graphics.
	75	+
41	76	config CLK_GLYMUR_TCSRCC
42		− tristate "GLYMUR TCSR Clock Controller"
	77	+ tristate "Glymur TCSR Clock Controller"
43	78	depends on ARM64 \|\| COMPILE_TEST
44	79	select QCOM_GDSC
45	80	help
46		− Support for the TCSR clock controller on GLYMUR devices.
	81	+ Support for the TCSR clock controller on Glymur devices.
47	82	Say Y if you want to use peripheral devices such as USB/PCIe/EDP.
48	83
	84	+config CLK_GLYMUR_VIDEOCC
	85	+ tristate "Glymur Video Clock Controller"
	86	+ depends on ARM64 \|\| COMPILE_TEST
	87	+ select CLK_GLYMUR_GCC
	88	+ help
	89	+ Support for the video clock controller on Glymur devices.
	90	+ Say Y if you want to support video devices and functionality such as
	91	+ video encode and decode.
	92	+
49	93	config CLK_KAANAPALI_CAMCC
50	94	tristate "Kaanapali Camera Clock Controller"
51	95	depends on ARM64 \|\| COMPILE_TEST
@@ -101,6 +145,16 @@ config CLK_KAANAPALI_VIDEOCC · 49 unmodified lines
101	145	Say Y if you want to support video devices and functionality such as
102	146	video encode/decode.
103	147
	148	+config CLK_NORD_GCC
	149	+ tristate "Nord Global Clock Controller"
	150	+ depends on ARM64 \|\| COMPILE_TEST
	151	+ select QCOM_GDSC
	152	+ help
	153	+ Support for the global clock controller on Nord devices.
	154	+ Say Y if you want to use peripheral devices such as UART,
	155	+ SPI, I2C, USB, SD/UFS, PCIe etc. The clock controller is a combination
	156	+ of GCC, SE_GCC, NE_GCC and NW_GCC.
	157	+
104	158	config CLK_X1E80100_CAMCC
105	159	tristate "X1E80100 Camera Clock Controller"
106	160	depends on ARM64 \|\| COMPILE_TEST
@@ -314,6 +368,14 @@ config IPQ_GCC_5018 · 207 unmodified lines
314	368	Say Y if you want to use peripheral devices such as UART, SPI,
315	369	i2c, USB, SD/eMMC, etc.
316	370
	371	+config IPQ_GCC_5210
	372	+ tristate "IPQ5210 Global Clock Controller"
	373	+ depends on ARM64 \|\| COMPILE_TEST
	374	+ help
	375	+ Support for the global clock controller on ipq5210 devices.
	376	+ Say Y if you want to use peripheral devices such as UART, SPI,
	377	+ i2c, USB, SD/eMMC, etc.
	378	+
317	379	config IPQ_GCC_5332
318	380	tristate "IPQ5332 Global Clock Controller"
319	381	depends on ARM64 \|\| COMPILE_TEST
@@ -622,6 +684,13 @@ config QCS_GCC_404 · 302 unmodified lines
622	684	Say Y if you want to use multimedia devices or peripheral
623	685	devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc.
624	686
	687	+config CLK_NORD_TCSRCC
	688	+ tristate "Nord TCSR Clock Controller"
	689	+ depends on ARM64 \|\| COMPILE_TEST
	690	+ help
	691	+ Support for the TCSR clock controller on Nord devices.
	692	+ Say Y if you want to use peripheral devices such as PCIe, USB, UFS etc.
	693	+
625	694	config SA_CAMCC_8775P
626	695	tristate "SA8775P Camera Clock Controller"
627	696	depends on ARM64 \|\| COMPILE_TEST
@@ -1481,6 +1550,15 @@ config SM_GPUCC_8650 · 853 unmodified lines
1481	1550	Say Y if you want to support graphics controller devices and
1482	1551	functionality such as 3D graphics.
1483	1552
	1553	+config SM_GPUCC_8750
	1554	+ tristate "SM8750 Graphics Clock Controller"
	1555	+ depends on ARM64 \|\| COMPILE_TEST
	1556	+ select SM_GCC_8750
	1557	+ help
	1558	+ Support for the graphics clock controller on SM8750 devices.
	1559	+ Say Y if you want to support graphics controller devices and
	1560	+ functionality such as 3D graphics.
	1561	+
1484	1562	config SM_LPASSCC_6115
1485	1563	tristate "SM6115 Low Power Audio Subsystem (LPASS) Clock Controller"
1486	1564	depends on ARM64 \|\| COMPILE_TEST
@@ -1579,10 +1657,10 @@ config SM_VIDEOCC_8250 · 92 unmodified lines
1579	1657	config SM_VIDEOCC_8350
1580	1658	tristate "SM8350 Video Clock Controller"
1581	1659	depends on ARM64 \|\| COMPILE_TEST
1582		− select SM_GCC_8350
	1660	+ depends on SM_GCC_8350 \|\| SC_GCC_8280XP
1583	1661	select QCOM_GDSC
1584	1662	help
1585		− Support for the video clock controller on SM8350 devices.
	1663	+ Support for the video clock controller on SM8350 or SC8280XP devices.
1586	1664	Say Y if you want to support video devices and functionality such as
1587	1665	video encode and decode.
1588	1666

drivers/clk/qcom/Makefile+9−0

@@ -20,16 +20,23 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o · 19 unmodified lines
20	20	# Keep alphabetically sorted by config
21	21	obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
22	22	obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
	23	+obj-$(CONFIG_CLK_ELIZA_DISPCC) += dispcc-eliza.o
	24	+obj-$(CONFIG_CLK_ELIZA_GCC) += gcc-eliza.o
	25	+obj-$(CONFIG_CLK_ELIZA_TCSRCC) += tcsrcc-eliza.o
23	26	obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
24	27	obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o
25	28	obj-$(CONFIG_CLK_GLYMUR_GCC) += gcc-glymur.o
	29	+obj-$(CONFIG_CLK_GLYMUR_GPUCC) += gpucc-glymur.o gxclkctl-kaanapali.o
26	30	obj-$(CONFIG_CLK_GLYMUR_TCSRCC) += tcsrcc-glymur.o
	31	+obj-$(CONFIG_CLK_GLYMUR_VIDEOCC) += videocc-glymur.o
27	32	obj-$(CONFIG_CLK_KAANAPALI_CAMCC) += cambistmclkcc-kaanapali.o camcc-kaanapali.o
28	33	obj-$(CONFIG_CLK_KAANAPALI_DISPCC) += dispcc-kaanapali.o
29	34	obj-$(CONFIG_CLK_KAANAPALI_GCC) += gcc-kaanapali.o
30	35	obj-$(CONFIG_CLK_KAANAPALI_GPUCC) += gpucc-kaanapali.o gxclkctl-kaanapali.o
31	36	obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) += tcsrcc-kaanapali.o
32	37	obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) += videocc-kaanapali.o
	38	+obj-$(CONFIG_CLK_NORD_GCC) += gcc-nord.o negcc-nord.o nwgcc-nord.o segcc-nord.o
	39	+obj-$(CONFIG_CLK_NORD_TCSRCC) += tcsrcc-nord.o
33	40	obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o
34	41	obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o
35	42	obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o
@@ -43,6 +50,7 @@ obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o · 7 unmodified lines
43	50	obj-$(CONFIG_IPQ_CMN_PLL) += ipq-cmn-pll.o
44	51	obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
45	52	obj-$(CONFIG_IPQ_GCC_5018) += gcc-ipq5018.o
	53	+obj-$(CONFIG_IPQ_GCC_5210) += gcc-ipq5210.o
46	54	obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o
47	55	obj-$(CONFIG_IPQ_GCC_5424) += gcc-ipq5424.o
48	56	obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
@@ -180,6 +188,7 @@ obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o · 131 unmodified lines
180	188	obj-$(CONFIG_SM_GPUCC_8450) += gpucc-sm8450.o
181	189	obj-$(CONFIG_SM_GPUCC_8550) += gpucc-sm8550.o
182	190	obj-$(CONFIG_SM_GPUCC_8650) += gpucc-sm8650.o
	191	+obj-$(CONFIG_SM_GPUCC_8750) += gpucc-sm8750.o gxclkctl-kaanapali.o
183	192	obj-$(CONFIG_SM_GPUCC_MILOS) += gpucc-milos.o
184	193	obj-$(CONFIG_SM_LPASSCC_6115) += lpasscc-sm6115.o
185	194	obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o

drivers/clk/qcom/apss-ipq5424.c+1−1

@@ -211,7 +211,7 @@ static struct clk_alpha_pll *ipa5424_apss_plls[] = { · 210 unmodified lines
211	211	&ipq5424_apss_pll,
212	212	};
213	213
214		−static struct qcom_cc_driver_data ipa5424_apss_driver_data = {
	214	+static const struct qcom_cc_driver_data ipa5424_apss_driver_data = {
215	215	.alpha_plls = ipa5424_apss_plls,
216	216	.num_alpha_plls = ARRAY_SIZE(ipa5424_apss_plls),
217	217	};

drivers/clk/qcom/cambistmclkcc-kaanapali.c+2−4

@@ -6,9 +6,7 @@ · 5 unmodified lines
6	6	#include <linux/clk-provider.h>
7	7	#include <linux/mod_devicetable.h>
8	8	#include <linux/module.h>
9		−#include <linux/of.h>
10	9	#include <linux/platform_device.h>
11		−#include <linux/pm_runtime.h>
12	10	#include <linux/regmap.h>
13	11
14	12	#include <dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h>
@@ -385,7 +383,7 @@ static struct clk_alpha_pll *cam_bist_mclk_cc_kaanapali_plls[] = { · 370 unmodified lines
385	383	&cam_bist_mclk_cc_pll0,
386	384	};
387	385
388		−static u32 cam_bist_mclk_cc_kaanapali_critical_cbcrs[] = {
	386	+static const u32 cam_bist_mclk_cc_kaanapali_critical_cbcrs[] = {
389	387	0x40e0, /* CAM_BIST_MCLK_CC_SLEEP_CLK */
390	388	};
391	389
@@ -397,7 +395,7 @@ static const struct regmap_config cam_bist_mclk_cc_kaanapali_regmap_config = { · 5 unmodified lines
397	395	.fast_io = true,
398	396	};
399	397
400		−static struct qcom_cc_driver_data cam_bist_mclk_cc_kaanapali_driver_data = {
	398	+static const struct qcom_cc_driver_data cam_bist_mclk_cc_kaanapali_driver_data = {
401	399	.alpha_plls = cam_bist_mclk_cc_kaanapali_plls,
402	400	.num_alpha_plls = ARRAY_SIZE(cam_bist_mclk_cc_kaanapali_plls),
403	401	.clk_cbcrs = cam_bist_mclk_cc_kaanapali_critical_cbcrs,

drivers/clk/qcom/cambistmclkcc-sm8750.c+2−2

@@ -402,7 +402,7 @@ static struct clk_alpha_pll *cam_bist_mclk_cc_sm8750_plls[] = { · 401 unmodified lines
402	402	&cam_bist_mclk_cc_pll0,
403	403	};
404	404
405		−static u32 cam_bist_mclk_cc_sm8750_critical_cbcrs[] = {
	405	+static const u32 cam_bist_mclk_cc_sm8750_critical_cbcrs[] = {
406	406	0x40f8, /* CAM_BIST_MCLK_CC_SLEEP_CLK */
407	407	};
408	408
@@ -414,7 +414,7 @@ static const struct regmap_config cam_bist_mclk_cc_sm8750_regmap_config = { · 5 unmodified lines
414	414	.fast_io = true,
415	415	};
416	416
417		−static struct qcom_cc_driver_data cam_bist_mclk_cc_sm8750_driver_data = {
	417	+static const struct qcom_cc_driver_data cam_bist_mclk_cc_sm8750_driver_data = {
418	418	.alpha_plls = cam_bist_mclk_cc_sm8750_plls,
419	419	.num_alpha_plls = ARRAY_SIZE(cam_bist_mclk_cc_sm8750_plls),
420	420	.clk_cbcrs = cam_bist_mclk_cc_sm8750_critical_cbcrs,

drivers/clk/qcom/camcc-kaanapali.c+2−4

@@ -6,9 +6,7 @@ · 5 unmodified lines
6	6	#include <linux/clk-provider.h>
7	7	#include <linux/mod_devicetable.h>
8	8	#include <linux/module.h>
9		−#include <linux/of.h>
10	9	#include <linux/platform_device.h>
11		−#include <linux/pm_runtime.h>
12	10	#include <linux/regmap.h>
13	11
14	12	#include <dt-bindings/clock/qcom,kaanapali-camcc.h>
@@ -2602,7 +2600,7 @@ static struct clk_alpha_pll *cam_cc_kaanapali_plls[] = { · 2587 unmodified lines
2602	2600	&cam_cc_pll7,
2603	2601	};
2604	2602
2605		−static u32 cam_cc_kaanapali_critical_cbcrs[] = {
	2603	+static const u32 cam_cc_kaanapali_critical_cbcrs[] = {
2606	2604	0x21398, /* CAM_CC_DRV_AHB_CLK */
2607	2605	0x21390, /* CAM_CC_DRV_XO_CLK */
2608	2606	0x21364, /* CAM_CC_GDSC_CLK */
@@ -2617,7 +2615,7 @@ static const struct regmap_config cam_cc_kaanapali_regmap_config = { · 8 unmodified lines
2617	2615	.fast_io = true,
2618	2616	};
2619	2617
2620		−static struct qcom_cc_driver_data cam_cc_kaanapali_driver_data = {
	2618	+static const struct qcom_cc_driver_data cam_cc_kaanapali_driver_data = {
2621	2619	.alpha_plls = cam_cc_kaanapali_plls,
2622	2620	.num_alpha_plls = ARRAY_SIZE(cam_cc_kaanapali_plls),
2623	2621	.clk_cbcrs = cam_cc_kaanapali_critical_cbcrs,

drivers/clk/qcom/camcc-milos.c+2−2

@@ -2104,7 +2104,7 @@ static struct clk_alpha_pll *cam_cc_milos_plls[] = { · 2103 unmodified lines
2104	2104	&cam_cc_pll6,
2105	2105	};
2106	2106
2107		−static u32 cam_cc_milos_critical_cbcrs[] = {
	2107	+static const u32 cam_cc_milos_critical_cbcrs[] = {
2108	2108	0x25038, /* CAM_CC_GDSC_CLK */
2109	2109	0x2505c, /* CAM_CC_SLEEP_CLK */
2110	2110	};
@@ -2117,7 +2117,7 @@ static const struct regmap_config cam_cc_milos_regmap_config = { · 6 unmodified lines
2117	2117	.fast_io = true,
2118	2118	};
2119	2119
2120		−static struct qcom_cc_driver_data cam_cc_milos_driver_data = {
	2120	+static const struct qcom_cc_driver_data cam_cc_milos_driver_data = {
2121	2121	.alpha_plls = cam_cc_milos_plls,
2122	2122	.num_alpha_plls = ARRAY_SIZE(cam_cc_milos_plls),
2123	2123	.clk_cbcrs = cam_cc_milos_critical_cbcrs,

drivers/clk/qcom/camcc-qcs615.c+1−1

@@ -1556,7 +1556,7 @@ static const struct regmap_config cam_cc_qcs615_regmap_config = { · 1555 unmodified lines
1556	1556	.fast_io = true,
1557	1557	};
1558	1558
1559		−static struct qcom_cc_driver_data cam_cc_qcs615_driver_data = {
	1559	+static const struct qcom_cc_driver_data cam_cc_qcs615_driver_data = {
1560	1560	.alpha_plls = cam_cc_qcs615_plls,
1561	1561	.num_alpha_plls = ARRAY_SIZE(cam_cc_qcs615_plls),
1562	1562	};

drivers/clk/qcom/camcc-sc8180x.c+32−35

@@ -7,7 +7,6 @@ · 6 unmodified lines
7	7	#include <linux/mod_devicetable.h>
8	8	#include <linux/module.h>
9	9	#include <linux/platform_device.h>
10		−#include <linux/pm_runtime.h>
11	10	#include <linux/regmap.h>
12	11
13	12	#include <dt-bindings/clock/qcom,sc8180x-camcc.h>
@@ -63,6 +62,7 @@ static const struct alpha_pll_config cam_cc_pll0_config = { · 49 unmodified lines
63	62
64	63	static struct clk_alpha_pll cam_cc_pll0 = {
65	64	.offset = 0x0,
	65	+ .config = &cam_cc_pll0_config,
66	66	.vco_table = trion_vco,
67	67	.num_vco = ARRAY_SIZE(trion_vco),
68	68	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
@@ -138,6 +138,7 @@ static const struct alpha_pll_config cam_cc_pll1_config = { · 69 unmodified lines
138	138
139	139	static struct clk_alpha_pll cam_cc_pll1 = {
140	140	.offset = 0x1000,
	141	+ .config = &cam_cc_pll1_config,
141	142	.vco_table = trion_vco,
142	143	.num_vco = ARRAY_SIZE(trion_vco),
143	144	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
@@ -167,6 +168,7 @@ static const struct alpha_pll_config cam_cc_pll2_config = { · 23 unmodified lines
167	168
168	169	static struct clk_alpha_pll cam_cc_pll2 = {
169	170	.offset = 0x2000,
	171	+ .config = &cam_cc_pll2_config,
170	172	.vco_table = regera_vco,
171	173	.num_vco = ARRAY_SIZE(regera_vco),
172	174	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_REGERA],
@@ -219,6 +221,7 @@ static const struct alpha_pll_config cam_cc_pll3_config = { · 46 unmodified lines
219	221
220	222	static struct clk_alpha_pll cam_cc_pll3 = {
221	223	.offset = 0x3000,
	224	+ .config = &cam_cc_pll3_config,
222	225	.vco_table = trion_vco,
223	226	.num_vco = ARRAY_SIZE(trion_vco),
224	227	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
@@ -248,6 +251,7 @@ static const struct alpha_pll_config cam_cc_pll4_config = { · 23 unmodified lines
248	251
249	252	static struct clk_alpha_pll cam_cc_pll4 = {
250	253	.offset = 0x4000,
	254	+ .config = &cam_cc_pll4_config,
251	255	.vco_table = trion_vco,
252	256	.num_vco = ARRAY_SIZE(trion_vco),
253	257	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
@@ -277,6 +281,7 @@ static const struct alpha_pll_config cam_cc_pll5_config = { · 23 unmodified lines
277	281
278	282	static struct clk_alpha_pll cam_cc_pll5 = {
279	283	.offset = 0x4078,
	284	+ .config = &cam_cc_pll5_config,
280	285	.vco_table = trion_vco,
281	286	.num_vco = ARRAY_SIZE(trion_vco),
282	287	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
@@ -306,6 +311,7 @@ static const struct alpha_pll_config cam_cc_pll6_config = { · 23 unmodified lines
306	311
307	312	static struct clk_alpha_pll cam_cc_pll6 = {
308	313	.offset = 0x40f0,
	314	+ .config = &cam_cc_pll6_config,
309	315	.vco_table = trion_vco,
310	316	.num_vco = ARRAY_SIZE(trion_vco),
311	317	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
@@ -2813,6 +2819,21 @@ static const struct qcom_reset_map cam_cc_sc8180x_resets[] = { · 2501 unmodified lines
2813	2819	[CAM_CC_MCLK7_BCR] = { 0x50e0 },
2814	2820	};
2815	2821
	2822	+static struct clk_alpha_pll *cam_cc_sc8180x_plls[] = {
	2823	+ &cam_cc_pll0,
	2824	+ &cam_cc_pll1,
	2825	+ &cam_cc_pll2,
	2826	+ &cam_cc_pll3,
	2827	+ &cam_cc_pll4,
	2828	+ &cam_cc_pll5,
	2829	+ &cam_cc_pll6,
	2830	+};
	2831	+
	2832	+static const u32 cam_cc_sc8180x_critical_cbcrs[] = {
	2833	+ 0xc1e4, /* CAM_CC_GDSC_CLK */
	2834	+ 0xc200, /* CAM_CC_SLEEP_CLK */
	2835	+};
	2836	+
2816	2837	static const struct regmap_config cam_cc_sc8180x_regmap_config = {
2817	2838	.reg_bits = 32,
2818	2839	.reg_stride = 4,
@@ -2821,6 +2842,13 @@ static const struct regmap_config cam_cc_sc8180x_regmap_config = { · 2 unmodified lines
2821	2842	.fast_io = true,
2822	2843	};
2823	2844
	2845	+static const struct qcom_cc_driver_data cam_cc_sc8180x_driver_data = {
	2846	+ .alpha_plls = cam_cc_sc8180x_plls,
	2847	+ .num_alpha_plls = ARRAY_SIZE(cam_cc_sc8180x_plls),
	2848	+ .clk_cbcrs = cam_cc_sc8180x_critical_cbcrs,
	2849	+ .num_clk_cbcrs = ARRAY_SIZE(cam_cc_sc8180x_critical_cbcrs),
	2850	+};
	2851	+
2824	2852	static const struct qcom_cc_desc cam_cc_sc8180x_desc = {
2825	2853	.config = &cam_cc_sc8180x_regmap_config,
2826	2854	.clks = cam_cc_sc8180x_clocks,
@@ -2829,6 +2857,8 @@ static const struct qcom_cc_desc cam_cc_sc8180x_desc = { · 2 unmodified lines
2829	2857	.num_resets = ARRAY_SIZE(cam_cc_sc8180x_resets),
2830	2858	.gdscs = cam_cc_sc8180x_gdscs,
2831	2859	.num_gdscs = ARRAY_SIZE(cam_cc_sc8180x_gdscs),
	2860	+ .use_rpm = true,
	2861	+ .driver_data = &cam_cc_sc8180x_driver_data,
2832	2862	};
2833	2863
2834	2864	static const struct of_device_id cam_cc_sc8180x_match_table[] = {
@@ -2839,40 +2869,7 @@ MODULE_DEVICE_TABLE(of, cam_cc_sc8180x_match_table); · 4 unmodified lines
2839	2869
2840	2870	static int cam_cc_sc8180x_probe(struct platform_device *pdev)
2841	2871	{
2842		− struct regmap *regmap;
2843		− int ret;
2844		−
2845		− ret = devm_pm_runtime_enable(&pdev->dev);
2846		− if (ret)
2847		− return ret;
2848		−
2849		− ret = pm_runtime_resume_and_get(&pdev->dev);
2850		− if (ret)
2851		− return ret;
2852		−
2853		− regmap = qcom_cc_map(pdev, &cam_cc_sc8180x_desc);
2854		− if (IS_ERR(regmap)) {
2855		− pm_runtime_put(&pdev->dev);
2856		− return PTR_ERR(regmap);
2857		− }
2858		−
2859		− clk_trion_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
2860		− clk_trion_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
2861		− clk_regera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
2862		− clk_trion_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
2863		− clk_trion_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
2864		− clk_trion_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
2865		− clk_trion_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
2866		−
2867		− /* Keep some clocks always enabled */
2868		− qcom_branch_set_clk_en(regmap, 0xc1e4); /* CAM_CC_GDSC_CLK */
2869		− qcom_branch_set_clk_en(regmap, 0xc200); /* CAM_CC_SLEEP_CLK */
2870		−
2871		− ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sc8180x_desc, regmap);
2872		−
2873		− pm_runtime_put(&pdev->dev);
2874		−
2875		− return ret;
	2872	+ return qcom_cc_probe(pdev, &cam_cc_sc8180x_desc);
2876	2873	}
2877	2874
2878	2875	static struct platform_driver cam_cc_sc8180x_driver = {

drivers/clk/qcom/camcc-sm8450.c+2−2

@@ -2915,7 +2915,7 @@ static struct clk_alpha_pll *cam_cc_sm8450_plls[] = { · 2914 unmodified lines
2915	2915	&cam_cc_pll8,
2916	2916	};
2917	2917
2918		−static u32 cam_cc_sm8450_critical_cbcrs[] = {
	2918	+static const u32 cam_cc_sm8450_critical_cbcrs[] = {
2919	2919	0x1320c, /* CAM_CC_GDSC_CLK */
2920	2920	};
2921	2921
@@ -3030,7 +3030,7 @@ static struct gdsc *cam_cc_sm8450_gdscs[] = { · 108 unmodified lines
3030	3030	[TITAN_TOP_GDSC] = &titan_top_gdsc,
3031	3031	};
3032	3032
3033		−static struct qcom_cc_driver_data cam_cc_sm8450_driver_data = {
	3033	+static const struct qcom_cc_driver_data cam_cc_sm8450_driver_data = {
3034	3034	.alpha_plls = cam_cc_sm8450_plls,
3035	3035	.num_alpha_plls = ARRAY_SIZE(cam_cc_sm8450_plls),
3036	3036	.clk_cbcrs = cam_cc_sm8450_critical_cbcrs,

drivers/clk/qcom/camcc-sm8550.c+2−2

@@ -3517,7 +3517,7 @@ static struct clk_alpha_pll *cam_cc_sm8550_plls[] = { · 3516 unmodified lines
3517	3517	&cam_cc_pll12,
3518	3518	};
3519	3519
3520		−static u32 cam_cc_sm8550_critical_cbcrs[] = {
	3520	+static const u32 cam_cc_sm8550_critical_cbcrs[] = {
3521	3521	0x1419c, /* CAM_CC_GDSC_CLK */
3522	3522	0x142cc, /* CAM_CC_SLEEP_CLK */
3523	3523	};
@@ -3530,7 +3530,7 @@ static const struct regmap_config cam_cc_sm8550_regmap_config = { · 6 unmodified lines
3530	3530	.fast_io = true,
3531	3531	};
3532	3532
3533		−static struct qcom_cc_driver_data cam_cc_sm8550_driver_data = {
	3533	+static const struct qcom_cc_driver_data cam_cc_sm8550_driver_data = {
3534	3534	.alpha_plls = cam_cc_sm8550_plls,
3535	3535	.num_alpha_plls = ARRAY_SIZE(cam_cc_sm8550_plls),
3536	3536	.clk_cbcrs = cam_cc_sm8550_critical_cbcrs,

drivers/clk/qcom/camcc-sm8650.c+2−2

@@ -3533,7 +3533,7 @@ static struct clk_alpha_pll *cam_cc_sm8650_plls[] = { · 3532 unmodified lines
3533	3533	&cam_cc_pll10,
3534	3534	};
3535	3535
3536		−static u32 cam_cc_sm8650_critical_cbcrs[] = {
	3536	+static const u32 cam_cc_sm8650_critical_cbcrs[] = {
3537	3537	0x132ec, /* CAM_CC_GDSC_CLK */
3538	3538	0x13308, /* CAM_CC_SLEEP_CLK */
3539	3539	0x13314, /* CAM_CC_DRV_XO_CLK */
@@ -3548,7 +3548,7 @@ static const struct regmap_config cam_cc_sm8650_regmap_config = { · 8 unmodified lines
3548	3548	.fast_io = true,
3549	3549	};
3550	3550
3551		−static struct qcom_cc_driver_data cam_cc_sm8650_driver_data = {
	3551	+static const struct qcom_cc_driver_data cam_cc_sm8650_driver_data = {
3552	3552	.alpha_plls = cam_cc_sm8650_plls,
3553	3553	.num_alpha_plls = ARRAY_SIZE(cam_cc_sm8650_plls),
3554	3554	.clk_cbcrs = cam_cc_sm8650_critical_cbcrs,

drivers/clk/qcom/camcc-sm8750.c+2−2

@@ -2651,7 +2651,7 @@ static struct clk_alpha_pll *cam_cc_sm8750_plls[] = { · 2650 unmodified lines
2651	2651	&cam_cc_pll6,
2652	2652	};
2653	2653
2654		−static u32 cam_cc_sm8750_critical_cbcrs[] = {
	2654	+static const u32 cam_cc_sm8750_critical_cbcrs[] = {
2655	2655	0x113c4, /* CAM_CC_DRV_AHB_CLK */
2656	2656	0x113c0, /* CAM_CC_DRV_XO_CLK */
2657	2657	0x1137c, /* CAM_CC_GDSC_CLK */
@@ -2666,7 +2666,7 @@ static const struct regmap_config cam_cc_sm8750_regmap_config = { · 8 unmodified lines
2666	2666	.fast_io = true,
2667	2667	};
2668	2668
2669		−static struct qcom_cc_driver_data cam_cc_sm8750_driver_data = {
	2669	+static const struct qcom_cc_driver_data cam_cc_sm8750_driver_data = {
2670	2670	.alpha_plls = cam_cc_sm8750_plls,
2671	2671	.num_alpha_plls = ARRAY_SIZE(cam_cc_sm8750_plls),
2672	2672	.clk_cbcrs = cam_cc_sm8750_critical_cbcrs,

drivers/clk/qcom/camcc-x1e80100.c+2−2

@@ -2434,7 +2434,7 @@ static struct clk_alpha_pll *cam_cc_x1e80100_plls[] = { · 2433 unmodified lines
2434	2434	&cam_cc_pll8,
2435	2435	};
2436	2436
2437		−static u32 cam_cc_x1e80100_critical_cbcrs[] = {
	2437	+static const u32 cam_cc_x1e80100_critical_cbcrs[] = {
2438	2438	0x13a9c, /* CAM_CC_GDSC_CLK */
2439	2439	0x13ab8, /* CAM_CC_SLEEP_CLK */
2440	2440	};
@@ -2447,7 +2447,7 @@ static const struct regmap_config cam_cc_x1e80100_regmap_config = { · 6 unmodified lines
2447	2447	.fast_io = true,
2448	2448	};
2449	2449
2450		−static struct qcom_cc_driver_data cam_cc_x1e80100_driver_data = {
	2450	+static const struct qcom_cc_driver_data cam_cc_x1e80100_driver_data = {
2451	2451	.alpha_plls = cam_cc_x1e80100_plls,
2452	2452	.num_alpha_plls = ARRAY_SIZE(cam_cc_x1e80100_plls),
2453	2453	.clk_cbcrs = cam_cc_x1e80100_critical_cbcrs,

drivers/clk/qcom/clk-rcg2.c+2−0

@@ -1117,6 +1117,8 @@ static const struct frac_entry frac_table_pixel[] = { · 1116 unmodified lines
1117	1117	{ 4, 9 },
1118	1118	{ 1, 1 },
1119	1119	{ 2, 3 },
	1120	+ { 16, 35},
	1121	+ { 4, 15},
1120	1122	{ }
1121	1123	};
1122	1124

drivers/clk/qcom/clk-rpmh.c+46−0

@@ -349,6 +349,10 @@ DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 2); · 348 unmodified lines
349	349	DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 4);
350	350	DEFINE_CLK_RPMH_ARC(qlink, "qphy.lvl", 0x1, 4);
351	351
	352	+DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a1, "lnbclka1", 1);
	353	+DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a1, "lnbclka2", 1);
	354	+DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a1, "lnbclka3", 1);
	355	+
352	356	DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2, "lnbclka1", 2);
353	357	DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a2, "lnbclka2", 2);
354	358	DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2, "lnbclka3", 2);
@@ -372,6 +376,8 @@ DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1); · 17 unmodified lines
372	376	DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1);
373	377
374	378	DEFINE_CLK_RPMH_VRM(rf_clk3, _a2, "rfclka3", 2);
	379	+DEFINE_CLK_RPMH_VRM(rf_clk4, _a2, "rfclka4", 2);
	380	+DEFINE_CLK_RPMH_VRM(rf_clk5, _a2, "rfclka5", 2);
375	381
376	382	DEFINE_CLK_RPMH_VRM(clk1, _a1, "clka1", 1);
377	383	DEFINE_CLK_RPMH_VRM(clk2, _a1, "clka2", 1);
@@ -940,6 +946,44 @@ static const struct clk_rpmh_desc clk_rpmh_kaanapali = { · 562 unmodified lines
940	946	.num_clks = ARRAY_SIZE(kaanapali_rpmh_clocks),
941	947	};
942	948
	949	+static struct clk_hw *eliza_rpmh_clocks[] = {
	950	+ [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
	951	+ [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
	952	+ [RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw,
	953	+ [RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw,
	954	+ [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw,
	955	+ [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw,
	956	+ [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
	957	+ [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
	958	+ [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
	959	+ [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
	960	+ [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a2.hw,
	961	+ [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a2_ao.hw,
	962	+ [RPMH_RF_CLK5] = &clk_rpmh_rf_clk5_a2.hw,
	963	+ [RPMH_RF_CLK5_A] = &clk_rpmh_rf_clk5_a2_ao.hw,
	964	+ [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
	965	+};
	966	+
	967	+static const struct clk_rpmh_desc clk_rpmh_eliza = {
	968	+ .clks = eliza_rpmh_clocks,
	969	+ .num_clks = ARRAY_SIZE(eliza_rpmh_clocks),
	970	+};
	971	+
	972	+static struct clk_hw *nord_rpmh_clocks[] = {
	973	+ [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div1.hw,
	974	+ [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div1_ao.hw,
	975	+ [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a1.hw,
	976	+ [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a1_ao.hw,
	977	+ [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a1.hw,
	978	+ [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a1_ao.hw,
	979	+ [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
	980	+};
	981	+
	982	+static const struct clk_rpmh_desc clk_rpmh_nord = {
	983	+ .clks = nord_rpmh_clocks,
	984	+ .num_clks = ARRAY_SIZE(nord_rpmh_clocks),
	985	+};
	986	+
943	987	static struct clk_hw of_clk_rpmh_hw_get(struct of_phandle_args clkspec,
944	988	void *data)
945	989	{
@@ -1029,9 +1073,11 @@ static int clk_rpmh_probe(struct platform_device *pdev) · 83 unmodified lines
1029	1073	}
1030	1074
1031	1075	static const struct of_device_id clk_rpmh_match_table[] = {
	1076	+ { .compatible = "qcom,eliza-rpmh-clk", .data = &clk_rpmh_eliza},
1032	1077	{ .compatible = "qcom,glymur-rpmh-clk", .data = &clk_rpmh_glymur},
1033	1078	{ .compatible = "qcom,kaanapali-rpmh-clk", .data = &clk_rpmh_kaanapali},
1034	1079	{ .compatible = "qcom,milos-rpmh-clk", .data = &clk_rpmh_milos},
	1080	+ { .compatible = "qcom,nord-rpmh-clk", .data = &clk_rpmh_nord},
1035	1081	{ .compatible = "qcom,qcs615-rpmh-clk", .data = &clk_rpmh_qcs615},
1036	1082	{ .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000},
1037	1083	{ .compatible = "qcom,sa8775p-rpmh-clk", .data = &clk_rpmh_sa8775p},

drivers/clk/qcom/common.h+2−2

@@ -28,7 +28,7 @@ struct qcom_icc_hws_data { · 27 unmodified lines
28	28	struct qcom_cc_driver_data {
29	29	struct clk_alpha_pll **alpha_plls;
30	30	size_t num_alpha_plls;
31		− u32 *clk_cbcrs;
	31	+ const u32 *clk_cbcrs;
32	32	size_t num_clk_cbcrs;
33	33	const struct clk_rcg_dfs_data *dfs_rcgs;
34	34	size_t num_dfs_rcgs;
@@ -49,7 +49,7 @@ struct qcom_cc_desc { · 14 unmodified lines
49	49	size_t num_icc_hws;
50	50	unsigned int icc_first_node_id;
51	51	bool use_rpm;
52		− struct qcom_cc_driver_data *driver_data;
	52	+ const struct qcom_cc_driver_data *driver_data;
53	53	};
54	54
55	55	/**

drivers/clk/qcom/dispcc-eliza.c+2121−0

@@ -0,0 +1,2121 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
	2	+/*
	3	+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
	4	+ * Copyright (c) 2023-2024, Linaro Ltd.
	5	+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
	6	+ */
	7	+
	8	+#include <linux/clk-provider.h>
	9	+#include <linux/kernel.h>
	10	+#include <linux/mod_devicetable.h>
	11	+#include <linux/module.h>
	12	+#include <linux/platform_device.h>
	13	+#include <linux/regmap.h>
	14	+
	15	+#include <dt-bindings/clock/qcom,eliza-dispcc.h>
	16	+
	17	+#include "common.h"
	18	+#include "clk-alpha-pll.h"
	19	+#include "clk-branch.h"
	20	+#include "clk-pll.h"
	21	+#include "clk-rcg.h"
	22	+#include "clk-regmap.h"
	23	+#include "clk-regmap-divider.h"
	24	+#include "clk-regmap-mux.h"
	25	+#include "gdsc.h"
	26	+#include "reset.h"
	27	+
	28	+/* Need to match the order of clocks in DT binding */
	29	+enum {
	30	+ DT_BI_TCXO,
	31	+ DT_BI_TCXO_AO,
	32	+ DT_AHB_CLK,
	33	+ DT_SLEEP_CLK,
	34	+
	35	+ DT_DSI0_PHY_PLL_OUT_BYTECLK,
	36	+ DT_DSI0_PHY_PLL_OUT_DSICLK,
	37	+ DT_DSI1_PHY_PLL_OUT_BYTECLK,
	38	+ DT_DSI1_PHY_PLL_OUT_DSICLK,
	39	+
	40	+ DT_DP0_PHY_PLL_LINK_CLK,
	41	+ DT_DP0_PHY_PLL_VCO_DIV_CLK,
	42	+ DT_DP1_PHY_PLL_LINK_CLK,
	43	+ DT_DP1_PHY_PLL_VCO_DIV_CLK,
	44	+ DT_DP2_PHY_PLL_LINK_CLK,
	45	+ DT_DP2_PHY_PLL_VCO_DIV_CLK,
	46	+ DT_DP3_PHY_PLL_LINK_CLK,
	47	+ DT_DP3_PHY_PLL_VCO_DIV_CLK,
	48	+ DT_HDMI_PHY_PLL_CLK,
	49	+};
	50	+
	51	+#define DISP_CC_MISC_CMD 0xF000
	52	+
	53	+enum {
	54	+ P_BI_TCXO,
	55	+ P_DISP_CC_PLL0_OUT_MAIN,
	56	+ P_DISP_CC_PLL1_OUT_EVEN,
	57	+ P_DISP_CC_PLL1_OUT_MAIN,
	58	+ P_DISP_CC_PLL2_OUT_MAIN,
	59	+ P_DP0_PHY_PLL_LINK_CLK,
	60	+ P_DP0_PHY_PLL_VCO_DIV_CLK,
	61	+ P_DP1_PHY_PLL_LINK_CLK,
	62	+ P_DP1_PHY_PLL_VCO_DIV_CLK,
	63	+ P_DP2_PHY_PLL_LINK_CLK,
	64	+ P_DP2_PHY_PLL_VCO_DIV_CLK,
	65	+ P_DP3_PHY_PLL_LINK_CLK,
	66	+ P_DP3_PHY_PLL_VCO_DIV_CLK,
	67	+ P_DSI0_PHY_PLL_OUT_BYTECLK,
	68	+ P_DSI0_PHY_PLL_OUT_DSICLK,
	69	+ P_DSI1_PHY_PLL_OUT_BYTECLK,
	70	+ P_DSI1_PHY_PLL_OUT_DSICLK,
	71	+ P_HDMI_PHY_PLL_CLK,
	72	+ P_SLEEP_CLK,
	73	+};
	74	+
	75	+static const struct pll_vco lucid_ole_vco[] = {
	76	+ { 249600000, 2300000000, 0 },
	77	+};
	78	+
	79	+static const struct pll_vco pongo_ole_vco[] = {
	80	+ { 38400000, 38400000, 0 },
	81	+};
	82	+
	83	+static struct alpha_pll_config disp_cc_pll0_config = {
	84	+ .l = 0xd,
	85	+ .cal_l = 0x44,
	86	+ .alpha = 0x6492,
	87	+ .config_ctl_val = 0x20485699,
	88	+ .config_ctl_hi_val = 0x00182261,
	89	+ .config_ctl_hi1_val = 0x82aa299c,
	90	+ .test_ctl_val = 0x00000000,
	91	+ .test_ctl_hi_val = 0x00000003,
	92	+ .test_ctl_hi1_val = 0x00009000,
	93	+ .test_ctl_hi2_val = 0x00000034,
	94	+ .user_ctl_val = 0x00000000,
	95	+ .user_ctl_hi_val = 0x00000005,
	96	+};
	97	+
	98	+static struct clk_alpha_pll disp_cc_pll0 = {
	99	+ .offset = 0x0,
	100	+ .config = &disp_cc_pll0_config,
	101	+ .vco_table = lucid_ole_vco,
	102	+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
	103	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
	104	+ .clkr = {
	105	+ .hw.init = &(const struct clk_init_data) {
	106	+ .name = "disp_cc_pll0",
	107	+ .parent_data = &(const struct clk_parent_data) {
	108	+ .index = DT_BI_TCXO,
	109	+ },
	110	+ .num_parents = 1,
	111	+ .ops = &clk_alpha_pll_lucid_evo_ops,
	112	+ },
	113	+ },
	114	+};
	115	+
	116	+static struct alpha_pll_config disp_cc_pll1_config = {
	117	+ .l = 0x1f,
	118	+ .cal_l = 0x44,
	119	+ .alpha = 0x4000,
	120	+ .config_ctl_val = 0x20485699,
	121	+ .config_ctl_hi_val = 0x00182261,
	122	+ .config_ctl_hi1_val = 0x82aa299c,
	123	+ .test_ctl_val = 0x00000000,
	124	+ .test_ctl_hi_val = 0x00000003,
	125	+ .test_ctl_hi1_val = 0x00009000,
	126	+ .test_ctl_hi2_val = 0x00000034,
	127	+ .user_ctl_val = 0x00000000,
	128	+ .user_ctl_hi_val = 0x00000005,
	129	+};
	130	+
	131	+static struct clk_alpha_pll disp_cc_pll1 = {
	132	+ .offset = 0x1000,
	133	+ .config = &disp_cc_pll1_config,
	134	+ .vco_table = lucid_ole_vco,
	135	+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
	136	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
	137	+ .clkr = {
	138	+ .hw.init = &(const struct clk_init_data) {
	139	+ .name = "disp_cc_pll1",
	140	+ .parent_data = &(const struct clk_parent_data) {
	141	+ .index = DT_BI_TCXO,
	142	+ },
	143	+ .num_parents = 1,
	144	+ .ops = &clk_alpha_pll_lucid_evo_ops,
	145	+ },
	146	+ },
	147	+};
	148	+
	149	+static const struct alpha_pll_config disp_cc_pll2_config = {
	150	+ .l = 0x493,
	151	+ .cal_l = 0x493,
	152	+ .alpha = 0x0,
	153	+ .config_ctl_val = 0x60000f6a,
	154	+ .config_ctl_hi_val = 0x0001c808,
	155	+ .config_ctl_hi1_val = 0x00000000,
	156	+ .config_ctl_hi2_val = 0x04008174,
	157	+ .test_ctl_val = 0x00000000,
	158	+ .test_ctl_hi_val = 0x0080c496,
	159	+ .test_ctl_hi1_val = 0x40100180,
	160	+ .test_ctl_hi2_val = 0x441001bc,
	161	+ .test_ctl_hi3_val = 0x000003d8,
	162	+ .user_ctl_val = 0x00000000,
	163	+ .user_ctl_hi_val = 0x00e50302,
	164	+};
	165	+
	166	+static struct clk_alpha_pll disp_cc_pll2 = {
	167	+ .offset = 0x2000,
	168	+ .config = &disp_cc_pll2_config,
	169	+ .vco_table = pongo_ole_vco,
	170	+ .num_vco = ARRAY_SIZE(pongo_ole_vco),
	171	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_PONGO_ELU],
	172	+ .clkr = {
	173	+ .hw.init = &(const struct clk_init_data) {
	174	+ .name = "disp_cc_pll2",
	175	+ .parent_data = &(const struct clk_parent_data) {
	176	+ .index = DT_SLEEP_CLK,
	177	+ },
	178	+ .num_parents = 1,
	179	+ .ops = &clk_alpha_pll_pongo_elu_ops,
	180	+ },
	181	+ },
	182	+};
	183	+
	184	+static const struct parent_map disp_cc_parent_map_0[] = {
	185	+ { P_BI_TCXO, 0 },
	186	+};
	187	+
	188	+static const struct clk_parent_data disp_cc_parent_data_0[] = {
	189	+ { .index = DT_BI_TCXO },
	190	+};
	191	+
	192	+static const struct clk_parent_data disp_cc_parent_data_0_ao[] = {
	193	+ { .index = DT_BI_TCXO_AO },
	194	+};
	195	+
	196	+static const struct parent_map disp_cc_parent_map_1[] = {
	197	+ { P_BI_TCXO, 0 },
	198	+ { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
	199	+ { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
	200	+ { P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
	201	+ { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
	202	+};
	203	+
	204	+static const struct clk_parent_data disp_cc_parent_data_1[] = {
	205	+ { .index = DT_BI_TCXO },
	206	+ { .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
	207	+ { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
	208	+ { .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
	209	+ { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
	210	+};
	211	+
	212	+static const struct parent_map disp_cc_parent_map_2[] = {
	213	+ { P_BI_TCXO, 0 },
	214	+ { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
	215	+ { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
	216	+ { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
	217	+};
	218	+
	219	+static const struct clk_parent_data disp_cc_parent_data_2[] = {
	220	+ { .index = DT_BI_TCXO },
	221	+ { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
	222	+ { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
	223	+ { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
	224	+};
	225	+
	226	+static const struct parent_map disp_cc_parent_map_3[] = {
	227	+ { P_BI_TCXO, 0 },
	228	+ { P_DP1_PHY_PLL_LINK_CLK, 2 },
	229	+ { P_DP2_PHY_PLL_LINK_CLK, 3 },
	230	+ { P_DP3_PHY_PLL_LINK_CLK, 4 },
	231	+};
	232	+
	233	+static const struct clk_parent_data disp_cc_parent_data_3[] = {
	234	+ { .index = DT_BI_TCXO },
	235	+ { .index = DT_DP1_PHY_PLL_LINK_CLK },
	236	+ { .index = DT_DP2_PHY_PLL_LINK_CLK },
	237	+ { .index = DT_DP3_PHY_PLL_LINK_CLK },
	238	+};
	239	+
	240	+static const struct parent_map disp_cc_parent_map_4[] = {
	241	+ { P_BI_TCXO, 0 },
	242	+ { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
	243	+ { P_DISP_CC_PLL2_OUT_MAIN, 2 },
	244	+ { P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
	245	+};
	246	+
	247	+static const struct clk_parent_data disp_cc_parent_data_4[] = {
	248	+ { .index = DT_BI_TCXO },
	249	+ { .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
	250	+ { .hw = &disp_cc_pll2.clkr.hw },
	251	+ { .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
	252	+};
	253	+
	254	+static const struct parent_map disp_cc_parent_map_5[] = {
	255	+ { P_BI_TCXO, 0 },
	256	+ { P_DP0_PHY_PLL_LINK_CLK, 1 },
	257	+ { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },
	258	+ { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
	259	+ { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
	260	+ { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
	261	+};
	262	+
	263	+static const struct clk_parent_data disp_cc_parent_data_5[] = {
	264	+ { .index = DT_BI_TCXO },
	265	+ { .index = DT_DP0_PHY_PLL_LINK_CLK },
	266	+ { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK },
	267	+ { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
	268	+ { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
	269	+ { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
	270	+};
	271	+
	272	+static const struct parent_map disp_cc_parent_map_6[] = {
	273	+ { P_BI_TCXO, 0 },
	274	+ { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
	275	+ { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
	276	+};
	277	+
	278	+static const struct clk_parent_data disp_cc_parent_data_6[] = {
	279	+ { .index = DT_BI_TCXO },
	280	+ { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
	281	+ { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
	282	+};
	283	+
	284	+static const struct parent_map disp_cc_parent_map_7[] = {
	285	+ { P_BI_TCXO, 0 },
	286	+ { P_DISP_CC_PLL1_OUT_MAIN, 4 },
	287	+ { P_DISP_CC_PLL1_OUT_EVEN, 6 },
	288	+};
	289	+
	290	+static const struct clk_parent_data disp_cc_parent_data_7[] = {
	291	+ { .index = DT_BI_TCXO },
	292	+ { .hw = &disp_cc_pll1.clkr.hw },
	293	+ { .hw = &disp_cc_pll1.clkr.hw },
	294	+};
	295	+
	296	+static const struct parent_map disp_cc_parent_map_8[] = {
	297	+ { P_BI_TCXO, 0 },
	298	+ { P_DP0_PHY_PLL_LINK_CLK, 1 },
	299	+ { P_DP1_PHY_PLL_LINK_CLK, 2 },
	300	+ { P_DP2_PHY_PLL_LINK_CLK, 3 },
	301	+ { P_DP3_PHY_PLL_LINK_CLK, 4 },
	302	+};
	303	+
	304	+static const struct clk_parent_data disp_cc_parent_data_8[] = {
	305	+ { .index = DT_BI_TCXO },
	306	+ { .index = DT_DP0_PHY_PLL_LINK_CLK },
	307	+ { .index = DT_DP1_PHY_PLL_LINK_CLK },
	308	+ { .index = DT_DP2_PHY_PLL_LINK_CLK },
	309	+ { .index = DT_DP3_PHY_PLL_LINK_CLK },
	310	+};
	311	+
	312	+static const struct parent_map disp_cc_parent_map_9[] = {
	313	+ { P_BI_TCXO, 0 },
	314	+ { P_DISP_CC_PLL0_OUT_MAIN, 1 },
	315	+};
	316	+
	317	+static const struct clk_parent_data disp_cc_parent_data_9[] = {
	318	+ { .index = DT_BI_TCXO },
	319	+ { .hw = &disp_cc_pll0.clkr.hw },
	320	+};
	321	+
	322	+static const struct parent_map disp_cc_parent_map_10[] = {
	323	+ { P_BI_TCXO, 0 },
	324	+ { P_HDMI_PHY_PLL_CLK, 1 },
	325	+};
	326	+
	327	+static const struct clk_parent_data disp_cc_parent_data_10[] = {
	328	+ { .index = DT_BI_TCXO },
	329	+ { .index = DT_HDMI_PHY_PLL_CLK },
	330	+};
	331	+
	332	+static const struct parent_map disp_cc_parent_map_11[] = {
	333	+ { P_BI_TCXO, 0 },
	334	+ { P_DISP_CC_PLL0_OUT_MAIN, 1 },
	335	+ { P_DISP_CC_PLL1_OUT_MAIN, 4 },
	336	+ { P_DISP_CC_PLL1_OUT_EVEN, 6 },
	337	+};
	338	+
	339	+static const struct clk_parent_data disp_cc_parent_data_11[] = {
	340	+ { .index = DT_BI_TCXO },
	341	+ { .hw = &disp_cc_pll0.clkr.hw },
	342	+ { .hw = &disp_cc_pll1.clkr.hw },
	343	+ { .hw = &disp_cc_pll1.clkr.hw },
	344	+};
	345	+
	346	+static const struct parent_map disp_cc_parent_map_12[] = {
	347	+ { P_BI_TCXO, 0 },
	348	+ { P_DISP_CC_PLL2_OUT_MAIN, 2 },
	349	+};
	350	+
	351	+static const struct clk_parent_data disp_cc_parent_data_12[] = {
	352	+ { .index = DT_BI_TCXO },
	353	+ { .hw = &disp_cc_pll2.clkr.hw },
	354	+};
	355	+
	356	+static const struct parent_map disp_cc_parent_map_13[] = {
	357	+ { P_SLEEP_CLK, 0 },
	358	+};
	359	+
	360	+static const struct clk_parent_data disp_cc_parent_data_13_ao[] = {
	361	+ { .index = DT_SLEEP_CLK },
	362	+};
	363	+
	364	+static const struct freq_tbl ftbl_disp_cc_esync0_clk_src[] = {
	365	+ F(19200000, P_BI_TCXO, 1, 0, 0),
	366	+ { }
	367	+};
	368	+
	369	+static struct clk_rcg2 disp_cc_esync0_clk_src = {
	370	+ .cmd_rcgr = 0x80c0,
	371	+ .mnd_width = 16,
	372	+ .hid_width = 5,
	373	+ .parent_map = disp_cc_parent_map_4,
	374	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	375	+ .clkr.hw.init = &(const struct clk_init_data) {
	376	+ .name = "disp_cc_esync0_clk_src",
	377	+ .parent_data = disp_cc_parent_data_4,
	378	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
	379	+ .flags = CLK_SET_RATE_PARENT,
	380	+ .ops = &clk_byte2_ops,
	381	+ },
	382	+};
	383	+
	384	+static struct clk_rcg2 disp_cc_esync1_clk_src = {
	385	+ .cmd_rcgr = 0x80d8,
	386	+ .mnd_width = 16,
	387	+ .hid_width = 5,
	388	+ .parent_map = disp_cc_parent_map_4,
	389	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	390	+ .clkr.hw.init = &(const struct clk_init_data) {
	391	+ .name = "disp_cc_esync1_clk_src",
	392	+ .parent_data = disp_cc_parent_data_4,
	393	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
	394	+ .flags = CLK_SET_RATE_PARENT,
	395	+ .ops = &clk_byte2_ops,
	396	+ },
	397	+};
	398	+
	399	+static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
	400	+ F(19200000, P_BI_TCXO, 1, 0, 0),
	401	+ F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
	402	+ F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
	403	+ { }
	404	+};
	405	+
	406	+static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
	407	+ .cmd_rcgr = 0x8360,
	408	+ .mnd_width = 0,
	409	+ .hid_width = 5,
	410	+ .parent_map = disp_cc_parent_map_7,
	411	+ .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
	412	+ .clkr.hw.init = &(const struct clk_init_data) {
	413	+ .name = "disp_cc_mdss_ahb_clk_src",
	414	+ .parent_data = disp_cc_parent_data_7,
	415	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
	416	+ .flags = CLK_SET_RATE_PARENT,
	417	+ .ops = &clk_rcg2_shared_ops,
	418	+ },
	419	+};
	420	+
	421	+static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
	422	+ .cmd_rcgr = 0x8180,
	423	+ .mnd_width = 0,
	424	+ .hid_width = 5,
	425	+ .parent_map = disp_cc_parent_map_1,
	426	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	427	+ .clkr.hw.init = &(const struct clk_init_data) {
	428	+ .name = "disp_cc_mdss_byte0_clk_src",
	429	+ .parent_data = disp_cc_parent_data_1,
	430	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
	431	+ .flags = CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
	432	+ .ops = &clk_byte2_ops,
	433	+ },
	434	+};
	435	+
	436	+static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
	437	+ .cmd_rcgr = 0x819c,
	438	+ .mnd_width = 0,
	439	+ .hid_width = 5,
	440	+ .parent_map = disp_cc_parent_map_1,
	441	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	442	+ .clkr.hw.init = &(const struct clk_init_data) {
	443	+ .name = "disp_cc_mdss_byte1_clk_src",
	444	+ .parent_data = disp_cc_parent_data_1,
	445	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
	446	+ .flags = CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
	447	+ .ops = &clk_byte2_ops,
	448	+ },
	449	+};
	450	+
	451	+static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {
	452	+ .cmd_rcgr = 0x8234,
	453	+ .mnd_width = 0,
	454	+ .hid_width = 5,
	455	+ .parent_map = disp_cc_parent_map_0,
	456	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	457	+ .clkr.hw.init = &(const struct clk_init_data) {
	458	+ .name = "disp_cc_mdss_dptx0_aux_clk_src",
	459	+ .parent_data = disp_cc_parent_data_0,
	460	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
	461	+ .flags = CLK_SET_RATE_PARENT,
	462	+ .ops = &clk_rcg2_ops,
	463	+ },
	464	+};
	465	+
	466	+static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
	467	+ .cmd_rcgr = 0x81e8,
	468	+ .mnd_width = 0,
	469	+ .hid_width = 5,
	470	+ .parent_map = disp_cc_parent_map_8,
	471	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	472	+ .clkr.hw.init = &(const struct clk_init_data) {
	473	+ .name = "disp_cc_mdss_dptx0_link_clk_src",
	474	+ .parent_data = disp_cc_parent_data_8,
	475	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_8),
	476	+ .flags = CLK_SET_RATE_PARENT,
	477	+ .ops = &clk_byte2_ops,
	478	+ },
	479	+};
	480	+
	481	+static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = {
	482	+ .cmd_rcgr = 0x8204,
	483	+ .mnd_width = 16,
	484	+ .hid_width = 5,
	485	+ .parent_map = disp_cc_parent_map_5,
	486	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	487	+ .clkr.hw.init = &(const struct clk_init_data) {
	488	+ .name = "disp_cc_mdss_dptx0_pixel0_clk_src",
	489	+ .parent_data = disp_cc_parent_data_5,
	490	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
	491	+ .flags = CLK_SET_RATE_PARENT,
	492	+ .ops = &clk_dp_ops,
	493	+ },
	494	+};
	495	+
	496	+static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = {
	497	+ .cmd_rcgr = 0x821c,
	498	+ .mnd_width = 16,
	499	+ .hid_width = 5,
	500	+ .parent_map = disp_cc_parent_map_5,
	501	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	502	+ .clkr.hw.init = &(const struct clk_init_data) {
	503	+ .name = "disp_cc_mdss_dptx0_pixel1_clk_src",
	504	+ .parent_data = disp_cc_parent_data_5,
	505	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
	506	+ .flags = CLK_SET_RATE_PARENT,
	507	+ .ops = &clk_dp_ops,
	508	+ },
	509	+};
	510	+
	511	+static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = {
	512	+ .cmd_rcgr = 0x8298,
	513	+ .mnd_width = 0,
	514	+ .hid_width = 5,
	515	+ .parent_map = disp_cc_parent_map_0,
	516	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	517	+ .clkr.hw.init = &(const struct clk_init_data) {
	518	+ .name = "disp_cc_mdss_dptx1_aux_clk_src",
	519	+ .parent_data = disp_cc_parent_data_0,
	520	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
	521	+ .flags = CLK_SET_RATE_PARENT,
	522	+ .ops = &clk_rcg2_ops,
	523	+ },
	524	+};
	525	+
	526	+static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {
	527	+ .cmd_rcgr = 0x827c,
	528	+ .mnd_width = 0,
	529	+ .hid_width = 5,
	530	+ .parent_map = disp_cc_parent_map_3,
	531	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	532	+ .clkr.hw.init = &(const struct clk_init_data) {
	533	+ .name = "disp_cc_mdss_dptx1_link_clk_src",
	534	+ .parent_data = disp_cc_parent_data_3,
	535	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
	536	+ .flags = CLK_SET_RATE_PARENT,
	537	+ .ops = &clk_byte2_ops,
	538	+ },
	539	+};
	540	+
	541	+static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = {
	542	+ .cmd_rcgr = 0x824c,
	543	+ .mnd_width = 16,
	544	+ .hid_width = 5,
	545	+ .parent_map = disp_cc_parent_map_2,
	546	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	547	+ .clkr.hw.init = &(const struct clk_init_data) {
	548	+ .name = "disp_cc_mdss_dptx1_pixel0_clk_src",
	549	+ .parent_data = disp_cc_parent_data_2,
	550	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
	551	+ .flags = CLK_SET_RATE_PARENT,
	552	+ .ops = &clk_dp_ops,
	553	+ },
	554	+};
	555	+
	556	+static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = {
	557	+ .cmd_rcgr = 0x8264,
	558	+ .mnd_width = 16,
	559	+ .hid_width = 5,
	560	+ .parent_map = disp_cc_parent_map_2,
	561	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	562	+ .clkr.hw.init = &(const struct clk_init_data) {
	563	+ .name = "disp_cc_mdss_dptx1_pixel1_clk_src",
	564	+ .parent_data = disp_cc_parent_data_2,
	565	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
	566	+ .flags = CLK_SET_RATE_PARENT,
	567	+ .ops = &clk_dp_ops,
	568	+ },
	569	+};
	570	+
	571	+static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = {
	572	+ .cmd_rcgr = 0x82fc,
	573	+ .mnd_width = 0,
	574	+ .hid_width = 5,
	575	+ .parent_map = disp_cc_parent_map_0,
	576	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	577	+ .clkr.hw.init = &(const struct clk_init_data) {
	578	+ .name = "disp_cc_mdss_dptx2_aux_clk_src",
	579	+ .parent_data = disp_cc_parent_data_0,
	580	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
	581	+ .flags = CLK_SET_RATE_PARENT,
	582	+ .ops = &clk_rcg2_ops,
	583	+ },
	584	+};
	585	+
	586	+static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {
	587	+ .cmd_rcgr = 0x82b0,
	588	+ .mnd_width = 0,
	589	+ .hid_width = 5,
	590	+ .parent_map = disp_cc_parent_map_3,
	591	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	592	+ .clkr.hw.init = &(const struct clk_init_data) {
	593	+ .name = "disp_cc_mdss_dptx2_link_clk_src",
	594	+ .parent_data = disp_cc_parent_data_3,
	595	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
	596	+ .flags = CLK_SET_RATE_PARENT,
	597	+ .ops = &clk_byte2_ops,
	598	+ },
	599	+};
	600	+
	601	+static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = {
	602	+ .cmd_rcgr = 0x82cc,
	603	+ .mnd_width = 16,
	604	+ .hid_width = 5,
	605	+ .parent_map = disp_cc_parent_map_2,
	606	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	607	+ .clkr.hw.init = &(const struct clk_init_data) {
	608	+ .name = "disp_cc_mdss_dptx2_pixel0_clk_src",
	609	+ .parent_data = disp_cc_parent_data_2,
	610	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
	611	+ .flags = CLK_SET_RATE_PARENT,
	612	+ .ops = &clk_dp_ops,
	613	+ },
	614	+};
	615	+
	616	+static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = {
	617	+ .cmd_rcgr = 0x82e4,
	618	+ .mnd_width = 16,
	619	+ .hid_width = 5,
	620	+ .parent_map = disp_cc_parent_map_2,
	621	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	622	+ .clkr.hw.init = &(const struct clk_init_data) {
	623	+ .name = "disp_cc_mdss_dptx2_pixel1_clk_src",
	624	+ .parent_data = disp_cc_parent_data_2,
	625	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
	626	+ .flags = CLK_SET_RATE_PARENT,
	627	+ .ops = &clk_dp_ops,
	628	+ },
	629	+};
	630	+
	631	+static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = {
	632	+ .cmd_rcgr = 0x8348,
	633	+ .mnd_width = 0,
	634	+ .hid_width = 5,
	635	+ .parent_map = disp_cc_parent_map_0,
	636	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	637	+ .clkr.hw.init = &(const struct clk_init_data) {
	638	+ .name = "disp_cc_mdss_dptx3_aux_clk_src",
	639	+ .parent_data = disp_cc_parent_data_0,
	640	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
	641	+ .flags = CLK_SET_RATE_PARENT,
	642	+ .ops = &clk_rcg2_ops,
	643	+ },
	644	+};
	645	+
	646	+static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {
	647	+ .cmd_rcgr = 0x832c,
	648	+ .mnd_width = 0,
	649	+ .hid_width = 5,
	650	+ .parent_map = disp_cc_parent_map_3,
	651	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	652	+ .clkr.hw.init = &(const struct clk_init_data) {
	653	+ .name = "disp_cc_mdss_dptx3_link_clk_src",
	654	+ .parent_data = disp_cc_parent_data_3,
	655	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
	656	+ .flags = CLK_SET_RATE_PARENT,
	657	+ .ops = &clk_byte2_ops,
	658	+ },
	659	+};
	660	+
	661	+static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = {
	662	+ .cmd_rcgr = 0x8314,
	663	+ .mnd_width = 16,
	664	+ .hid_width = 5,
	665	+ .parent_map = disp_cc_parent_map_2,
	666	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	667	+ .clkr.hw.init = &(const struct clk_init_data) {
	668	+ .name = "disp_cc_mdss_dptx3_pixel0_clk_src",
	669	+ .parent_data = disp_cc_parent_data_2,
	670	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
	671	+ .flags = CLK_SET_RATE_PARENT,
	672	+ .ops = &clk_dp_ops,
	673	+ },
	674	+};
	675	+
	676	+static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
	677	+ .cmd_rcgr = 0x81b8,
	678	+ .mnd_width = 0,
	679	+ .hid_width = 5,
	680	+ .parent_map = disp_cc_parent_map_6,
	681	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	682	+ .clkr.hw.init = &(const struct clk_init_data) {
	683	+ .name = "disp_cc_mdss_esc0_clk_src",
	684	+ .parent_data = disp_cc_parent_data_6,
	685	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
	686	+ .flags = CLK_SET_RATE_PARENT,
	687	+ .ops = &clk_rcg2_shared_ops,
	688	+ },
	689	+};
	690	+
	691	+static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
	692	+ .cmd_rcgr = 0x81d0,
	693	+ .mnd_width = 0,
	694	+ .hid_width = 5,
	695	+ .parent_map = disp_cc_parent_map_6,
	696	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	697	+ .clkr.hw.init = &(const struct clk_init_data) {
	698	+ .name = "disp_cc_mdss_esc1_clk_src",
	699	+ .parent_data = disp_cc_parent_data_6,
	700	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
	701	+ .flags = CLK_SET_RATE_PARENT,
	702	+ .ops = &clk_rcg2_shared_ops,
	703	+ },
	704	+};
	705	+
	706	+static struct clk_rcg2 disp_cc_mdss_hdmi_app_clk_src = {
	707	+ .cmd_rcgr = 0x83a8,
	708	+ .mnd_width = 0,
	709	+ .hid_width = 5,
	710	+ .parent_map = disp_cc_parent_map_9,
	711	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	712	+ .clkr.hw.init = &(const struct clk_init_data) {
	713	+ .name = "disp_cc_mdss_hdmi_app_clk_src",
	714	+ .parent_data = disp_cc_parent_data_9,
	715	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_9),
	716	+ .flags = CLK_SET_RATE_PARENT,
	717	+ .ops = &clk_rcg2_shared_ops,
	718	+ },
	719	+};
	720	+
	721	+static struct clk_rcg2 disp_cc_mdss_hdmi_pclk_clk_src = {
	722	+ .cmd_rcgr = 0x8390,
	723	+ .mnd_width = 16,
	724	+ .hid_width = 5,
	725	+ .parent_map = disp_cc_parent_map_10,
	726	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	727	+ .clkr.hw.init = &(const struct clk_init_data) {
	728	+ .name = "disp_cc_mdss_hdmi_pclk_clk_src",
	729	+ .parent_data = disp_cc_parent_data_10,
	730	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_10),
	731	+ .flags = CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
	732	+ .ops = &clk_pixel_ops,
	733	+ },
	734	+};
	735	+
	736	+static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
	737	+ F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
	738	+ F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
	739	+ F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
	740	+ F(207000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
	741	+ F(342000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
	742	+ F(417000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
	743	+ F(535000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
	744	+ F(600000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
	745	+ F(660000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
	746	+ { }
	747	+};
	748	+
	749	+static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
	750	+ .cmd_rcgr = 0x8150,
	751	+ .mnd_width = 0,
	752	+ .hid_width = 5,
	753	+ .parent_map = disp_cc_parent_map_11,
	754	+ .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
	755	+ .clkr.hw.init = &(const struct clk_init_data) {
	756	+ .name = "disp_cc_mdss_mdp_clk_src",
	757	+ .parent_data = disp_cc_parent_data_11,
	758	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_11),
	759	+ .flags = CLK_SET_RATE_PARENT,
	760	+ .ops = &clk_rcg2_shared_ops,
	761	+ },
	762	+};
	763	+
	764	+static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
	765	+ .cmd_rcgr = 0x8108,
	766	+ .mnd_width = 8,
	767	+ .hid_width = 5,
	768	+ .parent_map = disp_cc_parent_map_1,
	769	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	770	+ .clkr.hw.init = &(const struct clk_init_data) {
	771	+ .name = "disp_cc_mdss_pclk0_clk_src",
	772	+ .parent_data = disp_cc_parent_data_1,
	773	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
	774	+ .flags = CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
	775	+ .ops = &clk_pixel_ops,
	776	+ },
	777	+};
	778	+
	779	+static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
	780	+ .cmd_rcgr = 0x8120,
	781	+ .mnd_width = 8,
	782	+ .hid_width = 5,
	783	+ .parent_map = disp_cc_parent_map_1,
	784	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	785	+ .clkr.hw.init = &(const struct clk_init_data) {
	786	+ .name = "disp_cc_mdss_pclk1_clk_src",
	787	+ .parent_data = disp_cc_parent_data_1,
	788	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
	789	+ .flags = CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
	790	+ .ops = &clk_pixel_ops,
	791	+ },
	792	+};
	793	+
	794	+static struct clk_rcg2 disp_cc_mdss_pclk2_clk_src = {
	795	+ .cmd_rcgr = 0x8138,
	796	+ .mnd_width = 8,
	797	+ .hid_width = 5,
	798	+ .parent_map = disp_cc_parent_map_1,
	799	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	800	+ .clkr.hw.init = &(const struct clk_init_data) {
	801	+ .name = "disp_cc_mdss_pclk2_clk_src",
	802	+ .parent_data = disp_cc_parent_data_1,
	803	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
	804	+ .flags = CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
	805	+ .ops = &clk_pixel_ops,
	806	+ },
	807	+};
	808	+
	809	+static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
	810	+ .cmd_rcgr = 0x8168,
	811	+ .mnd_width = 0,
	812	+ .hid_width = 5,
	813	+ .parent_map = disp_cc_parent_map_0,
	814	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	815	+ .clkr.hw.init = &(const struct clk_init_data) {
	816	+ .name = "disp_cc_mdss_vsync_clk_src",
	817	+ .parent_data = disp_cc_parent_data_0,
	818	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
	819	+ .flags = CLK_SET_RATE_PARENT,
	820	+ .ops = &clk_rcg2_ops,
	821	+ },
	822	+};
	823	+
	824	+static const struct freq_tbl ftbl_disp_cc_osc_clk_src[] = {
	825	+ F(38400000, P_DISP_CC_PLL2_OUT_MAIN, 1, 0, 0),
	826	+ { }
	827	+};
	828	+
	829	+static struct clk_rcg2 disp_cc_osc_clk_src = {
	830	+ .cmd_rcgr = 0x80f0,
	831	+ .mnd_width = 0,
	832	+ .hid_width = 5,
	833	+ .parent_map = disp_cc_parent_map_12,
	834	+ .freq_tbl = ftbl_disp_cc_osc_clk_src,
	835	+ .clkr.hw.init = &(const struct clk_init_data) {
	836	+ .name = "disp_cc_osc_clk_src",
	837	+ .parent_data = disp_cc_parent_data_12,
	838	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_12),
	839	+ .flags = CLK_SET_RATE_PARENT,
	840	+ .ops = &clk_rcg2_ops,
	841	+ },
	842	+};
	843	+
	844	+static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
	845	+ F(32000, P_SLEEP_CLK, 1, 0, 0),
	846	+ { }
	847	+};
	848	+
	849	+static struct clk_rcg2 disp_cc_sleep_clk_src = {
	850	+ .cmd_rcgr = 0xe064,
	851	+ .mnd_width = 0,
	852	+ .hid_width = 5,
	853	+ .parent_map = disp_cc_parent_map_13,
	854	+ .freq_tbl = ftbl_disp_cc_sleep_clk_src,
	855	+ .clkr.hw.init = &(const struct clk_init_data) {
	856	+ .name = "disp_cc_sleep_clk_src",
	857	+ .parent_data = disp_cc_parent_data_13_ao,
	858	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_13_ao),
	859	+ .flags = CLK_SET_RATE_PARENT,
	860	+ .ops = &clk_rcg2_ops,
	861	+ },
	862	+};
	863	+
	864	+static struct clk_rcg2 disp_cc_xo_clk_src = {
	865	+ .cmd_rcgr = 0xe044,
	866	+ .mnd_width = 0,
	867	+ .hid_width = 5,
	868	+ .parent_map = disp_cc_parent_map_0,
	869	+ .freq_tbl = ftbl_disp_cc_esync0_clk_src,
	870	+ .clkr.hw.init = &(const struct clk_init_data) {
	871	+ .name = "disp_cc_xo_clk_src",
	872	+ .parent_data = disp_cc_parent_data_0_ao,
	873	+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_0_ao),
	874	+ .flags = CLK_SET_RATE_PARENT,
	875	+ .ops = &clk_rcg2_ops,
	876	+ },
	877	+};
	878	+
	879	+static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
	880	+ .reg = 0x8198,
	881	+ .shift = 0,
	882	+ .width = 4,
	883	+ .clkr.hw.init = &(const struct clk_init_data) {
	884	+ .name = "disp_cc_mdss_byte0_div_clk_src",
	885	+ .parent_hws = (const struct clk_hw*[]) {
	886	+ &disp_cc_mdss_byte0_clk_src.clkr.hw,
	887	+ },
	888	+ .num_parents = 1,
	889	+ .ops = &clk_regmap_div_ops,
	890	+ },
	891	+};
	892	+
	893	+static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
	894	+ .reg = 0x81b4,
	895	+ .shift = 0,
	896	+ .width = 4,
	897	+ .clkr.hw.init = &(const struct clk_init_data) {
	898	+ .name = "disp_cc_mdss_byte1_div_clk_src",
	899	+ .parent_hws = (const struct clk_hw*[]) {
	900	+ &disp_cc_mdss_byte1_clk_src.clkr.hw,
	901	+ },
	902	+ .num_parents = 1,
	903	+ .ops = &clk_regmap_div_ops,
	904	+ },
	905	+};
	906	+
	907	+static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = {
	908	+ .reg = 0x8200,
	909	+ .shift = 0,
	910	+ .width = 4,
	911	+ .clkr.hw.init = &(const struct clk_init_data) {
	912	+ .name = "disp_cc_mdss_dptx0_link_div_clk_src",
	913	+ .parent_hws = (const struct clk_hw*[]) {
	914	+ &disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
	915	+ },
	916	+ .num_parents = 1,
	917	+ .flags = CLK_SET_RATE_PARENT,
	918	+ .ops = &clk_regmap_div_ro_ops,
	919	+ },
	920	+};
	921	+
	922	+static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = {
	923	+ .reg = 0x8294,
	924	+ .shift = 0,
	925	+ .width = 4,
	926	+ .clkr.hw.init = &(const struct clk_init_data) {
	927	+ .name = "disp_cc_mdss_dptx1_link_div_clk_src",
	928	+ .parent_hws = (const struct clk_hw*[]) {
	929	+ &disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
	930	+ },
	931	+ .num_parents = 1,
	932	+ .flags = CLK_SET_RATE_PARENT,
	933	+ .ops = &clk_regmap_div_ro_ops,
	934	+ },
	935	+};
	936	+
	937	+static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = {
	938	+ .reg = 0x82c8,
	939	+ .shift = 0,
	940	+ .width = 4,
	941	+ .clkr.hw.init = &(const struct clk_init_data) {
	942	+ .name = "disp_cc_mdss_dptx2_link_div_clk_src",
	943	+ .parent_hws = (const struct clk_hw*[]) {
	944	+ &disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
	945	+ },
	946	+ .num_parents = 1,
	947	+ .flags = CLK_SET_RATE_PARENT,
	948	+ .ops = &clk_regmap_div_ro_ops,
	949	+ },
	950	+};
	951	+
	952	+static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = {
	953	+ .reg = 0x8344,
	954	+ .shift = 0,
	955	+ .width = 4,
	956	+ .clkr.hw.init = &(const struct clk_init_data) {
	957	+ .name = "disp_cc_mdss_dptx3_link_div_clk_src",
	958	+ .parent_hws = (const struct clk_hw*[]) {
	959	+ &disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
	960	+ },
	961	+ .num_parents = 1,
	962	+ .flags = CLK_SET_RATE_PARENT,
	963	+ .ops = &clk_regmap_div_ro_ops,
	964	+ },
	965	+};
	966	+
	967	+static struct clk_regmap_div disp_cc_mdss_hdmi_pclk_div_clk_src = {
	968	+ .reg = 0x838c,
	969	+ .shift = 0,
	970	+ .width = 4,
	971	+ .clkr.hw.init = &(const struct clk_init_data) {
	972	+ .name = "disp_cc_mdss_hdmi_pclk_div_clk_src",
	973	+ .parent_hws = (const struct clk_hw*[]) {
	974	+ &disp_cc_mdss_hdmi_pclk_clk_src.clkr.hw,
	975	+ },
	976	+ .num_parents = 1,
	977	+ .flags = CLK_SET_RATE_PARENT,
	978	+ .ops = &clk_regmap_div_ro_ops,
	979	+ },
	980	+};
	981	+
	982	+static struct clk_branch disp_cc_esync0_clk = {
	983	+ .halt_reg = 0x80b8,
	984	+ .halt_check = BRANCH_HALT,
	985	+ .clkr = {
	986	+ .enable_reg = 0x80b8,
	987	+ .enable_mask = BIT(0),
	988	+ .hw.init = &(const struct clk_init_data) {
	989	+ .name = "disp_cc_esync0_clk",
	990	+ .parent_hws = (const struct clk_hw*[]) {
	991	+ &disp_cc_esync0_clk_src.clkr.hw,
	992	+ },
	993	+ .num_parents = 1,
	994	+ .flags = CLK_SET_RATE_PARENT,
	995	+ .ops = &clk_branch2_ops,
	996	+ },
	997	+ },
	998	+};
	999	+
	1000	+static struct clk_branch disp_cc_esync1_clk = {
	1001	+ .halt_reg = 0x80bc,
	1002	+ .halt_check = BRANCH_HALT,
	1003	+ .clkr = {
	1004	+ .enable_reg = 0x80bc,
	1005	+ .enable_mask = BIT(0),
	1006	+ .hw.init = &(const struct clk_init_data) {
	1007	+ .name = "disp_cc_esync1_clk",
	1008	+ .parent_hws = (const struct clk_hw*[]) {
	1009	+ &disp_cc_esync1_clk_src.clkr.hw,
	1010	+ },
	1011	+ .num_parents = 1,
	1012	+ .flags = CLK_SET_RATE_PARENT,
	1013	+ .ops = &clk_branch2_ops,
	1014	+ },
	1015	+ },
	1016	+};
	1017	+
	1018	+static struct clk_branch disp_cc_mdss_accu_shift_clk = {
	1019	+ .halt_reg = 0xe060,
	1020	+ .halt_check = BRANCH_HALT_VOTED,
	1021	+ .clkr = {
	1022	+ .enable_reg = 0xe060,
	1023	+ .enable_mask = BIT(0),
	1024	+ .hw.init = &(const struct clk_init_data) {
	1025	+ .name = "disp_cc_mdss_accu_shift_clk",
	1026	+ .parent_hws = (const struct clk_hw*[]) {
	1027	+ &disp_cc_xo_clk_src.clkr.hw,
	1028	+ },
	1029	+ .num_parents = 1,
	1030	+ .flags = CLK_SET_RATE_PARENT,
	1031	+ .ops = &clk_branch2_ops,
	1032	+ },
	1033	+ },
	1034	+};
	1035	+
	1036	+static struct clk_branch disp_cc_mdss_ahb1_clk = {
	1037	+ .halt_reg = 0xa028,
	1038	+ .halt_check = BRANCH_HALT,
	1039	+ .clkr = {
	1040	+ .enable_reg = 0xa028,
	1041	+ .enable_mask = BIT(0),
	1042	+ .hw.init = &(const struct clk_init_data) {
	1043	+ .name = "disp_cc_mdss_ahb1_clk",
	1044	+ .parent_hws = (const struct clk_hw*[]) {
	1045	+ &disp_cc_mdss_ahb_clk_src.clkr.hw,
	1046	+ },
	1047	+ .num_parents = 1,
	1048	+ .flags = CLK_SET_RATE_PARENT,
	1049	+ .ops = &clk_branch2_ops,
	1050	+ },
	1051	+ },
	1052	+};
	1053	+
	1054	+static struct clk_branch disp_cc_mdss_ahb_clk = {
	1055	+ .halt_reg = 0x80b0,
	1056	+ .halt_check = BRANCH_HALT,
	1057	+ .clkr = {
	1058	+ .enable_reg = 0x80b0,
	1059	+ .enable_mask = BIT(0),
	1060	+ .hw.init = &(const struct clk_init_data) {
	1061	+ .name = "disp_cc_mdss_ahb_clk",
	1062	+ .parent_hws = (const struct clk_hw*[]) {
	1063	+ &disp_cc_mdss_ahb_clk_src.clkr.hw,
	1064	+ },
	1065	+ .num_parents = 1,
	1066	+ .flags = CLK_SET_RATE_PARENT,
	1067	+ .ops = &clk_branch2_ops,
	1068	+ },
	1069	+ },
	1070	+};
	1071	+
	1072	+static struct clk_branch disp_cc_mdss_byte0_clk = {
	1073	+ .halt_reg = 0x8034,
	1074	+ .halt_check = BRANCH_HALT,
	1075	+ .clkr = {
	1076	+ .enable_reg = 0x8034,
	1077	+ .enable_mask = BIT(0),
	1078	+ .hw.init = &(const struct clk_init_data) {
	1079	+ .name = "disp_cc_mdss_byte0_clk",
	1080	+ .parent_hws = (const struct clk_hw*[]) {
	1081	+ &disp_cc_mdss_byte0_clk_src.clkr.hw,
	1082	+ },
	1083	+ .num_parents = 1,
	1084	+ .flags = CLK_SET_RATE_PARENT,
	1085	+ .ops = &clk_branch2_ops,
	1086	+ },
	1087	+ },
	1088	+};
	1089	+
	1090	+static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
	1091	+ .halt_reg = 0x8038,
	1092	+ .halt_check = BRANCH_HALT,
	1093	+ .clkr = {
	1094	+ .enable_reg = 0x8038,
	1095	+ .enable_mask = BIT(0),
	1096	+ .hw.init = &(const struct clk_init_data) {
	1097	+ .name = "disp_cc_mdss_byte0_intf_clk",
	1098	+ .parent_hws = (const struct clk_hw*[]) {
	1099	+ &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
	1100	+ },
	1101	+ .num_parents = 1,
	1102	+ .flags = CLK_SET_RATE_PARENT,
	1103	+ .ops = &clk_branch2_ops,
	1104	+ },
	1105	+ },
	1106	+};
	1107	+
	1108	+static struct clk_branch disp_cc_mdss_byte1_clk = {
	1109	+ .halt_reg = 0x803c,
	1110	+ .halt_check = BRANCH_HALT,
	1111	+ .clkr = {
	1112	+ .enable_reg = 0x803c,
	1113	+ .enable_mask = BIT(0),
	1114	+ .hw.init = &(const struct clk_init_data) {
	1115	+ .name = "disp_cc_mdss_byte1_clk",
	1116	+ .parent_hws = (const struct clk_hw*[]) {
	1117	+ &disp_cc_mdss_byte1_clk_src.clkr.hw,
	1118	+ },
	1119	+ .num_parents = 1,
	1120	+ .flags = CLK_SET_RATE_PARENT,
	1121	+ .ops = &clk_branch2_ops,
	1122	+ },
	1123	+ },
	1124	+};
	1125	+
	1126	+static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
	1127	+ .halt_reg = 0x8040,
	1128	+ .halt_check = BRANCH_HALT,
	1129	+ .clkr = {
	1130	+ .enable_reg = 0x8040,
	1131	+ .enable_mask = BIT(0),
	1132	+ .hw.init = &(const struct clk_init_data) {
	1133	+ .name = "disp_cc_mdss_byte1_intf_clk",
	1134	+ .parent_hws = (const struct clk_hw*[]) {
	1135	+ &disp_cc_mdss_byte1_div_clk_src.clkr.hw,
	1136	+ },
	1137	+ .num_parents = 1,
	1138	+ .flags = CLK_SET_RATE_PARENT,
	1139	+ .ops = &clk_branch2_ops,
	1140	+ },
	1141	+ },
	1142	+};
	1143	+
	1144	+static struct clk_branch disp_cc_mdss_dptx0_aux_clk = {
	1145	+ .halt_reg = 0x8064,
	1146	+ .halt_check = BRANCH_HALT,
	1147	+ .clkr = {
	1148	+ .enable_reg = 0x8064,
	1149	+ .enable_mask = BIT(0),
	1150	+ .hw.init = &(const struct clk_init_data) {
	1151	+ .name = "disp_cc_mdss_dptx0_aux_clk",
	1152	+ .parent_hws = (const struct clk_hw*[]) {
	1153	+ &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw,
	1154	+ },
	1155	+ .num_parents = 1,
	1156	+ .flags = CLK_SET_RATE_PARENT,
	1157	+ .ops = &clk_branch2_ops,
	1158	+ },
	1159	+ },
	1160	+};
	1161	+
	1162	+static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = {
	1163	+ .halt_reg = 0x8058,
	1164	+ .halt_check = BRANCH_HALT,
	1165	+ .clkr = {
	1166	+ .enable_reg = 0x8058,
	1167	+ .enable_mask = BIT(0),
	1168	+ .hw.init = &(const struct clk_init_data) {
	1169	+ .name = "disp_cc_mdss_dptx0_crypto_clk",
	1170	+ .parent_hws = (const struct clk_hw*[]) {
	1171	+ &disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
	1172	+ },
	1173	+ .num_parents = 1,
	1174	+ .flags = CLK_SET_RATE_PARENT,
	1175	+ .ops = &clk_branch2_ops,
	1176	+ },
	1177	+ },
	1178	+};
	1179	+
	1180	+static struct clk_branch disp_cc_mdss_dptx0_link_clk = {
	1181	+ .halt_reg = 0x804c,
	1182	+ .halt_check = BRANCH_HALT,
	1183	+ .clkr = {
	1184	+ .enable_reg = 0x804c,
	1185	+ .enable_mask = BIT(0),
	1186	+ .hw.init = &(const struct clk_init_data) {
	1187	+ .name = "disp_cc_mdss_dptx0_link_clk",
	1188	+ .parent_hws = (const struct clk_hw*[]) {
	1189	+ &disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
	1190	+ },
	1191	+ .num_parents = 1,
	1192	+ .flags = CLK_SET_RATE_PARENT,
	1193	+ .ops = &clk_branch2_ops,
	1194	+ },
	1195	+ },
	1196	+};
	1197	+
	1198	+static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = {
	1199	+ .halt_reg = 0x8054,
	1200	+ .halt_check = BRANCH_HALT,
	1201	+ .clkr = {
	1202	+ .enable_reg = 0x8054,
	1203	+ .enable_mask = BIT(0),
	1204	+ .hw.init = &(const struct clk_init_data) {
	1205	+ .name = "disp_cc_mdss_dptx0_link_intf_clk",
	1206	+ .parent_hws = (const struct clk_hw*[]) {
	1207	+ &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
	1208	+ },
	1209	+ .num_parents = 1,
	1210	+ .flags = CLK_SET_RATE_PARENT,
	1211	+ .ops = &clk_branch2_ops,
	1212	+ },
	1213	+ },
	1214	+};
	1215	+
	1216	+static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = {
	1217	+ .halt_reg = 0x805c,
	1218	+ .halt_check = BRANCH_HALT,
	1219	+ .clkr = {
	1220	+ .enable_reg = 0x805c,
	1221	+ .enable_mask = BIT(0),
	1222	+ .hw.init = &(const struct clk_init_data) {
	1223	+ .name = "disp_cc_mdss_dptx0_pixel0_clk",
	1224	+ .parent_hws = (const struct clk_hw*[]) {
	1225	+ &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
	1226	+ },
	1227	+ .num_parents = 1,
	1228	+ .flags = CLK_SET_RATE_PARENT,
	1229	+ .ops = &clk_branch2_ops,
	1230	+ },
	1231	+ },
	1232	+};
	1233	+
	1234	+static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = {
	1235	+ .halt_reg = 0x8060,
	1236	+ .halt_check = BRANCH_HALT,
	1237	+ .clkr = {
	1238	+ .enable_reg = 0x8060,
	1239	+ .enable_mask = BIT(0),
	1240	+ .hw.init = &(const struct clk_init_data) {
	1241	+ .name = "disp_cc_mdss_dptx0_pixel1_clk",
	1242	+ .parent_hws = (const struct clk_hw*[]) {
	1243	+ &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
	1244	+ },
	1245	+ .num_parents = 1,
	1246	+ .flags = CLK_SET_RATE_PARENT,
	1247	+ .ops = &clk_branch2_ops,
	1248	+ },
	1249	+ },
	1250	+};
	1251	+
	1252	+static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = {
	1253	+ .halt_reg = 0x8050,
	1254	+ .halt_check = BRANCH_HALT,
	1255	+ .clkr = {
	1256	+ .enable_reg = 0x8050,
	1257	+ .enable_mask = BIT(0),
	1258	+ .hw.init = &(const struct clk_init_data) {
	1259	+ .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk",
	1260	+ .parent_hws = (const struct clk_hw*[]) {
	1261	+ &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
	1262	+ },
	1263	+ .num_parents = 1,
	1264	+ .flags = CLK_SET_RATE_PARENT,
	1265	+ .ops = &clk_branch2_ops,
	1266	+ },
	1267	+ },
	1268	+};
	1269	+
	1270	+static struct clk_branch disp_cc_mdss_dptx1_aux_clk = {
	1271	+ .halt_reg = 0x8080,
	1272	+ .halt_check = BRANCH_HALT,
	1273	+ .clkr = {
	1274	+ .enable_reg = 0x8080,
	1275	+ .enable_mask = BIT(0),
	1276	+ .hw.init = &(const struct clk_init_data) {
	1277	+ .name = "disp_cc_mdss_dptx1_aux_clk",
	1278	+ .parent_hws = (const struct clk_hw*[]) {
	1279	+ &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw,
	1280	+ },
	1281	+ .num_parents = 1,
	1282	+ .flags = CLK_SET_RATE_PARENT,
	1283	+ .ops = &clk_branch2_ops,
	1284	+ },
	1285	+ },
	1286	+};
	1287	+
	1288	+static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = {
	1289	+ .halt_reg = 0x807c,
	1290	+ .halt_check = BRANCH_HALT,
	1291	+ .clkr = {
	1292	+ .enable_reg = 0x807c,
	1293	+ .enable_mask = BIT(0),
	1294	+ .hw.init = &(const struct clk_init_data) {
	1295	+ .name = "disp_cc_mdss_dptx1_crypto_clk",
	1296	+ .parent_hws = (const struct clk_hw*[]) {
	1297	+ &disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
	1298	+ },
	1299	+ .num_parents = 1,
	1300	+ .flags = CLK_SET_RATE_PARENT,
	1301	+ .ops = &clk_branch2_ops,
	1302	+ },
	1303	+ },
	1304	+};
	1305	+
	1306	+static struct clk_branch disp_cc_mdss_dptx1_link_clk = {
	1307	+ .halt_reg = 0x8070,
	1308	+ .halt_check = BRANCH_HALT,
	1309	+ .clkr = {
	1310	+ .enable_reg = 0x8070,
	1311	+ .enable_mask = BIT(0),
	1312	+ .hw.init = &(const struct clk_init_data) {
	1313	+ .name = "disp_cc_mdss_dptx1_link_clk",
	1314	+ .parent_hws = (const struct clk_hw*[]) {
	1315	+ &disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
	1316	+ },
	1317	+ .num_parents = 1,
	1318	+ .flags = CLK_SET_RATE_PARENT,
	1319	+ .ops = &clk_branch2_ops,
	1320	+ },
	1321	+ },
	1322	+};
	1323	+
	1324	+static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = {
	1325	+ .halt_reg = 0x8078,
	1326	+ .halt_check = BRANCH_HALT,
	1327	+ .clkr = {
	1328	+ .enable_reg = 0x8078,
	1329	+ .enable_mask = BIT(0),
	1330	+ .hw.init = &(const struct clk_init_data) {
	1331	+ .name = "disp_cc_mdss_dptx1_link_intf_clk",
	1332	+ .parent_hws = (const struct clk_hw*[]) {
	1333	+ &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
	1334	+ },
	1335	+ .num_parents = 1,
	1336	+ .flags = CLK_SET_RATE_PARENT,
	1337	+ .ops = &clk_branch2_ops,
	1338	+ },
	1339	+ },
	1340	+};
	1341	+
	1342	+static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = {
	1343	+ .halt_reg = 0x8068,
	1344	+ .halt_check = BRANCH_HALT,
	1345	+ .clkr = {
	1346	+ .enable_reg = 0x8068,
	1347	+ .enable_mask = BIT(0),
	1348	+ .hw.init = &(const struct clk_init_data) {
	1349	+ .name = "disp_cc_mdss_dptx1_pixel0_clk",
	1350	+ .parent_hws = (const struct clk_hw*[]) {
	1351	+ &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
	1352	+ },
	1353	+ .num_parents = 1,
	1354	+ .flags = CLK_SET_RATE_PARENT,
	1355	+ .ops = &clk_branch2_ops,
	1356	+ },
	1357	+ },
	1358	+};
	1359	+
	1360	+static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = {
	1361	+ .halt_reg = 0x806c,
	1362	+ .halt_check = BRANCH_HALT,
	1363	+ .clkr = {
	1364	+ .enable_reg = 0x806c,
	1365	+ .enable_mask = BIT(0),
	1366	+ .hw.init = &(const struct clk_init_data) {
	1367	+ .name = "disp_cc_mdss_dptx1_pixel1_clk",
	1368	+ .parent_hws = (const struct clk_hw*[]) {
	1369	+ &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
	1370	+ },
	1371	+ .num_parents = 1,
	1372	+ .flags = CLK_SET_RATE_PARENT,
	1373	+ .ops = &clk_branch2_ops,
	1374	+ },
	1375	+ },
	1376	+};
	1377	+
	1378	+static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = {
	1379	+ .halt_reg = 0x8074,
	1380	+ .halt_check = BRANCH_HALT,
	1381	+ .clkr = {
	1382	+ .enable_reg = 0x8074,
	1383	+ .enable_mask = BIT(0),
	1384	+ .hw.init = &(const struct clk_init_data) {
	1385	+ .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk",
	1386	+ .parent_hws = (const struct clk_hw*[]) {
	1387	+ &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
	1388	+ },
	1389	+ .num_parents = 1,
	1390	+ .flags = CLK_SET_RATE_PARENT,
	1391	+ .ops = &clk_branch2_ops,
	1392	+ },
	1393	+ },
	1394	+};
	1395	+
	1396	+static struct clk_branch disp_cc_mdss_dptx2_aux_clk = {
	1397	+ .halt_reg = 0x8098,
	1398	+ .halt_check = BRANCH_HALT,
	1399	+ .clkr = {
	1400	+ .enable_reg = 0x8098,
	1401	+ .enable_mask = BIT(0),
	1402	+ .hw.init = &(const struct clk_init_data) {
	1403	+ .name = "disp_cc_mdss_dptx2_aux_clk",
	1404	+ .parent_hws = (const struct clk_hw*[]) {
	1405	+ &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw,
	1406	+ },
	1407	+ .num_parents = 1,
	1408	+ .flags = CLK_SET_RATE_PARENT,
	1409	+ .ops = &clk_branch2_ops,
	1410	+ },
	1411	+ },
	1412	+};
	1413	+
	1414	+static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = {
	1415	+ .halt_reg = 0x8094,
	1416	+ .halt_check = BRANCH_HALT,
	1417	+ .clkr = {
	1418	+ .enable_reg = 0x8094,
	1419	+ .enable_mask = BIT(0),
	1420	+ .hw.init = &(const struct clk_init_data) {
	1421	+ .name = "disp_cc_mdss_dptx2_crypto_clk",
	1422	+ .parent_hws = (const struct clk_hw*[]) {
	1423	+ &disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
	1424	+ },
	1425	+ .num_parents = 1,
	1426	+ .flags = CLK_SET_RATE_PARENT,
	1427	+ .ops = &clk_branch2_ops,
	1428	+ },
	1429	+ },
	1430	+};
	1431	+
	1432	+static struct clk_branch disp_cc_mdss_dptx2_link_clk = {
	1433	+ .halt_reg = 0x808c,
	1434	+ .halt_check = BRANCH_HALT,
	1435	+ .clkr = {
	1436	+ .enable_reg = 0x808c,
	1437	+ .enable_mask = BIT(0),
	1438	+ .hw.init = &(const struct clk_init_data) {
	1439	+ .name = "disp_cc_mdss_dptx2_link_clk",
	1440	+ .parent_hws = (const struct clk_hw*[]) {
	1441	+ &disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
	1442	+ },
	1443	+ .num_parents = 1,
	1444	+ .flags = CLK_SET_RATE_PARENT,
	1445	+ .ops = &clk_branch2_ops,
	1446	+ },
	1447	+ },
	1448	+};
	1449	+
	1450	+static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = {
	1451	+ .halt_reg = 0x8090,
	1452	+ .halt_check = BRANCH_HALT,
	1453	+ .clkr = {
	1454	+ .enable_reg = 0x8090,
	1455	+ .enable_mask = BIT(0),
	1456	+ .hw.init = &(const struct clk_init_data) {
	1457	+ .name = "disp_cc_mdss_dptx2_link_intf_clk",
	1458	+ .parent_hws = (const struct clk_hw*[]) {
	1459	+ &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw,
	1460	+ },
	1461	+ .num_parents = 1,
	1462	+ .flags = CLK_SET_RATE_PARENT,
	1463	+ .ops = &clk_branch2_ops,
	1464	+ },
	1465	+ },
	1466	+};
	1467	+
	1468	+static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = {
	1469	+ .halt_reg = 0x8084,
	1470	+ .halt_check = BRANCH_HALT,
	1471	+ .clkr = {
	1472	+ .enable_reg = 0x8084,
	1473	+ .enable_mask = BIT(0),
	1474	+ .hw.init = &(const struct clk_init_data) {
	1475	+ .name = "disp_cc_mdss_dptx2_pixel0_clk",
	1476	+ .parent_hws = (const struct clk_hw*[]) {
	1477	+ &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,
	1478	+ },
	1479	+ .num_parents = 1,
	1480	+ .flags = CLK_SET_RATE_PARENT,
	1481	+ .ops = &clk_branch2_ops,
	1482	+ },
	1483	+ },
	1484	+};
	1485	+
	1486	+static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = {
	1487	+ .halt_reg = 0x8088,
	1488	+ .halt_check = BRANCH_HALT,
	1489	+ .clkr = {
	1490	+ .enable_reg = 0x8088,
	1491	+ .enable_mask = BIT(0),
	1492	+ .hw.init = &(const struct clk_init_data) {
	1493	+ .name = "disp_cc_mdss_dptx2_pixel1_clk",
	1494	+ .parent_hws = (const struct clk_hw*[]) {
	1495	+ &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,
	1496	+ },
	1497	+ .num_parents = 1,
	1498	+ .flags = CLK_SET_RATE_PARENT,
	1499	+ .ops = &clk_branch2_ops,
	1500	+ },
	1501	+ },
	1502	+};
	1503	+
	1504	+static struct clk_branch disp_cc_mdss_dptx3_aux_clk = {
	1505	+ .halt_reg = 0x80a8,
	1506	+ .halt_check = BRANCH_HALT,
	1507	+ .clkr = {
	1508	+ .enable_reg = 0x80a8,
	1509	+ .enable_mask = BIT(0),
	1510	+ .hw.init = &(const struct clk_init_data) {
	1511	+ .name = "disp_cc_mdss_dptx3_aux_clk",
	1512	+ .parent_hws = (const struct clk_hw*[]) {
	1513	+ &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw,
	1514	+ },
	1515	+ .num_parents = 1,
	1516	+ .flags = CLK_SET_RATE_PARENT,
	1517	+ .ops = &clk_branch2_ops,
	1518	+ },
	1519	+ },
	1520	+};
	1521	+
	1522	+static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = {
	1523	+ .halt_reg = 0x80ac,
	1524	+ .halt_check = BRANCH_HALT,
	1525	+ .clkr = {
	1526	+ .enable_reg = 0x80ac,
	1527	+ .enable_mask = BIT(0),
	1528	+ .hw.init = &(const struct clk_init_data) {
	1529	+ .name = "disp_cc_mdss_dptx3_crypto_clk",
	1530	+ .parent_hws = (const struct clk_hw*[]) {
	1531	+ &disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
	1532	+ },
	1533	+ .num_parents = 1,
	1534	+ .flags = CLK_SET_RATE_PARENT,
	1535	+ .ops = &clk_branch2_ops,
	1536	+ },
	1537	+ },
	1538	+};
	1539	+
	1540	+static struct clk_branch disp_cc_mdss_dptx3_link_clk = {
	1541	+ .halt_reg = 0x80a0,
	1542	+ .halt_check = BRANCH_HALT,
	1543	+ .clkr = {
	1544	+ .enable_reg = 0x80a0,
	1545	+ .enable_mask = BIT(0),
	1546	+ .hw.init = &(const struct clk_init_data) {
	1547	+ .name = "disp_cc_mdss_dptx3_link_clk",
	1548	+ .parent_hws = (const struct clk_hw*[]) {
	1549	+ &disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
	1550	+ },
	1551	+ .num_parents = 1,
	1552	+ .flags = CLK_SET_RATE_PARENT,
	1553	+ .ops = &clk_branch2_ops,
	1554	+ },
	1555	+ },
	1556	+};
	1557	+
	1558	+static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = {
	1559	+ .halt_reg = 0x80a4,
	1560	+ .halt_check = BRANCH_HALT,
	1561	+ .clkr = {
	1562	+ .enable_reg = 0x80a4,
	1563	+ .enable_mask = BIT(0),
	1564	+ .hw.init = &(const struct clk_init_data) {
	1565	+ .name = "disp_cc_mdss_dptx3_link_intf_clk",
	1566	+ .parent_hws = (const struct clk_hw*[]) {
	1567	+ &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw,
	1568	+ },
	1569	+ .num_parents = 1,
	1570	+ .flags = CLK_SET_RATE_PARENT,
	1571	+ .ops = &clk_branch2_ops,
	1572	+ },
	1573	+ },
	1574	+};
	1575	+
	1576	+static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = {
	1577	+ .halt_reg = 0x809c,
	1578	+ .halt_check = BRANCH_HALT,
	1579	+ .clkr = {
	1580	+ .enable_reg = 0x809c,
	1581	+ .enable_mask = BIT(0),
	1582	+ .hw.init = &(const struct clk_init_data) {
	1583	+ .name = "disp_cc_mdss_dptx3_pixel0_clk",
	1584	+ .parent_hws = (const struct clk_hw*[]) {
	1585	+ &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,
	1586	+ },
	1587	+ .num_parents = 1,
	1588	+ .flags = CLK_SET_RATE_PARENT,
	1589	+ .ops = &clk_branch2_ops,
	1590	+ },
	1591	+ },
	1592	+};
	1593	+
	1594	+static struct clk_branch disp_cc_mdss_esc0_clk = {
	1595	+ .halt_reg = 0x8044,
	1596	+ .halt_check = BRANCH_HALT,
	1597	+ .clkr = {
	1598	+ .enable_reg = 0x8044,
	1599	+ .enable_mask = BIT(0),
	1600	+ .hw.init = &(const struct clk_init_data) {
	1601	+ .name = "disp_cc_mdss_esc0_clk",
	1602	+ .parent_hws = (const struct clk_hw*[]) {
	1603	+ &disp_cc_mdss_esc0_clk_src.clkr.hw,
	1604	+ },
	1605	+ .num_parents = 1,
	1606	+ .flags = CLK_SET_RATE_PARENT,
	1607	+ .ops = &clk_branch2_ops,
	1608	+ },
	1609	+ },
	1610	+};
	1611	+
	1612	+static struct clk_branch disp_cc_mdss_esc1_clk = {
	1613	+ .halt_reg = 0x8048,
	1614	+ .halt_check = BRANCH_HALT,
	1615	+ .clkr = {
	1616	+ .enable_reg = 0x8048,
	1617	+ .enable_mask = BIT(0),
	1618	+ .hw.init = &(const struct clk_init_data) {
	1619	+ .name = "disp_cc_mdss_esc1_clk",
	1620	+ .parent_hws = (const struct clk_hw*[]) {
	1621	+ &disp_cc_mdss_esc1_clk_src.clkr.hw,
	1622	+ },
	1623	+ .num_parents = 1,
	1624	+ .flags = CLK_SET_RATE_PARENT,
	1625	+ .ops = &clk_branch2_ops,
	1626	+ },
	1627	+ },
	1628	+};
	1629	+
	1630	+static struct clk_branch disp_cc_mdss_hdmi_ahbm_clk = {
	1631	+ .halt_reg = 0x8378,
	1632	+ .halt_check = BRANCH_HALT,
	1633	+ .clkr = {
	1634	+ .enable_reg = 0x8378,
	1635	+ .enable_mask = BIT(0),
	1636	+ .hw.init = &(const struct clk_init_data) {
	1637	+ .name = "disp_cc_mdss_hdmi_ahbm_clk",
	1638	+ .parent_hws = (const struct clk_hw*[]) {
	1639	+ &disp_cc_mdss_ahb_clk_src.clkr.hw,
	1640	+ },
	1641	+ .num_parents = 1,
	1642	+ .flags = CLK_SET_RATE_PARENT,
	1643	+ .ops = &clk_branch2_ops,
	1644	+ },
	1645	+ },
	1646	+};
	1647	+
	1648	+static struct clk_branch disp_cc_mdss_hdmi_app_clk = {
	1649	+ .halt_reg = 0x8388,
	1650	+ .halt_check = BRANCH_HALT,
	1651	+ .clkr = {
	1652	+ .enable_reg = 0x8388,
	1653	+ .enable_mask = BIT(0),
	1654	+ .hw.init = &(const struct clk_init_data) {
	1655	+ .name = "disp_cc_mdss_hdmi_app_clk",
	1656	+ .parent_hws = (const struct clk_hw*[]) {
	1657	+ &disp_cc_mdss_hdmi_app_clk_src.clkr.hw,
	1658	+ },
	1659	+ .num_parents = 1,
	1660	+ .flags = CLK_SET_RATE_PARENT,
	1661	+ .ops = &clk_branch2_ops,
	1662	+ },
	1663	+ },
	1664	+};
	1665	+
	1666	+static struct clk_branch disp_cc_mdss_hdmi_crypto_clk = {
	1667	+ .halt_reg = 0x8384,
	1668	+ .halt_check = BRANCH_HALT,
	1669	+ .clkr = {
	1670	+ .enable_reg = 0x8384,
	1671	+ .enable_mask = BIT(0),
	1672	+ .hw.init = &(const struct clk_init_data) {
	1673	+ .name = "disp_cc_mdss_hdmi_crypto_clk",
	1674	+ .parent_hws = (const struct clk_hw*[]) {
	1675	+ &disp_cc_mdss_hdmi_pclk_clk_src.clkr.hw,
	1676	+ },
	1677	+ .num_parents = 1,
	1678	+ .flags = CLK_SET_RATE_PARENT,
	1679	+ .ops = &clk_branch2_ops,
	1680	+ },
	1681	+ },
	1682	+};
	1683	+
	1684	+static struct clk_branch disp_cc_mdss_hdmi_intf_clk = {
	1685	+ .halt_reg = 0x8380,
	1686	+ .halt_check = BRANCH_HALT,
	1687	+ .clkr = {
	1688	+ .enable_reg = 0x8380,
	1689	+ .enable_mask = BIT(0),
	1690	+ .hw.init = &(const struct clk_init_data) {
	1691	+ .name = "disp_cc_mdss_hdmi_intf_clk",
	1692	+ .parent_hws = (const struct clk_hw*[]) {
	1693	+ &disp_cc_mdss_hdmi_pclk_div_clk_src.clkr.hw,
	1694	+ },
	1695	+ .num_parents = 1,
	1696	+ .flags = CLK_SET_RATE_PARENT,
	1697	+ .ops = &clk_branch2_ops,
	1698	+ },
	1699	+ },
	1700	+};
	1701	+
	1702	+static struct clk_branch disp_cc_mdss_hdmi_pclk_clk = {
	1703	+ .halt_reg = 0x837c,
	1704	+ .halt_check = BRANCH_HALT,
	1705	+ .clkr = {
	1706	+ .enable_reg = 0x837c,
	1707	+ .enable_mask = BIT(0),
	1708	+ .hw.init = &(const struct clk_init_data) {
	1709	+ .name = "disp_cc_mdss_hdmi_pclk_clk",
	1710	+ .parent_hws = (const struct clk_hw*[]) {
	1711	+ &disp_cc_mdss_hdmi_pclk_clk_src.clkr.hw,
	1712	+ },
	1713	+ .num_parents = 1,
	1714	+ .flags = CLK_SET_RATE_PARENT,
	1715	+ .ops = &clk_branch2_ops,
	1716	+ },
	1717	+ },
	1718	+};
	1719	+
	1720	+static struct clk_branch disp_cc_mdss_mdp1_clk = {
	1721	+ .halt_reg = 0xa004,
	1722	+ .halt_check = BRANCH_HALT,
	1723	+ .clkr = {
	1724	+ .enable_reg = 0xa004,
	1725	+ .enable_mask = BIT(0),
	1726	+ .hw.init = &(const struct clk_init_data) {
	1727	+ .name = "disp_cc_mdss_mdp1_clk",
	1728	+ .parent_hws = (const struct clk_hw*[]) {
	1729	+ &disp_cc_mdss_mdp_clk_src.clkr.hw,
	1730	+ },
	1731	+ .num_parents = 1,
	1732	+ .flags = CLK_SET_RATE_PARENT,
	1733	+ .ops = &clk_branch2_ops,
	1734	+ },
	1735	+ },
	1736	+};
	1737	+
	1738	+static struct clk_branch disp_cc_mdss_mdp_clk = {
	1739	+ .halt_reg = 0x8010,
	1740	+ .halt_check = BRANCH_HALT,
	1741	+ .clkr = {
	1742	+ .enable_reg = 0x8010,
	1743	+ .enable_mask = BIT(0),
	1744	+ .hw.init = &(const struct clk_init_data) {
	1745	+ .name = "disp_cc_mdss_mdp_clk",
	1746	+ .parent_hws = (const struct clk_hw*[]) {
	1747	+ &disp_cc_mdss_mdp_clk_src.clkr.hw,
	1748	+ },
	1749	+ .num_parents = 1,
	1750	+ .flags = CLK_SET_RATE_PARENT,
	1751	+ .ops = &clk_branch2_aon_ops,
	1752	+ },
	1753	+ },
	1754	+};
	1755	+
	1756	+static struct clk_branch disp_cc_mdss_mdp_lut1_clk = {
	1757	+ .halt_reg = 0xa014,
	1758	+ .halt_check = BRANCH_HALT,
	1759	+ .clkr = {
	1760	+ .enable_reg = 0xa014,
	1761	+ .enable_mask = BIT(0),
	1762	+ .hw.init = &(const struct clk_init_data) {
	1763	+ .name = "disp_cc_mdss_mdp_lut1_clk",
	1764	+ .parent_hws = (const struct clk_hw*[]) {
	1765	+ &disp_cc_mdss_mdp_clk_src.clkr.hw,
	1766	+ },
	1767	+ .num_parents = 1,
	1768	+ .flags = CLK_SET_RATE_PARENT,
	1769	+ .ops = &clk_branch2_ops,
	1770	+ },
	1771	+ },
	1772	+};
	1773	+
	1774	+static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
	1775	+ .halt_reg = 0x8020,
	1776	+ .halt_check = BRANCH_HALT_VOTED,
	1777	+ .clkr = {
	1778	+ .enable_reg = 0x8020,
	1779	+ .enable_mask = BIT(0),
	1780	+ .hw.init = &(const struct clk_init_data) {
	1781	+ .name = "disp_cc_mdss_mdp_lut_clk",
	1782	+ .parent_hws = (const struct clk_hw*[]) {
	1783	+ &disp_cc_mdss_mdp_clk_src.clkr.hw,
	1784	+ },
	1785	+ .num_parents = 1,
	1786	+ .flags = CLK_SET_RATE_PARENT,
	1787	+ .ops = &clk_branch2_ops,
	1788	+ },
	1789	+ },
	1790	+};
	1791	+
	1792	+static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
	1793	+ .halt_reg = 0xc004,
	1794	+ .halt_check = BRANCH_HALT_VOTED,
	1795	+ .clkr = {
	1796	+ .enable_reg = 0xc004,
	1797	+ .enable_mask = BIT(0),
	1798	+ .hw.init = &(const struct clk_init_data) {
	1799	+ .name = "disp_cc_mdss_non_gdsc_ahb_clk",
	1800	+ .parent_hws = (const struct clk_hw*[]) {
	1801	+ &disp_cc_mdss_ahb_clk_src.clkr.hw,
	1802	+ },
	1803	+ .num_parents = 1,
	1804	+ .flags = CLK_SET_RATE_PARENT,
	1805	+ .ops = &clk_branch2_ops,
	1806	+ },
	1807	+ },
	1808	+};
	1809	+
	1810	+static struct clk_branch disp_cc_mdss_pclk0_clk = {
	1811	+ .halt_reg = 0x8004,
	1812	+ .halt_check = BRANCH_HALT,
	1813	+ .clkr = {
	1814	+ .enable_reg = 0x8004,
	1815	+ .enable_mask = BIT(0),
	1816	+ .hw.init = &(const struct clk_init_data) {
	1817	+ .name = "disp_cc_mdss_pclk0_clk",
	1818	+ .parent_hws = (const struct clk_hw*[]) {
	1819	+ &disp_cc_mdss_pclk0_clk_src.clkr.hw,
	1820	+ },
	1821	+ .num_parents = 1,
	1822	+ .flags = CLK_SET_RATE_PARENT,
	1823	+ .ops = &clk_branch2_ops,
	1824	+ },
	1825	+ },
	1826	+};
	1827	+
	1828	+static struct clk_branch disp_cc_mdss_pclk1_clk = {
	1829	+ .halt_reg = 0x8008,
	1830	+ .halt_check = BRANCH_HALT,
	1831	+ .clkr = {
	1832	+ .enable_reg = 0x8008,
	1833	+ .enable_mask = BIT(0),
	1834	+ .hw.init = &(const struct clk_init_data) {
	1835	+ .name = "disp_cc_mdss_pclk1_clk",
	1836	+ .parent_hws = (const struct clk_hw*[]) {
	1837	+ &disp_cc_mdss_pclk1_clk_src.clkr.hw,
	1838	+ },
	1839	+ .num_parents = 1,
	1840	+ .flags = CLK_SET_RATE_PARENT,
	1841	+ .ops = &clk_branch2_ops,
	1842	+ },
	1843	+ },
	1844	+};
	1845	+
	1846	+static struct clk_branch disp_cc_mdss_pclk2_clk = {
	1847	+ .halt_reg = 0x800c,
	1848	+ .halt_check = BRANCH_HALT,
	1849	+ .clkr = {
	1850	+ .enable_reg = 0x800c,
	1851	+ .enable_mask = BIT(0),
	1852	+ .hw.init = &(const struct clk_init_data) {
	1853	+ .name = "disp_cc_mdss_pclk2_clk",
	1854	+ .parent_hws = (const struct clk_hw*[]) {
	1855	+ &disp_cc_mdss_pclk2_clk_src.clkr.hw,
	1856	+ },
	1857	+ .num_parents = 1,
	1858	+ .flags = CLK_SET_RATE_PARENT,
	1859	+ .ops = &clk_branch2_ops,
	1860	+ },
	1861	+ },
	1862	+};
	1863	+
	1864	+static struct clk_branch disp_cc_mdss_vsync1_clk = {
	1865	+ .halt_reg = 0xa024,
	1866	+ .halt_check = BRANCH_HALT,
	1867	+ .clkr = {
	1868	+ .enable_reg = 0xa024,
	1869	+ .enable_mask = BIT(0),
	1870	+ .hw.init = &(const struct clk_init_data) {
	1871	+ .name = "disp_cc_mdss_vsync1_clk",
	1872	+ .parent_hws = (const struct clk_hw*[]) {
	1873	+ &disp_cc_mdss_vsync_clk_src.clkr.hw,
	1874	+ },
	1875	+ .num_parents = 1,
	1876	+ .flags = CLK_SET_RATE_PARENT,
	1877	+ .ops = &clk_branch2_ops,
	1878	+ },
	1879	+ },
	1880	+};
	1881	+
	1882	+static struct clk_branch disp_cc_mdss_vsync_clk = {
	1883	+ .halt_reg = 0x8030,
	1884	+ .halt_check = BRANCH_HALT,
	1885	+ .clkr = {
	1886	+ .enable_reg = 0x8030,
	1887	+ .enable_mask = BIT(0),
	1888	+ .hw.init = &(const struct clk_init_data) {
	1889	+ .name = "disp_cc_mdss_vsync_clk",
	1890	+ .parent_hws = (const struct clk_hw*[]) {
	1891	+ &disp_cc_mdss_vsync_clk_src.clkr.hw,
	1892	+ },
	1893	+ .num_parents = 1,
	1894	+ .flags = CLK_SET_RATE_PARENT,
	1895	+ .ops = &clk_branch2_ops,
	1896	+ },
	1897	+ },
	1898	+};
	1899	+
	1900	+static struct clk_branch disp_cc_osc_clk = {
	1901	+ .halt_reg = 0x80b4,
	1902	+ .halt_check = BRANCH_HALT,
	1903	+ .clkr = {
	1904	+ .enable_reg = 0x80b4,
	1905	+ .enable_mask = BIT(0),
	1906	+ .hw.init = &(const struct clk_init_data) {
	1907	+ .name = "disp_cc_osc_clk",
	1908	+ .parent_hws = (const struct clk_hw*[]) {
	1909	+ &disp_cc_osc_clk_src.clkr.hw,
	1910	+ },
	1911	+ .num_parents = 1,
	1912	+ .flags = CLK_SET_RATE_PARENT,
	1913	+ .ops = &clk_branch2_ops,
	1914	+ },
	1915	+ },
	1916	+};
	1917	+
	1918	+static struct gdsc mdss_gdsc = {
	1919	+ .gdscr = 0x9000,
	1920	+ .en_rest_wait_val = 0x2,
	1921	+ .en_few_wait_val = 0x2,
	1922	+ .clk_dis_wait_val = 0xf,
	1923	+ .pd = {
	1924	+ .name = "mdss_gdsc",
	1925	+ },
	1926	+ .pwrsts = PWRSTS_OFF_ON,
	1927	+ .flags = POLL_CFG_GDSCR \| HW_CTRL \| RETAIN_FF_ENABLE,
	1928	+};
	1929	+
	1930	+static struct gdsc mdss_int2_gdsc = {
	1931	+ .gdscr = 0xb000,
	1932	+ .en_rest_wait_val = 0x2,
	1933	+ .en_few_wait_val = 0x2,
	1934	+ .clk_dis_wait_val = 0xf,
	1935	+ .pd = {
	1936	+ .name = "mdss_int2_gdsc",
	1937	+ },
	1938	+ .pwrsts = PWRSTS_OFF_ON,
	1939	+ .flags = POLL_CFG_GDSCR \| HW_CTRL \| RETAIN_FF_ENABLE,
	1940	+};
	1941	+
	1942	+static struct clk_regmap *disp_cc_eliza_clocks[] = {
	1943	+ [DISP_CC_ESYNC0_CLK] = &disp_cc_esync0_clk.clkr,
	1944	+ [DISP_CC_ESYNC0_CLK_SRC] = &disp_cc_esync0_clk_src.clkr,
	1945	+ [DISP_CC_ESYNC1_CLK] = &disp_cc_esync1_clk.clkr,
	1946	+ [DISP_CC_ESYNC1_CLK_SRC] = &disp_cc_esync1_clk_src.clkr,
	1947	+ [DISP_CC_MDSS_ACCU_SHIFT_CLK] = &disp_cc_mdss_accu_shift_clk.clkr,
	1948	+ [DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr,
	1949	+ [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
	1950	+ [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
	1951	+ [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
	1952	+ [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
	1953	+ [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
	1954	+ [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
	1955	+ [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
	1956	+ [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
	1957	+ [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,
	1958	+ [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
	1959	+ [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr,
	1960	+ [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr,
	1961	+ [DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr,
	1962	+ [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr,
	1963	+ [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr,
	1964	+ [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr,
	1965	+ [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr,
	1966	+ [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr,
	1967	+ [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr,
	1968	+ [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr,
	1969	+ [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr,
	1970	+ [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =
	1971	+ &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,
	1972	+ [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr,
	1973	+ [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr,
	1974	+ [DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr,
	1975	+ [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr,
	1976	+ [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr,
	1977	+ [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr,
	1978	+ [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr,
	1979	+ [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr,
	1980	+ [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr,
	1981	+ [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr,
	1982	+ [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr,
	1983	+ [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =
	1984	+ &disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,
	1985	+ [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr,
	1986	+ [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr,
	1987	+ [DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr,
	1988	+ [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr,
	1989	+ [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr,
	1990	+ [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr,
	1991	+ [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr,
	1992	+ [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr,
	1993	+ [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr,
	1994	+ [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr,
	1995	+ [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr,
	1996	+ [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr,
	1997	+ [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr,
	1998	+ [DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr,
	1999	+ [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr,
	2000	+ [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr,
	2001	+ [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr,
	2002	+ [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr,
	2003	+ [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr,
	2004	+ [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr,
	2005	+ [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
	2006	+ [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
	2007	+ [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
	2008	+ [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
	2009	+ [DISP_CC_MDSS_HDMI_AHBM_CLK] = &disp_cc_mdss_hdmi_ahbm_clk.clkr,
	2010	+ [DISP_CC_MDSS_HDMI_APP_CLK] = &disp_cc_mdss_hdmi_app_clk.clkr,
	2011	+ [DISP_CC_MDSS_HDMI_APP_CLK_SRC] = &disp_cc_mdss_hdmi_app_clk_src.clkr,
	2012	+ [DISP_CC_MDSS_HDMI_CRYPTO_CLK] = &disp_cc_mdss_hdmi_crypto_clk.clkr,
	2013	+ [DISP_CC_MDSS_HDMI_INTF_CLK] = &disp_cc_mdss_hdmi_intf_clk.clkr,
	2014	+ [DISP_CC_MDSS_HDMI_PCLK_CLK] = &disp_cc_mdss_hdmi_pclk_clk.clkr,
	2015	+ [DISP_CC_MDSS_HDMI_PCLK_CLK_SRC] = &disp_cc_mdss_hdmi_pclk_clk_src.clkr,
	2016	+ [DISP_CC_MDSS_HDMI_PCLK_DIV_CLK_SRC] = &disp_cc_mdss_hdmi_pclk_div_clk_src.clkr,
	2017	+ [DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr,
	2018	+ [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
	2019	+ [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
	2020	+ [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr,
	2021	+ [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
	2022	+ [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
	2023	+ [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
	2024	+ [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
	2025	+ [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
	2026	+ [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
	2027	+ [DISP_CC_MDSS_PCLK2_CLK] = &disp_cc_mdss_pclk2_clk.clkr,
	2028	+ [DISP_CC_MDSS_PCLK2_CLK_SRC] = &disp_cc_mdss_pclk2_clk_src.clkr,
	2029	+ [DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr,
	2030	+ [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
	2031	+ [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
	2032	+ [DISP_CC_OSC_CLK] = &disp_cc_osc_clk.clkr,
	2033	+ [DISP_CC_OSC_CLK_SRC] = &disp_cc_osc_clk_src.clkr,
	2034	+ [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
	2035	+ [DISP_CC_PLL1] = &disp_cc_pll1.clkr,
	2036	+ [DISP_CC_PLL2] = &disp_cc_pll2.clkr,
	2037	+ [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
	2038	+ [DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr,
	2039	+};
	2040	+
	2041	+static const struct qcom_reset_map disp_cc_eliza_resets[] = {
	2042	+ [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
	2043	+ [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
	2044	+ [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
	2045	+};
	2046	+
	2047	+static struct gdsc *disp_cc_eliza_gdscs[] = {
	2048	+ [MDSS_GDSC] = &mdss_gdsc,
	2049	+ [MDSS_INT2_GDSC] = &mdss_int2_gdsc,
	2050	+};
	2051	+
	2052	+static const struct regmap_config disp_cc_eliza_regmap_config = {
	2053	+ .reg_bits = 32,
	2054	+ .reg_stride = 4,
	2055	+ .val_bits = 32,
	2056	+ .max_register = 0xf004, /* 0x10000, 0x10004 and maybe others are for TZ */
	2057	+ .fast_io = true,
	2058	+};
	2059	+
	2060	+static struct clk_alpha_pll *disp_cc_eliza_plls[] = {
	2061	+ &disp_cc_pll0,
	2062	+ &disp_cc_pll1,
	2063	+ &disp_cc_pll2,
	2064	+};
	2065	+
	2066	+static const u32 disp_cc_eliza_critical_cbcrs[] = {
	2067	+ 0xe07c, /* DISP_CC_SLEEP_CLK */
	2068	+ 0xe05c, /* DISP_CC_XO_CLK */
	2069	+ 0xc00c, /* DISP_CC_MDSS_RSCC_AHB_CLK */
	2070	+ 0xc008, /* DISP_CC_MDSS_RSCC_VSYNC_CLK */
	2071	+};
	2072	+
	2073	+static void clk_eliza_regs_configure(struct device dev, struct regmap regmap)
	2074	+{
	2075	+ /* Enable clock gating for MDP clocks */
	2076	+ regmap_set_bits(regmap, DISP_CC_MISC_CMD, BIT(4));
	2077	+}
	2078	+
	2079	+static const struct qcom_cc_driver_data disp_cc_eliza_driver_data = {
	2080	+ .alpha_plls = disp_cc_eliza_plls,
	2081	+ .num_alpha_plls = ARRAY_SIZE(disp_cc_eliza_plls),
	2082	+ .clk_cbcrs = disp_cc_eliza_critical_cbcrs,
	2083	+ .num_clk_cbcrs = ARRAY_SIZE(disp_cc_eliza_critical_cbcrs),
	2084	+ .clk_regs_configure = clk_eliza_regs_configure,
	2085	+};
	2086	+
	2087	+static const struct qcom_cc_desc disp_cc_eliza_desc = {
	2088	+ .config = &disp_cc_eliza_regmap_config,
	2089	+ .clks = disp_cc_eliza_clocks,
	2090	+ .num_clks = ARRAY_SIZE(disp_cc_eliza_clocks),
	2091	+ .resets = disp_cc_eliza_resets,
	2092	+ .num_resets = ARRAY_SIZE(disp_cc_eliza_resets),
	2093	+ .gdscs = disp_cc_eliza_gdscs,
	2094	+ .num_gdscs = ARRAY_SIZE(disp_cc_eliza_gdscs),
	2095	+ .use_rpm = true,
	2096	+ .driver_data = &disp_cc_eliza_driver_data,
	2097	+};
	2098	+
	2099	+static const struct of_device_id disp_cc_eliza_match_table[] = {
	2100	+ { .compatible = "qcom,eliza-dispcc" },
	2101	+ { }
	2102	+};
	2103	+MODULE_DEVICE_TABLE(of, disp_cc_eliza_match_table);
	2104	+
	2105	+static int disp_cc_eliza_probe(struct platform_device *pdev)
	2106	+{
	2107	+ return qcom_cc_probe(pdev, &disp_cc_eliza_desc);
	2108	+}
	2109	+
	2110	+static struct platform_driver disp_cc_eliza_driver = {
	2111	+ .probe = disp_cc_eliza_probe,
	2112	+ .driver = {
	2113	+ .name = "dispcc-eliza",
	2114	+ .of_match_table = disp_cc_eliza_match_table,
	2115	+ },
	2116	+};
	2117	+
	2118	+module_platform_driver(disp_cc_eliza_driver);
	2119	+
	2120	+MODULE_DESCRIPTION("QTI DISPCC Eliza Driver");
	2121	+MODULE_LICENSE("GPL");

drivers/clk/qcom/dispcc-glymur.c+4−8

@@ -6,9 +6,7 @@ · 5 unmodified lines
6	6	#include <linux/clk-provider.h>
7	7	#include <linux/mod_devicetable.h>
8	8	#include <linux/module.h>
9		−#include <linux/of.h>
10	9	#include <linux/platform_device.h>
11		−#include <linux/pm_runtime.h>
12	10	#include <linux/regmap.h>
13	11
14	12	#include <dt-bindings/clock/qcom,glymur-dispcc.h>
@@ -417,7 +415,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { · 402 unmodified lines
417	415	.parent_data = disp_cc_parent_data_1,
418	416	.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
419	417	.flags = CLK_SET_RATE_PARENT,
420		− .ops = &clk_dp_ops,
	418	+ .ops = &clk_rcg2_shared_ops,
421	419	},
422	420	};
423	421
@@ -747,7 +745,6 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { · 323 unmodified lines
747	745	&disp_cc_mdss_byte0_clk_src.clkr.hw,
748	746	},
749	747	.num_parents = 1,
750		− .flags = CLK_SET_RATE_PARENT,
751	748	.ops = &clk_regmap_div_ops,
752	749	},
753	750	};
@@ -762,7 +759,6 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { · 8 unmodified lines
762	759	&disp_cc_mdss_byte1_clk_src.clkr.hw,
763	760	},
764	761	.num_parents = 1,
765		− .flags = CLK_SET_RATE_PARENT,
766	762	.ops = &clk_regmap_div_ops,
767	763	},
768	764	};
@@ -1925,7 +1921,7 @@ static struct clk_alpha_pll *disp_cc_glymur_plls[] = { · 1156 unmodified lines
1925	1921	&disp_cc_pll1,
1926	1922	};
1927	1923
1928		−static u32 disp_cc_glymur_critical_cbcrs[] = {
	1924	+static const u32 disp_cc_glymur_critical_cbcrs[] = {
1929	1925	0xe07c, /* DISP_CC_SLEEP_CLK */
1930	1926	0xe05c, /* DISP_CC_XO_CLK */
1931	1927	};
@@ -1938,7 +1934,7 @@ static const struct regmap_config disp_cc_glymur_regmap_config = { · 6 unmodified lines
1938	1934	.fast_io = true,
1939	1935	};
1940	1936
1941		−static struct qcom_cc_driver_data disp_cc_glymur_driver_data = {
	1937	+static const struct qcom_cc_driver_data disp_cc_glymur_driver_data = {
1942	1938	.alpha_plls = disp_cc_glymur_plls,
1943	1939	.num_alpha_plls = ARRAY_SIZE(disp_cc_glymur_plls),
1944	1940	.clk_cbcrs = disp_cc_glymur_critical_cbcrs,
@@ -1978,5 +1974,5 @@ static struct platform_driver disp_cc_glymur_driver = { · 33 unmodified lines
1978	1974
1979	1975	module_platform_driver(disp_cc_glymur_driver);
1980	1976
1981		−MODULE_DESCRIPTION("QTI DISPCC GLYMUR Driver");
	1977	+MODULE_DESCRIPTION("QTI DISPCC Glymur Driver");
1982	1978	MODULE_LICENSE("GPL");

drivers/clk/qcom/dispcc-kaanapali.c+2−6

@@ -6,9 +6,7 @@ · 5 unmodified lines
6	6	#include <linux/clk-provider.h>
7	7	#include <linux/mod_devicetable.h>
8	8	#include <linux/module.h>
9		−#include <linux/of.h>
10	9	#include <linux/platform_device.h>
11		−#include <linux/pm_runtime.h>
12	10	#include <linux/regmap.h>
13	11
14	12	#include <dt-bindings/clock/qcom,kaanapali-dispcc.h>
@@ -800,7 +798,6 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { · 785 unmodified lines
800	798	&disp_cc_mdss_byte0_clk_src.clkr.hw,
801	799	},
802	800	.num_parents = 1,
803		− .flags = CLK_SET_RATE_PARENT,
804	801	.ops = &clk_regmap_div_ops,
805	802	},
806	803	};
@@ -815,7 +812,6 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { · 8 unmodified lines
815	812	&disp_cc_mdss_byte1_clk_src.clkr.hw,
816	813	},
817	814	.num_parents = 1,
818		− .flags = CLK_SET_RATE_PARENT,
819	815	.ops = &clk_regmap_div_ops,
820	816	},
821	817	};
@@ -1890,7 +1886,7 @@ static struct clk_alpha_pll *disp_cc_kaanapali_plls[] = { · 1068 unmodified lines
1890	1886	&disp_cc_pll2,
1891	1887	};
1892	1888
1893		−static u32 disp_cc_kaanapali_critical_cbcrs[] = {
	1889	+static const u32 disp_cc_kaanapali_critical_cbcrs[] = {
1894	1890	0xe064, /* DISP_CC_SLEEP_CLK */
1895	1891	0xe05c, /* DISP_CC_XO_CLK */
1896	1892	0xc00c, /* DISP_CC_MDSS_RSCC_AHB_CLK */
@@ -1911,7 +1907,7 @@ static void clk_kaanapali_regs_configure(struct device dev, struct regmap regm · 14 unmodified lines
1911	1907	regmap_update_bits(regmap, DISP_CC_MISC_CMD, BIT(4), BIT(4));
1912	1908	}
1913	1909
1914		−static struct qcom_cc_driver_data disp_cc_kaanapali_driver_data = {
	1910	+static const struct qcom_cc_driver_data disp_cc_kaanapali_driver_data = {
1915	1911	.alpha_plls = disp_cc_kaanapali_plls,
1916	1912	.num_alpha_plls = ARRAY_SIZE(disp_cc_kaanapali_plls),
1917	1913	.clk_cbcrs = disp_cc_kaanapali_critical_cbcrs,

drivers/clk/qcom/dispcc-milos.c+3−6

@@ -4,12 +4,10 @@ · 3 unmodified lines
4	4	* Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
5	5	*/
6	6
7		−#include <linux/clk.h>
8	7	#include <linux/clk-provider.h>
9		−#include <linux/err.h>
10	8	#include <linux/kernel.h>
	9	+#include <linux/mod_devicetable.h>
11	10	#include <linux/module.h>
12		−#include <linux/of.h>
13	11	#include <linux/platform_device.h>
14	12	#include <linux/regmap.h>
15	13
@@ -394,7 +392,6 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { · 378 unmodified lines
394	392	&disp_cc_mdss_byte0_clk_src.clkr.hw,
395	393	},
396	394	.num_parents = 1,
397		− .flags = CLK_SET_RATE_PARENT,
398	395	.ops = &clk_regmap_div_ops,
399	396	},
400	397	};
@@ -909,7 +906,7 @@ static struct clk_alpha_pll *disp_cc_milos_plls[] = { · 508 unmodified lines
909	906	&disp_cc_pll0,
910	907	};
911	908
912		−static u32 disp_cc_milos_critical_cbcrs[] = {
	909	+static const u32 disp_cc_milos_critical_cbcrs[] = {
913	910	0xe06c, /* DISP_CC_SLEEP_CLK */
914	911	0xe04c, /* DISP_CC_XO_CLK */
915	912	};
@@ -929,7 +926,7 @@ static void disp_cc_milos_clk_regs_configure(struct device dev, struct regmap · 13 unmodified lines
929	926	}
930	927
931	928
932		−static struct qcom_cc_driver_data disp_cc_milos_driver_data = {
	929	+static const struct qcom_cc_driver_data disp_cc_milos_driver_data = {
933	930	.alpha_plls = disp_cc_milos_plls,
934	931	.num_alpha_plls = ARRAY_SIZE(disp_cc_milos_plls),
935	932	.clk_cbcrs = disp_cc_milos_critical_cbcrs,

drivers/clk/qcom/dispcc-qcs615.c+2−2

@@ -739,7 +739,7 @@ static struct clk_alpha_pll *disp_cc_qcs615_plls[] = { · 738 unmodified lines
739	739	&disp_cc_pll0,
740	740	};
741	741
742		−static u32 disp_cc_qcs615_critical_cbcrs[] = {
	742	+static const u32 disp_cc_qcs615_critical_cbcrs[] = {
743	743	0x6054, /* DISP_CC_XO_CLK */
744	744	};
745	745
@@ -751,7 +751,7 @@ static const struct regmap_config disp_cc_qcs615_regmap_config = { · 5 unmodified lines
751	751	.fast_io = true,
752	752	};
753	753
754		−static struct qcom_cc_driver_data disp_cc_qcs615_driver_data = {
	754	+static const struct qcom_cc_driver_data disp_cc_qcs615_driver_data = {
755	755	.alpha_plls = disp_cc_qcs615_plls,
756	756	.num_alpha_plls = ARRAY_SIZE(disp_cc_qcs615_plls),
757	757	.clk_cbcrs = disp_cc_qcs615_critical_cbcrs,

drivers/clk/qcom/dispcc-sc7180.c+8−0

@@ -17,6 +17,7 @@ · 16 unmodified lines
17	17	#include "clk-regmap-divider.h"
18	18	#include "common.h"
19	19	#include "gdsc.h"
	20	+#include "reset.h"
20	21
21	22	enum {
22	23	P_BI_TCXO,
@@ -636,6 +637,11 @@ static struct gdsc mdss_gdsc = { · 613 unmodified lines
636	637	.flags = HW_CTRL,
637	638	};
638	639
	640	+static const struct qcom_reset_map disp_cc_sc7180_resets[] = {
	641	+ [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
	642	+ [DISP_CC_MDSS_RSCC_BCR] = { 0x4000 },
	643	+};
	644	+
639	645	static struct gdsc *disp_cc_sc7180_gdscs[] = {
640	646	[MDSS_GDSC] = &mdss_gdsc,
641	647	};
@@ -687,6 +693,8 @@ static const struct qcom_cc_desc disp_cc_sc7180_desc = { · 45 unmodified lines
687	693	.config = &disp_cc_sc7180_regmap_config,
688	694	.clks = disp_cc_sc7180_clocks,
689	695	.num_clks = ARRAY_SIZE(disp_cc_sc7180_clocks),
	696	+ .resets = disp_cc_sc7180_resets,
	697	+ .num_resets = ARRAY_SIZE(disp_cc_sc7180_resets),
690	698	.gdscs = disp_cc_sc7180_gdscs,
691	699	.num_gdscs = ARRAY_SIZE(disp_cc_sc7180_gdscs),
692	700	};

drivers/clk/qcom/dispcc-sc8280xp.c+0−4

@@ -1160,7 +1160,6 @@ static struct clk_regmap_div disp0_cc_mdss_byte0_div_clk_src = { · 1159 unmodified lines
1160	1160	&disp0_cc_mdss_byte0_clk_src.clkr.hw,
1161	1161	},
1162	1162	.num_parents = 1,
1163		− .flags = CLK_SET_RATE_PARENT,
1164	1163	.ops = &clk_regmap_div_ops,
1165	1164	},
1166	1165	};
@@ -1175,7 +1174,6 @@ static struct clk_regmap_div disp1_cc_mdss_byte0_div_clk_src = { · 8 unmodified lines
1175	1174	&disp1_cc_mdss_byte0_clk_src.clkr.hw,
1176	1175	},
1177	1176	.num_parents = 1,
1178		− .flags = CLK_SET_RATE_PARENT,
1179	1177	.ops = &clk_regmap_div_ops,
1180	1178	},
1181	1179	};
@@ -1190,7 +1188,6 @@ static struct clk_regmap_div disp0_cc_mdss_byte1_div_clk_src = { · 8 unmodified lines
1190	1188	&disp0_cc_mdss_byte1_clk_src.clkr.hw,
1191	1189	},
1192	1190	.num_parents = 1,
1193		− .flags = CLK_SET_RATE_PARENT,
1194	1191	.ops = &clk_regmap_div_ops,
1195	1192	},
1196	1193	};
@@ -1205,7 +1202,6 @@ static struct clk_regmap_div disp1_cc_mdss_byte1_div_clk_src = { · 8 unmodified lines
1205	1202	&disp1_cc_mdss_byte1_clk_src.clkr.hw,
1206	1203	},
1207	1204	.num_parents = 1,
1208		− .flags = CLK_SET_RATE_PARENT,
1209	1205	.ops = &clk_regmap_div_ops,
1210	1206	},
1211	1207	};

drivers/clk/qcom/dispcc-sm4450.c+0−1

@@ -335,7 +335,6 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { · 334 unmodified lines
335	335	&disp_cc_mdss_byte0_clk_src.clkr.hw,
336	336	},
337	337	.num_parents = 1,
338		− .flags = CLK_SET_RATE_PARENT,
339	338	.ops = &clk_regmap_div_ops,
340	339	},
341	340	};

drivers/clk/qcom/dispcc-sm6115.c+7−0

@@ -22,6 +22,7 @@ · 21 unmodified lines
22	22	#include "clk-regmap-divider.h"
23	23	#include "common.h"
24	24	#include "gdsc.h"
	25	+#include "reset.h"
25	26
26	27	enum {
27	28	DT_BI_TCXO,
@@ -511,6 +512,10 @@ static struct clk_branch disp_cc_sleep_clk = { · 483 unmodified lines
511	512	},
512	513	};
513	514
	515	+static const struct qcom_reset_map disp_cc_sm6115_resets[] = {
	516	+ [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
	517	+};
	518	+
514	519	static struct gdsc mdss_gdsc = {
515	520	.gdscr = 0x3000,
516	521	.pd = {
@@ -561,6 +566,8 @@ static const struct qcom_cc_desc disp_cc_sm6115_desc = { · 44 unmodified lines
561	566	.config = &disp_cc_sm6115_regmap_config,
562	567	.clks = disp_cc_sm6115_clocks,
563	568	.num_clks = ARRAY_SIZE(disp_cc_sm6115_clocks),
	569	+ .resets = disp_cc_sm6115_resets,
	570	+ .num_resets = ARRAY_SIZE(disp_cc_sm6115_resets),
564	571	.gdscs = disp_cc_sm6115_gdscs,
565	572	.num_gdscs = ARRAY_SIZE(disp_cc_sm6115_gdscs),
566	573	};

drivers/clk/qcom/dispcc-sm6125.c+7−0

@@ -17,6 +17,7 @@ · 16 unmodified lines
17	17	#include "clk-regmap.h"
18	18	#include "common.h"
19	19	#include "gdsc.h"
	20	+#include "reset.h"
20	21
21	22	enum {
22	23	P_BI_TCXO,
@@ -607,6 +608,10 @@ static struct clk_branch disp_cc_xo_clk = { · 584 unmodified lines
607	608	},
608	609	};
609	610
	611	+static const struct qcom_reset_map disp_cc_sm6125_resets[] = {
	612	+ [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
	613	+};
	614	+
610	615	static struct gdsc mdss_gdsc = {
611	616	.gdscr = 0x3000,
612	617	.pd = {
@@ -663,6 +668,8 @@ static const struct qcom_cc_desc disp_cc_sm6125_desc = { · 50 unmodified lines
663	668	.config = &disp_cc_sm6125_regmap_config,
664	669	.clks = disp_cc_sm6125_clocks,
665	670	.num_clks = ARRAY_SIZE(disp_cc_sm6125_clocks),
	671	+ .resets = disp_cc_sm6125_resets,
	672	+ .num_resets = ARRAY_SIZE(disp_cc_sm6125_resets),
666	673	.gdscs = disp_cc_sm6125_gdscs,
667	674	.num_gdscs = ARRAY_SIZE(disp_cc_sm6125_gdscs),
668	675	};

drivers/clk/qcom/dispcc-sm8250.c+3−3

@@ -578,7 +578,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { · 577 unmodified lines
578	578	.name = "disp_cc_mdss_pclk0_clk_src",
579	579	.parent_data = disp_cc_parent_data_6,
580	580	.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
581		− .flags = CLK_SET_RATE_PARENT,
	581	+ .flags = CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
582	582	.ops = &clk_pixel_ops,
583	583	},
584	584	};
@@ -592,7 +592,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { · 7 unmodified lines
592	592	.name = "disp_cc_mdss_pclk1_clk_src",
593	593	.parent_data = disp_cc_parent_data_6,
594	594	.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
595		− .flags = CLK_SET_RATE_PARENT,
	595	+ .flags = CLK_SET_RATE_PARENT \| CLK_OPS_PARENT_ENABLE,
596	596	.ops = &clk_pixel_ops,
597	597	},
598	598	};
@@ -632,7 +632,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { · 33 unmodified lines
632	632	.parent_data = disp_cc_parent_data_1,
633	633	.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
634	634	.flags = CLK_SET_RATE_PARENT,
635		− .ops = &clk_rcg2_ops,
	635	+ .ops = &clk_rcg2_shared_ops,
636	636	},
637	637	};
638	638

drivers/clk/qcom/dispcc-sm8450.c+1−1

@@ -409,7 +409,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { · 408 unmodified lines
409	409	.parent_data = disp_cc_parent_data_1,
410	410	.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
411	411	.flags = CLK_SET_RATE_PARENT,
412		− .ops = &clk_dp_ops,
	412	+ .ops = &clk_rcg2_ops,
413	413	},
414	414	};
415	415

drivers/clk/qcom/dispcc0-sa8775p.c+0−2

@@ -591,7 +591,6 @@ static struct clk_regmap_div mdss_0_disp_cc_mdss_byte0_div_clk_src = { · 590 unmodified lines
591	591	&mdss_0_disp_cc_mdss_byte0_clk_src.clkr.hw,
592	592	},
593	593	.num_parents = 1,
594		− .flags = CLK_SET_RATE_PARENT,
595	594	.ops = &clk_regmap_div_ops,
596	595	},
597	596	};
@@ -606,7 +605,6 @@ static struct clk_regmap_div mdss_0_disp_cc_mdss_byte1_div_clk_src = { · 8 unmodified lines
606	605	&mdss_0_disp_cc_mdss_byte1_clk_src.clkr.hw,
607	606	},
608	607	.num_parents = 1,
609		− .flags = CLK_SET_RATE_PARENT,
610	608	.ops = &clk_regmap_div_ops,
611	609	},
612	610	};

drivers/clk/qcom/dispcc1-sa8775p.c+0−2

@@ -591,7 +591,6 @@ static struct clk_regmap_div mdss_1_disp_cc_mdss_byte0_div_clk_src = { · 590 unmodified lines
591	591	&mdss_1_disp_cc_mdss_byte0_clk_src.clkr.hw,
592	592	},
593	593	.num_parents = 1,
594		− .flags = CLK_SET_RATE_PARENT,
595	594	.ops = &clk_regmap_div_ops,
596	595	},
597	596	};
@@ -606,7 +605,6 @@ static struct clk_regmap_div mdss_1_disp_cc_mdss_byte1_div_clk_src = { · 8 unmodified lines
606	605	&mdss_1_disp_cc_mdss_byte1_clk_src.clkr.hw,
607	606	},
608	607	.num_parents = 1,
609		− .flags = CLK_SET_RATE_PARENT,
610	608	.ops = &clk_regmap_div_ops,
611	609	},
612	610	};

drivers/clk/qcom/gcc-eliza.c+3105−0

@@ -0,0 +1,3105 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
	2	+/*
	3	+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
	4	+ */
	5	+
	6	+#include <linux/clk-provider.h>
	7	+#include <linux/mod_devicetable.h>
	8	+#include <linux/module.h>
	9	+#include <linux/platform_device.h>
	10	+#include <linux/regmap.h>
	11	+
	12	+#include <dt-bindings/clock/qcom,eliza-gcc.h>
	13	+
	14	+#include "clk-alpha-pll.h"
	15	+#include "clk-branch.h"
	16	+#include "clk-pll.h"
	17	+#include "clk-rcg.h"
	18	+#include "clk-regmap.h"
	19	+#include "clk-regmap-divider.h"
	20	+#include "clk-regmap-mux.h"
	21	+#include "clk-regmap-phy-mux.h"
	22	+#include "common.h"
	23	+#include "gdsc.h"
	24	+#include "reset.h"
	25	+
	26	+enum {
	27	+ DT_BI_TCXO,
	28	+ DT_SLEEP_CLK,
	29	+ DT_PCIE_0_PIPE_CLK,
	30	+ DT_PCIE_1_PIPE_CLK,
	31	+ DT_UFS_PHY_RX_SYMBOL_0_CLK,
	32	+ DT_UFS_PHY_RX_SYMBOL_1_CLK,
	33	+ DT_UFS_PHY_TX_SYMBOL_0_CLK,
	34	+ DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
	35	+};
	36	+
	37	+enum {
	38	+ P_BI_TCXO,
	39	+ P_GCC_GPLL0_OUT_EVEN,
	40	+ P_GCC_GPLL0_OUT_MAIN,
	41	+ P_GCC_GPLL4_OUT_MAIN,
	42	+ P_GCC_GPLL7_OUT_MAIN,
	43	+ P_GCC_GPLL8_OUT_MAIN,
	44	+ P_GCC_GPLL9_OUT_MAIN,
	45	+ P_PCIE_0_PIPE_CLK,
	46	+ P_PCIE_1_PIPE_CLK,
	47	+ P_SLEEP_CLK,
	48	+ P_UFS_PHY_RX_SYMBOL_0_CLK,
	49	+ P_UFS_PHY_RX_SYMBOL_1_CLK,
	50	+ P_UFS_PHY_TX_SYMBOL_0_CLK,
	51	+ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
	52	+};
	53	+
	54	+static struct clk_alpha_pll gcc_gpll0 = {
	55	+ .offset = 0x0,
	56	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
	57	+ .clkr = {
	58	+ .enable_reg = 0x52020,
	59	+ .enable_mask = BIT(0),
	60	+ .hw.init = &(const struct clk_init_data) {
	61	+ .name = "gcc_gpll0",
	62	+ .parent_data = &(const struct clk_parent_data) {
	63	+ .index = DT_BI_TCXO,
	64	+ },
	65	+ .num_parents = 1,
	66	+ .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
	67	+ },
	68	+ },
	69	+};
	70	+
	71	+static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
	72	+ { 0x1, 2 },
	73	+ { }
	74	+};
	75	+
	76	+static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
	77	+ .offset = 0x0,
	78	+ .post_div_shift = 10,
	79	+ .post_div_table = post_div_table_gcc_gpll0_out_even,
	80	+ .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
	81	+ .width = 4,
	82	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
	83	+ .clkr.hw.init = &(const struct clk_init_data) {
	84	+ .name = "gcc_gpll0_out_even",
	85	+ .parent_hws = (const struct clk_hw*[]) {
	86	+ &gcc_gpll0.clkr.hw,
	87	+ },
	88	+ .num_parents = 1,
	89	+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
	90	+ },
	91	+};
	92	+
	93	+static struct clk_alpha_pll gcc_gpll4 = {
	94	+ .offset = 0x4000,
	95	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
	96	+ .clkr = {
	97	+ .enable_reg = 0x52020,
	98	+ .enable_mask = BIT(4),
	99	+ .hw.init = &(const struct clk_init_data) {
	100	+ .name = "gcc_gpll4",
	101	+ .parent_data = &(const struct clk_parent_data) {
	102	+ .index = DT_BI_TCXO,
	103	+ },
	104	+ .num_parents = 1,
	105	+ .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
	106	+ },
	107	+ },
	108	+};
	109	+
	110	+static struct clk_alpha_pll gcc_gpll7 = {
	111	+ .offset = 0x7000,
	112	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
	113	+ .clkr = {
	114	+ .enable_reg = 0x52020,
	115	+ .enable_mask = BIT(7),
	116	+ .hw.init = &(const struct clk_init_data) {
	117	+ .name = "gcc_gpll7",
	118	+ .parent_data = &(const struct clk_parent_data) {
	119	+ .index = DT_BI_TCXO,
	120	+ },
	121	+ .num_parents = 1,
	122	+ .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
	123	+ },
	124	+ },
	125	+};
	126	+
	127	+static struct clk_alpha_pll gcc_gpll8 = {
	128	+ .offset = 0x8000,
	129	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
	130	+ .clkr = {
	131	+ .enable_reg = 0x52020,
	132	+ .enable_mask = BIT(8),
	133	+ .hw.init = &(const struct clk_init_data) {
	134	+ .name = "gcc_gpll8",
	135	+ .parent_data = &(const struct clk_parent_data) {
	136	+ .index = DT_BI_TCXO,
	137	+ },
	138	+ .num_parents = 1,
	139	+ .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
	140	+ },
	141	+ },
	142	+};
	143	+
	144	+static struct clk_alpha_pll gcc_gpll9 = {
	145	+ .offset = 0x9000,
	146	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
	147	+ .clkr = {
	148	+ .enable_reg = 0x52020,
	149	+ .enable_mask = BIT(9),
	150	+ .hw.init = &(const struct clk_init_data) {
	151	+ .name = "gcc_gpll9",
	152	+ .parent_data = &(const struct clk_parent_data) {
	153	+ .index = DT_BI_TCXO,
	154	+ },
	155	+ .num_parents = 1,
	156	+ .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
	157	+ },
	158	+ },
	159	+};
	160	+
	161	+static const struct parent_map gcc_parent_map_0[] = {
	162	+ { P_BI_TCXO, 0 },
	163	+ { P_GCC_GPLL0_OUT_MAIN, 1 },
	164	+ { P_GCC_GPLL0_OUT_EVEN, 6 },
	165	+};
	166	+
	167	+static const struct clk_parent_data gcc_parent_data_0[] = {
	168	+ { .index = DT_BI_TCXO },
	169	+ { .hw = &gcc_gpll0.clkr.hw },
	170	+ { .hw = &gcc_gpll0_out_even.clkr.hw },
	171	+};
	172	+
	173	+static const struct parent_map gcc_parent_map_1[] = {
	174	+ { P_BI_TCXO, 0 },
	175	+ { P_GCC_GPLL0_OUT_MAIN, 1 },
	176	+ { P_SLEEP_CLK, 5 },
	177	+ { P_GCC_GPLL0_OUT_EVEN, 6 },
	178	+};
	179	+
	180	+static const struct clk_parent_data gcc_parent_data_1[] = {
	181	+ { .index = DT_BI_TCXO },
	182	+ { .hw = &gcc_gpll0.clkr.hw },
	183	+ { .index = DT_SLEEP_CLK },
	184	+ { .hw = &gcc_gpll0_out_even.clkr.hw },
	185	+};
	186	+
	187	+static const struct parent_map gcc_parent_map_2[] = {
	188	+ { P_BI_TCXO, 0 },
	189	+ { P_GCC_GPLL0_OUT_MAIN, 1 },
	190	+ { P_GCC_GPLL4_OUT_MAIN, 5 },
	191	+ { P_GCC_GPLL0_OUT_EVEN, 6 },
	192	+};
	193	+
	194	+static const struct clk_parent_data gcc_parent_data_2[] = {
	195	+ { .index = DT_BI_TCXO },
	196	+ { .hw = &gcc_gpll0.clkr.hw },
	197	+ { .hw = &gcc_gpll4.clkr.hw },
	198	+ { .hw = &gcc_gpll0_out_even.clkr.hw },
	199	+};
	200	+
	201	+static const struct parent_map gcc_parent_map_3[] = {
	202	+ { P_BI_TCXO, 0 },
	203	+ { P_SLEEP_CLK, 5 },
	204	+};
	205	+
	206	+static const struct clk_parent_data gcc_parent_data_3[] = {
	207	+ { .index = DT_BI_TCXO },
	208	+ { .index = DT_SLEEP_CLK },
	209	+};
	210	+
	211	+static const struct parent_map gcc_parent_map_4[] = {
	212	+ { P_BI_TCXO, 0 },
	213	+ { P_GCC_GPLL0_OUT_MAIN, 1 },
	214	+ { P_GCC_GPLL7_OUT_MAIN, 2 },
	215	+ { P_GCC_GPLL0_OUT_EVEN, 6 },
	216	+};
	217	+
	218	+static const struct clk_parent_data gcc_parent_data_4[] = {
	219	+ { .index = DT_BI_TCXO },
	220	+ { .hw = &gcc_gpll0.clkr.hw },
	221	+ { .hw = &gcc_gpll7.clkr.hw },
	222	+ { .hw = &gcc_gpll0_out_even.clkr.hw },
	223	+};
	224	+
	225	+static const struct parent_map gcc_parent_map_5[] = {
	226	+ { P_BI_TCXO, 0 },
	227	+ { P_GCC_GPLL0_OUT_MAIN, 1 },
	228	+ { P_GCC_GPLL8_OUT_MAIN, 2 },
	229	+ { P_GCC_GPLL0_OUT_EVEN, 6 },
	230	+};
	231	+
	232	+static const struct clk_parent_data gcc_parent_data_5[] = {
	233	+ { .index = DT_BI_TCXO },
	234	+ { .hw = &gcc_gpll0.clkr.hw },
	235	+ { .hw = &gcc_gpll8.clkr.hw },
	236	+ { .hw = &gcc_gpll0_out_even.clkr.hw },
	237	+};
	238	+
	239	+static const struct parent_map gcc_parent_map_6[] = {
	240	+ { P_BI_TCXO, 0 },
	241	+};
	242	+
	243	+static const struct clk_parent_data gcc_parent_data_6[] = {
	244	+ { .index = DT_BI_TCXO },
	245	+};
	246	+
	247	+static const struct parent_map gcc_parent_map_7[] = {
	248	+ { P_BI_TCXO, 0 },
	249	+ { P_GCC_GPLL0_OUT_MAIN, 1 },
	250	+ { P_GCC_GPLL9_OUT_MAIN, 2 },
	251	+ { P_GCC_GPLL4_OUT_MAIN, 5 },
	252	+ { P_GCC_GPLL0_OUT_EVEN, 6 },
	253	+};
	254	+
	255	+static const struct clk_parent_data gcc_parent_data_7[] = {
	256	+ { .index = DT_BI_TCXO },
	257	+ { .hw = &gcc_gpll0.clkr.hw },
	258	+ { .hw = &gcc_gpll9.clkr.hw },
	259	+ { .hw = &gcc_gpll4.clkr.hw },
	260	+ { .hw = &gcc_gpll0_out_even.clkr.hw },
	261	+};
	262	+
	263	+static const struct parent_map gcc_parent_map_8[] = {
	264	+ { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
	265	+ { P_BI_TCXO, 2 },
	266	+ { P_GCC_GPLL0_OUT_EVEN, 3 },
	267	+};
	268	+
	269	+static const struct clk_parent_data gcc_parent_data_8[] = {
	270	+ { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK },
	271	+ { .index = DT_BI_TCXO },
	272	+ { .hw = &gcc_gpll0_out_even.clkr.hw },
	273	+};
	274	+
	275	+static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
	276	+ .reg = 0x6b080,
	277	+ .clkr = {
	278	+ .hw.init = &(const struct clk_init_data) {
	279	+ .name = "gcc_pcie_0_pipe_clk_src",
	280	+ .parent_data = &(const struct clk_parent_data){
	281	+ .index = DT_PCIE_0_PIPE_CLK,
	282	+ },
	283	+ .num_parents = 1,
	284	+ .ops = &clk_regmap_phy_mux_ops,
	285	+ },
	286	+ },
	287	+};
	288	+
	289	+static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
	290	+ .reg = 0xac07c,
	291	+ .clkr = {
	292	+ .hw.init = &(const struct clk_init_data) {
	293	+ .name = "gcc_pcie_1_pipe_clk_src",
	294	+ .parent_data = &(const struct clk_parent_data){
	295	+ .index = DT_PCIE_1_PIPE_CLK,
	296	+ },
	297	+ .num_parents = 1,
	298	+ .ops = &clk_regmap_phy_mux_ops,
	299	+ },
	300	+ },
	301	+};
	302	+
	303	+static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
	304	+ .reg = 0x77068,
	305	+ .clkr = {
	306	+ .hw.init = &(const struct clk_init_data) {
	307	+ .name = "gcc_ufs_phy_rx_symbol_0_clk_src",
	308	+ .parent_data = &(const struct clk_parent_data){
	309	+ .index = DT_UFS_PHY_RX_SYMBOL_0_CLK,
	310	+ },
	311	+ .num_parents = 1,
	312	+ .ops = &clk_regmap_phy_mux_ops,
	313	+ },
	314	+ },
	315	+};
	316	+
	317	+static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
	318	+ .reg = 0x770ec,
	319	+ .clkr = {
	320	+ .hw.init = &(const struct clk_init_data) {
	321	+ .name = "gcc_ufs_phy_rx_symbol_1_clk_src",
	322	+ .parent_data = &(const struct clk_parent_data){
	323	+ .index = DT_UFS_PHY_RX_SYMBOL_1_CLK,
	324	+ },
	325	+ .num_parents = 1,
	326	+ .ops = &clk_regmap_phy_mux_ops,
	327	+ },
	328	+ },
	329	+};
	330	+
	331	+static struct clk_regmap_phy_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
	332	+ .reg = 0x77058,
	333	+ .clkr = {
	334	+ .hw.init = &(const struct clk_init_data) {
	335	+ .name = "gcc_ufs_phy_tx_symbol_0_clk_src",
	336	+ .parent_data = &(const struct clk_parent_data){
	337	+ .index = DT_UFS_PHY_TX_SYMBOL_0_CLK,
	338	+ },
	339	+ .num_parents = 1,
	340	+ .ops = &clk_regmap_phy_mux_ops,
	341	+ },
	342	+ },
	343	+};
	344	+
	345	+static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
	346	+ .reg = 0x39070,
	347	+ .shift = 0,
	348	+ .width = 2,
	349	+ .parent_map = gcc_parent_map_8,
	350	+ .clkr = {
	351	+ .hw.init = &(const struct clk_init_data) {
	352	+ .name = "gcc_usb3_prim_phy_pipe_clk_src",
	353	+ .parent_data = gcc_parent_data_8,
	354	+ .num_parents = ARRAY_SIZE(gcc_parent_data_8),
	355	+ .ops = &clk_regmap_mux_closest_ops,
	356	+ },
	357	+ },
	358	+};
	359	+
	360	+static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
	361	+ F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
	362	+ F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
	363	+ F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
	364	+ { }
	365	+};
	366	+
	367	+static struct clk_rcg2 gcc_gp1_clk_src = {
	368	+ .cmd_rcgr = 0x64004,
	369	+ .mnd_width = 16,
	370	+ .hid_width = 5,
	371	+ .parent_map = gcc_parent_map_1,
	372	+ .freq_tbl = ftbl_gcc_gp1_clk_src,
	373	+ .hw_clk_ctrl = true,
	374	+ .clkr.hw.init = &(const struct clk_init_data) {
	375	+ .name = "gcc_gp1_clk_src",
	376	+ .parent_data = gcc_parent_data_1,
	377	+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
	378	+ .flags = CLK_SET_RATE_PARENT,
	379	+ .ops = &clk_rcg2_shared_ops,
	380	+ },
	381	+};
	382	+
	383	+static struct clk_rcg2 gcc_gp2_clk_src = {
	384	+ .cmd_rcgr = 0x65004,
	385	+ .mnd_width = 16,
	386	+ .hid_width = 5,
	387	+ .parent_map = gcc_parent_map_1,
	388	+ .freq_tbl = ftbl_gcc_gp1_clk_src,
	389	+ .hw_clk_ctrl = true,
	390	+ .clkr.hw.init = &(const struct clk_init_data) {
	391	+ .name = "gcc_gp2_clk_src",
	392	+ .parent_data = gcc_parent_data_1,
	393	+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
	394	+ .flags = CLK_SET_RATE_PARENT,
	395	+ .ops = &clk_rcg2_shared_ops,
	396	+ },
	397	+};
	398	+
	399	+static struct clk_rcg2 gcc_gp3_clk_src = {
	400	+ .cmd_rcgr = 0x66004,
	401	+ .mnd_width = 16,
	402	+ .hid_width = 5,
	403	+ .parent_map = gcc_parent_map_1,
	404	+ .freq_tbl = ftbl_gcc_gp1_clk_src,
	405	+ .hw_clk_ctrl = true,
	406	+ .clkr.hw.init = &(const struct clk_init_data) {
	407	+ .name = "gcc_gp3_clk_src",
	408	+ .parent_data = gcc_parent_data_1,
	409	+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
	410	+ .flags = CLK_SET_RATE_PARENT,
	411	+ .ops = &clk_rcg2_shared_ops,
	412	+ },
	413	+};
	414	+
	415	+static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
	416	+ F(19200000, P_BI_TCXO, 1, 0, 0),
	417	+ { }
	418	+};
	419	+
	420	+static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
	421	+ .cmd_rcgr = 0x6b084,
	422	+ .mnd_width = 16,
	423	+ .hid_width = 5,
	424	+ .parent_map = gcc_parent_map_3,
	425	+ .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
	426	+ .hw_clk_ctrl = true,
	427	+ .clkr.hw.init = &(const struct clk_init_data) {
	428	+ .name = "gcc_pcie_0_aux_clk_src",
	429	+ .parent_data = gcc_parent_data_3,
	430	+ .num_parents = ARRAY_SIZE(gcc_parent_data_3),
	431	+ .flags = CLK_SET_RATE_PARENT,
	432	+ .ops = &clk_rcg2_shared_ops,
	433	+ },
	434	+};
	435	+
	436	+static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
	437	+ F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
	438	+ { }
	439	+};
	440	+
	441	+static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
	442	+ .cmd_rcgr = 0x6b068,
	443	+ .mnd_width = 0,
	444	+ .hid_width = 5,
	445	+ .parent_map = gcc_parent_map_0,
	446	+ .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
	447	+ .hw_clk_ctrl = true,
	448	+ .clkr.hw.init = &(const struct clk_init_data) {
	449	+ .name = "gcc_pcie_0_phy_rchng_clk_src",
	450	+ .parent_data = gcc_parent_data_0,
	451	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	452	+ .flags = CLK_SET_RATE_PARENT,
	453	+ .ops = &clk_rcg2_shared_ops,
	454	+ },
	455	+};
	456	+
	457	+static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
	458	+ .cmd_rcgr = 0xac080,
	459	+ .mnd_width = 16,
	460	+ .hid_width = 5,
	461	+ .parent_map = gcc_parent_map_3,
	462	+ .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
	463	+ .hw_clk_ctrl = true,
	464	+ .clkr.hw.init = &(const struct clk_init_data) {
	465	+ .name = "gcc_pcie_1_aux_clk_src",
	466	+ .parent_data = gcc_parent_data_3,
	467	+ .num_parents = ARRAY_SIZE(gcc_parent_data_3),
	468	+ .flags = CLK_SET_RATE_PARENT,
	469	+ .ops = &clk_rcg2_shared_ops,
	470	+ },
	471	+};
	472	+
	473	+static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
	474	+ .cmd_rcgr = 0xac064,
	475	+ .mnd_width = 0,
	476	+ .hid_width = 5,
	477	+ .parent_map = gcc_parent_map_0,
	478	+ .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
	479	+ .hw_clk_ctrl = true,
	480	+ .clkr.hw.init = &(const struct clk_init_data) {
	481	+ .name = "gcc_pcie_1_phy_rchng_clk_src",
	482	+ .parent_data = gcc_parent_data_0,
	483	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	484	+ .flags = CLK_SET_RATE_PARENT,
	485	+ .ops = &clk_rcg2_shared_ops,
	486	+ },
	487	+};
	488	+
	489	+static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
	490	+ F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
	491	+ { }
	492	+};
	493	+
	494	+static struct clk_rcg2 gcc_pdm2_clk_src = {
	495	+ .cmd_rcgr = 0x33010,
	496	+ .mnd_width = 0,
	497	+ .hid_width = 5,
	498	+ .parent_map = gcc_parent_map_0,
	499	+ .freq_tbl = ftbl_gcc_pdm2_clk_src,
	500	+ .hw_clk_ctrl = true,
	501	+ .clkr.hw.init = &(const struct clk_init_data) {
	502	+ .name = "gcc_pdm2_clk_src",
	503	+ .parent_data = gcc_parent_data_0,
	504	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	505	+ .flags = CLK_SET_RATE_PARENT,
	506	+ .ops = &clk_rcg2_shared_ops,
	507	+ },
	508	+};
	509	+
	510	+static const struct freq_tbl ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src[] = {
	511	+ F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
	512	+ F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
	513	+ F(19200000, P_BI_TCXO, 1, 0, 0),
	514	+ F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
	515	+ F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
	516	+ F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
	517	+ F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
	518	+ F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
	519	+ F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
	520	+ F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
	521	+ F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
	522	+ F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
	523	+ F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
	524	+ F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
	525	+ F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
	526	+ F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
	527	+ F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
	528	+ F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0),
	529	+ { }
	530	+};
	531	+
	532	+static struct clk_init_data gcc_qupv3_wrap1_qspi_ref_clk_src_init = {
	533	+ .name = "gcc_qupv3_wrap1_qspi_ref_clk_src",
	534	+ .parent_data = gcc_parent_data_4,
	535	+ .num_parents = ARRAY_SIZE(gcc_parent_data_4),
	536	+ .flags = CLK_SET_RATE_PARENT,
	537	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	538	+};
	539	+
	540	+static struct clk_rcg2 gcc_qupv3_wrap1_qspi_ref_clk_src = {
	541	+ .cmd_rcgr = 0x188c0,
	542	+ .mnd_width = 16,
	543	+ .hid_width = 5,
	544	+ .parent_map = gcc_parent_map_4,
	545	+ .freq_tbl = ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src,
	546	+ .hw_clk_ctrl = true,
	547	+ .clkr.hw.init = &gcc_qupv3_wrap1_qspi_ref_clk_src_init,
	548	+};
	549	+
	550	+static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = {
	551	+ F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
	552	+ F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
	553	+ F(19200000, P_BI_TCXO, 1, 0, 0),
	554	+ F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
	555	+ F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
	556	+ F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
	557	+ F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
	558	+ F(61440000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 625),
	559	+ F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
	560	+ F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
	561	+ F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
	562	+ F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
	563	+ F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
	564	+ F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
	565	+ F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
	566	+ F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
	567	+ F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
	568	+ { }
	569	+};
	570	+
	571	+static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
	572	+ .name = "gcc_qupv3_wrap1_s0_clk_src",
	573	+ .parent_data = gcc_parent_data_0,
	574	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	575	+ .flags = CLK_SET_RATE_PARENT,
	576	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	577	+};
	578	+
	579	+static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
	580	+ .cmd_rcgr = 0x18014,
	581	+ .mnd_width = 16,
	582	+ .hid_width = 5,
	583	+ .parent_map = gcc_parent_map_0,
	584	+ .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
	585	+ .hw_clk_ctrl = true,
	586	+ .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
	587	+};
	588	+
	589	+static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
	590	+ .name = "gcc_qupv3_wrap1_s1_clk_src",
	591	+ .parent_data = gcc_parent_data_0,
	592	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	593	+ .flags = CLK_SET_RATE_PARENT,
	594	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	595	+};
	596	+
	597	+static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
	598	+ .cmd_rcgr = 0x18150,
	599	+ .mnd_width = 16,
	600	+ .hid_width = 5,
	601	+ .parent_map = gcc_parent_map_0,
	602	+ .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
	603	+ .hw_clk_ctrl = true,
	604	+ .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
	605	+};
	606	+
	607	+static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s3_clk_src[] = {
	608	+ F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
	609	+ F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
	610	+ F(19200000, P_BI_TCXO, 1, 0, 0),
	611	+ F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
	612	+ F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
	613	+ F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
	614	+ F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
	615	+ F(61440000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 625),
	616	+ F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
	617	+ F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
	618	+ F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
	619	+ F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
	620	+ F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
	621	+ { }
	622	+};
	623	+
	624	+static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
	625	+ .name = "gcc_qupv3_wrap1_s3_clk_src",
	626	+ .parent_data = gcc_parent_data_0,
	627	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	628	+ .flags = CLK_SET_RATE_PARENT,
	629	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	630	+};
	631	+
	632	+static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
	633	+ .cmd_rcgr = 0x182a0,
	634	+ .mnd_width = 16,
	635	+ .hid_width = 5,
	636	+ .parent_map = gcc_parent_map_0,
	637	+ .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
	638	+ .hw_clk_ctrl = true,
	639	+ .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
	640	+};
	641	+
	642	+static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
	643	+ .name = "gcc_qupv3_wrap1_s4_clk_src",
	644	+ .parent_data = gcc_parent_data_0,
	645	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	646	+ .flags = CLK_SET_RATE_PARENT,
	647	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	648	+};
	649	+
	650	+static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
	651	+ .cmd_rcgr = 0x183dc,
	652	+ .mnd_width = 16,
	653	+ .hid_width = 5,
	654	+ .parent_map = gcc_parent_map_0,
	655	+ .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
	656	+ .hw_clk_ctrl = true,
	657	+ .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
	658	+};
	659	+
	660	+static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s5_clk_src[] = {
	661	+ F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
	662	+ F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
	663	+ F(19200000, P_BI_TCXO, 1, 0, 0),
	664	+ F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
	665	+ F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
	666	+ F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
	667	+ F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
	668	+ F(61440000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 625),
	669	+ F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
	670	+ F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
	671	+ F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
	672	+ F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
	673	+ F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
	674	+ F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
	675	+ F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
	676	+ F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
	677	+ F(128000000, P_GCC_GPLL0_OUT_MAIN, 1, 16, 75),
	678	+ { }
	679	+};
	680	+
	681	+static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
	682	+ .name = "gcc_qupv3_wrap1_s5_clk_src",
	683	+ .parent_data = gcc_parent_data_0,
	684	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	685	+ .flags = CLK_SET_RATE_PARENT,
	686	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	687	+};
	688	+
	689	+static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
	690	+ .cmd_rcgr = 0x18518,
	691	+ .mnd_width = 16,
	692	+ .hid_width = 5,
	693	+ .parent_map = gcc_parent_map_0,
	694	+ .freq_tbl = ftbl_gcc_qupv3_wrap1_s5_clk_src,
	695	+ .hw_clk_ctrl = true,
	696	+ .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
	697	+};
	698	+
	699	+static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
	700	+ .name = "gcc_qupv3_wrap1_s6_clk_src",
	701	+ .parent_data = gcc_parent_data_0,
	702	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	703	+ .flags = CLK_SET_RATE_PARENT,
	704	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	705	+};
	706	+
	707	+static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
	708	+ .cmd_rcgr = 0x18654,
	709	+ .mnd_width = 16,
	710	+ .hid_width = 5,
	711	+ .parent_map = gcc_parent_map_0,
	712	+ .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
	713	+ .hw_clk_ctrl = true,
	714	+ .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
	715	+};
	716	+
	717	+static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
	718	+ .name = "gcc_qupv3_wrap1_s7_clk_src",
	719	+ .parent_data = gcc_parent_data_0,
	720	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	721	+ .flags = CLK_SET_RATE_PARENT,
	722	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	723	+};
	724	+
	725	+static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
	726	+ .cmd_rcgr = 0x18790,
	727	+ .mnd_width = 16,
	728	+ .hid_width = 5,
	729	+ .parent_map = gcc_parent_map_0,
	730	+ .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
	731	+ .hw_clk_ctrl = true,
	732	+ .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
	733	+};
	734	+
	735	+static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
	736	+ .name = "gcc_qupv3_wrap2_s0_clk_src",
	737	+ .parent_data = gcc_parent_data_0,
	738	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	739	+ .flags = CLK_SET_RATE_PARENT,
	740	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	741	+};
	742	+
	743	+static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
	744	+ .cmd_rcgr = 0x1e014,
	745	+ .mnd_width = 16,
	746	+ .hid_width = 5,
	747	+ .parent_map = gcc_parent_map_0,
	748	+ .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
	749	+ .hw_clk_ctrl = true,
	750	+ .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
	751	+};
	752	+
	753	+static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
	754	+ .name = "gcc_qupv3_wrap2_s1_clk_src",
	755	+ .parent_data = gcc_parent_data_0,
	756	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	757	+ .flags = CLK_SET_RATE_PARENT,
	758	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	759	+};
	760	+
	761	+static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
	762	+ .cmd_rcgr = 0x1e150,
	763	+ .mnd_width = 16,
	764	+ .hid_width = 5,
	765	+ .parent_map = gcc_parent_map_0,
	766	+ .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
	767	+ .hw_clk_ctrl = true,
	768	+ .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
	769	+};
	770	+
	771	+static const struct freq_tbl ftbl_gcc_qupv3_wrap2_s2_clk_src[] = {
	772	+ F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
	773	+ F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
	774	+ F(19200000, P_BI_TCXO, 1, 0, 0),
	775	+ F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
	776	+ F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
	777	+ F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
	778	+ F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
	779	+ F(61440000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 625),
	780	+ F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
	781	+ F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
	782	+ F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
	783	+ F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
	784	+ F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
	785	+ F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
	786	+ F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
	787	+ F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
	788	+ F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
	789	+ { }
	790	+};
	791	+
	792	+static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
	793	+ .name = "gcc_qupv3_wrap2_s2_clk_src",
	794	+ .parent_data = gcc_parent_data_4,
	795	+ .num_parents = ARRAY_SIZE(gcc_parent_data_4),
	796	+ .flags = CLK_SET_RATE_PARENT,
	797	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	798	+};
	799	+
	800	+static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
	801	+ .cmd_rcgr = 0x1e28c,
	802	+ .mnd_width = 16,
	803	+ .hid_width = 5,
	804	+ .parent_map = gcc_parent_map_4,
	805	+ .freq_tbl = ftbl_gcc_qupv3_wrap2_s2_clk_src,
	806	+ .hw_clk_ctrl = true,
	807	+ .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
	808	+};
	809	+
	810	+static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
	811	+ .name = "gcc_qupv3_wrap2_s3_clk_src",
	812	+ .parent_data = gcc_parent_data_0,
	813	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	814	+ .flags = CLK_SET_RATE_PARENT,
	815	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	816	+};
	817	+
	818	+static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
	819	+ .cmd_rcgr = 0x1e3c8,
	820	+ .mnd_width = 16,
	821	+ .hid_width = 5,
	822	+ .parent_map = gcc_parent_map_0,
	823	+ .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
	824	+ .hw_clk_ctrl = true,
	825	+ .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
	826	+};
	827	+
	828	+static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
	829	+ .name = "gcc_qupv3_wrap2_s4_clk_src",
	830	+ .parent_data = gcc_parent_data_0,
	831	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	832	+ .flags = CLK_SET_RATE_PARENT,
	833	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	834	+};
	835	+
	836	+static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
	837	+ .cmd_rcgr = 0x1e504,
	838	+ .mnd_width = 16,
	839	+ .hid_width = 5,
	840	+ .parent_map = gcc_parent_map_0,
	841	+ .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
	842	+ .hw_clk_ctrl = true,
	843	+ .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
	844	+};
	845	+
	846	+static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
	847	+ .name = "gcc_qupv3_wrap2_s5_clk_src",
	848	+ .parent_data = gcc_parent_data_0,
	849	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	850	+ .flags = CLK_SET_RATE_PARENT,
	851	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	852	+};
	853	+
	854	+static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
	855	+ .cmd_rcgr = 0x1e640,
	856	+ .mnd_width = 16,
	857	+ .hid_width = 5,
	858	+ .parent_map = gcc_parent_map_0,
	859	+ .freq_tbl = ftbl_gcc_qupv3_wrap1_s5_clk_src,
	860	+ .hw_clk_ctrl = true,
	861	+ .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
	862	+};
	863	+
	864	+static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
	865	+ .name = "gcc_qupv3_wrap2_s6_clk_src",
	866	+ .parent_data = gcc_parent_data_4,
	867	+ .num_parents = ARRAY_SIZE(gcc_parent_data_4),
	868	+ .flags = CLK_SET_RATE_PARENT,
	869	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	870	+};
	871	+
	872	+static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
	873	+ .cmd_rcgr = 0x1e77c,
	874	+ .mnd_width = 16,
	875	+ .hid_width = 5,
	876	+ .parent_map = gcc_parent_map_4,
	877	+ .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
	878	+ .hw_clk_ctrl = true,
	879	+ .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
	880	+};
	881	+
	882	+static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
	883	+ .name = "gcc_qupv3_wrap2_s7_clk_src",
	884	+ .parent_data = gcc_parent_data_0,
	885	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	886	+ .flags = CLK_SET_RATE_PARENT,
	887	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	888	+};
	889	+
	890	+static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
	891	+ .cmd_rcgr = 0x1e8b8,
	892	+ .mnd_width = 16,
	893	+ .hid_width = 5,
	894	+ .parent_map = gcc_parent_map_0,
	895	+ .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
	896	+ .hw_clk_ctrl = true,
	897	+ .clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init,
	898	+};
	899	+
	900	+static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
	901	+ F(144000, P_BI_TCXO, 16, 3, 25),
	902	+ F(400000, P_BI_TCXO, 12, 1, 4),
	903	+ F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3),
	904	+ F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
	905	+ F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
	906	+ F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
	907	+ F(192000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
	908	+ F(384000000, P_GCC_GPLL8_OUT_MAIN, 1, 0, 0),
	909	+ { }
	910	+};
	911	+
	912	+static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
	913	+ .cmd_rcgr = 0xa9018,
	914	+ .mnd_width = 8,
	915	+ .hid_width = 5,
	916	+ .parent_map = gcc_parent_map_5,
	917	+ .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
	918	+ .hw_clk_ctrl = true,
	919	+ .clkr.hw.init = &(const struct clk_init_data) {
	920	+ .name = "gcc_sdcc1_apps_clk_src",
	921	+ .parent_data = gcc_parent_data_5,
	922	+ .num_parents = ARRAY_SIZE(gcc_parent_data_5),
	923	+ .flags = CLK_SET_RATE_PARENT,
	924	+ .ops = &clk_rcg2_shared_floor_ops,
	925	+ },
	926	+};
	927	+
	928	+static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
	929	+ F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
	930	+ F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
	931	+ F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
	932	+ { }
	933	+};
	934	+
	935	+static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
	936	+ .cmd_rcgr = 0xa9040,
	937	+ .mnd_width = 0,
	938	+ .hid_width = 5,
	939	+ .parent_map = gcc_parent_map_5,
	940	+ .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
	941	+ .hw_clk_ctrl = true,
	942	+ .clkr.hw.init = &(const struct clk_init_data) {
	943	+ .name = "gcc_sdcc1_ice_core_clk_src",
	944	+ .parent_data = gcc_parent_data_5,
	945	+ .num_parents = ARRAY_SIZE(gcc_parent_data_5),
	946	+ .flags = CLK_SET_RATE_PARENT,
	947	+ .ops = &clk_rcg2_shared_floor_ops,
	948	+ },
	949	+};
	950	+
	951	+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
	952	+ F(400000, P_BI_TCXO, 12, 1, 4),
	953	+ F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
	954	+ F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
	955	+ F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
	956	+ F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
	957	+ F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
	958	+ { }
	959	+};
	960	+
	961	+static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
	962	+ .cmd_rcgr = 0x1401c,
	963	+ .mnd_width = 8,
	964	+ .hid_width = 5,
	965	+ .parent_map = gcc_parent_map_7,
	966	+ .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
	967	+ .hw_clk_ctrl = true,
	968	+ .clkr.hw.init = &(const struct clk_init_data) {
	969	+ .name = "gcc_sdcc2_apps_clk_src",
	970	+ .parent_data = gcc_parent_data_7,
	971	+ .num_parents = ARRAY_SIZE(gcc_parent_data_7),
	972	+ .flags = CLK_SET_RATE_PARENT,
	973	+ .ops = &clk_rcg2_shared_floor_ops,
	974	+ },
	975	+};
	976	+
	977	+static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
	978	+ F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
	979	+ F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
	980	+ F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
	981	+ F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
	982	+ { }
	983	+};
	984	+
	985	+static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
	986	+ .cmd_rcgr = 0x77034,
	987	+ .mnd_width = 8,
	988	+ .hid_width = 5,
	989	+ .parent_map = gcc_parent_map_2,
	990	+ .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
	991	+ .hw_clk_ctrl = true,
	992	+ .clkr.hw.init = &(const struct clk_init_data) {
	993	+ .name = "gcc_ufs_phy_axi_clk_src",
	994	+ .parent_data = gcc_parent_data_2,
	995	+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
	996	+ .flags = CLK_SET_RATE_PARENT,
	997	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	998	+ },
	999	+};
	1000	+
	1001	+static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
	1002	+ F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
	1003	+ F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
	1004	+ F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
	1005	+ { }
	1006	+};
	1007	+
	1008	+static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
	1009	+ .cmd_rcgr = 0x7708c,
	1010	+ .mnd_width = 0,
	1011	+ .hid_width = 5,
	1012	+ .parent_map = gcc_parent_map_2,
	1013	+ .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
	1014	+ .hw_clk_ctrl = true,
	1015	+ .clkr.hw.init = &(const struct clk_init_data) {
	1016	+ .name = "gcc_ufs_phy_ice_core_clk_src",
	1017	+ .parent_data = gcc_parent_data_2,
	1018	+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
	1019	+ .flags = CLK_SET_RATE_PARENT,
	1020	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	1021	+ },
	1022	+};
	1023	+
	1024	+static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
	1025	+ F(9600000, P_BI_TCXO, 2, 0, 0),
	1026	+ F(19200000, P_BI_TCXO, 1, 0, 0),
	1027	+ { }
	1028	+};
	1029	+
	1030	+static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
	1031	+ .cmd_rcgr = 0x770c0,
	1032	+ .mnd_width = 0,
	1033	+ .hid_width = 5,
	1034	+ .parent_map = gcc_parent_map_6,
	1035	+ .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
	1036	+ .hw_clk_ctrl = true,
	1037	+ .clkr.hw.init = &(const struct clk_init_data) {
	1038	+ .name = "gcc_ufs_phy_phy_aux_clk_src",
	1039	+ .parent_data = gcc_parent_data_6,
	1040	+ .num_parents = ARRAY_SIZE(gcc_parent_data_6),
	1041	+ .flags = CLK_SET_RATE_PARENT,
	1042	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	1043	+ },
	1044	+};
	1045	+
	1046	+static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
	1047	+ .cmd_rcgr = 0x770a4,
	1048	+ .mnd_width = 0,
	1049	+ .hid_width = 5,
	1050	+ .parent_map = gcc_parent_map_2,
	1051	+ .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
	1052	+ .hw_clk_ctrl = true,
	1053	+ .clkr.hw.init = &(const struct clk_init_data) {
	1054	+ .name = "gcc_ufs_phy_unipro_core_clk_src",
	1055	+ .parent_data = gcc_parent_data_2,
	1056	+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
	1057	+ .flags = CLK_SET_RATE_PARENT,
	1058	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	1059	+ },
	1060	+};
	1061	+
	1062	+static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
	1063	+ F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
	1064	+ F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
	1065	+ F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
	1066	+ F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
	1067	+ { }
	1068	+};
	1069	+
	1070	+static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
	1071	+ .cmd_rcgr = 0x39030,
	1072	+ .mnd_width = 8,
	1073	+ .hid_width = 5,
	1074	+ .parent_map = gcc_parent_map_0,
	1075	+ .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
	1076	+ .hw_clk_ctrl = true,
	1077	+ .clkr.hw.init = &(const struct clk_init_data) {
	1078	+ .name = "gcc_usb30_prim_master_clk_src",
	1079	+ .parent_data = gcc_parent_data_0,
	1080	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	1081	+ .flags = CLK_SET_RATE_PARENT,
	1082	+ .ops = &clk_rcg2_shared_ops,
	1083	+ },
	1084	+};
	1085	+
	1086	+static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
	1087	+ .cmd_rcgr = 0x39048,
	1088	+ .mnd_width = 0,
	1089	+ .hid_width = 5,
	1090	+ .parent_map = gcc_parent_map_0,
	1091	+ .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
	1092	+ .hw_clk_ctrl = true,
	1093	+ .clkr.hw.init = &(const struct clk_init_data) {
	1094	+ .name = "gcc_usb30_prim_mock_utmi_clk_src",
	1095	+ .parent_data = gcc_parent_data_0,
	1096	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	1097	+ .flags = CLK_SET_RATE_PARENT,
	1098	+ .ops = &clk_rcg2_shared_ops,
	1099	+ },
	1100	+};
	1101	+
	1102	+static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
	1103	+ .cmd_rcgr = 0x39074,
	1104	+ .mnd_width = 0,
	1105	+ .hid_width = 5,
	1106	+ .parent_map = gcc_parent_map_3,
	1107	+ .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
	1108	+ .hw_clk_ctrl = true,
	1109	+ .clkr.hw.init = &(const struct clk_init_data) {
	1110	+ .name = "gcc_usb3_prim_phy_aux_clk_src",
	1111	+ .parent_data = gcc_parent_data_3,
	1112	+ .num_parents = ARRAY_SIZE(gcc_parent_data_3),
	1113	+ .flags = CLK_SET_RATE_PARENT,
	1114	+ .ops = &clk_rcg2_shared_ops,
	1115	+ },
	1116	+};
	1117	+
	1118	+static struct clk_regmap_div gcc_pcie_0_pipe_div2_clk_src = {
	1119	+ .reg = 0x6b0a4,
	1120	+ .shift = 0,
	1121	+ .width = 4,
	1122	+ .clkr.hw.init = &(const struct clk_init_data) {
	1123	+ .name = "gcc_pcie_0_pipe_div2_clk_src",
	1124	+ .parent_hws = (const struct clk_hw*[]) {
	1125	+ &gcc_pcie_0_pipe_clk_src.clkr.hw,
	1126	+ },
	1127	+ .num_parents = 1,
	1128	+ .flags = CLK_SET_RATE_PARENT,
	1129	+ .ops = &clk_regmap_div_ro_ops,
	1130	+ },
	1131	+};
	1132	+
	1133	+static struct clk_regmap_div gcc_pcie_1_pipe_div2_clk_src = {
	1134	+ .reg = 0xac0a0,
	1135	+ .shift = 0,
	1136	+ .width = 4,
	1137	+ .clkr.hw.init = &(const struct clk_init_data) {
	1138	+ .name = "gcc_pcie_1_pipe_div2_clk_src",
	1139	+ .parent_hws = (const struct clk_hw*[]) {
	1140	+ &gcc_pcie_1_pipe_clk_src.clkr.hw,
	1141	+ },
	1142	+ .num_parents = 1,
	1143	+ .flags = CLK_SET_RATE_PARENT,
	1144	+ .ops = &clk_regmap_div_ro_ops,
	1145	+ },
	1146	+};
	1147	+
	1148	+static struct clk_regmap_div gcc_qupv3_wrap1_s2_clk_src = {
	1149	+ .reg = 0x1828c,
	1150	+ .shift = 0,
	1151	+ .width = 4,
	1152	+ .clkr.hw.init = &(const struct clk_init_data) {
	1153	+ .name = "gcc_qupv3_wrap1_s2_clk_src",
	1154	+ .parent_hws = (const struct clk_hw*[]) {
	1155	+ &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw,
	1156	+ },
	1157	+ .num_parents = 1,
	1158	+ .flags = CLK_SET_RATE_PARENT,
	1159	+ .ops = &clk_regmap_div_ro_ops,
	1160	+ },
	1161	+};
	1162	+
	1163	+static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
	1164	+ .reg = 0x39060,
	1165	+ .shift = 0,
	1166	+ .width = 4,
	1167	+ .clkr.hw.init = &(const struct clk_init_data) {
	1168	+ .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
	1169	+ .parent_hws = (const struct clk_hw*[]) {
	1170	+ &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
	1171	+ },
	1172	+ .num_parents = 1,
	1173	+ .flags = CLK_SET_RATE_PARENT,
	1174	+ .ops = &clk_regmap_div_ro_ops,
	1175	+ },
	1176	+};
	1177	+
	1178	+static struct clk_branch gcc_aggre_noc_pcie_axi_clk = {
	1179	+ .halt_reg = 0x10068,
	1180	+ .halt_check = BRANCH_HALT_SKIP,
	1181	+ .hwcg_reg = 0x10068,
	1182	+ .hwcg_bit = 1,
	1183	+ .clkr = {
	1184	+ .enable_reg = 0x52000,
	1185	+ .enable_mask = BIT(30),
	1186	+ .hw.init = &(const struct clk_init_data) {
	1187	+ .name = "gcc_aggre_noc_pcie_axi_clk",
	1188	+ .ops = &clk_branch2_ops,
	1189	+ },
	1190	+ },
	1191	+};
	1192	+
	1193	+static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
	1194	+ .halt_reg = 0x770f4,
	1195	+ .halt_check = BRANCH_HALT_VOTED,
	1196	+ .hwcg_reg = 0x770f4,
	1197	+ .hwcg_bit = 1,
	1198	+ .clkr = {
	1199	+ .enable_reg = 0x770f4,
	1200	+ .enable_mask = BIT(0),
	1201	+ .hw.init = &(const struct clk_init_data) {
	1202	+ .name = "gcc_aggre_ufs_phy_axi_clk",
	1203	+ .parent_hws = (const struct clk_hw*[]) {
	1204	+ &gcc_ufs_phy_axi_clk_src.clkr.hw,
	1205	+ },
	1206	+ .num_parents = 1,
	1207	+ .flags = CLK_SET_RATE_PARENT,
	1208	+ .ops = &clk_branch2_ops,
	1209	+ },
	1210	+ },
	1211	+};
	1212	+
	1213	+static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
	1214	+ .halt_reg = 0x39094,
	1215	+ .halt_check = BRANCH_HALT_VOTED,
	1216	+ .clkr = {
	1217	+ .enable_reg = 0x39094,
	1218	+ .enable_mask = BIT(0),
	1219	+ .hw.init = &(const struct clk_init_data) {
	1220	+ .name = "gcc_aggre_usb3_prim_axi_clk",
	1221	+ .parent_hws = (const struct clk_hw*[]) {
	1222	+ &gcc_usb30_prim_master_clk_src.clkr.hw,
	1223	+ },
	1224	+ .num_parents = 1,
	1225	+ .flags = CLK_SET_RATE_PARENT,
	1226	+ .ops = &clk_branch2_ops,
	1227	+ },
	1228	+ },
	1229	+};
	1230	+
	1231	+static struct clk_branch gcc_boot_rom_ahb_clk = {
	1232	+ .halt_reg = 0x38004,
	1233	+ .halt_check = BRANCH_HALT_VOTED,
	1234	+ .hwcg_reg = 0x38004,
	1235	+ .hwcg_bit = 1,
	1236	+ .clkr = {
	1237	+ .enable_reg = 0x52000,
	1238	+ .enable_mask = BIT(10),
	1239	+ .hw.init = &(const struct clk_init_data) {
	1240	+ .name = "gcc_boot_rom_ahb_clk",
	1241	+ .ops = &clk_branch2_ops,
	1242	+ },
	1243	+ },
	1244	+};
	1245	+
	1246	+static struct clk_branch gcc_camera_hf_axi_clk = {
	1247	+ .halt_reg = 0x26014,
	1248	+ .halt_check = BRANCH_HALT_SKIP,
	1249	+ .hwcg_reg = 0x26014,
	1250	+ .hwcg_bit = 1,
	1251	+ .clkr = {
	1252	+ .enable_reg = 0x26014,
	1253	+ .enable_mask = BIT(0),
	1254	+ .hw.init = &(const struct clk_init_data) {
	1255	+ .name = "gcc_camera_hf_axi_clk",
	1256	+ .ops = &clk_branch2_ops,
	1257	+ },
	1258	+ },
	1259	+};
	1260	+
	1261	+static struct clk_branch gcc_camera_sf_axi_clk = {
	1262	+ .halt_reg = 0x26024,
	1263	+ .halt_check = BRANCH_HALT_SKIP,
	1264	+ .hwcg_reg = 0x26024,
	1265	+ .hwcg_bit = 1,
	1266	+ .clkr = {
	1267	+ .enable_reg = 0x26024,
	1268	+ .enable_mask = BIT(0),
	1269	+ .hw.init = &(const struct clk_init_data) {
	1270	+ .name = "gcc_camera_sf_axi_clk",
	1271	+ .ops = &clk_branch2_ops,
	1272	+ },
	1273	+ },
	1274	+};
	1275	+
	1276	+static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {
	1277	+ .halt_reg = 0x10050,
	1278	+ .halt_check = BRANCH_HALT_SKIP,
	1279	+ .hwcg_reg = 0x10050,
	1280	+ .hwcg_bit = 1,
	1281	+ .clkr = {
	1282	+ .enable_reg = 0x52000,
	1283	+ .enable_mask = BIT(20),
	1284	+ .hw.init = &(const struct clk_init_data) {
	1285	+ .name = "gcc_cfg_noc_pcie_anoc_ahb_clk",
	1286	+ .ops = &clk_branch2_ops,
	1287	+ },
	1288	+ },
	1289	+};
	1290	+
	1291	+static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
	1292	+ .halt_reg = 0x39090,
	1293	+ .halt_check = BRANCH_HALT_VOTED,
	1294	+ .clkr = {
	1295	+ .enable_reg = 0x39090,
	1296	+ .enable_mask = BIT(0),
	1297	+ .hw.init = &(const struct clk_init_data) {
	1298	+ .name = "gcc_cfg_noc_usb3_prim_axi_clk",
	1299	+ .parent_hws = (const struct clk_hw*[]) {
	1300	+ &gcc_usb30_prim_master_clk_src.clkr.hw,
	1301	+ },
	1302	+ .num_parents = 1,
	1303	+ .flags = CLK_SET_RATE_PARENT,
	1304	+ .ops = &clk_branch2_ops,
	1305	+ },
	1306	+ },
	1307	+};
	1308	+
	1309	+static struct clk_branch gcc_cnoc_pcie_sf_axi_clk = {
	1310	+ .halt_reg = 0x10058,
	1311	+ .halt_check = BRANCH_HALT_VOTED,
	1312	+ .hwcg_reg = 0x10058,
	1313	+ .hwcg_bit = 1,
	1314	+ .clkr = {
	1315	+ .enable_reg = 0x52008,
	1316	+ .enable_mask = BIT(6),
	1317	+ .hw.init = &(const struct clk_init_data) {
	1318	+ .name = "gcc_cnoc_pcie_sf_axi_clk",
	1319	+ .ops = &clk_branch2_ops,
	1320	+ },
	1321	+ },
	1322	+};
	1323	+
	1324	+static struct clk_branch gcc_ddrss_gpu_axi_clk = {
	1325	+ .halt_reg = 0x71158,
	1326	+ .halt_check = BRANCH_HALT_SKIP,
	1327	+ .hwcg_reg = 0x71158,
	1328	+ .hwcg_bit = 1,
	1329	+ .clkr = {
	1330	+ .enable_reg = 0x71158,
	1331	+ .enable_mask = BIT(0),
	1332	+ .hw.init = &(const struct clk_init_data) {
	1333	+ .name = "gcc_ddrss_gpu_axi_clk",
	1334	+ .ops = &clk_branch2_aon_ops,
	1335	+ },
	1336	+ },
	1337	+};
	1338	+
	1339	+static struct clk_branch gcc_ddrss_pcie_sf_qtb_clk = {
	1340	+ .halt_reg = 0x1007c,
	1341	+ .halt_check = BRANCH_HALT_SKIP,
	1342	+ .hwcg_reg = 0x1007c,
	1343	+ .hwcg_bit = 1,
	1344	+ .clkr = {
	1345	+ .enable_reg = 0x52000,
	1346	+ .enable_mask = BIT(19),
	1347	+ .hw.init = &(const struct clk_init_data) {
	1348	+ .name = "gcc_ddrss_pcie_sf_qtb_clk",
	1349	+ .ops = &clk_branch2_ops,
	1350	+ },
	1351	+ },
	1352	+};
	1353	+
	1354	+static struct clk_branch gcc_disp_hf_axi_clk = {
	1355	+ .halt_reg = 0x27008,
	1356	+ .halt_check = BRANCH_HALT_SKIP,
	1357	+ .clkr = {
	1358	+ .enable_reg = 0x27008,
	1359	+ .enable_mask = BIT(0),
	1360	+ .hw.init = &(const struct clk_init_data) {
	1361	+ .name = "gcc_disp_hf_axi_clk",
	1362	+ .ops = &clk_branch2_ops,
	1363	+ },
	1364	+ },
	1365	+};
	1366	+
	1367	+static struct clk_branch gcc_gp1_clk = {
	1368	+ .halt_reg = 0x64000,
	1369	+ .halt_check = BRANCH_HALT,
	1370	+ .clkr = {
	1371	+ .enable_reg = 0x64000,
	1372	+ .enable_mask = BIT(0),
	1373	+ .hw.init = &(const struct clk_init_data) {
	1374	+ .name = "gcc_gp1_clk",
	1375	+ .parent_hws = (const struct clk_hw*[]) {
	1376	+ &gcc_gp1_clk_src.clkr.hw,
	1377	+ },
	1378	+ .num_parents = 1,
	1379	+ .flags = CLK_SET_RATE_PARENT,
	1380	+ .ops = &clk_branch2_ops,
	1381	+ },
	1382	+ },
	1383	+};
	1384	+
	1385	+static struct clk_branch gcc_gp2_clk = {
	1386	+ .halt_reg = 0x65000,
	1387	+ .halt_check = BRANCH_HALT,
	1388	+ .clkr = {
	1389	+ .enable_reg = 0x65000,
	1390	+ .enable_mask = BIT(0),
	1391	+ .hw.init = &(const struct clk_init_data) {
	1392	+ .name = "gcc_gp2_clk",
	1393	+ .parent_hws = (const struct clk_hw*[]) {
	1394	+ &gcc_gp2_clk_src.clkr.hw,
	1395	+ },
	1396	+ .num_parents = 1,
	1397	+ .flags = CLK_SET_RATE_PARENT,
	1398	+ .ops = &clk_branch2_ops,
	1399	+ },
	1400	+ },
	1401	+};
	1402	+
	1403	+static struct clk_branch gcc_gp3_clk = {
	1404	+ .halt_reg = 0x66000,
	1405	+ .halt_check = BRANCH_HALT,
	1406	+ .clkr = {
	1407	+ .enable_reg = 0x66000,
	1408	+ .enable_mask = BIT(0),
	1409	+ .hw.init = &(const struct clk_init_data) {
	1410	+ .name = "gcc_gp3_clk",
	1411	+ .parent_hws = (const struct clk_hw*[]) {
	1412	+ &gcc_gp3_clk_src.clkr.hw,
	1413	+ },
	1414	+ .num_parents = 1,
	1415	+ .flags = CLK_SET_RATE_PARENT,
	1416	+ .ops = &clk_branch2_ops,
	1417	+ },
	1418	+ },
	1419	+};
	1420	+
	1421	+static struct clk_branch gcc_gpu_gemnoc_gfx_clk = {
	1422	+ .halt_reg = 0x71010,
	1423	+ .halt_check = BRANCH_HALT_VOTED,
	1424	+ .hwcg_reg = 0x71010,
	1425	+ .hwcg_bit = 1,
	1426	+ .clkr = {
	1427	+ .enable_reg = 0x71010,
	1428	+ .enable_mask = BIT(0),
	1429	+ .hw.init = &(const struct clk_init_data) {
	1430	+ .name = "gcc_gpu_gemnoc_gfx_clk",
	1431	+ .ops = &clk_branch2_ops,
	1432	+ },
	1433	+ },
	1434	+};
	1435	+
	1436	+static struct clk_branch gcc_gpu_gpll0_cph_clk_src = {
	1437	+ .halt_reg = 0x71150,
	1438	+ .halt_check = BRANCH_HALT_ENABLE_VOTED,
	1439	+ .clkr = {
	1440	+ .enable_reg = 0x71150,
	1441	+ .enable_mask = BIT(0),
	1442	+ .hw.init = &(const struct clk_init_data) {
	1443	+ .name = "gcc_gpu_gpll0_cph_clk_src",
	1444	+ .parent_hws = (const struct clk_hw*[]) {
	1445	+ &gcc_gpll0.clkr.hw,
	1446	+ },
	1447	+ .num_parents = 1,
	1448	+ .flags = CLK_SET_RATE_PARENT,
	1449	+ .ops = &clk_branch2_ops,
	1450	+ },
	1451	+ },
	1452	+};
	1453	+
	1454	+static struct clk_branch gcc_gpu_gpll0_div_cph_clk_src = {
	1455	+ .halt_reg = 0x71154,
	1456	+ .halt_check = BRANCH_HALT_ENABLE_VOTED,
	1457	+ .clkr = {
	1458	+ .enable_reg = 0x71154,
	1459	+ .enable_mask = BIT(0),
	1460	+ .hw.init = &(const struct clk_init_data) {
	1461	+ .name = "gcc_gpu_gpll0_div_cph_clk_src",
	1462	+ .parent_hws = (const struct clk_hw*[]) {
	1463	+ &gcc_gpll0_out_even.clkr.hw,
	1464	+ },
	1465	+ .num_parents = 1,
	1466	+ .flags = CLK_SET_RATE_PARENT,
	1467	+ .ops = &clk_branch2_ops,
	1468	+ },
	1469	+ },
	1470	+};
	1471	+
	1472	+static struct clk_branch gcc_gpu_smmu_vote_clk = {
	1473	+ .halt_reg = 0x7d000,
	1474	+ .halt_check = BRANCH_HALT_VOTED,
	1475	+ .clkr = {
	1476	+ .enable_reg = 0x7d000,
	1477	+ .enable_mask = BIT(0),
	1478	+ .hw.init = &(const struct clk_init_data) {
	1479	+ .name = "gcc_gpu_smmu_vote_clk",
	1480	+ .ops = &clk_branch2_ops,
	1481	+ },
	1482	+ },
	1483	+};
	1484	+
	1485	+static struct clk_branch gcc_mmu_tcu_vote_clk = {
	1486	+ .halt_reg = 0x7d02c,
	1487	+ .halt_check = BRANCH_HALT_VOTED,
	1488	+ .clkr = {
	1489	+ .enable_reg = 0x7d02c,
	1490	+ .enable_mask = BIT(0),
	1491	+ .hw.init = &(const struct clk_init_data) {
	1492	+ .name = "gcc_mmu_tcu_vote_clk",
	1493	+ .ops = &clk_branch2_ops,
	1494	+ },
	1495	+ },
	1496	+};
	1497	+
	1498	+static struct clk_branch gcc_pcie_0_aux_clk = {
	1499	+ .halt_reg = 0x6b044,
	1500	+ .halt_check = BRANCH_HALT_VOTED,
	1501	+ .clkr = {
	1502	+ .enable_reg = 0x52008,
	1503	+ .enable_mask = BIT(3),
	1504	+ .hw.init = &(const struct clk_init_data) {
	1505	+ .name = "gcc_pcie_0_aux_clk",
	1506	+ .parent_hws = (const struct clk_hw*[]) {
	1507	+ &gcc_pcie_0_aux_clk_src.clkr.hw,
	1508	+ },
	1509	+ .num_parents = 1,
	1510	+ .flags = CLK_SET_RATE_PARENT,
	1511	+ .ops = &clk_branch2_ops,
	1512	+ },
	1513	+ },
	1514	+};
	1515	+
	1516	+static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
	1517	+ .halt_reg = 0x6b040,
	1518	+ .halt_check = BRANCH_HALT_VOTED,
	1519	+ .hwcg_reg = 0x6b040,
	1520	+ .hwcg_bit = 1,
	1521	+ .clkr = {
	1522	+ .enable_reg = 0x52008,
	1523	+ .enable_mask = BIT(2),
	1524	+ .hw.init = &(const struct clk_init_data) {
	1525	+ .name = "gcc_pcie_0_cfg_ahb_clk",
	1526	+ .ops = &clk_branch2_ops,
	1527	+ },
	1528	+ },
	1529	+};
	1530	+
	1531	+static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
	1532	+ .halt_reg = 0x6b030,
	1533	+ .halt_check = BRANCH_HALT_SKIP,
	1534	+ .hwcg_reg = 0x6b030,
	1535	+ .hwcg_bit = 1,
	1536	+ .clkr = {
	1537	+ .enable_reg = 0x52008,
	1538	+ .enable_mask = BIT(1),
	1539	+ .hw.init = &(const struct clk_init_data) {
	1540	+ .name = "gcc_pcie_0_mstr_axi_clk",
	1541	+ .ops = &clk_branch2_ops,
	1542	+ },
	1543	+ },
	1544	+};
	1545	+
	1546	+static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
	1547	+ .halt_reg = 0x6b064,
	1548	+ .halt_check = BRANCH_HALT_VOTED,
	1549	+ .clkr = {
	1550	+ .enable_reg = 0x52000,
	1551	+ .enable_mask = BIT(22),
	1552	+ .hw.init = &(const struct clk_init_data) {
	1553	+ .name = "gcc_pcie_0_phy_rchng_clk",
	1554	+ .parent_hws = (const struct clk_hw*[]) {
	1555	+ &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
	1556	+ },
	1557	+ .num_parents = 1,
	1558	+ .flags = CLK_SET_RATE_PARENT,
	1559	+ .ops = &clk_branch2_ops,
	1560	+ },
	1561	+ },
	1562	+};
	1563	+
	1564	+static struct clk_branch gcc_pcie_0_pipe_clk = {
	1565	+ .halt_reg = 0x6b054,
	1566	+ .halt_check = BRANCH_HALT_SKIP,
	1567	+ .clkr = {
	1568	+ .enable_reg = 0x52008,
	1569	+ .enable_mask = BIT(4),
	1570	+ .hw.init = &(const struct clk_init_data) {
	1571	+ .name = "gcc_pcie_0_pipe_clk",
	1572	+ .parent_hws = (const struct clk_hw*[]) {
	1573	+ &gcc_pcie_0_pipe_clk_src.clkr.hw,
	1574	+ },
	1575	+ .num_parents = 1,
	1576	+ .flags = CLK_SET_RATE_PARENT,
	1577	+ .ops = &clk_branch2_ops,
	1578	+ },
	1579	+ },
	1580	+};
	1581	+
	1582	+static struct clk_branch gcc_pcie_0_pipe_div2_clk = {
	1583	+ .halt_reg = 0x6b0a8,
	1584	+ .halt_check = BRANCH_HALT_SKIP,
	1585	+ .clkr = {
	1586	+ .enable_reg = 0x52018,
	1587	+ .enable_mask = BIT(13),
	1588	+ .hw.init = &(const struct clk_init_data) {
	1589	+ .name = "gcc_pcie_0_pipe_div2_clk",
	1590	+ .parent_hws = (const struct clk_hw*[]) {
	1591	+ &gcc_pcie_0_pipe_div2_clk_src.clkr.hw,
	1592	+ },
	1593	+ .num_parents = 1,
	1594	+ .flags = CLK_SET_RATE_PARENT,
	1595	+ .ops = &clk_branch2_ops,
	1596	+ },
	1597	+ },
	1598	+};
	1599	+
	1600	+static struct clk_branch gcc_pcie_0_slv_axi_clk = {
	1601	+ .halt_reg = 0x6b020,
	1602	+ .halt_check = BRANCH_HALT_VOTED,
	1603	+ .hwcg_reg = 0x6b020,
	1604	+ .hwcg_bit = 1,
	1605	+ .clkr = {
	1606	+ .enable_reg = 0x52008,
	1607	+ .enable_mask = BIT(0),
	1608	+ .hw.init = &(const struct clk_init_data) {
	1609	+ .name = "gcc_pcie_0_slv_axi_clk",
	1610	+ .ops = &clk_branch2_ops,
	1611	+ },
	1612	+ },
	1613	+};
	1614	+
	1615	+static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
	1616	+ .halt_reg = 0x6b01c,
	1617	+ .halt_check = BRANCH_HALT_VOTED,
	1618	+ .clkr = {
	1619	+ .enable_reg = 0x52008,
	1620	+ .enable_mask = BIT(5),
	1621	+ .hw.init = &(const struct clk_init_data) {
	1622	+ .name = "gcc_pcie_0_slv_q2a_axi_clk",
	1623	+ .ops = &clk_branch2_ops,
	1624	+ },
	1625	+ },
	1626	+};
	1627	+
	1628	+static struct clk_branch gcc_pcie_1_aux_clk = {
	1629	+ .halt_reg = 0xac040,
	1630	+ .halt_check = BRANCH_HALT_VOTED,
	1631	+ .clkr = {
	1632	+ .enable_reg = 0x52000,
	1633	+ .enable_mask = BIT(29),
	1634	+ .hw.init = &(const struct clk_init_data) {
	1635	+ .name = "gcc_pcie_1_aux_clk",
	1636	+ .parent_hws = (const struct clk_hw*[]) {
	1637	+ &gcc_pcie_1_aux_clk_src.clkr.hw,
	1638	+ },
	1639	+ .num_parents = 1,
	1640	+ .flags = CLK_SET_RATE_PARENT,
	1641	+ .ops = &clk_branch2_ops,
	1642	+ },
	1643	+ },
	1644	+};
	1645	+
	1646	+static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
	1647	+ .halt_reg = 0xac03c,
	1648	+ .halt_check = BRANCH_HALT_VOTED,
	1649	+ .hwcg_reg = 0xac03c,
	1650	+ .hwcg_bit = 1,
	1651	+ .clkr = {
	1652	+ .enable_reg = 0x52000,
	1653	+ .enable_mask = BIT(28),
	1654	+ .hw.init = &(const struct clk_init_data) {
	1655	+ .name = "gcc_pcie_1_cfg_ahb_clk",
	1656	+ .ops = &clk_branch2_ops,
	1657	+ },
	1658	+ },
	1659	+};
	1660	+
	1661	+static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
	1662	+ .halt_reg = 0xac02c,
	1663	+ .halt_check = BRANCH_HALT_SKIP,
	1664	+ .hwcg_reg = 0xac02c,
	1665	+ .hwcg_bit = 1,
	1666	+ .clkr = {
	1667	+ .enable_reg = 0x52000,
	1668	+ .enable_mask = BIT(27),
	1669	+ .hw.init = &(const struct clk_init_data) {
	1670	+ .name = "gcc_pcie_1_mstr_axi_clk",
	1671	+ .ops = &clk_branch2_ops,
	1672	+ },
	1673	+ },
	1674	+};
	1675	+
	1676	+static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
	1677	+ .halt_reg = 0xac060,
	1678	+ .halt_check = BRANCH_HALT_VOTED,
	1679	+ .clkr = {
	1680	+ .enable_reg = 0x52000,
	1681	+ .enable_mask = BIT(24),
	1682	+ .hw.init = &(const struct clk_init_data) {
	1683	+ .name = "gcc_pcie_1_phy_rchng_clk",
	1684	+ .parent_hws = (const struct clk_hw*[]) {
	1685	+ &gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
	1686	+ },
	1687	+ .num_parents = 1,
	1688	+ .flags = CLK_SET_RATE_PARENT,
	1689	+ .ops = &clk_branch2_ops,
	1690	+ },
	1691	+ },
	1692	+};
	1693	+
	1694	+static struct clk_branch gcc_pcie_1_pipe_clk = {
	1695	+ .halt_reg = 0xac050,
	1696	+ .halt_check = BRANCH_HALT_SKIP,
	1697	+ .clkr = {
	1698	+ .enable_reg = 0x52000,
	1699	+ .enable_mask = BIT(23),
	1700	+ .hw.init = &(const struct clk_init_data) {
	1701	+ .name = "gcc_pcie_1_pipe_clk",
	1702	+ .parent_hws = (const struct clk_hw*[]) {
	1703	+ &gcc_pcie_1_pipe_clk_src.clkr.hw,
	1704	+ },
	1705	+ .num_parents = 1,
	1706	+ .flags = CLK_SET_RATE_PARENT,
	1707	+ .ops = &clk_branch2_ops,
	1708	+ },
	1709	+ },
	1710	+};
	1711	+
	1712	+static struct clk_branch gcc_pcie_1_pipe_div2_clk = {
	1713	+ .halt_reg = 0xac0a4,
	1714	+ .halt_check = BRANCH_HALT_SKIP,
	1715	+ .clkr = {
	1716	+ .enable_reg = 0x52018,
	1717	+ .enable_mask = BIT(15),
	1718	+ .hw.init = &(const struct clk_init_data) {
	1719	+ .name = "gcc_pcie_1_pipe_div2_clk",
	1720	+ .parent_hws = (const struct clk_hw*[]) {
	1721	+ &gcc_pcie_1_pipe_div2_clk_src.clkr.hw,
	1722	+ },
	1723	+ .num_parents = 1,
	1724	+ .flags = CLK_SET_RATE_PARENT,
	1725	+ .ops = &clk_branch2_ops,
	1726	+ },
	1727	+ },
	1728	+};
	1729	+
	1730	+static struct clk_branch gcc_pcie_1_slv_axi_clk = {
	1731	+ .halt_reg = 0xac01c,
	1732	+ .halt_check = BRANCH_HALT_VOTED,
	1733	+ .hwcg_reg = 0xac01c,
	1734	+ .hwcg_bit = 1,
	1735	+ .clkr = {
	1736	+ .enable_reg = 0x52000,
	1737	+ .enable_mask = BIT(26),
	1738	+ .hw.init = &(const struct clk_init_data) {
	1739	+ .name = "gcc_pcie_1_slv_axi_clk",
	1740	+ .ops = &clk_branch2_ops,
	1741	+ },
	1742	+ },
	1743	+};
	1744	+
	1745	+static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
	1746	+ .halt_reg = 0xac018,
	1747	+ .halt_check = BRANCH_HALT_VOTED,
	1748	+ .clkr = {
	1749	+ .enable_reg = 0x52000,
	1750	+ .enable_mask = BIT(25),
	1751	+ .hw.init = &(const struct clk_init_data) {
	1752	+ .name = "gcc_pcie_1_slv_q2a_axi_clk",
	1753	+ .ops = &clk_branch2_ops,
	1754	+ },
	1755	+ },
	1756	+};
	1757	+
	1758	+static struct clk_branch gcc_pdm2_clk = {
	1759	+ .halt_reg = 0x3300c,
	1760	+ .halt_check = BRANCH_HALT,
	1761	+ .clkr = {
	1762	+ .enable_reg = 0x3300c,
	1763	+ .enable_mask = BIT(0),
	1764	+ .hw.init = &(const struct clk_init_data) {
	1765	+ .name = "gcc_pdm2_clk",
	1766	+ .parent_hws = (const struct clk_hw*[]) {
	1767	+ &gcc_pdm2_clk_src.clkr.hw,
	1768	+ },
	1769	+ .num_parents = 1,
	1770	+ .flags = CLK_SET_RATE_PARENT,
	1771	+ .ops = &clk_branch2_ops,
	1772	+ },
	1773	+ },
	1774	+};
	1775	+
	1776	+static struct clk_branch gcc_pdm_ahb_clk = {
	1777	+ .halt_reg = 0x33004,
	1778	+ .halt_check = BRANCH_HALT_VOTED,
	1779	+ .hwcg_reg = 0x33004,
	1780	+ .hwcg_bit = 1,
	1781	+ .clkr = {
	1782	+ .enable_reg = 0x33004,
	1783	+ .enable_mask = BIT(0),
	1784	+ .hw.init = &(const struct clk_init_data) {
	1785	+ .name = "gcc_pdm_ahb_clk",
	1786	+ .ops = &clk_branch2_ops,
	1787	+ },
	1788	+ },
	1789	+};
	1790	+
	1791	+static struct clk_branch gcc_pdm_xo4_clk = {
	1792	+ .halt_reg = 0x33008,
	1793	+ .halt_check = BRANCH_HALT,
	1794	+ .clkr = {
	1795	+ .enable_reg = 0x33008,
	1796	+ .enable_mask = BIT(0),
	1797	+ .hw.init = &(const struct clk_init_data) {
	1798	+ .name = "gcc_pdm_xo4_clk",
	1799	+ .ops = &clk_branch2_ops,
	1800	+ },
	1801	+ },
	1802	+};
	1803	+
	1804	+static struct clk_branch gcc_qmip_camera_cmd_ahb_clk = {
	1805	+ .halt_reg = 0x26010,
	1806	+ .halt_check = BRANCH_HALT_VOTED,
	1807	+ .hwcg_reg = 0x26010,
	1808	+ .hwcg_bit = 1,
	1809	+ .clkr = {
	1810	+ .enable_reg = 0x26010,
	1811	+ .enable_mask = BIT(0),
	1812	+ .hw.init = &(const struct clk_init_data) {
	1813	+ .name = "gcc_qmip_camera_cmd_ahb_clk",
	1814	+ .ops = &clk_branch2_ops,
	1815	+ },
	1816	+ },
	1817	+};
	1818	+
	1819	+static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
	1820	+ .halt_reg = 0x26008,
	1821	+ .halt_check = BRANCH_HALT_VOTED,
	1822	+ .hwcg_reg = 0x26008,
	1823	+ .hwcg_bit = 1,
	1824	+ .clkr = {
	1825	+ .enable_reg = 0x26008,
	1826	+ .enable_mask = BIT(0),
	1827	+ .hw.init = &(const struct clk_init_data) {
	1828	+ .name = "gcc_qmip_camera_nrt_ahb_clk",
	1829	+ .ops = &clk_branch2_ops,
	1830	+ },
	1831	+ },
	1832	+};
	1833	+
	1834	+static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
	1835	+ .halt_reg = 0x2600c,
	1836	+ .halt_check = BRANCH_HALT_VOTED,
	1837	+ .hwcg_reg = 0x2600c,
	1838	+ .hwcg_bit = 1,
	1839	+ .clkr = {
	1840	+ .enable_reg = 0x2600c,
	1841	+ .enable_mask = BIT(0),
	1842	+ .hw.init = &(const struct clk_init_data) {
	1843	+ .name = "gcc_qmip_camera_rt_ahb_clk",
	1844	+ .ops = &clk_branch2_ops,
	1845	+ },
	1846	+ },
	1847	+};
	1848	+
	1849	+static struct clk_branch gcc_qmip_gpu_ahb_clk = {
	1850	+ .halt_reg = 0x71008,
	1851	+ .halt_check = BRANCH_HALT_VOTED,
	1852	+ .hwcg_reg = 0x71008,
	1853	+ .hwcg_bit = 1,
	1854	+ .clkr = {
	1855	+ .enable_reg = 0x71008,
	1856	+ .enable_mask = BIT(0),
	1857	+ .hw.init = &(const struct clk_init_data) {
	1858	+ .name = "gcc_qmip_gpu_ahb_clk",
	1859	+ .ops = &clk_branch2_ops,
	1860	+ },
	1861	+ },
	1862	+};
	1863	+
	1864	+static struct clk_branch gcc_qmip_pcie_ahb_clk = {
	1865	+ .halt_reg = 0x6b018,
	1866	+ .halt_check = BRANCH_HALT_VOTED,
	1867	+ .hwcg_reg = 0x6b018,
	1868	+ .hwcg_bit = 1,
	1869	+ .clkr = {
	1870	+ .enable_reg = 0x52000,
	1871	+ .enable_mask = BIT(11),
	1872	+ .hw.init = &(const struct clk_init_data) {
	1873	+ .name = "gcc_qmip_pcie_ahb_clk",
	1874	+ .ops = &clk_branch2_ops,
	1875	+ },
	1876	+ },
	1877	+};
	1878	+
	1879	+static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {
	1880	+ .halt_reg = 0x32010,
	1881	+ .halt_check = BRANCH_HALT_VOTED,
	1882	+ .hwcg_reg = 0x32010,
	1883	+ .hwcg_bit = 1,
	1884	+ .clkr = {
	1885	+ .enable_reg = 0x32010,
	1886	+ .enable_mask = BIT(0),
	1887	+ .hw.init = &(const struct clk_init_data) {
	1888	+ .name = "gcc_qmip_video_v_cpu_ahb_clk",
	1889	+ .ops = &clk_branch2_ops,
	1890	+ },
	1891	+ },
	1892	+};
	1893	+
	1894	+static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
	1895	+ .halt_reg = 0x3200c,
	1896	+ .halt_check = BRANCH_HALT_VOTED,
	1897	+ .hwcg_reg = 0x3200c,
	1898	+ .hwcg_bit = 1,
	1899	+ .clkr = {
	1900	+ .enable_reg = 0x3200c,
	1901	+ .enable_mask = BIT(0),
	1902	+ .hw.init = &(const struct clk_init_data) {
	1903	+ .name = "gcc_qmip_video_vcodec_ahb_clk",
	1904	+ .ops = &clk_branch2_ops,
	1905	+ },
	1906	+ },
	1907	+};
	1908	+
	1909	+static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
	1910	+ .halt_reg = 0x2301c,
	1911	+ .halt_check = BRANCH_HALT_VOTED,
	1912	+ .clkr = {
	1913	+ .enable_reg = 0x52008,
	1914	+ .enable_mask = BIT(18),
	1915	+ .hw.init = &(const struct clk_init_data) {
	1916	+ .name = "gcc_qupv3_wrap1_core_2x_clk",
	1917	+ .ops = &clk_branch2_ops,
	1918	+ },
	1919	+ },
	1920	+};
	1921	+
	1922	+static struct clk_branch gcc_qupv3_wrap1_core_clk = {
	1923	+ .halt_reg = 0x23008,
	1924	+ .halt_check = BRANCH_HALT_VOTED,
	1925	+ .clkr = {
	1926	+ .enable_reg = 0x52008,
	1927	+ .enable_mask = BIT(19),
	1928	+ .hw.init = &(const struct clk_init_data) {
	1929	+ .name = "gcc_qupv3_wrap1_core_clk",
	1930	+ .ops = &clk_branch2_ops,
	1931	+ },
	1932	+ },
	1933	+};
	1934	+
	1935	+static struct clk_branch gcc_qupv3_wrap1_qspi_ref_clk = {
	1936	+ .halt_reg = 0x188bc,
	1937	+ .halt_check = BRANCH_HALT_VOTED,
	1938	+ .clkr = {
	1939	+ .enable_reg = 0x52010,
	1940	+ .enable_mask = BIT(29),
	1941	+ .hw.init = &(const struct clk_init_data) {
	1942	+ .name = "gcc_qupv3_wrap1_qspi_ref_clk",
	1943	+ .parent_hws = (const struct clk_hw*[]) {
	1944	+ &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw,
	1945	+ },
	1946	+ .num_parents = 1,
	1947	+ .flags = CLK_SET_RATE_PARENT,
	1948	+ .ops = &clk_branch2_ops,
	1949	+ },
	1950	+ },
	1951	+};
	1952	+
	1953	+static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
	1954	+ .halt_reg = 0x18004,
	1955	+ .halt_check = BRANCH_HALT_VOTED,
	1956	+ .clkr = {
	1957	+ .enable_reg = 0x52008,
	1958	+ .enable_mask = BIT(22),
	1959	+ .hw.init = &(const struct clk_init_data) {
	1960	+ .name = "gcc_qupv3_wrap1_s0_clk",
	1961	+ .parent_hws = (const struct clk_hw*[]) {
	1962	+ &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
	1963	+ },
	1964	+ .num_parents = 1,
	1965	+ .flags = CLK_SET_RATE_PARENT,
	1966	+ .ops = &clk_branch2_ops,
	1967	+ },
	1968	+ },
	1969	+};
	1970	+
	1971	+static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
	1972	+ .halt_reg = 0x18140,
	1973	+ .halt_check = BRANCH_HALT_VOTED,
	1974	+ .clkr = {
	1975	+ .enable_reg = 0x52008,
	1976	+ .enable_mask = BIT(23),
	1977	+ .hw.init = &(const struct clk_init_data) {
	1978	+ .name = "gcc_qupv3_wrap1_s1_clk",
	1979	+ .parent_hws = (const struct clk_hw*[]) {
	1980	+ &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
	1981	+ },
	1982	+ .num_parents = 1,
	1983	+ .flags = CLK_SET_RATE_PARENT,
	1984	+ .ops = &clk_branch2_ops,
	1985	+ },
	1986	+ },
	1987	+};
	1988	+
	1989	+static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
	1990	+ .halt_reg = 0x1827c,
	1991	+ .halt_check = BRANCH_HALT_VOTED,
	1992	+ .clkr = {
	1993	+ .enable_reg = 0x52008,
	1994	+ .enable_mask = BIT(24),
	1995	+ .hw.init = &(const struct clk_init_data) {
	1996	+ .name = "gcc_qupv3_wrap1_s2_clk",
	1997	+ .parent_hws = (const struct clk_hw*[]) {
	1998	+ &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
	1999	+ },
	2000	+ .num_parents = 1,
	2001	+ .flags = CLK_SET_RATE_PARENT,
	2002	+ .ops = &clk_branch2_ops,
	2003	+ },
	2004	+ },
	2005	+};
	2006	+
	2007	+static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
	2008	+ .halt_reg = 0x18290,
	2009	+ .halt_check = BRANCH_HALT_VOTED,
	2010	+ .clkr = {
	2011	+ .enable_reg = 0x52008,
	2012	+ .enable_mask = BIT(25),
	2013	+ .hw.init = &(const struct clk_init_data) {
	2014	+ .name = "gcc_qupv3_wrap1_s3_clk",
	2015	+ .parent_hws = (const struct clk_hw*[]) {
	2016	+ &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
	2017	+ },
	2018	+ .num_parents = 1,
	2019	+ .flags = CLK_SET_RATE_PARENT,
	2020	+ .ops = &clk_branch2_ops,
	2021	+ },
	2022	+ },
	2023	+};
	2024	+
	2025	+static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
	2026	+ .halt_reg = 0x183cc,
	2027	+ .halt_check = BRANCH_HALT_VOTED,
	2028	+ .clkr = {
	2029	+ .enable_reg = 0x52008,
	2030	+ .enable_mask = BIT(26),
	2031	+ .hw.init = &(const struct clk_init_data) {
	2032	+ .name = "gcc_qupv3_wrap1_s4_clk",
	2033	+ .parent_hws = (const struct clk_hw*[]) {
	2034	+ &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
	2035	+ },
	2036	+ .num_parents = 1,
	2037	+ .flags = CLK_SET_RATE_PARENT,
	2038	+ .ops = &clk_branch2_ops,
	2039	+ },
	2040	+ },
	2041	+};
	2042	+
	2043	+static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
	2044	+ .halt_reg = 0x18508,
	2045	+ .halt_check = BRANCH_HALT_VOTED,
	2046	+ .clkr = {
	2047	+ .enable_reg = 0x52008,
	2048	+ .enable_mask = BIT(27),
	2049	+ .hw.init = &(const struct clk_init_data) {
	2050	+ .name = "gcc_qupv3_wrap1_s5_clk",
	2051	+ .parent_hws = (const struct clk_hw*[]) {
	2052	+ &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
	2053	+ },
	2054	+ .num_parents = 1,
	2055	+ .flags = CLK_SET_RATE_PARENT,
	2056	+ .ops = &clk_branch2_ops,
	2057	+ },
	2058	+ },
	2059	+};
	2060	+
	2061	+static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
	2062	+ .halt_reg = 0x18644,
	2063	+ .halt_check = BRANCH_HALT_VOTED,
	2064	+ .clkr = {
	2065	+ .enable_reg = 0x52008,
	2066	+ .enable_mask = BIT(28),
	2067	+ .hw.init = &(const struct clk_init_data) {
	2068	+ .name = "gcc_qupv3_wrap1_s6_clk",
	2069	+ .parent_hws = (const struct clk_hw*[]) {
	2070	+ &gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
	2071	+ },
	2072	+ .num_parents = 1,
	2073	+ .flags = CLK_SET_RATE_PARENT,
	2074	+ .ops = &clk_branch2_ops,
	2075	+ },
	2076	+ },
	2077	+};
	2078	+
	2079	+static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
	2080	+ .halt_reg = 0x18780,
	2081	+ .halt_check = BRANCH_HALT_VOTED,
	2082	+ .clkr = {
	2083	+ .enable_reg = 0x52010,
	2084	+ .enable_mask = BIT(16),
	2085	+ .hw.init = &(const struct clk_init_data) {
	2086	+ .name = "gcc_qupv3_wrap1_s7_clk",
	2087	+ .parent_hws = (const struct clk_hw*[]) {
	2088	+ &gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
	2089	+ },
	2090	+ .num_parents = 1,
	2091	+ .flags = CLK_SET_RATE_PARENT,
	2092	+ .ops = &clk_branch2_ops,
	2093	+ },
	2094	+ },
	2095	+};
	2096	+
	2097	+static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
	2098	+ .halt_reg = 0x23174,
	2099	+ .halt_check = BRANCH_HALT_VOTED,
	2100	+ .clkr = {
	2101	+ .enable_reg = 0x52010,
	2102	+ .enable_mask = BIT(3),
	2103	+ .hw.init = &(const struct clk_init_data) {
	2104	+ .name = "gcc_qupv3_wrap2_core_2x_clk",
	2105	+ .ops = &clk_branch2_ops,
	2106	+ },
	2107	+ },
	2108	+};
	2109	+
	2110	+static struct clk_branch gcc_qupv3_wrap2_core_clk = {
	2111	+ .halt_reg = 0x23160,
	2112	+ .halt_check = BRANCH_HALT_VOTED,
	2113	+ .clkr = {
	2114	+ .enable_reg = 0x52010,
	2115	+ .enable_mask = BIT(0),
	2116	+ .hw.init = &(const struct clk_init_data) {
	2117	+ .name = "gcc_qupv3_wrap2_core_clk",
	2118	+ .ops = &clk_branch2_ops,
	2119	+ },
	2120	+ },
	2121	+};
	2122	+
	2123	+static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
	2124	+ .halt_reg = 0x1e004,
	2125	+ .halt_check = BRANCH_HALT_VOTED,
	2126	+ .clkr = {
	2127	+ .enable_reg = 0x52010,
	2128	+ .enable_mask = BIT(4),
	2129	+ .hw.init = &(const struct clk_init_data) {
	2130	+ .name = "gcc_qupv3_wrap2_s0_clk",
	2131	+ .parent_hws = (const struct clk_hw*[]) {
	2132	+ &gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
	2133	+ },
	2134	+ .num_parents = 1,
	2135	+ .flags = CLK_SET_RATE_PARENT,
	2136	+ .ops = &clk_branch2_ops,
	2137	+ },
	2138	+ },
	2139	+};
	2140	+
	2141	+static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
	2142	+ .halt_reg = 0x1e140,
	2143	+ .halt_check = BRANCH_HALT_VOTED,
	2144	+ .clkr = {
	2145	+ .enable_reg = 0x52010,
	2146	+ .enable_mask = BIT(5),
	2147	+ .hw.init = &(const struct clk_init_data) {
	2148	+ .name = "gcc_qupv3_wrap2_s1_clk",
	2149	+ .parent_hws = (const struct clk_hw*[]) {
	2150	+ &gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
	2151	+ },
	2152	+ .num_parents = 1,
	2153	+ .flags = CLK_SET_RATE_PARENT,
	2154	+ .ops = &clk_branch2_ops,
	2155	+ },
	2156	+ },
	2157	+};
	2158	+
	2159	+static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
	2160	+ .halt_reg = 0x1e27c,
	2161	+ .halt_check = BRANCH_HALT_VOTED,
	2162	+ .clkr = {
	2163	+ .enable_reg = 0x52010,
	2164	+ .enable_mask = BIT(6),
	2165	+ .hw.init = &(const struct clk_init_data) {
	2166	+ .name = "gcc_qupv3_wrap2_s2_clk",
	2167	+ .parent_hws = (const struct clk_hw*[]) {
	2168	+ &gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
	2169	+ },
	2170	+ .num_parents = 1,
	2171	+ .flags = CLK_SET_RATE_PARENT,
	2172	+ .ops = &clk_branch2_ops,
	2173	+ },
	2174	+ },
	2175	+};
	2176	+
	2177	+static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
	2178	+ .halt_reg = 0x1e3b8,
	2179	+ .halt_check = BRANCH_HALT_VOTED,
	2180	+ .clkr = {
	2181	+ .enable_reg = 0x52010,
	2182	+ .enable_mask = BIT(7),
	2183	+ .hw.init = &(const struct clk_init_data) {
	2184	+ .name = "gcc_qupv3_wrap2_s3_clk",
	2185	+ .parent_hws = (const struct clk_hw*[]) {
	2186	+ &gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
	2187	+ },
	2188	+ .num_parents = 1,
	2189	+ .flags = CLK_SET_RATE_PARENT,
	2190	+ .ops = &clk_branch2_ops,
	2191	+ },
	2192	+ },
	2193	+};
	2194	+
	2195	+static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
	2196	+ .halt_reg = 0x1e4f4,
	2197	+ .halt_check = BRANCH_HALT_VOTED,
	2198	+ .clkr = {
	2199	+ .enable_reg = 0x52010,
	2200	+ .enable_mask = BIT(8),
	2201	+ .hw.init = &(const struct clk_init_data) {
	2202	+ .name = "gcc_qupv3_wrap2_s4_clk",
	2203	+ .parent_hws = (const struct clk_hw*[]) {
	2204	+ &gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
	2205	+ },
	2206	+ .num_parents = 1,
	2207	+ .flags = CLK_SET_RATE_PARENT,
	2208	+ .ops = &clk_branch2_ops,
	2209	+ },
	2210	+ },
	2211	+};
	2212	+
	2213	+static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
	2214	+ .halt_reg = 0x1e630,
	2215	+ .halt_check = BRANCH_HALT_VOTED,
	2216	+ .clkr = {
	2217	+ .enable_reg = 0x52010,
	2218	+ .enable_mask = BIT(9),
	2219	+ .hw.init = &(const struct clk_init_data) {
	2220	+ .name = "gcc_qupv3_wrap2_s5_clk",
	2221	+ .parent_hws = (const struct clk_hw*[]) {
	2222	+ &gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
	2223	+ },
	2224	+ .num_parents = 1,
	2225	+ .flags = CLK_SET_RATE_PARENT,
	2226	+ .ops = &clk_branch2_ops,
	2227	+ },
	2228	+ },
	2229	+};
	2230	+
	2231	+static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
	2232	+ .halt_reg = 0x1e76c,
	2233	+ .halt_check = BRANCH_HALT_VOTED,
	2234	+ .clkr = {
	2235	+ .enable_reg = 0x52010,
	2236	+ .enable_mask = BIT(10),
	2237	+ .hw.init = &(const struct clk_init_data) {
	2238	+ .name = "gcc_qupv3_wrap2_s6_clk",
	2239	+ .parent_hws = (const struct clk_hw*[]) {
	2240	+ &gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
	2241	+ },
	2242	+ .num_parents = 1,
	2243	+ .flags = CLK_SET_RATE_PARENT,
	2244	+ .ops = &clk_branch2_ops,
	2245	+ },
	2246	+ },
	2247	+};
	2248	+
	2249	+static struct clk_branch gcc_qupv3_wrap2_s7_clk = {
	2250	+ .halt_reg = 0x1e8a8,
	2251	+ .halt_check = BRANCH_HALT_VOTED,
	2252	+ .clkr = {
	2253	+ .enable_reg = 0x52010,
	2254	+ .enable_mask = BIT(17),
	2255	+ .hw.init = &(const struct clk_init_data) {
	2256	+ .name = "gcc_qupv3_wrap2_s7_clk",
	2257	+ .parent_hws = (const struct clk_hw*[]) {
	2258	+ &gcc_qupv3_wrap2_s7_clk_src.clkr.hw,
	2259	+ },
	2260	+ .num_parents = 1,
	2261	+ .flags = CLK_SET_RATE_PARENT,
	2262	+ .ops = &clk_branch2_ops,
	2263	+ },
	2264	+ },
	2265	+};
	2266	+
	2267	+static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
	2268	+ .halt_reg = 0x23000,
	2269	+ .halt_check = BRANCH_HALT_VOTED,
	2270	+ .clkr = {
	2271	+ .enable_reg = 0x52008,
	2272	+ .enable_mask = BIT(20),
	2273	+ .hw.init = &(const struct clk_init_data) {
	2274	+ .name = "gcc_qupv3_wrap_1_m_ahb_clk",
	2275	+ .ops = &clk_branch2_ops,
	2276	+ },
	2277	+ },
	2278	+};
	2279	+
	2280	+static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
	2281	+ .halt_reg = 0x23004,
	2282	+ .halt_check = BRANCH_HALT_VOTED,
	2283	+ .hwcg_reg = 0x23004,
	2284	+ .hwcg_bit = 1,
	2285	+ .clkr = {
	2286	+ .enable_reg = 0x52008,
	2287	+ .enable_mask = BIT(21),
	2288	+ .hw.init = &(const struct clk_init_data) {
	2289	+ .name = "gcc_qupv3_wrap_1_s_ahb_clk",
	2290	+ .ops = &clk_branch2_ops,
	2291	+ },
	2292	+ },
	2293	+};
	2294	+
	2295	+static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
	2296	+ .halt_reg = 0x23158,
	2297	+ .halt_check = BRANCH_HALT_VOTED,
	2298	+ .hwcg_reg = 0x23158,
	2299	+ .hwcg_bit = 1,
	2300	+ .clkr = {
	2301	+ .enable_reg = 0x52010,
	2302	+ .enable_mask = BIT(2),
	2303	+ .hw.init = &(const struct clk_init_data) {
	2304	+ .name = "gcc_qupv3_wrap_2_m_ahb_clk",
	2305	+ .ops = &clk_branch2_ops,
	2306	+ },
	2307	+ },
	2308	+};
	2309	+
	2310	+static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
	2311	+ .halt_reg = 0x2315c,
	2312	+ .halt_check = BRANCH_HALT_VOTED,
	2313	+ .hwcg_reg = 0x2315c,
	2314	+ .hwcg_bit = 1,
	2315	+ .clkr = {
	2316	+ .enable_reg = 0x52010,
	2317	+ .enable_mask = BIT(1),
	2318	+ .hw.init = &(const struct clk_init_data) {
	2319	+ .name = "gcc_qupv3_wrap_2_s_ahb_clk",
	2320	+ .ops = &clk_branch2_ops,
	2321	+ },
	2322	+ },
	2323	+};
	2324	+
	2325	+static struct clk_branch gcc_sdcc1_ahb_clk = {
	2326	+ .halt_reg = 0xa9004,
	2327	+ .halt_check = BRANCH_HALT,
	2328	+ .clkr = {
	2329	+ .enable_reg = 0xa9004,
	2330	+ .enable_mask = BIT(0),
	2331	+ .hw.init = &(const struct clk_init_data) {
	2332	+ .name = "gcc_sdcc1_ahb_clk",
	2333	+ .ops = &clk_branch2_ops,
	2334	+ },
	2335	+ },
	2336	+};
	2337	+
	2338	+static struct clk_branch gcc_sdcc1_apps_clk = {
	2339	+ .halt_reg = 0xa9008,
	2340	+ .halt_check = BRANCH_HALT,
	2341	+ .clkr = {
	2342	+ .enable_reg = 0xa9008,
	2343	+ .enable_mask = BIT(0),
	2344	+ .hw.init = &(const struct clk_init_data) {
	2345	+ .name = "gcc_sdcc1_apps_clk",
	2346	+ .parent_hws = (const struct clk_hw*[]) {
	2347	+ &gcc_sdcc1_apps_clk_src.clkr.hw,
	2348	+ },
	2349	+ .num_parents = 1,
	2350	+ .flags = CLK_SET_RATE_PARENT,
	2351	+ .ops = &clk_branch2_ops,
	2352	+ },
	2353	+ },
	2354	+};
	2355	+
	2356	+static struct clk_branch gcc_sdcc1_ice_core_clk = {
	2357	+ .halt_reg = 0xa9030,
	2358	+ .halt_check = BRANCH_HALT_VOTED,
	2359	+ .hwcg_reg = 0xa9030,
	2360	+ .hwcg_bit = 1,
	2361	+ .clkr = {
	2362	+ .enable_reg = 0xa9030,
	2363	+ .enable_mask = BIT(0),
	2364	+ .hw.init = &(const struct clk_init_data) {
	2365	+ .name = "gcc_sdcc1_ice_core_clk",
	2366	+ .parent_hws = (const struct clk_hw*[]) {
	2367	+ &gcc_sdcc1_ice_core_clk_src.clkr.hw,
	2368	+ },
	2369	+ .num_parents = 1,
	2370	+ .flags = CLK_SET_RATE_PARENT,
	2371	+ .ops = &clk_branch2_ops,
	2372	+ },
	2373	+ },
	2374	+};
	2375	+
	2376	+static struct clk_branch gcc_sdcc2_ahb_clk = {
	2377	+ .halt_reg = 0x14014,
	2378	+ .halt_check = BRANCH_HALT,
	2379	+ .clkr = {
	2380	+ .enable_reg = 0x14014,
	2381	+ .enable_mask = BIT(0),
	2382	+ .hw.init = &(const struct clk_init_data) {
	2383	+ .name = "gcc_sdcc2_ahb_clk",
	2384	+ .ops = &clk_branch2_ops,
	2385	+ },
	2386	+ },
	2387	+};
	2388	+
	2389	+static struct clk_branch gcc_sdcc2_apps_clk = {
	2390	+ .halt_reg = 0x14004,
	2391	+ .halt_check = BRANCH_HALT,
	2392	+ .clkr = {
	2393	+ .enable_reg = 0x14004,
	2394	+ .enable_mask = BIT(0),
	2395	+ .hw.init = &(const struct clk_init_data) {
	2396	+ .name = "gcc_sdcc2_apps_clk",
	2397	+ .parent_hws = (const struct clk_hw*[]) {
	2398	+ &gcc_sdcc2_apps_clk_src.clkr.hw,
	2399	+ },
	2400	+ .num_parents = 1,
	2401	+ .flags = CLK_SET_RATE_PARENT,
	2402	+ .ops = &clk_branch2_ops,
	2403	+ },
	2404	+ },
	2405	+};
	2406	+
	2407	+static struct clk_branch gcc_ufs_phy_ahb_clk = {
	2408	+ .halt_reg = 0x77028,
	2409	+ .halt_check = BRANCH_HALT_VOTED,
	2410	+ .hwcg_reg = 0x77028,
	2411	+ .hwcg_bit = 1,
	2412	+ .clkr = {
	2413	+ .enable_reg = 0x77028,
	2414	+ .enable_mask = BIT(0),
	2415	+ .hw.init = &(const struct clk_init_data) {
	2416	+ .name = "gcc_ufs_phy_ahb_clk",
	2417	+ .ops = &clk_branch2_ops,
	2418	+ },
	2419	+ },
	2420	+};
	2421	+
	2422	+static struct clk_branch gcc_ufs_phy_axi_clk = {
	2423	+ .halt_reg = 0x77018,
	2424	+ .halt_check = BRANCH_HALT_VOTED,
	2425	+ .hwcg_reg = 0x77018,
	2426	+ .hwcg_bit = 1,
	2427	+ .clkr = {
	2428	+ .enable_reg = 0x77018,
	2429	+ .enable_mask = BIT(0),
	2430	+ .hw.init = &(const struct clk_init_data) {
	2431	+ .name = "gcc_ufs_phy_axi_clk",
	2432	+ .parent_hws = (const struct clk_hw*[]) {
	2433	+ &gcc_ufs_phy_axi_clk_src.clkr.hw,
	2434	+ },
	2435	+ .num_parents = 1,
	2436	+ .flags = CLK_SET_RATE_PARENT,
	2437	+ .ops = &clk_branch2_ops,
	2438	+ },
	2439	+ },
	2440	+};
	2441	+
	2442	+static struct clk_branch gcc_ufs_phy_ice_core_clk = {
	2443	+ .halt_reg = 0x7707c,
	2444	+ .halt_check = BRANCH_HALT_VOTED,
	2445	+ .hwcg_reg = 0x7707c,
	2446	+ .hwcg_bit = 1,
	2447	+ .clkr = {
	2448	+ .enable_reg = 0x7707c,
	2449	+ .enable_mask = BIT(0),
	2450	+ .hw.init = &(const struct clk_init_data) {
	2451	+ .name = "gcc_ufs_phy_ice_core_clk",
	2452	+ .parent_hws = (const struct clk_hw*[]) {
	2453	+ &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
	2454	+ },
	2455	+ .num_parents = 1,
	2456	+ .flags = CLK_SET_RATE_PARENT,
	2457	+ .ops = &clk_branch2_ops,
	2458	+ },
	2459	+ },
	2460	+};
	2461	+
	2462	+static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
	2463	+ .halt_reg = 0x770bc,
	2464	+ .halt_check = BRANCH_HALT_VOTED,
	2465	+ .hwcg_reg = 0x770bc,
	2466	+ .hwcg_bit = 1,
	2467	+ .clkr = {
	2468	+ .enable_reg = 0x770bc,
	2469	+ .enable_mask = BIT(0),
	2470	+ .hw.init = &(const struct clk_init_data) {
	2471	+ .name = "gcc_ufs_phy_phy_aux_clk",
	2472	+ .parent_hws = (const struct clk_hw*[]) {
	2473	+ &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
	2474	+ },
	2475	+ .num_parents = 1,
	2476	+ .flags = CLK_SET_RATE_PARENT,
	2477	+ .ops = &clk_branch2_ops,
	2478	+ },
	2479	+ },
	2480	+};
	2481	+
	2482	+static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
	2483	+ .halt_reg = 0x77030,
	2484	+ .halt_check = BRANCH_HALT_DELAY,
	2485	+ .clkr = {
	2486	+ .enable_reg = 0x77030,
	2487	+ .enable_mask = BIT(0),
	2488	+ .hw.init = &(const struct clk_init_data) {
	2489	+ .name = "gcc_ufs_phy_rx_symbol_0_clk",
	2490	+ .parent_hws = (const struct clk_hw*[]) {
	2491	+ &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
	2492	+ },
	2493	+ .num_parents = 1,
	2494	+ .flags = CLK_SET_RATE_PARENT,
	2495	+ .ops = &clk_branch2_ops,
	2496	+ },
	2497	+ },
	2498	+};
	2499	+
	2500	+static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
	2501	+ .halt_reg = 0x770d8,
	2502	+ .halt_check = BRANCH_HALT_DELAY,
	2503	+ .clkr = {
	2504	+ .enable_reg = 0x770d8,
	2505	+ .enable_mask = BIT(0),
	2506	+ .hw.init = &(const struct clk_init_data) {
	2507	+ .name = "gcc_ufs_phy_rx_symbol_1_clk",
	2508	+ .parent_hws = (const struct clk_hw*[]) {
	2509	+ &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
	2510	+ },
	2511	+ .num_parents = 1,
	2512	+ .flags = CLK_SET_RATE_PARENT,
	2513	+ .ops = &clk_branch2_ops,
	2514	+ },
	2515	+ },
	2516	+};
	2517	+
	2518	+static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
	2519	+ .halt_reg = 0x7702c,
	2520	+ .halt_check = BRANCH_HALT_DELAY,
	2521	+ .clkr = {
	2522	+ .enable_reg = 0x7702c,
	2523	+ .enable_mask = BIT(0),
	2524	+ .hw.init = &(const struct clk_init_data) {
	2525	+ .name = "gcc_ufs_phy_tx_symbol_0_clk",
	2526	+ .parent_hws = (const struct clk_hw*[]) {
	2527	+ &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
	2528	+ },
	2529	+ .num_parents = 1,
	2530	+ .flags = CLK_SET_RATE_PARENT,
	2531	+ .ops = &clk_branch2_ops,
	2532	+ },
	2533	+ },
	2534	+};
	2535	+
	2536	+static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
	2537	+ .halt_reg = 0x7706c,
	2538	+ .halt_check = BRANCH_HALT_VOTED,
	2539	+ .hwcg_reg = 0x7706c,
	2540	+ .hwcg_bit = 1,
	2541	+ .clkr = {
	2542	+ .enable_reg = 0x7706c,
	2543	+ .enable_mask = BIT(0),
	2544	+ .hw.init = &(const struct clk_init_data) {
	2545	+ .name = "gcc_ufs_phy_unipro_core_clk",
	2546	+ .parent_hws = (const struct clk_hw*[]) {
	2547	+ &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
	2548	+ },
	2549	+ .num_parents = 1,
	2550	+ .flags = CLK_SET_RATE_PARENT,
	2551	+ .ops = &clk_branch2_ops,
	2552	+ },
	2553	+ },
	2554	+};
	2555	+
	2556	+static struct clk_branch gcc_usb30_prim_atb_clk = {
	2557	+ .halt_reg = 0x3908c,
	2558	+ .halt_check = BRANCH_HALT_VOTED,
	2559	+ .clkr = {
	2560	+ .enable_reg = 0x3908c,
	2561	+ .enable_mask = BIT(0),
	2562	+ .hw.init = &(const struct clk_init_data) {
	2563	+ .name = "gcc_usb30_prim_atb_clk",
	2564	+ .parent_hws = (const struct clk_hw*[]) {
	2565	+ &gcc_usb30_prim_master_clk_src.clkr.hw,
	2566	+ },
	2567	+ .num_parents = 1,
	2568	+ .flags = CLK_SET_RATE_PARENT,
	2569	+ .ops = &clk_branch2_ops,
	2570	+ },
	2571	+ },
	2572	+};
	2573	+
	2574	+static struct clk_branch gcc_usb30_prim_master_clk = {
	2575	+ .halt_reg = 0x39018,
	2576	+ .halt_check = BRANCH_HALT,
	2577	+ .clkr = {
	2578	+ .enable_reg = 0x39018,
	2579	+ .enable_mask = BIT(0),
	2580	+ .hw.init = &(const struct clk_init_data) {
	2581	+ .name = "gcc_usb30_prim_master_clk",
	2582	+ .parent_hws = (const struct clk_hw*[]) {
	2583	+ &gcc_usb30_prim_master_clk_src.clkr.hw,
	2584	+ },
	2585	+ .num_parents = 1,
	2586	+ .flags = CLK_SET_RATE_PARENT,
	2587	+ .ops = &clk_branch2_ops,
	2588	+ },
	2589	+ },
	2590	+};
	2591	+
	2592	+static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
	2593	+ .halt_reg = 0x3902c,
	2594	+ .halt_check = BRANCH_HALT,
	2595	+ .clkr = {
	2596	+ .enable_reg = 0x3902c,
	2597	+ .enable_mask = BIT(0),
	2598	+ .hw.init = &(const struct clk_init_data) {
	2599	+ .name = "gcc_usb30_prim_mock_utmi_clk",
	2600	+ .parent_hws = (const struct clk_hw*[]) {
	2601	+ &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
	2602	+ },
	2603	+ .num_parents = 1,
	2604	+ .flags = CLK_SET_RATE_PARENT,
	2605	+ .ops = &clk_branch2_ops,
	2606	+ },
	2607	+ },
	2608	+};
	2609	+
	2610	+static struct clk_branch gcc_usb30_prim_sleep_clk = {
	2611	+ .halt_reg = 0x39028,
	2612	+ .halt_check = BRANCH_HALT,
	2613	+ .clkr = {
	2614	+ .enable_reg = 0x39028,
	2615	+ .enable_mask = BIT(0),
	2616	+ .hw.init = &(const struct clk_init_data) {
	2617	+ .name = "gcc_usb30_prim_sleep_clk",
	2618	+ .ops = &clk_branch2_ops,
	2619	+ },
	2620	+ },
	2621	+};
	2622	+
	2623	+static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
	2624	+ .halt_reg = 0x39064,
	2625	+ .halt_check = BRANCH_HALT,
	2626	+ .clkr = {
	2627	+ .enable_reg = 0x39064,
	2628	+ .enable_mask = BIT(0),
	2629	+ .hw.init = &(const struct clk_init_data) {
	2630	+ .name = "gcc_usb3_prim_phy_aux_clk",
	2631	+ .parent_hws = (const struct clk_hw*[]) {
	2632	+ &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
	2633	+ },
	2634	+ .num_parents = 1,
	2635	+ .flags = CLK_SET_RATE_PARENT,
	2636	+ .ops = &clk_branch2_ops,
	2637	+ },
	2638	+ },
	2639	+};
	2640	+
	2641	+static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
	2642	+ .halt_reg = 0x39068,
	2643	+ .halt_check = BRANCH_HALT,
	2644	+ .clkr = {
	2645	+ .enable_reg = 0x39068,
	2646	+ .enable_mask = BIT(0),
	2647	+ .hw.init = &(const struct clk_init_data) {
	2648	+ .name = "gcc_usb3_prim_phy_com_aux_clk",
	2649	+ .parent_hws = (const struct clk_hw*[]) {
	2650	+ &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
	2651	+ },
	2652	+ .num_parents = 1,
	2653	+ .flags = CLK_SET_RATE_PARENT,
	2654	+ .ops = &clk_branch2_ops,
	2655	+ },
	2656	+ },
	2657	+};
	2658	+
	2659	+static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
	2660	+ .halt_reg = 0x3906c,
	2661	+ .halt_check = BRANCH_HALT_DELAY,
	2662	+ .hwcg_reg = 0x3906c,
	2663	+ .hwcg_bit = 1,
	2664	+ .clkr = {
	2665	+ .enable_reg = 0x3906c,
	2666	+ .enable_mask = BIT(0),
	2667	+ .hw.init = &(const struct clk_init_data) {
	2668	+ .name = "gcc_usb3_prim_phy_pipe_clk",
	2669	+ .parent_hws = (const struct clk_hw*[]) {
	2670	+ &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
	2671	+ },
	2672	+ .num_parents = 1,
	2673	+ .flags = CLK_SET_RATE_PARENT,
	2674	+ .ops = &clk_branch2_ops,
	2675	+ },
	2676	+ },
	2677	+};
	2678	+
	2679	+static struct clk_branch gcc_video_axi0_clk = {
	2680	+ .halt_reg = 0x32018,
	2681	+ .halt_check = BRANCH_HALT_SKIP,
	2682	+ .hwcg_reg = 0x32018,
	2683	+ .hwcg_bit = 1,
	2684	+ .clkr = {
	2685	+ .enable_reg = 0x32018,
	2686	+ .enable_mask = BIT(0),
	2687	+ .hw.init = &(const struct clk_init_data) {
	2688	+ .name = "gcc_video_axi0_clk",
	2689	+ .ops = &clk_branch2_ops,
	2690	+ },
	2691	+ },
	2692	+};
	2693	+
	2694	+static struct clk_branch gcc_video_axi1_clk = {
	2695	+ .halt_reg = 0x32028,
	2696	+ .halt_check = BRANCH_HALT_SKIP,
	2697	+ .hwcg_reg = 0x32028,
	2698	+ .hwcg_bit = 1,
	2699	+ .clkr = {
	2700	+ .enable_reg = 0x32028,
	2701	+ .enable_mask = BIT(0),
	2702	+ .hw.init = &(const struct clk_init_data) {
	2703	+ .name = "gcc_video_axi1_clk",
	2704	+ .ops = &clk_branch2_ops,
	2705	+ },
	2706	+ },
	2707	+};
	2708	+
	2709	+static struct gdsc gcc_pcie_0_gdsc = {
	2710	+ .gdscr = 0x6b004,
	2711	+ .en_rest_wait_val = 0x2,
	2712	+ .en_few_wait_val = 0x2,
	2713	+ .clk_dis_wait_val = 0xf,
	2714	+ .collapse_ctrl = 0x5214c,
	2715	+ .collapse_mask = BIT(0),
	2716	+ .pd = {
	2717	+ .name = "gcc_pcie_0_gdsc",
	2718	+ },
	2719	+ .pwrsts = PWRSTS_OFF_ON,
	2720	+ .flags = POLL_CFG_GDSCR \| RETAIN_FF_ENABLE \| VOTABLE,
	2721	+};
	2722	+
	2723	+static struct gdsc gcc_pcie_0_phy_gdsc = {
	2724	+ .gdscr = 0x6c000,
	2725	+ .en_rest_wait_val = 0x2,
	2726	+ .en_few_wait_val = 0x2,
	2727	+ .clk_dis_wait_val = 0x2,
	2728	+ .collapse_ctrl = 0x5214c,
	2729	+ .collapse_mask = BIT(2),
	2730	+ .pd = {
	2731	+ .name = "gcc_pcie_0_phy_gdsc",
	2732	+ },
	2733	+ .pwrsts = PWRSTS_OFF_ON,
	2734	+ .flags = POLL_CFG_GDSCR \| RETAIN_FF_ENABLE \| VOTABLE,
	2735	+};
	2736	+
	2737	+static struct gdsc gcc_pcie_1_gdsc = {
	2738	+ .gdscr = 0xac004,
	2739	+ .en_rest_wait_val = 0x2,
	2740	+ .en_few_wait_val = 0x2,
	2741	+ .clk_dis_wait_val = 0xf,
	2742	+ .collapse_ctrl = 0x5214c,
	2743	+ .collapse_mask = BIT(3),
	2744	+ .pd = {
	2745	+ .name = "gcc_pcie_1_gdsc",
	2746	+ },
	2747	+ .pwrsts = PWRSTS_OFF_ON,
	2748	+ .flags = POLL_CFG_GDSCR \| RETAIN_FF_ENABLE \| VOTABLE,
	2749	+};
	2750	+
	2751	+static struct gdsc gcc_pcie_1_phy_gdsc = {
	2752	+ .gdscr = 0xad000,
	2753	+ .en_rest_wait_val = 0x2,
	2754	+ .en_few_wait_val = 0x2,
	2755	+ .clk_dis_wait_val = 0x2,
	2756	+ .collapse_ctrl = 0x5214c,
	2757	+ .collapse_mask = BIT(4),
	2758	+ .pd = {
	2759	+ .name = "gcc_pcie_1_phy_gdsc",
	2760	+ },
	2761	+ .pwrsts = PWRSTS_OFF_ON,
	2762	+ .flags = POLL_CFG_GDSCR \| RETAIN_FF_ENABLE \| VOTABLE,
	2763	+};
	2764	+
	2765	+static struct gdsc gcc_ufs_mem_phy_gdsc = {
	2766	+ .gdscr = 0x9e000,
	2767	+ .en_rest_wait_val = 0x2,
	2768	+ .en_few_wait_val = 0x2,
	2769	+ .clk_dis_wait_val = 0x2,
	2770	+ .pd = {
	2771	+ .name = "gcc_ufs_mem_phy_gdsc",
	2772	+ },
	2773	+ .pwrsts = PWRSTS_OFF_ON,
	2774	+ .flags = POLL_CFG_GDSCR \| RETAIN_FF_ENABLE,
	2775	+};
	2776	+
	2777	+static struct gdsc gcc_ufs_phy_gdsc = {
	2778	+ .gdscr = 0x77004,
	2779	+ .en_rest_wait_val = 0x2,
	2780	+ .en_few_wait_val = 0x2,
	2781	+ .clk_dis_wait_val = 0xf,
	2782	+ .pd = {
	2783	+ .name = "gcc_ufs_phy_gdsc",
	2784	+ },
	2785	+ .pwrsts = PWRSTS_OFF_ON,
	2786	+ .flags = POLL_CFG_GDSCR \| RETAIN_FF_ENABLE,
	2787	+};
	2788	+
	2789	+static struct gdsc gcc_usb30_prim_gdsc = {
	2790	+ .gdscr = 0x39004,
	2791	+ .en_rest_wait_val = 0x2,
	2792	+ .en_few_wait_val = 0x2,
	2793	+ .clk_dis_wait_val = 0xf,
	2794	+ .pd = {
	2795	+ .name = "gcc_usb30_prim_gdsc",
	2796	+ },
	2797	+ .pwrsts = PWRSTS_OFF_ON,
	2798	+ .flags = POLL_CFG_GDSCR \| RETAIN_FF_ENABLE,
	2799	+};
	2800	+
	2801	+static struct gdsc gcc_usb3_phy_gdsc = {
	2802	+ .gdscr = 0x50018,
	2803	+ .en_rest_wait_val = 0x2,
	2804	+ .en_few_wait_val = 0x2,
	2805	+ .clk_dis_wait_val = 0x2,
	2806	+ .pd = {
	2807	+ .name = "gcc_usb3_phy_gdsc",
	2808	+ },
	2809	+ .pwrsts = PWRSTS_OFF_ON,
	2810	+ .flags = POLL_CFG_GDSCR \| RETAIN_FF_ENABLE,
	2811	+};
	2812	+
	2813	+static struct clk_regmap *gcc_eliza_clocks[] = {
	2814	+ [GCC_AGGRE_NOC_PCIE_AXI_CLK] = &gcc_aggre_noc_pcie_axi_clk.clkr,
	2815	+ [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
	2816	+ [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
	2817	+ [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
	2818	+ [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
	2819	+ [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
	2820	+ [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,
	2821	+ [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
	2822	+ [GCC_CNOC_PCIE_SF_AXI_CLK] = &gcc_cnoc_pcie_sf_axi_clk.clkr,
	2823	+ [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
	2824	+ [GCC_DDRSS_PCIE_SF_QTB_CLK] = &gcc_ddrss_pcie_sf_qtb_clk.clkr,
	2825	+ [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
	2826	+ [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
	2827	+ [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
	2828	+ [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
	2829	+ [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
	2830	+ [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
	2831	+ [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
	2832	+ [GCC_GPLL0] = &gcc_gpll0.clkr,
	2833	+ [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
	2834	+ [GCC_GPLL4] = &gcc_gpll4.clkr,
	2835	+ [GCC_GPLL7] = &gcc_gpll7.clkr,
	2836	+ [GCC_GPLL8] = &gcc_gpll8.clkr,
	2837	+ [GCC_GPLL9] = &gcc_gpll9.clkr,
	2838	+ [GCC_GPU_GEMNOC_GFX_CLK] = &gcc_gpu_gemnoc_gfx_clk.clkr,
	2839	+ [GCC_GPU_GPLL0_CPH_CLK_SRC] = &gcc_gpu_gpll0_cph_clk_src.clkr,
	2840	+ [GCC_GPU_GPLL0_DIV_CPH_CLK_SRC] = &gcc_gpu_gpll0_div_cph_clk_src.clkr,
	2841	+ [GCC_GPU_SMMU_VOTE_CLK] = &gcc_gpu_smmu_vote_clk.clkr,
	2842	+ [GCC_MMU_TCU_VOTE_CLK] = &gcc_mmu_tcu_vote_clk.clkr,
	2843	+ [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
	2844	+ [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
	2845	+ [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
	2846	+ [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
	2847	+ [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
	2848	+ [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
	2849	+ [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
	2850	+ [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
	2851	+ [GCC_PCIE_0_PIPE_DIV2_CLK] = &gcc_pcie_0_pipe_div2_clk.clkr,
	2852	+ [GCC_PCIE_0_PIPE_DIV2_CLK_SRC] = &gcc_pcie_0_pipe_div2_clk_src.clkr,
	2853	+ [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
	2854	+ [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
	2855	+ [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
	2856	+ [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
	2857	+ [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
	2858	+ [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
	2859	+ [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
	2860	+ [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
	2861	+ [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
	2862	+ [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
	2863	+ [GCC_PCIE_1_PIPE_DIV2_CLK] = &gcc_pcie_1_pipe_div2_clk.clkr,
	2864	+ [GCC_PCIE_1_PIPE_DIV2_CLK_SRC] = &gcc_pcie_1_pipe_div2_clk_src.clkr,
	2865	+ [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
	2866	+ [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
	2867	+ [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
	2868	+ [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
	2869	+ [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
	2870	+ [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
	2871	+ [GCC_QMIP_CAMERA_CMD_AHB_CLK] = &gcc_qmip_camera_cmd_ahb_clk.clkr,
	2872	+ [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
	2873	+ [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
	2874	+ [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,
	2875	+ [GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr,
	2876	+ [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr,
	2877	+ [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
	2878	+ [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
	2879	+ [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
	2880	+ [GCC_QUPV3_WRAP1_QSPI_REF_CLK] = &gcc_qupv3_wrap1_qspi_ref_clk.clkr,
	2881	+ [GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr,
	2882	+ [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
	2883	+ [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
	2884	+ [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
	2885	+ [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
	2886	+ [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
	2887	+ [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
	2888	+ [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
	2889	+ [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
	2890	+ [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
	2891	+ [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
	2892	+ [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
	2893	+ [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
	2894	+ [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
	2895	+ [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
	2896	+ [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
	2897	+ [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
	2898	+ [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
	2899	+ [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
	2900	+ [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
	2901	+ [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
	2902	+ [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
	2903	+ [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
	2904	+ [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
	2905	+ [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
	2906	+ [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
	2907	+ [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
	2908	+ [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
	2909	+ [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
	2910	+ [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
	2911	+ [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
	2912	+ [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
	2913	+ [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
	2914	+ [GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr,
	2915	+ [GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr,
	2916	+ [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
	2917	+ [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
	2918	+ [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
	2919	+ [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
	2920	+ [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
	2921	+ [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
	2922	+ [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
	2923	+ [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
	2924	+ [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
	2925	+ [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
	2926	+ [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
	2927	+ [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
	2928	+ [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
	2929	+ [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
	2930	+ [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
	2931	+ [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
	2932	+ [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
	2933	+ [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
	2934	+ [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
	2935	+ [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
	2936	+ [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
	2937	+ [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
	2938	+ [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
	2939	+ [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
	2940	+ [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
	2941	+ [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
	2942	+ [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
	2943	+ [GCC_USB30_PRIM_ATB_CLK] = &gcc_usb30_prim_atb_clk.clkr,
	2944	+ [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
	2945	+ [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
	2946	+ [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
	2947	+ [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
	2948	+ [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
	2949	+ [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
	2950	+ [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
	2951	+ [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
	2952	+ [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
	2953	+ [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
	2954	+ [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
	2955	+ [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
	2956	+ [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
	2957	+};
	2958	+
	2959	+static struct gdsc *gcc_eliza_gdscs[] = {
	2960	+ [GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc,
	2961	+ [GCC_PCIE_0_PHY_GDSC] = &gcc_pcie_0_phy_gdsc,
	2962	+ [GCC_PCIE_1_GDSC] = &gcc_pcie_1_gdsc,
	2963	+ [GCC_PCIE_1_PHY_GDSC] = &gcc_pcie_1_phy_gdsc,
	2964	+ [GCC_UFS_MEM_PHY_GDSC] = &gcc_ufs_mem_phy_gdsc,
	2965	+ [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc,
	2966	+ [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
	2967	+ [GCC_USB3_PHY_GDSC] = &gcc_usb3_phy_gdsc,
	2968	+};
	2969	+
	2970	+static const struct qcom_reset_map gcc_eliza_resets[] = {
	2971	+ [GCC_CAMERA_BCR] = { 0x26000 },
	2972	+ [GCC_DISPLAY_BCR] = { 0x27000 },
	2973	+ [GCC_GPU_BCR] = { 0x71000 },
	2974	+ [GCC_PCIE_0_BCR] = { 0x6b000 },
	2975	+ [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
	2976	+ [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
	2977	+ [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
	2978	+ [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
	2979	+ [GCC_PCIE_1_BCR] = { 0xac000 },
	2980	+ [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
	2981	+ [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
	2982	+ [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
	2983	+ [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 },
	2984	+ [GCC_PCIE_PHY_BCR] = { 0x6f000 },
	2985	+ [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
	2986	+ [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
	2987	+ [GCC_PCIE_RSCC_BCR] = { 0x11000 },
	2988	+ [GCC_PDM_BCR] = { 0x33000 },
	2989	+ [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
	2990	+ [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
	2991	+ [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
	2992	+ [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
	2993	+ [GCC_SDCC1_BCR] = { 0xa9000 },
	2994	+ [GCC_SDCC2_BCR] = { 0x14000 },
	2995	+ [GCC_UFS_PHY_BCR] = { 0x77000 },
	2996	+ [GCC_USB30_PRIM_BCR] = { 0x39000 },
	2997	+ [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
	2998	+ [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
	2999	+ [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
	3000	+ [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
	3001	+ [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
	3002	+ [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
	3003	+ [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 },
	3004	+ [GCC_VIDEO_AXI1_CLK_ARES] = { 0x32028, 2 },
	3005	+ [GCC_VIDEO_BCR] = { 0x32000 },
	3006	+};
	3007	+
	3008	+static const u32 gcc_eliza_critical_cbcrs[] = {
	3009	+ 0xa0004, /* GCC_CAM_BIST_MCLK_AHB_CLK */
	3010	+ 0x26004, /* GCC_CAMERA_AHB_CLK */
	3011	+ 0x26034, /* GCC_CAMERA_XO_CLK */
	3012	+ 0x27004, /* GCC_DISP_AHB_CLK */
	3013	+ 0x71004, /* GCC_GPU_CFG_AHB_CLK */
	3014	+ 0x52010, /* GCC_PCIE_RSCC_CFG_AHB_CLK */
	3015	+ 0x52010, /* GCC_PCIE_RSCC_XO_CLK */
	3016	+ 0x32004, /* GCC_VIDEO_AHB_CLK */
	3017	+ 0x32038, /* GCC_VIDEO_XO_CLK */
	3018	+};
	3019	+
	3020	+static const struct clk_rcg_dfs_data gcc_eliza_dfs_clocks[] = {
	3021	+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_ref_clk_src),
	3022	+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
	3023	+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
	3024	+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
	3025	+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
	3026	+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
	3027	+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
	3028	+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
	3029	+ DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
	3030	+ DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
	3031	+ DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
	3032	+ DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
	3033	+ DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
	3034	+ DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
	3035	+ DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),
	3036	+ DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src),
	3037	+};
	3038	+
	3039	+static const struct regmap_config gcc_eliza_regmap_config = {
	3040	+ .reg_bits = 32,
	3041	+ .reg_stride = 4,
	3042	+ .val_bits = 32,
	3043	+ .max_register = 0x1f41f0,
	3044	+ .fast_io = true,
	3045	+};
	3046	+
	3047	+static void clk_eliza_regs_configure(struct device dev, struct regmap regmap)
	3048	+{
	3049	+ /* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */
	3050	+ qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
	3051	+ qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
	3052	+}
	3053	+
	3054	+static const struct qcom_cc_driver_data gcc_eliza_driver_data = {
	3055	+ .clk_cbcrs = gcc_eliza_critical_cbcrs,
	3056	+ .num_clk_cbcrs = ARRAY_SIZE(gcc_eliza_critical_cbcrs),
	3057	+ .dfs_rcgs = gcc_eliza_dfs_clocks,
	3058	+ .num_dfs_rcgs = ARRAY_SIZE(gcc_eliza_dfs_clocks),
	3059	+ .clk_regs_configure = clk_eliza_regs_configure,
	3060	+};
	3061	+
	3062	+static const struct qcom_cc_desc gcc_eliza_desc = {
	3063	+ .config = &gcc_eliza_regmap_config,
	3064	+ .clks = gcc_eliza_clocks,
	3065	+ .num_clks = ARRAY_SIZE(gcc_eliza_clocks),
	3066	+ .resets = gcc_eliza_resets,
	3067	+ .num_resets = ARRAY_SIZE(gcc_eliza_resets),
	3068	+ .gdscs = gcc_eliza_gdscs,
	3069	+ .num_gdscs = ARRAY_SIZE(gcc_eliza_gdscs),
	3070	+ .driver_data = &gcc_eliza_driver_data,
	3071	+};
	3072	+
	3073	+static const struct of_device_id gcc_eliza_match_table[] = {
	3074	+ { .compatible = "qcom,eliza-gcc" },
	3075	+ { }
	3076	+};
	3077	+MODULE_DEVICE_TABLE(of, gcc_eliza_match_table);
	3078	+
	3079	+static int gcc_eliza_probe(struct platform_device *pdev)
	3080	+{
	3081	+ return qcom_cc_probe(pdev, &gcc_eliza_desc);
	3082	+}
	3083	+
	3084	+static struct platform_driver gcc_eliza_driver = {
	3085	+ .probe = gcc_eliza_probe,
	3086	+ .driver = {
	3087	+ .name = "gcc-eliza",
	3088	+ .of_match_table = gcc_eliza_match_table,
	3089	+ },
	3090	+};
	3091	+
	3092	+static int __init gcc_eliza_init(void)
	3093	+{
	3094	+ return platform_driver_register(&gcc_eliza_driver);
	3095	+}
	3096	+subsys_initcall(gcc_eliza_init);
	3097	+
	3098	+static void __exit gcc_eliza_exit(void)
	3099	+{
	3100	+ platform_driver_unregister(&gcc_eliza_driver);
	3101	+}
	3102	+module_exit(gcc_eliza_exit);
	3103	+
	3104	+MODULE_DESCRIPTION("QTI GCC Eliza Driver");
	3105	+MODULE_LICENSE("GPL");

drivers/clk/qcom/gcc-glymur.c+4−4

@@ -6,7 +6,6 @@ · 5 unmodified lines
6	6	#include <linux/clk-provider.h>
7	7	#include <linux/mod_devicetable.h>
8	8	#include <linux/module.h>
9		−#include <linux/of.h>
10	9	#include <linux/platform_device.h>
11	10	#include <linux/regmap.h>
12	11
@@ -8507,6 +8506,7 @@ static const struct qcom_reset_map gcc_glymur_resets[] = { · 8494 unmodified lines
8507	8506	[GCC_VIDEO_AXI0_CLK_ARES] = { 0x3201c, 2 },
8508	8507	[GCC_VIDEO_AXI1_CLK_ARES] = { 0x32044, 2 },
8509	8508	[GCC_VIDEO_BCR] = { 0x32000 },
	8509	+ [GCC_VIDEO_AXI0C_CLK_ARES] = { 0x32030, 2 },
8510	8510	};
8511	8511
8512	8512	static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
@@ -8538,7 +8538,7 @@ static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { · 25 unmodified lines
8538	8538	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src),
8539	8539	};
8540	8540
8541		−static u32 gcc_glymur_critical_cbcrs[] = {
	8541	+static const u32 gcc_glymur_critical_cbcrs[] = {
8542	8542	0x26004, /* GCC_CAMERA_AHB_CLK */
8543	8543	0x26040, /* GCC_CAMERA_XO_CLK */
8544	8544	0x27004, /* GCC_DISP_AHB_CLK */
@@ -8561,7 +8561,7 @@ static void clk_glymur_regs_configure(struct device dev, struct regmap regmap) · 16 unmodified lines
8561	8561	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
8562	8562	}
8563	8563
8564		−static struct qcom_cc_driver_data gcc_glymur_driver_data = {
	8564	+static const struct qcom_cc_driver_data gcc_glymur_driver_data = {
8565	8565	.clk_cbcrs = gcc_glymur_critical_cbcrs,
8566	8566	.num_clk_cbcrs = ARRAY_SIZE(gcc_glymur_critical_cbcrs),
8567	8567	.dfs_rcgs = gcc_dfs_clocks,
@@ -8611,5 +8611,5 @@ static void __exit gcc_glymur_exit(void) · 43 unmodified lines
8611	8611	}
8612	8612	module_exit(gcc_glymur_exit);
8613	8613
8614		−MODULE_DESCRIPTION("QTI GCC GLYMUR Driver");
	8614	+MODULE_DESCRIPTION("QTI GCC Glymur Driver");
8615	8615	MODULE_LICENSE("GPL");

drivers/clk/qcom/gcc-ipq5210.c+2661−0

@@ -0,0 +1,2661 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
	2	+/*
	3	+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
	4	+ */
	5	+
	6	+#include <linux/clk-provider.h>
	7	+#include <linux/module.h>
	8	+#include <linux/platform_device.h>
	9	+#include <linux/regmap.h>
	10	+
	11	+#include <dt-bindings/clock/qcom,ipq5210-gcc.h>
	12	+#include <dt-bindings/reset/qcom,ipq5210-gcc.h>
	13	+
	14	+#include "clk-alpha-pll.h"
	15	+#include "clk-branch.h"
	16	+#include "clk-rcg.h"
	17	+#include "clk-regmap.h"
	18	+#include "clk-regmap-divider.h"
	19	+#include "clk-regmap-mux.h"
	20	+#include "clk-regmap-phy-mux.h"
	21	+#include "reset.h"
	22	+
	23	+enum {
	24	+ DT_XO,
	25	+ DT_SLEEP_CLK,
	26	+ DT_PCIE30_PHY0_PIPE_CLK,
	27	+ DT_PCIE30_PHY1_PIPE_CLK,
	28	+ DT_USB3_PHY0_CC_PIPE_CLK,
	29	+ DT_NSS_CMN_CLK,
	30	+};
	31	+
	32	+enum {
	33	+ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC,
	34	+ P_GPLL0_OUT_AUX,
	35	+ P_GPLL0_OUT_MAIN,
	36	+ P_GPLL2_OUT_AUX,
	37	+ P_GPLL2_OUT_MAIN,
	38	+ P_GPLL4_OUT_AUX,
	39	+ P_GPLL4_OUT_MAIN,
	40	+ P_NSS_CMN_CLK,
	41	+ P_SLEEP_CLK,
	42	+ P_USB3PHY_0_PIPE,
	43	+ P_XO,
	44	+};
	45	+
	46	+static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO };
	47	+
	48	+static struct clk_alpha_pll gpll0_main = {
	49	+ .offset = 0x20000,
	50	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
	51	+ .clkr = {
	52	+ .enable_reg = 0xb000,
	53	+ .enable_mask = BIT(0),
	54	+ .hw.init = &(const struct clk_init_data) {
	55	+ .name = "gpll0_main",
	56	+ .parent_data = &gcc_parent_data_xo,
	57	+ .num_parents = 1,
	58	+ .ops = &clk_alpha_pll_ops,
	59	+ },
	60	+ },
	61	+};
	62	+
	63	+static struct clk_fixed_factor gpll0_div2 = {
	64	+ .mult = 1,
	65	+ .div = 2,
	66	+ .hw.init = &(const struct clk_init_data) {
	67	+ .name = "gpll0_div2",
	68	+ .parent_hws = (const struct clk_hw *[]) {
	69	+ &gpll0_main.clkr.hw
	70	+ },
	71	+ .num_parents = 1,
	72	+ .ops = &clk_fixed_factor_ops,
	73	+ },
	74	+};
	75	+
	76	+static struct clk_alpha_pll_postdiv gpll0 = {
	77	+ .offset = 0x20000,
	78	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
	79	+ .width = 4,
	80	+ .clkr.hw.init = &(const struct clk_init_data) {
	81	+ .name = "gpll0",
	82	+ .parent_hws = (const struct clk_hw *[]) {
	83	+ &gpll0_main.clkr.hw
	84	+ },
	85	+ .num_parents = 1,
	86	+ .ops = &clk_alpha_pll_postdiv_ro_ops,
	87	+ },
	88	+};
	89	+
	90	+static struct clk_alpha_pll gpll2_main = {
	91	+ .offset = 0x21000,
	92	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
	93	+ .clkr = {
	94	+ .enable_reg = 0xb000,
	95	+ .enable_mask = BIT(1),
	96	+ .hw.init = &(const struct clk_init_data) {
	97	+ .name = "gpll2_main",
	98	+ .parent_data = &gcc_parent_data_xo,
	99	+ .num_parents = 1,
	100	+ .ops = &clk_alpha_pll_ops,
	101	+ },
	102	+ },
	103	+};
	104	+
	105	+static const struct clk_div_table post_div_table_gpll2[] = {
	106	+ { 0x1, 2 },
	107	+ { }
	108	+};
	109	+
	110	+static struct clk_alpha_pll_postdiv gpll2 = {
	111	+ .offset = 0x21000,
	112	+ .post_div_table = post_div_table_gpll2,
	113	+ .num_post_div = ARRAY_SIZE(post_div_table_gpll2),
	114	+ .width = 4,
	115	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
	116	+ .clkr.hw.init = &(const struct clk_init_data) {
	117	+ .name = "gpll2",
	118	+ .parent_hws = (const struct clk_hw*[]) {
	119	+ &gpll2_main.clkr.hw,
	120	+ },
	121	+ .num_parents = 1,
	122	+ .ops = &clk_alpha_pll_postdiv_ro_ops,
	123	+ },
	124	+};
	125	+
	126	+static struct clk_alpha_pll gpll4_main = {
	127	+ .offset = 0x22000,
	128	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
	129	+ .clkr = {
	130	+ .enable_reg = 0xb000,
	131	+ .enable_mask = BIT(2),
	132	+ .hw.init = &(const struct clk_init_data) {
	133	+ .name = "gpll4_main",
	134	+ .parent_data = &gcc_parent_data_xo,
	135	+ .num_parents = 1,
	136	+ .ops = &clk_alpha_pll_ops,
	137	+ /*
	138	+ * There are no consumers for this GPLL in kernel yet,
	139	+ * (will be added soon), so the clock framework
	140	+ * disables this source. But some of the clocks
	141	+ * initialized by boot loaders uses this source. So we
	142	+ * need to keep this clock ON. Add the
	143	+ * CLK_IGNORE_UNUSED flag so the clock will not be
	144	+ * disabled. Once the consumer in kernel is added, we
	145	+ * can get rid of this flag.
	146	+ */
	147	+ .flags = CLK_IS_CRITICAL,
	148	+ },
	149	+ },
	150	+};
	151	+static const struct parent_map gcc_parent_map_xo[] = {
	152	+ { P_XO, 0 },
	153	+};
	154	+
	155	+static const struct parent_map gcc_parent_map_0[] = {
	156	+ { P_XO, 0 },
	157	+ { P_GPLL0_OUT_MAIN, 1 },
	158	+ { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
	159	+};
	160	+
	161	+static const struct clk_parent_data gcc_parent_data_0[] = {
	162	+ { .index = DT_XO },
	163	+ { .hw = &gpll0.clkr.hw },
	164	+ { .hw = &gpll0_div2.hw },
	165	+};
	166	+
	167	+static const struct parent_map gcc_parent_map_1[] = {
	168	+ { P_XO, 0 },
	169	+ { P_GPLL0_OUT_MAIN, 1 },
	170	+};
	171	+
	172	+static const struct clk_parent_data gcc_parent_data_1[] = {
	173	+ { .index = DT_XO },
	174	+ { .hw = &gpll0.clkr.hw },
	175	+};
	176	+
	177	+static const struct parent_map gcc_parent_map_2[] = {
	178	+ { P_XO, 0 },
	179	+ { P_GPLL0_OUT_MAIN, 1 },
	180	+ { P_GPLL4_OUT_MAIN, 2 },
	181	+};
	182	+
	183	+static const struct clk_parent_data gcc_parent_data_2[] = {
	184	+ { .index = DT_XO },
	185	+ { .hw = &gpll0.clkr.hw },
	186	+ { .hw = &gpll4_main.clkr.hw },
	187	+};
	188	+
	189	+static const struct parent_map gcc_parent_map_3[] = {
	190	+ { P_XO, 0 },
	191	+};
	192	+
	193	+static const struct clk_parent_data gcc_parent_data_3[] = {
	194	+ { .index = DT_XO },
	195	+};
	196	+
	197	+static const struct parent_map gcc_parent_map_4[] = {
	198	+ { P_XO, 0 },
	199	+ { P_NSS_CMN_CLK, 1 },
	200	+ { P_GPLL0_OUT_AUX, 2 },
	201	+ { P_GPLL2_OUT_AUX, 3 },
	202	+};
	203	+
	204	+static const struct clk_parent_data gcc_parent_data_4[] = {
	205	+ { .index = DT_XO },
	206	+ { .index = DT_NSS_CMN_CLK },
	207	+ { .hw = &gpll0.clkr.hw },
	208	+ { .hw = &gpll2_main.clkr.hw },
	209	+};
	210	+
	211	+static const struct parent_map gcc_parent_map_5[] = {
	212	+ { P_XO, 0 },
	213	+ { P_GPLL0_OUT_MAIN, 1 },
	214	+ { P_GPLL0_OUT_AUX, 2 },
	215	+ { P_SLEEP_CLK, 6 },
	216	+};
	217	+
	218	+static const struct clk_parent_data gcc_parent_data_5[] = {
	219	+ { .index = DT_XO },
	220	+ { .hw = &gpll0.clkr.hw },
	221	+ { .hw = &gpll0.clkr.hw },
	222	+ { .index = DT_SLEEP_CLK },
	223	+};
	224	+
	225	+static const struct parent_map gcc_parent_map_6[] = {
	226	+ { P_XO, 0 },
	227	+ { P_GPLL0_OUT_MAIN, 1 },
	228	+ { P_GPLL2_OUT_MAIN, 2 },
	229	+ { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
	230	+};
	231	+
	232	+static const struct clk_parent_data gcc_parent_data_6[] = {
	233	+ { .index = DT_XO },
	234	+ { .hw = &gpll0.clkr.hw },
	235	+ { .hw = &gpll2.clkr.hw },
	236	+ { .hw = &gpll0_div2.hw },
	237	+};
	238	+
	239	+static const struct parent_map gcc_parent_map_7[] = {
	240	+ { P_XO, 0 },
	241	+ { P_GPLL0_OUT_MAIN, 1 },
	242	+ { P_GPLL4_OUT_MAIN, 2 },
	243	+ { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
	244	+};
	245	+
	246	+static const struct clk_parent_data gcc_parent_data_7[] = {
	247	+ { .index = DT_XO },
	248	+ { .hw = &gpll0.clkr.hw },
	249	+ { .hw = &gpll4_main.clkr.hw },
	250	+ { .hw = &gpll0_div2.hw },
	251	+};
	252	+
	253	+static const struct parent_map gcc_parent_map_8[] = {
	254	+ { P_XO, 0 },
	255	+ { P_GPLL0_OUT_AUX, 2 },
	256	+ { P_SLEEP_CLK, 6 },
	257	+};
	258	+
	259	+static const struct clk_parent_data gcc_parent_data_8[] = {
	260	+ { .index = DT_XO },
	261	+ { .hw = &gpll0.clkr.hw },
	262	+ { .index = DT_SLEEP_CLK },
	263	+};
	264	+
	265	+static const struct parent_map gcc_parent_map_9[] = {
	266	+ { P_XO, 0 },
	267	+ { P_GPLL4_OUT_AUX, 1 },
	268	+ { P_GPLL0_OUT_MAIN, 3 },
	269	+ { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
	270	+};
	271	+
	272	+static const struct clk_parent_data gcc_parent_data_9[] = {
	273	+ { .index = DT_XO },
	274	+ { .hw = &gpll4_main.clkr.hw },
	275	+ { .hw = &gpll0.clkr.hw },
	276	+ { .hw = &gpll0_div2.hw },
	277	+};
	278	+
	279	+static const struct parent_map gcc_parent_map_10[] = {
	280	+ { P_XO, 0 },
	281	+ { P_GPLL4_OUT_MAIN, 1 },
	282	+ { P_GPLL0_OUT_AUX, 2 },
	283	+ { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
	284	+};
	285	+
	286	+static const struct clk_parent_data gcc_parent_data_10[] = {
	287	+ { .index = DT_XO },
	288	+ { .hw = &gpll4_main.clkr.hw },
	289	+ { .hw = &gpll0.clkr.hw },
	290	+ { .hw = &gpll0_div2.hw },
	291	+};
	292	+
	293	+static const struct parent_map gcc_parent_map_11[] = {
	294	+ { P_XO, 0 },
	295	+ { P_GPLL4_OUT_MAIN, 1 },
	296	+ { P_GPLL0_OUT_AUX, 2 },
	297	+ { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
	298	+};
	299	+
	300	+static const struct clk_parent_data gcc_parent_data_11[] = {
	301	+ { .index = DT_XO },
	302	+ { .hw = &gpll4_main.clkr.hw },
	303	+ { .hw = &gpll0.clkr.hw },
	304	+ { .hw = &gpll0_div2.hw },
	305	+};
	306	+
	307	+static const struct parent_map gcc_parent_map_12[] = {
	308	+ { P_XO, 0 },
	309	+ { P_GPLL0_OUT_MAIN, 1 },
	310	+ { P_GPLL2_OUT_AUX, 2 },
	311	+};
	312	+
	313	+static const struct clk_parent_data gcc_parent_data_12[] = {
	314	+ { .index = DT_XO },
	315	+ { .hw = &gpll0.clkr.hw },
	316	+ { .hw = &gpll2_main.clkr.hw },
	317	+};
	318	+
	319	+static const struct parent_map gcc_parent_map_13[] = {
	320	+ { P_SLEEP_CLK, 6 },
	321	+};
	322	+
	323	+static const struct clk_parent_data gcc_parent_data_13[] = {
	324	+ { .index = DT_SLEEP_CLK },
	325	+};
	326	+
	327	+static const struct freq_tbl ftbl_gcc_adss_pwm_clk_src[] = {
	328	+ F(24000000, P_XO, 1, 0, 0),
	329	+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
	330	+ { }
	331	+};
	332	+
	333	+static struct clk_rcg2 gcc_adss_pwm_clk_src = {
	334	+ .cmd_rcgr = 0x1c004,
	335	+ .mnd_width = 0,
	336	+ .hid_width = 5,
	337	+ .parent_map = gcc_parent_map_1,
	338	+ .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
	339	+ .clkr.hw.init = &(const struct clk_init_data) {
	340	+ .name = "gcc_adss_pwm_clk_src",
	341	+ .parent_data = gcc_parent_data_1,
	342	+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
	343	+ .ops = &clk_rcg2_ops,
	344	+ },
	345	+};
	346	+
	347	+static const struct freq_tbl ftbl_gcc_nss_ts_clk_src[] = {
	348	+ F(24000000, P_XO, 1, 0, 0),
	349	+ { }
	350	+};
	351	+
	352	+static struct clk_rcg2 gcc_nss_ts_clk_src = {
	353	+ .cmd_rcgr = 0x17088,
	354	+ .mnd_width = 0,
	355	+ .hid_width = 5,
	356	+ .parent_map = gcc_parent_map_3,
	357	+ .freq_tbl = ftbl_gcc_nss_ts_clk_src,
	358	+ .clkr.hw.init = &(const struct clk_init_data) {
	359	+ .name = "gcc_nss_ts_clk_src",
	360	+ .parent_data = gcc_parent_data_3,
	361	+ .num_parents = ARRAY_SIZE(gcc_parent_data_3),
	362	+ .ops = &clk_rcg2_ops,
	363	+ },
	364	+};
	365	+
	366	+static const struct freq_tbl ftbl_gcc_system_noc_bfdcd_clk_src[] = {
	367	+ F(24000000, P_XO, 1, 0, 0),
	368	+ F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
	369	+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
	370	+ F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
	371	+ { }
	372	+};
	373	+
	374	+static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = {
	375	+ .cmd_rcgr = 0x2e004,
	376	+ .freq_tbl = ftbl_gcc_system_noc_bfdcd_clk_src,
	377	+ .hid_width = 5,
	378	+ .parent_map = gcc_parent_map_7,
	379	+ .clkr.hw.init = &(const struct clk_init_data) {
	380	+ .name = "gcc_system_noc_bfdcd_clk_src",
	381	+ .parent_data = gcc_parent_data_7,
	382	+ .num_parents = ARRAY_SIZE(gcc_parent_data_7),
	383	+ .ops = &clk_rcg2_ops,
	384	+ },
	385	+};
	386	+
	387	+static const struct freq_tbl ftbl_gcc_nssnoc_memnoc_bfdcd_clk_src[] = {
	388	+ F(429000000, P_NSS_CMN_CLK, 1, 0, 0),
	389	+ { }
	390	+};
	391	+
	392	+static struct clk_rcg2 gcc_nssnoc_memnoc_bfdcd_clk_src = {
	393	+ .cmd_rcgr = 0x17004,
	394	+ .mnd_width = 0,
	395	+ .hid_width = 5,
	396	+ .parent_map = gcc_parent_map_4,
	397	+ .freq_tbl = ftbl_gcc_nssnoc_memnoc_bfdcd_clk_src,
	398	+ .clkr.hw.init = &(const struct clk_init_data) {
	399	+ .name = "gcc_nssnoc_memnoc_bfdcd_clk_src",
	400	+ .parent_data = gcc_parent_data_4,
	401	+ .num_parents = ARRAY_SIZE(gcc_parent_data_4),
	402	+ .ops = &clk_rcg2_ops,
	403	+ },
	404	+};
	405	+
	406	+static const struct freq_tbl ftbl_gcc_pcie0_axi_m_clk_src[] = {
	407	+ F(200000000, P_GPLL4_OUT_MAIN, 6, 0, 0),
	408	+ { }
	409	+};
	410	+
	411	+static struct clk_rcg2 gcc_pcie0_axi_m_clk_src = {
	412	+ .cmd_rcgr = 0x28018,
	413	+ .mnd_width = 0,
	414	+ .hid_width = 5,
	415	+ .parent_map = gcc_parent_map_2,
	416	+ .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src,
	417	+ .clkr.hw.init = &(const struct clk_init_data) {
	418	+ .name = "gcc_pcie0_axi_m_clk_src",
	419	+ .parent_data = gcc_parent_data_2,
	420	+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
	421	+ .ops = &clk_rcg2_ops,
	422	+ },
	423	+};
	424	+
	425	+static struct clk_rcg2 gcc_pcie0_axi_s_clk_src = {
	426	+ .cmd_rcgr = 0x28020,
	427	+ .mnd_width = 0,
	428	+ .hid_width = 5,
	429	+ .parent_map = gcc_parent_map_2,
	430	+ .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src,
	431	+ .clkr.hw.init = &(const struct clk_init_data) {
	432	+ .name = "gcc_pcie0_axi_s_clk_src",
	433	+ .parent_data = gcc_parent_data_2,
	434	+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
	435	+ .ops = &clk_rcg2_ops,
	436	+ },
	437	+};
	438	+
	439	+static struct clk_rcg2 gcc_pcie0_rchng_clk_src = {
	440	+ .cmd_rcgr = 0x28028,
	441	+ .mnd_width = 0,
	442	+ .hid_width = 5,
	443	+ .parent_map = gcc_parent_map_1,
	444	+ .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
	445	+ .clkr.hw.init = &(const struct clk_init_data) {
	446	+ .name = "gcc_pcie0_rchng_clk_src",
	447	+ .parent_data = gcc_parent_data_1,
	448	+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
	449	+ .ops = &clk_rcg2_ops,
	450	+ },
	451	+};
	452	+
	453	+static const struct freq_tbl ftbl_gcc_pcie1_axi_m_clk_src[] = {
	454	+ F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
	455	+ { }
	456	+};
	457	+
	458	+static struct clk_rcg2 gcc_pcie1_axi_m_clk_src = {
	459	+ .cmd_rcgr = 0x29018,
	460	+ .mnd_width = 0,
	461	+ .hid_width = 5,
	462	+ .parent_map = gcc_parent_map_2,
	463	+ .freq_tbl = ftbl_gcc_pcie1_axi_m_clk_src,
	464	+ .clkr.hw.init = &(const struct clk_init_data) {
	465	+ .name = "gcc_pcie1_axi_m_clk_src",
	466	+ .parent_data = gcc_parent_data_2,
	467	+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
	468	+ .ops = &clk_rcg2_ops,
	469	+ },
	470	+};
	471	+
	472	+static struct clk_rcg2 gcc_pcie1_axi_s_clk_src = {
	473	+ .cmd_rcgr = 0x29020,
	474	+ .mnd_width = 0,
	475	+ .hid_width = 5,
	476	+ .parent_map = gcc_parent_map_2,
	477	+ .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src,
	478	+ .clkr.hw.init = &(const struct clk_init_data) {
	479	+ .name = "gcc_pcie1_axi_s_clk_src",
	480	+ .parent_data = gcc_parent_data_2,
	481	+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
	482	+ .ops = &clk_rcg2_ops,
	483	+ },
	484	+};
	485	+
	486	+static struct clk_rcg2 gcc_pcie1_rchng_clk_src = {
	487	+ .cmd_rcgr = 0x29028,
	488	+ .mnd_width = 0,
	489	+ .hid_width = 5,
	490	+ .parent_map = gcc_parent_map_1,
	491	+ .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
	492	+ .clkr.hw.init = &(const struct clk_init_data) {
	493	+ .name = "gcc_pcie1_rchng_clk_src",
	494	+ .parent_data = gcc_parent_data_1,
	495	+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
	496	+ .ops = &clk_rcg2_ops,
	497	+ },
	498	+};
	499	+
	500	+static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] = {
	501	+ F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
	502	+ { }
	503	+};
	504	+
	505	+static struct clk_rcg2 gcc_pcie_aux_clk_src = {
	506	+ .cmd_rcgr = 0x28004,
	507	+ .mnd_width = 16,
	508	+ .hid_width = 5,
	509	+ .parent_map = gcc_parent_map_5,
	510	+ .freq_tbl = ftbl_gcc_pcie_aux_clk_src,
	511	+ .clkr.hw.init = &(const struct clk_init_data) {
	512	+ .name = "gcc_pcie_aux_clk_src",
	513	+ .parent_data = gcc_parent_data_5,
	514	+ .num_parents = ARRAY_SIZE(gcc_parent_data_5),
	515	+ .ops = &clk_rcg2_ops,
	516	+ },
	517	+};
	518	+
	519	+static const struct freq_tbl ftbl_gcc_qupv3_wrap_se0_clk_src[] = {
	520	+ F(960000, P_XO, 10, 2, 5),
	521	+ F(3686636, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 2, 217),
	522	+ F(4800000, P_XO, 5, 0, 0),
	523	+ F(7373272, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 4, 217),
	524	+ F(9600000, P_XO, 2.5, 0, 0),
	525	+ F(14746544, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 8, 217),
	526	+ F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
	527	+ F(24000000, P_XO, 1, 0, 0),
	528	+ F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
	529	+ F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),
	530	+ F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),
	531	+ F(46400000, P_GPLL0_OUT_MAIN, 2, 29, 250),
	532	+ F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),
	533	+ F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
	534	+ F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),
	535	+ F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),
	536	+ F(58986175, P_GPLL0_OUT_MAIN, 1, 16, 217),
	537	+ F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),
	538	+ F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
	539	+ { }
	540	+};
	541	+
	542	+static struct clk_rcg2 gcc_qupv3_wrap_se0_clk_src = {
	543	+ .cmd_rcgr = 0x4004,
	544	+ .mnd_width = 8,
	545	+ .hid_width = 5,
	546	+ .parent_map = gcc_parent_map_0,
	547	+ .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src,
	548	+ .clkr.hw.init = &(const struct clk_init_data) {
	549	+ .name = "gcc_qupv3_wrap_se0_clk_src",
	550	+ .parent_data = gcc_parent_data_0,
	551	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	552	+ .ops = &clk_rcg2_ops,
	553	+ },
	554	+};
	555	+
	556	+static struct clk_rcg2 gcc_qupv3_wrap_se1_clk_src = {
	557	+ .cmd_rcgr = 0x5004,
	558	+ .mnd_width = 8,
	559	+ .hid_width = 5,
	560	+ .parent_map = gcc_parent_map_0,
	561	+ .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src,
	562	+ .clkr.hw.init = &(const struct clk_init_data) {
	563	+ .name = "gcc_qupv3_wrap_se1_clk_src",
	564	+ .parent_data = gcc_parent_data_0,
	565	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	566	+ .ops = &clk_rcg2_ops,
	567	+ },
	568	+};
	569	+
	570	+static struct clk_rcg2 gcc_qupv3_wrap_se2_clk_src = {
	571	+ .cmd_rcgr = 0x2018,
	572	+ .mnd_width = 8,
	573	+ .hid_width = 5,
	574	+ .parent_map = gcc_parent_map_0,
	575	+ .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src,
	576	+ .clkr.hw.init = &(const struct clk_init_data) {
	577	+ .name = "gcc_qupv3_wrap_se2_clk_src",
	578	+ .parent_data = gcc_parent_data_0,
	579	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	580	+ .ops = &clk_rcg2_ops,
	581	+ },
	582	+};
	583	+
	584	+static struct clk_rcg2 gcc_qupv3_wrap_se3_clk_src = {
	585	+ .cmd_rcgr = 0x2034,
	586	+ .mnd_width = 8,
	587	+ .hid_width = 5,
	588	+ .parent_map = gcc_parent_map_0,
	589	+ .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src,
	590	+ .clkr.hw.init = &(const struct clk_init_data) {
	591	+ .name = "gcc_qupv3_wrap_se3_clk_src",
	592	+ .parent_data = gcc_parent_data_0,
	593	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	594	+ .ops = &clk_rcg2_ops,
	595	+ },
	596	+};
	597	+
	598	+static struct clk_rcg2 gcc_qupv3_wrap_se4_clk_src = {
	599	+ .cmd_rcgr = 0x3018,
	600	+ .mnd_width = 8,
	601	+ .hid_width = 5,
	602	+ .parent_map = gcc_parent_map_0,
	603	+ .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src,
	604	+ .clkr.hw.init = &(const struct clk_init_data) {
	605	+ .name = "gcc_qupv3_wrap_se4_clk_src",
	606	+ .parent_data = gcc_parent_data_0,
	607	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	608	+ .ops = &clk_rcg2_ops,
	609	+ },
	610	+};
	611	+
	612	+static struct clk_rcg2 gcc_qupv3_wrap_se5_clk_src = {
	613	+ .cmd_rcgr = 0x3034,
	614	+ .mnd_width = 8,
	615	+ .hid_width = 5,
	616	+ .parent_map = gcc_parent_map_0,
	617	+ .freq_tbl = ftbl_gcc_qupv3_wrap_se0_clk_src,
	618	+ .clkr.hw.init = &(const struct clk_init_data) {
	619	+ .name = "gcc_qupv3_wrap_se5_clk_src",
	620	+ .parent_data = gcc_parent_data_0,
	621	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	622	+ .ops = &clk_rcg2_ops,
	623	+ },
	624	+};
	625	+
	626	+static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
	627	+ F(144000, P_XO, 16, 12, 125),
	628	+ F(400000, P_XO, 12, 1, 5),
	629	+ F(24000000, P_GPLL2_OUT_MAIN, 12, 1, 2),
	630	+ F(48000000, P_GPLL2_OUT_MAIN, 12, 0, 0),
	631	+ F(96000000, P_GPLL2_OUT_MAIN, 6, 0, 0),
	632	+ F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
	633	+ F(192000000, P_GPLL2_OUT_MAIN, 3, 0, 0),
	634	+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
	635	+ { }
	636	+};
	637	+
	638	+static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
	639	+ .cmd_rcgr = 0x33004,
	640	+ .mnd_width = 8,
	641	+ .hid_width = 5,
	642	+ .parent_map = gcc_parent_map_6,
	643	+ .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
	644	+ .clkr.hw.init = &(const struct clk_init_data) {
	645	+ .name = "gcc_sdcc1_apps_clk_src",
	646	+ .parent_data = gcc_parent_data_6,
	647	+ .num_parents = ARRAY_SIZE(gcc_parent_data_6),
	648	+ .ops = &clk_rcg2_floor_ops,
	649	+ },
	650	+};
	651	+
	652	+static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
	653	+ F(300000000, P_GPLL4_OUT_MAIN, 4, 0, 0),
	654	+ { }
	655	+};
	656	+
	657	+static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
	658	+ .cmd_rcgr = 0x33018,
	659	+ .mnd_width = 8,
	660	+ .hid_width = 5,
	661	+ .parent_map = gcc_parent_map_7,
	662	+ .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
	663	+ .clkr.hw.init = &(const struct clk_init_data) {
	664	+ .name = "gcc_sdcc1_ice_core_clk_src",
	665	+ .parent_data = gcc_parent_data_7,
	666	+ .num_parents = ARRAY_SIZE(gcc_parent_data_7),
	667	+ .ops = &clk_rcg2_floor_ops,
	668	+ },
	669	+};
	670	+
	671	+static struct clk_rcg2 gcc_uniphy_sys_clk_src = {
	672	+ .cmd_rcgr = 0x17090,
	673	+ .mnd_width = 0,
	674	+ .hid_width = 5,
	675	+ .parent_map = gcc_parent_map_3,
	676	+ .freq_tbl = ftbl_gcc_nss_ts_clk_src,
	677	+ .clkr.hw.init = &(const struct clk_init_data) {
	678	+ .name = "gcc_uniphy_sys_clk_src",
	679	+ .parent_data = gcc_parent_data_3,
	680	+ .num_parents = ARRAY_SIZE(gcc_parent_data_3),
	681	+ .ops = &clk_rcg2_ops,
	682	+ },
	683	+};
	684	+
	685	+static struct clk_rcg2 gcc_usb0_aux_clk_src = {
	686	+ .cmd_rcgr = 0x2c018,
	687	+ .mnd_width = 16,
	688	+ .hid_width = 5,
	689	+ .parent_map = gcc_parent_map_8,
	690	+ .freq_tbl = ftbl_gcc_nss_ts_clk_src,
	691	+ .clkr.hw.init = &(const struct clk_init_data) {
	692	+ .name = "gcc_usb0_aux_clk_src",
	693	+ .parent_data = gcc_parent_data_8,
	694	+ .num_parents = ARRAY_SIZE(gcc_parent_data_8),
	695	+ .ops = &clk_rcg2_ops,
	696	+ },
	697	+};
	698	+
	699	+static const struct freq_tbl ftbl_gcc_usb0_master_clk_src[] = {
	700	+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
	701	+ { }
	702	+};
	703	+
	704	+static struct clk_rcg2 gcc_usb0_master_clk_src = {
	705	+ .cmd_rcgr = 0x2c004,
	706	+ .mnd_width = 8,
	707	+ .hid_width = 5,
	708	+ .parent_map = gcc_parent_map_0,
	709	+ .freq_tbl = ftbl_gcc_usb0_master_clk_src,
	710	+ .clkr.hw.init = &(const struct clk_init_data) {
	711	+ .name = "gcc_usb0_master_clk_src",
	712	+ .parent_data = gcc_parent_data_0,
	713	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	714	+ .ops = &clk_rcg2_ops,
	715	+ },
	716	+};
	717	+
	718	+static const struct freq_tbl ftbl_gcc_usb0_mock_utmi_clk_src[] = {
	719	+ F(60000000, P_GPLL4_OUT_AUX, 10, 1, 2),
	720	+ { }
	721	+};
	722	+
	723	+static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = {
	724	+ .cmd_rcgr = 0x2c02c,
	725	+ .mnd_width = 8,
	726	+ .hid_width = 5,
	727	+ .parent_map = gcc_parent_map_9,
	728	+ .freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src,
	729	+ .clkr.hw.init = &(const struct clk_init_data) {
	730	+ .name = "gcc_usb0_mock_utmi_clk_src",
	731	+ .parent_data = gcc_parent_data_9,
	732	+ .num_parents = ARRAY_SIZE(gcc_parent_data_9),
	733	+ .ops = &clk_rcg2_ops,
	734	+ },
	735	+};
	736	+
	737	+static const struct freq_tbl ftbl_gcc_qdss_at_clk_src[] = {
	738	+ F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
	739	+ { }
	740	+};
	741	+
	742	+static struct clk_rcg2 gcc_qdss_at_clk_src = {
	743	+ .cmd_rcgr = 0x2d004,
	744	+ .mnd_width = 0,
	745	+ .hid_width = 5,
	746	+ .parent_map = gcc_parent_map_10,
	747	+ .freq_tbl = ftbl_gcc_qdss_at_clk_src,
	748	+ .clkr.hw.init = &(const struct clk_init_data) {
	749	+ .name = "gcc_qdss_at_clk_src",
	750	+ .parent_data = gcc_parent_data_10,
	751	+ .num_parents = ARRAY_SIZE(gcc_parent_data_10),
	752	+ .ops = &clk_rcg2_ops,
	753	+ },
	754	+};
	755	+
	756	+static const struct freq_tbl ftbl_gcc_qdss_tsctr_clk_src[] = {
	757	+ F(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
	758	+ { }
	759	+};
	760	+
	761	+static struct clk_rcg2 gcc_qdss_tsctr_clk_src = {
	762	+ .cmd_rcgr = 0x2d01c,
	763	+ .mnd_width = 0,
	764	+ .hid_width = 5,
	765	+ .parent_map = gcc_parent_map_10,
	766	+ .freq_tbl = ftbl_gcc_qdss_tsctr_clk_src,
	767	+ .clkr.hw.init = &(const struct clk_init_data) {
	768	+ .name = "gcc_qdss_tsctr_clk_src",
	769	+ .parent_data = gcc_parent_data_10,
	770	+ .num_parents = ARRAY_SIZE(gcc_parent_data_10),
	771	+ .ops = &clk_rcg2_ops,
	772	+ },
	773	+};
	774	+
	775	+static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] = {
	776	+ F(24000000, P_XO, 1, 0, 0),
	777	+ F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
	778	+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
	779	+ { }
	780	+};
	781	+
	782	+static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src = {
	783	+ .cmd_rcgr = 0x31004,
	784	+ .mnd_width = 0,
	785	+ .hid_width = 5,
	786	+ .parent_map = gcc_parent_map_0,
	787	+ .freq_tbl = ftbl_gcc_pcnoc_bfdcd_clk_src,
	788	+ .clkr.hw.init = &(const struct clk_init_data) {
	789	+ .name = "gcc_pcnoc_bfdcd_clk_src",
	790	+ .parent_data = gcc_parent_data_0,
	791	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	792	+ .ops = &clk_rcg2_ops,
	793	+ /*
	794	+ * There are no consumers for this source in kernel yet,
	795	+ * (will be added soon), so the clock framework
	796	+ * disables this source. But some of the clocks
	797	+ * initialized by boot loaders uses this source. So we
	798	+ * need to keep this clock ON. Add the
	799	+ * CLK_IGNORE_UNUSED flag so the clock will not be
	800	+ * disabled. Once the consumer in kernel is added, we
	801	+ * can get rid of this flag.
	802	+ */
	803	+ .flags = CLK_IS_CRITICAL,
	804	+ },
	805	+};
	806	+
	807	+static const struct freq_tbl ftbl_gcc_qpic_io_macro_clk_src[] = {
	808	+ F(24000000, P_XO, 1, 0, 0),
	809	+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
	810	+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
	811	+ F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
	812	+ F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
	813	+ { }
	814	+};
	815	+
	816	+static struct clk_rcg2 gcc_qpic_io_macro_clk_src = {
	817	+ .cmd_rcgr = 0x32004,
	818	+ .mnd_width = 0,
	819	+ .hid_width = 5,
	820	+ .parent_map = gcc_parent_map_12,
	821	+ .freq_tbl = ftbl_gcc_qpic_io_macro_clk_src,
	822	+ .clkr.hw.init = &(const struct clk_init_data) {
	823	+ .name = "gcc_qpic_io_macro_clk_src",
	824	+ .parent_data = gcc_parent_data_12,
	825	+ .num_parents = ARRAY_SIZE(gcc_parent_data_12),
	826	+ .ops = &clk_rcg2_ops,
	827	+ },
	828	+};
	829	+
	830	+static const struct freq_tbl ftbl_gcc_qpic_clk_src[] = {
	831	+ F(24000000, P_XO, 1, 0, 0),
	832	+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
	833	+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
	834	+ { }
	835	+};
	836	+
	837	+static struct clk_rcg2 gcc_qpic_clk_src = {
	838	+ .cmd_rcgr = 0x32020,
	839	+ .mnd_width = 0,
	840	+ .hid_width = 5,
	841	+ .parent_map = gcc_parent_map_12,
	842	+ .freq_tbl = ftbl_gcc_qpic_clk_src,
	843	+ .clkr.hw.init = &(const struct clk_init_data) {
	844	+ .name = "gcc_qpic_clk_src",
	845	+ .parent_data = gcc_parent_data_12,
	846	+ .num_parents = ARRAY_SIZE(gcc_parent_data_12),
	847	+ .ops = &clk_rcg2_ops,
	848	+ },
	849	+};
	850	+
	851	+static const struct freq_tbl ftbl_gcc_pon_tm2x_clk_src[] = {
	852	+ F(342860000, P_GPLL4_OUT_MAIN, 3.5, 0, 0),
	853	+ { }
	854	+};
	855	+
	856	+static struct clk_rcg2 gcc_pon_tm2x_clk_src = {
	857	+ .cmd_rcgr = 0x3c004,
	858	+ .mnd_width = 0,
	859	+ .hid_width = 5,
	860	+ .parent_map = gcc_parent_map_11,
	861	+ .freq_tbl = ftbl_gcc_pon_tm2x_clk_src,
	862	+ .clkr.hw.init = &(const struct clk_init_data) {
	863	+ .name = "gcc_pon_tm2x_clk_src",
	864	+ .parent_data = gcc_parent_data_11,
	865	+ .num_parents = ARRAY_SIZE(gcc_parent_data_11),
	866	+ .ops = &clk_rcg2_ops,
	867	+ },
	868	+};
	869	+
	870	+static const struct freq_tbl ftbl_gcc_sleep_clk_src[] = {
	871	+ F(32000, P_SLEEP_CLK, 1, 0, 0),
	872	+ { }
	873	+};
	874	+
	875	+static struct clk_rcg2 gcc_sleep_clk_src = {
	876	+ .cmd_rcgr = 0x3400c,
	877	+ .mnd_width = 0,
	878	+ .hid_width = 5,
	879	+ .parent_map = gcc_parent_map_13,
	880	+ .freq_tbl = ftbl_gcc_sleep_clk_src,
	881	+ .clkr.hw.init = &(const struct clk_init_data) {
	882	+ .name = "gcc_sleep_clk_src",
	883	+ .parent_data = gcc_parent_data_13,
	884	+ .num_parents = ARRAY_SIZE(gcc_parent_data_13),
	885	+ .ops = &clk_rcg2_ops,
	886	+ },
	887	+};
	888	+
	889	+static const struct freq_tbl ftbl_gcc_lpass_sway_clk_src[] = {
	890	+ F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
	891	+ { }
	892	+};
	893	+
	894	+static struct clk_rcg2 gcc_lpass_sway_clk_src = {
	895	+ .cmd_rcgr = 0x27004,
	896	+ .mnd_width = 0,
	897	+ .hid_width = 5,
	898	+ .parent_map = gcc_parent_map_1,
	899	+ .freq_tbl = ftbl_gcc_lpass_sway_clk_src,
	900	+ .clkr.hw.init = &(const struct clk_init_data) {
	901	+ .name = "gcc_lpass_sway_clk_src",
	902	+ .parent_data = gcc_parent_data_1,
	903	+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
	904	+ .ops = &clk_rcg2_ops,
	905	+ },
	906	+};
	907	+
	908	+static struct clk_rcg2 gcc_lpass_axim_clk_src = {
	909	+ .cmd_rcgr = 0x2700c,
	910	+ .mnd_width = 0,
	911	+ .hid_width = 5,
	912	+ .parent_map = gcc_parent_map_1,
	913	+ .freq_tbl = ftbl_gcc_lpass_sway_clk_src,
	914	+ .clkr.hw.init = &(const struct clk_init_data) {
	915	+ .name = "gcc_lpass_axim_clk_src",
	916	+ .parent_data = gcc_parent_data_1,
	917	+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
	918	+ .ops = &clk_rcg2_ops,
	919	+ },
	920	+};
	921	+
	922	+static struct clk_regmap_div gcc_nssnoc_memnoc_div_clk_src = {
	923	+ .reg = 0x1700c,
	924	+ .shift = 0,
	925	+ .width = 4,
	926	+ .clkr.hw.init = &(const struct clk_init_data) {
	927	+ .name = "gcc_nssnoc_memnoc_div_clk_src",
	928	+ .parent_hws = (const struct clk_hw*[]) {
	929	+ &gcc_nssnoc_memnoc_bfdcd_clk_src.clkr.hw,
	930	+ },
	931	+ .num_parents = 1,
	932	+ .flags = CLK_SET_RATE_PARENT,
	933	+ .ops = &clk_regmap_div_ro_ops,
	934	+ },
	935	+};
	936	+
	937	+static struct clk_regmap_div gcc_usb0_mock_utmi_div_clk_src = {
	938	+ .reg = 0x2c040,
	939	+ .shift = 0,
	940	+ .width = 2,
	941	+ .clkr.hw.init = &(const struct clk_init_data) {
	942	+ .name = "gcc_usb0_mock_utmi_div_clk_src",
	943	+ .parent_hws = (const struct clk_hw*[]) {
	944	+ &gcc_usb0_mock_utmi_clk_src.clkr.hw,
	945	+ },
	946	+ .num_parents = 1,
	947	+ .flags = CLK_SET_RATE_PARENT,
	948	+ .ops = &clk_regmap_div_ro_ops,
	949	+ },
	950	+};
	951	+
	952	+static struct clk_fixed_factor gcc_pon_tm_div_clk_src = {
	953	+ .mult = 1,
	954	+ .div = 2,
	955	+ .hw.init = &(const struct clk_init_data) {
	956	+ .name = "gcc_pon_tm_div_clk_src",
	957	+ .parent_hws = (const struct clk_hw *[]) {
	958	+ &gcc_pon_tm2x_clk_src.clkr.hw
	959	+ },
	960	+ .num_parents = 1,
	961	+ .flags = CLK_SET_RATE_PARENT,
	962	+ .ops = &clk_fixed_factor_ops,
	963	+ },
	964	+};
	965	+
	966	+static struct clk_branch gcc_adss_pwm_clk = {
	967	+ .halt_reg = 0x1c00c,
	968	+ .halt_check = BRANCH_HALT,
	969	+ .clkr = {
	970	+ .enable_reg = 0x1c00c,
	971	+ .enable_mask = BIT(0),
	972	+ .hw.init = &(const struct clk_init_data) {
	973	+ .name = "gcc_adss_pwm_clk",
	974	+ .parent_hws = (const struct clk_hw*[]) {
	975	+ &gcc_adss_pwm_clk_src.clkr.hw,
	976	+ },
	977	+ .num_parents = 1,
	978	+ .flags = CLK_SET_RATE_PARENT,
	979	+ .ops = &clk_branch2_ops,
	980	+ },
	981	+ },
	982	+};
	983	+
	984	+static struct clk_branch gcc_cnoc_pcie0_1lane_s_clk = {
	985	+ .halt_reg = 0x31088,
	986	+ .halt_check = BRANCH_HALT,
	987	+ .clkr = {
	988	+ .enable_reg = 0x31088,
	989	+ .enable_mask = BIT(0),
	990	+ .hw.init = &(const struct clk_init_data) {
	991	+ .name = "gcc_cnoc_pcie0_1lane_s_clk",
	992	+ .parent_hws = (const struct clk_hw*[]) {
	993	+ &gcc_pcie0_axi_s_clk_src.clkr.hw,
	994	+ },
	995	+ .num_parents = 1,
	996	+ .flags = CLK_SET_RATE_PARENT,
	997	+ .ops = &clk_branch2_ops,
	998	+ },
	999	+ },
	1000	+};
	1001	+
	1002	+static struct clk_branch gcc_cnoc_pcie1_2lane_s_clk = {
	1003	+ .halt_reg = 0x3108c,
	1004	+ .halt_check = BRANCH_HALT,
	1005	+ .clkr = {
	1006	+ .enable_reg = 0x3108c,
	1007	+ .enable_mask = BIT(0),
	1008	+ .hw.init = &(const struct clk_init_data) {
	1009	+ .name = "gcc_cnoc_pcie1_2lane_s_clk",
	1010	+ .parent_hws = (const struct clk_hw*[]) {
	1011	+ &gcc_pcie1_axi_s_clk_src.clkr.hw,
	1012	+ },
	1013	+ .num_parents = 1,
	1014	+ .flags = CLK_SET_RATE_PARENT,
	1015	+ .ops = &clk_branch2_ops,
	1016	+ },
	1017	+ },
	1018	+};
	1019	+
	1020	+static struct clk_branch gcc_cnoc_usb_clk = {
	1021	+ .halt_reg = 0x310a8,
	1022	+ .halt_check = BRANCH_HALT,
	1023	+ .clkr = {
	1024	+ .enable_reg = 0x310a8,
	1025	+ .enable_mask = BIT(0),
	1026	+ .hw.init = &(const struct clk_init_data) {
	1027	+ .name = "gcc_cnoc_usb_clk",
	1028	+ .parent_hws = (const struct clk_hw*[]) {
	1029	+ &gcc_usb0_master_clk_src.clkr.hw,
	1030	+ },
	1031	+ .num_parents = 1,
	1032	+ .flags = CLK_SET_RATE_PARENT,
	1033	+ .ops = &clk_branch2_ops,
	1034	+ },
	1035	+ },
	1036	+};
	1037	+
	1038	+static struct clk_branch gcc_mdio_ahb_clk = {
	1039	+ .halt_reg = 0x17040,
	1040	+ .halt_check = BRANCH_HALT,
	1041	+ .clkr = {
	1042	+ .enable_reg = 0x17040,
	1043	+ .enable_mask = BIT(0),
	1044	+ .hw.init = &(const struct clk_init_data) {
	1045	+ .name = "gcc_mdio_ahb_clk",
	1046	+ .parent_hws = (const struct clk_hw*[]) {
	1047	+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
	1048	+ },
	1049	+ .num_parents = 1,
	1050	+ .flags = CLK_SET_RATE_PARENT,
	1051	+ .ops = &clk_branch2_ops,
	1052	+ },
	1053	+ },
	1054	+};
	1055	+
	1056	+static struct clk_branch gcc_mdio_gephy_ahb_clk = {
	1057	+ .halt_reg = 0x17098,
	1058	+ .halt_check = BRANCH_HALT,
	1059	+ .clkr = {
	1060	+ .enable_reg = 0x17098,
	1061	+ .enable_mask = BIT(0),
	1062	+ .hw.init = &(const struct clk_init_data) {
	1063	+ .name = "gcc_mdio_gephy_ahb_clk",
	1064	+ .parent_hws = (const struct clk_hw*[]) {
	1065	+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
	1066	+ },
	1067	+ .num_parents = 1,
	1068	+ .flags = CLK_SET_RATE_PARENT,
	1069	+ .ops = &clk_branch2_ops,
	1070	+ },
	1071	+ },
	1072	+};
	1073	+
	1074	+static struct clk_branch gcc_nss_ts_clk = {
	1075	+ .halt_reg = 0x17018,
	1076	+ .halt_check = BRANCH_HALT,
	1077	+ .clkr = {
	1078	+ .enable_reg = 0x17018,
	1079	+ .enable_mask = BIT(0),
	1080	+ .hw.init = &(const struct clk_init_data) {
	1081	+ .name = "gcc_nss_ts_clk",
	1082	+ .parent_hws = (const struct clk_hw*[]) {
	1083	+ &gcc_nss_ts_clk_src.clkr.hw,
	1084	+ },
	1085	+ .num_parents = 1,
	1086	+ .flags = CLK_SET_RATE_PARENT,
	1087	+ .ops = &clk_branch2_ops,
	1088	+ },
	1089	+ },
	1090	+};
	1091	+
	1092	+static struct clk_branch gcc_nsscc_clk = {
	1093	+ .halt_reg = 0x17034,
	1094	+ .halt_check = BRANCH_HALT,
	1095	+ .clkr = {
	1096	+ .enable_reg = 0x17034,
	1097	+ .enable_mask = BIT(0),
	1098	+ .hw.init = &(const struct clk_init_data) {
	1099	+ .name = "gcc_nsscc_clk",
	1100	+ .parent_hws = (const struct clk_hw*[]) {
	1101	+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
	1102	+ },
	1103	+ .num_parents = 1,
	1104	+ .flags = CLK_SET_RATE_PARENT,
	1105	+ .ops = &clk_branch2_ops,
	1106	+ },
	1107	+ },
	1108	+};
	1109	+
	1110	+static struct clk_branch gcc_nsscfg_clk = {
	1111	+ .halt_reg = 0x1702c,
	1112	+ .halt_check = BRANCH_HALT,
	1113	+ .clkr = {
	1114	+ .enable_reg = 0x1702c,
	1115	+ .enable_mask = BIT(0),
	1116	+ .hw.init = &(const struct clk_init_data) {
	1117	+ .name = "gcc_nsscfg_clk",
	1118	+ .parent_hws = (const struct clk_hw*[]) {
	1119	+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
	1120	+ },
	1121	+ .num_parents = 1,
	1122	+ .flags = CLK_SET_RATE_PARENT,
	1123	+ .ops = &clk_branch2_ops,
	1124	+ },
	1125	+ },
	1126	+};
	1127	+
	1128	+static struct clk_branch gcc_nssnoc_atb_clk = {
	1129	+ .halt_reg = 0x17014,
	1130	+ .halt_check = BRANCH_HALT,
	1131	+ .clkr = {
	1132	+ .enable_reg = 0x17014,
	1133	+ .enable_mask = BIT(0),
	1134	+ .hw.init = &(const struct clk_init_data) {
	1135	+ .name = "gcc_nssnoc_atb_clk",
	1136	+ .parent_hws = (const struct clk_hw*[]) {
	1137	+ &gcc_qdss_at_clk_src.clkr.hw,
	1138	+ },
	1139	+ .num_parents = 1,
	1140	+ .flags = CLK_SET_RATE_PARENT,
	1141	+ .ops = &clk_branch2_ops,
	1142	+ },
	1143	+ },
	1144	+};
	1145	+
	1146	+static struct clk_branch gcc_nssnoc_memnoc_1_clk = {
	1147	+ .halt_reg = 0x17084,
	1148	+ .halt_check = BRANCH_HALT,
	1149	+ .clkr = {
	1150	+ .enable_reg = 0x17084,
	1151	+ .enable_mask = BIT(0),
	1152	+ .hw.init = &(const struct clk_init_data) {
	1153	+ .name = "gcc_nssnoc_memnoc_1_clk",
	1154	+ .parent_hws = (const struct clk_hw*[]) {
	1155	+ &gcc_nssnoc_memnoc_div_clk_src.clkr.hw,
	1156	+ },
	1157	+ .num_parents = 1,
	1158	+ .flags = CLK_SET_RATE_PARENT,
	1159	+ .ops = &clk_branch2_ops,
	1160	+ },
	1161	+ },
	1162	+};
	1163	+
	1164	+static struct clk_branch gcc_nssnoc_memnoc_clk = {
	1165	+ .halt_reg = 0x17024,
	1166	+ .halt_check = BRANCH_HALT,
	1167	+ .clkr = {
	1168	+ .enable_reg = 0x17024,
	1169	+ .enable_mask = BIT(0),
	1170	+ .hw.init = &(const struct clk_init_data) {
	1171	+ .name = "gcc_nssnoc_memnoc_clk",
	1172	+ .parent_hws = (const struct clk_hw*[]) {
	1173	+ &gcc_nssnoc_memnoc_div_clk_src.clkr.hw,
	1174	+ },
	1175	+ .num_parents = 1,
	1176	+ .flags = CLK_SET_RATE_PARENT,
	1177	+ .ops = &clk_branch2_ops,
	1178	+ },
	1179	+ },
	1180	+};
	1181	+
	1182	+static struct clk_branch gcc_nssnoc_nsscc_clk = {
	1183	+ .halt_reg = 0x17030,
	1184	+ .halt_check = BRANCH_HALT,
	1185	+ .clkr = {
	1186	+ .enable_reg = 0x17030,
	1187	+ .enable_mask = BIT(0),
	1188	+ .hw.init = &(const struct clk_init_data) {
	1189	+ .name = "gcc_nssnoc_nsscc_clk",
	1190	+ .parent_hws = (const struct clk_hw*[]) {
	1191	+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
	1192	+ },
	1193	+ .num_parents = 1,
	1194	+ .flags = CLK_SET_RATE_PARENT,
	1195	+ .ops = &clk_branch2_ops,
	1196	+ },
	1197	+ },
	1198	+};
	1199	+
	1200	+static struct clk_rcg2 gcc_xo_clk_src = {
	1201	+ .cmd_rcgr = 0x34004,
	1202	+ .mnd_width = 0,
	1203	+ .hid_width = 5,
	1204	+ .parent_map = gcc_parent_map_xo,
	1205	+ .freq_tbl = ftbl_gcc_nss_ts_clk_src,
	1206	+ .clkr.hw.init = &(const struct clk_init_data) {
	1207	+ .name = "gcc_xo_clk_src",
	1208	+ .parent_data = &gcc_parent_data_xo,
	1209	+ .num_parents = 1,
	1210	+ .ops = &clk_rcg2_ops,
	1211	+ },
	1212	+};
	1213	+
	1214	+static struct clk_fixed_factor gcc_xo_div4_clk_src = {
	1215	+ .mult = 1,
	1216	+ .div = 4,
	1217	+ .hw.init = &(const struct clk_init_data) {
	1218	+ .name = "gcc_xo_div4_clk_src",
	1219	+ .parent_hws = (const struct clk_hw *[]) {
	1220	+ &gcc_xo_clk_src.clkr.hw
	1221	+ },
	1222	+ .num_parents = 1,
	1223	+ .flags = CLK_SET_RATE_PARENT,
	1224	+ .ops = &clk_fixed_factor_ops,
	1225	+ },
	1226	+};
	1227	+
	1228	+static struct clk_branch gcc_gephy_sys_clk = {
	1229	+ .halt_reg = 0x2a004,
	1230	+ .halt_check = BRANCH_HALT,
	1231	+ .clkr = {
	1232	+ .enable_reg = 0x2a004,
	1233	+ .enable_mask = BIT(0),
	1234	+ .hw.init = &(const struct clk_init_data) {
	1235	+ .name = "gcc_gephy_sys_clk",
	1236	+ .parent_hws = (const struct clk_hw*[]) {
	1237	+ &gcc_xo_clk_src.clkr.hw,
	1238	+ },
	1239	+ .num_parents = 1,
	1240	+ .flags = CLK_SET_RATE_PARENT,
	1241	+ .ops = &clk_branch2_ops,
	1242	+ },
	1243	+ },
	1244	+};
	1245	+
	1246	+static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {
	1247	+ .halt_reg = 0x17080,
	1248	+ .halt_check = BRANCH_HALT,
	1249	+ .clkr = {
	1250	+ .enable_reg = 0x17080,
	1251	+ .enable_mask = BIT(0),
	1252	+ .hw.init = &(const struct clk_init_data) {
	1253	+ .name = "gcc_nssnoc_pcnoc_1_clk",
	1254	+ .parent_hws = (const struct clk_hw*[]) {
	1255	+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw
	1256	+ },
	1257	+ .num_parents = 1,
	1258	+ .flags = CLK_SET_RATE_PARENT,
	1259	+ .ops = &clk_branch2_ops,
	1260	+ },
	1261	+ },
	1262	+};
	1263	+
	1264	+static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
	1265	+ .halt_reg = 0x1701c,
	1266	+ .halt_check = BRANCH_HALT,
	1267	+ .clkr = {
	1268	+ .enable_reg = 0x1701c,
	1269	+ .enable_mask = BIT(0),
	1270	+ .hw.init = &(const struct clk_init_data) {
	1271	+ .name = "gcc_nssnoc_qosgen_ref_clk",
	1272	+ .parent_hws = (const struct clk_hw *[]){
	1273	+ &gcc_xo_div4_clk_src.hw
	1274	+ },
	1275	+ .num_parents = 1,
	1276	+ .flags = CLK_SET_RATE_PARENT,
	1277	+ .ops = &clk_branch2_ops,
	1278	+ },
	1279	+ },
	1280	+};
	1281	+
	1282	+static struct clk_branch gcc_nssnoc_snoc_1_clk = {
	1283	+ .halt_reg = 0x1707c,
	1284	+ .halt_check = BRANCH_HALT,
	1285	+ .clkr = {
	1286	+ .enable_reg = 0x1707c,
	1287	+ .enable_mask = BIT(0),
	1288	+ .hw.init = &(const struct clk_init_data) {
	1289	+ .name = "gcc_nssnoc_snoc_1_clk",
	1290	+ .parent_hws = (const struct clk_hw*[]) {
	1291	+ &gcc_system_noc_bfdcd_clk_src.clkr.hw
	1292	+ },
	1293	+ .num_parents = 1,
	1294	+ .flags = CLK_SET_RATE_PARENT,
	1295	+ .ops = &clk_branch2_ops,
	1296	+ },
	1297	+ },
	1298	+};
	1299	+
	1300	+static struct clk_branch gcc_nssnoc_snoc_clk = {
	1301	+ .halt_reg = 0x17028,
	1302	+ .halt_check = BRANCH_HALT,
	1303	+ .clkr = {
	1304	+ .enable_reg = 0x17028,
	1305	+ .enable_mask = BIT(0),
	1306	+ .hw.init = &(const struct clk_init_data) {
	1307	+ .name = "gcc_nssnoc_snoc_clk",
	1308	+ .parent_hws = (const struct clk_hw*[]) {
	1309	+ &gcc_system_noc_bfdcd_clk_src.clkr.hw,
	1310	+ },
	1311	+ .num_parents = 1,
	1312	+ .flags = CLK_SET_RATE_PARENT,
	1313	+ .ops = &clk_branch2_ops,
	1314	+ },
	1315	+ },
	1316	+};
	1317	+
	1318	+static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
	1319	+ .halt_reg = 0x17020,
	1320	+ .halt_check = BRANCH_HALT,
	1321	+ .clkr = {
	1322	+ .enable_reg = 0x17020,
	1323	+ .enable_mask = BIT(0),
	1324	+ .hw.init = &(const struct clk_init_data) {
	1325	+ .name = "gcc_nssnoc_timeout_ref_clk",
	1326	+ .parent_hws = (const struct clk_hw*[]) {
	1327	+ &gcc_xo_div4_clk_src.hw,
	1328	+ },
	1329	+ .num_parents = 1,
	1330	+ .flags = CLK_SET_RATE_PARENT,
	1331	+ .ops = &clk_branch2_ops,
	1332	+ },
	1333	+ },
	1334	+};
	1335	+
	1336	+static struct clk_branch gcc_nssnoc_xo_dcd_clk = {
	1337	+ .halt_reg = 0x17074,
	1338	+ .halt_check = BRANCH_HALT,
	1339	+ .clkr = {
	1340	+ .enable_reg = 0x17074,
	1341	+ .enable_mask = BIT(0),
	1342	+ .hw.init = &(const struct clk_init_data) {
	1343	+ .name = "gcc_nssnoc_xo_dcd_clk",
	1344	+ .parent_hws = (const struct clk_hw*[]) {
	1345	+ &gcc_xo_clk_src.clkr.hw,
	1346	+ },
	1347	+ .num_parents = 1,
	1348	+ .flags = CLK_SET_RATE_PARENT,
	1349	+ .ops = &clk_branch2_ops,
	1350	+ },
	1351	+ },
	1352	+};
	1353	+
	1354	+static struct clk_branch gcc_pcie0_ahb_clk = {
	1355	+ .halt_reg = 0x28030,
	1356	+ .halt_check = BRANCH_HALT,
	1357	+ .clkr = {
	1358	+ .enable_reg = 0x28030,
	1359	+ .enable_mask = BIT(0),
	1360	+ .hw.init = &(const struct clk_init_data) {
	1361	+ .name = "gcc_pcie0_ahb_clk",
	1362	+ .parent_hws = (const struct clk_hw*[]) {
	1363	+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
	1364	+ },
	1365	+ .num_parents = 1,
	1366	+ .flags = CLK_SET_RATE_PARENT,
	1367	+ .ops = &clk_branch2_ops,
	1368	+ },
	1369	+ },
	1370	+};
	1371	+
	1372	+static struct clk_branch gcc_pcie0_aux_clk = {
	1373	+ .halt_reg = 0x28070,
	1374	+ .halt_check = BRANCH_HALT,
	1375	+ .clkr = {
	1376	+ .enable_reg = 0x28070,
	1377	+ .enable_mask = BIT(0),
	1378	+ .hw.init = &(const struct clk_init_data) {
	1379	+ .name = "gcc_pcie0_aux_clk",
	1380	+ .parent_hws = (const struct clk_hw*[]) {
	1381	+ &gcc_pcie_aux_clk_src.clkr.hw,
	1382	+ },
	1383	+ .num_parents = 1,
	1384	+ .flags = CLK_SET_RATE_PARENT,
	1385	+ .ops = &clk_branch2_ops,
	1386	+ },
	1387	+ },
	1388	+};
	1389	+
	1390	+static struct clk_branch gcc_pcie0_axi_m_clk = {
	1391	+ .halt_reg = 0x28038,
	1392	+ .halt_check = BRANCH_HALT,
	1393	+ .clkr = {
	1394	+ .enable_reg = 0x28038,
	1395	+ .enable_mask = BIT(0),
	1396	+ .hw.init = &(const struct clk_init_data) {
	1397	+ .name = "gcc_pcie0_axi_m_clk",
	1398	+ .parent_hws = (const struct clk_hw*[]) {
	1399	+ &gcc_pcie0_axi_m_clk_src.clkr.hw,
	1400	+ },
	1401	+ .num_parents = 1,
	1402	+ .flags = CLK_SET_RATE_PARENT,
	1403	+ .ops = &clk_branch2_ops,
	1404	+ },
	1405	+ },
	1406	+};
	1407	+
	1408	+static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
	1409	+ .halt_reg = 0x28048,
	1410	+ .halt_check = BRANCH_HALT,
	1411	+ .clkr = {
	1412	+ .enable_reg = 0x28048,
	1413	+ .enable_mask = BIT(0),
	1414	+ .hw.init = &(const struct clk_init_data) {
	1415	+ .name = "gcc_pcie0_axi_s_bridge_clk",
	1416	+ .parent_hws = (const struct clk_hw*[]) {
	1417	+ &gcc_pcie0_axi_s_clk_src.clkr.hw,
	1418	+ },
	1419	+ .num_parents = 1,
	1420	+ .flags = CLK_SET_RATE_PARENT,
	1421	+ .ops = &clk_branch2_ops,
	1422	+ },
	1423	+ },
	1424	+};
	1425	+
	1426	+static struct clk_branch gcc_pcie0_axi_s_clk = {
	1427	+ .halt_reg = 0x28040,
	1428	+ .halt_check = BRANCH_HALT,
	1429	+ .clkr = {
	1430	+ .enable_reg = 0x28040,
	1431	+ .enable_mask = BIT(0),
	1432	+ .hw.init = &(const struct clk_init_data) {
	1433	+ .name = "gcc_pcie0_axi_s_clk",
	1434	+ .parent_hws = (const struct clk_hw*[]) {
	1435	+ &gcc_pcie0_axi_s_clk_src.clkr.hw,
	1436	+ },
	1437	+ .num_parents = 1,
	1438	+ .flags = CLK_SET_RATE_PARENT,
	1439	+ .ops = &clk_branch2_ops,
	1440	+ },
	1441	+ },
	1442	+};
	1443	+
	1444	+static struct clk_regmap_phy_mux gcc_pcie0_pipe_clk_src = {
	1445	+ .reg = 0x28064,
	1446	+ .clkr = {
	1447	+ .hw.init = &(const struct clk_init_data) {
	1448	+ .name = "pcie0_pipe_clk_src",
	1449	+ .parent_data = &(const struct clk_parent_data) {
	1450	+ .index = DT_PCIE30_PHY0_PIPE_CLK,
	1451	+ },
	1452	+ .num_parents = 1,
	1453	+ .ops = &clk_regmap_phy_mux_ops,
	1454	+ },
	1455	+ },
	1456	+};
	1457	+
	1458	+static struct clk_branch gcc_pcie0_pipe_clk = {
	1459	+ .halt_reg = 0x28068,
	1460	+ .halt_check = BRANCH_HALT_DELAY,
	1461	+ .clkr = {
	1462	+ .enable_reg = 0x28068,
	1463	+ .enable_mask = BIT(0),
	1464	+ .hw.init = &(const struct clk_init_data) {
	1465	+ .name = "gcc_pcie0_pipe_clk",
	1466	+ .parent_hws = (const struct clk_hw *[]) {
	1467	+ &gcc_pcie0_pipe_clk_src.clkr.hw
	1468	+ },
	1469	+ .num_parents = 1,
	1470	+ .flags = CLK_SET_RATE_PARENT,
	1471	+ .ops = &clk_branch2_ops,
	1472	+ },
	1473	+ },
	1474	+};
	1475	+
	1476	+static struct clk_branch gcc_pcie1_ahb_clk = {
	1477	+ .halt_reg = 0x29030,
	1478	+ .halt_check = BRANCH_HALT,
	1479	+ .clkr = {
	1480	+ .enable_reg = 0x29030,
	1481	+ .enable_mask = BIT(0),
	1482	+ .hw.init = &(const struct clk_init_data) {
	1483	+ .name = "gcc_pcie1_ahb_clk",
	1484	+ .parent_hws = (const struct clk_hw*[]) {
	1485	+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
	1486	+ },
	1487	+ .num_parents = 1,
	1488	+ .flags = CLK_SET_RATE_PARENT,
	1489	+ .ops = &clk_branch2_ops,
	1490	+ },
	1491	+ },
	1492	+};
	1493	+
	1494	+static struct clk_branch gcc_pcie1_aux_clk = {
	1495	+ .halt_reg = 0x29074,
	1496	+ .halt_check = BRANCH_HALT,
	1497	+ .clkr = {
	1498	+ .enable_reg = 0x29074,
	1499	+ .enable_mask = BIT(0),
	1500	+ .hw.init = &(const struct clk_init_data) {
	1501	+ .name = "gcc_pcie1_aux_clk",
	1502	+ .parent_hws = (const struct clk_hw*[]) {
	1503	+ &gcc_pcie_aux_clk_src.clkr.hw,
	1504	+ },
	1505	+ .num_parents = 1,
	1506	+ .flags = CLK_SET_RATE_PARENT,
	1507	+ .ops = &clk_branch2_ops,
	1508	+ },
	1509	+ },
	1510	+};
	1511	+
	1512	+static struct clk_branch gcc_pcie1_axi_m_clk = {
	1513	+ .halt_reg = 0x29038,
	1514	+ .halt_check = BRANCH_HALT,
	1515	+ .clkr = {
	1516	+ .enable_reg = 0x29038,
	1517	+ .enable_mask = BIT(0),
	1518	+ .hw.init = &(const struct clk_init_data) {
	1519	+ .name = "gcc_pcie1_axi_m_clk",
	1520	+ .parent_hws = (const struct clk_hw*[]) {
	1521	+ &gcc_pcie1_axi_m_clk_src.clkr.hw,
	1522	+ },
	1523	+ .num_parents = 1,
	1524	+ .flags = CLK_SET_RATE_PARENT,
	1525	+ .ops = &clk_branch2_ops,
	1526	+ },
	1527	+ },
	1528	+};
	1529	+
	1530	+static struct clk_branch gcc_pcie1_axi_s_bridge_clk = {
	1531	+ .halt_reg = 0x29048,
	1532	+ .halt_check = BRANCH_HALT,
	1533	+ .clkr = {
	1534	+ .enable_reg = 0x29048,
	1535	+ .enable_mask = BIT(0),
	1536	+ .hw.init = &(const struct clk_init_data) {
	1537	+ .name = "gcc_pcie1_axi_s_bridge_clk",
	1538	+ .parent_hws = (const struct clk_hw*[]) {
	1539	+ &gcc_pcie1_axi_s_clk_src.clkr.hw,
	1540	+ },
	1541	+ .num_parents = 1,
	1542	+ .flags = CLK_SET_RATE_PARENT,
	1543	+ .ops = &clk_branch2_ops,
	1544	+ },
	1545	+ },
	1546	+};
	1547	+
	1548	+static struct clk_branch gcc_pcie1_axi_s_clk = {
	1549	+ .halt_reg = 0x29040,
	1550	+ .halt_check = BRANCH_HALT,
	1551	+ .clkr = {
	1552	+ .enable_reg = 0x29040,
	1553	+ .enable_mask = BIT(0),
	1554	+ .hw.init = &(const struct clk_init_data) {
	1555	+ .name = "gcc_pcie1_axi_s_clk",
	1556	+ .parent_hws = (const struct clk_hw*[]) {
	1557	+ &gcc_pcie1_axi_s_clk_src.clkr.hw,
	1558	+ },
	1559	+ .num_parents = 1,
	1560	+ .flags = CLK_SET_RATE_PARENT,
	1561	+ .ops = &clk_branch2_ops,
	1562	+ },
	1563	+ },
	1564	+};
	1565	+
	1566	+static struct clk_regmap_phy_mux gcc_pcie1_pipe_clk_src = {
	1567	+ .reg = 0x29064,
	1568	+ .clkr = {
	1569	+ .hw.init = &(const struct clk_init_data) {
	1570	+ .name = "pcie1_pipe_clk_src",
	1571	+ .parent_data = &(const struct clk_parent_data) {
	1572	+ .index = DT_PCIE30_PHY1_PIPE_CLK,
	1573	+ },
	1574	+ .num_parents = 1,
	1575	+ .ops = &clk_regmap_phy_mux_ops,
	1576	+ },
	1577	+ },
	1578	+};
	1579	+
	1580	+static struct clk_branch gcc_pcie1_pipe_clk = {
	1581	+ .halt_reg = 0x29068,
	1582	+ .halt_check = BRANCH_HALT_DELAY,
	1583	+ .clkr = {
	1584	+ .enable_reg = 0x29068,
	1585	+ .enable_mask = BIT(0),
	1586	+ .hw.init = &(const struct clk_init_data) {
	1587	+ .name = "gcc_pcie1_pipe_clk",
	1588	+ .parent_hws = (const struct clk_hw *[]) {
	1589	+ &gcc_pcie1_pipe_clk_src.clkr.hw
	1590	+ },
	1591	+ .num_parents = 1,
	1592	+ .flags = CLK_SET_RATE_PARENT,
	1593	+ .ops = &clk_branch2_ops,
	1594	+ },
	1595	+ },
	1596	+};
	1597	+
	1598	+static struct clk_branch gcc_qrng_ahb_clk = {
	1599	+ .halt_reg = 0x13024,
	1600	+ .halt_check = BRANCH_HALT_VOTED,
	1601	+ .clkr = {
	1602	+ .enable_reg = 0xb004,
	1603	+ .enable_mask = BIT(10),
	1604	+ .hw.init = &(const struct clk_init_data) {
	1605	+ .name = "gcc_qrng_ahb_clk",
	1606	+ .parent_hws = (const struct clk_hw*[]) {
	1607	+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
	1608	+ },
	1609	+ .num_parents = 1,
	1610	+ .flags = CLK_SET_RATE_PARENT,
	1611	+ .ops = &clk_branch2_ops,
	1612	+ },
	1613	+ },
	1614	+};
	1615	+
	1616	+static struct clk_branch gcc_qupv3_ahb_mst_clk = {
	1617	+ .halt_reg = 0x1014,
	1618	+ .halt_check = BRANCH_HALT_VOTED,
	1619	+ .clkr = {
	1620	+ .enable_reg = 0xb004,
	1621	+ .enable_mask = BIT(14),
	1622	+ .hw.init = &(const struct clk_init_data) {
	1623	+ .name = "gcc_qupv3_ahb_mst_clk",
	1624	+ .parent_hws = (const struct clk_hw*[]) {
	1625	+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
	1626	+ },
	1627	+ .num_parents = 1,
	1628	+ .flags = CLK_SET_RATE_PARENT,
	1629	+ .ops = &clk_branch2_ops,
	1630	+ },
	1631	+ },
	1632	+};
	1633	+
	1634	+static struct clk_branch gcc_qupv3_ahb_slv_clk = {
	1635	+ .halt_reg = 0x102c,
	1636	+ .halt_check = BRANCH_HALT_VOTED,
	1637	+ .clkr = {
	1638	+ .enable_reg = 0xb004,
	1639	+ .enable_mask = BIT(4),
	1640	+ .hw.init = &(const struct clk_init_data) {
	1641	+ .name = "gcc_qupv3_ahb_slv_clk",
	1642	+ .parent_hws = (const struct clk_hw*[]) {
	1643	+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
	1644	+ },
	1645	+ .num_parents = 1,
	1646	+ .flags = CLK_SET_RATE_PARENT,
	1647	+ .ops = &clk_branch2_ops,
	1648	+ },
	1649	+ },
	1650	+};
	1651	+
	1652	+static struct clk_branch gcc_qupv3_wrap_se0_clk = {
	1653	+ .halt_reg = 0x4020,
	1654	+ .halt_check = BRANCH_HALT,
	1655	+ .clkr = {
	1656	+ .enable_reg = 0x4020,
	1657	+ .enable_mask = BIT(0),
	1658	+ .hw.init = &(const struct clk_init_data) {
	1659	+ .name = "gcc_qupv3_wrap_se0_clk",
	1660	+ .parent_hws = (const struct clk_hw*[]) {
	1661	+ &gcc_qupv3_wrap_se0_clk_src.clkr.hw,
	1662	+ },
	1663	+ .num_parents = 1,
	1664	+ .flags = CLK_SET_RATE_PARENT,
	1665	+ .ops = &clk_branch2_ops,
	1666	+ },
	1667	+ },
	1668	+};
	1669	+
	1670	+static struct clk_branch gcc_qupv3_wrap_se1_clk = {
	1671	+ .halt_reg = 0x5020,
	1672	+ .halt_check = BRANCH_HALT,
	1673	+ .clkr = {
	1674	+ .enable_reg = 0x5020,
	1675	+ .enable_mask = BIT(0),
	1676	+ .hw.init = &(const struct clk_init_data) {
	1677	+ .name = "gcc_qupv3_wrap_se1_clk",
	1678	+ .parent_hws = (const struct clk_hw*[]) {
	1679	+ &gcc_qupv3_wrap_se1_clk_src.clkr.hw,
	1680	+ },
	1681	+ .num_parents = 1,
	1682	+ .flags = CLK_SET_RATE_PARENT,
	1683	+ .ops = &clk_branch2_ops,
	1684	+ },
	1685	+ },
	1686	+};
	1687	+
	1688	+static struct clk_branch gcc_qupv3_wrap_se2_clk = {
	1689	+ .halt_reg = 0x202c,
	1690	+ .halt_check = BRANCH_HALT,
	1691	+ .clkr = {
	1692	+ .enable_reg = 0x202c,
	1693	+ .enable_mask = BIT(0),
	1694	+ .hw.init = &(const struct clk_init_data) {
	1695	+ .name = "gcc_qupv3_wrap_se2_clk",
	1696	+ .parent_hws = (const struct clk_hw*[]) {
	1697	+ &gcc_qupv3_wrap_se2_clk_src.clkr.hw,
	1698	+ },
	1699	+ .num_parents = 1,
	1700	+ .flags = CLK_SET_RATE_PARENT,
	1701	+ .ops = &clk_branch2_ops,
	1702	+ },
	1703	+ },
	1704	+};
	1705	+
	1706	+static struct clk_branch gcc_qupv3_wrap_se3_clk = {
	1707	+ .halt_reg = 0x2048,
	1708	+ .halt_check = BRANCH_HALT,
	1709	+ .clkr = {
	1710	+ .enable_reg = 0x2048,
	1711	+ .enable_mask = BIT(0),
	1712	+ .hw.init = &(const struct clk_init_data) {
	1713	+ .name = "gcc_qupv3_wrap_se3_clk",
	1714	+ .parent_hws = (const struct clk_hw*[]) {
	1715	+ &gcc_qupv3_wrap_se3_clk_src.clkr.hw,
	1716	+ },
	1717	+ .num_parents = 1,
	1718	+ .flags = CLK_SET_RATE_PARENT,
	1719	+ .ops = &clk_branch2_ops,
	1720	+ },
	1721	+ },
	1722	+};
	1723	+
	1724	+static struct clk_branch gcc_qupv3_wrap_se4_clk = {
	1725	+ .halt_reg = 0x302c,
	1726	+ .halt_check = BRANCH_HALT,
	1727	+ .clkr = {
	1728	+ .enable_reg = 0x302c,
	1729	+ .enable_mask = BIT(0),
	1730	+ .hw.init = &(const struct clk_init_data) {
	1731	+ .name = "gcc_qupv3_wrap_se4_clk",
	1732	+ .parent_hws = (const struct clk_hw*[]) {
	1733	+ &gcc_qupv3_wrap_se4_clk_src.clkr.hw,
	1734	+ },
	1735	+ .num_parents = 1,
	1736	+ .flags = CLK_SET_RATE_PARENT,
	1737	+ .ops = &clk_branch2_ops,
	1738	+ },
	1739	+ },
	1740	+};
	1741	+
	1742	+static struct clk_branch gcc_qupv3_wrap_se5_clk = {
	1743	+ .halt_reg = 0x3048,
	1744	+ .halt_check = BRANCH_HALT,
	1745	+ .clkr = {
	1746	+ .enable_reg = 0x3048,
	1747	+ .enable_mask = BIT(0),
	1748	+ .hw.init = &(const struct clk_init_data) {
	1749	+ .name = "gcc_qupv3_wrap_se5_clk",
	1750	+ .parent_hws = (const struct clk_hw*[]) {
	1751	+ &gcc_qupv3_wrap_se5_clk_src.clkr.hw,
	1752	+ },
	1753	+ .num_parents = 1,
	1754	+ .flags = CLK_SET_RATE_PARENT,
	1755	+ .ops = &clk_branch2_ops,
	1756	+ },
	1757	+ },
	1758	+};
	1759	+
	1760	+static struct clk_branch gcc_sdcc1_ahb_clk = {
	1761	+ .halt_reg = 0x3303c,
	1762	+ .halt_check = BRANCH_HALT,
	1763	+ .clkr = {
	1764	+ .enable_reg = 0x3303c,
	1765	+ .enable_mask = BIT(0),
	1766	+ .hw.init = &(const struct clk_init_data) {
	1767	+ .name = "gcc_sdcc1_ahb_clk",
	1768	+ .parent_hws = (const struct clk_hw*[]) {
	1769	+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw
	1770	+ },
	1771	+ .num_parents = 1,
	1772	+ .flags = CLK_SET_RATE_PARENT,
	1773	+ .ops = &clk_branch2_ops,
	1774	+ },
	1775	+ },
	1776	+};
	1777	+
	1778	+static struct clk_branch gcc_sdcc1_apps_clk = {
	1779	+ .halt_reg = 0x3302c,
	1780	+ .halt_check = BRANCH_HALT,
	1781	+ .clkr = {
	1782	+ .enable_reg = 0x3302c,
	1783	+ .enable_mask = BIT(0),
	1784	+ .hw.init = &(const struct clk_init_data) {
	1785	+ .name = "gcc_sdcc1_apps_clk",
	1786	+ .parent_hws = (const struct clk_hw*[]) {
	1787	+ &gcc_sdcc1_apps_clk_src.clkr.hw,
	1788	+ },
	1789	+ .num_parents = 1,
	1790	+ .flags = CLK_SET_RATE_PARENT,
	1791	+ .ops = &clk_branch2_ops,
	1792	+ },
	1793	+ },
	1794	+};
	1795	+
	1796	+static struct clk_branch gcc_sdcc1_ice_core_clk = {
	1797	+ .halt_reg = 0x33034,
	1798	+ .halt_check = BRANCH_HALT,
	1799	+ .clkr = {
	1800	+ .enable_reg = 0x33034,
	1801	+ .enable_mask = BIT(0),
	1802	+ .hw.init = &(const struct clk_init_data) {
	1803	+ .name = "gcc_sdcc1_ice_core_clk",
	1804	+ .parent_hws = (const struct clk_hw*[]) {
	1805	+ &gcc_sdcc1_ice_core_clk_src.clkr.hw,
	1806	+ },
	1807	+ .num_parents = 1,
	1808	+ .flags = CLK_SET_RATE_PARENT,
	1809	+ .ops = &clk_branch2_ops,
	1810	+ },
	1811	+ },
	1812	+};
	1813	+
	1814	+static struct clk_branch gcc_snoc_pcie0_axi_m_clk = {
	1815	+ .halt_reg = 0x2e04c,
	1816	+ .halt_check = BRANCH_HALT,
	1817	+ .clkr = {
	1818	+ .enable_reg = 0x2e04c,
	1819	+ .enable_mask = BIT(0),
	1820	+ .hw.init = &(const struct clk_init_data) {
	1821	+ .name = "gcc_snoc_pcie0_axi_m_clk",
	1822	+ .parent_hws = (const struct clk_hw*[]) {
	1823	+ &gcc_pcie0_axi_m_clk_src.clkr.hw,
	1824	+ },
	1825	+ .num_parents = 1,
	1826	+ .flags = CLK_SET_RATE_PARENT,
	1827	+ .ops = &clk_branch2_ops,
	1828	+ },
	1829	+ },
	1830	+};
	1831	+
	1832	+static struct clk_branch gcc_snoc_pcie1_axi_m_clk = {
	1833	+ .halt_reg = 0x2e050,
	1834	+ .halt_check = BRANCH_HALT,
	1835	+ .clkr = {
	1836	+ .enable_reg = 0x2e050,
	1837	+ .enable_mask = BIT(0),
	1838	+ .hw.init = &(const struct clk_init_data) {
	1839	+ .name = "gcc_snoc_pcie1_axi_m_clk",
	1840	+ .parent_hws = (const struct clk_hw*[]) {
	1841	+ &gcc_pcie1_axi_m_clk_src.clkr.hw,
	1842	+ },
	1843	+ .num_parents = 1,
	1844	+ .flags = CLK_SET_RATE_PARENT,
	1845	+ .ops = &clk_branch2_ops,
	1846	+ },
	1847	+ },
	1848	+};
	1849	+
	1850	+static struct clk_branch gcc_uniphy0_ahb_clk = {
	1851	+ .halt_reg = 0x1704c,
	1852	+ .halt_check = BRANCH_HALT,
	1853	+ .clkr = {
	1854	+ .enable_reg = 0x1704c,
	1855	+ .enable_mask = BIT(0),
	1856	+ .hw.init = &(const struct clk_init_data) {
	1857	+ .name = "gcc_uniphy0_ahb_clk",
	1858	+ .parent_hws = (const struct clk_hw*[]) {
	1859	+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
	1860	+ },
	1861	+ .num_parents = 1,
	1862	+ .flags = CLK_SET_RATE_PARENT,
	1863	+ .ops = &clk_branch2_ops,
	1864	+ },
	1865	+ },
	1866	+};
	1867	+
	1868	+static struct clk_branch gcc_uniphy0_sys_clk = {
	1869	+ .halt_reg = 0x17048,
	1870	+ .halt_check = BRANCH_HALT,
	1871	+ .clkr = {
	1872	+ .enable_reg = 0x17048,
	1873	+ .enable_mask = BIT(0),
	1874	+ .hw.init = &(const struct clk_init_data) {
	1875	+ .name = "gcc_uniphy0_sys_clk",
	1876	+ .parent_hws = (const struct clk_hw*[]) {
	1877	+ &gcc_uniphy_sys_clk_src.clkr.hw,
	1878	+ },
	1879	+ .num_parents = 1,
	1880	+ .flags = CLK_SET_RATE_PARENT,
	1881	+ .ops = &clk_branch2_ops,
	1882	+ },
	1883	+ },
	1884	+};
	1885	+
	1886	+static struct clk_branch gcc_uniphy1_ahb_clk = {
	1887	+ .halt_reg = 0x1705c,
	1888	+ .halt_check = BRANCH_HALT,
	1889	+ .clkr = {
	1890	+ .enable_reg = 0x1705c,
	1891	+ .enable_mask = BIT(0),
	1892	+ .hw.init = &(const struct clk_init_data) {
	1893	+ .name = "gcc_uniphy1_ahb_clk",
	1894	+ .parent_hws = (const struct clk_hw*[]) {
	1895	+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
	1896	+ },
	1897	+ .num_parents = 1,
	1898	+ .flags = CLK_SET_RATE_PARENT,
	1899	+ .ops = &clk_branch2_ops,
	1900	+ },
	1901	+ },
	1902	+};
	1903	+
	1904	+static struct clk_branch gcc_uniphy1_sys_clk = {
	1905	+ .halt_reg = 0x17058,
	1906	+ .halt_check = BRANCH_HALT,
	1907	+ .clkr = {
	1908	+ .enable_reg = 0x17058,
	1909	+ .enable_mask = BIT(0),
	1910	+ .hw.init = &(const struct clk_init_data) {
	1911	+ .name = "gcc_uniphy1_sys_clk",
	1912	+ .parent_hws = (const struct clk_hw*[]) {
	1913	+ &gcc_uniphy_sys_clk_src.clkr.hw,
	1914	+ },
	1915	+ .num_parents = 1,
	1916	+ .flags = CLK_SET_RATE_PARENT,
	1917	+ .ops = &clk_branch2_ops,
	1918	+ },
	1919	+ },
	1920	+};
	1921	+
	1922	+static struct clk_branch gcc_uniphy2_ahb_clk = {
	1923	+ .halt_reg = 0x1706c,
	1924	+ .halt_check = BRANCH_HALT,
	1925	+ .clkr = {
	1926	+ .enable_reg = 0x1706c,
	1927	+ .enable_mask = BIT(0),
	1928	+ .hw.init = &(const struct clk_init_data) {
	1929	+ .name = "gcc_uniphy2_ahb_clk",
	1930	+ .parent_hws = (const struct clk_hw*[]) {
	1931	+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
	1932	+ },
	1933	+ .num_parents = 1,
	1934	+ .flags = CLK_SET_RATE_PARENT,
	1935	+ .ops = &clk_branch2_ops,
	1936	+ },
	1937	+ },
	1938	+};
	1939	+
	1940	+static struct clk_branch gcc_uniphy2_sys_clk = {
	1941	+ .halt_reg = 0x17068,
	1942	+ .halt_check = BRANCH_HALT,
	1943	+ .clkr = {
	1944	+ .enable_reg = 0x17068,
	1945	+ .enable_mask = BIT(0),
	1946	+ .hw.init = &(const struct clk_init_data) {
	1947	+ .name = "gcc_uniphy2_sys_clk",
	1948	+ .parent_hws = (const struct clk_hw*[]) {
	1949	+ &gcc_uniphy_sys_clk_src.clkr.hw,
	1950	+ },
	1951	+ .num_parents = 1,
	1952	+ .flags = CLK_SET_RATE_PARENT,
	1953	+ .ops = &clk_branch2_ops,
	1954	+ },
	1955	+ },
	1956	+};
	1957	+
	1958	+static struct clk_branch gcc_usb0_aux_clk = {
	1959	+ .halt_reg = 0x2c04c,
	1960	+ .halt_check = BRANCH_HALT,
	1961	+ .clkr = {
	1962	+ .enable_reg = 0x2c04c,
	1963	+ .enable_mask = BIT(0),
	1964	+ .hw.init = &(const struct clk_init_data) {
	1965	+ .name = "gcc_usb0_aux_clk",
	1966	+ .parent_hws = (const struct clk_hw*[]) {
	1967	+ &gcc_usb0_aux_clk_src.clkr.hw,
	1968	+ },
	1969	+ .num_parents = 1,
	1970	+ .flags = CLK_SET_RATE_PARENT,
	1971	+ .ops = &clk_branch2_ops,
	1972	+ },
	1973	+ },
	1974	+};
	1975	+
	1976	+static struct clk_branch gcc_usb0_master_clk = {
	1977	+ .halt_reg = 0x2c044,
	1978	+ .halt_check = BRANCH_HALT,
	1979	+ .clkr = {
	1980	+ .enable_reg = 0x2c044,
	1981	+ .enable_mask = BIT(0),
	1982	+ .hw.init = &(const struct clk_init_data) {
	1983	+ .name = "gcc_usb0_master_clk",
	1984	+ .parent_hws = (const struct clk_hw*[]) {
	1985	+ &gcc_usb0_master_clk_src.clkr.hw,
	1986	+ },
	1987	+ .num_parents = 1,
	1988	+ .flags = CLK_SET_RATE_PARENT,
	1989	+ .ops = &clk_branch2_ops,
	1990	+ },
	1991	+ },
	1992	+};
	1993	+
	1994	+static struct clk_branch gcc_usb0_mock_utmi_clk = {
	1995	+ .halt_reg = 0x2c050,
	1996	+ .halt_check = BRANCH_HALT,
	1997	+ .clkr = {
	1998	+ .enable_reg = 0x2c050,
	1999	+ .enable_mask = BIT(0),
	2000	+ .hw.init = &(const struct clk_init_data) {
	2001	+ .name = "gcc_usb0_mock_utmi_clk",
	2002	+ .parent_hws = (const struct clk_hw*[]) {
	2003	+ &gcc_usb0_mock_utmi_div_clk_src.clkr.hw,
	2004	+ },
	2005	+ .num_parents = 1,
	2006	+ .flags = CLK_SET_RATE_PARENT,
	2007	+ .ops = &clk_branch2_ops,
	2008	+ },
	2009	+ },
	2010	+};
	2011	+
	2012	+static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
	2013	+ .halt_reg = 0x2c05c,
	2014	+ .halt_check = BRANCH_HALT,
	2015	+ .clkr = {
	2016	+ .enable_reg = 0x2c05c,
	2017	+ .enable_mask = BIT(0),
	2018	+ .hw.init = &(const struct clk_init_data) {
	2019	+ .name = "gcc_usb0_phy_cfg_ahb_clk",
	2020	+ .parent_hws = (const struct clk_hw*[]) {
	2021	+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
	2022	+ },
	2023	+ .num_parents = 1,
	2024	+ .flags = CLK_SET_RATE_PARENT,
	2025	+ .ops = &clk_branch2_ops,
	2026	+ },
	2027	+ },
	2028	+};
	2029	+
	2030	+static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = {
	2031	+ .reg = 0x2c074,
	2032	+ .clkr = {
	2033	+ .hw.init = &(const struct clk_init_data) {
	2034	+ .name = "gcc_usb0_pipe_clk_src",
	2035	+ .parent_data = &(const struct clk_parent_data) {
	2036	+ .index = DT_USB3_PHY0_CC_PIPE_CLK,
	2037	+ },
	2038	+ .num_parents = 1,
	2039	+ .ops = &clk_regmap_phy_mux_ops,
	2040	+ },
	2041	+ },
	2042	+};
	2043	+
	2044	+static struct clk_branch gcc_usb0_pipe_clk = {
	2045	+ .halt_reg = 0x2c054,
	2046	+ .halt_check = BRANCH_HALT_DELAY,
	2047	+ .clkr = {
	2048	+ .enable_reg = 0x2c054,
	2049	+ .enable_mask = BIT(0),
	2050	+ .hw.init = &(const struct clk_init_data) {
	2051	+ .name = "gcc_usb0_pipe_clk",
	2052	+ .parent_hws = (const struct clk_hw *[]) {
	2053	+ &gcc_usb0_pipe_clk_src.clkr.hw
	2054	+ },
	2055	+ .num_parents = 1,
	2056	+ .flags = CLK_SET_RATE_PARENT,
	2057	+ .ops = &clk_branch2_ops,
	2058	+ },
	2059	+ },
	2060	+};
	2061	+
	2062	+static struct clk_branch gcc_usb0_sleep_clk = {
	2063	+ .halt_reg = 0x2c058,
	2064	+ .halt_check = BRANCH_HALT,
	2065	+ .clkr = {
	2066	+ .enable_reg = 0x2c058,
	2067	+ .enable_mask = BIT(0),
	2068	+ .hw.init = &(const struct clk_init_data) {
	2069	+ .name = "gcc_usb0_sleep_clk",
	2070	+ .parent_hws = (const struct clk_hw*[]) {
	2071	+ &gcc_sleep_clk_src.clkr.hw,
	2072	+ },
	2073	+ .num_parents = 1,
	2074	+ .flags = CLK_SET_RATE_PARENT,
	2075	+ .ops = &clk_branch2_ops,
	2076	+ },
	2077	+ },
	2078	+};
	2079	+
	2080	+static struct clk_branch gcc_pcie0_rchng_clk = {
	2081	+ .halt_reg = 0x28028,
	2082	+ .halt_check = BRANCH_HALT,
	2083	+ .clkr = {
	2084	+ .enable_reg = 0x28028,
	2085	+ .enable_mask = BIT(1),
	2086	+ .hw.init = &(const struct clk_init_data) {
	2087	+ .name = "gcc_pcie0_rchng_clk",
	2088	+ .parent_hws = (const struct clk_hw *[]) {
	2089	+ &gcc_pcie0_rchng_clk_src.clkr.hw
	2090	+ },
	2091	+ .num_parents = 1,
	2092	+ .flags = CLK_SET_RATE_PARENT,
	2093	+ .ops = &clk_branch2_ops,
	2094	+ },
	2095	+ },
	2096	+};
	2097	+
	2098	+static struct clk_branch gcc_pcie1_rchng_clk = {
	2099	+ .halt_reg = 0x29028,
	2100	+ .halt_check = BRANCH_HALT,
	2101	+ .clkr = {
	2102	+ .enable_reg = 0x29028,
	2103	+ .enable_mask = BIT(1),
	2104	+ .hw.init = &(const struct clk_init_data) {
	2105	+ .name = "gcc_pcie1_rchng_clk",
	2106	+ .parent_hws = (const struct clk_hw *[]) {
	2107	+ &gcc_pcie1_rchng_clk_src.clkr.hw
	2108	+ },
	2109	+ .num_parents = 1,
	2110	+ .flags = CLK_SET_RATE_PARENT,
	2111	+ .ops = &clk_branch2_ops,
	2112	+ },
	2113	+ },
	2114	+};
	2115	+
	2116	+static struct clk_branch gcc_qpic_ahb_clk = {
	2117	+ .halt_reg = 0x32010,
	2118	+ .halt_check = BRANCH_HALT,
	2119	+ .clkr = {
	2120	+ .enable_reg = 0x32010,
	2121	+ .enable_mask = BIT(0),
	2122	+ .hw.init = &(const struct clk_init_data) {
	2123	+ .name = "gcc_qpic_ahb_clk",
	2124	+ .parent_hws = (const struct clk_hw*[]) {
	2125	+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
	2126	+ },
	2127	+ .num_parents = 1,
	2128	+ .flags = CLK_SET_RATE_PARENT,
	2129	+ .ops = &clk_branch2_ops,
	2130	+ },
	2131	+ },
	2132	+};
	2133	+
	2134	+static struct clk_branch gcc_qpic_clk = {
	2135	+ .halt_reg = 0x32028,
	2136	+ .halt_check = BRANCH_HALT,
	2137	+ .clkr = {
	2138	+ .enable_reg = 0x32028,
	2139	+ .enable_mask = BIT(0),
	2140	+ .hw.init = &(const struct clk_init_data) {
	2141	+ .name = "gcc_qpic_clk",
	2142	+ .parent_hws = (const struct clk_hw*[]) {
	2143	+ &gcc_qpic_clk_src.clkr.hw,
	2144	+ },
	2145	+ .num_parents = 1,
	2146	+ .flags = CLK_SET_RATE_PARENT,
	2147	+ .ops = &clk_branch2_ops,
	2148	+ },
	2149	+ },
	2150	+};
	2151	+
	2152	+static struct clk_branch gcc_qpic_io_macro_clk = {
	2153	+ .halt_reg = 0x3200c,
	2154	+ .halt_check = BRANCH_HALT,
	2155	+ .clkr = {
	2156	+ .enable_reg = 0x3200c,
	2157	+ .enable_mask = BIT(0),
	2158	+ .hw.init = &(const struct clk_init_data) {
	2159	+ .name = "gcc_qpic_io_macro_clk",
	2160	+ .parent_hws = (const struct clk_hw*[]) {
	2161	+ &gcc_qpic_io_macro_clk_src.clkr.hw,
	2162	+ },
	2163	+ .num_parents = 1,
	2164	+ .flags = CLK_SET_RATE_PARENT,
	2165	+ .ops = &clk_branch2_ops,
	2166	+ },
	2167	+ },
	2168	+};
	2169	+
	2170	+static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
	2171	+ .halt_reg = 0x3a004,
	2172	+ .halt_check = BRANCH_HALT,
	2173	+ .clkr = {
	2174	+ .enable_reg = 0x3a004,
	2175	+ .enable_mask = BIT(0),
	2176	+ .hw.init = &(const struct clk_init_data) {
	2177	+ .name = "gcc_cmn_12gpll_ahb_clk",
	2178	+ .parent_hws = (const struct clk_hw*[]) {
	2179	+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
	2180	+ },
	2181	+ .num_parents = 1,
	2182	+ .flags = CLK_SET_RATE_PARENT,
	2183	+ .ops = &clk_branch2_ops,
	2184	+ },
	2185	+ },
	2186	+};
	2187	+
	2188	+static struct clk_branch gcc_cmn_12gpll_sys_clk = {
	2189	+ .halt_reg = 0x3a008,
	2190	+ .halt_check = BRANCH_HALT,
	2191	+ .clkr = {
	2192	+ .enable_reg = 0x3a008,
	2193	+ .enable_mask = BIT(0),
	2194	+ .hw.init = &(const struct clk_init_data) {
	2195	+ .name = "gcc_cmn_12gpll_sys_clk",
	2196	+ .parent_hws = (const struct clk_hw*[]) {
	2197	+ &gcc_uniphy_sys_clk_src.clkr.hw,
	2198	+ },
	2199	+ .num_parents = 1,
	2200	+ .flags = CLK_SET_RATE_PARENT,
	2201	+ .ops = &clk_branch2_ops,
	2202	+ },
	2203	+ },
	2204	+};
	2205	+
	2206	+static struct clk_branch gcc_qdss_at_clk = {
	2207	+ .halt_reg = 0x2d034,
	2208	+ .halt_check = BRANCH_HALT,
	2209	+ .clkr = {
	2210	+ .enable_reg = 0x2d034,
	2211	+ .enable_mask = BIT(0),
	2212	+ .hw.init = &(const struct clk_init_data) {
	2213	+ .name = "gcc_qdss_at_clk",
	2214	+ .parent_hws = (const struct clk_hw*[]) {
	2215	+ &gcc_qdss_at_clk_src.clkr.hw,
	2216	+ },
	2217	+ .num_parents = 1,
	2218	+ .flags = CLK_SET_RATE_PARENT,
	2219	+ .ops = &clk_branch2_ops,
	2220	+ },
	2221	+ },
	2222	+};
	2223	+
	2224	+static struct clk_branch gcc_qdss_dap_clk = {
	2225	+ .halt_reg = 0x2d058,
	2226	+ .halt_check = BRANCH_HALT_VOTED,
	2227	+ .clkr = {
	2228	+ .enable_reg = 0xb004,
	2229	+ .enable_mask = BIT(2),
	2230	+ .hw.init = &(const struct clk_init_data) {
	2231	+ .name = "gcc_qdss_dap_clk",
	2232	+ .parent_hws = (const struct clk_hw*[]) {
	2233	+ &gcc_qdss_tsctr_clk_src.clkr.hw,
	2234	+ },
	2235	+ .num_parents = 1,
	2236	+ .flags = CLK_SET_RATE_PARENT,
	2237	+ .ops = &clk_branch2_ops,
	2238	+ },
	2239	+ },
	2240	+};
	2241	+
	2242	+static struct clk_branch gcc_pon_apb_clk = {
	2243	+ .halt_reg = 0x3c01c,
	2244	+ .halt_check = BRANCH_HALT,
	2245	+ .clkr = {
	2246	+ .enable_reg = 0x3c01c,
	2247	+ .enable_mask = BIT(0),
	2248	+ .hw.init = &(const struct clk_init_data) {
	2249	+ .name = "gcc_pon_apb_clk",
	2250	+ .parent_hws = (const struct clk_hw*[]) {
	2251	+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
	2252	+ },
	2253	+ .num_parents = 1,
	2254	+ .flags = CLK_SET_RATE_PARENT,
	2255	+ .ops = &clk_branch2_ops,
	2256	+ },
	2257	+ },
	2258	+};
	2259	+
	2260	+static struct clk_branch gcc_pon_tm_clk = {
	2261	+ .halt_reg = 0x3c014,
	2262	+ .halt_check = BRANCH_HALT,
	2263	+ .clkr = {
	2264	+ .enable_reg = 0x3c014,
	2265	+ .enable_mask = BIT(0),
	2266	+ .hw.init = &(const struct clk_init_data) {
	2267	+ .name = "gcc_pon_tm_clk",
	2268	+ .parent_hws = (const struct clk_hw*[]) {
	2269	+ &gcc_pon_tm_div_clk_src.hw,
	2270	+ },
	2271	+ .num_parents = 1,
	2272	+ .flags = CLK_SET_RATE_PARENT,
	2273	+ .ops = &clk_branch2_ops,
	2274	+ },
	2275	+ },
	2276	+};
	2277	+
	2278	+static struct clk_branch gcc_pon_tm2x_clk = {
	2279	+ .halt_reg = 0x3c00c,
	2280	+ .halt_check = BRANCH_HALT,
	2281	+ .clkr = {
	2282	+ .enable_reg = 0x3c00c,
	2283	+ .enable_mask = BIT(0),
	2284	+ .hw.init = &(const struct clk_init_data) {
	2285	+ .name = "gcc_pon_tm2x_clk",
	2286	+ .parent_hws = (const struct clk_hw*[]) {
	2287	+ &gcc_pon_tm2x_clk_src.clkr.hw,
	2288	+ },
	2289	+ .num_parents = 1,
	2290	+ .flags = CLK_SET_RATE_PARENT,
	2291	+ .ops = &clk_branch2_ops,
	2292	+ },
	2293	+ },
	2294	+};
	2295	+
	2296	+static struct clk_branch gcc_snoc_lpass_clk = {
	2297	+ .halt_reg = 0x2e028,
	2298	+ .halt_check = BRANCH_HALT,
	2299	+ .clkr = {
	2300	+ .enable_reg = 0x2e028,
	2301	+ .enable_mask = BIT(0),
	2302	+ .hw.init = &(const struct clk_init_data) {
	2303	+ .name = "gcc_snoc_lpass_clk",
	2304	+ .parent_hws = (const struct clk_hw*[]) {
	2305	+ &gcc_lpass_axim_clk_src.clkr.hw,
	2306	+ },
	2307	+ .num_parents = 1,
	2308	+ .flags = CLK_SET_RATE_PARENT,
	2309	+ .ops = &clk_branch2_ops,
	2310	+ },
	2311	+ },
	2312	+};
	2313	+
	2314	+static struct clk_branch gcc_lpass_sway_clk = {
	2315	+ .halt_reg = 0x27014,
	2316	+ .halt_check = BRANCH_HALT,
	2317	+ .clkr = {
	2318	+ .enable_reg = 0x27014,
	2319	+ .enable_mask = BIT(0),
	2320	+ .hw.init = &(const struct clk_init_data) {
	2321	+ .name = "gcc_lpass_sway_clk",
	2322	+ .parent_hws = (const struct clk_hw*[]) {
	2323	+ &gcc_lpass_sway_clk_src.clkr.hw,
	2324	+ },
	2325	+ .num_parents = 1,
	2326	+ .flags = CLK_SET_RATE_PARENT,
	2327	+ .ops = &clk_branch2_ops,
	2328	+ },
	2329	+ },
	2330	+};
	2331	+
	2332	+static struct clk_branch gcc_cnoc_lpass_cfg_clk = {
	2333	+ .halt_reg = 0x31020,
	2334	+ .halt_check = BRANCH_HALT,
	2335	+ .clkr = {
	2336	+ .enable_reg = 0x31020,
	2337	+ .enable_mask = BIT(0),
	2338	+ .hw.init = &(const struct clk_init_data) {
	2339	+ .name = "gcc_cnoc_lpass_cfg_clk",
	2340	+ .parent_hws = (const struct clk_hw*[]) {
	2341	+ &gcc_lpass_sway_clk_src.clkr.hw,
	2342	+ },
	2343	+ .num_parents = 1,
	2344	+ .flags = CLK_SET_RATE_PARENT,
	2345	+ .ops = &clk_branch2_ops,
	2346	+ },
	2347	+ },
	2348	+};
	2349	+
	2350	+static struct clk_branch gcc_lpass_core_axim_clk = {
	2351	+ .halt_reg = 0x27018,
	2352	+ .halt_check = BRANCH_HALT,
	2353	+ .clkr = {
	2354	+ .enable_reg = 0x27018,
	2355	+ .enable_mask = BIT(0),
	2356	+ .hw.init = &(const struct clk_init_data) {
	2357	+ .name = "gcc_lpass_core_axim_clk",
	2358	+ .parent_hws = (const struct clk_hw*[]) {
	2359	+ &gcc_lpass_axim_clk_src.clkr.hw,
	2360	+ },
	2361	+ .num_parents = 1,
	2362	+ .flags = CLK_SET_RATE_PARENT,
	2363	+ .ops = &clk_branch2_ops,
	2364	+ },
	2365	+ },
	2366	+};
	2367	+
	2368	+static __maybe_unused struct clk_regmap *gcc_ipq5210_clocks[] = {
	2369	+ [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
	2370	+ [GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr,
	2371	+ [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
	2372	+ [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
	2373	+ [GCC_CNOC_LPASS_CFG_CLK] = &gcc_cnoc_lpass_cfg_clk.clkr,
	2374	+ [GCC_CNOC_PCIE0_1LANE_S_CLK] = &gcc_cnoc_pcie0_1lane_s_clk.clkr,
	2375	+ [GCC_CNOC_PCIE1_2LANE_S_CLK] = &gcc_cnoc_pcie1_2lane_s_clk.clkr,
	2376	+ [GCC_CNOC_USB_CLK] = &gcc_cnoc_usb_clk.clkr,
	2377	+ [GCC_GEPHY_SYS_CLK] = &gcc_gephy_sys_clk.clkr,
	2378	+ [GCC_LPASS_AXIM_CLK_SRC] = &gcc_lpass_axim_clk_src.clkr,
	2379	+ [GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
	2380	+ [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
	2381	+ [GCC_LPASS_SWAY_CLK_SRC] = &gcc_lpass_sway_clk_src.clkr,
	2382	+ [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
	2383	+ [GCC_MDIO_GEPHY_AHB_CLK] = &gcc_mdio_gephy_ahb_clk.clkr,
	2384	+ [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
	2385	+ [GCC_NSS_TS_CLK_SRC] = &gcc_nss_ts_clk_src.clkr,
	2386	+ [GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
	2387	+ [GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
	2388	+ [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
	2389	+ [GCC_NSSNOC_MEMNOC_1_CLK] = &gcc_nssnoc_memnoc_1_clk.clkr,
	2390	+ [GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &gcc_nssnoc_memnoc_bfdcd_clk_src.clkr,
	2391	+ [GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr,
	2392	+ [GCC_NSSNOC_MEMNOC_DIV_CLK_SRC] = &gcc_nssnoc_memnoc_div_clk_src.clkr,
	2393	+ [GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
	2394	+ [GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
	2395	+ [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
	2396	+ [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
	2397	+ [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
	2398	+ [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
	2399	+ [GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,
	2400	+ [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
	2401	+ [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
	2402	+ [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
	2403	+ [GCC_PCIE0_AXI_M_CLK_SRC] = &gcc_pcie0_axi_m_clk_src.clkr,
	2404	+ [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
	2405	+ [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
	2406	+ [GCC_PCIE0_AXI_S_CLK_SRC] = &gcc_pcie0_axi_s_clk_src.clkr,
	2407	+ [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
	2408	+ [GCC_PCIE0_PIPE_CLK_SRC] = &gcc_pcie0_pipe_clk_src.clkr,
	2409	+ [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
	2410	+ [GCC_PCIE0_RCHNG_CLK_SRC] = &gcc_pcie0_rchng_clk_src.clkr,
	2411	+ [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
	2412	+ [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
	2413	+ [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
	2414	+ [GCC_PCIE1_AXI_M_CLK_SRC] = &gcc_pcie1_axi_m_clk_src.clkr,
	2415	+ [GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
	2416	+ [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
	2417	+ [GCC_PCIE1_AXI_S_CLK_SRC] = &gcc_pcie1_axi_s_clk_src.clkr,
	2418	+ [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
	2419	+ [GCC_PCIE1_PIPE_CLK_SRC] = &gcc_pcie1_pipe_clk_src.clkr,
	2420	+ [GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr,
	2421	+ [GCC_PCIE1_RCHNG_CLK_SRC] = &gcc_pcie1_rchng_clk_src.clkr,
	2422	+ [GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr,
	2423	+ [GCC_PCNOC_BFDCD_CLK_SRC] = &gcc_pcnoc_bfdcd_clk_src.clkr,
	2424	+ [GCC_PON_APB_CLK] = &gcc_pon_apb_clk.clkr,
	2425	+ [GCC_PON_TM_CLK] = &gcc_pon_tm_clk.clkr,
	2426	+ [GCC_PON_TM2X_CLK] = &gcc_pon_tm2x_clk.clkr,
	2427	+ [GCC_PON_TM2X_CLK_SRC] = &gcc_pon_tm2x_clk_src.clkr,
	2428	+ [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
	2429	+ [GCC_QDSS_AT_CLK_SRC] = &gcc_qdss_at_clk_src.clkr,
	2430	+ [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
	2431	+ [GCC_QDSS_TSCTR_CLK_SRC] = &gcc_qdss_tsctr_clk_src.clkr,
	2432	+ [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
	2433	+ [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
	2434	+ [GCC_QPIC_CLK_SRC] = &gcc_qpic_clk_src.clkr,
	2435	+ [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
	2436	+ [GCC_QPIC_IO_MACRO_CLK_SRC] = &gcc_qpic_io_macro_clk_src.clkr,
	2437	+ [GCC_QRNG_AHB_CLK] = &gcc_qrng_ahb_clk.clkr,
	2438	+ [GCC_QUPV3_AHB_MST_CLK] = &gcc_qupv3_ahb_mst_clk.clkr,
	2439	+ [GCC_QUPV3_AHB_SLV_CLK] = &gcc_qupv3_ahb_slv_clk.clkr,
	2440	+ [GCC_QUPV3_WRAP_SE0_CLK] = &gcc_qupv3_wrap_se0_clk.clkr,
	2441	+ [GCC_QUPV3_WRAP_SE0_CLK_SRC] = &gcc_qupv3_wrap_se0_clk_src.clkr,
	2442	+ [GCC_QUPV3_WRAP_SE1_CLK] = &gcc_qupv3_wrap_se1_clk.clkr,
	2443	+ [GCC_QUPV3_WRAP_SE1_CLK_SRC] = &gcc_qupv3_wrap_se1_clk_src.clkr,
	2444	+ [GCC_QUPV3_WRAP_SE2_CLK] = &gcc_qupv3_wrap_se2_clk.clkr,
	2445	+ [GCC_QUPV3_WRAP_SE2_CLK_SRC] = &gcc_qupv3_wrap_se2_clk_src.clkr,
	2446	+ [GCC_QUPV3_WRAP_SE3_CLK] = &gcc_qupv3_wrap_se3_clk.clkr,
	2447	+ [GCC_QUPV3_WRAP_SE3_CLK_SRC] = &gcc_qupv3_wrap_se3_clk_src.clkr,
	2448	+ [GCC_QUPV3_WRAP_SE4_CLK] = &gcc_qupv3_wrap_se4_clk.clkr,
	2449	+ [GCC_QUPV3_WRAP_SE4_CLK_SRC] = &gcc_qupv3_wrap_se4_clk_src.clkr,
	2450	+ [GCC_QUPV3_WRAP_SE5_CLK] = &gcc_qupv3_wrap_se5_clk.clkr,
	2451	+ [GCC_QUPV3_WRAP_SE5_CLK_SRC] = &gcc_qupv3_wrap_se5_clk_src.clkr,
	2452	+ [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
	2453	+ [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
	2454	+ [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
	2455	+ [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
	2456	+ [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
	2457	+ [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
	2458	+ [GCC_SNOC_LPASS_CLK] = &gcc_snoc_lpass_clk.clkr,
	2459	+ [GCC_SNOC_PCIE0_AXI_M_CLK] = &gcc_snoc_pcie0_axi_m_clk.clkr,
	2460	+ [GCC_SNOC_PCIE1_AXI_M_CLK] = &gcc_snoc_pcie1_axi_m_clk.clkr,
	2461	+ [GCC_SYSTEM_NOC_BFDCD_CLK_SRC] = &gcc_system_noc_bfdcd_clk_src.clkr,
	2462	+ [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
	2463	+ [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
	2464	+ [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
	2465	+ [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
	2466	+ [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
	2467	+ [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
	2468	+ [GCC_UNIPHY_SYS_CLK_SRC] = &gcc_uniphy_sys_clk_src.clkr,
	2469	+ [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
	2470	+ [GCC_USB0_AUX_CLK_SRC] = &gcc_usb0_aux_clk_src.clkr,
	2471	+ [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
	2472	+ [GCC_USB0_MASTER_CLK_SRC] = &gcc_usb0_master_clk_src.clkr,
	2473	+ [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
	2474	+ [GCC_USB0_MOCK_UTMI_CLK_SRC] = &gcc_usb0_mock_utmi_clk_src.clkr,
	2475	+ [GCC_USB0_MOCK_UTMI_DIV_CLK_SRC] = &gcc_usb0_mock_utmi_div_clk_src.clkr,
	2476	+ [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
	2477	+ [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
	2478	+ [GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr,
	2479	+ [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
	2480	+ [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
	2481	+ [GPLL0_MAIN] = &gpll0_main.clkr,
	2482	+ [GPLL0] = &gpll0.clkr,
	2483	+ [GPLL2_MAIN] = &gpll2_main.clkr,
	2484	+ [GPLL2] = &gpll2.clkr,
	2485	+ [GPLL4_MAIN] = &gpll4_main.clkr,
	2486	+};
	2487	+
	2488	+static const struct qcom_reset_map gcc_ipq5210_resets[] = {
	2489	+ [GCC_ADSS_BCR] = { 0x1c000 },
	2490	+ [GCC_ADSS_PWM_ARES] = { 0x1c00c, 2 },
	2491	+ [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000 },
	2492	+ [GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_ARES] = { 0x3800c, 2 },
	2493	+ [GCC_APSS_AHB_ARES] = { 0x24014, 2 },
	2494	+ [GCC_APSS_ATB_ARES] = { 0x24034, 2 },
	2495	+ [GCC_APSS_AXI_ARES] = { 0x24018, 2 },
	2496	+ [GCC_APSS_TS_ARES] = { 0x24030, 2 },
	2497	+ [GCC_BOOT_ROM_AHB_ARES] = { 0x1302c, 2 },
	2498	+ [GCC_BOOT_ROM_BCR] = { 0x13028 },
	2499	+ [GCC_GEPHY_BCR] = { 0x2a000 },
	2500	+ [GCC_GEPHY_SYS_ARES] = { 0x2a004, 2 },
	2501	+ [GCC_GP1_ARES] = { 0x8018, 2 },
	2502	+ [GCC_GP2_ARES] = { 0x9018, 2 },
	2503	+ [GCC_GP3_ARES] = { 0xa018, 2 },
	2504	+ [GCC_MDIO_AHB_ARES] = { 0x17040, 2 },
	2505	+ [GCC_MDIO_BCR] = { 0x1703c },
	2506	+ [GCC_MDIO_GEPHY_AHB_ARES] = { 0x17098, 2 },
	2507	+ [GCC_NSS_BCR] = { 0x17000 },
	2508	+ [GCC_NSS_TS_ARES] = { 0x17018, 2 },
	2509	+ [GCC_NSSCC_ARES] = { 0x17034, 2 },
	2510	+ [GCC_NSSCFG_ARES] = { 0x1702c, 2 },
	2511	+ [GCC_NSSNOC_ATB_ARES] = { 0x17014, 2 },
	2512	+ [GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17084, 2 },
	2513	+ [GCC_NSSNOC_MEMNOC_ARES] = { 0x17024, 2 },
	2514	+ [GCC_NSSNOC_NSSCC_ARES] = { 0x17030, 2 },
	2515	+ [GCC_NSSNOC_PCNOC_1_ARES] = { 0x17080, 2 },
	2516	+ [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x1701c, 2 },
	2517	+ [GCC_NSSNOC_SNOC_1_ARES] = { 0x1707c, 2 },
	2518	+ [GCC_NSSNOC_SNOC_ARES] = { 0x17028, 2 },
	2519	+ [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17020, 2 },
	2520	+ [GCC_NSSNOC_XO_DCD_ARES] = { 0x17074, 2 },
	2521	+ [GCC_PCIE0_AHB_ARES] = { 0x28030, 2 },
	2522	+ [GCC_PCIE0_AUX_ARES] = { 0x28070, 2 },
	2523	+ [GCC_PCIE0_AXI_M_ARES] = { 0x28038, 2 },
	2524	+ [GCC_PCIE0_AXI_S_BRIDGE_ARES] = { 0x28048, 2 },
	2525	+ [GCC_PCIE0_AXI_S_ARES] = { 0x28040, 2 },
	2526	+ [GCC_PCIE0_BCR] = { 0x28000 },
	2527	+ [GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054 },
	2528	+ [GCC_PCIE0_PIPE_RESET] = { 0x28058, 0 },
	2529	+ [GCC_PCIE0_CORE_STICKY_RESET] = { 0x28058, 1 },
	2530	+ [GCC_PCIE0_AXI_S_STICKY_RESET] = { 0x28058, 2 },
	2531	+ [GCC_PCIE0_AXI_S_RESET] = { 0x28058, 3 },
	2532	+ [GCC_PCIE0_AXI_M_STICKY_RESET] = { 0x28058, 4 },
	2533	+ [GCC_PCIE0_AXI_M_RESET] = { 0x28058, 5 },
	2534	+ [GCC_PCIE0_AUX_RESET] = { 0x28058, 6 },
	2535	+ [GCC_PCIE0_AHB_RESET] = { 0x28058, 7 },
	2536	+ [GCC_PCIE0_PHY_BCR] = { 0x28060 },
	2537	+ [GCC_PCIE0_PIPE_ARES] = { 0x28068, 2 },
	2538	+ [GCC_PCIE0PHY_PHY_BCR] = { 0x2805c },
	2539	+ [GCC_PCIE1_AHB_ARES] = { 0x29030, 2 },
	2540	+ [GCC_PCIE1_AUX_ARES] = { 0x29074, 2 },
	2541	+ [GCC_PCIE1_AXI_M_ARES] = { 0x29038, 2 },
	2542	+ [GCC_PCIE1_AXI_S_BRIDGE_ARES] = { 0x29048, 2 },
	2543	+ [GCC_PCIE1_AXI_S_ARES] = { 0x29040, 2 },
	2544	+ [GCC_PCIE1_BCR] = { 0x29000 },
	2545	+ [GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054 },
	2546	+ [GCC_PCIE1_PIPE_RESET] = { 0x29058, 0 },
	2547	+ [GCC_PCIE1_CORE_STICKY_RESET] = { 0x29058, 1 },
	2548	+ [GCC_PCIE1_AXI_S_STICKY_RESET] = { 0x29058, 2 },
	2549	+ [GCC_PCIE1_AXI_S_RESET] = { 0x29058, 3 },
	2550	+ [GCC_PCIE1_AXI_M_STICKY_RESET] = { 0x29058, 4 },
	2551	+ [GCC_PCIE1_AXI_M_RESET] = { 0x29058, 5 },
	2552	+ [GCC_PCIE1_AUX_RESET] = { 0x29058, 6 },
	2553	+ [GCC_PCIE1_AHB_RESET] = { 0x29058, 7 },
	2554	+ [GCC_PCIE1_PHY_BCR] = { 0x29060 },
	2555	+ [GCC_PCIE1_PIPE_ARES] = { 0x29068, 2 },
	2556	+ [GCC_PCIE1PHY_PHY_BCR] = { 0x2905c },
	2557	+ [GCC_QRNG_AHB_ARES] = { 0x13024, 2 },
	2558	+ [GCC_QRNG_BCR] = { 0x13020 },
	2559	+ [GCC_QUPV3_2X_CORE_ARES] = { 0x1020, 2 },
	2560	+ [GCC_QUPV3_AHB_MST_ARES] = { 0x1014, 2 },
	2561	+ [GCC_QUPV3_AHB_SLV_ARES] = { 0x102c, 2 },
	2562	+ [GCC_QUPV3_BCR] = { 0x1000 },
	2563	+ [GCC_QUPV3_CORE_ARES] = { 0x1018, 2 },
	2564	+ [GCC_QUPV3_WRAP_SE0_ARES] = { 0x4020, 2 },
	2565	+ [GCC_QUPV3_WRAP_SE0_BCR] = { 0x4000 },
	2566	+ [GCC_QUPV3_WRAP_SE1_ARES] = { 0x5020, 2 },
	2567	+ [GCC_QUPV3_WRAP_SE1_BCR] = { 0x5000 },
	2568	+ [GCC_QUPV3_WRAP_SE2_ARES] = { 0x202c, 2 },
	2569	+ [GCC_QUPV3_WRAP_SE2_BCR] = { 0x2000 },
	2570	+ [GCC_QUPV3_WRAP_SE3_ARES] = { 0x2048, 2 },
	2571	+ [GCC_QUPV3_WRAP_SE3_BCR] = { 0x2030 },
	2572	+ [GCC_QUPV3_WRAP_SE4_ARES] = { 0x302c, 2 },
	2573	+ [GCC_QUPV3_WRAP_SE4_BCR] = { 0x3000 },
	2574	+ [GCC_QUPV3_WRAP_SE5_ARES] = { 0x3048, 2 },
	2575	+ [GCC_QUPV3_WRAP_SE5_BCR] = { 0x3030 },
	2576	+ [GCC_QUSB2_0_PHY_BCR] = { 0x2c068 },
	2577	+ [GCC_SDCC1_AHB_ARES] = { 0x3303c, 2 },
	2578	+ [GCC_SDCC1_APPS_ARES] = { 0x3302c, 2 },
	2579	+ [GCC_SDCC1_ICE_CORE_ARES] = { 0x33034, 2 },
	2580	+ [GCC_SDCC_BCR] = { 0x33000 },
	2581	+ [GCC_TLMM_AHB_ARES] = { 0x3e004, 2 },
	2582	+ [GCC_TLMM_ARES] = { 0x3e008, 2 },
	2583	+ [GCC_TLMM_BCR] = { 0x3e000 },
	2584	+ [GCC_UNIPHY0_AHB_ARES] = { 0x1704c, 2 },
	2585	+ [GCC_UNIPHY0_BCR] = { 0x17044 },
	2586	+ [GCC_UNIPHY0_SYS_ARES] = { 0x17048, 2 },
	2587	+ [GCC_UNIPHY1_AHB_ARES] = { 0x1705c, 2 },
	2588	+ [GCC_UNIPHY1_BCR] = { 0x17054 },
	2589	+ [GCC_UNIPHY1_SYS_ARES] = { 0x17058, 2 },
	2590	+ [GCC_UNIPHY2_AHB_ARES] = { 0x1706c, 2 },
	2591	+ [GCC_UNIPHY2_BCR] = { 0x17064 },
	2592	+ [GCC_UNIPHY2_SYS_ARES] = { 0x17068, 2 },
	2593	+ [GCC_USB0_AUX_ARES] = { 0x2c04c, 2 },
	2594	+ [GCC_USB0_MASTER_ARES] = { 0x2c044, 2 },
	2595	+ [GCC_USB0_MOCK_UTMI_ARES] = { 0x2c050, 2 },
	2596	+ [GCC_USB0_PHY_BCR] = { 0x2c06c },
	2597	+ [GCC_USB0_PHY_CFG_AHB_ARES] = { 0x2c05c, 2 },
	2598	+ [GCC_USB0_PIPE_ARES] = { 0x2c054, 2 },
	2599	+ [GCC_USB0_SLEEP_ARES] = { 0x2c058, 2 },
	2600	+ [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070 },
	2601	+ [GCC_USB_BCR] = { 0x2c000 },
	2602	+ [GCC_QDSS_BCR] = { 0x2d000 },
	2603	+};
	2604	+
	2605	+static const struct of_device_id gcc_ipq5210_match_table[] = {
	2606	+ { .compatible = "qcom,ipq5210-gcc" },
	2607	+ { }
	2608	+};
	2609	+MODULE_DEVICE_TABLE(of, gcc_ipq5210_match_table);
	2610	+
	2611	+static const struct regmap_config gcc_ipq5210_regmap_config = {
	2612	+ .reg_bits = 32,
	2613	+ .reg_stride = 4,
	2614	+ .val_bits = 32,
	2615	+ .max_register = 0x3f024,
	2616	+ .fast_io = true,
	2617	+};
	2618	+
	2619	+static struct clk_hw *gcc_ipq5210_hws[] = {
	2620	+ &gpll0_div2.hw,
	2621	+ &gcc_xo_div4_clk_src.hw,
	2622	+ &gcc_pon_tm_div_clk_src.hw,
	2623	+};
	2624	+
	2625	+static const struct qcom_cc_desc gcc_ipq5210_desc = {
	2626	+ .config = &gcc_ipq5210_regmap_config,
	2627	+ .clks = gcc_ipq5210_clocks,
	2628	+ .num_clks = ARRAY_SIZE(gcc_ipq5210_clocks),
	2629	+ .resets = gcc_ipq5210_resets,
	2630	+ .num_resets = ARRAY_SIZE(gcc_ipq5210_resets),
	2631	+ .clk_hws = gcc_ipq5210_hws,
	2632	+ .num_clk_hws = ARRAY_SIZE(gcc_ipq5210_hws),
	2633	+};
	2634	+
	2635	+static int gcc_ipq5210_probe(struct platform_device *pdev)
	2636	+{
	2637	+ return qcom_cc_probe(pdev, &gcc_ipq5210_desc);
	2638	+}
	2639	+
	2640	+static struct platform_driver gcc_ipq5210_driver = {
	2641	+ .probe = gcc_ipq5210_probe,
	2642	+ .driver = {
	2643	+ .name = "qcom,gcc-ipq5210",
	2644	+ .of_match_table = gcc_ipq5210_match_table,
	2645	+ },
	2646	+};
	2647	+
	2648	+static int __init gcc_ipq5210_init(void)
	2649	+{
	2650	+ return platform_driver_register(&gcc_ipq5210_driver);
	2651	+}
	2652	+core_initcall(gcc_ipq5210_init);
	2653	+
	2654	+static void __exit gcc_ipq5210_exit(void)
	2655	+{
	2656	+ platform_driver_unregister(&gcc_ipq5210_driver);
	2657	+}
	2658	+module_exit(gcc_ipq5210_exit);
	2659	+
	2660	+MODULE_DESCRIPTION("QTI GCC IPQ5210 Driver");
	2661	+MODULE_LICENSE("GPL");

drivers/clk/qcom/gcc-ipq6018.c+1−1

@@ -400,7 +400,7 @@ static struct clk_branch gcc_xo_clk_src = { · 399 unmodified lines
400	400	.fw_name = "xo",
401	401	},
402	402	.num_parents = 1,
403		− .flags = CLK_SET_RATE_PARENT,
	403	+ .flags = CLK_SET_RATE_PARENT \| CLK_IS_CRITICAL,
404	404	.ops = &clk_branch2_ops,
405	405	},
406	406	},

drivers/clk/qcom/gcc-kaanapali.c+2−3

@@ -6,7 +6,6 @@ · 5 unmodified lines
6	6	#include <linux/clk-provider.h>
7	7	#include <linux/mod_devicetable.h>
8	8	#include <linux/module.h>
9		−#include <linux/of.h>
10	9	#include <linux/platform_device.h>
11	10	#include <linux/regmap.h>
12	11
@@ -3458,7 +3457,7 @@ static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { · 3445 unmodified lines
3458	3457	DEFINE_RCG_DFS(gcc_qupv3_wrap4_s4_clk_src),
3459	3458	};
3460	3459
3461		−static u32 gcc_kaanapali_critical_cbcrs[] = {
	3460	+static const u32 gcc_kaanapali_critical_cbcrs[] = {
3462	3461	0xa0004, /* GCC_CAM_BIST_MCLK_AHB_CLK */
3463	3462	0x26004, /* GCC_CAMERA_AHB_CLK */
3464	3463	0x2603c, /* GCC_CAMERA_XO_CLK */
@@ -3486,7 +3485,7 @@ static void clk_kaanapali_regs_configure(struct device dev, struct regmap regm · 21 unmodified lines
3486	3485	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
3487	3486	}
3488	3487
3489		−static struct qcom_cc_driver_data gcc_kaanapali_driver_data = {
	3488	+static const struct qcom_cc_driver_data gcc_kaanapali_driver_data = {
3490	3489	.clk_cbcrs = gcc_kaanapali_critical_cbcrs,
3491	3490	.num_clk_cbcrs = ARRAY_SIZE(gcc_kaanapali_critical_cbcrs),
3492	3491	.dfs_rcgs = gcc_dfs_clocks,

drivers/clk/qcom/gcc-milos.c+2−2

@@ -3152,7 +3152,7 @@ static struct gdsc *gcc_milos_gdscs[] = { · 3151 unmodified lines
3152	3152	[USB3_PHY_GDSC] = &usb3_phy_gdsc,
3153	3153	};
3154	3154
3155		−static u32 gcc_milos_critical_cbcrs[] = {
	3155	+static const u32 gcc_milos_critical_cbcrs[] = {
3156	3156	0x26004, /* GCC_CAMERA_AHB_CLK */
3157	3157	0x26018, /* GCC_CAMERA_HF_XO_CLK */
3158	3158	0x2601c, /* GCC_CAMERA_SF_XO_CLK */
@@ -3171,7 +3171,7 @@ static const struct regmap_config gcc_milos_regmap_config = { · 12 unmodified lines
3171	3171	.fast_io = true,
3172	3172	};
3173	3173
3174		−static struct qcom_cc_driver_data gcc_milos_driver_data = {
	3174	+static const struct qcom_cc_driver_data gcc_milos_driver_data = {
3175	3175	.clk_cbcrs = gcc_milos_critical_cbcrs,
3176	3176	.num_clk_cbcrs = ARRAY_SIZE(gcc_milos_critical_cbcrs),
3177	3177	.dfs_rcgs = gcc_milos_dfs_clocks,

drivers/clk/qcom/gcc-nord.c+1902−0

@@ -0,0 +1,1902 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
	2	+/*
	3	+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
	4	+ */
	5	+
	6	+#include <linux/clk-provider.h>
	7	+#include <linux/mod_devicetable.h>
	8	+#include <linux/module.h>
	9	+#include <linux/platform_device.h>
	10	+#include <linux/regmap.h>
	11	+
	12	+#include <dt-bindings/clock/qcom,nord-gcc.h>
	13	+
	14	+#include "clk-alpha-pll.h"
	15	+#include "clk-branch.h"
	16	+#include "clk-pll.h"
	17	+#include "clk-rcg.h"
	18	+#include "clk-regmap.h"
	19	+#include "clk-regmap-divider.h"
	20	+#include "clk-regmap-mux.h"
	21	+#include "clk-regmap-phy-mux.h"
	22	+#include "common.h"
	23	+#include "gdsc.h"
	24	+#include "reset.h"
	25	+
	26	+enum {
	27	+ DT_BI_TCXO,
	28	+ DT_SLEEP_CLK,
	29	+ DT_PCIE_A_PIPE_CLK,
	30	+ DT_PCIE_B_PIPE_CLK,
	31	+ DT_PCIE_C_PIPE_CLK,
	32	+ DT_PCIE_D_PIPE_CLK,
	33	+};
	34	+
	35	+enum {
	36	+ P_BI_TCXO,
	37	+ P_GCC_GPLL0_OUT_EVEN,
	38	+ P_GCC_GPLL0_OUT_MAIN,
	39	+ P_PCIE_A_PIPE_CLK,
	40	+ P_PCIE_B_PIPE_CLK,
	41	+ P_PCIE_C_PIPE_CLK,
	42	+ P_PCIE_D_PIPE_CLK,
	43	+ P_SLEEP_CLK,
	44	+};
	45	+
	46	+static struct clk_alpha_pll gcc_gpll0 = {
	47	+ .offset = 0x0,
	48	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
	49	+ .clkr = {
	50	+ .enable_reg = 0x9d020,
	51	+ .enable_mask = BIT(0),
	52	+ .hw.init = &(const struct clk_init_data) {
	53	+ .name = "gcc_gpll0",
	54	+ .parent_data = &(const struct clk_parent_data) {
	55	+ .index = DT_BI_TCXO,
	56	+ },
	57	+ .num_parents = 1,
	58	+ .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
	59	+ },
	60	+ },
	61	+};
	62	+
	63	+static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
	64	+ { 0x1, 2 },
	65	+ { }
	66	+};
	67	+
	68	+static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
	69	+ .offset = 0x0,
	70	+ .post_div_shift = 10,
	71	+ .post_div_table = post_div_table_gcc_gpll0_out_even,
	72	+ .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
	73	+ .width = 4,
	74	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
	75	+ .clkr.hw.init = &(const struct clk_init_data) {
	76	+ .name = "gcc_gpll0_out_even",
	77	+ .parent_hws = (const struct clk_hw*[]) {
	78	+ &gcc_gpll0.clkr.hw,
	79	+ },
	80	+ .num_parents = 1,
	81	+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
	82	+ },
	83	+};
	84	+
	85	+static const struct parent_map gcc_parent_map_0[] = {
	86	+ { P_BI_TCXO, 0 },
	87	+ { P_GCC_GPLL0_OUT_MAIN, 1 },
	88	+ { P_GCC_GPLL0_OUT_EVEN, 6 },
	89	+};
	90	+
	91	+static const struct clk_parent_data gcc_parent_data_0[] = {
	92	+ { .index = DT_BI_TCXO },
	93	+ { .hw = &gcc_gpll0.clkr.hw },
	94	+ { .hw = &gcc_gpll0_out_even.clkr.hw },
	95	+};
	96	+
	97	+static const struct parent_map gcc_parent_map_1[] = {
	98	+ { P_BI_TCXO, 0 },
	99	+ { P_SLEEP_CLK, 5 },
	100	+};
	101	+
	102	+static const struct clk_parent_data gcc_parent_data_1[] = {
	103	+ { .index = DT_BI_TCXO },
	104	+ { .index = DT_SLEEP_CLK },
	105	+};
	106	+
	107	+static const struct parent_map gcc_parent_map_2[] = {
	108	+ { P_BI_TCXO, 0 },
	109	+ { P_GCC_GPLL0_OUT_MAIN, 1 },
	110	+ { P_SLEEP_CLK, 5 },
	111	+ { P_GCC_GPLL0_OUT_EVEN, 6 },
	112	+};
	113	+
	114	+static const struct clk_parent_data gcc_parent_data_2[] = {
	115	+ { .index = DT_BI_TCXO },
	116	+ { .hw = &gcc_gpll0.clkr.hw },
	117	+ { .index = DT_SLEEP_CLK },
	118	+ { .hw = &gcc_gpll0_out_even.clkr.hw },
	119	+};
	120	+
	121	+static const struct parent_map gcc_parent_map_3[] = {
	122	+ { P_BI_TCXO, 0 },
	123	+ { P_GCC_GPLL0_OUT_MAIN, 1 },
	124	+};
	125	+
	126	+static const struct clk_parent_data gcc_parent_data_3[] = {
	127	+ { .index = DT_BI_TCXO },
	128	+ { .hw = &gcc_gpll0.clkr.hw },
	129	+};
	130	+
	131	+static struct clk_regmap_phy_mux gcc_pcie_a_pipe_clk_src = {
	132	+ .reg = 0x49094,
	133	+ .clkr = {
	134	+ .hw.init = &(const struct clk_init_data) {
	135	+ .name = "gcc_pcie_a_pipe_clk_src",
	136	+ .parent_data = &(const struct clk_parent_data){
	137	+ .index = DT_PCIE_A_PIPE_CLK,
	138	+ },
	139	+ .num_parents = 1,
	140	+ .ops = &clk_regmap_phy_mux_ops,
	141	+ },
	142	+ },
	143	+};
	144	+
	145	+static struct clk_regmap_phy_mux gcc_pcie_b_pipe_clk_src = {
	146	+ .reg = 0x4a094,
	147	+ .clkr = {
	148	+ .hw.init = &(const struct clk_init_data) {
	149	+ .name = "gcc_pcie_b_pipe_clk_src",
	150	+ .parent_data = &(const struct clk_parent_data){
	151	+ .index = DT_PCIE_B_PIPE_CLK,
	152	+ },
	153	+ .num_parents = 1,
	154	+ .ops = &clk_regmap_phy_mux_ops,
	155	+ },
	156	+ },
	157	+};
	158	+
	159	+static struct clk_regmap_phy_mux gcc_pcie_c_pipe_clk_src = {
	160	+ .reg = 0x4b094,
	161	+ .clkr = {
	162	+ .hw.init = &(const struct clk_init_data) {
	163	+ .name = "gcc_pcie_c_pipe_clk_src",
	164	+ .parent_data = &(const struct clk_parent_data){
	165	+ .index = DT_PCIE_C_PIPE_CLK,
	166	+ },
	167	+ .num_parents = 1,
	168	+ .ops = &clk_regmap_phy_mux_ops,
	169	+ },
	170	+ },
	171	+};
	172	+
	173	+static struct clk_regmap_phy_mux gcc_pcie_d_pipe_clk_src = {
	174	+ .reg = 0x4c094,
	175	+ .clkr = {
	176	+ .hw.init = &(const struct clk_init_data) {
	177	+ .name = "gcc_pcie_d_pipe_clk_src",
	178	+ .parent_data = &(const struct clk_parent_data){
	179	+ .index = DT_PCIE_D_PIPE_CLK,
	180	+ },
	181	+ .num_parents = 1,
	182	+ .ops = &clk_regmap_phy_mux_ops,
	183	+ },
	184	+ },
	185	+};
	186	+
	187	+static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
	188	+ F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
	189	+ F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
	190	+ F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
	191	+ { }
	192	+};
	193	+
	194	+static struct clk_rcg2 gcc_gp1_clk_src = {
	195	+ .cmd_rcgr = 0x30004,
	196	+ .mnd_width = 16,
	197	+ .hid_width = 5,
	198	+ .parent_map = gcc_parent_map_2,
	199	+ .freq_tbl = ftbl_gcc_gp1_clk_src,
	200	+ .hw_clk_ctrl = true,
	201	+ .clkr.hw.init = &(const struct clk_init_data) {
	202	+ .name = "gcc_gp1_clk_src",
	203	+ .parent_data = gcc_parent_data_2,
	204	+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
	205	+ .flags = CLK_SET_RATE_PARENT,
	206	+ .ops = &clk_rcg2_shared_ops,
	207	+ },
	208	+};
	209	+
	210	+static struct clk_rcg2 gcc_gp2_clk_src = {
	211	+ .cmd_rcgr = 0x31004,
	212	+ .mnd_width = 16,
	213	+ .hid_width = 5,
	214	+ .parent_map = gcc_parent_map_2,
	215	+ .freq_tbl = ftbl_gcc_gp1_clk_src,
	216	+ .hw_clk_ctrl = true,
	217	+ .clkr.hw.init = &(const struct clk_init_data) {
	218	+ .name = "gcc_gp2_clk_src",
	219	+ .parent_data = gcc_parent_data_2,
	220	+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
	221	+ .flags = CLK_SET_RATE_PARENT,
	222	+ .ops = &clk_rcg2_shared_ops,
	223	+ },
	224	+};
	225	+
	226	+static const struct freq_tbl ftbl_gcc_pcie_a_aux_clk_src[] = {
	227	+ F(19200000, P_BI_TCXO, 1, 0, 0),
	228	+ { }
	229	+};
	230	+
	231	+static struct clk_rcg2 gcc_pcie_a_aux_clk_src = {
	232	+ .cmd_rcgr = 0x49098,
	233	+ .mnd_width = 16,
	234	+ .hid_width = 5,
	235	+ .parent_map = gcc_parent_map_1,
	236	+ .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
	237	+ .hw_clk_ctrl = true,
	238	+ .clkr.hw.init = &(const struct clk_init_data) {
	239	+ .name = "gcc_pcie_a_aux_clk_src",
	240	+ .parent_data = gcc_parent_data_1,
	241	+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
	242	+ .flags = CLK_SET_RATE_PARENT,
	243	+ .ops = &clk_rcg2_shared_ops,
	244	+ },
	245	+};
	246	+
	247	+static struct clk_rcg2 gcc_pcie_a_phy_aux_clk_src = {
	248	+ .cmd_rcgr = 0x4d020,
	249	+ .mnd_width = 16,
	250	+ .hid_width = 5,
	251	+ .parent_map = gcc_parent_map_1,
	252	+ .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
	253	+ .hw_clk_ctrl = true,
	254	+ .clkr.hw.init = &(const struct clk_init_data) {
	255	+ .name = "gcc_pcie_a_phy_aux_clk_src",
	256	+ .parent_data = gcc_parent_data_1,
	257	+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
	258	+ .flags = CLK_SET_RATE_PARENT,
	259	+ .ops = &clk_rcg2_shared_ops,
	260	+ },
	261	+};
	262	+
	263	+static const struct freq_tbl ftbl_gcc_pcie_a_phy_rchng_clk_src[] = {
	264	+ F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
	265	+ F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
	266	+ { }
	267	+};
	268	+
	269	+static struct clk_rcg2 gcc_pcie_a_phy_rchng_clk_src = {
	270	+ .cmd_rcgr = 0x4907c,
	271	+ .mnd_width = 0,
	272	+ .hid_width = 5,
	273	+ .parent_map = gcc_parent_map_0,
	274	+ .freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src,
	275	+ .hw_clk_ctrl = true,
	276	+ .clkr.hw.init = &(const struct clk_init_data) {
	277	+ .name = "gcc_pcie_a_phy_rchng_clk_src",
	278	+ .parent_data = gcc_parent_data_0,
	279	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	280	+ .flags = CLK_SET_RATE_PARENT,
	281	+ .ops = &clk_rcg2_shared_ops,
	282	+ },
	283	+};
	284	+
	285	+static struct clk_rcg2 gcc_pcie_b_aux_clk_src = {
	286	+ .cmd_rcgr = 0x4a098,
	287	+ .mnd_width = 16,
	288	+ .hid_width = 5,
	289	+ .parent_map = gcc_parent_map_1,
	290	+ .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
	291	+ .hw_clk_ctrl = true,
	292	+ .clkr.hw.init = &(const struct clk_init_data) {
	293	+ .name = "gcc_pcie_b_aux_clk_src",
	294	+ .parent_data = gcc_parent_data_1,
	295	+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
	296	+ .flags = CLK_SET_RATE_PARENT,
	297	+ .ops = &clk_rcg2_shared_ops,
	298	+ },
	299	+};
	300	+
	301	+static struct clk_rcg2 gcc_pcie_b_phy_aux_clk_src = {
	302	+ .cmd_rcgr = 0x4e020,
	303	+ .mnd_width = 16,
	304	+ .hid_width = 5,
	305	+ .parent_map = gcc_parent_map_1,
	306	+ .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
	307	+ .hw_clk_ctrl = true,
	308	+ .clkr.hw.init = &(const struct clk_init_data) {
	309	+ .name = "gcc_pcie_b_phy_aux_clk_src",
	310	+ .parent_data = gcc_parent_data_1,
	311	+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
	312	+ .flags = CLK_SET_RATE_PARENT,
	313	+ .ops = &clk_rcg2_shared_ops,
	314	+ },
	315	+};
	316	+
	317	+static struct clk_rcg2 gcc_pcie_b_phy_rchng_clk_src = {
	318	+ .cmd_rcgr = 0x4a07c,
	319	+ .mnd_width = 0,
	320	+ .hid_width = 5,
	321	+ .parent_map = gcc_parent_map_0,
	322	+ .freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src,
	323	+ .hw_clk_ctrl = true,
	324	+ .clkr.hw.init = &(const struct clk_init_data) {
	325	+ .name = "gcc_pcie_b_phy_rchng_clk_src",
	326	+ .parent_data = gcc_parent_data_0,
	327	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	328	+ .flags = CLK_SET_RATE_PARENT,
	329	+ .ops = &clk_rcg2_shared_ops,
	330	+ },
	331	+};
	332	+
	333	+static struct clk_rcg2 gcc_pcie_c_aux_clk_src = {
	334	+ .cmd_rcgr = 0x4b098,
	335	+ .mnd_width = 16,
	336	+ .hid_width = 5,
	337	+ .parent_map = gcc_parent_map_1,
	338	+ .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
	339	+ .hw_clk_ctrl = true,
	340	+ .clkr.hw.init = &(const struct clk_init_data) {
	341	+ .name = "gcc_pcie_c_aux_clk_src",
	342	+ .parent_data = gcc_parent_data_1,
	343	+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
	344	+ .flags = CLK_SET_RATE_PARENT,
	345	+ .ops = &clk_rcg2_shared_ops,
	346	+ },
	347	+};
	348	+
	349	+static struct clk_rcg2 gcc_pcie_c_phy_aux_clk_src = {
	350	+ .cmd_rcgr = 0x4f020,
	351	+ .mnd_width = 16,
	352	+ .hid_width = 5,
	353	+ .parent_map = gcc_parent_map_1,
	354	+ .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
	355	+ .hw_clk_ctrl = true,
	356	+ .clkr.hw.init = &(const struct clk_init_data) {
	357	+ .name = "gcc_pcie_c_phy_aux_clk_src",
	358	+ .parent_data = gcc_parent_data_1,
	359	+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
	360	+ .flags = CLK_SET_RATE_PARENT,
	361	+ .ops = &clk_rcg2_shared_ops,
	362	+ },
	363	+};
	364	+
	365	+static struct clk_rcg2 gcc_pcie_c_phy_rchng_clk_src = {
	366	+ .cmd_rcgr = 0x4b07c,
	367	+ .mnd_width = 0,
	368	+ .hid_width = 5,
	369	+ .parent_map = gcc_parent_map_3,
	370	+ .freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src,
	371	+ .hw_clk_ctrl = true,
	372	+ .clkr.hw.init = &(const struct clk_init_data) {
	373	+ .name = "gcc_pcie_c_phy_rchng_clk_src",
	374	+ .parent_data = gcc_parent_data_3,
	375	+ .num_parents = ARRAY_SIZE(gcc_parent_data_3),
	376	+ .flags = CLK_SET_RATE_PARENT,
	377	+ .ops = &clk_rcg2_shared_ops,
	378	+ },
	379	+};
	380	+
	381	+static struct clk_rcg2 gcc_pcie_d_aux_clk_src = {
	382	+ .cmd_rcgr = 0x4c098,
	383	+ .mnd_width = 16,
	384	+ .hid_width = 5,
	385	+ .parent_map = gcc_parent_map_1,
	386	+ .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
	387	+ .hw_clk_ctrl = true,
	388	+ .clkr.hw.init = &(const struct clk_init_data) {
	389	+ .name = "gcc_pcie_d_aux_clk_src",
	390	+ .parent_data = gcc_parent_data_1,
	391	+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
	392	+ .flags = CLK_SET_RATE_PARENT,
	393	+ .ops = &clk_rcg2_shared_ops,
	394	+ },
	395	+};
	396	+
	397	+static struct clk_rcg2 gcc_pcie_d_phy_aux_clk_src = {
	398	+ .cmd_rcgr = 0x50020,
	399	+ .mnd_width = 16,
	400	+ .hid_width = 5,
	401	+ .parent_map = gcc_parent_map_1,
	402	+ .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
	403	+ .hw_clk_ctrl = true,
	404	+ .clkr.hw.init = &(const struct clk_init_data) {
	405	+ .name = "gcc_pcie_d_phy_aux_clk_src",
	406	+ .parent_data = gcc_parent_data_1,
	407	+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
	408	+ .flags = CLK_SET_RATE_PARENT,
	409	+ .ops = &clk_rcg2_shared_ops,
	410	+ },
	411	+};
	412	+
	413	+static struct clk_rcg2 gcc_pcie_d_phy_rchng_clk_src = {
	414	+ .cmd_rcgr = 0x4c07c,
	415	+ .mnd_width = 0,
	416	+ .hid_width = 5,
	417	+ .parent_map = gcc_parent_map_3,
	418	+ .freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src,
	419	+ .hw_clk_ctrl = true,
	420	+ .clkr.hw.init = &(const struct clk_init_data) {
	421	+ .name = "gcc_pcie_d_phy_rchng_clk_src",
	422	+ .parent_data = gcc_parent_data_3,
	423	+ .num_parents = ARRAY_SIZE(gcc_parent_data_3),
	424	+ .flags = CLK_SET_RATE_PARENT,
	425	+ .ops = &clk_rcg2_shared_ops,
	426	+ },
	427	+};
	428	+
	429	+static struct clk_rcg2 gcc_pcie_noc_refgen_clk_src = {
	430	+ .cmd_rcgr = 0x52094,
	431	+ .mnd_width = 0,
	432	+ .hid_width = 5,
	433	+ .parent_map = gcc_parent_map_0,
	434	+ .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
	435	+ .hw_clk_ctrl = true,
	436	+ .clkr.hw.init = &(const struct clk_init_data) {
	437	+ .name = "gcc_pcie_noc_refgen_clk_src",
	438	+ .parent_data = gcc_parent_data_0,
	439	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	440	+ .flags = CLK_SET_RATE_PARENT,
	441	+ .ops = &clk_rcg2_shared_ops,
	442	+ },
	443	+};
	444	+
	445	+static struct clk_rcg2 gcc_pcie_noc_safety_clk_src = {
	446	+ .cmd_rcgr = 0x520ac,
	447	+ .mnd_width = 0,
	448	+ .hid_width = 5,
	449	+ .parent_map = gcc_parent_map_0,
	450	+ .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
	451	+ .hw_clk_ctrl = true,
	452	+ .clkr.hw.init = &(const struct clk_init_data) {
	453	+ .name = "gcc_pcie_noc_safety_clk_src",
	454	+ .parent_data = gcc_parent_data_0,
	455	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	456	+ .flags = CLK_SET_RATE_PARENT,
	457	+ .ops = &clk_rcg2_shared_ops,
	458	+ },
	459	+};
	460	+
	461	+static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
	462	+ F(40000000, P_GCC_GPLL0_OUT_MAIN, 15, 0, 0),
	463	+ F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
	464	+ { }
	465	+};
	466	+
	467	+static struct clk_rcg2 gcc_pdm2_clk_src = {
	468	+ .cmd_rcgr = 0x1a010,
	469	+ .mnd_width = 0,
	470	+ .hid_width = 5,
	471	+ .parent_map = gcc_parent_map_0,
	472	+ .freq_tbl = ftbl_gcc_pdm2_clk_src,
	473	+ .hw_clk_ctrl = true,
	474	+ .clkr.hw.init = &(const struct clk_init_data) {
	475	+ .name = "gcc_pdm2_clk_src",
	476	+ .parent_data = gcc_parent_data_0,
	477	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	478	+ .flags = CLK_SET_RATE_PARENT,
	479	+ .ops = &clk_rcg2_shared_ops,
	480	+ },
	481	+};
	482	+
	483	+static const struct freq_tbl ftbl_gcc_qupv3_wrap3_qspi_ref_clk_src[] = {
	484	+ F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
	485	+ F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
	486	+ F(19200000, P_BI_TCXO, 1, 0, 0),
	487	+ F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
	488	+ F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
	489	+ F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
	490	+ F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
	491	+ F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
	492	+ F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
	493	+ F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
	494	+ F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
	495	+ F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
	496	+ F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
	497	+ F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
	498	+ F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
	499	+ F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
	500	+ F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
	501	+ F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
	502	+ { }
	503	+};
	504	+
	505	+static struct clk_init_data gcc_qupv3_wrap3_qspi_ref_clk_src_init = {
	506	+ .name = "gcc_qupv3_wrap3_qspi_ref_clk_src",
	507	+ .parent_data = gcc_parent_data_0,
	508	+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
	509	+ .flags = CLK_SET_RATE_PARENT,
	510	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	511	+};
	512	+
	513	+static struct clk_rcg2 gcc_qupv3_wrap3_qspi_ref_clk_src = {
	514	+ .cmd_rcgr = 0x23174,
	515	+ .mnd_width = 16,
	516	+ .hid_width = 5,
	517	+ .parent_map = gcc_parent_map_0,
	518	+ .freq_tbl = ftbl_gcc_qupv3_wrap3_qspi_ref_clk_src,
	519	+ .hw_clk_ctrl = true,
	520	+ .clkr.hw.init = &gcc_qupv3_wrap3_qspi_ref_clk_src_init,
	521	+};
	522	+
	523	+static struct clk_regmap_div gcc_qupv3_wrap3_s0_clk_src = {
	524	+ .reg = 0x2316c,
	525	+ .shift = 0,
	526	+ .width = 4,
	527	+ .clkr.hw.init = &(const struct clk_init_data) {
	528	+ .name = "gcc_qupv3_wrap3_s0_clk_src",
	529	+ .parent_hws = (const struct clk_hw*[]) {
	530	+ &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr.hw,
	531	+ },
	532	+ .num_parents = 1,
	533	+ .flags = CLK_SET_RATE_PARENT,
	534	+ .ops = &clk_regmap_div_ro_ops,
	535	+ },
	536	+};
	537	+
	538	+static struct clk_branch gcc_boot_rom_ahb_clk = {
	539	+ .halt_reg = 0x1f004,
	540	+ .halt_check = BRANCH_HALT,
	541	+ .clkr = {
	542	+ .enable_reg = 0x1f004,
	543	+ .enable_mask = BIT(0),
	544	+ .hw.init = &(const struct clk_init_data) {
	545	+ .name = "gcc_boot_rom_ahb_clk",
	546	+ .ops = &clk_branch2_ops,
	547	+ },
	548	+ },
	549	+};
	550	+
	551	+static struct clk_branch gcc_gp1_clk = {
	552	+ .halt_reg = 0x30000,
	553	+ .halt_check = BRANCH_HALT,
	554	+ .clkr = {
	555	+ .enable_reg = 0x30000,
	556	+ .enable_mask = BIT(0),
	557	+ .hw.init = &(const struct clk_init_data) {
	558	+ .name = "gcc_gp1_clk",
	559	+ .parent_hws = (const struct clk_hw*[]) {
	560	+ &gcc_gp1_clk_src.clkr.hw,
	561	+ },
	562	+ .num_parents = 1,
	563	+ .flags = CLK_SET_RATE_PARENT,
	564	+ .ops = &clk_branch2_ops,
	565	+ },
	566	+ },
	567	+};
	568	+
	569	+static struct clk_branch gcc_gp2_clk = {
	570	+ .halt_reg = 0x31000,
	571	+ .halt_check = BRANCH_HALT,
	572	+ .clkr = {
	573	+ .enable_reg = 0x31000,
	574	+ .enable_mask = BIT(0),
	575	+ .hw.init = &(const struct clk_init_data) {
	576	+ .name = "gcc_gp2_clk",
	577	+ .parent_hws = (const struct clk_hw*[]) {
	578	+ &gcc_gp2_clk_src.clkr.hw,
	579	+ },
	580	+ .num_parents = 1,
	581	+ .flags = CLK_SET_RATE_PARENT,
	582	+ .ops = &clk_branch2_ops,
	583	+ },
	584	+ },
	585	+};
	586	+
	587	+static struct clk_branch gcc_mmu_0_tcu_vote_clk = {
	588	+ .halt_reg = 0x7d094,
	589	+ .halt_check = BRANCH_HALT_VOTED,
	590	+ .clkr = {
	591	+ .enable_reg = 0x7d094,
	592	+ .enable_mask = BIT(0),
	593	+ .hw.init = &(const struct clk_init_data) {
	594	+ .name = "gcc_mmu_0_tcu_vote_clk",
	595	+ .ops = &clk_branch2_ops,
	596	+ },
	597	+ },
	598	+};
	599	+
	600	+static struct clk_branch gcc_pcie_a_aux_clk = {
	601	+ .halt_reg = 0x49058,
	602	+ .halt_check = BRANCH_HALT_VOTED,
	603	+ .hwcg_reg = 0x49058,
	604	+ .hwcg_bit = 1,
	605	+ .clkr = {
	606	+ .enable_reg = 0x9d008,
	607	+ .enable_mask = BIT(14),
	608	+ .hw.init = &(const struct clk_init_data) {
	609	+ .name = "gcc_pcie_a_aux_clk",
	610	+ .parent_hws = (const struct clk_hw*[]) {
	611	+ &gcc_pcie_a_aux_clk_src.clkr.hw,
	612	+ },
	613	+ .num_parents = 1,
	614	+ .flags = CLK_SET_RATE_PARENT,
	615	+ .ops = &clk_branch2_ops,
	616	+ },
	617	+ },
	618	+};
	619	+
	620	+static struct clk_branch gcc_pcie_a_cfg_ahb_clk = {
	621	+ .halt_reg = 0x49054,
	622	+ .halt_check = BRANCH_HALT_VOTED,
	623	+ .hwcg_reg = 0x49054,
	624	+ .hwcg_bit = 1,
	625	+ .clkr = {
	626	+ .enable_reg = 0x9d008,
	627	+ .enable_mask = BIT(13),
	628	+ .hw.init = &(const struct clk_init_data) {
	629	+ .name = "gcc_pcie_a_cfg_ahb_clk",
	630	+ .ops = &clk_branch2_ops,
	631	+ },
	632	+ },
	633	+};
	634	+
	635	+static struct clk_branch gcc_pcie_a_dti_qtc_clk = {
	636	+ .halt_reg = 0x49018,
	637	+ .halt_check = BRANCH_HALT_SKIP,
	638	+ .hwcg_reg = 0x49018,
	639	+ .hwcg_bit = 1,
	640	+ .clkr = {
	641	+ .enable_reg = 0x9d008,
	642	+ .enable_mask = BIT(8),
	643	+ .hw.init = &(const struct clk_init_data) {
	644	+ .name = "gcc_pcie_a_dti_qtc_clk",
	645	+ .ops = &clk_branch2_ops,
	646	+ },
	647	+ },
	648	+};
	649	+
	650	+static struct clk_branch gcc_pcie_a_mstr_axi_clk = {
	651	+ .halt_reg = 0x49040,
	652	+ .halt_check = BRANCH_HALT_SKIP,
	653	+ .hwcg_reg = 0x49040,
	654	+ .hwcg_bit = 1,
	655	+ .clkr = {
	656	+ .enable_reg = 0x9d008,
	657	+ .enable_mask = BIT(12),
	658	+ .hw.init = &(const struct clk_init_data) {
	659	+ .name = "gcc_pcie_a_mstr_axi_clk",
	660	+ .ops = &clk_branch2_ops,
	661	+ },
	662	+ },
	663	+};
	664	+
	665	+static struct clk_branch gcc_pcie_a_phy_aux_clk = {
	666	+ .halt_reg = 0x4d01c,
	667	+ .halt_check = BRANCH_HALT_VOTED,
	668	+ .clkr = {
	669	+ .enable_reg = 0x9d010,
	670	+ .enable_mask = BIT(12),
	671	+ .hw.init = &(const struct clk_init_data) {
	672	+ .name = "gcc_pcie_a_phy_aux_clk",
	673	+ .parent_hws = (const struct clk_hw*[]) {
	674	+ &gcc_pcie_a_phy_aux_clk_src.clkr.hw,
	675	+ },
	676	+ .num_parents = 1,
	677	+ .flags = CLK_SET_RATE_PARENT,
	678	+ .ops = &clk_branch2_ops,
	679	+ },
	680	+ },
	681	+};
	682	+
	683	+static struct clk_branch gcc_pcie_a_phy_rchng_clk = {
	684	+ .halt_reg = 0x49078,
	685	+ .halt_check = BRANCH_HALT_VOTED,
	686	+ .hwcg_reg = 0x49078,
	687	+ .hwcg_bit = 1,
	688	+ .clkr = {
	689	+ .enable_reg = 0x9d008,
	690	+ .enable_mask = BIT(16),
	691	+ .hw.init = &(const struct clk_init_data) {
	692	+ .name = "gcc_pcie_a_phy_rchng_clk",
	693	+ .parent_hws = (const struct clk_hw*[]) {
	694	+ &gcc_pcie_a_phy_rchng_clk_src.clkr.hw,
	695	+ },
	696	+ .num_parents = 1,
	697	+ .flags = CLK_SET_RATE_PARENT,
	698	+ .ops = &clk_branch2_ops,
	699	+ },
	700	+ },
	701	+};
	702	+
	703	+static struct clk_branch gcc_pcie_a_pipe_clk = {
	704	+ .halt_reg = 0x49068,
	705	+ .halt_check = BRANCH_HALT_VOTED,
	706	+ .hwcg_reg = 0x49068,
	707	+ .hwcg_bit = 1,
	708	+ .clkr = {
	709	+ .enable_reg = 0x9d008,
	710	+ .enable_mask = BIT(15),
	711	+ .hw.init = &(const struct clk_init_data) {
	712	+ .name = "gcc_pcie_a_pipe_clk",
	713	+ .parent_hws = (const struct clk_hw*[]) {
	714	+ &gcc_pcie_a_pipe_clk_src.clkr.hw,
	715	+ },
	716	+ .num_parents = 1,
	717	+ .flags = CLK_SET_RATE_PARENT,
	718	+ .ops = &clk_branch2_ops,
	719	+ },
	720	+ },
	721	+};
	722	+
	723	+static struct clk_branch gcc_pcie_a_slv_axi_clk = {
	724	+ .halt_reg = 0x4902c,
	725	+ .halt_check = BRANCH_HALT_VOTED,
	726	+ .hwcg_reg = 0x4902c,
	727	+ .hwcg_bit = 1,
	728	+ .clkr = {
	729	+ .enable_reg = 0x9d008,
	730	+ .enable_mask = BIT(11),
	731	+ .hw.init = &(const struct clk_init_data) {
	732	+ .name = "gcc_pcie_a_slv_axi_clk",
	733	+ .ops = &clk_branch2_ops,
	734	+ },
	735	+ },
	736	+};
	737	+
	738	+static struct clk_branch gcc_pcie_a_slv_q2a_axi_clk = {
	739	+ .halt_reg = 0x49024,
	740	+ .halt_check = BRANCH_HALT_VOTED,
	741	+ .hwcg_reg = 0x49024,
	742	+ .hwcg_bit = 1,
	743	+ .clkr = {
	744	+ .enable_reg = 0x9d008,
	745	+ .enable_mask = BIT(10),
	746	+ .hw.init = &(const struct clk_init_data) {
	747	+ .name = "gcc_pcie_a_slv_q2a_axi_clk",
	748	+ .ops = &clk_branch2_ops,
	749	+ },
	750	+ },
	751	+};
	752	+
	753	+static struct clk_branch gcc_pcie_b_aux_clk = {
	754	+ .halt_reg = 0x4a058,
	755	+ .halt_check = BRANCH_HALT_VOTED,
	756	+ .clkr = {
	757	+ .enable_reg = 0x9d008,
	758	+ .enable_mask = BIT(23),
	759	+ .hw.init = &(const struct clk_init_data) {
	760	+ .name = "gcc_pcie_b_aux_clk",
	761	+ .parent_hws = (const struct clk_hw*[]) {
	762	+ &gcc_pcie_b_aux_clk_src.clkr.hw,
	763	+ },
	764	+ .num_parents = 1,
	765	+ .flags = CLK_SET_RATE_PARENT,
	766	+ .ops = &clk_branch2_ops,
	767	+ },
	768	+ },
	769	+};
	770	+
	771	+static struct clk_branch gcc_pcie_b_cfg_ahb_clk = {
	772	+ .halt_reg = 0x4a054,
	773	+ .halt_check = BRANCH_HALT_VOTED,
	774	+ .hwcg_reg = 0x4a054,
	775	+ .hwcg_bit = 1,
	776	+ .clkr = {
	777	+ .enable_reg = 0x9d008,
	778	+ .enable_mask = BIT(22),
	779	+ .hw.init = &(const struct clk_init_data) {
	780	+ .name = "gcc_pcie_b_cfg_ahb_clk",
	781	+ .ops = &clk_branch2_ops,
	782	+ },
	783	+ },
	784	+};
	785	+
	786	+static struct clk_branch gcc_pcie_b_dti_qtc_clk = {
	787	+ .halt_reg = 0x4a018,
	788	+ .halt_check = BRANCH_HALT_SKIP,
	789	+ .hwcg_reg = 0x4a018,
	790	+ .hwcg_bit = 1,
	791	+ .clkr = {
	792	+ .enable_reg = 0x9d008,
	793	+ .enable_mask = BIT(17),
	794	+ .hw.init = &(const struct clk_init_data) {
	795	+ .name = "gcc_pcie_b_dti_qtc_clk",
	796	+ .ops = &clk_branch2_ops,
	797	+ },
	798	+ },
	799	+};
	800	+
	801	+static struct clk_branch gcc_pcie_b_mstr_axi_clk = {
	802	+ .halt_reg = 0x4a040,
	803	+ .halt_check = BRANCH_HALT_SKIP,
	804	+ .hwcg_reg = 0x4a040,
	805	+ .hwcg_bit = 1,
	806	+ .clkr = {
	807	+ .enable_reg = 0x9d008,
	808	+ .enable_mask = BIT(21),
	809	+ .hw.init = &(const struct clk_init_data) {
	810	+ .name = "gcc_pcie_b_mstr_axi_clk",
	811	+ .ops = &clk_branch2_ops,
	812	+ },
	813	+ },
	814	+};
	815	+
	816	+static struct clk_branch gcc_pcie_b_phy_aux_clk = {
	817	+ .halt_reg = 0x4e01c,
	818	+ .halt_check = BRANCH_HALT_VOTED,
	819	+ .clkr = {
	820	+ .enable_reg = 0x9d010,
	821	+ .enable_mask = BIT(13),
	822	+ .hw.init = &(const struct clk_init_data) {
	823	+ .name = "gcc_pcie_b_phy_aux_clk",
	824	+ .parent_hws = (const struct clk_hw*[]) {
	825	+ &gcc_pcie_b_phy_aux_clk_src.clkr.hw,
	826	+ },
	827	+ .num_parents = 1,
	828	+ .flags = CLK_SET_RATE_PARENT,
	829	+ .ops = &clk_branch2_ops,
	830	+ },
	831	+ },
	832	+};
	833	+
	834	+static struct clk_branch gcc_pcie_b_phy_rchng_clk = {
	835	+ .halt_reg = 0x4a078,
	836	+ .halt_check = BRANCH_HALT_VOTED,
	837	+ .clkr = {
	838	+ .enable_reg = 0x9d008,
	839	+ .enable_mask = BIT(25),
	840	+ .hw.init = &(const struct clk_init_data) {
	841	+ .name = "gcc_pcie_b_phy_rchng_clk",
	842	+ .parent_hws = (const struct clk_hw*[]) {
	843	+ &gcc_pcie_b_phy_rchng_clk_src.clkr.hw,
	844	+ },
	845	+ .num_parents = 1,
	846	+ .flags = CLK_SET_RATE_PARENT,
	847	+ .ops = &clk_branch2_ops,
	848	+ },
	849	+ },
	850	+};
	851	+
	852	+static struct clk_branch gcc_pcie_b_pipe_clk = {
	853	+ .halt_reg = 0x4a068,
	854	+ .halt_check = BRANCH_HALT_VOTED,
	855	+ .clkr = {
	856	+ .enable_reg = 0x9d008,
	857	+ .enable_mask = BIT(24),
	858	+ .hw.init = &(const struct clk_init_data) {
	859	+ .name = "gcc_pcie_b_pipe_clk",
	860	+ .parent_hws = (const struct clk_hw*[]) {
	861	+ &gcc_pcie_b_pipe_clk_src.clkr.hw,
	862	+ },
	863	+ .num_parents = 1,
	864	+ .flags = CLK_SET_RATE_PARENT,
	865	+ .ops = &clk_branch2_ops,
	866	+ },
	867	+ },
	868	+};
	869	+
	870	+static struct clk_branch gcc_pcie_b_slv_axi_clk = {
	871	+ .halt_reg = 0x4a02c,
	872	+ .halt_check = BRANCH_HALT_VOTED,
	873	+ .hwcg_reg = 0x4a02c,
	874	+ .hwcg_bit = 1,
	875	+ .clkr = {
	876	+ .enable_reg = 0x9d008,
	877	+ .enable_mask = BIT(20),
	878	+ .hw.init = &(const struct clk_init_data) {
	879	+ .name = "gcc_pcie_b_slv_axi_clk",
	880	+ .ops = &clk_branch2_ops,
	881	+ },
	882	+ },
	883	+};
	884	+
	885	+static struct clk_branch gcc_pcie_b_slv_q2a_axi_clk = {
	886	+ .halt_reg = 0x4a024,
	887	+ .halt_check = BRANCH_HALT_VOTED,
	888	+ .clkr = {
	889	+ .enable_reg = 0x9d008,
	890	+ .enable_mask = BIT(19),
	891	+ .hw.init = &(const struct clk_init_data) {
	892	+ .name = "gcc_pcie_b_slv_q2a_axi_clk",
	893	+ .ops = &clk_branch2_ops,
	894	+ },
	895	+ },
	896	+};
	897	+
	898	+static struct clk_branch gcc_pcie_c_aux_clk = {
	899	+ .halt_reg = 0x4b058,
	900	+ .halt_check = BRANCH_HALT_VOTED,
	901	+ .clkr = {
	902	+ .enable_reg = 0x9d010,
	903	+ .enable_mask = BIT(0),
	904	+ .hw.init = &(const struct clk_init_data) {
	905	+ .name = "gcc_pcie_c_aux_clk",
	906	+ .parent_hws = (const struct clk_hw*[]) {
	907	+ &gcc_pcie_c_aux_clk_src.clkr.hw,
	908	+ },
	909	+ .num_parents = 1,
	910	+ .flags = CLK_SET_RATE_PARENT,
	911	+ .ops = &clk_branch2_ops,
	912	+ },
	913	+ },
	914	+};
	915	+
	916	+static struct clk_branch gcc_pcie_c_cfg_ahb_clk = {
	917	+ .halt_reg = 0x4b054,
	918	+ .halt_check = BRANCH_HALT_VOTED,
	919	+ .hwcg_reg = 0x4b054,
	920	+ .hwcg_bit = 1,
	921	+ .clkr = {
	922	+ .enable_reg = 0x9d008,
	923	+ .enable_mask = BIT(31),
	924	+ .hw.init = &(const struct clk_init_data) {
	925	+ .name = "gcc_pcie_c_cfg_ahb_clk",
	926	+ .ops = &clk_branch2_ops,
	927	+ },
	928	+ },
	929	+};
	930	+
	931	+static struct clk_branch gcc_pcie_c_dti_qtc_clk = {
	932	+ .halt_reg = 0x4b018,
	933	+ .halt_check = BRANCH_HALT_SKIP,
	934	+ .hwcg_reg = 0x4b018,
	935	+ .hwcg_bit = 1,
	936	+ .clkr = {
	937	+ .enable_reg = 0x9d008,
	938	+ .enable_mask = BIT(26),
	939	+ .hw.init = &(const struct clk_init_data) {
	940	+ .name = "gcc_pcie_c_dti_qtc_clk",
	941	+ .ops = &clk_branch2_ops,
	942	+ },
	943	+ },
	944	+};
	945	+
	946	+static struct clk_branch gcc_pcie_c_mstr_axi_clk = {
	947	+ .halt_reg = 0x4b040,
	948	+ .halt_check = BRANCH_HALT_SKIP,
	949	+ .hwcg_reg = 0x4b040,
	950	+ .hwcg_bit = 1,
	951	+ .clkr = {
	952	+ .enable_reg = 0x9d008,
	953	+ .enable_mask = BIT(30),
	954	+ .hw.init = &(const struct clk_init_data) {
	955	+ .name = "gcc_pcie_c_mstr_axi_clk",
	956	+ .ops = &clk_branch2_ops,
	957	+ },
	958	+ },
	959	+};
	960	+
	961	+static struct clk_branch gcc_pcie_c_phy_aux_clk = {
	962	+ .halt_reg = 0x4f01c,
	963	+ .halt_check = BRANCH_HALT_VOTED,
	964	+ .clkr = {
	965	+ .enable_reg = 0x9d010,
	966	+ .enable_mask = BIT(14),
	967	+ .hw.init = &(const struct clk_init_data) {
	968	+ .name = "gcc_pcie_c_phy_aux_clk",
	969	+ .parent_hws = (const struct clk_hw*[]) {
	970	+ &gcc_pcie_c_phy_aux_clk_src.clkr.hw,
	971	+ },
	972	+ .num_parents = 1,
	973	+ .flags = CLK_SET_RATE_PARENT,
	974	+ .ops = &clk_branch2_ops,
	975	+ },
	976	+ },
	977	+};
	978	+
	979	+static struct clk_branch gcc_pcie_c_phy_rchng_clk = {
	980	+ .halt_reg = 0x4b078,
	981	+ .halt_check = BRANCH_HALT_VOTED,
	982	+ .clkr = {
	983	+ .enable_reg = 0x9d010,
	984	+ .enable_mask = BIT(2),
	985	+ .hw.init = &(const struct clk_init_data) {
	986	+ .name = "gcc_pcie_c_phy_rchng_clk",
	987	+ .parent_hws = (const struct clk_hw*[]) {
	988	+ &gcc_pcie_c_phy_rchng_clk_src.clkr.hw,
	989	+ },
	990	+ .num_parents = 1,
	991	+ .flags = CLK_SET_RATE_PARENT,
	992	+ .ops = &clk_branch2_ops,
	993	+ },
	994	+ },
	995	+};
	996	+
	997	+static struct clk_branch gcc_pcie_c_pipe_clk = {
	998	+ .halt_reg = 0x4b068,
	999	+ .halt_check = BRANCH_HALT_VOTED,
	1000	+ .clkr = {
	1001	+ .enable_reg = 0x9d010,
	1002	+ .enable_mask = BIT(1),
	1003	+ .hw.init = &(const struct clk_init_data) {
	1004	+ .name = "gcc_pcie_c_pipe_clk",
	1005	+ .parent_hws = (const struct clk_hw*[]) {
	1006	+ &gcc_pcie_c_pipe_clk_src.clkr.hw,
	1007	+ },
	1008	+ .num_parents = 1,
	1009	+ .flags = CLK_SET_RATE_PARENT,
	1010	+ .ops = &clk_branch2_ops,
	1011	+ },
	1012	+ },
	1013	+};
	1014	+
	1015	+static struct clk_branch gcc_pcie_c_slv_axi_clk = {
	1016	+ .halt_reg = 0x4b02c,
	1017	+ .halt_check = BRANCH_HALT_VOTED,
	1018	+ .hwcg_reg = 0x4b02c,
	1019	+ .hwcg_bit = 1,
	1020	+ .clkr = {
	1021	+ .enable_reg = 0x9d008,
	1022	+ .enable_mask = BIT(29),
	1023	+ .hw.init = &(const struct clk_init_data) {
	1024	+ .name = "gcc_pcie_c_slv_axi_clk",
	1025	+ .ops = &clk_branch2_ops,
	1026	+ },
	1027	+ },
	1028	+};
	1029	+
	1030	+static struct clk_branch gcc_pcie_c_slv_q2a_axi_clk = {
	1031	+ .halt_reg = 0x4b024,
	1032	+ .halt_check = BRANCH_HALT_VOTED,
	1033	+ .clkr = {
	1034	+ .enable_reg = 0x9d008,
	1035	+ .enable_mask = BIT(28),
	1036	+ .hw.init = &(const struct clk_init_data) {
	1037	+ .name = "gcc_pcie_c_slv_q2a_axi_clk",
	1038	+ .ops = &clk_branch2_ops,
	1039	+ },
	1040	+ },
	1041	+};
	1042	+
	1043	+static struct clk_branch gcc_pcie_d_aux_clk = {
	1044	+ .halt_reg = 0x4c058,
	1045	+ .halt_check = BRANCH_HALT_VOTED,
	1046	+ .clkr = {
	1047	+ .enable_reg = 0x9d010,
	1048	+ .enable_mask = BIT(9),
	1049	+ .hw.init = &(const struct clk_init_data) {
	1050	+ .name = "gcc_pcie_d_aux_clk",
	1051	+ .parent_hws = (const struct clk_hw*[]) {
	1052	+ &gcc_pcie_d_aux_clk_src.clkr.hw,
	1053	+ },
	1054	+ .num_parents = 1,
	1055	+ .flags = CLK_SET_RATE_PARENT,
	1056	+ .ops = &clk_branch2_ops,
	1057	+ },
	1058	+ },
	1059	+};
	1060	+
	1061	+static struct clk_branch gcc_pcie_d_cfg_ahb_clk = {
	1062	+ .halt_reg = 0x4c054,
	1063	+ .halt_check = BRANCH_HALT_VOTED,
	1064	+ .hwcg_reg = 0x4c054,
	1065	+ .hwcg_bit = 1,
	1066	+ .clkr = {
	1067	+ .enable_reg = 0x9d010,
	1068	+ .enable_mask = BIT(8),
	1069	+ .hw.init = &(const struct clk_init_data) {
	1070	+ .name = "gcc_pcie_d_cfg_ahb_clk",
	1071	+ .ops = &clk_branch2_ops,
	1072	+ },
	1073	+ },
	1074	+};
	1075	+
	1076	+static struct clk_branch gcc_pcie_d_dti_qtc_clk = {
	1077	+ .halt_reg = 0x4c018,
	1078	+ .halt_check = BRANCH_HALT_SKIP,
	1079	+ .hwcg_reg = 0x4c018,
	1080	+ .hwcg_bit = 1,
	1081	+ .clkr = {
	1082	+ .enable_reg = 0x9d010,
	1083	+ .enable_mask = BIT(3),
	1084	+ .hw.init = &(const struct clk_init_data) {
	1085	+ .name = "gcc_pcie_d_dti_qtc_clk",
	1086	+ .ops = &clk_branch2_ops,
	1087	+ },
	1088	+ },
	1089	+};
	1090	+
	1091	+static struct clk_branch gcc_pcie_d_mstr_axi_clk = {
	1092	+ .halt_reg = 0x4c040,
	1093	+ .halt_check = BRANCH_HALT_SKIP,
	1094	+ .hwcg_reg = 0x4c040,
	1095	+ .hwcg_bit = 1,
	1096	+ .clkr = {
	1097	+ .enable_reg = 0x9d010,
	1098	+ .enable_mask = BIT(7),
	1099	+ .hw.init = &(const struct clk_init_data) {
	1100	+ .name = "gcc_pcie_d_mstr_axi_clk",
	1101	+ .ops = &clk_branch2_ops,
	1102	+ },
	1103	+ },
	1104	+};
	1105	+
	1106	+static struct clk_branch gcc_pcie_d_phy_aux_clk = {
	1107	+ .halt_reg = 0x5001c,
	1108	+ .halt_check = BRANCH_HALT_VOTED,
	1109	+ .clkr = {
	1110	+ .enable_reg = 0x9d010,
	1111	+ .enable_mask = BIT(16),
	1112	+ .hw.init = &(const struct clk_init_data) {
	1113	+ .name = "gcc_pcie_d_phy_aux_clk",
	1114	+ .parent_hws = (const struct clk_hw*[]) {
	1115	+ &gcc_pcie_d_phy_aux_clk_src.clkr.hw,
	1116	+ },
	1117	+ .num_parents = 1,
	1118	+ .flags = CLK_SET_RATE_PARENT,
	1119	+ .ops = &clk_branch2_ops,
	1120	+ },
	1121	+ },
	1122	+};
	1123	+
	1124	+static struct clk_branch gcc_pcie_d_phy_rchng_clk = {
	1125	+ .halt_reg = 0x4c078,
	1126	+ .halt_check = BRANCH_HALT_VOTED,
	1127	+ .clkr = {
	1128	+ .enable_reg = 0x9d010,
	1129	+ .enable_mask = BIT(11),
	1130	+ .hw.init = &(const struct clk_init_data) {
	1131	+ .name = "gcc_pcie_d_phy_rchng_clk",
	1132	+ .parent_hws = (const struct clk_hw*[]) {
	1133	+ &gcc_pcie_d_phy_rchng_clk_src.clkr.hw,
	1134	+ },
	1135	+ .num_parents = 1,
	1136	+ .flags = CLK_SET_RATE_PARENT,
	1137	+ .ops = &clk_branch2_ops,
	1138	+ },
	1139	+ },
	1140	+};
	1141	+
	1142	+static struct clk_branch gcc_pcie_d_pipe_clk = {
	1143	+ .halt_reg = 0x4c068,
	1144	+ .halt_check = BRANCH_HALT_VOTED,
	1145	+ .clkr = {
	1146	+ .enable_reg = 0x9d010,
	1147	+ .enable_mask = BIT(10),
	1148	+ .hw.init = &(const struct clk_init_data) {
	1149	+ .name = "gcc_pcie_d_pipe_clk",
	1150	+ .parent_hws = (const struct clk_hw*[]) {
	1151	+ &gcc_pcie_d_pipe_clk_src.clkr.hw,
	1152	+ },
	1153	+ .num_parents = 1,
	1154	+ .flags = CLK_SET_RATE_PARENT,
	1155	+ .ops = &clk_branch2_ops,
	1156	+ },
	1157	+ },
	1158	+};
	1159	+
	1160	+static struct clk_branch gcc_pcie_d_slv_axi_clk = {
	1161	+ .halt_reg = 0x4c02c,
	1162	+ .halt_check = BRANCH_HALT_VOTED,
	1163	+ .hwcg_reg = 0x4c02c,
	1164	+ .hwcg_bit = 1,
	1165	+ .clkr = {
	1166	+ .enable_reg = 0x9d010,
	1167	+ .enable_mask = BIT(6),
	1168	+ .hw.init = &(const struct clk_init_data) {
	1169	+ .name = "gcc_pcie_d_slv_axi_clk",
	1170	+ .ops = &clk_branch2_ops,
	1171	+ },
	1172	+ },
	1173	+};
	1174	+
	1175	+static struct clk_branch gcc_pcie_d_slv_q2a_axi_clk = {
	1176	+ .halt_reg = 0x4c024,
	1177	+ .halt_check = BRANCH_HALT_VOTED,
	1178	+ .clkr = {
	1179	+ .enable_reg = 0x9d010,
	1180	+ .enable_mask = BIT(5),
	1181	+ .hw.init = &(const struct clk_init_data) {
	1182	+ .name = "gcc_pcie_d_slv_q2a_axi_clk",
	1183	+ .ops = &clk_branch2_ops,
	1184	+ },
	1185	+ },
	1186	+};
	1187	+
	1188	+static struct clk_branch gcc_pcie_link_ahb_clk = {
	1189	+ .halt_reg = 0x52464,
	1190	+ .halt_check = BRANCH_HALT,
	1191	+ .clkr = {
	1192	+ .enable_reg = 0x52464,
	1193	+ .enable_mask = BIT(0),
	1194	+ .hw.init = &(const struct clk_init_data) {
	1195	+ .name = "gcc_pcie_link_ahb_clk",
	1196	+ .ops = &clk_branch2_ops,
	1197	+ },
	1198	+ },
	1199	+};
	1200	+
	1201	+static struct clk_branch gcc_pcie_link_xo_clk = {
	1202	+ .halt_reg = 0x52468,
	1203	+ .halt_check = BRANCH_HALT_VOTED,
	1204	+ .hwcg_reg = 0x52468,
	1205	+ .hwcg_bit = 1,
	1206	+ .clkr = {
	1207	+ .enable_reg = 0x52468,
	1208	+ .enable_mask = BIT(0),
	1209	+ .hw.init = &(const struct clk_init_data) {
	1210	+ .name = "gcc_pcie_link_xo_clk",
	1211	+ .ops = &clk_branch2_ops,
	1212	+ },
	1213	+ },
	1214	+};
	1215	+
	1216	+static struct clk_branch gcc_pcie_noc_async_bridge_clk = {
	1217	+ .halt_reg = 0x52048,
	1218	+ .halt_check = BRANCH_HALT_SKIP,
	1219	+ .hwcg_reg = 0x52048,
	1220	+ .hwcg_bit = 1,
	1221	+ .clkr = {
	1222	+ .enable_reg = 0x9d018,
	1223	+ .enable_mask = BIT(18),
	1224	+ .hw.init = &(const struct clk_init_data) {
	1225	+ .name = "gcc_pcie_noc_async_bridge_clk",
	1226	+ .ops = &clk_branch2_ops,
	1227	+ },
	1228	+ },
	1229	+};
	1230	+
	1231	+static struct clk_branch gcc_pcie_noc_cnoc_sf_qx_clk = {
	1232	+ .halt_reg = 0x52040,
	1233	+ .halt_check = BRANCH_HALT_VOTED,
	1234	+ .hwcg_reg = 0x52040,
	1235	+ .hwcg_bit = 1,
	1236	+ .clkr = {
	1237	+ .enable_reg = 0x9d010,
	1238	+ .enable_mask = BIT(24),
	1239	+ .hw.init = &(const struct clk_init_data) {
	1240	+ .name = "gcc_pcie_noc_cnoc_sf_qx_clk",
	1241	+ .ops = &clk_branch2_ops,
	1242	+ },
	1243	+ },
	1244	+};
	1245	+
	1246	+static struct clk_branch gcc_pcie_noc_m_cfg_clk = {
	1247	+ .halt_reg = 0x52060,
	1248	+ .halt_check = BRANCH_HALT_VOTED,
	1249	+ .hwcg_reg = 0x52060,
	1250	+ .hwcg_bit = 1,
	1251	+ .clkr = {
	1252	+ .enable_reg = 0x9d018,
	1253	+ .enable_mask = BIT(4),
	1254	+ .hw.init = &(const struct clk_init_data) {
	1255	+ .name = "gcc_pcie_noc_m_cfg_clk",
	1256	+ .ops = &clk_branch2_ops,
	1257	+ },
	1258	+ },
	1259	+};
	1260	+
	1261	+static struct clk_branch gcc_pcie_noc_m_pdb_clk = {
	1262	+ .halt_reg = 0x52084,
	1263	+ .halt_check = BRANCH_HALT_VOTED,
	1264	+ .hwcg_reg = 0x52084,
	1265	+ .hwcg_bit = 1,
	1266	+ .clkr = {
	1267	+ .enable_reg = 0x9d018,
	1268	+ .enable_mask = BIT(8),
	1269	+ .hw.init = &(const struct clk_init_data) {
	1270	+ .name = "gcc_pcie_noc_m_pdb_clk",
	1271	+ .ops = &clk_branch2_ops,
	1272	+ },
	1273	+ },
	1274	+};
	1275	+
	1276	+static struct clk_branch gcc_pcie_noc_mstr_axi_clk = {
	1277	+ .halt_reg = 0x52050,
	1278	+ .halt_check = BRANCH_HALT_SKIP,
	1279	+ .hwcg_reg = 0x52050,
	1280	+ .hwcg_bit = 1,
	1281	+ .clkr = {
	1282	+ .enable_reg = 0x9d010,
	1283	+ .enable_mask = BIT(25),
	1284	+ .hw.init = &(const struct clk_init_data) {
	1285	+ .name = "gcc_pcie_noc_mstr_axi_clk",
	1286	+ .ops = &clk_branch2_ops,
	1287	+ },
	1288	+ },
	1289	+};
	1290	+
	1291	+static struct clk_branch gcc_pcie_noc_pwrctl_clk = {
	1292	+ .halt_reg = 0x52080,
	1293	+ .halt_check = BRANCH_HALT_VOTED,
	1294	+ .clkr = {
	1295	+ .enable_reg = 0x9d018,
	1296	+ .enable_mask = BIT(7),
	1297	+ .hw.init = &(const struct clk_init_data) {
	1298	+ .name = "gcc_pcie_noc_pwrctl_clk",
	1299	+ .ops = &clk_branch2_ops,
	1300	+ },
	1301	+ },
	1302	+};
	1303	+
	1304	+static struct clk_branch gcc_pcie_noc_qosgen_extref_clk = {
	1305	+ .halt_reg = 0x52074,
	1306	+ .halt_check = BRANCH_HALT_VOTED,
	1307	+ .clkr = {
	1308	+ .enable_reg = 0x9d010,
	1309	+ .enable_mask = BIT(19),
	1310	+ .hw.init = &(const struct clk_init_data) {
	1311	+ .name = "gcc_pcie_noc_qosgen_extref_clk",
	1312	+ .ops = &clk_branch2_ops,
	1313	+ },
	1314	+ },
	1315	+};
	1316	+
	1317	+static struct clk_branch gcc_pcie_noc_refgen_clk = {
	1318	+ .halt_reg = 0x52078,
	1319	+ .halt_check = BRANCH_HALT,
	1320	+ .clkr = {
	1321	+ .enable_reg = 0x52078,
	1322	+ .enable_mask = BIT(0),
	1323	+ .hw.init = &(const struct clk_init_data) {
	1324	+ .name = "gcc_pcie_noc_refgen_clk",
	1325	+ .parent_hws = (const struct clk_hw*[]) {
	1326	+ &gcc_pcie_noc_refgen_clk_src.clkr.hw,
	1327	+ },
	1328	+ .num_parents = 1,
	1329	+ .flags = CLK_SET_RATE_PARENT,
	1330	+ .ops = &clk_branch2_ops,
	1331	+ },
	1332	+ },
	1333	+};
	1334	+
	1335	+static struct clk_branch gcc_pcie_noc_s_cfg_clk = {
	1336	+ .halt_reg = 0x52064,
	1337	+ .halt_check = BRANCH_HALT_VOTED,
	1338	+ .clkr = {
	1339	+ .enable_reg = 0x9d018,
	1340	+ .enable_mask = BIT(5),
	1341	+ .hw.init = &(const struct clk_init_data) {
	1342	+ .name = "gcc_pcie_noc_s_cfg_clk",
	1343	+ .ops = &clk_branch2_ops,
	1344	+ },
	1345	+ },
	1346	+};
	1347	+
	1348	+static struct clk_branch gcc_pcie_noc_s_pdb_clk = {
	1349	+ .halt_reg = 0x5208c,
	1350	+ .halt_check = BRANCH_HALT_VOTED,
	1351	+ .hwcg_reg = 0x5208c,
	1352	+ .hwcg_bit = 1,
	1353	+ .clkr = {
	1354	+ .enable_reg = 0x9d018,
	1355	+ .enable_mask = BIT(9),
	1356	+ .hw.init = &(const struct clk_init_data) {
	1357	+ .name = "gcc_pcie_noc_s_pdb_clk",
	1358	+ .ops = &clk_branch2_ops,
	1359	+ },
	1360	+ },
	1361	+};
	1362	+
	1363	+static struct clk_branch gcc_pcie_noc_safety_clk = {
	1364	+ .halt_reg = 0x5207c,
	1365	+ .halt_check = BRANCH_HALT,
	1366	+ .clkr = {
	1367	+ .enable_reg = 0x5207c,
	1368	+ .enable_mask = BIT(0),
	1369	+ .hw.init = &(const struct clk_init_data) {
	1370	+ .name = "gcc_pcie_noc_safety_clk",
	1371	+ .parent_hws = (const struct clk_hw*[]) {
	1372	+ &gcc_pcie_noc_safety_clk_src.clkr.hw,
	1373	+ },
	1374	+ .num_parents = 1,
	1375	+ .flags = CLK_SET_RATE_PARENT,
	1376	+ .ops = &clk_branch2_ops,
	1377	+ },
	1378	+ },
	1379	+};
	1380	+
	1381	+static struct clk_branch gcc_pcie_noc_slave_axi_clk = {
	1382	+ .halt_reg = 0x52058,
	1383	+ .halt_check = BRANCH_HALT_VOTED,
	1384	+ .hwcg_reg = 0x52058,
	1385	+ .hwcg_bit = 1,
	1386	+ .clkr = {
	1387	+ .enable_reg = 0x9d010,
	1388	+ .enable_mask = BIT(26),
	1389	+ .hw.init = &(const struct clk_init_data) {
	1390	+ .name = "gcc_pcie_noc_slave_axi_clk",
	1391	+ .ops = &clk_branch2_ops,
	1392	+ },
	1393	+ },
	1394	+};
	1395	+
	1396	+static struct clk_branch gcc_pcie_noc_tsctr_clk = {
	1397	+ .halt_reg = 0x52070,
	1398	+ .halt_check = BRANCH_HALT_VOTED,
	1399	+ .clkr = {
	1400	+ .enable_reg = 0x9d010,
	1401	+ .enable_mask = BIT(18),
	1402	+ .hw.init = &(const struct clk_init_data) {
	1403	+ .name = "gcc_pcie_noc_tsctr_clk",
	1404	+ .ops = &clk_branch2_ops,
	1405	+ },
	1406	+ },
	1407	+};
	1408	+
	1409	+static struct clk_branch gcc_pcie_noc_xo_clk = {
	1410	+ .halt_reg = 0x52068,
	1411	+ .halt_check = BRANCH_HALT_VOTED,
	1412	+ .clkr = {
	1413	+ .enable_reg = 0x9d018,
	1414	+ .enable_mask = BIT(6),
	1415	+ .hw.init = &(const struct clk_init_data) {
	1416	+ .name = "gcc_pcie_noc_xo_clk",
	1417	+ .ops = &clk_branch2_ops,
	1418	+ },
	1419	+ },
	1420	+};
	1421	+
	1422	+static struct clk_branch gcc_pdm2_clk = {
	1423	+ .halt_reg = 0x1a00c,
	1424	+ .halt_check = BRANCH_HALT,
	1425	+ .clkr = {
	1426	+ .enable_reg = 0x1a00c,
	1427	+ .enable_mask = BIT(0),
	1428	+ .hw.init = &(const struct clk_init_data) {
	1429	+ .name = "gcc_pdm2_clk",
	1430	+ .parent_hws = (const struct clk_hw*[]) {
	1431	+ &gcc_pdm2_clk_src.clkr.hw,
	1432	+ },
	1433	+ .num_parents = 1,
	1434	+ .flags = CLK_SET_RATE_PARENT,
	1435	+ .ops = &clk_branch2_ops,
	1436	+ },
	1437	+ },
	1438	+};
	1439	+
	1440	+static struct clk_branch gcc_pdm_ahb_clk = {
	1441	+ .halt_reg = 0x1a004,
	1442	+ .halt_check = BRANCH_HALT_VOTED,
	1443	+ .hwcg_reg = 0x1a004,
	1444	+ .hwcg_bit = 1,
	1445	+ .clkr = {
	1446	+ .enable_reg = 0x1a004,
	1447	+ .enable_mask = BIT(0),
	1448	+ .hw.init = &(const struct clk_init_data) {
	1449	+ .name = "gcc_pdm_ahb_clk",
	1450	+ .ops = &clk_branch2_ops,
	1451	+ },
	1452	+ },
	1453	+};
	1454	+
	1455	+static struct clk_branch gcc_pdm_xo4_clk = {
	1456	+ .halt_reg = 0x1a008,
	1457	+ .halt_check = BRANCH_HALT,
	1458	+ .clkr = {
	1459	+ .enable_reg = 0x1a008,
	1460	+ .enable_mask = BIT(0),
	1461	+ .hw.init = &(const struct clk_init_data) {
	1462	+ .name = "gcc_pdm_xo4_clk",
	1463	+ .ops = &clk_branch2_ops,
	1464	+ },
	1465	+ },
	1466	+};
	1467	+
	1468	+static struct clk_branch gcc_qupv3_wrap3_core_2x_clk = {
	1469	+ .halt_reg = 0x23020,
	1470	+ .halt_check = BRANCH_HALT_VOTED,
	1471	+ .clkr = {
	1472	+ .enable_reg = 0x9d000,
	1473	+ .enable_mask = BIT(24),
	1474	+ .hw.init = &(const struct clk_init_data) {
	1475	+ .name = "gcc_qupv3_wrap3_core_2x_clk",
	1476	+ .ops = &clk_branch2_ops,
	1477	+ },
	1478	+ },
	1479	+};
	1480	+
	1481	+static struct clk_branch gcc_qupv3_wrap3_core_clk = {
	1482	+ .halt_reg = 0x2300c,
	1483	+ .halt_check = BRANCH_HALT_VOTED,
	1484	+ .clkr = {
	1485	+ .enable_reg = 0x9d000,
	1486	+ .enable_mask = BIT(23),
	1487	+ .hw.init = &(const struct clk_init_data) {
	1488	+ .name = "gcc_qupv3_wrap3_core_clk",
	1489	+ .ops = &clk_branch2_ops,
	1490	+ },
	1491	+ },
	1492	+};
	1493	+
	1494	+static struct clk_branch gcc_qupv3_wrap3_m_clk = {
	1495	+ .halt_reg = 0x23004,
	1496	+ .halt_check = BRANCH_HALT_VOTED,
	1497	+ .hwcg_reg = 0x23004,
	1498	+ .hwcg_bit = 1,
	1499	+ .clkr = {
	1500	+ .enable_reg = 0x9d000,
	1501	+ .enable_mask = BIT(22),
	1502	+ .hw.init = &(const struct clk_init_data) {
	1503	+ .name = "gcc_qupv3_wrap3_m_clk",
	1504	+ .ops = &clk_branch2_ops,
	1505	+ },
	1506	+ },
	1507	+};
	1508	+
	1509	+static struct clk_branch gcc_qupv3_wrap3_qspi_ref_clk = {
	1510	+ .halt_reg = 0x23170,
	1511	+ .halt_check = BRANCH_HALT_VOTED,
	1512	+ .clkr = {
	1513	+ .enable_reg = 0x9d000,
	1514	+ .enable_mask = BIT(26),
	1515	+ .hw.init = &(const struct clk_init_data) {
	1516	+ .name = "gcc_qupv3_wrap3_qspi_ref_clk",
	1517	+ .parent_hws = (const struct clk_hw*[]) {
	1518	+ &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr.hw,
	1519	+ },
	1520	+ .num_parents = 1,
	1521	+ .flags = CLK_SET_RATE_PARENT,
	1522	+ .ops = &clk_branch2_ops,
	1523	+ },
	1524	+ },
	1525	+};
	1526	+
	1527	+static struct clk_branch gcc_qupv3_wrap3_s0_clk = {
	1528	+ .halt_reg = 0x2315c,
	1529	+ .halt_check = BRANCH_HALT_VOTED,
	1530	+ .clkr = {
	1531	+ .enable_reg = 0x9d000,
	1532	+ .enable_mask = BIT(25),
	1533	+ .hw.init = &(const struct clk_init_data) {
	1534	+ .name = "gcc_qupv3_wrap3_s0_clk",
	1535	+ .parent_hws = (const struct clk_hw*[]) {
	1536	+ &gcc_qupv3_wrap3_s0_clk_src.clkr.hw,
	1537	+ },
	1538	+ .num_parents = 1,
	1539	+ .flags = CLK_SET_RATE_PARENT,
	1540	+ .ops = &clk_branch2_ops,
	1541	+ },
	1542	+ },
	1543	+};
	1544	+
	1545	+static struct clk_branch gcc_qupv3_wrap3_s_ahb_clk = {
	1546	+ .halt_reg = 0x23008,
	1547	+ .halt_check = BRANCH_HALT_VOTED,
	1548	+ .hwcg_reg = 0x23008,
	1549	+ .hwcg_bit = 1,
	1550	+ .clkr = {
	1551	+ .enable_reg = 0x9d010,
	1552	+ .enable_mask = BIT(15),
	1553	+ .hw.init = &(const struct clk_init_data) {
	1554	+ .name = "gcc_qupv3_wrap3_s_ahb_clk",
	1555	+ .ops = &clk_branch2_ops,
	1556	+ },
	1557	+ },
	1558	+};
	1559	+
	1560	+static struct clk_branch gcc_smmu_pcie_qtc_vote_clk = {
	1561	+ .halt_reg = 0x7d0b8,
	1562	+ .halt_check = BRANCH_HALT_VOTED,
	1563	+ .clkr = {
	1564	+ .enable_reg = 0x7d0b8,
	1565	+ .enable_mask = BIT(0),
	1566	+ .hw.init = &(const struct clk_init_data) {
	1567	+ .name = "gcc_smmu_pcie_qtc_vote_clk",
	1568	+ .ops = &clk_branch2_ops,
	1569	+ },
	1570	+ },
	1571	+};
	1572	+
	1573	+static struct gdsc gcc_pcie_a_gdsc = {
	1574	+ .gdscr = 0x49004,
	1575	+ .en_rest_wait_val = 0x2,
	1576	+ .en_few_wait_val = 0x2,
	1577	+ .clk_dis_wait_val = 0xf,
	1578	+ .collapse_ctrl = 0x8d02c,
	1579	+ .collapse_mask = BIT(1),
	1580	+ .pd = {
	1581	+ .name = "gcc_pcie_a_gdsc",
	1582	+ },
	1583	+ .pwrsts = PWRSTS_OFF_ON,
	1584	+ .flags = POLL_CFG_GDSCR \| RETAIN_FF_ENABLE \| VOTABLE,
	1585	+};
	1586	+
	1587	+static struct gdsc gcc_pcie_a_phy_gdsc = {
	1588	+ .gdscr = 0x4d004,
	1589	+ .en_rest_wait_val = 0x2,
	1590	+ .en_few_wait_val = 0x2,
	1591	+ .clk_dis_wait_val = 0x2,
	1592	+ .collapse_ctrl = 0x8d02c,
	1593	+ .collapse_mask = BIT(5),
	1594	+ .pd = {
	1595	+ .name = "gcc_pcie_a_phy_gdsc",
	1596	+ },
	1597	+ .pwrsts = PWRSTS_OFF_ON,
	1598	+ .flags = POLL_CFG_GDSCR \| RETAIN_FF_ENABLE \| VOTABLE,
	1599	+};
	1600	+
	1601	+static struct gdsc gcc_pcie_b_gdsc = {
	1602	+ .gdscr = 0x4a004,
	1603	+ .en_rest_wait_val = 0x2,
	1604	+ .en_few_wait_val = 0x2,
	1605	+ .clk_dis_wait_val = 0xf,
	1606	+ .collapse_ctrl = 0x8d02c,
	1607	+ .collapse_mask = BIT(2),
	1608	+ .pd = {
	1609	+ .name = "gcc_pcie_b_gdsc",
	1610	+ },
	1611	+ .pwrsts = PWRSTS_OFF_ON,
	1612	+ .flags = POLL_CFG_GDSCR \| RETAIN_FF_ENABLE \| VOTABLE,
	1613	+};
	1614	+
	1615	+static struct gdsc gcc_pcie_b_phy_gdsc = {
	1616	+ .gdscr = 0x4e004,
	1617	+ .en_rest_wait_val = 0x2,
	1618	+ .en_few_wait_val = 0x2,
	1619	+ .clk_dis_wait_val = 0x2,
	1620	+ .collapse_ctrl = 0x8d02c,
	1621	+ .collapse_mask = BIT(6),
	1622	+ .pd = {
	1623	+ .name = "gcc_pcie_b_phy_gdsc",
	1624	+ },
	1625	+ .pwrsts = PWRSTS_OFF_ON,
	1626	+ .flags = POLL_CFG_GDSCR \| RETAIN_FF_ENABLE \| VOTABLE,
	1627	+};
	1628	+
	1629	+static struct gdsc gcc_pcie_c_gdsc = {
	1630	+ .gdscr = 0x4b004,
	1631	+ .en_rest_wait_val = 0x2,
	1632	+ .en_few_wait_val = 0x2,
	1633	+ .clk_dis_wait_val = 0xf,
	1634	+ .collapse_ctrl = 0x8d02c,
	1635	+ .collapse_mask = BIT(3),
	1636	+ .pd = {
	1637	+ .name = "gcc_pcie_c_gdsc",
	1638	+ },
	1639	+ .pwrsts = PWRSTS_OFF_ON,
	1640	+ .flags = POLL_CFG_GDSCR \| RETAIN_FF_ENABLE \| VOTABLE,
	1641	+};
	1642	+
	1643	+static struct gdsc gcc_pcie_c_phy_gdsc = {
	1644	+ .gdscr = 0x4f004,
	1645	+ .en_rest_wait_val = 0x2,
	1646	+ .en_few_wait_val = 0x2,
	1647	+ .clk_dis_wait_val = 0x2,
	1648	+ .collapse_ctrl = 0x8d02c,
	1649	+ .collapse_mask = BIT(7),
	1650	+ .pd = {
	1651	+ .name = "gcc_pcie_c_phy_gdsc",
	1652	+ },
	1653	+ .pwrsts = PWRSTS_OFF_ON,
	1654	+ .flags = POLL_CFG_GDSCR \| RETAIN_FF_ENABLE \| VOTABLE,
	1655	+};
	1656	+
	1657	+static struct gdsc gcc_pcie_d_gdsc = {
	1658	+ .gdscr = 0x4c004,
	1659	+ .en_rest_wait_val = 0x2,
	1660	+ .en_few_wait_val = 0x2,
	1661	+ .clk_dis_wait_val = 0xf,
	1662	+ .collapse_ctrl = 0x8d02c,
	1663	+ .collapse_mask = BIT(4),
	1664	+ .pd = {
	1665	+ .name = "gcc_pcie_d_gdsc",
	1666	+ },
	1667	+ .pwrsts = PWRSTS_OFF_ON,
	1668	+ .flags = POLL_CFG_GDSCR \| RETAIN_FF_ENABLE \| VOTABLE,
	1669	+};
	1670	+
	1671	+static struct gdsc gcc_pcie_d_phy_gdsc = {
	1672	+ .gdscr = 0x50004,
	1673	+ .en_rest_wait_val = 0x2,
	1674	+ .en_few_wait_val = 0x2,
	1675	+ .clk_dis_wait_val = 0x2,
	1676	+ .collapse_ctrl = 0x8d02c,
	1677	+ .collapse_mask = BIT(8),
	1678	+ .pd = {
	1679	+ .name = "gcc_pcie_d_phy_gdsc",
	1680	+ },
	1681	+ .pwrsts = PWRSTS_OFF_ON,
	1682	+ .flags = POLL_CFG_GDSCR \| RETAIN_FF_ENABLE \| VOTABLE,
	1683	+};
	1684	+
	1685	+static struct gdsc gcc_pcie_noc_gdsc = {
	1686	+ .gdscr = 0x52004,
	1687	+ .gds_hw_ctrl = 0x52018,
	1688	+ .en_rest_wait_val = 0x2,
	1689	+ .en_few_wait_val = 0x2,
	1690	+ .clk_dis_wait_val = 0xf,
	1691	+ .collapse_ctrl = 0x8d02c,
	1692	+ .collapse_mask = BIT(0),
	1693	+ .pd = {
	1694	+ .name = "gcc_pcie_noc_gdsc",
	1695	+ },
	1696	+ .pwrsts = PWRSTS_OFF_ON,
	1697	+ .flags = POLL_CFG_GDSCR \| RETAIN_FF_ENABLE \| VOTABLE,
	1698	+};
	1699	+
	1700	+static struct clk_regmap *gcc_nord_clocks[] = {
	1701	+ [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
	1702	+ [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
	1703	+ [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
	1704	+ [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
	1705	+ [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
	1706	+ [GCC_GPLL0] = &gcc_gpll0.clkr,
	1707	+ [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
	1708	+ [GCC_MMU_0_TCU_VOTE_CLK] = &gcc_mmu_0_tcu_vote_clk.clkr,
	1709	+ [GCC_PCIE_A_AUX_CLK] = &gcc_pcie_a_aux_clk.clkr,
	1710	+ [GCC_PCIE_A_AUX_CLK_SRC] = &gcc_pcie_a_aux_clk_src.clkr,
	1711	+ [GCC_PCIE_A_CFG_AHB_CLK] = &gcc_pcie_a_cfg_ahb_clk.clkr,
	1712	+ [GCC_PCIE_A_DTI_QTC_CLK] = &gcc_pcie_a_dti_qtc_clk.clkr,
	1713	+ [GCC_PCIE_A_MSTR_AXI_CLK] = &gcc_pcie_a_mstr_axi_clk.clkr,
	1714	+ [GCC_PCIE_A_PHY_AUX_CLK] = &gcc_pcie_a_phy_aux_clk.clkr,
	1715	+ [GCC_PCIE_A_PHY_AUX_CLK_SRC] = &gcc_pcie_a_phy_aux_clk_src.clkr,
	1716	+ [GCC_PCIE_A_PHY_RCHNG_CLK] = &gcc_pcie_a_phy_rchng_clk.clkr,
	1717	+ [GCC_PCIE_A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_a_phy_rchng_clk_src.clkr,
	1718	+ [GCC_PCIE_A_PIPE_CLK] = &gcc_pcie_a_pipe_clk.clkr,
	1719	+ [GCC_PCIE_A_PIPE_CLK_SRC] = &gcc_pcie_a_pipe_clk_src.clkr,
	1720	+ [GCC_PCIE_A_SLV_AXI_CLK] = &gcc_pcie_a_slv_axi_clk.clkr,
	1721	+ [GCC_PCIE_A_SLV_Q2A_AXI_CLK] = &gcc_pcie_a_slv_q2a_axi_clk.clkr,
	1722	+ [GCC_PCIE_B_AUX_CLK] = &gcc_pcie_b_aux_clk.clkr,
	1723	+ [GCC_PCIE_B_AUX_CLK_SRC] = &gcc_pcie_b_aux_clk_src.clkr,
	1724	+ [GCC_PCIE_B_CFG_AHB_CLK] = &gcc_pcie_b_cfg_ahb_clk.clkr,
	1725	+ [GCC_PCIE_B_DTI_QTC_CLK] = &gcc_pcie_b_dti_qtc_clk.clkr,
	1726	+ [GCC_PCIE_B_MSTR_AXI_CLK] = &gcc_pcie_b_mstr_axi_clk.clkr,
	1727	+ [GCC_PCIE_B_PHY_AUX_CLK] = &gcc_pcie_b_phy_aux_clk.clkr,
	1728	+ [GCC_PCIE_B_PHY_AUX_CLK_SRC] = &gcc_pcie_b_phy_aux_clk_src.clkr,
	1729	+ [GCC_PCIE_B_PHY_RCHNG_CLK] = &gcc_pcie_b_phy_rchng_clk.clkr,
	1730	+ [GCC_PCIE_B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_b_phy_rchng_clk_src.clkr,
	1731	+ [GCC_PCIE_B_PIPE_CLK] = &gcc_pcie_b_pipe_clk.clkr,
	1732	+ [GCC_PCIE_B_PIPE_CLK_SRC] = &gcc_pcie_b_pipe_clk_src.clkr,
	1733	+ [GCC_PCIE_B_SLV_AXI_CLK] = &gcc_pcie_b_slv_axi_clk.clkr,
	1734	+ [GCC_PCIE_B_SLV_Q2A_AXI_CLK] = &gcc_pcie_b_slv_q2a_axi_clk.clkr,
	1735	+ [GCC_PCIE_C_AUX_CLK] = &gcc_pcie_c_aux_clk.clkr,
	1736	+ [GCC_PCIE_C_AUX_CLK_SRC] = &gcc_pcie_c_aux_clk_src.clkr,
	1737	+ [GCC_PCIE_C_CFG_AHB_CLK] = &gcc_pcie_c_cfg_ahb_clk.clkr,
	1738	+ [GCC_PCIE_C_DTI_QTC_CLK] = &gcc_pcie_c_dti_qtc_clk.clkr,
	1739	+ [GCC_PCIE_C_MSTR_AXI_CLK] = &gcc_pcie_c_mstr_axi_clk.clkr,
	1740	+ [GCC_PCIE_C_PHY_AUX_CLK] = &gcc_pcie_c_phy_aux_clk.clkr,
	1741	+ [GCC_PCIE_C_PHY_AUX_CLK_SRC] = &gcc_pcie_c_phy_aux_clk_src.clkr,
	1742	+ [GCC_PCIE_C_PHY_RCHNG_CLK] = &gcc_pcie_c_phy_rchng_clk.clkr,
	1743	+ [GCC_PCIE_C_PHY_RCHNG_CLK_SRC] = &gcc_pcie_c_phy_rchng_clk_src.clkr,
	1744	+ [GCC_PCIE_C_PIPE_CLK] = &gcc_pcie_c_pipe_clk.clkr,
	1745	+ [GCC_PCIE_C_PIPE_CLK_SRC] = &gcc_pcie_c_pipe_clk_src.clkr,
	1746	+ [GCC_PCIE_C_SLV_AXI_CLK] = &gcc_pcie_c_slv_axi_clk.clkr,
	1747	+ [GCC_PCIE_C_SLV_Q2A_AXI_CLK] = &gcc_pcie_c_slv_q2a_axi_clk.clkr,
	1748	+ [GCC_PCIE_D_AUX_CLK] = &gcc_pcie_d_aux_clk.clkr,
	1749	+ [GCC_PCIE_D_AUX_CLK_SRC] = &gcc_pcie_d_aux_clk_src.clkr,
	1750	+ [GCC_PCIE_D_CFG_AHB_CLK] = &gcc_pcie_d_cfg_ahb_clk.clkr,
	1751	+ [GCC_PCIE_D_DTI_QTC_CLK] = &gcc_pcie_d_dti_qtc_clk.clkr,
	1752	+ [GCC_PCIE_D_MSTR_AXI_CLK] = &gcc_pcie_d_mstr_axi_clk.clkr,
	1753	+ [GCC_PCIE_D_PHY_AUX_CLK] = &gcc_pcie_d_phy_aux_clk.clkr,
	1754	+ [GCC_PCIE_D_PHY_AUX_CLK_SRC] = &gcc_pcie_d_phy_aux_clk_src.clkr,
	1755	+ [GCC_PCIE_D_PHY_RCHNG_CLK] = &gcc_pcie_d_phy_rchng_clk.clkr,
	1756	+ [GCC_PCIE_D_PHY_RCHNG_CLK_SRC] = &gcc_pcie_d_phy_rchng_clk_src.clkr,
	1757	+ [GCC_PCIE_D_PIPE_CLK] = &gcc_pcie_d_pipe_clk.clkr,
	1758	+ [GCC_PCIE_D_PIPE_CLK_SRC] = &gcc_pcie_d_pipe_clk_src.clkr,
	1759	+ [GCC_PCIE_D_SLV_AXI_CLK] = &gcc_pcie_d_slv_axi_clk.clkr,
	1760	+ [GCC_PCIE_D_SLV_Q2A_AXI_CLK] = &gcc_pcie_d_slv_q2a_axi_clk.clkr,
	1761	+ [GCC_PCIE_LINK_AHB_CLK] = &gcc_pcie_link_ahb_clk.clkr,
	1762	+ [GCC_PCIE_LINK_XO_CLK] = &gcc_pcie_link_xo_clk.clkr,
	1763	+ [GCC_PCIE_NOC_ASYNC_BRIDGE_CLK] = &gcc_pcie_noc_async_bridge_clk.clkr,
	1764	+ [GCC_PCIE_NOC_CNOC_SF_QX_CLK] = &gcc_pcie_noc_cnoc_sf_qx_clk.clkr,
	1765	+ [GCC_PCIE_NOC_M_CFG_CLK] = &gcc_pcie_noc_m_cfg_clk.clkr,
	1766	+ [GCC_PCIE_NOC_M_PDB_CLK] = &gcc_pcie_noc_m_pdb_clk.clkr,
	1767	+ [GCC_PCIE_NOC_MSTR_AXI_CLK] = &gcc_pcie_noc_mstr_axi_clk.clkr,
	1768	+ [GCC_PCIE_NOC_PWRCTL_CLK] = &gcc_pcie_noc_pwrctl_clk.clkr,
	1769	+ [GCC_PCIE_NOC_QOSGEN_EXTREF_CLK] = &gcc_pcie_noc_qosgen_extref_clk.clkr,
	1770	+ [GCC_PCIE_NOC_REFGEN_CLK] = &gcc_pcie_noc_refgen_clk.clkr,
	1771	+ [GCC_PCIE_NOC_REFGEN_CLK_SRC] = &gcc_pcie_noc_refgen_clk_src.clkr,
	1772	+ [GCC_PCIE_NOC_S_CFG_CLK] = &gcc_pcie_noc_s_cfg_clk.clkr,
	1773	+ [GCC_PCIE_NOC_S_PDB_CLK] = &gcc_pcie_noc_s_pdb_clk.clkr,
	1774	+ [GCC_PCIE_NOC_SAFETY_CLK] = &gcc_pcie_noc_safety_clk.clkr,
	1775	+ [GCC_PCIE_NOC_SAFETY_CLK_SRC] = &gcc_pcie_noc_safety_clk_src.clkr,
	1776	+ [GCC_PCIE_NOC_SLAVE_AXI_CLK] = &gcc_pcie_noc_slave_axi_clk.clkr,
	1777	+ [GCC_PCIE_NOC_TSCTR_CLK] = &gcc_pcie_noc_tsctr_clk.clkr,
	1778	+ [GCC_PCIE_NOC_XO_CLK] = &gcc_pcie_noc_xo_clk.clkr,
	1779	+ [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
	1780	+ [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
	1781	+ [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
	1782	+ [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
	1783	+ [GCC_QUPV3_WRAP3_CORE_2X_CLK] = &gcc_qupv3_wrap3_core_2x_clk.clkr,
	1784	+ [GCC_QUPV3_WRAP3_CORE_CLK] = &gcc_qupv3_wrap3_core_clk.clkr,
	1785	+ [GCC_QUPV3_WRAP3_M_CLK] = &gcc_qupv3_wrap3_m_clk.clkr,
	1786	+ [GCC_QUPV3_WRAP3_QSPI_REF_CLK] = &gcc_qupv3_wrap3_qspi_ref_clk.clkr,
	1787	+ [GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr,
	1788	+ [GCC_QUPV3_WRAP3_S0_CLK] = &gcc_qupv3_wrap3_s0_clk.clkr,
	1789	+ [GCC_QUPV3_WRAP3_S0_CLK_SRC] = &gcc_qupv3_wrap3_s0_clk_src.clkr,
	1790	+ [GCC_QUPV3_WRAP3_S_AHB_CLK] = &gcc_qupv3_wrap3_s_ahb_clk.clkr,
	1791	+ [GCC_SMMU_PCIE_QTC_VOTE_CLK] = &gcc_smmu_pcie_qtc_vote_clk.clkr,
	1792	+};
	1793	+
	1794	+static struct gdsc *gcc_nord_gdscs[] = {
	1795	+ [GCC_PCIE_A_GDSC] = &gcc_pcie_a_gdsc,
	1796	+ [GCC_PCIE_A_PHY_GDSC] = &gcc_pcie_a_phy_gdsc,
	1797	+ [GCC_PCIE_B_GDSC] = &gcc_pcie_b_gdsc,
	1798	+ [GCC_PCIE_B_PHY_GDSC] = &gcc_pcie_b_phy_gdsc,
	1799	+ [GCC_PCIE_C_GDSC] = &gcc_pcie_c_gdsc,
	1800	+ [GCC_PCIE_C_PHY_GDSC] = &gcc_pcie_c_phy_gdsc,
	1801	+ [GCC_PCIE_D_GDSC] = &gcc_pcie_d_gdsc,
	1802	+ [GCC_PCIE_D_PHY_GDSC] = &gcc_pcie_d_phy_gdsc,
	1803	+ [GCC_PCIE_NOC_GDSC] = &gcc_pcie_noc_gdsc,
	1804	+};
	1805	+
	1806	+static const struct qcom_reset_map gcc_nord_resets[] = {
	1807	+ [GCC_PCIE_A_BCR] = { 0x49000 },
	1808	+ [GCC_PCIE_A_LINK_DOWN_BCR] = { 0xb9000 },
	1809	+ [GCC_PCIE_A_NOCSR_COM_PHY_BCR] = { 0xb900c },
	1810	+ [GCC_PCIE_A_PHY_BCR] = { 0x4d000 },
	1811	+ [GCC_PCIE_A_PHY_CFG_AHB_BCR] = { 0xb9014 },
	1812	+ [GCC_PCIE_A_PHY_COM_BCR] = { 0xb9018 },
	1813	+ [GCC_PCIE_A_PHY_NOCSR_COM_PHY_BCR] = { 0xb9010 },
	1814	+ [GCC_PCIE_B_BCR] = { 0x4a000 },
	1815	+ [GCC_PCIE_B_LINK_DOWN_BCR] = { 0xba000 },
	1816	+ [GCC_PCIE_B_NOCSR_COM_PHY_BCR] = { 0xba008 },
	1817	+ [GCC_PCIE_B_PHY_BCR] = { 0x4e000 },
	1818	+ [GCC_PCIE_B_PHY_CFG_AHB_BCR] = { 0xba010 },
	1819	+ [GCC_PCIE_B_PHY_COM_BCR] = { 0xba014 },
	1820	+ [GCC_PCIE_B_PHY_NOCSR_COM_PHY_BCR] = { 0xba00c },
	1821	+ [GCC_PCIE_C_BCR] = { 0x4b000 },
	1822	+ [GCC_PCIE_C_LINK_DOWN_BCR] = { 0xbb07c },
	1823	+ [GCC_PCIE_C_NOCSR_COM_PHY_BCR] = { 0xbb084 },
	1824	+ [GCC_PCIE_C_PHY_BCR] = { 0x4f000 },
	1825	+ [GCC_PCIE_C_PHY_CFG_AHB_BCR] = { 0xbb08c },
	1826	+ [GCC_PCIE_C_PHY_COM_BCR] = { 0xbb090 },
	1827	+ [GCC_PCIE_C_PHY_NOCSR_COM_PHY_BCR] = { 0xbb088 },
	1828	+ [GCC_PCIE_D_BCR] = { 0x4c000 },
	1829	+ [GCC_PCIE_D_LINK_DOWN_BCR] = { 0xbc000 },
	1830	+ [GCC_PCIE_D_NOCSR_COM_PHY_BCR] = { 0xbc008 },
	1831	+ [GCC_PCIE_D_PHY_BCR] = { 0x50000 },
	1832	+ [GCC_PCIE_D_PHY_CFG_AHB_BCR] = { 0xbc010 },
	1833	+ [GCC_PCIE_D_PHY_COM_BCR] = { 0xbc014 },
	1834	+ [GCC_PCIE_D_PHY_NOCSR_COM_PHY_BCR] = { 0xbc00c },
	1835	+ [GCC_PCIE_NOC_BCR] = { 0x52000 },
	1836	+ [GCC_PDM_BCR] = { 0x1a000 },
	1837	+ [GCC_QUPV3_WRAPPER_3_BCR] = { 0x23000 },
	1838	+ [GCC_TCSR_PCIE_BCR] = { 0xb901c },
	1839	+};
	1840	+
	1841	+static const struct clk_rcg_dfs_data gcc_nord_dfs_clocks[] = {
	1842	+ DEFINE_RCG_DFS(gcc_qupv3_wrap3_qspi_ref_clk_src),
	1843	+};
	1844	+
	1845	+static const struct regmap_config gcc_nord_regmap_config = {
	1846	+ .reg_bits = 32,
	1847	+ .reg_stride = 4,
	1848	+ .val_bits = 32,
	1849	+ .max_register = 0x1f41f0,
	1850	+ .fast_io = true,
	1851	+};
	1852	+
	1853	+static struct qcom_cc_driver_data gcc_nord_driver_data = {
	1854	+ .dfs_rcgs = gcc_nord_dfs_clocks,
	1855	+ .num_dfs_rcgs = ARRAY_SIZE(gcc_nord_dfs_clocks),
	1856	+};
	1857	+
	1858	+static const struct qcom_cc_desc gcc_nord_desc = {
	1859	+ .config = &gcc_nord_regmap_config,
	1860	+ .clks = gcc_nord_clocks,
	1861	+ .num_clks = ARRAY_SIZE(gcc_nord_clocks),
	1862	+ .resets = gcc_nord_resets,
	1863	+ .num_resets = ARRAY_SIZE(gcc_nord_resets),
	1864	+ .gdscs = gcc_nord_gdscs,
	1865	+ .num_gdscs = ARRAY_SIZE(gcc_nord_gdscs),
	1866	+ .use_rpm = true,
	1867	+ .driver_data = &gcc_nord_driver_data,
	1868	+};
	1869	+
	1870	+static const struct of_device_id gcc_nord_match_table[] = {
	1871	+ { .compatible = "qcom,nord-gcc" },
	1872	+ { }
	1873	+};
	1874	+MODULE_DEVICE_TABLE(of, gcc_nord_match_table);
	1875	+
	1876	+static int gcc_nord_probe(struct platform_device *pdev)
	1877	+{
	1878	+ return qcom_cc_probe(pdev, &gcc_nord_desc);
	1879	+}
	1880	+
	1881	+static struct platform_driver gcc_nord_driver = {
	1882	+ .probe = gcc_nord_probe,
	1883	+ .driver = {
	1884	+ .name = "gcc-nord",
	1885	+ .of_match_table = gcc_nord_match_table,
	1886	+ },
	1887	+};
	1888	+
	1889	+static int __init gcc_nord_init(void)
	1890	+{
	1891	+ return platform_driver_register(&gcc_nord_driver);
	1892	+}
	1893	+subsys_initcall(gcc_nord_init);
	1894	+
	1895	+static void __exit gcc_nord_exit(void)
	1896	+{
	1897	+ platform_driver_unregister(&gcc_nord_driver);
	1898	+}
	1899	+module_exit(gcc_nord_exit);
	1900	+
	1901	+MODULE_DESCRIPTION("QTI GCC NORD Driver");
	1902	+MODULE_LICENSE("GPL");

drivers/clk/qcom/gcc-sc8180x.c+89−37

@@ -4172,7 +4172,7 @@ static struct gdsc usb30_sec_gdsc = { · 4171 unmodified lines
4172	4172	.pd = {
4173	4173	.name = "usb30_sec_gdsc",
4174	4174	},
4175		− .pwrsts = PWRSTS_OFF_ON,
	4175	+ .pwrsts = PWRSTS_RET_ON,
4176	4176	.flags = POLL_CFG_GDSCR,
4177	4177	};
4178	4178
@@ -4190,7 +4190,7 @@ static struct gdsc usb30_prim_gdsc = { · 11 unmodified lines
4190	4190	.pd = {
4191	4191	.name = "usb30_prim_gdsc",
4192	4192	},
4193		− .pwrsts = PWRSTS_OFF_ON,
	4193	+ .pwrsts = PWRSTS_RET_ON,
4194	4194	.flags = POLL_CFG_GDSCR,
4195	4195	};
4196	4196
@@ -4199,7 +4199,7 @@ static struct gdsc pcie_0_gdsc = { · 2 unmodified lines
4199	4199	.pd = {
4200	4200	.name = "pcie_0_gdsc",
4201	4201	},
4202		− .pwrsts = PWRSTS_OFF_ON,
	4202	+ .pwrsts = PWRSTS_RET_ON,
4203	4203	.flags = POLL_CFG_GDSCR,
4204	4204	};
4205	4205
@@ -4226,7 +4226,7 @@ static struct gdsc pcie_1_gdsc = { · 20 unmodified lines
4226	4226	.pd = {
4227	4227	.name = "pcie_1_gdsc",
4228	4228	},
4229		− .pwrsts = PWRSTS_OFF_ON,
	4229	+ .pwrsts = PWRSTS_RET_ON,
4230	4230	.flags = POLL_CFG_GDSCR,
4231	4231	};
4232	4232
@@ -4235,7 +4235,7 @@ static struct gdsc pcie_2_gdsc = { · 2 unmodified lines
4235	4235	.pd = {
4236	4236	.name = "pcie_2_gdsc",
4237	4237	},
4238		− .pwrsts = PWRSTS_OFF_ON,
	4238	+ .pwrsts = PWRSTS_RET_ON,
4239	4239	.flags = POLL_CFG_GDSCR,
4240	4240	};
4241	4241
@@ -4253,7 +4253,7 @@ static struct gdsc pcie_3_gdsc = { · 11 unmodified lines
4253	4253	.pd = {
4254	4254	.name = "pcie_3_gdsc",
4255	4255	},
4256		− .pwrsts = PWRSTS_OFF_ON,
	4256	+ .pwrsts = PWRSTS_RET_ON,
4257	4257	.flags = POLL_CFG_GDSCR,
4258	4258	};
4259	4259
@@ -4262,10 +4262,55 @@ static struct gdsc usb30_mp_gdsc = { · 2 unmodified lines
4262	4262	.pd = {
4263	4263	.name = "usb30_mp_gdsc",
4264	4264	},
4265		− .pwrsts = PWRSTS_OFF_ON,
	4265	+ .pwrsts = PWRSTS_RET_ON,
4266	4266	.flags = POLL_CFG_GDSCR,
4267	4267	};
4268	4268
	4269	+static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
	4270	+ .gdscr = 0x7d050,
	4271	+ .pd = {
	4272	+ .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
	4273	+ },
	4274	+ .pwrsts = PWRSTS_OFF_ON,
	4275	+ .flags = VOTABLE,
	4276	+};
	4277	+
	4278	+static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
	4279	+ .gdscr = 0x7d058,
	4280	+ .pd = {
	4281	+ .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
	4282	+ },
	4283	+ .pwrsts = PWRSTS_OFF_ON,
	4284	+ .flags = VOTABLE,
	4285	+};
	4286	+
	4287	+static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
	4288	+ .gdscr = 0x7d054,
	4289	+ .pd = {
	4290	+ .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
	4291	+ },
	4292	+ .pwrsts = PWRSTS_OFF_ON,
	4293	+ .flags = VOTABLE,
	4294	+};
	4295	+
	4296	+static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {
	4297	+ .gdscr = 0x7d05c,
	4298	+ .pd = {
	4299	+ .name = "hlos1_vote_turing_mmu_tbu0_gdsc",
	4300	+ },
	4301	+ .pwrsts = PWRSTS_OFF_ON,
	4302	+ .flags = VOTABLE,
	4303	+};
	4304	+
	4305	+static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {
	4306	+ .gdscr = 0x7d060,
	4307	+ .pd = {
	4308	+ .name = "hlos1_vote_turing_mmu_tbu1_gdsc",
	4309	+ },
	4310	+ .pwrsts = PWRSTS_OFF_ON,
	4311	+ .flags = VOTABLE,
	4312	+};
	4313	+
4269	4314	static struct clk_regmap *gcc_sc8180x_clocks[] = {
4270	4315	[GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
4271	4316	[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
@@ -4560,7 +4605,7 @@ static const struct qcom_reset_map gcc_sc8180x_resets[] = { · 288 unmodified lines
4560	4605	[GCC_VIDEO_AXI1_CLK_BCR] = { .reg = 0xb028, .bit = 2, .udelay = 150 },
4561	4606	};
4562	4607
4563		−static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
	4608	+static const struct clk_rcg_dfs_data gcc_sc8180x_dfs_clocks[] = {
4564	4609	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
4565	4610	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
4566	4611	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
@@ -4595,6 +4640,24 @@ static struct gdsc *gcc_sc8180x_gdscs[] = { · 28 unmodified lines
4595	4640	[USB30_MP_GDSC] = &usb30_mp_gdsc,
4596	4641	[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
4597	4642	[USB30_SEC_GDSC] = &usb30_sec_gdsc,
	4643	+ [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
	4644	+ [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
	4645	+ [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
	4646	+ [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,
	4647	+ [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
	4648	+};
	4649	+
	4650	+static const u32 gcc_sc8180x_critical_cbcrs[] = {
	4651	+ 0xb004, /* GCC_VIDEO_AHB_CLK */
	4652	+ 0xb008, /* GCC_CAMERA_AHB_CLK */
	4653	+ 0xb00c, /* GCC_DISP_AHB_CLK */
	4654	+ 0xb040, /* GCC_VIDEO_XO_CLK */
	4655	+ 0xb044, /* GCC_CAMERA_XO_CLK */
	4656	+ 0xb048, /* GCC_DISP_XO_CLK */
	4657	+ 0x48004, /* GCC_CPUSS_GNOC_CLK */
	4658	+ 0x48190, /* GCC_CPUSS_DVM_BUS_CLK */
	4659	+ 0x4d004, /* GCC_NPU_CFG_AHB_CLK */
	4660	+ 0x71004, /* GCC_GPU_CFG_AHB_CLK */
4598	4661	};
4599	4662
4600	4663	static const struct regmap_config gcc_sc8180x_regmap_config = {
@@ -4605,6 +4668,21 @@ static const struct regmap_config gcc_sc8180x_regmap_config = { · 4 unmodified lines
4605	4668	.fast_io = true,
4606	4669	};
4607	4670
	4671	+static void clk_sc8180x_regs_configure(struct device dev, struct regmap regmap)
	4672	+{
	4673	+ /* Disable the GPLL0 active input to NPU and GPU via MISC registers */
	4674	+ regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
	4675	+ regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
	4676	+}
	4677	+
	4678	+static const struct qcom_cc_driver_data gcc_sc8180x_driver_data = {
	4679	+ .clk_cbcrs = gcc_sc8180x_critical_cbcrs,
	4680	+ .num_clk_cbcrs = ARRAY_SIZE(gcc_sc8180x_critical_cbcrs),
	4681	+ .dfs_rcgs = gcc_sc8180x_dfs_clocks,
	4682	+ .num_dfs_rcgs = ARRAY_SIZE(gcc_sc8180x_dfs_clocks),
	4683	+ .clk_regs_configure = clk_sc8180x_regs_configure,
	4684	+};
	4685	+
4608	4686	static const struct qcom_cc_desc gcc_sc8180x_desc = {
4609	4687	.config = &gcc_sc8180x_regmap_config,
4610	4688	.clks = gcc_sc8180x_clocks,
@@ -4613,6 +4691,8 @@ static const struct qcom_cc_desc gcc_sc8180x_desc = { · 2 unmodified lines
4613	4691	.num_resets = ARRAY_SIZE(gcc_sc8180x_resets),
4614	4692	.gdscs = gcc_sc8180x_gdscs,
4615	4693	.num_gdscs = ARRAY_SIZE(gcc_sc8180x_gdscs),
	4694	+ .use_rpm = true,
	4695	+ .driver_data = &gcc_sc8180x_driver_data,
4616	4696	};
4617	4697
4618	4698	static const struct of_device_id gcc_sc8180x_match_table[] = {
@@ -4623,35 +4703,7 @@ MODULE_DEVICE_TABLE(of, gcc_sc8180x_match_table); · 4 unmodified lines
4623	4703
4624	4704	static int gcc_sc8180x_probe(struct platform_device *pdev)
4625	4705	{
4626		− struct regmap *regmap;
4627		− int ret;
4628		−
4629		− regmap = qcom_cc_map(pdev, &gcc_sc8180x_desc);
4630		− if (IS_ERR(regmap))
4631		− return PTR_ERR(regmap);
4632		−
4633		− /* Keep some clocks always-on */
4634		− qcom_branch_set_clk_en(regmap, 0xb004); /* GCC_VIDEO_AHB_CLK */
4635		− qcom_branch_set_clk_en(regmap, 0xb008); /* GCC_CAMERA_AHB_CLK */
4636		− qcom_branch_set_clk_en(regmap, 0xb00c); /* GCC_DISP_AHB_CLK */
4637		− qcom_branch_set_clk_en(regmap, 0xb040); /* GCC_VIDEO_XO_CLK */
4638		− qcom_branch_set_clk_en(regmap, 0xb044); /* GCC_CAMERA_XO_CLK */
4639		− qcom_branch_set_clk_en(regmap, 0xb048); /* GCC_DISP_XO_CLK */
4640		− qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */
4641		− qcom_branch_set_clk_en(regmap, 0x48190); /* GCC_CPUSS_DVM_BUS_CLK */
4642		− qcom_branch_set_clk_en(regmap, 0x4d004); /* GCC_NPU_CFG_AHB_CLK */
4643		− qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
4644		−
4645		− /* Disable the GPLL0 active input to NPU and GPU via MISC registers */
4646		− regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
4647		− regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
4648		−
4649		− ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
4650		− ARRAY_SIZE(gcc_dfs_clocks));
4651		− if (ret)
4652		− return ret;
4653		−
4654		− return qcom_cc_really_probe(&pdev->dev, &gcc_sc8180x_desc, regmap);
	4706	+ return qcom_cc_probe(pdev, &gcc_sc8180x_desc);
4655	4707	}
4656	4708
4657	4709	static struct platform_driver gcc_sc8180x_driver = {

drivers/clk/qcom/gcc-x1e80100.c+1−0

@@ -7480,6 +7480,7 @@ static int gcc_x1e80100_probe(struct platform_device *pdev) · 7479 unmodified lines
7480	7480	qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */
7481	7481	qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */
7482	7482	qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
	7483	+ qcom_branch_set_clk_en(regmap, 0x7d01c); /* GCC_HLOS1_VOTE_AGGRE_NOC_MMU_USB_QTB_CLK */
7483	7484
7484	7485	/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
7485	7486	regmap_write(regmap, 0x52224, 0x0);

drivers/clk/qcom/gdsc.c+11−1

@@ -518,10 +518,20 @@ static int gdsc_add_subdomain_list(struct dev_pm_domain_list *pd_list, · 517 unmodified lines
518	518
519	519	ret = pm_genpd_add_subdomain(genpd, subdomain);
520	520	if (ret)
521		− return ret;
	521	+ goto remove_added_subdomains;
522	522	}
523	523
524	524	return 0;
	525	+
	526	+remove_added_subdomains:
	527	+ for (i--; i >= 0; i--) {
	528	+ struct device *dev = pd_list->pd_devs[i];
	529	+ struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain);
	530	+
	531	+ pm_genpd_remove_subdomain(genpd, subdomain);
	532	+ }
	533	+
	534	+ return ret;
525	535	}
526	536
527	537	static void gdsc_remove_subdomain_list(struct dev_pm_domain_list *pd_list,

drivers/clk/qcom/gpucc-glymur.c+618−0

@@ -0,0 +1,618 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
	2	+/*
	3	+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
	4	+ */
	5	+
	6	+#include <linux/clk-provider.h>
	7	+#include <linux/mod_devicetable.h>
	8	+#include <linux/module.h>
	9	+#include <linux/platform_device.h>
	10	+#include <linux/regmap.h>
	11	+
	12	+#include <dt-bindings/clock/qcom,glymur-gpucc.h>
	13	+
	14	+#include "clk-alpha-pll.h"
	15	+#include "clk-branch.h"
	16	+#include "clk-pll.h"
	17	+#include "clk-rcg.h"
	18	+#include "clk-regmap.h"
	19	+#include "clk-regmap-divider.h"
	20	+#include "clk-regmap-mux.h"
	21	+#include "common.h"
	22	+#include "gdsc.h"
	23	+#include "reset.h"
	24	+
	25	+enum {
	26	+ DT_BI_TCXO,
	27	+ DT_GPLL0_OUT_MAIN,
	28	+ DT_GPLL0_OUT_MAIN_DIV,
	29	+};
	30	+
	31	+enum {
	32	+ P_BI_TCXO,
	33	+ P_GPLL0_OUT_MAIN,
	34	+ P_GPLL0_OUT_MAIN_DIV,
	35	+ P_GPU_CC_PLL0_OUT_EVEN,
	36	+ P_GPU_CC_PLL0_OUT_MAIN,
	37	+ P_GPU_CC_PLL0_OUT_ODD,
	38	+};
	39	+
	40	+static const struct pll_vco taycan_eko_t_vco[] = {
	41	+ { 249600000, 2500000000, 0 },
	42	+};
	43	+
	44	+/* 1150.0 MHz Configuration */
	45	+static const struct alpha_pll_config gpu_cc_pll0_config = {
	46	+ .l = 0x3b,
	47	+ .alpha = 0xe555,
	48	+ .config_ctl_val = 0x25c400e7,
	49	+ .config_ctl_hi_val = 0x0a8060e0,
	50	+ .config_ctl_hi1_val = 0xf51dea20,
	51	+ .user_ctl_val = 0x00000408,
	52	+ .user_ctl_hi_val = 0x00000002,
	53	+};
	54	+
	55	+static struct clk_alpha_pll gpu_cc_pll0 = {
	56	+ .offset = 0x0,
	57	+ .config = &gpu_cc_pll0_config,
	58	+ .vco_table = taycan_eko_t_vco,
	59	+ .num_vco = ARRAY_SIZE(taycan_eko_t_vco),
	60	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
	61	+ .clkr = {
	62	+ .hw.init = &(const struct clk_init_data) {
	63	+ .name = "gpu_cc_pll0",
	64	+ .parent_data = &(const struct clk_parent_data) {
	65	+ .index = DT_BI_TCXO,
	66	+ },
	67	+ .num_parents = 1,
	68	+ .ops = &clk_alpha_pll_taycan_eko_t_ops,
	69	+ },
	70	+ },
	71	+};
	72	+
	73	+static const struct clk_div_table post_div_table_gpu_cc_pll0_out_even[] = {
	74	+ { 0x1, 2 },
	75	+ { }
	76	+};
	77	+
	78	+static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_even = {
	79	+ .offset = 0x0,
	80	+ .post_div_shift = 10,
	81	+ .post_div_table = post_div_table_gpu_cc_pll0_out_even,
	82	+ .num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_even),
	83	+ .width = 4,
	84	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
	85	+ .clkr.hw.init = &(const struct clk_init_data) {
	86	+ .name = "gpu_cc_pll0_out_even",
	87	+ .parent_hws = (const struct clk_hw*[]) {
	88	+ &gpu_cc_pll0.clkr.hw,
	89	+ },
	90	+ .num_parents = 1,
	91	+ .flags = CLK_SET_RATE_PARENT,
	92	+ .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops,
	93	+ },
	94	+};
	95	+
	96	+static const struct parent_map gpu_cc_parent_map_0[] = {
	97	+ { P_BI_TCXO, 0 },
	98	+ { P_GPLL0_OUT_MAIN, 5 },
	99	+ { P_GPLL0_OUT_MAIN_DIV, 6 },
	100	+};
	101	+
	102	+static const struct clk_parent_data gpu_cc_parent_data_0[] = {
	103	+ { .index = DT_BI_TCXO },
	104	+ { .index = DT_GPLL0_OUT_MAIN },
	105	+ { .index = DT_GPLL0_OUT_MAIN_DIV },
	106	+};
	107	+
	108	+static const struct parent_map gpu_cc_parent_map_1[] = {
	109	+ { P_BI_TCXO, 0 },
	110	+ { P_GPU_CC_PLL0_OUT_MAIN, 1 },
	111	+ { P_GPU_CC_PLL0_OUT_EVEN, 2 },
	112	+ { P_GPU_CC_PLL0_OUT_ODD, 3 },
	113	+ { P_GPLL0_OUT_MAIN, 5 },
	114	+ { P_GPLL0_OUT_MAIN_DIV, 6 },
	115	+};
	116	+
	117	+static const struct clk_parent_data gpu_cc_parent_data_1[] = {
	118	+ { .index = DT_BI_TCXO },
	119	+ { .hw = &gpu_cc_pll0.clkr.hw },
	120	+ { .hw = &gpu_cc_pll0_out_even.clkr.hw },
	121	+ { .hw = &gpu_cc_pll0.clkr.hw },
	122	+ { .index = DT_GPLL0_OUT_MAIN },
	123	+ { .index = DT_GPLL0_OUT_MAIN_DIV },
	124	+};
	125	+
	126	+static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
	127	+ F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
	128	+ { }
	129	+};
	130	+
	131	+static struct clk_rcg2 gpu_cc_ff_clk_src = {
	132	+ .cmd_rcgr = 0x9474,
	133	+ .mnd_width = 0,
	134	+ .hid_width = 5,
	135	+ .parent_map = gpu_cc_parent_map_0,
	136	+ .freq_tbl = ftbl_gpu_cc_ff_clk_src,
	137	+ .clkr.hw.init = &(const struct clk_init_data) {
	138	+ .name = "gpu_cc_ff_clk_src",
	139	+ .parent_data = gpu_cc_parent_data_0,
	140	+ .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
	141	+ .flags = CLK_SET_RATE_PARENT,
	142	+ .ops = &clk_rcg2_shared_ops,
	143	+ },
	144	+};
	145	+
	146	+static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
	147	+ F(19200000, P_BI_TCXO, 1, 0, 0),
	148	+ F(575000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
	149	+ F(700000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
	150	+ F(725000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
	151	+ F(750000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
	152	+ { }
	153	+};
	154	+
	155	+static struct clk_rcg2 gpu_cc_gmu_clk_src = {
	156	+ .cmd_rcgr = 0x9318,
	157	+ .mnd_width = 0,
	158	+ .hid_width = 5,
	159	+ .parent_map = gpu_cc_parent_map_1,
	160	+ .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
	161	+ .clkr.hw.init = &(const struct clk_init_data) {
	162	+ .name = "gpu_cc_gmu_clk_src",
	163	+ .parent_data = gpu_cc_parent_data_1,
	164	+ .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
	165	+ .flags = CLK_SET_RATE_PARENT,
	166	+ .ops = &clk_rcg2_shared_ops,
	167	+ },
	168	+};
	169	+
	170	+static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
	171	+ F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
	172	+ F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
	173	+ F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
	174	+ { }
	175	+};
	176	+
	177	+static struct clk_rcg2 gpu_cc_hub_clk_src = {
	178	+ .cmd_rcgr = 0x93f0,
	179	+ .mnd_width = 0,
	180	+ .hid_width = 5,
	181	+ .parent_map = gpu_cc_parent_map_1,
	182	+ .freq_tbl = ftbl_gpu_cc_hub_clk_src,
	183	+ .clkr.hw.init = &(const struct clk_init_data) {
	184	+ .name = "gpu_cc_hub_clk_src",
	185	+ .parent_data = gpu_cc_parent_data_1,
	186	+ .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
	187	+ .flags = CLK_SET_RATE_PARENT,
	188	+ .ops = &clk_rcg2_shared_ops,
	189	+ },
	190	+};
	191	+
	192	+static struct clk_regmap_div gpu_cc_hub_div_clk_src = {
	193	+ .reg = 0x9430,
	194	+ .shift = 0,
	195	+ .width = 4,
	196	+ .clkr.hw.init = &(const struct clk_init_data) {
	197	+ .name = "gpu_cc_hub_div_clk_src",
	198	+ .parent_hws = (const struct clk_hw*[]) {
	199	+ &gpu_cc_hub_clk_src.clkr.hw,
	200	+ },
	201	+ .num_parents = 1,
	202	+ .flags = CLK_SET_RATE_PARENT,
	203	+ .ops = &clk_regmap_div_ro_ops,
	204	+ },
	205	+};
	206	+
	207	+static struct clk_branch gpu_cc_ahb_clk = {
	208	+ .halt_reg = 0x90bc,
	209	+ .halt_check = BRANCH_HALT_DELAY,
	210	+ .clkr = {
	211	+ .enable_reg = 0x90bc,
	212	+ .enable_mask = BIT(0),
	213	+ .hw.init = &(const struct clk_init_data) {
	214	+ .name = "gpu_cc_ahb_clk",
	215	+ .parent_hws = (const struct clk_hw*[]) {
	216	+ &gpu_cc_hub_div_clk_src.clkr.hw,
	217	+ },
	218	+ .num_parents = 1,
	219	+ .flags = CLK_SET_RATE_PARENT,
	220	+ .ops = &clk_branch2_ops,
	221	+ },
	222	+ },
	223	+};
	224	+
	225	+static struct clk_branch gpu_cc_cx_accu_shift_clk = {
	226	+ .halt_reg = 0x9108,
	227	+ .halt_check = BRANCH_HALT_VOTED,
	228	+ .clkr = {
	229	+ .enable_reg = 0x9108,
	230	+ .enable_mask = BIT(0),
	231	+ .hw.init = &(const struct clk_init_data) {
	232	+ .name = "gpu_cc_cx_accu_shift_clk",
	233	+ .ops = &clk_branch2_ops,
	234	+ },
	235	+ },
	236	+};
	237	+
	238	+static struct clk_branch gpu_cc_cx_ff_clk = {
	239	+ .halt_reg = 0x90ec,
	240	+ .halt_check = BRANCH_HALT,
	241	+ .clkr = {
	242	+ .enable_reg = 0x90ec,
	243	+ .enable_mask = BIT(0),
	244	+ .hw.init = &(const struct clk_init_data) {
	245	+ .name = "gpu_cc_cx_ff_clk",
	246	+ .parent_hws = (const struct clk_hw*[]) {
	247	+ &gpu_cc_ff_clk_src.clkr.hw,
	248	+ },
	249	+ .num_parents = 1,
	250	+ .flags = CLK_SET_RATE_PARENT,
	251	+ .ops = &clk_branch2_ops,
	252	+ },
	253	+ },
	254	+};
	255	+
	256	+static struct clk_branch gpu_cc_cx_gmu_clk = {
	257	+ .halt_reg = 0x90d4,
	258	+ .halt_check = BRANCH_HALT_VOTED,
	259	+ .clkr = {
	260	+ .enable_reg = 0x90d4,
	261	+ .enable_mask = BIT(0),
	262	+ .hw.init = &(const struct clk_init_data) {
	263	+ .name = "gpu_cc_cx_gmu_clk",
	264	+ .parent_hws = (const struct clk_hw*[]) {
	265	+ &gpu_cc_gmu_clk_src.clkr.hw,
	266	+ },
	267	+ .num_parents = 1,
	268	+ .flags = CLK_SET_RATE_PARENT,
	269	+ .ops = &clk_branch2_aon_ops,
	270	+ },
	271	+ },
	272	+};
	273	+
	274	+static struct clk_branch gpu_cc_cxo_clk = {
	275	+ .halt_reg = 0x90e4,
	276	+ .halt_check = BRANCH_HALT,
	277	+ .clkr = {
	278	+ .enable_reg = 0x90e4,
	279	+ .enable_mask = BIT(0),
	280	+ .hw.init = &(const struct clk_init_data) {
	281	+ .name = "gpu_cc_cxo_clk",
	282	+ .ops = &clk_branch2_ops,
	283	+ },
	284	+ },
	285	+};
	286	+
	287	+static struct clk_branch gpu_cc_demet_clk = {
	288	+ .halt_reg = 0x9010,
	289	+ .halt_check = BRANCH_HALT_VOTED,
	290	+ .clkr = {
	291	+ .enable_reg = 0x9010,
	292	+ .enable_mask = BIT(0),
	293	+ .hw.init = &(const struct clk_init_data) {
	294	+ .name = "gpu_cc_demet_clk",
	295	+ .ops = &clk_branch2_ops,
	296	+ },
	297	+ },
	298	+};
	299	+
	300	+static struct clk_branch gpu_cc_dpm_clk = {
	301	+ .halt_reg = 0x910c,
	302	+ .halt_check = BRANCH_HALT,
	303	+ .clkr = {
	304	+ .enable_reg = 0x910c,
	305	+ .enable_mask = BIT(0),
	306	+ .hw.init = &(const struct clk_init_data) {
	307	+ .name = "gpu_cc_dpm_clk",
	308	+ .ops = &clk_branch2_ops,
	309	+ },
	310	+ },
	311	+};
	312	+
	313	+static struct clk_branch gpu_cc_freq_measure_clk = {
	314	+ .halt_reg = 0x900c,
	315	+ .halt_check = BRANCH_HALT,
	316	+ .clkr = {
	317	+ .enable_reg = 0x900c,
	318	+ .enable_mask = BIT(0),
	319	+ .hw.init = &(const struct clk_init_data) {
	320	+ .name = "gpu_cc_freq_measure_clk",
	321	+ .ops = &clk_branch2_ops,
	322	+ },
	323	+ },
	324	+};
	325	+
	326	+static struct clk_branch gpu_cc_gpu_smmu_vote_clk = {
	327	+ .halt_reg = 0x7000,
	328	+ .halt_check = BRANCH_HALT_VOTED,
	329	+ .clkr = {
	330	+ .enable_reg = 0x7000,
	331	+ .enable_mask = BIT(0),
	332	+ .hw.init = &(const struct clk_init_data) {
	333	+ .name = "gpu_cc_gpu_smmu_vote_clk",
	334	+ .ops = &clk_branch2_ops,
	335	+ },
	336	+ },
	337	+};
	338	+
	339	+static struct clk_branch gpu_cc_gx_accu_shift_clk = {
	340	+ .halt_reg = 0x9070,
	341	+ .halt_check = BRANCH_HALT_VOTED,
	342	+ .clkr = {
	343	+ .enable_reg = 0x9070,
	344	+ .enable_mask = BIT(0),
	345	+ .hw.init = &(const struct clk_init_data) {
	346	+ .name = "gpu_cc_gx_accu_shift_clk",
	347	+ .ops = &clk_branch2_ops,
	348	+ },
	349	+ },
	350	+};
	351	+
	352	+static struct clk_branch gpu_cc_gx_acd_ahb_ff_clk = {
	353	+ .halt_reg = 0x9068,
	354	+ .halt_check = BRANCH_HALT,
	355	+ .clkr = {
	356	+ .enable_reg = 0x9068,
	357	+ .enable_mask = BIT(0),
	358	+ .hw.init = &(const struct clk_init_data) {
	359	+ .name = "gpu_cc_gx_acd_ahb_ff_clk",
	360	+ .parent_hws = (const struct clk_hw*[]) {
	361	+ &gpu_cc_ff_clk_src.clkr.hw,
	362	+ },
	363	+ .num_parents = 1,
	364	+ .flags = CLK_SET_RATE_PARENT,
	365	+ .ops = &clk_branch2_ops,
	366	+ },
	367	+ },
	368	+};
	369	+
	370	+static struct clk_branch gpu_cc_gx_ahb_ff_clk = {
	371	+ .halt_reg = 0x9064,
	372	+ .halt_check = BRANCH_HALT,
	373	+ .clkr = {
	374	+ .enable_reg = 0x9064,
	375	+ .enable_mask = BIT(0),
	376	+ .hw.init = &(const struct clk_init_data) {
	377	+ .name = "gpu_cc_gx_ahb_ff_clk",
	378	+ .parent_hws = (const struct clk_hw*[]) {
	379	+ &gpu_cc_ff_clk_src.clkr.hw,
	380	+ },
	381	+ .num_parents = 1,
	382	+ .flags = CLK_SET_RATE_PARENT,
	383	+ .ops = &clk_branch2_ops,
	384	+ },
	385	+ },
	386	+};
	387	+
	388	+static struct clk_branch gpu_cc_gx_gmu_clk = {
	389	+ .halt_reg = 0x9060,
	390	+ .halt_check = BRANCH_HALT,
	391	+ .clkr = {
	392	+ .enable_reg = 0x9060,
	393	+ .enable_mask = BIT(0),
	394	+ .hw.init = &(const struct clk_init_data) {
	395	+ .name = "gpu_cc_gx_gmu_clk",
	396	+ .parent_hws = (const struct clk_hw*[]) {
	397	+ &gpu_cc_gmu_clk_src.clkr.hw,
	398	+ },
	399	+ .num_parents = 1,
	400	+ .flags = CLK_SET_RATE_PARENT,
	401	+ .ops = &clk_branch2_ops,
	402	+ },
	403	+ },
	404	+};
	405	+
	406	+static struct clk_branch gpu_cc_gx_rcg_ahb_ff_clk = {
	407	+ .halt_reg = 0x906c,
	408	+ .halt_check = BRANCH_HALT_VOTED,
	409	+ .clkr = {
	410	+ .enable_reg = 0x906c,
	411	+ .enable_mask = BIT(0),
	412	+ .hw.init = &(const struct clk_init_data) {
	413	+ .name = "gpu_cc_gx_rcg_ahb_ff_clk",
	414	+ .parent_hws = (const struct clk_hw*[]) {
	415	+ &gpu_cc_ff_clk_src.clkr.hw,
	416	+ },
	417	+ .num_parents = 1,
	418	+ .flags = CLK_SET_RATE_PARENT,
	419	+ .ops = &clk_branch2_ops,
	420	+ },
	421	+ },
	422	+};
	423	+
	424	+static struct clk_branch gpu_cc_hub_aon_clk = {
	425	+ .halt_reg = 0x93ec,
	426	+ .halt_check = BRANCH_HALT_VOTED,
	427	+ .clkr = {
	428	+ .enable_reg = 0x93ec,
	429	+ .enable_mask = BIT(0),
	430	+ .hw.init = &(const struct clk_init_data) {
	431	+ .name = "gpu_cc_hub_aon_clk",
	432	+ .parent_hws = (const struct clk_hw*[]) {
	433	+ &gpu_cc_hub_clk_src.clkr.hw,
	434	+ },
	435	+ .num_parents = 1,
	436	+ .flags = CLK_SET_RATE_PARENT,
	437	+ .ops = &clk_branch2_aon_ops,
	438	+ },
	439	+ },
	440	+};
	441	+
	442	+static struct clk_branch gpu_cc_hub_cx_int_clk = {
	443	+ .halt_reg = 0x90e8,
	444	+ .halt_check = BRANCH_HALT_VOTED,
	445	+ .clkr = {
	446	+ .enable_reg = 0x90e8,
	447	+ .enable_mask = BIT(0),
	448	+ .hw.init = &(const struct clk_init_data) {
	449	+ .name = "gpu_cc_hub_cx_int_clk",
	450	+ .parent_hws = (const struct clk_hw*[]) {
	451	+ &gpu_cc_hub_clk_src.clkr.hw,
	452	+ },
	453	+ .num_parents = 1,
	454	+ .flags = CLK_SET_RATE_PARENT,
	455	+ .ops = &clk_branch2_aon_ops,
	456	+ },
	457	+ },
	458	+};
	459	+
	460	+static struct clk_branch gpu_cc_memnoc_gfx_clk = {
	461	+ .halt_reg = 0x90f0,
	462	+ .halt_check = BRANCH_HALT_VOTED,
	463	+ .clkr = {
	464	+ .enable_reg = 0x90f0,
	465	+ .enable_mask = BIT(0),
	466	+ .hw.init = &(const struct clk_init_data) {
	467	+ .name = "gpu_cc_memnoc_gfx_clk",
	468	+ .ops = &clk_branch2_ops,
	469	+ },
	470	+ },
	471	+};
	472	+
	473	+static struct clk_branch gpu_cc_rscc_hub_aon_clk = {
	474	+ .halt_reg = 0x93e8,
	475	+ .halt_check = BRANCH_HALT,
	476	+ .clkr = {
	477	+ .enable_reg = 0x93e8,
	478	+ .enable_mask = BIT(0),
	479	+ .hw.init = &(const struct clk_init_data) {
	480	+ .name = "gpu_cc_rscc_hub_aon_clk",
	481	+ .parent_hws = (const struct clk_hw*[]) {
	482	+ &gpu_cc_hub_clk_src.clkr.hw,
	483	+ },
	484	+ .num_parents = 1,
	485	+ .flags = CLK_SET_RATE_PARENT,
	486	+ .ops = &clk_branch2_ops,
	487	+ },
	488	+ },
	489	+};
	490	+
	491	+static struct clk_branch gpu_cc_sleep_clk = {
	492	+ .halt_reg = 0x90cc,
	493	+ .halt_check = BRANCH_HALT,
	494	+ .clkr = {
	495	+ .enable_reg = 0x90cc,
	496	+ .enable_mask = BIT(0),
	497	+ .hw.init = &(const struct clk_init_data) {
	498	+ .name = "gpu_cc_sleep_clk",
	499	+ .ops = &clk_branch2_ops,
	500	+ },
	501	+ },
	502	+};
	503	+
	504	+static struct gdsc gpu_cc_cx_gdsc = {
	505	+ .gdscr = 0x9080,
	506	+ .gds_hw_ctrl = 0x9094,
	507	+ .en_rest_wait_val = 0x2,
	508	+ .en_few_wait_val = 0x2,
	509	+ .clk_dis_wait_val = 0xf,
	510	+ .pd = {
	511	+ .name = "gpu_cc_cx_gdsc",
	512	+ },
	513	+ .pwrsts = PWRSTS_OFF_ON,
	514	+ .flags = POLL_CFG_GDSCR \| RETAIN_FF_ENABLE,
	515	+};
	516	+
	517	+static struct clk_regmap *gpu_cc_glymur_clocks[] = {
	518	+ [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
	519	+ [GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr,
	520	+ [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
	521	+ [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
	522	+ [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
	523	+ [GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr,
	524	+ [GPU_CC_DPM_CLK] = &gpu_cc_dpm_clk.clkr,
	525	+ [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
	526	+ [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
	527	+ [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
	528	+ [GPU_CC_GPU_SMMU_VOTE_CLK] = &gpu_cc_gpu_smmu_vote_clk.clkr,
	529	+ [GPU_CC_GX_ACCU_SHIFT_CLK] = &gpu_cc_gx_accu_shift_clk.clkr,
	530	+ [GPU_CC_GX_ACD_AHB_FF_CLK] = &gpu_cc_gx_acd_ahb_ff_clk.clkr,
	531	+ [GPU_CC_GX_AHB_FF_CLK] = &gpu_cc_gx_ahb_ff_clk.clkr,
	532	+ [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
	533	+ [GPU_CC_GX_RCG_AHB_FF_CLK] = &gpu_cc_gx_rcg_ahb_ff_clk.clkr,
	534	+ [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
	535	+ [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
	536	+ [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
	537	+ [GPU_CC_HUB_DIV_CLK_SRC] = &gpu_cc_hub_div_clk_src.clkr,
	538	+ [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
	539	+ [GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
	540	+ [GPU_CC_PLL0_OUT_EVEN] = &gpu_cc_pll0_out_even.clkr,
	541	+ [GPU_CC_RSCC_HUB_AON_CLK] = &gpu_cc_rscc_hub_aon_clk.clkr,
	542	+ [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
	543	+};
	544	+
	545	+static struct gdsc *gpu_cc_glymur_gdscs[] = {
	546	+ [GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc,
	547	+};
	548	+
	549	+static const struct qcom_reset_map gpu_cc_glymur_resets[] = {
	550	+ [GPU_CC_CB_BCR] = { 0x93a0 },
	551	+ [GPU_CC_CX_BCR] = { 0x907c },
	552	+ [GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
	553	+ [GPU_CC_FF_BCR] = { 0x9470 },
	554	+ [GPU_CC_GMU_BCR] = { 0x9314 },
	555	+ [GPU_CC_GX_BCR] = { 0x905c },
	556	+ [GPU_CC_XO_BCR] = { 0x9000 },
	557	+};
	558	+
	559	+static struct clk_alpha_pll *gpu_cc_glymur_plls[] = {
	560	+ &gpu_cc_pll0,
	561	+};
	562	+
	563	+static const u32 gpu_cc_glymur_critical_cbcrs[] = {
	564	+ 0x93a4, /* GPU_CC_CB_CLK */
	565	+ 0x9008, /* GPU_CC_CXO_AON_CLK */
	566	+ 0x9004, /* GPU_CC_RSCC_XO_AON_CLK */
	567	+};
	568	+
	569	+static const struct regmap_config gpu_cc_glymur_regmap_config = {
	570	+ .reg_bits = 32,
	571	+ .reg_stride = 4,
	572	+ .val_bits = 32,
	573	+ .max_register = 0x95e8,
	574	+ .fast_io = true,
	575	+};
	576	+
	577	+static const struct qcom_cc_driver_data gpu_cc_glymur_driver_data = {
	578	+ .alpha_plls = gpu_cc_glymur_plls,
	579	+ .num_alpha_plls = ARRAY_SIZE(gpu_cc_glymur_plls),
	580	+ .clk_cbcrs = gpu_cc_glymur_critical_cbcrs,
	581	+ .num_clk_cbcrs = ARRAY_SIZE(gpu_cc_glymur_critical_cbcrs),
	582	+};
	583	+
	584	+static const struct qcom_cc_desc gpu_cc_glymur_desc = {
	585	+ .config = &gpu_cc_glymur_regmap_config,
	586	+ .clks = gpu_cc_glymur_clocks,
	587	+ .num_clks = ARRAY_SIZE(gpu_cc_glymur_clocks),
	588	+ .resets = gpu_cc_glymur_resets,
	589	+ .num_resets = ARRAY_SIZE(gpu_cc_glymur_resets),
	590	+ .gdscs = gpu_cc_glymur_gdscs,
	591	+ .num_gdscs = ARRAY_SIZE(gpu_cc_glymur_gdscs),
	592	+ .use_rpm = true,
	593	+ .driver_data = &gpu_cc_glymur_driver_data,
	594	+};
	595	+
	596	+static const struct of_device_id gpu_cc_glymur_match_table[] = {
	597	+ { .compatible = "qcom,glymur-gpucc" },
	598	+ { }
	599	+};
	600	+MODULE_DEVICE_TABLE(of, gpu_cc_glymur_match_table);
	601	+
	602	+static int gpu_cc_glymur_probe(struct platform_device *pdev)
	603	+{
	604	+ return qcom_cc_probe(pdev, &gpu_cc_glymur_desc);
	605	+}
	606	+
	607	+static struct platform_driver gpu_cc_glymur_driver = {
	608	+ .probe = gpu_cc_glymur_probe,
	609	+ .driver = {
	610	+ .name = "gpucc-glymur",
	611	+ .of_match_table = gpu_cc_glymur_match_table,
	612	+ },
	613	+};
	614	+
	615	+module_platform_driver(gpu_cc_glymur_driver);
	616	+
	617	+MODULE_DESCRIPTION("QTI GPUCC Glymur Driver");
	618	+MODULE_LICENSE("GPL");

drivers/clk/qcom/gpucc-kaanapali.c+2−3

@@ -6,7 +6,6 @@ · 5 unmodified lines
6	6	#include <linux/clk-provider.h>
7	7	#include <linux/mod_devicetable.h>
8	8	#include <linux/module.h>
9		−#include <linux/of.h>
10	9	#include <linux/platform_device.h>
11	10	#include <linux/regmap.h>
12	11
@@ -424,7 +423,7 @@ static struct clk_alpha_pll *gpu_cc_kaanapali_plls[] = { · 411 unmodified lines
424	423	&gpu_cc_pll0,
425	424	};
426	425
427		−static u32 gpu_cc_kaanapali_critical_cbcrs[] = {
	426	+static const u32 gpu_cc_kaanapali_critical_cbcrs[] = {
428	427	0x9008, /* GPU_CC_CXO_AON_CLK */
429	428	0x93e8, /* GPU_CC_RSCC_HUB_AON_CLK */
430	429	0x9004, /* GPU_CC_RSCC_XO_AON_CLK */
@@ -438,7 +437,7 @@ static const struct regmap_config gpu_cc_kaanapali_regmap_config = { · 7 unmodified lines
438	437	.fast_io = true,
439	438	};
440	439
441		−static struct qcom_cc_driver_data gpu_cc_kaanapali_driver_data = {
	440	+static const struct qcom_cc_driver_data gpu_cc_kaanapali_driver_data = {
442	441	.alpha_plls = gpu_cc_kaanapali_plls,
443	442	.num_alpha_plls = ARRAY_SIZE(gpu_cc_kaanapali_plls),
444	443	.clk_cbcrs = gpu_cc_kaanapali_critical_cbcrs,

drivers/clk/qcom/gpucc-milos.c+2−2

@@ -500,7 +500,7 @@ static struct clk_alpha_pll *gpu_cc_milos_plls[] = { · 499 unmodified lines
500	500	&gpu_cc_pll0,
501	501	};
502	502
503		−static u32 gpu_cc_milos_critical_cbcrs[] = {
	503	+static const u32 gpu_cc_milos_critical_cbcrs[] = {
504	504	0x93a4, /* GPU_CC_CB_CLK */
505	505	0x9008, /* GPU_CC_CXO_AON_CLK */
506	506	0x9010, /* GPU_CC_DEMET_CLK */
@@ -518,7 +518,7 @@ static const struct regmap_config gpu_cc_milos_regmap_config = { · 11 unmodified lines
518	518	.fast_io = true,
519	519	};
520	520
521		−static struct qcom_cc_driver_data gpu_cc_milos_driver_data = {
	521	+static const struct qcom_cc_driver_data gpu_cc_milos_driver_data = {
522	522	.alpha_plls = gpu_cc_milos_plls,
523	523	.num_alpha_plls = ARRAY_SIZE(gpu_cc_milos_plls),
524	524	.clk_cbcrs = gpu_cc_milos_critical_cbcrs,

drivers/clk/qcom/gpucc-qcs615.c+2−2

@@ -459,7 +459,7 @@ static struct clk_alpha_pll *gpu_cc_qcs615_plls[] = { · 458 unmodified lines
459	459	&gpu_cc_pll1,
460	460	};
461	461
462		−static u32 gpu_cc_qcs615_critical_cbcrs[] = {
	462	+static const u32 gpu_cc_qcs615_critical_cbcrs[] = {
463	463	0x1078, /* GPU_CC_AHB_CLK */
464	464	};
465	465
@@ -485,7 +485,7 @@ static void clk_qcs615_regs_crc_configure(struct device dev, struct regmap reg · 19 unmodified lines
485	485	regmap_update_bits(regmap, 0x1024, 0x00800000, 0x00800000);
486	486	}
487	487
488		−static struct qcom_cc_driver_data gpu_cc_qcs615_driver_data = {
	488	+static const struct qcom_cc_driver_data gpu_cc_qcs615_driver_data = {
489	489	.alpha_plls = gpu_cc_qcs615_plls,
490	490	.num_alpha_plls = ARRAY_SIZE(gpu_cc_qcs615_plls),
491	491	.clk_cbcrs = gpu_cc_qcs615_critical_cbcrs,

drivers/clk/qcom/gpucc-sm8750.c+473−0

@@ -0,0 +1,473 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
	2	+/*
	3	+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
	4	+ */
	5	+#include <linux/clk-provider.h>
	6	+#include <linux/mod_devicetable.h>
	7	+#include <linux/module.h>
	8	+#include <linux/platform_device.h>
	9	+#include <linux/pm_runtime.h>
	10	+#include <linux/regmap.h>
	11	+
	12	+#include <dt-bindings/clock/qcom,sm8750-gpucc.h>
	13	+
	14	+#include "clk-alpha-pll.h"
	15	+#include "clk-branch.h"
	16	+#include "clk-rcg.h"
	17	+#include "clk-regmap.h"
	18	+#include "clk-regmap-divider.h"
	19	+#include "clk-regmap-mux.h"
	20	+#include "gdsc.h"
	21	+#include "reset.h"
	22	+
	23	+enum {
	24	+ DT_BI_TCXO,
	25	+ DT_GPLL0_OUT_MAIN,
	26	+ DT_GPLL0_OUT_MAIN_DIV,
	27	+};
	28	+
	29	+enum {
	30	+ P_BI_TCXO,
	31	+ P_GPLL0_OUT_MAIN,
	32	+ P_GPLL0_OUT_MAIN_DIV,
	33	+ P_GPU_CC_PLL0_OUT_EVEN,
	34	+ P_GPU_CC_PLL0_OUT_MAIN,
	35	+ P_GPU_CC_PLL0_OUT_ODD,
	36	+};
	37	+
	38	+static const struct pll_vco taycan_elu_vco[] = {
	39	+ { 249600000, 2500000000, 0 },
	40	+};
	41	+
	42	+static const struct alpha_pll_config gpu_cc_pll0_config = {
	43	+ .l = 0x34,
	44	+ .alpha = 0x1555,
	45	+ .config_ctl_val = 0x19660387,
	46	+ .config_ctl_hi_val = 0x098060a0,
	47	+ .config_ctl_hi1_val = 0xb416cb20,
	48	+ .user_ctl_val = 0x00000400,
	49	+ .user_ctl_hi_val = 0x00000002,
	50	+};
	51	+
	52	+static struct clk_alpha_pll gpu_cc_pll0 = {
	53	+ .offset = 0x0,
	54	+ .config = &gpu_cc_pll0_config,
	55	+ .vco_table = taycan_elu_vco,
	56	+ .num_vco = ARRAY_SIZE(taycan_elu_vco),
	57	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU],
	58	+ .clkr = {
	59	+ .hw.init = &(const struct clk_init_data) {
	60	+ .name = "gpu_cc_pll0",
	61	+ .parent_data = &(const struct clk_parent_data) {
	62	+ .index = DT_BI_TCXO,
	63	+ },
	64	+ .num_parents = 1,
	65	+ .ops = &clk_alpha_pll_taycan_elu_ops,
	66	+ },
	67	+ },
	68	+};
	69	+
	70	+static const struct clk_div_table post_div_table_gpu_cc_pll0_out_even[] = {
	71	+ { 0x1, 2 },
	72	+ { }
	73	+};
	74	+
	75	+static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_even = {
	76	+ .offset = 0x0,
	77	+ .post_div_shift = 10,
	78	+ .post_div_table = post_div_table_gpu_cc_pll0_out_even,
	79	+ .num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_even),
	80	+ .width = 4,
	81	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU],
	82	+ .clkr.hw.init = &(const struct clk_init_data) {
	83	+ .name = "gpu_cc_pll0_out_even",
	84	+ .parent_hws = (const struct clk_hw*[]) {
	85	+ &gpu_cc_pll0.clkr.hw,
	86	+ },
	87	+ .num_parents = 1,
	88	+ .flags = CLK_SET_RATE_PARENT,
	89	+ .ops = &clk_alpha_pll_postdiv_taycan_elu_ops,
	90	+ },
	91	+};
	92	+
	93	+static const struct parent_map gpu_cc_parent_map_1[] = {
	94	+ { P_BI_TCXO, 0 },
	95	+ { P_GPU_CC_PLL0_OUT_MAIN, 1 },
	96	+ { P_GPU_CC_PLL0_OUT_EVEN, 2 },
	97	+ { P_GPU_CC_PLL0_OUT_ODD, 3 },
	98	+ { P_GPLL0_OUT_MAIN, 5 },
	99	+ { P_GPLL0_OUT_MAIN_DIV, 6 },
	100	+};
	101	+
	102	+static const struct clk_parent_data gpu_cc_parent_data_1[] = {
	103	+ { .index = DT_BI_TCXO },
	104	+ { .hw = &gpu_cc_pll0.clkr.hw },
	105	+ { .hw = &gpu_cc_pll0_out_even.clkr.hw },
	106	+ { .hw = &gpu_cc_pll0.clkr.hw },
	107	+ { .index = DT_GPLL0_OUT_MAIN },
	108	+ { .index = DT_GPLL0_OUT_MAIN_DIV },
	109	+};
	110	+
	111	+static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
	112	+ F(19200000, P_BI_TCXO, 1, 0, 0),
	113	+ F(500000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
	114	+ F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
	115	+ F(687500000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
	116	+ { }
	117	+};
	118	+
	119	+static struct clk_rcg2 gpu_cc_gmu_clk_src = {
	120	+ .cmd_rcgr = 0x9318,
	121	+ .mnd_width = 0,
	122	+ .hid_width = 5,
	123	+ .parent_map = gpu_cc_parent_map_1,
	124	+ .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
	125	+ .clkr.hw.init = &(const struct clk_init_data) {
	126	+ .name = "gpu_cc_gmu_clk_src",
	127	+ .parent_data = gpu_cc_parent_data_1,
	128	+ .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
	129	+ .flags = CLK_SET_RATE_PARENT,
	130	+ .ops = &clk_rcg2_shared_ops,
	131	+ },
	132	+};
	133	+
	134	+static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
	135	+ F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
	136	+ F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
	137	+ F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
	138	+ { }
	139	+};
	140	+
	141	+static struct clk_rcg2 gpu_cc_hub_clk_src = {
	142	+ .cmd_rcgr = 0x93ec,
	143	+ .mnd_width = 0,
	144	+ .hid_width = 5,
	145	+ .parent_map = gpu_cc_parent_map_1,
	146	+ .freq_tbl = ftbl_gpu_cc_hub_clk_src,
	147	+ .clkr.hw.init = &(const struct clk_init_data) {
	148	+ .name = "gpu_cc_hub_clk_src",
	149	+ .parent_data = gpu_cc_parent_data_1,
	150	+ .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
	151	+ .flags = CLK_SET_RATE_PARENT,
	152	+ .ops = &clk_rcg2_shared_ops,
	153	+ },
	154	+};
	155	+
	156	+static struct clk_regmap_div gpu_cc_hub_div_clk_src = {
	157	+ .reg = 0x942c,
	158	+ .shift = 0,
	159	+ .width = 4,
	160	+ .clkr.hw.init = &(const struct clk_init_data) {
	161	+ .name = "gpu_cc_hub_div_clk_src",
	162	+ .parent_hws = (const struct clk_hw*[]) {
	163	+ &gpu_cc_hub_clk_src.clkr.hw,
	164	+ },
	165	+ .num_parents = 1,
	166	+ .flags = CLK_SET_RATE_PARENT,
	167	+ .ops = &clk_regmap_div_ro_ops,
	168	+ },
	169	+};
	170	+
	171	+static struct clk_branch gpu_cc_ahb_clk = {
	172	+ .halt_reg = 0x90bc,
	173	+ .halt_check = BRANCH_HALT_DELAY,
	174	+ .clkr = {
	175	+ .enable_reg = 0x90bc,
	176	+ .enable_mask = BIT(0),
	177	+ .hw.init = &(const struct clk_init_data) {
	178	+ .name = "gpu_cc_ahb_clk",
	179	+ .parent_hws = (const struct clk_hw*[]) {
	180	+ &gpu_cc_hub_div_clk_src.clkr.hw,
	181	+ },
	182	+ .num_parents = 1,
	183	+ .flags = CLK_SET_RATE_PARENT,
	184	+ .ops = &clk_branch2_ops,
	185	+ },
	186	+ },
	187	+};
	188	+
	189	+static struct clk_branch gpu_cc_cx_accu_shift_clk = {
	190	+ .halt_reg = 0x910c,
	191	+ .halt_check = BRANCH_HALT_VOTED,
	192	+ .clkr = {
	193	+ .enable_reg = 0x910c,
	194	+ .enable_mask = BIT(0),
	195	+ .hw.init = &(const struct clk_init_data) {
	196	+ .name = "gpu_cc_cx_accu_shift_clk",
	197	+ .ops = &clk_branch2_ops,
	198	+ },
	199	+ },
	200	+};
	201	+
	202	+static struct clk_branch gpu_cc_cx_gmu_clk = {
	203	+ .halt_reg = 0x90d4,
	204	+ .halt_check = BRANCH_HALT_VOTED,
	205	+ .clkr = {
	206	+ .enable_reg = 0x90d4,
	207	+ .enable_mask = BIT(0),
	208	+ .hw.init = &(const struct clk_init_data) {
	209	+ .name = "gpu_cc_cx_gmu_clk",
	210	+ .parent_hws = (const struct clk_hw*[]) {
	211	+ &gpu_cc_gmu_clk_src.clkr.hw,
	212	+ },
	213	+ .num_parents = 1,
	214	+ .flags = CLK_SET_RATE_PARENT,
	215	+ .ops = &clk_branch2_aon_ops,
	216	+ },
	217	+ },
	218	+};
	219	+
	220	+static struct clk_branch gpu_cc_cxo_clk = {
	221	+ .halt_reg = 0x90e4,
	222	+ .halt_check = BRANCH_HALT,
	223	+ .clkr = {
	224	+ .enable_reg = 0x90e4,
	225	+ .enable_mask = BIT(0),
	226	+ .hw.init = &(const struct clk_init_data) {
	227	+ .name = "gpu_cc_cxo_clk",
	228	+ .ops = &clk_branch2_ops,
	229	+ },
	230	+ },
	231	+};
	232	+
	233	+static struct clk_branch gpu_cc_demet_clk = {
	234	+ .halt_reg = 0x9010,
	235	+ .halt_check = BRANCH_HALT_VOTED,
	236	+ .clkr = {
	237	+ .enable_reg = 0x9010,
	238	+ .enable_mask = BIT(0),
	239	+ .hw.init = &(const struct clk_init_data) {
	240	+ .name = "gpu_cc_demet_clk",
	241	+ .ops = &clk_branch2_ops,
	242	+ },
	243	+ },
	244	+};
	245	+
	246	+static struct clk_branch gpu_cc_dpm_clk = {
	247	+ .halt_reg = 0x9110,
	248	+ .halt_check = BRANCH_HALT,
	249	+ .clkr = {
	250	+ .enable_reg = 0x9110,
	251	+ .enable_mask = BIT(0),
	252	+ .hw.init = &(const struct clk_init_data) {
	253	+ .name = "gpu_cc_dpm_clk",
	254	+ .ops = &clk_branch2_ops,
	255	+ },
	256	+ },
	257	+};
	258	+
	259	+static struct clk_branch gpu_cc_freq_measure_clk = {
	260	+ .halt_reg = 0x900c,
	261	+ .halt_check = BRANCH_HALT,
	262	+ .clkr = {
	263	+ .enable_reg = 0x900c,
	264	+ .enable_mask = BIT(0),
	265	+ .hw.init = &(const struct clk_init_data) {
	266	+ .name = "gpu_cc_freq_measure_clk",
	267	+ .ops = &clk_branch2_ops,
	268	+ },
	269	+ },
	270	+};
	271	+
	272	+static struct clk_branch gpu_cc_gx_accu_shift_clk = {
	273	+ .halt_reg = 0x9070,
	274	+ .halt_check = BRANCH_HALT_VOTED,
	275	+ .clkr = {
	276	+ .enable_reg = 0x9070,
	277	+ .enable_mask = BIT(0),
	278	+ .hw.init = &(const struct clk_init_data) {
	279	+ .name = "gpu_cc_gx_accu_shift_clk",
	280	+ .ops = &clk_branch2_ops,
	281	+ },
	282	+ },
	283	+};
	284	+
	285	+static struct clk_branch gpu_cc_gx_gmu_clk = {
	286	+ .halt_reg = 0x9060,
	287	+ .halt_check = BRANCH_HALT,
	288	+ .clkr = {
	289	+ .enable_reg = 0x9060,
	290	+ .enable_mask = BIT(0),
	291	+ .hw.init = &(const struct clk_init_data) {
	292	+ .name = "gpu_cc_gx_gmu_clk",
	293	+ .parent_hws = (const struct clk_hw*[]) {
	294	+ &gpu_cc_gmu_clk_src.clkr.hw,
	295	+ },
	296	+ .num_parents = 1,
	297	+ .flags = CLK_SET_RATE_PARENT,
	298	+ .ops = &clk_branch2_ops,
	299	+ },
	300	+ },
	301	+};
	302	+
	303	+static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
	304	+ .halt_reg = 0x7000,
	305	+ .halt_check = BRANCH_HALT_VOTED,
	306	+ .clkr = {
	307	+ .enable_reg = 0x7000,
	308	+ .enable_mask = BIT(0),
	309	+ .hw.init = &(const struct clk_init_data) {
	310	+ .name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
	311	+ .ops = &clk_branch2_ops,
	312	+ },
	313	+ },
	314	+};
	315	+
	316	+static struct clk_branch gpu_cc_hub_aon_clk = {
	317	+ .halt_reg = 0x93e8,
	318	+ .halt_check = BRANCH_HALT_VOTED,
	319	+ .clkr = {
	320	+ .enable_reg = 0x93e8,
	321	+ .enable_mask = BIT(0),
	322	+ .hw.init = &(const struct clk_init_data) {
	323	+ .name = "gpu_cc_hub_aon_clk",
	324	+ .parent_hws = (const struct clk_hw*[]) {
	325	+ &gpu_cc_hub_clk_src.clkr.hw,
	326	+ },
	327	+ .num_parents = 1,
	328	+ .flags = CLK_SET_RATE_PARENT,
	329	+ .ops = &clk_branch2_aon_ops,
	330	+ },
	331	+ },
	332	+};
	333	+
	334	+static struct clk_branch gpu_cc_hub_cx_int_clk = {
	335	+ .halt_reg = 0x90e8,
	336	+ .halt_check = BRANCH_HALT_VOTED,
	337	+ .clkr = {
	338	+ .enable_reg = 0x90e8,
	339	+ .enable_mask = BIT(0),
	340	+ .hw.init = &(const struct clk_init_data) {
	341	+ .name = "gpu_cc_hub_cx_int_clk",
	342	+ .parent_hws = (const struct clk_hw*[]) {
	343	+ &gpu_cc_hub_clk_src.clkr.hw,
	344	+ },
	345	+ .num_parents = 1,
	346	+ .flags = CLK_SET_RATE_PARENT,
	347	+ .ops = &clk_branch2_aon_ops,
	348	+ },
	349	+ },
	350	+};
	351	+
	352	+static struct clk_branch gpu_cc_memnoc_gfx_clk = {
	353	+ .halt_reg = 0x90f4,
	354	+ .halt_check = BRANCH_HALT_VOTED,
	355	+ .clkr = {
	356	+ .enable_reg = 0x90f4,
	357	+ .enable_mask = BIT(0),
	358	+ .hw.init = &(const struct clk_init_data) {
	359	+ .name = "gpu_cc_memnoc_gfx_clk",
	360	+ .ops = &clk_branch2_ops,
	361	+ },
	362	+ },
	363	+};
	364	+
	365	+static struct gdsc gpu_cc_cx_gdsc = {
	366	+ .gdscr = 0x9080,
	367	+ .gds_hw_ctrl = 0x9094,
	368	+ .en_rest_wait_val = 0x2,
	369	+ .en_few_wait_val = 0x2,
	370	+ .clk_dis_wait_val = 0x8,
	371	+ .pd = {
	372	+ .name = "gpu_cc_cx_gdsc",
	373	+ },
	374	+ .pwrsts = PWRSTS_OFF_ON,
	375	+ .flags = RETAIN_FF_ENABLE \| VOTABLE,
	376	+};
	377	+
	378	+static struct clk_regmap *gpu_cc_sm8750_clocks[] = {
	379	+ [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
	380	+ [GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr,
	381	+ [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
	382	+ [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
	383	+ [GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr,
	384	+ [GPU_CC_DPM_CLK] = &gpu_cc_dpm_clk.clkr,
	385	+ [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
	386	+ [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
	387	+ [GPU_CC_GX_ACCU_SHIFT_CLK] = &gpu_cc_gx_accu_shift_clk.clkr,
	388	+ [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
	389	+ [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
	390	+ [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
	391	+ [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
	392	+ [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
	393	+ [GPU_CC_HUB_DIV_CLK_SRC] = &gpu_cc_hub_div_clk_src.clkr,
	394	+ [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
	395	+ [GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
	396	+ [GPU_CC_PLL0_OUT_EVEN] = &gpu_cc_pll0_out_even.clkr,
	397	+};
	398	+
	399	+static struct gdsc *gpu_cc_sm8750_gdscs[] = {
	400	+ [GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc,
	401	+};
	402	+
	403	+static const struct qcom_reset_map gpu_cc_sm8750_resets[] = {
	404	+ [GPU_CC_GPU_CC_XO_BCR] = { 0x9000 },
	405	+ [GPU_CC_GPU_CC_GX_BCR] = { 0x905c },
	406	+ [GPU_CC_GPU_CC_CX_BCR] = { 0x907c },
	407	+ [GPU_CC_GPU_CC_GMU_BCR] = { 0x9314 },
	408	+ [GPU_CC_GPU_CC_CB_BCR] = { 0x93a0 },
	409	+ [GPU_CC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
	410	+};
	411	+
	412	+static const struct regmap_config gpu_cc_sm8750_regmap_config = {
	413	+ .reg_bits = 32,
	414	+ .reg_stride = 4,
	415	+ .val_bits = 32,
	416	+ .max_register = 0x9800,
	417	+ .fast_io = true,
	418	+};
	419	+
	420	+static struct clk_alpha_pll *gpu_cc_alpha_plls[] = {
	421	+ &gpu_cc_pll0,
	422	+};
	423	+
	424	+static u32 gpu_cc_sm8750_critical_cbcrs[] = {
	425	+ 0x9004, /* GPU_CC_RSCC_XO_AON_CLK */
	426	+ 0x9008, /* GPU_CC_CXO_AON_CLK */
	427	+ 0x9064, /* GPU_CC_GX_AHB_FF_CLK */
	428	+ 0x90cc, /* GPU_CC_SLEEP_CLK */
	429	+ 0x93a4, /* GPU_CC_CB_CLK */
	430	+ 0x93a8, /* GPU_CC_RSCC_HUB_AON_CLK */
	431	+};
	432	+
	433	+static struct qcom_cc_driver_data gpu_cc_sm8750_driver_data = {
	434	+ .alpha_plls = gpu_cc_alpha_plls,
	435	+ .num_alpha_plls = ARRAY_SIZE(gpu_cc_alpha_plls),
	436	+ .clk_cbcrs = gpu_cc_sm8750_critical_cbcrs,
	437	+ .num_clk_cbcrs = ARRAY_SIZE(gpu_cc_sm8750_critical_cbcrs),
	438	+};
	439	+
	440	+static const struct qcom_cc_desc gpu_cc_sm8750_desc = {
	441	+ .config = &gpu_cc_sm8750_regmap_config,
	442	+ .clks = gpu_cc_sm8750_clocks,
	443	+ .num_clks = ARRAY_SIZE(gpu_cc_sm8750_clocks),
	444	+ .resets = gpu_cc_sm8750_resets,
	445	+ .num_resets = ARRAY_SIZE(gpu_cc_sm8750_resets),
	446	+ .gdscs = gpu_cc_sm8750_gdscs,
	447	+ .num_gdscs = ARRAY_SIZE(gpu_cc_sm8750_gdscs),
	448	+ .use_rpm = true,
	449	+ .driver_data = &gpu_cc_sm8750_driver_data,
	450	+};
	451	+
	452	+static const struct of_device_id gpu_cc_sm8750_match_table[] = {
	453	+ { .compatible = "qcom,sm8750-gpucc" },
	454	+ { }
	455	+};
	456	+MODULE_DEVICE_TABLE(of, gpu_cc_sm8750_match_table);
	457	+
	458	+static int gpu_cc_sm8750_probe(struct platform_device *pdev)
	459	+{
	460	+ return qcom_cc_probe(pdev, &gpu_cc_sm8750_desc);
	461	+}
	462	+
	463	+static struct platform_driver gpu_cc_sm8750_driver = {
	464	+ .probe = gpu_cc_sm8750_probe,
	465	+ .driver = {
	466	+ .name = "sm8750-gpucc",
	467	+ .of_match_table = gpu_cc_sm8750_match_table,
	468	+ },
	469	+};
	470	+module_platform_driver(gpu_cc_sm8750_driver);
	471	+
	472	+MODULE_DESCRIPTION("QTI GPU_CC SM8750 Driver");
	473	+MODULE_LICENSE("GPL");

drivers/clk/qcom/gxclkctl-kaanapali.c+2−1

@@ -6,7 +6,6 @@ · 5 unmodified lines
6	6	#include <linux/clk-provider.h>
7	7	#include <linux/mod_devicetable.h>
8	8	#include <linux/module.h>
9		−#include <linux/of.h>
10	9	#include <linux/platform_device.h>
11	10	#include <linux/regmap.h>
12	11
@@ -52,7 +51,9 @@ static const struct qcom_cc_desc gx_clkctl_kaanapali_desc = { · 39 unmodified lines
52	51	};
53	52
54	53	static const struct of_device_id gx_clkctl_kaanapali_match_table[] = {
	54	+ { .compatible = "qcom,glymur-gxclkctl" },
55	55	{ .compatible = "qcom,kaanapali-gxclkctl" },
	56	+ { .compatible = "qcom,sm8750-gxclkctl" },
56	57	{ }
57	58	};
58	59	MODULE_DEVICE_TABLE(of, gx_clkctl_kaanapali_match_table);

drivers/clk/qcom/ipq-cmn-pll.c+16−0

@@ -52,6 +52,8 @@ · 51 unmodified lines
52	52	#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
53	53	#include <dt-bindings/clock/qcom,ipq5018-cmn-pll.h>
54	54	#include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h>
	55	+#include <dt-bindings/clock/qcom,ipq6018-cmn-pll.h>
	56	+#include <dt-bindings/clock/qcom,ipq8074-cmn-pll.h>
55	57
56	58	#define CMN_PLL_REFCLK_SRC_SELECTION 0x28
57	59	#define CMN_PLL_REFCLK_SRC_DIV GENMASK(9, 8)
@@ -117,6 +119,18 @@ static const struct cmn_pll_fixed_output_clk ipq5018_output_clks[] = { · 59 unmodified lines
117	119	{ /* Sentinel */ }
118	120	};
119	121
	122	+static const struct cmn_pll_fixed_output_clk ipq6018_output_clks[] = {
	123	+ CLK_PLL_OUTPUT(IPQ6018_BIAS_PLL_CC_CLK, "bias_pll_cc_clk", 300000000UL),
	124	+ CLK_PLL_OUTPUT(IPQ6018_BIAS_PLL_NSS_NOC_CLK, "bias_pll_nss_noc_clk", 416500000UL),
	125	+ { /* Sentinel */ }
	126	+};
	127	+
	128	+static const struct cmn_pll_fixed_output_clk ipq8074_output_clks[] = {
	129	+ CLK_PLL_OUTPUT(IPQ8074_BIAS_PLL_CC_CLK, "bias_pll_cc_clk", 300000000UL),
	130	+ CLK_PLL_OUTPUT(IPQ8074_BIAS_PLL_NSS_NOC_CLK, "bias_pll_nss_noc_clk", 416500000UL),
	131	+ { /* Sentinel */ }
	132	+};
	133	+
120	134	static const struct cmn_pll_fixed_output_clk ipq5424_output_clks[] = {
121	135	CLK_PLL_OUTPUT(IPQ5424_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
122	136	CLK_PLL_OUTPUT(IPQ5424_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
@@ -448,6 +462,8 @@ static const struct dev_pm_ops ipq_cmn_pll_pm_ops = { · 325 unmodified lines
448	462	static const struct of_device_id ipq_cmn_pll_clk_ids[] = {
449	463	{ .compatible = "qcom,ipq5018-cmn-pll", .data = &ipq5018_output_clks },
450	464	{ .compatible = "qcom,ipq5424-cmn-pll", .data = &ipq5424_output_clks },
	465	+ { .compatible = "qcom,ipq6018-cmn-pll", .data = &ipq6018_output_clks },
	466	+ { .compatible = "qcom,ipq8074-cmn-pll", .data = &ipq8074_output_clks },
451	467	{ .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks },
452	468	{ }
453	469	};

drivers/clk/qcom/negcc-nord.c+1987−0

@@ -0,0 +1,1987 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
	2	+/*
	3	+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
	4	+ */
	5	+
	6	+#include <linux/clk-provider.h>
	7	+#include <linux/mod_devicetable.h>
	8	+#include <linux/module.h>
	9	+#include <linux/platform_device.h>
	10	+#include <linux/regmap.h>
	11	+
	12	+#include <dt-bindings/clock/qcom,nord-negcc.h>
	13	+
	14	+#include "clk-alpha-pll.h"
	15	+#include "clk-branch.h"
	16	+#include "clk-pll.h"
	17	+#include "clk-rcg.h"
	18	+#include "clk-regmap.h"
	19	+#include "clk-regmap-divider.h"
	20	+#include "clk-regmap-mux.h"
	21	+#include "clk-regmap-phy-mux.h"
	22	+#include "common.h"
	23	+#include "gdsc.h"
	24	+#include "reset.h"
	25	+
	26	+enum {
	27	+ DT_BI_TCXO,
	28	+ DT_SLEEP_CLK,
	29	+ DT_UFS_PHY_RX_SYMBOL_0_CLK,
	30	+ DT_UFS_PHY_RX_SYMBOL_1_CLK,
	31	+ DT_UFS_PHY_TX_SYMBOL_0_CLK,
	32	+ DT_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK,
	33	+ DT_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK,
	34	+};
	35	+
	36	+enum {
	37	+ P_BI_TCXO,
	38	+ P_NE_GCC_GPLL0_OUT_EVEN,
	39	+ P_NE_GCC_GPLL0_OUT_MAIN,
	40	+ P_NE_GCC_GPLL2_OUT_MAIN,
	41	+ P_SLEEP_CLK,
	42	+ P_UFS_PHY_RX_SYMBOL_0_CLK,
	43	+ P_UFS_PHY_RX_SYMBOL_1_CLK,
	44	+ P_UFS_PHY_TX_SYMBOL_0_CLK,
	45	+ P_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK,
	46	+ P_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK,
	47	+};
	48	+
	49	+static struct clk_alpha_pll ne_gcc_gpll0 = {
	50	+ .offset = 0x0,
	51	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
	52	+ .clkr = {
	53	+ .enable_reg = 0x0,
	54	+ .enable_mask = BIT(0),
	55	+ .hw.init = &(const struct clk_init_data) {
	56	+ .name = "ne_gcc_gpll0",
	57	+ .parent_data = &(const struct clk_parent_data) {
	58	+ .index = DT_BI_TCXO,
	59	+ },
	60	+ .num_parents = 1,
	61	+ .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
	62	+ },
	63	+ },
	64	+};
	65	+
	66	+static const struct clk_div_table post_div_table_ne_gcc_gpll0_out_even[] = {
	67	+ { 0x1, 2 },
	68	+ { }
	69	+};
	70	+
	71	+static struct clk_alpha_pll_postdiv ne_gcc_gpll0_out_even = {
	72	+ .offset = 0x0,
	73	+ .post_div_shift = 10,
	74	+ .post_div_table = post_div_table_ne_gcc_gpll0_out_even,
	75	+ .num_post_div = ARRAY_SIZE(post_div_table_ne_gcc_gpll0_out_even),
	76	+ .width = 4,
	77	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
	78	+ .clkr.hw.init = &(const struct clk_init_data) {
	79	+ .name = "ne_gcc_gpll0_out_even",
	80	+ .parent_hws = (const struct clk_hw*[]) {
	81	+ &ne_gcc_gpll0.clkr.hw,
	82	+ },
	83	+ .num_parents = 1,
	84	+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
	85	+ },
	86	+};
	87	+
	88	+static struct clk_alpha_pll ne_gcc_gpll2 = {
	89	+ .offset = 0x2000,
	90	+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
	91	+ .clkr = {
	92	+ .enable_reg = 0x0,
	93	+ .enable_mask = BIT(2),
	94	+ .hw.init = &(const struct clk_init_data) {
	95	+ .name = "ne_gcc_gpll2",
	96	+ .parent_data = &(const struct clk_parent_data) {
	97	+ .index = DT_BI_TCXO,
	98	+ },
	99	+ .num_parents = 1,
	100	+ .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
	101	+ },
	102	+ },
	103	+};
	104	+
	105	+static const struct parent_map ne_gcc_parent_map_0[] = {
	106	+ { P_BI_TCXO, 0 },
	107	+ { P_NE_GCC_GPLL0_OUT_MAIN, 1 },
	108	+};
	109	+
	110	+static const struct clk_parent_data ne_gcc_parent_data_0[] = {
	111	+ { .index = DT_BI_TCXO },
	112	+ { .hw = &ne_gcc_gpll0.clkr.hw },
	113	+};
	114	+
	115	+static const struct parent_map ne_gcc_parent_map_1[] = {
	116	+ { P_BI_TCXO, 0 },
	117	+ { P_NE_GCC_GPLL0_OUT_MAIN, 1 },
	118	+ { P_NE_GCC_GPLL0_OUT_EVEN, 5 },
	119	+};
	120	+
	121	+static const struct clk_parent_data ne_gcc_parent_data_1[] = {
	122	+ { .index = DT_BI_TCXO },
	123	+ { .hw = &ne_gcc_gpll0.clkr.hw },
	124	+ { .hw = &ne_gcc_gpll0_out_even.clkr.hw },
	125	+};
	126	+
	127	+static const struct parent_map ne_gcc_parent_map_2[] = {
	128	+ { P_BI_TCXO, 0 },
	129	+ { P_NE_GCC_GPLL0_OUT_MAIN, 1 },
	130	+ { P_NE_GCC_GPLL2_OUT_MAIN, 3 },
	131	+};
	132	+
	133	+static const struct clk_parent_data ne_gcc_parent_data_2[] = {
	134	+ { .index = DT_BI_TCXO },
	135	+ { .hw = &ne_gcc_gpll0.clkr.hw },
	136	+ { .hw = &ne_gcc_gpll2.clkr.hw },
	137	+};
	138	+
	139	+static const struct parent_map ne_gcc_parent_map_3[] = {
	140	+ { P_BI_TCXO, 0 },
	141	+ { P_SLEEP_CLK, 5 },
	142	+};
	143	+
	144	+static const struct clk_parent_data ne_gcc_parent_data_3[] = {
	145	+ { .index = DT_BI_TCXO },
	146	+ { .index = DT_SLEEP_CLK },
	147	+};
	148	+
	149	+static const struct parent_map ne_gcc_parent_map_4[] = {
	150	+ { P_BI_TCXO, 0 },
	151	+ { P_NE_GCC_GPLL0_OUT_MAIN, 1 },
	152	+ { P_SLEEP_CLK, 5 },
	153	+};
	154	+
	155	+static const struct clk_parent_data ne_gcc_parent_data_4[] = {
	156	+ { .index = DT_BI_TCXO },
	157	+ { .hw = &ne_gcc_gpll0.clkr.hw },
	158	+ { .index = DT_SLEEP_CLK },
	159	+};
	160	+
	161	+static const struct parent_map ne_gcc_parent_map_5[] = {
	162	+ { P_BI_TCXO, 0 },
	163	+};
	164	+
	165	+static const struct clk_parent_data ne_gcc_parent_data_5[] = {
	166	+ { .index = DT_BI_TCXO },
	167	+};
	168	+
	169	+static const struct parent_map ne_gcc_parent_map_6[] = {
	170	+ { P_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK, 0 },
	171	+ { P_BI_TCXO, 2 },
	172	+};
	173	+
	174	+static const struct clk_parent_data ne_gcc_parent_data_6[] = {
	175	+ { .index = DT_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK },
	176	+ { .index = DT_BI_TCXO },
	177	+};
	178	+
	179	+static const struct parent_map ne_gcc_parent_map_7[] = {
	180	+ { P_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK, 0 },
	181	+ { P_BI_TCXO, 2 },
	182	+};
	183	+
	184	+static const struct clk_parent_data ne_gcc_parent_data_7[] = {
	185	+ { .index = DT_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK },
	186	+ { .index = DT_BI_TCXO },
	187	+};
	188	+
	189	+static struct clk_regmap_phy_mux ne_gcc_ufs_phy_rx_symbol_0_clk_src = {
	190	+ .reg = 0x33068,
	191	+ .clkr = {
	192	+ .hw.init = &(const struct clk_init_data) {
	193	+ .name = "ne_gcc_ufs_phy_rx_symbol_0_clk_src",
	194	+ .parent_data = &(const struct clk_parent_data){
	195	+ .index = DT_UFS_PHY_RX_SYMBOL_0_CLK,
	196	+ },
	197	+ .num_parents = 1,
	198	+ .ops = &clk_regmap_phy_mux_ops,
	199	+ },
	200	+ },
	201	+};
	202	+
	203	+static struct clk_regmap_phy_mux ne_gcc_ufs_phy_rx_symbol_1_clk_src = {
	204	+ .reg = 0x330f0,
	205	+ .clkr = {
	206	+ .hw.init = &(const struct clk_init_data) {
	207	+ .name = "ne_gcc_ufs_phy_rx_symbol_1_clk_src",
	208	+ .parent_data = &(const struct clk_parent_data){
	209	+ .index = DT_UFS_PHY_RX_SYMBOL_1_CLK,
	210	+ },
	211	+ .num_parents = 1,
	212	+ .ops = &clk_regmap_phy_mux_ops,
	213	+ },
	214	+ },
	215	+};
	216	+
	217	+static struct clk_regmap_phy_mux ne_gcc_ufs_phy_tx_symbol_0_clk_src = {
	218	+ .reg = 0x33058,
	219	+ .clkr = {
	220	+ .hw.init = &(const struct clk_init_data) {
	221	+ .name = "ne_gcc_ufs_phy_tx_symbol_0_clk_src",
	222	+ .parent_data = &(const struct clk_parent_data){
	223	+ .index = DT_UFS_PHY_TX_SYMBOL_0_CLK,
	224	+ },
	225	+ .num_parents = 1,
	226	+ .ops = &clk_regmap_phy_mux_ops,
	227	+ },
	228	+ },
	229	+};
	230	+
	231	+static struct clk_regmap_mux ne_gcc_usb3_prim_phy_pipe_clk_src = {
	232	+ .reg = 0x2a078,
	233	+ .shift = 0,
	234	+ .width = 2,
	235	+ .parent_map = ne_gcc_parent_map_6,
	236	+ .clkr = {
	237	+ .hw.init = &(const struct clk_init_data) {
	238	+ .name = "ne_gcc_usb3_prim_phy_pipe_clk_src",
	239	+ .parent_data = ne_gcc_parent_data_6,
	240	+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_6),
	241	+ .ops = &clk_regmap_mux_closest_ops,
	242	+ },
	243	+ },
	244	+};
	245	+
	246	+static struct clk_regmap_mux ne_gcc_usb3_sec_phy_pipe_clk_src = {
	247	+ .reg = 0x2c078,
	248	+ .shift = 0,
	249	+ .width = 2,
	250	+ .parent_map = ne_gcc_parent_map_7,
	251	+ .clkr = {
	252	+ .hw.init = &(const struct clk_init_data) {
	253	+ .name = "ne_gcc_usb3_sec_phy_pipe_clk_src",
	254	+ .parent_data = ne_gcc_parent_data_7,
	255	+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_7),
	256	+ .ops = &clk_regmap_mux_closest_ops,
	257	+ },
	258	+ },
	259	+};
	260	+
	261	+static const struct freq_tbl ftbl_ne_gcc_gp1_clk_src[] = {
	262	+ F(66666667, P_NE_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
	263	+ F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
	264	+ F(200000000, P_NE_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
	265	+ { }
	266	+};
	267	+
	268	+static struct clk_rcg2 ne_gcc_gp1_clk_src = {
	269	+ .cmd_rcgr = 0x21004,
	270	+ .mnd_width = 16,
	271	+ .hid_width = 5,
	272	+ .parent_map = ne_gcc_parent_map_4,
	273	+ .freq_tbl = ftbl_ne_gcc_gp1_clk_src,
	274	+ .hw_clk_ctrl = true,
	275	+ .clkr.hw.init = &(const struct clk_init_data) {
	276	+ .name = "ne_gcc_gp1_clk_src",
	277	+ .parent_data = ne_gcc_parent_data_4,
	278	+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_4),
	279	+ .flags = CLK_SET_RATE_PARENT,
	280	+ .ops = &clk_rcg2_shared_ops,
	281	+ },
	282	+};
	283	+
	284	+static struct clk_rcg2 ne_gcc_gp2_clk_src = {
	285	+ .cmd_rcgr = 0x22004,
	286	+ .mnd_width = 16,
	287	+ .hid_width = 5,
	288	+ .parent_map = ne_gcc_parent_map_4,
	289	+ .freq_tbl = ftbl_ne_gcc_gp1_clk_src,
	290	+ .hw_clk_ctrl = true,
	291	+ .clkr.hw.init = &(const struct clk_init_data) {
	292	+ .name = "ne_gcc_gp2_clk_src",
	293	+ .parent_data = ne_gcc_parent_data_4,
	294	+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_4),
	295	+ .flags = CLK_SET_RATE_PARENT,
	296	+ .ops = &clk_rcg2_shared_ops,
	297	+ },
	298	+};
	299	+
	300	+static const struct freq_tbl ftbl_ne_gcc_qupv3_wrap2_s0_clk_src[] = {
	301	+ F(7372800, P_NE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625),
	302	+ F(14745600, P_NE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625),
	303	+ F(19200000, P_BI_TCXO, 1, 0, 0),
	304	+ F(29491200, P_NE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625),
	305	+ F(32000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 75),
	306	+ F(48000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 25),
	307	+ F(51200000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 32, 375),
	308	+ F(64000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 8, 75),
	309	+ F(66666667, P_NE_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
	310	+ F(75000000, P_NE_GCC_GPLL0_OUT_MAIN, 8, 0, 0),
	311	+ F(80000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 15),
	312	+ F(96000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 25),
	313	+ F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
	314	+ F(102400000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 64, 375),
	315	+ F(112000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 14, 75),
	316	+ F(117964800, P_NE_GCC_GPLL0_OUT_MAIN, 1, 3072, 15625),
	317	+ F(120000000, P_NE_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
	318	+ { }
	319	+};
	320	+
	321	+static struct clk_init_data ne_gcc_qupv3_wrap2_s0_clk_src_init = {
	322	+ .name = "ne_gcc_qupv3_wrap2_s0_clk_src",
	323	+ .parent_data = ne_gcc_parent_data_0,
	324	+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
	325	+ .flags = CLK_SET_RATE_PARENT,
	326	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	327	+};
	328	+
	329	+static struct clk_rcg2 ne_gcc_qupv3_wrap2_s0_clk_src = {
	330	+ .cmd_rcgr = 0x3816c,
	331	+ .mnd_width = 16,
	332	+ .hid_width = 5,
	333	+ .parent_map = ne_gcc_parent_map_0,
	334	+ .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s0_clk_src,
	335	+ .hw_clk_ctrl = true,
	336	+ .clkr.hw.init = &ne_gcc_qupv3_wrap2_s0_clk_src_init,
	337	+};
	338	+
	339	+static struct clk_init_data ne_gcc_qupv3_wrap2_s1_clk_src_init = {
	340	+ .name = "ne_gcc_qupv3_wrap2_s1_clk_src",
	341	+ .parent_data = ne_gcc_parent_data_0,
	342	+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
	343	+ .flags = CLK_SET_RATE_PARENT,
	344	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	345	+};
	346	+
	347	+static struct clk_rcg2 ne_gcc_qupv3_wrap2_s1_clk_src = {
	348	+ .cmd_rcgr = 0x382a8,
	349	+ .mnd_width = 16,
	350	+ .hid_width = 5,
	351	+ .parent_map = ne_gcc_parent_map_0,
	352	+ .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s0_clk_src,
	353	+ .hw_clk_ctrl = true,
	354	+ .clkr.hw.init = &ne_gcc_qupv3_wrap2_s1_clk_src_init,
	355	+};
	356	+
	357	+static const struct freq_tbl ftbl_ne_gcc_qupv3_wrap2_s2_clk_src[] = {
	358	+ F(7372800, P_NE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625),
	359	+ F(14745600, P_NE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625),
	360	+ F(19200000, P_BI_TCXO, 1, 0, 0),
	361	+ F(29491200, P_NE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625),
	362	+ F(32000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 75),
	363	+ F(48000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 25),
	364	+ F(51200000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 32, 375),
	365	+ F(64000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 8, 75),
	366	+ F(66666667, P_NE_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
	367	+ F(75000000, P_NE_GCC_GPLL0_OUT_MAIN, 8, 0, 0),
	368	+ F(80000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 15),
	369	+ F(96000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 25),
	370	+ F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
	371	+ { }
	372	+};
	373	+
	374	+static struct clk_init_data ne_gcc_qupv3_wrap2_s2_clk_src_init = {
	375	+ .name = "ne_gcc_qupv3_wrap2_s2_clk_src",
	376	+ .parent_data = ne_gcc_parent_data_0,
	377	+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
	378	+ .flags = CLK_SET_RATE_PARENT,
	379	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	380	+};
	381	+
	382	+static struct clk_rcg2 ne_gcc_qupv3_wrap2_s2_clk_src = {
	383	+ .cmd_rcgr = 0x383e4,
	384	+ .mnd_width = 16,
	385	+ .hid_width = 5,
	386	+ .parent_map = ne_gcc_parent_map_0,
	387	+ .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src,
	388	+ .hw_clk_ctrl = true,
	389	+ .clkr.hw.init = &ne_gcc_qupv3_wrap2_s2_clk_src_init,
	390	+};
	391	+
	392	+static struct clk_init_data ne_gcc_qupv3_wrap2_s3_clk_src_init = {
	393	+ .name = "ne_gcc_qupv3_wrap2_s3_clk_src",
	394	+ .parent_data = ne_gcc_parent_data_0,
	395	+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
	396	+ .flags = CLK_SET_RATE_PARENT,
	397	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	398	+};
	399	+
	400	+static struct clk_rcg2 ne_gcc_qupv3_wrap2_s3_clk_src = {
	401	+ .cmd_rcgr = 0x38520,
	402	+ .mnd_width = 16,
	403	+ .hid_width = 5,
	404	+ .parent_map = ne_gcc_parent_map_0,
	405	+ .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src,
	406	+ .hw_clk_ctrl = true,
	407	+ .clkr.hw.init = &ne_gcc_qupv3_wrap2_s3_clk_src_init,
	408	+};
	409	+
	410	+static struct clk_init_data ne_gcc_qupv3_wrap2_s4_clk_src_init = {
	411	+ .name = "ne_gcc_qupv3_wrap2_s4_clk_src",
	412	+ .parent_data = ne_gcc_parent_data_0,
	413	+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
	414	+ .flags = CLK_SET_RATE_PARENT,
	415	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	416	+};
	417	+
	418	+static struct clk_rcg2 ne_gcc_qupv3_wrap2_s4_clk_src = {
	419	+ .cmd_rcgr = 0x3865c,
	420	+ .mnd_width = 16,
	421	+ .hid_width = 5,
	422	+ .parent_map = ne_gcc_parent_map_0,
	423	+ .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src,
	424	+ .hw_clk_ctrl = true,
	425	+ .clkr.hw.init = &ne_gcc_qupv3_wrap2_s4_clk_src_init,
	426	+};
	427	+
	428	+static struct clk_init_data ne_gcc_qupv3_wrap2_s5_clk_src_init = {
	429	+ .name = "ne_gcc_qupv3_wrap2_s5_clk_src",
	430	+ .parent_data = ne_gcc_parent_data_0,
	431	+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
	432	+ .flags = CLK_SET_RATE_PARENT,
	433	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	434	+};
	435	+
	436	+static struct clk_rcg2 ne_gcc_qupv3_wrap2_s5_clk_src = {
	437	+ .cmd_rcgr = 0x38798,
	438	+ .mnd_width = 16,
	439	+ .hid_width = 5,
	440	+ .parent_map = ne_gcc_parent_map_0,
	441	+ .freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src,
	442	+ .hw_clk_ctrl = true,
	443	+ .clkr.hw.init = &ne_gcc_qupv3_wrap2_s5_clk_src_init,
	444	+};
	445	+
	446	+static struct clk_init_data ne_gcc_qupv3_wrap2_s6_clk_src_init = {
	447	+ .name = "ne_gcc_qupv3_wrap2_s6_clk_src",
	448	+ .parent_data = ne_gcc_parent_data_0,
	449	+ .num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
	450	+ .flags = CLK_SET_RATE_PARENT,
	451	+ .ops = &clk_rcg2_shared_no_init_park_ops,
	452	+};
	453	+
	454	+static struct clk_rcg2 ne_gcc_qupv3_wrap2_s6_clk_src = {
	455	+ .cmd_rcgr = 0x388d4,
	456	+ .mnd_width = 16,

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drivers/clk/qcom/videocc-sm8550.c+2−2

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drivers/clk/qcom/videocc-sm8750.c+2−3

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drivers/clk/renesas/Kconfig+6−1

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drivers/clk/renesas/Makefile+1−0

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drivers/clk/renesas/r9a06g032-clocks.c+3−2

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drivers/clk/renesas/r9a07g043-cpg.c+9−0

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drivers/clk/renesas/r9a07g044-cpg.c+13−0

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drivers/clk/renesas/r9a08g045-cpg.c+9−0

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drivers/clk/renesas/r9a08g046-cpg.c+153−0

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drivers/clk/renesas/r9a09g047-cpg.c+29−0

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drivers/clk/renesas/r9a09g056-cpg.c+27−33

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drivers/clk/renesas/r9a09g057-cpg.c+25−35

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drivers/clk/renesas/renesas-cpg-mssr.c+2−2

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drivers/clk/renesas/rzg2l-cpg.c+78−13

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drivers/clk/renesas/rzg2l-cpg.h+8−0

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drivers/clk/rockchip/Kconfig+7−0

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drivers/clk/rockchip/Makefile+1−0

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drivers/clk/rockchip/clk-rk3568.c+6−0

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drivers/clk/rockchip/clk-rv1103b.c+658−0

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drivers/clk/rockchip/clk.h+49−0

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drivers/clk/samsung/Makefile+1−0

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drivers/clk/samsung/clk-artpec9.c+1224−0

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drivers/clk/samsung/clk-exynos850.c+6−1

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drivers/clk/samsung/clk-exynosautov920.c+52−0

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drivers/clk/samsung/clk-gs101.c+26−26

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drivers/clk/samsung/clk-pll.c+177−8

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drivers/clk/samsung/clk-pll.h+17−0

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drivers/clk/samsung/clk.c+2−2

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drivers/clk/spacemit/ccu_mix.c+1−1

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drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c+16−1

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drivers/clk/tenstorrent/Kconfig+14−0

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drivers/clk/tenstorrent/Makefile+3−0

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drivers/clk/tenstorrent/atlantis-prcm.c+870−0

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drivers/clk/visconti/pll.c+1−1

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drivers/reset/Kconfig+11−0

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drivers/reset/Makefile+1−0

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drivers/reset/reset-tenstorrent-atlantis.c+173−0

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include/dt-bindings/clock/bt1-ccu.h+0−48

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include/dt-bindings/clock/econet,en751221-scu.h+12−0

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include/dt-bindings/clock/eswin,eic7700-clock.h+285−0

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include/dt-bindings/clock/exynos850.h+1−0

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include/dt-bindings/clock/qcom,dispcc-sc7180.h+6−1

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include/dt-bindings/clock/qcom,eliza-dispcc.h+118−0

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include/dt-bindings/clock/qcom,gcc-sc8180x.h+5−0

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include/dt-bindings/clock/qcom,glymur-gcc.h+1−0

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include/dt-bindings/clock/qcom,glymur-gpucc.h+51−0

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include/dt-bindings/clock/qcom,glymur-videocc.h+45−0

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include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h+15−0

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include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h+15−0

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include/dt-bindings/clock/qcom,nord-gcc.h+147−0

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include/dt-bindings/clock/qcom,nord-negcc.h+124−0

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include/dt-bindings/clock/qcom,nord-nwgcc.h+69−0

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include/dt-bindings/clock/qcom,nord-segcc.h+98−0

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include/dt-bindings/clock/qcom,nord-tcsrcc.h+26−0

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include/dt-bindings/clock/qcom,sm8750-gpucc.h+50−0

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include/dt-bindings/clock/samsung,exynosautov920.h+6−0

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include/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h+103−0

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include/dt-bindings/clock/vf610-clock.h+5−1

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include/dt-bindings/reset/econet,en751221-scu.h+49−0

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include/linux/clk-provider.h+26−40

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