lael-labs/linux

.mailmap+1−0

@@ -17,6 +17,7 @@ Aleksey Gorelov <aleksey_gorelov@phoenix.com> · 16 unmodified lines
17	Al Viro <viro@ftp.linux.org.uk>	17	Al Viro <viro@ftp.linux.org.uk>
18	Al Viro <viro@zenIV.linux.org.uk>	18	Al Viro <viro@zenIV.linux.org.uk>
19	Andreas Herrmann <aherrman@de.ibm.com>	19	Andreas Herrmann <aherrman@de.ibm.com>
		20	Andrey Ryabinin <ryabinin.a.a@gmail.com> <a.ryabinin@samsung.com>
20	Andrew Morton <akpm@linux-foundation.org>	21	Andrew Morton <akpm@linux-foundation.org>
21	Andrew Vasquez <andrew.vasquez@qlogic.com>	22	Andrew Vasquez <andrew.vasquez@qlogic.com>
22	Andy Adamson <andros@citi.umich.edu>	23	Andy Adamson <andros@citi.umich.edu>

Documentation/devicetree/bindings/arm/cpus.txt+1−0

@@ -199,6 +199,7 @@ nodes to be present and contain the properties described below. · 198 unmodified lines
199	"qcom,kpss-acc-v1"	199	"qcom,kpss-acc-v1"
200	"qcom,kpss-acc-v2"	200	"qcom,kpss-acc-v2"
201	"rockchip,rk3066-smp"	201	"rockchip,rk3066-smp"
		202	"ste,dbx500-smp"
202		203
203	- cpu-release-addr	204	- cpu-release-addr
204	Usage: required for systems that have an "enable-method"	205	Usage: required for systems that have an "enable-method"

Documentation/devicetree/bindings/dma/apm-xgene-dma.txt+1−1

@@ -35,7 +35,7 @@ Example: · 34 unmodified lines
35	device_type = "dma";	35	device_type = "dma";
36	reg = <0x0 0x1f270000 0x0 0x10000>,	36	reg = <0x0 0x1f270000 0x0 0x10000>,
37	<0x0 0x1f200000 0x0 0x10000>,	37	<0x0 0x1f200000 0x0 0x10000>,
38	<0x0 0x1b008000 0x0 0x2000>,	38	<0x0 0x1b000000 0x0 0x400000>,
39	<0x0 0x1054a000 0x0 0x100>;	39	<0x0 0x1054a000 0x0 0x100>;
40	interrupts = <0x0 0x82 0x4>,	40	interrupts = <0x0 0x82 0x4>,
41	<0x0 0xb8 0x4>,	41	<0x0 0xb8 0x4>,

Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt+3−0

@@ -35,3 +35,6 @@ the PCIe specification. · 34 unmodified lines
35		35
36	NOTE: this only applies to the SMMU itself, not	36	NOTE: this only applies to the SMMU itself, not
37	masters connected upstream of the SMMU.	37	masters connected upstream of the SMMU.
		38
		39	- hisilicon,broken-prefetch-cmd
		40	: Avoid sending CMD_PREFETCH_* commands to the SMMU.

Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt+0−2

 	       "fsl,imx6sx-usdhc"
 Optional properties:
-- fsl,cd-controller : Indicate to use controller internal card detection
 - fsl,wp-controller : Indicate to use controller internal write protection
 - fsl,delay-line : Specify the number of delay cells for override mode.
   This is used to set the clock delay for DLL(Delay Line) on override mode
 	compatible = "fsl,imx51-esdhc";
 	reg = <0x70004000 0x4000>;
 	interrupts = <1>;
-	fsl,cd-controller;
 	fsl,wp-controller;
 };

Documentation/devicetree/bindings/phy/ti-phy.txt+16−0

@@ -82,6 +82,9 @@ Optional properties: · 81 unmodified lines
82	- id: If there are multiple instance of the same type, in order to	82	- id: If there are multiple instance of the same type, in order to
83	differentiate between each instance "id" can be used (e.g., multi-lane PCIe	83	differentiate between each instance "id" can be used (e.g., multi-lane PCIe
84	PHY). If "id" is not provided, it is set to default value of '1'.	84	PHY). If "id" is not provided, it is set to default value of '1'.
		85	- syscon-pllreset: Handle to system control region that contains the
		86	CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
		87	register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.
85		88
86	This is usually a subnode of ocp2scp to which it is connected.	89	This is usually a subnode of ocp2scp to which it is connected.
87		90
@@ -100,3 +103,16 @@ usb3phy@4a084400 { · 12 unmodified lines
100	"sysclk",	103	"sysclk",
101	"refclk";	104	"refclk";
102	};	105	};
		106
		107	sata_phy: phy@4A096000 {
		108	compatible = "ti,phy-pipe3-sata";
		109	reg = <0x4A096000 0x80>, /* phy_rx */
		110	<0x4A096400 0x64>, /* phy_tx */
		111	<0x4A096800 0x40>; /* pll_ctrl */
		112	reg-names = "phy_rx", "phy_tx", "pll_ctrl";
		113	ctrl-module = <&omap_control_sata>;
		114	clocks = <&sys_clkin1>, <&sata_ref_clk>;
		115	clock-names = "sysclk", "refclk";
		116	syscon-pllreset = <&scm_conf 0x3fc>;
		117	#phy-cells = <0>;
		118	};

Documentation/devicetree/bindings/sound/mt8173-max98090.txt+2−0

 Required properties:
 - compatible : "mediatek,mt8173-max98090"
 - mediatek,audio-codec: the phandle of the MAX98090 audio codec
+- mediatek,platform: the phandle of MT8173 ASoC platform
 Example:
 	sound {
 		compatible = "mediatek,mt8173-max98090";
 		mediatek,audio-codec = <&max98090>;
+		mediatek,platform = <&afe>;
 	};

Documentation/devicetree/bindings/sound/mt8173-rt5650-rt5676.txt+2−0

 Required properties:
 - compatible : "mediatek,mt8173-rt5650-rt5676"
 - mediatek,audio-codec: the phandles of rt5650 and rt5676 codecs
+- mediatek,platform: the phandle of MT8173 ASoC platform
 Example:
 	sound {
 		compatible = "mediatek,mt8173-rt5650-rt5676";
 		mediatek,audio-codec = <&rt5650 &rt5676>;
+		mediatek,platform = <&afe>;
 	};

Documentation/devicetree/bindings/spi/spi-ath79.txt+3−3

@@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller · 2 unmodified lines
3	Required properties:	3	Required properties:
4	- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback.	4	- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback.
5	- reg: Base address and size of the controllers memory area	5	- reg: Base address and size of the controllers memory area
6	- clocks: phandle to the AHB clock.	6	- clocks: phandle of the AHB clock.
7	- clock-names: has to be "ahb".	7	- clock-names: has to be "ahb".
8	- #address-cells: <1>, as required by generic SPI binding.	8	- #address-cells: <1>, as required by generic SPI binding.
9	- #size-cells: <0>, also as required by generic SPI binding.	9	- #size-cells: <0>, also as required by generic SPI binding.
@@ -12,9 +12,9 @@ Child nodes as per the generic SPI binding. · 2 unmodified lines
12		12
13	Example:	13	Example:
14		14
15	spi@1F000000 {	15	spi@1f000000 {
16	compatible = "qca,ar9132-spi", "qca,ar7100-spi";	16	compatible = "qca,ar9132-spi", "qca,ar7100-spi";
17	reg = <0x1F000000 0x10>;	17	reg = <0x1f000000 0x10>;
18		18
19	clocks = <&pll 2>;	19	clocks = <&pll 2>;
20	clock-names = "ahb";	20	clock-names = "ahb";

Documentation/hwmon/nct7904+2−2

@@ -35,11 +35,11 @@ temp1_input Local temperature (1/1000 degree, · 34 unmodified lines
35	temp[2-9]_input CPU temperatures (1/1000 degree,	35	temp[2-9]_input CPU temperatures (1/1000 degree,
36	0.125 degree resolution)	36	0.125 degree resolution)
37		37
38	fan[1-4]_mode R/W, 0/1 for manual or SmartFan mode	38	pwm[1-4]_enable R/W, 1/2 for manual or SmartFan mode
39	Setting SmartFan mode is supported only if it has been	39	Setting SmartFan mode is supported only if it has been
40	previously configured by BIOS (or configuration EEPROM)	40	previously configured by BIOS (or configuration EEPROM)
41		41
42	fan[1-4]_pwm R/O in SmartFan mode, R/W in manual control mode	42	pwm[1-4] R/O in SmartFan mode, R/W in manual control mode
43		43
44	The driver checks sensor control registers and does not export the sensors	44	The driver checks sensor control registers and does not export the sensors
45	that are not enabled. Anyway, a sensor that is enabled may actually be not	45	that are not enabled. Anyway, a sensor that is enabled may actually be not

Documentation/input/alps.txt+4−2

@@ -119,8 +119,10 @@ ALPS Absolute Mode - Protocol Version 2 · 118 unmodified lines
119	byte 5: 0 z6 z5 z4 z3 z2 z1 z0	119	byte 5: 0 z6 z5 z4 z3 z2 z1 z0
120		120
121	Protocol Version 2 DualPoint devices send standard PS/2 mouse packets for	121	Protocol Version 2 DualPoint devices send standard PS/2 mouse packets for
122	the DualPoint Stick. For non interleaved dualpoint devices the pointingstick	122	the DualPoint Stick. The M, R and L bits signal the combined status of both
123	buttons get reported separately in the PSM, PSR and PSL bits.	123	the pointingstick and touchpad buttons, except for Dell dualpoint devices
		124	where the pointingstick buttons get reported separately in the PSM, PSR
		125	and PSL bits.
124		126
125	Dualpoint device -- interleaved packet format	127	Dualpoint device -- interleaved packet format
126	---------------------------------------------	128	---------------------------------------------

Documentation/target/tcm_mod_builder.py+14−7

@@ -199,7 +199,8 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): · 198 unmodified lines
199	buf += "#include <linux/string.h>\n"	199	buf += "#include <linux/string.h>\n"
200	buf += "#include <linux/configfs.h>\n"	200	buf += "#include <linux/configfs.h>\n"
201	buf += "#include <linux/ctype.h>\n"	201	buf += "#include <linux/ctype.h>\n"
202	buf += "#include <asm/unaligned.h>\n\n"	202	buf += "#include <asm/unaligned.h>\n"
		203	buf += "#include <scsi/scsi_proto.h>\n\n"
203	buf += "#include <target/target_core_base.h>\n"	204	buf += "#include <target/target_core_base.h>\n"
204	buf += "#include <target/target_core_fabric.h>\n"	205	buf += "#include <target/target_core_fabric.h>\n"
205	buf += "#include <target/target_core_fabric_configfs.h>\n"	206	buf += "#include <target/target_core_fabric_configfs.h>\n"
@@ -230,8 +231,14 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): · 24 unmodified lines
230	buf += " }\n"	231	buf += " }\n"
231	buf += " tpg->" + fabric_mod_port + " = " + fabric_mod_port + ";\n"	232	buf += " tpg->" + fabric_mod_port + " = " + fabric_mod_port + ";\n"
232	buf += " tpg->" + fabric_mod_port + "_tpgt = tpgt;\n\n"	233	buf += " tpg->" + fabric_mod_port + "_tpgt = tpgt;\n\n"
233	buf += " ret = core_tpg_register(&" + fabric_mod_name + "_ops, wwn,\n"	234
234	buf += " &tpg->se_tpg, SCSI_PROTOCOL_SAS);\n"	235	if proto_ident == "FC":
		236	buf += " ret = core_tpg_register(wwn, &tpg->se_tpg, SCSI_PROTOCOL_FCP);\n"
		237	elif proto_ident == "SAS":
		238	buf += " ret = core_tpg_register(wwn, &tpg->se_tpg, SCSI_PROTOCOL_SAS);\n"
		239	elif proto_ident == "iSCSI":
		240	buf += " ret = core_tpg_register(wwn, &tpg->se_tpg, SCSI_PROTOCOL_ISCSI);\n"
		241
235	buf += " if (ret < 0) {\n"	242	buf += " if (ret < 0) {\n"
236	buf += " kfree(tpg);\n"	243	buf += " kfree(tpg);\n"
237	buf += " return NULL;\n"	244	buf += " return NULL;\n"
@@ -292,7 +299,7 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): · 54 unmodified lines
292		299
293	buf += "static const struct target_core_fabric_ops " + fabric_mod_name + "_ops = {\n"	300	buf += "static const struct target_core_fabric_ops " + fabric_mod_name + "_ops = {\n"
294	buf += " .module = THIS_MODULE,\n"	301	buf += " .module = THIS_MODULE,\n"
295	buf += " .name = " + fabric_mod_name + ",\n"	302	buf += " .name = \"" + fabric_mod_name + "\",\n"
296	buf += " .get_fabric_name = " + fabric_mod_name + "_get_fabric_name,\n"	303	buf += " .get_fabric_name = " + fabric_mod_name + "_get_fabric_name,\n"
297	buf += " .tpg_get_wwn = " + fabric_mod_name + "_get_fabric_wwn,\n"	304	buf += " .tpg_get_wwn = " + fabric_mod_name + "_get_fabric_wwn,\n"
298	buf += " .tpg_get_tag = " + fabric_mod_name + "_get_tag,\n"	305	buf += " .tpg_get_tag = " + fabric_mod_name + "_get_tag,\n"
@@ -322,17 +329,17 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): · 23 unmodified lines
322	buf += " .fabric_make_tpg = " + fabric_mod_name + "_make_tpg,\n"	329	buf += " .fabric_make_tpg = " + fabric_mod_name + "_make_tpg,\n"
323	buf += " .fabric_drop_tpg = " + fabric_mod_name + "_drop_tpg,\n"	330	buf += " .fabric_drop_tpg = " + fabric_mod_name + "_drop_tpg,\n"
324	buf += "\n"	331	buf += "\n"
325	buf += " .tfc_wwn_attrs = " + fabric_mod_name + "_wwn_attrs;\n"	332	buf += " .tfc_wwn_attrs = " + fabric_mod_name + "_wwn_attrs,\n"
326	buf += "};\n\n"	333	buf += "};\n\n"
327		334
328	buf += "static int __init " + fabric_mod_name + "_init(void)\n"	335	buf += "static int __init " + fabric_mod_name + "_init(void)\n"
329	buf += "{\n"	336	buf += "{\n"
330	buf += " return target_register_template(" + fabric_mod_name + "_ops);\n"	337	buf += " return target_register_template(&" + fabric_mod_name + "_ops);\n"
331	buf += "};\n\n"	338	buf += "};\n\n"
332		339
333	buf += "static void __exit " + fabric_mod_name + "_exit(void)\n"	340	buf += "static void __exit " + fabric_mod_name + "_exit(void)\n"
334	buf += "{\n"	341	buf += "{\n"
335	buf += " target_unregister_template(" + fabric_mod_name + "_ops);\n"	342	buf += " target_unregister_template(&" + fabric_mod_name + "_ops);\n"
336	buf += "};\n\n"	343	buf += "};\n\n"
337		344
338	buf += "MODULE_DESCRIPTION(\"" + fabric_mod_name.upper() + " series fabric driver\");\n"	345	buf += "MODULE_DESCRIPTION(\"" + fabric_mod_name.upper() + " series fabric driver\");\n"

MAINTAINERS+29−2

 F:	drivers/gpu/drm/rockchip/
 F:	Documentation/devicetree/bindings/video/rockchip*
+DRM DRIVERS FOR STI
+M:	Benjamin Gaignard <benjamin.gaignard@linaro.org>
+M:	Vincent Abriou <vincent.abriou@st.com>
+L:	dri-devel@lists.freedesktop.org
+T:	git http://git.linaro.org/people/benjamin.gaignard/kernel.git
+S:	Maintained
+F:	drivers/gpu/drm/sti
+F:	Documentation/devicetree/bindings/gpu/st,stih4xx.txt
 DSBR100 USB FM RADIO DRIVER
 M:	Alexey Klimov <klimov.linux@gmail.com>
 L:	linux-media@vger.kernel.org
 IRQCHIP DRIVERS
 M:	Thomas Gleixner <tglx@linutronix.de>
 M:	Jason Cooper <jason@lakedaemon.net>
+M:	Marc Zyngier <marc.zyngier@arm.com>
 L:	linux-kernel@vger.kernel.org
 S:	Maintained
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
 F:	drivers/irqchip/
 IRQ DOMAINS (IRQ NUMBER MAPPING LIBRARY)
-M:	Benjamin Herrenschmidt <benh@kernel.crashing.org>
+M:	Jiang Liu <jiang.liu@linux.intel.com>
+M:	Marc Zyngier <marc.zyngier@arm.com>
 S:	Maintained
+T:	git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
 F:	Documentation/IRQ-domain.txt
 F:	include/linux/irqdomain.h
 F:	kernel/irq/irqdomain.c
+F:	kernel/irq/msi.c
 ISAPNP
 M:	Jaroslav Kysela <perex@perex.cz>
 F:	Documentation/s390/kvm.txt
 F:	arch/s390/include/asm/kvm*
 F:	arch/s390/kvm/
-F:	drivers/s390/kvm/
 KERNEL VIRTUAL MACHINE (KVM) FOR ARM
 M:	Christoffer Dall <christoffer.dall@linaro.org>
 S:	Maintained
 F:	drivers/media/usb/msi2500/
+MSYSTEMS DISKONCHIP G3 MTD DRIVER
+M:	Robert Jarzmik <robert.jarzmik@free.fr>
+L:	linux-mtd@lists.infradead.org
+S:	Maintained
+F:	drivers/mtd/devices/docg3*
 MT9M032 APTINA SENSOR DRIVER
 M:	Laurent Pinchart <laurent.pinchart@ideasonboard.com>
 L:	linux-media@vger.kernel.org
 F:	include/linux/virtio_*.h
 F:	include/uapi/linux/virtio_*.h
+VIRTIO DRIVERS FOR S390
+M:	Christian Borntraeger <borntraeger@de.ibm.com>
+M:	Cornelia Huck <cornelia.huck@de.ibm.com>
+L:	linux-s390@vger.kernel.org
+L:	virtualization@lists.linux-foundation.org
+L:	kvm@vger.kernel.org
+S:	Supported
+F:	drivers/s390/virtio/
 VIRTIO GPU DRIVER
 M:	David Airlie <airlied@linux.ie>
 M:	Gerd Hoffmann <kraxel@redhat.com>

Makefile+8−3

 VERSION = 4
 PATCHLEVEL = 2
 SUBLEVEL = 0
-EXTRAVERSION = -rc3
+EXTRAVERSION = -rc7
 NAME = Hurr durr I'ma sheep
 # *DOCUMENTATION*
 # Defaults to vmlinux, but the arch makefile usually adds further targets
 all: vmlinux
+# The arch Makefile can set ARCH_{CPP,A,C}FLAGS to override the default
+# values of the respective KBUILD_* variables
+ARCH_CPPFLAGS :=
+ARCH_AFLAGS :=
+ARCH_CFLAGS :=
 include arch/$(SRCARCH)/Makefile
 KBUILD_CFLAGS	+= $(call cc-option,-fno-delete-null-pointer-checks,)
 mod_compress_cmd = true
 ifdef CONFIG_MODULE_COMPRESS
   ifdef CONFIG_MODULE_COMPRESS_GZIP
-    mod_compress_cmd = gzip -n
+    mod_compress_cmd = gzip -n -f
   endif # CONFIG_MODULE_COMPRESS_GZIP
   ifdef CONFIG_MODULE_COMPRESS_XZ
-    mod_compress_cmd = xz
+    mod_compress_cmd = xz -f
   endif # CONFIG_MODULE_COMPRESS_XZ
 endif # CONFIG_MODULE_COMPRESS
 export mod_compress_cmd

arch/arc/Kconfig+11−2

 config ARC_PAGE_SIZE_16K
 	bool "16KB"
-	depends on ARC_MMU_V3
+	depends on ARC_MMU_V3 || ARC_MMU_V4
 config ARC_PAGE_SIZE_4K
 	bool "4KB"
-	depends on ARC_MMU_V3
+	depends on ARC_MMU_V3 || ARC_MMU_V4
 endchoice
 	default y
 	depends on !ARC_CANT_LLSC
+config ARC_STAR_9000923308
+	bool "Workaround for llock/scond livelock"
+	default y
+	depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC
 config ARC_HAS_SWAPE
 	bool "Insn: SWAPE (endian-swap)"
 	default y
 	  dest operands with 2 possible source operands.
 	default y
+config ARC_HAS_DIV_REM
+	bool "Insn: div, divu, rem, remu"
+	default y
 config ARC_HAS_RTC
 	bool "Local 64-bit r/o cycle counter"
 	default n

arch/arc/Makefile+9−1

 cflags-$(CONFIG_ARC_HAS_LLSC)		+= -mlock
 cflags-$(CONFIG_ARC_HAS_SWAPE)		+= -mswape
+ifdef CONFIG_ISA_ARCV2
 ifndef CONFIG_ARC_HAS_LL64
-cflags-$(CONFIG_ISA_ARCV2)		+= -mno-ll64
+cflags-y				+= -mno-ll64
+endif
+ifndef CONFIG_ARC_HAS_DIV_REM
+cflags-y				+= -mno-div-rem
+endif
 endif
 cflags-$(CONFIG_ARC_DW2_UNWIND)		+= -fasynchronous-unwind-tables

arch/arc/include/asm/arcregs.h+3−4

@@ -89,11 +89,10 @@ · 88 unmodified lines
89	#define ECR_C_BIT_DTLB_LD_MISS 8	89	#define ECR_C_BIT_DTLB_LD_MISS 8
90	#define ECR_C_BIT_DTLB_ST_MISS 9	90	#define ECR_C_BIT_DTLB_ST_MISS 9
91		91
92
93	/* Auxiliary registers */	92	/* Auxiliary registers */
94	#define AUX_IDENTITY 4	93	#define AUX_IDENTITY 4
95	#define AUX_INTR_VEC_BASE 0x25	94	#define AUX_INTR_VEC_BASE 0x25
96		95	#define AUX_NON_VOL 0x5e
97		96
98	/*	97	/*
99	* Floating Pt Registers	98	* Floating Pt Registers
@@ -240,9 +239,9 @@ struct bcr_extn_xymem { · 140 unmodified lines
240		239
241	struct bcr_perip {	240	struct bcr_perip {
242	#ifdef CONFIG_CPU_BIG_ENDIAN	241	#ifdef CONFIG_CPU_BIG_ENDIAN
243	unsigned int start:8, pad2:8, sz:8, pad:8;	242	unsigned int start:8, pad2:8, sz:8, ver:8;
244	#else	243	#else
245	unsigned int pad:8, sz:8, pad2:8, start:8;	244	unsigned int ver:8, sz:8, pad2:8, start:8;
246	#endif	245	#endif
247	};	246	};
248		247

arch/arc/include/asm/atomic.h+55−23

@@ -23,33 +23,60 @@ · 22 unmodified lines
23		23
24	#define atomic_set(v, i) (((v)->counter) = (i))	24	#define atomic_set(v, i) (((v)->counter) = (i))
25		25
26	#ifdef CONFIG_ISA_ARCV2	26	#ifdef CONFIG_ARC_STAR_9000923308
27	#define PREFETCHW " prefetchw [%1] \n"	27
28	#else	28	#define SCOND_FAIL_RETRY_VAR_DEF \
29	#define PREFETCHW	29	unsigned int delay = 1, tmp; \
		30
		31	#define SCOND_FAIL_RETRY_ASM \
		32	" bz 4f \n" \
		33	" ; --- scond fail delay --- \n" \
		34	" mov %[tmp], %[delay] \n" /* tmp = delay */ \
		35	"2: brne.d %[tmp], 0, 2b \n" /* while (tmp != 0) */ \
		36	" sub %[tmp], %[tmp], 1 \n" /* tmp-- */ \
		37	" rol %[delay], %[delay] \n" /* delay = 2 / \
		38	" b 1b \n" /* start over */ \
		39	"4: ; --- success --- \n" \
		40
		41	#define SCOND_FAIL_RETRY_VARS \
		42	,[delay] "+&r" (delay),[tmp] "=&r" (tmp) \
		43
		44	#else /* !CONFIG_ARC_STAR_9000923308 */
		45
		46	#define SCOND_FAIL_RETRY_VAR_DEF
		47
		48	#define SCOND_FAIL_RETRY_ASM \
		49	" bnz 1b \n" \
		50
		51	#define SCOND_FAIL_RETRY_VARS
		52
30	#endif	53	#endif
31		54
32	#define ATOMIC_OP(op, c_op, asm_op) \	55	#define ATOMIC_OP(op, c_op, asm_op) \
33	static inline void atomic_##op(int i, atomic_t *v) \	56	static inline void atomic_##op(int i, atomic_t *v) \
34	{ \	57	{ \
35	unsigned int temp; \	58	unsigned int val; \
		59	SCOND_FAIL_RETRY_VAR_DEF \
36	\	60	\
37	__asm__ __volatile__( \	61	__asm__ __volatile__( \
38	"1: \n" \	62	"1: llock %[val], [%[ctr]] \n" \
39	PREFETCHW \	63	" " #asm_op " %[val], %[val], %[i] \n" \
40	" llock %0, [%1] \n" \	64	" scond %[val], [%[ctr]] \n" \
41	" " #asm_op " %0, %0, %2 \n" \	65	" \n" \
42	" scond %0, [%1] \n" \	66	SCOND_FAIL_RETRY_ASM \
43	" bnz 1b \n" \	67	\
44	: "=&r"(temp) /* Early clobber, to prevent reg reuse */ \	68	: [val] "=&r" (val) /* Early clobber to prevent reg reuse */ \
45	: "r"(&v->counter), "ir"(i) \	69	SCOND_FAIL_RETRY_VARS \
		70	: [ctr] "r" (&v->counter), /* Not "m": llock only supports reg direct addr mode */ \
		71	[i] "ir" (i) \
46	: "cc"); \	72	: "cc"); \
47	} \	73	} \
48		74
49	#define ATOMIC_OP_RETURN(op, c_op, asm_op) \	75	#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
50	static inline int atomic_##op##_return(int i, atomic_t *v) \	76	static inline int atomic_##op##_return(int i, atomic_t *v) \
51	{ \	77	{ \
52	unsigned int temp; \	78	unsigned int val; \
		79	SCOND_FAIL_RETRY_VAR_DEF \
53	\	80	\
54	/* \	81	/* \
55	* Explicit full memory barrier needed before/after as \	82	* Explicit full memory barrier needed before/after as \
@@ -58,19 +85,21 @@ static inline int atomic_##op##_return(int i, atomic_t *v) \ · 2 unmodified lines
58	smp_mb(); \	85	smp_mb(); \
59	\	86	\
60	__asm__ __volatile__( \	87	__asm__ __volatile__( \
61	"1: \n" \	88	"1: llock %[val], [%[ctr]] \n" \
62	PREFETCHW \	89	" " #asm_op " %[val], %[val], %[i] \n" \
63	" llock %0, [%1] \n" \	90	" scond %[val], [%[ctr]] \n" \
64	" " #asm_op " %0, %0, %2 \n" \	91	" \n" \
65	" scond %0, [%1] \n" \	92	SCOND_FAIL_RETRY_ASM \
66	" bnz 1b \n" \	93	\
67	: "=&r"(temp) \	94	: [val] "=&r" (val) \
68	: "r"(&v->counter), "ir"(i) \	95	SCOND_FAIL_RETRY_VARS \
		96	: [ctr] "r" (&v->counter), \
		97	[i] "ir" (i) \
69	: "cc"); \	98	: "cc"); \
70	\	99	\
71	smp_mb(); \	100	smp_mb(); \
72	\	101	\
73	return temp; \	102	return val; \
74	}	103	}
75		104
76	#else /* !CONFIG_ARC_HAS_LLSC */	105	#else /* !CONFIG_ARC_HAS_LLSC */
@@ -150,6 +179,9 @@ ATOMIC_OP(and, &=, and) · 73 unmodified lines
150	#undef ATOMIC_OPS	179	#undef ATOMIC_OPS
151	#undef ATOMIC_OP_RETURN	180	#undef ATOMIC_OP_RETURN
152	#undef ATOMIC_OP	181	#undef ATOMIC_OP
		182	#undef SCOND_FAIL_RETRY_VAR_DEF
		183	#undef SCOND_FAIL_RETRY_ASM
		184	#undef SCOND_FAIL_RETRY_VARS
153		185
154	/**	186	/**
155	* __atomic_add_unless - add unless the number is a given value	187	* __atomic_add_unless - add unless the number is a given value

arch/arc/include/asm/ptrace.h+27−27

@@ -20,20 +20,20 @@ · 19 unmodified lines
20	struct pt_regs {	20	struct pt_regs {
21		21
22	/* Real registers */	22	/* Real registers */
23	long bta; /* bta_l1, bta_l2, erbta */	23	unsigned long bta; /* bta_l1, bta_l2, erbta */
24		24
25	long lp_start, lp_end, lp_count;	25	unsigned long lp_start, lp_end, lp_count;
26		26
27	long status32; /* status32_l1, status32_l2, erstatus */	27	unsigned long status32; /* status32_l1, status32_l2, erstatus */
28	long ret; /* ilink1, ilink2 or eret */	28	unsigned long ret; /* ilink1, ilink2 or eret */
29	long blink;	29	unsigned long blink;
30	long fp;	30	unsigned long fp;
31	long r26; /* gp */	31	unsigned long r26; /* gp */
32		32
33	long r12, r11, r10, r9, r8, r7, r6, r5, r4, r3, r2, r1, r0;	33	unsigned long r12, r11, r10, r9, r8, r7, r6, r5, r4, r3, r2, r1, r0;
34		34
35	long sp; /* user/kernel sp depending on where we came from */	35	unsigned long sp; /* User/Kernel depending on where we came from */
36	long orig_r0;	36	unsigned long orig_r0;
37		37
38	/*	38	/*
39	* To distinguish bet excp, syscall, irq	39	* To distinguish bet excp, syscall, irq
@@ -55,13 +55,13 @@ struct pt_regs { · 15 unmodified lines
55	unsigned long event;	55	unsigned long event;
56	};	56	};
57		57
58	long user_r25;	58	unsigned long user_r25;
59	};	59	};
60	#else	60	#else
61		61
62	struct pt_regs {	62	struct pt_regs {
63		63
64	long orig_r0;	64	unsigned long orig_r0;
65		65
66	union {	66	union {
67	struct {	67	struct {
@@ -76,26 +76,26 @@ struct pt_regs { · 8 unmodified lines
76	unsigned long event;	76	unsigned long event;
77	};	77	};
78		78
79	long bta; /* bta_l1, bta_l2, erbta */	79	unsigned long bta; /* bta_l1, bta_l2, erbta */
80		80
81	long user_r25;	81	unsigned long user_r25;
82		82
83	long r26; /* gp */	83	unsigned long r26; /* gp */
84	long fp;	84	unsigned long fp;
85	long sp; /* user/kernel sp depending on where we came from */	85	unsigned long sp; /* user/kernel sp depending on where we came from */
86		86
87	long r12;	87	unsigned long r12;
88		88
89	/------- Below list auto saved by h/w -----------/	89	/------- Below list auto saved by h/w -----------/
90	long r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11;	90	unsigned long r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11;
91		91
92	long blink;	92	unsigned long blink;
93	long lp_end, lp_start, lp_count;	93	unsigned long lp_end, lp_start, lp_count;
94		94
95	long ei, ldi, jli;	95	unsigned long ei, ldi, jli;
96		96
97	long ret;	97	unsigned long ret;
98	long status32;	98	unsigned long status32;
99	};	99	};
100		100
101	#endif	101	#endif
@@ -103,10 +103,10 @@ struct pt_regs { · 1 unmodified line
103	/* Callee saved registers - need to be saved only when you are scheduled out */	103	/* Callee saved registers - need to be saved only when you are scheduled out */
104		104
105	struct callee_regs {	105	struct callee_regs {
106	long r25, r24, r23, r22, r21, r20, r19, r18, r17, r16, r15, r14, r13;	106	unsigned long r25, r24, r23, r22, r21, r20, r19, r18, r17, r16, r15, r14, r13;
107	};	107	};
108		108
109	#define instruction_pointer(regs) (unsigned long)((regs)->ret)	109	#define instruction_pointer(regs) ((regs)->ret)
110	#define profile_pc(regs) instruction_pointer(regs)	110	#define profile_pc(regs) instruction_pointer(regs)
111		111
112	/* return 1 if user mode or 0 if kernel mode */	112	/* return 1 if user mode or 0 if kernel mode */
@@ -142,7 +142,7 @@ struct callee_regs { · 29 unmodified lines
142		142
143	static inline long regs_return_value(struct pt_regs *regs)	143	static inline long regs_return_value(struct pt_regs *regs)
144	{	144	{
145	return regs->r0;	145	return (long)regs->r0;
146	}	146	}
147		147
148	#endif /* !__ASSEMBLY__ */	148	#endif /* !__ASSEMBLY__ */

arch/arc/include/asm/spinlock.h+523−15

@@ -18,9 +18,518 @@ · 17 unmodified lines
18	#define arch_spin_unlock_wait(x) \	18	#define arch_spin_unlock_wait(x) \
19	do { while (arch_spin_is_locked(x)) cpu_relax(); } while (0)	19	do { while (arch_spin_is_locked(x)) cpu_relax(); } while (0)
20		20
		21	#ifdef CONFIG_ARC_HAS_LLSC
		22
		23	/*
		24	* A normal LLOCK/SCOND based system, w/o need for livelock workaround
		25	*/
		26	#ifndef CONFIG_ARC_STAR_9000923308
		27
21	static inline void arch_spin_lock(arch_spinlock_t *lock)	28	static inline void arch_spin_lock(arch_spinlock_t *lock)
22	{	29	{
23	unsigned int tmp = __ARCH_SPIN_LOCK_LOCKED__;	30	unsigned int val;
		31
		32	smp_mb();
		33
		34	__asm__ __volatile__(
		35	"1: llock %[val], [%[slock]] \n"
		36	" breq %[val], %[LOCKED], 1b \n" /* spin while LOCKED */
		37	" scond %[LOCKED], [%[slock]] \n" /* acquire */
		38	" bnz 1b \n"
		39	" \n"
		40	: [val] "=&r" (val)
		41	: [slock] "r" (&(lock->slock)),
		42	[LOCKED] "r" (__ARCH_SPIN_LOCK_LOCKED__)
		43	: "memory", "cc");
		44
		45	smp_mb();
		46	}
		47
		48	/* 1 - lock taken successfully */
		49	static inline int arch_spin_trylock(arch_spinlock_t *lock)
		50	{
		51	unsigned int val, got_it = 0;
		52
		53	smp_mb();
		54
		55	__asm__ __volatile__(
		56	"1: llock %[val], [%[slock]] \n"
		57	" breq %[val], %[LOCKED], 4f \n" /* already LOCKED, just bail */
		58	" scond %[LOCKED], [%[slock]] \n" /* acquire */
		59	" bnz 1b \n"
		60	" mov %[got_it], 1 \n"
		61	"4: \n"
		62	" \n"
		63	: [val] "=&r" (val),
		64	[got_it] "+&r" (got_it)
		65	: [slock] "r" (&(lock->slock)),
		66	[LOCKED] "r" (__ARCH_SPIN_LOCK_LOCKED__)
		67	: "memory", "cc");
		68
		69	smp_mb();
		70
		71	return got_it;
		72	}
		73
		74	static inline void arch_spin_unlock(arch_spinlock_t *lock)
		75	{
		76	smp_mb();
		77
		78	lock->slock = __ARCH_SPIN_LOCK_UNLOCKED__;
		79
		80	smp_mb();
		81	}
		82
		83	/*
		84	* Read-write spinlocks, allowing multiple readers but only one writer.
		85	* Unfair locking as Writers could be starved indefinitely by Reader(s)
		86	*/
		87
		88	static inline void arch_read_lock(arch_rwlock_t *rw)
		89	{
		90	unsigned int val;
		91
		92	smp_mb();
		93
		94	/*
		95	* zero means writer holds the lock exclusively, deny Reader.
		96	* Otherwise grant lock to first/subseq reader
		97	*
		98	* if (rw->counter > 0) {
		99	* rw->counter--;
		100	* ret = 1;
		101	* }
		102	*/
		103
		104	__asm__ __volatile__(
		105	"1: llock %[val], [%[rwlock]] \n"
		106	" brls %[val], %[WR_LOCKED], 1b\n" /* <= 0: spin while write locked */
		107	" sub %[val], %[val], 1 \n" /* reader lock */
		108	" scond %[val], [%[rwlock]] \n"
		109	" bnz 1b \n"
		110	" \n"
		111	: [val] "=&r" (val)
		112	: [rwlock] "r" (&(rw->counter)),
		113	[WR_LOCKED] "ir" (0)
		114	: "memory", "cc");
		115
		116	smp_mb();
		117	}
		118
		119	/* 1 - lock taken successfully */
		120	static inline int arch_read_trylock(arch_rwlock_t *rw)
		121	{
		122	unsigned int val, got_it = 0;
		123
		124	smp_mb();
		125
		126	__asm__ __volatile__(
		127	"1: llock %[val], [%[rwlock]] \n"
		128	" brls %[val], %[WR_LOCKED], 4f\n" /* <= 0: already write locked, bail */
		129	" sub %[val], %[val], 1 \n" /* counter-- */
		130	" scond %[val], [%[rwlock]] \n"
		131	" bnz 1b \n" /* retry if collided with someone */
		132	" mov %[got_it], 1 \n"
		133	" \n"
		134	"4: ; --- done --- \n"
		135
		136	: [val] "=&r" (val),
		137	[got_it] "+&r" (got_it)
		138	: [rwlock] "r" (&(rw->counter)),
		139	[WR_LOCKED] "ir" (0)
		140	: "memory", "cc");
		141
		142	smp_mb();
		143
		144	return got_it;
		145	}
		146
		147	static inline void arch_write_lock(arch_rwlock_t *rw)
		148	{
		149	unsigned int val;
		150
		151	smp_mb();
		152
		153	/*
		154	* If reader(s) hold lock (lock < __ARCH_RW_LOCK_UNLOCKED__),
		155	* deny writer. Otherwise if unlocked grant to writer
		156	* Hence the claim that Linux rwlocks are unfair to writers.
		157	* (can be starved for an indefinite time by readers).
		158	*
		159	* if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) {
		160	* rw->counter = 0;
		161	* ret = 1;
		162	* }
		163	*/
		164
		165	__asm__ __volatile__(
		166	"1: llock %[val], [%[rwlock]] \n"
		167	" brne %[val], %[UNLOCKED], 1b \n" /* while !UNLOCKED spin */
		168	" mov %[val], %[WR_LOCKED] \n"
		169	" scond %[val], [%[rwlock]] \n"
		170	" bnz 1b \n"
		171	" \n"
		172	: [val] "=&r" (val)
		173	: [rwlock] "r" (&(rw->counter)),
		174	[UNLOCKED] "ir" (__ARCH_RW_LOCK_UNLOCKED__),
		175	[WR_LOCKED] "ir" (0)
		176	: "memory", "cc");
		177
		178	smp_mb();
		179	}
		180
		181	/* 1 - lock taken successfully */
		182	static inline int arch_write_trylock(arch_rwlock_t *rw)
		183	{
		184	unsigned int val, got_it = 0;
		185
		186	smp_mb();
		187
		188	__asm__ __volatile__(
		189	"1: llock %[val], [%[rwlock]] \n"
		190	" brne %[val], %[UNLOCKED], 4f \n" /* !UNLOCKED, bail */
		191	" mov %[val], %[WR_LOCKED] \n"
		192	" scond %[val], [%[rwlock]] \n"
		193	" bnz 1b \n" /* retry if collided with someone */
		194	" mov %[got_it], 1 \n"
		195	" \n"
		196	"4: ; --- done --- \n"
		197
		198	: [val] "=&r" (val),
		199	[got_it] "+&r" (got_it)
		200	: [rwlock] "r" (&(rw->counter)),
		201	[UNLOCKED] "ir" (__ARCH_RW_LOCK_UNLOCKED__),
		202	[WR_LOCKED] "ir" (0)
		203	: "memory", "cc");
		204
		205	smp_mb();
		206
		207	return got_it;
		208	}
		209
		210	static inline void arch_read_unlock(arch_rwlock_t *rw)
		211	{
		212	unsigned int val;
		213
		214	smp_mb();
		215
		216	/*
		217	* rw->counter++;
		218	*/
		219	__asm__ __volatile__(
		220	"1: llock %[val], [%[rwlock]] \n"
		221	" add %[val], %[val], 1 \n"
		222	" scond %[val], [%[rwlock]] \n"
		223	" bnz 1b \n"
		224	" \n"
		225	: [val] "=&r" (val)
		226	: [rwlock] "r" (&(rw->counter))
		227	: "memory", "cc");
		228
		229	smp_mb();
		230	}
		231
		232	static inline void arch_write_unlock(arch_rwlock_t *rw)
		233	{
		234	smp_mb();
		235
		236	rw->counter = __ARCH_RW_LOCK_UNLOCKED__;
		237
		238	smp_mb();
		239	}
		240
		241	#else /* CONFIG_ARC_STAR_9000923308 */
		242
		243	/*
		244	* HS38x4 could get into a LLOCK/SCOND livelock in case of multiple overlapping
		245	* coherency transactions in the SCU. The exclusive line state keeps rotating
		246	* among contenting cores leading to a never ending cycle. So break the cycle
		247	* by deferring the retry of failed exclusive access (SCOND). The actual delay
		248	* needed is function of number of contending cores as well as the unrelated
		249	* coherency traffic from other cores. To keep the code simple, start off with
		250	* small delay of 1 which would suffice most cases and in case of contention
		251	* double the delay. Eventually the delay is sufficient such that the coherency
		252	* pipeline is drained, thus a subsequent exclusive access would succeed.
		253	*/
		254
		255	#define SCOND_FAIL_RETRY_VAR_DEF \
		256	unsigned int delay, tmp; \
		257
		258	#define SCOND_FAIL_RETRY_ASM \
		259	" ; --- scond fail delay --- \n" \
		260	" mov %[tmp], %[delay] \n" /* tmp = delay */ \
		261	"2: brne.d %[tmp], 0, 2b \n" /* while (tmp != 0) */ \
		262	" sub %[tmp], %[tmp], 1 \n" /* tmp-- */ \
		263	" rol %[delay], %[delay] \n" /* delay = 2 / \
		264	" b 1b \n" /* start over */ \
		265	" \n" \
		266	"4: ; --- done --- \n" \
		267
		268	#define SCOND_FAIL_RETRY_VARS \
		269	,[delay] "=&r" (delay), [tmp] "=&r" (tmp) \
		270
		271	static inline void arch_spin_lock(arch_spinlock_t *lock)
		272	{
		273	unsigned int val;
		274	SCOND_FAIL_RETRY_VAR_DEF;
		275
		276	smp_mb();
		277
		278	__asm__ __volatile__(
		279	"0: mov %[delay], 1 \n"
		280	"1: llock %[val], [%[slock]] \n"
		281	" breq %[val], %[LOCKED], 0b \n" /* spin while LOCKED */
		282	" scond %[LOCKED], [%[slock]] \n" /* acquire */
		283	" bz 4f \n" /* done */
		284	" \n"
		285	SCOND_FAIL_RETRY_ASM
		286
		287	: [val] "=&r" (val)
		288	SCOND_FAIL_RETRY_VARS
		289	: [slock] "r" (&(lock->slock)),
		290	[LOCKED] "r" (__ARCH_SPIN_LOCK_LOCKED__)
		291	: "memory", "cc");
		292
		293	smp_mb();
		294	}
		295
		296	/* 1 - lock taken successfully */
		297	static inline int arch_spin_trylock(arch_spinlock_t *lock)
		298	{
		299	unsigned int val, got_it = 0;
		300	SCOND_FAIL_RETRY_VAR_DEF;
		301
		302	smp_mb();
		303
		304	__asm__ __volatile__(
		305	"0: mov %[delay], 1 \n"
		306	"1: llock %[val], [%[slock]] \n"
		307	" breq %[val], %[LOCKED], 4f \n" /* already LOCKED, just bail */
		308	" scond %[LOCKED], [%[slock]] \n" /* acquire */
		309	" bz.d 4f \n"
		310	" mov.z %[got_it], 1 \n" /* got it */
		311	" \n"
		312	SCOND_FAIL_RETRY_ASM
		313
		314	: [val] "=&r" (val),
		315	[got_it] "+&r" (got_it)
		316	SCOND_FAIL_RETRY_VARS
		317	: [slock] "r" (&(lock->slock)),
		318	[LOCKED] "r" (__ARCH_SPIN_LOCK_LOCKED__)
		319	: "memory", "cc");
		320
		321	smp_mb();
		322
		323	return got_it;
		324	}
		325
		326	static inline void arch_spin_unlock(arch_spinlock_t *lock)
		327	{
		328	smp_mb();
		329
		330	lock->slock = __ARCH_SPIN_LOCK_UNLOCKED__;
		331
		332	smp_mb();
		333	}
		334
		335	/*
		336	* Read-write spinlocks, allowing multiple readers but only one writer.
		337	* Unfair locking as Writers could be starved indefinitely by Reader(s)
		338	*/
		339
		340	static inline void arch_read_lock(arch_rwlock_t *rw)
		341	{
		342	unsigned int val;
		343	SCOND_FAIL_RETRY_VAR_DEF;
		344
		345	smp_mb();
		346
		347	/*
		348	* zero means writer holds the lock exclusively, deny Reader.
		349	* Otherwise grant lock to first/subseq reader
		350	*
		351	* if (rw->counter > 0) {
		352	* rw->counter--;
		353	* ret = 1;
		354	* }
		355	*/
		356
		357	__asm__ __volatile__(
		358	"0: mov %[delay], 1 \n"
		359	"1: llock %[val], [%[rwlock]] \n"
		360	" brls %[val], %[WR_LOCKED], 0b\n" /* <= 0: spin while write locked */
		361	" sub %[val], %[val], 1 \n" /* reader lock */
		362	" scond %[val], [%[rwlock]] \n"
		363	" bz 4f \n" /* done */
		364	" \n"
		365	SCOND_FAIL_RETRY_ASM
		366
		367	: [val] "=&r" (val)
		368	SCOND_FAIL_RETRY_VARS
		369	: [rwlock] "r" (&(rw->counter)),
		370	[WR_LOCKED] "ir" (0)
		371	: "memory", "cc");
		372
		373	smp_mb();
		374	}
		375
		376	/* 1 - lock taken successfully */
		377	static inline int arch_read_trylock(arch_rwlock_t *rw)
		378	{
		379	unsigned int val, got_it = 0;
		380	SCOND_FAIL_RETRY_VAR_DEF;
		381
		382	smp_mb();
		383
		384	__asm__ __volatile__(
		385	"0: mov %[delay], 1 \n"
		386	"1: llock %[val], [%[rwlock]] \n"
		387	" brls %[val], %[WR_LOCKED], 4f\n" /* <= 0: already write locked, bail */
		388	" sub %[val], %[val], 1 \n" /* counter-- */
		389	" scond %[val], [%[rwlock]] \n"
		390	" bz.d 4f \n"
		391	" mov.z %[got_it], 1 \n" /* got it */
		392	" \n"
		393	SCOND_FAIL_RETRY_ASM
		394
		395	: [val] "=&r" (val),
		396	[got_it] "+&r" (got_it)
		397	SCOND_FAIL_RETRY_VARS
		398	: [rwlock] "r" (&(rw->counter)),
		399	[WR_LOCKED] "ir" (0)
		400	: "memory", "cc");
		401
		402	smp_mb();
		403
		404	return got_it;
		405	}
		406
		407	static inline void arch_write_lock(arch_rwlock_t *rw)
		408	{
		409	unsigned int val;
		410	SCOND_FAIL_RETRY_VAR_DEF;
		411
		412	smp_mb();
		413
		414	/*
		415	* If reader(s) hold lock (lock < __ARCH_RW_LOCK_UNLOCKED__),
		416	* deny writer. Otherwise if unlocked grant to writer
		417	* Hence the claim that Linux rwlocks are unfair to writers.
		418	* (can be starved for an indefinite time by readers).
		419	*
		420	* if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) {
		421	* rw->counter = 0;
		422	* ret = 1;
		423	* }
		424	*/
		425
		426	__asm__ __volatile__(
		427	"0: mov %[delay], 1 \n"
		428	"1: llock %[val], [%[rwlock]] \n"
		429	" brne %[val], %[UNLOCKED], 0b \n" /* while !UNLOCKED spin */
		430	" mov %[val], %[WR_LOCKED] \n"
		431	" scond %[val], [%[rwlock]] \n"
		432	" bz 4f \n"
		433	" \n"
		434	SCOND_FAIL_RETRY_ASM
		435
		436	: [val] "=&r" (val)
		437	SCOND_FAIL_RETRY_VARS
		438	: [rwlock] "r" (&(rw->counter)),
		439	[UNLOCKED] "ir" (__ARCH_RW_LOCK_UNLOCKED__),
		440	[WR_LOCKED] "ir" (0)
		441	: "memory", "cc");
		442
		443	smp_mb();
		444	}
		445
		446	/* 1 - lock taken successfully */
		447	static inline int arch_write_trylock(arch_rwlock_t *rw)
		448	{
		449	unsigned int val, got_it = 0;
		450	SCOND_FAIL_RETRY_VAR_DEF;
		451
		452	smp_mb();
		453
		454	__asm__ __volatile__(
		455	"0: mov %[delay], 1 \n"
		456	"1: llock %[val], [%[rwlock]] \n"
		457	" brne %[val], %[UNLOCKED], 4f \n" /* !UNLOCKED, bail */
		458	" mov %[val], %[WR_LOCKED] \n"
		459	" scond %[val], [%[rwlock]] \n"
		460	" bz.d 4f \n"
		461	" mov.z %[got_it], 1 \n" /* got it */
		462	" \n"
		463	SCOND_FAIL_RETRY_ASM
		464
		465	: [val] "=&r" (val),
		466	[got_it] "+&r" (got_it)
		467	SCOND_FAIL_RETRY_VARS
		468	: [rwlock] "r" (&(rw->counter)),
		469	[UNLOCKED] "ir" (__ARCH_RW_LOCK_UNLOCKED__),
		470	[WR_LOCKED] "ir" (0)
		471	: "memory", "cc");
		472
		473	smp_mb();
		474
		475	return got_it;
		476	}
		477
		478	static inline void arch_read_unlock(arch_rwlock_t *rw)
		479	{
		480	unsigned int val;
		481
		482	smp_mb();
		483
		484	/*
		485	* rw->counter++;
		486	*/
		487	__asm__ __volatile__(
		488	"1: llock %[val], [%[rwlock]] \n"
		489	" add %[val], %[val], 1 \n"
		490	" scond %[val], [%[rwlock]] \n"
		491	" bnz 1b \n"
		492	" \n"
		493	: [val] "=&r" (val)
		494	: [rwlock] "r" (&(rw->counter))
		495	: "memory", "cc");
		496
		497	smp_mb();
		498	}
		499
		500	static inline void arch_write_unlock(arch_rwlock_t *rw)
		501	{
		502	unsigned int val;
		503
		504	smp_mb();
		505
		506	/*
		507	* rw->counter = __ARCH_RW_LOCK_UNLOCKED__;
		508	*/
		509	__asm__ __volatile__(
		510	"1: llock %[val], [%[rwlock]] \n"
		511	" scond %[UNLOCKED], [%[rwlock]]\n"
		512	" bnz 1b \n"
		513	" \n"
		514	: [val] "=&r" (val)
		515	: [rwlock] "r" (&(rw->counter)),
		516	[UNLOCKED] "r" (__ARCH_RW_LOCK_UNLOCKED__)
		517	: "memory", "cc");
		518
		519	smp_mb();
		520	}
		521
		522	#undef SCOND_FAIL_RETRY_VAR_DEF
		523	#undef SCOND_FAIL_RETRY_ASM
		524	#undef SCOND_FAIL_RETRY_VARS
		525
		526	#endif /* CONFIG_ARC_STAR_9000923308 */
		527
		528	#else /* !CONFIG_ARC_HAS_LLSC */
		529
		530	static inline void arch_spin_lock(arch_spinlock_t *lock)
		531	{
		532	unsigned int val = __ARCH_SPIN_LOCK_LOCKED__;
24		533
25	/*	534	/*
26	* This smp_mb() is technically superfluous, we only need the one	535	* This smp_mb() is technically superfluous, we only need the one
@@ -33,7 +542,7 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) · 6 unmodified lines
33	__asm__ __volatile__(	542	__asm__ __volatile__(
34	"1: ex %0, [%1] \n"	543	"1: ex %0, [%1] \n"
35	" breq %0, %2, 1b \n"	544	" breq %0, %2, 1b \n"
36	: "+&r" (tmp)	545	: "+&r" (val)
37	: "r"(&(lock->slock)), "ir"(__ARCH_SPIN_LOCK_LOCKED__)	546	: "r"(&(lock->slock)), "ir"(__ARCH_SPIN_LOCK_LOCKED__)
38	: "memory");	547	: "memory");
39		548
@@ -48,26 +557,27 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) · 8 unmodified lines
48	smp_mb();	557	smp_mb();
49	}	558	}
50		559
		560	/* 1 - lock taken successfully */
51	static inline int arch_spin_trylock(arch_spinlock_t *lock)	561	static inline int arch_spin_trylock(arch_spinlock_t *lock)
52	{	562	{
53	unsigned int tmp = __ARCH_SPIN_LOCK_LOCKED__;	563	unsigned int val = __ARCH_SPIN_LOCK_LOCKED__;
54		564
55	smp_mb();	565	smp_mb();
56		566
57	__asm__ __volatile__(	567	__asm__ __volatile__(
58	"1: ex %0, [%1] \n"	568	"1: ex %0, [%1] \n"
59	: "+r" (tmp)	569	: "+r" (val)
60	: "r"(&(lock->slock))	570	: "r"(&(lock->slock))
61	: "memory");	571	: "memory");
62		572
63	smp_mb();	573	smp_mb();
64		574
65	return (tmp == __ARCH_SPIN_LOCK_UNLOCKED__);	575	return (val == __ARCH_SPIN_LOCK_UNLOCKED__);
66	}	576	}
67		577
68	static inline void arch_spin_unlock(arch_spinlock_t *lock)	578	static inline void arch_spin_unlock(arch_spinlock_t *lock)
69	{	579	{
70	unsigned int tmp = __ARCH_SPIN_LOCK_UNLOCKED__;	580	unsigned int val = __ARCH_SPIN_LOCK_UNLOCKED__;
71		581
72	/*	582	/*
73	* RELEASE barrier: given the instructions avail on ARCv2, full barrier	583	* RELEASE barrier: given the instructions avail on ARCv2, full barrier
@@ -77,7 +587,7 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock) · 3 unmodified lines
77		587
78	__asm__ __volatile__(	588	__asm__ __volatile__(
79	" ex %0, [%1] \n"	589	" ex %0, [%1] \n"
80	: "+r" (tmp)	590	: "+r" (val)
81	: "r"(&(lock->slock))	591	: "r"(&(lock->slock))
82	: "memory");	592	: "memory");
83		593
@@ -90,19 +600,12 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock) · 6 unmodified lines
90		600
91	/*	601	/*
92	* Read-write spinlocks, allowing multiple readers but only one writer.	602	* Read-write spinlocks, allowing multiple readers but only one writer.
		603	* Unfair locking as Writers could be starved indefinitely by Reader(s)
93	*	604	*
94	* The spinlock itself is contained in @counter and access to it is	605	* The spinlock itself is contained in @counter and access to it is
95	* serialized with @lock_mutex.	606	* serialized with @lock_mutex.
96	*
97	* Unfair locking as Writers could be starved indefinitely by Reader(s)
98	*/	607	*/
99		608
100	/* Would read_trylock() succeed? */
101	#define arch_read_can_lock(x) ((x)->counter > 0)
102
103	/* Would write_trylock() succeed? */
104	#define arch_write_can_lock(x) ((x)->counter == __ARCH_RW_LOCK_UNLOCKED__)
105
106	/* 1 - lock taken successfully */	609	/* 1 - lock taken successfully */
107	static inline int arch_read_trylock(arch_rwlock_t *rw)	610	static inline int arch_read_trylock(arch_rwlock_t *rw)
108	{	611	{
@@ -173,6 +676,11 @@ static inline void arch_write_unlock(arch_rwlock_t *rw) · 64 unmodified lines
173	arch_spin_unlock(&(rw->lock_mutex));	676	arch_spin_unlock(&(rw->lock_mutex));
174	}	677	}
175		678
		679	#endif
		680
		681	#define arch_read_can_lock(x) ((x)->counter > 0)
		682	#define arch_write_can_lock(x) ((x)->counter == __ARCH_RW_LOCK_UNLOCKED__)
		683
176	#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)	684	#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
177	#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)	685	#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
178		686

arch/arc/include/asm/spinlock_types.h+2−0

  */
 typedef struct {
 	volatile unsigned int	counter;
+#ifndef CONFIG_ARC_HAS_LLSC
 	arch_spinlock_t		lock_mutex;
+#endif
 } arch_rwlock_t;
 #define __ARCH_RW_LOCK_UNLOCKED__	0x01000000

arch/arc/include/uapi/asm/ptrace.h+10−10

@@ -32,20 +32,20 @@ · 31 unmodified lines
32	*/	32	*/
33	struct user_regs_struct {	33	struct user_regs_struct {
34		34
35	long pad;	35	unsigned long pad;
36	struct {	36	struct {
37	long bta, lp_start, lp_end, lp_count;	37	unsigned long bta, lp_start, lp_end, lp_count;
38	long status32, ret, blink, fp, gp;	38	unsigned long status32, ret, blink, fp, gp;
39	long r12, r11, r10, r9, r8, r7, r6, r5, r4, r3, r2, r1, r0;	39	unsigned long r12, r11, r10, r9, r8, r7, r6, r5, r4, r3, r2, r1, r0;
40	long sp;	40	unsigned long sp;
41	} scratch;	41	} scratch;
42	long pad2;	42	unsigned long pad2;
43	struct {	43	struct {
44	long r25, r24, r23, r22, r21, r20;	44	unsigned long r25, r24, r23, r22, r21, r20;
45	long r19, r18, r17, r16, r15, r14, r13;	45	unsigned long r19, r18, r17, r16, r15, r14, r13;
46	} callee;	46	} callee;
47	long efa; /* break pt addr, for break points in delay slots */	47	unsigned long efa; /* break pt addr, for break points in delay slots */
48	long stop_pc; /* give dbg stop_pc after ensuring brkpt trap */	48	unsigned long stop_pc; /* give dbg stop_pc after ensuring brkpt trap */
49	};	49	};
50	#endif /* !__ASSEMBLY__ */	50	#endif /* !__ASSEMBLY__ */
51		51

arch/arc/kernel/setup.c+11−1

 	struct bcr_perip uncached_space;
 	struct bcr_generic bcr;
 	struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
+	unsigned long perip_space;
 	FIX_PTR(cpu);
 	READ_BCR(AUX_IDENTITY, cpu->core);
 	cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
 	READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space);
-	BUG_ON((uncached_space.start << 24) != ARC_UNCACHED_ADDR_SPACE);
+        if (uncached_space.ver < 3)
+		perip_space = uncached_space.start << 24;
+	else
+		perip_space = read_aux_reg(AUX_NON_VOL) & 0xF0000000;
+	BUG_ON(perip_space != ARC_UNCACHED_ADDR_SPACE);
 	READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy);
 		pr_warn("CONFIG_ARC_FPU_SAVE_RESTORE needed for working apps\n");
 	else if (!cpu->extn.fpu_dp && fpu_enabled)
 		panic("FPU non-existent, disable CONFIG_ARC_FPU_SAVE_RESTORE\n");
+	if (is_isa_arcv2() && IS_ENABLED(CONFIG_SMP) && cpu->isa.atomic &&
+	    !IS_ENABLED(CONFIG_ARC_STAR_9000923308))
+		panic("llock/scond livelock workaround missing\n");
 }
 /*

arch/arc/kernel/time.c+15−25

@@ -203,34 +203,24 @@ static int arc_clkevent_set_next_event(unsigned long delta, · 202 unmodified lines
203	return 0;	203	return 0;
204	}	204	}
205		205
206	static void arc_clkevent_set_mode(enum clock_event_mode mode,	206	static int arc_clkevent_set_periodic(struct clock_event_device *dev)
207	struct clock_event_device *dev)
208	{	207	{
209	switch (mode) {	208	/*
210	case CLOCK_EVT_MODE_PERIODIC:	209	* At X Hz, 1 sec = 1000ms -> X cycles;
211	/*	210	* 10ms -> X / 100 cycles
212	* At X Hz, 1 sec = 1000ms -> X cycles;	211	*/
213	* 10ms -> X / 100 cycles	212	arc_timer_event_setup(arc_get_core_freq() / HZ);
214	*/	213	return 0;
215	arc_timer_event_setup(arc_get_core_freq() / HZ);
216	break;
217	case CLOCK_EVT_MODE_ONESHOT:
218	break;
219	default:
220	break;
221	}
222
223	return;
224	}	214	}
225		215
226	static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {	216	static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
227	.name = "ARC Timer0",	217	.name = "ARC Timer0",
228	.features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_PERIODIC,	218	.features = CLOCK_EVT_FEAT_ONESHOT \|
229	.mode = CLOCK_EVT_MODE_UNUSED,	219	CLOCK_EVT_FEAT_PERIODIC,
230	.rating = 300,	220	.rating = 300,
231	.irq = TIMER0_IRQ, /* hardwired, no need for resources */	221	.irq = TIMER0_IRQ, /* hardwired, no need for resources */
232	.set_next_event = arc_clkevent_set_next_event,	222	.set_next_event = arc_clkevent_set_next_event,
233	.set_mode = arc_clkevent_set_mode,	223	.set_state_periodic = arc_clkevent_set_periodic,
234	};	224	};
235		225
236	static irqreturn_t timer_irq_handler(int irq, void *dev_id)	226	static irqreturn_t timer_irq_handler(int irq, void *dev_id)
@@ -240,7 +230,7 @@ static irqreturn_t timer_irq_handler(int irq, void *dev_id) · 3 unmodified lines
240	* irq_set_chip_and_handler() asked for handle_percpu_devid_irq()	230	* irq_set_chip_and_handler() asked for handle_percpu_devid_irq()
241	*/	231	*/
242	struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);	232	struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
243	int irq_reenable = evt->mode == CLOCK_EVT_MODE_PERIODIC;	233	int irq_reenable = clockevent_state_periodic(evt);
244		234
245	/*	235	/*
246	* Any write to CTRL reg ACks the interrupt, we rewrite the	236	* Any write to CTRL reg ACks the interrupt, we rewrite the

arch/arc/lib/memcpy-archs.S+1−1

@@ -206,7 +206,7 @@ unalignedOffby3: · 205 unmodified lines
206	ld.ab r6, [r1, 4]	206	ld.ab r6, [r1, 4]
207	prefetch [r1, 28] ;Prefetch the next read location	207	prefetch [r1, 28] ;Prefetch the next read location
208	ld.ab r8, [r1,4]	208	ld.ab r8, [r1,4]
209	prefetch [r3, 32] ;Prefetch the next write location	209	prefetchw [r3, 32] ;Prefetch the next write location
210		210
211	SHIFT_1 (r7, r6, 8)	211	SHIFT_1 (r7, r6, 8)
212	or r7, r7, r5	212	or r7, r7, r5

arch/arc/lib/memset-archs.S+36−7

 #undef PREALLOC_NOT_AVAIL
-#ifdef PREALLOC_NOT_AVAIL
-#define PREWRITE(A,B)	prefetchw [(A),(B)]
-#else
-#define PREWRITE(A,B)	prealloc [(A),(B)]
-#endif
 ENTRY(memset)
 	prefetchw [r0]		; Prefetch the write location
 	mov.f	0, r2
 ;;; Convert len to Dwords, unfold x8
 	lsr.f	lp_count, lp_count, 6
 	lpnz	@.Lset64bytes
 	;; LOOP START
-	PREWRITE(r3, 64)	;Prefetch the next write location
+#ifdef PREALLOC_NOT_AVAIL
+	prefetchw [r3, 64]	;Prefetch the next write location
+#else
+	prealloc  [r3, 64]
+#endif
+#ifdef CONFIG_ARC_HAS_LL64
 	std.ab	r4, [r3, 8]
 	std.ab	r4, [r3, 8]
 	std.ab	r4, [r3, 8]
 	std.ab	r4, [r3, 8]
 	std.ab	r4, [r3, 8]
 	std.ab	r4, [r3, 8]
+#else
+	st.ab	r4, [r3, 4]
+	st.ab	r4, [r3, 4]
+	st.ab	r4, [r3, 4]
+	st.ab	r4, [r3, 4]
+	st.ab	r4, [r3, 4]
+	st.ab	r4, [r3, 4]
+	st.ab	r4, [r3, 4]
+	st.ab	r4, [r3, 4]
+	st.ab	r4, [r3, 4]
+	st.ab	r4, [r3, 4]
+	st.ab	r4, [r3, 4]
+	st.ab	r4, [r3, 4]
+	st.ab	r4, [r3, 4]
+	st.ab	r4, [r3, 4]
+	st.ab	r4, [r3, 4]
+	st.ab	r4, [r3, 4]
+#endif
 .Lset64bytes:
 	lsr.f	lp_count, r2, 5 ;Last remaining  max 124 bytes
 	lpnz	.Lset32bytes
 	;; LOOP START
 	prefetchw   [r3, 32]	;Prefetch the next write location
+#ifdef CONFIG_ARC_HAS_LL64
 	std.ab	r4, [r3, 8]
 	std.ab	r4, [r3, 8]
 	std.ab	r4, [r3, 8]
 	std.ab	r4, [r3, 8]
+#else
+	st.ab	r4, [r3, 4]
+	st.ab	r4, [r3, 4]
+	st.ab	r4, [r3, 4]
+	st.ab	r4, [r3, 4]
+	st.ab	r4, [r3, 4]
+	st.ab	r4, [r3, 4]
+	st.ab	r4, [r3, 4]
+	st.ab	r4, [r3, 4]
+#endif
 .Lset32bytes:
 	and.f	lp_count, r2, 0x1F ;Last remaining 31 bytes

arch/arc/plat-axs10x/axs10x.c+15−0

@@ -389,6 +389,21 @@ axs103_set_freq(unsigned int id, unsigned int fd, unsigned int od) · 388 unmodified lines
389		389
390	static void __init axs103_early_init(void)	390	static void __init axs103_early_init(void)
391	{	391	{
		392	/*
		393	* AXS103 configurations for SMP/QUAD configurations share device tree
		394	* which defaults to 90 MHz. However recent failures of Quad config
		395	* revealed P&R timing violations so clamp it down to safe 50 MHz
		396	* Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack
		397	*
		398	* This hack is really hacky as of now. Fix it properly by getting the
		399	* number of cores as return value of platform's early SMP callback
		400	*/
		401	#ifdef CONFIG_ARC_MCIP
		402	unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
		403	if (num_cores > 2)
		404	arc_set_core_freq(50 * 1000000);
		405	#endif
		406
392	switch (arc_get_core_freq()/1000000) {	407	switch (arc_get_core_freq()/1000000) {
393	case 33:	408	case 33:
394	axs103_set_freq(1, 1, 1);	409	axs103_set_freq(1, 1, 1);

arch/arm/boot/dts/dra7.dtsi+2−1

 				ranges = <0 0x2000 0x2000>;
 				scm_conf: scm_conf@0 {
-					compatible = "syscon";
+					compatible = "syscon", "simple-bus";
 					reg = <0x0 0x1400>;
 					#address-cells = <1>;
 					#size-cells = <1>;
 				ctrl-module = <&omap_control_sata>;
 				clocks = <&sys_clkin1>, <&sata_ref_clk>;
 				clock-names = "sysclk", "refclk";
+				syscon-pllreset = <&scm_conf 0x3fc>;
 				#phy-cells = <0>;
 			};

arch/arm/boot/dts/exynos3250.dtsi+1−1

@@ -138,8 +138,8 @@ · 137 unmodified lines
138		138
139	mipi_phy: video-phy@10020710 {	139	mipi_phy: video-phy@10020710 {
140	compatible = "samsung,s5pv210-mipi-video-phy";	140	compatible = "samsung,s5pv210-mipi-video-phy";
141	reg = <0x10020710 8>;
142	#phy-cells = <1>;	141	#phy-cells = <1>;
		142	syscon = <&pmu_system_controller>;
143	};	143	};
144		144
145	pd_cam: cam-power-domain@10023C00 {	145	pd_cam: cam-power-domain@10023C00 {

arch/arm/boot/dts/exynos4210-origen.dts+4−0

 	};
 };
+&cpu0 {
+	cpu0-supply = <&buck1_reg>;
+};
 &fimd {
 	pinctrl-0 = <&lcd_en &lcd_clk &lcd_data24 &pwm0_out>;
 	pinctrl-names = "default";

arch/arm/boot/dts/exynos4210-trats.dts+4−0

 	};
 };
+&cpu0 {
+	cpu0-supply = <&varm_breg>;
+};
 &dsi_0 {
 	vddcore-supply = <&vusb_reg>;
 	vddio-supply = <&vmipi_reg>;

arch/arm/boot/dts/exynos4210-universal_c210.dts+4−0

 	};
 };
+&cpu0 {
+	cpu0-supply = <&vdd_arm_reg>;
+};
 &pinctrl_1 {
 	hdmi_hpd: hdmi-hpd {
 		samsung,pins = "gpx3-7";

arch/arm/boot/dts/exynos4210.dtsi+12−0

@@ -40,6 +40,18 @@ · 39 unmodified lines
40	device_type = "cpu";	40	device_type = "cpu";
41	compatible = "arm,cortex-a9";	41	compatible = "arm,cortex-a9";
42	reg = <0x900>;	42	reg = <0x900>;
		43	clocks = <&clock CLK_ARM_CLK>;
		44	clock-names = "cpu";
		45	clock-latency = <160000>;
		46
		47	operating-points = <
		48	1200000 1250000
		49	1000000 1150000
		50	800000 1075000
		51	500000 975000
		52	400000 975000
		53	200000 950000
		54	>;
43	cooling-min-level = <4>;	55	cooling-min-level = <4>;
44	cooling-max-level = <2>;	56	cooling-max-level = <2>;
45	#cooling-cells = <2>; /* min followed by max */	57	#cooling-cells = <2>; /* min followed by max */

arch/arm/boot/dts/imx25-pdk.dts+3−2

  */
 /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include "imx25.dtsi"
 &esdhc1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_esdhc1>;
-	cd-gpios = <&gpio2 1 0>;
+	cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
-	wp-gpios = <&gpio2 0 0>;
+	wp-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };

arch/arm/boot/dts/imx35.dtsi+4−4

@@ -286,8 +286,8 @@ · 285 unmodified lines
286	can1: can@53fe4000 {	286	can1: can@53fe4000 {
287	compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";	287	compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";
288	reg = <0x53fe4000 0x1000>;	288	reg = <0x53fe4000 0x1000>;
289	clocks = <&clks 33>;	289	clocks = <&clks 33>, <&clks 33>;
290	clock-names = "ipg";	290	clock-names = "ipg", "per";
291	interrupts = <43>;	291	interrupts = <43>;
292	status = "disabled";	292	status = "disabled";
293	};	293	};
@@ -295,8 +295,8 @@ · 1 unmodified line
295	can2: can@53fe8000 {	295	can2: can@53fe8000 {
296	compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";	296	compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";
297	reg = <0x53fe8000 0x1000>;	297	reg = <0x53fe8000 0x1000>;
298	clocks = <&clks 34>;	298	clocks = <&clks 34>, <&clks 34>;
299	clock-names = "ipg";	299	clock-names = "ipg", "per";
300	interrupts = <44>;	300	interrupts = <44>;
301	status = "disabled";	301	status = "disabled";
302	};	302	};

arch/arm/boot/dts/imx51-apf51dev.dts+1−1

@@ -98,7 +98,7 @@ · 97 unmodified lines
98	&esdhc1 {	98	&esdhc1 {
99	pinctrl-names = "default";	99	pinctrl-names = "default";
100	pinctrl-0 = <&pinctrl_esdhc1>;	100	pinctrl-0 = <&pinctrl_esdhc1>;
101	cd-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;	101	cd-gpios = <&gpio2 29 GPIO_ACTIVE_LOW>;
102	bus-width = <4>;	102	bus-width = <4>;
103	status = "okay";	103	status = "okay";
104	};	104	};

arch/arm/boot/dts/imx53-ard.dts+2−2

@@ -103,8 +103,8 @@ · 102 unmodified lines
103	&esdhc1 {	103	&esdhc1 {
104	pinctrl-names = "default";	104	pinctrl-names = "default";
105	pinctrl-0 = <&pinctrl_esdhc1>;	105	pinctrl-0 = <&pinctrl_esdhc1>;
106	cd-gpios = <&gpio1 1 0>;	106	cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
107	wp-gpios = <&gpio1 9 0>;	107	wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
108	status = "okay";	108	status = "okay";
109	};	109	};
110		110

arch/arm/boot/dts/imx53-m53evk.dts+2−2

@@ -124,8 +124,8 @@ · 123 unmodified lines
124	&esdhc1 {	124	&esdhc1 {
125	pinctrl-names = "default";	125	pinctrl-names = "default";
126	pinctrl-0 = <&pinctrl_esdhc1>;	126	pinctrl-0 = <&pinctrl_esdhc1>;
127	cd-gpios = <&gpio1 1 0>;	127	cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
128	wp-gpios = <&gpio1 9 0>;	128	wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
129	status = "okay";	129	status = "okay";
130	};	130	};
131		131

arch/arm/boot/dts/imx53-qsb-common.dtsi+2−2

@@ -147,8 +147,8 @@ · 146 unmodified lines
147	&esdhc3 {	147	&esdhc3 {
148	pinctrl-names = "default";	148	pinctrl-names = "default";
149	pinctrl-0 = <&pinctrl_esdhc3>;	149	pinctrl-0 = <&pinctrl_esdhc3>;
150	cd-gpios = <&gpio3 11 0>;	150	cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
151	wp-gpios = <&gpio3 12 0>;	151	wp-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
152	bus-width = <8>;	152	bus-width = <8>;
153	status = "okay";	153	status = "okay";
154	};	154	};

arch/arm/boot/dts/imx53-smd.dts+2−2

@@ -41,8 +41,8 @@ · 40 unmodified lines
41	&esdhc1 {	41	&esdhc1 {
42	pinctrl-names = "default";	42	pinctrl-names = "default";
43	pinctrl-0 = <&pinctrl_esdhc1>;	43	pinctrl-0 = <&pinctrl_esdhc1>;
44	cd-gpios = <&gpio3 13 0>;	44	cd-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
45	wp-gpios = <&gpio4 11 0>;	45	wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
46	status = "okay";	46	status = "okay";
47	};	47	};
48		48

arch/arm/boot/dts/imx53-tqma53.dtsi+2−2

@@ -41,8 +41,8 @@ · 40 unmodified lines
41	pinctrl-0 = <&pinctrl_esdhc2>,	41	pinctrl-0 = <&pinctrl_esdhc2>,
42	<&pinctrl_esdhc2_cdwp>;	42	<&pinctrl_esdhc2_cdwp>;
43	vmmc-supply = <&reg_3p3v>;	43	vmmc-supply = <&reg_3p3v>;
44	wp-gpios = <&gpio1 2 0>;	44	wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
45	cd-gpios = <&gpio1 4 0>;	45	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
46	status = "disabled";	46	status = "disabled";
47	};	47	};
48		48

arch/arm/boot/dts/imx53-tx53.dtsi+2−2

@@ -183,7 +183,7 @@ · 182 unmodified lines
183	};	183	};
184		184
185	&esdhc1 {	185	&esdhc1 {
186	cd-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;	186	cd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
187	fsl,wp-controller;	187	fsl,wp-controller;
188	pinctrl-names = "default";	188	pinctrl-names = "default";
189	pinctrl-0 = <&pinctrl_esdhc1>;	189	pinctrl-0 = <&pinctrl_esdhc1>;
@@ -191,7 +191,7 @@ · 1 unmodified line
191	};	191	};
192		192
193	&esdhc2 {	193	&esdhc2 {
194	cd-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>;	194	cd-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
195	fsl,wp-controller;	195	fsl,wp-controller;
196	pinctrl-names = "default";	196	pinctrl-names = "default";
197	pinctrl-0 = <&pinctrl_esdhc2>;	197	pinctrl-0 = <&pinctrl_esdhc2>;

arch/arm/boot/dts/imx53-voipac-bsb.dts+2−2

@@ -119,8 +119,8 @@ · 118 unmodified lines
119	&esdhc2 {	119	&esdhc2 {
120	pinctrl-names = "default";	120	pinctrl-names = "default";
121	pinctrl-0 = <&pinctrl_esdhc2>;	121	pinctrl-0 = <&pinctrl_esdhc2>;
122	cd-gpios = <&gpio3 25 0>;	122	cd-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
123	wp-gpios = <&gpio2 19 0>;	123	wp-gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
124	vmmc-supply = <&reg_3p3v>;	124	vmmc-supply = <&reg_3p3v>;
125	status = "okay";	125	status = "okay";
126	};	126	};

arch/arm/boot/dts/imx6dl-riotboard.dts+4−4

@@ -305,8 +305,8 @@ · 304 unmodified lines
305	&usdhc2 {	305	&usdhc2 {
306	pinctrl-names = "default";	306	pinctrl-names = "default";
307	pinctrl-0 = <&pinctrl_usdhc2>;	307	pinctrl-0 = <&pinctrl_usdhc2>;
308	cd-gpios = <&gpio1 4 0>;	308	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
309	wp-gpios = <&gpio1 2 0>;	309	wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
310	vmmc-supply = <&reg_3p3v>;	310	vmmc-supply = <&reg_3p3v>;
311	status = "okay";	311	status = "okay";
312	};	312	};
@@ -314,8 +314,8 @@ · 1 unmodified line
314	&usdhc3 {	314	&usdhc3 {
315	pinctrl-names = "default";	315	pinctrl-names = "default";
316	pinctrl-0 = <&pinctrl_usdhc3>;	316	pinctrl-0 = <&pinctrl_usdhc3>;
317	cd-gpios = <&gpio7 0 0>;	317	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
318	wp-gpios = <&gpio7 1 0>;	318	wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
319	vmmc-supply = <&reg_3p3v>;	319	vmmc-supply = <&reg_3p3v>;
320	status = "okay";	320	status = "okay";
321	};	321	};

arch/arm/boot/dts/imx6q-arm2.dts+3−2

  */
 /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
 #include "imx6q.dtsi"
 / {
 };
 &usdhc3 {
-	cd-gpios = <&gpio6 11 0>;
+	cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
-	wp-gpios = <&gpio6 14 0>;
+	wp-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>;
 	vmmc-supply = <&reg_3p3v>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc3

arch/arm/boot/dts/imx6q-gk802.dts+2−1

  */
 /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
 #include "imx6q.dtsi"
 / {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc3>;
 	bus-width = <4>;
-	cd-gpios = <&gpio6 11 0>;
+	cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
 	vmmc-supply = <&reg_3p3v>;
 	status = "okay";
 };

arch/arm/boot/dts/imx6q-tbs2910.dts+2−2

@@ -251,7 +251,7 @@ · 250 unmodified lines
251	pinctrl-names = "default";	251	pinctrl-names = "default";
252	pinctrl-0 = <&pinctrl_usdhc2>;	252	pinctrl-0 = <&pinctrl_usdhc2>;
253	bus-width = <4>;	253	bus-width = <4>;
254	cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;	254	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
255	vmmc-supply = <&reg_3p3v>;	255	vmmc-supply = <&reg_3p3v>;
256	status = "okay";	256	status = "okay";
257	};	257	};
@@ -260,7 +260,7 @@ · 2 unmodified lines
260	pinctrl-names = "default";	260	pinctrl-names = "default";
261	pinctrl-0 = <&pinctrl_usdhc3>;	261	pinctrl-0 = <&pinctrl_usdhc3>;
262	bus-width = <4>;	262	bus-width = <4>;
263	cd-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;	263	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
264	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;	264	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
265	vmmc-supply = <&reg_3p3v>;	265	vmmc-supply = <&reg_3p3v>;
266	status = "okay";	266	status = "okay";

arch/arm/boot/dts/imx6qdl-aristainetos.dtsi+2−2

@@ -173,7 +173,7 @@ · 172 unmodified lines
173	pinctrl-names = "default";	173	pinctrl-names = "default";
174	pinctrl-0 = <&pinctrl_usdhc1>;	174	pinctrl-0 = <&pinctrl_usdhc1>;
175	vmmc-supply = <&reg_3p3v>;	175	vmmc-supply = <&reg_3p3v>;
176	cd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>;	176	cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
177	status = "okay";	177	status = "okay";
178	};	178	};
179		179
@@ -181,7 +181,7 @@ · 1 unmodified line
181	pinctrl-names = "default";	181	pinctrl-names = "default";
182	pinctrl-0 = <&pinctrl_usdhc2>;	182	pinctrl-0 = <&pinctrl_usdhc2>;
183	vmmc-supply = <&reg_3p3v>;	183	vmmc-supply = <&reg_3p3v>;
184	cd-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;	184	cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
185	status = "okay";	185	status = "okay";
186	};	186	};
187		187

arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi+2−2

@@ -392,7 +392,7 @@ · 391 unmodified lines
392	&usdhc1 {	392	&usdhc1 {
393	pinctrl-names = "default";	393	pinctrl-names = "default";
394	pinctrl-0 = <&pinctrl_usdhc1>;	394	pinctrl-0 = <&pinctrl_usdhc1>;
395	cd-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;	395	cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
396	no-1-8-v;	396	no-1-8-v;
397	status = "okay";	397	status = "okay";
398	};	398	};
@@ -400,7 +400,7 @@ · 1 unmodified line
400	&usdhc2 {	400	&usdhc2 {
401	pinctrl-names = "default";	401	pinctrl-names = "default";
402	pinctrl-0 = <&pinctrl_usdhc2>;	402	pinctrl-0 = <&pinctrl_usdhc2>;
403	cd-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;	403	cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
404	wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;	404	wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
405	no-1-8-v;	405	no-1-8-v;
406	status = "okay";	406	status = "okay";

arch/arm/boot/dts/imx6qdl-cubox-i.dtsi+1−1

@@ -258,6 +258,6 @@ · 257 unmodified lines
258	pinctrl-names = "default";	258	pinctrl-names = "default";
259	pinctrl-0 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2>;	259	pinctrl-0 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2>;
260	vmmc-supply = <&reg_3p3v>;	260	vmmc-supply = <&reg_3p3v>;
261	cd-gpios = <&gpio1 4 0>;	261	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
262	status = "okay";	262	status = "okay";
263	};	263	};

arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi+3−1

+#include <dt-bindings/gpio/gpio.h>
 / {
 	regulators {
 		compatible = "simple-bus";
 &usdhc2 { /* module slot */
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc2>;
-	cd-gpios = <&gpio2 2 0>;
+	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };

arch/arm/boot/dts/imx6qdl-gw52xx.dtsi+1−1

@@ -318,7 +318,7 @@ · 317 unmodified lines
318	&usdhc3 {	318	&usdhc3 {
319	pinctrl-names = "default";	319	pinctrl-names = "default";
320	pinctrl-0 = <&pinctrl_usdhc3>;	320	pinctrl-0 = <&pinctrl_usdhc3>;
321	cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;	321	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
322	vmmc-supply = <&reg_3p3v>;	322	vmmc-supply = <&reg_3p3v>;
323	status = "okay";	323	status = "okay";
324	};	324	};

arch/arm/boot/dts/imx6qdl-gw53xx.dtsi+1−1

@@ -324,7 +324,7 @@ · 323 unmodified lines
324	&usdhc3 {	324	&usdhc3 {
325	pinctrl-names = "default";	325	pinctrl-names = "default";
326	pinctrl-0 = <&pinctrl_usdhc3>;	326	pinctrl-0 = <&pinctrl_usdhc3>;
327	cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;	327	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
328	vmmc-supply = <&reg_3p3v>;	328	vmmc-supply = <&reg_3p3v>;
329	status = "okay";	329	status = "okay";
330	};	330	};

arch/arm/boot/dts/imx6qdl-gw54xx.dtsi+1−1

@@ -417,7 +417,7 @@ · 416 unmodified lines
417	&usdhc3 {	417	&usdhc3 {
418	pinctrl-names = "default";	418	pinctrl-names = "default";
419	pinctrl-0 = <&pinctrl_usdhc3>;	419	pinctrl-0 = <&pinctrl_usdhc3>;
420	cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;	420	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
421	vmmc-supply = <&reg_3p3v>;	421	vmmc-supply = <&reg_3p3v>;
422	status = "okay";	422	status = "okay";
423	};	423	};

arch/arm/boot/dts/imx6qdl-hummingboard.dtsi+1−1

@@ -299,6 +299,6 @@ · 298 unmodified lines
299	&pinctrl_hummingboard_usdhc2	299	&pinctrl_hummingboard_usdhc2
300	>;	300	>;
301	vmmc-supply = <&reg_3p3v>;	301	vmmc-supply = <&reg_3p3v>;
302	cd-gpios = <&gpio1 4 0>;	302	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
303	status = "okay";	303	status = "okay";
304	};	304	};

arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi+2−2

@@ -453,7 +453,7 @@ · 452 unmodified lines
453	&usdhc3 {	453	&usdhc3 {
454	pinctrl-names = "default";	454	pinctrl-names = "default";
455	pinctrl-0 = <&pinctrl_usdhc3>;	455	pinctrl-0 = <&pinctrl_usdhc3>;
456	cd-gpios = <&gpio7 0 0>;	456	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
457	vmmc-supply = <&reg_3p3v>;	457	vmmc-supply = <&reg_3p3v>;
458	status = "okay";	458	status = "okay";
459	};	459	};
@@ -461,7 +461,7 @@ · 1 unmodified line
461	&usdhc4 {	461	&usdhc4 {
462	pinctrl-names = "default";	462	pinctrl-names = "default";
463	pinctrl-0 = <&pinctrl_usdhc4>;	463	pinctrl-0 = <&pinctrl_usdhc4>;
464	cd-gpios = <&gpio2 6 0>;	464	cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
465	vmmc-supply = <&reg_3p3v>;	465	vmmc-supply = <&reg_3p3v>;
466	status = "okay";	466	status = "okay";
467	};	467	};

arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi+4−4

@@ -409,8 +409,8 @@ · 408 unmodified lines
409	&usdhc2 {	409	&usdhc2 {
410	pinctrl-names = "default";	410	pinctrl-names = "default";
411	pinctrl-0 = <&pinctrl_usdhc2>;	411	pinctrl-0 = <&pinctrl_usdhc2>;
412	cd-gpios = <&gpio1 4 0>;	412	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
413	wp-gpios = <&gpio1 2 0>;	413	wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
414	status = "disabled";	414	status = "disabled";
415	};	415	};
416		416
@@ -418,7 +418,7 @@ · 1 unmodified line
418	pinctrl-names = "default";	418	pinctrl-names = "default";
419	pinctrl-0 = <&pinctrl_usdhc3	419	pinctrl-0 = <&pinctrl_usdhc3
420	&pinctrl_usdhc3_cdwp>;	420	&pinctrl_usdhc3_cdwp>;
421	cd-gpios = <&gpio1 27 0>;	421	cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
422	wp-gpios = <&gpio1 29 0>;	422	wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
423	status = "disabled";	423	status = "disabled";
424	};	424	};

arch/arm/boot/dts/imx6qdl-rex.dtsi+2−2

@@ -342,7 +342,7 @@ · 341 unmodified lines
342	pinctrl-0 = <&pinctrl_usdhc2>;	342	pinctrl-0 = <&pinctrl_usdhc2>;
343	bus-width = <4>;	343	bus-width = <4>;
344	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;	344	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
345	wp-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;	345	wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
346	status = "okay";	346	status = "okay";
347	};	347	};
348		348
@@ -351,6 +351,6 @@ · 2 unmodified lines
351	pinctrl-0 = <&pinctrl_usdhc3>;	351	pinctrl-0 = <&pinctrl_usdhc3>;
352	bus-width = <4>;	352	bus-width = <4>;
353	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;	353	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
354	wp-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;	354	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
355	status = "okay";	355	status = "okay";
356	};	356	};

arch/arm/boot/dts/imx6qdl-sabreauto.dtsi+2−2

@@ -467,8 +467,8 @@ · 466 unmodified lines
467	pinctrl-0 = <&pinctrl_usdhc3>;	467	pinctrl-0 = <&pinctrl_usdhc3>;
468	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;	468	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
469	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;	469	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
470	cd-gpios = <&gpio6 15 0>;	470	cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
471	wp-gpios = <&gpio1 13 0>;	471	wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
472	status = "okay";	472	status = "okay";
473	};	473	};
474		474

arch/arm/boot/dts/imx6qdl-sabrelite.dtsi+3−3

@@ -448,8 +448,8 @@ · 447 unmodified lines
448	&usdhc3 {	448	&usdhc3 {
449	pinctrl-names = "default";	449	pinctrl-names = "default";
450	pinctrl-0 = <&pinctrl_usdhc3>;	450	pinctrl-0 = <&pinctrl_usdhc3>;
451	cd-gpios = <&gpio7 0 0>;	451	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
452	wp-gpios = <&gpio7 1 0>;	452	wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
453	vmmc-supply = <&reg_3p3v>;	453	vmmc-supply = <&reg_3p3v>;
454	status = "okay";	454	status = "okay";
455	};	455	};
@@ -457,7 +457,7 @@ · 1 unmodified line
457	&usdhc4 {	457	&usdhc4 {
458	pinctrl-names = "default";	458	pinctrl-names = "default";
459	pinctrl-0 = <&pinctrl_usdhc4>;	459	pinctrl-0 = <&pinctrl_usdhc4>;
460	cd-gpios = <&gpio2 6 0>;	460	cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
461	vmmc-supply = <&reg_3p3v>;	461	vmmc-supply = <&reg_3p3v>;
462	status = "okay";	462	status = "okay";
463	};	463	};

arch/arm/boot/dts/imx6qdl-sabresd.dtsi+4−4

@@ -562,8 +562,8 @@ · 561 unmodified lines
562	pinctrl-names = "default";	562	pinctrl-names = "default";
563	pinctrl-0 = <&pinctrl_usdhc2>;	563	pinctrl-0 = <&pinctrl_usdhc2>;
564	bus-width = <8>;	564	bus-width = <8>;
565	cd-gpios = <&gpio2 2 0>;	565	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
566	wp-gpios = <&gpio2 3 0>;	566	wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
567	status = "okay";	567	status = "okay";
568	};	568	};
569		569
@@ -571,8 +571,8 @@ · 1 unmodified line
571	pinctrl-names = "default";	571	pinctrl-names = "default";
572	pinctrl-0 = <&pinctrl_usdhc3>;	572	pinctrl-0 = <&pinctrl_usdhc3>;
573	bus-width = <8>;	573	bus-width = <8>;
574	cd-gpios = <&gpio2 0 0>;	574	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
575	wp-gpios = <&gpio2 1 0>;	575	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
576	status = "okay";	576	status = "okay";
577	};	577	};
578		578

arch/arm/boot/dts/imx6qdl-tx6.dtsi+2−2

@@ -680,7 +680,7 @@ · 679 unmodified lines
680	pinctrl-0 = <&pinctrl_usdhc1>;	680	pinctrl-0 = <&pinctrl_usdhc1>;
681	bus-width = <4>;	681	bus-width = <4>;
682	no-1-8-v;	682	no-1-8-v;
683	cd-gpios = <&gpio7 2 0>;	683	cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
684	fsl,wp-controller;	684	fsl,wp-controller;
685	status = "okay";	685	status = "okay";
686	};	686	};
@@ -690,7 +690,7 @@ · 3 unmodified lines
690	pinctrl-0 = <&pinctrl_usdhc2>;	690	pinctrl-0 = <&pinctrl_usdhc2>;
691	bus-width = <4>;	691	bus-width = <4>;
692	no-1-8-v;	692	no-1-8-v;
693	cd-gpios = <&gpio7 3 0>;	693	cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
694	fsl,wp-controller;	694	fsl,wp-controller;
695	status = "okay";	695	status = "okay";
696	};	696	};

arch/arm/boot/dts/imx6qdl-wandboard.dtsi+4−2

  *
  */
+#include <dt-bindings/gpio/gpio.h>
 / {
 	regulators {
 		compatible = "simple-bus";
 &usdhc1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc1>;
-	cd-gpios = <&gpio1 2 0>;
+	cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 &usdhc3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc3>;
-	cd-gpios = <&gpio3 9 0>;
+	cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };

arch/arm/boot/dts/imx6qdl.dtsi+4−4

@@ -181,10 +181,10 @@ · 180 unmodified lines
181	interrupt-names = "msi";	181	interrupt-names = "msi";
182	#interrupt-cells = <1>;	182	#interrupt-cells = <1>;
183	interrupt-map-mask = <0 0 0 0x7>;	183	interrupt-map-mask = <0 0 0 0x7>;
184	interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,	184	interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
185	<0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,	185	<0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
186	<0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,	186	<0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
187	<0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	187	<0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
188	clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,	188	clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
189	<&clks IMX6QDL_CLK_LVDS1_GATE>,	189	<&clks IMX6QDL_CLK_LVDS1_GATE>,
190	<&clks IMX6QDL_CLK_PCIE_REF_125M>;	190	<&clks IMX6QDL_CLK_PCIE_REF_125M>;

arch/arm/boot/dts/imx6sl-evk.dts+5−5

@@ -617,8 +617,8 @@ · 616 unmodified lines
617	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;	617	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
618	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;	618	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
619	bus-width = <8>;	619	bus-width = <8>;
620	cd-gpios = <&gpio4 7 0>;	620	cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
621	wp-gpios = <&gpio4 6 0>;	621	wp-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
622	status = "okay";	622	status = "okay";
623	};	623	};
624		624
@@ -627,8 +627,8 @@ · 2 unmodified lines
627	pinctrl-0 = <&pinctrl_usdhc2>;	627	pinctrl-0 = <&pinctrl_usdhc2>;
628	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;	628	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
629	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;	629	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
630	cd-gpios = <&gpio5 0 0>;	630	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
631	wp-gpios = <&gpio4 29 0>;	631	wp-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
632	status = "okay";	632	status = "okay";
633	};	633	};
634		634
@@ -637,6 +637,6 @@ · 2 unmodified lines
637	pinctrl-0 = <&pinctrl_usdhc3>;	637	pinctrl-0 = <&pinctrl_usdhc3>;
638	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;	638	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
639	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;	639	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
640	cd-gpios = <&gpio3 22 0>;	640	cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
641	status = "okay";	641	status = "okay";
642	};	642	};

arch/arm/boot/dts/imx6sx-sabreauto.dts+2−2

@@ -49,7 +49,7 @@ · 48 unmodified lines
49	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;	49	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
50	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;	50	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
51	bus-width = <8>;	51	bus-width = <8>;
52	cd-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>;	52	cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
53	wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;	53	wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
54	keep-power-in-suspend;	54	keep-power-in-suspend;
55	enable-sdio-wakeup;	55	enable-sdio-wakeup;
@@ -61,7 +61,7 @@ · 5 unmodified lines
61	pinctrl-names = "default";	61	pinctrl-names = "default";
62	pinctrl-0 = <&pinctrl_usdhc4>;	62	pinctrl-0 = <&pinctrl_usdhc4>;
63	bus-width = <8>;	63	bus-width = <8>;
64	cd-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;	64	cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
65	no-1-8-v;	65	no-1-8-v;
66	keep-power-in-suspend;	66	keep-power-in-suspend;
67	enable-sdio-wakup;	67	enable-sdio-wakup;

arch/arm/boot/dts/imx6sx-sdb.dtsi+2−2

@@ -293,7 +293,7 @@ · 292 unmodified lines
293	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;	293	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
294	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;	294	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
295	bus-width = <8>;	295	bus-width = <8>;
296	cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;	296	cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
297	wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;	297	wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
298	keep-power-in-suspend;	298	keep-power-in-suspend;
299	enable-sdio-wakeup;	299	enable-sdio-wakeup;
@@ -304,7 +304,7 @@ · 4 unmodified lines
304	&usdhc4 {	304	&usdhc4 {
305	pinctrl-names = "default";	305	pinctrl-names = "default";
306	pinctrl-0 = <&pinctrl_usdhc4>;	306	pinctrl-0 = <&pinctrl_usdhc4>;
307	cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;	307	cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>;
308	wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;	308	wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
309	status = "okay";	309	status = "okay";
310	};	310	};

arch/arm/boot/dts/imx7d-sdb.dts+2−2

@@ -234,8 +234,8 @@ · 233 unmodified lines
234	&usdhc1 {	234	&usdhc1 {
235	pinctrl-names = "default";	235	pinctrl-names = "default";
236	pinctrl-0 = <&pinctrl_usdhc1>;	236	pinctrl-0 = <&pinctrl_usdhc1>;
237	cd-gpios = <&gpio5 0 0>;	237	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
238	wp-gpios = <&gpio5 1 0>;	238	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
239	enable-sdio-wakeup;	239	enable-sdio-wakeup;
240	keep-power-in-suspend;	240	keep-power-in-suspend;
241	status = "okay";	241	status = "okay";

arch/arm/boot/dts/k2e-clocks.dtsi+2−3

 		#clock-cells = <0>;
 		compatible = "ti,keystone,main-pll-clock";
 		clocks = <&refclksys>;
-		reg = <0x02620350 4>, <0x02310110 4>;
+		reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
-		reg-names = "control", "multiplier";
+		reg-names = "control", "multiplier", "post-divider";
-		fixed-postdiv = <2>;
 	};
 	papllclk: papllclk@2620358 {

arch/arm/boot/dts/k2e.dtsi+11−4

@@ -131,10 +131,17 @@ · 130 unmodified lines
131	<GIC_SPI 376 IRQ_TYPE_EDGE_RISING>;	131	<GIC_SPI 376 IRQ_TYPE_EDGE_RISING>;
132	};	132	};
133	};	133	};
		134
		135	mdio: mdio@24200f00 {
		136	compatible = "ti,keystone_mdio", "ti,davinci_mdio";
		137	#address-cells = <1>;
		138	#size-cells = <0>;
		139	reg = <0x24200f00 0x100>;
		140	status = "disabled";
		141	clocks = <&clkcpgmac>;
		142	clock-names = "fck";
		143	bus_freq = <2500000>;
		144	};
134	/include/ "k2e-netcp.dtsi"	145	/include/ "k2e-netcp.dtsi"
135	};	146	};
136	};	147	};
137
138	&mdio {
139	reg = <0x24200f00 0x100>;
140	};

arch/arm/boot/dts/k2hk-clocks.dtsi+2−3

 		#clock-cells = <0>;
 		compatible = "ti,keystone,main-pll-clock";
 		clocks = <&refclksys>;
-		reg = <0x02620350 4>, <0x02310110 4>;
+		reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
-		reg-names = "control", "multiplier";
+		reg-names = "control", "multiplier", "post-divider";
-		fixed-postdiv = <2>;
 	};
 	papllclk: papllclk@2620358 {

arch/arm/boot/dts/k2hk.dtsi+11−0

@@ -98,6 +98,17 @@ · 97 unmodified lines
98	#gpio-cells = <2>;	98	#gpio-cells = <2>;
99	gpio,syscon-dev = <&devctrl 0x25c>;	99	gpio,syscon-dev = <&devctrl 0x25c>;
100	};	100	};
		101
		102	mdio: mdio@02090300 {
		103	compatible = "ti,keystone_mdio", "ti,davinci_mdio";
		104	#address-cells = <1>;
		105	#size-cells = <0>;
		106	reg = <0x02090300 0x100>;
		107	status = "disabled";
		108	clocks = <&clkcpgmac>;
		109	clock-names = "fck";
		110	bus_freq = <2500000>;
		111	};
101	/include/ "k2hk-netcp.dtsi"	112	/include/ "k2hk-netcp.dtsi"
102	};	113	};
103	};	114	};

arch/arm/boot/dts/k2l-clocks.dtsi+2−3

 		#clock-cells = <0>;
 		compatible = "ti,keystone,main-pll-clock";
 		clocks = <&refclksys>;
-		reg = <0x02620350 4>, <0x02310110 4>;
+		reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
-		reg-names = "control", "multiplier";
+		reg-names = "control", "multiplier", "post-divider";
-		fixed-postdiv = <2>;
 	};
 	papllclk: papllclk@2620358 {

arch/arm/boot/dts/k2l.dtsi+11−5

 	};
 	soc {
 		/include/ "k2l-clocks.dtsi"
 		uart2: serial@02348400 {
 			#gpio-cells = <2>;
 			gpio,syscon-dev = <&devctrl 0x24c>;
 		};
+		mdio: mdio@26200f00 {
+			compatible	= "ti,keystone_mdio", "ti,davinci_mdio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x26200f00 0x100>;
+			status = "disabled";
+			clocks = <&clkcpgmac>;
+			clock-names = "fck";
+			bus_freq	= <2500000>;
+		};
 		/include/ "k2l-netcp.dtsi"
 	};
 };
        /* Pin muxed. Enabled and configured by Bootloader */
        status = "disabled";
 };
-&mdio {
-	reg = <0x26200f00 0x100>;
-};

arch/arm/boot/dts/keystone.dtsi+0−11

@@ -267,17 +267,6 @@ · 266 unmodified lines
267	1 0 0x21000A00 0x00000100>;	267	1 0 0x21000A00 0x00000100>;
268	};	268	};
269		269
270	mdio: mdio@02090300 {
271	compatible = "ti,keystone_mdio", "ti,davinci_mdio";
272	#address-cells = <1>;
273	#size-cells = <0>;
274	reg = <0x02090300 0x100>;
275	status = "disabled";
276	clocks = <&clkpa>;
277	clock-names = "fck";
278	bus_freq = <2500000>;
279	};
280
281	kirq0: keystone_irq@26202a0 {	270	kirq0: keystone_irq@26202a0 {
282	compatible = "ti,keystone-irq";	271	compatible = "ti,keystone-irq";
283	interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;	272	interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;

arch/arm/boot/dts/omap2430.dtsi+2−1

@@ -51,7 +51,8 @@ · 50 unmodified lines
51	};	51	};
52		52
53	scm_conf: scm_conf@270 {	53	scm_conf: scm_conf@270 {
54	compatible = "syscon";	54	compatible = "syscon",
		55	"simple-bus";
55	reg = <0x270 0x240>;	56	reg = <0x270 0x240>;
56	#address-cells = <1>;	57	#address-cells = <1>;
57	#size-cells = <1>;	58	#size-cells = <1>;

arch/arm/boot/dts/omap4.dtsi+2−1

@@ -191,7 +191,8 @@ · 190 unmodified lines
191	};	191	};
192		192
193	omap4_padconf_global: omap4_padconf_global@5a0 {	193	omap4_padconf_global: omap4_padconf_global@5a0 {
194	compatible = "syscon";	194	compatible = "syscon",
		195	"simple-bus";
195	reg = <0x5a0 0x170>;	196	reg = <0x5a0 0x170>;
196	#address-cells = <1>;	197	#address-cells = <1>;
197	#size-cells = <1>;	198	#size-cells = <1>;

arch/arm/boot/dts/omap5.dtsi+2−1

@@ -180,7 +180,8 @@ · 179 unmodified lines
180	};	180	};
181		181
182	omap5_padconf_global: omap5_padconf_global@5a0 {	182	omap5_padconf_global: omap5_padconf_global@5a0 {
183	compatible = "syscon";	183	compatible = "syscon",
		184	"simple-bus";
184	reg = <0x5a0 0xec>;	185	reg = <0x5a0 0xec>;
185	#address-cells = <1>;	186	#address-cells = <1>;
186	#size-cells = <1>;	187	#size-cells = <1>;

arch/arm/boot/dts/ste-dbx5x0.dtsi+27−26

 #include "skeleton.dtsi"
 / {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "ste,dbx500-smp";
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+				core1 {
+					cpu = <&CPU1>;
+				};
+			};
+		};
+		CPU0: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0x300>;
+		};
+		CPU1: cpu@301 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0x301>;
+		};
+	};
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		interrupt-parent = <&intc>;
 		ranges;
-		cpus {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			cpu-map {
-				cluster0 {
-					core0 {
-						cpu = <&CPU0>;
-					};
-					core1 {
-						cpu = <&CPU1>;
-					};
-				};
-			};
-			CPU0: cpu@0 {
-				device_type = "cpu";
-				compatible = "arm,cortex-a9";
-				reg = <0>;
-			};
-			CPU1: cpu@1 {
-				device_type = "cpu";
-				compatible = "arm,cortex-a9";
-				reg = <1>;
-			};
-		};
 		ptm@801ae000 {
 			compatible = "arm,coresight-etm3x", "arm,primecell";
 			reg = <0x801ae000 0x1000>;

arch/arm/boot/dts/ste-nomadik-nhk15.dts+1−0

@@ -17,6 +17,7 @@ · 16 unmodified lines
17	};	17	};
18		18
19	aliases {	19	aliases {
		20	serial1 = &uart1;
20	stmpe-i2c0 = &stmpe0;	21	stmpe-i2c0 = &stmpe0;
21	stmpe-i2c1 = &stmpe1;	22	stmpe-i2c1 = &stmpe1;
22	};	23	};

arch/arm/boot/dts/ste-nomadik-s8815.dts+4−0

 		bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk";
 	};
+	aliases {
+		serial1 = &uart1;
+	};
 	src@101e0000 {
 		/* These chrystal drivers are not used on this board */
 		disable-sxtalo;

arch/arm/boot/dts/ste-nomadik-stn8815.dtsi+1−0

@@ -757,6 +757,7 @@ · 756 unmodified lines
757	clock-names = "uartclk", "apb_pclk";	757	clock-names = "uartclk", "apb_pclk";
758	pinctrl-names = "default";	758	pinctrl-names = "default";
759	pinctrl-0 = <&uart0_default_mux>;	759	pinctrl-0 = <&uart0_default_mux>;
		760	status = "disabled";
760	};	761	};
761		762
762	uart1: uart@101fb000 {	763	uart1: uart@101fb000 {

arch/arm/kernel/entry-common.S+1−0

@@ -61,6 +61,7 @@ work_pending: · 60 unmodified lines
61	movlt scno, #(__NR_restart_syscall - __NR_SYSCALL_BASE)	61	movlt scno, #(__NR_restart_syscall - __NR_SYSCALL_BASE)
62	ldmia sp, {r0 - r6} @ have to reload r0 - r6	62	ldmia sp, {r0 - r6} @ have to reload r0 - r6
63	b local_restart @ ... and off we go	63	b local_restart @ ... and off we go
		64	ENDPROC(ret_fast_syscall)
64		65
65	/*	66	/*
66	* "slow" syscall return path. "why" tells us if this was a real syscall.	67	* "slow" syscall return path. "why" tells us if this was a real syscall.

arch/arm/kernel/head.S+3−0

 	sub	lr, r4, r5			@ mmu has been enabled
 	add	r3, r7, lr
 	ldrd	r4, [r3, #0]			@ get secondary_data.pgdir
+ARM_BE8(eor	r4, r4, r5)			@ Swap r5 and r4 in BE:
+ARM_BE8(eor	r5, r4, r5)			@ it can be done in 3 steps
+ARM_BE8(eor	r4, r4, r5)			@ without using a temp reg.
 	ldr	r8, [r3, #8]			@ get secondary_data.swapper_pg_dir
 	badr	lr, __enable_mmu		@ return address
 	mov	r13, r12			@ __secondary_switched address

arch/arm/kernel/vdso.c+3−4

  */
 void update_vsyscall(struct timekeeper *tk)
 {
-	struct timespec xtime_coarse;
 	struct timespec64 *wtm = &tk->wall_to_monotonic;
 	if (!cntvct_ok) {
 	vdso_write_begin(vdso_data);
-	xtime_coarse = __current_kernel_time();
 	vdso_data->tk_is_cntvct			= tk_is_cntvct(tk);
-	vdso_data->xtime_coarse_sec		= xtime_coarse.tv_sec;
+	vdso_data->xtime_coarse_sec		= tk->xtime_sec;
-	vdso_data->xtime_coarse_nsec		= xtime_coarse.tv_nsec;
+	vdso_data->xtime_coarse_nsec		= (u32)(tk->tkr_mono.xtime_nsec >>
+							tk->tkr_mono.shift);
 	vdso_data->wtm_clock_sec		= wtm->tv_sec;
 	vdso_data->wtm_clock_nsec		= wtm->tv_nsec;

arch/arm/mach-exynos/pm_domains.c+1−2

 		pd->base = of_iomap(np, 0);
 		if (!pd->base) {
 			pr_warn("%s: failed to map memory\n", __func__);
-			kfree(pd->pd.name);
+			kfree_const(pd->pd.name);
 			kfree(pd);
-			of_node_put(np);
 			continue;
 		}

arch/arm/mach-omap2/omap_hwmod.c+16−8

  * registers.  This address is needed early so the OCP registers that
  * are part of the device's address space can be ioremapped properly.
  *
+ * If SYSC access is not needed, the registers will not be remapped
+ * and non-availability of MPU access is not treated as an error.
+ *
  * Returns 0 on success, -EINVAL if an invalid hwmod is passed, and
  * -ENXIO on absent or invalid register target address space.
  */
 	_save_mpu_port_index(oh);
+	/* if we don't need sysc access we don't need to ioremap */
+	if (!oh->class->sysc)
+		return 0;
+	/* we can't continue without MPU PORT if we need sysc access */
 	if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
 		return -ENXIO;
 			 oh->name);
 		/* Extract the IO space from device tree blob */
-		if (!np)
+		if (!np) {
+			pr_err("omap_hwmod: %s: no dt node\n", oh->name);
 			return -ENXIO;
+		}
 		va_start = of_iomap(np, index + oh->mpu_rt_idx);
 	} else {
 				oh->name, np->name);
 	}
-	if (oh->class->sysc) {
+	r = _init_mpu_rt_base(oh, NULL, index, np);
-		r = _init_mpu_rt_base(oh, NULL, index, np);
+	if (r < 0) {
-		if (r < 0) {
+		WARN(1, "omap_hwmod: %s: doesn't have mpu register target base\n",
-			WARN(1, "omap_hwmod: %s: doesn't have mpu register target base\n",
+		     oh->name);
-			     oh->name);
+		return 0;
-			return 0;
-		}
 	}
 	r = _init_clocks(oh, NULL);

arch/arm/mach-omap2/omap_hwmod_7xx_data.c+2−3

 	.syss_offs	= 0x0014,
 	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-			   SIDLE_SMART_WKUP),
 	.sysc_fields	= &omap_hwmod_sysc_type1,
 };
 	.class		= &dra7xx_gpmc_hwmod_class,
 	.clkdm_name	= "l3main1_clkdm",
 	/* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
-	.flags		= HWMOD_SWSUP_SIDLE | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
+	.flags		= DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 	.main_clk	= "l3_iclk_div",
 	.prcm = {
 		.omap4 = {

arch/arm/net/bpf_jit_32.c+44−13

 int bpf_jit_enable __read_mostly;
-static u64 jit_get_skb_b(struct sk_buff *skb, unsigned offset)
+static inline int call_neg_helper(struct sk_buff *skb, int offset, void *ret,
+		      unsigned int size)
+{
+	void *ptr = bpf_internal_load_pointer_neg_helper(skb, offset, size);
+	if (!ptr)
+		return -EFAULT;
+	memcpy(ret, ptr, size);
+	return 0;
+}
+static u64 jit_get_skb_b(struct sk_buff *skb, int offset)
 {
 	u8 ret;
 	int err;
-	err = skb_copy_bits(skb, offset, &ret, 1);
+	if (offset < 0)
+		err = call_neg_helper(skb, offset, &ret, 1);
+	else
+		err = skb_copy_bits(skb, offset, &ret, 1);
 	return (u64)err << 32 | ret;
 }
-static u64 jit_get_skb_h(struct sk_buff *skb, unsigned offset)
+static u64 jit_get_skb_h(struct sk_buff *skb, int offset)
 {
 	u16 ret;
 	int err;
-	err = skb_copy_bits(skb, offset, &ret, 2);
+	if (offset < 0)
+		err = call_neg_helper(skb, offset, &ret, 2);
+	else
+		err = skb_copy_bits(skb, offset, &ret, 2);
 	return (u64)err << 32 | ntohs(ret);
 }
-static u64 jit_get_skb_w(struct sk_buff *skb, unsigned offset)
+static u64 jit_get_skb_w(struct sk_buff *skb, int offset)
 {
 	u32 ret;
 	int err;
-	err = skb_copy_bits(skb, offset, &ret, 4);
+	if (offset < 0)
+		err = call_neg_helper(skb, offset, &ret, 4);
+	else
+		err = skb_copy_bits(skb, offset, &ret, 4);
 	return (u64)err << 32 | ntohl(ret);
 }
 		case BPF_LD | BPF_B | BPF_ABS:
 			load_order = 0;
 load:
-			/* the interpreter will deal with the negative K */
-			if ((int)k < 0)
-				return -ENOTSUPP;
 			emit_mov_i(r_off, k, ctx);
 load_common:
 			ctx->seen |= SEEN_DATA | SEEN_CALL;
 				emit(ARM_SUB_I(r_scratch, r_skb_hl,
 					       1 << load_order), ctx);
 				emit(ARM_CMP_R(r_scratch, r_off), ctx);
-				condt = ARM_COND_HS;
+				condt = ARM_COND_GE;
 			} else {
 				emit(ARM_CMP_R(r_skb_hl, r_off), ctx);
 				condt = ARM_COND_HI;
 			}
+			/*
+			 * test for negative offset, only if we are
+			 * currently scheduled to take the fast
+			 * path. this will update the flags so that
+			 * the slowpath instruction are ignored if the
+			 * offset is negative.
+			 *
+			 * for loard_order == 0 the HI condition will
+			 * make loads at offset 0 take the slow path too.
+			 */
+			_emit(condt, ARM_CMP_I(r_off, 0), ctx);
 			_emit(condt, ARM_ADD_R(r_scratch, r_off, r_skb_data),
 			      ctx);
 			off = offsetof(struct sk_buff, vlan_tci);
 			emit(ARM_LDRH_I(r_A, r_skb, off), ctx);
 			if (code == (BPF_ANC | SKF_AD_VLAN_TAG))
-				OP_IMM3(ARM_AND, r_A, r_A, VLAN_VID_MASK, ctx);
+				OP_IMM3(ARM_AND, r_A, r_A, ~VLAN_TAG_PRESENT, ctx);
-			else
+			else {
-				OP_IMM3(ARM_AND, r_A, r_A, VLAN_TAG_PRESENT, ctx);
+				OP_IMM3(ARM_LSR, r_A, r_A, 12, ctx);
+				OP_IMM3(ARM_AND, r_A, r_A, 0x1, ctx);
+			}
 			break;
 		case BPF_ANC | SKF_AD_QUEUE:
 			ctx->seen |= SEEN_SKB;

arch/arm/vdso/Makefile+1−1

@@ -14,7 +14,7 @@ VDSO_LDFLAGS += -Wl,-z,max-page-size=4096 -Wl,-z,common-page-size=4096 · 13 unmodified lines
14	VDSO_LDFLAGS += -nostdlib -shared	14	VDSO_LDFLAGS += -nostdlib -shared
15	VDSO_LDFLAGS += $(call cc-ldoption, -Wl$(comma)--hash-style=sysv)	15	VDSO_LDFLAGS += $(call cc-ldoption, -Wl$(comma)--hash-style=sysv)
16	VDSO_LDFLAGS += $(call cc-ldoption, -Wl$(comma)--build-id)	16	VDSO_LDFLAGS += $(call cc-ldoption, -Wl$(comma)--build-id)
17	VDSO_LDFLAGS += $(call cc-option, -fuse-ld=bfd)	17	VDSO_LDFLAGS += $(call cc-ldoption, -fuse-ld=bfd)
18		18
19	obj-$(CONFIG_VDSO) += vdso.o	19	obj-$(CONFIG_VDSO) += vdso.o
20	extra-$(CONFIG_VDSO) += vdso.lds	20	extra-$(CONFIG_VDSO) += vdso.lds

arch/arm64/boot/dts/apm/apm-storm.dtsi+1−1

@@ -823,7 +823,7 @@ · 822 unmodified lines
823	device_type = "dma";	823	device_type = "dma";
824	reg = <0x0 0x1f270000 0x0 0x10000>,	824	reg = <0x0 0x1f270000 0x0 0x10000>,
825	<0x0 0x1f200000 0x0 0x10000>,	825	<0x0 0x1f200000 0x0 0x10000>,
826	<0x0 0x1b008000 0x0 0x2000>,	826	<0x0 0x1b000000 0x0 0x400000>,
827	<0x0 0x1054a000 0x0 0x100>;	827	<0x0 0x1054a000 0x0 0x100>;
828	interrupts = <0x0 0x82 0x4>,	828	interrupts = <0x0 0x82 0x4>,
829	<0x0 0xb8 0x4>,	829	<0x0 0xb8 0x4>,

arch/arm64/kernel/efi.c+2−2

@@ -122,12 +122,12 @@ static int __init uefi_init(void) · 121 unmodified lines
122		122
123	/* Show what we know for posterity */	123	/* Show what we know for posterity */
124	c16 = early_memremap(efi_to_phys(efi.systab->fw_vendor),	124	c16 = early_memremap(efi_to_phys(efi.systab->fw_vendor),
125	sizeof(vendor));	125	sizeof(vendor) * sizeof(efi_char16_t));
126	if (c16) {	126	if (c16) {
127	for (i = 0; i < (int) sizeof(vendor) - 1 && *c16; ++i)	127	for (i = 0; i < (int) sizeof(vendor) - 1 && *c16; ++i)
128	vendor[i] = c16[i];	128	vendor[i] = c16[i];
129	vendor[i] = '\0';	129	vendor[i] = '\0';
130	early_memunmap(c16, sizeof(vendor));	130	early_memunmap(c16, sizeof(vendor) * sizeof(efi_char16_t));
131	}	131	}
132		132
133	pr_info("EFI v%u.%.02u by %s\n",	133	pr_info("EFI v%u.%.02u by %s\n",

arch/arm64/kernel/entry.S+3−2

  *
  */
 ENTRY(cpu_switch_to)
-	add	x8, x0, #THREAD_CPU_CONTEXT
+	mov	x10, #THREAD_CPU_CONTEXT
+	add	x8, x0, x10
 	mov	x9, sp
 	stp	x19, x20, [x8], #16		// store callee-saved registers
 	stp	x21, x22, [x8], #16
 	stp	x27, x28, [x8], #16
 	stp	x29, x9, [x8], #16
 	str	lr, [x8]
-	add	x8, x1, #THREAD_CPU_CONTEXT
+	add	x8, x1, x10
 	ldp	x19, x20, [x8], #16		// restore callee-saved registers
 	ldp	x21, x22, [x8], #16
 	ldp	x23, x24, [x8], #16

arch/arm64/kernel/irq.c+2−2

@@ -61,7 +61,7 @@ void __init init_IRQ(void) · 60 unmodified lines
61	static bool migrate_one_irq(struct irq_desc *desc)	61	static bool migrate_one_irq(struct irq_desc *desc)
62	{	62	{
63	struct irq_data *d = irq_desc_get_irq_data(desc);	63	struct irq_data *d = irq_desc_get_irq_data(desc);
64	const struct cpumask *affinity = d->affinity;	64	const struct cpumask *affinity = irq_data_get_affinity_mask(d);
65	struct irq_chip *c;	65	struct irq_chip *c;
66	bool ret = false;	66	bool ret = false;
67		67
@@ -81,7 +81,7 @@ static bool migrate_one_irq(struct irq_desc *desc) · 13 unmodified lines
81	if (!c->irq_set_affinity)	81	if (!c->irq_set_affinity)
82	pr_debug("IRQ%u: unable to set affinity\n", d->irq);	82	pr_debug("IRQ%u: unable to set affinity\n", d->irq);
83	else if (c->irq_set_affinity(d, affinity, false) == IRQ_SET_MASK_OK && ret)	83	else if (c->irq_set_affinity(d, affinity, false) == IRQ_SET_MASK_OK && ret)
84	cpumask_copy(d->affinity, affinity);	84	cpumask_copy(irq_data_get_affinity_mask(d), affinity);
85		85
86	return ret;	86	return ret;
87	}	87	}

arch/arm64/kernel/signal32.c+2−3

 		 * Other callers might not initialize the si_lsb field,
 		 * so check explicitely for the right codes here.
 		 */
-		if (from->si_code == BUS_MCEERR_AR || from->si_code == BUS_MCEERR_AO)
+		if (from->si_signo == SIGBUS &&
+		    (from->si_code == BUS_MCEERR_AR || from->si_code == BUS_MCEERR_AO))
 			err |= __put_user(from->si_addr_lsb, &to->si_addr_lsb);
 #endif
 		break;
 int copy_siginfo_from_user32(siginfo_t *to, compat_siginfo_t __user *from)
 {
-	memset(to, 0, sizeof *to);
 	if (copy_from_user(to, from, __ARCH_SI_PREAMBLE_SIZE) ||
 	    copy_from_user(to->_sifields._pad,
 			   from->_sifields._pad, SI_PAD_SIZE))

arch/arm64/kernel/vdso.c+3−4

  */
 void update_vsyscall(struct timekeeper *tk)
 {
-	struct timespec xtime_coarse;
 	u32 use_syscall = strcmp(tk->tkr_mono.clock->name, "arch_sys_counter");
 	++vdso_data->tb_seq_count;
 	smp_wmb();
-	xtime_coarse = __current_kernel_time();
 	vdso_data->use_syscall			= use_syscall;
-	vdso_data->xtime_coarse_sec		= xtime_coarse.tv_sec;
+	vdso_data->xtime_coarse_sec		= tk->xtime_sec;
-	vdso_data->xtime_coarse_nsec		= xtime_coarse.tv_nsec;
+	vdso_data->xtime_coarse_nsec		= tk->tkr_mono.xtime_nsec >>
+							tk->tkr_mono.shift;
 	vdso_data->wtm_clock_sec		= tk->wall_to_monotonic.tv_sec;
 	vdso_data->wtm_clock_nsec		= tk->wall_to_monotonic.tv_nsec;

arch/avr32/kernel/time.c+33−32

@@ -18,6 +18,7 @@ · 17 unmodified lines
18		18
19	#include <mach/pm.h>	19	#include <mach/pm.h>
20		20
		21	static bool disable_cpu_idle_poll;
21		22
22	static cycle_t read_cycle_count(struct clocksource *cs)	23	static cycle_t read_cycle_count(struct clocksource *cs)
23	{	24	{
@@ -80,45 +81,45 @@ static int comparator_next_event(unsigned long delta, · 56 unmodified lines
80	return 0;	81	return 0;
81	}	82	}
82		83
83	static void comparator_mode(enum clock_event_mode mode,	84	static int comparator_shutdown(struct clock_event_device *evdev)
84	struct clock_event_device *evdev)
85	{	85	{
86	switch (mode) {	86	pr_debug("%s: %s\n", __func__, evdev->name);
87	case CLOCK_EVT_MODE_ONESHOT:	87	sysreg_write(COMPARE, 0);
88	pr_debug("%s: start\n", evdev->name);	88
89	/* FALLTHROUGH */	89	if (disable_cpu_idle_poll) {
90	case CLOCK_EVT_MODE_RESUME:	90	disable_cpu_idle_poll = false;
91	/*	91	/*
92	* If we're using the COUNT and COMPARE registers we	92	* Only disable idle poll if we have forced that
93	* need to force idle poll.	93	* in a previous call.
94	*/	94	*/
95	cpu_idle_poll_ctrl(true);	95	cpu_idle_poll_ctrl(false);
96	break;
97	case CLOCK_EVT_MODE_UNUSED:
98	case CLOCK_EVT_MODE_SHUTDOWN:
99	sysreg_write(COMPARE, 0);
100	pr_debug("%s: stop\n", evdev->name);
101	if (evdev->mode == CLOCK_EVT_MODE_ONESHOT \|\|
102	evdev->mode == CLOCK_EVT_MODE_RESUME) {
103	/*
104	* Only disable idle poll if we have forced that
105	* in a previous call.
106	*/
107	cpu_idle_poll_ctrl(false);
108	}
109	break;
110	default:
111	BUG();
112	}	96	}
		97	return 0;
		98	}
		99
		100	static int comparator_set_oneshot(struct clock_event_device *evdev)
		101	{
		102	pr_debug("%s: %s\n", __func__, evdev->name);
		103
		104	disable_cpu_idle_poll = true;
		105	/*
		106	* If we're using the COUNT and COMPARE registers we
		107	* need to force idle poll.
		108	*/
		109	cpu_idle_poll_ctrl(true);
		110
		111	return 0;
113	}	112	}
114		113
115	static struct clock_event_device comparator = {	114	static struct clock_event_device comparator = {
116	.name = "avr32_comparator",	115	.name = "avr32_comparator",
117	.features = CLOCK_EVT_FEAT_ONESHOT,	116	.features = CLOCK_EVT_FEAT_ONESHOT,
118	.shift = 16,	117	.shift = 16,
119	.rating = 50,	118	.rating = 50,
120	.set_next_event = comparator_next_event,	119	.set_next_event = comparator_next_event,
121	.set_mode = comparator_mode,	120	.set_state_shutdown = comparator_shutdown,
		121	.set_state_oneshot = comparator_set_oneshot,
		122	.tick_resume = comparator_set_oneshot,
122	};	123	};
123		124
124	void read_persistent_clock(struct timespec *ts)	125	void read_persistent_clock(struct timespec *ts)

arch/avr32/mach-at32ap/clock.c+19−1

 {
 	unsigned long flags;
+	if (!clk)
+		return 0;
 	spin_lock_irqsave(&clk_lock, flags);
 	__clk_enable(clk);
 	spin_unlock_irqrestore(&clk_lock, flags);
 {
 	unsigned long flags;
+	if (IS_ERR_OR_NULL(clk))
+		return;
 	spin_lock_irqsave(&clk_lock, flags);
 	__clk_disable(clk);
 	spin_unlock_irqrestore(&clk_lock, flags);
 	unsigned long flags;
 	unsigned long rate;
+	if (!clk)
+		return 0;
 	spin_lock_irqsave(&clk_lock, flags);
 	rate = clk->get_rate(clk);
 	spin_unlock_irqrestore(&clk_lock, flags);
 {
 	unsigned long flags, actual_rate;
+	if (!clk)
+		return 0;
 	if (!clk->set_rate)
 		return -ENOSYS;
 	unsigned long flags;
 	long ret;
+	if (!clk)
+		return 0;
 	if (!clk->set_rate)
 		return -ENOSYS;
 	unsigned long flags;
 	int ret;
+	if (!clk)
+		return 0;
 	if (!clk->set_parent)
 		return -ENOSYS;
 struct clk *clk_get_parent(struct clk *clk)
 {
-	return clk->parent;
+	return !clk ? NULL : clk->parent;
 }
 EXPORT_SYMBOL(clk_get_parent);

arch/m32r/include/asm/io.h+5−0

 #define iowrite16 writew
 #define iowrite32 writel
+#define ioread16be(addr)	be16_to_cpu(readw(addr))
+#define ioread32be(addr)	be32_to_cpu(readl(addr))
+#define iowrite16be(v, addr)	writew(cpu_to_be16(v), (addr))
+#define iowrite32be(v, addr)	writel(cpu_to_be32(v), (addr))
 #define mmiowb()
 #define flush_write_buffers() do { } while (0)  /* M32R_FIXME */

arch/mips/Kconfig+0−1

@@ -151,7 +151,6 @@ config BMIPS_GENERIC · 150 unmodified lines
151	select BCM7120_L2_IRQ	151	select BCM7120_L2_IRQ
152	select BRCMSTB_L2_IRQ	152	select BRCMSTB_L2_IRQ
153	select IRQ_MIPS_CPU	153	select IRQ_MIPS_CPU
154	select RAW_IRQ_ACCESSORS
155	select DMA_NONCOHERENT	154	select DMA_NONCOHERENT
156	select SYS_SUPPORTS_32BIT_KERNEL	155	select SYS_SUPPORTS_32BIT_KERNEL
157	select SYS_SUPPORTS_LITTLE_ENDIAN	156	select SYS_SUPPORTS_LITTLE_ENDIAN

arch/mips/ath79/setup.c+1−0

@@ -190,6 +190,7 @@ int get_c0_perfcount_int(void) · 189 unmodified lines
190	{	190	{
191	return ATH79_MISC_IRQ(5);	191	return ATH79_MISC_IRQ(5);
192	}	192	}
		193	EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
193		194
194	unsigned int get_c0_compare_int(void)	195	unsigned int get_c0_compare_int(void)
195	{	196	{

arch/mips/cavium-octeon/smp.c+1−1

@@ -42,7 +42,7 @@ static irqreturn_t mailbox_interrupt(int irq, void *dev_id) · 41 unmodified lines
42	cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);	42	cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);
43		43
44	if (action & SMP_CALL_FUNCTION)	44	if (action & SMP_CALL_FUNCTION)
45	smp_call_function_interrupt();	45	generic_smp_call_function_interrupt();
46	if (action & SMP_RESCHEDULE_YOURSELF)	46	if (action & SMP_RESCHEDULE_YOURSELF)
47	scheduler_ipi();	47	scheduler_ipi();
48		48

arch/mips/include/asm/mach-bcm63xx/dma-coherence.h+0−10

@@ -1,10 +0,0 @@
1	#ifndef __ASM_MACH_BCM63XX_DMA_COHERENCE_H
2	#define __ASM_MACH_BCM63XX_DMA_COHERENCE_H
3
4	#include <asm/bmips.h>
5
6	#define plat_post_dma_flush bmips_post_dma_flush
7
8	#include <asm/mach-generic/dma-coherence.h>
9
10	#endif /* __ASM_MACH_BCM63XX_DMA_COHERENCE_H */

arch/mips/include/asm/pgtable.h+31−0

@@ -182,8 +182,39 @@ static inline void set_pte(pte_t *ptep, pte_t pteval) · 181 unmodified lines
182	* Make sure the buddy is global too (if it's !none,	182	* Make sure the buddy is global too (if it's !none,
183	* it better already be global)	183	* it better already be global)
184	*/	184	*/
		185	#ifdef CONFIG_SMP
		186	/*
		187	* For SMP, multiple CPUs can race, so we need to do
		188	* this atomically.
		189	*/
		190	#ifdef CONFIG_64BIT
		191	#define LL_INSN "lld"
		192	#define SC_INSN "scd"
		193	#else /* CONFIG_32BIT */
		194	#define LL_INSN "ll"
		195	#define SC_INSN "sc"
		196	#endif
		197	unsigned long page_global = _PAGE_GLOBAL;
		198	unsigned long tmp;
		199
		200	__asm__ __volatile__ (
		201	" .set push\n"
		202	" .set noreorder\n"
		203	"1: " LL_INSN " %[tmp], %[buddy]\n"
		204	" bnez %[tmp], 2f\n"
		205	" or %[tmp], %[tmp], %[global]\n"
		206	" " SC_INSN " %[tmp], %[buddy]\n"
		207	" beqz %[tmp], 1b\n"
		208	" nop\n"
		209	"2:\n"
		210	" .set pop"
		211	: [buddy] "+m" (buddy->pte),
		212	[tmp] "=&r" (tmp)
		213	: [global] "r" (page_global));
		214	#else /* !CONFIG_SMP */
185	if (pte_none(*buddy))	215	if (pte_none(*buddy))
186	pte_val(buddy) = pte_val(buddy) \| _PAGE_GLOBAL;	216	pte_val(buddy) = pte_val(buddy) \| _PAGE_GLOBAL;
		217	#endif /* CONFIG_SMP */
187	}	218	}
188	#endif	219	#endif
189	}	220	}

arch/mips/include/asm/smp.h+0−2

@@ -83,8 +83,6 @@ static inline void __cpu_die(unsigned int cpu) · 82 unmodified lines
83	extern void play_dead(void);	83	extern void play_dead(void);
84	#endif	84	#endif
85		85
86	extern asmlinkage void smp_call_function_interrupt(void);
87
88	static inline void arch_send_call_function_single_ipi(int cpu)	86	static inline void arch_send_call_function_single_ipi(int cpu)
89	{	87	{
90	extern struct plat_smp_ops mp_ops; / private */	88	extern struct plat_smp_ops mp_ops; / private */

arch/mips/include/asm/stackframe.h+25−0

@@ -152,6 +152,31 @@ · 151 unmodified lines
152	.set noreorder	152	.set noreorder
153	bltz k0, 8f	153	bltz k0, 8f
154	move k1, sp	154	move k1, sp
		155	#ifdef CONFIG_EVA
		156	/*
		157	* Flush interAptiv's Return Prediction Stack (RPS) by writing
		158	* EntryHi. Toggling Config7.RPS is slower and less portable.
		159	*
		160	* The RPS isn't automatically flushed when exceptions are
		161	* taken, which can result in kernel mode speculative accesses
		162	* to user addresses if the RPS mispredicts. That's harmless
		163	* when user and kernel share the same address space, but with
		164	* EVA the same user segments may be unmapped to kernel mode,
		165	* even containing sensitive MMIO regions or invalid memory.
		166	*
		167	* This can happen when the kernel sets the return address to
		168	* ret_from_* and jr's to the exception handler, which looks
		169	* more like a tail call than a function call. If nested calls
		170	* don't evict the last user address in the RPS, it will
		171	* mispredict the return and fetch from a user controlled
		172	* address into the icache.
		173	*
		174	* More recent EVA-capable cores with MAAR to restrict
		175	* speculative accesses aren't affected.
		176	*/
		177	MFC0 k0, CP0_ENTRYHI
		178	MTC0 k0, CP0_ENTRYHI
		179	#endif
155	.set reorder	180	.set reorder
156	/* Called from user mode, new stack. */	181	/* Called from user mode, new stack. */
157	get_saved_sp	182	get_saved_sp

arch/mips/kernel/mips-mt-fpaff.c+3−2

 				      unsigned long __user *user_mask_ptr)
 {
 	unsigned int real_len;
-	cpumask_t mask;
+	cpumask_t allowed, mask;
 	int retval;
 	struct task_struct *p;
 	if (retval)
 		goto out_unlock;
-	cpumask_and(&mask, &p->thread.user_cpus_allowed, cpu_possible_mask);
+	cpumask_or(&allowed, &p->thread.user_cpus_allowed, &p->cpus_allowed);
+	cpumask_and(&mask, &allowed, cpu_active_mask);
 out_unlock:
 	read_unlock(&tasklist_lock);

arch/mips/kernel/prom.c+1−1

@@ -38,7 +38,7 @@ char *mips_get_machine_name(void) · 37 unmodified lines
38	return mips_machine_name;	38	return mips_machine_name;
39	}	39	}
40		40
41	#ifdef CONFIG_OF	41	#ifdef CONFIG_USE_OF
42	void __init early_init_dt_add_memory_arch(u64 base, u64 size)	42	void __init early_init_dt_add_memory_arch(u64 base, u64 size)
43	{	43	{
44	return add_memory_region(base, size, BOOT_MEM_RAM);	44	return add_memory_region(base, size, BOOT_MEM_RAM);

arch/mips/kernel/relocate_kernel.S+4−4

@@ -24,7 +24,7 @@ LEAF(relocate_new_kernel) · 23 unmodified lines
24		24
25	process_entry:	25	process_entry:
26	PTR_L s2, (s0)	26	PTR_L s2, (s0)
27	PTR_ADD s0, s0, SZREG	27	PTR_ADDIU s0, s0, SZREG
28		28
29	/*	29	/*
30	* In case of a kdump/crash kernel, the indirection page is not	30	* In case of a kdump/crash kernel, the indirection page is not
@@ -61,9 +61,9 @@ copy_word: · 30 unmodified lines
61	/* copy page word by word */	61	/* copy page word by word */
62	REG_L s5, (s2)	62	REG_L s5, (s2)
63	REG_S s5, (s4)	63	REG_S s5, (s4)
64	PTR_ADD s4, s4, SZREG	64	PTR_ADDIU s4, s4, SZREG
65	PTR_ADD s2, s2, SZREG	65	PTR_ADDIU s2, s2, SZREG
66	LONG_SUB s6, s6, 1	66	LONG_ADDIU s6, s6, -1
67	beq s6, zero, process_entry	67	beq s6, zero, process_entry
68	b copy_word	68	b copy_word
69	b process_entry	69	b process_entry

arch/mips/kernel/scall64-64.S+1−1

@@ -80,7 +80,7 @@ syscall_trace_entry: · 79 unmodified lines
80	SAVE_STATIC	80	SAVE_STATIC
81	move s0, t2	81	move s0, t2
82	move a0, sp	82	move a0, sp
83	daddiu a1, v0, __NR_64_Linux	83	move a1, v0
84	jal syscall_trace_enter	84	jal syscall_trace_enter
85		85
86	bltz v0, 2f # seccomp failed? Skip syscall	86	bltz v0, 2f # seccomp failed? Skip syscall

arch/mips/kernel/scall64-n32.S+1−1

@@ -72,7 +72,7 @@ n32_syscall_trace_entry: · 71 unmodified lines
72	SAVE_STATIC	72	SAVE_STATIC
73	move s0, t2	73	move s0, t2
74	move a0, sp	74	move a0, sp
75	daddiu a1, v0, __NR_N32_Linux	75	move a1, v0
76	jal syscall_trace_enter	76	jal syscall_trace_enter
77		77
78	bltz v0, 2f # seccomp failed? Skip syscall	78	bltz v0, 2f # seccomp failed? Skip syscall

arch/mips/kernel/signal32.c+0−2

@@ -409,8 +409,6 @@ int copy_siginfo_to_user32(compat_siginfo_t __user to, const siginfo_t from) · 408 unmodified lines
409		409
410	int copy_siginfo_from_user32(siginfo_t to, compat_siginfo_t __user from)	410	int copy_siginfo_from_user32(siginfo_t to, compat_siginfo_t __user from)
411	{	411	{
412	memset(to, 0, sizeof *to);
413
414	if (copy_from_user(to, from, 3*sizeof(int)) \|\|	412	if (copy_from_user(to, from, 3*sizeof(int)) \|\|
415	copy_from_user(to->_sifields._pad,	413	copy_from_user(to->_sifields._pad,
416	from->_sifields._pad, SI_PAD_SIZE32))	414	from->_sifields._pad, SI_PAD_SIZE32))

arch/mips/kernel/smp-bmips.c+2−2

@@ -284,7 +284,7 @@ static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id) · 283 unmodified lines
284	if (action == 0)	284	if (action == 0)
285	scheduler_ipi();	285	scheduler_ipi();
286	else	286	else
287	smp_call_function_interrupt();	287	generic_smp_call_function_interrupt();
288		288
289	return IRQ_HANDLED;	289	return IRQ_HANDLED;
290	}	290	}
@@ -336,7 +336,7 @@ static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id) · 45 unmodified lines
336	if (action & SMP_RESCHEDULE_YOURSELF)	336	if (action & SMP_RESCHEDULE_YOURSELF)
337	scheduler_ipi();	337	scheduler_ipi();
338	if (action & SMP_CALL_FUNCTION)	338	if (action & SMP_CALL_FUNCTION)
339	smp_call_function_interrupt();	339	generic_smp_call_function_interrupt();
340		340
341	return IRQ_HANDLED;	341	return IRQ_HANDLED;
342	}	342	}

arch/mips/kernel/smp.c+0−10

@@ -192,16 +192,6 @@ asmlinkage void start_secondary(void) · 191 unmodified lines
192	cpu_startup_entry(CPUHP_ONLINE);	192	cpu_startup_entry(CPUHP_ONLINE);
193	}	193	}
194		194
195	/*
196	* Call into both interrupt handlers, as we share the IPI for them
197	*/
198	void __irq_entry smp_call_function_interrupt(void)
199	{
200	irq_enter();
201	generic_smp_call_function_interrupt();
202	irq_exit();
203	}
204
205	static void stop_this_cpu(void *dummy)	195	static void stop_this_cpu(void *dummy)
206	{	196	{
207	/*	197	/*

arch/mips/kernel/traps.c+13−0

 void show_stack(struct task_struct *task, unsigned long *sp)
 {
 	struct pt_regs regs;
+	mm_segment_t old_fs = get_fs();
 	if (sp) {
 		regs.regs[29] = (unsigned long)sp;
 		regs.regs[31] = 0;
 			prepare_frametrace(&regs);
 		}
 	}
+	/*
+	 * show_stack() deals exclusively with kernel mode, so be sure to access
+	 * the stack in the kernel (not user) address space.
+	 */
+	set_fs(KERNEL_DS);
 	show_stacktrace(task, &regs);
+	set_fs(old_fs);
 }
 static void show_code(unsigned int __user *pc)
 	const int field = 2 * sizeof(unsigned long);
 	int multi_match = regs->cp0_status & ST0_TS;
 	enum ctx_state prev_state;
+	mm_segment_t old_fs = get_fs();
 	prev_state = exception_enter();
 	show_regs(regs);
 		dump_tlb_all();
 	}
+	if (!user_mode(regs))
+		set_fs(KERNEL_DS);
 	show_code((unsigned int __user *) regs->cp0_epc);
+	set_fs(old_fs);
 	/*
 	 * Some chips may have other causes of machine check (e.g. SB1
 	 * graduation timer)

arch/mips/kernel/unaligned.c+1−1

@@ -438,7 +438,7 @@ do { \ · 437 unmodified lines
438	: "memory"); \	438	: "memory"); \
439	} while(0)	439	} while(0)
440		440
441	#define StoreDW(addr, value, res) \	441	#define _StoreDW(addr, value, res) \
442	do { \	442	do { \
443	__asm__ __volatile__ ( \	443	__asm__ __volatile__ ( \
444	".set\tpush\n\t" \	444	".set\tpush\n\t" \

arch/mips/lantiq/irq.c+2−1

 static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
 {
-	smp_call_function_interrupt();
+	generic_smp_call_function_interrupt();
 	return IRQ_HANDLED;
 }
 {
 	return ltq_perfcount_irq;
 }
+EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
 unsigned int get_c0_compare_int(void)
 {

arch/mips/loongson64/loongson-3/smp.c+5−2

 	if (action & SMP_RESCHEDULE_YOURSELF)
 		scheduler_ipi();
-	if (action & SMP_CALL_FUNCTION)
+	if (action & SMP_CALL_FUNCTION) {
-		smp_call_function_interrupt();
+		irq_enter();
+		generic_smp_call_function_interrupt();
+		irq_exit();
+	}
 	if (action & SMP_ASK_C0COUNT) {
 		BUG_ON(cpu != 0);

arch/mips/mm/cache.c+4−4

arch/mips/mm/fault.c+2−1

 #endif
 				goto bad_area;
 			}
-			if (!(vma->vm_flags & VM_READ)) {
+			if (!(vma->vm_flags & VM_READ) &&
+			    exception_epc(regs) != address) {
 #if 0
 				pr_notice("Cpu%d[%s:%d:%0*lx:%ld:%0*lx] RI violation\n",
 					  raw_smp_processor_id(),

arch/mips/mti-malta/malta-int.c+1−1

@@ -222,7 +222,7 @@ static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) · 221 unmodified lines
222		222
223	static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)	223	static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
224	{	224	{
225	smp_call_function_interrupt();	225	generic_smp_call_function_interrupt();
226		226
227	return IRQ_HANDLED;	227	return IRQ_HANDLED;
228	}	228	}

arch/mips/mti-malta/malta-time.c+10−6

 	return mips_cpu_perf_irq;
 }
+EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
 unsigned int get_c0_compare_int(void)
 {
 static void __init init_rtc(void)
 {
-	/* stop the clock whilst setting it up */
+	unsigned char freq, ctrl;
-	CMOS_WRITE(RTC_SET | RTC_24H, RTC_CONTROL);
-	/* 32KHz time base */
+	/* Set 32KHz time base if not already set */
-	CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_FREQ_SELECT);
+	freq = CMOS_READ(RTC_FREQ_SELECT);
+	if ((freq & RTC_DIV_CTL) != RTC_REF_CLCK_32KHZ)
+		CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_FREQ_SELECT);
-	/* start the clock */
+	/* Ensure SET bit is clear so RTC can run */
-	CMOS_WRITE(RTC_24H, RTC_CONTROL);
+	ctrl = CMOS_READ(RTC_CONTROL);
+	if (ctrl & RTC_SET)
+		CMOS_WRITE(ctrl & ~RTC_SET, RTC_CONTROL);
 }
 void __init plat_time_init(void)

arch/mips/mti-sead3/sead3-time.c+1−0

@@ -77,6 +77,7 @@ int get_c0_perfcount_int(void) · 76 unmodified lines
77	return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;	77	return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
78	return -1;	78	return -1;
79	}	79	}
		80	EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
80		81
81	unsigned int get_c0_compare_int(void)	82	unsigned int get_c0_compare_int(void)
82	{	83	{

arch/mips/netlogic/common/smp.c+1−1

@@ -86,7 +86,7 @@ void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc) · 85 unmodified lines
86	{	86	{
87	clear_c0_eimr(irq);	87	clear_c0_eimr(irq);
88	ack_c0_eirr(irq);	88	ack_c0_eirr(irq);
89	smp_call_function_interrupt();	89	generic_smp_call_function_interrupt();
90	set_c0_eimr(irq);	90	set_c0_eimr(irq);
91	}	91	}
92		92

arch/mips/paravirt/paravirt-smp.c+1−1

@@ -114,7 +114,7 @@ static irqreturn_t paravirt_reched_interrupt(int irq, void *dev_id) · 113 unmodified lines
114		114
115	static irqreturn_t paravirt_function_interrupt(int irq, void *dev_id)	115	static irqreturn_t paravirt_function_interrupt(int irq, void *dev_id)
116	{	116	{
117	smp_call_function_interrupt();	117	generic_smp_call_function_interrupt();
118	return IRQ_HANDLED;	118	return IRQ_HANDLED;
119	}	119	}
120		120

arch/mips/pistachio/time.c+1−0

@@ -26,6 +26,7 @@ int get_c0_perfcount_int(void) · 25 unmodified lines
26	{	26	{
27	return gic_get_c0_perfcount_int();	27	return gic_get_c0_perfcount_int();
28	}	28	}
		29	EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
29		30
30	int get_c0_fdc_int(void)	31	int get_c0_fdc_int(void)
31	{	32	{

arch/mips/pmcs-msp71xx/msp_smp.c+1−1

@@ -44,7 +44,7 @@ static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) · 43 unmodified lines
44		44
45	static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)	45	static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
46	{	46	{
47	smp_call_function_interrupt();	47	generic_smp_call_function_interrupt();
48		48
49	return IRQ_HANDLED;	49	return IRQ_HANDLED;
50	}	50	}

arch/mips/ralink/irq.c+1−0

@@ -89,6 +89,7 @@ int get_c0_perfcount_int(void) · 88 unmodified lines
89	{	89	{
90	return rt_perfcount_irq;	90	return rt_perfcount_irq;
91	}	91	}
		92	EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
92		93
93	unsigned int get_c0_compare_int(void)	94	unsigned int get_c0_compare_int(void)
94	{	95	{

arch/mips/sgi-ip27/ip27-irq.c+6−2

 		scheduler_ipi();
 	} else if (pend0 & (1UL << CPU_CALL_A_IRQ)) {
 		LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ);
-		smp_call_function_interrupt();
+		irq_enter();
+		generic_smp_call_function_interrupt();
+		irq_exit();
 	} else if (pend0 & (1UL << CPU_CALL_B_IRQ)) {
 		LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ);
-		smp_call_function_interrupt();
+		irq_enter();
+		generic_smp_call_function_interrupt();
+		irq_exit();
 	} else
 #endif
 	{

arch/mips/sibyte/bcm1480/smp.c+5−4

 #include <asm/sibyte/bcm1480_regs.h>
 #include <asm/sibyte/bcm1480_int.h>
-extern void smp_call_function_interrupt(void);
 /*
  * These are routines for dealing with the bcm1480 smp capabilities
  * independent of board/firmware
 	if (action & SMP_RESCHEDULE_YOURSELF)
 		scheduler_ipi();
-	if (action & SMP_CALL_FUNCTION)
+	if (action & SMP_CALL_FUNCTION) {
-		smp_call_function_interrupt();
+		irq_enter();
+		generic_smp_call_function_interrupt();
+		irq_exit();
+	}
 }

arch/mips/sibyte/sb1250/smp.c+5−2

 	if (action & SMP_RESCHEDULE_YOURSELF)
 		scheduler_ipi();
-	if (action & SMP_CALL_FUNCTION)
+	if (action & SMP_CALL_FUNCTION) {
-		smp_call_function_interrupt();
+		irq_enter();
+		generic_smp_call_function_interrupt();
+		irq_exit();
+	}
 }

arch/powerpc/kernel/signal_32.c+0−2

@@ -966,8 +966,6 @@ int copy_siginfo_to_user32(struct compat_siginfo __user d, const siginfo_t s) · 965 unmodified lines
966		966
967	int copy_siginfo_from_user32(siginfo_t to, struct compat_siginfo __user from)	967	int copy_siginfo_from_user32(siginfo_t to, struct compat_siginfo __user from)
968	{	968	{
969	memset(to, 0, sizeof *to);
970
971	if (copy_from_user(to, from, 3*sizeof(int)) \|\|	969	if (copy_from_user(to, from, 3*sizeof(int)) \|\|
972	copy_from_user(to->_sifields._pad,	970	copy_from_user(to->_sifields._pad,
973	from->_sifields._pad, SI_PAD_SIZE32))	971	from->_sifields._pad, SI_PAD_SIZE32))

arch/powerpc/platforms/powernv/eeh-powernv.c+1−1

@@ -1478,7 +1478,7 @@ static int pnv_eeh_next_error(struct eeh_pe **pe) · 1477 unmodified lines
1478	}	1478	}
1479		1479
1480	/* Unmask the event */	1480	/* Unmask the event */
1481	if (eeh_enabled())	1481	if (ret == EEH_NEXT_ERR_NONE && eeh_enabled())
1482	enable_irq(eeh_event_irq);	1482	enable_irq(eeh_event_irq);
1483		1483
1484	return ret;	1484	return ret;

arch/powerpc/platforms/powernv/pci-ioda.c+6−5

 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
 		unsigned levels, unsigned long limit,
-		unsigned long *current_offset)
+		unsigned long *current_offset, unsigned long *total_allocated)
 {
 	struct page *tce_mem = NULL;
 	__be64 *addr, *tmp;
 	}
 	addr = page_address(tce_mem);
 	memset(addr, 0, allocated);
+	*total_allocated += allocated;
 	--levels;
 	if (!levels) {
 	for (i = 0; i < entries; ++i) {
 		tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
-				levels, limit, current_offset);
+				levels, limit, current_offset, total_allocated);
 		if (!tmp)
 			break;
 		struct iommu_table *tbl)
 {
 	void *addr;
-	unsigned long offset = 0, level_shift;
+	unsigned long offset = 0, level_shift, total_allocated = 0;
 	const unsigned window_shift = ilog2(window_size);
 	unsigned entries_shift = window_shift - page_shift;
 	unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
 	/* Allocate TCE table */
 	addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
-			levels, tce_table_size, &offset);
+			levels, tce_table_size, &offset, &total_allocated);
 	/* addr==NULL means that the first level allocation failed */
 	if (!addr)
 			page_shift);
 	tbl->it_level_size = 1ULL << (level_shift - 3);
 	tbl->it_indirect_levels = levels - 1;
-	tbl->it_allocated_size = offset;
+	tbl->it_allocated_size = total_allocated;
 	pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
 			window_size, tce_table_size, bus_offset);

arch/s390/kernel/asm-offsets.c+7−8

 int main(void)
 {
-	DEFINE(__THREAD_info, offsetof(struct task_struct, stack));
+	DEFINE(__TASK_thread_info, offsetof(struct task_struct, stack));
-	DEFINE(__THREAD_ksp, offsetof(struct task_struct, thread.ksp));
+	DEFINE(__TASK_thread, offsetof(struct task_struct, thread));
-	DEFINE(__THREAD_mm_segment, offsetof(struct task_struct, thread.mm_segment));
-	BLANK();
 	DEFINE(__TASK_pid, offsetof(struct task_struct, pid));
 	BLANK();
-	DEFINE(__THREAD_per_cause, offsetof(struct task_struct, thread.per_event.cause));
+	DEFINE(__THREAD_ksp, offsetof(struct thread_struct, ksp));
-	DEFINE(__THREAD_per_address, offsetof(struct task_struct, thread.per_event.address));
+	DEFINE(__THREAD_per_cause, offsetof(struct thread_struct, per_event.cause));
-	DEFINE(__THREAD_per_paid, offsetof(struct task_struct, thread.per_event.paid));
+	DEFINE(__THREAD_per_address, offsetof(struct thread_struct, per_event.address));
+	DEFINE(__THREAD_per_paid, offsetof(struct thread_struct, per_event.paid));
+	DEFINE(__THREAD_trap_tdb, offsetof(struct thread_struct, trap_tdb));
 	BLANK();
 	DEFINE(__TI_task, offsetof(struct thread_info, task));
 	DEFINE(__TI_flags, offsetof(struct thread_info, flags));
 	DEFINE(__LC_VDSO_PER_CPU, offsetof(struct _lowcore, vdso_per_cpu_data));
 	DEFINE(__LC_GMAP, offsetof(struct _lowcore, gmap));
 	DEFINE(__LC_PGM_TDB, offsetof(struct _lowcore, pgm_tdb));
-	DEFINE(__THREAD_trap_tdb, offsetof(struct task_struct, thread.trap_tdb));
 	DEFINE(__GMAP_ASCE, offsetof(struct gmap, asce));
 	DEFINE(__SIE_PROG0C, offsetof(struct kvm_s390_sie_block, prog0c));
 	DEFINE(__SIE_PROG20, offsetof(struct kvm_s390_sie_block, prog20));

arch/s390/kernel/cache.c+2−0

@@ -138,6 +138,8 @@ int init_cache_level(unsigned int cpu) · 137 unmodified lines
138	union cache_topology ct;	138	union cache_topology ct;
139	enum cache_type ctype;	139	enum cache_type ctype;
140		140
		141	if (!test_facility(34))
		142	return -EOPNOTSUPP;
141	if (!this_cpu_ci)	143	if (!this_cpu_ci)
142	return -EINVAL;	144	return -EINVAL;
143	ct.raw = ecag(EXTRACT_TOPOLOGY, 0, 0);	145	ct.raw = ecag(EXTRACT_TOPOLOGY, 0, 0);

arch/s390/kernel/entry.S+9−4

  */
 ENTRY(__switch_to)
 	stmg	%r6,%r15,__SF_GPRS(%r15)	# store gprs of prev task
-	stg	%r15,__THREAD_ksp(%r2)		# store kernel stack of prev
+	lgr	%r1,%r2
-	lg	%r4,__THREAD_info(%r2)		# get thread_info of prev
+	aghi	%r1,__TASK_thread		# thread_struct of prev task
-	lg	%r5,__THREAD_info(%r3)		# get thread_info of next
+	lg	%r4,__TASK_thread_info(%r2)	# get thread_info of prev
+	lg	%r5,__TASK_thread_info(%r3)	# get thread_info of next
+	stg	%r15,__THREAD_ksp(%r1)		# store kernel stack of prev
+	lgr	%r1,%r3
+	aghi	%r1,__TASK_thread		# thread_struct of next task
 	lgr	%r15,%r5
 	aghi	%r15,STACK_INIT			# end of kernel stack of next
 	stg	%r3,__LC_CURRENT		# store task struct of next
 	stg	%r5,__LC_THREAD_INFO		# store thread info of next
 	stg	%r15,__LC_KERNEL_STACK		# store end of kernel stack
+	lg	%r15,__THREAD_ksp(%r1)		# load kernel stack of next
 	lctl	%c4,%c4,__TASK_pid(%r3)		# load pid to control reg. 4
 	mvc	__LC_CURRENT_PID+4(4,%r0),__TASK_pid(%r3) # store pid of next
-	lg	%r15,__THREAD_ksp(%r3)		# load kernel stack of next
 	lmg	%r6,%r15,__SF_GPRS(%r15)	# load gprs of next task
 	br	%r14
 	LAST_BREAK %r14
 	lg	%r15,__LC_KERNEL_STACK
 	lg	%r14,__TI_task(%r12)
+	aghi	%r14,__TASK_thread	# pointer to thread_struct
 	lghi	%r13,__LC_PGM_TDB
 	tm	__LC_PGM_ILC+2,0x02	# check for transaction abort
 	jz	2f

arch/s390/kernel/traps.c+2−2

@@ -259,7 +259,7 @@ void vector_exception(struct pt_regs *regs) · 258 unmodified lines
259	}	259	}
260		260
261	/* get vector interrupt code from fpc */	261	/* get vector interrupt code from fpc */
262	asm volatile("stfpc %0" : "=m" (current->thread.fp_regs.fpc));	262	asm volatile("stfpc %0" : "=Q" (current->thread.fp_regs.fpc));
263	vic = (current->thread.fp_regs.fpc & 0xf00) >> 8;	263	vic = (current->thread.fp_regs.fpc & 0xf00) >> 8;
264	switch (vic) {	264	switch (vic) {
265	case 1: /* invalid vector operation */	265	case 1: /* invalid vector operation */
@@ -297,7 +297,7 @@ void data_exception(struct pt_regs *regs) · 31 unmodified lines
297		297
298	location = get_trap_ip(regs);	298	location = get_trap_ip(regs);
299		299
300	asm volatile("stfpc %0" : "=m" (current->thread.fp_regs.fpc));	300	asm volatile("stfpc %0" : "=Q" (current->thread.fp_regs.fpc));
301	/* Check for vector register enablement */	301	/* Check for vector register enablement */
302	if (MACHINE_HAS_VX && !current->thread.vxrs &&	302	if (MACHINE_HAS_VX && !current->thread.vxrs &&
303	(current->thread.fp_regs.fpc & FPC_DXC_MASK) == 0xfe00) {	303	(current->thread.fp_regs.fpc & FPC_DXC_MASK) == 0xfe00) {

arch/s390/kvm/kvm-s390.c+2−2

 static int kvm_s390_handle_requests(struct kvm_vcpu *vcpu)
 {
-	if (!vcpu->requests)
-		return 0;
 retry:
 	kvm_s390_vcpu_request_handled(vcpu);
+	if (!vcpu->requests)
+		return 0;
 	/*
 	 * We use MMU_RELOAD just to re-arm the ipte notifier for the
 	 * guest prefix page. gmap_ipte_notify will wait on the ptl lock.

arch/s390/net/bpf_jit_comp.c+7−7

@@ -448,13 +448,13 @@ static void bpf_jit_prologue(struct bpf_jit *jit) · 447 unmodified lines
448	EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA, REG_0,	448	EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA, REG_0,
449	BPF_REG_1, offsetof(struct sk_buff, data));	449	BPF_REG_1, offsetof(struct sk_buff, data));
450	}	450	}
451	/* BPF compatibility: clear A (%b7) and X (%b8) registers */	451	/* BPF compatibility: clear A (%b0) and X (%b7) registers */
452	if (REG_SEEN(BPF_REG_7))	452	if (REG_SEEN(BPF_REG_A))
453	/* lghi %b7,0 */	453	/* lghi %ba,0 */
454	EMIT4_IMM(0xa7090000, BPF_REG_7, 0);	454	EMIT4_IMM(0xa7090000, BPF_REG_A, 0);
455	if (REG_SEEN(BPF_REG_8))	455	if (REG_SEEN(BPF_REG_X))
456	/* lghi %b8,0 */	456	/* lghi %bx,0 */
457	EMIT4_IMM(0xa7090000, BPF_REG_8, 0);	457	EMIT4_IMM(0xa7090000, BPF_REG_X, 0);
458	}	458	}
459		459
460	/*	460	/*

arch/sparc/include/asm/visasm.h+5−11

@@ -28,16 +28,10 @@ · 27 unmodified lines
28	* Must preserve %o5 between VISEntryHalf and VISExitHalf */	28	* Must preserve %o5 between VISEntryHalf and VISExitHalf */
29		29
30	#define VISEntryHalf \	30	#define VISEntryHalf \
31	rd %fprs, %o5; \	31	VISEntry
32	andcc %o5, FPRS_FEF, %g0; \	32
33	be,pt %icc, 297f; \	33	#define VISExitHalf \
34	sethi %hi(298f), %g7; \	34	VISExit
35	sethi %hi(VISenterhalf), %g1; \
36	jmpl %g1 + %lo(VISenterhalf), %g0; \
37	or %g7, %lo(298f), %g7; \
38	clr %o5; \
39	297: wr %o5, FPRS_FEF, %fprs; \
40	298:
41		35
42	#define VISEntryHalfFast(fail_label) \	36	#define VISEntryHalfFast(fail_label) \
43	rd %fprs, %o5; \	37	rd %fprs, %o5; \
@@ -47,7 +41,7 @@ · 3 unmodified lines
47	ba,a,pt %xcc, fail_label; \	41	ba,a,pt %xcc, fail_label; \
48	297: wr %o5, FPRS_FEF, %fprs;	42	297: wr %o5, FPRS_FEF, %fprs;
49		43
50	#define VISExitHalf \	44	#define VISExitHalfFast \
51	wr %o5, 0, %fprs;	45	wr %o5, 0, %fprs;
52		46
53	#ifndef __ASSEMBLY__	47	#ifndef __ASSEMBLY__

arch/sparc/lib/NG4memcpy.S+4−1

@@ -240,8 +240,11 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ · 239 unmodified lines
240	add %o0, 0x40, %o0	240	add %o0, 0x40, %o0
241	bne,pt %icc, 1b	241	bne,pt %icc, 1b
242	LOAD(prefetch, %g1 + 0x200, #n_reads_strong)	242	LOAD(prefetch, %g1 + 0x200, #n_reads_strong)
		243	#ifdef NON_USER_COPY
		244	VISExitHalfFast
		245	#else
243	VISExitHalf	246	VISExitHalf
244		247	#endif
245	brz,pn %o2, .Lexit	248	brz,pn %o2, .Lexit
246	cmp %o2, 19	249	cmp %o2, 19
247	ble,pn %icc, .Lsmall_unaligned	250	ble,pn %icc, .Lsmall_unaligned

arch/sparc/lib/VISsave.S+2−65

@@ -44,9 +44,8 @@ vis1: ldub [%g6 + TI_FPSAVED], %g3 · 43 unmodified lines
44		44
45	stx %g3, [%g6 + TI_GSR]	45	stx %g3, [%g6 + TI_GSR]
46	2: add %g6, %g1, %g3	46	2: add %g6, %g1, %g3
47	cmp %o5, FPRS_DU	47	mov FPRS_DU \| FPRS_DL \| FPRS_FEF, %o5
48	be,pn %icc, 6f	48	sll %g1, 3, %g1
49	sll %g1, 3, %g1
50	stb %o5, [%g3 + TI_FPSAVED]	49	stb %o5, [%g3 + TI_FPSAVED]
51	rd %gsr, %g2	50	rd %gsr, %g2
52	add %g6, %g1, %g3	51	add %g6, %g1, %g3
@@ -80,65 +79,3 @@ vis1: ldub [%g6 + TI_FPSAVED], %g3 · 27 unmodified lines
80	.align 32	79	.align 32
81	80: jmpl %g7 + %g0, %g0	80	80: jmpl %g7 + %g0, %g0
82	nop	81	nop
83
84	6: ldub [%g3 + TI_FPSAVED], %o5
85	or %o5, FPRS_DU, %o5
86	add %g6, TI_FPREGS+0x80, %g2
87	stb %o5, [%g3 + TI_FPSAVED]
88
89	sll %g1, 5, %g1
90	add %g6, TI_FPREGS+0xc0, %g3
91	wr %g0, FPRS_FEF, %fprs
92	membar #Sync
93	stda %f32, [%g2 + %g1] ASI_BLK_P
94	stda %f48, [%g3 + %g1] ASI_BLK_P
95	membar #Sync
96	ba,pt %xcc, 80f
97	nop
98
99	.align 32
100	80: jmpl %g7 + %g0, %g0
101	nop
102
103	.align 32
104	VISenterhalf:
105	ldub [%g6 + TI_FPDEPTH], %g1
106	brnz,a,pn %g1, 1f
107	cmp %g1, 1
108	stb %g0, [%g6 + TI_FPSAVED]
109	stx %fsr, [%g6 + TI_XFSR]
110	clr %o5
111	jmpl %g7 + %g0, %g0
112	wr %g0, FPRS_FEF, %fprs
113
114	1: bne,pn %icc, 2f
115	srl %g1, 1, %g1
116	ba,pt %xcc, vis1
117	sub %g7, 8, %g7
118	2: addcc %g6, %g1, %g3
119	sll %g1, 3, %g1
120	andn %o5, FPRS_DU, %g2
121	stb %g2, [%g3 + TI_FPSAVED]
122
123	rd %gsr, %g2
124	add %g6, %g1, %g3
125	stx %g2, [%g3 + TI_GSR]
126	add %g6, %g1, %g2
127	stx %fsr, [%g2 + TI_XFSR]
128	sll %g1, 5, %g1
129	3: andcc %o5, FPRS_DL, %g0
130	be,pn %icc, 4f
131	add %g6, TI_FPREGS, %g2
132
133	add %g6, TI_FPREGS+0x40, %g3
134	membar #Sync
135	stda %f0, [%g2 + %g1] ASI_BLK_P
136	stda %f16, [%g3 + %g1] ASI_BLK_P
137	membar #Sync
138	ba,pt %xcc, 4f
139	nop
140
141	.align 32
142	4: and %o5, FPRS_DU, %o5
143	jmpl %g7 + %g0, %g0
144	wr %o5, FPRS_FEF, %fprs

arch/sparc/lib/ksyms.c+0−4

 void VISenter(void);
 EXPORT_SYMBOL(VISenter);
-/* CRYPTO code needs this */
-void VISenterhalf(void);
-EXPORT_SYMBOL(VISenterhalf);
 extern void xor_vis_2(unsigned long, unsigned long *, unsigned long *);
 extern void xor_vis_3(unsigned long, unsigned long *, unsigned long *,
 		unsigned long *);

arch/tile/kernel/compat_signal.c+0−2

@@ -113,8 +113,6 @@ int copy_siginfo_from_user32(siginfo_t to, struct compat_siginfo __user from) · 112 unmodified lines
113	if (!access_ok(VERIFY_READ, from, sizeof(struct compat_siginfo)))	113	if (!access_ok(VERIFY_READ, from, sizeof(struct compat_siginfo)))
114	return -EFAULT;	114	return -EFAULT;
115		115
116	memset(to, 0, sizeof(*to));
117
118	err = __get_user(to->si_signo, &from->si_signo);	116	err = __get_user(to->si_signo, &from->si_signo);
119	err \|= __get_user(to->si_errno, &from->si_errno);	117	err \|= __get_user(to->si_errno, &from->si_errno);
120	err \|= __get_user(to->si_code, &from->si_code);	118	err \|= __get_user(to->si_code, &from->si_code);

arch/tile/kernel/setup.c+1−1

@@ -1139,7 +1139,7 @@ static void __init load_hv_initrd(void) · 1138 unmodified lines
1139		1139
1140	void __init free_initrd_mem(unsigned long begin, unsigned long end)	1140	void __init free_initrd_mem(unsigned long begin, unsigned long end)
1141	{	1141	{
1142	free_bootmem(__pa(begin), end - begin);	1142	free_bootmem_late(__pa(begin), end - begin);
1143	}	1143	}
1144		1144
1145	static int __init setup_initrd(char *str)	1145	static int __init setup_initrd(char *str)

arch/x86/boot/compressed/eboot.c+4−0

 		unsigned int e820_type = 0;
 		unsigned long m = efi->efi_memmap;
+#ifdef CONFIG_X86_64
+		m |= (u64)efi->efi_memmap_hi << 32;
+#endif
 		d = (efi_memory_desc_t *)(m + (i * efi->efi_memdesc_size));
 		switch (d->type) {
 		case EFI_RESERVED_TYPE:

arch/x86/entry/entry_64_compat.S+11−6

 	 */
 	andl	$~TS_COMPAT, ASM_THREAD_INFO(TI_status, %rsp, SIZEOF_PTREGS)
 	movl	RIP(%rsp), %ecx		/* User %eip */
+	movq    RAX(%rsp), %rax
 	RESTORE_RSI_RDI
 	xorl	%edx, %edx		/* Do not leak kernel information */
 	xorq	%r8, %r8
 	movl	RDX(%rsp), %edx		/* arg3 */
 	movl	RSI(%rsp), %ecx		/* arg4 */
 	movl	RDI(%rsp), %r8d		/* arg5 */
-	movl	%ebp, %r9d		/* arg6 */
 	.endm
 	.macro auditsys_exit exit
 1:	setbe	%al			/* 1 if error, 0 if not */
 	movzbl	%al, %edi		/* zero-extend that into %edi */
 	call	__audit_syscall_exit
-	movq	RAX(%rsp), %rax		/* reload syscall return value */
 	movl	$(_TIF_ALLWORK_MASK & ~_TIF_SYSCALL_AUDIT), %edi
 	DISABLE_INTERRUPTS(CLBR_NONE)
 	TRACE_IRQS_OFF
 sysenter_auditsys:
 	auditsys_entry_common
+	movl	%ebp, %r9d		/* reload 6th syscall arg */
 	jmp	sysenter_dispatch
 sysexit_audit:
 	 * 32-bit zero extended:
 	 */
 	ASM_STAC
-1:	movl	(%r8), %ebp
+1:	movl	(%r8), %r9d
 	_ASM_EXTABLE(1b, ia32_badarg)
 	ASM_CLAC
 	orl	$TS_COMPAT, ASM_THREAD_INFO(TI_status, %rsp, SIZEOF_PTREGS)
 cstar_do_call:
 	/* 32-bit syscall -> 64-bit C ABI argument conversion */
 	movl	%edi, %r8d		/* arg5 */
-	movl	%ebp, %r9d		/* arg6 */
+	/* r9 already loaded */		/* arg6 */
 	xchg	%ecx, %esi		/* rsi:arg2, rcx:arg4 */
 	movl	%ebx, %edi		/* arg1 */
 	movl	%edx, %edx		/* arg3 (zero extension) */
 	call	*ia32_sys_call_table(, %rax, 8)
 	movq	%rax, RAX(%rsp)
 1:
-	movl	RCX(%rsp), %ebp
 	DISABLE_INTERRUPTS(CLBR_NONE)
 	TRACE_IRQS_OFF
 	testl	$_TIF_ALLWORK_MASK, ASM_THREAD_INFO(TI_flags, %rsp, SIZEOF_PTREGS)
 	RESTORE_RSI_RDI_RDX
 	movl	RIP(%rsp), %ecx
 	movl	EFLAGS(%rsp), %r11d
+	movq    RAX(%rsp), %rax
 	xorq	%r10, %r10
 	xorq	%r9, %r9
 	xorq	%r8, %r8
 #ifdef CONFIG_AUDITSYSCALL
 cstar_auditsys:
+	movl	%r9d, R9(%rsp)		/* register to be clobbered by call */
 	auditsys_entry_common
+	movl	R9(%rsp), %r9d		/* reload 6th syscall arg */
 	jmp	cstar_dispatch
 sysretl_audit:
 	testl	$(_TIF_WORK_SYSCALL_ENTRY & ~_TIF_SYSCALL_AUDIT), ASM_THREAD_INFO(TI_flags, %rsp, SIZEOF_PTREGS)
 	jz	cstar_auditsys
 #endif
+	xchgl	%r9d, %ebp
 	SAVE_EXTRA_REGS
 	xorl	%eax, %eax		/* Do not leak kernel information */
 	movq	%rax, R11(%rsp)
 	movq	%rax, R10(%rsp)
-	movq	%rax, R9(%rsp)
+	movq	%r9, R9(%rsp)
 	movq	%rax, R8(%rsp)
 	movq	%rsp, %rdi		/* &pt_regs -> arg1 */
 	call	syscall_trace_enter
+	movl	R9(%rsp), %r9d
 	/* Reload arg registers from stack. (see sysenter_tracesys) */
 	movl	RCX(%rsp), %ecx
 	movl	%eax, %eax		/* zero extension */
 	RESTORE_EXTRA_REGS
+	xchgl	%ebp, %r9d
 	jmp	cstar_do_call
 END(entry_SYSCALL_compat)

arch/x86/include/asm/desc.h+0−15

@@ -280,21 +280,6 @@ static inline void clear_LDT(void) · 279 unmodified lines
280	set_ldt(NULL, 0);	280	set_ldt(NULL, 0);
281	}	281	}
282		282
283	/*
284	* load one particular LDT into the current CPU
285	*/
286	static inline void load_LDT_nolock(mm_context_t *pc)
287	{
288	set_ldt(pc->ldt, pc->size);
289	}
290
291	static inline void load_LDT(mm_context_t *pc)
292	{
293	preempt_disable();
294	load_LDT_nolock(pc);
295	preempt_enable();
296	}
297
298	static inline unsigned long get_desc_base(const struct desc_struct *desc)	283	static inline unsigned long get_desc_base(const struct desc_struct *desc)
299	{	284	{
300	return (unsigned)(desc->base0 \| ((desc->base1) << 16) \| ((desc->base2) << 24));	285	return (unsigned)(desc->base0 \| ((desc->base1) << 16) \| ((desc->base2) << 24));

arch/x86/include/asm/mmu.h+1−2

@@ -9,8 +9,7 @@ · 8 unmodified lines
9	* we put the segment information here.	9	* we put the segment information here.
10	*/	10	*/
11	typedef struct {	11	typedef struct {
12	void *ldt;	12	struct ldt_struct *ldt;
13	int size;
14		13
15	#ifdef CONFIG_X86_64	14	#ifdef CONFIG_X86_64
16	/* True if mm supports a task running in 32 bit compatibility mode. */	15	/* True if mm supports a task running in 32 bit compatibility mode. */

arch/x86/include/asm/mmu_context.h+49−5

@@ -33,6 +33,50 @@ static inline void load_mm_cr4(struct mm_struct *mm) · 32 unmodified lines
33	static inline void load_mm_cr4(struct mm_struct *mm) {}	33	static inline void load_mm_cr4(struct mm_struct *mm) {}
34	#endif	34	#endif
35		35
		36	/*
		37	* ldt_structs can be allocated, used, and freed, but they are never
		38	* modified while live.
		39	*/
		40	struct ldt_struct {
		41	/*
		42	* Xen requires page-aligned LDTs with special permissions. This is
		43	* needed to prevent us from installing evil descriptors such as
		44	* call gates. On native, we could merge the ldt_struct and LDT
		45	* allocations, but it's not worth trying to optimize.
		46	*/
		47	struct desc_struct *entries;
		48	int size;
		49	};
		50
		51	static inline void load_mm_ldt(struct mm_struct *mm)
		52	{
		53	struct ldt_struct *ldt;
		54
		55	/* lockless_dereference synchronizes with smp_store_release */
		56	ldt = lockless_dereference(mm->context.ldt);
		57
		58	/*
		59	* Any change to mm->context.ldt is followed by an IPI to all
		60	* CPUs with the mm active. The LDT will not be freed until
		61	* after the IPI is handled by all such CPUs. This means that,
		62	* if the ldt_struct changes before we return, the values we see
		63	* will be safe, and the new values will be loaded before we run
		64	* any user code.
		65	*
		66	* NB: don't try to convert this to use RCU without extreme care.
		67	* We would still need IRQs off, because we don't want to change
		68	* the local LDT after an IPI loaded a newer value than the one
		69	* that we can see.
		70	*/
		71
		72	if (unlikely(ldt))
		73	set_ldt(ldt->entries, ldt->size);
		74	else
		75	clear_LDT();
		76
		77	DEBUG_LOCKS_WARN_ON(preemptible());
		78	}
		79
36	/*	80	/*
37	* Used for LDT copy/destruction.	81	* Used for LDT copy/destruction.
38	*/	82	*/
@@ -78,12 +122,12 @@ static inline void switch_mm(struct mm_struct prev, struct mm_struct next, · 39 unmodified lines
78	* was called and then modify_ldt changed	122	* was called and then modify_ldt changed
79	* prev->context.ldt but suppressed an IPI to this CPU.	123	* prev->context.ldt but suppressed an IPI to this CPU.
80	* In this case, prev->context.ldt != NULL, because we	124	* In this case, prev->context.ldt != NULL, because we
81	* never free an LDT while the mm still exists. That	125	* never set context.ldt to NULL while the mm still
82	* means that next->context.ldt != prev->context.ldt,	126	* exists. That means that next->context.ldt !=
83	* because mms never share an LDT.	127	* prev->context.ldt, because mms never share an LDT.
84	*/	128	*/
85	if (unlikely(prev->context.ldt != next->context.ldt))	129	if (unlikely(prev->context.ldt != next->context.ldt))
86	load_LDT_nolock(&next->context);	130	load_mm_ldt(next);
87	}	131	}
88	#ifdef CONFIG_SMP	132	#ifdef CONFIG_SMP
89	else {	133	else {
@@ -106,7 +150,7 @@ static inline void switch_mm(struct mm_struct prev, struct mm_struct next, · 16 unmodified lines
106	load_cr3(next->pgd);	150	load_cr3(next->pgd);
107	trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);	151	trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
108	load_mm_cr4(next);	152	load_mm_cr4(next);
109	load_LDT_nolock(&next->context);	153	load_mm_ldt(next);
110	}	154	}
111	}	155	}
112	#endif	156	#endif

arch/x86/include/asm/sigcontext.h+3−3

@@ -57,9 +57,9 @@ struct sigcontext { · 56 unmodified lines
57	unsigned long ip;	57	unsigned long ip;
58	unsigned long flags;	58	unsigned long flags;
59	unsigned short cs;	59	unsigned short cs;
60	unsigned short __pad2; /* Was called gs, but was always zero. */	60	unsigned short gs;
61	unsigned short __pad1; /* Was called fs, but was always zero. */	61	unsigned short fs;
62	unsigned short ss;	62	unsigned short __pad0;
63	unsigned long err;	63	unsigned long err;
64	unsigned long trapno;	64	unsigned long trapno;
65	unsigned long oldmask;	65	unsigned long oldmask;

arch/x86/include/uapi/asm/kvm.h+2−2

@@ -354,7 +354,7 @@ struct kvm_xcrs { · 353 unmodified lines
354	struct kvm_sync_regs {	354	struct kvm_sync_regs {
355	};	355	};
356		356
357	#define KVM_QUIRK_LINT0_REENABLED (1 << 0)	357	#define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0)
358	#define KVM_QUIRK_CD_NW_CLEARED (1 << 1)	358	#define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1)
359		359
360	#endif /* _ASM_X86_KVM_H */	360	#endif /* _ASM_X86_KVM_H */

arch/x86/include/uapi/asm/sigcontext.h+3−18

@@ -177,24 +177,9 @@ struct sigcontext { · 176 unmodified lines
177	__u64 rip;	177	__u64 rip;
178	__u64 eflags; /* RFLAGS */	178	__u64 eflags; /* RFLAGS */
179	__u16 cs;	179	__u16 cs;
180		180	__u16 gs;
181	/*	181	__u16 fs;
182	* Prior to 2.5.64 ("[PATCH] x86-64 updates for 2.5.64-bk3"),	182	__u16 __pad0;
183	* Linux saved and restored fs and gs in these slots. This
184	* was counterproductive, as fsbase and gsbase were never
185	* saved, so arch_prctl was presumably unreliable.
186	*
187	* If these slots are ever needed for any other purpose, there
188	* is some risk that very old 64-bit binaries could get
189	* confused. I doubt that many such binaries still work,
190	* though, since the same patch in 2.5.64 also removed the
191	* 64-bit set_thread_area syscall, so it appears that there is
192	* no TLS API that works in both pre- and post-2.5.64 kernels.
193	*/
194	__u16 __pad2; /* Was gs. */
195	__u16 __pad1; /* Was fs. */
196
197	__u16 ss;
198	__u64 err;	183	__u64 err;
199	__u64 trapno;	184	__u64 trapno;
200	__u64 oldmask;	185	__u64 oldmask;

arch/x86/kernel/apic/io_apic.c+1−1

@@ -943,7 +943,7 @@ static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info) · 942 unmodified lines
943	*/	943	*/
944	if (irq < nr_legacy_irqs() && data->count == 1) {	944	if (irq < nr_legacy_irqs() && data->count == 1) {
945	if (info->ioapic_trigger != data->trigger)	945	if (info->ioapic_trigger != data->trigger)
946	mp_register_handler(irq, data->trigger);	946	mp_register_handler(irq, info->ioapic_trigger);
947	data->entry.trigger = data->trigger = info->ioapic_trigger;	947	data->entry.trigger = data->trigger = info->ioapic_trigger;
948	data->entry.polarity = data->polarity = info->ioapic_polarity;	948	data->entry.polarity = data->polarity = info->ioapic_polarity;
949	}	949	}

arch/x86/kernel/cpu/common.c+2−2

@@ -1410,7 +1410,7 @@ void cpu_init(void) · 1409 unmodified lines
1410	load_sp0(t, &current->thread);	1410	load_sp0(t, &current->thread);
1411	set_tss_desc(cpu, t);	1411	set_tss_desc(cpu, t);
1412	load_TR_desc();	1412	load_TR_desc();
1413	load_LDT(&init_mm.context);	1413	load_mm_ldt(&init_mm);
1414		1414
1415	clear_all_debug_regs();	1415	clear_all_debug_regs();
1416	dbg_restore_debug_regs();	1416	dbg_restore_debug_regs();
@@ -1459,7 +1459,7 @@ void cpu_init(void) · 42 unmodified lines
1459	load_sp0(t, thread);	1459	load_sp0(t, thread);
1460	set_tss_desc(cpu, t);	1460	set_tss_desc(cpu, t);
1461	load_TR_desc();	1461	load_TR_desc();
1462	load_LDT(&init_mm.context);	1462	load_mm_ldt(&init_mm);
1463		1463
1464	t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);	1464	t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1465		1465

arch/x86/kernel/cpu/perf_event.c+8−4

 	int idx = segment >> 3;
 	if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
+		struct ldt_struct *ldt;
 		if (idx > LDT_ENTRIES)
 			return 0;
-		if (idx > current->active_mm->context.size)
+		/* IRQs are off, so this synchronizes with smp_store_release */
+		ldt = lockless_dereference(current->active_mm->context.ldt);
+		if (!ldt || idx > ldt->size)
 			return 0;
-		desc = current->active_mm->context.ldt;
+		desc = &ldt->entries[idx];
 	} else {
 		if (idx > GDT_ENTRIES)
 			return 0;
-		desc = raw_cpu_ptr(gdt_page.gdt);
+		desc = raw_cpu_ptr(gdt_page.gdt) + idx;
 	}
-	return get_desc_base(desc + idx);
+	return get_desc_base(desc);
 }
 #ifdef CONFIG_COMPAT

arch/x86/kernel/cpu/perf_event_intel.c+16−7

@@ -2534,7 +2534,7 @@ static int intel_pmu_cpu_prepare(int cpu) · 2533 unmodified lines
2534	if (x86_pmu.extra_regs \|\| x86_pmu.lbr_sel_map) {	2534	if (x86_pmu.extra_regs \|\| x86_pmu.lbr_sel_map) {
2535	cpuc->shared_regs = allocate_shared_regs(cpu);	2535	cpuc->shared_regs = allocate_shared_regs(cpu);
2536	if (!cpuc->shared_regs)	2536	if (!cpuc->shared_regs)
2537	return NOTIFY_BAD;	2537	goto err;
2538	}	2538	}
2539		2539
2540	if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {	2540	if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
@@ -2542,18 +2542,27 @@ static int intel_pmu_cpu_prepare(int cpu) · 1 unmodified line
2542		2542
2543	cpuc->constraint_list = kzalloc(sz, GFP_KERNEL);	2543	cpuc->constraint_list = kzalloc(sz, GFP_KERNEL);
2544	if (!cpuc->constraint_list)	2544	if (!cpuc->constraint_list)
2545	return NOTIFY_BAD;	2545	goto err_shared_regs;
2546		2546
2547	cpuc->excl_cntrs = allocate_excl_cntrs(cpu);	2547	cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
2548	if (!cpuc->excl_cntrs) {	2548	if (!cpuc->excl_cntrs)
2549	kfree(cpuc->constraint_list);	2549	goto err_constraint_list;
2550	kfree(cpuc->shared_regs);	2550
2551	return NOTIFY_BAD;
2552	}
2553	cpuc->excl_thread_id = 0;	2551	cpuc->excl_thread_id = 0;
2554	}	2552	}
2555		2553
2556	return NOTIFY_OK;	2554	return NOTIFY_OK;
		2555
		2556	err_constraint_list:
		2557	kfree(cpuc->constraint_list);
		2558	cpuc->constraint_list = NULL;
		2559
		2560	err_shared_regs:
		2561	kfree(cpuc->shared_regs);
		2562	cpuc->shared_regs = NULL;
		2563
		2564	err:
		2565	return NOTIFY_BAD;
2557	}	2566	}
2558		2567
2559	static void intel_pmu_cpu_starting(int cpu)	2568	static void intel_pmu_cpu_starting(int cpu)

arch/x86/kernel/cpu/perf_event_intel_cqm.c+11−5

 	if (!cqm_group_leader(event))
 		return 0;
+	/*
+	 * Getting up-to-date values requires an SMP IPI which is not
+	 * possible if we're being called in interrupt context. Return
+	 * the cached values instead.
+	 */
+	if (unlikely(in_interrupt()))
+		goto out;
 	/*
 	 * Notice that we don't perform the reading of an RMID
 	 * atomically, because we can't hold a spin lock across the
 	cpumask_set_cpu(cpu, &cqm_cpumask);
 }
-static void intel_cqm_cpu_prepare(unsigned int cpu)
+static void intel_cqm_cpu_starting(unsigned int cpu)
 {
 	struct intel_pqr_state *state = &per_cpu(pqr_state, cpu);
 	struct cpuinfo_x86 *c = &cpu_data(cpu);
 	unsigned int cpu  = (unsigned long)hcpu;
 	switch (action & ~CPU_TASKS_FROZEN) {
-	case CPU_UP_PREPARE:
-		intel_cqm_cpu_prepare(cpu);
-		break;
 	case CPU_DOWN_PREPARE:
 		intel_cqm_cpu_exit(cpu);
 		break;
 	case CPU_STARTING:
+		intel_cqm_cpu_starting(cpu);
 		cqm_pick_event_reader(cpu);
 		break;
 	}
 		goto out;
 	for_each_online_cpu(i) {
-		intel_cqm_cpu_prepare(i);
+		intel_cqm_cpu_starting(i);
 		cqm_pick_event_reader(i);
 	}

arch/x86/kernel/fpu/init.c+6−0

 	setup_clear_cpu_cap(X86_FEATURE_XSAVE);
 	setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
+	setup_clear_cpu_cap(X86_FEATURE_XSAVEC);
 	setup_clear_cpu_cap(X86_FEATURE_XSAVES);
 	setup_clear_cpu_cap(X86_FEATURE_AVX);
 	setup_clear_cpu_cap(X86_FEATURE_AVX2);
+	setup_clear_cpu_cap(X86_FEATURE_AVX512F);
+	setup_clear_cpu_cap(X86_FEATURE_AVX512PF);
+	setup_clear_cpu_cap(X86_FEATURE_AVX512ER);
+	setup_clear_cpu_cap(X86_FEATURE_AVX512CD);
+	setup_clear_cpu_cap(X86_FEATURE_MPX);
 	return 1;
 }

arch/x86/kernel/ldt.c+142−120

@@ -12,6 +12,7 @@ · 11 unmodified lines
12	#include <linux/string.h>	12	#include <linux/string.h>
13	#include <linux/mm.h>	13	#include <linux/mm.h>
14	#include <linux/smp.h>	14	#include <linux/smp.h>
		15	#include <linux/slab.h>
15	#include <linux/vmalloc.h>	16	#include <linux/vmalloc.h>
16	#include <linux/uaccess.h>	17	#include <linux/uaccess.h>
17		18
@@ -20,82 +21,82 @@ · 2 unmodified lines
20	#include <asm/mmu_context.h>	21	#include <asm/mmu_context.h>
21	#include <asm/syscalls.h>	22	#include <asm/syscalls.h>
22		23
23	#ifdef CONFIG_SMP	24	/* context.lock is held for us, so we don't need any locking. */
24	static void flush_ldt(void *current_mm)	25	static void flush_ldt(void *current_mm)
25	{	26	{
26	if (current->active_mm == current_mm)	27	mm_context_t *pc;
27	load_LDT(&current->active_mm->context);	28
		29	if (current->active_mm != current_mm)
		30	return;
		31
		32	pc = &current->active_mm->context;
		33	set_ldt(pc->ldt->entries, pc->ldt->size);
28	}	34	}
29	#endif
30		35
31	static int alloc_ldt(mm_context_t *pc, int mincount, int reload)	36	/* The caller must call finalize_ldt_struct on the result. LDT starts zeroed. */
		37	static struct ldt_struct *alloc_ldt_struct(int size)
32	{	38	{
33	void oldldt, newldt;	39	struct ldt_struct *new_ldt;
34	int oldsize;	40	int alloc_size;
35		41
36	if (mincount <= pc->size)	42	if (size > LDT_ENTRIES)
37	return 0;	43	return NULL;
38	oldsize = pc->size;	44
39	mincount = (mincount + (PAGE_SIZE / LDT_ENTRY_SIZE - 1)) &	45	new_ldt = kmalloc(sizeof(struct ldt_struct), GFP_KERNEL);
40	(~(PAGE_SIZE / LDT_ENTRY_SIZE - 1));	46	if (!new_ldt)
41	if (mincount * LDT_ENTRY_SIZE > PAGE_SIZE)	47	return NULL;
42	newldt = vmalloc(mincount * LDT_ENTRY_SIZE);	48
		49	BUILD_BUG_ON(LDT_ENTRY_SIZE != sizeof(struct desc_struct));
		50	alloc_size = size * LDT_ENTRY_SIZE;
		51
		52	/*
		53	* Xen is very picky: it requires a page-aligned LDT that has no
		54	* trailing nonzero bytes in any page that contains LDT descriptors.
		55	* Keep it simple: zero the whole allocation and never allocate less
		56	* than PAGE_SIZE.
		57	*/
		58	if (alloc_size > PAGE_SIZE)
		59	new_ldt->entries = vzalloc(alloc_size);
43	else	60	else
44	newldt = (void *)__get_free_page(GFP_KERNEL);	61	new_ldt->entries = kzalloc(PAGE_SIZE, GFP_KERNEL);
45
46	if (!newldt)
47	return -ENOMEM;
48		62
49	if (oldsize)	63	if (!new_ldt->entries) {
50	memcpy(newldt, pc->ldt, oldsize * LDT_ENTRY_SIZE);	64	kfree(new_ldt);
51	oldldt = pc->ldt;	65	return NULL;
52	memset(newldt + oldsize * LDT_ENTRY_SIZE, 0,	66	}
53	(mincount - oldsize) * LDT_ENTRY_SIZE);
54		67
55	paravirt_alloc_ldt(newldt, mincount);	68	new_ldt->size = size;
		69	return new_ldt;
		70	}
56		71
57	#ifdef CONFIG_X86_64	72	/* After calling this, the LDT is immutable. */
58	/* CHECKME: Do we really need this ? */	73	static void finalize_ldt_struct(struct ldt_struct *ldt)
59	wmb();	74	{
60	#endif	75	paravirt_alloc_ldt(ldt->entries, ldt->size);
61	pc->ldt = newldt;
62	wmb();
63	pc->size = mincount;
64	wmb();
65
66	if (reload) {
67	#ifdef CONFIG_SMP
68	preempt_disable();
69	load_LDT(pc);
70	if (!cpumask_equal(mm_cpumask(current->mm),
71	cpumask_of(smp_processor_id())))
72	smp_call_function(flush_ldt, current->mm, 1);
73	preempt_enable();
74	#else
75	load_LDT(pc);
76	#endif
77	}
78	if (oldsize) {
79	paravirt_free_ldt(oldldt, oldsize);
80	if (oldsize * LDT_ENTRY_SIZE > PAGE_SIZE)
81	vfree(oldldt);
82	else
83	put_page(virt_to_page(oldldt));
84	}
85	return 0;
86	}	76	}
87		77
88	static inline int copy_ldt(mm_context_t new, mm_context_t old)	78	/* context.lock is held */
		79	static void install_ldt(struct mm_struct *current_mm,
		80	struct ldt_struct *ldt)
89	{	81	{
90	int err = alloc_ldt(new, old->size, 0);	82	/* Synchronizes with lockless_dereference in load_mm_ldt. */
91	int i;	83	smp_store_release(&current_mm->context.ldt, ldt);
		84
		85	/* Activate the LDT for all CPUs using current_mm. */
		86	on_each_cpu_mask(mm_cpumask(current_mm), flush_ldt, current_mm, true);
		87	}
92		88
93	if (err < 0)	89	static void free_ldt_struct(struct ldt_struct *ldt)
94	return err;	90	{
		91	if (likely(!ldt))
		92	return;
95		93
96	for (i = 0; i < old->size; i++)	94	paravirt_free_ldt(ldt->entries, ldt->size);
97	write_ldt_entry(new->ldt, i, old->ldt + i * LDT_ENTRY_SIZE);	95	if (ldt->size * LDT_ENTRY_SIZE > PAGE_SIZE)
98	return 0;	96	vfree(ldt->entries);
		97	else
		98	kfree(ldt->entries);
		99	kfree(ldt);
99	}	100	}
100		101
101	/*	102	/*
@@ -104,17 +105,37 @@ static inline int copy_ldt(mm_context_t new, mm_context_t old) · 2 unmodified lines
104	*/	105	*/
105	int init_new_context(struct task_struct tsk, struct mm_struct mm)	106	int init_new_context(struct task_struct tsk, struct mm_struct mm)
106	{	107	{
		108	struct ldt_struct *new_ldt;
107	struct mm_struct *old_mm;	109	struct mm_struct *old_mm;
108	int retval = 0;	110	int retval = 0;
109		111
110	mutex_init(&mm->context.lock);	112	mutex_init(&mm->context.lock);
111	mm->context.size = 0;
112	old_mm = current->mm;	113	old_mm = current->mm;
113	if (old_mm && old_mm->context.size > 0) {	114	if (!old_mm) {
114	mutex_lock(&old_mm->context.lock);	115	mm->context.ldt = NULL;
115	retval = copy_ldt(&mm->context, &old_mm->context);	116	return 0;
116	mutex_unlock(&old_mm->context.lock);
117	}	117	}
		118
		119	mutex_lock(&old_mm->context.lock);
		120	if (!old_mm->context.ldt) {
		121	mm->context.ldt = NULL;
		122	goto out_unlock;
		123	}
		124
		125	new_ldt = alloc_ldt_struct(old_mm->context.ldt->size);
		126	if (!new_ldt) {
		127	retval = -ENOMEM;
		128	goto out_unlock;
		129	}
		130
		131	memcpy(new_ldt->entries, old_mm->context.ldt->entries,
		132	new_ldt->size * LDT_ENTRY_SIZE);
		133	finalize_ldt_struct(new_ldt);
		134
		135	mm->context.ldt = new_ldt;
		136
		137	out_unlock:
		138	mutex_unlock(&old_mm->context.lock);
118	return retval;	139	return retval;
119	}	140	}
120		141
@@ -125,53 +146,47 @@ int init_new_context(struct task_struct tsk, struct mm_struct mm) · 4 unmodified lines
125	*/	146	*/
126	void destroy_context(struct mm_struct *mm)	147	void destroy_context(struct mm_struct *mm)
127	{	148	{
128	if (mm->context.size) {	149	free_ldt_struct(mm->context.ldt);
129	#ifdef CONFIG_X86_32	150	mm->context.ldt = NULL;
130	/* CHECKME: Can this ever happen ? */
131	if (mm == current->active_mm)
132	clear_LDT();
133	#endif
134	paravirt_free_ldt(mm->context.ldt, mm->context.size);
135	if (mm->context.size * LDT_ENTRY_SIZE > PAGE_SIZE)
136	vfree(mm->context.ldt);
137	else
138	put_page(virt_to_page(mm->context.ldt));
139	mm->context.size = 0;
140	}
141	}	151	}
142		152
143	static int read_ldt(void __user *ptr, unsigned long bytecount)	153	static int read_ldt(void __user *ptr, unsigned long bytecount)
144	{	154	{
145	int err;	155	int retval;
146	unsigned long size;	156	unsigned long size;
147	struct mm_struct *mm = current->mm;	157	struct mm_struct *mm = current->mm;
148		158
149	if (!mm->context.size)	159	mutex_lock(&mm->context.lock);
150	return 0;	160
		161	if (!mm->context.ldt) {
		162	retval = 0;
		163	goto out_unlock;
		164	}
		165
151	if (bytecount > LDT_ENTRY_SIZE * LDT_ENTRIES)	166	if (bytecount > LDT_ENTRY_SIZE * LDT_ENTRIES)
152	bytecount = LDT_ENTRY_SIZE * LDT_ENTRIES;	167	bytecount = LDT_ENTRY_SIZE * LDT_ENTRIES;
153		168
154	mutex_lock(&mm->context.lock);	169	size = mm->context.ldt->size * LDT_ENTRY_SIZE;
155	size = mm->context.size * LDT_ENTRY_SIZE;
156	if (size > bytecount)	170	if (size > bytecount)
157	size = bytecount;	171	size = bytecount;
158		172
159	err = 0;	173	if (copy_to_user(ptr, mm->context.ldt->entries, size)) {
160	if (copy_to_user(ptr, mm->context.ldt, size))	174	retval = -EFAULT;
161	err = -EFAULT;	175	goto out_unlock;
162	mutex_unlock(&mm->context.lock);	176	}
163	if (err < 0)	177
164	goto error_return;
165	if (size != bytecount) {	178	if (size != bytecount) {
166	/* zero-fill the rest */	179	/* Zero-fill the rest and pretend we read bytecount bytes. */
167	if (clear_user(ptr + size, bytecount - size) != 0) {	180	if (clear_user(ptr + size, bytecount - size)) {
168	err = -EFAULT;	181	retval = -EFAULT;
169	goto error_return;	182	goto out_unlock;
170	}	183	}
171	}	184	}
172	return bytecount;	185	retval = bytecount;
173	error_return:	186
174	return err;	187	out_unlock:
		188	mutex_unlock(&mm->context.lock);
		189	return retval;
175	}	190	}
176		191
177	static int read_default_ldt(void __user *ptr, unsigned long bytecount)	192	static int read_default_ldt(void __user *ptr, unsigned long bytecount)
@@ -195,6 +210,8 @@ static int write_ldt(void __user *ptr, unsigned long bytecount, int oldmode) · 17 unmodified lines
195	struct desc_struct ldt;	210	struct desc_struct ldt;
196	int error;	211	int error;
197	struct user_desc ldt_info;	212	struct user_desc ldt_info;
		213	int oldsize, newsize;
		214	struct ldt_struct new_ldt, old_ldt;
198		215
199	error = -EINVAL;	216	error = -EINVAL;
200	if (bytecount != sizeof(ldt_info))	217	if (bytecount != sizeof(ldt_info))
@@ -213,34 +230,39 @@ static int write_ldt(void __user *ptr, unsigned long bytecount, int oldmode) · 12 unmodified lines
213	goto out;	230	goto out;
214	}	231	}
215		232
216	mutex_lock(&mm->context.lock);	233	if ((oldmode && !ldt_info.base_addr && !ldt_info.limit) \|\|
217	if (ldt_info.entry_number >= mm->context.size) {	234	LDT_empty(&ldt_info)) {
218	error = alloc_ldt(&current->mm->context,	235	/* The user wants to clear the entry. */
219	ldt_info.entry_number + 1, 1);	236	memset(&ldt, 0, sizeof(ldt));
220	if (error < 0)	237	} else {
221	goto out_unlock;	238	if (!IS_ENABLED(CONFIG_X86_16BIT) && !ldt_info.seg_32bit) {
222	}	239	error = -EINVAL;
223		240	goto out;
224	/* Allow LDTs to be cleared by the user. */
225	if (ldt_info.base_addr == 0 && ldt_info.limit == 0) {
226	if (oldmode \|\| LDT_empty(&ldt_info)) {
227	memset(&ldt, 0, sizeof(ldt));
228	goto install;
229	}	241	}
		242
		243	fill_ldt(&ldt, &ldt_info);
		244	if (oldmode)
		245	ldt.avl = 0;
230	}	246	}
231		247
232	if (!IS_ENABLED(CONFIG_X86_16BIT) && !ldt_info.seg_32bit) {	248	mutex_lock(&mm->context.lock);
233	error = -EINVAL;	249
		250	old_ldt = mm->context.ldt;
		251	oldsize = old_ldt ? old_ldt->size : 0;
		252	newsize = max((int)(ldt_info.entry_number + 1), oldsize);
		253
		254	error = -ENOMEM;
		255	new_ldt = alloc_ldt_struct(newsize);
		256	if (!new_ldt)
234	goto out_unlock;	257	goto out_unlock;
235	}
236		258
237	fill_ldt(&ldt, &ldt_info);	259	if (old_ldt)
238	if (oldmode)	260	memcpy(new_ldt->entries, old_ldt->entries, oldsize * LDT_ENTRY_SIZE);
239	ldt.avl = 0;	261	new_ldt->entries[ldt_info.entry_number] = ldt;
		262	finalize_ldt_struct(new_ldt);
240		263
241	/* Install the new entry ... */	264	install_ldt(mm, new_ldt);
242	install:	265	free_ldt_struct(old_ldt);
243	write_ldt_entry(mm->context.ldt, ldt_info.entry_number, &ldt);
244	error = 0;	266	error = 0;
245		267
246	out_unlock:	268	out_unlock:

arch/x86/kernel/process_64.c+2−2

@@ -121,11 +121,11 @@ void __show_regs(struct pt_regs *regs, int all) · 120 unmodified lines
121	void release_thread(struct task_struct *dead_task)	121	void release_thread(struct task_struct *dead_task)
122	{	122	{
123	if (dead_task->mm) {	123	if (dead_task->mm) {
124	if (dead_task->mm->context.size) {	124	if (dead_task->mm->context.ldt) {
125	pr_warn("WARNING: dead process %s still has LDT? <%p/%d>\n",	125	pr_warn("WARNING: dead process %s still has LDT? <%p/%d>\n",
126	dead_task->comm,	126	dead_task->comm,
127	dead_task->mm->context.ldt,	127	dead_task->mm->context.ldt,
128	dead_task->mm->context.size);	128	dead_task->mm->context.ldt->size);
129	BUG();	129	BUG();
130	}	130	}
131	}	131	}

arch/x86/kernel/signal.c+11−15

 		COPY(r15);
 #endif /* CONFIG_X86_64 */
+#ifdef CONFIG_X86_32
 		COPY_SEG_CPL3(cs);
 		COPY_SEG_CPL3(ss);
+#else /* !CONFIG_X86_32 */
+		/* Kernel saves and restores only the CS segment register on signals,
+		 * which is the bare minimum needed to allow mixed 32/64-bit code.
+		 * App's signal handler can save/restore other segments if needed. */
+		COPY_SEG_CPL3(cs);
+#endif /* CONFIG_X86_32 */
 		get_user_ex(tmpflags, &sc->flags);
 		regs->flags = (regs->flags & ~FIX_EFLAGS) | (tmpflags & FIX_EFLAGS);
 #else /* !CONFIG_X86_32 */
 		put_user_ex(regs->flags, &sc->flags);
 		put_user_ex(regs->cs, &sc->cs);
-		put_user_ex(0, &sc->__pad2);
+		put_user_ex(0, &sc->gs);
-		put_user_ex(0, &sc->__pad1);
+		put_user_ex(0, &sc->fs);
-		put_user_ex(regs->ss, &sc->ss);
 #endif /* CONFIG_X86_32 */
 		put_user_ex(fpstate, &sc->fpstate);
 	regs->sp = (unsigned long)frame;
-	/*
+	/* Set up the CS register to run signal handlers in 64-bit mode,
-	 * Set up the CS and SS registers to run signal handlers in
+	   even if the handler happens to be interrupting 32-bit code. */
-	 * 64-bit mode, even if the handler happens to be interrupting
-	 * 32-bit or 16-bit code.
-	 *
-	 * SS is subtle.  In 64-bit mode, we don't need any particular
-	 * SS descriptor, but we do need SS to be valid.  It's possible
-	 * that the old SS is entirely bogus -- this can happen if the
-	 * signal we're trying to deliver is #GP or #SS caused by a bad
-	 * SS value.
-	 */
 	regs->cs = __USER_CS;
-	regs->ss = __USER_DS;
 	return 0;
 }

arch/x86/kernel/step.c+5−3

 #include <linux/mm.h>
 #include <linux/ptrace.h>
 #include <asm/desc.h>
+#include <asm/mmu_context.h>
 unsigned long convert_ip_to_linear(struct task_struct *child, struct pt_regs *regs)
 {
 		struct desc_struct *desc;
 		unsigned long base;
-		seg &= ~7UL;
+		seg >>= 3;
 		mutex_lock(&child->mm->context.lock);
-		if (unlikely((seg >> 3) >= child->mm->context.size))
+		if (unlikely(!child->mm->context.ldt ||
+			     seg >= child->mm->context.ldt->size))
 			addr = -1L; /* bogus selector, access would fault */
 		else {
-			desc = child->mm->context.ldt + seg;
+			desc = &child->mm->context.ldt->entries[seg];
 			base = get_desc_base(desc);
 			/* 16-bit code segment? */

arch/x86/kvm/lapic.c+1−1

@@ -1595,7 +1595,7 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) · 1594 unmodified lines
1595	for (i = 0; i < APIC_LVT_NUM; i++)	1595	for (i = 0; i < APIC_LVT_NUM; i++)
1596	apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);	1596	apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1597	apic_update_lvtt(apic);	1597	apic_update_lvtt(apic);
1598	if (!(vcpu->kvm->arch.disabled_quirks & KVM_QUIRK_LINT0_REENABLED))	1598	if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
1599	apic_set_reg(apic, APIC_LVT0,	1599	apic_set_reg(apic, APIC_LVT0,
1600	SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));	1600	SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1601	apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0));	1601	apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0));

arch/x86/kvm/mtrr.c+30−10

@@ -120,6 +120,16 @@ static u8 mtrr_default_type(struct kvm_mtrr *mtrr_state) · 119 unmodified lines
120	return mtrr_state->deftype & IA32_MTRR_DEF_TYPE_TYPE_MASK;	120	return mtrr_state->deftype & IA32_MTRR_DEF_TYPE_TYPE_MASK;
121	}	121	}
122		122
		123	static u8 mtrr_disabled_type(void)
		124	{
		125	/*
		126	* Intel SDM 11.11.2.2: all MTRRs are disabled when
		127	* IA32_MTRR_DEF_TYPE.E bit is cleared, and the UC
		128	* memory type is applied to all of physical memory.
		129	*/
		130	return MTRR_TYPE_UNCACHABLE;
		131	}
		132
123	/*	133	/*
124	* Three terms are used in the following code:	134	* Three terms are used in the following code:
125	* - segment, it indicates the address segments covered by fixed MTRRs.	135	* - segment, it indicates the address segments covered by fixed MTRRs.
@@ -434,6 +444,8 @@ struct mtrr_iter { · 308 unmodified lines
434		444
435	/* output fields. */	445	/* output fields. */
436	int mem_type;	446	int mem_type;
		447	/* mtrr is completely disabled? */
		448	bool mtrr_disabled;
437	/* [start, end) is not fully covered in MTRRs? */	449	/* [start, end) is not fully covered in MTRRs? */
438	bool partial_map;	450	bool partial_map;
439		451
@@ -549,7 +561,7 @@ static void mtrr_lookup_var_next(struct mtrr_iter *iter) · 109 unmodified lines
549	static void mtrr_lookup_start(struct mtrr_iter *iter)	561	static void mtrr_lookup_start(struct mtrr_iter *iter)
550	{	562	{
551	if (!mtrr_is_enabled(iter->mtrr_state)) {	563	if (!mtrr_is_enabled(iter->mtrr_state)) {
552	iter->partial_map = true;	564	iter->mtrr_disabled = true;
553	return;	565	return;
554	}	566	}
555		567
@@ -563,6 +575,7 @@ static void mtrr_lookup_init(struct mtrr_iter *iter, · 7 unmodified lines
563	iter->mtrr_state = mtrr_state;	575	iter->mtrr_state = mtrr_state;
564	iter->start = start;	576	iter->start = start;
565	iter->end = end;	577	iter->end = end;
		578	iter->mtrr_disabled = false;
566	iter->partial_map = false;	579	iter->partial_map = false;
567	iter->fixed = false;	580	iter->fixed = false;
568	iter->range = NULL;	581	iter->range = NULL;
@@ -656,15 +669,19 @@ u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) · 87 unmodified lines
656	return MTRR_TYPE_WRBACK;	669	return MTRR_TYPE_WRBACK;
657	}	670	}
658		671
659	/* It is not covered by MTRRs. */	672	if (iter.mtrr_disabled)
660	if (iter.partial_map) {	673	return mtrr_disabled_type();
661	/*	674
662	* We just check one page, partially covered by MTRRs is	675	/* not contained in any MTRRs. */
663	* impossible.	676	if (type == -1)
664	*/	677	return mtrr_default_type(mtrr_state);
665	WARN_ON(type != -1);	678
666	type = mtrr_default_type(mtrr_state);	679	/*
667	}	680	* We just check one page, partially covered by MTRRs is
		681	* impossible.
		682	*/
		683	WARN_ON(iter.partial_map);
		684
668	return type;	685	return type;
669	}	686	}
670	EXPORT_SYMBOL_GPL(kvm_mtrr_get_guest_memory_type);	687	EXPORT_SYMBOL_GPL(kvm_mtrr_get_guest_memory_type);
@@ -689,6 +706,9 @@ bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, · 18 unmodified lines
689	return false;	706	return false;
690	}	707	}
691		708
		709	if (iter.mtrr_disabled)
		710	return true;
		711
692	if (!iter.partial_map)	712	if (!iter.partial_map)
693	return true;	713	return true;
694		714

arch/x86/kvm/svm.c+1−1

@@ -1672,7 +1672,7 @@ static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) · 1671 unmodified lines
1672	* does not do it - this results in some delay at	1672	* does not do it - this results in some delay at
1673	* reboot	1673	* reboot
1674	*/	1674	*/
1675	if (!(vcpu->kvm->arch.disabled_quirks & KVM_QUIRK_CD_NW_CLEARED))	1675	if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1676	cr0 &= ~(X86_CR0_CD \| X86_CR0_NW);	1676	cr0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1677	svm->vmcb->save.cr0 = cr0;	1677	svm->vmcb->save.cr0 = cr0;
1678	mark_dirty(svm->vmcb, VMCB_CR);	1678	mark_dirty(svm->vmcb, VMCB_CR);

arch/x86/kvm/vmx.c+4−1

 	if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
 		ipat = VMX_EPT_IPAT_BIT;
-		cache = MTRR_TYPE_UNCACHABLE;
+		if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
+			cache = MTRR_TYPE_WRBACK;
+		else
+			cache = MTRR_TYPE_UNCACHABLE;
 		goto exit;
 	}

arch/x86/kvm/x86.c+6−1

 		if (guest_cpuid_has_tsc_adjust(vcpu)) {
 			if (!msr_info->host_initiated) {
 				s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
-				kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
+				adjust_tsc_offset_guest(vcpu, adj);
 			}
 			vcpu->arch.ia32_tsc_adjust_msr = data;
 		}
 static void process_smi(struct kvm_vcpu *vcpu)
 {
 	struct kvm_segment cs, ds;
+	struct desc_ptr dt;
 	char buf[512];
 	u32 cr0;
 	kvm_x86_ops->set_cr4(vcpu, 0);
+	/* Undocumented: IDT limit is set to zero on entry to SMM.  */
+	dt.address = dt.size = 0;
+	kvm_x86_ops->set_idt(vcpu, &dt);
 	__kvm_set_dr(vcpu, 7, DR7_FIXED_1);
 	cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;

arch/x86/kvm/x86.h+5−0

 	return kvm_register_write(vcpu, reg, val);
 }
+static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk)
+{
+	return !(kvm->arch.disabled_quirks & quirk);
+}
 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu);
 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu);
 void kvm_set_pending_timer(struct kvm_vcpu *vcpu);

arch/x86/math-emu/fpu_entry.c+1−2

 #include <asm/uaccess.h>
 #include <asm/traps.h>
-#include <asm/desc.h>
 #include <asm/user.h>
 #include <asm/fpu/internal.h>
 			math_abort(FPU_info, SIGILL);
 		}
-		code_descriptor = LDT_DESCRIPTOR(FPU_CS);
+		code_descriptor = FPU_get_ldt_descriptor(FPU_CS);
 		if (SEG_D_SIZE(code_descriptor)) {
 			/* The above test may be wrong, the book is not clear */
 			/* Segmented 32 bit protected mode */

arch/x86/math-emu/fpu_system.h+18−3

@@ -16,9 +16,24 @@ · 15 unmodified lines
16	#include <linux/kernel.h>	16	#include <linux/kernel.h>
17	#include <linux/mm.h>	17	#include <linux/mm.h>
18		18
19	/* s is always from a cpu register, and the cpu does bounds checking	19	#include <asm/desc.h>
20	* during register load --> no further bounds checks needed */	20	#include <asm/mmu_context.h>
21	#define LDT_DESCRIPTOR(s) (((struct desc_struct *)current->mm->context.ldt)[(s) >> 3])	21
		22	static inline struct desc_struct FPU_get_ldt_descriptor(unsigned seg)
		23	{
		24	static struct desc_struct zero_desc;
		25	struct desc_struct ret = zero_desc;
		26
		27	#ifdef CONFIG_MODIFY_LDT_SYSCALL
		28	seg >>= 3;
		29	mutex_lock(&current->mm->context.lock);
		30	if (current->mm->context.ldt && seg < current->mm->context.ldt->size)
		31	ret = current->mm->context.ldt->entries[seg];
		32	mutex_unlock(&current->mm->context.lock);
		33	#endif
		34	return ret;
		35	}
		36
22	#define SEG_D_SIZE(x) ((x).b & (3 << 21))	37	#define SEG_D_SIZE(x) ((x).b & (3 << 21))
23	#define SEG_G_BIT(x) ((x).b & (1 << 23))	38	#define SEG_G_BIT(x) ((x).b & (1 << 23))
24	#define SEG_GRANULARITY(x) (((x).b & (1 << 23)) ? 4096 : 1)	39	#define SEG_GRANULARITY(x) (((x).b & (1 << 23)) ? 4096 : 1)

arch/x86/math-emu/get_address.c+1−2

 #include <linux/stddef.h>
 #include <asm/uaccess.h>
-#include <asm/desc.h>
 #include "fpu_system.h"
 #include "exception.h"
 		addr->selector = PM_REG_(segment);
 	}
-	descriptor = LDT_DESCRIPTOR(PM_REG_(segment));
+	descriptor = FPU_get_ldt_descriptor(addr->selector);
 	base_address = SEG_BASE_ADDR(descriptor);
 	address = base_address + offset;
 	limit = base_address

arch/x86/mm/ioremap.c+6−17

 		    !PageReserved(pfn_to_page(start_pfn + i)))
 			return 1;
-	WARN_ONCE(1, "ioremap on RAM pfn 0x%lx\n", start_pfn);
 	return 0;
 }
 	pgprot_t prot;
 	int retval;
 	void __iomem *ret_addr;
-	int ram_region;
 	/* Don't allow wraparound or zero size */
 	last_addr = phys_addr + size - 1;
 	/*
 	 * Don't allow anybody to remap normal RAM that we're using..
 	 */
-	/* First check if whole region can be identified as RAM or not */
+	pfn      = phys_addr >> PAGE_SHIFT;
-	ram_region = region_is_ram(phys_addr, size);
+	last_pfn = last_addr >> PAGE_SHIFT;
-	if (ram_region > 0) {
+	if (walk_system_ram_range(pfn, last_pfn - pfn + 1, NULL,
-		WARN_ONCE(1, "ioremap on RAM at 0x%lx - 0x%lx\n",
+					  __ioremap_check_ram) == 1) {
-				(unsigned long int)phys_addr,
+		WARN_ONCE(1, "ioremap on RAM at %pa - %pa\n",
-				(unsigned long int)last_addr);
+			  &phys_addr, &last_addr);
 		return NULL;
 	}
-	/* If could not be identified(-1), check page by page */
-	if (ram_region < 0) {
-		pfn      = phys_addr >> PAGE_SHIFT;
-		last_pfn = last_addr >> PAGE_SHIFT;
-		if (walk_system_ram_range(pfn, last_pfn - pfn + 1, NULL,
-					  __ioremap_check_ram) == 1)
-			return NULL;
-	}
 	/*
 	 * Mappings have to be page-aligned
 	 */

arch/x86/mm/mmap.c+7−0

@@ -126,3 +126,10 @@ void arch_pick_mmap_layout(struct mm_struct *mm) · 125 unmodified lines
126	mm->get_unmapped_area = arch_get_unmapped_area_topdown;	126	mm->get_unmapped_area = arch_get_unmapped_area_topdown;
127	}	127	}
128	}	128	}
		129
		130	const char arch_vma_name(struct vm_area_struct vma)
		131	{
		132	if (vma->vm_flags & VM_MPX)
		133	return "[mpx]";
		134	return NULL;
		135	}

arch/x86/mm/mpx.c+3−21

 #define CREATE_TRACE_POINTS
 #include <asm/trace/mpx.h>
-static const char *mpx_mapping_name(struct vm_area_struct *vma)
-{
-	return "[mpx]";
-}
-static struct vm_operations_struct mpx_vma_ops = {
-	.name = mpx_mapping_name,
-};
-static int is_mpx_vma(struct vm_area_struct *vma)
-{
-	return (vma->vm_ops == &mpx_vma_ops);
-}
 static inline unsigned long mpx_bd_size_bytes(struct mm_struct *mm)
 {
 	if (is_64bit_mm(mm))
 /*
  * This is really a simplified "vm_mmap". it only handles MPX
  * bounds tables (the bounds directory is user-allocated).
- *
- * Later on, we use the vma->vm_ops to uniquely identify these
- * VMAs.
  */
 static unsigned long mpx_mmap(unsigned long len)
 {
 		ret = -ENOMEM;
 		goto out;
 	}
-	vma->vm_ops = &mpx_vma_ops;
 	if (vm_flags & VM_LOCKED) {
 		up_write(&mm->mmap_sem);
 		 * so stop immediately and return an error.  This
 		 * probably results in a SIGSEGV.
 		 */
-		if (!is_mpx_vma(vma))
+		if (!(vma->vm_flags & VM_MPX))
 			return -EINVAL;
 		len = min(vma->vm_end, end) - addr;
 	 * lots of tables even though we have no actual table
 	 * entries in use.
 	 */
-	while (next && is_mpx_vma(next))
+	while (next && (next->vm_flags & VM_MPX))
 		next = next->vm_next;
-	while (prev && is_mpx_vma(prev))
+	while (prev && (prev->vm_flags & VM_MPX))
 		prev = prev->vm_prev;
 	/*
 	 * We know 'start' and 'end' lie within an area controlled

arch/x86/mm/tlb.c+1−1

@@ -117,7 +117,7 @@ static void flush_tlb_func(void *info) · 116 unmodified lines
117	} else {	117	} else {
118	unsigned long addr;	118	unsigned long addr;
119	unsigned long nr_pages =	119	unsigned long nr_pages =
120	f->flush_end - f->flush_start / PAGE_SIZE;	120	(f->flush_end - f->flush_start) / PAGE_SIZE;
121	addr = f->flush_start;	121	addr = f->flush_start;
122	while (addr < f->flush_end) {	122	while (addr < f->flush_end) {
123	__flush_tlb_single(addr);	123	__flush_tlb_single(addr);

arch/x86/net/bpf_jit_comp.c+4−4

arch/x86/platform/efi/efi.c+5−0

 static int __init arch_parse_efi_cmdline(char *str)
 {
+	if (!str) {
+		pr_warn("need at least one option\n");
+		return -EINVAL;
+	}
 	if (parse_option_str(str, "old_map"))
 		set_bit(EFI_OLD_MEMMAP, &efi.flags);
 	if (parse_option_str(str, "debug"))

arch/x86/power/cpu.c+2−1

 #include <asm/fpu/internal.h>
 #include <asm/debugreg.h>
 #include <asm/cpu.h>
+#include <asm/mmu_context.h>
 #ifdef CONFIG_X86_32
 __visible unsigned long saved_context_ebx;
 	syscall_init();				/* This sets MSR_*STAR and related */
 #endif
 	load_TR_desc();				/* This does ltr */
-	load_LDT(&current->active_mm->context);	/* This does lldt */
+	load_mm_ldt(current->active_mm);	/* This does lldt */
 	fpu__resume_cpu();
 }

arch/x86/xen/Makefile+2−2

@@ -13,13 +13,13 @@ CFLAGS_mmu.o := $(nostackp) · 12 unmodified lines
13	obj-y := enlighten.o setup.o multicalls.o mmu.o irq.o \	13	obj-y := enlighten.o setup.o multicalls.o mmu.o irq.o \
14	time.o xen-asm.o xen-asm_$(BITS).o \	14	time.o xen-asm.o xen-asm_$(BITS).o \
15	grant-table.o suspend.o platform-pci-unplug.o \	15	grant-table.o suspend.o platform-pci-unplug.o \
16	p2m.o	16	p2m.o apic.o
17		17
18	obj-$(CONFIG_EVENT_TRACING) += trace.o	18	obj-$(CONFIG_EVENT_TRACING) += trace.o
19		19
20	obj-$(CONFIG_SMP) += smp.o	20	obj-$(CONFIG_SMP) += smp.o
21	obj-$(CONFIG_PARAVIRT_SPINLOCKS)+= spinlock.o	21	obj-$(CONFIG_PARAVIRT_SPINLOCKS)+= spinlock.o
22	obj-$(CONFIG_XEN_DEBUG_FS) += debugfs.o	22	obj-$(CONFIG_XEN_DEBUG_FS) += debugfs.o
23	obj-$(CONFIG_XEN_DOM0) += apic.o vga.o	23	obj-$(CONFIG_XEN_DOM0) += vga.o
24	obj-$(CONFIG_SWIOTLB_XEN) += pci-swiotlb-xen.o	24	obj-$(CONFIG_SWIOTLB_XEN) += pci-swiotlb-xen.o
25	obj-$(CONFIG_XEN_EFI) += efi.o	25	obj-$(CONFIG_XEN_EFI) += efi.o

arch/x86/xen/enlighten.c+40−0

@@ -483,6 +483,7 @@ static void set_aliased_prot(void *v, pgprot_t prot) · 482 unmodified lines
483	pte_t pte;	483	pte_t pte;
484	unsigned long pfn;	484	unsigned long pfn;
485	struct page *page;	485	struct page *page;
		486	unsigned char dummy;
486		487
487	ptep = lookup_address((unsigned long)v, &level);	488	ptep = lookup_address((unsigned long)v, &level);
488	BUG_ON(ptep == NULL);	489	BUG_ON(ptep == NULL);
@@ -492,6 +493,32 @@ static void set_aliased_prot(void *v, pgprot_t prot) · 3 unmodified lines
492		493
493	pte = pfn_pte(pfn, prot);	494	pte = pfn_pte(pfn, prot);
494		495
		496	/*
		497	* Careful: update_va_mapping() will fail if the virtual address
		498	* we're poking isn't populated in the page tables. We don't
		499	* need to worry about the direct map (that's always in the page
		500	* tables), but we need to be careful about vmap space. In
		501	* particular, the top level page table can lazily propagate
		502	* entries between processes, so if we've switched mms since we
		503	* vmapped the target in the first place, we might not have the
		504	* top-level page table entry populated.
		505	*
		506	* We disable preemption because we want the same mm active when
		507	* we probe the target and when we issue the hypercall. We'll
		508	* have the same nominal mm, but if we're a kernel thread, lazy
		509	* mm dropping could change our pgd.
		510	*
		511	* Out of an abundance of caution, this uses __get_user() to fault
		512	* in the target address just in case there's some obscure case
		513	* in which the target address isn't readable.
		514	*/
		515
		516	preempt_disable();
		517
		518	pagefault_disable(); /* Avoid warnings due to being atomic. */
		519	__get_user(dummy, (unsigned char __user __force *)v);
		520	pagefault_enable();
		521
495	if (HYPERVISOR_update_va_mapping((unsigned long)v, pte, 0))	522	if (HYPERVISOR_update_va_mapping((unsigned long)v, pte, 0))
496	BUG();	523	BUG();
497		524
@@ -503,6 +530,8 @@ static void set_aliased_prot(void *v, pgprot_t prot) · 5 unmodified lines
503	BUG();	530	BUG();
504	} else	531	} else
505	kmap_flush_unused();	532	kmap_flush_unused();
		533
		534	preempt_enable();
506	}	535	}
507		536
508	static void xen_alloc_ldt(struct desc_struct *ldt, unsigned entries)	537	static void xen_alloc_ldt(struct desc_struct *ldt, unsigned entries)
@@ -510,6 +539,17 @@ static void xen_alloc_ldt(struct desc_struct *ldt, unsigned entries) · 1 unmodified line
510	const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE;	539	const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE;
511	int i;	540	int i;
512		541
		542	/*
		543	* We need to mark the all aliases of the LDT pages RO. We
		544	* don't need to call vm_flush_aliases(), though, since that's
		545	* only responsible for flushing aliases out the TLBs, not the
		546	* page tables, and Xen will flush the TLB for us if needed.
		547	*
		548	* To avoid confusing future readers: none of this is necessary
		549	* to load the LDT. The hypervisor only checks this when the
		550	* LDT is faulted in due to subsequent descriptor access.
		551	*/
		552
513	for(i = 0; i < entries; i += entries_per_page)	553	for(i = 0; i < entries; i += entries_per_page)
514	set_aliased_prot(ldt + i, PAGE_KERNEL_RO);	554	set_aliased_prot(ldt + i, PAGE_KERNEL_RO);
515	}	555	}

arch/x86/xen/xen-ops.h+2−4

 #ifdef CONFIG_XEN_DOM0
 void __init xen_init_vga(const struct dom0_vga_console_info *, size_t size);
-void __init xen_init_apic(void);
 #else
 static inline void __init xen_init_vga(const struct dom0_vga_console_info *info,
 				       size_t size)
 {
 }
-static inline void __init xen_init_apic(void)
-{
-}
 #endif
+void __init xen_init_apic(void);
 #ifdef CONFIG_XEN_EFI
 extern void xen_efi_init(void);
 #else

block/bio.c+14−3

  * Allocates and returns a new bio which represents @sectors from the start of
  * @bio, and updates @bio to represent the remaining sectors.
  *
- * The newly allocated bio will point to @bio's bi_io_vec; it is the caller's
+ * Unless this is a discard request the newly allocated bio will point
- * responsibility to ensure that @bio is not freed before the split.
+ * to @bio's bi_io_vec; it is the caller's responsibility to ensure that
+ * @bio is not freed before the split.
  */
 struct bio *bio_split(struct bio *bio, int sectors,
 		      gfp_t gfp, struct bio_set *bs)
 	BUG_ON(sectors <= 0);
 	BUG_ON(sectors >= bio_sectors(bio));
-	split = bio_clone_fast(bio, gfp, bs);
+	/*
+	 * Discards need a mutable bio_vec to accommodate the payload
+	 * required by the DSM TRIM and UNMAP commands.
+	 */
+	if (bio->bi_rw & REQ_DISCARD)
+		split = bio_clone_bioset(bio, gfp, bs);
+	else
+		split = bio_clone_fast(bio, gfp, bs);
 	if (!split)
 		return NULL;
 	bio->bi_css = blkcg_css;
 	return 0;
 }
+EXPORT_SYMBOL_GPL(bio_associate_blkcg);
 /**
  * bio_associate_current - associate a bio with %current
 	bio->bi_css = task_get_css(current, blkio_cgrp_id);
 	return 0;
 }
+EXPORT_SYMBOL_GPL(bio_associate_current);
 /**
  * bio_disassociate_task - undo bio_associate_current()

block/blk-cgroup.c+5−1

 		return -EINVAL;
 	disk = get_gendisk(MKDEV(major, minor), &part);
-	if (!disk || part)
+	if (!disk)
 		return -EINVAL;
+	if (part) {
+		put_disk(disk);
+		return -EINVAL;
+	}
 	rcu_read_lock();
 	spin_lock_irq(disk->queue->queue_lock);

block/blk-settings.c+2−2

@@ -241,8 +241,8 @@ EXPORT_SYMBOL(blk_queue_bounce_limit); · 240 unmodified lines
241	* Description:	241	* Description:
242	* Enables a low level driver to set a hard upper limit,	242	* Enables a low level driver to set a hard upper limit,
243	* max_hw_sectors, on the size of requests. max_hw_sectors is set by	243	* max_hw_sectors, on the size of requests. max_hw_sectors is set by
244	* the device driver based upon the combined capabilities of I/O	244	* the device driver based upon the capabilities of the I/O
245	* controller and storage device.	245	* controller.
246	*	246	*
247	* max_sectors is a soft limit imposed by the block layer for	247	* max_sectors is a soft limit imposed by the block layer for
248	* filesystem type requests. This value can be overridden on a	248	* filesystem type requests. This value can be overridden on a

drivers/acpi/device_pm.c+1−1

@@ -231,7 +231,7 @@ int acpi_device_set_power(struct acpi_device *device, int state) · 230 unmodified lines
231	dev_warn(&device->dev, "Failed to change power state to %s\n",	231	dev_warn(&device->dev, "Failed to change power state to %s\n",
232	acpi_power_state_string(state));	232	acpi_power_state_string(state));
233	} else {	233	} else {
234	device->power.state = state;	234	device->power.state = target_state;
235	ACPI_DEBUG_PRINT((ACPI_DB_INFO,	235	ACPI_DEBUG_PRINT((ACPI_DB_INFO,
236	"Device [%s] transitioned to %s\n",	236	"Device [%s] transitioned to %s\n",
237	device->pnp.bus_id,	237	device->pnp.bus_id,

drivers/ata/libata-core.c+18−3

 		dev->max_sectors = min_t(unsigned int, ATA_MAX_SECTORS_128,
 					 dev->max_sectors);
+	if (dev->horkage & ATA_HORKAGE_MAX_SEC_1024)
+		dev->max_sectors = min_t(unsigned int, ATA_MAX_SECTORS_1024,
+					 dev->max_sectors);
 	if (dev->horkage & ATA_HORKAGE_MAX_SEC_LBA48)
 		dev->max_sectors = ATA_MAX_SECTORS_LBA48;
 	{ "Slimtype DVD A  DS8A8SH", NULL,	ATA_HORKAGE_MAX_SEC_LBA48 },
 	{ "Slimtype DVD A  DS8A9SH", NULL,	ATA_HORKAGE_MAX_SEC_LBA48 },
+	/*
+	 * Causes silent data corruption with higher max sects.
+	 * http://lkml.kernel.org/g/x49wpy40ysk.fsf@segfault.boston.devel.redhat.com
+	 */
+	{ "ST380013AS",		"3.20",		ATA_HORKAGE_MAX_SEC_1024 },
 	/* Devices we expect to fail diagnostics */
 	/* Devices where NCQ should be avoided */
 	{ "ST3320[68]13AS",	"SD1[5-9]",	ATA_HORKAGE_NONCQ |
 						ATA_HORKAGE_FIRMWARE_WARN },
-	/* Seagate Momentus SpinPoint M8 seem to have FPMDA_AA issues */
+	/* drives which fail FPDMA_AA activation (some may freeze afterwards) */
 	{ "ST1000LM024 HN-M101MBB", "2AR10001",	ATA_HORKAGE_BROKEN_FPDMA_AA },
 	{ "ST1000LM024 HN-M101MBB", "2BA30001",	ATA_HORKAGE_BROKEN_FPDMA_AA },
+	{ "VB0250EAVER",	"HPG7",		ATA_HORKAGE_BROKEN_FPDMA_AA },
 	/* Blacklist entries taken from Silicon Image 3124/3132
 	   Windows driver .inf file - also several Linux problem reports */
 						ATA_HORKAGE_ZERO_AFTER_TRIM, },
 	{ "Crucial_CT*M500*",		NULL,	ATA_HORKAGE_NO_NCQ_TRIM |
 						ATA_HORKAGE_ZERO_AFTER_TRIM, },
-	{ "Micron_M5[15]0*",		"MU01",	ATA_HORKAGE_NO_NCQ_TRIM |
+	{ "Micron_M5[15]0_*",		"MU01",	ATA_HORKAGE_NO_NCQ_TRIM |
 						ATA_HORKAGE_ZERO_AFTER_TRIM, },
 	{ "Crucial_CT*M550*",		"MU01",	ATA_HORKAGE_NO_NCQ_TRIM |
 						ATA_HORKAGE_ZERO_AFTER_TRIM, },
 	{ "Samsung SSD 8*",		NULL,	ATA_HORKAGE_NO_NCQ_TRIM |
 						ATA_HORKAGE_ZERO_AFTER_TRIM, },
+	/* devices that don't properly handle TRIM commands */
+	{ "SuperSSpeed S238*",		NULL,	ATA_HORKAGE_NOTRIM, },
 	/*
 	 * As defined, the DRAT (Deterministic Read After Trim) and RZAT
 	 * (Return Zero After Trim) flags in the ATA Command Set are
 	else /* In the ancient relic department - skip all of this */
 		return 0;
-	err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0, 0);
+	/* On some disks, this command causes spin-up, so we need longer timeout */
+	err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0, 15000);
 	DPRINTK("EXIT, err_mask=%x\n", err_mask);
 	return err_mask;

drivers/ata/libata-pmp.c+7−0

@@ -460,6 +460,13 @@ static void sata_pmp_quirks(struct ata_port *ap) · 459 unmodified lines
460	ATA_LFLAG_NO_SRST \|	460	ATA_LFLAG_NO_SRST \|
461	ATA_LFLAG_ASSUME_ATA;	461	ATA_LFLAG_ASSUME_ATA;
462	}	462	}
		463	} else if (vendor == 0x11ab && devid == 0x4140) {
		464	/* Marvell 4140 quirks */
		465	ata_for_each_link(link, ap, EDGE) {
		466	/* port 4 is for SEMB device and it doesn't like SRST */
		467	if (link->pmp == 4)
		468	link->flags \|= ATA_LFLAG_DISABLED;
		469	}
463	}	470	}
464	}	471	}
465		472

drivers/ata/libata-scsi.c+2−1

@@ -2568,7 +2568,8 @@ static unsigned int ata_scsiop_read_cap(struct ata_scsi_args args, u8 rbuf) · 2567 unmodified lines
2568	rbuf[14] = (lowest_aligned >> 8) & 0x3f;	2568	rbuf[14] = (lowest_aligned >> 8) & 0x3f;
2569	rbuf[15] = lowest_aligned;	2569	rbuf[15] = lowest_aligned;
2570		2570
2571	if (ata_id_has_trim(args->id)) {	2571	if (ata_id_has_trim(args->id) &&
		2572	!(dev->horkage & ATA_HORKAGE_NOTRIM)) {
2572	rbuf[14] \|= 0x80; /* LBPME */	2573	rbuf[14] \|= 0x80; /* LBPME */
2573		2574
2574	if (ata_id_has_zero_after_trim(args->id) &&	2575	if (ata_id_has_zero_after_trim(args->id) &&

drivers/ata/libata-transport.c+2−0

@@ -569,6 +569,8 @@ show_ata_dev_trim(struct device *dev, · 568 unmodified lines
569		569
570	if (!ata_id_has_trim(ata_dev->id))	570	if (!ata_id_has_trim(ata_dev->id))
571	mode = "unsupported";	571	mode = "unsupported";
		572	else if (ata_dev->horkage & ATA_HORKAGE_NOTRIM)
		573	mode = "forced_unsupported";
572	else if (ata_dev->horkage & ATA_HORKAGE_NO_NCQ_TRIM)	574	else if (ata_dev->horkage & ATA_HORKAGE_NO_NCQ_TRIM)
573	mode = "forced_unqueued";	575	mode = "forced_unqueued";
574	else if (ata_fpdma_dsm_supported(ata_dev))	576	else if (ata_fpdma_dsm_supported(ata_dev))

drivers/base/regmap/regcache-rbtree.c+14−5

 	if (!blk)
 		return -ENOMEM;
-	present = krealloc(rbnode->cache_present,
+	if (BITS_TO_LONGS(blklen) > BITS_TO_LONGS(rbnode->blklen)) {
-		    BITS_TO_LONGS(blklen) * sizeof(*present), GFP_KERNEL);
+		present = krealloc(rbnode->cache_present,
-	if (!present) {
+				   BITS_TO_LONGS(blklen) * sizeof(*present),
-		kfree(blk);
+				   GFP_KERNEL);
-		return -ENOMEM;
+		if (!present) {
+			kfree(blk);
+			return -ENOMEM;
+		}
+		memset(present + BITS_TO_LONGS(rbnode->blklen), 0,
+		       (BITS_TO_LONGS(blklen) - BITS_TO_LONGS(rbnode->blklen))
+		       * sizeof(*present));
+	} else {
+		present = rbnode->cache_present;
 	}
 	/* insert the register value in the correct place in the rbnode block */

drivers/block/null_blk.c+9−9

@@ -240,19 +240,19 @@ static enum hrtimer_restart null_cmd_timer_expired(struct hrtimer *timer) · 239 unmodified lines
240	while ((entry = llist_del_all(&cq->list)) != NULL) {	240	while ((entry = llist_del_all(&cq->list)) != NULL) {
241	entry = llist_reverse_order(entry);	241	entry = llist_reverse_order(entry);
242	do {	242	do {
		243	struct request_queue *q = NULL;
		244
243	cmd = container_of(entry, struct nullb_cmd, ll_list);	245	cmd = container_of(entry, struct nullb_cmd, ll_list);
244	entry = entry->next;	246	entry = entry->next;
		247	if (cmd->rq)
		248	q = cmd->rq->q;
245	end_cmd(cmd);	249	end_cmd(cmd);
246		250
247	if (cmd->rq) {	251	if (q && !q->mq_ops && blk_queue_stopped(q)) {
248	struct request_queue *q = cmd->rq->q;	252	spin_lock(q->queue_lock);
249		253	if (blk_queue_stopped(q))
250	if (!q->mq_ops && blk_queue_stopped(q)) {	254	blk_start_queue(q);
251	spin_lock(q->queue_lock);	255	spin_unlock(q->queue_lock);
252	if (blk_queue_stopped(q))
253	blk_start_queue(q);
254	spin_unlock(q->queue_lock);
255	}
256	}	256	}
257	} while (entry);	257	} while (entry);
258	}	258	}

drivers/block/rbd.c+17−5

 #  define rbd_assert(expr)	((void) 0)
 #endif /* !RBD_DEBUG */
+static void rbd_osd_copyup_callback(struct rbd_obj_request *obj_request);
 static int rbd_img_obj_request_submit(struct rbd_obj_request *obj_request);
 static void rbd_img_parent_read(struct rbd_obj_request *obj_request);
 static void rbd_dev_remove_parent(struct rbd_device *rbd_dev);
 	obj_request_done_set(obj_request);
 }
+static void rbd_osd_call_callback(struct rbd_obj_request *obj_request)
+{
+	dout("%s: obj %p\n", __func__, obj_request);
+	if (obj_request_img_data_test(obj_request))
+		rbd_osd_copyup_callback(obj_request);
+	else
+		obj_request_done_set(obj_request);
+}
 static void rbd_osd_req_callback(struct ceph_osd_request *osd_req,
 				struct ceph_msg *msg)
 {
 		rbd_osd_discard_callback(obj_request);
 		break;
 	case CEPH_OSD_OP_CALL:
+		rbd_osd_call_callback(obj_request);
+		break;
 	case CEPH_OSD_OP_NOTIFY_ACK:
 	case CEPH_OSD_OP_WATCH:
 		rbd_osd_trivial_callback(obj_request);
 }
 static void
-rbd_img_obj_copyup_callback(struct rbd_obj_request *obj_request)
+rbd_osd_copyup_callback(struct rbd_obj_request *obj_request)
 {
 	struct rbd_img_request *img_request;
 	struct rbd_device *rbd_dev;
 	struct page **pages;
 	u32 page_count;
+	dout("%s: obj %p\n", __func__, obj_request);
 	rbd_assert(obj_request->type == OBJ_REQUEST_BIO ||
 		obj_request->type == OBJ_REQUEST_NODATA);
 	rbd_assert(obj_request_img_data_test(obj_request));
 	if (!obj_request->result)
 		obj_request->xferred = obj_request->length;
-	/* Finish up with the normal image object callback */
+	obj_request_done_set(obj_request);
-	rbd_img_obj_callback(obj_request);
 }
 static void
 	/* All set, send it off. */
-	orig_request->callback = rbd_img_obj_copyup_callback;
 	osdc = &rbd_dev->rbd_client->client->osdc;
 	img_result = rbd_obj_request_submit(osdc, orig_request);
 	if (!img_result)

drivers/block/xen-blkback/blkback.c+2−2

@@ -369,8 +369,8 @@ static void purge_persistent_gnt(struct xen_blkif *blkif) · 368 unmodified lines
369	return;	369	return;
370	}	370	}
371		371
372	if (work_pending(&blkif->persistent_purge_work)) {	372	if (work_busy(&blkif->persistent_purge_work)) {
373	pr_alert_ratelimited("Scheduled work from previous purge is still pending, cannot purge list\n");	373	pr_alert_ratelimited("Scheduled work from previous purge is still busy, cannot purge list\n");
374	return;	374	return;
375	}	375	}
376		376

drivers/block/xen-blkfront.c+72−56

 	((_segs + SEGS_PER_INDIRECT_FRAME - 1)/SEGS_PER_INDIRECT_FRAME)
 static int blkfront_setup_indirect(struct blkfront_info *info);
+static int blkfront_gather_backend_features(struct blkfront_info *info);
 static int get_id_from_freelist(struct blkfront_info *info)
 {
 				 * Add the used indirect page back to the list of
 				 * available pages for indirect grefs.
 				 */
-				indirect_page = pfn_to_page(s->indirect_grants[i]->pfn);
+				if (!info->feature_persistent) {
-				list_add(&indirect_page->lru, &info->indirect_pages);
+					indirect_page = pfn_to_page(s->indirect_grants[i]->pfn);
+					list_add(&indirect_page->lru, &info->indirect_pages);
+				}
 				s->indirect_grants[i]->gref = GRANT_INVALID_REF;
 				list_add_tail(&s->indirect_grants[i]->node, &info->grants);
 			}
 	info->shadow_free = info->ring.req_prod_pvt;
 	info->shadow[BLK_RING_SIZE(info)-1].req.u.rw.id = 0x0fffffff;
-	rc = blkfront_setup_indirect(info);
+	rc = blkfront_gather_backend_features(info);
 	if (rc) {
 		kfree(copy);
 		return rc;
 static int blkfront_setup_indirect(struct blkfront_info *info)
 {
-	unsigned int indirect_segments, segs;
+	unsigned int segs;
 	int err, i;
-	err = xenbus_gather(XBT_NIL, info->xbdev->otherend,
+	if (info->max_indirect_segments == 0)
-			    "feature-max-indirect-segments", "%u", &indirect_segments,
-			    NULL);
-	if (err) {
-		info->max_indirect_segments = 0;
 		segs = BLKIF_MAX_SEGMENTS_PER_REQUEST;
-	} else {
+	else
-		info->max_indirect_segments = min(indirect_segments,
-						  xen_blkif_max_segments);
 		segs = info->max_indirect_segments;
-	}
 	err = fill_grant_buffer(info, (segs + INDIRECT_GREFS(segs)) * BLK_RING_SIZE(info));
 	if (err)
 	return -ENOMEM;
 }
+/*
+ * Gather all backend feature-*
+ */
+static int blkfront_gather_backend_features(struct blkfront_info *info)
+{
+	int err;
+	int barrier, flush, discard, persistent;
+	unsigned int indirect_segments;
+	info->feature_flush = 0;
+	err = xenbus_gather(XBT_NIL, info->xbdev->otherend,
+			"feature-barrier", "%d", &barrier,
+			NULL);
+	/*
+	 * If there's no "feature-barrier" defined, then it means
+	 * we're dealing with a very old backend which writes
+	 * synchronously; nothing to do.
+	 *
+	 * If there are barriers, then we use flush.
+	 */
+	if (!err && barrier)
+		info->feature_flush = REQ_FLUSH | REQ_FUA;
+	/*
+	 * And if there is "feature-flush-cache" use that above
+	 * barriers.
+	 */
+	err = xenbus_gather(XBT_NIL, info->xbdev->otherend,
+			"feature-flush-cache", "%d", &flush,
+			NULL);
+	if (!err && flush)
+		info->feature_flush = REQ_FLUSH;
+	err = xenbus_gather(XBT_NIL, info->xbdev->otherend,
+			"feature-discard", "%d", &discard,
+			NULL);
+	if (!err && discard)
+		blkfront_setup_discard(info);
+	err = xenbus_gather(XBT_NIL, info->xbdev->otherend,
+			"feature-persistent", "%u", &persistent,
+			NULL);
+	if (err)
+		info->feature_persistent = 0;
+	else
+		info->feature_persistent = persistent;
+	err = xenbus_gather(XBT_NIL, info->xbdev->otherend,
+			    "feature-max-indirect-segments", "%u", &indirect_segments,
+			    NULL);
+	if (err)
+		info->max_indirect_segments = 0;
+	else
+		info->max_indirect_segments = min(indirect_segments,
+						  xen_blkif_max_segments);
+	return blkfront_setup_indirect(info);
+}
 /*
  * Invoked when the backend is finally 'ready' (and has told produced
  * the details about the physical device - #sectors, size, etc).
 	unsigned int physical_sector_size;
 	unsigned int binfo;
 	int err;
-	int barrier, flush, discard, persistent;
 	switch (info->connected) {
 	case BLKIF_STATE_CONNECTED:
 	if (err != 1)
 		physical_sector_size = sector_size;
-	info->feature_flush = 0;
+	err = blkfront_gather_backend_features(info);
-	err = xenbus_gather(XBT_NIL, info->xbdev->otherend,
-			    "feature-barrier", "%d", &barrier,
-			    NULL);
-	/*
-	 * If there's no "feature-barrier" defined, then it means
-	 * we're dealing with a very old backend which writes
-	 * synchronously; nothing to do.
-	 *
-	 * If there are barriers, then we use flush.
-	 */
-	if (!err && barrier)
-		info->feature_flush = REQ_FLUSH | REQ_FUA;
-	/*
-	 * And if there is "feature-flush-cache" use that above
-	 * barriers.
-	 */
-	err = xenbus_gather(XBT_NIL, info->xbdev->otherend,
-			    "feature-flush-cache", "%d", &flush,
-			    NULL);
-	if (!err && flush)
-		info->feature_flush = REQ_FLUSH;
-	err = xenbus_gather(XBT_NIL, info->xbdev->otherend,
-			    "feature-discard", "%d", &discard,
-			    NULL);
-	if (!err && discard)
-		blkfront_setup_discard(info);
-	err = xenbus_gather(XBT_NIL, info->xbdev->otherend,
-			    "feature-persistent", "%u", &persistent,
-			    NULL);
-	if (err)
-		info->feature_persistent = 0;
-	else
-		info->feature_persistent = persistent;
-	err = blkfront_setup_indirect(info);
 	if (err) {
 		xenbus_dev_fatal(info->xbdev, err, "setup_indirect at %s",
 				 info->xbdev->otherend);

drivers/block/zram/zram_drv.c+2−4

 	kfree(meta);
 }
-static struct zram_meta *zram_meta_alloc(int device_id, u64 disksize)
+static struct zram_meta *zram_meta_alloc(char *pool_name, u64 disksize)
 {
 	size_t num_pages;
-	char pool_name[8];
 	struct zram_meta *meta = kmalloc(sizeof(*meta), GFP_KERNEL);
 	if (!meta)
 		goto out_error;
 	}
-	snprintf(pool_name, sizeof(pool_name), "zram%d", device_id);
 	meta->mem_pool = zs_create_pool(pool_name, GFP_NOIO | __GFP_HIGHMEM);
 	if (!meta->mem_pool) {
 		pr_err("Error creating memory pool\n");
 		return -EINVAL;
 	disksize = PAGE_ALIGN(disksize);
-	meta = zram_meta_alloc(zram->disk->first_minor, disksize);
+	meta = zram_meta_alloc(zram->disk->disk_name, disksize);
 	if (!meta)
 		return -ENOMEM;

drivers/bluetooth/btbcm.c+5−6

@@ -472,12 +472,11 @@ int btbcm_setup_apple(struct hci_dev *hdev) · 471 unmodified lines
472		472
473	/* Read Verbose Config Version Info */	473	/* Read Verbose Config Version Info */
474	skb = btbcm_read_verbose_config(hdev);	474	skb = btbcm_read_verbose_config(hdev);
475	if (IS_ERR(skb))	475	if (!IS_ERR(skb)) {
476	return PTR_ERR(skb);	476	BT_INFO("%s: BCM: chip id %u build %4.4u", hdev->name, skb->data[1],
477		477	get_unaligned_le16(skb->data + 5));
478	BT_INFO("%s: BCM: chip id %u build %4.4u", hdev->name, skb->data[1],	478	kfree_skb(skb);
479	get_unaligned_le16(skb->data + 5));	479	}
480	kfree_skb(skb);
481		480
482	set_bit(HCI_QUIRK_STRICT_DUPLICATE_FILTER, &hdev->quirks);	481	set_bit(HCI_QUIRK_STRICT_DUPLICATE_FILTER, &hdev->quirks);
483		482

drivers/char/hw_random/core.c+1−1

@@ -429,7 +429,7 @@ static int hwrng_fillfn(void *unused) · 428 unmodified lines
429	static void start_khwrngd(void)	429	static void start_khwrngd(void)
430	{	430	{
431	hwrng_fill = kthread_run(hwrng_fillfn, NULL, "hwrng");	431	hwrng_fill = kthread_run(hwrng_fillfn, NULL, "hwrng");
432	if (hwrng_fill == ERR_PTR(-ENOMEM)) {	432	if (IS_ERR(hwrng_fill)) {
433	pr_err("hwrng_fill thread creation failed");	433	pr_err("hwrng_fill thread creation failed");
434	hwrng_fill = NULL;	434	hwrng_fill = NULL;
435	}	435	}

drivers/clk/pxa/clk-pxa3xx.c+1−1

@@ -126,7 +126,7 @@ PARENTS(pxa3xx_ac97_bus) = { "ring_osc_60mhz", "ac97" }; · 125 unmodified lines
126	PARENTS(pxa3xx_sbus) = { "ring_osc_60mhz", "system_bus" };	126	PARENTS(pxa3xx_sbus) = { "ring_osc_60mhz", "system_bus" };
127	PARENTS(pxa3xx_smemcbus) = { "ring_osc_60mhz", "smemc" };	127	PARENTS(pxa3xx_smemcbus) = { "ring_osc_60mhz", "smemc" };
128		128
129	#define CKEN_AB(bit) ((CKEN_ ## bit > 31) ? &CKENA : &CKENB)	129	#define CKEN_AB(bit) ((CKEN_ ## bit > 31) ? &CKENB : &CKENA)
130	#define PXA3XX_CKEN(dev_id, con_id, parents, mult_lp, div_lp, mult_hp, \	130	#define PXA3XX_CKEN(dev_id, con_id, parents, mult_lp, div_lp, mult_hp, \
131	div_hp, bit, is_lp, flags) \	131	div_hp, bit, is_lp, flags) \
132	PXA_CKEN(dev_id, con_id, bit, parents, mult_lp, div_lp, \	132	PXA_CKEN(dev_id, con_id, bit, parents, mult_lp, div_lp, \

drivers/clocksource/sh_cmt.c+6−0

 {
 	struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
+	if (!ch->cs_enabled)
+		return;
 	sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
 	pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
 }
 {
 	struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
+	if (!ch->cs_enabled)
+		return;
 	pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
 	sh_cmt_start(ch, FLAG_CLOCKSOURCE);
 }

drivers/cpufreq/cpufreq.c+55−53

 	int ret = 0;
 	/* Some related CPUs might not be present (physically hotplugged) */
-	for_each_cpu_and(j, policy->related_cpus, cpu_present_mask) {
+	for_each_cpu(j, policy->real_cpus) {
 		if (j == policy->kobj_cpu)
 			continue;
 	unsigned int j;
 	/* Some related CPUs might not be present (physically hotplugged) */
-	for_each_cpu_and(j, policy->related_cpus, cpu_present_mask) {
+	for_each_cpu(j, policy->real_cpus) {
 		if (j == policy->kobj_cpu)
 			continue;
 	if (!zalloc_cpumask_var(&policy->related_cpus, GFP_KERNEL))
 		goto err_free_cpumask;
+	if (!zalloc_cpumask_var(&policy->real_cpus, GFP_KERNEL))
+		goto err_free_rcpumask;
 	ret = kobject_init_and_add(&policy->kobj, &ktype_cpufreq, &dev->kobj,
 				   "cpufreq");
 	if (ret) {
 		pr_err("%s: failed to init policy->kobj: %d\n", __func__, ret);
-		goto err_free_rcpumask;
+		goto err_free_real_cpus;
 	}
 	INIT_LIST_HEAD(&policy->policy_list);
 	return policy;
+err_free_real_cpus:
+	free_cpumask_var(policy->real_cpus);
 err_free_rcpumask:
 	free_cpumask_var(policy->related_cpus);
 err_free_cpumask:
 	write_unlock_irqrestore(&cpufreq_driver_lock, flags);
 	cpufreq_policy_put_kobj(policy, notify);
+	free_cpumask_var(policy->real_cpus);
 	free_cpumask_var(policy->related_cpus);
 	free_cpumask_var(policy->cpus);
 	kfree(policy);
 	pr_debug("adding CPU %u\n", cpu);
-	/*
+	if (cpu_is_offline(cpu)) {
-	 * Only possible if 'cpu' wasn't physically present earlier and we are
+		/*
-	 * here from subsys_interface add callback. A hotplug notifier will
+		 * Only possible if we are here from the subsys_interface add
-	 * follow and we will handle it like logical CPU hotplug then. For now,
+		 * callback.  A hotplug notifier will follow and we will handle
-	 * just create the sysfs link.
+		 * it as CPU online then.  For now, just create the sysfs link,
-	 */
+		 * unless there is no policy or the link is already present.
-	if (cpu_is_offline(cpu))
+		 */
-		return add_cpu_dev_symlink(per_cpu(cpufreq_cpu_data, cpu), cpu);
+		policy = per_cpu(cpufreq_cpu_data, cpu);
+		return policy && !cpumask_test_and_set_cpu(cpu, policy->real_cpus)
+			? add_cpu_dev_symlink(policy, cpu) : 0;
+	}
 	if (!down_read_trylock(&cpufreq_rwsem))
 		return 0;
 	/* related cpus should atleast have policy->cpus */
 	cpumask_or(policy->related_cpus, policy->related_cpus, policy->cpus);
+	/* Remember which CPUs have been present at the policy creation time. */
+	if (!recover_policy)
+		cpumask_and(policy->real_cpus, policy->cpus, cpu_present_mask);
 	/*
 	 * affected cpus must always be the one, which are online. We aren't
 	 * managing offline cpus here.
 	return ret;
 }
-static int __cpufreq_remove_dev_prepare(struct device *dev,
+static int __cpufreq_remove_dev_prepare(struct device *dev)
-					struct subsys_interface *sif)
 {
 	unsigned int cpu = dev->id;
 	int ret = 0;
 	if (has_target()) {
 		ret = __cpufreq_governor(policy, CPUFREQ_GOV_STOP);
-		if (ret) {
+		if (ret)
 			pr_err("%s: Failed to stop governor\n", __func__);
-			return ret;
-		}
 	}
 	down_write(&policy->rwsem);
 	return ret;
 }
-static int __cpufreq_remove_dev_finish(struct device *dev,
+static int __cpufreq_remove_dev_finish(struct device *dev)
-				       struct subsys_interface *sif)
 {
 	unsigned int cpu = dev->id;
 	int ret;
 	/* If cpu is last user of policy, free policy */
 	if (has_target()) {
 		ret = __cpufreq_governor(policy, CPUFREQ_GOV_POLICY_EXIT);
-		if (ret) {
+		if (ret)
 			pr_err("%s: Failed to exit governor\n", __func__);
-			return ret;
-		}
 	}
 	/*
 	if (cpufreq_driver->exit)
 		cpufreq_driver->exit(policy);
-	/* Free the policy only if the driver is getting removed. */
-	if (sif)
-		cpufreq_policy_free(policy, true);
 	return 0;
 }
 static int cpufreq_remove_dev(struct device *dev, struct subsys_interface *sif)
 {
 	unsigned int cpu = dev->id;
-	int ret;
+	struct cpufreq_policy *policy = per_cpu(cpufreq_cpu_data, cpu);
-	/*
-	 * Only possible if 'cpu' is getting physically removed now. A hotplug
-	 * notifier should have already been called and we just need to remove
-	 * link or free policy here.
-	 */
-	if (cpu_is_offline(cpu)) {
-		struct cpufreq_policy *policy = per_cpu(cpufreq_cpu_data, cpu);
-		struct cpumask mask;
-		if (!policy)
+	if (!policy)
-			return 0;
+		return 0;
-		cpumask_copy(&mask, policy->related_cpus);
+	if (cpu_online(cpu)) {
-		cpumask_clear_cpu(cpu, &mask);
+		__cpufreq_remove_dev_prepare(dev);
+		__cpufreq_remove_dev_finish(dev);
+	}
-		/*
+	cpumask_clear_cpu(cpu, policy->real_cpus);
-		 * Free policy only if all policy->related_cpus are removed
-		 * physically.
-		 */
-		if (cpumask_intersects(&mask, cpu_present_mask)) {
-			remove_cpu_dev_symlink(policy, cpu);
-			return 0;
-		}
+	if (cpumask_empty(policy->real_cpus)) {
 		cpufreq_policy_free(policy, true);
 		return 0;
 	}
-	ret = __cpufreq_remove_dev_prepare(dev, sif);
+	if (cpu != policy->kobj_cpu) {
+		remove_cpu_dev_symlink(policy, cpu);
+	} else {
+		/*
+		 * The CPU owning the policy object is going away.  Move it to
+		 * another suitable CPU.
+		 */
+		unsigned int new_cpu = cpumask_first(policy->real_cpus);
+		struct device *new_dev = get_cpu_device(new_cpu);
+		dev_dbg(dev, "%s: Moving policy object to CPU%u\n", __func__, new_cpu);
-	if (!ret)
+		sysfs_remove_link(&new_dev->kobj, "cpufreq");
-		ret = __cpufreq_remove_dev_finish(dev, sif);
+		policy->kobj_cpu = new_cpu;
+		WARN_ON(kobject_move(&policy->kobj, &new_dev->kobj));
+	}
-	return ret;
+	return 0;
 }
 static void handle_update(struct work_struct *work)
 			break;
 		case CPU_DOWN_PREPARE:
-			__cpufreq_remove_dev_prepare(dev, NULL);
+			__cpufreq_remove_dev_prepare(dev);
 			break;
 		case CPU_POST_DEAD:
-			__cpufreq_remove_dev_finish(dev, NULL);
+			__cpufreq_remove_dev_finish(dev);
 			break;
 		case CPU_DOWN_FAILED:

drivers/cpufreq/intel_pstate.c+1−0

@@ -681,6 +681,7 @@ static struct cpu_defaults knl_params = { · 680 unmodified lines
681	.get_max = core_get_max_pstate,	681	.get_max = core_get_max_pstate,
682	.get_min = core_get_min_pstate,	682	.get_min = core_get_min_pstate,
683	.get_turbo = knl_get_turbo_pstate,	683	.get_turbo = knl_get_turbo_pstate,
		684	.get_scaling = core_get_scaling,
684	.set = core_set_pstate,	685	.set = core_set_pstate,
685	},	686	},
686	};	687	};

drivers/cpufreq/loongson2_cpufreq.c+1−1

@@ -20,7 +20,7 @@ · 19 unmodified lines
20	#include <asm/clock.h>	20	#include <asm/clock.h>
21	#include <asm/idle.h>	21	#include <asm/idle.h>
22		22
23	#include <asm/mach-loongson/loongson.h>	23	#include <asm/mach-loongson64/loongson.h>
24		24
25	static uint nowait;	25	static uint nowait;
26		26

drivers/crypto/ixp4xx_crypto.c+0−1

@@ -905,7 +905,6 @@ static int ablk_perform(struct ablkcipher_request *req, int encrypt) · 904 unmodified lines
905	crypt->mode \|= NPE_OP_NOT_IN_PLACE;	905	crypt->mode \|= NPE_OP_NOT_IN_PLACE;
906	/* This was never tested by Intel	906	/* This was never tested by Intel
907	* for more than one dst buffer, I think. */	907	* for more than one dst buffer, I think. */
908	BUG_ON(req->dst->length < nbytes);
909	req_ctx->dst = NULL;	908	req_ctx->dst = NULL;
910	if (!chainup_buffers(dev, req->dst, nbytes, &dst_hook,	909	if (!chainup_buffers(dev, req->dst, nbytes, &dst_hook,
911	flags, DMA_FROM_DEVICE))	910	flags, DMA_FROM_DEVICE))

drivers/crypto/qat/qat_common/qat_algs.c+16−8

@@ -73,7 +73,8 @@ · 72 unmodified lines
73	ICP_QAT_HW_CIPHER_KEY_CONVERT, \	73	ICP_QAT_HW_CIPHER_KEY_CONVERT, \
74	ICP_QAT_HW_CIPHER_DECRYPT)	74	ICP_QAT_HW_CIPHER_DECRYPT)
75		75
76	static atomic_t active_dev;	76	static DEFINE_MUTEX(algs_lock);
		77	static unsigned int active_devs;
77		78
78	struct qat_alg_buf {	79	struct qat_alg_buf {
79	uint32_t len;	80	uint32_t len;
@@ -1280,7 +1281,10 @@ static struct crypto_alg qat_algs[] = { { · 1200 unmodified lines
1280		1281
1281	int qat_algs_register(void)	1282	int qat_algs_register(void)
1282	{	1283	{
1283	if (atomic_add_return(1, &active_dev) == 1) {	1284	int ret = 0;
		1285
		1286	mutex_lock(&algs_lock);
		1287	if (++active_devs == 1) {
1284	int i;	1288	int i;
1285		1289
1286	for (i = 0; i < ARRAY_SIZE(qat_algs); i++)	1290	for (i = 0; i < ARRAY_SIZE(qat_algs); i++)
@@ -1289,21 +1293,25 @@ int qat_algs_register(void) · 2 unmodified lines
1289	CRYPTO_ALG_TYPE_AEAD \| CRYPTO_ALG_ASYNC :	1293	CRYPTO_ALG_TYPE_AEAD \| CRYPTO_ALG_ASYNC :
1290	CRYPTO_ALG_TYPE_ABLKCIPHER \| CRYPTO_ALG_ASYNC;	1294	CRYPTO_ALG_TYPE_ABLKCIPHER \| CRYPTO_ALG_ASYNC;
1291		1295
1292	return crypto_register_algs(qat_algs, ARRAY_SIZE(qat_algs));	1296	ret = crypto_register_algs(qat_algs, ARRAY_SIZE(qat_algs));
1293	}	1297	}
1294	return 0;	1298	mutex_unlock(&algs_lock);
		1299	return ret;
1295	}	1300	}
1296		1301
1297	int qat_algs_unregister(void)	1302	int qat_algs_unregister(void)
1298	{	1303	{
1299	if (atomic_sub_return(1, &active_dev) == 0)	1304	int ret = 0;
1300	return crypto_unregister_algs(qat_algs, ARRAY_SIZE(qat_algs));	1305
1301	return 0;	1306	mutex_lock(&algs_lock);
		1307	if (--active_devs == 0)
		1308	ret = crypto_unregister_algs(qat_algs, ARRAY_SIZE(qat_algs));
		1309	mutex_unlock(&algs_lock);
		1310	return ret;
1302	}	1311	}
1303		1312
1304	int qat_algs_init(void)	1313	int qat_algs_init(void)
1305	{	1314	{
1306	atomic_set(&active_dev, 0);
1307	crypto_get_default_rng();	1315	crypto_get_default_rng();
1308	return 0;	1316	return 0;
1309	}	1317	}

drivers/dma/at_hdmac.c+87−45

 	BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\
 	BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
+#define ATC_MAX_DSCR_TRIALS	10
 /*
  * Initial number of descriptors to allocate for each channel. This could
  * be increased during dma usage.
  *
  * @current_len: the number of bytes left before reading CTRLA
  * @ctrla: the value of CTRLA
- * @desc: the descriptor containing the transfer width
  */
-static inline int atc_calc_bytes_left(int current_len, u32 ctrla,
+static inline int atc_calc_bytes_left(int current_len, u32 ctrla)
-					struct at_desc *desc)
 {
-	return current_len - ((ctrla & ATC_BTSIZE_MAX) << desc->tx_width);
+	u32 btsize = (ctrla & ATC_BTSIZE_MAX);
-}
+	u32 src_width = ATC_REG_TO_SRC_WIDTH(ctrla);
-/**
+	/*
- * atc_calc_bytes_left_from_reg - calculates the number of bytes left according
+	 * According to the datasheet, when reading the Control A Register
- * to the current value of CTRLA.
+	 * (ctrla), the Buffer Transfer Size (btsize) bitfield refers to the
- *
+	 * number of transfers completed on the Source Interface.
- * @current_len: the number of bytes left before reading CTRLA
+	 * So btsize is always a number of source width transfers.
- * @atchan: the channel to read CTRLA for
+	 */
- * @desc: the descriptor containing the transfer width
+	return current_len - (btsize << src_width);
- */
-static inline int atc_calc_bytes_left_from_reg(int current_len,
-			struct at_dma_chan *atchan, struct at_desc *desc)
-{
-	u32 ctrla = channel_readl(atchan, CTRLA);
-	return atc_calc_bytes_left(current_len, ctrla, desc);
 }
 /**
 	struct at_desc *desc_first = atc_first_active(atchan);
 	struct at_desc *desc;
 	int ret;
-	u32 ctrla, dscr;
+	u32 ctrla, dscr, trials;
 	/*
 	 * If the cookie doesn't match to the currently running transfer then
 		 * the channel's DSCR register and compare it against the value
 		 * of the hardware linked list structure of each child
 		 * descriptor.
+		 *
+		 * The CTRLA register provides us with the amount of data
+		 * already read from the source for the current child
+		 * descriptor. So we can compute a more accurate residue by also
+		 * removing the number of bytes corresponding to this amount of
+		 * data.
+		 *
+		 * However, the DSCR and CTRLA registers cannot be read both
+		 * atomically. Hence a race condition may occur: the first read
+		 * register may refer to one child descriptor whereas the second
+		 * read may refer to a later child descriptor in the list
+		 * because of the DMA transfer progression inbetween the two
+		 * reads.
+		 *
+		 * One solution could have been to pause the DMA transfer, read
+		 * the DSCR and CTRLA then resume the DMA transfer. Nonetheless,
+		 * this approach presents some drawbacks:
+		 * - If the DMA transfer is paused, RX overruns or TX underruns
+		 *   are more likey to occur depending on the system latency.
+		 *   Taking the USART driver as an example, it uses a cyclic DMA
+		 *   transfer to read data from the Receive Holding Register
+		 *   (RHR) to avoid RX overruns since the RHR is not protected
+		 *   by any FIFO on most Atmel SoCs. So pausing the DMA transfer
+		 *   to compute the residue would break the USART driver design.
+		 * - The atc_pause() function masks interrupts but we'd rather
+		 *   avoid to do so for system latency purpose.
+		 *
+		 * Then we'd rather use another solution: the DSCR is read a
+		 * first time, the CTRLA is read in turn, next the DSCR is read
+		 * a second time. If the two consecutive read values of the DSCR
+		 * are the same then we assume both refers to the very same
+		 * child descriptor as well as the CTRLA value read inbetween
+		 * does. For cyclic tranfers, the assumption is that a full loop
+		 * is "not so fast".
+		 * If the two DSCR values are different, we read again the CTRLA
+		 * then the DSCR till two consecutive read values from DSCR are
+		 * equal or till the maxium trials is reach.
+		 * This algorithm is very unlikely not to find a stable value for
+		 * DSCR.
 		 */
-		ctrla = channel_readl(atchan, CTRLA);
-		rmb(); /* ensure CTRLA is read before DSCR */
 		dscr = channel_readl(atchan, DSCR);
+		rmb(); /* ensure DSCR is read before CTRLA */
+		ctrla = channel_readl(atchan, CTRLA);
+		for (trials = 0; trials < ATC_MAX_DSCR_TRIALS; ++trials) {
+			u32 new_dscr;
+			rmb(); /* ensure DSCR is read after CTRLA */
+			new_dscr = channel_readl(atchan, DSCR);
+			/*
+			 * If the DSCR register value has not changed inside the
+			 * DMA controller since the previous read, we assume
+			 * that both the dscr and ctrla values refers to the
+			 * very same descriptor.
+			 */
+			if (likely(new_dscr == dscr))
+				break;
+			/*
+			 * DSCR has changed inside the DMA controller, so the
+			 * previouly read value of CTRLA may refer to an already
+			 * processed descriptor hence could be outdated.
+			 * We need to update ctrla to match the current
+			 * descriptor.
+			 */
+			dscr = new_dscr;
+			rmb(); /* ensure DSCR is read before CTRLA */
+			ctrla = channel_readl(atchan, CTRLA);
+		}
+		if (unlikely(trials >= ATC_MAX_DSCR_TRIALS))
+			return -ETIMEDOUT;
 		/* for the first descriptor we can be more accurate */
 		if (desc_first->lli.dscr == dscr)
-			return atc_calc_bytes_left(ret, ctrla, desc_first);
+			return atc_calc_bytes_left(ret, ctrla);
 		ret -= desc_first->len;
 		list_for_each_entry(desc, &desc_first->tx_list, desc_node) {
 		}
 		/*
-		 * For the last descriptor in the chain we can calculate
+		 * For the current descriptor in the chain we can calculate
 		 * the remaining bytes using the channel's register.
-		 * Note that the transfer width of the first and last
-		 * descriptor may differ.
 		 */
-		if (!desc->lli.dscr)
+		ret = atc_calc_bytes_left(ret, ctrla);
-			ret = atc_calc_bytes_left_from_reg(ret, atchan, desc);
 	} else {
 		/* single transfer */
-		ret = atc_calc_bytes_left_from_reg(ret, atchan, desc_first);
+		ctrla = channel_readl(atchan, CTRLA);
+		ret = atc_calc_bytes_left(ret, ctrla);
 	}
 	return ret;
 	desc->txd.cookie = -EBUSY;
 	desc->total_len = desc->len = len;
-	desc->tx_width = dwidth;
 	/* set end-of-link to the last link descriptor of list*/
 	set_desc_eol(desc);
 	first->txd.cookie = -EBUSY;
 	first->total_len = len;
-	/* set transfer width for the calculation of the residue */
-	first->tx_width = src_width;
-	prev->tx_width = src_width;
 	/* set end-of-link to the last link descriptor of list*/
 	set_desc_eol(desc);
 	first->txd.cookie = -EBUSY;
 	first->total_len = total_len;
-	/* set transfer width for the calculation of the residue */
-	first->tx_width = reg_width;
-	prev->tx_width = reg_width;
 	/* first link descriptor of list is responsible of flags */
 	first->txd.flags = flags; /* client is in control of this ack */
 		desc->txd.cookie = 0;
 		desc->len = len;
-		/*
-		 * Although we only need the transfer width for the first and
-		 * the last descriptor, its easier to set it to all descriptors.
-		 */
-		desc->tx_width = src_width;
 		atc_desc_chain(&first, &prev, desc);
 		/* update the lengths and addresses for the next loop cycle */
 	/* First descriptor of the chain embedds additional information */
 	first->txd.cookie = -EBUSY;
 	first->total_len = buf_len;
-	first->tx_width = reg_width;
 	return &first->txd;

drivers/dma/at_hdmac_regs.h+1−2

 #define		ATC_SRC_WIDTH_BYTE	(0x0 << 24)
 #define		ATC_SRC_WIDTH_HALFWORD	(0x1 << 24)
 #define		ATC_SRC_WIDTH_WORD	(0x2 << 24)
+#define		ATC_REG_TO_SRC_WIDTH(r)	(((r) >> 24) & 0x3)
 #define	ATC_DST_WIDTH_MASK	(0x3 << 28)	/* Destination Single Transfer Size */
 #define		ATC_DST_WIDTH(x)	((x) << 28)
 #define		ATC_DST_WIDTH_BYTE	(0x0 << 28)
  * @txd: support for the async_tx api
  * @desc_node: node on the channed descriptors list
  * @len: descriptor byte count
- * @tx_width: transfer width
  * @total_len: total transaction byte count
  */
 struct at_desc {
 	struct dma_async_tx_descriptor	txd;
 	struct list_head		desc_node;
 	size_t				len;
-	u32				tx_width;
 	size_t				total_len;
 	/* Interleaved data */

drivers/dma/at_xdmac.c+14−12

 	 * descriptor view 2 since some fields of the configuration register
 	 * depend on transfer size and src/dest addresses.
 	 */
-	if (at_xdmac_chan_is_cyclic(atchan)) {
+	if (at_xdmac_chan_is_cyclic(atchan))
 		reg = AT_XDMAC_CNDC_NDVIEW_NDV1;
-		at_xdmac_chan_write(atchan, AT_XDMAC_CC, first->lld.mbr_cfg);
+	else if (first->lld.mbr_ubc & AT_XDMAC_MBR_UBC_NDV3)
-	} else if (first->lld.mbr_ubc & AT_XDMAC_MBR_UBC_NDV3) {
 		reg = AT_XDMAC_CNDC_NDVIEW_NDV3;
-	} else {
+	else
-		/*
-		 * No need to write AT_XDMAC_CC reg, it will be done when the
-		 * descriptor is fecthed.
-		 */
 		reg = AT_XDMAC_CNDC_NDVIEW_NDV2;
-	}
+	/*
+	 * Even if the register will be updated from the configuration in the
+	 * descriptor when using view 2 or higher, the PROT bit won't be set
+	 * properly. This bit can be modified only by using the channel
+	 * configuration register.
+	 */
+	at_xdmac_chan_write(atchan, AT_XDMAC_CC, first->lld.mbr_cfg);
 	reg |= AT_XDMAC_CNDC_NDDUP
 	       | AT_XDMAC_CNDC_NDSUP
 			desc->lld.mbr_sa = mem;
 			desc->lld.mbr_da = atchan->sconfig.dst_addr;
 		}
-		desc->lld.mbr_cfg = atchan->cfg;
+		dwidth = at_xdmac_get_dwidth(atchan->cfg);
-		dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg);
 		fixed_dwidth = IS_ALIGNED(len, 1 << dwidth)
-			       ? at_xdmac_get_dwidth(desc->lld.mbr_cfg)
+			       ? dwidth
 			       : AT_XDMAC_CC_DWIDTH_BYTE;
 		desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2			/* next descriptor view */
 			| AT_XDMAC_MBR_UBC_NDEN					/* next descriptor dst parameter update */
 			| AT_XDMAC_MBR_UBC_NSEN					/* next descriptor src parameter update */
 			| (len >> fixed_dwidth);				/* microblock length */
+		desc->lld.mbr_cfg = (atchan->cfg & ~AT_XDMAC_CC_DWIDTH_MASK) |
+				    AT_XDMAC_CC_DWIDTH(fixed_dwidth);
 		dev_dbg(chan2dev(chan),
 			 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
 			 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);

drivers/dma/mv_xor.c+5−4

@@ -162,10 +162,11 @@ static void mv_chan_set_mode(struct mv_xor_chan *chan, · 161 unmodified lines
162	config &= ~0x7;	162	config &= ~0x7;
163	config \|= op_mode;	163	config \|= op_mode;
164		164
165	if (IS_ENABLED(__BIG_ENDIAN))	165	#if defined(__BIG_ENDIAN)
166	config \|= XOR_DESCRIPTOR_SWAP;	166	config \|= XOR_DESCRIPTOR_SWAP;
167	else	167	#else
168	config &= ~XOR_DESCRIPTOR_SWAP;	168	config &= ~XOR_DESCRIPTOR_SWAP;
		169	#endif
169		170
170	writel_relaxed(config, XOR_CONFIG(chan));	171	writel_relaxed(config, XOR_CONFIG(chan));
171	chan->current_type = type;	172	chan->current_type = type;

drivers/dma/pl330.c+2−1

 			desc->txd.callback = last->txd.callback;
 			desc->txd.callback_param = last->txd.callback_param;
 		}
-		last->last = false;
+		desc->last = false;
 		dma_cookie_assign(&desc->txd);
 		desc->rqcfg.brst_len = 1;
 	desc->rqcfg.brst_len = get_burst_len(desc, len);
+	desc->bytes_requested = len;
 	desc->txd.flags = flags;

drivers/dma/virt-dma.c+6−13

@@ -29,7 +29,7 @@ dma_cookie_t vchan_tx_submit(struct dma_async_tx_descriptor *tx) · 28 unmodified lines
29	spin_lock_irqsave(&vc->lock, flags);	29	spin_lock_irqsave(&vc->lock, flags);
30	cookie = dma_cookie_assign(tx);	30	cookie = dma_cookie_assign(tx);
31		31
32	list_move_tail(&vd->node, &vc->desc_submitted);	32	list_add_tail(&vd->node, &vc->desc_submitted);
33	spin_unlock_irqrestore(&vc->lock, flags);	33	spin_unlock_irqrestore(&vc->lock, flags);
34		34
35	dev_dbg(vc->chan.device->dev, "vchan %p: txd %p[%x]: submitted\n",	35	dev_dbg(vc->chan.device->dev, "vchan %p: txd %p[%x]: submitted\n",
@@ -83,10 +83,8 @@ static void vchan_complete(unsigned long arg) · 47 unmodified lines
83	cb_data = vd->tx.callback_param;	83	cb_data = vd->tx.callback_param;
84		84
85	list_del(&vd->node);	85	list_del(&vd->node);
86	if (async_tx_test_ack(&vd->tx))	86
87	list_add(&vd->node, &vc->desc_allocated);	87	vc->desc_free(vd);
88	else
89	vc->desc_free(vd);
90		88
91	if (cb)	89	if (cb)
92	cb(cb_data);	90	cb(cb_data);
@@ -98,13 +96,9 @@ void vchan_dma_desc_free_list(struct virt_dma_chan vc, struct list_head head) · 5 unmodified lines
98	while (!list_empty(head)) {	96	while (!list_empty(head)) {
99	struct virt_dma_desc *vd = list_first_entry(head,	97	struct virt_dma_desc *vd = list_first_entry(head,
100	struct virt_dma_desc, node);	98	struct virt_dma_desc, node);
101	if (async_tx_test_ack(&vd->tx)) {	99	list_del(&vd->node);
102	list_move_tail(&vd->node, &vc->desc_allocated);	100	dev_dbg(vc->chan.device->dev, "txd %p: freeing\n", vd);
103	} else {	101	vc->desc_free(vd);
104	dev_dbg(vc->chan.device->dev, "txd %p: freeing\n", vd);
105	list_del(&vd->node);
106	vc->desc_free(vd);
107	}
108	}	102	}
109	}	103	}
110	EXPORT_SYMBOL_GPL(vchan_dma_desc_free_list);	104	EXPORT_SYMBOL_GPL(vchan_dma_desc_free_list);
@@ -114,7 +108,6 @@ void vchan_init(struct virt_dma_chan vc, struct dma_device dmadev) · 3 unmodified lines
114	dma_cookie_init(&vc->chan);	108	dma_cookie_init(&vc->chan);
115		109
116	spin_lock_init(&vc->lock);	110	spin_lock_init(&vc->lock);
117	INIT_LIST_HEAD(&vc->desc_allocated);
118	INIT_LIST_HEAD(&vc->desc_submitted);	111	INIT_LIST_HEAD(&vc->desc_submitted);
119	INIT_LIST_HEAD(&vc->desc_issued);	112	INIT_LIST_HEAD(&vc->desc_issued);
120	INIT_LIST_HEAD(&vc->desc_completed);	113	INIT_LIST_HEAD(&vc->desc_completed);

drivers/dma/virt-dma.h+1−12

 	spinlock_t lock;
 	/* protected by vc.lock */
-	struct list_head desc_allocated;
 	struct list_head desc_submitted;
 	struct list_head desc_issued;
 	struct list_head desc_completed;
 	struct virt_dma_desc *vd, unsigned long tx_flags)
 {
 	extern dma_cookie_t vchan_tx_submit(struct dma_async_tx_descriptor *);
-	unsigned long flags;
 	dma_async_tx_descriptor_init(&vd->tx, &vc->chan);
 	vd->tx.flags = tx_flags;
 	vd->tx.tx_submit = vchan_tx_submit;
-	spin_lock_irqsave(&vc->lock, flags);
-	list_add_tail(&vd->node, &vc->desc_allocated);
-	spin_unlock_irqrestore(&vc->lock, flags);
 	return &vd->tx;
 }
 }
 /**
- * vchan_get_all_descriptors - obtain all allocated, submitted and issued
+ * vchan_get_all_descriptors - obtain all submitted and issued descriptors
- *                             descriptors
  * vc: virtual channel to get descriptors from
  * head: list of descriptors found
  *
 static inline void vchan_get_all_descriptors(struct virt_dma_chan *vc,
 	struct list_head *head)
 {
-	list_splice_tail_init(&vc->desc_allocated, head);
 	list_splice_tail_init(&vc->desc_submitted, head);
 	list_splice_tail_init(&vc->desc_issued, head);
 	list_splice_tail_init(&vc->desc_completed, head);
 static inline void vchan_free_chan_resources(struct virt_dma_chan *vc)
 {
-	struct virt_dma_desc *vd;
 	unsigned long flags;
 	LIST_HEAD(head);
 	spin_lock_irqsave(&vc->lock, flags);
 	vchan_get_all_descriptors(vc, &head);
-	list_for_each_entry(vd, &head, node)
-		async_tx_clear_ack(&vd->tx);
 	spin_unlock_irqrestore(&vc->lock, flags);
 	vchan_dma_desc_free_list(vc, &head);

drivers/dma/xgene-dma.c+3−0

 #define XGENE_DMA_MEM_RAM_SHUTDOWN		0xD070
 #define XGENE_DMA_BLK_MEM_RDY			0xD074
 #define XGENE_DMA_BLK_MEM_RDY_VAL		0xFFFFFFFF
+#define XGENE_DMA_RING_CMD_SM_OFFSET		0x8000
 /* X-Gene SoC EFUSE csr register and bit defination */
 #define XGENE_SOC_JTAG1_SHADOW			0x18
 		return -ENOMEM;
 	}
+	pdma->csr_ring_cmd += XGENE_DMA_RING_CMD_SM_OFFSET;
 	/* Get efuse csr region */
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
 	if (!res) {

drivers/edac/ppc4xx_edac.c+1−1

@@ -920,7 +920,7 @@ static int ppc4xx_edac_init_csrows(struct mem_ctl_info *mci, u32 mcopt1) · 919 unmodified lines
920	*/	920	*/
921		921
922	for (row = 0; row < mci->nr_csrows; row++) {	922	for (row = 0; row < mci->nr_csrows; row++) {
923	struct csrow_info *csi = &mci->csrows[row];	923	struct csrow_info *csi = mci->csrows[row];
924		924
925	/*	925	/*
926	* Get the configuration settings for this	926	* Get the configuration settings for this

drivers/extcon/extcon-palmas.c+0−13

 	status = devm_extcon_dev_register(&pdev->dev, palmas_usb->edev);
 	if (status) {
 		dev_err(&pdev->dev, "failed to register extcon device\n");
-		kfree(palmas_usb->edev->name);
 		return status;
 	}
 		if (status < 0) {
 			dev_err(&pdev->dev, "can't get IRQ %d, err %d\n",
 					palmas_usb->id_irq, status);
-			kfree(palmas_usb->edev->name);
 			return status;
 		}
 	}
 		if (status < 0) {
 			dev_err(&pdev->dev, "can't get IRQ %d, err %d\n",
 					palmas_usb->vbus_irq, status);
-			kfree(palmas_usb->edev->name);
 			return status;
 		}
 	}
 	return 0;
 }
-static int palmas_usb_remove(struct platform_device *pdev)
-{
-	struct palmas_usb *palmas_usb = platform_get_drvdata(pdev);
-	kfree(palmas_usb->edev->name);
-	return 0;
-}
 #ifdef CONFIG_PM_SLEEP
 static int palmas_usb_suspend(struct device *dev)
 {
 static struct platform_driver palmas_usb_driver = {
 	.probe = palmas_usb_probe,
-	.remove = palmas_usb_remove,
 	.driver = {
 		.name = "palmas-usb",
 		.of_match_table = of_palmas_match_tbl,

drivers/extcon/extcon.c+44−17

@@ -124,25 +124,35 @@ static int find_cable_index_by_id(struct extcon_dev *edev, const unsigned int id · 123 unmodified lines
124	return -EINVAL;	124	return -EINVAL;
125	}	125	}
126		126
127	static int find_cable_index_by_name(struct extcon_dev edev, const char name)	127	static int find_cable_id_by_name(struct extcon_dev edev, const char name)
128	{	128	{
129	unsigned int id = EXTCON_NONE;	129	unsigned int id = -EINVAL;
130	int i = 0;	130	int i = 0;
131		131
132	if (edev->max_supported == 0)	132	/* Find the id of extcon cable */
133	return -EINVAL;
134
135	/* Find the the number of extcon cable */
136	while (extcon_name[i]) {	133	while (extcon_name[i]) {
137	if (!strncmp(extcon_name[i], name, CABLE_NAME_MAX)) {	134	if (!strncmp(extcon_name[i], name, CABLE_NAME_MAX)) {
138	id = i;	135	id = i;
139	break;	136	break;
140	}	137	}
		138	i++;
141	}	139	}
142		140
143	if (id == EXTCON_NONE)	141	return id;
		142	}
		143
		144	static int find_cable_index_by_name(struct extcon_dev edev, const char name)
		145	{
		146	unsigned int id;
		147
		148	if (edev->max_supported == 0)
144	return -EINVAL;	149	return -EINVAL;
145		150
		151	/* Find the the number of extcon cable */
		152	id = find_cable_id_by_name(edev, name);
		153	if (id < 0)
		154	return id;
		155
146	return find_cable_index_by_id(edev, id);	156	return find_cable_index_by_id(edev, id);
147	}	157	}
148		158
@@ -228,9 +238,11 @@ static ssize_t cable_state_show(struct device *dev, · 79 unmodified lines
228	struct extcon_cable *cable = container_of(attr, struct extcon_cable,	238	struct extcon_cable *cable = container_of(attr, struct extcon_cable,
229	attr_state);	239	attr_state);
230		240
		241	int i = cable->cable_index;
		242
231	return sprintf(buf, "%d\n",	243	return sprintf(buf, "%d\n",
232	extcon_get_cable_state_(cable->edev,	244	extcon_get_cable_state_(cable->edev,
233	cable->cable_index));	245	cable->edev->supported_cable[i]));
234	}	246	}
235		247
236	/**	248	/**
@@ -263,20 +275,25 @@ int extcon_update_state(struct extcon_dev *edev, u32 mask, u32 state) · 26 unmodified lines
263	spin_lock_irqsave(&edev->lock, flags);	275	spin_lock_irqsave(&edev->lock, flags);
264		276
265	if (edev->state != ((edev->state & ~mask) \| (state & mask))) {	277	if (edev->state != ((edev->state & ~mask) \| (state & mask))) {
		278	u32 old_state;
		279
266	if (check_mutually_exclusive(edev, (edev->state & ~mask) \|	280	if (check_mutually_exclusive(edev, (edev->state & ~mask) \|
267	(state & mask))) {	281	(state & mask))) {
268	spin_unlock_irqrestore(&edev->lock, flags);	282	spin_unlock_irqrestore(&edev->lock, flags);
269	return -EPERM;	283	return -EPERM;
270	}	284	}
271		285
272	for (index = 0; index < edev->max_supported; index++) {	286	old_state = edev->state;
273	if (is_extcon_changed(edev->state, state, index, &attached))
274	raw_notifier_call_chain(&edev->nh[index], attached, edev);
275	}
276
277	edev->state &= ~mask;	287	edev->state &= ~mask;
278	edev->state \|= state & mask;	288	edev->state \|= state & mask;
279		289
		290	for (index = 0; index < edev->max_supported; index++) {
		291	if (is_extcon_changed(old_state, edev->state, index,
		292	&attached))
		293	raw_notifier_call_chain(&edev->nh[index],
		294	attached, edev);
		295	}
		296
280	/* This could be in interrupt handler */	297	/* This could be in interrupt handler */
281	prop_buf = (char *)get_zeroed_page(GFP_ATOMIC);	298	prop_buf = (char *)get_zeroed_page(GFP_ATOMIC);
282	if (prop_buf) {	299	if (prop_buf) {
@@ -361,8 +378,13 @@ EXPORT_SYMBOL_GPL(extcon_get_cable_state_); · 78 unmodified lines
361	*/	378	*/
362	int extcon_get_cable_state(struct extcon_dev edev, const char cable_name)	379	int extcon_get_cable_state(struct extcon_dev edev, const char cable_name)
363	{	380	{
364	return extcon_get_cable_state_(edev, find_cable_index_by_name	381	unsigned int id;
365	(edev, cable_name));	382
		383	id = find_cable_id_by_name(edev, cable_name);
		384	if (id < 0)
		385	return id;
		386
		387	return extcon_get_cable_state_(edev, id);
366	}	388	}
367	EXPORT_SYMBOL_GPL(extcon_get_cable_state);	389	EXPORT_SYMBOL_GPL(extcon_get_cable_state);
368		390
@@ -404,8 +426,13 @@ EXPORT_SYMBOL_GPL(extcon_set_cable_state_); · 35 unmodified lines
404	int extcon_set_cable_state(struct extcon_dev *edev,	426	int extcon_set_cable_state(struct extcon_dev *edev,
405	const char *cable_name, bool cable_state)	427	const char *cable_name, bool cable_state)
406	{	428	{
407	return extcon_set_cable_state_(edev, find_cable_index_by_name	429	unsigned int id;
408	(edev, cable_name), cable_state);	430
		431	id = find_cable_id_by_name(edev, cable_name);
		432	if (id < 0)
		433	return id;
		434
		435	return extcon_set_cable_state_(edev, id, cable_state);
409	}	436	}
410	EXPORT_SYMBOL_GPL(extcon_set_cable_state);	437	EXPORT_SYMBOL_GPL(extcon_set_cable_state);
411		438

drivers/firmware/efi/cper.c+12−3

 	return ret;
 }
-static void cper_print_mem(const char *pfx, const struct cper_sec_mem_err *mem)
+static void cper_print_mem(const char *pfx, const struct cper_sec_mem_err *mem,
+	int len)
 {
 	struct cper_mem_err_compact cmem;
+	/* Don't trust UEFI 2.1/2.2 structure with bad validation bits */
+	if (len == sizeof(struct cper_sec_mem_err_old) &&
+	    (mem->validation_bits & ~(CPER_MEM_VALID_RANK_NUMBER - 1))) {
+		pr_err(FW_WARN "valid bits set for fields beyond structure\n");
+		return;
+	}
 	if (mem->validation_bits & CPER_MEM_VALID_ERROR_STATUS)
 		printk("%s""error_status: 0x%016llx\n", pfx, mem->error_status);
 	if (mem->validation_bits & CPER_MEM_VALID_PA)
 	} else if (!uuid_le_cmp(*sec_type, CPER_SEC_PLATFORM_MEM)) {
 		struct cper_sec_mem_err *mem_err = (void *)(gdata + 1);
 		printk("%s""section_type: memory error\n", newpfx);
-		if (gdata->error_data_length >= sizeof(*mem_err))
+		if (gdata->error_data_length >=
-			cper_print_mem(newpfx, mem_err);
+		    sizeof(struct cper_sec_mem_err_old))
+			cper_print_mem(newpfx, mem_err,
+				       gdata->error_data_length);
 		else
 			goto err_section_too_small;
 	} else if (!uuid_le_cmp(*sec_type, CPER_SEC_PCIE)) {

drivers/firmware/efi/efi.c+5−0

 static int __init parse_efi_cmdline(char *str)
 {
+	if (!str) {
+		pr_warn("need at least one option\n");
+		return -EINVAL;
+	}
 	if (parse_option_str(str, "noruntime"))
 		disable_runtime = true;

drivers/gpu/drm/amd/amdgpu/amdgpu.h+15−1

 	uint32_t			me_feature_version;
 	uint32_t			ce_feature_version;
 	uint32_t			pfp_feature_version;
+	uint32_t			rlc_feature_version;
+	uint32_t			mec_feature_version;
+	uint32_t			mec2_feature_version;
 	struct amdgpu_ring		gfx_ring[AMDGPU_MAX_GFX_RINGS];
 	unsigned			num_gfx_rings;
 	struct amdgpu_ring		compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
 #define AMDGPU_MAX_VCE_HANDLES	16
 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
+#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
+#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
 struct amdgpu_vce {
 	struct amdgpu_bo	*vcpu_bo;
 	uint64_t		gpu_addr;
 	const struct firmware	*fw;	/* VCE firmware */
 	struct amdgpu_ring	ring[AMDGPU_MAX_VCE_RINGS];
 	struct amdgpu_irq_src	irq;
+	unsigned		harvest_config;
 };
 /*
 	/* SDMA firmware */
 	const struct firmware	*fw;
 	uint32_t		fw_version;
+	uint32_t		feature_version;
 	struct amdgpu_ring	ring;
 };
 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
+struct amdgpu_ip_block_status {
+	bool valid;
+	bool sw;
+	bool hw;
+};
 struct amdgpu_device {
 	struct device			*dev;
 	struct drm_device		*ddev;
 	const struct amdgpu_ip_block_version *ip_blocks;
 	int				num_ip_blocks;
-	bool				*ip_block_enabled;
+	struct amdgpu_ip_block_status	*ip_block_status;
 	struct mutex	mn_lock;
 	DECLARE_HASHTABLE(mn_hash, 7);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+22−16

 		return -EINVAL;
 	}
-	adev->ip_block_enabled = kcalloc(adev->num_ip_blocks, sizeof(bool), GFP_KERNEL);
+	adev->ip_block_status = kcalloc(adev->num_ip_blocks,
-	if (adev->ip_block_enabled == NULL)
+					sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
+	if (adev->ip_block_status == NULL)
 		return -ENOMEM;
 	if (adev->ip_blocks == NULL) {
 	for (i = 0; i < adev->num_ip_blocks; i++) {
 		if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
 			DRM_ERROR("disabled ip block: %d\n", i);
-			adev->ip_block_enabled[i] = false;
+			adev->ip_block_status[i].valid = false;
 		} else {
 			if (adev->ip_blocks[i].funcs->early_init) {
 				r = adev->ip_blocks[i].funcs->early_init((void *)adev);
 				if (r == -ENOENT)
-					adev->ip_block_enabled[i] = false;
+					adev->ip_block_status[i].valid = false;
 				else if (r)
 					return r;
 				else
-					adev->ip_block_enabled[i] = true;
+					adev->ip_block_status[i].valid = true;
 			} else {
-				adev->ip_block_enabled[i] = true;
+				adev->ip_block_status[i].valid = true;
 			}
 		}
 	}
 	int i, r;
 	for (i = 0; i < adev->num_ip_blocks; i++) {
-		if (!adev->ip_block_enabled[i])
+		if (!adev->ip_block_status[i].valid)
 			continue;
 		r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
 		if (r)
 			return r;
+		adev->ip_block_status[i].sw = true;
 		/* need to do gmc hw init early so we can allocate gpu mem */
 		if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
 			r = amdgpu_vram_scratch_init(adev);
 			r = amdgpu_wb_init(adev);
 			if (r)
 				return r;
+			adev->ip_block_status[i].hw = true;
 		}
 	}
 	for (i = 0; i < adev->num_ip_blocks; i++) {
-		if (!adev->ip_block_enabled[i])
+		if (!adev->ip_block_status[i].sw)
 			continue;
 		/* gmc hw init is done early */
 		if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
 		r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
 		if (r)
 			return r;
+		adev->ip_block_status[i].hw = true;
 	}
 	return 0;
 	int i = 0, r;
 	for (i = 0; i < adev->num_ip_blocks; i++) {
-		if (!adev->ip_block_enabled[i])
+		if (!adev->ip_block_status[i].valid)
 			continue;
 		/* enable clockgating to save power */
 		r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
 	int i, r;
 	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
-		if (!adev->ip_block_enabled[i])
+		if (!adev->ip_block_status[i].hw)
 			continue;
 		if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
 			amdgpu_wb_fini(adev);
 			return r;
 		r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
 		/* XXX handle errors */
+		adev->ip_block_status[i].hw = false;
 	}
 	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
-		if (!adev->ip_block_enabled[i])
+		if (!adev->ip_block_status[i].sw)
 			continue;
 		r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
 		/* XXX handle errors */
-		adev->ip_block_enabled[i] = false;
+		adev->ip_block_status[i].sw = false;
+		adev->ip_block_status[i].valid = false;
 	}
 	return 0;
 	int i, r;
 	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
-		if (!adev->ip_block_enabled[i])
+		if (!adev->ip_block_status[i].valid)
 			continue;
 		/* ungate blocks so that suspend can properly shut them down */
 		r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
 	int i, r;
 	for (i = 0; i < adev->num_ip_blocks; i++) {
-		if (!adev->ip_block_enabled[i])
+		if (!adev->ip_block_status[i].valid)
 			continue;
 		r = adev->ip_blocks[i].funcs->resume(adev);
 		if (r)
 	amdgpu_fence_driver_fini(adev);
 	amdgpu_fbdev_fini(adev);
 	r = amdgpu_fini(adev);
-	kfree(adev->ip_block_enabled);
+	kfree(adev->ip_block_status);
-	adev->ip_block_enabled = NULL;
+	adev->ip_block_status = NULL;
 	adev->accel_working = false;
 	/* free i2c buses */
 	amdgpu_i2c_fini(adev);

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c+5−3

@@ -449,7 +449,7 @@ out: · 448 unmodified lines
449	* vital here, so they are not reported back to userspace.	449	* vital here, so they are not reported back to userspace.
450	*/	450	*/
451	static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,	451	static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
452	struct amdgpu_bo_va *bo_va)	452	struct amdgpu_bo_va *bo_va, uint32_t operation)
453	{	453	{
454	struct ttm_validate_buffer tv, *entry;	454	struct ttm_validate_buffer tv, *entry;
455	struct amdgpu_bo_list_entry *vm_bos;	455	struct amdgpu_bo_list_entry *vm_bos;
@@ -485,7 +485,9 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, · 29 unmodified lines
485	if (r)	485	if (r)
486	goto error_unlock;	486	goto error_unlock;
487		487
488	r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem);	488
		489	if (operation == AMDGPU_VA_OP_MAP)
		490	r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem);
489		491
490	error_unlock:	492	error_unlock:
491	mutex_unlock(&bo_va->vm->mutex);	493	mutex_unlock(&bo_va->vm->mutex);
@@ -580,7 +582,7 @@ int amdgpu_gem_va_ioctl(struct drm_device dev, void data, · 88 unmodified lines
580	}	582	}
581		583
582	if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE))	584	if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE))
583	amdgpu_gem_va_update_vm(adev, bo_va);	585	amdgpu_gem_va_update_vm(adev, bo_va, args->operation);
584		586
585	drm_gem_object_unreference_unlocked(gobj);	587	drm_gem_object_unreference_unlocked(gobj);
586	return r;	588	return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c+8−8

@@ -180,16 +180,16 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, · 179 unmodified lines
180	if (vm) {	180	if (vm) {
181	/* do context switch */	181	/* do context switch */
182	amdgpu_vm_flush(ring, vm, ib->sync.last_vm_update);	182	amdgpu_vm_flush(ring, vm, ib->sync.last_vm_update);
183	}
184		183
185	if (vm && ring->funcs->emit_gds_switch)	184	if (ring->funcs->emit_gds_switch)
186	amdgpu_ring_emit_gds_switch(ring, ib->vm->ids[ring->idx].id,	185	amdgpu_ring_emit_gds_switch(ring, ib->vm->ids[ring->idx].id,
187	ib->gds_base, ib->gds_size,	186	ib->gds_base, ib->gds_size,
188	ib->gws_base, ib->gws_size,	187	ib->gws_base, ib->gws_size,
189	ib->oa_base, ib->oa_size);	188	ib->oa_base, ib->oa_size);
190		189
191	if (ring->funcs->emit_hdp_flush)	190	if (ring->funcs->emit_hdp_flush)
192	amdgpu_ring_emit_hdp_flush(ring);	191	amdgpu_ring_emit_hdp_flush(ring);
		192	}
193		193
194	old_ctx = ring->current_ctx;	194	old_ctx = ring->current_ctx;
195	for (i = 0; i < num_ibs; ++i) {	195	for (i = 0; i < num_ibs; ++i) {

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c+11−9

 		for (i = 0; i < adev->num_ip_blocks; i++) {
 			if (adev->ip_blocks[i].type == type &&
-			    adev->ip_block_enabled[i]) {
+			    adev->ip_block_status[i].valid) {
 				ip.hw_ip_version_major = adev->ip_blocks[i].major;
 				ip.hw_ip_version_minor = adev->ip_blocks[i].minor;
 				ip.capabilities_flags = 0;
 		for (i = 0; i < adev->num_ip_blocks; i++)
 			if (adev->ip_blocks[i].type == type &&
-			    adev->ip_block_enabled[i] &&
+			    adev->ip_block_status[i].valid &&
 			    count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 				count++;
 			break;
 		case AMDGPU_INFO_FW_GFX_RLC:
 			fw_info.ver = adev->gfx.rlc_fw_version;
-			fw_info.feature = 0;
+			fw_info.feature = adev->gfx.rlc_feature_version;
 			break;
 		case AMDGPU_INFO_FW_GFX_MEC:
-			if (info->query_fw.index == 0)
+			if (info->query_fw.index == 0) {
 				fw_info.ver = adev->gfx.mec_fw_version;
-			else if (info->query_fw.index == 1)
+				fw_info.feature = adev->gfx.mec_feature_version;
+			} else if (info->query_fw.index == 1) {
 				fw_info.ver = adev->gfx.mec2_fw_version;
-			else
+				fw_info.feature = adev->gfx.mec2_feature_version;
+			} else
 				return -EINVAL;
-			fw_info.feature = 0;
 			break;
 		case AMDGPU_INFO_FW_SMC:
 			fw_info.ver = adev->pm.fw_version;
 			if (info->query_fw.index >= 2)
 				return -EINVAL;
 			fw_info.ver = adev->sdma[info->query_fw.index].fw_version;
-			fw_info.feature = 0;
+			fw_info.feature = adev->sdma[info->query_fw.index].feature_version;
 			break;
 		default:
 			return -EINVAL;
 		return n ? -EFAULT : 0;
 	}
 	case AMDGPU_INFO_DEV_INFO: {
-		struct drm_amdgpu_info_device dev_info;
+		struct drm_amdgpu_info_device dev_info = {};
 		struct amdgpu_cu_info cu_info;
 		dev_info.device_id = dev->pdev->device;
 		memcpy(&dev_info.cu_bitmap[0], &cu_info.bitmap[0], sizeof(cu_info.bitmap));
 		dev_info.vram_type = adev->mc.vram_type;
 		dev_info.vram_bit_width = adev->mc.vram_width;
+		dev_info.vce_harvest_config = adev->vce.harvest_config;
 		return copy_to_user(out, &dev_info,
 				    min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c+14−3

 	unsigned height_in_mb = ALIGN(height / 16, 2);
 	unsigned fs_in_mb = width_in_mb * height_in_mb;
-	unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
+	unsigned image_size, tmp, min_dpb_size, num_dpb_buffer, min_ctx_size;
 	image_size = width * height;
 	image_size += image_size / 2;
 		num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
 		min_dpb_size = image_size * num_dpb_buffer;
+		min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
+					   * 16 * num_dpb_buffer + 52 * 1024;
 		break;
 	default:
 	buf_sizes[0x1] = dpb_size;
 	buf_sizes[0x2] = image_size;
+	buf_sizes[0x4] = min_ctx_size;
 	return 0;
 }
 			return -EINVAL;
 		}
+	} else if (cmd == 0x206) {
+		if ((end - start) < ctx->buf_sizes[4]) {
+			DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
+					  (unsigned)(end - start),
+					  ctx->buf_sizes[4]);
+			return -EINVAL;
+		}
 	} else if ((cmd != 0x100) && (cmd != 0x204)) {
 		DRM_ERROR("invalid UVD command %X!\n", cmd);
 		return -EINVAL;
 	struct amdgpu_uvd_cs_ctx ctx = {};
 	unsigned buf_sizes[] = {
 		[0x00000000]	=	2048,
-		[0x00000001]	=	32 * 1024 * 1024,
+		[0x00000001]	=	0xFFFFFFFF,
-		[0x00000002]	=	2048 * 1152 * 3,
+		[0x00000002]	=	0xFFFFFFFF,
 		[0x00000003]	=	2048,
+		[0x00000004]	=	0xFFFFFFFF,
 	};
 	struct amdgpu_ib *ib = &parser->ibs[ib_idx];
 	int r;

drivers/gpu/drm/amd/amdgpu/cik_sdma.c+1−0

@@ -500,6 +500,7 @@ static int cik_sdma_load_microcode(struct amdgpu_device *adev) · 499 unmodified lines
500	amdgpu_ucode_print_sdma_hdr(&hdr->header);	500	amdgpu_ucode_print_sdma_hdr(&hdr->header);
501	fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;	501	fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
502	adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);	502	adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
		503	adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
503	fw_data = (const __le32 *)	504	fw_data = (const __le32 *)
504	(adev->sdma[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));	505	(adev->sdma[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
505	WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);	506	WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);

drivers/gpu/drm/amd/amdgpu/cz_dpm.c+54−16

@@ -494,29 +494,67 @@ static void cz_dpm_fini(struct amdgpu_device *adev) · 493 unmodified lines
494	amdgpu_free_extended_power_table(adev);	494	amdgpu_free_extended_power_table(adev);
495	}	495	}
496		496
		497	#define ixSMUSVI_NB_CURRENTVID 0xD8230044
		498	#define CURRENT_NB_VID_MASK 0xff000000
		499	#define CURRENT_NB_VID__SHIFT 24
		500	#define ixSMUSVI_GFX_CURRENTVID 0xD8230048
		501	#define CURRENT_GFX_VID_MASK 0xff000000
		502	#define CURRENT_GFX_VID__SHIFT 24
		503
497	static void	504	static void
498	cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,	505	cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
499	struct seq_file *m)	506	struct seq_file *m)
500	{	507	{
		508	struct cz_power_info *pi = cz_get_pi(adev);
501	struct amdgpu_clock_voltage_dependency_table *table =	509	struct amdgpu_clock_voltage_dependency_table *table =
502	&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;	510	&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
503	u32 current_index =	511	struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
504	(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &	512	&adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
505	TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>	513	struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
506	TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;	514	&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
507	u32 sclk, tmp;	515	u32 sclk_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX),
508	u16 vddc;	516	TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
509		517	u32 uvd_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
510	if (current_index >= NUM_SCLK_LEVELS) {	518	TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
511	seq_printf(m, "invalid dpm profile %d\n", current_index);	519	u32 vce_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
		520	TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
		521	u32 sclk, vclk, dclk, ecclk, tmp;
		522	u16 vddnb, vddgfx;
		523
		524	if (sclk_index >= NUM_SCLK_LEVELS) {
		525	seq_printf(m, "invalid sclk dpm profile %d\n", sclk_index);
512	} else {	526	} else {
513	sclk = table->entries[current_index].clk;	527	sclk = table->entries[sclk_index].clk;
514	tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) &	528	seq_printf(m, "%u sclk: %u\n", sclk_index, sclk);
515	SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>	529	}
516	SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT;	530
517	vddc = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);	531	tmp = (RREG32_SMC(ixSMUSVI_NB_CURRENTVID) &
518	seq_printf(m, "power level %d sclk: %u vddc: %u\n",	532	CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
519	current_index, sclk, vddc);	533	vddnb = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
		534	tmp = (RREG32_SMC(ixSMUSVI_GFX_CURRENTVID) &
		535	CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
		536	vddgfx = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
		537	seq_printf(m, "vddnb: %u vddgfx: %u\n", vddnb, vddgfx);
		538
		539	seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");
		540	if (!pi->uvd_power_gated) {
		541	if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
		542	seq_printf(m, "invalid uvd dpm level %d\n", uvd_index);
		543	} else {
		544	vclk = uvd_table->entries[uvd_index].vclk;
		545	dclk = uvd_table->entries[uvd_index].dclk;
		546	seq_printf(m, "%u uvd vclk: %u dclk: %u\n", uvd_index, vclk, dclk);
		547	}
		548	}
		549
		550	seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en");
		551	if (!pi->vce_power_gated) {
		552	if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
		553	seq_printf(m, "invalid vce dpm level %d\n", vce_index);
		554	} else {
		555	ecclk = vce_table->entries[vce_index].ecclk;
		556	seq_printf(m, "%u vce ecclk: %u\n", vce_index, ecclk);
		557	}
520	}	558	}
521	}	559	}
522		560

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c+4−0

 	struct drm_device *dev = crtc->dev;
 	struct amdgpu_device *adev = dev->dev_private;
 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
+	unsigned type;
 	switch (mode) {
 	case DRM_MODE_DPMS_ON:
 		dce_v10_0_vga_enable(crtc, true);
 		amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
 		dce_v10_0_vga_enable(crtc, false);
+		/* Make sure VBLANK interrupt is still enabled */
+		type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
+		amdgpu_irq_update(adev, &adev->crtc_irq, type);
 		drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
 		dce_v10_0_crtc_load_lut(crtc);
 		break;

drivers/gpu/drm/amd/amdgpu/dce_v11_0.c+4−0

 	struct drm_device *dev = crtc->dev;
 	struct amdgpu_device *adev = dev->dev_private;
 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
+	unsigned type;
 	switch (mode) {
 	case DRM_MODE_DPMS_ON:
 		dce_v11_0_vga_enable(crtc, true);
 		amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
 		dce_v11_0_vga_enable(crtc, false);
+		/* Make sure VBLANK interrupt is still enabled */
+		type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
+		amdgpu_irq_update(adev, &adev->crtc_irq, type);
 		drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
 		dce_v11_0_crtc_load_lut(crtc);
 		break;

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c+42−12

  * sheduling on the ring.  This function schedules the IB
  * on the gfx ring for execution by the GPU.
  */
-static void gfx_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
+static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 				  struct amdgpu_ib *ib)
 {
 	bool need_ctx_switch = ring->current_ctx != ib->ctx;
 	u32 next_rptr = ring->wptr + 5;
 	/* drop the CE preamble IB for the same context */
-	if ((ring->type == AMDGPU_RING_TYPE_GFX) &&
+	if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
-	    (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
-	    !need_ctx_switch)
 		return;
-	if (ring->type == AMDGPU_RING_TYPE_COMPUTE)
+	if (need_ctx_switch)
-		control |= INDIRECT_BUFFER_VALID;
-	if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX)
 		next_rptr += 2;
 	next_rptr += 4;
 	amdgpu_ring_write(ring, next_rptr);
 	/* insert SWITCH_BUFFER packet before first IB in the ring frame */
-	if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) {
+	if (need_ctx_switch) {
 		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
 		amdgpu_ring_write(ring, 0);
 	}
 	amdgpu_ring_write(ring, control);
 }
+static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
+				  struct amdgpu_ib *ib)
+{
+	u32 header, control = 0;
+	u32 next_rptr = ring->wptr + 5;
+	control |= INDIRECT_BUFFER_VALID;
+	next_rptr += 4;
+	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+	amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
+	amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
+	amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
+	amdgpu_ring_write(ring, next_rptr);
+	header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
+	control |= ib->length_dw |
+			   (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
+	amdgpu_ring_write(ring, header);
+	amdgpu_ring_write(ring,
+#ifdef __BIG_ENDIAN
+					  (2 << 0) |
+#endif
+					  (ib->gpu_addr & 0xFFFFFFFC));
+	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
+	amdgpu_ring_write(ring, control);
+}
 /**
  * gfx_v7_0_ring_test_ib - basic ring IB test
  *
 	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 	amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
 	adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
+	adev->gfx.mec_feature_version = le32_to_cpu(
+					mec_hdr->ucode_feature_version);
 	gfx_v7_0_cp_compute_enable(adev, false);
 		mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
 		amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
 		adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
+		adev->gfx.mec2_feature_version = le32_to_cpu(
+				mec2_hdr->ucode_feature_version);
 		/* MEC2 */
 		fw_data = (const __le32 *)
 	hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
 	amdgpu_ucode_print_rlc_hdr(&hdr->header);
 	adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
+	adev->gfx.rlc_feature_version = le32_to_cpu(
+					hdr->ucode_feature_version);
 	gfx_v7_0_rlc_stop(adev);
 		dev_info(adev->dev, "  CP_HPD_EOP_CONTROL=0x%08X\n",
 			 RREG32(mmCP_HPD_EOP_CONTROL));
-		for (queue = 0; queue < 8; i++) {
+		for (queue = 0; queue < 8; queue++) {
 			cik_srbm_select(adev, me, pipe, queue, 0);
 			dev_info(adev->dev, "  queue: %d\n", queue);
 			dev_info(adev->dev, "  CP_PQ_WPTR_POLL_CNTL=0x%08X\n",
 	.get_wptr = gfx_v7_0_ring_get_wptr_gfx,
 	.set_wptr = gfx_v7_0_ring_set_wptr_gfx,
 	.parse_cs = NULL,
-	.emit_ib = gfx_v7_0_ring_emit_ib,
+	.emit_ib = gfx_v7_0_ring_emit_ib_gfx,
 	.emit_fence = gfx_v7_0_ring_emit_fence_gfx,
 	.emit_semaphore = gfx_v7_0_ring_emit_semaphore,
 	.emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
 	.get_wptr = gfx_v7_0_ring_get_wptr_compute,
 	.set_wptr = gfx_v7_0_ring_set_wptr_compute,
 	.parse_cs = NULL,
-	.emit_ib = gfx_v7_0_ring_emit_ib,
+	.emit_ib = gfx_v7_0_ring_emit_ib_compute,
 	.emit_fence = gfx_v7_0_ring_emit_fence_compute,
 	.emit_semaphore = gfx_v7_0_ring_emit_semaphore,
 	.emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c+60−25

 	int err;
 	struct amdgpu_firmware_info *info = NULL;
 	const struct common_firmware_header *header = NULL;
+	const struct gfx_firmware_header_v1_0 *cp_hdr;
 	DRM_DEBUG("\n");
 	err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 	if (err)
 		goto out;
+	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
+	adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+	adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
 	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 	err = amdgpu_ucode_validate(adev->gfx.me_fw);
 	if (err)
 		goto out;
+	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
+	adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+	adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
 	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 	err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 	if (err)
 		goto out;
+	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
+	adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+	adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 	err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 	if (err)
 		goto out;
 	err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
+	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
+	adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+	adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 	err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 	if (err)
 		goto out;
+	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
+	adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+	adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 	err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 		err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 		if (err)
 			goto out;
+		cp_hdr = (const struct gfx_firmware_header_v1_0 *)
+						adev->gfx.mec2_fw->data;
+		adev->gfx.mec2_fw_version = le32_to_cpu(
+						cp_hdr->header.ucode_version);
+		adev->gfx.mec2_feature_version = le32_to_cpu(
+						cp_hdr->ucode_feature_version);
 	} else {
 		err = 0;
 		adev->gfx.mec2_fw = NULL;
 		adev->gfx.config.max_shader_engines = 1;
 		adev->gfx.config.max_tile_pipes = 2;
 		adev->gfx.config.max_sh_per_se = 1;
+		adev->gfx.config.max_backends_per_se = 2;
 		switch (adev->pdev->revision) {
 		case 0xc4:
 		case 0xcc:
 			/* B10 */
 			adev->gfx.config.max_cu_per_sh = 8;
-			adev->gfx.config.max_backends_per_se = 2;
 			break;
 		case 0xc5:
 		case 0x81:
 		case 0xcd:
 			/* B8 */
 			adev->gfx.config.max_cu_per_sh = 6;
-			adev->gfx.config.max_backends_per_se = 2;
 			break;
 		case 0xc6:
 		case 0xca:
 		case 0xce:
 			/* B6 */
 			adev->gfx.config.max_cu_per_sh = 6;
-			adev->gfx.config.max_backends_per_se = 2;
 			break;
 		case 0xc7:
 		case 0x87:
 		default:
 			/* B4 */
 			adev->gfx.config.max_cu_per_sh = 4;
-			adev->gfx.config.max_backends_per_se = 1;
 			break;
 		}
 	hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 	amdgpu_ucode_print_rlc_hdr(&hdr->header);
-	adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
 			   le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 	amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
 	amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
 	amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
-	adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
-	adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
-	adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
-	adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
-	adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
-	adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
 	gfx_v8_0_cp_gfx_enable(adev, false);
 	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 	amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
-	adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
 	fw_data = (const __le32 *)
 		(adev->gfx.mec_fw->data +
 		mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
 		amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
-		adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
 		fw_data = (const __le32 *)
 			(adev->gfx.mec2_fw->data +
 				WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
 				       AMDGPU_DOORBELL_KIQ << 2);
 				WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
-						0x7FFFF << 2);
+				       AMDGPU_DOORBELL_MEC_RING7 << 2);
 			}
 			tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
 			tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 	amdgpu_ring_write(ring, 0x20); /* poll interval */
 }
-static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring,
+static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 				  struct amdgpu_ib *ib)
 {
 	bool need_ctx_switch = ring->current_ctx != ib->ctx;
 	u32 next_rptr = ring->wptr + 5;
 	/* drop the CE preamble IB for the same context */
-	if ((ring->type == AMDGPU_RING_TYPE_GFX) &&
+	if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
-	    (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
-	    !need_ctx_switch)
 		return;
-	if (ring->type == AMDGPU_RING_TYPE_COMPUTE)
+	if (need_ctx_switch)
-		control |= INDIRECT_BUFFER_VALID;
-	if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX)
 		next_rptr += 2;
 	next_rptr += 4;
 	amdgpu_ring_write(ring, next_rptr);
 	/* insert SWITCH_BUFFER packet before first IB in the ring frame */
-	if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) {
+	if (need_ctx_switch) {
 		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
 		amdgpu_ring_write(ring, 0);
 	}
 	amdgpu_ring_write(ring, control);
 }
+static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
+				  struct amdgpu_ib *ib)
+{
+	u32 header, control = 0;
+	u32 next_rptr = ring->wptr + 5;
+	control |= INDIRECT_BUFFER_VALID;
+	next_rptr += 4;
+	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+	amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
+	amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
+	amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
+	amdgpu_ring_write(ring, next_rptr);
+	header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
+	control |= ib->length_dw |
+			   (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
+	amdgpu_ring_write(ring, header);
+	amdgpu_ring_write(ring,
+#ifdef __BIG_ENDIAN
+					  (2 << 0) |
+#endif
+					  (ib->gpu_addr & 0xFFFFFFFC));
+	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
+	amdgpu_ring_write(ring, control);
+}
 static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
 					 u64 seq, unsigned flags)
 {
 	.get_wptr = gfx_v8_0_ring_get_wptr_gfx,
 	.set_wptr = gfx_v8_0_ring_set_wptr_gfx,
 	.parse_cs = NULL,
-	.emit_ib = gfx_v8_0_ring_emit_ib,
+	.emit_ib = gfx_v8_0_ring_emit_ib_gfx,
 	.emit_fence = gfx_v8_0_ring_emit_fence_gfx,
 	.emit_semaphore = gfx_v8_0_ring_emit_semaphore,
 	.emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
 	.get_wptr = gfx_v8_0_ring_get_wptr_compute,
 	.set_wptr = gfx_v8_0_ring_set_wptr_compute,
 	.parse_cs = NULL,
-	.emit_ib = gfx_v8_0_ring_emit_ib,
+	.emit_ib = gfx_v8_0_ring_emit_ib_compute,
 	.emit_fence = gfx_v8_0_ring_emit_fence_compute,
 	.emit_semaphore = gfx_v8_0_ring_emit_semaphore,
 	.emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c+4−2

 	int err, i;
 	struct amdgpu_firmware_info *info = NULL;
 	const struct common_firmware_header *header = NULL;
+	const struct sdma_firmware_header_v1_0 *hdr;
 	DRM_DEBUG("\n");
 		err = amdgpu_ucode_validate(adev->sdma[i].fw);
 		if (err)
 			goto out;
+		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
+		adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
+		adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 		if (adev->firmware.smu_load) {
 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 			hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
 			amdgpu_ucode_print_sdma_hdr(&hdr->header);
 			fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
-			adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 			fw_data = (const __le32 *)
 				(adev->sdma[i].fw->data +
 				 le32_to_cpu(hdr->header.ucode_array_offset_bytes));

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c+4−2

 	int err, i;
 	struct amdgpu_firmware_info *info = NULL;
 	const struct common_firmware_header *header = NULL;
+	const struct sdma_firmware_header_v1_0 *hdr;
 	DRM_DEBUG("\n");
 		err = amdgpu_ucode_validate(adev->sdma[i].fw);
 		if (err)
 			goto out;
+		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
+		adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
+		adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 		if (adev->firmware.smu_load) {
 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
 		amdgpu_ucode_print_sdma_hdr(&hdr->header);
 		fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
-		adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 		fw_data = (const __le32 *)
 			(adev->sdma[i].fw->data +
 				le32_to_cpu(hdr->header.ucode_array_offset_bytes));

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c+48−0

@@ -35,6 +35,8 @@ · 34 unmodified lines
35	#include "oss/oss_2_0_d.h"	35	#include "oss/oss_2_0_d.h"
36	#include "oss/oss_2_0_sh_mask.h"	36	#include "oss/oss_2_0_sh_mask.h"
37	#include "gca/gfx_8_0_d.h"	37	#include "gca/gfx_8_0_d.h"
		38	#include "smu/smu_7_1_2_d.h"
		39	#include "smu/smu_7_1_2_sh_mask.h"
38		40
39	#define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04	41	#define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04
40	#define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10	42	#define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10
@@ -112,6 +114,10 @@ static int vce_v3_0_start(struct amdgpu_device *adev) · 71 unmodified lines
112		114
113	mutex_lock(&adev->grbm_idx_mutex);	115	mutex_lock(&adev->grbm_idx_mutex);
114	for (idx = 0; idx < 2; ++idx) {	116	for (idx = 0; idx < 2; ++idx) {
		117
		118	if (adev->vce.harvest_config & (1 << idx))
		119	continue;
		120
115	if(idx == 0)	121	if(idx == 0)
116	WREG32_P(mmGRBM_GFX_INDEX, 0,	122	WREG32_P(mmGRBM_GFX_INDEX, 0,
117	~GRBM_GFX_INDEX__VCE_INSTANCE_MASK);	123	~GRBM_GFX_INDEX__VCE_INSTANCE_MASK);
@@ -190,10 +196,52 @@ static int vce_v3_0_start(struct amdgpu_device *adev) · 72 unmodified lines
190	return 0;	196	return 0;
191	}	197	}
192		198
		199	#define ixVCE_HARVEST_FUSE_MACRO__ADDRESS 0xC0014074
		200	#define VCE_HARVEST_FUSE_MACRO__SHIFT 27
		201	#define VCE_HARVEST_FUSE_MACRO__MASK 0x18000000
		202
		203	static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)
		204	{
		205	u32 tmp;
		206	unsigned ret;
		207
		208	if (adev->flags & AMDGPU_IS_APU)
		209	tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) &
		210	VCE_HARVEST_FUSE_MACRO__MASK) >>
		211	VCE_HARVEST_FUSE_MACRO__SHIFT;
		212	else
		213	tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) &
		214	CC_HARVEST_FUSES__VCE_DISABLE_MASK) >>
		215	CC_HARVEST_FUSES__VCE_DISABLE__SHIFT;
		216
		217	switch (tmp) {
		218	case 1:
		219	ret = AMDGPU_VCE_HARVEST_VCE0;
		220	break;
		221	case 2:
		222	ret = AMDGPU_VCE_HARVEST_VCE1;
		223	break;
		224	case 3:
		225	ret = AMDGPU_VCE_HARVEST_VCE0 \| AMDGPU_VCE_HARVEST_VCE1;
		226	break;
		227	default:
		228	ret = 0;
		229	}
		230
		231	return ret;
		232	}
		233
193	static int vce_v3_0_early_init(void *handle)	234	static int vce_v3_0_early_init(void *handle)
194	{	235	{
195	struct amdgpu_device adev = (struct amdgpu_device )handle;	236	struct amdgpu_device adev = (struct amdgpu_device )handle;
196		237
		238	adev->vce.harvest_config = vce_v3_0_get_harvest_config(adev);
		239
		240	if ((adev->vce.harvest_config &
		241	(AMDGPU_VCE_HARVEST_VCE0 \| AMDGPU_VCE_HARVEST_VCE1)) ==
		242	(AMDGPU_VCE_HARVEST_VCE0 \| AMDGPU_VCE_HARVEST_VCE1))
		243	return -ENOENT;
		244
197	vce_v3_0_set_ring_funcs(adev);	245	vce_v3_0_set_ring_funcs(adev);
198	vce_v3_0_set_irq_funcs(adev);	246	vce_v3_0_set_irq_funcs(adev);
199		247

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c+1−0

@@ -357,6 +357,7 @@ int atmel_hlcdc_crtc_create(struct drm_device *dev) · 356 unmodified lines
357	planes->overlays[i]->base.possible_crtcs = 1 << crtc->id;	357	planes->overlays[i]->base.possible_crtcs = 1 << crtc->id;
358		358
359	drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs);	359	drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs);
		360	drm_crtc_vblank_reset(&crtc->base);
360		361
361	dc->crtc = &crtc->base;	362	dc->crtc = &crtc->base;
362		363

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c+6−6

 	pm_runtime_enable(dev->dev);
-	ret = atmel_hlcdc_dc_modeset_init(dev);
+	ret = drm_vblank_init(dev, 1);
 	if (ret < 0) {
-		dev_err(dev->dev, "failed to initialize mode setting\n");
+		dev_err(dev->dev, "failed to initialize vblank\n");
 		goto err_periph_clk_disable;
 	}
-	drm_mode_config_reset(dev);
+	ret = atmel_hlcdc_dc_modeset_init(dev);
-	ret = drm_vblank_init(dev, 1);
 	if (ret < 0) {
-		dev_err(dev->dev, "failed to initialize vblank\n");
+		dev_err(dev->dev, "failed to initialize mode setting\n");
 		goto err_periph_clk_disable;
 	}
+	drm_mode_config_reset(dev);
 	pm_runtime_get_sync(dev->dev);
 	ret = drm_irq_install(dev, dc->hlcdc->irq);
 	pm_runtime_put_sync(dev->dev);

drivers/gpu/drm/drm_atomic_helper.c+9−1

@@ -196,7 +196,12 @@ update_connector_routing(struct drm_atomic_state *state, int conn_idx) · 195 unmodified lines
196	}	196	}
197		197
198	funcs = connector->helper_private;	198	funcs = connector->helper_private;
199	new_encoder = funcs->best_encoder(connector);	199
		200	if (funcs->atomic_best_encoder)
		201	new_encoder = funcs->atomic_best_encoder(connector,
		202	connector_state);
		203	else
		204	new_encoder = funcs->best_encoder(connector);
200		205
201	if (!new_encoder) {	206	if (!new_encoder) {
202	DRM_DEBUG_ATOMIC("No suitable encoder found for [CONNECTOR:%d:%s]\n",	207	DRM_DEBUG_ATOMIC("No suitable encoder found for [CONNECTOR:%d:%s]\n",
@@ -229,6 +234,9 @@ update_connector_routing(struct drm_atomic_state *state, int conn_idx) · 26 unmodified lines
229	}	234	}
230	}	235	}
231		236
		237	if (WARN_ON(!connector_state->crtc))
		238	return -EINVAL;
		239
232	connector_state->best_encoder = new_encoder;	240	connector_state->best_encoder = new_encoder;
233	idx = drm_crtc_index(connector_state->crtc);	241	idx = drm_crtc_index(connector_state->crtc);
234		242

drivers/gpu/drm/drm_crtc.c+1−4

 			encoder->funcs->reset(encoder);
 	mutex_lock(&dev->mode_config.mutex);
-	drm_for_each_connector(connector, dev) {
+	drm_for_each_connector(connector, dev)
-		connector->status = connector_status_unknown;
 		if (connector->funcs->reset)
 			connector->funcs->reset(connector);
-	}
 	mutex_unlock(&dev->mode_config.mutex);
 }
 EXPORT_SYMBOL(drm_mode_config_reset);

drivers/gpu/drm/drm_dp_mst_topology.c+0−1

@@ -1294,7 +1294,6 @@ retry: · 1293 unmodified lines
1294	goto retry;	1294	goto retry;
1295	}	1295	}
1296	DRM_DEBUG_KMS("failed to dpcd write %d %d\n", tosend, ret);	1296	DRM_DEBUG_KMS("failed to dpcd write %d %d\n", tosend, ret);
1297	WARN(1, "fail\n");
1298		1297
1299	return -EIO;	1298	return -EIO;
1300	}	1299	}

drivers/gpu/drm/drm_irq.c+1−1

@@ -75,7 +75,7 @@ module_param_named(timestamp_precision_usec, drm_timestamp_precision, int, 0600) · 74 unmodified lines
75	module_param_named(timestamp_monotonic, drm_timestamp_monotonic, int, 0600);	75	module_param_named(timestamp_monotonic, drm_timestamp_monotonic, int, 0600);
76		76
77	static void store_vblank(struct drm_device *dev, int crtc,	77	static void store_vblank(struct drm_device *dev, int crtc,
78	unsigned vblank_count_inc,	78	u32 vblank_count_inc,
79	struct timeval *t_vblank)	79	struct timeval *t_vblank)
80	{	80	{
81	struct drm_vblank_crtc *vblank = &dev->vblank[crtc];	81	struct drm_vblank_crtc *vblank = &dev->vblank[crtc];

drivers/gpu/drm/exynos/exynos_drm_fimc.c+0−1

@@ -1745,7 +1745,6 @@ static int fimc_probe(struct platform_device *pdev) · 1744 unmodified lines
1745	spin_lock_init(&ctx->lock);	1745	spin_lock_init(&ctx->lock);
1746	platform_set_drvdata(pdev, ctx);	1746	platform_set_drvdata(pdev, ctx);
1747		1747
1748	pm_runtime_set_active(dev);
1749	pm_runtime_enable(dev);	1748	pm_runtime_enable(dev);
1750		1749
1751	ret = exynos_drm_ippdrv_register(ippdrv);	1750	ret = exynos_drm_ippdrv_register(ippdrv);

drivers/gpu/drm/exynos/exynos_drm_gsc.c+2−4

 	gsc_write(cfg, GSC_IN_CON);
-	ctx->rotation = cfg &
+	ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0;
-		(GSC_IN_ROT_90 | GSC_IN_ROT_270) ? 1 : 0;
 	*swap = ctx->rotation;
 	return 0;
 	gsc_write(cfg, GSC_IN_CON);
-	ctx->rotation = cfg &
+	ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0;
-		(GSC_IN_ROT_90 | GSC_IN_ROT_270) ? 1 : 0;
 	*swap = ctx->rotation;
 	return 0;

drivers/gpu/drm/exynos/exynos_hdmi.c+6−1

 {
 	struct hdmi_context *hdata = ctx_from_connector(connector);
 	struct edid *edid;
+	int ret;
 	if (!hdata->ddc_adpt)
 		return -ENODEV;
 	drm_mode_connector_update_edid_property(connector, edid);
-	return drm_add_edid_modes(connector, edid);
+	ret = drm_add_edid_modes(connector, edid);
+	kfree(edid);
+	return ret;
 }
 static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)

drivers/gpu/drm/exynos/exynos_mixer.c+14−7

 	/* handling VSYNC */
 	if (val & MXR_INT_STATUS_VSYNC) {
+		/* vsync interrupt use different bit for read and clear */
+		val |= MXR_INT_CLEAR_VSYNC;
+		val &= ~MXR_INT_STATUS_VSYNC;
 		/* interlace scan need to check shadow register */
 		if (ctx->interlace) {
 			base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
 out:
 	/* clear interrupts */
-	if (~val & MXR_INT_EN_VSYNC) {
-		/* vsync interrupt use different bit for read and clear */
-		val &= ~MXR_INT_EN_VSYNC;
-		val |= MXR_INT_CLEAR_VSYNC;
-	}
 	mixer_reg_write(res, MXR_INT_STATUS, val);
 	spin_unlock(&res->reg_slock);
 	}
 	/* enable vsync interrupt */
-	mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC,
+	mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
-			MXR_INT_EN_VSYNC);
+	mixer_reg_writemask(res, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC);
 	return 0;
 }
 	struct mixer_context *mixer_ctx = crtc->ctx;
 	struct mixer_resources *res = &mixer_ctx->mixer_res;
+	if (!mixer_ctx->powered) {
+		mixer_ctx->int_en &= MXR_INT_EN_VSYNC;
+		return;
+	}
 	/* disable vsync interrupt */
+	mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
 	mixer_reg_writemask(res, MXR_INT_EN, 0, MXR_INT_EN_VSYNC);
 }
 	mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET);
+	if (ctx->int_en & MXR_INT_EN_VSYNC)
+		mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
 	mixer_reg_write(res, MXR_INT_EN, ctx->int_en);
 	mixer_win_reset(ctx);
 }

drivers/gpu/drm/i2c/tda998x_drv.c+2−2

 tda998x_write_if(struct tda998x_priv *priv, uint8_t bit, uint16_t addr,
 		 uint8_t *buf, size_t size)
 {
-	buf[PB(0)] = tda998x_cksum(buf, size);
 	reg_clear(priv, REG_DIP_IF_FLAGS, bit);
 	reg_write_range(priv, addr, buf, size);
 	reg_set(priv, REG_DIP_IF_FLAGS, bit);
 	buf[PB(4)] = p->audio_frame[4];
 	buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */
+	buf[PB(0)] = tda998x_cksum(buf, sizeof(buf));
 	tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf,
 			 sizeof(buf));
 }

drivers/gpu/drm/i915/i915_drv.h+8−9

@@ -3359,15 +3359,14 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); · 3358 unmodified lines
3359	#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)	3359	#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3360		3360
3361	#define I915_READ64_2x32(lower_reg, upper_reg) ({ \	3361	#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3362	u32 upper = I915_READ(upper_reg); \	3362	u32 upper, lower, tmp; \
3363	u32 lower = I915_READ(lower_reg); \	3363	tmp = I915_READ(upper_reg); \
3364	u32 tmp = I915_READ(upper_reg); \	3364	do { \
3365	if (upper != tmp) { \	3365	upper = tmp; \
3366	upper = tmp; \	3366	lower = I915_READ(lower_reg); \
3367	lower = I915_READ(lower_reg); \	3367	tmp = I915_READ(upper_reg); \
3368	WARN_ON(I915_READ(upper_reg) != upper); \	3368	} while (upper != tmp); \
3369	} \	3369	(u64)upper << 32 \| lower; })
3370	(u64)upper << 32 \| lower; })
3371		3370
3372	#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)	3371	#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3373	#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)	3372	#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)

drivers/gpu/drm/i915/i915_gem_gtt.c+11−0

@@ -2003,6 +2003,17 @@ static int ggtt_bind_vma(struct i915_vma *vma, · 2002 unmodified lines
2003	vma->vm->insert_entries(vma->vm, pages,	2003	vma->vm->insert_entries(vma->vm, pages,
2004	vma->node.start,	2004	vma->node.start,
2005	cache_level, pte_flags);	2005	cache_level, pte_flags);
		2006
		2007	/* Note the inconsistency here is due to absence of the
		2008	* aliasing ppgtt on gen4 and earlier. Though we always
		2009	* request PIN_USER for execbuffer (translated to LOCAL_BIND),
		2010	* without the appgtt, we cannot honour that request and so
		2011	* must substitute it with a global binding. Since we do this
		2012	* behind the upper layers back, we need to explicitly set
		2013	* the bound flag ourselves.
		2014	*/
		2015	vma->bound \|= GLOBAL_BIND;
		2016
2006	}	2017	}
2007		2018
2008	if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) {	2019	if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) {

drivers/gpu/drm/i915/i915_gem_tiling.c+4−1

 	}
 	/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
-	args->phys_swizzle_mode = args->swizzle_mode;
+	if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
+		args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
+	else
+		args->phys_swizzle_mode = args->swizzle_mode;
 	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
 		args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
 	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)

drivers/gpu/drm/i915/intel_bios.c+23−4

 	const union child_device_config *p_child;
 	union child_device_config *child_dev_ptr;
 	int i, child_device_num, count;
-	u16	block_size;
+	u8 expected_size;
+	u16 block_size;
 	p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
 	if (!p_defs) {
 		DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n");
 		return;
 	}
-	if (p_defs->child_dev_size < sizeof(*p_child)) {
+	if (bdb->version < 195) {
-		DRM_ERROR("General definiton block child device size is too small.\n");
+		expected_size = 33;
+	} else if (bdb->version == 195) {
+		expected_size = 37;
+	} else if (bdb->version <= 197) {
+		expected_size = 38;
+	} else {
+		expected_size = 38;
+		DRM_DEBUG_DRIVER("Expected child_device_config size for BDB version %u not known; assuming %u\n",
+				 expected_size, bdb->version);
+	}
+	if (expected_size > sizeof(*p_child)) {
+		DRM_ERROR("child_device_config cannot fit in p_child\n");
+		return;
+	}
+	if (p_defs->child_dev_size != expected_size) {
+		DRM_ERROR("Size mismatch; child_device_config size=%u (expected %u); bdb->version: %u\n",
+			  p_defs->child_dev_size, expected_size, bdb->version);
 		return;
 	}
 	/* get the block size of general definitions */
 		child_dev_ptr = dev_priv->vbt.child_dev + count;
 		count++;
-		memcpy(child_dev_ptr, p_child, sizeof(*p_child));
+		memcpy(child_dev_ptr, p_child, p_defs->child_dev_size);
 	}
 	return;
 }

drivers/gpu/drm/i915/intel_dp_mst.c+11−0

 	return MODE_OK;
 }
+static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector,
+							 struct drm_connector_state *state)
+{
+	struct intel_connector *intel_connector = to_intel_connector(connector);
+	struct intel_dp *intel_dp = intel_connector->mst_port;
+	struct intel_crtc *crtc = to_intel_crtc(state->crtc);
+	return &intel_dp->mst_encoders[crtc->pipe]->base.base;
+}
 static struct drm_encoder *intel_mst_best_encoder(struct drm_connector *connector)
 {
 	struct intel_connector *intel_connector = to_intel_connector(connector);
 static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = {
 	.get_modes = intel_dp_mst_get_modes,
 	.mode_valid = intel_dp_mst_mode_valid,
+	.atomic_best_encoder = intel_mst_atomic_best_encoder,
 	.best_encoder = intel_mst_best_encoder,
 };

drivers/gpu/drm/i915/intel_uncore.c+19−7

 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_reg_read *reg = data;
 	struct register_whitelist const *entry = whitelist;
+	unsigned size;
+	u64 offset;
 	int i, ret = 0;
 	for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
-		if (entry->offset == reg->offset &&
+		if (entry->offset == (reg->offset & -entry->size) &&
 		    (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
 			break;
 	}
 	if (i == ARRAY_SIZE(whitelist))
 		return -EINVAL;
+	/* We use the low bits to encode extra flags as the register should
+	 * be naturally aligned (and those that are not so aligned merely
+	 * limit the available flags for that register).
+	 */
+	offset = entry->offset;
+	size = entry->size;
+	size |= reg->offset ^ offset;
 	intel_runtime_pm_get(dev_priv);
-	switch (entry->size) {
+	switch (size) {
+	case 8 | 1:
+		reg->val = I915_READ64_2x32(offset, offset+4);
+		break;
 	case 8:
-		reg->val = I915_READ64(reg->offset);
+		reg->val = I915_READ64(offset);
 		break;
 	case 4:
-		reg->val = I915_READ(reg->offset);
+		reg->val = I915_READ(offset);
 		break;
 	case 2:
-		reg->val = I915_READ16(reg->offset);
+		reg->val = I915_READ16(offset);
 		break;
 	case 1:
-		reg->val = I915_READ8(reg->offset);
+		reg->val = I915_READ8(offset);
 		break;
 	default:
-		MISSING_CASE(entry->size);
 		ret = -EINVAL;
 		goto out;
 	}

drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c+3−1

 	uint32_t op_mode = 0;
 	uint32_t phasex_step = MDP4_VG_PHASE_STEP_DEFAULT;
 	uint32_t phasey_step = MDP4_VG_PHASE_STEP_DEFAULT;
-	enum mdp4_frame_format frame_type = mdp4_get_frame_format(fb);
+	enum mdp4_frame_format frame_type;
 	if (!(crtc && fb)) {
 		DBG("%s: disabled!", mdp4_plane->name);
 		return 0;
 	}
+	frame_type = mdp4_get_frame_format(fb);
 	/* src values are in Q16 fixed point, convert to integer: */
 	src_x = src_x >> 16;
 	src_y = src_y >> 16;

drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c+13−0

@@ -76,7 +76,20 @@ static void mdp5_prepare_commit(struct msm_kms kms, struct drm_atomic_state st · 75 unmodified lines
76		76
77	static void mdp5_complete_commit(struct msm_kms kms, struct drm_atomic_state state)	77	static void mdp5_complete_commit(struct msm_kms kms, struct drm_atomic_state state)
78	{	78	{
		79	int i;
79	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));	80	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
		81	int nplanes = mdp5_kms->dev->mode_config.num_total_plane;
		82
		83	for (i = 0; i < nplanes; i++) {
		84	struct drm_plane *plane = state->planes[i];
		85	struct drm_plane_state *plane_state = state->plane_states[i];
		86
		87	if (!plane)
		88	continue;
		89
		90	mdp5_plane_complete_commit(plane, plane_state);
		91	}
		92
80	mdp5_disable(mdp5_kms);	93	mdp5_disable(mdp5_kms);
81	}	94	}
82		95

drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h+2−0

 		struct drm_mode_object *obj);
 uint32_t mdp5_plane_get_flush(struct drm_plane *plane);
 void mdp5_plane_complete_flip(struct drm_plane *plane);
+void mdp5_plane_complete_commit(struct drm_plane *plane,
+	struct drm_plane_state *state);
 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane);
 struct drm_plane *mdp5_plane_init(struct drm_device *dev,
 		enum mdp5_pipe pipe, bool private_plane, uint32_t reg_offset);

drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c+14−19

 	uint32_t nformats;
 	uint32_t formats[32];
-	bool enabled;
 };
 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
 	return state->fb && state->crtc;
 }
-static int mdp5_plane_disable(struct drm_plane *plane)
-{
-	struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
-	struct mdp5_kms *mdp5_kms = get_kms(plane);
-	enum mdp5_pipe pipe = mdp5_plane->pipe;
-	DBG("%s: disable", mdp5_plane->name);
-	if (mdp5_kms) {
-		/* Release the memory we requested earlier from the SMP: */
-		mdp5_smp_release(mdp5_kms->smp, pipe);
-	}
-	return 0;
-}
 static void mdp5_plane_destroy(struct drm_plane *plane)
 {
 	struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
 	if (!plane_enabled(state)) {
 		to_mdp5_plane_state(state)->pending = true;
-		mdp5_plane_disable(plane);
 	} else if (to_mdp5_plane_state(state)->mode_changed) {
 		int ret;
 		to_mdp5_plane_state(state)->pending = true;
 	return mdp5_plane->flush_mask;
 }
+/* called after vsync in thread context */
+void mdp5_plane_complete_commit(struct drm_plane *plane,
+	struct drm_plane_state *state)
+{
+	struct mdp5_kms *mdp5_kms = get_kms(plane);
+	struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
+	enum mdp5_pipe pipe = mdp5_plane->pipe;
+	if (!plane_enabled(plane->state)) {
+		DBG("%s: free SMP", mdp5_plane->name);
+		mdp5_smp_release(mdp5_kms->smp, pipe);
+	}
+}
 /* initialize plane */
 struct drm_plane *mdp5_plane_init(struct drm_device *dev,
 		enum mdp5_pipe pipe, bool private_plane, uint32_t reg_offset)

drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c+74−13

@@ -34,22 +34,44 @@ · 33 unmodified lines
34	* and CANNOT be re-allocated (eg: MMB0 and MMB1 both tied to RGB0).	34	* and CANNOT be re-allocated (eg: MMB0 and MMB1 both tied to RGB0).
35	*	35	*
36	* For each block that can be dynamically allocated, it can be either	36	* For each block that can be dynamically allocated, it can be either
37	* free, or pending/in-use by a client. The updates happen in three steps:	37	* free:
		38	* The block is free.
		39	*
		40	* pending:
		41	* The block is allocated to some client and not free.
		42	*
		43	* configured:
		44	* The block is allocated to some client, and assigned to that
		45	* client in MDP5_MDP_SMP_ALLOC registers.
		46	*
		47	* inuse:
		48	* The block is being actively used by a client.
		49	*
		50	* The updates happen in the following steps:
38	*	51	*
39	* 1) mdp5_smp_request():	52	* 1) mdp5_smp_request():
40	* When plane scanout is setup, calculate required number of	53	* When plane scanout is setup, calculate required number of
41	* blocks needed per client, and request. Blocks not inuse or	54	* blocks needed per client, and request. Blocks neither inuse nor
42	* pending by any other client are added to client's pending	55	* configured nor pending by any other client are added to client's
43	* set.	56	* pending set.
		57	* For shrinking, blocks in pending but not in configured can be freed
		58	* directly, but those already in configured will be freed later by
		59	* mdp5_smp_commit.
44	*	60	*
45	* 2) mdp5_smp_configure():	61	* 2) mdp5_smp_configure():
46	* As hw is programmed, before FLUSH, MDP5_MDP_SMP_ALLOC registers	62	* As hw is programmed, before FLUSH, MDP5_MDP_SMP_ALLOC registers
47	* are configured for the union(pending, inuse)	63	* are configured for the union(pending, inuse)
		64	* Current pending is copied to configured.
		65	* It is assumed that mdp5_smp_request and mdp5_smp_configure not run
		66	* concurrently for the same pipe.
48	*	67	*
49	* 3) mdp5_smp_commit():	68	* 3) mdp5_smp_commit():
50	* After next vblank, copy pending -> inuse. Optionally update	69	* After next vblank, copy configured -> inuse. Optionally update
51	* MDP5_SMP_ALLOC registers if there are newly unused blocks	70	* MDP5_SMP_ALLOC registers if there are newly unused blocks
52	*	71	*
		72	* 4) mdp5_smp_release():
		73	* Must be called after the pipe is disabled and no longer uses any SMB
		74	*
53	* On the next vblank after changes have been committed to hw, the	75	* On the next vblank after changes have been committed to hw, the
54	* client's pending blocks become it's in-use blocks (and no-longer	76	* client's pending blocks become it's in-use blocks (and no-longer
55	* in-use blocks become available to other clients).	77	* in-use blocks become available to other clients).
@@ -77,6 +99,9 @@ struct mdp5_smp { · 21 unmodified lines
77	struct mdp5_client_smp_state client_state[MAX_CLIENTS];	99	struct mdp5_client_smp_state client_state[MAX_CLIENTS];
78	};	100	};
79		101
		102	static void update_smp_state(struct mdp5_smp *smp,
		103	u32 cid, mdp5_smp_state_t *assigned);
		104
80	static inline	105	static inline
81	struct mdp5_kms get_kms(struct mdp5_smp smp)	106	struct mdp5_kms get_kms(struct mdp5_smp smp)
82	{	107	{
@@ -149,7 +174,12 @@ static int smp_request_block(struct mdp5_smp *smp, · 66 unmodified lines
149	for (i = cur_nblks; i > nblks; i--) {	174	for (i = cur_nblks; i > nblks; i--) {
150	int blk = find_first_bit(ps->pending, cnt);	175	int blk = find_first_bit(ps->pending, cnt);
151	clear_bit(blk, ps->pending);	176	clear_bit(blk, ps->pending);
152	/* don't clear in global smp_state until _commit() */	177
		178	/* clear in global smp_state if not in configured
		179	* otherwise until _commit()
		180	*/
		181	if (!test_bit(blk, ps->configured))
		182	clear_bit(blk, smp->state);
153	}	183	}
154	}	184	}
155		185
@@ -223,10 +253,33 @@ int mdp5_smp_request(struct mdp5_smp *smp, enum mdp5_pipe pipe, u32 fmt, u32 wid · 67 unmodified lines
223	/* Release SMP blocks for all clients of the pipe */	253	/* Release SMP blocks for all clients of the pipe */
224	void mdp5_smp_release(struct mdp5_smp *smp, enum mdp5_pipe pipe)	254	void mdp5_smp_release(struct mdp5_smp *smp, enum mdp5_pipe pipe)
225	{	255	{
226	int i, nblks;	256	int i;
		257	unsigned long flags;
		258	int cnt = smp->blk_cnt;
		259
		260	for (i = 0; i < pipe2nclients(pipe); i++) {
		261	mdp5_smp_state_t assigned;
		262	u32 cid = pipe2client(pipe, i);
		263	struct mdp5_client_smp_state *ps = &smp->client_state[cid];
		264
		265	spin_lock_irqsave(&smp->state_lock, flags);
		266
		267	/* clear hw assignment */
		268	bitmap_or(assigned, ps->inuse, ps->configured, cnt);
		269	update_smp_state(smp, CID_UNUSED, &assigned);
		270
		271	/* free to global pool */
		272	bitmap_andnot(smp->state, smp->state, ps->pending, cnt);
		273	bitmap_andnot(smp->state, smp->state, assigned, cnt);
		274
		275	/* clear client's infor */
		276	bitmap_zero(ps->pending, cnt);
		277	bitmap_zero(ps->configured, cnt);
		278	bitmap_zero(ps->inuse, cnt);
		279
		280	spin_unlock_irqrestore(&smp->state_lock, flags);
		281	}
227		282
228	for (i = 0, nblks = 0; i < pipe2nclients(pipe); i++)
229	smp_request_block(smp, pipe2client(pipe, i), 0);
230	set_fifo_thresholds(smp, pipe, 0);	283	set_fifo_thresholds(smp, pipe, 0);
231	}	284	}
232		285
@@ -274,12 +327,20 @@ void mdp5_smp_configure(struct mdp5_smp *smp, enum mdp5_pipe pipe) · 41 unmodified lines
274	u32 cid = pipe2client(pipe, i);	327	u32 cid = pipe2client(pipe, i);
275	struct mdp5_client_smp_state *ps = &smp->client_state[cid];	328	struct mdp5_client_smp_state *ps = &smp->client_state[cid];
276		329
277	bitmap_or(assigned, ps->inuse, ps->pending, cnt);	330	/*
		331	* if vblank has not happened since last smp_configure
		332	* skip the configure for now
		333	*/
		334	if (!bitmap_equal(ps->inuse, ps->configured, cnt))
		335	continue;
		336
		337	bitmap_copy(ps->configured, ps->pending, cnt);
		338	bitmap_or(assigned, ps->inuse, ps->configured, cnt);
278	update_smp_state(smp, cid, &assigned);	339	update_smp_state(smp, cid, &assigned);
279	}	340	}
280	}	341	}
281		342
282	/* step #3: after vblank, copy pending -> inuse: */	343	/* step #3: after vblank, copy configured -> inuse: */
283	void mdp5_smp_commit(struct mdp5_smp *smp, enum mdp5_pipe pipe)	344	void mdp5_smp_commit(struct mdp5_smp *smp, enum mdp5_pipe pipe)
284	{	345	{
285	int cnt = smp->blk_cnt;	346	int cnt = smp->blk_cnt;
@@ -295,7 +356,7 @@ void mdp5_smp_commit(struct mdp5_smp *smp, enum mdp5_pipe pipe) · 9 unmodified lines
295	* using, which can be released and made available to other	356	* using, which can be released and made available to other
296	* clients:	357	* clients:
297	*/	358	*/
298	if (bitmap_andnot(released, ps->inuse, ps->pending, cnt)) {	359	if (bitmap_andnot(released, ps->inuse, ps->configured, cnt)) {
299	unsigned long flags;	360	unsigned long flags;
300		361
301	spin_lock_irqsave(&smp->state_lock, flags);	362	spin_lock_irqsave(&smp->state_lock, flags);
@@ -306,7 +367,7 @@ void mdp5_smp_commit(struct mdp5_smp *smp, enum mdp5_pipe pipe) · 4 unmodified lines
306	update_smp_state(smp, CID_UNUSED, &released);	367	update_smp_state(smp, CID_UNUSED, &released);
307	}	368	}
308		369
309	bitmap_copy(ps->inuse, ps->pending, cnt);	370	bitmap_copy(ps->inuse, ps->configured, cnt);
310	}	371	}
311	}	372	}
312		373

drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.h+1−0

@@ -23,6 +23,7 @@ · 22 unmodified lines
23		23
24	struct mdp5_client_smp_state {	24	struct mdp5_client_smp_state {
25	mdp5_smp_state_t inuse;	25	mdp5_smp_state_t inuse;
		26	mdp5_smp_state_t configured;
26	mdp5_smp_state_t pending;	27	mdp5_smp_state_t pending;
27	};	28	};
28		29

drivers/gpu/drm/msm/msm_atomic.c+2−6

 	timeout = ktime_add_ms(ktime_get(), 1000);
-	ret = msm_wait_fence_interruptable(dev, c->fence, &timeout);
+	/* uninterruptible wait */
-	if (ret) {
+	msm_wait_fence(dev, c->fence, &timeout, false);
-		WARN_ON(ret);  // TODO unswap state back?  or??
-		commit_destroy(c);
-		return ret;
-	}
 	complete_commit(c);

drivers/gpu/drm/msm/msm_drv.c+9−4

  * Fences:
  */
-int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
+int msm_wait_fence(struct drm_device *dev, uint32_t fence,
-		ktime_t *timeout)
+		ktime_t *timeout , bool interruptible)
 {
 	struct msm_drm_private *priv = dev->dev_private;
 	int ret;
 			remaining_jiffies = timespec_to_jiffies(&ts);
 		}
-		ret = wait_event_interruptible_timeout(priv->fence_event,
+		if (interruptible)
+			ret = wait_event_interruptible_timeout(priv->fence_event,
+				fence_completed(dev, fence),
+				remaining_jiffies);
+		else
+			ret = wait_event_timeout(priv->fence_event,
 				fence_completed(dev, fence),
 				remaining_jiffies);
 		return -EINVAL;
 	}
-	return msm_wait_fence_interruptable(dev, args->fence, &timeout);
+	return msm_wait_fence(dev, args->fence, &timeout, true);
 }
 static const struct drm_ioctl_desc msm_ioctls[] = {

drivers/gpu/drm/msm/msm_drv.h+2−2

@@ -164,8 +164,8 @@ int msm_atomic_commit(struct drm_device *dev, · 163 unmodified lines
164		164
165	int msm_register_mmu(struct drm_device dev, struct msm_mmu mmu);	165	int msm_register_mmu(struct drm_device dev, struct msm_mmu mmu);
166		166
167	int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,	167	int msm_wait_fence(struct drm_device *dev, uint32_t fence,
168	ktime_t *timeout);	168	ktime_t *timeout, bool interruptible);
169	int msm_queue_fence_cb(struct drm_device *dev,	169	int msm_queue_fence_cb(struct drm_device *dev,
170	struct msm_fence_cb *cb, uint32_t fence);	170	struct msm_fence_cb *cb, uint32_t fence);
171	void msm_update_fence(struct drm_device *dev, uint32_t fence);	171	void msm_update_fence(struct drm_device *dev, uint32_t fence);

drivers/gpu/drm/msm/msm_gem.c+1−1

@@ -460,7 +460,7 @@ int msm_gem_cpu_prep(struct drm_gem_object obj, uint32_t op, ktime_t timeout) · 459 unmodified lines
460	if (op & MSM_PREP_NOSYNC)	460	if (op & MSM_PREP_NOSYNC)
461	timeout = NULL;	461	timeout = NULL;
462		462
463	ret = msm_wait_fence_interruptable(dev, fence, timeout);	463	ret = msm_wait_fence(dev, fence, timeout, true);
464	}	464	}
465		465
466	/* TODO cache maintenance */	466	/* TODO cache maintenance */

drivers/gpu/drm/msm/msm_gem_prime.c+6−2

@@ -23,8 +23,12 @@ · 22 unmodified lines
23	struct sg_table msm_gem_prime_get_sg_table(struct drm_gem_object obj)	23	struct sg_table msm_gem_prime_get_sg_table(struct drm_gem_object obj)
24	{	24	{
25	struct msm_gem_object *msm_obj = to_msm_bo(obj);	25	struct msm_gem_object *msm_obj = to_msm_bo(obj);
26	BUG_ON(!msm_obj->sgt); /* should have already pinned! */	26	int npages = obj->size >> PAGE_SHIFT;
27	return msm_obj->sgt;	27
		28	if (WARN_ON(!msm_obj->pages)) /* should have already pinned! */
		29	return NULL;
		30
		31	return drm_prime_pages_to_sg(msm_obj->pages, npages);
28	}	32	}
29		33
30	void msm_gem_prime_vmap(struct drm_gem_object obj)	34	void msm_gem_prime_vmap(struct drm_gem_object obj)

drivers/gpu/drm/nouveau/nouveau_drm.c+3−0

 	nvkm_vm_ref(NULL, &nvxx_client(&cli->base)->vm, NULL);
 	nvif_client_fini(&cli->base);
 	usif_client_fini(cli);
+	kfree(cli);
 }
 static void
 	pm_runtime_get_sync(dev->dev);
+	mutex_lock(&cli->mutex);
 	if (cli->abi16)
 		nouveau_abi16_fini(cli->abi16);
+	mutex_unlock(&cli->mutex);
 	mutex_lock(&drm->client.mutex);
 	list_del(&cli->head);

drivers/gpu/drm/nouveau/nouveau_platform.c+16−0

@@ -92,6 +92,8 @@ static int nouveau_platform_power_down(struct nouveau_platform_gpu *gpu) · 91 unmodified lines
92	return 0;	92	return 0;
93	}	93	}
94		94
		95	#if IS_ENABLED(CONFIG_IOMMU_API)
		96
95	static void nouveau_platform_probe_iommu(struct device *dev,	97	static void nouveau_platform_probe_iommu(struct device *dev,
96	struct nouveau_platform_gpu *gpu)	98	struct nouveau_platform_gpu *gpu)
97	{	99	{
@@ -158,6 +160,20 @@ static void nouveau_platform_remove_iommu(struct device *dev, · 60 unmodified lines
158	}	160	}
159	}	161	}
160		162
		163	#else
		164
		165	static void nouveau_platform_probe_iommu(struct device *dev,
		166	struct nouveau_platform_gpu *gpu)
		167	{
		168	}
		169
		170	static void nouveau_platform_remove_iommu(struct device *dev,
		171	struct nouveau_platform_gpu *gpu)
		172	{
		173	}
		174
		175	#endif
		176
161	static int nouveau_platform_probe(struct platform_device *pdev)	177	static int nouveau_platform_probe(struct platform_device *pdev)
162	{	178	{
163	struct nouveau_platform_gpu *gpu;	179	struct nouveau_platform_gpu *gpu;

drivers/gpu/drm/nouveau/nouveau_ttm.c+9−0

 	node->page_shift = 12;
 	switch (drm->device.info.family) {
+	case NV_DEVICE_INFO_V0_TNT:
+	case NV_DEVICE_INFO_V0_CELSIUS:
+	case NV_DEVICE_INFO_V0_KELVIN:
+	case NV_DEVICE_INFO_V0_RANKINE:
+	case NV_DEVICE_INFO_V0_CURIE:
+		break;
 	case NV_DEVICE_INFO_V0_TESLA:
 		if (drm->device.info.chipset != 0x50)
 			node->memtype = (nvbo->tile_flags & 0x7f00) >> 8;
 		break;
 	case NV_DEVICE_INFO_V0_FERMI:
 	case NV_DEVICE_INFO_V0_KEPLER:
+	case NV_DEVICE_INFO_V0_MAXWELL:
 		node->memtype = (nvbo->tile_flags & 0xff00) >> 8;
 		break;
 	default:
+		NV_WARN(drm, "%s: unhandled family type %x\n", __func__,
+			drm->device.info.family);
 		break;
 	}

drivers/gpu/drm/nouveau/nv04_fbcon.c+1−1

@@ -203,7 +203,7 @@ nv04_fbcon_accel_init(struct fb_info *info) · 202 unmodified lines
203	if (ret)	203	if (ret)
204	return ret;	204	return ret;
205		205
206	if (RING_SPACE(chan, 49)) {	206	if (RING_SPACE(chan, 49 + (device->info.chipset >= 0x11 ? 4 : 0))) {
207	nouveau_fbcon_gpu_lockup(info);	207	nouveau_fbcon_gpu_lockup(info);
208	return 0;	208	return 0;
209	}	209	}

drivers/gpu/drm/nouveau/nv50_display.c+1−1

@@ -979,7 +979,7 @@ nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update) · 978 unmodified lines
979	{	979	{
980	struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);	980	struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
981		981
982	if (show && nv_crtc->cursor.nvbo)	982	if (show && nv_crtc->cursor.nvbo && nv_crtc->base.enabled)
983	nv50_crtc_cursor_show(nv_crtc);	983	nv50_crtc_cursor_show(nv_crtc);
984	else	984	else
985	nv50_crtc_cursor_hide(nv_crtc);	985	nv50_crtc_cursor_hide(nv_crtc);

drivers/gpu/drm/nouveau/nv50_fbcon.c+2−1

 	if (ret)
 		return ret;
-	ret = RING_SPACE(chan, 59);
+	ret = RING_SPACE(chan, 58);
 	if (ret) {
 		nouveau_fbcon_gpu_lockup(info);
 		return ret;
 	OUT_RING(chan, info->var.yres_virtual);
 	OUT_RING(chan, upper_32_bits(fb->vma.offset));
 	OUT_RING(chan, lower_32_bits(fb->vma.offset));
+	FIRE_RING(chan);
 	return 0;
 }

drivers/gpu/drm/nouveau/nvc0_fbcon.c+1−1

@@ -188,7 +188,7 @@ nvc0_fbcon_accel_init(struct fb_info *info) · 187 unmodified lines
188	return -EINVAL;	188	return -EINVAL;
189	}	189	}
190		190
191	ret = RING_SPACE(chan, 60);	191	ret = RING_SPACE(chan, 58);
192	if (ret) {	192	if (ret) {
193	WARN_ON(1);	193	WARN_ON(1);
194	nouveau_fbcon_gpu_lockup(info);	194	nouveau_fbcon_gpu_lockup(info);

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf110.c+1−1

@@ -809,7 +809,7 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl, · 808 unmodified lines
809	case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break;	809	case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break;
810	default:	810	default:
811	nv_error(priv, "unknown SOR mc 0x%08x\n", ctrl);	811	nv_error(priv, "unknown SOR mc 0x%08x\n", ctrl);
812	return 0x0000;	812	return NULL;
813	}	813	}
814	}	814	}
815		815

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c+38−1

@@ -663,6 +663,37 @@ gf100_gr_zbc_init(struct gf100_gr_priv *priv) · 662 unmodified lines
663	gf100_gr_zbc_clear_depth(priv, index);	663	gf100_gr_zbc_clear_depth(priv, index);
664	}	664	}
665		665
		666	/**
		667	* Wait until GR goes idle. GR is considered idle if it is disabled by the
		668	* MC (0x200) register, or GR is not busy and a context switch is not in
		669	* progress.
		670	*/
		671	int
		672	gf100_gr_wait_idle(struct gf100_gr_priv *priv)
		673	{
		674	unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000);
		675	bool gr_enabled, ctxsw_active, gr_busy;
		676
		677	do {
		678	/*
		679	* required to make sure FIFO_ENGINE_STATUS (0x2640) is
		680	* up-to-date
		681	*/
		682	nv_rd32(priv, 0x400700);
		683
		684	gr_enabled = nv_rd32(priv, 0x200) & 0x1000;
		685	ctxsw_active = nv_rd32(priv, 0x2640) & 0x8000;
		686	gr_busy = nv_rd32(priv, 0x40060c) & 0x1;
		687
		688	if (!gr_enabled \|\| (!gr_busy && !ctxsw_active))
		689	return 0;
		690	} while (time_before(jiffies, end_jiffies));
		691
		692	nv_error(priv, "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n",
		693	gr_enabled, ctxsw_active, gr_busy);
		694	return -EAGAIN;
		695	}
		696
666	void	697	void
667	gf100_gr_mmio(struct gf100_gr_priv priv, const struct gf100_gr_pack p)	698	gf100_gr_mmio(struct gf100_gr_priv priv, const struct gf100_gr_pack p)
668	{	699	{
@@ -699,7 +730,13 @@ gf100_gr_icmd(struct gf100_gr_priv priv, const struct gf100_gr_pack p) · 30 unmodified lines
699		730
700	while (addr < next) {	731	while (addr < next) {
701	nv_wr32(priv, 0x400200, addr);	732	nv_wr32(priv, 0x400200, addr);
702	nv_wait(priv, 0x400700, 0x00000002, 0x00000000);	733	/**
		734	* Wait for GR to go idle after submitting a
		735	* GO_IDLE bundle
		736	*/
		737	if ((addr & 0xffff) == 0xe100)
		738	gf100_gr_wait_idle(priv);
		739	nv_wait(priv, 0x400700, 0x00000004, 0x00000000);
703	addr += init->pitch;	740	addr += init->pitch;
704	}	741	}
705	}	742	}

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h+1−0

@@ -181,6 +181,7 @@ struct gf100_gr_oclass { · 180 unmodified lines
181	int ppc_nr;	181	int ppc_nr;
182	};	182	};
183		183
		184	int gf100_gr_wait_idle(struct gf100_gr_priv *);
184	void gf100_gr_mmio(struct gf100_gr_priv , const struct gf100_gr_pack );	185	void gf100_gr_mmio(struct gf100_gr_priv , const struct gf100_gr_pack );
185	void gf100_gr_icmd(struct gf100_gr_priv , const struct gf100_gr_pack );	186	void gf100_gr_icmd(struct gf100_gr_priv , const struct gf100_gr_pack );
186	void gf100_gr_mthd(struct gf100_gr_priv , const struct gf100_gr_pack );	187	void gf100_gr_mthd(struct gf100_gr_priv , const struct gf100_gr_pack );

drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c+8−6

 nvkm_perfctx_dtor(struct nvkm_object *object)
 {
 	struct nvkm_pm *ppm = (void *)object->engine;
+	struct nvkm_perfctx *ctx = (void *)object;
 	mutex_lock(&nv_subdev(ppm)->mutex);
-	nvkm_engctx_destroy(&ppm->context->base);
+	nvkm_engctx_destroy(&ctx->base);
-	ppm->context = NULL;
+	if (ppm->context == ctx)
+		ppm->context = NULL;
 	mutex_unlock(&nv_subdev(ppm)->mutex);
 }
 	mutex_lock(&nv_subdev(ppm)->mutex);
 	if (ppm->context == NULL)
 		ppm->context = ctx;
-	mutex_unlock(&nv_subdev(ppm)->mutex);
 	if (ctx != ppm->context)
-		return -EBUSY;
+		ret = -EBUSY;
+	mutex_unlock(&nv_subdev(ppm)->mutex);
-	return 0;
+	return ret;
 }
 struct nvkm_oclass

drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c+40−0

@@ -1284,6 +1284,44 @@ init_zm_reg_sequence(struct nvbios_init *init) · 1283 unmodified lines
1284	}	1284	}
1285	}	1285	}
1286		1286
		1287	/**
		1288	* INIT_PLL_INDIRECT - opcode 0x59
		1289	*
		1290	*/
		1291	static void
		1292	init_pll_indirect(struct nvbios_init *init)
		1293	{
		1294	struct nvkm_bios *bios = init->bios;
		1295	u32 reg = nv_ro32(bios, init->offset + 1);
		1296	u16 addr = nv_ro16(bios, init->offset + 5);
		1297	u32 freq = (u32)nv_ro16(bios, addr) * 1000;
		1298
		1299	trace("PLL_INDIRECT\tR[0x%06x] =PLL= VBIOS[%04x] = %dkHz\n",
		1300	reg, addr, freq);
		1301	init->offset += 7;
		1302
		1303	init_prog_pll(init, reg, freq);
		1304	}
		1305
		1306	/**
		1307	* INIT_ZM_REG_INDIRECT - opcode 0x5a
		1308	*
		1309	*/
		1310	static void
		1311	init_zm_reg_indirect(struct nvbios_init *init)
		1312	{
		1313	struct nvkm_bios *bios = init->bios;
		1314	u32 reg = nv_ro32(bios, init->offset + 1);
		1315	u16 addr = nv_ro16(bios, init->offset + 5);
		1316	u32 data = nv_ro32(bios, addr);
		1317
		1318	trace("ZM_REG_INDIRECT\tR[0x%06x] = VBIOS[0x%04x] = 0x%08x\n",
		1319	reg, addr, data);
		1320	init->offset += 7;
		1321
		1322	init_wr32(init, addr, data);
		1323	}
		1324
1287	/**	1325	/**
1288	* INIT_SUB_DIRECT - opcode 0x5b	1326	* INIT_SUB_DIRECT - opcode 0x5b
1289	*	1327	*
@@ -2145,6 +2183,8 @@ static struct nvbios_init_opcode { · 855 unmodified lines
2145	[0x56] = { init_condition_time },	2183	[0x56] = { init_condition_time },
2146	[0x57] = { init_ltime },	2184	[0x57] = { init_ltime },
2147	[0x58] = { init_zm_reg_sequence },	2185	[0x58] = { init_zm_reg_sequence },
		2186	[0x59] = { init_pll_indirect },
		2187	[0x5a] = { init_zm_reg_indirect },
2148	[0x5b] = { init_sub_direct },	2188	[0x5b] = { init_sub_direct },
2149	[0x5c] = { init_jump },	2189	[0x5c] = { init_jump },
2150	[0x5e] = { init_i2c_if },	2190	[0x5e] = { init_i2c_if },

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c+2−1

@@ -180,7 +180,8 @@ gt215_clk_info(struct nvkm_clk *clock, int clk, u32 khz, · 179 unmodified lines
180	struct gt215_clk_info *info)	180	struct gt215_clk_info *info)
181	{	181	{
182	struct gt215_clk_priv priv = (void )clock;	182	struct gt215_clk_priv priv = (void )clock;
183	u32 oclk, sclk, sdiv, diff;	183	u32 oclk, sclk, sdiv;
		184	s32 diff;
184		185
185	info->clk = 0;	186	info->clk = 0;
186		187

drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk20a.c+8−0

@@ -38,6 +38,14 @@ gk20a_ibus_init_priv_ring(struct gk20a_ibus_priv *priv) · 37 unmodified lines
38	nv_wr32(priv, 0x12004c, 0x4);	38	nv_wr32(priv, 0x12004c, 0x4);
39	nv_wr32(priv, 0x122204, 0x2);	39	nv_wr32(priv, 0x122204, 0x2);
40	nv_rd32(priv, 0x122204);	40	nv_rd32(priv, 0x122204);
		41
		42	/*
		43	* Bug: increase clock timeout to avoid operation failure at high
		44	* gpcclk rate.
		45	*/
		46	nv_wr32(priv, 0x122354, 0x800);
		47	nv_wr32(priv, 0x128328, 0x800);
		48	nv_wr32(priv, 0x124320, 0x800);
41	}	49	}
42		50
43	static void	51	static void

drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c+8−0

 {
 	struct nv04_instmem_priv *priv = (void *)nvkm_instmem(object);
 	struct nv04_instobj_priv *node = (void *)object;
+	struct nvkm_subdev *subdev = (void *)priv;
+	mutex_lock(&subdev->mutex);
 	nvkm_mm_free(&priv->heap, &node->mem);
+	mutex_unlock(&subdev->mutex);
 	nvkm_instobj_destroy(&node->base);
 }
 	struct nv04_instmem_priv *priv = (void *)nvkm_instmem(parent);
 	struct nv04_instobj_priv *node;
 	struct nvkm_instobj_args *args = data;
+	struct nvkm_subdev *subdev = (void *)priv;
 	int ret;
 	if (!args->align)
 	if (ret)
 		return ret;
+	mutex_lock(&subdev->mutex);
 	ret = nvkm_mm_head(&priv->heap, 0, 1, args->size, args->size,
 			   args->align, &node->mem);
+	mutex_unlock(&subdev->mutex);
 	if (ret)
 		return ret;

drivers/gpu/drm/radeon/atombios_encoders.c+1−2

@@ -2299,8 +2299,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, · 2298 unmodified lines
2299	encoder_mode = atombios_get_encoder_mode(encoder);	2299	encoder_mode = atombios_get_encoder_mode(encoder);
2300	if (connector && (radeon_audio != 0) &&	2300	if (connector && (radeon_audio != 0) &&
2301	((encoder_mode == ATOM_ENCODER_MODE_HDMI) \|\|	2301	((encoder_mode == ATOM_ENCODER_MODE_HDMI) \|\|
2302	(ENCODER_MODE_IS_DP(encoder_mode) &&	2302	ENCODER_MODE_IS_DP(encoder_mode)))
2303	drm_detect_monitor_audio(radeon_connector_edid(connector)))))
2304	radeon_audio_mode_set(encoder, adjusted_mode);	2303	radeon_audio_mode_set(encoder, adjusted_mode);
2305	}	2304	}
2306		2305

drivers/gpu/drm/radeon/dce6_afmt.c+28−34

@@ -93,30 +93,26 @@ void dce6_afmt_select_pin(struct drm_encoder *encoder) · 92 unmodified lines
93	struct radeon_device *rdev = encoder->dev->dev_private;	93	struct radeon_device *rdev = encoder->dev->dev_private;
94	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	94	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
95	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	95	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
96	u32 offset;
97		96
98	if (!dig \|\| !dig->afmt \|\| !dig->afmt->pin)	97	if (!dig \|\| !dig->afmt \|\| !dig->pin)
99	return;	98	return;
100		99
101	offset = dig->afmt->offset;	100	WREG32(AFMT_AUDIO_SRC_CONTROL + dig->afmt->offset,
102		101	AFMT_AUDIO_SRC_SELECT(dig->pin->id));
103	WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
104	AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
105	}	102	}
106		103
107	void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,	104	void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
108	struct drm_connector connector, struct drm_display_mode mode)	105	struct drm_connector *connector,
		106	struct drm_display_mode *mode)
109	{	107	{
110	struct radeon_device *rdev = encoder->dev->dev_private;	108	struct radeon_device *rdev = encoder->dev->dev_private;
111	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	109	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
112	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	110	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
113	u32 tmp = 0, offset;	111	u32 tmp = 0;
114		112
115	if (!dig \|\| !dig->afmt \|\| !dig->afmt->pin)	113	if (!dig \|\| !dig->afmt \|\| !dig->pin)
116	return;	114	return;
117		115
118	offset = dig->afmt->pin->offset;
119
120	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {	116	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
121	if (connector->latency_present[1])	117	if (connector->latency_present[1])
122	tmp = VIDEO_LIPSYNC(connector->video_latency[1]) \|	118	tmp = VIDEO_LIPSYNC(connector->video_latency[1]) \|
@@ -130,24 +126,24 @@ void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, · 7 unmodified lines
130	else	126	else
131	tmp = VIDEO_LIPSYNC(0) \| AUDIO_LIPSYNC(0);	127	tmp = VIDEO_LIPSYNC(0) \| AUDIO_LIPSYNC(0);
132	}	128	}
133	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);	129	WREG32_ENDPOINT(dig->pin->offset,
		130	AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
134	}	131	}
135		132
136	void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,	133	void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
137	u8 *sadb, int sad_count)	134	u8 *sadb, int sad_count)
138	{	135	{
139	struct radeon_device *rdev = encoder->dev->dev_private;	136	struct radeon_device *rdev = encoder->dev->dev_private;
140	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	137	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
141	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	138	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
142	u32 offset, tmp;	139	u32 tmp;
143		140
144	if (!dig \|\| !dig->afmt \|\| !dig->afmt->pin)	141	if (!dig \|\| !dig->afmt \|\| !dig->pin)
145	return;	142	return;
146		143
147	offset = dig->afmt->pin->offset;
148
149	/* program the speaker allocation */	144	/* program the speaker allocation */
150	tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);	145	tmp = RREG32_ENDPOINT(dig->pin->offset,
		146	AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
151	tmp &= ~(DP_CONNECTION \| SPEAKER_ALLOCATION_MASK);	147	tmp &= ~(DP_CONNECTION \| SPEAKER_ALLOCATION_MASK);
152	/* set HDMI mode */	148	/* set HDMI mode */
153	tmp \|= HDMI_CONNECTION;	149	tmp \|= HDMI_CONNECTION;
@@ -155,24 +151,24 @@ void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, · 1 unmodified line
155	tmp \|= SPEAKER_ALLOCATION(sadb[0]);	151	tmp \|= SPEAKER_ALLOCATION(sadb[0]);
156	else	152	else
157	tmp \|= SPEAKER_ALLOCATION(5); /* stereo */	153	tmp \|= SPEAKER_ALLOCATION(5); /* stereo */
158	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);	154	WREG32_ENDPOINT(dig->pin->offset,
		155	AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
159	}	156	}
160		157
161	void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,	158	void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
162	u8 *sadb, int sad_count)	159	u8 *sadb, int sad_count)
163	{	160	{
164	struct radeon_device *rdev = encoder->dev->dev_private;	161	struct radeon_device *rdev = encoder->dev->dev_private;
165	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	162	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
166	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	163	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
167	u32 offset, tmp;	164	u32 tmp;
168		165
169	if (!dig \|\| !dig->afmt \|\| !dig->afmt->pin)	166	if (!dig \|\| !dig->afmt \|\| !dig->pin)
170	return;	167	return;
171		168
172	offset = dig->afmt->pin->offset;
173
174	/* program the speaker allocation */	169	/* program the speaker allocation */
175	tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);	170	tmp = RREG32_ENDPOINT(dig->pin->offset,
		171	AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
176	tmp &= ~(HDMI_CONNECTION \| SPEAKER_ALLOCATION_MASK);	172	tmp &= ~(HDMI_CONNECTION \| SPEAKER_ALLOCATION_MASK);
177	/* set DP mode */	173	/* set DP mode */
178	tmp \|= DP_CONNECTION;	174	tmp \|= DP_CONNECTION;
@@ -180,13 +176,13 @@ void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, · 1 unmodified line
180	tmp \|= SPEAKER_ALLOCATION(sadb[0]);	176	tmp \|= SPEAKER_ALLOCATION(sadb[0]);
181	else	177	else
182	tmp \|= SPEAKER_ALLOCATION(5); /* stereo */	178	tmp \|= SPEAKER_ALLOCATION(5); /* stereo */
183	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);	179	WREG32_ENDPOINT(dig->pin->offset,
		180	AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
184	}	181	}
185		182
186	void dce6_afmt_write_sad_regs(struct drm_encoder *encoder,	183	void dce6_afmt_write_sad_regs(struct drm_encoder *encoder,
187	struct cea_sad *sads, int sad_count)	184	struct cea_sad *sads, int sad_count)
188	{	185	{
189	u32 offset;
190	int i;	186	int i;
191	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	187	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
192	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	188	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
@@ -206,11 +202,9 @@ void dce6_afmt_write_sad_regs(struct drm_encoder *encoder, · 13 unmodified lines
206	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },	202	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
207	};	203	};
208		204
209	if (!dig \|\| !dig->afmt \|\| !dig->afmt->pin)	205	if (!dig \|\| !dig->afmt \|\| !dig->pin)
210	return;	206	return;
211		207
212	offset = dig->afmt->pin->offset;
213
214	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {	208	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
215	u32 value = 0;	209	u32 value = 0;
216	u8 stereo_freqs = 0;	210	u8 stereo_freqs = 0;
@@ -237,7 +231,7 @@ void dce6_afmt_write_sad_regs(struct drm_encoder *encoder, · 20 unmodified lines
237		231
238	value \|= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);	232	value \|= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
239		233
240	WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value);	234	WREG32_ENDPOINT(dig->pin->offset, eld_reg_to_type[i][0], value);
241	}	235	}
242	}	236	}
243		237
@@ -253,7 +247,7 @@ void dce6_audio_enable(struct radeon_device *rdev, · 9 unmodified lines
253	}	247	}
254		248
255	void dce6_hdmi_audio_set_dto(struct radeon_device *rdev,	249	void dce6_hdmi_audio_set_dto(struct radeon_device *rdev,
256	struct radeon_crtc *crtc, unsigned int clock)	250	struct radeon_crtc *crtc, unsigned int clock)
257	{	251	{
258	/* Two dtos; generally use dto0 for HDMI */	252	/* Two dtos; generally use dto0 for HDMI */
259	u32 value = 0;	253	u32 value = 0;
@@ -272,7 +266,7 @@ void dce6_hdmi_audio_set_dto(struct radeon_device *rdev, · 12 unmodified lines
272	}	266	}
273		267
274	void dce6_dp_audio_set_dto(struct radeon_device *rdev,	268	void dce6_dp_audio_set_dto(struct radeon_device *rdev,
275	struct radeon_crtc *crtc, unsigned int clock)	269	struct radeon_crtc *crtc, unsigned int clock)
276	{	270	{
277	/* Two dtos; generally use dto1 for DP */	271	/* Two dtos; generally use dto1 for DP */
278	u32 value = 0;	272	u32 value = 0;

drivers/gpu/drm/radeon/radeon_audio.c+97−107

 static void radeon_audio_enable(struct radeon_device *rdev,
 				struct r600_audio_pin *pin, u8 enable_mask)
 {
+	struct drm_encoder *encoder;
+	struct radeon_encoder *radeon_encoder;
+	struct radeon_encoder_atom_dig *dig;
+	int pin_count = 0;
+	if (!pin)
+		return;
+	if (rdev->mode_info.mode_config_initialized) {
+		list_for_each_entry(encoder, &rdev->ddev->mode_config.encoder_list, head) {
+			if (radeon_encoder_is_digital(encoder)) {
+				radeon_encoder = to_radeon_encoder(encoder);
+				dig = radeon_encoder->enc_priv;
+				if (dig->pin == pin)
+					pin_count++;
+			}
+		}
+		if ((pin_count > 1) && (enable_mask == 0))
+			return;
+	}
 	if (rdev->audio.funcs->enable)
 		rdev->audio.funcs->enable(rdev, pin, enable_mask);
 }
 static void radeon_audio_write_sad_regs(struct drm_encoder *encoder)
 {
-	struct radeon_encoder *radeon_encoder;
+	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
-	struct drm_connector *connector;
+	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
-	struct radeon_connector *radeon_connector = NULL;
 	struct cea_sad *sads;
 	int sad_count;
-	list_for_each_entry(connector,
+	if (!connector)
-		&encoder->dev->mode_config.connector_list, head) {
-		if (connector->encoder == encoder) {
-			radeon_connector = to_radeon_connector(connector);
-			break;
-		}
-	}
-	if (!radeon_connector) {
-		DRM_ERROR("Couldn't find encoder's connector\n");
 		return;
-	}
 	sad_count = drm_edid_to_sad(radeon_connector_edid(connector), &sads);
 	if (sad_count <= 0) {
 	}
 	BUG_ON(!sads);
-	radeon_encoder = to_radeon_encoder(encoder);
 	if (radeon_encoder->audio && radeon_encoder->audio->write_sad_regs)
 		radeon_encoder->audio->write_sad_regs(encoder, sads, sad_count);
 static void radeon_audio_write_speaker_allocation(struct drm_encoder *encoder)
 {
+	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
-	struct drm_connector *connector;
-	struct radeon_connector *radeon_connector = NULL;
 	u8 *sadb = NULL;
 	int sad_count;
-	list_for_each_entry(connector,
+	if (!connector)
-			    &encoder->dev->mode_config.connector_list, head) {
-		if (connector->encoder == encoder) {
-			radeon_connector = to_radeon_connector(connector);
-			break;
-		}
-	}
-	if (!radeon_connector) {
-		DRM_ERROR("Couldn't find encoder's connector\n");
 		return;
-	}
-	sad_count = drm_edid_to_speaker_allocation(
+	sad_count = drm_edid_to_speaker_allocation(radeon_connector_edid(connector),
-		radeon_connector_edid(connector), &sadb);
+						   &sadb);
 	if (sad_count < 0) {
 		DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n",
 			  sad_count);
 }
 static void radeon_audio_write_latency_fields(struct drm_encoder *encoder,
-	struct drm_display_mode *mode)
+					      struct drm_display_mode *mode)
 {
-	struct radeon_encoder *radeon_encoder;
+	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
-	struct drm_connector *connector;
+	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
-	struct radeon_connector *radeon_connector = 0;
-	list_for_each_entry(connector,
-		&encoder->dev->mode_config.connector_list, head) {
-		if (connector->encoder == encoder) {
-			radeon_connector = to_radeon_connector(connector);
-			break;
-		}
-	}
-	if (!radeon_connector) {
+	if (!connector)
-		DRM_ERROR("Couldn't find encoder's connector\n");
 		return;
-	}
-	radeon_encoder = to_radeon_encoder(encoder);
 	if (radeon_encoder->audio && radeon_encoder->audio->write_latency_fields)
 		radeon_encoder->audio->write_latency_fields(encoder, connector, mode);
 }
 void radeon_audio_detect(struct drm_connector *connector,
+			 struct drm_encoder *encoder,
 			 enum drm_connector_status status)
 {
-	struct radeon_device *rdev;
+	struct drm_device *dev = connector->dev;
-	struct radeon_encoder *radeon_encoder;
+	struct radeon_device *rdev = dev->dev_private;
+	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 	struct radeon_encoder_atom_dig *dig;
-	if (!connector || !connector->encoder)
+	if (!radeon_audio_chipset_supported(rdev))
 		return;
-	rdev = connector->encoder->dev->dev_private;
+	if (!radeon_encoder_is_digital(encoder))
-	if (!radeon_audio_chipset_supported(rdev))
 		return;
-	radeon_encoder = to_radeon_encoder(connector->encoder);
 	dig = radeon_encoder->enc_priv;
 	if (status == connector_status_connected) {
-		if (!drm_detect_monitor_audio(radeon_connector_edid(connector))) {
-			radeon_encoder->audio = NULL;
-			return;
-		}
 		if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
 			struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 			radeon_encoder->audio = rdev->audio.hdmi_funcs;
 		}
-		dig->afmt->pin = radeon_audio_get_pin(connector->encoder);
+		if (drm_detect_monitor_audio(radeon_connector_edid(connector))) {
-		radeon_audio_enable(rdev, dig->afmt->pin, 0xf);
+			if (!dig->pin)
+				dig->pin = radeon_audio_get_pin(encoder);
+			radeon_audio_enable(rdev, dig->pin, 0xf);
+		} else {
+			radeon_audio_enable(rdev, dig->pin, 0);
+			dig->pin = NULL;
+		}
 	} else {
-		radeon_audio_enable(rdev, dig->afmt->pin, 0);
+		radeon_audio_enable(rdev, dig->pin, 0);
-		dig->afmt->pin = NULL;
+		dig->pin = NULL;
 	}
 }
 }
 static int radeon_audio_set_avi_packet(struct drm_encoder *encoder,
-	struct drm_display_mode *mode)
+				       struct drm_display_mode *mode)
 {
 	struct radeon_device *rdev = encoder->dev->dev_private;
 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
-	struct drm_connector *connector;
+	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
-	struct radeon_connector *radeon_connector = NULL;
 	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
 	struct hdmi_avi_infoframe frame;
 	int err;
-	list_for_each_entry(connector,
+	if (!connector)
-		&encoder->dev->mode_config.connector_list, head) {
+		return -EINVAL;
-		if (connector->encoder == encoder) {
-			radeon_connector = to_radeon_connector(connector);
-			break;
-		}
-	}
-	if (!radeon_connector) {
-		DRM_ERROR("Couldn't find encoder's connector\n");
-		return -ENOENT;
-	}
 	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 	if (err < 0) {
 		return err;
 	}
-	if (dig && dig->afmt &&
+	if (dig && dig->afmt && radeon_encoder->audio &&
-		radeon_encoder->audio && radeon_encoder->audio->set_avi_packet)
+	    radeon_encoder->audio->set_avi_packet)
 		radeon_encoder->audio->set_avi_packet(rdev, dig->afmt->offset,
 			buffer, sizeof(buffer));
 {
 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
+	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 	if (!dig || !dig->afmt)
 		return;
-	radeon_audio_set_mute(encoder, true);
+	if (!connector)
+		return;
-	radeon_audio_write_speaker_allocation(encoder);
+	if (drm_detect_monitor_audio(radeon_connector_edid(connector))) {
-	radeon_audio_write_sad_regs(encoder);
+		radeon_audio_set_mute(encoder, true);
-	radeon_audio_write_latency_fields(encoder, mode);
-	radeon_audio_set_dto(encoder, mode->clock);
-	radeon_audio_set_vbi_packet(encoder);
-	radeon_hdmi_set_color_depth(encoder);
-	radeon_audio_update_acr(encoder, mode->clock);
-	radeon_audio_set_audio_packet(encoder);
-	radeon_audio_select_pin(encoder);
-	if (radeon_audio_set_avi_packet(encoder, mode) < 0)
+		radeon_audio_write_speaker_allocation(encoder);
-		return;
+		radeon_audio_write_sad_regs(encoder);
+		radeon_audio_write_latency_fields(encoder, mode);
+		radeon_audio_set_dto(encoder, mode->clock);
+		radeon_audio_set_vbi_packet(encoder);
+		radeon_hdmi_set_color_depth(encoder);
+		radeon_audio_update_acr(encoder, mode->clock);
+		radeon_audio_set_audio_packet(encoder);
+		radeon_audio_select_pin(encoder);
+		if (radeon_audio_set_avi_packet(encoder, mode) < 0)
+			return;
-	radeon_audio_set_mute(encoder, false);
+		radeon_audio_set_mute(encoder, false);
+	} else {
+		radeon_hdmi_set_color_depth(encoder);
+		if (radeon_audio_set_avi_packet(encoder, mode) < 0)
+			return;
+	}
 }
 static void radeon_audio_dp_mode_set(struct drm_encoder *encoder,
-	struct drm_display_mode *mode)
+				     struct drm_display_mode *mode)
 {
 	struct drm_device *dev = encoder->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	if (!dig || !dig->afmt)
 		return;
-	radeon_audio_write_speaker_allocation(encoder);
+	if (!connector)
-	radeon_audio_write_sad_regs(encoder);
-	radeon_audio_write_latency_fields(encoder, mode);
-	if (rdev->clock.dp_extclk || ASIC_IS_DCE5(rdev))
-		radeon_audio_set_dto(encoder, rdev->clock.default_dispclk * 10);
-	else
-		radeon_audio_set_dto(encoder, dig_connector->dp_clock);
-	radeon_audio_set_audio_packet(encoder);
-	radeon_audio_select_pin(encoder);
-	if (radeon_audio_set_avi_packet(encoder, mode) < 0)
 		return;
+	if (drm_detect_monitor_audio(radeon_connector_edid(connector))) {
+		radeon_audio_write_speaker_allocation(encoder);
+		radeon_audio_write_sad_regs(encoder);
+		radeon_audio_write_latency_fields(encoder, mode);
+		if (rdev->clock.dp_extclk || ASIC_IS_DCE5(rdev))
+			radeon_audio_set_dto(encoder, rdev->clock.default_dispclk * 10);
+		else
+			radeon_audio_set_dto(encoder, dig_connector->dp_clock);
+		radeon_audio_set_audio_packet(encoder);
+		radeon_audio_select_pin(encoder);
+		if (radeon_audio_set_avi_packet(encoder, mode) < 0)
+			return;
+	}
 }
 void radeon_audio_mode_set(struct drm_encoder *encoder,
-	struct drm_display_mode *mode)
+			   struct drm_display_mode *mode)
 {
 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

drivers/gpu/drm/radeon/radeon_audio.h+2−1

@@ -68,7 +68,8 @@ struct radeon_audio_funcs · 67 unmodified lines
68		68
69	int radeon_audio_init(struct radeon_device *rdev);	69	int radeon_audio_init(struct radeon_device *rdev);
70	void radeon_audio_detect(struct drm_connector *connector,	70	void radeon_audio_detect(struct drm_connector *connector,
71	enum drm_connector_status status);	71	struct drm_encoder *encoder,
		72	enum drm_connector_status status);
72	u32 radeon_audio_endpoint_rreg(struct radeon_device *rdev,	73	u32 radeon_audio_endpoint_rreg(struct radeon_device *rdev,
73	u32 offset, u32 reg);	74	u32 offset, u32 reg);
74	void radeon_audio_endpoint_wreg(struct radeon_device *rdev,	75	void radeon_audio_endpoint_wreg(struct radeon_device *rdev,

drivers/gpu/drm/radeon/radeon_combios.c+6−1

 			if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
 			    (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
+				u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
+				if (hss > lvds->native_mode.hdisplay)
+					hss = (10 - 1) * 8;
 				lvds->native_mode.htotal = lvds->native_mode.hdisplay +
 					(RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
 				lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
-					(RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
+					hss;
 				lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
 					(RBIOS8(tmp + 23) * 8);

drivers/gpu/drm/radeon/radeon_connectors.c+14−4

 	/* updated in get modes as well since we need to know if it's analog or digital */
 	radeon_connector_update_scratch_regs(connector, ret);
-	if (radeon_audio != 0)
+	if ((radeon_audio != 0) && radeon_connector->use_digital) {
-		radeon_audio_detect(connector, ret);
+		const struct drm_connector_helper_funcs *connector_funcs =
+			connector->helper_private;
+		encoder = connector_funcs->best_encoder(connector);
+		if (encoder && (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)) {
+			radeon_connector_get_edid(connector);
+			radeon_audio_detect(connector, encoder, ret);
+		}
+	}
 exit:
 	pm_runtime_mark_last_busy(connector->dev->dev);
 	radeon_connector_update_scratch_regs(connector, ret);
-	if (radeon_audio != 0)
+	if ((radeon_audio != 0) && encoder) {
-		radeon_audio_detect(connector, ret);
+		radeon_connector_get_edid(connector);
+		radeon_audio_detect(connector, encoder, ret);
+	}
 out:
 	pm_runtime_mark_last_busy(connector->dev->dev);

drivers/gpu/drm/radeon/radeon_mode.h+1−1

 	int offset;
 	bool last_buffer_filled_status;
 	int id;
-	struct r600_audio_pin *pin;
 };
 struct radeon_mode_info {
 	uint8_t backlight_level;
 	int panel_mode;
 	struct radeon_afmt *afmt;
+	struct r600_audio_pin *pin;
 	int active_mst_links;
 };

drivers/gpu/drm/ttm/ttm_bo_util.c+2−1

 	else if (boot_cpu_data.x86 > 3)
 		tmp = pgprot_noncached(tmp);
 #endif
-#if defined(__ia64__) || defined(__arm__) || defined(__powerpc__)
+#if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \
+    defined(__powerpc__)
 	if (caching_flags & TTM_PL_FLAG_WC)
 		tmp = pgprot_writecombine(tmp);
 	else

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c+2−2

 	ret = ttm_eu_reserve_buffers(&ticket, &sw_context->validate_nodes,
 				     true, NULL);
 	if (unlikely(ret != 0))
-		goto out_err;
+		goto out_err_nores;
 	ret = vmw_validate_buffers(dev_priv, sw_context);
 	if (unlikely(ret != 0))
 	vmw_resource_relocations_free(&sw_context->res_relocations);
 	vmw_fifo_commit(dev_priv, command_size);
+	mutex_unlock(&dev_priv->binding_mutex);
 	vmw_query_bo_switch_commit(dev_priv, sw_context);
 	ret = vmw_execbuf_fence_commands(file_priv, dev_priv,
 		DRM_ERROR("Fence submission error. Syncing.\n");
 	vmw_resource_list_unreserve(&sw_context->resource_list, false);
-	mutex_unlock(&dev_priv->binding_mutex);
 	ttm_eu_fence_buffer_objects(&ticket, &sw_context->validate_nodes,
 				    (void *) fence);

drivers/hid/hid-apple.c+6−0

 		.driver_data = APPLE_HAS_FN | APPLE_ISO_KEYBOARD },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING8_JIS),
 		.driver_data = APPLE_HAS_FN | APPLE_RDESC_JIS },
+	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING9_ANSI),
+		.driver_data = APPLE_HAS_FN },
+	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING9_ISO),
+		.driver_data = APPLE_HAS_FN | APPLE_ISO_KEYBOARD },
+	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING9_JIS),
+		.driver_data = APPLE_HAS_FN | APPLE_RDESC_JIS },
 	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_2009_ANSI),
 		.driver_data = APPLE_NUMLOCK_EMULATION | APPLE_HAS_FN },
 	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_2009_ISO),

drivers/hid/hid-core.c+6−0

 	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING8_ANSI) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING8_ISO) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING8_JIS) },
+	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING9_ANSI) },
+	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING9_ISO) },
+	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING9_JIS) },
 	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_2009_ANSI) },
 	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_2009_ISO) },
 	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_WIRELESS_2009_JIS) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING8_ANSI) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING8_ISO) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING8_JIS) },
+	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING9_ANSI) },
+	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING9_ISO) },
+	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_WELLSPRING9_JIS) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_FOUNTAIN_TP_ONLY) },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER1_TP_ONLY) },
 	{ }

drivers/hid/hid-cp2112.c+2−0

@@ -356,6 +356,8 @@ static int cp2112_read(struct cp2112_device dev, u8 data, size_t size) · 355 unmodified lines
356	struct cp2112_force_read_report report;	356	struct cp2112_force_read_report report;
357	int ret;	357	int ret;
358		358
		359	if (size > sizeof(dev->read_data))
		360	size = sizeof(dev->read_data);
359	report.report = CP2112_DATA_READ_FORCE_SEND;	361	report.report = CP2112_DATA_READ_FORCE_SEND;
360	report.length = cpu_to_be16(size);	362	report.length = cpu_to_be16(size);
361		363

drivers/hid/hid-ids.h+3−0

 #define USB_DEVICE_ID_APPLE_WELLSPRING8_ANSI	0x0290
 #define USB_DEVICE_ID_APPLE_WELLSPRING8_ISO	0x0291
 #define USB_DEVICE_ID_APPLE_WELLSPRING8_JIS	0x0292
+#define USB_DEVICE_ID_APPLE_WELLSPRING9_ANSI	0x0272
+#define USB_DEVICE_ID_APPLE_WELLSPRING9_ISO		0x0273
+#define USB_DEVICE_ID_APPLE_WELLSPRING9_JIS		0x0274
 #define USB_DEVICE_ID_APPLE_FOUNTAIN_TP_ONLY	0x030a
 #define USB_DEVICE_ID_APPLE_GEYSER1_TP_ONLY	0x030b
 #define USB_DEVICE_ID_APPLE_IRCONTROL	0x8240

drivers/hid/hid-input.c+5−2

 static void hidinput_cleanup_battery(struct hid_device *dev)
 {
+	const struct power_supply_desc *psy_desc;
 	if (!dev->battery)
 		return;
+	psy_desc = dev->battery->desc;
 	power_supply_unregister(dev->battery);
-	kfree(dev->battery->desc->name);
+	kfree(psy_desc->name);
-	kfree(dev->battery->desc);
+	kfree(psy_desc);
 	dev->battery = NULL;
 }
 #else  /* !CONFIG_HID_BATTERY_STRENGTH */

drivers/hid/hid-multitouch.c+7−0

 	/*
 	 * some egalax touchscreens have "application == HID_DG_TOUCHSCREEN"
 	 * for the stylus.
+	 * The check for mt_report_id ensures we don't process
+	 * HID_DG_CONTACTCOUNT from the pen report as it is outside the physical
+	 * collection, but within the report ID.
 	 */
 	if (field->physical == HID_DG_STYLUS)
 		return 0;
+	else if ((field->physical == 0) &&
+		 (field->report->id != td->mt_report_id) &&
+		 (td->mt_report_id != -1))
+		return 0;
 	if (field->application == HID_DG_TOUCHSCREEN ||
 	    field->application == HID_DG_TOUCHPAD)

drivers/hid/hid-uclogic.c+1−1

@@ -858,7 +858,7 @@ static int uclogic_tablet_enable(struct hid_device *hdev) · 857 unmodified lines
858	for (p = drvdata->rdesc;	858	for (p = drvdata->rdesc;
859	p <= drvdata->rdesc + drvdata->rsize - 4;) {	859	p <= drvdata->rdesc + drvdata->rsize - 4;) {
860	if (p[0] == 0xFE && p[1] == 0xED && p[2] == 0x1D &&	860	if (p[0] == 0xFE && p[1] == 0xED && p[2] == 0x1D &&
861	p[3] < sizeof(params)) {	861	p[3] < ARRAY_SIZE(params)) {
862	v = params[p[3]];	862	v = params[p[3]];
863	put_unaligned(cpu_to_le32(v), (s32 *)p);	863	put_unaligned(cpu_to_le32(v), (s32 *)p);
864	p += 4;	864	p += 4;

drivers/hid/usbhid/hid-quirks.c+3−0

 	{ USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_MOUSE_C05A, HID_QUIRK_ALWAYS_POLL },
 	{ USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_MOUSE_C06A, HID_QUIRK_ALWAYS_POLL },
 	{ USB_VENDOR_ID_MGE, USB_DEVICE_ID_MGE_UPS, HID_QUIRK_NOGET },
+	{ USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_SURFACE_PRO_2, HID_QUIRK_NO_INIT_REPORTS },
+	{ USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_2, HID_QUIRK_NO_INIT_REPORTS },
+	{ USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TOUCH_COVER_2, HID_QUIRK_NO_INIT_REPORTS },
 	{ USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_3, HID_QUIRK_NO_INIT_REPORTS },
 	{ USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_3_JP, HID_QUIRK_NO_INIT_REPORTS },
 	{ USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_POWER_COVER, HID_QUIRK_NO_INIT_REPORTS },

drivers/hid/wacom_sys.c+41−35

 	pad_input_dev = NULL;
 	wacom_wac->pad_registered = false;
 fail_register_pad_input:
-	input_unregister_device(touch_input_dev);
+	if (touch_input_dev)
+		input_unregister_device(touch_input_dev);
 	wacom_wac->touch_input = NULL;
 	wacom_wac->touch_registered = false;
 fail_register_touch_input:
-	input_unregister_device(pen_input_dev);
+	if (pen_input_dev)
+		input_unregister_device(pen_input_dev);
 	wacom_wac->pen_input = NULL;
 	wacom_wac->pen_registered = false;
 fail_register_pen_input:
 	return error;
 }
+/*
+ * Not all devices report physical dimensions from HID.
+ * Compute the default from hardcoded logical dimension
+ * and resolution before driver overwrites them.
+ */
+static void wacom_set_default_phy(struct wacom_features *features)
+{
+	if (features->x_resolution) {
+		features->x_phy = (features->x_max * 100) /
+					features->x_resolution;
+		features->y_phy = (features->y_max * 100) /
+					features->y_resolution;
+	}
+}
+static void wacom_calculate_res(struct wacom_features *features)
+{
+	/* set unit to "100th of a mm" for devices not reported by HID */
+	if (!features->unit) {
+		features->unit = 0x11;
+		features->unitExpo = -3;
+	}
+	features->x_resolution = wacom_calc_hid_res(features->x_max,
+						    features->x_phy,
+						    features->unit,
+						    features->unitExpo);
+	features->y_resolution = wacom_calc_hid_res(features->y_max,
+						    features->y_phy,
+						    features->unit,
+						    features->unitExpo);
+}
 static void wacom_wireless_work(struct work_struct *work)
 {
 	struct wacom *wacom = container_of(work, struct wacom, work);
 		if (wacom_wac1->features.type != INTUOSHT &&
 		    wacom_wac1->features.type != BAMBOO_PT)
 			wacom_wac1->features.device_type |= WACOM_DEVICETYPE_PAD;
+		wacom_set_default_phy(&wacom_wac1->features);
+		wacom_calculate_res(&wacom_wac1->features);
 		snprintf(wacom_wac1->pen_name, WACOM_NAME_MAX, "%s (WL) Pen",
 			 wacom_wac1->features.name);
 		snprintf(wacom_wac1->pad_name, WACOM_NAME_MAX, "%s (WL) Pad",
 			wacom_wac2->features =
 				*((struct wacom_features *)id->driver_data);
 			wacom_wac2->features.pktlen = WACOM_PKGLEN_BBTOUCH3;
+			wacom_set_default_phy(&wacom_wac2->features);
 			wacom_wac2->features.x_max = wacom_wac2->features.y_max = 4096;
+			wacom_calculate_res(&wacom_wac2->features);
 			snprintf(wacom_wac2->touch_name, WACOM_NAME_MAX,
 				 "%s (WL) Finger",wacom_wac2->features.name);
 			snprintf(wacom_wac2->pad_name, WACOM_NAME_MAX,
 	}
 }
-/*
- * Not all devices report physical dimensions from HID.
- * Compute the default from hardcoded logical dimension
- * and resolution before driver overwrites them.
- */
-static void wacom_set_default_phy(struct wacom_features *features)
-{
-	if (features->x_resolution) {
-		features->x_phy = (features->x_max * 100) /
-					features->x_resolution;
-		features->y_phy = (features->y_max * 100) /
-					features->y_resolution;
-	}
-}
-static void wacom_calculate_res(struct wacom_features *features)
-{
-	/* set unit to "100th of a mm" for devices not reported by HID */
-	if (!features->unit) {
-		features->unit = 0x11;
-		features->unitExpo = -3;
-	}
-	features->x_resolution = wacom_calc_hid_res(features->x_max,
-						    features->x_phy,
-						    features->unit,
-						    features->unitExpo);
-	features->y_resolution = wacom_calc_hid_res(features->y_max,
-						    features->y_phy,
-						    features->unit,
-						    features->unitExpo);
-}
 static size_t wacom_compute_pktlen(struct hid_device *hdev)
 {
 	struct hid_report_enum *report_enum;

drivers/hid/wacom_wac.c+3−0

 			features->x_max = 4096;
 			features->y_max = 4096;
 		}
+		else if (features->pktlen == WACOM_PKGLEN_BBTOUCH) {
+			features->device_type |= WACOM_DEVICETYPE_PAD;
+		}
 	}
 	/*

drivers/hwmon/dell-smm-hwmon.c+17−1

@@ -929,6 +929,21 @@ static struct dmi_system_id i8k_dmi_table[] __initdata = { · 928 unmodified lines
929		929
930	MODULE_DEVICE_TABLE(dmi, i8k_dmi_table);	930	MODULE_DEVICE_TABLE(dmi, i8k_dmi_table);
931		931
		932	static struct dmi_system_id i8k_blacklist_dmi_table[] __initdata = {
		933	{
		934	/*
		935	* CPU fan speed going up and down on Dell Studio XPS 8100
		936	* for unknown reasons.
		937	*/
		938	.ident = "Dell Studio XPS 8100",
		939	.matches = {
		940	DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
		941	DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Studio XPS 8100"),
		942	},
		943	},
		944	{ }
		945	};
		946
932	/*	947	/*
933	* Probe for the presence of a supported laptop.	948	* Probe for the presence of a supported laptop.
934	*/	949	*/
@@ -940,7 +955,8 @@ static int __init i8k_probe(void) · 5 unmodified lines
940	/*	955	/*
941	* Get DMI information	956	* Get DMI information
942	*/	957	*/
943	if (!dmi_check_system(i8k_dmi_table)) {	958	if (!dmi_check_system(i8k_dmi_table) \|\|
		959	dmi_check_system(i8k_blacklist_dmi_table)) {
944	if (!ignore_dmi && !force)	960	if (!ignore_dmi && !force)
945	return -ENODEV;	961	return -ENODEV;
946		962

drivers/hwmon/g762.c+1−0

@@ -582,6 +582,7 @@ static const struct of_device_id g762_dt_match[] = { · 581 unmodified lines
582	{ .compatible = "gmt,g763" },	582	{ .compatible = "gmt,g763" },
583	{ },	583	{ },
584	};	584	};
		585	MODULE_DEVICE_TABLE(of, g762_dt_match);
585		586
586	/*	587	/*
587	* Grab clock (a required property), enable it, get (fixed) clock frequency	588	* Grab clock (a required property), enable it, get (fixed) clock frequency

drivers/hwmon/nct7802.c+1−1

@@ -195,7 +195,7 @@ abort: · 194 unmodified lines
195	}	195	}
196		196
197	static int nct7802_write_voltage(struct nct7802_data *data, int nr, int index,	197	static int nct7802_write_voltage(struct nct7802_data *data, int nr, int index,
198	unsigned int voltage)	198	unsigned long voltage)
199	{	199	{
200	int shift = 8 - REG_VOLTAGE_LIMIT_MSB_SHIFT[index - 1][nr];	200	int shift = 8 - REG_VOLTAGE_LIMIT_MSB_SHIFT[index - 1][nr];
201	int err;	201	int err;

drivers/hwmon/nct7904.c+30−28

@@ -412,8 +412,9 @@ static ssize_t show_pwm(struct device *dev, · 411 unmodified lines
412	return sprintf(buf, "%d\n", val);	412	return sprintf(buf, "%d\n", val);
413	}	413	}
414		414
415	static ssize_t store_mode(struct device dev, struct device_attribute devattr,	415	static ssize_t store_enable(struct device *dev,
416	const char *buf, size_t count)	416	struct device_attribute *devattr,
		417	const char *buf, size_t count)
417	{	418	{
418	int index = to_sensor_dev_attr(devattr)->index;	419	int index = to_sensor_dev_attr(devattr)->index;
419	struct nct7904_data *data = dev_get_drvdata(dev);	420	struct nct7904_data *data = dev_get_drvdata(dev);
@@ -422,18 +423,18 @@ static ssize_t store_mode(struct device dev, struct device_attribute devattr, · 2 unmodified lines
422		423
423	if (kstrtoul(buf, 10, &val) < 0)	424	if (kstrtoul(buf, 10, &val) < 0)
424	return -EINVAL;	425	return -EINVAL;
425	if (val > 1 \|\| (val && !data->fan_mode[index]))	426	if (val < 1 \|\| val > 2 \|\| (val == 2 && !data->fan_mode[index]))
426	return -EINVAL;	427	return -EINVAL;
427		428
428	ret = nct7904_write_reg(data, BANK_3, FANCTL1_FMR_REG + index,	429	ret = nct7904_write_reg(data, BANK_3, FANCTL1_FMR_REG + index,
429	val ? data->fan_mode[index] : 0);	430	val == 2 ? data->fan_mode[index] : 0);
430		431
431	return ret ? ret : count;	432	return ret ? ret : count;
432	}	433	}
433		434
434	/* Return 0 for manual mode or 1 for SmartFan mode */	435	/* Return 1 for manual mode or 2 for SmartFan mode */
435	static ssize_t show_mode(struct device *dev,	436	static ssize_t show_enable(struct device *dev,
436	struct device_attribute devattr, char buf)	437	struct device_attribute devattr, char buf)
437	{	438	{
438	int index = to_sensor_dev_attr(devattr)->index;	439	int index = to_sensor_dev_attr(devattr)->index;
439	struct nct7904_data *data = dev_get_drvdata(dev);	440	struct nct7904_data *data = dev_get_drvdata(dev);
@@ -443,36 +444,36 @@ static ssize_t show_mode(struct device *dev, · 3 unmodified lines
443	if (val < 0)	444	if (val < 0)
444	return val;	445	return val;
445		446
446	return sprintf(buf, "%d\n", val ? 1 : 0);	447	return sprintf(buf, "%d\n", val ? 2 : 1);
447	}	448	}
448		449
449	/* 2 attributes per channel: pwm and mode */	450	/* 2 attributes per channel: pwm and mode */
450	static SENSOR_DEVICE_ATTR(fan1_pwm, S_IRUGO \| S_IWUSR,	451	static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO \| S_IWUSR,
451	show_pwm, store_pwm, 0);	452	show_pwm, store_pwm, 0);
452	static SENSOR_DEVICE_ATTR(fan1_mode, S_IRUGO \| S_IWUSR,	453	static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO \| S_IWUSR,
453	show_mode, store_mode, 0);	454	show_enable, store_enable, 0);
454	static SENSOR_DEVICE_ATTR(fan2_pwm, S_IRUGO \| S_IWUSR,	455	static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO \| S_IWUSR,
455	show_pwm, store_pwm, 1);	456	show_pwm, store_pwm, 1);
456	static SENSOR_DEVICE_ATTR(fan2_mode, S_IRUGO \| S_IWUSR,	457	static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO \| S_IWUSR,
457	show_mode, store_mode, 1);	458	show_enable, store_enable, 1);
458	static SENSOR_DEVICE_ATTR(fan3_pwm, S_IRUGO \| S_IWUSR,	459	static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO \| S_IWUSR,
459	show_pwm, store_pwm, 2);	460	show_pwm, store_pwm, 2);
460	static SENSOR_DEVICE_ATTR(fan3_mode, S_IRUGO \| S_IWUSR,	461	static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO \| S_IWUSR,
461	show_mode, store_mode, 2);	462	show_enable, store_enable, 2);
462	static SENSOR_DEVICE_ATTR(fan4_pwm, S_IRUGO \| S_IWUSR,	463	static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO \| S_IWUSR,
463	show_pwm, store_pwm, 3);	464	show_pwm, store_pwm, 3);
464	static SENSOR_DEVICE_ATTR(fan4_mode, S_IRUGO \| S_IWUSR,	465	static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO \| S_IWUSR,
465	show_mode, store_mode, 3);	466	show_enable, store_enable, 3);
466		467
467	static struct attribute *nct7904_fanctl_attrs[] = {	468	static struct attribute *nct7904_fanctl_attrs[] = {
468	&sensor_dev_attr_fan1_pwm.dev_attr.attr,	469	&sensor_dev_attr_pwm1.dev_attr.attr,
469	&sensor_dev_attr_fan1_mode.dev_attr.attr,	470	&sensor_dev_attr_pwm1_enable.dev_attr.attr,
470	&sensor_dev_attr_fan2_pwm.dev_attr.attr,	471	&sensor_dev_attr_pwm2.dev_attr.attr,
471	&sensor_dev_attr_fan2_mode.dev_attr.attr,	472	&sensor_dev_attr_pwm2_enable.dev_attr.attr,
472	&sensor_dev_attr_fan3_pwm.dev_attr.attr,	473	&sensor_dev_attr_pwm3.dev_attr.attr,
473	&sensor_dev_attr_fan3_mode.dev_attr.attr,	474	&sensor_dev_attr_pwm3_enable.dev_attr.attr,
474	&sensor_dev_attr_fan4_pwm.dev_attr.attr,	475	&sensor_dev_attr_pwm4.dev_attr.attr,
475	&sensor_dev_attr_fan4_mode.dev_attr.attr,	476	&sensor_dev_attr_pwm4_enable.dev_attr.attr,
476	NULL	477	NULL
477	};	478	};
478		479
@@ -574,6 +575,7 @@ static const struct i2c_device_id nct7904_id[] = { · 95 unmodified lines
574	{"nct7904", 0},	575	{"nct7904", 0},
575	{}	576	{}
576	};	577	};
		578	MODULE_DEVICE_TABLE(i2c, nct7904_id);
577		579
578	static struct i2c_driver nct7904_driver = {	580	static struct i2c_driver nct7904_driver = {
579	.class = I2C_CLASS_HWMON,	581	.class = I2C_CLASS_HWMON,

drivers/i2c/busses/i2c-bfin-twi.c+2−2

@@ -692,7 +692,7 @@ static int i2c_bfin_twi_probe(struct platform_device *pdev) · 691 unmodified lines
692		692
693	platform_set_drvdata(pdev, iface);	693	platform_set_drvdata(pdev, iface);
694		694
695	dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "	695	dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Controller, "
696	"regs_base@%p\n", iface->regs_base);	696	"regs_base@%p\n", iface->regs_base);
697		697
698	return 0;	698	return 0;
@@ -735,6 +735,6 @@ subsys_initcall(i2c_bfin_twi_init); · 36 unmodified lines
735	module_exit(i2c_bfin_twi_exit);	735	module_exit(i2c_bfin_twi_exit);
736		736
737	MODULE_AUTHOR("Bryan Wu, Sonic Zhang");	737	MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
738	MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");	738	MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Controller Driver");
739	MODULE_LICENSE("GPL");	739	MODULE_LICENSE("GPL");
740	MODULE_ALIAS("platform:i2c-bfin-twi");	740	MODULE_ALIAS("platform:i2c-bfin-twi");

drivers/i2c/busses/i2c-omap.c+11−0

 	u32 reg;
 	reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
+	/* enable test mode */
 	reg |= OMAP_I2C_SYSTEST_ST_EN;
+	/* select SDA/SCL IO mode */
+	reg |= 3 << OMAP_I2C_SYSTEST_TMODE_SHIFT;
+	/* set SCL to high-impedance state (reset value is 0) */
+	reg |= OMAP_I2C_SYSTEST_SCL_O;
+	/* set SDA to high-impedance state (reset value is 0) */
+	reg |= OMAP_I2C_SYSTEST_SDA_O;
 	omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
 }
 	u32 reg;
 	reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
+	/* restore reset values */
 	reg &= ~OMAP_I2C_SYSTEST_ST_EN;
+	reg &= ~OMAP_I2C_SYSTEST_TMODE_MASK;
+	reg &= ~OMAP_I2C_SYSTEST_SCL_O;
+	reg &= ~OMAP_I2C_SYSTEST_SDA_O;
 	omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
 }

drivers/i2c/i2c-core.c+17−7

 	if (bri->prepare_recovery)
 		bri->prepare_recovery(adap);
+	bri->set_scl(adap, val);
+	ndelay(RECOVERY_NDELAY);
 	/*
 	 * By this time SCL is high, as we need to give 9 falling-rising edges
 	 */
 int i2c_generic_scl_recovery(struct i2c_adapter *adap)
 {
-	adap->bus_recovery_info->set_scl(adap, 1);
 	return i2c_generic_recovery(adap);
 }
 EXPORT_SYMBOL_GPL(i2c_generic_scl_recovery);
 struct i2c_client *of_find_i2c_device_by_node(struct device_node *node)
 {
 	struct device *dev;
+	struct i2c_client *client;
-	dev = bus_find_device(&i2c_bus_type, NULL, node,
+	dev = bus_find_device(&i2c_bus_type, NULL, node, of_dev_node_match);
-					 of_dev_node_match);
 	if (!dev)
 		return NULL;
-	return i2c_verify_client(dev);
+	client = i2c_verify_client(dev);
+	if (!client)
+		put_device(dev);
+	return client;
 }
 EXPORT_SYMBOL(of_find_i2c_device_by_node);
 struct i2c_adapter *of_find_i2c_adapter_by_node(struct device_node *node)
 {
 	struct device *dev;
+	struct i2c_adapter *adapter;
-	dev = bus_find_device(&i2c_bus_type, NULL, node,
+	dev = bus_find_device(&i2c_bus_type, NULL, node, of_dev_node_match);
-					 of_dev_node_match);
 	if (!dev)
 		return NULL;
-	return i2c_verify_adapter(dev);
+	adapter = i2c_verify_adapter(dev);
+	if (!adapter)
+		put_device(dev);
+	return adapter;
 }
 EXPORT_SYMBOL(of_find_i2c_adapter_by_node);
 #else

drivers/i2c/i2c-slave-eeprom.c+0−6

 	struct eeprom_data *eeprom;
 	unsigned long flags;
-	if (off + count > attr->size)
-		return -EFBIG;
 	eeprom = dev_get_drvdata(container_of(kobj, struct device, kobj));
 	spin_lock_irqsave(&eeprom->buffer_lock, flags);
 	struct eeprom_data *eeprom;
 	unsigned long flags;
-	if (off + count > attr->size)
-		return -EFBIG;
 	eeprom = dev_get_drvdata(container_of(kobj, struct device, kobj));
 	spin_lock_irqsave(&eeprom->buffer_lock, flags);

drivers/iio/accel/mma8452.c+4−4

@@ -557,21 +557,21 @@ static void mma8452_transient_interrupt(struct iio_dev *indio_dev) · 556 unmodified lines
557	if (src & MMA8452_TRANSIENT_SRC_XTRANSE)	557	if (src & MMA8452_TRANSIENT_SRC_XTRANSE)
558	iio_push_event(indio_dev,	558	iio_push_event(indio_dev,
559	IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,	559	IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
560	IIO_EV_TYPE_THRESH,	560	IIO_EV_TYPE_MAG,
561	IIO_EV_DIR_RISING),	561	IIO_EV_DIR_RISING),
562	ts);	562	ts);
563		563
564	if (src & MMA8452_TRANSIENT_SRC_YTRANSE)	564	if (src & MMA8452_TRANSIENT_SRC_YTRANSE)
565	iio_push_event(indio_dev,	565	iio_push_event(indio_dev,
566	IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,	566	IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
567	IIO_EV_TYPE_THRESH,	567	IIO_EV_TYPE_MAG,
568	IIO_EV_DIR_RISING),	568	IIO_EV_DIR_RISING),
569	ts);	569	ts);
570		570
571	if (src & MMA8452_TRANSIENT_SRC_ZTRANSE)	571	if (src & MMA8452_TRANSIENT_SRC_ZTRANSE)
572	iio_push_event(indio_dev,	572	iio_push_event(indio_dev,
573	IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,	573	IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
574	IIO_EV_TYPE_THRESH,	574	IIO_EV_TYPE_MAG,
575	IIO_EV_DIR_RISING),	575	IIO_EV_DIR_RISING),
576	ts);	576	ts);
577	}	577	}
@@ -644,7 +644,7 @@ static int mma8452_reg_access_dbg(struct iio_dev *indio_dev, · 66 unmodified lines
644		644
645	static const struct iio_event_spec mma8452_transient_event[] = {	645	static const struct iio_event_spec mma8452_transient_event[] = {
646	{	646	{
647	.type = IIO_EV_TYPE_THRESH,	647	.type = IIO_EV_TYPE_MAG,
648	.dir = IIO_EV_DIR_RISING,	648	.dir = IIO_EV_DIR_RISING,
649	.mask_separate = BIT(IIO_EV_INFO_ENABLE),	649	.mask_separate = BIT(IIO_EV_INFO_ENABLE),
650	.mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) \|	650	.mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) \|

drivers/iio/adc/mcp320x.c+2−0

@@ -299,6 +299,8 @@ static int mcp320x_probe(struct spi_device *spi) · 298 unmodified lines
299	indio_dev->channels = chip_info->channels;	299	indio_dev->channels = chip_info->channels;
300	indio_dev->num_channels = chip_info->num_channels;	300	indio_dev->num_channels = chip_info->num_channels;
301		301
		302	adc->chip_info = chip_info;
		303
302	adc->transfer[0].tx_buf = &adc->tx_buf;	304	adc->transfer[0].tx_buf = &adc->tx_buf;
303	adc->transfer[0].len = sizeof(adc->tx_buf);	305	adc->transfer[0].len = sizeof(adc->tx_buf);
304	adc->transfer[1].rx_buf = adc->rx_buf;	306	adc->transfer[1].rx_buf = adc->rx_buf;

drivers/iio/adc/vf610_adc.c+1−1

@@ -635,7 +635,7 @@ static int vf610_adc_reg_access(struct iio_dev *indio_dev, · 634 unmodified lines
635	struct vf610_adc *info = iio_priv(indio_dev);	635	struct vf610_adc *info = iio_priv(indio_dev);
636		636
637	if ((readval == NULL) \|\|	637	if ((readval == NULL) \|\|
638	(!(reg % 4) \|\| (reg > VF610_REG_ADC_PCTL)))	638	((reg % 4) \|\| (reg > VF610_REG_ADC_PCTL)))
639	return -EINVAL;	639	return -EINVAL;
640		640
641	*readval = readl(info->regs + reg);	641	*readval = readl(info->regs + reg);

drivers/iio/light/stk3310.c+13−13

 			      int *val, int *val2)
 {
 	u8 reg;
-	u16 buf;
+	__be16 buf;
 	int ret;
 	struct stk3310_data *data = iio_priv(indio_dev);
 		dev_err(&data->client->dev, "register read failed\n");
 		return ret;
 	}
-	*val = swab16(buf);
+	*val = be16_to_cpu(buf);
 	return IIO_VAL_INT;
 }
 			       int val, int val2)
 {
 	u8 reg;
-	u16 buf;
+	__be16 buf;
 	int ret;
 	unsigned int index;
 	struct stk3310_data *data = iio_priv(indio_dev);
 	else
 		return -EINVAL;
-	buf = swab16(val);
+	buf = cpu_to_be16(val);
 	ret = regmap_bulk_write(data->regmap, reg, &buf, 2);
 	if (ret < 0)
 		dev_err(&client->dev, "failed to set PS threshold!\n");
 			    int *val, int *val2, long mask)
 {
 	u8 reg;
-	u16 buf;
+	__be16 buf;
 	int ret;
 	unsigned int index;
 	struct stk3310_data *data = iio_priv(indio_dev);
 			mutex_unlock(&data->lock);
 			return ret;
 		}
-		*val = swab16(buf);
+		*val = be16_to_cpu(buf);
 		mutex_unlock(&data->lock);
 		return IIO_VAL_INT;
 	case IIO_CHAN_INFO_INT_TIME:
 	if (ret < 0)
 		return ret;
-	ret = iio_device_register(indio_dev);
+	if (client->irq < 0)
-	if (ret < 0) {
-		dev_err(&client->dev, "device_register failed\n");
-		stk3310_set_state(data, STK3310_STATE_STANDBY);
-	}
-	if (client->irq <= 0)
 		client->irq = stk3310_gpio_probe(client);
 	if (client->irq >= 0) {
 					client->irq);
 	}
+	ret = iio_device_register(indio_dev);
+	if (ret < 0) {
+		dev_err(&client->dev, "device_register failed\n");
+		stk3310_set_state(data, STK3310_STATE_STANDBY);
+	}
 	return ret;
 }

drivers/iio/magnetometer/Kconfig+1−0

@@ -90,6 +90,7 @@ config IIO_ST_MAGN_SPI_3AXIS · 89 unmodified lines
90	config BMC150_MAGN	90	config BMC150_MAGN
91	tristate "Bosch BMC150 Magnetometer Driver"	91	tristate "Bosch BMC150 Magnetometer Driver"
92	depends on I2C	92	depends on I2C
		93	select REGMAP_I2C
93	select IIO_BUFFER	94	select IIO_BUFFER
94	select IIO_TRIGGERED_BUFFER	95	select IIO_TRIGGERED_BUFFER
95	help	96	help

drivers/iio/magnetometer/bmc150_magn.c+2−2

@@ -706,11 +706,11 @@ static int bmc150_magn_init(struct bmc150_magn_data *data) · 705 unmodified lines
706	goto err_poweroff;	706	goto err_poweroff;
707	}	707	}
708	if (chip_id != BMC150_MAGN_CHIP_ID_VAL) {	708	if (chip_id != BMC150_MAGN_CHIP_ID_VAL) {
709	dev_err(&data->client->dev, "Invalid chip id 0x%x\n", ret);	709	dev_err(&data->client->dev, "Invalid chip id 0x%x\n", chip_id);
710	ret = -ENODEV;	710	ret = -ENODEV;
711	goto err_poweroff;	711	goto err_poweroff;
712	}	712	}
713	dev_dbg(&data->client->dev, "Chip id %x\n", ret);	713	dev_dbg(&data->client->dev, "Chip id %x\n", chip_id);
714		714
715	preset = bmc150_magn_presets_table[BMC150_MAGN_DEFAULT_PRESET];	715	preset = bmc150_magn_presets_table[BMC150_MAGN_DEFAULT_PRESET];
716	ret = bmc150_magn_set_odr(data, preset.odr);	716	ret = bmc150_magn_set_odr(data, preset.odr);

drivers/iio/magnetometer/mmc35240.c+7−5

@@ -202,8 +202,8 @@ static int mmc35240_hw_set(struct mmc35240_data *data, bool set) · 201 unmodified lines
202	coil_bit = MMC35240_CTRL0_RESET_BIT;	202	coil_bit = MMC35240_CTRL0_RESET_BIT;
203		203
204	return regmap_update_bits(data->regmap, MMC35240_REG_CTRL0,	204	return regmap_update_bits(data->regmap, MMC35240_REG_CTRL0,
205	MMC35240_CTRL0_REFILL_BIT,	205	coil_bit, coil_bit);
206	coil_bit);	206
207	}	207	}
208		208
209	static int mmc35240_init(struct mmc35240_data *data)	209	static int mmc35240_init(struct mmc35240_data *data)
@@ -222,14 +222,15 @@ static int mmc35240_init(struct mmc35240_data *data) · 12 unmodified lines
222		222
223	/*	223	/*
224	* make sure we restore sensor characteristics, by doing	224	* make sure we restore sensor characteristics, by doing
225	* a RESET/SET sequence	225	* a SET/RESET sequence, the axis polarity being naturally
		226	* aligned after RESET
226	*/	227	*/
227	ret = mmc35240_hw_set(data, false);	228	ret = mmc35240_hw_set(data, true);
228	if (ret < 0)	229	if (ret < 0)
229	return ret;	230	return ret;
230	usleep_range(MMC53240_WAIT_SET_RESET, MMC53240_WAIT_SET_RESET + 1);	231	usleep_range(MMC53240_WAIT_SET_RESET, MMC53240_WAIT_SET_RESET + 1);
231		232
232	ret = mmc35240_hw_set(data, true);	233	ret = mmc35240_hw_set(data, false);
233	if (ret < 0)	234	if (ret < 0)
234	return ret;	235	return ret;
235		236
@@ -503,6 +504,7 @@ static int mmc35240_probe(struct i2c_client *client, · 267 unmodified lines
503	}	504	}
504		505
505	data = iio_priv(indio_dev);	506	data = iio_priv(indio_dev);
		507	i2c_set_clientdata(client, indio_dev);
506	data->client = client;	508	data->client = client;
507	data->regmap = regmap;	509	data->regmap = regmap;
508	data->res = MMC35240_16_BITS_SLOW;	510	data->res = MMC35240_16_BITS_SLOW;

drivers/iio/temperature/mlx90614.c+1−1

@@ -204,7 +204,7 @@ static int mlx90614_read_raw(struct iio_dev *indio_dev, · 203 unmodified lines
204	*val = ret;	204	*val = ret;
205	return IIO_VAL_INT;	205	return IIO_VAL_INT;
206	case IIO_CHAN_INFO_OFFSET:	206	case IIO_CHAN_INFO_OFFSET:
207	*val = 13657;	207	*val = -13657;
208	*val2 = 500000;	208	*val2 = 500000;
209	return IIO_VAL_INT_PLUS_MICRO;	209	return IIO_VAL_INT_PLUS_MICRO;
210	case IIO_CHAN_INFO_SCALE:	210	case IIO_CHAN_INFO_SCALE:

drivers/infiniband/hw/cxgb3/iwch_provider.c+4−0

 	/*
 	 * T3 only supports 32 bits of size.
 	 */
+	if (sizeof(phys_addr_t) > 4) {
+		pr_warn_once(MOD "Cannot support dma_mrs on this platform.\n");
+		return ERR_PTR(-ENOTSUPP);
+	}
 	bl.size = 0xffffffff;
 	bl.addr = 0;
 	kva = 0;

drivers/infiniband/hw/ipath/ipath_driver.c+4−2

  * SOFTWARE.
  */
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 #include <linux/sched.h>
 #include <linux/spinlock.h>
 #include <linux/idr.h>
 	u32 bar0 = 0, bar1 = 0;
 #ifdef CONFIG_X86_64
-	if (WARN(pat_enabled(),
+	if (pat_enabled()) {
-		 "ipath needs PAT disabled, boot with nopat kernel parameter\n")) {
+		pr_warn("ipath needs PAT disabled, boot with nopat kernel parameter\n");
 		ret = -ENODEV;
 		goto bail;
 	}

drivers/infiniband/hw/ocrdma/ocrdma.h+34−19

@@ -1,21 +1,36 @@
1	/*******************************************************************	1	/* This file is part of the Emulex RoCE Device Driver for
2	* This file is part of the Emulex RoCE Device Driver for *	2	* RoCE (RDMA over Converged Ethernet) adapters.
3	* RoCE (RDMA over Converged Ethernet) adapters. *	3	* Copyright (C) 2012-2015 Emulex. All rights reserved.
4	* Copyright (C) 2008-2012 Emulex. All rights reserved. *	4	* EMULEX and SLI are trademarks of Emulex.
5	* EMULEX and SLI are trademarks of Emulex. *	5	* www.emulex.com
6	* www.emulex.com *	6	*
7	* *	7	* This software is available to you under a choice of one of two licenses.
8	* This program is free software; you can redistribute it and/or *	8	* You may choose to be licensed under the terms of the GNU General Public
9	* modify it under the terms of version 2 of the GNU General *	9	* License (GPL) Version 2, available from the file COPYING in the main
10	* Public License as published by the Free Software Foundation. *	10	* directory of this source tree, or the BSD license below:
11	* This program is distributed in the hope that it will be useful. *	11	*
12	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *	12	* Redistribution and use in source and binary forms, with or without
13	* WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *	13	* modification, are permitted provided that the following conditions
14	* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *	14	* are met:
15	* DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *	15	*
16	* TO BE LEGALLY INVALID. See the GNU General Public License for *	16	* - Redistributions of source code must retain the above copyright notice,
17	* more details, a copy of which can be found in the file COPYING *	17	* this list of conditions and the following disclaimer.
18	* included with this package. *	18	*
		19	* - Redistributions in binary form must reproduce the above copyright
		20	* notice, this list of conditions and the following disclaimer in
		21	* the documentation and/or other materials provided with the distribution.
		22	*
		23	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		24	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
		25	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
		26	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
		27	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
		28	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
		29	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
		30	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
		31	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
		32	* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
		33	* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19	*	34	*
20	* Contact Information:	35	* Contact Information:
21	* linux-drivers@emulex.com	36	* linux-drivers@emulex.com
@@ -23,7 +38,7 @@ · 1 unmodified line
23	* Emulex	38	* Emulex
24	* 3333 Susan Street	39	* 3333 Susan Street
25	* Costa Mesa, CA 92626	40	* Costa Mesa, CA 92626
26	*******************************************************************/	41	*/
27		42
28	#ifndef __OCRDMA_H__	43	#ifndef __OCRDMA_H__
29	#define __OCRDMA_H__	44	#define __OCRDMA_H__

drivers/infiniband/hw/ocrdma/ocrdma_abi.h+34−19

@@ -1,21 +1,36 @@
1	/*******************************************************************	1	/* This file is part of the Emulex RoCE Device Driver for
2	* This file is part of the Emulex RoCE Device Driver for *	2	* RoCE (RDMA over Converged Ethernet) adapters.
3	* RoCE (RDMA over Converged Ethernet) adapters. *	3	* Copyright (C) 2012-2015 Emulex. All rights reserved.
4	* Copyright (C) 2008-2012 Emulex. All rights reserved. *	4	* EMULEX and SLI are trademarks of Emulex.
5	* EMULEX and SLI are trademarks of Emulex. *	5	* www.emulex.com
6	* www.emulex.com *	6	*
7	* *	7	* This software is available to you under a choice of one of two licenses.
8	* This program is free software; you can redistribute it and/or *	8	* You may choose to be licensed under the terms of the GNU General Public
9	* modify it under the terms of version 2 of the GNU General *	9	* License (GPL) Version 2, available from the file COPYING in the main
10	* Public License as published by the Free Software Foundation. *	10	* directory of this source tree, or the BSD license below:
11	* This program is distributed in the hope that it will be useful. *	11	*
12	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *	12	* Redistribution and use in source and binary forms, with or without
13	* WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *	13	* modification, are permitted provided that the following conditions
14	* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *	14	* are met:
15	* DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *	15	*
16	* TO BE LEGALLY INVALID. See the GNU General Public License for *	16	* - Redistributions of source code must retain the above copyright notice,
17	* more details, a copy of which can be found in the file COPYING *	17	* this list of conditions and the following disclaimer.
18	* included with this package. *	18	*
		19	* - Redistributions in binary form must reproduce the above copyright
		20	* notice, this list of conditions and the following disclaimer in
		21	* the documentation and/or other materials provided with the distribution.
		22	*
		23	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		24	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
		25	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
		26	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
		27	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
		28	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
		29	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
		30	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
		31	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
		32	* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
		33	* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19	*	34	*
20	* Contact Information:	35	* Contact Information:
21	* linux-drivers@emulex.com	36	* linux-drivers@emulex.com
@@ -23,7 +38,7 @@ · 1 unmodified line
23	* Emulex	38	* Emulex
24	* 3333 Susan Street	39	* 3333 Susan Street
25	* Costa Mesa, CA 92626	40	* Costa Mesa, CA 92626
26	*******************************************************************/	41	*/
27		42
28	#ifndef __OCRDMA_ABI_H__	43	#ifndef __OCRDMA_ABI_H__
29	#define __OCRDMA_ABI_H__	44	#define __OCRDMA_ABI_H__

drivers/infiniband/hw/ocrdma/ocrdma_ah.c+34−19

@@ -1,21 +1,36 @@
1	/*******************************************************************	1	/* This file is part of the Emulex RoCE Device Driver for
2	* This file is part of the Emulex RoCE Device Driver for *	2	* RoCE (RDMA over Converged Ethernet) adapters.
3	* RoCE (RDMA over Converged Ethernet) adapters. *	3	* Copyright (C) 2012-2015 Emulex. All rights reserved.
4	* Copyright (C) 2008-2012 Emulex. All rights reserved. *	4	* EMULEX and SLI are trademarks of Emulex.
5	* EMULEX and SLI are trademarks of Emulex. *	5	* www.emulex.com
6	* www.emulex.com *	6	*
7	* *	7	* This software is available to you under a choice of one of two licenses.
8	* This program is free software; you can redistribute it and/or *	8	* You may choose to be licensed under the terms of the GNU General Public
9	* modify it under the terms of version 2 of the GNU General *	9	* License (GPL) Version 2, available from the file COPYING in the main
10	* Public License as published by the Free Software Foundation. *	10	* directory of this source tree, or the BSD license below:
11	* This program is distributed in the hope that it will be useful. *	11	*
12	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *	12	* Redistribution and use in source and binary forms, with or without
13	* WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *	13	* modification, are permitted provided that the following conditions
14	* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *	14	* are met:
15	* DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *	15	*
16	* TO BE LEGALLY INVALID. See the GNU General Public License for *	16	* - Redistributions of source code must retain the above copyright notice,
17	* more details, a copy of which can be found in the file COPYING *	17	* this list of conditions and the following disclaimer.
18	* included with this package. *	18	*
		19	* - Redistributions in binary form must reproduce the above copyright
		20	* notice, this list of conditions and the following disclaimer in
		21	* the documentation and/or other materials provided with the distribution.
		22	*
		23	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		24	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
		25	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
		26	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
		27	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
		28	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
		29	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
		30	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
		31	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
		32	* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
		33	* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19	*	34	*
20	* Contact Information:	35	* Contact Information:
21	* linux-drivers@emulex.com	36	* linux-drivers@emulex.com
@@ -23,7 +38,7 @@ · 1 unmodified line
23	* Emulex	38	* Emulex
24	* 3333 Susan Street	39	* 3333 Susan Street
25	* Costa Mesa, CA 92626	40	* Costa Mesa, CA 92626
26	*******************************************************************/	41	*/
27		42
28	#include <net/neighbour.h>	43	#include <net/neighbour.h>
29	#include <net/netevent.h>	44	#include <net/netevent.h>

drivers/infiniband/hw/ocrdma/ocrdma_ah.h+34−19

@@ -1,21 +1,36 @@
1	/*******************************************************************	1	/* This file is part of the Emulex RoCE Device Driver for
2	* This file is part of the Emulex RoCE Device Driver for *	2	* RoCE (RDMA over Converged Ethernet) adapters.
3	* RoCE (RDMA over Converged Ethernet) adapters. *	3	* Copyright (C) 2012-2015 Emulex. All rights reserved.
4	* Copyright (C) 2008-2012 Emulex. All rights reserved. *	4	* EMULEX and SLI are trademarks of Emulex.
5	* EMULEX and SLI are trademarks of Emulex. *	5	* www.emulex.com
6	* www.emulex.com *	6	*
7	* *	7	* This software is available to you under a choice of one of two licenses.
8	* This program is free software; you can redistribute it and/or *	8	* You may choose to be licensed under the terms of the GNU General Public
9	* modify it under the terms of version 2 of the GNU General *	9	* License (GPL) Version 2, available from the file COPYING in the main
10	* Public License as published by the Free Software Foundation. *	10	* directory of this source tree, or the BSD license below:
11	* This program is distributed in the hope that it will be useful. *	11	*
12	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *	12	* Redistribution and use in source and binary forms, with or without
13	* WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *	13	* modification, are permitted provided that the following conditions
14	* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *	14	* are met:
15	* DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *	15	*
16	* TO BE LEGALLY INVALID. See the GNU General Public License for *	16	* - Redistributions of source code must retain the above copyright notice,
17	* more details, a copy of which can be found in the file COPYING *	17	* this list of conditions and the following disclaimer.
18	* included with this package. *	18	*
		19	* - Redistributions in binary form must reproduce the above copyright
		20	* notice, this list of conditions and the following disclaimer in
		21	* the documentation and/or other materials provided with the distribution.
		22	*
		23	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		24	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
		25	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
		26	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
		27	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
		28	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
		29	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
		30	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
		31	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
		32	* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
		33	* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19	*	34	*
20	* Contact Information:	35	* Contact Information:
21	* linux-drivers@emulex.com	36	* linux-drivers@emulex.com
@@ -23,7 +38,7 @@ · 1 unmodified line
23	* Emulex	38	* Emulex
24	* 3333 Susan Street	39	* 3333 Susan Street
25	* Costa Mesa, CA 92626	40	* Costa Mesa, CA 92626
26	*******************************************************************/	41	*/
27		42
28	#ifndef __OCRDMA_AH_H__	43	#ifndef __OCRDMA_AH_H__
29	#define __OCRDMA_AH_H__	44	#define __OCRDMA_AH_H__

drivers/infiniband/hw/ocrdma/ocrdma_hw.c+34−19

@@ -1,21 +1,36 @@
1	/*******************************************************************	1	/* This file is part of the Emulex RoCE Device Driver for
2	* This file is part of the Emulex RoCE Device Driver for *	2	* RoCE (RDMA over Converged Ethernet) adapters.
3	* RoCE (RDMA over Converged Ethernet) CNA Adapters. *	3	* Copyright (C) 2012-2015 Emulex. All rights reserved.
4	* Copyright (C) 2008-2012 Emulex. All rights reserved. *	4	* EMULEX and SLI are trademarks of Emulex.
5	* EMULEX and SLI are trademarks of Emulex. *	5	* www.emulex.com
6	* www.emulex.com *	6	*
7	* *	7	* This software is available to you under a choice of one of two licenses.
8	* This program is free software; you can redistribute it and/or *	8	* You may choose to be licensed under the terms of the GNU General Public
9	* modify it under the terms of version 2 of the GNU General *	9	* License (GPL) Version 2, available from the file COPYING in the main
10	* Public License as published by the Free Software Foundation. *	10	* directory of this source tree, or the BSD license below:
11	* This program is distributed in the hope that it will be useful. *	11	*
12	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *	12	* Redistribution and use in source and binary forms, with or without
13	* WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *	13	* modification, are permitted provided that the following conditions
14	* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *	14	* are met:
15	* DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *	15	*
16	* TO BE LEGALLY INVALID. See the GNU General Public License for *	16	* - Redistributions of source code must retain the above copyright notice,
17	* more details, a copy of which can be found in the file COPYING *	17	* this list of conditions and the following disclaimer.
18	* included with this package. *	18	*
		19	* - Redistributions in binary form must reproduce the above copyright
		20	* notice, this list of conditions and the following disclaimer in
		21	* the documentation and/or other materials provided with the distribution.
		22	*
		23	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		24	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
		25	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
		26	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
		27	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
		28	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
		29	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
		30	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
		31	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
		32	* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
		33	* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19	*	34	*
20	* Contact Information:	35	* Contact Information:
21	* linux-drivers@emulex.com	36	* linux-drivers@emulex.com
@@ -23,7 +38,7 @@ · 1 unmodified line
23	* Emulex	38	* Emulex
24	* 3333 Susan Street	39	* 3333 Susan Street
25	* Costa Mesa, CA 92626	40	* Costa Mesa, CA 92626
26	*******************************************************************/	41	*/
27		42
28	#include <linux/sched.h>	43	#include <linux/sched.h>
29	#include <linux/interrupt.h>	44	#include <linux/interrupt.h>

drivers/infiniband/hw/ocrdma/ocrdma_hw.h+34−19

@@ -1,21 +1,36 @@
1	/*******************************************************************	1	/* This file is part of the Emulex RoCE Device Driver for
2	* This file is part of the Emulex RoCE Device Driver for *	2	* RoCE (RDMA over Converged Ethernet) adapters.
3	* RoCE (RDMA over Converged Ethernet) CNA Adapters. *	3	* Copyright (C) 2012-2015 Emulex. All rights reserved.
4	* Copyright (C) 2008-2012 Emulex. All rights reserved. *	4	* EMULEX and SLI are trademarks of Emulex.
5	* EMULEX and SLI are trademarks of Emulex. *	5	* www.emulex.com
6	* www.emulex.com *	6	*
7	* *	7	* This software is available to you under a choice of one of two licenses.
8	* This program is free software; you can redistribute it and/or *	8	* You may choose to be licensed under the terms of the GNU General Public
9	* modify it under the terms of version 2 of the GNU General *	9	* License (GPL) Version 2, available from the file COPYING in the main
10	* Public License as published by the Free Software Foundation. *	10	* directory of this source tree, or the BSD license below:
11	* This program is distributed in the hope that it will be useful. *	11	*
12	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *	12	* Redistribution and use in source and binary forms, with or without
13	* WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *	13	* modification, are permitted provided that the following conditions
14	* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *	14	* are met:
15	* DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *	15	*
16	* TO BE LEGALLY INVALID. See the GNU General Public License for *	16	* - Redistributions of source code must retain the above copyright notice,
17	* more details, a copy of which can be found in the file COPYING *	17	* this list of conditions and the following disclaimer.
18	* included with this package. *	18	*
		19	* - Redistributions in binary form must reproduce the above copyright
		20	* notice, this list of conditions and the following disclaimer in
		21	* the documentation and/or other materials provided with the distribution.
		22	*
		23	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		24	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
		25	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
		26	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
		27	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
		28	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
		29	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
		30	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
		31	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
		32	* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
		33	* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19	*	34	*
20	* Contact Information:	35	* Contact Information:
21	* linux-drivers@emulex.com	36	* linux-drivers@emulex.com
@@ -23,7 +38,7 @@ · 1 unmodified line
23	* Emulex	38	* Emulex
24	* 3333 Susan Street	39	* 3333 Susan Street
25	* Costa Mesa, CA 92626	40	* Costa Mesa, CA 92626
26	*******************************************************************/	41	*/
27		42
28	#ifndef __OCRDMA_HW_H__	43	#ifndef __OCRDMA_HW_H__
29	#define __OCRDMA_HW_H__	44	#define __OCRDMA_HW_H__

drivers/infiniband/hw/ocrdma/ocrdma_main.c+35−20

@@ -1,21 +1,36 @@
1	/*******************************************************************	1	/* This file is part of the Emulex RoCE Device Driver for
2	* This file is part of the Emulex RoCE Device Driver for *	2	* RoCE (RDMA over Converged Ethernet) adapters.
3	* RoCE (RDMA over Converged Ethernet) adapters. *	3	* Copyright (C) 2012-2015 Emulex. All rights reserved.
4	* Copyright (C) 2008-2012 Emulex. All rights reserved. *	4	* EMULEX and SLI are trademarks of Emulex.
5	* EMULEX and SLI are trademarks of Emulex. *	5	* www.emulex.com
6	* www.emulex.com *	6	*
7	* *	7	* This software is available to you under a choice of one of two licenses.
8	* This program is free software; you can redistribute it and/or *	8	* You may choose to be licensed under the terms of the GNU General Public
9	* modify it under the terms of version 2 of the GNU General *	9	* License (GPL) Version 2, available from the file COPYING in the main
10	* Public License as published by the Free Software Foundation. *	10	* directory of this source tree, or the BSD license below:
11	* This program is distributed in the hope that it will be useful. *	11	*
12	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *	12	* Redistribution and use in source and binary forms, with or without
13	* WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *	13	* modification, are permitted provided that the following conditions
14	* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *	14	* are met:
15	* DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *	15	*
16	* TO BE LEGALLY INVALID. See the GNU General Public License for *	16	* - Redistributions of source code must retain the above copyright notice,
17	* more details, a copy of which can be found in the file COPYING *	17	* this list of conditions and the following disclaimer.
18	* included with this package. *	18	*
		19	* - Redistributions in binary form must reproduce the above copyright
		20	* notice, this list of conditions and the following disclaimer in
		21	* the documentation and/or other materials provided with the distribution.
		22	*
		23	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		24	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
		25	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
		26	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
		27	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
		28	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
		29	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
		30	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
		31	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
		32	* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
		33	* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19	*	34	*
20	* Contact Information:	35	* Contact Information:
21	* linux-drivers@emulex.com	36	* linux-drivers@emulex.com
@@ -23,7 +38,7 @@ · 1 unmodified line
23	* Emulex	38	* Emulex
24	* 3333 Susan Street	39	* 3333 Susan Street
25	* Costa Mesa, CA 92626	40	* Costa Mesa, CA 92626
26	*******************************************************************/	41	*/
27		42
28	#include <linux/module.h>	43	#include <linux/module.h>
29	#include <linux/idr.h>	44	#include <linux/idr.h>
@@ -46,7 +61,7 @@ · 16 unmodified lines
46	MODULE_VERSION(OCRDMA_ROCE_DRV_VERSION);	61	MODULE_VERSION(OCRDMA_ROCE_DRV_VERSION);
47	MODULE_DESCRIPTION(OCRDMA_ROCE_DRV_DESC " " OCRDMA_ROCE_DRV_VERSION);	62	MODULE_DESCRIPTION(OCRDMA_ROCE_DRV_DESC " " OCRDMA_ROCE_DRV_VERSION);
48	MODULE_AUTHOR("Emulex Corporation");	63	MODULE_AUTHOR("Emulex Corporation");
49	MODULE_LICENSE("GPL");	64	MODULE_LICENSE("Dual BSD/GPL");
50		65
51	static LIST_HEAD(ocrdma_dev_list);	66	static LIST_HEAD(ocrdma_dev_list);
52	static DEFINE_SPINLOCK(ocrdma_devlist_lock);	67	static DEFINE_SPINLOCK(ocrdma_devlist_lock);

drivers/infiniband/hw/ocrdma/ocrdma_sli.h+34−19

@@ -1,21 +1,36 @@
1	/*******************************************************************	1	/* This file is part of the Emulex RoCE Device Driver for
2	* This file is part of the Emulex RoCE Device Driver for *	2	* RoCE (RDMA over Converged Ethernet) adapters.
3	* RoCE (RDMA over Converged Ethernet) adapters. *	3	* Copyright (C) 2012-2015 Emulex. All rights reserved.
4	* Copyright (C) 2008-2012 Emulex. All rights reserved. *	4	* EMULEX and SLI are trademarks of Emulex.
5	* EMULEX and SLI are trademarks of Emulex. *	5	* www.emulex.com
6	* www.emulex.com *	6	*
7	* *	7	* This software is available to you under a choice of one of two licenses.
8	* This program is free software; you can redistribute it and/or *	8	* You may choose to be licensed under the terms of the GNU General Public
9	* modify it under the terms of version 2 of the GNU General *	9	* License (GPL) Version 2, available from the file COPYING in the main
10	* Public License as published by the Free Software Foundation. *	10	* directory of this source tree, or the BSD license below:
11	* This program is distributed in the hope that it will be useful. *	11	*
12	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *	12	* Redistribution and use in source and binary forms, with or without
13	* WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *	13	* modification, are permitted provided that the following conditions
14	* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *	14	* are met:
15	* DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *	15	*
16	* TO BE LEGALLY INVALID. See the GNU General Public License for *	16	* - Redistributions of source code must retain the above copyright notice,
17	* more details, a copy of which can be found in the file COPYING *	17	* this list of conditions and the following disclaimer.
18	* included with this package. *	18	*
		19	* - Redistributions in binary form must reproduce the above copyright
		20	* notice, this list of conditions and the following disclaimer in
		21	* the documentation and/or other materials provided with the distribution.
		22	*
		23	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		24	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
		25	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
		26	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
		27	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
		28	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
		29	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
		30	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
		31	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
		32	* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
		33	* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19	*	34	*
20	* Contact Information:	35	* Contact Information:
21	* linux-drivers@emulex.com	36	* linux-drivers@emulex.com
@@ -23,7 +38,7 @@ · 1 unmodified line
23	* Emulex	38	* Emulex
24	* 3333 Susan Street	39	* 3333 Susan Street
25	* Costa Mesa, CA 92626	40	* Costa Mesa, CA 92626
26	*******************************************************************/	41	*/
27		42
28	#ifndef __OCRDMA_SLI_H__	43	#ifndef __OCRDMA_SLI_H__
29	#define __OCRDMA_SLI_H__	44	#define __OCRDMA_SLI_H__

drivers/infiniband/hw/ocrdma/ocrdma_stats.c+34−19

@@ -1,21 +1,36 @@
1	/*******************************************************************	1	/* This file is part of the Emulex RoCE Device Driver for
2	* This file is part of the Emulex RoCE Device Driver for *	2	* RoCE (RDMA over Converged Ethernet) adapters.
3	* RoCE (RDMA over Converged Ethernet) adapters. *	3	* Copyright (C) 2012-2015 Emulex. All rights reserved.
4	* Copyright (C) 2008-2014 Emulex. All rights reserved. *	4	* EMULEX and SLI are trademarks of Emulex.
5	* EMULEX and SLI are trademarks of Emulex. *	5	* www.emulex.com
6	* www.emulex.com *	6	*
7	* *	7	* This software is available to you under a choice of one of two licenses.
8	* This program is free software; you can redistribute it and/or *	8	* You may choose to be licensed under the terms of the GNU General Public
9	* modify it under the terms of version 2 of the GNU General *	9	* License (GPL) Version 2, available from the file COPYING in the main
10	* Public License as published by the Free Software Foundation. *	10	* directory of this source tree, or the BSD license below:
11	* This program is distributed in the hope that it will be useful. *	11	*
12	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *	12	* Redistribution and use in source and binary forms, with or without
13	* WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *	13	* modification, are permitted provided that the following conditions
14	* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *	14	* are met:
15	* DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *	15	*
16	* TO BE LEGALLY INVALID. See the GNU General Public License for *	16	* - Redistributions of source code must retain the above copyright notice,
17	* more details, a copy of which can be found in the file COPYING *	17	* this list of conditions and the following disclaimer.
18	* included with this package. *	18	*
		19	* - Redistributions in binary form must reproduce the above copyright
		20	* notice, this list of conditions and the following disclaimer in
		21	* the documentation and/or other materials provided with the distribution.
		22	*
		23	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		24	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
		25	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
		26	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
		27	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
		28	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
		29	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
		30	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
		31	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
		32	* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
		33	* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19	*	34	*
20	* Contact Information:	35	* Contact Information:
21	* linux-drivers@emulex.com	36	* linux-drivers@emulex.com
@@ -23,7 +38,7 @@ · 1 unmodified line
23	* Emulex	38	* Emulex
24	* 3333 Susan Street	39	* 3333 Susan Street
25	* Costa Mesa, CA 92626	40	* Costa Mesa, CA 92626
26	*******************************************************************/	41	*/
27		42
28	#include <rdma/ib_addr.h>	43	#include <rdma/ib_addr.h>
29	#include <rdma/ib_pma.h>	44	#include <rdma/ib_pma.h>

drivers/infiniband/hw/ocrdma/ocrdma_stats.h+34−19

@@ -1,21 +1,36 @@
1	/*******************************************************************	1	/* This file is part of the Emulex RoCE Device Driver for
2	* This file is part of the Emulex RoCE Device Driver for *	2	* RoCE (RDMA over Converged Ethernet) adapters.
3	* RoCE (RDMA over Converged Ethernet) adapters. *	3	* Copyright (C) 2012-2015 Emulex. All rights reserved.
4	* Copyright (C) 2008-2014 Emulex. All rights reserved. *	4	* EMULEX and SLI are trademarks of Emulex.
5	* EMULEX and SLI are trademarks of Emulex. *	5	* www.emulex.com
6	* www.emulex.com *	6	*
7	* *	7	* This software is available to you under a choice of one of two licenses.
8	* This program is free software; you can redistribute it and/or *	8	* You may choose to be licensed under the terms of the GNU General Public
9	* modify it under the terms of version 2 of the GNU General *	9	* License (GPL) Version 2, available from the file COPYING in the main
10	* Public License as published by the Free Software Foundation. *	10	* directory of this source tree, or the BSD license below:
11	* This program is distributed in the hope that it will be useful. *	11	*
12	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *	12	* Redistribution and use in source and binary forms, with or without
13	* WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *	13	* modification, are permitted provided that the following conditions
14	* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *	14	* are met:
15	* DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *	15	*
16	* TO BE LEGALLY INVALID. See the GNU General Public License for *	16	* - Redistributions of source code must retain the above copyright notice,
17	* more details, a copy of which can be found in the file COPYING *	17	* this list of conditions and the following disclaimer.
18	* included with this package. *	18	*
		19	* - Redistributions in binary form must reproduce the above copyright
		20	* notice, this list of conditions and the following disclaimer in
		21	* the documentation and/or other materials provided with the distribution.
		22	*
		23	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		24	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
		25	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
		26	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
		27	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
		28	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
		29	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
		30	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
		31	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
		32	* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
		33	* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19	*	34	*
20	* Contact Information:	35	* Contact Information:
21	* linux-drivers@emulex.com	36	* linux-drivers@emulex.com
@@ -23,7 +38,7 @@ · 1 unmodified line
23	* Emulex	38	* Emulex
24	* 3333 Susan Street	39	* 3333 Susan Street
25	* Costa Mesa, CA 92626	40	* Costa Mesa, CA 92626
26	*******************************************************************/	41	*/
27		42
28	#ifndef __OCRDMA_STATS_H__	43	#ifndef __OCRDMA_STATS_H__
29	#define __OCRDMA_STATS_H__	44	#define __OCRDMA_STATS_H__

drivers/infiniband/hw/ocrdma/ocrdma_verbs.c+34−19

@@ -1,21 +1,36 @@
1	/*******************************************************************	1	/* This file is part of the Emulex RoCE Device Driver for
2	* This file is part of the Emulex RoCE Device Driver for *	2	* RoCE (RDMA over Converged Ethernet) adapters.
3	* RoCE (RDMA over Converged Ethernet) adapters. *	3	* Copyright (C) 2012-2015 Emulex. All rights reserved.
4	* Copyright (C) 2008-2012 Emulex. All rights reserved. *	4	* EMULEX and SLI are trademarks of Emulex.
5	* EMULEX and SLI are trademarks of Emulex. *	5	* www.emulex.com
6	* www.emulex.com *	6	*
7	* *	7	* This software is available to you under a choice of one of two licenses.
8	* This program is free software; you can redistribute it and/or *	8	* You may choose to be licensed under the terms of the GNU General Public
9	* modify it under the terms of version 2 of the GNU General *	9	* License (GPL) Version 2, available from the file COPYING in the main
10	* Public License as published by the Free Software Foundation. *	10	* directory of this source tree, or the BSD license below:
11	* This program is distributed in the hope that it will be useful. *	11	*
12	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *	12	* Redistribution and use in source and binary forms, with or without
13	* WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *	13	* modification, are permitted provided that the following conditions
14	* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *	14	* are met:
15	* DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *	15	*
16	* TO BE LEGALLY INVALID. See the GNU General Public License for *	16	* - Redistributions of source code must retain the above copyright notice,
17	* more details, a copy of which can be found in the file COPYING *	17	* this list of conditions and the following disclaimer.
18	* included with this package. *	18	*
		19	* - Redistributions in binary form must reproduce the above copyright
		20	* notice, this list of conditions and the following disclaimer in
		21	* the documentation and/or other materials provided with the distribution.
		22	*
		23	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		24	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
		25	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
		26	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
		27	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
		28	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
		29	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
		30	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
		31	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
		32	* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
		33	* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19	*	34	*
20	* Contact Information:	35	* Contact Information:
21	* linux-drivers@emulex.com	36	* linux-drivers@emulex.com
@@ -23,7 +38,7 @@ · 1 unmodified line
23	* Emulex	38	* Emulex
24	* 3333 Susan Street	39	* 3333 Susan Street
25	* Costa Mesa, CA 92626	40	* Costa Mesa, CA 92626
26	*******************************************************************/	41	*/
27		42
28	#include <linux/dma-mapping.h>	43	#include <linux/dma-mapping.h>
29	#include <rdma/ib_verbs.h>	44	#include <rdma/ib_verbs.h>

drivers/infiniband/hw/ocrdma/ocrdma_verbs.h+34−19

@@ -1,21 +1,36 @@
1	/*******************************************************************	1	/* This file is part of the Emulex RoCE Device Driver for
2	* This file is part of the Emulex RoCE Device Driver for *	2	* RoCE (RDMA over Converged Ethernet) adapters.
3	* RoCE (RDMA over Converged Ethernet) adapters. *	3	* Copyright (C) 2012-2015 Emulex. All rights reserved.
4	* Copyright (C) 2008-2012 Emulex. All rights reserved. *	4	* EMULEX and SLI are trademarks of Emulex.
5	* EMULEX and SLI are trademarks of Emulex. *	5	* www.emulex.com
6	* www.emulex.com *	6	*
7	* *	7	* This software is available to you under a choice of one of two licenses.
8	* This program is free software; you can redistribute it and/or *	8	* You may choose to be licensed under the terms of the GNU General Public
9	* modify it under the terms of version 2 of the GNU General *	9	* License (GPL) Version 2, available from the file COPYING in the main
10	* Public License as published by the Free Software Foundation. *	10	* directory of this source tree, or the BSD license below:
11	* This program is distributed in the hope that it will be useful. *	11	*
12	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *	12	* Redistribution and use in source and binary forms, with or without
13	* WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *	13	* modification, are permitted provided that the following conditions
14	* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *	14	* are met:
15	* DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *	15	*
16	* TO BE LEGALLY INVALID. See the GNU General Public License for *	16	* - Redistributions of source code must retain the above copyright notice,
17	* more details, a copy of which can be found in the file COPYING *	17	* this list of conditions and the following disclaimer.
18	* included with this package. *	18	*
		19	* - Redistributions in binary form must reproduce the above copyright
		20	* notice, this list of conditions and the following disclaimer in
		21	* the documentation and/or other materials provided with the distribution.
		22	*
		23	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		24	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
		25	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
		26	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
		27	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
		28	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
		29	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
		30	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
		31	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
		32	* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
		33	* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19	*	34	*
20	* Contact Information:	35	* Contact Information:
21	* linux-drivers@emulex.com	36	* linux-drivers@emulex.com
@@ -23,7 +38,7 @@ · 1 unmodified line
23	* Emulex	38	* Emulex
24	* 3333 Susan Street	39	* 3333 Susan Street
25	* Costa Mesa, CA 92626	40	* Costa Mesa, CA 92626
26	*******************************************************************/	41	*/
27		42
28	#ifndef __OCRDMA_VERBS_H__	43	#ifndef __OCRDMA_VERBS_H__
29	#define __OCRDMA_VERBS_H__	44	#define __OCRDMA_VERBS_H__

drivers/infiniband/ulp/ipoib/ipoib_verbs.c+2−1

@@ -177,7 +177,8 @@ int ipoib_transport_dev_init(struct net_device dev, struct ib_device ca) · 176 unmodified lines
177	else	177	else
178	size += ipoib_recvq_size * ipoib_max_conn_qp;	178	size += ipoib_recvq_size * ipoib_max_conn_qp;
179	} else	179	} else
180	goto out_free_wq;	180	if (ret != -ENOSYS)
		181	goto out_free_wq;
181		182
182	cq_attr.cqe = size;	183	cq_attr.cqe = size;
183	priv->recv_cq = ib_create_cq(priv->ca, ipoib_ib_completion, NULL,	184	priv->recv_cq = ib_create_cq(priv->ca, ipoib_ib_completion, NULL,

drivers/infiniband/ulp/isert/ib_isert.c+11−5

 	ret = isert_rdma_post_recvl(isert_conn);
 	if (ret)
 		goto out_conn_dev;
+	/*
+	 * Obtain the second reference now before isert_rdma_accept() to
+	 * ensure that any initiator generated REJECT CM event that occurs
+	 * asynchronously won't drop the last reference until the error path
+	 * in iscsi_target_login_sess_out() does it's ->iscsit_free_conn() ->
+	 * isert_free_conn() -> isert_put_conn() -> kref_put().
+	 */
+	if (!kref_get_unless_zero(&isert_conn->kref)) {
+		isert_warn("conn %p connect_release is running\n", isert_conn);
+		goto out_conn_dev;
+	}
 	ret = isert_rdma_accept(isert_conn);
 	if (ret)
 	isert_info("conn %p\n", isert_conn);
-	if (!kref_get_unless_zero(&isert_conn->kref)) {
-		isert_warn("conn %p connect_release is running\n", isert_conn);
-		return;
-	}
 	mutex_lock(&isert_conn->mutex);
 	if (isert_conn->state != ISER_CONN_FULL_FEATURE)
 		isert_conn->state = ISER_CONN_UP;

drivers/input/input-leds.c+14−2

 {
 }
+static int input_leds_get_count(struct input_dev *dev)
+{
+	unsigned int led_code;
+	int count = 0;
+	for_each_set_bit(led_code, dev->ledbit, LED_CNT)
+		if (input_led_info[led_code].name)
+			count++;
+	return count;
+}
 static int input_leds_connect(struct input_handler *handler,
 			      struct input_dev *dev,
 			      const struct input_device_id *id)
 	int led_no;
 	int error;
-	num_leds = bitmap_weight(dev->ledbit, LED_CNT);
+	num_leds = input_leds_get_count(dev);
 	if (!num_leds)
 		return -ENXIO;
 		led->handle = &leds->handle;
 		led->code = led_code;
-		if (WARN_ON(!input_led_info[led_code].name))
+		if (!input_led_info[led_code].name)
 			continue;
 		led->cdev.name = kasprintf(GFP_KERNEL, "%s::%s",

drivers/input/joystick/turbografx.c+1−1

@@ -196,7 +196,7 @@ static struct tgfx __init tgfx_probe(int parport, int n_buttons, int n_devs) · 195 unmodified lines
196	if (n_buttons[i] < 1)	196	if (n_buttons[i] < 1)
197	continue;	197	continue;
198		198
199	if (n_buttons[i] > 6) {	199	if (n_buttons[i] > ARRAY_SIZE(tgfx_buttons)) {
200	printk(KERN_ERR "turbografx.c: Invalid number of buttons %d\n", n_buttons[i]);	200	printk(KERN_ERR "turbografx.c: Invalid number of buttons %d\n", n_buttons[i]);
201	err = -EINVAL;	201	err = -EINVAL;
202	goto err_unreg_devs;	202	goto err_unreg_devs;

drivers/input/misc/axp20x-pek.c+1−0

@@ -292,3 +292,4 @@ module_platform_driver(axp20x_pek_driver); · 291 unmodified lines
292	MODULE_DESCRIPTION("axp20x Power Button");	292	MODULE_DESCRIPTION("axp20x Power Button");
293	MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");	293	MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
294	MODULE_LICENSE("GPL");	294	MODULE_LICENSE("GPL");
		295	MODULE_ALIAS("platform:axp20x-pek");

drivers/input/misc/twl4030-vibra.c+2−1

@@ -183,7 +183,8 @@ static bool twl4030_vibra_check_coexist(struct twl4030_vibra_data *pdata, · 182 unmodified lines
183	if (pdata && pdata->coexist)	183	if (pdata && pdata->coexist)
184	return true;	184	return true;
185		185
186	if (of_find_node_by_name(node, "codec")) {	186	node = of_find_node_by_name(node, "codec");
		187	if (node) {
187	of_node_put(node);	188	of_node_put(node);
188	return true;	189	return true;
189	}	190	}

drivers/input/mouse/alps.c+6−2

 #include <linux/input/mt.h>
 #include <linux/serio.h>
 #include <linux/libps2.h>
+#include <linux/dmi.h>
 #include "psmouse.h"
 #include "alps.h"
 #define ALPS_FOUR_BUTTONS	0x40	/* 4 direction button present */
 #define ALPS_PS2_INTERLEAVED	0x80	/* 3-byte PS/2 packet interleaved with
 					   6-byte ALPS packet */
+#define ALPS_DELL		0x100	/* device is a Dell laptop */
 #define ALPS_BUTTONPAD		0x200	/* device is a clickpad */
 static const struct alps_model_info alps_model_data[] = {
 		return;
 	}
-	/* Non interleaved V2 dualpoint has separate stick button bits */
+	/* Dell non interleaved V2 dualpoint has separate stick button bits */
 	if (priv->proto_version == ALPS_PROTO_V2 &&
-	    priv->flags == (ALPS_PASS | ALPS_DUALPOINT)) {
+	    priv->flags == (ALPS_DELL | ALPS_PASS | ALPS_DUALPOINT)) {
 		left |= packet[0] & 1;
 		right |= packet[0] & 2;
 		middle |= packet[0] & 4;
 	priv->byte0 = protocol->byte0;
 	priv->mask0 = protocol->mask0;
 	priv->flags = protocol->flags;
+	if (dmi_name_in_vendors("Dell"))
+		priv->flags |= ALPS_DELL;
 	priv->x_max = 2000;
 	priv->y_max = 1400;

drivers/input/mouse/bcm5974.c+112−53

  * Apple USB BCM5974 (Macbook Air and Penryn Macbook Pro) multitouch driver
  *
  * Copyright (C) 2008	   Henrik Rydberg (rydberg@euromail.se)
+ * Copyright (C) 2015      John Horan (knasher@gmail.com)
  *
  * The USB initialization and package decoding was made by
  * Scott Shawcroft as part of the touchd user-space driver project:
 #define USB_DEVICE_ID_APPLE_WELLSPRING8_ANSI	0x0290
 #define USB_DEVICE_ID_APPLE_WELLSPRING8_ISO	0x0291
 #define USB_DEVICE_ID_APPLE_WELLSPRING8_JIS	0x0292
+/* MacbookPro12,1 (2015) */
+#define USB_DEVICE_ID_APPLE_WELLSPRING9_ANSI	0x0272
+#define USB_DEVICE_ID_APPLE_WELLSPRING9_ISO	0x0273
+#define USB_DEVICE_ID_APPLE_WELLSPRING9_JIS	0x0274
 #define BCM5974_DEVICE(prod) {					\
 	.match_flags = (USB_DEVICE_ID_MATCH_DEVICE |		\
 	BCM5974_DEVICE(USB_DEVICE_ID_APPLE_WELLSPRING8_ANSI),
 	BCM5974_DEVICE(USB_DEVICE_ID_APPLE_WELLSPRING8_ISO),
 	BCM5974_DEVICE(USB_DEVICE_ID_APPLE_WELLSPRING8_JIS),
+	/* MacbookPro12,1 */
+	BCM5974_DEVICE(USB_DEVICE_ID_APPLE_WELLSPRING9_ANSI),
+	BCM5974_DEVICE(USB_DEVICE_ID_APPLE_WELLSPRING9_ISO),
+	BCM5974_DEVICE(USB_DEVICE_ID_APPLE_WELLSPRING9_JIS),
 	/* Terminating entry */
 	{}
 };
 enum tp_type {
 	TYPE1,			/* plain trackpad */
 	TYPE2,			/* button integrated in trackpad */
-	TYPE3			/* additional header fields since June 2013 */
+	TYPE3,			/* additional header fields since June 2013 */
+	TYPE4			/* additional header field for pressure data */
 };
 /* trackpad finger data offsets, le16-aligned */
-#define FINGER_TYPE1		(13 * sizeof(__le16))
+#define HEADER_TYPE1		(13 * sizeof(__le16))
-#define FINGER_TYPE2		(15 * sizeof(__le16))
+#define HEADER_TYPE2		(15 * sizeof(__le16))
-#define FINGER_TYPE3		(19 * sizeof(__le16))
+#define HEADER_TYPE3		(19 * sizeof(__le16))
+#define HEADER_TYPE4		(23 * sizeof(__le16))
 /* trackpad button data offsets */
+#define BUTTON_TYPE1		0
 #define BUTTON_TYPE2		15
 #define BUTTON_TYPE3		23
+#define BUTTON_TYPE4		31
 /* list of device capability bits */
 #define HAS_INTEGRATED_BUTTON	1
+/* trackpad finger data block size */
+#define FSIZE_TYPE1		(14 * sizeof(__le16))
+#define FSIZE_TYPE2		(14 * sizeof(__le16))
+#define FSIZE_TYPE3		(14 * sizeof(__le16))
+#define FSIZE_TYPE4		(15 * sizeof(__le16))
+/* offset from header to finger struct */
+#define DELTA_TYPE1		(0 * sizeof(__le16))
+#define DELTA_TYPE2		(0 * sizeof(__le16))
+#define DELTA_TYPE3		(0 * sizeof(__le16))
+#define DELTA_TYPE4		(1 * sizeof(__le16))
+/* usb control message mode switch data */
+#define USBMSG_TYPE1		8, 0x300, 0, 0, 0x1, 0x8
+#define USBMSG_TYPE2		8, 0x300, 0, 0, 0x1, 0x8
+#define USBMSG_TYPE3		8, 0x300, 0, 0, 0x1, 0x8
+#define USBMSG_TYPE4		2, 0x302, 2, 1, 0x1, 0x0
+/* Wellspring initialization constants */
+#define BCM5974_WELLSPRING_MODE_READ_REQUEST_ID		1
+#define BCM5974_WELLSPRING_MODE_WRITE_REQUEST_ID	9
 /* trackpad finger structure, le16-aligned */
 struct tp_finger {
 	__le16 origin;		/* zero when switching track finger */
 	__le16 orientation;	/* 16384 when point, else 15 bit angle */
 	__le16 touch_major;	/* touch area, major axis */
 	__le16 touch_minor;	/* touch area, minor axis */
-	__le16 unused[3];	/* zeros */
+	__le16 unused[2];	/* zeros */
+	__le16 pressure;	/* pressure on forcetouch touchpad */
 	__le16 multi;		/* one finger: varies, more fingers: constant */
 } __attribute__((packed,aligned(2)));
 /* trackpad finger data size, empirically at least ten fingers */
 #define MAX_FINGERS		16
-#define SIZEOF_FINGER		sizeof(struct tp_finger)
-#define SIZEOF_ALL_FINGERS	(MAX_FINGERS * SIZEOF_FINGER)
 #define MAX_FINGER_ORIENTATION	16384
 /* device-specific parameters */
 	int bt_datalen;		/* data length of the button interface */
 	int tp_ep;		/* the endpoint of the trackpad interface */
 	enum tp_type tp_type;	/* type of trackpad interface */
-	int tp_offset;		/* offset to trackpad finger data */
+	int tp_header;		/* bytes in header block */
 	int tp_datalen;		/* data length of the trackpad interface */
+	int tp_button;		/* offset to button data */
+	int tp_fsize;		/* bytes in single finger block */
+	int tp_delta;		/* offset from header to finger struct */
+	int um_size;		/* usb control message length */
+	int um_req_val;		/* usb control message value */
+	int um_req_idx;		/* usb control message index */
+	int um_switch_idx;	/* usb control message mode switch index */
+	int um_switch_on;	/* usb control message mode switch on */
+	int um_switch_off;	/* usb control message mode switch off */
 	struct bcm5974_param p;	/* finger pressure limits */
 	struct bcm5974_param w;	/* finger width limits */
 	struct bcm5974_param x;	/* horizontal limits */
 	int slots[MAX_FINGERS];				/* slot assignments */
 };
+/* trackpad finger block data, le16-aligned */
+static const struct tp_finger *get_tp_finger(const struct bcm5974 *dev, int i)
+{
+	const struct bcm5974_config *c = &dev->cfg;
+	u8 *f_base = dev->tp_data + c->tp_header + c->tp_delta;
+	return (const struct tp_finger *)(f_base + i * c->tp_fsize);
+}
+#define DATAFORMAT(type)				\
+	type,						\
+	HEADER_##type,					\
+	HEADER_##type + (MAX_FINGERS) * (FSIZE_##type),	\
+	BUTTON_##type,					\
+	FSIZE_##type,					\
+	DELTA_##type,					\
+	USBMSG_##type
 /* logical signal quality */
 #define SN_PRESSURE	45		/* pressure signal-to-noise ratio */
 #define SN_WIDTH	25		/* width signal-to-noise ratio */
 		USB_DEVICE_ID_APPLE_WELLSPRING_JIS,
 		0,
 		0x84, sizeof(struct bt_data),
-		0x81, TYPE1, FINGER_TYPE1, FINGER_TYPE1 + SIZEOF_ALL_FINGERS,
+		0x81, DATAFORMAT(TYPE1),
 		{ SN_PRESSURE, 0, 256 },
 		{ SN_WIDTH, 0, 2048 },
 		{ SN_COORD, -4824, 5342 },
 		USB_DEVICE_ID_APPLE_WELLSPRING2_JIS,
 		0,
 		0x84, sizeof(struct bt_data),
-		0x81, TYPE1, FINGER_TYPE1, FINGER_TYPE1 + SIZEOF_ALL_FINGERS,
+		0x81, DATAFORMAT(TYPE1),
 		{ SN_PRESSURE, 0, 256 },
 		{ SN_WIDTH, 0, 2048 },
 		{ SN_COORD, -4824, 4824 },
 		USB_DEVICE_ID_APPLE_WELLSPRING3_JIS,
 		HAS_INTEGRATED_BUTTON,
 		0x84, sizeof(struct bt_data),
-		0x81, TYPE2, FINGER_TYPE2, FINGER_TYPE2 + SIZEOF_ALL_FINGERS,
+		0x81, DATAFORMAT(TYPE2),
 		{ SN_PRESSURE, 0, 300 },
 		{ SN_WIDTH, 0, 2048 },
 		{ SN_COORD, -4460, 5166 },
 		USB_DEVICE_ID_APPLE_WELLSPRING4_JIS,
 		HAS_INTEGRATED_BUTTON,
 		0x84, sizeof(struct bt_data),
-		0x81, TYPE2, FINGER_TYPE2, FINGER_TYPE2 + SIZEOF_ALL_FINGERS,
+		0x81, DATAFORMAT(TYPE2),
 		{ SN_PRESSURE, 0, 300 },
 		{ SN_WIDTH, 0, 2048 },
 		{ SN_COORD, -4620, 5140 },
 		USB_DEVICE_ID_APPLE_WELLSPRING4A_JIS,
 		HAS_INTEGRATED_BUTTON,
 		0x84, sizeof(struct bt_data),
-		0x81, TYPE2, FINGER_TYPE2, FINGER_TYPE2 + SIZEOF_ALL_FINGERS,
+		0x81, DATAFORMAT(TYPE2),
 		{ SN_PRESSURE, 0, 300 },
 		{ SN_WIDTH, 0, 2048 },
 		{ SN_COORD, -4616, 5112 },
 		USB_DEVICE_ID_APPLE_WELLSPRING5_JIS,
 		HAS_INTEGRATED_BUTTON,
 		0x84, sizeof(struct bt_data),
-		0x81, TYPE2, FINGER_TYPE2, FINGER_TYPE2 + SIZEOF_ALL_FINGERS,
+		0x81, DATAFORMAT(TYPE2),
 		{ SN_PRESSURE, 0, 300 },
 		{ SN_WIDTH, 0, 2048 },
 		{ SN_COORD, -4415, 5050 },
 		USB_DEVICE_ID_APPLE_WELLSPRING6_JIS,
 		HAS_INTEGRATED_BUTTON,
 		0x84, sizeof(struct bt_data),
-		0x81, TYPE2, FINGER_TYPE2, FINGER_TYPE2 + SIZEOF_ALL_FINGERS,
+		0x81, DATAFORMAT(TYPE2),
 		{ SN_PRESSURE, 0, 300 },
 		{ SN_WIDTH, 0, 2048 },
 		{ SN_COORD, -4620, 5140 },
 		USB_DEVICE_ID_APPLE_WELLSPRING5A_JIS,
 		HAS_INTEGRATED_BUTTON,
 		0x84, sizeof(struct bt_data),
-		0x81, TYPE2, FINGER_TYPE2, FINGER_TYPE2 + SIZEOF_ALL_FINGERS,
+		0x81, DATAFORMAT(TYPE2),
 		{ SN_PRESSURE, 0, 300 },
 		{ SN_WIDTH, 0, 2048 },
 		{ SN_COORD, -4750, 5280 },
 		USB_DEVICE_ID_APPLE_WELLSPRING6A_JIS,
 		HAS_INTEGRATED_BUTTON,
 		0x84, sizeof(struct bt_data),
-		0x81, TYPE2, FINGER_TYPE2, FINGER_TYPE2 + SIZEOF_ALL_FINGERS,
+		0x81, DATAFORMAT(TYPE2),
 		{ SN_PRESSURE, 0, 300 },
 		{ SN_WIDTH, 0, 2048 },
 		{ SN_COORD, -4620, 5140 },
 		USB_DEVICE_ID_APPLE_WELLSPRING7_JIS,
 		HAS_INTEGRATED_BUTTON,
 		0x84, sizeof(struct bt_data),
-		0x81, TYPE2, FINGER_TYPE2, FINGER_TYPE2 + SIZEOF_ALL_FINGERS,
+		0x81, DATAFORMAT(TYPE2),
 		{ SN_PRESSURE, 0, 300 },
 		{ SN_WIDTH, 0, 2048 },
 		{ SN_COORD, -4750, 5280 },
 		USB_DEVICE_ID_APPLE_WELLSPRING7A_JIS,
 		HAS_INTEGRATED_BUTTON,
 		0x84, sizeof(struct bt_data),
-		0x81, TYPE2, FINGER_TYPE2, FINGER_TYPE2 + SIZEOF_ALL_FINGERS,
+		0x81, DATAFORMAT(TYPE2),
 		{ SN_PRESSURE, 0, 300 },
 		{ SN_WIDTH, 0, 2048 },
 		{ SN_COORD, -4750, 5280 },
 		USB_DEVICE_ID_APPLE_WELLSPRING8_JIS,
 		HAS_INTEGRATED_BUTTON,
 		0, sizeof(struct bt_data),
-		0x83, TYPE3, FINGER_TYPE3, FINGER_TYPE3 + SIZEOF_ALL_FINGERS,
+		0x83, DATAFORMAT(TYPE3),
 		{ SN_PRESSURE, 0, 300 },
 		{ SN_WIDTH, 0, 2048 },
 		{ SN_COORD, -4620, 5140 },
 		{ SN_COORD, -150, 6600 },
 		{ SN_ORIENT, -MAX_FINGER_ORIENTATION, MAX_FINGER_ORIENTATION }
 	},
+	{
+		USB_DEVICE_ID_APPLE_WELLSPRING9_ANSI,
+		USB_DEVICE_ID_APPLE_WELLSPRING9_ISO,
+		USB_DEVICE_ID_APPLE_WELLSPRING9_JIS,
+		HAS_INTEGRATED_BUTTON,
+		0, sizeof(struct bt_data),
+		0x83, DATAFORMAT(TYPE4),
+		{ SN_PRESSURE, 0, 300 },
+		{ SN_WIDTH, 0, 2048 },
+		{ SN_COORD, -4828, 5345 },
+		{ SN_COORD, -203, 6803 },
+		{ SN_ORIENT, -MAX_FINGER_ORIENTATION, MAX_FINGER_ORIENTATION }
+	},
 	{}
 };
 	struct input_dev *input = dev->input;
 	int raw_n, i, n = 0;
-	if (size < c->tp_offset || (size - c->tp_offset) % SIZEOF_FINGER != 0)
+	if (size < c->tp_header || (size - c->tp_header) % c->tp_fsize != 0)
 		return -EIO;
-	/* finger data, le16-aligned */
+	raw_n = (size - c->tp_header) / c->tp_fsize;
-	f = (const struct tp_finger *)(dev->tp_data + c->tp_offset);
-	raw_n = (size - c->tp_offset) / SIZEOF_FINGER;
 	for (i = 0; i < raw_n; i++) {
-		if (raw2int(f[i].touch_major) == 0)
+		f = get_tp_finger(dev, i);
+		if (raw2int(f->touch_major) == 0)
 			continue;
-		dev->pos[n].x = raw2int(f[i].abs_x);
+		dev->pos[n].x = raw2int(f->abs_x);
-		dev->pos[n].y = c->y.min + c->y.max - raw2int(f[i].abs_y);
+		dev->pos[n].y = c->y.min + c->y.max - raw2int(f->abs_y);
-		dev->index[n++] = &f[i];
+		dev->index[n++] = f;
 	}
 	input_mt_assign_slots(input, dev->slots, dev->pos, n, 0);
 	input_mt_sync_frame(input);
-	report_synaptics_data(input, c, f, raw_n);
+	report_synaptics_data(input, c, get_tp_finger(dev, 0), raw_n);
-	/* type 2 reports button events via ibt only */
+	/* later types report button events via integrated button only */
-	if (c->tp_type == TYPE2) {
+	if (c->caps & HAS_INTEGRATED_BUTTON) {
-		int ibt = raw2int(dev->tp_data[BUTTON_TYPE2]);
+		int ibt = raw2int(dev->tp_data[c->tp_button]);
 		input_report_key(input, BTN_LEFT, ibt);
 	}
-	if (c->tp_type == TYPE3)
-		input_report_key(input, BTN_LEFT, dev->tp_data[BUTTON_TYPE3]);
 	input_sync(input);
 	return 0;
 }
-/* Wellspring initialization constants */
-#define BCM5974_WELLSPRING_MODE_READ_REQUEST_ID		1
-#define BCM5974_WELLSPRING_MODE_WRITE_REQUEST_ID	9
-#define BCM5974_WELLSPRING_MODE_REQUEST_VALUE		0x300
-#define BCM5974_WELLSPRING_MODE_REQUEST_INDEX		0
-#define BCM5974_WELLSPRING_MODE_VENDOR_VALUE		0x01
-#define BCM5974_WELLSPRING_MODE_NORMAL_VALUE		0x08
 static int bcm5974_wellspring_mode(struct bcm5974 *dev, bool on)
 {
+	const struct bcm5974_config *c = &dev->cfg;
 	int retval = 0, size;
 	char *data;
 	if (dev->cfg.tp_type == TYPE3)
 		return 0;
-	data = kmalloc(8, GFP_KERNEL);
+	data = kmalloc(c->um_size, GFP_KERNEL);
 	if (!data) {
 		dev_err(&dev->intf->dev, "out of memory\n");
 		retval = -ENOMEM;
 	size = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0),
 			BCM5974_WELLSPRING_MODE_READ_REQUEST_ID,
 			USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE,
-			BCM5974_WELLSPRING_MODE_REQUEST_VALUE,
+			c->um_req_val, c->um_req_idx, data, c->um_size, 5000);
-			BCM5974_WELLSPRING_MODE_REQUEST_INDEX, data, 8, 5000);
-	if (size != 8) {
+	if (size != c->um_size) {
 		dev_err(&dev->intf->dev, "could not read from device\n");
 		retval = -EIO;
 		goto out;
 	}
 	/* apply the mode switch */
-	data[0] = on ?
+	data[c->um_switch_idx] = on ? c->um_switch_on : c->um_switch_off;
-		BCM5974_WELLSPRING_MODE_VENDOR_VALUE :
-		BCM5974_WELLSPRING_MODE_NORMAL_VALUE;
 	/* write configuration */
 	size = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
 			BCM5974_WELLSPRING_MODE_WRITE_REQUEST_ID,
 			USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE,
-			BCM5974_WELLSPRING_MODE_REQUEST_VALUE,
+			c->um_req_val, c->um_req_idx, data, c->um_size, 5000);
-			BCM5974_WELLSPRING_MODE_REQUEST_INDEX, data, 8, 5000);
-	if (size != 8) {
+	if (size != c->um_size) {
 		dev_err(&dev->intf->dev, "could not write to device\n");
 		retval = -EIO;
 		goto out;

drivers/input/mouse/elantech.c+28−7

 	struct elantech_data *etd = psmouse->private;
 	unsigned char *packet = psmouse->packet;
 	unsigned char packet_type = packet[3] & 0x03;
+	unsigned int ic_version;
 	bool sanity_check;
 	if (etd->tp_dev && (packet[3] & 0x0f) == 0x06)
 		return PACKET_TRACKPOINT;
+	/* This represents the version of IC body. */
+	ic_version = (etd->fw_version & 0x0f0000) >> 16;
 	/*
 	 * Sanity check based on the constant bits of a packet.
 	 * The constant bits change depending on the value of
-	 * the hardware flag 'crc_enabled' but are the same for
+	 * the hardware flag 'crc_enabled' and the version of
-	 * every packet, regardless of the type.
+	 * the IC body, but are the same for every packet,
+	 * regardless of the type.
 	 */
 	if (etd->crc_enabled)
 		sanity_check = ((packet[3] & 0x08) == 0x00);
+	else if (ic_version == 7 && etd->samples[1] == 0x2A)
+		sanity_check = ((packet[3] & 0x1c) == 0x10);
 	else
 		sanity_check = ((packet[0] & 0x0c) == 0x04 &&
 				(packet[3] & 0x1c) == 0x10);
  * Avatar AVIU-145A2       0x361f00        ?               clickpad
  * Fujitsu LIFEBOOK E544   0x470f00        d0, 12, 09      2 hw buttons
  * Fujitsu LIFEBOOK E554   0x570f01        40, 14, 0c      2 hw buttons
+ * Fujitsu T725            0x470f01        05, 12, 09      2 hw buttons
  * Fujitsu H730            0x570f00        c0, 14, 0c      3 hw buttons (**)
  * Gigabyte U2442          0x450f01        58, 17, 0c      2 hw buttons
  * Lenovo L430             0x350f02        b9, 15, 0c      2 hw buttons (*)
 	struct input_dev *dev = psmouse->dev;
 	struct elantech_data *etd = psmouse->private;
 	unsigned int x_min = 0, y_min = 0, x_max = 0, y_max = 0, width = 0;
-	unsigned int x_res = 0, y_res = 0;
+	unsigned int x_res = 31, y_res = 31;
 	if (elantech_set_range(psmouse, &x_min, &y_min, &x_max, &y_max, &width))
 		return -1;
 		/* For X to recognize me as touchpad. */
 		input_set_abs_params(dev, ABS_X, x_min, x_max, 0, 0);
 		input_set_abs_params(dev, ABS_Y, y_min, y_max, 0, 0);
-		input_abs_set_res(dev, ABS_X, x_res);
-		input_abs_set_res(dev, ABS_Y, y_res);
 		/*
 		 * range of pressure and width is the same as v2,
 		 * report ABS_PRESSURE, ABS_TOOL_WIDTH for compatibility.
 		input_mt_init_slots(dev, ETP_MAX_FINGERS, 0);
 		input_set_abs_params(dev, ABS_MT_POSITION_X, x_min, x_max, 0, 0);
 		input_set_abs_params(dev, ABS_MT_POSITION_Y, y_min, y_max, 0, 0);
-		input_abs_set_res(dev, ABS_MT_POSITION_X, x_res);
-		input_abs_set_res(dev, ABS_MT_POSITION_Y, y_res);
 		input_set_abs_params(dev, ABS_MT_PRESSURE, ETP_PMIN_V2,
 				     ETP_PMAX_V2, 0, 0);
 		/*
 		break;
 	}
+	input_abs_set_res(dev, ABS_X, x_res);
+	input_abs_set_res(dev, ABS_Y, y_res);
+	if (etd->hw_version > 1) {
+		input_abs_set_res(dev, ABS_MT_POSITION_X, x_res);
+		input_abs_set_res(dev, ABS_MT_POSITION_Y, y_res);
+	}
 	etd->y_max = y_max;
 	etd->width = width;
 		     etd->capabilities[0], etd->capabilities[1],
 		     etd->capabilities[2]);
+	if (etd->hw_version != 1) {
+		if (etd->send_cmd(psmouse, ETP_SAMPLE_QUERY, etd->samples)) {
+			psmouse_err(psmouse, "failed to query sample data\n");
+			goto init_fail;
+		}
+		psmouse_info(psmouse,
+			     "Elan sample query result %02x, %02x, %02x\n",
+			     etd->samples[0], etd->samples[1], etd->samples[2]);
+	}
 	if (elantech_set_absolute_mode(psmouse)) {
 		psmouse_err(psmouse,
 			    "failed to put touchpad into absolute mode.\n");

drivers/input/mouse/elantech.h+1−0

@@ -129,6 +129,7 @@ struct elantech_data { · 128 unmodified lines
129	unsigned char reg_26;	129	unsigned char reg_26;
130	unsigned char debug;	130	unsigned char debug;
131	unsigned char capabilities[3];	131	unsigned char capabilities[3];
		132	unsigned char samples[3];
132	bool paritycheck;	133	bool paritycheck;
133	bool jumpy_cursor;	134	bool jumpy_cursor;
134	bool reports_pressure;	135	bool reports_pressure;

drivers/input/mouse/synaptics.c+2−2

@@ -1484,12 +1484,12 @@ static int __synaptics_init(struct psmouse *psmouse, bool absolute_mode) · 1483 unmodified lines
1484	priv->pkt_type = SYN_MODEL_NEWABS(priv->model_id) ? SYN_NEWABS : SYN_OLDABS;	1484	priv->pkt_type = SYN_MODEL_NEWABS(priv->model_id) ? SYN_NEWABS : SYN_OLDABS;
1485		1485
1486	psmouse_info(psmouse,	1486	psmouse_info(psmouse,
1487	"Touchpad model: %ld, fw: %ld.%ld, id: %#lx, caps: %#lx/%#lx/%#lx, board id: %lu, fw id: %lu\n",	1487	"Touchpad model: %ld, fw: %ld.%ld, id: %#lx, caps: %#lx/%#lx/%#lx/%#lx, board id: %lu, fw id: %lu\n",
1488	SYN_ID_MODEL(priv->identity),	1488	SYN_ID_MODEL(priv->identity),
1489	SYN_ID_MAJOR(priv->identity), SYN_ID_MINOR(priv->identity),	1489	SYN_ID_MAJOR(priv->identity), SYN_ID_MINOR(priv->identity),
1490	priv->model_id,	1490	priv->model_id,
1491	priv->capabilities, priv->ext_cap, priv->ext_cap_0c,	1491	priv->capabilities, priv->ext_cap, priv->ext_cap_0c,
1492	priv->board_id, priv->firmware_id);	1492	priv->ext_cap_10, priv->board_id, priv->firmware_id);
1493		1493
1494	set_input_params(psmouse, priv);	1494	set_input_params(psmouse, priv);
1495		1495

drivers/input/touchscreen/goodix.c+36−0

@@ -15,6 +15,7 @@ · 14 unmodified lines
15	*/	15	*/
16		16
17	#include <linux/kernel.h>	17	#include <linux/kernel.h>
		18	#include <linux/dmi.h>
18	#include <linux/i2c.h>	19	#include <linux/i2c.h>
19	#include <linux/input.h>	20	#include <linux/input.h>
20	#include <linux/input/mt.h>	21	#include <linux/input/mt.h>
@@ -34,6 +35,7 @@ struct goodix_ts_data { · 13 unmodified lines
34	int abs_y_max;	35	int abs_y_max;
35	unsigned int max_touch_num;	36	unsigned int max_touch_num;
36	unsigned int int_trigger_type;	37	unsigned int int_trigger_type;
		38	bool rotated_screen;
37	};	39	};
38		40
39	#define GOODIX_MAX_HEIGHT 4096	41	#define GOODIX_MAX_HEIGHT 4096
@@ -60,6 +62,30 @@ static const unsigned long goodix_irq_flags[] = { · 20 unmodified lines
60	IRQ_TYPE_LEVEL_HIGH,	62	IRQ_TYPE_LEVEL_HIGH,
61	};	63	};
62		64
		65	/*
		66	* Those tablets have their coordinates origin at the bottom right
		67	* of the tablet, as if rotated 180 degrees
		68	*/
		69	static const struct dmi_system_id rotated_screen[] = {
		70	#if defined(CONFIG_DMI) && defined(CONFIG_X86)
		71	{
		72	.ident = "WinBook TW100",
		73	.matches = {
		74	DMI_MATCH(DMI_SYS_VENDOR, "WinBook"),
		75	DMI_MATCH(DMI_PRODUCT_NAME, "TW100")
		76	}
		77	},
		78	{
		79	.ident = "WinBook TW700",
		80	.matches = {
		81	DMI_MATCH(DMI_SYS_VENDOR, "WinBook"),
		82	DMI_MATCH(DMI_PRODUCT_NAME, "TW700")
		83	},
		84	},
		85	#endif
		86	{}
		87	};
		88
63	/**	89	/**
64	* goodix_i2c_read - read data from a register of the i2c slave device.	90	* goodix_i2c_read - read data from a register of the i2c slave device.
65	*	91	*
@@ -129,6 +155,11 @@ static void goodix_ts_report_touch(struct goodix_ts_data ts, u8 coor_data) · 63 unmodified lines
129	int input_y = get_unaligned_le16(&coor_data[3]);	155	int input_y = get_unaligned_le16(&coor_data[3]);
130	int input_w = get_unaligned_le16(&coor_data[5]);	156	int input_w = get_unaligned_le16(&coor_data[5]);
131		157
		158	if (ts->rotated_screen) {
		159	input_x = ts->abs_x_max - input_x;
		160	input_y = ts->abs_y_max - input_y;
		161	}
		162
132	input_mt_slot(ts->input_dev, id);	163	input_mt_slot(ts->input_dev, id);
133	input_mt_report_slot_state(ts->input_dev, MT_TOOL_FINGER, true);	164	input_mt_report_slot_state(ts->input_dev, MT_TOOL_FINGER, true);
134	input_report_abs(ts->input_dev, ABS_MT_POSITION_X, input_x);	165	input_report_abs(ts->input_dev, ABS_MT_POSITION_X, input_x);
@@ -223,6 +254,11 @@ static void goodix_read_config(struct goodix_ts_data *ts) · 88 unmodified lines
223	ts->abs_y_max = GOODIX_MAX_HEIGHT;	254	ts->abs_y_max = GOODIX_MAX_HEIGHT;
224	ts->max_touch_num = GOODIX_MAX_CONTACTS;	255	ts->max_touch_num = GOODIX_MAX_CONTACTS;
225	}	256	}
		257
		258	ts->rotated_screen = dmi_check_system(rotated_screen);
		259	if (ts->rotated_screen)
		260	dev_dbg(&ts->client->dev,
		261	"Applying '180 degrees rotated screen' quirk\n");
226	}	262	}
227		263
228	/**	264	/**

drivers/input/touchscreen/usbtouchscreen.c+3−0

@@ -627,6 +627,9 @@ static int dmc_tsc10_init(struct usbtouch_usb *usbtouch) · 626 unmodified lines
627	goto err_out;	627	goto err_out;
628	}	628	}
629		629
		630	/* TSC-25 data sheet specifies a delay after the RESET command */
		631	msleep(150);
		632
630	/* set coordinate output rate */	633	/* set coordinate output rate */
631	buf[0] = buf[1] = 0xFF;	634	buf[0] = buf[1] = 0xFF;
632	ret = usb_control_msg(dev, usb_rcvctrlpipe (dev, 0),	635	ret = usb_control_msg(dev, usb_rcvctrlpipe (dev, 0),

drivers/iommu/amd_iommu.c+29−69

@@ -76,8 +76,6 @@ LIST_HEAD(hpet_map); · 75 unmodified lines
76	* Domain for untranslated devices - only allocated	76	* Domain for untranslated devices - only allocated
77	* if iommu=pt passed on kernel cmd line.	77	* if iommu=pt passed on kernel cmd line.
78	*/	78	*/
79	static struct protection_domain *pt_domain;
80
81	static const struct iommu_ops amd_iommu_ops;	79	static const struct iommu_ops amd_iommu_ops;
82		80
83	static ATOMIC_NOTIFIER_HEAD(ppr_notifier);	81	static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
@@ -96,7 +94,7 @@ struct iommu_dev_data { · 12 unmodified lines
96	struct protection_domain domain; / Domain the device is bound to */	94	struct protection_domain domain; / Domain the device is bound to */
97	u16 devid; /* PCI Device ID */	95	u16 devid; /* PCI Device ID */
98	bool iommu_v2; /* Device can make use of IOMMUv2 */	96	bool iommu_v2; /* Device can make use of IOMMUv2 */
99	bool passthrough; /* Default for device is pt_domain */	97	bool passthrough; /* Device is identity mapped */
100	struct {	98	struct {
101	bool enabled;	99	bool enabled;
102	int qdep;	100	int qdep;
@@ -116,7 +114,6 @@ struct iommu_cmd { · 13 unmodified lines
116	struct kmem_cache *amd_iommu_irq_cache;	114	struct kmem_cache *amd_iommu_irq_cache;
117		115
118	static void update_domain(struct protection_domain *domain);	116	static void update_domain(struct protection_domain *domain);
119	static int alloc_passthrough_domain(void);
120	static int protection_domain_init(struct protection_domain *domain);	117	static int protection_domain_init(struct protection_domain *domain);
121		118
122	/****************************************************************************	119	/****************************************************************************
@@ -2167,15 +2164,17 @@ static int attach_device(struct device *dev, · 2044 unmodified lines
2167	dev_data = get_dev_data(dev);	2164	dev_data = get_dev_data(dev);
2168		2165
2169	if (domain->flags & PD_IOMMUV2_MASK) {	2166	if (domain->flags & PD_IOMMUV2_MASK) {
2170	if (!dev_data->iommu_v2 \|\| !dev_data->passthrough)	2167	if (!dev_data->passthrough)
2171	return -EINVAL;	2168	return -EINVAL;
2172		2169
2173	if (pdev_iommuv2_enable(pdev) != 0)	2170	if (dev_data->iommu_v2) {
2174	return -EINVAL;	2171	if (pdev_iommuv2_enable(pdev) != 0)
		2172	return -EINVAL;
2175		2173
2176	dev_data->ats.enabled = true;	2174	dev_data->ats.enabled = true;
2177	dev_data->ats.qdep = pci_ats_queue_depth(pdev);	2175	dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2178	dev_data->pri_tlp = pci_pri_tlp_required(pdev);	2176	dev_data->pri_tlp = pci_pri_tlp_required(pdev);
		2177	}
2179	} else if (amd_iommu_iotlb_sup &&	2178	} else if (amd_iommu_iotlb_sup &&
2180	pci_enable_ats(pdev, PAGE_SHIFT) == 0) {	2179	pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2181	dev_data->ats.enabled = true;	2180	dev_data->ats.enabled = true;
@@ -2221,15 +2220,6 @@ static void __detach_device(struct iommu_dev_data *dev_data) · 39 unmodified lines
2221	do_detach(head);	2220	do_detach(head);
2222		2221
2223	spin_unlock_irqrestore(&domain->lock, flags);	2222	spin_unlock_irqrestore(&domain->lock, flags);
2224
2225	/*
2226	* If we run in passthrough mode the device must be assigned to the
2227	* passthrough domain if it is detached from any other domain.
2228	* Make sure we can deassign from the pt_domain itself.
2229	*/
2230	if (dev_data->passthrough &&
2231	(dev_data->domain == NULL && domain != pt_domain))
2232	__attach_device(dev_data, pt_domain);
2233	}	2223	}
2234		2224
2235	/*	2225	/*
@@ -2249,7 +2239,7 @@ static void detach_device(struct device *dev) · 13 unmodified lines
2249	__detach_device(dev_data);	2239	__detach_device(dev_data);
2250	write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);	2240	write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2251		2241
2252	if (domain->flags & PD_IOMMUV2_MASK)	2242	if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2253	pdev_iommuv2_disable(to_pci_dev(dev));	2243	pdev_iommuv2_disable(to_pci_dev(dev));
2254	else if (dev_data->ats.enabled)	2244	else if (dev_data->ats.enabled)
2255	pci_disable_ats(to_pci_dev(dev));	2245	pci_disable_ats(to_pci_dev(dev));
@@ -2287,17 +2277,15 @@ static int amd_iommu_add_device(struct device *dev) · 31 unmodified lines
2287		2277
2288	BUG_ON(!dev_data);	2278	BUG_ON(!dev_data);
2289		2279
2290	if (dev_data->iommu_v2)	2280	if (iommu_pass_through \|\| dev_data->iommu_v2)
2291	iommu_request_dm_for_dev(dev);	2281	iommu_request_dm_for_dev(dev);
2292		2282
2293	/* Domains are initialized for this device - have a look what we ended up with */	2283	/* Domains are initialized for this device - have a look what we ended up with */
2294	domain = iommu_get_domain_for_dev(dev);	2284	domain = iommu_get_domain_for_dev(dev);
2295	if (domain->type == IOMMU_DOMAIN_IDENTITY) {	2285	if (domain->type == IOMMU_DOMAIN_IDENTITY)
2296	dev_data->passthrough = true;	2286	dev_data->passthrough = true;
2297	dev->archdata.dma_ops = &nommu_dma_ops;	2287	else
2298	} else {
2299	dev->archdata.dma_ops = &amd_iommu_dma_ops;	2288	dev->archdata.dma_ops = &amd_iommu_dma_ops;
2300	}
2301		2289
2302	out:	2290	out:
2303	iommu_completion_wait(iommu);	2291	iommu_completion_wait(iommu);
@@ -2862,8 +2850,17 @@ int __init amd_iommu_init_api(void) · 558 unmodified lines
2862		2850
2863	int __init amd_iommu_init_dma_ops(void)	2851	int __init amd_iommu_init_dma_ops(void)
2864	{	2852	{
		2853	swiotlb = iommu_pass_through ? 1 : 0;
2865	iommu_detected = 1;	2854	iommu_detected = 1;
2866	swiotlb = 0;	2855
		2856	/*
		2857	* In case we don't initialize SWIOTLB (actually the common case
		2858	* when AMD IOMMU is enabled), make sure there are global
		2859	* dma_ops set as a fall-back for devices not handled by this
		2860	* driver (for example non-PCI devices).
		2861	*/
		2862	if (!swiotlb)
		2863	dma_ops = &nommu_dma_ops;
2867		2864
2868	amd_iommu_stats_init();	2865	amd_iommu_stats_init();
2869		2866
@@ -2947,21 +2944,6 @@ out_err: · 77 unmodified lines
2947	return NULL;	2944	return NULL;
2948	}	2945	}
2949		2946
2950	static int alloc_passthrough_domain(void)
2951	{
2952	if (pt_domain != NULL)
2953	return 0;
2954
2955	/* allocate passthrough domain */
2956	pt_domain = protection_domain_alloc();
2957	if (!pt_domain)
2958	return -ENOMEM;
2959
2960	pt_domain->mode = PAGE_MODE_NONE;
2961
2962	return 0;
2963	}
2964
2965	static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)	2947	static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2966	{	2948	{
2967	struct protection_domain *pdomain;	2949	struct protection_domain *pdomain;
@@ -3222,33 +3204,6 @@ static const struct iommu_ops amd_iommu_ops = { · 254 unmodified lines
3222	*	3204	*
3223	*****************************************************************************/	3205	*****************************************************************************/
3224		3206
3225	int __init amd_iommu_init_passthrough(void)
3226	{
3227	struct iommu_dev_data *dev_data;
3228	struct pci_dev *dev = NULL;
3229	int ret;
3230
3231	ret = alloc_passthrough_domain();
3232	if (ret)
3233	return ret;
3234
3235	for_each_pci_dev(dev) {
3236	if (!check_device(&dev->dev))
3237	continue;
3238
3239	dev_data = get_dev_data(&dev->dev);
3240	dev_data->passthrough = true;
3241
3242	attach_device(&dev->dev, pt_domain);
3243	}
3244
3245	amd_iommu_stats_init();
3246
3247	pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3248
3249	return 0;
3250	}
3251
3252	/* IOMMUv2 specific functions */	3207	/* IOMMUv2 specific functions */
3253	int amd_iommu_register_ppr_notifier(struct notifier_block *nb)	3208	int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3254	{	3209	{
@@ -3363,7 +3318,12 @@ static int __flush_pasid(struct protection_domain *domain, int pasid, · 108 unmodified lines
3363	struct amd_iommu *iommu;	3318	struct amd_iommu *iommu;
3364	int qdep;	3319	int qdep;
3365		3320
3366	BUG_ON(!dev_data->ats.enabled);	3321	/*
		3322	There might be non-IOMMUv2 capable devices in an IOMMUv2
		3323	* domain.
		3324	*/
		3325	if (!dev_data->ats.enabled)
		3326	continue;
3367		3327
3368	qdep = dev_data->ats.qdep;	3328	qdep = dev_data->ats.qdep;
3369	iommu = amd_iommu_rlookup_table[dev_data->devid];	3329	iommu = amd_iommu_rlookup_table[dev_data->devid];

drivers/iommu/amd_iommu_init.c+1−9

 	return true;
 }
-static int amd_iommu_init_dma(void)
-{
-	if (iommu_pass_through)
-		return amd_iommu_init_passthrough();
-	else
-		return amd_iommu_init_dma_ops();
-}
 /****************************************************************************
  *
  * AMD IOMMU Initialization State Machine
 		init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
 		break;
 	case IOMMU_INTERRUPTS_EN:
-		ret = amd_iommu_init_dma();
+		ret = amd_iommu_init_dma_ops();
 		init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
 		break;
 	case IOMMU_DMA_OPS:

drivers/iommu/amd_iommu_v2.c+21−3

 static void free_device_state(struct device_state *dev_state)
 {
+	struct iommu_group *group;
 	/*
 	 * First detach device from domain - No more PRI requests will arrive
 	 * from that device after it is unbound from the IOMMUv2 domain.
 	 */
-	iommu_detach_device(dev_state->domain, &dev_state->pdev->dev);
+	group = iommu_group_get(&dev_state->pdev->dev);
+	if (WARN_ON(!group))
+		return;
+	iommu_detach_group(dev_state->domain, group);
+	iommu_group_put(group);
 	/* Everything is down now, free the IOMMUv2 domain */
 	iommu_domain_free(dev_state->domain);
 int amd_iommu_init_device(struct pci_dev *pdev, int pasids)
 {
 	struct device_state *dev_state;
+	struct iommu_group *group;
 	unsigned long flags;
 	int ret, tmp;
 	u16 devid;
 	if (ret)
 		goto out_free_domain;
-	ret = iommu_attach_device(dev_state->domain, &pdev->dev);
+	group = iommu_group_get(&pdev->dev);
-	if (ret != 0)
+	if (!group)
 		goto out_free_domain;
+	ret = iommu_attach_group(dev_state->domain, group);
+	if (ret != 0)
+		goto out_drop_group;
+	iommu_group_put(group);
 	spin_lock_irqsave(&state_lock, flags);
 	if (__get_device_state(devid) != NULL) {
 	return 0;
+out_drop_group:
+	iommu_group_put(group);
 out_free_domain:
 	iommu_domain_free(dev_state->domain);

drivers/iommu/arm-smmu-v3.c+46−14

  * Stream table.
  *
  * Linear: Enough to cover 1 << IDR1.SIDSIZE entries
- * 2lvl: 8k L1 entries, 256 lazy entries per table (each table covers a PCI bus)
+ * 2lvl: 128k L1 entries,
+ *       256 lazy entries per table (each table covers a PCI bus)
  */
-#define STRTAB_L1_SZ_SHIFT		16
+#define STRTAB_L1_SZ_SHIFT		20
 #define STRTAB_SPLIT			8
 #define STRTAB_L1_DESC_DWORDS		1
 #define ARM64_TCR_TG0_SHIFT		14
 #define ARM64_TCR_TG0_MASK		0x3UL
 #define CTXDESC_CD_0_TCR_IRGN0_SHIFT	8
-#define ARM64_TCR_IRGN0_SHIFT		24
+#define ARM64_TCR_IRGN0_SHIFT		8
 #define ARM64_TCR_IRGN0_MASK		0x3UL
 #define CTXDESC_CD_0_TCR_ORGN0_SHIFT	10
-#define ARM64_TCR_ORGN0_SHIFT		26
+#define ARM64_TCR_ORGN0_SHIFT		10
 #define ARM64_TCR_ORGN0_MASK		0x3UL
 #define CTXDESC_CD_0_TCR_SH0_SHIFT	12
 #define ARM64_TCR_SH0_SHIFT		12
 #define ARM_SMMU_FEAT_HYP		(1 << 12)
 	u32				features;
+#define ARM_SMMU_OPT_SKIP_PREFETCH	(1 << 0)
+	u32				options;
 	struct arm_smmu_cmdq		cmdq;
 	struct arm_smmu_evtq		evtq;
 	struct arm_smmu_priq		priq;
 static DEFINE_SPINLOCK(arm_smmu_devices_lock);
 static LIST_HEAD(arm_smmu_devices);
+struct arm_smmu_option_prop {
+	u32 opt;
+	const char *prop;
+};
+static struct arm_smmu_option_prop arm_smmu_options[] = {
+	{ ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" },
+	{ 0, NULL},
+};
 static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
 {
 	return container_of(dom, struct arm_smmu_domain, domain);
 }
+static void parse_driver_options(struct arm_smmu_device *smmu)
+{
+	int i = 0;
+	do {
+		if (of_property_read_bool(smmu->dev->of_node,
+						arm_smmu_options[i].prop)) {
+			smmu->options |= arm_smmu_options[i].opt;
+			dev_notice(smmu->dev, "option %s\n",
+				arm_smmu_options[i].prop);
+		}
+	} while (arm_smmu_options[++i].opt);
+}
 /* Low-level queue manipulation functions */
 static bool queue_full(struct arm_smmu_queue *q)
 {
 	arm_smmu_sync_ste_for_sid(smmu, sid);
 	/* It's likely that we'll want to use the new STE soon */
-	arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd);
+	if (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH))
+		arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd);
 }
 static void arm_smmu_init_bypass_stes(u64 *strtab, unsigned int nent)
 		return 0;
 	size = 1 << (STRTAB_SPLIT + ilog2(STRTAB_STE_DWORDS) + 3);
-	strtab = &cfg->strtab[sid >> STRTAB_SPLIT << STRTAB_L1_DESC_DWORDS];
+	strtab = &cfg->strtab[(sid >> STRTAB_SPLIT) * STRTAB_L1_DESC_DWORDS];
 	desc->span = STRTAB_SPLIT + 1;
 	desc->l2ptr = dma_zalloc_coherent(smmu->dev, size, &desc->l2ptr_dma,
 {
 	void *strtab;
 	u64 reg;
-	u32 size;
+	u32 size, l1size;
 	int ret;
 	struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
 	/* Calculate the L1 size, capped to the SIDSIZE */
 	size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_L1_DESC_DWORDS) + 3);
 	size = min(size, smmu->sid_bits - STRTAB_SPLIT);
-	if (size + STRTAB_SPLIT < smmu->sid_bits)
+	cfg->num_l1_ents = 1 << size;
+	size += STRTAB_SPLIT;
+	if (size < smmu->sid_bits)
 		dev_warn(smmu->dev,
 			 "2-level strtab only covers %u/%u bits of SID\n",
-			 size + STRTAB_SPLIT, smmu->sid_bits);
+			 size, smmu->sid_bits);
-	cfg->num_l1_ents = 1 << size;
+	l1size = cfg->num_l1_ents * (STRTAB_L1_DESC_DWORDS << 3);
-	size = cfg->num_l1_ents * (STRTAB_L1_DESC_DWORDS << 3);
+	strtab = dma_zalloc_coherent(smmu->dev, l1size, &cfg->strtab_dma,
-	strtab = dma_zalloc_coherent(smmu->dev, size, &cfg->strtab_dma,
 				     GFP_KERNEL);
 	if (!strtab) {
 		dev_err(smmu->dev,
 	ret = arm_smmu_init_l1_strtab(smmu);
 	if (ret)
 		dma_free_coherent(smmu->dev,
-				  cfg->num_l1_ents *
+				  l1size,
-				  (STRTAB_L1_DESC_DWORDS << 3),
 				  strtab,
 				  cfg->strtab_dma);
 	return ret;
 	if (irq > 0)
 		smmu->gerr_irq = irq;
+	parse_driver_options(smmu);
 	/* Probe the h/w */
 	ret = arm_smmu_device_probe(smmu);
 	if (ret)

drivers/iommu/intel-iommu.c+6−3

 static void domain_exit(struct dmar_domain *domain)
 {
+	struct dmar_drhd_unit *drhd;
+	struct intel_iommu *iommu;
 	struct page *freelist = NULL;
-	int i;
 	/* Domain 0 is reserved, so dont process it */
 	if (!domain)
 	/* clear attached or cached domains */
 	rcu_read_lock();
-	for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus)
+	for_each_active_iommu(iommu, drhd)
-		iommu_detach_domain(domain, g_iommus[i]);
+		if (domain_type_is_vm(domain) ||
+		    test_bit(iommu->seq_id, domain->iommu_bmp))
+			iommu_detach_domain(domain, iommu);
 	rcu_read_unlock();
 	dma_free_pagelist(freelist);

drivers/irqchip/irq-mips-gic.c+1−1

@@ -538,7 +538,7 @@ static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) · 537 unmodified lines
538		538
539	static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)	539	static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
540	{	540	{
541	smp_call_function_interrupt();	541	generic_smp_call_function_interrupt();
542		542
543	return IRQ_HANDLED;	543	return IRQ_HANDLED;
544	}	544	}

drivers/isdn/gigaset/ser-gigaset.c+10−25

 	cs->hw.ser->tty = tty;
 	atomic_set(&cs->hw.ser->refcnt, 1);
 	init_completion(&cs->hw.ser->dead_cmp);
 	tty->disc_data = cs;
+	/* Set the amount of data we're willing to receive per call
+	 * from the hardware driver to half of the input buffer size
+	 * to leave some reserve.
+	 * Note: We don't do flow control towards the hardware driver.
+	 * If more data is received than will fit into the input buffer,
+	 * it will be dropped and an error will be logged. This should
+	 * never happen as the device is slow and the buffer size ample.
+	 */
+	tty->receive_room = RBUFSIZE/2;
 	/* OK.. Initialization of the datastructures and the HW is done.. Now
 	 * startup system and notify the LL that we are ready to run
 	 */
 	return 0;
 }
-/*
- * Read on the tty.
- * Unused, received data goes only to the Gigaset driver.
- */
-static ssize_t
-gigaset_tty_read(struct tty_struct *tty, struct file *file,
-		 unsigned char __user *buf, size_t count)
-{
-	return -EAGAIN;
-}
-/*
- * Write on the tty.
- * Unused, transmit data comes only from the Gigaset driver.
- */
-static ssize_t
-gigaset_tty_write(struct tty_struct *tty, struct file *file,
-		  const unsigned char *buf, size_t count)
-{
-	return -EAGAIN;
-}
 /*
  * Ioctl on the tty.
  * Called in process context only.
 	.open		= gigaset_tty_open,
 	.close		= gigaset_tty_close,
 	.hangup		= gigaset_tty_hangup,
-	.read		= gigaset_tty_read,
-	.write		= gigaset_tty_write,
 	.ioctl		= gigaset_tty_ioctl,
 	.receive_buf	= gigaset_tty_receive,
 	.write_wakeup	= gigaset_tty_wakeup,

drivers/macintosh/ans-lcd.c+1−1

@@ -7,7 +7,7 @@ · 6 unmodified lines
7	#include <linux/kernel.h>	7	#include <linux/kernel.h>
8	#include <linux/miscdevice.h>	8	#include <linux/miscdevice.h>
9	#include <linux/fcntl.h>	9	#include <linux/fcntl.h>
10	#include <linux/init.h>	10	#include <linux/module.h>
11	#include <linux/delay.h>	11	#include <linux/delay.h>
12	#include <linux/fs.h>	12	#include <linux/fs.h>
13		13

drivers/md/Kconfig+1−1

@@ -259,7 +259,7 @@ config DM_CRYPT · 258 unmodified lines
259	the ciphers you're going to use in the cryptoapi configuration.	259	the ciphers you're going to use in the cryptoapi configuration.
260		260
261	For further information on dm-crypt and userspace tools see:	261	For further information on dm-crypt and userspace tools see:
262	<http://code.google.com/p/cryptsetup/wiki/DMCrypt>	262	<https://gitlab.com/cryptsetup/cryptsetup/wikis/DMCrypt>
263		263
264	To compile this code as a module, choose M here: the module will	264	To compile this code as a module, choose M here: the module will
265	be called dm-crypt.	265	be called dm-crypt.

drivers/md/bitmap.c+17−11

 	bitmap_super_t *sb;
 	unsigned long chunksize, daemon_sleep, write_behind;
-	bitmap->storage.sb_page = alloc_page(GFP_KERNEL);
+	bitmap->storage.sb_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
 	if (bitmap->storage.sb_page == NULL)
 		return -ENOMEM;
 	bitmap->storage.sb_page->index = 0;
 	sb->state = cpu_to_le32(bitmap->flags);
 	bitmap->events_cleared = bitmap->mddev->events;
 	sb->events_cleared = cpu_to_le64(bitmap->mddev->events);
+	bitmap->mddev->bitmap_info.nodes = 0;
 	kunmap_atomic(sb);
 	unsigned long sectors_reserved = 0;
 	int err = -EINVAL;
 	struct page *sb_page;
+	loff_t offset = bitmap->mddev->bitmap_info.offset;
 	if (!bitmap->storage.file && !bitmap->mddev->bitmap_info.offset) {
 		chunksize = 128 * 1024 * 1024;
 		bm_blocks = ((bm_blocks+7) >> 3) + sizeof(bitmap_super_t);
 		/* to 4k blocks */
 		bm_blocks = DIV_ROUND_UP_SECTOR_T(bm_blocks, 4096);
-		bitmap->mddev->bitmap_info.offset += bitmap->cluster_slot * (bm_blocks << 3);
+		offset = bitmap->mddev->bitmap_info.offset + (bitmap->cluster_slot * (bm_blocks << 3));
 		pr_info("%s:%d bm slot: %d offset: %llu\n", __func__, __LINE__,
-			bitmap->cluster_slot, (unsigned long long)bitmap->mddev->bitmap_info.offset);
+			bitmap->cluster_slot, offset);
 	}
 	if (bitmap->storage.file) {
 				bitmap, bytes, sb_page);
 	} else {
 		err = read_sb_page(bitmap->mddev,
-				   bitmap->mddev->bitmap_info.offset,
+				   offset,
 				   sb_page,
 				   0, sizeof(bitmap_super_t));
 	}
 	daemon_sleep = le32_to_cpu(sb->daemon_sleep) * HZ;
 	write_behind = le32_to_cpu(sb->write_behind);
 	sectors_reserved = le32_to_cpu(sb->sectors_reserved);
-	nodes = le32_to_cpu(sb->nodes);
+	/* XXX: This is a hack to ensure that we don't use clustering
-	strlcpy(bitmap->mddev->bitmap_info.cluster_name, sb->cluster_name, 64);
+	 *  in case:
+	 *	- dm-raid is in use and
+	 *	- the nodes written in bitmap_sb is erroneous.
+	 */
+	if (!bitmap->mddev->sync_super) {
+		nodes = le32_to_cpu(sb->nodes);
+		strlcpy(bitmap->mddev->bitmap_info.cluster_name,
+				sb->cluster_name, 64);
+	}
 	/* verify that the bitmap-specific fields are valid */
 	if (sb->magic != cpu_to_le32(BITMAP_MAGIC))
 	kunmap_atomic(sb);
 	/* Assiging chunksize is required for "re_read" */
 	bitmap->mddev->bitmap_info.chunksize = chunksize;
-	if (nodes && (bitmap->cluster_slot < 0)) {
+	if (err == 0 && nodes && (bitmap->cluster_slot < 0)) {
 		err = md_setup_cluster(bitmap->mddev, nodes);
 		if (err) {
 			pr_err("%s: Could not setup cluster service (%d)\n",
 	if (IS_ERR(bitmap))
 		return PTR_ERR(bitmap);
-	rv = bitmap_read_sb(bitmap);
-	if (rv)
-		goto err;
 	rv = bitmap_init_from_disk(bitmap, 0);
 	if (rv)
 		goto err;

drivers/md/dm-cache-policy-mq.c+0−2

@@ -1471,5 +1471,3 @@ module_exit(mq_exit); · 1470 unmodified lines
1471	MODULE_AUTHOR("Joe Thornber <dm-devel@redhat.com>");	1471	MODULE_AUTHOR("Joe Thornber <dm-devel@redhat.com>");
1472	MODULE_LICENSE("GPL");	1472	MODULE_LICENSE("GPL");
1473	MODULE_DESCRIPTION("mq cache policy");	1473	MODULE_DESCRIPTION("mq cache policy");
1474
1475	MODULE_ALIAS("dm-cache-default");

drivers/md/dm-cache-policy-smq.c+3−1

 	if (from_cblock(cache_size)) {
 		mq->cache_hit_bits = alloc_bitset(from_cblock(cache_size));
-		if (!mq->cache_hit_bits && mq->cache_hit_bits) {
+		if (!mq->cache_hit_bits) {
 			DMERR("couldn't allocate cache hit bitset");
 			goto bad_cache_hit_bits;
 		}
 MODULE_AUTHOR("Joe Thornber <dm-devel@redhat.com>");
 MODULE_LICENSE("GPL");
 MODULE_DESCRIPTION("smq cache policy");
+MODULE_ALIAS("dm-cache-default");

drivers/md/dm-cache-target.c+4−3

 		wake_up(&cache->migration_wait);
 	mempool_free(mg, cache->migration_pool);
+	wake_worker(cache);
 }
 static int prealloc_data_structs(struct cache *cache, struct prealloc *p)
 		 * this bio might require one, we pause until there are some
 		 * prepared mappings to process.
 		 */
+		prealloc_used = true;
 		if (prealloc_data_structs(cache, &structs)) {
 			spin_lock_irqsave(&cache->lock, flags);
 			bio_list_merge(&cache->deferred_bios, &bios);
 			process_discard_bio(cache, &structs, bio);
 		else
 			process_bio(cache, &structs, bio);
-		prealloc_used = true;
 	}
 	if (prealloc_used)
 		 * this bio might require one, we pause until there are some
 		 * prepared mappings to process.
 		 */
+		prealloc_used = true;
 		if (prealloc_data_structs(cache, &structs)) {
 			spin_lock_irqsave(&cache->lock, flags);
 			list_splice(&cells, &cache->deferred_cells);
 		}
 		process_cell(cache, &structs, cell);
-		prealloc_used = true;
 	}
 	if (prealloc_used)
 		if (policy_writeback_work(cache->policy, &oblock, &cblock, busy))
 			break; /* no work to do */
+		prealloc_used = true;
 		if (prealloc_data_structs(cache, &structs) ||
 		    get_cell(cache, oblock, &structs, &old_ocell)) {
 			policy_set_dirty(cache->policy, oblock);
 		}
 		writeback(cache, &structs, oblock, cblock, old_ocell);
-		prealloc_used = true;
 	}
 	if (prealloc_used)

drivers/md/dm-thin-metadata.c+2−2

@@ -1293,8 +1293,8 @@ static int __release_metadata_snap(struct dm_pool_metadata *pmd) · 1292 unmodified lines
1293	return r;	1293	return r;
1294		1294
1295	disk_super = dm_block_data(copy);	1295	disk_super = dm_block_data(copy);
1296	dm_sm_dec_block(pmd->metadata_sm, le64_to_cpu(disk_super->data_mapping_root));	1296	dm_btree_del(&pmd->info, le64_to_cpu(disk_super->data_mapping_root));
1297	dm_sm_dec_block(pmd->metadata_sm, le64_to_cpu(disk_super->device_details_root));	1297	dm_btree_del(&pmd->details_info, le64_to_cpu(disk_super->device_details_root));
1298	dm_sm_dec_block(pmd->metadata_sm, held_root);	1298	dm_sm_dec_block(pmd->metadata_sm, held_root);
1299		1299
1300	return dm_tm_unlock(pmd->tm, copy);	1300	return dm_tm_unlock(pmd->tm, copy);

drivers/md/dm-thin.c+8−3

 	requeue_deferred_cells(tc);
 }
-static void error_retry_list(struct pool *pool)
+static void error_retry_list_with_code(struct pool *pool, int error)
 {
 	struct thin_c *tc;
 	rcu_read_lock();
 	list_for_each_entry_rcu(tc, &pool->active_thins, list)
-		error_thin_bio_list(tc, &tc->retry_on_resume_list, -EIO);
+		error_thin_bio_list(tc, &tc->retry_on_resume_list, error);
 	rcu_read_unlock();
 }
+static void error_retry_list(struct pool *pool)
+{
+	return error_retry_list_with_code(pool, -EIO);
+}
 /*
  * This section of code contains the logic for processing a thin device's IO.
  * Much of the code depends on pool object resources (lists, workqueues, etc)
 	if (get_pool_mode(pool) == PM_OUT_OF_DATA_SPACE && !pool->pf.error_if_no_space) {
 		pool->pf.error_if_no_space = true;
 		notify_of_pool_mode_change_to_oods(pool);
-		error_retry_list(pool);
+		error_retry_list_with_code(pool, -ENOSPC);
 	}
 }

drivers/md/dm.c+10−17

@@ -1729,7 +1729,8 @@ static int dm_merge_bvec(struct request_queue *q, · 1728 unmodified lines
1729	struct mapped_device *md = q->queuedata;	1729	struct mapped_device *md = q->queuedata;
1730	struct dm_table *map = dm_get_live_table_fast(md);	1730	struct dm_table *map = dm_get_live_table_fast(md);
1731	struct dm_target *ti;	1731	struct dm_target *ti;
1732	sector_t max_sectors, max_size = 0;	1732	sector_t max_sectors;
		1733	int max_size = 0;
1733		1734
1734	if (unlikely(!map))	1735	if (unlikely(!map))
1735	goto out;	1736	goto out;
@@ -1742,18 +1743,10 @@ static int dm_merge_bvec(struct request_queue *q, · 6 unmodified lines
1742	* Find maximum amount of I/O that won't need splitting	1743	* Find maximum amount of I/O that won't need splitting
1743	*/	1744	*/
1744	max_sectors = min(max_io_len(bvm->bi_sector, ti),	1745	max_sectors = min(max_io_len(bvm->bi_sector, ti),
1745	(sector_t) queue_max_sectors(q));	1746	(sector_t) BIO_MAX_SECTORS);
1746	max_size = (max_sectors << SECTOR_SHIFT) - bvm->bi_size;	1747	max_size = (max_sectors << SECTOR_SHIFT) - bvm->bi_size;
1747		1748	if (max_size < 0)
1748	/*	1749	max_size = 0;
1749	* FIXME: this stop-gap fix _must_ be cleaned up (by passing a sector_t
1750	* to the targets' merge function since it holds sectors not bytes).
1751	* Just doing this as an interim fix for stable@ because the more
1752	* comprehensive cleanup of switching to sector_t will impact every
1753	* DM target that implements a ->merge hook.
1754	*/
1755	if (max_size > INT_MAX)
1756	max_size = INT_MAX;
1757		1750
1758	/*	1751	/*
1759	* merge_bvec_fn() returns number of bytes	1752	* merge_bvec_fn() returns number of bytes
@@ -1761,13 +1754,13 @@ static int dm_merge_bvec(struct request_queue *q, · 1 unmodified line
1761	* max is precomputed maximal io size	1754	* max is precomputed maximal io size
1762	*/	1755	*/
1763	if (max_size && ti->type->merge)	1756	if (max_size && ti->type->merge)
1764	max_size = ti->type->merge(ti, bvm, biovec, (int) max_size);	1757	max_size = ti->type->merge(ti, bvm, biovec, max_size);
1765	/*	1758	/*
1766	* If the target doesn't support merge method and some of the devices	1759	* If the target doesn't support merge method and some of the devices
1767	* provided their merge_bvec method (we know this by looking for the	1760	* provided their merge_bvec method (we know this by looking at
1768	* max_hw_sectors that dm_set_device_limits may set), then we can't	1761	* queue_max_hw_sectors), then we can't allow bios with multiple vector
1769	* allow bios with multiple vector entries. So always set max_size	1762	* entries. So always set max_size to 0, and the code below allows
1770	* to 0, and the code below allows just one page.	1763	* just one page.
1771	*/	1764	*/
1772	else if (queue_max_hw_sectors(q) <= PAGE_SIZE >> 9)	1765	else if (queue_max_hw_sectors(q) <= PAGE_SIZE >> 9)
1773	max_size = 0;	1766	max_size = 0;

drivers/md/md-cluster.c+11−1

 /* md_cluster_info flags */
 #define		MD_CLUSTER_WAITING_FOR_NEWDISK		1
+#define		MD_CLUSTER_SUSPEND_READ_BALANCING	2
 struct md_cluster_info {
 static void recover_prep(void *arg)
 {
+	struct mddev *mddev = arg;
+	struct md_cluster_info *cinfo = mddev->cluster_info;
+	set_bit(MD_CLUSTER_SUSPEND_READ_BALANCING, &cinfo->state);
 }
 static void recover_slot(void *arg, struct dlm_slot *slot)
 	cinfo->slot_number = our_slot;
 	complete(&cinfo->completion);
+	clear_bit(MD_CLUSTER_SUSPEND_READ_BALANCING, &cinfo->state);
 }
 static const struct dlm_lockspace_ops md_ls_ops = {
 	resync_send(mddev, RESYNCING, 0, 0);
 }
-static int area_resyncing(struct mddev *mddev, sector_t lo, sector_t hi)
+static int area_resyncing(struct mddev *mddev, int direction,
+		sector_t lo, sector_t hi)
 {
 	struct md_cluster_info *cinfo = mddev->cluster_info;
 	int ret = 0;
 	struct suspend_info *s;
+	if ((direction == READ) &&
+		test_bit(MD_CLUSTER_SUSPEND_READ_BALANCING, &cinfo->state))
+		return 1;
 	spin_lock_irq(&cinfo->suspend_lock);
 	if (list_empty(&cinfo->suspend_list))
 		goto out;

drivers/md/md-cluster.h+1−1

@@ -18,7 +18,7 @@ struct md_cluster_operations { · 17 unmodified lines
18	int (metadata_update_start)(struct mddev mddev);	18	int (metadata_update_start)(struct mddev mddev);
19	int (metadata_update_finish)(struct mddev mddev);	19	int (metadata_update_finish)(struct mddev mddev);
20	int (metadata_update_cancel)(struct mddev mddev);	20	int (metadata_update_cancel)(struct mddev mddev);
21	int (area_resyncing)(struct mddev mddev, sector_t lo, sector_t hi);	21	int (area_resyncing)(struct mddev mddev, int direction, sector_t lo, sector_t hi);
22	int (add_new_disk_start)(struct mddev mddev, struct md_rdev *rdev);	22	int (add_new_disk_start)(struct mddev mddev, struct md_rdev *rdev);
23	int (add_new_disk_finish)(struct mddev mddev);	23	int (add_new_disk_finish)(struct mddev mddev);
24	int (new_disk_ack)(struct mddev mddev, bool ack);	24	int (new_disk_ack)(struct mddev mddev, bool ack);

drivers/md/md.c+4−2

 {
 	struct md_personality *pers = mddev->pers;
 	mddev_detach(mddev);
+	/* Ensure ->event_work is done */
+	flush_workqueue(md_misc_wq);
 	spin_lock(&mddev->lock);
 	mddev->ready = 0;
 	mddev->pers = NULL;
 	char *ptr;
 	int err;
-	file = kmalloc(sizeof(*file), GFP_NOIO);
+	file = kzalloc(sizeof(*file), GFP_NOIO);
 	if (!file)
 		return -ENOMEM;
 	err = request_module("md-cluster");
 	if (err) {
 		pr_err("md-cluster module not found.\n");
-		return err;
+		return -ENOENT;
 	}
 	spin_lock(&pers_lock);

drivers/md/persistent-data/dm-btree-internal.h+6−0

@@ -138,4 +138,10 @@ int lower_bound(struct btree_node *n, uint64_t key); · 137 unmodified lines
138		138
139	extern struct dm_block_validator btree_node_validator;	139	extern struct dm_block_validator btree_node_validator;
140		140
		141	/*
		142	* Value type for upper levels of multi-level btrees.
		143	*/
		144	extern void init_le64_type(struct dm_transaction_manager *tm,
		145	struct dm_btree_value_type *vt);
		146
141	#endif /* DM_BTREE_INTERNAL_H */	147	#endif /* DM_BTREE_INTERNAL_H */

drivers/md/persistent-data/dm-btree-remove.c+7−10

 	return r;
 }
-static struct dm_btree_value_type le64_type = {
-	.context = NULL,
-	.size = sizeof(__le64),
-	.inc = NULL,
-	.dec = NULL,
-	.equal = NULL
-};
 int dm_btree_remove(struct dm_btree_info *info, dm_block_t root,
 		    uint64_t *keys, dm_block_t *new_root)
 {
 	int index = 0, r = 0;
 	struct shadow_spine spine;
 	struct btree_node *n;
+	struct dm_btree_value_type le64_vt;
+	init_le64_type(info->tm, &le64_vt);
 	init_shadow_spine(&spine, info);
 	for (level = 0; level < info->levels; level++) {
 		r = remove_raw(&spine, info,
 			       (level == last_level ?
-				&info->value_type : &le64_type),
+				&info->value_type : &le64_vt),
 			       root, keys[level], (unsigned *)&index);
 		if (r < 0)
 			break;
 	int index = 0, r = 0;
 	struct shadow_spine spine;
 	struct btree_node *n;
+	struct dm_btree_value_type le64_vt;
 	uint64_t k;
+	init_le64_type(info->tm, &le64_vt);
 	init_shadow_spine(&spine, info);
 	for (level = 0; level < last_level; level++) {
-		r = remove_raw(&spine, info, &le64_type,
+		r = remove_raw(&spine, info, &le64_vt,
 			       root, keys[level], (unsigned *) &index);
 		if (r < 0)
 			goto out;
 					     value_ptr(n, index));
 		delete_at(n, index);
+		keys[last_level] = k + 1ull;
 	} else
 		r = -ENODATA;

drivers/md/persistent-data/dm-btree-spine.c+37−0

@@ -249,3 +249,40 @@ int shadow_root(struct shadow_spine *s) · 248 unmodified lines
249	{	249	{
250	return s->root;	250	return s->root;
251	}	251	}
		252
		253	static void le64_inc(void context, const void value_le)
		254	{
		255	struct dm_transaction_manager *tm = context;
		256	__le64 v_le;
		257
		258	memcpy(&v_le, value_le, sizeof(v_le));
		259	dm_tm_inc(tm, le64_to_cpu(v_le));
		260	}
		261
		262	static void le64_dec(void context, const void value_le)
		263	{
		264	struct dm_transaction_manager *tm = context;
		265	__le64 v_le;
		266
		267	memcpy(&v_le, value_le, sizeof(v_le));
		268	dm_tm_dec(tm, le64_to_cpu(v_le));
		269	}
		270
		271	static int le64_equal(void context, const void value1_le, const void *value2_le)
		272	{
		273	__le64 v1_le, v2_le;
		274
		275	memcpy(&v1_le, value1_le, sizeof(v1_le));
		276	memcpy(&v2_le, value2_le, sizeof(v2_le));
		277	return v1_le == v2_le;
		278	}
		279
		280	void init_le64_type(struct dm_transaction_manager *tm,
		281	struct dm_btree_value_type *vt)
		282	{
		283	vt->context = tm;
		284	vt->size = sizeof(__le64);
		285	vt->inc = le64_inc;
		286	vt->dec = le64_dec;
		287	vt->equal = le64_equal;
		288	}

drivers/md/persistent-data/dm-btree.c+1−6

 	struct btree_node *n;
 	struct dm_btree_value_type le64_type;
-	le64_type.context = NULL;
+	init_le64_type(info->tm, &le64_type);
-	le64_type.size = sizeof(__le64);
-	le64_type.inc = NULL;
-	le64_type.dec = NULL;
-	le64_type.equal = NULL;
 	init_shadow_spine(&spine, info);
 	for (level = 0; level < (info->levels - 1); level++) {

drivers/md/raid1.c+11−8

 		spin_lock_irqsave(&conf->device_lock, flags);
 		if (r1_bio->mddev->degraded == conf->raid_disks ||
 		    (r1_bio->mddev->degraded == conf->raid_disks-1 &&
-		     !test_bit(Faulty, &conf->mirrors[mirror].rdev->flags)))
+		     test_bit(In_sync, &conf->mirrors[mirror].rdev->flags)))
 			uptodate = 1;
 		spin_unlock_irqrestore(&conf->device_lock, flags);
 	}
 	if ((conf->mddev->recovery_cp < this_sector + sectors) ||
 	    (mddev_is_clustered(conf->mddev) &&
-	    md_cluster_ops->area_resyncing(conf->mddev, this_sector,
+	    md_cluster_ops->area_resyncing(conf->mddev, READ, this_sector,
 		    this_sector + sectors)))
 		choose_first = 1;
 	else
 	    ((bio_end_sector(bio) > mddev->suspend_lo &&
 	    bio->bi_iter.bi_sector < mddev->suspend_hi) ||
 	    (mddev_is_clustered(mddev) &&
-	     md_cluster_ops->area_resyncing(mddev, bio->bi_iter.bi_sector, bio_end_sector(bio))))) {
+	     md_cluster_ops->area_resyncing(mddev, WRITE,
+		     bio->bi_iter.bi_sector, bio_end_sector(bio))))) {
 		/* As the suspend_* range is controlled by
 		 * userspace, we want an interruptible
 		 * wait.
 			if (bio_end_sector(bio) <= mddev->suspend_lo ||
 			    bio->bi_iter.bi_sector >= mddev->suspend_hi ||
 			    (mddev_is_clustered(mddev) &&
-			     !md_cluster_ops->area_resyncing(mddev,
+			     !md_cluster_ops->area_resyncing(mddev, WRITE,
 				     bio->bi_iter.bi_sector, bio_end_sector(bio))))
 				break;
 			schedule();
 {
 	char b[BDEVNAME_SIZE];
 	struct r1conf *conf = mddev->private;
+	unsigned long flags;
 	/*
 	 * If it is not operational, then we have already marked it as dead
 		return;
 	}
 	set_bit(Blocked, &rdev->flags);
+	spin_lock_irqsave(&conf->device_lock, flags);
 	if (test_and_clear_bit(In_sync, &rdev->flags)) {
-		unsigned long flags;
-		spin_lock_irqsave(&conf->device_lock, flags);
 		mddev->degraded++;
 		set_bit(Faulty, &rdev->flags);
-		spin_unlock_irqrestore(&conf->device_lock, flags);
 	} else
 		set_bit(Faulty, &rdev->flags);
+	spin_unlock_irqrestore(&conf->device_lock, flags);
 	/*
 	 * if recovery is running, make sure it aborts.
 	 */
 	 * Find all failed disks within the RAID1 configuration
 	 * and mark them readable.
 	 * Called under mddev lock, so rcu protection not needed.
+	 * device_lock used to avoid races with raid1_end_read_request
+	 * which expects 'In_sync' flags and ->degraded to be consistent.
 	 */
+	spin_lock_irqsave(&conf->device_lock, flags);
 	for (i = 0; i < conf->raid_disks; i++) {
 		struct md_rdev *rdev = conf->mirrors[i].rdev;
 		struct md_rdev *repl = conf->mirrors[conf->raid_disks + i].rdev;
 			sysfs_notify_dirent_safe(rdev->sysfs_state);
 		}
 	}
-	spin_lock_irqsave(&conf->device_lock, flags);
 	mddev->degraded -= count;
 	spin_unlock_irqrestore(&conf->device_lock, flags);

drivers/md/raid10.c+4−1

 			/* far_copies must be 1 */
 			conf->prev.stride = conf->dev_sectors;
 	}
+	conf->reshape_safe = conf->reshape_progress;
 	spin_lock_init(&conf->device_lock);
 	INIT_LIST_HEAD(&conf->retry_list);
 		}
 		conf->offset_diff = min_offset_diff;
-		conf->reshape_safe = conf->reshape_progress;
 		clear_bit(MD_RECOVERY_SYNC, &mddev->recovery);
 		clear_bit(MD_RECOVERY_CHECK, &mddev->recovery);
 		set_bit(MD_RECOVERY_RESHAPE, &mddev->recovery);
 		conf->reshape_progress = size;
 	} else
 		conf->reshape_progress = 0;
+	conf->reshape_safe = conf->reshape_progress;
 	spin_unlock_irq(&conf->device_lock);
 	if (mddev->delta_disks && mddev->bitmap) {
 		rdev->new_data_offset = rdev->data_offset;
 	smp_wmb();
 	conf->reshape_progress = MaxSector;
+	conf->reshape_safe = MaxSector;
 	mddev->reshape_position = MaxSector;
 	spin_unlock_irq(&conf->device_lock);
 	return ret;
 	md_finish_reshape(conf->mddev);
 	smp_wmb();
 	conf->reshape_progress = MaxSector;
+	conf->reshape_safe = MaxSector;
 	spin_unlock_irq(&conf->device_lock);
 	/* read-ahead size must cover two whole stripes, which is

drivers/md/raid5.c+30−8

@@ -2162,6 +2162,9 @@ static int resize_stripes(struct r5conf *conf, int newsize) · 2161 unmodified lines
2162	if (!sc)	2162	if (!sc)
2163	return -ENOMEM;	2163	return -ENOMEM;
2164		2164
		2165	/* Need to ensure auto-resizing doesn't interfere */
		2166	mutex_lock(&conf->cache_size_mutex);
		2167
2165	for (i = conf->max_nr_stripes; i; i--) {	2168	for (i = conf->max_nr_stripes; i; i--) {
2166	nsh = alloc_stripe(sc, GFP_KERNEL);	2169	nsh = alloc_stripe(sc, GFP_KERNEL);
2167	if (!nsh)	2170	if (!nsh)
@@ -2178,6 +2181,7 @@ static int resize_stripes(struct r5conf *conf, int newsize) · 10 unmodified lines
2178	kmem_cache_free(sc, nsh);	2181	kmem_cache_free(sc, nsh);
2179	}	2182	}
2180	kmem_cache_destroy(sc);	2183	kmem_cache_destroy(sc);
		2184	mutex_unlock(&conf->cache_size_mutex);
2181	return -ENOMEM;	2185	return -ENOMEM;
2182	}	2186	}
2183	/* Step 2 - Must use GFP_NOIO now.	2187	/* Step 2 - Must use GFP_NOIO now.
@@ -2224,6 +2228,7 @@ static int resize_stripes(struct r5conf *conf, int newsize) · 40 unmodified lines
2224	} else	2228	} else
2225	err = -ENOMEM;	2229	err = -ENOMEM;
2226		2230
		2231	mutex_unlock(&conf->cache_size_mutex);
2227	/* Step 4, return new stripes to service */	2232	/* Step 4, return new stripes to service */
2228	while(!list_empty(&newstripes)) {	2233	while(!list_empty(&newstripes)) {
2229	nsh = list_entry(newstripes.next, struct stripe_head, lru);	2234	nsh = list_entry(newstripes.next, struct stripe_head, lru);
@@ -2251,7 +2256,7 @@ static int resize_stripes(struct r5conf *conf, int newsize) · 21 unmodified lines
2251	static int drop_one_stripe(struct r5conf *conf)	2256	static int drop_one_stripe(struct r5conf *conf)
2252	{	2257	{
2253	struct stripe_head *sh;	2258	struct stripe_head *sh;
2254	int hash = (conf->max_nr_stripes - 1) % NR_STRIPE_HASH_LOCKS;	2259	int hash = (conf->max_nr_stripes - 1) & STRIPE_HASH_LOCKS_MASK;
2255		2260
2256	spin_lock_irq(conf->hash_locks + hash);	2261	spin_lock_irq(conf->hash_locks + hash);
2257	sh = get_free_stripe(conf, hash);	2262	sh = get_free_stripe(conf, hash);
@@ -4061,8 +4066,10 @@ static void analyse_stripe(struct stripe_head sh, struct stripe_head_state s) · 1803 unmodified lines
4061	&first_bad, &bad_sectors))	4066	&first_bad, &bad_sectors))
4062	set_bit(R5_ReadRepl, &dev->flags);	4067	set_bit(R5_ReadRepl, &dev->flags);
4063	else {	4068	else {
4064	if (rdev)	4069	if (rdev && !test_bit(Faulty, &rdev->flags))
4065	set_bit(R5_NeedReplace, &dev->flags);	4070	set_bit(R5_NeedReplace, &dev->flags);
		4071	else
		4072	clear_bit(R5_NeedReplace, &dev->flags);
4066	rdev = rcu_dereference(conf->disks[i].rdev);	4073	rdev = rcu_dereference(conf->disks[i].rdev);
4067	clear_bit(R5_ReadRepl, &dev->flags);	4074	clear_bit(R5_ReadRepl, &dev->flags);
4068	}	4075	}
@@ -5857,12 +5864,14 @@ static void raid5d(struct md_thread *thread) · 1788 unmodified lines
5857	pr_debug("%d stripes handled\n", handled);	5864	pr_debug("%d stripes handled\n", handled);
5858		5865
5859	spin_unlock_irq(&conf->device_lock);	5866	spin_unlock_irq(&conf->device_lock);
5860	if (test_and_clear_bit(R5_ALLOC_MORE, &conf->cache_state)) {	5867	if (test_and_clear_bit(R5_ALLOC_MORE, &conf->cache_state) &&
		5868	mutex_trylock(&conf->cache_size_mutex)) {
5861	grow_one_stripe(conf, __GFP_NOWARN);	5869	grow_one_stripe(conf, __GFP_NOWARN);
5862	/* Set flag even if allocation failed. This helps	5870	/* Set flag even if allocation failed. This helps
5863	* slow down allocation requests when mem is short	5871	* slow down allocation requests when mem is short
5864	*/	5872	*/
5865	set_bit(R5_DID_ALLOC, &conf->cache_state);	5873	set_bit(R5_DID_ALLOC, &conf->cache_state);
		5874	mutex_unlock(&conf->cache_size_mutex);
5866	}	5875	}
5867		5876
5868	async_tx_issue_pending_all();	5877	async_tx_issue_pending_all();
@@ -5894,18 +5903,22 @@ raid5_set_cache_size(struct mddev *mddev, int size) · 25 unmodified lines
5894	return -EINVAL;	5903	return -EINVAL;
5895		5904
5896	conf->min_nr_stripes = size;	5905	conf->min_nr_stripes = size;
		5906	mutex_lock(&conf->cache_size_mutex);
5897	while (size < conf->max_nr_stripes &&	5907	while (size < conf->max_nr_stripes &&
5898	drop_one_stripe(conf))	5908	drop_one_stripe(conf))
5899	;	5909	;
		5910	mutex_unlock(&conf->cache_size_mutex);
5900		5911
5901		5912
5902	err = md_allow_write(mddev);	5913	err = md_allow_write(mddev);
5903	if (err)	5914	if (err)
5904	return err;	5915	return err;
5905		5916
		5917	mutex_lock(&conf->cache_size_mutex);
5906	while (size > conf->max_nr_stripes)	5918	while (size > conf->max_nr_stripes)
5907	if (!grow_one_stripe(conf, GFP_KERNEL))	5919	if (!grow_one_stripe(conf, GFP_KERNEL))
5908	break;	5920	break;
		5921	mutex_unlock(&conf->cache_size_mutex);
5909		5922
5910	return 0;	5923	return 0;
5911	}	5924	}
@@ -6371,11 +6384,19 @@ static unsigned long raid5_cache_scan(struct shrinker *shrink, · 459 unmodified lines
6371	struct shrink_control *sc)	6384	struct shrink_control *sc)
6372	{	6385	{
6373	struct r5conf *conf = container_of(shrink, struct r5conf, shrinker);	6386	struct r5conf *conf = container_of(shrink, struct r5conf, shrinker);
6374	int ret = 0;	6387	unsigned long ret = SHRINK_STOP;
6375	while (ret < sc->nr_to_scan) {	6388
6376	if (drop_one_stripe(conf) == 0)	6389	if (mutex_trylock(&conf->cache_size_mutex)) {
6377	return SHRINK_STOP;	6390	ret= 0;
6378	ret++;	6391	while (ret < sc->nr_to_scan &&
		6392	conf->max_nr_stripes > conf->min_nr_stripes) {
		6393	if (drop_one_stripe(conf) == 0) {
		6394	ret = SHRINK_STOP;
		6395	break;
		6396	}
		6397	ret++;
		6398	}
		6399	mutex_unlock(&conf->cache_size_mutex);
6379	}	6400	}
6380	return ret;	6401	return ret;
6381	}	6402	}
@@ -6444,6 +6465,7 @@ static struct r5conf setup_conf(struct mddev mddev) · 62 unmodified lines
6444	goto abort;	6465	goto abort;
6445	spin_lock_init(&conf->device_lock);	6466	spin_lock_init(&conf->device_lock);
6446	seqcount_init(&conf->gen_lock);	6467	seqcount_init(&conf->gen_lock);
		6468	mutex_init(&conf->cache_size_mutex);
6447	init_waitqueue_head(&conf->wait_for_quiescent);	6469	init_waitqueue_head(&conf->wait_for_quiescent);
6448	for (i = 0; i < NR_STRIPE_HASH_LOCKS; i++) {	6470	for (i = 0; i < NR_STRIPE_HASH_LOCKS; i++) {
6449	init_waitqueue_head(&conf->wait_for_stripe[i]);	6471	init_waitqueue_head(&conf->wait_for_stripe[i]);

drivers/md/raid5.h+2−1

@@ -482,7 +482,8 @@ struct r5conf { · 481 unmodified lines
482	*/	482	*/
483	int active_name;	483	int active_name;
484	char cache_name[2][32];	484	char cache_name[2][32];
485	struct kmem_cache slab_cache; / for allocating stripes */	485	struct kmem_cache slab_cache; / for allocating stripes */
		486	struct mutex cache_size_mutex; /* Protect changes to cache size */
486		487
487	int seq_flush, seq_write;	488	int seq_flush, seq_write;
488	int quiesce;	489	int quiesce;

drivers/media/pci/ivtv/ivtvfb.c+9−6

     Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/fb.h>
 {
 	int rc;
+#ifdef CONFIG_X86_64
+	if (pat_enabled()) {
+		pr_warn("ivtvfb needs PAT disabled, boot with nopat kernel parameter\n");
+		return -ENODEV;
+	}
+#endif
 	if (itv->osd_info) {
 		IVTVFB_ERR("Card %d already initialised\n", ivtvfb_card_id);
 		return -EBUSY;
 	int registered = 0;
 	int err;
-#ifdef CONFIG_X86_64
-	if (WARN(pat_enabled(),
-		 "ivtvfb needs PAT disabled, boot with nopat kernel parameter\n")) {
-		return -ENODEV;
-	}
-#endif
 	if (ivtvfb_card_id < -1 || ivtvfb_card_id >= IVTV_MAX_CARDS) {
 		printk(KERN_ERR "ivtvfb:  ivtvfb_card_id parameter is out of range (valid range: -1 - %d)\n",

drivers/memory/omap-gpmc.c+6−0

 {
 	int i;
+	if (!gpmc_base)
+		return;
 	gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
 	gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
 	gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
 {
 	int i;
+	if (!gpmc_base)
+		return;
 	gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
 	gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
 	gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);

drivers/mfd/Kconfig+1−1

@@ -115,7 +115,7 @@ config MFD_CROS_EC_I2C · 114 unmodified lines
115		115
116	config MFD_CROS_EC_SPI	116	config MFD_CROS_EC_SPI
117	tristate "ChromeOS Embedded Controller (SPI)"	117	tristate "ChromeOS Embedded Controller (SPI)"
118	depends on MFD_CROS_EC && CROS_EC_PROTO && SPI && OF	118	depends on MFD_CROS_EC && CROS_EC_PROTO && SPI
119		119
120	---help---	120	---help---
121	If you say Y here, you get support for talking to the ChromeOS EC	121	If you say Y here, you get support for talking to the ChromeOS EC

drivers/mfd/arizona-core.c+7−9

 		arizona->has_fully_powered_off = true;
-		disable_irq(arizona->irq);
+		disable_irq_nosync(arizona->irq);
 		arizona_enable_reset(arizona);
 		regulator_bulk_disable(arizona->num_core_supplies,
 				       arizona->core_supplies);
 			     arizona->pdata.gpio_defaults[i]);
 	}
-	pm_runtime_set_autosuspend_delay(arizona->dev, 100);
-	pm_runtime_use_autosuspend(arizona->dev);
-	pm_runtime_enable(arizona->dev);
 	/* Chip default */
 	if (!arizona->pdata.clk32k_src)
 		arizona->pdata.clk32k_src = ARIZONA_32KZ_MCLK2;
 					   arizona->pdata.spk_fmt[i]);
 	}
+	pm_runtime_set_active(arizona->dev);
+	pm_runtime_enable(arizona->dev);
 	/* Set up for interrupts */
 	ret = arizona_irq_init(arizona);
 	if (ret != 0)
 		goto err_reset;
+	pm_runtime_set_autosuspend_delay(arizona->dev, 100);
+	pm_runtime_use_autosuspend(arizona->dev);
 	arizona_request_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, "CLKGEN error",
 			    arizona_clkgen_err, arizona);
 	arizona_request_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, "Overclocked",
 		goto err_irq;
 	}
-#ifdef CONFIG_PM
-	regulator_disable(arizona->dcvdd);
-#endif
 	return 0;
 err_irq:

drivers/misc/eeprom/at24.c+0−3

@@ -438,9 +438,6 @@ static ssize_t at24_bin_write(struct file filp, struct kobject kobj, · 437 unmodified lines
438	{	438	{
439	struct at24_data *at24;	439	struct at24_data *at24;
440		440
441	if (unlikely(off >= attr->size))
442	return -EFBIG;
443
444	at24 = dev_get_drvdata(container_of(kobj, struct device, kobj));	441	at24 = dev_get_drvdata(container_of(kobj, struct device, kobj));
445	return at24_write(at24, buf, off, count);	442	return at24_write(at24, buf, off, count);
446	}	443	}

drivers/misc/mei/main.c+1−1

@@ -682,7 +682,7 @@ int mei_register(struct mei_device dev, struct device parent) · 681 unmodified lines
682	/* Fill in the data structures */	682	/* Fill in the data structures */
683	devno = MKDEV(MAJOR(mei_devt), dev->minor);	683	devno = MKDEV(MAJOR(mei_devt), dev->minor);
684	cdev_init(&dev->cdev, &mei_fops);	684	cdev_init(&dev->cdev, &mei_fops);
685	dev->cdev.owner = mei_fops.owner;	685	dev->cdev.owner = parent->driver->owner;
686		686
687	/* Add the device */	687	/* Add the device */
688	ret = cdev_add(&dev->cdev, devno, 1);	688	ret = cdev_add(&dev->cdev, devno, 1);

drivers/misc/mic/scif/scif_nodeqp.c+5−10

 }
 static struct scatterlist *
-scif_p2p_setsg(void __iomem *va, int page_size, int page_cnt)
+scif_p2p_setsg(phys_addr_t pa, int page_size, int page_cnt)
 {
 	struct scatterlist *sg;
 	struct page *page;
 		return NULL;
 	sg_init_table(sg, page_cnt);
 	for (i = 0; i < page_cnt; i++) {
-		page = vmalloc_to_page((void __force *)va);
+		page = pfn_to_page(pa >> PAGE_SHIFT);
-		if (!page)
-			goto p2p_sg_err;
 		sg_set_page(&sg[i], page, page_size, 0);
-		va += page_size;
+		pa += page_size;
 	}
 	return sg;
-p2p_sg_err:
-	kfree(sg);
-	return NULL;
 }
 /* Init p2p mappings required to access peerdev from scifdev */
 	p2p = kzalloc(sizeof(*p2p), GFP_KERNEL);
 	if (!p2p)
 		return NULL;
-	p2p->ppi_sg[SCIF_PPI_MMIO] = scif_p2p_setsg(psdev->mmio->va,
+	p2p->ppi_sg[SCIF_PPI_MMIO] = scif_p2p_setsg(psdev->mmio->pa,
 						    PAGE_SIZE, num_mmio_pages);
 	if (!p2p->ppi_sg[SCIF_PPI_MMIO])
 		goto free_p2p;
 	p2p->sg_nentries[SCIF_PPI_MMIO] = num_mmio_pages;
 	sg_page_shift = get_order(min(psdev->aper->len, (u64)(1 << 30)));
 	num_aper_chunks = num_aper_pages >> (sg_page_shift - PAGE_SHIFT);
-	p2p->ppi_sg[SCIF_PPI_APER] = scif_p2p_setsg(psdev->aper->va,
+	p2p->ppi_sg[SCIF_PPI_APER] = scif_p2p_setsg(psdev->aper->pa,
 						    1 << sg_page_shift,
 						    num_aper_chunks);
 	p2p->sg_nentries[SCIF_PPI_APER] = num_aper_chunks;

drivers/mmc/card/block.c+2−0

@@ -208,6 +208,8 @@ static ssize_t power_ro_lock_show(struct device *dev, · 207 unmodified lines
208		208
209	ret = snprintf(buf, PAGE_SIZE, "%d\n", locked);	209	ret = snprintf(buf, PAGE_SIZE, "%d\n", locked);
210		210
		211	mmc_blk_put(md);
		212
211	return ret;	213	return ret;
212	}	214	}
213		215

drivers/mmc/host/Kconfig+1−0

@@ -779,6 +779,7 @@ config MMC_TOSHIBA_PCI · 778 unmodified lines
779		779
780	config MMC_MTK	780	config MMC_MTK
781	tristate "MediaTek SD/MMC Card Interface support"	781	tristate "MediaTek SD/MMC Card Interface support"
		782	depends on HAS_DMA
782	help	783	help
783	This selects the MediaTek(R) Secure digital and Multimedia card Interface.	784	This selects the MediaTek(R) Secure digital and Multimedia card Interface.
784	If you have a machine with a integrated SD/MMC card reader, say Y or M here.	785	If you have a machine with a integrated SD/MMC card reader, say Y or M here.

drivers/mmc/host/omap_hsmmc.c+6−5

 		if (status & (CTO_EN | CCRC_EN))
 			end_cmd = 1;
+		if (host->data || host->response_busy) {
+			end_trans = !end_cmd;
+			host->response_busy = 0;
+		}
 		if (status & (CTO_EN | DTO_EN))
 			hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
-		else if (status & (CCRC_EN | DCRC_EN))
+		else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN |
+				   BADA_EN))
 			hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
 		if (status & ACE_EN) {
 			}
 			dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
 		}
-		if (host->data || host->response_busy) {
-			end_trans = !end_cmd;
-			host->response_busy = 0;
-		}
 	}
 	OMAP_HSMMC_WRITE(host->base, STAT, status);

drivers/mmc/host/sdhci-esdhc-imx.c+104−106

@@ -581,13 +581,8 @@ static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) · 580 unmodified lines
581	static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)	581	static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
582	{	582	{
583	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);	583	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
584	struct pltfm_imx_data *imx_data = pltfm_host->priv;
585	struct esdhc_platform_data *boarddata = &imx_data->boarddata;
586		584
587	if (boarddata->f_max && (boarddata->f_max < pltfm_host->clock))	585	return pltfm_host->clock;
588	return boarddata->f_max;
589	else
590	return pltfm_host->clock;
591	}	586	}
592		587
593	static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)	588	static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
@@ -878,34 +873,19 @@ static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { · 284 unmodified lines
878	static int	873	static int
879	sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,	874	sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
880	struct sdhci_host *host,	875	struct sdhci_host *host,
881	struct esdhc_platform_data *boarddata)	876	struct pltfm_imx_data *imx_data)
882	{	877	{
883	struct device_node *np = pdev->dev.of_node;	878	struct device_node *np = pdev->dev.of_node;
884		879	struct esdhc_platform_data *boarddata = &imx_data->boarddata;
885	if (!np)	880	int ret;
886	return -ENODEV;
887
888	if (of_get_property(np, "non-removable", NULL))
889	boarddata->cd_type = ESDHC_CD_PERMANENT;
890
891	if (of_get_property(np, "fsl,cd-controller", NULL))
892	boarddata->cd_type = ESDHC_CD_CONTROLLER;
893		881
894	if (of_get_property(np, "fsl,wp-controller", NULL))	882	if (of_get_property(np, "fsl,wp-controller", NULL))
895	boarddata->wp_type = ESDHC_WP_CONTROLLER;	883	boarddata->wp_type = ESDHC_WP_CONTROLLER;
896		884
897	boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
898	if (gpio_is_valid(boarddata->cd_gpio))
899	boarddata->cd_type = ESDHC_CD_GPIO;
900
901	boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);	885	boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
902	if (gpio_is_valid(boarddata->wp_gpio))	886	if (gpio_is_valid(boarddata->wp_gpio))
903	boarddata->wp_type = ESDHC_WP_GPIO;	887	boarddata->wp_type = ESDHC_WP_GPIO;
904		888
905	of_property_read_u32(np, "bus-width", &boarddata->max_bus_width);
906
907	of_property_read_u32(np, "max-frequency", &boarddata->f_max);
908
909	if (of_find_property(np, "no-1-8-v", NULL))	889	if (of_find_property(np, "no-1-8-v", NULL))
910	boarddata->support_vsel = false;	890	boarddata->support_vsel = false;
911	else	891	else
@@ -916,29 +896,119 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, · 4 unmodified lines
916		896
917	mmc_of_parse_voltage(np, &host->ocr_mask);	897	mmc_of_parse_voltage(np, &host->ocr_mask);
918		898
		899	/* sdr50 and sdr104 needs work on 1.8v signal voltage */
		900	if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) &&
		901	!IS_ERR(imx_data->pins_default)) {
		902	imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
		903	ESDHC_PINCTRL_STATE_100MHZ);
		904	imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
		905	ESDHC_PINCTRL_STATE_200MHZ);
		906	if (IS_ERR(imx_data->pins_100mhz) \|\|
		907	IS_ERR(imx_data->pins_200mhz)) {
		908	dev_warn(mmc_dev(host->mmc),
		909	"could not get ultra high speed state, work on normal mode\n");
		910	/*
		911	* fall back to not support uhs by specify no 1.8v quirk
		912	*/
		913	host->quirks2 \|= SDHCI_QUIRK2_NO_1_8_V;
		914	}
		915	} else {
		916	host->quirks2 \|= SDHCI_QUIRK2_NO_1_8_V;
		917	}
		918
919	/* call to generic mmc_of_parse to support additional capabilities */	919	/* call to generic mmc_of_parse to support additional capabilities */
920	return mmc_of_parse(host->mmc);	920	ret = mmc_of_parse(host->mmc);
		921	if (ret)
		922	return ret;
		923
		924	if (!IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
		925	host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
		926
		927	return 0;
921	}	928	}
922	#else	929	#else
923	static inline int	930	static inline int
924	sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,	931	sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
925	struct sdhci_host *host,	932	struct sdhci_host *host,
926	struct esdhc_platform_data *boarddata)	933	struct pltfm_imx_data *imx_data)
927	{	934	{
928	return -ENODEV;	935	return -ENODEV;
929	}	936	}
930	#endif	937	#endif
931		938
		939	static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
		940	struct sdhci_host *host,
		941	struct pltfm_imx_data *imx_data)
		942	{
		943	struct esdhc_platform_data *boarddata = &imx_data->boarddata;
		944	int err;
		945
		946	if (!host->mmc->parent->platform_data) {
		947	dev_err(mmc_dev(host->mmc), "no board data!\n");
		948	return -EINVAL;
		949	}
		950
		951	imx_data->boarddata = ((struct esdhc_platform_data )
		952	host->mmc->parent->platform_data);
		953	/* write_protect */
		954	if (boarddata->wp_type == ESDHC_WP_GPIO) {
		955	err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
		956	if (err) {
		957	dev_err(mmc_dev(host->mmc),
		958	"failed to request write-protect gpio!\n");
		959	return err;
		960	}
		961	host->mmc->caps2 \|= MMC_CAP2_RO_ACTIVE_HIGH;
		962	}
		963
		964	/* card_detect */
		965	switch (boarddata->cd_type) {
		966	case ESDHC_CD_GPIO:
		967	err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
		968	if (err) {
		969	dev_err(mmc_dev(host->mmc),
		970	"failed to request card-detect gpio!\n");
		971	return err;
		972	}
		973	/* fall through */
		974
		975	case ESDHC_CD_CONTROLLER:
		976	/* we have a working card_detect back */
		977	host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
		978	break;
		979
		980	case ESDHC_CD_PERMANENT:
		981	host->mmc->caps \|= MMC_CAP_NONREMOVABLE;
		982	break;
		983
		984	case ESDHC_CD_NONE:
		985	break;
		986	}
		987
		988	switch (boarddata->max_bus_width) {
		989	case 8:
		990	host->mmc->caps \|= MMC_CAP_8_BIT_DATA \| MMC_CAP_4_BIT_DATA;
		991	break;
		992	case 4:
		993	host->mmc->caps \|= MMC_CAP_4_BIT_DATA;
		994	break;
		995	case 1:
		996	default:
		997	host->quirks \|= SDHCI_QUIRK_FORCE_1_BIT_DATA;
		998	break;
		999	}
		1000
		1001	return 0;
		1002	}
		1003
932	static int sdhci_esdhc_imx_probe(struct platform_device *pdev)	1004	static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
933	{	1005	{
934	const struct of_device_id *of_id =	1006	const struct of_device_id *of_id =
935	of_match_device(imx_esdhc_dt_ids, &pdev->dev);	1007	of_match_device(imx_esdhc_dt_ids, &pdev->dev);
936	struct sdhci_pltfm_host *pltfm_host;	1008	struct sdhci_pltfm_host *pltfm_host;
937	struct sdhci_host *host;	1009	struct sdhci_host *host;
938	struct esdhc_platform_data *boarddata;
939	int err;	1010	int err;
940	struct pltfm_imx_data *imx_data;	1011	struct pltfm_imx_data *imx_data;
941	bool dt = true;
942		1012
943	host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0);	1013	host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0);
944	if (IS_ERR(host))	1014	if (IS_ERR(host))
@@ -1030,84 +1100,12 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) · 85 unmodified lines
1030	if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)	1100	if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1031	host->quirks \|= SDHCI_QUIRK_BROKEN_ADMA;	1101	host->quirks \|= SDHCI_QUIRK_BROKEN_ADMA;
1032		1102
1033	boarddata = &imx_data->boarddata;	1103	if (of_id)
1034	if (sdhci_esdhc_imx_probe_dt(pdev, host, boarddata) < 0) {	1104	err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1035	if (!host->mmc->parent->platform_data) {	1105	else
1036	dev_err(mmc_dev(host->mmc), "no board data!\n");	1106	err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
1037	err = -EINVAL;	1107	if (err)
1038	goto disable_clk;	1108	goto disable_clk;
1039	}
1040	imx_data->boarddata = ((struct esdhc_platform_data )
1041	host->mmc->parent->platform_data);
1042	dt = false;
1043	}
1044	/* write_protect */
1045	if (boarddata->wp_type == ESDHC_WP_GPIO && !dt) {
1046	err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
1047	if (err) {
1048	dev_err(mmc_dev(host->mmc),
1049	"failed to request write-protect gpio!\n");
1050	goto disable_clk;
1051	}
1052	host->mmc->caps2 \|= MMC_CAP2_RO_ACTIVE_HIGH;
1053	}
1054
1055	/* card_detect */
1056	switch (boarddata->cd_type) {
1057	case ESDHC_CD_GPIO:
1058	if (dt)
1059	break;
1060	err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
1061	if (err) {
1062	dev_err(mmc_dev(host->mmc),
1063	"failed to request card-detect gpio!\n");
1064	goto disable_clk;
1065	}
1066	/* fall through */
1067
1068	case ESDHC_CD_CONTROLLER:
1069	/* we have a working card_detect back */
1070	host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1071	break;
1072
1073	case ESDHC_CD_PERMANENT:
1074	host->mmc->caps \|= MMC_CAP_NONREMOVABLE;
1075	break;
1076
1077	case ESDHC_CD_NONE:
1078	break;
1079	}
1080
1081	switch (boarddata->max_bus_width) {
1082	case 8:
1083	host->mmc->caps \|= MMC_CAP_8_BIT_DATA \| MMC_CAP_4_BIT_DATA;
1084	break;
1085	case 4:
1086	host->mmc->caps \|= MMC_CAP_4_BIT_DATA;
1087	break;
1088	case 1:
1089	default:
1090	host->quirks \|= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1091	break;
1092	}
1093
1094	/* sdr50 and sdr104 needs work on 1.8v signal voltage */
1095	if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) &&
1096	!IS_ERR(imx_data->pins_default)) {
1097	imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1098	ESDHC_PINCTRL_STATE_100MHZ);
1099	imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1100	ESDHC_PINCTRL_STATE_200MHZ);
1101	if (IS_ERR(imx_data->pins_100mhz) \|\|
1102	IS_ERR(imx_data->pins_200mhz)) {
1103	dev_warn(mmc_dev(host->mmc),
1104	"could not get ultra high speed state, work on normal mode\n");
1105	/* fall back to not support uhs by specify no 1.8v quirk */
1106	host->quirks2 \|= SDHCI_QUIRK2_NO_1_8_V;
1107	}
1108	} else {
1109	host->quirks2 \|= SDHCI_QUIRK2_NO_1_8_V;
1110	}
1111		1109
1112	err = sdhci_add_host(host);	1110	err = sdhci_add_host(host);
1113	if (err)	1111	if (err)

drivers/mmc/host/sdhci-esdhc.h+1−1

@@ -45,6 +45,6 @@ · 44 unmodified lines
45	#define ESDHC_DMA_SYSCTL 0x40c	45	#define ESDHC_DMA_SYSCTL 0x40c
46	#define ESDHC_DMA_SNOOP 0x00000040	46	#define ESDHC_DMA_SNOOP 0x00000040
47		47
48	#define ESDHC_HOST_CONTROL_RES 0x05	48	#define ESDHC_HOST_CONTROL_RES 0x01
49		49
50	#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */	50	#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */

drivers/mmc/host/sdhci-pxav3.c+1−0

@@ -411,6 +411,7 @@ static int sdhci_pxav3_probe(struct platform_device *pdev) · 410 unmodified lines
411	goto err_of_parse;	411	goto err_of_parse;
412	sdhci_get_of_property(pdev);	412	sdhci_get_of_property(pdev);
413	pdata = pxav3_get_mmc_pdata(dev);	413	pdata = pxav3_get_mmc_pdata(dev);
		414	pdev->dev.platform_data = pdata;
414	} else if (pdata) {	415	} else if (pdata) {
415	/* on-chip device */	416	/* on-chip device */
416	if (pdata->flags & PXA_FLAG_CARD_PERMANENT)	417	if (pdata->flags & PXA_FLAG_CARD_PERMANENT)

drivers/mmc/host/sdhci.c+12−4

 	u32 max_current_caps;
 	unsigned int ocr_avail;
 	unsigned int override_timeout_clk;
+	u32 max_clk;
 	int ret;
 	WARN_ON(host == NULL);
 						      GFP_KERNEL);
 		host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
 		if (!host->adma_table || !host->align_buffer) {
-			dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
+			if (host->adma_table)
-					  host->adma_table, host->adma_addr);
+				dma_free_coherent(mmc_dev(mmc),
+						  host->adma_table_sz,
+						  host->adma_table,
+						  host->adma_addr);
 			kfree(host->align_buffer);
 			pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
 				mmc_hostname(mmc));
 	 * Set host parameters.
 	 */
 	mmc->ops = &sdhci_ops;
-	mmc->f_max = host->max_clk;
+	max_clk = host->max_clk;
 	if (host->ops->get_min_clock)
 		mmc->f_min = host->ops->get_min_clock(host);
 	else if (host->version >= SDHCI_SPEC_300) {
 		if (host->clk_mul) {
 			mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
-			mmc->f_max = host->max_clk * host->clk_mul;
+			max_clk = host->max_clk * host->clk_mul;
 		} else
 			mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
 	} else
 		mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
+	if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
+		mmc->f_max = max_clk;
 	if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
 		host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
 					SDHCI_TIMEOUT_CLK_SHIFT;

drivers/net/bonding/bond_main.c+32−3

 	call_netdevice_notifiers(NETDEV_CHANGEADDR, bond_dev);
 }
+static struct slave *bond_get_old_active(struct bonding *bond,
+					 struct slave *new_active)
+{
+	struct slave *slave;
+	struct list_head *iter;
+	bond_for_each_slave(bond, slave, iter) {
+		if (slave == new_active)
+			continue;
+		if (ether_addr_equal(bond->dev->dev_addr, slave->dev->dev_addr))
+			return slave;
+	}
+	return NULL;
+}
 /* bond_do_fail_over_mac
  *
  * Perform special MAC address swapping for fail_over_mac settings
 		if (!new_active)
 			return;
+		if (!old_active)
+			old_active = bond_get_old_active(bond, new_active);
 		if (old_active) {
 			ether_addr_copy(tmp_mac, new_active->dev->dev_addr);
 			ether_addr_copy(saddr.sa_data,
 		   slave ? slave->dev->name : "NULL");
 	if (!slave || !bond->send_peer_notif ||
+	    !netif_carrier_ok(bond->dev) ||
 	    test_bit(__LINK_STATE_LINKWATCH_PENDING, &slave->dev->state))
 		return false;
 err_undo_flags:
 	/* Enslave of first slave has failed and we need to fix master's mac */
-	if (!bond_has_slaves(bond) &&
+	if (!bond_has_slaves(bond)) {
-	    ether_addr_equal_64bits(bond_dev->dev_addr, slave_dev->dev_addr))
+		if (ether_addr_equal_64bits(bond_dev->dev_addr,
-		eth_hw_addr_random(bond_dev);
+					    slave_dev->dev_addr))
+			eth_hw_addr_random(bond_dev);
+		if (bond_dev->type != ARPHRD_ETHER) {
+			ether_setup(bond_dev);
+			bond_dev->flags |= IFF_MASTER;
+			bond_dev->priv_flags &= ~IFF_TX_SKB_SHARING;
+		}
+	}
 	return res;
 }
 		bond_dev->priv_flags |= IFF_DISABLE_NETPOLL;
 		netdev_info(bond_dev, "Destroying bond %s\n",
 			    bond_dev->name);
+		bond_remove_proc_entry(bond);
 		unregister_netdevice(bond_dev);
 	}
 	return ret;

drivers/net/can/at91_can.c+4−4

 	cf->can_id |= CAN_ERR_CRTL;
 	cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
-	netif_receive_skb(skb);
 	stats->rx_packets++;
 	stats->rx_bytes += cf->can_dlc;
+	netif_receive_skb(skb);
 }
 /**
 	}
 	at91_read_mb(dev, mb, cf);
-	netif_receive_skb(skb);
 	stats->rx_packets++;
 	stats->rx_bytes += cf->can_dlc;
+	netif_receive_skb(skb);
 	can_led_event(dev, CAN_LED_EVENT_RX);
 }
 		return 0;
 	at91_poll_err_frame(dev, cf, reg_sr);
-	netif_receive_skb(skb);
 	dev->stats.rx_packets++;
 	dev->stats.rx_bytes += cf->can_dlc;
+	netif_receive_skb(skb);
 	return 1;
 }
 		return;
 	at91_irq_err_state(dev, cf, new_state);
-	netif_rx(skb);
 	dev->stats.rx_packets++;
 	dev->stats.rx_bytes += cf->can_dlc;
+	netif_rx(skb);
 	priv->can.state = new_state;
 }

drivers/net/can/bfin_can.c+2−4

 		cf->data[6 - i] = (6 - i) < cf->can_dlc ? (val >> 8) : 0;
 	}
-	netif_rx(skb);
 	stats->rx_packets++;
 	stats->rx_bytes += cf->can_dlc;
+	netif_rx(skb);
 }
 static int bfin_can_err(struct net_device *dev, u16 isrc, u16 status)
 	priv->can.state = state;
-	netif_rx(skb);
 	stats->rx_packets++;
 	stats->rx_bytes += cf->can_dlc;
+	netif_rx(skb);
 	return 0;
 }

drivers/net/can/cc770/cc770.c+2−2

 		for (i = 0; i < cf->can_dlc; i++)
 			cf->data[i] = cc770_read_reg(priv, msgobj[mo].data[i]);
 	}
-	netif_rx(skb);
 	stats->rx_packets++;
 	stats->rx_bytes += cf->can_dlc;
+	netif_rx(skb);
 }
 static int cc770_err(struct net_device *dev, u8 status)
 		}
 	}
-	netif_rx(skb);
 	stats->rx_packets++;
 	stats->rx_bytes += cf->can_dlc;
+	netif_rx(skb);
 	return 0;
 }

drivers/net/can/flexcan.c+3−4

 		return 0;
 	do_bus_err(dev, cf, reg_esr);
-	netif_receive_skb(skb);
 	dev->stats.rx_packets++;
 	dev->stats.rx_bytes += cf->can_dlc;
+	netif_receive_skb(skb);
 	return 1;
 }
 	if (unlikely(new_state == CAN_STATE_BUS_OFF))
 		can_bus_off(dev);
-	netif_receive_skb(skb);
 	dev->stats.rx_packets++;
 	dev->stats.rx_bytes += cf->can_dlc;
+	netif_receive_skb(skb);
 	return 1;
 }
 	}
 	flexcan_read_fifo(dev, cf);
-	netif_receive_skb(skb);
 	stats->rx_packets++;
 	stats->rx_bytes += cf->can_dlc;
+	netif_receive_skb(skb);
 	can_led_event(dev, CAN_LED_EVENT_RX);

drivers/net/can/grcan.c+2−1

 				cf->data[i] = (u8)(slot[j] >> shift);
 			}
 		}
-		netif_receive_skb(skb);
 		/* Update statistics and read pointer */
 		stats->rx_packets++;
 		stats->rx_bytes += cf->can_dlc;
+		netif_receive_skb(skb);
 		rd = grcan_ring_add(rd, GRCAN_MSG_SIZE, dma->rx.size);
 	}

drivers/net/can/sja1000/sja1000.c+2−4

 	/* release receive buffer */
 	sja1000_write_cmdreg(priv, CMD_RRB);
-	netif_rx(skb);
 	stats->rx_packets++;
 	stats->rx_bytes += cf->can_dlc;
+	netif_rx(skb);
 	can_led_event(dev, CAN_LED_EVENT_RX);
 }
 			can_bus_off(dev);
 	}
-	netif_rx(skb);
 	stats->rx_packets++;
 	stats->rx_bytes += cf->can_dlc;
+	netif_rx(skb);
 	return 0;
 }

drivers/net/can/slcan.c+1−1

 	memcpy(skb_put(skb, sizeof(struct can_frame)),
 	       &cf, sizeof(struct can_frame));
-	netif_rx_ni(skb);
 	sl->dev->stats.rx_packets++;
 	sl->dev->stats.rx_bytes += cf.can_dlc;
+	netif_rx_ni(skb);
 }
 /* parse tty input stream */

drivers/net/can/spi/mcp251x.c+8−9

 	if (ret)
 		goto out_clk;
-	priv->power = devm_regulator_get(&spi->dev, "vdd");
+	priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
-	priv->transceiver = devm_regulator_get(&spi->dev, "xceiver");
+	priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
 	if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
 	    (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
 		ret = -EPROBE_DEFER;
 	struct spi_device *spi = to_spi_device(dev);
 	struct mcp251x_priv *priv = spi_get_drvdata(spi);
-	if (priv->after_suspend & AFTER_SUSPEND_POWER) {
+	if (priv->after_suspend & AFTER_SUSPEND_POWER)
 		mcp251x_power_enable(priv->power, 1);
+	if (priv->after_suspend & AFTER_SUSPEND_UP) {
+		mcp251x_power_enable(priv->transceiver, 1);
 		queue_work(priv->wq, &priv->restart_work);
 	} else {
-		if (priv->after_suspend & AFTER_SUSPEND_UP) {
+		priv->after_suspend = 0;
-			mcp251x_power_enable(priv->transceiver, 1);
-			queue_work(priv->wq, &priv->restart_work);
-		} else {
-			priv->after_suspend = 0;
-		}
 	}
 	priv->force_quit = 0;
 	enable_irq(spi->irq);
 	return 0;

drivers/net/can/ti_hecc.c+1−1

 		}
 	}
-	netif_rx(skb);
 	stats->rx_packets++;
 	stats->rx_bytes += cf->can_dlc;
+	netif_rx(skb);
 	return 0;
 }

drivers/net/can/usb/ems_usb.c+2−4

 			cf->data[i] = msg->msg.can_msg.msg[i];
 	}
-	netif_rx(skb);
 	stats->rx_packets++;
 	stats->rx_bytes += cf->can_dlc;
+	netif_rx(skb);
 }
 static void ems_usb_rx_err(struct ems_usb *dev, struct ems_cpc_msg *msg)
 		stats->rx_errors++;
 	}
-	netif_rx(skb);
 	stats->rx_packets++;
 	stats->rx_bytes += cf->can_dlc;
+	netif_rx(skb);
 }
 /*

drivers/net/can/usb/esd_usb2.c+2−4

 			cf->data[7] = rxerr;
 		}
-		netif_rx(skb);
 		priv->bec.txerr = txerr;
 		priv->bec.rxerr = rxerr;
 		stats->rx_packets++;
 		stats->rx_bytes += cf->can_dlc;
+		netif_rx(skb);
 	}
 }
 				cf->data[i] = msg->msg.rx.data[i];
 		}
-		netif_rx(skb);
 		stats->rx_packets++;
 		stats->rx_bytes += cf->can_dlc;
+		netif_rx(skb);
 	}
 	return;

drivers/net/can/usb/peak_usb/pcan_usb.c+3−4

 		hwts->hwtstamp = timeval_to_ktime(tv);
 	}
-	netif_rx(skb);
 	mc->netdev->stats.rx_packets++;
 	mc->netdev->stats.rx_bytes += cf->can_dlc;
+	netif_rx(skb);
 	return 0;
 }
 	hwts = skb_hwtstamps(skb);
 	hwts->hwtstamp = timeval_to_ktime(tv);
-	/* push the skb */
-	netif_rx(skb);
 	/* update statistics */
 	mc->netdev->stats.rx_packets++;
 	mc->netdev->stats.rx_bytes += cf->can_dlc;
+	/* push the skb */
+	netif_rx(skb);
 	return 0;

drivers/net/can/usb/peak_usb/pcan_usb_pro.c+2−2

 	hwts = skb_hwtstamps(skb);
 	hwts->hwtstamp = timeval_to_ktime(tv);
-	netif_rx(skb);
 	netdev->stats.rx_packets++;
 	netdev->stats.rx_bytes += can_frame->can_dlc;
+	netif_rx(skb);
 	return 0;
 }
 	peak_usb_get_ts_tv(&usb_if->time_ref, le32_to_cpu(er->ts32), &tv);
 	hwts = skb_hwtstamps(skb);
 	hwts->hwtstamp = timeval_to_ktime(tv);
-	netif_rx(skb);
 	netdev->stats.rx_packets++;
 	netdev->stats.rx_bytes += can_frame->can_dlc;
+	netif_rx(skb);
 	return 0;
 }

drivers/net/can/usb/usb_8dev.c+2−4

 	priv->bec.txerr = txerr;
 	priv->bec.rxerr = rxerr;
-	netif_rx(skb);
 	stats->rx_packets++;
 	stats->rx_bytes += cf->can_dlc;
+	netif_rx(skb);
 }
 /* Read data and status frames */
 		else
 			memcpy(cf->data, msg->data, cf->can_dlc);
-		netif_rx(skb);
 		stats->rx_packets++;
 		stats->rx_bytes += cf->can_dlc;
+		netif_rx(skb);
 		can_led_event(priv->netdev, CAN_LED_EVENT_RX);
 	} else {

drivers/net/dsa/bcm_sf2.c+13−2

@@ -696,9 +696,20 @@ static int bcm_sf2_sw_setup(struct dsa_switch *ds) · 695 unmodified lines
696	}	696	}
697		697
698	/* Include the pseudo-PHY address and the broadcast PHY address to	698	/* Include the pseudo-PHY address and the broadcast PHY address to
699	* divert reads towards our workaround	699	* divert reads towards our workaround. This is only required for
		700	* 7445D0, since 7445E0 disconnects the internal switch pseudo-PHY such
		701	* that we can use the regular SWITCH_MDIO master controller instead.
		702	*
		703	* By default, DSA initializes ds->phys_mii_mask to ds->phys_port_mask
		704	* to have a 1:1 mapping between Port address and PHY address in order
		705	* to utilize the slave_mii_bus instance to read from Port PHYs. This is
		706	* not what we want here, so we initialize phys_mii_mask 0 to always
		707	* utilize the "master" MDIO bus backed by the "mdio-unimac" driver.
700	*/	708	*/
701	ds->phys_mii_mask \|= ((1 << BRCM_PSEUDO_PHY_ADDR) \| (1 << 0));	709	if (of_machine_is_compatible("brcm,bcm7445d0"))
		710	ds->phys_mii_mask \|= ((1 << BRCM_PSEUDO_PHY_ADDR) \| (1 << 0));
		711	else
		712	ds->phys_mii_mask = 0;
702		713
703	rev = reg_readl(priv, REG_SWITCH_REVISION);	714	rev = reg_readl(priv, REG_SWITCH_REVISION);
704	priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &	715	priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &

drivers/net/dsa/mv88e6xxx.c+1−1

@@ -1163,7 +1163,7 @@ int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask) · 1162 unmodified lines
1163		1163
1164	newfid = __ffs(ps->fid_mask);	1164	newfid = __ffs(ps->fid_mask);
1165	ps->fid[port] = newfid;	1165	ps->fid[port] = newfid;
1166	ps->fid_mask &= (1 << newfid);	1166	ps->fid_mask &= ~(1 << newfid);
1167	ps->bridge_mask[fid] &= ~(1 << port);	1167	ps->bridge_mask[fid] &= ~(1 << port);
1168	ps->bridge_mask[newfid] = 1 << port;	1168	ps->bridge_mask[newfid] = 1 << port;
1169		1169

drivers/net/ethernet/3com/3c59x.c+8−9

 			vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
 		}
 		if (i != RX_RING_SIZE) {
-			int j;
 			pr_emerg("%s: no memory for rx ring\n", dev->name);
-			for (j = 0; j < i; j++) {
-				if (vp->rx_skbuff[j]) {
-					dev_kfree_skb(vp->rx_skbuff[j]);
-					vp->rx_skbuff[j] = NULL;
-				}
-			}
 			retval = -ENOMEM;
-			goto err_free_irq;
+			goto err_free_skb;
 		}
 		/* Wrap the ring. */
 		vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
 	if (!retval)
 		goto out;
-err_free_irq:
+err_free_skb:
+	for (i = 0; i < RX_RING_SIZE; i++) {
+		if (vp->rx_skbuff[i]) {
+			dev_kfree_skb(vp->rx_skbuff[i]);
+			vp->rx_skbuff[i] = NULL;
+		}
+	}
 	free_irq(dev->irq, dev);
 err:
 	if (vortex_debug > 1)

drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c+1−1

 	if (likely(skb)) {
 		(*pkts_compl)++;
 		(*bytes_compl) += skb->len;
+		dev_kfree_skb_any(skb);
 	}
-	dev_kfree_skb_any(skb);
 	tx_buf->first_bd = 0;
 	tx_buf->skb = NULL;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c+16−0

@@ -1718,6 +1718,22 @@ static int bnx2x_nvram_write(struct bnx2x bp, u32 offset, u8 data_buf, · 1717 unmodified lines
1718	offset += sizeof(u32);	1718	offset += sizeof(u32);
1719	data_buf += sizeof(u32);	1719	data_buf += sizeof(u32);
1720	written_so_far += sizeof(u32);	1720	written_so_far += sizeof(u32);
		1721
		1722	/* At end of each 4Kb page, release nvram lock to allow MFW
		1723	* chance to take it for its own use.
		1724	*/
		1725	if ((cmd_flags & MCPR_NVM_COMMAND_LAST) &&
		1726	(written_so_far < buf_size)) {
		1727	DP(BNX2X_MSG_ETHTOOL \| BNX2X_MSG_NVM,
		1728	"Releasing NVM lock after offset 0x%x\n",
		1729	(u32)(offset - sizeof(u32)));
		1730	bnx2x_release_nvram_lock(bp);
		1731	usleep_range(1000, 2000);
		1732	rc = bnx2x_acquire_nvram_lock(bp);
		1733	if (rc)
		1734	return rc;
		1735	}
		1736
1721	cmd_flags = 0;	1737	cmd_flags = 0;
1722	}	1738	}
1723		1739

drivers/net/ethernet/brocade/bna/bnad.c+1−1

 			if (!next_cmpl->valid)
 				break;
 		}
+		packets++;
 		/* TODO: BNA_CQ_EF_LOCAL ? */
 		if (unlikely(flags & (BNA_CQ_EF_MAC_ERROR |
 		else
 			bnad_cq_setup_skb_frags(rcb, skb, sop_ci, nvecs, len);
-		packets++;
 		rcb->rxq->rx_packets++;
 		rcb->rxq->rx_bytes += totlen;
 		ccb->bytes_per_intr += totlen;

drivers/net/ethernet/cadence/macb.c+83−42

 	return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
 }
+/* I/O accessors */
+static u32 hw_readl_native(struct macb *bp, int offset)
+{
+	return __raw_readl(bp->regs + offset);
+}
+static void hw_writel_native(struct macb *bp, int offset, u32 value)
+{
+	__raw_writel(value, bp->regs + offset);
+}
+static u32 hw_readl(struct macb *bp, int offset)
+{
+	return readl_relaxed(bp->regs + offset);
+}
+static void hw_writel(struct macb *bp, int offset, u32 value)
+{
+	writel_relaxed(value, bp->regs + offset);
+}
+/*
+ * Find the CPU endianness by using the loopback bit of NCR register. When the
+ * CPU is in big endian we need to program swaped mode for management
+ * descriptor access.
+ */
+static bool hw_is_native_io(void __iomem *addr)
+{
+	u32 value = MACB_BIT(LLB);
+	__raw_writel(value, addr + MACB_NCR);
+	value = __raw_readl(addr + MACB_NCR);
+	/* Write 0 back to disable everything */
+	__raw_writel(0, addr + MACB_NCR);
+	return value == MACB_BIT(LLB);
+}
+static bool hw_is_gem(void __iomem *addr, bool native_io)
+{
+	u32 id;
+	if (native_io)
+		id = __raw_readl(addr + MACB_MID);
+	else
+		id = readl_relaxed(addr + MACB_MID);
+	return MACB_BFEXT(IDNUM, id) >= 0x2;
+}
 static void macb_set_hwaddr(struct macb *bp)
 {
 	u32 bottom;
 		}
 	}
-	netdev_info(bp->dev, "invalid hw address, using random\n");
+	dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
 	eth_hw_addr_random(bp->dev);
 }
 	struct macb *bp = netdev_priv(dev);
 	struct phy_device *phydev = bp->phy_dev;
 	unsigned long flags;
 	int status_change = 0;
 	spin_lock_irqsave(&bp->lock, flags);
 static void macb_update_stats(struct macb *bp)
 {
-	u32 __iomem *reg = bp->regs + MACB_PFR;
 	u32 *p = &bp->hw_stats.macb.rx_pause_frames;
 	u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
+	int offset = MACB_PFR;
 	WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
-	for(; p < end; p++, reg++)
+	for(; p < end; p++, offset += 4)
-		*p += readl_relaxed(reg);
+		*p += bp->macb_reg_readl(bp, offset);
 }
 static int macb_halt_tx(struct macb *bp)
 }
 #endif
-static inline unsigned int macb_count_tx_descriptors(struct macb *bp,
-						     unsigned int len)
-{
-	return (len + bp->max_tx_length - 1) / bp->max_tx_length;
-}
 static unsigned int macb_tx_map(struct macb *bp,
 				struct macb_queue *queue,
 				struct sk_buff *skb)
 	 * socket buffer: skb fragments of jumbo frames may need to be
 	 * splitted into many buffer descriptors.
 	 */
-	count = macb_count_tx_descriptors(bp, skb_headlen(skb));
+	count = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
 	nr_frags = skb_shinfo(skb)->nr_frags;
 	for (f = 0; f < nr_frags; f++) {
 		frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
-		count += macb_count_tx_descriptors(bp, frag_size);
+		count += DIV_ROUND_UP(frag_size, bp->max_tx_length);
 	}
 	spin_lock_irqsave(&bp->lock, flags);
 static void macb_configure_dma(struct macb *bp)
 {
 	u32 dmacfg;
-	u32 tmp, ncr;
 	if (macb_is_gem(bp)) {
 		dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
 		dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
 		dmacfg &= ~GEM_BIT(ENDIA_PKT);
-		/* Find the CPU endianness by using the loopback bit of net_ctrl
+		if (bp->native_io)
-		 * register. save it first. When the CPU is in big endian we
-		 * need to program swaped mode for management descriptor access.
-		 */
-		ncr = macb_readl(bp, NCR);
-		__raw_writel(MACB_BIT(LLB), bp->regs + MACB_NCR);
-		tmp =  __raw_readl(bp->regs + MACB_NCR);
-		if (tmp == MACB_BIT(LLB))
 			dmacfg &= ~GEM_BIT(ENDIA_DESC);
 		else
 			dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
-		/* Restore net_ctrl */
-		macb_writel(bp, NCR, ncr);
 		if (bp->dev->features & NETIF_F_HW_CSUM)
 			dmacfg |= GEM_BIT(TXCOEN);
 		else
 static void gem_update_stats(struct macb *bp)
 {
-	int i;
+	unsigned int i;
 	u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
 	for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
 		u32 offset = gem_statistics[i].offset;
-		u64 val = readl_relaxed(bp->regs + offset);
+		u64 val = bp->macb_reg_readl(bp, offset);
 		bp->ethtool_stats[i] += val;
 		*p += val;
 		if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
 			/* Add GEM_OCTTXH, GEM_OCTRXH */
-			val = readl_relaxed(bp->regs + offset + 4);
+			val = bp->macb_reg_readl(bp, offset + 4);
 			bp->ethtool_stats[i] += ((u64)val) << 32;
 			*(++p) += val;
 		}
 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
 {
-	int i;
+	unsigned int i;
 	switch (sset) {
 	case ETH_SS_STATS:
 	if (dt_conf)
 		bp->caps = dt_conf->caps;
-	if (macb_is_gem_hw(bp->regs)) {
+	if (hw_is_gem(bp->regs, bp->native_io)) {
 		bp->caps |= MACB_CAPS_MACB_IS_GEM;
 		dcfg = gem_readl(bp, DCFG1);
 			bp->caps |= MACB_CAPS_FIFO_MODE;
 	}
-	netdev_dbg(bp->dev, "Cadence caps 0x%08x\n", bp->caps);
+	dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
 }
 static void macb_probe_queues(void __iomem *mem,
+			      bool native_io,
 			      unsigned int *queue_mask,
 			      unsigned int *num_queues)
 {
 	 * we are early in the probe process and don't have the
 	 * MACB_CAPS_MACB_IS_GEM flag positioned
 	 */
-	if (!macb_is_gem_hw(mem))
+	if (!hw_is_gem(mem, native_io))
 		return;
 	/* bit 0 is never set but queue 0 always exists */
 	struct clk *pclk, *hclk, *tx_clk;
 	unsigned int queue_mask, num_queues;
 	struct macb_platform_data *pdata;
+	bool native_io;
 	struct phy_device *phydev;
 	struct net_device *dev;
 	struct resource *regs;
 	struct macb *bp;
 	int err;
+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	mem = devm_ioremap_resource(&pdev->dev, regs);
+	if (IS_ERR(mem))
+		return PTR_ERR(mem);
 	if (np) {
 		const struct of_device_id *match;
 	if (err)
 		return err;
-	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	native_io = hw_is_native_io(mem);
-	mem = devm_ioremap_resource(&pdev->dev, regs);
-	if (IS_ERR(mem)) {
-		err = PTR_ERR(mem);
-		goto err_disable_clocks;
-	}
-	macb_probe_queues(mem, &queue_mask, &num_queues);
+	macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
 	dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
 	if (!dev) {
 		err = -ENOMEM;
 	bp->pdev = pdev;
 	bp->dev = dev;
 	bp->regs = mem;
+	bp->native_io = native_io;
+	if (native_io) {
+		bp->macb_reg_readl = hw_readl_native;
+		bp->macb_reg_writel = hw_writel_native;
+	} else {
+		bp->macb_reg_readl = hw_readl;
+		bp->macb_reg_writel = hw_writel;
+	}
 	bp->num_queues = num_queues;
 	bp->queue_mask = queue_mask;
 	if (macb_config)
 	bp->pclk = pclk;
 	bp->hclk = hclk;
 	bp->tx_clk = tx_clk;
-	if (macb_config->jumbo_max_len) {
+	if (macb_config)
 		bp->jumbo_max_len = macb_config->jumbo_max_len;
-	}
 	spin_lock_init(&bp->lock);

drivers/net/ethernet/cadence/macb.h+14−20

 	 | GEM_BF(name, value))
 /* Register access macros */
-#define macb_readl(port,reg)				\
+#define macb_readl(port, reg)		(port)->macb_reg_readl((port), MACB_##reg)
-	readl_relaxed((port)->regs + MACB_##reg)
+#define macb_writel(port, reg, value)	(port)->macb_reg_writel((port), MACB_##reg, (value))
-#define macb_writel(port,reg,value)			\
+#define gem_readl(port, reg)		(port)->macb_reg_readl((port), GEM_##reg)
-	writel_relaxed((value), (port)->regs + MACB_##reg)
+#define gem_writel(port, reg, value)	(port)->macb_reg_writel((port), GEM_##reg, (value))
-#define gem_readl(port, reg)				\
+#define queue_readl(queue, reg)		(queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg)
-	readl_relaxed((port)->regs + GEM_##reg)
+#define queue_writel(queue, reg, value)	(queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value))
-#define gem_writel(port, reg, value)			\
-	writel_relaxed((value), (port)->regs + GEM_##reg)
-#define queue_readl(queue, reg)				\
-	readl_relaxed((queue)->bp->regs + (queue)->reg)
-#define queue_writel(queue, reg, value)			\
-	writel_relaxed((value), (queue)->bp->regs + (queue)->reg)
 /* Conditional GEM/MACB macros.  These perform the operation to the correct
  * register dependent on whether the device is a GEM or a MACB.  For registers
 struct macb {
 	void __iomem		*regs;
+	bool			native_io;
+	/* hardware IO accessors */
+	u32	(*macb_reg_readl)(struct macb *bp, int offset);
+	void	(*macb_reg_writel)(struct macb *bp, int offset, u32 value);
 	unsigned int		rx_tail;
 	unsigned int		rx_prepared_head;
 	struct mii_bus		*mii_bus;
 	struct phy_device	*phy_dev;
-	unsigned int 		link;
+	int 			link;
-	unsigned int 		speed;
+	int 			speed;
-	unsigned int 		duplex;
+	int 			duplex;
 	u32			caps;
 	unsigned int		dma_burst_length;
 	return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
 }
-static inline bool macb_is_gem_hw(void __iomem *addr)
-{
-	return !!(MACB_BFEXT(IDNUM, readl_relaxed(addr + MACB_MID)) >= 0x2);
-}
 #endif /* _MACB_H */

drivers/net/ethernet/cavium/Kconfig+0−3

 config THUNDER_NIC_PF
 	tristate "Thunder Physical function driver"
 	depends on 64BIT
-	default ARCH_THUNDER
 	select THUNDER_NIC_BGX
 	---help---
 	  This driver supports Thunder's NIC physical function.
 config THUNDER_NIC_VF
 	tristate "Thunder Virtual function driver"
 	depends on 64BIT
-	default ARCH_THUNDER
 	---help---
 	  This driver supports Thunder's NIC virtual function
 config	THUNDER_NIC_BGX
 	tristate "Thunder MAC interface driver (BGX)"
 	depends on 64BIT
-	default ARCH_THUNDER
 	---help---
 	  This driver supports programming and controlling of MAC
 	  interface from NIC physical function driver.

drivers/net/ethernet/cavium/thunder/nic.h+11−1

  */
 #define NICPF_CLK_PER_INT_TICK		2
+/* Time to wait before we decide that a SQ is stuck.
+ *
+ * Since both pkt rx and tx notifications are done with same CQ,
+ * when packets are being received at very high rate (eg: L2 forwarding)
+ * then freeing transmitted skbs will be delayed and watchdog
+ * will kick in, resetting interface. Hence keeping this value high.
+ */
+#define	NICVF_TX_TIMEOUT		(50 * HZ)
 struct nicvf_cq_poll {
 	u8	cq_idx;		/* Completion queue index */
 	struct	napi_struct napi;
 	/* Tx */
 	u64 tx_frames_ok;
 	u64 tx_drops;
-	u64 tx_busy;
 	u64 tx_tso;
+	u64 txq_stop;
+	u64 txq_wake;
 };
 struct nicvf {

drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c+16−10

 	NICVF_DRV_STAT(rx_frames_jumbo),
 	NICVF_DRV_STAT(rx_drops),
 	NICVF_DRV_STAT(tx_frames_ok),
-	NICVF_DRV_STAT(tx_busy),
 	NICVF_DRV_STAT(tx_tso),
 	NICVF_DRV_STAT(tx_drops),
+	NICVF_DRV_STAT(txq_stop),
+	NICVF_DRV_STAT(txq_wake),
 };
 static const struct nicvf_stat nicvf_queue_stats[] = {
 static void nicvf_get_strings(struct net_device *netdev, u32 sset, u8 *data)
 {
+	struct nicvf *nic = netdev_priv(netdev);
 	int stats, qidx;
 	if (sset != ETH_SS_STATS)
 		data += ETH_GSTRING_LEN;
 	}
-	for (qidx = 0; qidx < MAX_RCV_QUEUES_PER_QS; qidx++) {
+	for (qidx = 0; qidx < nic->qs->rq_cnt; qidx++) {
 		for (stats = 0; stats < nicvf_n_queue_stats; stats++) {
 			sprintf(data, "rxq%d: %s", qidx,
 				nicvf_queue_stats[stats].name);
 		}
 	}
-	for (qidx = 0; qidx < MAX_SND_QUEUES_PER_QS; qidx++) {
+	for (qidx = 0; qidx < nic->qs->sq_cnt; qidx++) {
 		for (stats = 0; stats < nicvf_n_queue_stats; stats++) {
 			sprintf(data, "txq%d: %s", qidx,
 				nicvf_queue_stats[stats].name);
 static int nicvf_get_sset_count(struct net_device *netdev, int sset)
 {
+	struct nicvf *nic = netdev_priv(netdev);
 	if (sset != ETH_SS_STATS)
 		return -EINVAL;
 	return nicvf_n_hw_stats + nicvf_n_drv_stats +
 		(nicvf_n_queue_stats *
-		 (MAX_RCV_QUEUES_PER_QS + MAX_SND_QUEUES_PER_QS)) +
+		 (nic->qs->rq_cnt + nic->qs->sq_cnt)) +
 		BGX_RX_STATS_COUNT + BGX_TX_STATS_COUNT;
 }
 		*(data++) = ((u64 *)&nic->drv_stats)
 				[nicvf_drv_stats[stat].index];
-	for (qidx = 0; qidx < MAX_RCV_QUEUES_PER_QS; qidx++) {
+	for (qidx = 0; qidx < nic->qs->rq_cnt; qidx++) {
 		for (stat = 0; stat < nicvf_n_queue_stats; stat++)
 			*(data++) = ((u64 *)&nic->qs->rq[qidx].stats)
 					[nicvf_queue_stats[stat].index];
 	}
-	for (qidx = 0; qidx < MAX_SND_QUEUES_PER_QS; qidx++) {
+	for (qidx = 0; qidx < nic->qs->sq_cnt; qidx++) {
 		for (stat = 0; stat < nicvf_n_queue_stats; stat++)
 			*(data++) = ((u64 *)&nic->qs->sq[qidx].stats)
 					[nicvf_queue_stats[stat].index];
 {
 	struct nicvf *nic = netdev_priv(dev);
 	int err = 0;
+	bool if_up = netif_running(dev);
 	if (!channel->rx_count || !channel->tx_count)
 		return -EINVAL;
 	if (channel->tx_count > MAX_SND_QUEUES_PER_QS)
 		return -EINVAL;
+	if (if_up)
+		nicvf_stop(dev);
 	nic->qs->rq_cnt = channel->rx_count;
 	nic->qs->sq_cnt = channel->tx_count;
 	nic->qs->cq_cnt = max(nic->qs->rq_cnt, nic->qs->sq_cnt);
 	if (err)
 		return err;
-	if (!netif_running(dev))
+	if (if_up)
-		return err;
+		nicvf_open(dev);
-	nicvf_stop(dev);
-	nicvf_open(dev);
 	netdev_info(dev, "Setting num Tx rings to %d, Rx rings to %d success\n",
 		    nic->qs->sq_cnt, nic->qs->rq_cnt);

drivers/net/ethernet/cavium/thunder/nicvf_main.c+39−16

 				    nic->duplex == DUPLEX_FULL ?
 				"Full duplex" : "Half duplex");
 			netif_carrier_on(nic->netdev);
-			netif_tx_wake_all_queues(nic->netdev);
+			netif_tx_start_all_queues(nic->netdev);
 		} else {
 			netdev_info(nic->netdev, "%s: Link is Down\n",
 				    nic->netdev->name);
 	if (skb) {
 		prefetch(skb);
 		dev_consume_skb_any(skb);
+		sq->skbuff[cqe_tx->sqe_ptr] = (u64)NULL;
 	}
 }
 static int nicvf_cq_intr_handler(struct net_device *netdev, u8 cq_idx,
 				 struct napi_struct *napi, int budget)
 {
-	int processed_cqe, work_done = 0;
+	int processed_cqe, work_done = 0, tx_done = 0;
 	int cqe_count, cqe_head;
 	struct nicvf *nic = netdev_priv(netdev);
 	struct queue_set *qs = nic->qs;
 	struct cmp_queue *cq = &qs->cq[cq_idx];
 	struct cqe_rx_t *cq_desc;
+	struct netdev_queue *txq;
 	spin_lock_bh(&cq->lock);
 loop:
 	cqe_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD, cq_idx) >> 9;
 	cqe_head &= 0xFFFF;
-	netdev_dbg(nic->netdev, "%s cqe_count %d cqe_head %d\n",
+	netdev_dbg(nic->netdev, "%s CQ%d cqe_count %d cqe_head %d\n",
-		   __func__, cqe_count, cqe_head);
+		   __func__, cq_idx, cqe_count, cqe_head);
 	while (processed_cqe < cqe_count) {
 		/* Get the CQ descriptor */
 		cq_desc = (struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head);
 			break;
 		}
-		netdev_dbg(nic->netdev, "cq_desc->cqe_type %d\n",
+		netdev_dbg(nic->netdev, "CQ%d cq_desc->cqe_type %d\n",
-			   cq_desc->cqe_type);
+			   cq_idx, cq_desc->cqe_type);
 		switch (cq_desc->cqe_type) {
 		case CQE_TYPE_RX:
 			nicvf_rcv_pkt_handler(netdev, napi, cq,
 		case CQE_TYPE_SEND:
 			nicvf_snd_pkt_handler(netdev, cq,
 					      (void *)cq_desc, CQE_TYPE_SEND);
+			tx_done++;
 		break;
 		case CQE_TYPE_INVALID:
 		case CQE_TYPE_RX_SPLIT:
 		}
 		processed_cqe++;
 	}
-	netdev_dbg(nic->netdev, "%s processed_cqe %d work_done %d budget %d\n",
+	netdev_dbg(nic->netdev,
-		   __func__, processed_cqe, work_done, budget);
+		   "%s CQ%d processed_cqe %d work_done %d budget %d\n",
+		   __func__, cq_idx, processed_cqe, work_done, budget);
 	/* Ring doorbell to inform H/W to reuse processed CQEs */
 	nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_DOOR,
 		goto loop;
 done:
+	/* Wakeup TXQ if its stopped earlier due to SQ full */
+	if (tx_done) {
+		txq = netdev_get_tx_queue(netdev, cq_idx);
+		if (netif_tx_queue_stopped(txq)) {
+			netif_tx_start_queue(txq);
+			nic->drv_stats.txq_wake++;
+			if (netif_msg_tx_err(nic))
+				netdev_warn(netdev,
+					    "%s: Transmit queue wakeup SQ%d\n",
+					    netdev->name, cq_idx);
+		}
+	}
 	spin_unlock_bh(&cq->lock);
 	return work_done;
 }
 	struct net_device *netdev = napi->dev;
 	struct nicvf *nic = netdev_priv(netdev);
 	struct nicvf_cq_poll *cq;
-	struct netdev_queue *txq;
 	cq = container_of(napi, struct nicvf_cq_poll, napi);
 	work_done = nicvf_cq_intr_handler(netdev, cq->cq_idx, napi, budget);
-	txq = netdev_get_tx_queue(netdev, cq->cq_idx);
-	if (netif_tx_queue_stopped(txq))
-		netif_tx_wake_queue(txq);
 	if (work_done < budget) {
 		/* Slow packet rate, exit polling */
 		napi_complete(napi);
 		return NETDEV_TX_OK;
 	}
-	if (!nicvf_sq_append_skb(nic, skb) && !netif_tx_queue_stopped(txq)) {
+	if (!netif_tx_queue_stopped(txq) && !nicvf_sq_append_skb(nic, skb)) {
 		netif_tx_stop_queue(txq);
-		nic->drv_stats.tx_busy++;
+		nic->drv_stats.txq_stop++;
 		if (netif_msg_tx_err(nic))
 			netdev_warn(netdev,
 				    "%s: Transmit ring full, stopping SQ%d\n",
 	nicvf_send_msg_to_pf(nic, &mbx);
 	netif_carrier_off(netdev);
-	netif_tx_disable(netdev);
 	/* Disable RBDR & QS error interrupts */
 	for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) {
 		kfree(cq_poll);
 	}
+	netif_tx_disable(netdev);
 	/* Free resources */
 	nicvf_config_data_transfer(nic, false);
 	for (qidx = 0; qidx < qs->rbdr_cnt; qidx++)
 		nicvf_enable_intr(nic, NICVF_INTR_RBDR, qidx);
+	nic->drv_stats.txq_stop = 0;
+	nic->drv_stats.txq_wake = 0;
 	netif_carrier_on(netdev);
 	netif_tx_start_all_queues(netdev);
 	netdev->hw_features = netdev->features;
 	netdev->netdev_ops = &nicvf_netdev_ops;
+	netdev->watchdog_timeo = NICVF_TX_TIMEOUT;
 	INIT_WORK(&nic->reset_task, nicvf_reset_task);
 	pci_disable_device(pdev);
 }
+static void nicvf_shutdown(struct pci_dev *pdev)
+{
+	nicvf_remove(pdev);
+}
 static struct pci_driver nicvf_driver = {
 	.name = DRV_NAME,
 	.id_table = nicvf_id_table,
 	.probe = nicvf_probe,
 	.remove = nicvf_remove,
+	.shutdown = nicvf_shutdown,
 };
 static int __init nicvf_init_module(void)

drivers/net/ethernet/cavium/thunder/nicvf_queues.c+11−6

 	/* Allocate a new page */
 	if (!nic->rb_page) {
-		nic->rb_page = alloc_pages(gfp | __GFP_COMP, order);
+		nic->rb_page = alloc_pages(gfp | __GFP_COMP | __GFP_NOWARN,
+					   order);
 		if (!nic->rb_page) {
-			netdev_err(nic->netdev, "Failed to allocate new rcv buffer\n");
+			netdev_err(nic->netdev,
+				   "Failed to allocate new rcv buffer\n");
 			return -ENOMEM;
 		}
 		nic->rb_page_offset = 0;
 		return;
 	if (sq->tso_hdrs)
-		dma_free_coherent(&nic->pdev->dev, sq->dmem.q_len,
+		dma_free_coherent(&nic->pdev->dev,
+				  sq->dmem.q_len * TSO_HEADER_SIZE,
 				  sq->tso_hdrs, sq->tso_hdrs_phys);
 	kfree(sq->skbuff);
 			continue;
 		}
 		skb = (struct sk_buff *)sq->skbuff[sq->head];
+		if (skb)
+			dev_kfree_skb_any(skb);
 		atomic64_add(1, (atomic64_t *)&netdev->stats.tx_packets);
 		atomic64_add(hdr->tot_len,
 			     (atomic64_t *)&netdev->stats.tx_bytes);
-		dev_kfree_skb_any(skb);
 		nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1);
 	}
 }
 	memset(gather, 0, SND_QUEUE_DESC_SIZE);
 	gather->subdesc_type = SQ_DESC_TYPE_GATHER;
-	gather->ld_type = NIC_SEND_LD_TYPE_E_LDWB;
+	gather->ld_type = NIC_SEND_LD_TYPE_E_LDD;
 	gather->size = size;
 	gather->addr = data;
 }
 		}
 		nicvf_sq_add_hdr_subdesc(sq, hdr_qentry,
 					 seg_subdescs - 1, skb, seg_len);
-		sq->skbuff[hdr_qentry] = 0;
+		sq->skbuff[hdr_qentry] = (u64)NULL;
 		qentry = nicvf_get_nxt_sqentry(sq, qentry);
 		desc_cnt += seg_subdescs;
 	/* Inform HW to xmit all TSO segments */
 	nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_DOOR,
 			      skb_get_queue_mapping(skb), desc_cnt);
+	nic->drv_stats.tx_tso++;
 	return 1;
 }

drivers/net/ethernet/cavium/thunder/nicvf_queues.h+11−3

 #define SND_QUEUE_CNT		8
 #define CMP_QUEUE_CNT		8 /* Max of RCV and SND qcount */
-#define SND_QSIZE		SND_QUEUE_SIZE4
+#define SND_QSIZE		SND_QUEUE_SIZE2
 #define SND_QUEUE_LEN		(1ULL << (SND_QSIZE + 10))
 #define MAX_SND_QUEUE_LEN	(1ULL << (SND_QUEUE_SIZE6 + 10))
 #define SND_QUEUE_THRESH	2ULL
 /* Since timestamp not enabled, otherwise 2 */
 #define MAX_CQE_PER_PKT_XMIT		1
-#define CMP_QSIZE		CMP_QUEUE_SIZE4
+/* Keep CQ and SQ sizes same, if timestamping
+ * is enabled this equation will change.
+ */
+#define CMP_QSIZE		CMP_QUEUE_SIZE2
 #define CMP_QUEUE_LEN		(1ULL << (CMP_QSIZE + 10))
 #define CMP_QUEUE_CQE_THRESH	0
 #define CMP_QUEUE_TIMER_THRESH	220 /* 10usec */
 #define MAX_CQES_FOR_TX		((SND_QUEUE_LEN / MIN_SQ_DESC_PER_PKT_XMIT) * \
 				 MAX_CQE_PER_PKT_XMIT)
-#define RQ_CQ_DROP		((CMP_QUEUE_LEN - MAX_CQES_FOR_TX) / 256)
+/* Calculate number of CQEs to reserve for all SQEs.
+ * Its 1/256th level of CQ size.
+ * '+ 1' to account for pipelining
+ */
+#define RQ_CQ_DROP		((256 / (CMP_QUEUE_LEN / \
+				 (CMP_QUEUE_LEN - MAX_CQES_FOR_TX))) + 1)
 /* Descriptor size in bytes */
 #define SND_QUEUE_DESC_SIZE	16

drivers/net/ethernet/cavium/thunder/thunder_bgx.c+4−1

 	bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cmrx_cfg);
 	bgx_flush_dmac_addrs(bgx, lmacid);
-	if (lmac->phydev)
+	if ((bgx->lmac_type != BGX_MODE_XFI) &&
+	    (bgx->lmac_type != BGX_MODE_XLAUI) &&
+	    (bgx->lmac_type != BGX_MODE_40G_KR) &&
+	    (bgx->lmac_type != BGX_MODE_10G_KR) && lmac->phydev)
 		phy_disconnect(lmac->phydev);
 	lmac->phydev = NULL;

drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c+2−1

 					EXT_MEM1_SIZE_G(size));
 		}
 	} else {
-		if (i & EXT_MEM_ENABLE_F)
+		if (i & EXT_MEM_ENABLE_F) {
 			size = t4_read_reg(adap, MA_EXT_MEMORY_BAR_A);
 			add_debugfs_mem(adap, "mc", MEM_MC,
 					EXT_MEM_SIZE_G(size));
+		}
 	}
 	de = debugfs_create_file_size("flash", S_IRUSR, adap->debugfs_root, adap,

drivers/net/ethernet/emulex/benet/be_cmds.h+5−0

 					 BE_IF_FLAGS_VLAN_PROMISCUOUS |\
 					 BE_IF_FLAGS_MCAST_PROMISCUOUS)
+#define BE_IF_EN_FLAGS	(BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_PASS_L3L4_ERRORS |\
+			BE_IF_FLAGS_MULTICAST | BE_IF_FLAGS_UNTAGGED)
+#define BE_IF_ALL_FILT_FLAGS	(BE_IF_EN_FLAGS | BE_IF_FLAGS_ALL_PROMISCUOUS)
 /* An RX interface is an object with one or more MAC addresses and
  * filtering capabilities. */
 struct be_cmd_req_if_create {

drivers/net/ethernet/emulex/benet/be_main.c+120−67

@@ -273,6 +273,10 @@ static int be_mac_addr_set(struct net_device netdev, void p) · 272 unmodified lines
273	if (ether_addr_equal(addr->sa_data, netdev->dev_addr))	273	if (ether_addr_equal(addr->sa_data, netdev->dev_addr))
274	return 0;	274	return 0;
275		275
		276	/* if device is not running, copy MAC to netdev->dev_addr */
		277	if (!netif_running(netdev))
		278	goto done;
		279
276	/* The PMAC_ADD cmd may fail if the VF doesn't have FILTMGMT	280	/* The PMAC_ADD cmd may fail if the VF doesn't have FILTMGMT
277	* privilege or if PF did not provision the new MAC address.	281	* privilege or if PF did not provision the new MAC address.
278	* On BE3, this cmd will always fail if the VF doesn't have the	282	* On BE3, this cmd will always fail if the VF doesn't have the
@@ -307,9 +311,9 @@ static int be_mac_addr_set(struct net_device netdev, void p) · 28 unmodified lines
307	status = -EPERM;	311	status = -EPERM;
308	goto err;	312	goto err;
309	}	313	}
310		314	done:
311	memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);	315	ether_addr_copy(netdev->dev_addr, addr->sa_data);
312	dev_info(dev, "MAC address changed to %pM\n", mac);	316	dev_info(dev, "MAC address changed to %pM\n", addr->sa_data);
313	return 0;	317	return 0;
314	err:	318	err:
315	dev_warn(dev, "MAC address change to %pM failed\n", addr->sa_data);	319	dev_warn(dev, "MAC address change to %pM failed\n", addr->sa_data);
@@ -2447,10 +2451,24 @@ static void be_eq_clean(struct be_eq_obj *eqo) · 2131 unmodified lines
2447	be_eq_notify(eqo->adapter, eqo->q.id, false, true, num, 0);	2451	be_eq_notify(eqo->adapter, eqo->q.id, false, true, num, 0);
2448	}	2452	}
2449		2453
2450	static void be_rx_cq_clean(struct be_rx_obj *rxo)	2454	/* Free posted rx buffers that were not used */
		2455	static void be_rxq_clean(struct be_rx_obj *rxo)
2451	{	2456	{
2452	struct be_rx_page_info *page_info;
2453	struct be_queue_info *rxq = &rxo->q;	2457	struct be_queue_info *rxq = &rxo->q;
		2458	struct be_rx_page_info *page_info;
		2459
		2460	while (atomic_read(&rxq->used) > 0) {
		2461	page_info = get_rx_page_info(rxo);
		2462	put_page(page_info->page);
		2463	memset(page_info, 0, sizeof(*page_info));
		2464	}
		2465	BUG_ON(atomic_read(&rxq->used));
		2466	rxq->tail = 0;
		2467	rxq->head = 0;
		2468	}
		2469
		2470	static void be_rx_cq_clean(struct be_rx_obj *rxo)
		2471	{
2454	struct be_queue_info *rx_cq = &rxo->cq;	2472	struct be_queue_info *rx_cq = &rxo->cq;
2455	struct be_rx_compl_info *rxcp;	2473	struct be_rx_compl_info *rxcp;
2456	struct be_adapter *adapter = rxo->adapter;	2474	struct be_adapter *adapter = rxo->adapter;
@@ -2487,16 +2505,6 @@ static void be_rx_cq_clean(struct be_rx_obj *rxo) · 30 unmodified lines
2487		2505
2488	/* After cleanup, leave the CQ in unarmed state */	2506	/* After cleanup, leave the CQ in unarmed state */
2489	be_cq_notify(adapter, rx_cq->id, false, 0);	2507	be_cq_notify(adapter, rx_cq->id, false, 0);
2490
2491	/* Then free posted rx buffers that were not used */
2492	while (atomic_read(&rxq->used) > 0) {
2493	page_info = get_rx_page_info(rxo);
2494	put_page(page_info->page);
2495	memset(page_info, 0, sizeof(*page_info));
2496	}
2497	BUG_ON(atomic_read(&rxq->used));
2498	rxq->tail = 0;
2499	rxq->head = 0;
2500	}	2508	}
2501		2509
2502	static void be_tx_compl_clean(struct be_adapter *adapter)	2510	static void be_tx_compl_clean(struct be_adapter *adapter)
@@ -2576,8 +2584,8 @@ static void be_evt_queues_destroy(struct be_adapter *adapter) · 73 unmodified lines
2576	be_cmd_q_destroy(adapter, &eqo->q, QTYPE_EQ);	2584	be_cmd_q_destroy(adapter, &eqo->q, QTYPE_EQ);
2577	napi_hash_del(&eqo->napi);	2585	napi_hash_del(&eqo->napi);
2578	netif_napi_del(&eqo->napi);	2586	netif_napi_del(&eqo->napi);
		2587	free_cpumask_var(eqo->affinity_mask);
2579	}	2588	}
2580	free_cpumask_var(eqo->affinity_mask);
2581	be_queue_free(adapter, &eqo->q);	2589	be_queue_free(adapter, &eqo->q);
2582	}	2590	}
2583	}	2591	}
@@ -2594,13 +2602,7 @@ static int be_evt_queues_create(struct be_adapter *adapter) · 10 unmodified lines
2594		2602
2595	for_all_evt_queues(adapter, eqo, i) {	2603	for_all_evt_queues(adapter, eqo, i) {
2596	int numa_node = dev_to_node(&adapter->pdev->dev);	2604	int numa_node = dev_to_node(&adapter->pdev->dev);
2597	if (!zalloc_cpumask_var(&eqo->affinity_mask, GFP_KERNEL))	2605
2598	return -ENOMEM;
2599	cpumask_set_cpu(cpumask_local_spread(i, numa_node),
2600	eqo->affinity_mask);
2601	netif_napi_add(adapter->netdev, &eqo->napi, be_poll,
2602	BE_NAPI_WEIGHT);
2603	napi_hash_add(&eqo->napi);
2604	aic = &adapter->aic_obj[i];	2606	aic = &adapter->aic_obj[i];
2605	eqo->adapter = adapter;	2607	eqo->adapter = adapter;
2606	eqo->idx = i;	2608	eqo->idx = i;
@@ -2616,6 +2618,14 @@ static int be_evt_queues_create(struct be_adapter *adapter) · 9 unmodified lines
2616	rc = be_cmd_eq_create(adapter, eqo);	2618	rc = be_cmd_eq_create(adapter, eqo);
2617	if (rc)	2619	if (rc)
2618	return rc;	2620	return rc;
		2621
		2622	if (!zalloc_cpumask_var(&eqo->affinity_mask, GFP_KERNEL))
		2623	return -ENOMEM;
		2624	cpumask_set_cpu(cpumask_local_spread(i, numa_node),
		2625	eqo->affinity_mask);
		2626	netif_napi_add(adapter->netdev, &eqo->napi, be_poll,
		2627	BE_NAPI_WEIGHT);
		2628	napi_hash_add(&eqo->napi);
2619	}	2629	}
2620	return 0;	2630	return 0;
2621	}	2631	}
@@ -3354,13 +3364,54 @@ static void be_rx_qs_destroy(struct be_adapter *adapter) · 732 unmodified lines
3354	for_all_rx_queues(adapter, rxo, i) {	3364	for_all_rx_queues(adapter, rxo, i) {
3355	q = &rxo->q;	3365	q = &rxo->q;
3356	if (q->created) {	3366	if (q->created) {
		3367	/* If RXQs are destroyed while in an "out of buffer"
		3368	* state, there is a possibility of an HW stall on
		3369	* Lancer. So, post 64 buffers to each queue to relieve
		3370	* the "out of buffer" condition.
		3371	* Make sure there's space in the RXQ before posting.
		3372	*/
		3373	if (lancer_chip(adapter)) {
		3374	be_rx_cq_clean(rxo);
		3375	if (atomic_read(&q->used) == 0)
		3376	be_post_rx_frags(rxo, GFP_KERNEL,
		3377	MAX_RX_POST);
		3378	}
		3379
3357	be_cmd_rxq_destroy(adapter, q);	3380	be_cmd_rxq_destroy(adapter, q);
3358	be_rx_cq_clean(rxo);	3381	be_rx_cq_clean(rxo);
		3382	be_rxq_clean(rxo);
3359	}	3383	}
3360	be_queue_free(adapter, q);	3384	be_queue_free(adapter, q);
3361	}	3385	}
3362	}	3386	}
3363		3387
		3388	static void be_disable_if_filters(struct be_adapter *adapter)
		3389	{
		3390	be_cmd_pmac_del(adapter, adapter->if_handle,
		3391	adapter->pmac_id[0], 0);
		3392
		3393	be_clear_uc_list(adapter);
		3394
		3395	/* The IFACE flags are enabled in the open path and cleared
		3396	* in the close path. When a VF gets detached from the host and
		3397	* assigned to a VM the following happens:
		3398	* - VF's IFACE flags get cleared in the detach path
		3399	* - IFACE create is issued by the VF in the attach path
		3400	* Due to a bug in the BE3/Skyhawk-R FW
		3401	* (Lancer FW doesn't have the bug), the IFACE capability flags
		3402	* specified along with the IFACE create cmd issued by a VF are not
		3403	* honoured by FW. As a consequence, if a new driver
		3404	* (that enables/disables IFACE flags in open/close)
		3405	* is loaded in the host and an old driver is * used by a VM/VF,
		3406	* the IFACE gets created without the needed flags.
		3407	* To avoid this, disable RX-filter flags only for Lancer.
		3408	*/
		3409	if (lancer_chip(adapter)) {
		3410	be_cmd_rx_filter(adapter, BE_IF_ALL_FILT_FLAGS, OFF);
		3411	adapter->if_flags &= ~BE_IF_ALL_FILT_FLAGS;
		3412	}
		3413	}
		3414
3364	static int be_close(struct net_device *netdev)	3415	static int be_close(struct net_device *netdev)
3365	{	3416	{
3366	struct be_adapter *adapter = netdev_priv(netdev);	3417	struct be_adapter *adapter = netdev_priv(netdev);
@@ -3373,6 +3424,8 @@ static int be_close(struct net_device *netdev) · 6 unmodified lines
3373	if (!(adapter->flags & BE_FLAGS_SETUP_DONE))	3424	if (!(adapter->flags & BE_FLAGS_SETUP_DONE))
3374	return 0;	3425	return 0;
3375		3426
		3427	be_disable_if_filters(adapter);
		3428
3376	be_roce_dev_close(adapter);	3429	be_roce_dev_close(adapter);
3377		3430
3378	if (adapter->flags & BE_FLAGS_NAPI_ENABLED) {	3431	if (adapter->flags & BE_FLAGS_NAPI_ENABLED) {
@@ -3392,7 +3445,6 @@ static int be_close(struct net_device *netdev) · 13 unmodified lines
3392	be_tx_compl_clean(adapter);	3445	be_tx_compl_clean(adapter);
3393		3446
3394	be_rx_qs_destroy(adapter);	3447	be_rx_qs_destroy(adapter);
3395	be_clear_uc_list(adapter);
3396		3448
3397	for_all_evt_queues(adapter, eqo, i) {	3449	for_all_evt_queues(adapter, eqo, i) {
3398	if (msix_enabled(adapter))	3450	if (msix_enabled(adapter))
@@ -3477,6 +3529,31 @@ static int be_rx_qs_create(struct be_adapter *adapter) · 78 unmodified lines
3477	return 0;	3529	return 0;
3478	}	3530	}
3479		3531
		3532	static int be_enable_if_filters(struct be_adapter *adapter)
		3533	{
		3534	int status;
		3535
		3536	status = be_cmd_rx_filter(adapter, BE_IF_EN_FLAGS, ON);
		3537	if (status)
		3538	return status;
		3539
		3540	/* For BE3 VFs, the PF programs the initial MAC address */
		3541	if (!(BEx_chip(adapter) && be_virtfn(adapter))) {
		3542	status = be_cmd_pmac_add(adapter, adapter->netdev->dev_addr,
		3543	adapter->if_handle,
		3544	&adapter->pmac_id[0], 0);
		3545	if (status)
		3546	return status;
		3547	}
		3548
		3549	if (adapter->vlans_added)
		3550	be_vid_config(adapter);
		3551
		3552	be_set_rx_mode(adapter->netdev);
		3553
		3554	return 0;
		3555	}
		3556
3480	static int be_open(struct net_device *netdev)	3557	static int be_open(struct net_device *netdev)
3481	{	3558	{
3482	struct be_adapter *adapter = netdev_priv(netdev);	3559	struct be_adapter *adapter = netdev_priv(netdev);
@@ -3490,6 +3567,10 @@ static int be_open(struct net_device *netdev) · 7 unmodified lines
3490	if (status)	3567	if (status)
3491	goto err;	3568	goto err;
3492		3569
		3570	status = be_enable_if_filters(adapter);
		3571	if (status)
		3572	goto err;
		3573
3493	status = be_irq_register(adapter);	3574	status = be_irq_register(adapter);
3494	if (status)	3575	if (status)
3495	goto err;	3576	goto err;
@@ -3686,16 +3767,6 @@ static void be_cancel_err_detection(struct be_adapter *adapter) · 190 unmodified lines
3686	}	3767	}
3687	}	3768	}
3688		3769
3689	static void be_mac_clear(struct be_adapter *adapter)
3690	{
3691	if (adapter->pmac_id) {
3692	be_cmd_pmac_del(adapter, adapter->if_handle,
3693	adapter->pmac_id[0], 0);
3694	kfree(adapter->pmac_id);
3695	adapter->pmac_id = NULL;
3696	}
3697	}
3698
3699	#ifdef CONFIG_BE2NET_VXLAN	3770	#ifdef CONFIG_BE2NET_VXLAN
3700	static void be_disable_vxlan_offloads(struct be_adapter *adapter)	3771	static void be_disable_vxlan_offloads(struct be_adapter *adapter)
3701	{	3772	{
@@ -3770,8 +3841,8 @@ static int be_clear(struct be_adapter *adapter) · 68 unmodified lines
3770	#ifdef CONFIG_BE2NET_VXLAN	3841	#ifdef CONFIG_BE2NET_VXLAN
3771	be_disable_vxlan_offloads(adapter);	3842	be_disable_vxlan_offloads(adapter);
3772	#endif	3843	#endif
3773	/* delete the primary mac along with the uc-mac list */	3844	kfree(adapter->pmac_id);
3774	be_mac_clear(adapter);	3845	adapter->pmac_id = NULL;
3775		3846
3776	be_cmd_if_destroy(adapter, adapter->if_handle, 0);	3847	be_cmd_if_destroy(adapter, adapter->if_handle, 0);
3777		3848
@@ -3782,25 +3853,11 @@ static int be_clear(struct be_adapter *adapter) · 4 unmodified lines
3782	return 0;	3853	return 0;
3783	}	3854	}
3784		3855
3785	static int be_if_create(struct be_adapter adapter, u32 if_handle,
3786	u32 cap_flags, u32 vf)
3787	{
3788	u32 en_flags;
3789
3790	en_flags = BE_IF_FLAGS_UNTAGGED \| BE_IF_FLAGS_BROADCAST \|
3791	BE_IF_FLAGS_MULTICAST \| BE_IF_FLAGS_PASS_L3L4_ERRORS \|
3792	BE_IF_FLAGS_RSS \| BE_IF_FLAGS_DEFQ_RSS;
3793
3794	en_flags &= cap_flags;
3795
3796	return be_cmd_if_create(adapter, cap_flags, en_flags, if_handle, vf);
3797	}
3798
3799	static int be_vfs_if_create(struct be_adapter *adapter)	3856	static int be_vfs_if_create(struct be_adapter *adapter)
3800	{	3857	{
3801	struct be_resources res = {0};	3858	struct be_resources res = {0};
		3859	u32 cap_flags, en_flags, vf;
3802	struct be_vf_cfg *vf_cfg;	3860	struct be_vf_cfg *vf_cfg;
3803	u32 cap_flags, vf;
3804	int status;	3861	int status;
3805		3862
3806	/* If a FW profile exists, then cap_flags are updated */	3863	/* If a FW profile exists, then cap_flags are updated */
@@ -3821,8 +3878,12 @@ static int be_vfs_if_create(struct be_adapter *adapter) · 14 unmodified lines
3821	}	3878	}
3822	}	3879	}
3823		3880
3824	status = be_if_create(adapter, &vf_cfg->if_handle,	3881	en_flags = cap_flags & (BE_IF_FLAGS_UNTAGGED \|
3825	cap_flags, vf + 1);	3882	BE_IF_FLAGS_BROADCAST \|
		3883	BE_IF_FLAGS_MULTICAST \|
		3884	BE_IF_FLAGS_PASS_L3L4_ERRORS);
		3885	status = be_cmd_if_create(adapter, cap_flags, en_flags,
		3886	&vf_cfg->if_handle, vf + 1);
3826	if (status)	3887	if (status)
3827	return status;	3888	return status;
3828	}	3889	}
@@ -4194,15 +4255,8 @@ static int be_mac_setup(struct be_adapter *adapter) · 365 unmodified lines
4194		4255
4195	memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);	4256	memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
4196	memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);	4257	memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
4197	} else {
4198	/* Maybe the HW was reset; dev_addr must be re-programmed */
4199	memcpy(mac, adapter->netdev->dev_addr, ETH_ALEN);
4200	}	4258	}
4201		4259
4202	/* For BE3-R VFs, the PF programs the initial MAC address */
4203	if (!(BEx_chip(adapter) && be_virtfn(adapter)))
4204	be_cmd_pmac_add(adapter, mac, adapter->if_handle,
4205	&adapter->pmac_id[0], 0);
4206	return 0;	4260	return 0;
4207	}	4261	}
4208		4262
@@ -4342,6 +4396,7 @@ static int be_func_init(struct be_adapter *adapter) · 133 unmodified lines
4342	static int be_setup(struct be_adapter *adapter)	4396	static int be_setup(struct be_adapter *adapter)
4343	{	4397	{
4344	struct device *dev = &adapter->pdev->dev;	4398	struct device *dev = &adapter->pdev->dev;
		4399	u32 en_flags;
4345	int status;	4400	int status;
4346		4401
4347	status = be_func_init(adapter);	4402	status = be_func_init(adapter);
@@ -4364,8 +4419,11 @@ static int be_setup(struct be_adapter *adapter) · 16 unmodified lines
4364	if (status)	4419	if (status)
4365	goto err;	4420	goto err;
4366		4421
4367	status = be_if_create(adapter, &adapter->if_handle,	4422	/* will enable all the needed filter flags in be_open() */
4368	be_if_cap_flags(adapter), 0);	4423	en_flags = BE_IF_FLAGS_RSS \| BE_IF_FLAGS_DEFQ_RSS;
		4424	en_flags = en_flags & be_if_cap_flags(adapter);
		4425	status = be_cmd_if_create(adapter, be_if_cap_flags(adapter), en_flags,
		4426	&adapter->if_handle, 0);
4369	if (status)	4427	if (status)
4370	goto err;	4428	goto err;
4371		4429
@@ -4391,11 +4449,6 @@ static int be_setup(struct be_adapter *adapter) · 19 unmodified lines
4391	dev_err(dev, "Please upgrade firmware to version >= 4.0\n");	4449	dev_err(dev, "Please upgrade firmware to version >= 4.0\n");
4392	}	4450	}
4393		4451
4394	if (adapter->vlans_added)
4395	be_vid_config(adapter);
4396
4397	be_set_rx_mode(adapter->netdev);
4398
4399	status = be_cmd_set_flow_control(adapter, adapter->tx_fc,	4452	status = be_cmd_set_flow_control(adapter, adapter->tx_fc,
4400	adapter->rx_fc);	4453	adapter->rx_fc);
4401	if (status)	4454	if (status)

drivers/net/ethernet/freescale/fec.h+1−0

@@ -562,6 +562,7 @@ struct fec_enet_private { · 561 unmodified lines
562	};	562	};
563		563
564	void fec_ptp_init(struct platform_device *pdev);	564	void fec_ptp_init(struct platform_device *pdev);
		565	void fec_ptp_stop(struct platform_device *pdev);
565	void fec_ptp_start_cyclecounter(struct net_device *ndev);	566	void fec_ptp_start_cyclecounter(struct net_device *ndev);
566	int fec_ptp_set(struct net_device ndev, struct ifreq ifr);	567	int fec_ptp_set(struct net_device ndev, struct ifreq ifr);
567	int fec_ptp_get(struct net_device ndev, struct ifreq ifr);	568	int fec_ptp_get(struct net_device ndev, struct ifreq ifr);

drivers/net/ethernet/freescale/fec_main.c+10−9

 			fep->bufdesc_size;
 	/* Allocate memory for buffer descriptors. */
-	cbd_base = dma_alloc_coherent(NULL, bd_size, &bd_dma,
+	cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
-				      GFP_KERNEL);
+				       GFP_KERNEL);
 	if (!cbd_base) {
 		return -ENOMEM;
 	}
 		fep->reg_phy = NULL;
 	}
+	pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
+	pm_runtime_use_autosuspend(&pdev->dev);
+	pm_runtime_get_noresume(&pdev->dev);
+	pm_runtime_set_active(&pdev->dev);
+	pm_runtime_enable(&pdev->dev);
 	fec_reset_phy(pdev);
 	if (fep->bufdesc_ex)
 	netif_carrier_off(ndev);
 	fec_enet_clk_enable(ndev, false);
 	pinctrl_pm_select_sleep_state(&pdev->dev);
-	pm_runtime_set_active(&pdev->dev);
-	pm_runtime_enable(&pdev->dev);
 	ret = register_netdev(ndev);
 	if (ret)
 	fep->rx_copybreak = COPYBREAK_DEFAULT;
 	INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
-	pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
-	pm_runtime_use_autosuspend(&pdev->dev);
 	pm_runtime_mark_last_busy(&pdev->dev);
 	pm_runtime_put_autosuspend(&pdev->dev);
 failed_mii_init:
 failed_irq:
 failed_init:
+	fec_ptp_stop(pdev);
 	if (fep->reg_phy)
 		regulator_disable(fep->reg_phy);
 failed_regulator:
 	struct net_device *ndev = platform_get_drvdata(pdev);
 	struct fec_enet_private *fep = netdev_priv(ndev);
-	cancel_delayed_work_sync(&fep->time_keep);
 	cancel_work_sync(&fep->tx_timeout_work);
+	fec_ptp_stop(pdev);
 	unregister_netdev(ndev);
 	fec_enet_mii_remove(fep);
 	if (fep->reg_phy)
 		regulator_disable(fep->reg_phy);
-	if (fep->ptp_clock)
-		ptp_clock_unregister(fep->ptp_clock);
 	of_node_put(fep->phy_node);
 	free_netdev(ndev);

drivers/net/ethernet/freescale/fec_ptp.c+10−0

@@ -604,6 +604,16 @@ void fec_ptp_init(struct platform_device *pdev) · 603 unmodified lines
604	schedule_delayed_work(&fep->time_keep, HZ);	604	schedule_delayed_work(&fep->time_keep, HZ);
605	}	605	}
606		606
		607	void fec_ptp_stop(struct platform_device *pdev)
		608	{
		609	struct net_device *ndev = platform_get_drvdata(pdev);
		610	struct fec_enet_private *fep = netdev_priv(ndev);
		611
		612	cancel_delayed_work_sync(&fep->time_keep);
		613	if (fep->ptp_clock)
		614	ptp_clock_unregister(fep->ptp_clock);
		615	}
		616
607	/**	617	/**
608	* fec_ptp_check_pps_event	618	* fec_ptp_check_pps_event
609	* @fep: the fec_enet_private structure handle	619	* @fep: the fec_enet_private structure handle

drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c+2−1

@@ -586,7 +586,8 @@ static int fs_enet_start_xmit(struct sk_buff skb, struct net_device dev) · 585 unmodified lines
586	frag = skb_shinfo(skb)->frags;	586	frag = skb_shinfo(skb)->frags;
587	while (nr_frags) {	587	while (nr_frags) {
588	CBDC_SC(bdp,	588	CBDC_SC(bdp,
589	BD_ENET_TX_STATS \| BD_ENET_TX_LAST \| BD_ENET_TX_TC);	589	BD_ENET_TX_STATS \| BD_ENET_TX_INTR \| BD_ENET_TX_LAST \|
		590	BD_ENET_TX_TC);
590	CBDS_SC(bdp, BD_ENET_TX_READY);	591	CBDS_SC(bdp, BD_ENET_TX_READY);
591		592
592	if ((CBDR_SC(bdp) & BD_ENET_TX_WRAP) == 0)	593	if ((CBDR_SC(bdp) & BD_ENET_TX_WRAP) == 0)

drivers/net/ethernet/freescale/fs_enet/mac-fec.c+1−1

@@ -110,7 +110,7 @@ static int do_pd_setup(struct fs_enet_private *fep) · 109 unmodified lines
110	}	110	}
111		111
112	#define FEC_NAPI_RX_EVENT_MSK (FEC_ENET_RXF \| FEC_ENET_RXB)	112	#define FEC_NAPI_RX_EVENT_MSK (FEC_ENET_RXF \| FEC_ENET_RXB)
113	#define FEC_NAPI_TX_EVENT_MSK (FEC_ENET_TXF \| FEC_ENET_TXB)	113	#define FEC_NAPI_TX_EVENT_MSK (FEC_ENET_TXF)
114	#define FEC_RX_EVENT (FEC_ENET_RXF)	114	#define FEC_RX_EVENT (FEC_ENET_RXF)
115	#define FEC_TX_EVENT (FEC_ENET_TXF)	115	#define FEC_TX_EVENT (FEC_ENET_TXF)
116	#define FEC_ERR_EVENT_MSK (FEC_ENET_HBERR \| FEC_ENET_BABR \| \	116	#define FEC_ERR_EVENT_MSK (FEC_ENET_HBERR \| FEC_ENET_BABR \| \

drivers/net/ethernet/freescale/gianfar.c+32−72

@@ -565,22 +565,6 @@ static void gfar_ints_enable(struct gfar_private *priv) · 564 unmodified lines
565	}	565	}
566	}	566	}
567		567
568	static void lock_tx_qs(struct gfar_private *priv)
569	{
570	int i;
571
572	for (i = 0; i < priv->num_tx_queues; i++)
573	spin_lock(&priv->tx_queue[i]->txlock);
574	}
575
576	static void unlock_tx_qs(struct gfar_private *priv)
577	{
578	int i;
579
580	for (i = 0; i < priv->num_tx_queues; i++)
581	spin_unlock(&priv->tx_queue[i]->txlock);
582	}
583
584	static int gfar_alloc_tx_queues(struct gfar_private *priv)	568	static int gfar_alloc_tx_queues(struct gfar_private *priv)
585	{	569	{
586	int i;	570	int i;
@@ -1376,7 +1360,6 @@ static int gfar_probe(struct platform_device *ofdev) · 789 unmodified lines
1376	priv->dev = &ofdev->dev;	1360	priv->dev = &ofdev->dev;
1377	SET_NETDEV_DEV(dev, &ofdev->dev);	1361	SET_NETDEV_DEV(dev, &ofdev->dev);
1378		1362
1379	spin_lock_init(&priv->bflock);
1380	INIT_WORK(&priv->reset_task, gfar_reset_task);	1363	INIT_WORK(&priv->reset_task, gfar_reset_task);
1381		1364
1382	platform_set_drvdata(ofdev, priv);	1365	platform_set_drvdata(ofdev, priv);
@@ -1470,9 +1453,8 @@ static int gfar_probe(struct platform_device *ofdev) · 87 unmodified lines
1470	goto register_fail;	1453	goto register_fail;
1471	}	1454	}
1472		1455
1473	device_init_wakeup(&dev->dev,	1456	device_set_wakeup_capable(&dev->dev, priv->device_flags &
1474	priv->device_flags &	1457	FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1475	FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1476		1458
1477	/* fill out IRQ number and name fields */	1459	/* fill out IRQ number and name fields */
1478	for (i = 0; i < priv->num_grps; i++) {	1460	for (i = 0; i < priv->num_grps; i++) {
@@ -1540,48 +1522,37 @@ static int gfar_suspend(struct device *dev) · 61 unmodified lines
1540	struct gfar_private *priv = dev_get_drvdata(dev);	1522	struct gfar_private *priv = dev_get_drvdata(dev);
1541	struct net_device *ndev = priv->ndev;	1523	struct net_device *ndev = priv->ndev;
1542	struct gfar __iomem *regs = priv->gfargrp[0].regs;	1524	struct gfar __iomem *regs = priv->gfargrp[0].regs;
1543	unsigned long flags;
1544	u32 tempval;	1525	u32 tempval;
1545
1546	int magic_packet = priv->wol_en &&	1526	int magic_packet = priv->wol_en &&
1547	(priv->device_flags &	1527	(priv->device_flags &
1548	FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);	1528	FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1549		1529
		1530	if (!netif_running(ndev))
		1531	return 0;
		1532
		1533	disable_napi(priv);
		1534	netif_tx_lock(ndev);
1550	netif_device_detach(ndev);	1535	netif_device_detach(ndev);
		1536	netif_tx_unlock(ndev);
1551		1537
1552	if (netif_running(ndev)) {	1538	gfar_halt(priv);
1553		1539
1554	local_irq_save(flags);	1540	if (magic_packet) {
1555	lock_tx_qs(priv);	1541	/* Enable interrupt on Magic Packet */
		1542	gfar_write(&regs->imask, IMASK_MAG);
1556		1543
1557	gfar_halt_nodisable(priv);	1544	/* Enable Magic Packet mode */
		1545	tempval = gfar_read(&regs->maccfg2);
		1546	tempval \|= MACCFG2_MPEN;
		1547	gfar_write(&regs->maccfg2, tempval);
1558		1548
1559	/* Disable Tx, and Rx if wake-on-LAN is disabled. */	1549	/* re-enable the Rx block */
1560	tempval = gfar_read(&regs->maccfg1);	1550	tempval = gfar_read(&regs->maccfg1);
1561		1551	tempval \|= MACCFG1_RX_EN;
1562	tempval &= ~MACCFG1_TX_EN;
1563
1564	if (!magic_packet)
1565	tempval &= ~MACCFG1_RX_EN;
1566
1567	gfar_write(&regs->maccfg1, tempval);	1552	gfar_write(&regs->maccfg1, tempval);
1568		1553
1569	unlock_tx_qs(priv);	1554	} else {
1570	local_irq_restore(flags);	1555	phy_stop(priv->phydev);
1571
1572	disable_napi(priv);
1573
1574	if (magic_packet) {
1575	/* Enable interrupt on Magic Packet */
1576	gfar_write(&regs->imask, IMASK_MAG);
1577
1578	/* Enable Magic Packet mode */
1579	tempval = gfar_read(&regs->maccfg2);
1580	tempval \|= MACCFG2_MPEN;
1581	gfar_write(&regs->maccfg2, tempval);
1582	} else {
1583	phy_stop(priv->phydev);
1584	}
1585	}	1556	}
1586		1557
1587	return 0;	1558	return 0;
@@ -1592,37 +1563,26 @@ static int gfar_resume(struct device *dev) · 4 unmodified lines
1592	struct gfar_private *priv = dev_get_drvdata(dev);	1563	struct gfar_private *priv = dev_get_drvdata(dev);
1593	struct net_device *ndev = priv->ndev;	1564	struct net_device *ndev = priv->ndev;
1594	struct gfar __iomem *regs = priv->gfargrp[0].regs;	1565	struct gfar __iomem *regs = priv->gfargrp[0].regs;
1595	unsigned long flags;
1596	u32 tempval;	1566	u32 tempval;
1597	int magic_packet = priv->wol_en &&	1567	int magic_packet = priv->wol_en &&
1598	(priv->device_flags &	1568	(priv->device_flags &
1599	FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);	1569	FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1600		1570
1601	if (!netif_running(ndev)) {	1571	if (!netif_running(ndev))
1602	netif_device_attach(ndev);
1603	return 0;	1572	return 0;
1604	}
1605		1573
1606	if (!magic_packet && priv->phydev)	1574	if (magic_packet) {
		1575	/* Disable Magic Packet mode */
		1576	tempval = gfar_read(&regs->maccfg2);
		1577	tempval &= ~MACCFG2_MPEN;
		1578	gfar_write(&regs->maccfg2, tempval);
		1579	} else {
1607	phy_start(priv->phydev);	1580	phy_start(priv->phydev);
1608		1581	}
1609	/* Disable Magic Packet mode, in case something
1610	* else woke us up.
1611	*/
1612	local_irq_save(flags);
1613	lock_tx_qs(priv);
1614
1615	tempval = gfar_read(&regs->maccfg2);
1616	tempval &= ~MACCFG2_MPEN;
1617	gfar_write(&regs->maccfg2, tempval);
1618		1582
1619	gfar_start(priv);	1583	gfar_start(priv);
1620		1584
1621	unlock_tx_qs(priv);
1622	local_irq_restore(flags);
1623
1624	netif_device_attach(ndev);	1585	netif_device_attach(ndev);
1625
1626	enable_napi(priv);	1586	enable_napi(priv);
1627		1587
1628	return 0;	1588	return 0;
@@ -2045,7 +2005,8 @@ static int register_grp_irqs(struct gfar_priv_grp *grp) · 416 unmodified lines
2045	/* Install our interrupt handlers for Error,	2005	/* Install our interrupt handlers for Error,
2046	* Transmit, and Receive	2006	* Transmit, and Receive
2047	*/	2007	*/
2048	err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,	2008	err = request_irq(gfar_irq(grp, ER)->irq, gfar_error,
		2009	IRQF_NO_SUSPEND,
2049	gfar_irq(grp, ER)->name, grp);	2010	gfar_irq(grp, ER)->name, grp);
2050	if (err < 0) {	2011	if (err < 0) {
2051	netif_err(priv, intr, dev, "Can't get IRQ %d\n",	2012	netif_err(priv, intr, dev, "Can't get IRQ %d\n",
@@ -2068,7 +2029,8 @@ static int register_grp_irqs(struct gfar_priv_grp *grp) · 16 unmodified lines
2068	goto rx_irq_fail;	2029	goto rx_irq_fail;
2069	}	2030	}
2070	} else {	2031	} else {
2071	err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,	2032	err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt,
		2033	IRQF_NO_SUSPEND,
2072	gfar_irq(grp, TX)->name, grp);	2034	gfar_irq(grp, TX)->name, grp);
2073	if (err < 0) {	2035	if (err < 0) {
2074	netif_err(priv, intr, dev, "Can't get IRQ %d\n",	2036	netif_err(priv, intr, dev, "Can't get IRQ %d\n",
@@ -2169,8 +2131,6 @@ static int gfar_enet_open(struct net_device *dev) · 94 unmodified lines
2169	if (err)	2131	if (err)
2170	return err;	2132	return err;
2171		2133
2172	device_set_wakeup_enable(&dev->dev, priv->wol_en);
2173
2174	return err;	2134	return err;
2175	}	2135	}
2176		2136

drivers/net/ethernet/freescale/gianfar.h+0−3

@@ -1145,9 +1145,6 @@ struct gfar_private { · 1144 unmodified lines
1145	int oldduplex;	1145	int oldduplex;
1146	int oldlink;	1146	int oldlink;
1147		1147
1148	/* Bitfield update lock */
1149	spinlock_t bflock;
1150
1151	uint32_t msg_enable;	1148	uint32_t msg_enable;
1152		1149
1153	struct work_struct reset_task;	1150	struct work_struct reset_task;

drivers/net/ethernet/freescale/gianfar_ethtool.c+5−345

@@ -653,7 +653,6 @@ static void gfar_get_wol(struct net_device dev, struct ethtool_wolinfo wol) · 652 unmodified lines
653	static int gfar_set_wol(struct net_device dev, struct ethtool_wolinfo wol)	653	static int gfar_set_wol(struct net_device dev, struct ethtool_wolinfo wol)
654	{	654	{
655	struct gfar_private *priv = netdev_priv(dev);	655	struct gfar_private *priv = netdev_priv(dev);
656	unsigned long flags;
657		656
658	if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&	657	if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
659	wol->wolopts != 0)	658	wol->wolopts != 0)
@@ -664,9 +663,7 @@ static int gfar_set_wol(struct net_device dev, struct ethtool_wolinfo wol) · 4 unmodified lines
664		663
665	device_set_wakeup_enable(&dev->dev, wol->wolopts & WAKE_MAGIC);	664	device_set_wakeup_enable(&dev->dev, wol->wolopts & WAKE_MAGIC);
666		665
667	spin_lock_irqsave(&priv->bflock, flags);	666	priv->wol_en = !!device_may_wakeup(&dev->dev);
668	priv->wol_en = !!device_may_wakeup(&dev->dev);
669	spin_unlock_irqrestore(&priv->bflock, flags);
670		667
671	return 0;	668	return 0;
672	}	669	}
@@ -903,27 +900,6 @@ static int gfar_check_filer_hardware(struct gfar_private *priv) · 230 unmodified lines
903	return 0;	900	return 0;
904	}	901	}
905		902
906	static int gfar_comp_asc(const void a, const void b)
907	{
908	return memcmp(a, b, 4);
909	}
910
911	static int gfar_comp_desc(const void a, const void b)
912	{
913	return -memcmp(a, b, 4);
914	}
915
916	static void gfar_swap(void a, void b, int size)
917	{
918	u32 *_a = a;
919	u32 *_b = b;
920
921	swap(_a[0], _b[0]);
922	swap(_a[1], _b[1]);
923	swap(_a[2], _b[2]);
924	swap(_a[3], _b[3]);
925	}
926
927	/* Write a mask to filer cache */	903	/* Write a mask to filer cache */
928	static void gfar_set_mask(u32 mask, struct filer_table *tab)	904	static void gfar_set_mask(u32 mask, struct filer_table *tab)
929	{	905	{
@@ -1273,310 +1249,6 @@ static int gfar_convert_to_filer(struct ethtool_rx_flow_spec *rule, · 343 unmodified lines
1273	return 0;	1249	return 0;
1274	}	1250	}
1275		1251
1276	/* Copy size filer entries */
1277	static void gfar_copy_filer_entries(struct gfar_filer_entry dst[0],
1278	struct gfar_filer_entry src[0], s32 size)
1279	{
1280	while (size > 0) {
1281	size--;
1282	dst[size].ctrl = src[size].ctrl;
1283	dst[size].prop = src[size].prop;
1284	}
1285	}
1286
1287	/* Delete the contents of the filer-table between start and end
1288	* and collapse them
1289	*/
1290	static int gfar_trim_filer_entries(u32 begin, u32 end, struct filer_table *tab)
1291	{
1292	int length;
1293
1294	if (end > MAX_FILER_CACHE_IDX \|\| end < begin)
1295	return -EINVAL;
1296
1297	end++;
1298	length = end - begin;
1299
1300	/* Copy */
1301	while (end < tab->index) {
1302	tab->fe[begin].ctrl = tab->fe[end].ctrl;
1303	tab->fe[begin++].prop = tab->fe[end++].prop;
1304
1305	}
1306	/* Fill up with don't cares */
1307	while (begin < tab->index) {
1308	tab->fe[begin].ctrl = 0x60;
1309	tab->fe[begin].prop = 0xFFFFFFFF;
1310	begin++;
1311	}
1312
1313	tab->index -= length;
1314	return 0;
1315	}
1316
1317	/* Make space on the wanted location */
1318	static int gfar_expand_filer_entries(u32 begin, u32 length,
1319	struct filer_table *tab)
1320	{
1321	if (length == 0 \|\| length + tab->index > MAX_FILER_CACHE_IDX \|\|
1322	begin > MAX_FILER_CACHE_IDX)
1323	return -EINVAL;
1324
1325	gfar_copy_filer_entries(&(tab->fe[begin + length]), &(tab->fe[begin]),
1326	tab->index - length + 1);
1327
1328	tab->index += length;
1329	return 0;
1330	}
1331
1332	static int gfar_get_next_cluster_start(int start, struct filer_table *tab)
1333	{
1334	for (; (start < tab->index) && (start < MAX_FILER_CACHE_IDX - 1);
1335	start++) {
1336	if ((tab->fe[start].ctrl & (RQFCR_AND \| RQFCR_CLE)) ==
1337	(RQFCR_AND \| RQFCR_CLE))
1338	return start;
1339	}
1340	return -1;
1341	}
1342
1343	static int gfar_get_next_cluster_end(int start, struct filer_table *tab)
1344	{
1345	for (; (start < tab->index) && (start < MAX_FILER_CACHE_IDX - 1);
1346	start++) {
1347	if ((tab->fe[start].ctrl & (RQFCR_AND \| RQFCR_CLE)) ==
1348	(RQFCR_CLE))
1349	return start;
1350	}
1351	return -1;
1352	}
1353
1354	/* Uses hardwares clustering option to reduce
1355	* the number of filer table entries
1356	*/
1357	static void gfar_cluster_filer(struct filer_table *tab)
1358	{
1359	s32 i = -1, j, iend, jend;
1360
1361	while ((i = gfar_get_next_cluster_start(++i, tab)) != -1) {
1362	j = i;
1363	while ((j = gfar_get_next_cluster_start(++j, tab)) != -1) {
1364	/* The cluster entries self and the previous one
1365	* (a mask) must be identical!
1366	*/
1367	if (tab->fe[i].ctrl != tab->fe[j].ctrl)
1368	break;
1369	if (tab->fe[i].prop != tab->fe[j].prop)
1370	break;
1371	if (tab->fe[i - 1].ctrl != tab->fe[j - 1].ctrl)
1372	break;
1373	if (tab->fe[i - 1].prop != tab->fe[j - 1].prop)
1374	break;
1375	iend = gfar_get_next_cluster_end(i, tab);
1376	jend = gfar_get_next_cluster_end(j, tab);
1377	if (jend == -1 \|\| iend == -1)
1378	break;
1379
1380	/* First we make some free space, where our cluster
1381	* element should be. Then we copy it there and finally
1382	* delete in from its old location.
1383	*/
1384	if (gfar_expand_filer_entries(iend, (jend - j), tab) ==
1385	-EINVAL)
1386	break;
1387
1388	gfar_copy_filer_entries(&(tab->fe[iend + 1]),
1389	&(tab->fe[jend + 1]), jend - j);
1390
1391	if (gfar_trim_filer_entries(jend - 1,
1392	jend + (jend - j),
1393	tab) == -EINVAL)
1394	return;
1395
1396	/* Mask out cluster bit */
1397	tab->fe[iend].ctrl &= ~(RQFCR_CLE);
1398	}
1399	}
1400	}
1401
1402	/* Swaps the masked bits of a1<>a2 and b1<>b2 */
1403	static void gfar_swap_bits(struct gfar_filer_entry *a1,
1404	struct gfar_filer_entry *a2,
1405	struct gfar_filer_entry *b1,
1406	struct gfar_filer_entry *b2, u32 mask)
1407	{
1408	u32 temp[4];
1409	temp[0] = a1->ctrl & mask;
1410	temp[1] = a2->ctrl & mask;
1411	temp[2] = b1->ctrl & mask;
1412	temp[3] = b2->ctrl & mask;
1413
1414	a1->ctrl &= ~mask;
1415	a2->ctrl &= ~mask;
1416	b1->ctrl &= ~mask;
1417	b2->ctrl &= ~mask;
1418
1419	a1->ctrl \|= temp[1];
1420	a2->ctrl \|= temp[0];
1421	b1->ctrl \|= temp[3];
1422	b2->ctrl \|= temp[2];
1423	}
1424
1425	/* Generate a list consisting of masks values with their start and
1426	* end of validity and block as indicator for parts belonging
1427	* together (glued by ANDs) in mask_table
1428	*/
1429	static u32 gfar_generate_mask_table(struct gfar_mask_entry *mask_table,
1430	struct filer_table *tab)
1431	{
1432	u32 i, and_index = 0, block_index = 1;
1433
1434	for (i = 0; i < tab->index; i++) {
1435
1436	/* LSByte of control = 0 sets a mask */
1437	if (!(tab->fe[i].ctrl & 0xF)) {
1438	mask_table[and_index].mask = tab->fe[i].prop;
1439	mask_table[and_index].start = i;
1440	mask_table[and_index].block = block_index;
1441	if (and_index >= 1)
1442	mask_table[and_index - 1].end = i - 1;
1443	and_index++;
1444	}
1445	/* cluster starts and ends will be separated because they should
1446	* hold their position
1447	*/
1448	if (tab->fe[i].ctrl & RQFCR_CLE)
1449	block_index++;
1450	/* A not set AND indicates the end of a depended block */
1451	if (!(tab->fe[i].ctrl & RQFCR_AND))
1452	block_index++;
1453	}
1454
1455	mask_table[and_index - 1].end = i - 1;
1456
1457	return and_index;
1458	}
1459
1460	/* Sorts the entries of mask_table by the values of the masks.
1461	* Important: The 0xFF80 flags of the first and last entry of a
1462	* block must hold their position (which queue, CLusterEnable, ReJEct,
1463	* AND)
1464	*/
1465	static void gfar_sort_mask_table(struct gfar_mask_entry *mask_table,
1466	struct filer_table *temp_table, u32 and_index)
1467	{
1468	/* Pointer to compare function (_asc or _desc) */
1469	int (gfar_comp)(const void , const void *);
1470
1471	u32 i, size = 0, start = 0, prev = 1;
1472	u32 old_first, old_last, new_first, new_last;
1473
1474	gfar_comp = &gfar_comp_desc;
1475
1476	for (i = 0; i < and_index; i++) {
1477	if (prev != mask_table[i].block) {
1478	old_first = mask_table[start].start + 1;
1479	old_last = mask_table[i - 1].end;
1480	sort(mask_table + start, size,
1481	sizeof(struct gfar_mask_entry),
1482	gfar_comp, &gfar_swap);
1483
1484	/* Toggle order for every block. This makes the
1485	* thing more efficient!
1486	*/
1487	if (gfar_comp == gfar_comp_desc)
1488	gfar_comp = &gfar_comp_asc;
1489	else
1490	gfar_comp = &gfar_comp_desc;
1491
1492	new_first = mask_table[start].start + 1;
1493	new_last = mask_table[i - 1].end;
1494
1495	gfar_swap_bits(&temp_table->fe[new_first],
1496	&temp_table->fe[old_first],
1497	&temp_table->fe[new_last],
1498	&temp_table->fe[old_last],
1499	RQFCR_QUEUE \| RQFCR_CLE \|
1500	RQFCR_RJE \| RQFCR_AND);
1501
1502	start = i;
1503	size = 0;
1504	}
1505	size++;
1506	prev = mask_table[i].block;
1507	}
1508	}
1509
1510	/* Reduces the number of masks needed in the filer table to save entries
1511	* This is done by sorting the masks of a depended block. A depended block is
1512	* identified by gluing ANDs or CLE. The sorting order toggles after every
1513	* block. Of course entries in scope of a mask must change their location with
1514	* it.
1515	*/
1516	static int gfar_optimize_filer_masks(struct filer_table *tab)
1517	{
1518	struct filer_table *temp_table;
1519	struct gfar_mask_entry *mask_table;
1520
1521	u32 and_index = 0, previous_mask = 0, i = 0, j = 0, size = 0;
1522	s32 ret = 0;
1523
1524	/* We need a copy of the filer table because
1525	* we want to change its order
1526	*/
1527	temp_table = kmemdup(tab, sizeof(*temp_table), GFP_KERNEL);
1528	if (temp_table == NULL)
1529	return -ENOMEM;
1530
1531	mask_table = kcalloc(MAX_FILER_CACHE_IDX / 2 + 1,
1532	sizeof(struct gfar_mask_entry), GFP_KERNEL);
1533
1534	if (mask_table == NULL) {
1535	ret = -ENOMEM;
1536	goto end;
1537	}
1538
1539	and_index = gfar_generate_mask_table(mask_table, tab);
1540
1541	gfar_sort_mask_table(mask_table, temp_table, and_index);
1542
1543	/* Now we can copy the data from our duplicated filer table to
1544	* the real one in the order the mask table says
1545	*/
1546	for (i = 0; i < and_index; i++) {
1547	size = mask_table[i].end - mask_table[i].start + 1;
1548	gfar_copy_filer_entries(&(tab->fe[j]),
1549	&(temp_table->fe[mask_table[i].start]), size);
1550	j += size;
1551	}
1552
1553	/* And finally we just have to check for duplicated masks and drop the
1554	* second ones
1555	*/
1556	for (i = 0; i < tab->index && i < MAX_FILER_CACHE_IDX; i++) {
1557	if (tab->fe[i].ctrl == 0x80) {
1558	previous_mask = i++;
1559	break;
1560	}
1561	}
1562	for (; i < tab->index && i < MAX_FILER_CACHE_IDX; i++) {
1563	if (tab->fe[i].ctrl == 0x80) {
1564	if (tab->fe[i].prop == tab->fe[previous_mask].prop) {
1565	/* Two identical ones found!
1566	* So drop the second one!
1567	*/
1568	gfar_trim_filer_entries(i, i, tab);
1569	} else
1570	/* Not identical! */
1571	previous_mask = i;
1572	}
1573	}
1574
1575	kfree(mask_table);
1576	end: kfree(temp_table);
1577	return ret;
1578	}
1579
1580	/* Write the bit-pattern from software's buffer to hardware registers */	1252	/* Write the bit-pattern from software's buffer to hardware registers */
1581	static int gfar_write_filer_table(struct gfar_private *priv,	1253	static int gfar_write_filer_table(struct gfar_private *priv,
1582	struct filer_table *tab)	1254	struct filer_table *tab)
@@ -1586,11 +1258,10 @@ static int gfar_write_filer_table(struct gfar_private *priv, · 3 unmodified lines
1586	return -EBUSY;	1258	return -EBUSY;
1587		1259
1588	/* Fill regular entries */	1260	/* Fill regular entries */
1589	for (; i < MAX_FILER_IDX - 1 && (tab->fe[i].ctrl \| tab->fe[i].prop);	1261	for (; i < MAX_FILER_IDX && (tab->fe[i].ctrl \| tab->fe[i].prop); i++)
1590	i++)
1591	gfar_write_filer(priv, i, tab->fe[i].ctrl, tab->fe[i].prop);	1262	gfar_write_filer(priv, i, tab->fe[i].ctrl, tab->fe[i].prop);
1592	/* Fill the rest with fall-troughs */	1263	/* Fill the rest with fall-troughs */
1593	for (; i < MAX_FILER_IDX - 1; i++)	1264	for (; i < MAX_FILER_IDX; i++)
1594	gfar_write_filer(priv, i, 0x60, 0xFFFFFFFF);	1265	gfar_write_filer(priv, i, 0x60, 0xFFFFFFFF);
1595	/* Last entry must be default accept	1266	/* Last entry must be default accept
1596	* because that's what people expect	1267	* because that's what people expect
@@ -1624,7 +1295,6 @@ static int gfar_process_filer_changes(struct gfar_private *priv) · 27 unmodified lines
1624	{	1295	{
1625	struct ethtool_flow_spec_container *j;	1296	struct ethtool_flow_spec_container *j;
1626	struct filer_table *tab;	1297	struct filer_table *tab;
1627	s32 i = 0;
1628	s32 ret = 0;	1298	s32 ret = 0;
1629		1299
1630	/* So index is set to zero, too! */	1300	/* So index is set to zero, too! */
@@ -1649,17 +1319,6 @@ static int gfar_process_filer_changes(struct gfar_private *priv) · 18 unmodified lines
1649	}	1319	}
1650	}	1320	}
1651		1321
1652	i = tab->index;
1653
1654	/* Optimizations to save entries */
1655	gfar_cluster_filer(tab);
1656	gfar_optimize_filer_masks(tab);
1657
1658	pr_debug("\tSummary:\n"
1659	"\tData on hardware: %d\n"
1660	"\tCompression rate: %d%%\n",
1661	tab->index, 100 - (100 * tab->index) / i);
1662
1663	/* Write everything to hardware */	1322	/* Write everything to hardware */
1664	ret = gfar_write_filer_table(priv, tab);	1323	ret = gfar_write_filer_table(priv, tab);
1665	if (ret == -EBUSY) {	1324	if (ret == -EBUSY) {
@@ -1725,13 +1384,14 @@ static int gfar_add_cls(struct gfar_private *priv, · 59 unmodified lines
1725	}	1384	}
1726		1385
1727	process:	1386	process:
		1387	priv->rx_list.count++;
1728	ret = gfar_process_filer_changes(priv);	1388	ret = gfar_process_filer_changes(priv);
1729	if (ret)	1389	if (ret)
1730	goto clean_list;	1390	goto clean_list;
1731	priv->rx_list.count++;
1732	return ret;	1391	return ret;
1733		1392
1734	clean_list:	1393	clean_list:
		1394	priv->rx_list.count--;
1735	list_del(&temp->list);	1395	list_del(&temp->list);
1736	clean_mem:	1396	clean_mem:
1737	kfree(temp);	1397	kfree(temp);

drivers/net/ethernet/marvell/mvneta.c+10−12

 		     struct mvneta_rx_queue *rxq)
 {
 	struct net_device *dev = pp->dev;
-	int rx_done, rx_filled;
+	int rx_done;
 	u32 rcvd_pkts = 0;
 	u32 rcvd_bytes = 0;
 		rx_todo = rx_done;
 	rx_done = 0;
-	rx_filled = 0;
 	/* Fairness NAPI loop */
 	while (rx_done < rx_todo) {
 		int rx_bytes, err;
 		rx_done++;
-		rx_filled++;
 		rx_status = rx_desc->status;
 		rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
 		data = (unsigned char *)rx_desc->buf_cookie;
 			continue;
 		}
+		/* Refill processing */
+		err = mvneta_rx_refill(pp, rx_desc);
+		if (err) {
+			netdev_err(dev, "Linux processing - Can't refill\n");
+			rxq->missed++;
+			goto err_drop_frame;
+		}
 		skb = build_skb(data, pp->frag_size > PAGE_SIZE ? 0 : pp->frag_size);
 		if (!skb)
 			goto err_drop_frame;
 		mvneta_rx_csum(pp, rx_status, skb);
 		napi_gro_receive(&pp->napi, skb);
-		/* Refill processing */
-		err = mvneta_rx_refill(pp, rx_desc);
-		if (err) {
-			netdev_err(dev, "Linux processing - Can't refill\n");
-			rxq->missed++;
-			rx_filled--;
-		}
 	}
 	if (rcvd_pkts) {
 	}
 	/* Update rxq management counters */
-	mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_filled);
+	mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
 	return rx_done;
 }

drivers/net/ethernet/marvell/mvpp2.c+167−77

@@ -27,6 +27,8 @@ · 26 unmodified lines
27	#include <linux/of_address.h>	27	#include <linux/of_address.h>
28	#include <linux/phy.h>	28	#include <linux/phy.h>
29	#include <linux/clk.h>	29	#include <linux/clk.h>
		30	#include <linux/hrtimer.h>
		31	#include <linux/ktime.h>
30	#include <uapi/linux/ppp_defs.h>	32	#include <uapi/linux/ppp_defs.h>
31	#include <net/ip.h>	33	#include <net/ip.h>
32	#include <net/ipv6.h>	34	#include <net/ipv6.h>
@@ -299,6 +301,7 @@ · 266 unmodified lines
299		301
300	/* Coalescing */	302	/* Coalescing */
301	#define MVPP2_TXDONE_COAL_PKTS_THRESH 15	303	#define MVPP2_TXDONE_COAL_PKTS_THRESH 15
		304	#define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
302	#define MVPP2_RX_COAL_PKTS 32	305	#define MVPP2_RX_COAL_PKTS 32
303	#define MVPP2_RX_COAL_USEC 100	306	#define MVPP2_RX_COAL_USEC 100
304		307
@@ -660,6 +663,14 @@ struct mvpp2_pcpu_stats { · 355 unmodified lines
660	u64 tx_bytes;	663	u64 tx_bytes;
661	};	664	};
662		665
		666	/* Per-CPU port control */
		667	struct mvpp2_port_pcpu {
		668	struct hrtimer tx_done_timer;
		669	bool timer_scheduled;
		670	/* Tasklet for egress finalization */
		671	struct tasklet_struct tx_done_tasklet;
		672	};
		673
663	struct mvpp2_port {	674	struct mvpp2_port {
664	u8 id;	675	u8 id;
665		676
@@ -679,6 +690,9 @@ struct mvpp2_port { · 13 unmodified lines
679	u32 pending_cause_rx;	690	u32 pending_cause_rx;
680	struct napi_struct napi;	691	struct napi_struct napi;
681		692
		693	/* Per-CPU port control */
		694	struct mvpp2_port_pcpu __percpu *pcpu;
		695
682	/* Flags */	696	/* Flags */
683	unsigned long flags;	697	unsigned long flags;
684		698
@@ -776,6 +790,9 @@ struct mvpp2_txq_pcpu { · 91 unmodified lines
776	/* Array of transmitted skb */	790	/* Array of transmitted skb */
777	struct sk_buff **tx_skb;	791	struct sk_buff **tx_skb;
778		792
		793	/* Array of transmitted buffers' physical addresses */
		794	dma_addr_t *tx_buffs;
		795
779	/* Index of last TX DMA descriptor that was inserted */	796	/* Index of last TX DMA descriptor that was inserted */
780	int txq_put_index;	797	int txq_put_index;
781		798
@@ -913,8 +930,6 @@ struct mvpp2_bm_pool { · 131 unmodified lines
913	/* Occupied buffers indicator */	930	/* Occupied buffers indicator */
914	atomic_t in_use;	931	atomic_t in_use;
915	int in_use_thresh;	932	int in_use_thresh;
916
917	spinlock_t lock;
918	};	933	};
919		934
920	struct mvpp2_buff_hdr {	935	struct mvpp2_buff_hdr {
@@ -963,9 +978,13 @@ static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu) · 42 unmodified lines
963	}	978	}
964		979
965	static void mvpp2_txq_inc_put(struct mvpp2_txq_pcpu *txq_pcpu,	980	static void mvpp2_txq_inc_put(struct mvpp2_txq_pcpu *txq_pcpu,
966	struct sk_buff *skb)	981	struct sk_buff *skb,
		982	struct mvpp2_tx_desc *tx_desc)
967	{	983	{
968	txq_pcpu->tx_skb[txq_pcpu->txq_put_index] = skb;	984	txq_pcpu->tx_skb[txq_pcpu->txq_put_index] = skb;
		985	if (skb)
		986	txq_pcpu->tx_buffs[txq_pcpu->txq_put_index] =
		987	tx_desc->buf_phys_addr;
969	txq_pcpu->txq_put_index++;	988	txq_pcpu->txq_put_index++;
970	if (txq_pcpu->txq_put_index == txq_pcpu->size)	989	if (txq_pcpu->txq_put_index == txq_pcpu->size)
971	txq_pcpu->txq_put_index = 0;	990	txq_pcpu->txq_put_index = 0;
@@ -3376,7 +3395,6 @@ static int mvpp2_bm_pool_create(struct platform_device *pdev, · 2404 unmodified lines
3376	bm_pool->pkt_size = 0;	3395	bm_pool->pkt_size = 0;
3377	bm_pool->buf_num = 0;	3396	bm_pool->buf_num = 0;
3378	atomic_set(&bm_pool->in_use, 0);	3397	atomic_set(&bm_pool->in_use, 0);
3379	spin_lock_init(&bm_pool->lock);
3380		3398
3381	return 0;	3399	return 0;
3382	}	3400	}
@@ -3647,7 +3665,6 @@ static struct mvpp2_bm_pool * · 264 unmodified lines
3647	mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,	3665	mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
3648	int pkt_size)	3666	int pkt_size)
3649	{	3667	{
3650	unsigned long flags = 0;
3651	struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];	3668	struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
3652	int num;	3669	int num;
3653		3670
@@ -3656,8 +3673,6 @@ mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type, · 2 unmodified lines
3656	return NULL;	3673	return NULL;
3657	}	3674	}
3658		3675
3659	spin_lock_irqsave(&new_pool->lock, flags);
3660
3661	if (new_pool->type == MVPP2_BM_FREE)	3676	if (new_pool->type == MVPP2_BM_FREE)
3662	new_pool->type = type;	3677	new_pool->type = type;
3663		3678
@@ -3686,8 +3701,6 @@ mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type, · 22 unmodified lines
3686	if (num != pkts_num) {	3701	if (num != pkts_num) {
3687	WARN(1, "pool %d: %d of %d allocated\n",	3702	WARN(1, "pool %d: %d of %d allocated\n",
3688	new_pool->id, num, pkts_num);	3703	new_pool->id, num, pkts_num);
3689	/* We need to undo the bufs_add() allocations */
3690	spin_unlock_irqrestore(&new_pool->lock, flags);
3691	return NULL;	3704	return NULL;
3692	}	3705	}
3693	}	3706	}
@@ -3695,15 +3708,12 @@ mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type, · 1 unmodified line
3695	mvpp2_bm_pool_bufsize_set(port->priv, new_pool,	3708	mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
3696	MVPP2_RX_BUF_SIZE(new_pool->pkt_size));	3709	MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
3697		3710
3698	spin_unlock_irqrestore(&new_pool->lock, flags);
3699
3700	return new_pool;	3711	return new_pool;
3701	}	3712	}
3702		3713
3703	/* Initialize pools for swf */	3714	/* Initialize pools for swf */
3704	static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)	3715	static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
3705	{	3716	{
3706	unsigned long flags = 0;
3707	int rxq;	3717	int rxq;
3708		3718
3709	if (!port->pool_long) {	3719	if (!port->pool_long) {
@@ -3714,9 +3724,7 @@ static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) · 4 unmodified lines
3714	if (!port->pool_long)	3724	if (!port->pool_long)
3715	return -ENOMEM;	3725	return -ENOMEM;
3716		3726
3717	spin_lock_irqsave(&port->pool_long->lock, flags);
3718	port->pool_long->port_map \|= (1 << port->id);	3727	port->pool_long->port_map \|= (1 << port->id);
3719	spin_unlock_irqrestore(&port->pool_long->lock, flags);
3720		3728
3721	for (rxq = 0; rxq < rxq_number; rxq++)	3729	for (rxq = 0; rxq < rxq_number; rxq++)
3722	mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);	3730	mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
@@ -3730,9 +3738,7 @@ static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) · 7 unmodified lines
3730	if (!port->pool_short)	3738	if (!port->pool_short)
3731	return -ENOMEM;	3739	return -ENOMEM;
3732		3740
3733	spin_lock_irqsave(&port->pool_short->lock, flags);
3734	port->pool_short->port_map \|= (1 << port->id);	3741	port->pool_short->port_map \|= (1 << port->id);
3735	spin_unlock_irqrestore(&port->pool_short->lock, flags);
3736		3742
3737	for (rxq = 0; rxq < rxq_number; rxq++)	3743	for (rxq = 0; rxq < rxq_number; rxq++)
3738	mvpp2_rxq_short_pool_set(port, rxq,	3744	mvpp2_rxq_short_pool_set(port, rxq,
@@ -3806,7 +3812,6 @@ static void mvpp2_interrupts_unmask(void *arg) · 67 unmodified lines
3806		3812
3807	mvpp2_write(port->priv, MVPP2_ISR_RX_TX_MASK_REG(port->id),	3813	mvpp2_write(port->priv, MVPP2_ISR_RX_TX_MASK_REG(port->id),
3808	(MVPP2_CAUSE_MISC_SUM_MASK \|	3814	(MVPP2_CAUSE_MISC_SUM_MASK \|
3809	MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK \|
3810	MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK));	3815	MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK));
3811	}	3816	}
3812		3817
@@ -4382,23 +4387,6 @@ static void mvpp2_rx_time_coal_set(struct mvpp2_port *port, · 569 unmodified lines
4382	rxq->time_coal = usec;	4387	rxq->time_coal = usec;
4383	}	4388	}
4384		4389
4385	/* Set threshold for TX_DONE pkts coalescing */
4386	static void mvpp2_tx_done_pkts_coal_set(void *arg)
4387	{
4388	struct mvpp2_port *port = arg;
4389	int queue;
4390	u32 val;
4391
4392	for (queue = 0; queue < txq_number; queue++) {
4393	struct mvpp2_tx_queue *txq = port->txqs[queue];
4394
4395	val = (txq->done_pkts_coal << MVPP2_TRANSMITTED_THRESH_OFFSET) &
4396	MVPP2_TRANSMITTED_THRESH_MASK;
4397	mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4398	mvpp2_write(port->priv, MVPP2_TXQ_THRESH_REG, val);
4399	}
4400	}
4401
4402	/* Free Tx queue skbuffs */	4390	/* Free Tx queue skbuffs */
4403	static void mvpp2_txq_bufs_free(struct mvpp2_port *port,	4391	static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
4404	struct mvpp2_tx_queue *txq,	4392	struct mvpp2_tx_queue *txq,
@@ -4407,8 +4395,8 @@ static void mvpp2_txq_bufs_free(struct mvpp2_port *port, · 2 unmodified lines
4407	int i;	4395	int i;
4408		4396
4409	for (i = 0; i < num; i++) {	4397	for (i = 0; i < num; i++) {
4410	struct mvpp2_tx_desc *tx_desc = txq->descs +	4398	dma_addr_t buf_phys_addr =
4411	txq_pcpu->txq_get_index;	4399	txq_pcpu->tx_buffs[txq_pcpu->txq_get_index];
4412	struct sk_buff *skb = txq_pcpu->tx_skb[txq_pcpu->txq_get_index];	4400	struct sk_buff *skb = txq_pcpu->tx_skb[txq_pcpu->txq_get_index];
4413		4401
4414	mvpp2_txq_inc_get(txq_pcpu);	4402	mvpp2_txq_inc_get(txq_pcpu);
@@ -4416,8 +4404,8 @@ static void mvpp2_txq_bufs_free(struct mvpp2_port *port, · 1 unmodified line
4416	if (!skb)	4404	if (!skb)
4417	continue;	4405	continue;
4418		4406
4419	dma_unmap_single(port->dev->dev.parent, tx_desc->buf_phys_addr,	4407	dma_unmap_single(port->dev->dev.parent, buf_phys_addr,
4420	tx_desc->data_size, DMA_TO_DEVICE);	4408	skb_headlen(skb), DMA_TO_DEVICE);
4421	dev_kfree_skb_any(skb);	4409	dev_kfree_skb_any(skb);
4422	}	4410	}
4423	}	4411	}
@@ -4433,7 +4421,7 @@ static inline struct mvpp2_rx_queue mvpp2_get_rx_queue(struct mvpp2_port port, · 9 unmodified lines
4433	static inline struct mvpp2_tx_queue mvpp2_get_tx_queue(struct mvpp2_port port,	4421	static inline struct mvpp2_tx_queue mvpp2_get_tx_queue(struct mvpp2_port port,
4434	u32 cause)	4422	u32 cause)
4435	{	4423	{
4436	int queue = fls(cause >> 16) - 1;	4424	int queue = fls(cause) - 1;
4437		4425
4438	return port->txqs[queue];	4426	return port->txqs[queue];
4439	}	4427	}
@@ -4460,6 +4448,29 @@ static void mvpp2_txq_done(struct mvpp2_port port, struct mvpp2_tx_queue txq, · 20 unmodified lines
4460	netif_tx_wake_queue(nq);	4448	netif_tx_wake_queue(nq);
4461	}	4449	}
4462		4450
		4451	static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause)
		4452	{
		4453	struct mvpp2_tx_queue *txq;
		4454	struct mvpp2_txq_pcpu *txq_pcpu;
		4455	unsigned int tx_todo = 0;
		4456
		4457	while (cause) {
		4458	txq = mvpp2_get_tx_queue(port, cause);
		4459	if (!txq)
		4460	break;
		4461
		4462	txq_pcpu = this_cpu_ptr(txq->pcpu);
		4463
		4464	if (txq_pcpu->count) {
		4465	mvpp2_txq_done(port, txq, txq_pcpu);
		4466	tx_todo += txq_pcpu->count;
		4467	}
		4468
		4469	cause &= ~(1 << txq->log_id);
		4470	}
		4471	return tx_todo;
		4472	}
		4473
4463	/* Rx/Tx queue initialization/cleanup methods */	4474	/* Rx/Tx queue initialization/cleanup methods */
4464		4475
4465	/* Allocate and initialize descriptors for aggr TXQ */	4476	/* Allocate and initialize descriptors for aggr TXQ */
@@ -4649,12 +4660,13 @@ static int mvpp2_txq_init(struct mvpp2_port *port, · 183 unmodified lines
4649	txq_pcpu->tx_skb = kmalloc(txq_pcpu->size *	4660	txq_pcpu->tx_skb = kmalloc(txq_pcpu->size *
4650	sizeof(*txq_pcpu->tx_skb),	4661	sizeof(*txq_pcpu->tx_skb),
4651	GFP_KERNEL);	4662	GFP_KERNEL);
4652	if (!txq_pcpu->tx_skb) {	4663	if (!txq_pcpu->tx_skb)
4653	dma_free_coherent(port->dev->dev.parent,	4664	goto error;
4654	txq->size * MVPP2_DESC_ALIGNED_SIZE,	4665
4655	txq->descs, txq->descs_phys);	4666	txq_pcpu->tx_buffs = kmalloc(txq_pcpu->size *
4656	return -ENOMEM;	4667	sizeof(dma_addr_t), GFP_KERNEL);
4657	}	4668	if (!txq_pcpu->tx_buffs)
		4669	goto error;
4658		4670
4659	txq_pcpu->count = 0;	4671	txq_pcpu->count = 0;
4660	txq_pcpu->reserved_num = 0;	4672	txq_pcpu->reserved_num = 0;
@@ -4663,6 +4675,19 @@ static int mvpp2_txq_init(struct mvpp2_port *port, · 2 unmodified lines
4663	}	4675	}
4664		4676
4665	return 0;	4677	return 0;
		4678
		4679	error:
		4680	for_each_present_cpu(cpu) {
		4681	txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
		4682	kfree(txq_pcpu->tx_skb);
		4683	kfree(txq_pcpu->tx_buffs);
		4684	}
		4685
		4686	dma_free_coherent(port->dev->dev.parent,
		4687	txq->size * MVPP2_DESC_ALIGNED_SIZE,
		4688	txq->descs, txq->descs_phys);
		4689
		4690	return -ENOMEM;
4666	}	4691	}
4667		4692
4668	/* Free allocated TXQ resources */	4693	/* Free allocated TXQ resources */
@@ -4675,6 +4700,7 @@ static void mvpp2_txq_deinit(struct mvpp2_port *port, · 6 unmodified lines
4675	for_each_present_cpu(cpu) {	4700	for_each_present_cpu(cpu) {
4676	txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);	4701	txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4677	kfree(txq_pcpu->tx_skb);	4702	kfree(txq_pcpu->tx_skb);
		4703	kfree(txq_pcpu->tx_buffs);
4678	}	4704	}
4679		4705
4680	if (txq->descs)	4706	if (txq->descs)
@@ -4805,7 +4831,6 @@ static int mvpp2_setup_txqs(struct mvpp2_port *port) · 124 unmodified lines
4805	goto err_cleanup;	4831	goto err_cleanup;
4806	}	4832	}
4807		4833
4808	on_each_cpu(mvpp2_tx_done_pkts_coal_set, port, 1);
4809	on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);	4834	on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
4810	return 0;	4835	return 0;
4811		4836
@@ -4887,6 +4912,49 @@ static void mvpp2_link_event(struct net_device *dev) · 75 unmodified lines
4887	}	4912	}
4888	}	4913	}
4889		4914
		4915	static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu)
		4916	{
		4917	ktime_t interval;
		4918
		4919	if (!port_pcpu->timer_scheduled) {
		4920	port_pcpu->timer_scheduled = true;
		4921	interval = ktime_set(0, MVPP2_TXDONE_HRTIMER_PERIOD_NS);
		4922	hrtimer_start(&port_pcpu->tx_done_timer, interval,
		4923	HRTIMER_MODE_REL_PINNED);
		4924	}
		4925	}
		4926
		4927	static void mvpp2_tx_proc_cb(unsigned long data)
		4928	{
		4929	struct net_device dev = (struct net_device )data;
		4930	struct mvpp2_port *port = netdev_priv(dev);
		4931	struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu);
		4932	unsigned int tx_todo, cause;
		4933
		4934	if (!netif_running(dev))
		4935	return;
		4936	port_pcpu->timer_scheduled = false;
		4937
		4938	/* Process all the Tx queues */
		4939	cause = (1 << txq_number) - 1;
		4940	tx_todo = mvpp2_tx_done(port, cause);
		4941
		4942	/* Set the timer in case not all the packets were processed */
		4943	if (tx_todo)
		4944	mvpp2_timer_set(port_pcpu);
		4945	}
		4946
		4947	static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer)
		4948	{
		4949	struct mvpp2_port_pcpu *port_pcpu = container_of(timer,
		4950	struct mvpp2_port_pcpu,
		4951	tx_done_timer);
		4952
		4953	tasklet_schedule(&port_pcpu->tx_done_tasklet);
		4954
		4955	return HRTIMER_NORESTART;
		4956	}
		4957
4890	/* Main RX/TX processing routines */	4958	/* Main RX/TX processing routines */
4891		4959
4892	/* Display more error info */	4960	/* Display more error info */
@@ -5144,11 +5212,11 @@ static int mvpp2_tx_frag_process(struct mvpp2_port port, struct sk_buff skb, · 251 unmodified lines
5144	if (i == (skb_shinfo(skb)->nr_frags - 1)) {	5212	if (i == (skb_shinfo(skb)->nr_frags - 1)) {
5145	/* Last descriptor */	5213	/* Last descriptor */
5146	tx_desc->command = MVPP2_TXD_L_DESC;	5214	tx_desc->command = MVPP2_TXD_L_DESC;
5147	mvpp2_txq_inc_put(txq_pcpu, skb);	5215	mvpp2_txq_inc_put(txq_pcpu, skb, tx_desc);
5148	} else {	5216	} else {
5149	/* Descriptor in the middle: Not First, Not Last */	5217	/* Descriptor in the middle: Not First, Not Last */
5150	tx_desc->command = 0;	5218	tx_desc->command = 0;
5151	mvpp2_txq_inc_put(txq_pcpu, NULL);	5219	mvpp2_txq_inc_put(txq_pcpu, NULL, tx_desc);
5152	}	5220	}
5153	}	5221	}
5154		5222
@@ -5214,12 +5282,12 @@ static int mvpp2_tx(struct sk_buff skb, struct net_device dev) · 59 unmodified lines
5214	/* First and Last descriptor */	5282	/* First and Last descriptor */
5215	tx_cmd \|= MVPP2_TXD_F_DESC \| MVPP2_TXD_L_DESC;	5283	tx_cmd \|= MVPP2_TXD_F_DESC \| MVPP2_TXD_L_DESC;
5216	tx_desc->command = tx_cmd;	5284	tx_desc->command = tx_cmd;
5217	mvpp2_txq_inc_put(txq_pcpu, skb);	5285	mvpp2_txq_inc_put(txq_pcpu, skb, tx_desc);
5218	} else {	5286	} else {
5219	/* First but not Last */	5287	/* First but not Last */
5220	tx_cmd \|= MVPP2_TXD_F_DESC \| MVPP2_TXD_PADDING_DISABLE;	5288	tx_cmd \|= MVPP2_TXD_F_DESC \| MVPP2_TXD_PADDING_DISABLE;
5221	tx_desc->command = tx_cmd;	5289	tx_desc->command = tx_cmd;
5222	mvpp2_txq_inc_put(txq_pcpu, NULL);	5290	mvpp2_txq_inc_put(txq_pcpu, NULL, tx_desc);
5223		5291
5224	/* Continue with other skb fragments */	5292	/* Continue with other skb fragments */
5225	if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) {	5293	if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) {
@@ -5255,6 +5323,17 @@ out: · 29 unmodified lines
5255	dev_kfree_skb_any(skb);	5323	dev_kfree_skb_any(skb);
5256	}	5324	}
5257		5325
		5326	/* Finalize TX processing */
		5327	if (txq_pcpu->count >= txq->done_pkts_coal)
		5328	mvpp2_txq_done(port, txq, txq_pcpu);
		5329
		5330	/* Set the timer in case not all frags were processed */
		5331	if (txq_pcpu->count <= frags && txq_pcpu->count > 0) {
		5332	struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu);
		5333
		5334	mvpp2_timer_set(port_pcpu);
		5335	}
		5336
5258	return NETDEV_TX_OK;	5337	return NETDEV_TX_OK;
5259	}	5338	}
5260		5339
@@ -5268,10 +5347,11 @@ static inline void mvpp2_cause_error(struct net_device *dev, int cause) · 7 unmodified lines
5268	netdev_err(dev, "tx fifo underrun error\n");	5347	netdev_err(dev, "tx fifo underrun error\n");
5269	}	5348	}
5270		5349
5271	static void mvpp2_txq_done_percpu(void *arg)	5350	static int mvpp2_poll(struct napi_struct *napi, int budget)
5272	{	5351	{
5273	struct mvpp2_port *port = arg;	5352	u32 cause_rx_tx, cause_rx, cause_misc;
5274	u32 cause_rx_tx, cause_tx, cause_misc;	5353	int rx_done = 0;
		5354	struct mvpp2_port *port = netdev_priv(napi->dev);
5275		5355
5276	/* Rx/Tx cause register	5356	/* Rx/Tx cause register
5277	*	5357	*
@@ -5285,7 +5365,7 @@ static void mvpp2_txq_done_percpu(void *arg) · 7 unmodified lines
5285	*/	5365	*/
5286	cause_rx_tx = mvpp2_read(port->priv,	5366	cause_rx_tx = mvpp2_read(port->priv,
5287	MVPP2_ISR_RX_TX_CAUSE_REG(port->id));	5367	MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
5288	cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;	5368	cause_rx_tx &= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
5289	cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;	5369	cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
5290		5370
5291	if (cause_misc) {	5371	if (cause_misc) {
@@ -5297,26 +5377,6 @@ static void mvpp2_txq_done_percpu(void *arg) · 5 unmodified lines
5297	cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK);	5377	cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK);
5298	}	5378	}
5299		5379
5300	/* Release TX descriptors */
5301	if (cause_tx) {
5302	struct mvpp2_tx_queue *txq = mvpp2_get_tx_queue(port, cause_tx);
5303	struct mvpp2_txq_pcpu *txq_pcpu = this_cpu_ptr(txq->pcpu);
5304
5305	if (txq_pcpu->count)
5306	mvpp2_txq_done(port, txq, txq_pcpu);
5307	}
5308	}
5309
5310	static int mvpp2_poll(struct napi_struct *napi, int budget)
5311	{
5312	u32 cause_rx_tx, cause_rx;
5313	int rx_done = 0;
5314	struct mvpp2_port *port = netdev_priv(napi->dev);
5315
5316	on_each_cpu(mvpp2_txq_done_percpu, port, 1);
5317
5318	cause_rx_tx = mvpp2_read(port->priv,
5319	MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
5320	cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;	5380	cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
5321		5381
5322	/* Process RX packets */	5382	/* Process RX packets */
@@ -5561,6 +5621,8 @@ err_cleanup_rxqs: · 238 unmodified lines
5561	static int mvpp2_stop(struct net_device *dev)	5621	static int mvpp2_stop(struct net_device *dev)
5562	{	5622	{
5563	struct mvpp2_port *port = netdev_priv(dev);	5623	struct mvpp2_port *port = netdev_priv(dev);
		5624	struct mvpp2_port_pcpu *port_pcpu;
		5625	int cpu;
5564		5626
5565	mvpp2_stop_dev(port);	5627	mvpp2_stop_dev(port);
5566	mvpp2_phy_disconnect(port);	5628	mvpp2_phy_disconnect(port);
@@ -5569,6 +5631,13 @@ static int mvpp2_stop(struct net_device *dev) · 2 unmodified lines
5569	on_each_cpu(mvpp2_interrupts_mask, port, 1);	5631	on_each_cpu(mvpp2_interrupts_mask, port, 1);
5570		5632
5571	free_irq(port->irq, port);	5633	free_irq(port->irq, port);
		5634	for_each_present_cpu(cpu) {
		5635	port_pcpu = per_cpu_ptr(port->pcpu, cpu);
		5636
		5637	hrtimer_cancel(&port_pcpu->tx_done_timer);
		5638	port_pcpu->timer_scheduled = false;
		5639	tasklet_kill(&port_pcpu->tx_done_tasklet);
		5640	}
5572	mvpp2_cleanup_rxqs(port);	5641	mvpp2_cleanup_rxqs(port);
5573	mvpp2_cleanup_txqs(port);	5642	mvpp2_cleanup_txqs(port);
5574		5643
@@ -5784,7 +5853,6 @@ static int mvpp2_ethtool_set_coalesce(struct net_device *dev, · 209 unmodified lines
5784	txq->done_pkts_coal = c->tx_max_coalesced_frames;	5853	txq->done_pkts_coal = c->tx_max_coalesced_frames;
5785	}	5854	}
5786		5855
5787	on_each_cpu(mvpp2_tx_done_pkts_coal_set, port, 1);
5788	return 0;	5856	return 0;
5789	}	5857	}
5790		5858
@@ -6035,6 +6103,7 @@ static int mvpp2_port_probe(struct platform_device *pdev, · 244 unmodified lines
6035	{	6103	{
6036	struct device_node *phy_node;	6104	struct device_node *phy_node;
6037	struct mvpp2_port *port;	6105	struct mvpp2_port *port;
		6106	struct mvpp2_port_pcpu *port_pcpu;
6038	struct net_device *dev;	6107	struct net_device *dev;
6039	struct resource *res;	6108	struct resource *res;
6040	const char *dt_mac_addr;	6109	const char *dt_mac_addr;
@@ -6044,7 +6113,7 @@ static int mvpp2_port_probe(struct platform_device *pdev, · 3 unmodified lines
6044	int features;	6113	int features;
6045	int phy_mode;	6114	int phy_mode;
6046	int priv_common_regs_num = 2;	6115	int priv_common_regs_num = 2;
6047	int err, i;	6116	int err, i, cpu;
6048		6117
6049	dev = alloc_etherdev_mqs(sizeof(struct mvpp2_port), txq_number,	6118	dev = alloc_etherdev_mqs(sizeof(struct mvpp2_port), txq_number,
6050	rxq_number);	6119	rxq_number);
@@ -6135,6 +6204,24 @@ static int mvpp2_port_probe(struct platform_device *pdev, · 84 unmodified lines
6135	}	6204	}
6136	mvpp2_port_power_up(port);	6205	mvpp2_port_power_up(port);
6137		6206
		6207	port->pcpu = alloc_percpu(struct mvpp2_port_pcpu);
		6208	if (!port->pcpu) {
		6209	err = -ENOMEM;
		6210	goto err_free_txq_pcpu;
		6211	}
		6212
		6213	for_each_present_cpu(cpu) {
		6214	port_pcpu = per_cpu_ptr(port->pcpu, cpu);
		6215
		6216	hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC,
		6217	HRTIMER_MODE_REL_PINNED);
		6218	port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb;
		6219	port_pcpu->timer_scheduled = false;
		6220
		6221	tasklet_init(&port_pcpu->tx_done_tasklet, mvpp2_tx_proc_cb,
		6222	(unsigned long)dev);
		6223	}
		6224
6138	netif_napi_add(dev, &port->napi, mvpp2_poll, NAPI_POLL_WEIGHT);	6225	netif_napi_add(dev, &port->napi, mvpp2_poll, NAPI_POLL_WEIGHT);
6139	features = NETIF_F_SG \| NETIF_F_IP_CSUM;	6226	features = NETIF_F_SG \| NETIF_F_IP_CSUM;
6140	dev->features = features \| NETIF_F_RXCSUM;	6227	dev->features = features \| NETIF_F_RXCSUM;
@@ -6144,7 +6231,7 @@ static int mvpp2_port_probe(struct platform_device *pdev, · 3 unmodified lines
6144	err = register_netdev(dev);	6231	err = register_netdev(dev);
6145	if (err < 0) {	6232	if (err < 0) {
6146	dev_err(&pdev->dev, "failed to register netdev\n");	6233	dev_err(&pdev->dev, "failed to register netdev\n");
6147	goto err_free_txq_pcpu;	6234	goto err_free_port_pcpu;
6148	}	6235	}
6149	netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);	6236	netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);
6150		6237
@@ -6153,6 +6240,8 @@ static int mvpp2_port_probe(struct platform_device *pdev, · 2 unmodified lines
6153	priv->port_list[id] = port;	6240	priv->port_list[id] = port;
6154	return 0;	6241	return 0;
6155		6242
		6243	err_free_port_pcpu:
		6244	free_percpu(port->pcpu);
6156	err_free_txq_pcpu:	6245	err_free_txq_pcpu:
6157	for (i = 0; i < txq_number; i++)	6246	for (i = 0; i < txq_number; i++)
6158	free_percpu(port->txqs[i]->pcpu);	6247	free_percpu(port->txqs[i]->pcpu);
@@ -6171,6 +6260,7 @@ static void mvpp2_port_remove(struct mvpp2_port *port) · 12 unmodified lines
6171	int i;	6260	int i;
6172		6261
6173	unregister_netdev(port->dev);	6262	unregister_netdev(port->dev);
		6263	free_percpu(port->pcpu);
6174	free_percpu(port->stats);	6264	free_percpu(port->stats);
6175	for (i = 0; i < txq_number; i++)	6265	for (i = 0; i < txq_number; i++)
6176	free_percpu(port->txqs[i]->pcpu);	6266	free_percpu(port->txqs[i]->pcpu);

drivers/net/ethernet/mellanox/mlx4/cmd.c+15−2

 {
 	struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 	struct mlx4_cmd_context *context;
+	long ret_wait;
 	int err = 0;
 	down(&cmd->event_sem);
 	if (err)
 		goto out_reset;
-	if (!wait_for_completion_timeout(&context->done,
+	if (op == MLX4_CMD_SENSE_PORT) {
-					 msecs_to_jiffies(timeout))) {
+		ret_wait =
+			wait_for_completion_interruptible_timeout(&context->done,
+								  msecs_to_jiffies(timeout));
+		if (ret_wait < 0) {
+			context->fw_status = 0;
+			context->out_param = 0;
+			context->result = 0;
+		}
+	} else {
+		ret_wait = (long)wait_for_completion_timeout(&context->done,
+							     msecs_to_jiffies(timeout));
+	}
+	if (!ret_wait) {
 		mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
 			  op);
 		if (op == MLX4_CMD_NOP) {

drivers/net/ethernet/mellanox/mlx4/en_rx.c+0−1

@@ -246,7 +246,6 @@ static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, · 245 unmodified lines
246		246
247	static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring)	247	static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring)
248	{	248	{
249	BUG_ON((u32)(ring->prod - ring->cons) > ring->actual_size);
250	return ring->prod == ring->cons;	249	return ring->prod == ring->cons;
251	}	250	}
252		251

drivers/net/ethernet/mellanox/mlx4/eq.c+2−2

@@ -601,7 +601,7 @@ static int mlx4_eq_int(struct mlx4_dev dev, struct mlx4_eq eq) · 600 unmodified lines
601	continue;	601	continue;
602	mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN to slave: %d, port:%d\n",	602	mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN to slave: %d, port:%d\n",
603	__func__, i, port);	603	__func__, i, port);
604	s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state;	604	s_info = &priv->mfunc.master.vf_oper[i].vport[port].state;
605	if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) {	605	if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) {
606	eqe->event.port_change.port =	606	eqe->event.port_change.port =
607	cpu_to_be32(	607	cpu_to_be32(
@@ -640,7 +640,7 @@ static int mlx4_eq_int(struct mlx4_dev dev, struct mlx4_eq eq) · 32 unmodified lines
640	continue;	640	continue;
641	if (i == mlx4_master_func_num(dev))	641	if (i == mlx4_master_func_num(dev))
642	continue;	642	continue;
643	s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state;	643	s_info = &priv->mfunc.master.vf_oper[i].vport[port].state;
644	if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) {	644	if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) {
645	eqe->event.port_change.port =	645	eqe->event.port_change.port =
646	cpu_to_be32(	646	cpu_to_be32(

drivers/net/ethernet/mellanox/mlx4/main.c+5−0

 		} else if (err == -ENOENT) {
 			err = 0;
 			continue;
+		} else if (mlx4_is_slave(dev) && err == -EINVAL) {
+			priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev);
+			mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n",
+				  MLX4_SINK_COUNTER_INDEX(dev));
+			err = 0;
 		} else {
 			mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n",
 				 __func__, port + 1, err);

drivers/net/ethernet/mellanox/mlx5/core/main.c+2−0

@@ -391,6 +391,8 @@ static int handle_hca_cap(struct mlx5_core_dev *dev) · 390 unmodified lines
391	/* disable cmdif checksum */	391	/* disable cmdif checksum */
392	MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);	392	MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
393		393
		394	MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
		395
394	err = set_caps(dev, set_ctx, set_sz);	396	err = set_caps(dev, set_ctx, set_sz);
395		397
396	query_ex:	398	query_ex:

drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c+1−1

@@ -1415,7 +1415,7 @@ static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter) · 1414 unmodified lines
1415	if (fw->size & 0xF) {	1415	if (fw->size & 0xF) {
1416	addr = dest + size;	1416	addr = dest + size;
1417	for (i = 0; i < (fw->size & 0xF); i++)	1417	for (i = 0; i < (fw->size & 0xF); i++)
1418	data[i] = temp[size + i];	1418	data[i] = ((u8 *)temp)[size + i];
1419	for (; i < 16; i++)	1419	for (; i < 16; i++)
1420	data[i] = 0;	1420	data[i] = 0;
1421	ret = qlcnic_ms_mem_write128(adapter, addr,	1421	ret = qlcnic_ms_mem_write128(adapter, addr,

drivers/net/ethernet/realtek/r8169.c+3−1

 	case RTL_GIGA_MAC_VER_46:
 	case RTL_GIGA_MAC_VER_47:
 	case RTL_GIGA_MAC_VER_48:
+		RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
+		break;
 	case RTL_GIGA_MAC_VER_49:
 	case RTL_GIGA_MAC_VER_50:
 	case RTL_GIGA_MAC_VER_51:
-		RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
+		RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
 		break;
 	default:
 		RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);

drivers/net/ethernet/renesas/ravb_main.c+38−36

 	struct ravb_desc *desc = NULL;
 	int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
 	int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q];
-	struct sk_buff *skb;
 	dma_addr_t dma_addr;
-	void *buffer;
 	int i;
 	priv->cur_rx[q] = 0;
 	memset(priv->rx_ring[q], 0, rx_ring_size);
 	/* Build RX ring buffer */
 	for (i = 0; i < priv->num_rx_ring[q]; i++) {
-		priv->rx_skb[q][i] = NULL;
-		skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1);
-		if (!skb)
-			break;
-		ravb_set_buffer_align(skb);
 		/* RX descriptor */
 		rx_desc = &priv->rx_ring[q][i];
 		/* The size of the buffer should be on 16-byte boundary. */
 		rx_desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16));
-		dma_addr = dma_map_single(&ndev->dev, skb->data,
+		dma_addr = dma_map_single(&ndev->dev, priv->rx_skb[q][i]->data,
 					  ALIGN(PKT_BUF_SZ, 16),
 					  DMA_FROM_DEVICE);
-		if (dma_mapping_error(&ndev->dev, dma_addr)) {
+		/* We just set the data size to 0 for a failed mapping which
-			dev_kfree_skb(skb);
+		 * should prevent DMA from happening...
-			break;
+		 */
-		}
+		if (dma_mapping_error(&ndev->dev, dma_addr))
-		priv->rx_skb[q][i] = skb;
+			rx_desc->ds_cc = cpu_to_le16(0);
 		rx_desc->dptr = cpu_to_le32(dma_addr);
 		rx_desc->die_dt = DT_FEMPTY;
 	}
 	rx_desc = &priv->rx_ring[q][i];
 	rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
 	rx_desc->die_dt = DT_LINKFIX; /* type */
-	priv->dirty_rx[q] = (u32)(i - priv->num_rx_ring[q]);
 	memset(priv->tx_ring[q], 0, tx_ring_size);
 	/* Build TX ring buffer */
 	for (i = 0; i < priv->num_tx_ring[q]; i++) {
-		priv->tx_skb[q][i] = NULL;
-		priv->tx_buffers[q][i] = NULL;
-		buffer = kmalloc(PKT_BUF_SZ + RAVB_ALIGN - 1, GFP_KERNEL);
-		if (!buffer)
-			break;
-		/* Aligned TX buffer */
-		priv->tx_buffers[q][i] = buffer;
 		tx_desc = &priv->tx_ring[q][i];
 		tx_desc->die_dt = DT_EEMPTY;
 	}
 static int ravb_ring_init(struct net_device *ndev, int q)
 {
 	struct ravb_private *priv = netdev_priv(ndev);
+	struct sk_buff *skb;
 	int ring_size;
+	void *buffer;
+	int i;
 	/* Allocate RX and TX skb rings */
 	priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
 	if (!priv->rx_skb[q] || !priv->tx_skb[q])
 		goto error;
+	for (i = 0; i < priv->num_rx_ring[q]; i++) {
+		skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1);
+		if (!skb)
+			goto error;
+		ravb_set_buffer_align(skb);
+		priv->rx_skb[q][i] = skb;
+	}
 	/* Allocate rings for the aligned buffers */
 	priv->tx_buffers[q] = kcalloc(priv->num_tx_ring[q],
 				      sizeof(*priv->tx_buffers[q]), GFP_KERNEL);
 	if (!priv->tx_buffers[q])
 		goto error;
+	for (i = 0; i < priv->num_tx_ring[q]; i++) {
+		buffer = kmalloc(PKT_BUF_SZ + RAVB_ALIGN - 1, GFP_KERNEL);
+		if (!buffer)
+			goto error;
+		/* Aligned TX buffer */
+		priv->tx_buffers[q][i] = buffer;
+	}
 	/* Allocate all RX descriptors. */
 	ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
 	priv->rx_ring[q] = dma_alloc_coherent(NULL, ring_size,
 		if (--boguscnt < 0)
 			break;
+		/* We use 0-byte descriptors to mark the DMA mapping errors */
+		if (!pkt_len)
+			continue;
 		if (desc_status & MSC_MC)
 			stats->multicast++;
 			skb = priv->rx_skb[q][entry];
 			priv->rx_skb[q][entry] = NULL;
-			dma_sync_single_for_cpu(&ndev->dev,
+			dma_unmap_single(&ndev->dev, le32_to_cpu(desc->dptr),
-						le32_to_cpu(desc->dptr),
+					 ALIGN(PKT_BUF_SZ, 16),
-						ALIGN(PKT_BUF_SZ, 16),
+					 DMA_FROM_DEVICE);
-						DMA_FROM_DEVICE);
 			get_ts &= (q == RAVB_NC) ?
 					RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
 					~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
 			if (!skb)
 				break;	/* Better luck next round. */
 			ravb_set_buffer_align(skb);
-			dma_unmap_single(&ndev->dev, le32_to_cpu(desc->dptr),
-					 ALIGN(PKT_BUF_SZ, 16),
-					 DMA_FROM_DEVICE);
 			dma_addr = dma_map_single(&ndev->dev, skb->data,
 						  le16_to_cpu(desc->ds_cc),
 						  DMA_FROM_DEVICE);
 			skb_checksum_none_assert(skb);
-			if (dma_mapping_error(&ndev->dev, dma_addr)) {
+			/* We just set the data size to 0 for a failed mapping
-				dev_kfree_skb_any(skb);
+			 * which should prevent DMA  from happening...
-				break;
+			 */
-			}
+			if (dma_mapping_error(&ndev->dev, dma_addr))
+				desc->ds_cc = cpu_to_le16(0);
 			desc->dptr = cpu_to_le32(dma_addr);
 			priv->rx_skb[q][entry] = skb;
 		}
 	u32 dma_addr;
 	void *buffer;
 	u32 entry;
-	u32 tccr;
 	spin_lock_irqsave(&priv->lock, flags);
 	if (priv->cur_tx[q] - priv->dirty_tx[q] >= priv->num_tx_ring[q]) {
 	dma_wmb();
 	desc->die_dt = DT_FSINGLE;
-	tccr = ravb_read(ndev, TCCR);
+	ravb_write(ndev, ravb_read(ndev, TCCR) | (TCCR_TSRQ0 << q), TCCR);
-	if (!(tccr & (TCCR_TSRQ0 << q)))
-		ravb_write(ndev, tccr | (TCCR_TSRQ0 << q), TCCR);
 	priv->cur_tx[q]++;
 	if (priv->cur_tx[q] - priv->dirty_tx[q] >= priv->num_tx_ring[q] &&

drivers/net/ethernet/rocker/rocker.c+1−0

@@ -4821,6 +4821,7 @@ static void rocker_remove_ports(const struct rocker *rocker) · 4820 unmodified lines
4821	rocker_port_ig_tbl(rocker_port, SWITCHDEV_TRANS_NONE,	4821	rocker_port_ig_tbl(rocker_port, SWITCHDEV_TRANS_NONE,
4822	ROCKER_OP_FLAG_REMOVE);	4822	ROCKER_OP_FLAG_REMOVE);
4823	unregister_netdev(rocker_port->dev);	4823	unregister_netdev(rocker_port->dev);
		4824	free_netdev(rocker_port->dev);
4824	}	4825	}
4825	kfree(rocker->ports);	4826	kfree(rocker->ports);
4826	}	4827	}

drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c+2−2

@@ -42,7 +42,7 @@ · 41 unmodified lines
42	#define NSS_COMMON_CLK_DIV_MASK 0x7f	42	#define NSS_COMMON_CLK_DIV_MASK 0x7f
43		43
44	#define NSS_COMMON_CLK_SRC_CTRL 0x14	44	#define NSS_COMMON_CLK_SRC_CTRL 0x14
45	#define NSS_COMMON_CLK_SRC_CTRL_OFFSET(x) (1 << x)	45	#define NSS_COMMON_CLK_SRC_CTRL_OFFSET(x) (x)
46	/* Mode is coded on 1 bit but is different depending on the MAC ID:	46	/* Mode is coded on 1 bit but is different depending on the MAC ID:
47	* MAC0: QSGMII=0 RGMII=1	47	* MAC0: QSGMII=0 RGMII=1
48	* MAC1: QSGMII=0 SGMII=0 RGMII=1	48	* MAC1: QSGMII=0 SGMII=0 RGMII=1
@@ -291,7 +291,7 @@ static void ipq806x_gmac_setup(struct platform_device pdev) · 242 unmodified lines
291		291
292	/* Configure the clock src according to the mode */	292	/* Configure the clock src according to the mode */
293	regmap_read(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, &val);	293	regmap_read(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, &val);
294	val &= ~NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id);	294	val &= ~(1 << NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id));
295	switch (gmac->phy_mode) {	295	switch (gmac->phy_mode) {
296	case PHY_INTERFACE_MODE_RGMII:	296	case PHY_INTERFACE_MODE_RGMII:
297	val \|= NSS_COMMON_CLK_SRC_CTRL_RGMII(gmac->id) <<	297	val \|= NSS_COMMON_CLK_SRC_CTRL_RGMII(gmac->id) <<

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c+1−1

@@ -2843,7 +2843,7 @@ int stmmac_dvr_probe(struct device *device, · 2842 unmodified lines
2843	if (res->mac)	2843	if (res->mac)
2844	memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);	2844	memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
2845		2845
2846	dev_set_drvdata(device, priv);	2846	dev_set_drvdata(device, priv->dev);
2847		2847
2848	/* Verify driver arguments */	2848	/* Verify driver arguments */
2849	stmmac_verify_args();	2849	stmmac_verify_args();

drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c+4−0

@@ -413,3 +413,7 @@ static int stmmac_pltfr_resume(struct device *dev) · 412 unmodified lines
413	SIMPLE_DEV_PM_OPS(stmmac_pltfr_pm_ops, stmmac_pltfr_suspend,	413	SIMPLE_DEV_PM_OPS(stmmac_pltfr_pm_ops, stmmac_pltfr_suspend,
414	stmmac_pltfr_resume);	414	stmmac_pltfr_resume);
415	EXPORT_SYMBOL_GPL(stmmac_pltfr_pm_ops);	415	EXPORT_SYMBOL_GPL(stmmac_pltfr_pm_ops);
		416
		417	MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet platform support");
		418	MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
		419	MODULE_LICENSE("GPL");

drivers/net/ethernet/sun/niu.c+1−3

 		struct sk_buff *skb_new;
 		skb_new = skb_realloc_headroom(skb, len);
-		if (!skb_new) {
+		if (!skb_new)
-			rp->tx_errors++;
 			goto out_drop;
-		}
 		kfree_skb(skb);
 		skb = skb_new;
 	} else

drivers/net/ethernet/ti/cpsw.c+3−6

 static int cpsw_poll(struct napi_struct *napi, int budget)
 {
 	struct cpsw_priv	*priv = napi_to_priv(napi);
-	int			num_tx, num_rx;
+	int			num_rx;
-	num_tx = cpdma_chan_process(priv->txch, 128);
 	num_rx = cpdma_chan_process(priv->rxch, budget);
 	if (num_rx < budget) {
 		}
 	}
-	if (num_rx || num_tx)
+	if (num_rx)
-		cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
+		cpsw_dbg(priv, intr, "poll %d rx pkts\n", num_rx);
-			 num_rx, num_tx);
 	return num_rx;
 }

drivers/net/ethernet/ti/netcp.h+1−1

 	struct list_head	rxhook_list_head;
 	unsigned int		rx_queue_id;
 	void			*rx_fdq[KNAV_DMA_FDQ_PER_CHAN];
-	u32			rx_buffer_sizes[KNAV_DMA_FDQ_PER_CHAN];
 	struct napi_struct	rx_napi;
 	struct napi_struct	tx_napi;
 /* SGMII functions */
 int netcp_sgmii_reset(void __iomem *sgmii_ofs, int port);
+bool netcp_sgmii_rtreset(void __iomem *sgmii_ofs, int port, bool set);
 int netcp_sgmii_get_port_link(void __iomem *sgmii_ofs, int port);
 int netcp_sgmii_config(void __iomem *sgmii_ofs, int port, u32 interface);

drivers/net/ethernet/ti/netcp_core.c+25−26

 #define NETCP_SOP_OFFSET	(NET_IP_ALIGN + NET_SKB_PAD)
 #define NETCP_NAPI_WEIGHT	64
 #define NETCP_TX_TIMEOUT	(5 * HZ)
+#define NETCP_PACKET_SIZE	(ETH_FRAME_LEN + ETH_FCS_LEN)
 #define NETCP_MIN_PACKET_SIZE	ETH_ZLEN
 #define NETCP_MAX_MCAST_ADDR	16
 	if (likely(fdq == 0)) {
 		unsigned int primary_buf_len;
 		/* Allocate a primary receive queue entry */
-		buf_len = netcp->rx_buffer_sizes[0] + NETCP_SOP_OFFSET;
+		buf_len = NETCP_PACKET_SIZE + NETCP_SOP_OFFSET;
 		primary_buf_len = SKB_DATA_ALIGN(buf_len) +
 				SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
-		if (primary_buf_len <= PAGE_SIZE) {
+		bufptr = netdev_alloc_frag(primary_buf_len);
-			bufptr = netdev_alloc_frag(primary_buf_len);
+		pad[1] = primary_buf_len;
-			pad[1] = primary_buf_len;
-		} else {
-			bufptr = kmalloc(primary_buf_len, GFP_ATOMIC |
-					 GFP_DMA32 | __GFP_COLD);
-			pad[1] = 0;
-		}
 		if (unlikely(!bufptr)) {
-			dev_warn_ratelimited(netcp->ndev_dev, "Primary RX buffer alloc failed\n");
+			dev_warn_ratelimited(netcp->ndev_dev,
+					     "Primary RX buffer alloc failed\n");
 			goto fail;
 		}
 		dma = dma_map_single(netcp->dev, bufptr, buf_len,
 				     DMA_TO_DEVICE);
+		if (unlikely(dma_mapping_error(netcp->dev, dma)))
+			goto fail;
 		pad[0] = (u32)bufptr;
 	} else {
 		/* Allocate a secondary receive queue entry */
-		page = alloc_page(GFP_ATOMIC | GFP_DMA32 | __GFP_COLD);
+		page = alloc_page(GFP_ATOMIC | GFP_DMA | __GFP_COLD);
 		if (unlikely(!page)) {
 			dev_warn_ratelimited(netcp->ndev_dev, "Secondary page alloc failed\n");
 			goto fail;
 	/* Map the linear buffer */
 	dma_addr = dma_map_single(dev, skb->data, pkt_len, DMA_TO_DEVICE);
-	if (unlikely(!dma_addr)) {
+	if (unlikely(dma_mapping_error(dev, dma_addr))) {
 		dev_err(netcp->ndev_dev, "Failed to map skb buffer\n");
 		return NULL;
 	}
 	knav_queue_disable_notify(netcp->rx_queue);
 	/* open Rx FDQs */
-	for (i = 0; i < KNAV_DMA_FDQ_PER_CHAN &&
+	for (i = 0; i < KNAV_DMA_FDQ_PER_CHAN && netcp->rx_queue_depths[i];
-	     netcp->rx_queue_depths[i] && netcp->rx_buffer_sizes[i]; ++i) {
+	     ++i) {
 		snprintf(name, sizeof(name), "rx-fdq-%s-%d", ndev->name, i);
 		netcp->rx_fdq[i] = knav_queue_open(name, KNAV_QUEUE_GP, 0);
 		if (IS_ERR_OR_NULL(netcp->rx_fdq[i])) {
 	}
 	mutex_unlock(&netcp_modules_lock);
-	netcp_rxpool_refill(netcp);
 	napi_enable(&netcp->rx_napi);
 	napi_enable(&netcp->tx_napi);
 	knav_queue_enable_notify(netcp->tx_compl_q);
 	knav_queue_enable_notify(netcp->rx_queue);
+	netcp_rxpool_refill(netcp);
 	netif_tx_wake_all_queues(ndev);
 	dev_dbg(netcp->ndev_dev, "netcp device %s opened\n", ndev->name);
 	return 0;
 		netcp->rx_queue_depths[0] = 128;
 	}
-	ret = of_property_read_u32_array(node_interface, "rx-buffer-size",
-					 netcp->rx_buffer_sizes,
-					 KNAV_DMA_FDQ_PER_CHAN);
-	if (ret) {
-		dev_err(dev, "missing \"rx-buffer-size\" parameter\n");
-		netcp->rx_buffer_sizes[0] = 1536;
-	}
 	ret = of_property_read_u32_array(node_interface, "rx-pool", temp, 2);
 	if (ret < 0) {
 		dev_err(dev, "missing \"rx-pool\" parameter\n");
 static int netcp_remove(struct platform_device *pdev)
 {
 	struct netcp_device *netcp_device = platform_get_drvdata(pdev);
+	struct netcp_intf *netcp_intf, *netcp_tmp;
 	struct netcp_inst_modpriv *inst_modpriv, *tmp;
 	struct netcp_module *module;
 		list_del(&inst_modpriv->inst_list);
 		kfree(inst_modpriv);
 	}
-	WARN(!list_empty(&netcp_device->interface_head), "%s interface list not empty!\n",
-	     pdev->name);
-	devm_kfree(&pdev->dev, netcp_device);
+	/* now that all modules are removed, clean up the interfaces */
+	list_for_each_entry_safe(netcp_intf, netcp_tmp,
+				 &netcp_device->interface_head,
+				 interface_list) {
+		netcp_delete_interface(netcp_device, netcp_intf->ndev);
+	}
+	WARN(!list_empty(&netcp_device->interface_head),
+	     "%s interface list not empty!\n", pdev->name);
 	pm_runtime_put_sync(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
 	platform_set_drvdata(pdev, NULL);

drivers/net/ethernet/ti/netcp_ethss.c+37−30

@@ -1901,11 +1901,28 @@ static void gbe_port_config(struct gbe_priv gbe_dev, struct gbe_slave slave, · 1900 unmodified lines
1901	writel(slave->mac_control, GBE_REG_ADDR(slave, emac_regs, mac_control));	1901	writel(slave->mac_control, GBE_REG_ADDR(slave, emac_regs, mac_control));
1902	}	1902	}
1903		1903
		1904	static void gbe_sgmii_rtreset(struct gbe_priv *priv,
		1905	struct gbe_slave *slave, bool set)
		1906	{
		1907	void __iomem *sgmii_port_regs;
		1908
		1909	if (SLAVE_LINK_IS_XGMII(slave))
		1910	return;
		1911
		1912	if ((priv->ss_version == GBE_SS_VERSION_14) && (slave->slave_num >= 2))
		1913	sgmii_port_regs = priv->sgmii_port34_regs;
		1914	else
		1915	sgmii_port_regs = priv->sgmii_port_regs;
		1916
		1917	netcp_sgmii_rtreset(sgmii_port_regs, slave->slave_num, set);
		1918	}
		1919
1904	static void gbe_slave_stop(struct gbe_intf *intf)	1920	static void gbe_slave_stop(struct gbe_intf *intf)
1905	{	1921	{
1906	struct gbe_priv *gbe_dev = intf->gbe_dev;	1922	struct gbe_priv *gbe_dev = intf->gbe_dev;
1907	struct gbe_slave *slave = intf->slave;	1923	struct gbe_slave *slave = intf->slave;
1908		1924
		1925	gbe_sgmii_rtreset(gbe_dev, slave, true);
1909	gbe_port_reset(slave);	1926	gbe_port_reset(slave);
1910	/* Disable forwarding */	1927	/* Disable forwarding */
1911	cpsw_ale_control_set(gbe_dev->ale, slave->port_num,	1928	cpsw_ale_control_set(gbe_dev->ale, slave->port_num,
@@ -1947,6 +1964,7 @@ static int gbe_slave_open(struct gbe_intf *gbe_intf) · 35 unmodified lines
1947		1964
1948	gbe_sgmii_config(priv, slave);	1965	gbe_sgmii_config(priv, slave);
1949	gbe_port_reset(slave);	1966	gbe_port_reset(slave);
		1967	gbe_sgmii_rtreset(priv, slave, false);
1950	gbe_port_config(priv, slave, priv->rx_packet_max);	1968	gbe_port_config(priv, slave, priv->rx_packet_max);
1951	gbe_set_slave_mac(slave, gbe_intf);	1969	gbe_set_slave_mac(slave, gbe_intf);
1952	/* enable forwarding */	1970	/* enable forwarding */
@@ -2490,10 +2508,9 @@ static void free_secondary_ports(struct gbe_priv *gbe_dev) · 537 unmodified lines
2490	{	2508	{
2491	struct gbe_slave *slave;	2509	struct gbe_slave *slave;
2492		2510
2493	for (;;) {	2511	while (!list_empty(&gbe_dev->secondary_slaves)) {
2494	slave = first_sec_slave(gbe_dev);	2512	slave = first_sec_slave(gbe_dev);
2495	if (!slave)	2513
2496	break;
2497	if (slave->phy)	2514	if (slave->phy)
2498	phy_disconnect(slave->phy);	2515	phy_disconnect(slave->phy);
2499	list_del(&slave->slave_list);	2516	list_del(&slave->slave_list);
@@ -2839,14 +2856,13 @@ static int gbe_probe(struct netcp_device netcp_device, struct device dev, · 339 unmodified lines
2839	&gbe_dev->dma_chan_name);	2856	&gbe_dev->dma_chan_name);
2840	if (ret < 0) {	2857	if (ret < 0) {
2841	dev_err(dev, "missing \"tx-channel\" parameter\n");	2858	dev_err(dev, "missing \"tx-channel\" parameter\n");
2842	ret = -ENODEV;	2859	return -EINVAL;
2843	goto quit;
2844	}	2860	}
2845		2861
2846	if (!strcmp(node->name, "gbe")) {	2862	if (!strcmp(node->name, "gbe")) {
2847	ret = get_gbe_resource_version(gbe_dev, node);	2863	ret = get_gbe_resource_version(gbe_dev, node);
2848	if (ret)	2864	if (ret)
2849	goto quit;	2865	return ret;
2850		2866
2851	dev_dbg(dev, "ss_version: 0x%08x\n", gbe_dev->ss_version);	2867	dev_dbg(dev, "ss_version: 0x%08x\n", gbe_dev->ss_version);
2852		2868
@@ -2857,22 +2873,20 @@ static int gbe_probe(struct netcp_device netcp_device, struct device dev, · 4 unmodified lines
2857	else	2873	else
2858	ret = -ENODEV;	2874	ret = -ENODEV;
2859		2875
2860	if (ret)
2861	goto quit;
2862	} else if (!strcmp(node->name, "xgbe")) {	2876	} else if (!strcmp(node->name, "xgbe")) {
2863	ret = set_xgbe_ethss10_priv(gbe_dev, node);	2877	ret = set_xgbe_ethss10_priv(gbe_dev, node);
2864	if (ret)	2878	if (ret)
2865	goto quit;	2879	return ret;
2866	ret = netcp_xgbe_serdes_init(gbe_dev->xgbe_serdes_regs,	2880	ret = netcp_xgbe_serdes_init(gbe_dev->xgbe_serdes_regs,
2867	gbe_dev->ss_regs);	2881	gbe_dev->ss_regs);
2868	if (ret)
2869	goto quit;
2870	} else {	2882	} else {
2871	dev_err(dev, "unknown GBE node(%s)\n", node->name);	2883	dev_err(dev, "unknown GBE node(%s)\n", node->name);
2872	ret = -ENODEV;	2884	ret = -ENODEV;
2873	goto quit;
2874	}	2885	}
2875		2886
		2887	if (ret)
		2888	return ret;
		2889
2876	interfaces = of_get_child_by_name(node, "interfaces");	2890	interfaces = of_get_child_by_name(node, "interfaces");
2877	if (!interfaces)	2891	if (!interfaces)
2878	dev_err(dev, "could not find interfaces\n");	2892	dev_err(dev, "could not find interfaces\n");
@@ -2880,11 +2894,11 @@ static int gbe_probe(struct netcp_device netcp_device, struct device dev, · 1 unmodified line
2880	ret = netcp_txpipe_init(&gbe_dev->tx_pipe, netcp_device,	2894	ret = netcp_txpipe_init(&gbe_dev->tx_pipe, netcp_device,
2881	gbe_dev->dma_chan_name, gbe_dev->tx_queue_id);	2895	gbe_dev->dma_chan_name, gbe_dev->tx_queue_id);
2882	if (ret)	2896	if (ret)
2883	goto quit;	2897	return ret;
2884		2898
2885	ret = netcp_txpipe_open(&gbe_dev->tx_pipe);	2899	ret = netcp_txpipe_open(&gbe_dev->tx_pipe);
2886	if (ret)	2900	if (ret)
2887	goto quit;	2901	return ret;
2888		2902
2889	/* Create network interfaces */	2903	/* Create network interfaces */
2890	INIT_LIST_HEAD(&gbe_dev->gbe_intf_head);	2904	INIT_LIST_HEAD(&gbe_dev->gbe_intf_head);
@@ -2899,6 +2913,7 @@ static int gbe_probe(struct netcp_device netcp_device, struct device dev, · 8 unmodified lines
2899	if (gbe_dev->num_slaves >= gbe_dev->max_num_slaves)	2913	if (gbe_dev->num_slaves >= gbe_dev->max_num_slaves)
2900	break;	2914	break;
2901	}	2915	}
		2916	of_node_put(interfaces);
2902		2917
2903	if (!gbe_dev->num_slaves)	2918	if (!gbe_dev->num_slaves)
2904	dev_warn(dev, "No network interface configured\n");	2919	dev_warn(dev, "No network interface configured\n");
@@ -2911,9 +2926,10 @@ static int gbe_probe(struct netcp_device netcp_device, struct device dev, · 6 unmodified lines
2911	of_node_put(secondary_ports);	2926	of_node_put(secondary_ports);
2912		2927
2913	if (!gbe_dev->num_slaves) {	2928	if (!gbe_dev->num_slaves) {
2914	dev_err(dev, "No network interface or secondary ports configured\n");	2929	dev_err(dev,
		2930	"No network interface or secondary ports configured\n");
2915	ret = -ENODEV;	2931	ret = -ENODEV;
2916	goto quit;	2932	goto free_sec_ports;
2917	}	2933	}
2918		2934
2919	memset(&ale_params, 0, sizeof(ale_params));	2935	memset(&ale_params, 0, sizeof(ale_params));
@@ -2927,7 +2943,7 @@ static int gbe_probe(struct netcp_device netcp_device, struct device dev, · 7 unmodified lines
2927	if (!gbe_dev->ale) {	2943	if (!gbe_dev->ale) {
2928	dev_err(gbe_dev->dev, "error initializing ale engine\n");	2944	dev_err(gbe_dev->dev, "error initializing ale engine\n");
2929	ret = -ENODEV;	2945	ret = -ENODEV;
2930	goto quit;	2946	goto free_sec_ports;
2931	} else {	2947	} else {
2932	dev_dbg(gbe_dev->dev, "Created a gbe ale engine\n");	2948	dev_dbg(gbe_dev->dev, "Created a gbe ale engine\n");
2933	}	2949	}
@@ -2943,14 +2959,8 @@ static int gbe_probe(struct netcp_device netcp_device, struct device dev, · 9 unmodified lines
2943	*inst_priv = gbe_dev;	2959	*inst_priv = gbe_dev;
2944	return 0;	2960	return 0;
2945		2961
2946	quit:	2962	free_sec_ports:
2947	if (gbe_dev->hw_stats)	2963	free_secondary_ports(gbe_dev);
2948	devm_kfree(dev, gbe_dev->hw_stats);
2949	cpsw_ale_destroy(gbe_dev->ale);
2950	if (gbe_dev->ss_regs)
2951	devm_iounmap(dev, gbe_dev->ss_regs);
2952	of_node_put(interfaces);
2953	devm_kfree(dev, gbe_dev);
2954	return ret;	2964	return ret;
2955	}	2965	}
2956		2966
@@ -3023,12 +3033,9 @@ static int gbe_remove(struct netcp_device netcp_device, void inst_priv) · 66 unmodified lines
3023	free_secondary_ports(gbe_dev);	3033	free_secondary_ports(gbe_dev);
3024		3034
3025	if (!list_empty(&gbe_dev->gbe_intf_head))	3035	if (!list_empty(&gbe_dev->gbe_intf_head))
3026	dev_alert(gbe_dev->dev, "unreleased ethss interfaces present\n");	3036	dev_alert(gbe_dev->dev,
		3037	"unreleased ethss interfaces present\n");
3027		3038
3028	devm_kfree(gbe_dev->dev, gbe_dev->hw_stats);
3029	devm_iounmap(gbe_dev->dev, gbe_dev->ss_regs);
3030	memset(gbe_dev, 0x00, sizeof(*gbe_dev));
3031	devm_kfree(gbe_dev->dev, gbe_dev);
3032	return 0;	3039	return 0;
3033	}	3040	}
3034		3041

drivers/net/ethernet/ti/netcp_sgmii.c+28−2

@@ -18,6 +18,9 @@ · 17 unmodified lines
18		18
19	#include "netcp.h"	19	#include "netcp.h"
20		20
		21	#define SGMII_SRESET_RESET BIT(0)
		22	#define SGMII_SRESET_RTRESET BIT(1)
		23
21	#define SGMII_REG_STATUS_LOCK BIT(4)	24	#define SGMII_REG_STATUS_LOCK BIT(4)
22	#define SGMII_REG_STATUS_LINK BIT(0)	25	#define SGMII_REG_STATUS_LINK BIT(0)
23	#define SGMII_REG_STATUS_AUTONEG BIT(2)	26	#define SGMII_REG_STATUS_AUTONEG BIT(2)
@@ -51,12 +54,35 @@ static void sgmii_write_reg_bit(void __iomem *base, int reg, u32 val) · 27 unmodified lines
51	int netcp_sgmii_reset(void __iomem *sgmii_ofs, int port)	54	int netcp_sgmii_reset(void __iomem *sgmii_ofs, int port)
52	{	55	{
53	/* Soft reset */	56	/* Soft reset */
54	sgmii_write_reg_bit(sgmii_ofs, SGMII_SRESET_REG(port), 0x1);	57	sgmii_write_reg_bit(sgmii_ofs, SGMII_SRESET_REG(port),
55	while (sgmii_read_reg(sgmii_ofs, SGMII_SRESET_REG(port)) != 0x0)	58	SGMII_SRESET_RESET);
		59
		60	while ((sgmii_read_reg(sgmii_ofs, SGMII_SRESET_REG(port)) &
		61	SGMII_SRESET_RESET) != 0x0)
56	;	62	;
		63
57	return 0;	64	return 0;
58	}	65	}
59		66
		67	/* port is 0 based */
		68	bool netcp_sgmii_rtreset(void __iomem *sgmii_ofs, int port, bool set)
		69	{
		70	u32 reg;
		71	bool oldval;
		72
		73	/* Initiate a soft reset */
		74	reg = sgmii_read_reg(sgmii_ofs, SGMII_SRESET_REG(port));
		75	oldval = (reg & SGMII_SRESET_RTRESET) != 0x0;
		76	if (set)
		77	reg \|= SGMII_SRESET_RTRESET;
		78	else
		79	reg &= ~SGMII_SRESET_RTRESET;
		80	sgmii_write_reg(sgmii_ofs, SGMII_SRESET_REG(port), reg);
		81	wmb();
		82
		83	return oldval;
		84	}
		85
60	int netcp_sgmii_get_port_link(void __iomem *sgmii_ofs, int port)	86	int netcp_sgmii_get_port_link(void __iomem *sgmii_ofs, int port)
61	{	87	{
62	u32 status = 0, link = 0;	88	u32 status = 0, link = 0;

drivers/net/hamradio/mkiss.c+4−3

 	dev->type = ARPHRD_AX25;
 	/* Perform the low-level AX25 initialization. */
-	if ((err = ax_open(ax->dev))) {
+	err = ax_open(ax->dev);
+	if (err)
 		goto out_free_netdev;
-	}
-	if (register_netdev(dev))
+	err = register_netdev(dev);
+	if (err)
 		goto out_free_buffers;
 	/* after register_netdev() - because else printk smashes the kernel */

drivers/net/ipvlan/ipvlan.h+6−3

 	struct ipvl_port	*port;
 	struct net_device	*phy_dev;
 	struct list_head	addrs;
-	int			ipv4cnt;
-	int			ipv6cnt;
 	struct ipvl_pcpu_stats	__percpu *pcpu_stats;
 	DECLARE_BITMAP(mac_filters, IPVLAN_MAC_FILTER_SIZE);
 	netdev_features_t	sfeatures;
 	return rcu_dereference(d->rx_handler_data);
 }
+static inline struct ipvl_port *ipvlan_port_get_rcu_bh(const struct net_device *d)
+{
+	return rcu_dereference_bh(d->rx_handler_data);
+}
 static inline struct ipvl_port *ipvlan_port_get_rtnl(const struct net_device *d)
 {
 	return rtnl_dereference(d->rx_handler_data);
 bool ipvlan_addr_busy(struct ipvl_port *port, void *iaddr, bool is_v6);
 struct ipvl_addr *ipvlan_ht_addr_lookup(const struct ipvl_port *port,
 					const void *iaddr, bool is_v6);
-void ipvlan_ht_addr_del(struct ipvl_addr *addr, bool sync);
+void ipvlan_ht_addr_del(struct ipvl_addr *addr);
 #endif /* __IPVLAN_H */

drivers/net/ipvlan/ipvlan_core.c+2−4

 		hlist_add_head_rcu(&addr->hlnode, &port->hlhead[hash]);
 }
-void ipvlan_ht_addr_del(struct ipvl_addr *addr, bool sync)
+void ipvlan_ht_addr_del(struct ipvl_addr *addr)
 {
 	hlist_del_init_rcu(&addr->hlnode);
-	if (sync)
-		synchronize_rcu();
 }
 struct ipvl_addr *ipvlan_find_addr(const struct ipvl_dev *ipvlan,
 int ipvlan_queue_xmit(struct sk_buff *skb, struct net_device *dev)
 {
 	struct ipvl_dev *ipvlan = netdev_priv(dev);
-	struct ipvl_port *port = ipvlan_port_get_rcu(ipvlan->phy_dev);
+	struct ipvl_port *port = ipvlan_port_get_rcu_bh(ipvlan->phy_dev);
 	if (!port)
 		goto out;

drivers/net/ipvlan/ipvlan_main.c+19−23

@@ -153,10 +153,9 @@ static int ipvlan_open(struct net_device *dev) · 152 unmodified lines
153	else	153	else
154	dev->flags &= ~IFF_NOARP;	154	dev->flags &= ~IFF_NOARP;
155		155
156	if (ipvlan->ipv6cnt > 0 \|\| ipvlan->ipv4cnt > 0) {	156	list_for_each_entry(addr, &ipvlan->addrs, anode)
157	list_for_each_entry(addr, &ipvlan->addrs, anode)	157	ipvlan_ht_addr_add(ipvlan, addr);
158	ipvlan_ht_addr_add(ipvlan, addr);	158
159	}
160	return dev_uc_add(phy_dev, phy_dev->dev_addr);	159	return dev_uc_add(phy_dev, phy_dev->dev_addr);
161	}	160	}
162		161
@@ -171,10 +170,9 @@ static int ipvlan_stop(struct net_device *dev) · 8 unmodified lines
171		170
172	dev_uc_del(phy_dev, phy_dev->dev_addr);	171	dev_uc_del(phy_dev, phy_dev->dev_addr);
173		172
174	if (ipvlan->ipv6cnt > 0 \|\| ipvlan->ipv4cnt > 0) {	173	list_for_each_entry(addr, &ipvlan->addrs, anode)
175	list_for_each_entry(addr, &ipvlan->addrs, anode)	174	ipvlan_ht_addr_del(addr);
176	ipvlan_ht_addr_del(addr, !dev->dismantle);	175
177	}
178	return 0;	176	return 0;
179	}	177	}
180		178
@@ -471,8 +469,6 @@ static int ipvlan_link_new(struct net src_net, struct net_device dev, · 290 unmodified lines
471	ipvlan->port = port;	469	ipvlan->port = port;
472	ipvlan->sfeatures = IPVLAN_FEATURES;	470	ipvlan->sfeatures = IPVLAN_FEATURES;
473	INIT_LIST_HEAD(&ipvlan->addrs);	471	INIT_LIST_HEAD(&ipvlan->addrs);
474	ipvlan->ipv4cnt = 0;
475	ipvlan->ipv6cnt = 0;
476		472
477	/* TODO Probably put random address here to be presented to the	473	/* TODO Probably put random address here to be presented to the
478	* world but keep using the physical-dev address for the outgoing	474	* world but keep using the physical-dev address for the outgoing
@@ -508,12 +504,12 @@ static void ipvlan_link_delete(struct net_device dev, struct list_head head) · 29 unmodified lines
508	struct ipvl_dev *ipvlan = netdev_priv(dev);	504	struct ipvl_dev *ipvlan = netdev_priv(dev);
509	struct ipvl_addr addr, next;	505	struct ipvl_addr addr, next;
510		506
511	if (ipvlan->ipv6cnt > 0 \|\| ipvlan->ipv4cnt > 0) {	507	list_for_each_entry_safe(addr, next, &ipvlan->addrs, anode) {
512	list_for_each_entry_safe(addr, next, &ipvlan->addrs, anode) {	508	ipvlan_ht_addr_del(addr);
513	ipvlan_ht_addr_del(addr, !dev->dismantle);	509	list_del(&addr->anode);
514	list_del(&addr->anode);	510	kfree_rcu(addr, rcu);
515	}
516	}	511	}
		512
517	list_del_rcu(&ipvlan->pnode);	513	list_del_rcu(&ipvlan->pnode);
518	unregister_netdevice_queue(dev, head);	514	unregister_netdevice_queue(dev, head);
519	netdev_upper_dev_unlink(ipvlan->phy_dev, dev);	515	netdev_upper_dev_unlink(ipvlan->phy_dev, dev);
@@ -627,7 +623,7 @@ static int ipvlan_add_addr6(struct ipvl_dev ipvlan, struct in6_addr ip6_addr) · 107 unmodified lines
627	memcpy(&addr->ip6addr, ip6_addr, sizeof(struct in6_addr));	623	memcpy(&addr->ip6addr, ip6_addr, sizeof(struct in6_addr));
628	addr->atype = IPVL_IPV6;	624	addr->atype = IPVL_IPV6;
629	list_add_tail(&addr->anode, &ipvlan->addrs);	625	list_add_tail(&addr->anode, &ipvlan->addrs);
630	ipvlan->ipv6cnt++;	626
631	/* If the interface is not up, the address will be added to the hash	627	/* If the interface is not up, the address will be added to the hash
632	* list by ipvlan_open.	628	* list by ipvlan_open.
633	*/	629	*/
@@ -645,10 +641,8 @@ static void ipvlan_del_addr6(struct ipvl_dev ipvlan, struct in6_addr ip6_addr) · 11 unmodified lines
645	if (!addr)	641	if (!addr)
646	return;	642	return;
647		643
648	ipvlan_ht_addr_del(addr, true);	644	ipvlan_ht_addr_del(addr);
649	list_del(&addr->anode);	645	list_del(&addr->anode);
650	ipvlan->ipv6cnt--;
651	WARN_ON(ipvlan->ipv6cnt < 0);
652	kfree_rcu(addr, rcu);	646	kfree_rcu(addr, rcu);
653		647
654	return;	648	return;
@@ -661,6 +655,10 @@ static int ipvlan_addr6_event(struct notifier_block *unused, · 6 unmodified lines
661	struct net_device dev = (struct net_device )if6->idev->dev;	655	struct net_device dev = (struct net_device )if6->idev->dev;
662	struct ipvl_dev *ipvlan = netdev_priv(dev);	656	struct ipvl_dev *ipvlan = netdev_priv(dev);
663		657
		658	/* FIXME IPv6 autoconf calls us from bh without RTNL */
		659	if (in_softirq())
		660	return NOTIFY_DONE;
		661
664	if (!netif_is_ipvlan(dev))	662	if (!netif_is_ipvlan(dev))
665	return NOTIFY_DONE;	663	return NOTIFY_DONE;
666		664
@@ -699,7 +697,7 @@ static int ipvlan_add_addr4(struct ipvl_dev ipvlan, struct in_addr ip4_addr) · 32 unmodified lines
699	memcpy(&addr->ip4addr, ip4_addr, sizeof(struct in_addr));	697	memcpy(&addr->ip4addr, ip4_addr, sizeof(struct in_addr));
700	addr->atype = IPVL_IPV4;	698	addr->atype = IPVL_IPV4;
701	list_add_tail(&addr->anode, &ipvlan->addrs);	699	list_add_tail(&addr->anode, &ipvlan->addrs);
702	ipvlan->ipv4cnt++;	700
703	/* If the interface is not up, the address will be added to the hash	701	/* If the interface is not up, the address will be added to the hash
704	* list by ipvlan_open.	702	* list by ipvlan_open.
705	*/	703	*/
@@ -717,10 +715,8 @@ static void ipvlan_del_addr4(struct ipvl_dev ipvlan, struct in_addr ip4_addr) · 11 unmodified lines
717	if (!addr)	715	if (!addr)
718	return;	716	return;
719		717
720	ipvlan_ht_addr_del(addr, true);	718	ipvlan_ht_addr_del(addr);
721	list_del(&addr->anode);	719	list_del(&addr->anode);
722	ipvlan->ipv4cnt--;
723	WARN_ON(ipvlan->ipv4cnt < 0);
724	kfree_rcu(addr, rcu);	720	kfree_rcu(addr, rcu);
725		721
726	return;	722	return;

drivers/net/macvtap.c+7−0

 	struct virtio_net_hdr vnet_hdr = { 0 };
 	int vnet_hdr_len = 0;
 	int copylen = 0;
+	int depth;
 	bool zerocopy = false;
 	size_t linear;
 	ssize_t n;
 	skb_probe_transport_header(skb, ETH_HLEN);
+	/* Move network header to the right position for VLAN tagged packets */
+	if ((skb->protocol == htons(ETH_P_8021Q) ||
+	     skb->protocol == htons(ETH_P_8021AD)) &&
+	    __vlan_get_protocol(skb, skb->protocol, &depth) != 0)
+		skb_set_network_header(skb, depth);
 	rcu_read_lock();
 	vlan = rcu_dereference(q->vlan);
 	/* copy skb_ubuf_info for callback when skb has no error */

drivers/net/ntb_netdev.c+8−1

 	netdev_dbg(ndev, "%s: %d byte payload received\n", __func__, len);
+	if (len < 0) {
+		ndev->stats.rx_errors++;
+		ndev->stats.rx_length_errors++;
+		goto enqueue_again;
+	}
 	skb_put(skb, len);
 	skb->protocol = eth_type_trans(skb, ndev);
 	skb->ip_summed = CHECKSUM_NONE;
 		return;
 	}
+enqueue_again:
 	rc = ntb_transport_rx_enqueue(qp, skb, skb->data, ndev->mtu + ETH_HLEN);
 	if (rc) {
 		dev_kfree_skb(skb);
 		rc = ntb_transport_rx_enqueue(dev->qp, skb, skb->data,
 					      ndev->mtu + ETH_HLEN);
-		if (rc == -EINVAL) {
+		if (rc) {
 			dev_kfree_skb(skb);
 			goto err;
 		}

drivers/net/phy/dp83867.c+1−1

@@ -164,7 +164,7 @@ static int dp83867_config_init(struct phy_device *phydev) · 163 unmodified lines
164	return ret;	164	return ret;
165	}	165	}
166		166
167	if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) \|\|	167	if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
168	(phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {	168	(phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
169	val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,	169	val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
170	DP83867_DEVADDR, phydev->addr);	170	DP83867_DEVADDR, phydev->addr);

drivers/net/phy/mdio_bus.c+17−2

@@ -421,6 +421,8 @@ static int mdio_bus_match(struct device dev, struct device_driver drv) · 420 unmodified lines
421	{	421	{
422	struct phy_device *phydev = to_phy_device(dev);	422	struct phy_device *phydev = to_phy_device(dev);
423	struct phy_driver *phydrv = to_phy_driver(drv);	423	struct phy_driver *phydrv = to_phy_driver(drv);
		424	const int num_ids = ARRAY_SIZE(phydev->c45_ids.device_ids);
		425	int i;
424		426
425	if (of_driver_match_device(dev, drv))	427	if (of_driver_match_device(dev, drv))
426	return 1;	428	return 1;
@@ -428,8 +430,21 @@ static int mdio_bus_match(struct device dev, struct device_driver drv) · 1 unmodified line
428	if (phydrv->match_phy_device)	430	if (phydrv->match_phy_device)
429	return phydrv->match_phy_device(phydev);	431	return phydrv->match_phy_device(phydev);
430		432
431	return (phydrv->phy_id & phydrv->phy_id_mask) ==	433	if (phydev->is_c45) {
432	(phydev->phy_id & phydrv->phy_id_mask);	434	for (i = 1; i < num_ids; i++) {
		435	if (!(phydev->c45_ids.devices_in_package & (1 << i)))
		436	continue;
		437
		438	if ((phydrv->phy_id & phydrv->phy_id_mask) ==
		439	(phydev->c45_ids.device_ids[i] &
		440	phydrv->phy_id_mask))
		441	return 1;
		442	}
		443	return 0;
		444	} else {
		445	return (phydrv->phy_id & phydrv->phy_id_mask) ==
		446	(phydev->phy_id & phydrv->phy_id_mask);
		447	}
433	}	448	}
434		449
435	#ifdef CONFIG_PM	450	#ifdef CONFIG_PM

drivers/net/usb/qmi_wwan.c+1−0

@@ -757,6 +757,7 @@ static const struct usb_device_id products[] = { · 756 unmodified lines
757	{QMI_FIXED_INTF(0x1199, 0x901c, 8)}, /* Sierra Wireless EM7700 */	757	{QMI_FIXED_INTF(0x1199, 0x901c, 8)}, /* Sierra Wireless EM7700 */
758	{QMI_FIXED_INTF(0x1199, 0x901f, 8)}, /* Sierra Wireless EM7355 */	758	{QMI_FIXED_INTF(0x1199, 0x901f, 8)}, /* Sierra Wireless EM7355 */
759	{QMI_FIXED_INTF(0x1199, 0x9041, 8)}, /* Sierra Wireless MC7305/MC7355 */	759	{QMI_FIXED_INTF(0x1199, 0x9041, 8)}, /* Sierra Wireless MC7305/MC7355 */
		760	{QMI_FIXED_INTF(0x1199, 0x9041, 10)}, /* Sierra Wireless MC7305/MC7355 */
760	{QMI_FIXED_INTF(0x1199, 0x9051, 8)}, /* Netgear AirCard 340U */	761	{QMI_FIXED_INTF(0x1199, 0x9051, 8)}, /* Netgear AirCard 340U */
761	{QMI_FIXED_INTF(0x1199, 0x9053, 8)}, /* Sierra Wireless Modem */	762	{QMI_FIXED_INTF(0x1199, 0x9053, 8)}, /* Sierra Wireless Modem */
762	{QMI_FIXED_INTF(0x1199, 0x9054, 8)}, /* Sierra Wireless Modem */	763	{QMI_FIXED_INTF(0x1199, 0x9054, 8)}, /* Sierra Wireless Modem */

drivers/net/usb/r8152.c+137−52

@@ -27,7 +27,7 @@ · 26 unmodified lines
27	#include <linux/usb/cdc.h>	27	#include <linux/usb/cdc.h>
28		28
29	/* Version Information */	29	/* Version Information */
30	#define DRIVER_VERSION "v1.08.0 (2015/01/13)"	30	#define DRIVER_VERSION "v1.08.1 (2015/07/28)"
31	#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"	31	#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
32	#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"	32	#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
33	#define MODULENAME "r8152"	33	#define MODULENAME "r8152"
@@ -1902,11 +1902,10 @@ static void rtl_drop_queued_tx(struct r8152 *tp) · 1868 unmodified lines
1902	static void rtl8152_tx_timeout(struct net_device *netdev)	1902	static void rtl8152_tx_timeout(struct net_device *netdev)
1903	{	1903	{
1904	struct r8152 *tp = netdev_priv(netdev);	1904	struct r8152 *tp = netdev_priv(netdev);
1905	int i;
1906		1905
1907	netif_warn(tp, tx_err, netdev, "Tx timeout\n");	1906	netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1908	for (i = 0; i < RTL8152_MAX_TX; i++)	1907
1909	usb_unlink_urb(tp->tx_info[i].urb);	1908	usb_queue_reset_device(tp->intf);
1910	}	1909	}
1911		1910
1912	static void rtl8152_set_rx_mode(struct net_device *netdev)	1911	static void rtl8152_set_rx_mode(struct net_device *netdev)
@@ -2075,7 +2074,6 @@ static int rtl_start_rx(struct r8152 *tp) · 162 unmodified lines
2075	{	2074	{
2076	int i, ret = 0;	2075	int i, ret = 0;
2077		2076
2078	napi_disable(&tp->napi);
2079	INIT_LIST_HEAD(&tp->rx_done);	2077	INIT_LIST_HEAD(&tp->rx_done);
2080	for (i = 0; i < RTL8152_MAX_RX; i++) {	2078	for (i = 0; i < RTL8152_MAX_RX; i++) {
2081	INIT_LIST_HEAD(&tp->rx_info[i].list);	2079	INIT_LIST_HEAD(&tp->rx_info[i].list);
@@ -2083,7 +2081,6 @@ static int rtl_start_rx(struct r8152 *tp) · 1 unmodified line
2083	if (ret)	2081	if (ret)
2084	break;	2082	break;
2085	}	2083	}
2086	napi_enable(&tp->napi);
2087		2084
2088	if (ret && ++i < RTL8152_MAX_RX) {	2085	if (ret && ++i < RTL8152_MAX_RX) {
2089	struct list_head rx_queue;	2086	struct list_head rx_queue;
@@ -2166,6 +2163,7 @@ static int rtl8153_enable(struct r8152 *tp) · 76 unmodified lines
2166	if (test_bit(RTL8152_UNPLUG, &tp->flags))	2163	if (test_bit(RTL8152_UNPLUG, &tp->flags))
2167	return -ENODEV;	2164	return -ENODEV;
2168		2165
		2166	usb_disable_lpm(tp->udev);
2169	set_tx_qlen(tp);	2167	set_tx_qlen(tp);
2170	rtl_set_eee_plus(tp);	2168	rtl_set_eee_plus(tp);
2171	r8153_set_rx_early_timeout(tp);	2169	r8153_set_rx_early_timeout(tp);
@@ -2337,11 +2335,61 @@ static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) · 165 unmodified lines
2337	device_set_wakeup_enable(&tp->udev->dev, false);	2335	device_set_wakeup_enable(&tp->udev->dev, false);
2338	}	2336	}
2339		2337
		2338	static void r8153_u1u2en(struct r8152 *tp, bool enable)
		2339	{
		2340	u8 u1u2[8];
		2341
		2342	if (enable)
		2343	memset(u1u2, 0xff, sizeof(u1u2));
		2344	else
		2345	memset(u1u2, 0x00, sizeof(u1u2));
		2346
		2347	usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
		2348	}
		2349
		2350	static void r8153_u2p3en(struct r8152 *tp, bool enable)
		2351	{
		2352	u32 ocp_data;
		2353
		2354	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
		2355	if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
		2356	ocp_data \|= U2P3_ENABLE;
		2357	else
		2358	ocp_data &= ~U2P3_ENABLE;
		2359	ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
		2360	}
		2361
		2362	static void r8153_power_cut_en(struct r8152 *tp, bool enable)
		2363	{
		2364	u32 ocp_data;
		2365
		2366	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
		2367	if (enable)
		2368	ocp_data \|= PWR_EN \| PHASE2_EN;
		2369	else
		2370	ocp_data &= ~(PWR_EN \| PHASE2_EN);
		2371	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
		2372
		2373	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
		2374	ocp_data &= ~PCUT_STATUS;
		2375	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
		2376	}
		2377
		2378	static bool rtl_can_wakeup(struct r8152 *tp)
		2379	{
		2380	struct usb_device *udev = tp->udev;
		2381
		2382	return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
		2383	}
		2384
2340	static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)	2385	static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2341	{	2386	{
2342	if (enable) {	2387	if (enable) {
2343	u32 ocp_data;	2388	u32 ocp_data;
2344		2389
		2390	r8153_u1u2en(tp, false);
		2391	r8153_u2p3en(tp, false);
		2392
2345	__rtl_set_wol(tp, WAKE_ANY);	2393	__rtl_set_wol(tp, WAKE_ANY);
2346		2394
2347	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);	2395	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
@@ -2353,6 +2401,8 @@ static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) · 5 unmodified lines
2353	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);	2401	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2354	} else {	2402	} else {
2355	__rtl_set_wol(tp, tp->saved_wolopts);	2403	__rtl_set_wol(tp, tp->saved_wolopts);
		2404	r8153_u2p3en(tp, true);
		2405	r8153_u1u2en(tp, true);
2356	}	2406	}
2357	}	2407	}
2358		2408
@@ -2599,46 +2649,6 @@ static void r8153_hw_phy_cfg(struct r8152 *tp) · 240 unmodified lines
2599	set_bit(PHY_RESET, &tp->flags);	2649	set_bit(PHY_RESET, &tp->flags);
2600	}	2650	}
2601		2651
2602	static void r8153_u1u2en(struct r8152 *tp, bool enable)
2603	{
2604	u8 u1u2[8];
2605
2606	if (enable)
2607	memset(u1u2, 0xff, sizeof(u1u2));
2608	else
2609	memset(u1u2, 0x00, sizeof(u1u2));
2610
2611	usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2612	}
2613
2614	static void r8153_u2p3en(struct r8152 *tp, bool enable)
2615	{
2616	u32 ocp_data;
2617
2618	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2619	if (enable)
2620	ocp_data \|= U2P3_ENABLE;
2621	else
2622	ocp_data &= ~U2P3_ENABLE;
2623	ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2624	}
2625
2626	static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2627	{
2628	u32 ocp_data;
2629
2630	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2631	if (enable)
2632	ocp_data \|= PWR_EN \| PHASE2_EN;
2633	else
2634	ocp_data &= ~(PWR_EN \| PHASE2_EN);
2635	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2636
2637	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2638	ocp_data &= ~PCUT_STATUS;
2639	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2640	}
2641
2642	static void r8153_first_init(struct r8152 *tp)	2652	static void r8153_first_init(struct r8152 *tp)
2643	{	2653	{
2644	u32 ocp_data;	2654	u32 ocp_data;
@@ -2781,6 +2791,7 @@ static void rtl8153_disable(struct r8152 *tp) · 136 unmodified lines
2781	r8153_disable_aldps(tp);	2791	r8153_disable_aldps(tp);
2782	rtl_disable(tp);	2792	rtl_disable(tp);
2783	r8153_enable_aldps(tp);	2793	r8153_enable_aldps(tp);
		2794	usb_enable_lpm(tp->udev);
2784	}	2795	}
2785		2796
2786	static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)	2797	static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
@@ -2901,9 +2912,13 @@ static void rtl8153_up(struct r8152 *tp) · 114 unmodified lines
2901	if (test_bit(RTL8152_UNPLUG, &tp->flags))	2912	if (test_bit(RTL8152_UNPLUG, &tp->flags))
2902	return;	2913	return;
2903		2914
		2915	r8153_u1u2en(tp, false);
2904	r8153_disable_aldps(tp);	2916	r8153_disable_aldps(tp);
2905	r8153_first_init(tp);	2917	r8153_first_init(tp);
2906	r8153_enable_aldps(tp);	2918	r8153_enable_aldps(tp);
		2919	r8153_u2p3en(tp, true);
		2920	r8153_u1u2en(tp, true);
		2921	usb_enable_lpm(tp->udev);
2907	}	2922	}
2908		2923
2909	static void rtl8153_down(struct r8152 *tp)	2924	static void rtl8153_down(struct r8152 *tp)
@@ -2914,6 +2929,7 @@ static void rtl8153_down(struct r8152 *tp) · 4 unmodified lines
2914	}	2929	}
2915		2930
2916	r8153_u1u2en(tp, false);	2931	r8153_u1u2en(tp, false);
		2932	r8153_u2p3en(tp, false);
2917	r8153_power_cut_en(tp, false);	2933	r8153_power_cut_en(tp, false);
2918	r8153_disable_aldps(tp);	2934	r8153_disable_aldps(tp);
2919	r8153_enter_oob(tp);	2935	r8153_enter_oob(tp);
@@ -2932,8 +2948,10 @@ static void set_carrier(struct r8152 *tp) · 12 unmodified lines
2932	if (!netif_carrier_ok(netdev)) {	2948	if (!netif_carrier_ok(netdev)) {
2933	tp->rtl_ops.enable(tp);	2949	tp->rtl_ops.enable(tp);
2934	set_bit(RTL8152_SET_RX_MODE, &tp->flags);	2950	set_bit(RTL8152_SET_RX_MODE, &tp->flags);
		2951	napi_disable(&tp->napi);
2935	netif_carrier_on(netdev);	2952	netif_carrier_on(netdev);
2936	rtl_start_rx(tp);	2953	rtl_start_rx(tp);
		2954	napi_enable(&tp->napi);
2937	}	2955	}
2938	} else {	2956	} else {
2939	if (netif_carrier_ok(netdev)) {	2957	if (netif_carrier_ok(netdev)) {
@@ -3252,6 +3270,7 @@ static void r8153_init(struct r8152 *tp) · 312 unmodified lines
3252	msleep(20);	3270	msleep(20);
3253	}	3271	}
3254		3272
		3273	usb_disable_lpm(tp->udev);
3255	r8153_u2p3en(tp, false);	3274	r8153_u2p3en(tp, false);
3256		3275
3257	if (tp->version == RTL_VER_04) {	3276	if (tp->version == RTL_VER_04) {
@@ -3319,6 +3338,59 @@ static void r8153_init(struct r8152 *tp) · 61 unmodified lines
3319	r8153_enable_aldps(tp);	3338	r8153_enable_aldps(tp);
3320	r8152b_enable_fc(tp);	3339	r8152b_enable_fc(tp);
3321	rtl_tally_reset(tp);	3340	rtl_tally_reset(tp);
		3341	r8153_u2p3en(tp, true);
		3342	}
		3343
		3344	static int rtl8152_pre_reset(struct usb_interface *intf)
		3345	{
		3346	struct r8152 *tp = usb_get_intfdata(intf);
		3347	struct net_device *netdev;
		3348
		3349	if (!tp)
		3350	return 0;
		3351
		3352	netdev = tp->netdev;
		3353	if (!netif_running(netdev))
		3354	return 0;
		3355
		3356	napi_disable(&tp->napi);
		3357	clear_bit(WORK_ENABLE, &tp->flags);
		3358	usb_kill_urb(tp->intr_urb);
		3359	cancel_delayed_work_sync(&tp->schedule);
		3360	if (netif_carrier_ok(netdev)) {
		3361	netif_stop_queue(netdev);
		3362	mutex_lock(&tp->control);
		3363	tp->rtl_ops.disable(tp);
		3364	mutex_unlock(&tp->control);
		3365	}
		3366
		3367	return 0;
		3368	}
		3369
		3370	static int rtl8152_post_reset(struct usb_interface *intf)
		3371	{
		3372	struct r8152 *tp = usb_get_intfdata(intf);
		3373	struct net_device *netdev;
		3374
		3375	if (!tp)
		3376	return 0;
		3377
		3378	netdev = tp->netdev;
		3379	if (!netif_running(netdev))
		3380	return 0;
		3381
		3382	set_bit(WORK_ENABLE, &tp->flags);
		3383	if (netif_carrier_ok(netdev)) {
		3384	mutex_lock(&tp->control);
		3385	tp->rtl_ops.enable(tp);
		3386	rtl8152_set_rx_mode(netdev);
		3387	mutex_unlock(&tp->control);
		3388	netif_wake_queue(netdev);
		3389	}
		3390
		3391	napi_enable(&tp->napi);
		3392
		3393	return 0;
3322	}	3394	}
3323		3395
3324	static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)	3396	static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
@@ -3374,9 +3446,11 @@ static int rtl8152_resume(struct usb_interface *intf) · 49 unmodified lines
3374	if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {	3446	if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3375	rtl_runtime_suspend_enable(tp, false);	3447	rtl_runtime_suspend_enable(tp, false);
3376	clear_bit(SELECTIVE_SUSPEND, &tp->flags);	3448	clear_bit(SELECTIVE_SUSPEND, &tp->flags);
		3449	napi_disable(&tp->napi);
3377	set_bit(WORK_ENABLE, &tp->flags);	3450	set_bit(WORK_ENABLE, &tp->flags);
3378	if (netif_carrier_ok(tp->netdev))	3451	if (netif_carrier_ok(tp->netdev))
3379	rtl_start_rx(tp);	3452	rtl_start_rx(tp);
		3453	napi_enable(&tp->napi);
3380	} else {	3454	} else {
3381	tp->rtl_ops.up(tp);	3455	tp->rtl_ops.up(tp);
3382	rtl8152_set_speed(tp, AUTONEG_ENABLE,	3456	rtl8152_set_speed(tp, AUTONEG_ENABLE,
@@ -3403,12 +3477,15 @@ static void rtl8152_get_wol(struct net_device dev, struct ethtool_wolinfo wol) · 20 unmodified lines
3403	if (usb_autopm_get_interface(tp->intf) < 0)	3477	if (usb_autopm_get_interface(tp->intf) < 0)
3404	return;	3478	return;
3405		3479
3406	mutex_lock(&tp->control);	3480	if (!rtl_can_wakeup(tp)) {
3407		3481	wol->supported = 0;
3408	wol->supported = WAKE_ANY;	3482	wol->wolopts = 0;
3409	wol->wolopts = __rtl_get_wol(tp);	3483	} else {
3410		3484	mutex_lock(&tp->control);
3411	mutex_unlock(&tp->control);	3485	wol->supported = WAKE_ANY;
		3486	wol->wolopts = __rtl_get_wol(tp);
		3487	mutex_unlock(&tp->control);
		3488	}
3412		3489
3413	usb_autopm_put_interface(tp->intf);	3490	usb_autopm_put_interface(tp->intf);
3414	}	3491	}
@@ -3418,6 +3495,9 @@ static int rtl8152_set_wol(struct net_device dev, struct ethtool_wolinfo wol) · 3 unmodified lines
3418	struct r8152 *tp = netdev_priv(dev);	3495	struct r8152 *tp = netdev_priv(dev);
3419	int ret;	3496	int ret;
3420		3497
		3498	if (!rtl_can_wakeup(tp))
		3499	return -EOPNOTSUPP;
		3500
3421	ret = usb_autopm_get_interface(tp->intf);	3501	ret = usb_autopm_get_interface(tp->intf);
3422	if (ret < 0)	3502	if (ret < 0)
3423	goto out_set_wol;	3503	goto out_set_wol;
@@ -4059,6 +4139,9 @@ static int rtl8152_probe(struct usb_interface *intf, · 635 unmodified lines
4059	goto out1;	4139	goto out1;
4060	}	4140	}
4061		4141
		4142	if (!rtl_can_wakeup(tp))
		4143	__rtl_set_wol(tp, 0);
		4144
4062	tp->saved_wolopts = __rtl_get_wol(tp);	4145	tp->saved_wolopts = __rtl_get_wol(tp);
4063	if (tp->saved_wolopts)	4146	if (tp->saved_wolopts)
4064	device_set_wakeup_enable(&udev->dev, true);	4147	device_set_wakeup_enable(&udev->dev, true);
@@ -4132,6 +4215,8 @@ static struct usb_driver rtl8152_driver = { · 67 unmodified lines
4132	.suspend = rtl8152_suspend,	4215	.suspend = rtl8152_suspend,
4133	.resume = rtl8152_resume,	4216	.resume = rtl8152_resume,
4134	.reset_resume = rtl8152_resume,	4217	.reset_resume = rtl8152_resume,
		4218	.pre_reset = rtl8152_pre_reset,
		4219	.post_reset = rtl8152_post_reset,
4135	.supports_autosuspend = 1,	4220	.supports_autosuspend = 1,
4136	.disable_hub_initiated_lpm = 1,	4221	.disable_hub_initiated_lpm = 1,
4137	};	4222	};

drivers/net/virtio_net.c+4−3

 	/* Do we support "hardware" checksums? */
 	if (virtio_has_feature(vdev, VIRTIO_NET_F_CSUM)) {
 		/* This opens up the world of extra features. */
-		dev->hw_features |= NETIF_F_HW_CSUM|NETIF_F_SG|NETIF_F_FRAGLIST;
+		dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_SG;
 		if (csum)
-			dev->features |= NETIF_F_HW_CSUM|NETIF_F_SG|NETIF_F_FRAGLIST;
+			dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
 		if (virtio_has_feature(vdev, VIRTIO_NET_F_GSO)) {
 			dev->hw_features |= NETIF_F_TSO | NETIF_F_UFO
 	else
 		vi->hdr_len = sizeof(struct virtio_net_hdr);
-	if (virtio_has_feature(vdev, VIRTIO_F_ANY_LAYOUT))
+	if (virtio_has_feature(vdev, VIRTIO_F_ANY_LAYOUT) ||
+	    virtio_has_feature(vdev, VIRTIO_F_VERSION_1))
 		vi->any_header_sg = true;
 	if (virtio_has_feature(vdev, VIRTIO_NET_F_CTRL_VQ))

drivers/net/wan/cosa.c+2−1

 		chan->netdev->base_addr = chan->cosa->datareg;
 		chan->netdev->irq = chan->cosa->irq;
 		chan->netdev->dma = chan->cosa->dma;
-		if (register_hdlc_device(chan->netdev)) {
+		err = register_hdlc_device(chan->netdev);
+		if (err) {
 			netdev_warn(chan->netdev,
 				    "register_hdlc_device() failed\n");
 			free_netdev(chan->netdev);

drivers/net/wireless/ath/ath9k/hw.c+1−0

@@ -279,6 +279,7 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah) · 278 unmodified lines
279	return;	279	return;
280	case AR9300_DEVID_QCA956X:	280	case AR9300_DEVID_QCA956X:
281	ah->hw_version.macVersion = AR_SREV_VERSION_9561;	281	ah->hw_version.macVersion = AR_SREV_VERSION_9561;
		282	return;
282	}	283	}
283		284
284	val = REG_READ(ah, AR_SREV) & AR_SREV_ID;	285	val = REG_READ(ah, AR_SREV) & AR_SREV_ID;

drivers/net/wireless/b43/tables_nphy.c+1−1

@@ -3728,7 +3728,7 @@ const u32 b43_nphy_get_tx_gain_table(struct b43_wldev dev) · 3727 unmodified lines
3728	switch (phy->rev) {	3728	switch (phy->rev) {
3729	case 6:	3729	case 6:
3730	case 5:	3730	case 5:
3731	if (sprom->fem.ghz5.extpa_gain == 3)	3731	if (sprom->fem.ghz2.extpa_gain == 3)
3732	return b43_ntab_tx_gain_epa_rev3_hi_pwr_2g;	3732	return b43_ntab_tx_gain_epa_rev3_hi_pwr_2g;
3733	/* fall through */	3733	/* fall through */
3734	case 4:	3734	case 4:

drivers/net/wireless/iwlwifi/iwl-fh.h+6−0

 #define RX_QUEUE_MASK                         255
 #define RX_QUEUE_SIZE_LOG                     8
+/*
+ * RX related structures and functions
+ */
+#define RX_FREE_BUFFERS 64
+#define RX_LOW_WATERMARK 8
 /**
  * struct iwl_rb_status - reserve buffer status
  * 	host memory mapped FH registers

drivers/net/wireless/iwlwifi/iwl-nvm-parse.c+5−7

@@ -540,13 +540,11 @@ static void iwl_set_hw_address_family_8000(struct device *dev, · 539 unmodified lines
540	hw_addr = (const u8 *)(mac_override +	540	hw_addr = (const u8 *)(mac_override +
541	MAC_ADDRESS_OVERRIDE_FAMILY_8000);	541	MAC_ADDRESS_OVERRIDE_FAMILY_8000);
542		542
543	/* The byte order is little endian 16 bit, meaning 214365 */	543	/*
544	data->hw_addr[0] = hw_addr[1];	544	* Store the MAC address from MAO section.
545	data->hw_addr[1] = hw_addr[0];	545	* No byte swapping is required in MAO section
546	data->hw_addr[2] = hw_addr[3];	546	*/
547	data->hw_addr[3] = hw_addr[2];	547	memcpy(data->hw_addr, hw_addr, ETH_ALEN);
548	data->hw_addr[4] = hw_addr[5];
549	data->hw_addr[5] = hw_addr[4];
550		548
551	/*	549	/*
552	* Force the use of the OTP MAC address in case of reserved MAC	550	* Force the use of the OTP MAC address in case of reserved MAC

drivers/net/wireless/iwlwifi/mvm/fw-api-scan.h+2−1

  * iwl_umac_scan_flags
  *@IWL_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request
  *	can be preempted by other scan requests with higher priority.
- *	The low priority scan is aborted.
+ *	The low priority scan will be resumed when the higher proirity scan is
+ *	completed.
  *@IWL_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver
  *	when scan starts.
  */

drivers/net/wireless/iwlwifi/mvm/scan.c+4−1

 	cmd->scan_priority =
 		iwl_mvm_scan_priority(mvm, IWL_SCAN_PRIORITY_EXT_6);
-	if (iwl_mvm_scan_total_iterations(params) == 0)
+	if (iwl_mvm_scan_total_iterations(params) == 1)
 		cmd->ooc_priority =
 			iwl_mvm_scan_priority(mvm, IWL_SCAN_PRIORITY_EXT_6);
 	else
 	cmd->uid = cpu_to_le32(uid);
 	cmd->general_flags = cpu_to_le32(iwl_mvm_scan_umac_flags(mvm, params));
+	if (type == IWL_MVM_SCAN_SCHED)
+		cmd->flags = cpu_to_le32(IWL_UMAC_SCAN_FLAG_PREEMPTIVE);
 	if (iwl_mvm_scan_use_ebs(mvm, vif, n_iterations))
 		cmd->channel_flags = IWL_SCAN_CHANNEL_FLAG_EBS |
 				     IWL_SCAN_CHANNEL_FLAG_EBS_ACCURATE |

drivers/net/wireless/iwlwifi/mvm/sta.c+2−1

 	bool mcast = !(keyconf->flags & IEEE80211_KEY_FLAG_PAIRWISE);
 	u8 sta_id;
 	int ret;
+	static const u8 __maybe_unused zero_addr[ETH_ALEN] = {0};
 	lockdep_assert_held(&mvm->mutex);
 end:
 	IWL_DEBUG_WEP(mvm, "key: cipher=%x len=%d idx=%d sta=%pM ret=%d\n",
 		      keyconf->cipher, keyconf->keylen, keyconf->keyidx,
-		      sta->addr, ret);
+		      sta ? sta->addr : zero_addr, ret);
 	return ret;
 }

drivers/net/wireless/iwlwifi/mvm/time-event.c+1−1

@@ -86,7 +86,7 @@ void iwl_mvm_te_clear_data(struct iwl_mvm *mvm, · 85 unmodified lines
86	{	86	{
87	lockdep_assert_held(&mvm->time_event_lock);	87	lockdep_assert_held(&mvm->time_event_lock);
88		88
89	if (te_data->id == TE_MAX)	89	if (!te_data->vif)
90	return;	90	return;
91		91
92	list_del(&te_data->list);	92	list_del(&te_data->list);

drivers/net/wireless/iwlwifi/mvm/tx.c+1−1

@@ -252,7 +252,7 @@ void iwl_mvm_set_tx_cmd_rate(struct iwl_mvm mvm, struct iwl_tx_cmd tx_cmd, · 251 unmodified lines
252		252
253	if (info->band == IEEE80211_BAND_2GHZ &&	253	if (info->band == IEEE80211_BAND_2GHZ &&
254	!iwl_mvm_bt_coex_is_shared_ant_avail(mvm))	254	!iwl_mvm_bt_coex_is_shared_ant_avail(mvm))
255	rate_flags = BIT(mvm->cfg->non_shared_ant) << RATE_MCS_ANT_POS;	255	rate_flags = mvm->cfg->non_shared_ant << RATE_MCS_ANT_POS;
256	else	256	else
257	rate_flags =	257	rate_flags =
258	BIT(mvm->mgmt_last_antenna_idx) << RATE_MCS_ANT_POS;	258	BIT(mvm->mgmt_last_antenna_idx) << RATE_MCS_ANT_POS;

drivers/net/wireless/iwlwifi/pcie/drv.c+3−2

 /* 3165 Series */
 	{IWL_PCI_DEVICE(0x3165, 0x4010, iwl3165_2ac_cfg)},
 	{IWL_PCI_DEVICE(0x3165, 0x4012, iwl3165_2ac_cfg)},
+	{IWL_PCI_DEVICE(0x3166, 0x4212, iwl3165_2ac_cfg)},
 	{IWL_PCI_DEVICE(0x3165, 0x4410, iwl3165_2ac_cfg)},
 	{IWL_PCI_DEVICE(0x3165, 0x4510, iwl3165_2ac_cfg)},
 	{IWL_PCI_DEVICE(0x3165, 0x4110, iwl3165_2ac_cfg)},
 	{IWL_PCI_DEVICE(0x3166, 0x4310, iwl3165_2ac_cfg)},
 	{IWL_PCI_DEVICE(0x3166, 0x4210, iwl3165_2ac_cfg)},
 	{IWL_PCI_DEVICE(0x3165, 0x8010, iwl3165_2ac_cfg)},
+	{IWL_PCI_DEVICE(0x3165, 0x8110, iwl3165_2ac_cfg)},
 /* 7265 Series */
 	{IWL_PCI_DEVICE(0x095A, 0x5010, iwl7265_2ac_cfg)},
 	{IWL_PCI_DEVICE(0x24F4, 0x1130, iwl8260_2ac_cfg)},
 	{IWL_PCI_DEVICE(0x24F4, 0x1030, iwl8260_2ac_cfg)},
 	{IWL_PCI_DEVICE(0x24F3, 0xC010, iwl8260_2ac_cfg)},
+	{IWL_PCI_DEVICE(0x24F3, 0xC110, iwl8260_2ac_cfg)},
 	{IWL_PCI_DEVICE(0x24F3, 0xD010, iwl8260_2ac_cfg)},
-	{IWL_PCI_DEVICE(0x24F4, 0xC030, iwl8260_2ac_cfg)},
-	{IWL_PCI_DEVICE(0x24F4, 0xD030, iwl8260_2ac_cfg)},
 	{IWL_PCI_DEVICE(0x24F3, 0xC050, iwl8260_2ac_cfg)},
 	{IWL_PCI_DEVICE(0x24F3, 0xD050, iwl8260_2ac_cfg)},
 	{IWL_PCI_DEVICE(0x24F3, 0x8010, iwl8260_2ac_cfg)},

drivers/net/wireless/iwlwifi/pcie/internal.h+8−43

 #include "iwl-io.h"
 #include "iwl-op-mode.h"
-/*
- * RX related structures and functions
- */
-#define RX_NUM_QUEUES 1
-#define RX_POST_REQ_ALLOC 2
-#define RX_CLAIM_REQ_ALLOC 8
-#define RX_POOL_SIZE ((RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC) * RX_NUM_QUEUES)
-#define RX_LOW_WATERMARK 8
 struct iwl_host_cmd;
 /*This file includes the declaration that are internal to the
  * struct iwl_rxq - Rx queue
  * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
  * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
+ * @pool:
+ * @queue:
  * @read: Shared index to newest available Rx buffer
  * @write: Shared index to oldest written Rx packet
  * @free_count: Number of pre-allocated buffers in rx_free
- * @used_count: Number of RBDs handled to allocator to use for allocation
  * @write_actual:
- * @rx_free: list of RBDs with allocated RB ready for use
+ * @rx_free: list of free SKBs for use
- * @rx_used: list of RBDs with no RB attached
+ * @rx_used: List of Rx buffers with no SKB
  * @need_update: flag to indicate we need to update read/write index
  * @rb_stts: driver's pointer to receive buffer status
  * @rb_stts_dma: bus address of receive buffer status
  * @lock:
- * @pool: initial pool of iwl_rx_mem_buffer for the queue
- * @queue: actual rx queue
  *
  * NOTE:  rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
  */
 struct iwl_rxq {
 	__le32 *bd;
 	dma_addr_t bd_dma;
+	struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
+	struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
 	u32 read;
 	u32 write;
 	u32 free_count;
-	u32 used_count;
 	u32 write_actual;
 	struct list_head rx_free;
 	struct list_head rx_used;
 	struct iwl_rb_status *rb_stts;
 	dma_addr_t rb_stts_dma;
 	spinlock_t lock;
-	struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE];
-	struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
-};
-/**
- * struct iwl_rb_allocator - Rx allocator
- * @pool: initial pool of allocator
- * @req_pending: number of requests the allcator had not processed yet
- * @req_ready: number of requests honored and ready for claiming
- * @rbd_allocated: RBDs with pages allocated and ready to be handled to
- *	the queue. This is a list of &struct iwl_rx_mem_buffer
- * @rbd_empty: RBDs with no page attached for allocator use. This is a list
- *	of &struct iwl_rx_mem_buffer
- * @lock: protects the rbd_allocated and rbd_empty lists
- * @alloc_wq: work queue for background calls
- * @rx_alloc: work struct for background calls
- */
-struct iwl_rb_allocator {
-	struct iwl_rx_mem_buffer pool[RX_POOL_SIZE];
-	atomic_t req_pending;
-	atomic_t req_ready;
-	struct list_head rbd_allocated;
-	struct list_head rbd_empty;
-	spinlock_t lock;
-	struct workqueue_struct *alloc_wq;
-	struct work_struct rx_alloc;
 };
 struct iwl_dma_ptr {
 /**
  * struct iwl_trans_pcie - PCIe transport specific data
  * @rxq: all the RX queue data
- * @rba: allocator for RX replenishing
+ * @rx_replenish: work that will be called when buffers need to be allocated
  * @drv - pointer to iwl_drv
  * @trans: pointer to the generic transport area
  * @scd_base_addr: scheduler sram base address in SRAM
  */
 struct iwl_trans_pcie {
 	struct iwl_rxq rxq;
-	struct iwl_rb_allocator rba;
+	struct work_struct rx_replenish;
 	struct iwl_trans *trans;
 	struct iwl_drv *drv;

drivers/net/wireless/iwlwifi/pcie/rx.c+83−331

@@ -1,7 +1,7 @@
1	/******************************************************************************	1	/******************************************************************************
2	*	2	*
3	* Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.	3	* Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
4	* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH	4	* Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
5	*	5	*
6	* Portions of this file are derived from the ipw3945 project, as well	6	* Portions of this file are derived from the ipw3945 project, as well
7	* as portions of the ieee80211 subsystem header files.	7	* as portions of the ieee80211 subsystem header files.
@@ -74,29 +74,16 @@ · 66 unmodified lines
74	* resets the Rx queue buffers with new memory.	74	* resets the Rx queue buffers with new memory.
75	*	75	*
76	* The management in the driver is as follows:	76	* The management in the driver is as follows:
77	* + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free.	77	* + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
78	* When the interrupt handler is called, the request is processed.	78	* iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
79	* The page is either stolen - transferred to the upper layer	79	* to replenish the iwl->rxq->rx_free.
80	* or reused - added immediately to the iwl->rxq->rx_free list.	80	* + In iwl_pcie_rx_replenish (scheduled) if 'processed' != 'read' then the
81	* + When the page is stolen - the driver updates the matching queue's used	81	* iwl->rxq is replenished and the READ INDEX is updated (updating the
82	* count, detaches the RBD and transfers it to the queue used list.	82	* 'processed' and 'read' driver indexes as well)
83	* When there are two used RBDs - they are transferred to the allocator empty
84	* list. Work is then scheduled for the allocator to start allocating
85	* eight buffers.
86	* When there are another 6 used RBDs - they are transferred to the allocator
87	* empty list and the driver tries to claim the pre-allocated buffers and
88	* add them to iwl->rxq->rx_free. If it fails - it continues to claim them
89	* until ready.
90	* When there are 8+ buffers in the free list - either from allocation or from
91	* 8 reused unstolen pages - restock is called to update the FW and indexes.
92	* + In order to make sure the allocator always has RBDs to use for allocation
93	* the allocator has initial pool in the size of num_queues*(8-2) - the
94	* maximum missing RBDs per allocation request (request posted with 2
95	* empty RBDs, there is no guarantee when the other 6 RBDs are supplied).
96	* The queues supplies the recycle of the rest of the RBDs.
97	* + A received packet is processed and handed to the kernel network stack,	83	* + A received packet is processed and handed to the kernel network stack,
98	* detached from the iwl->rxq. The driver 'processed' index is updated.	84	* detached from the iwl->rxq. The driver 'processed' index is updated.
99	* + If there are no allocated buffers in iwl->rxq->rx_free,	85	* + The Host/Firmware iwl->rxq is replenished at irq thread time from the
		86	* rx_free list. If there are no allocated buffers in iwl->rxq->rx_free,
100	* the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.	87	* the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.
101	* If there were enough free buffers and RX_STALLED is set it is cleared.	88	* If there were enough free buffers and RX_STALLED is set it is cleared.
102	*	89	*
@@ -105,32 +92,18 @@ · 2 unmodified lines
105	*	92	*
106	* iwl_rxq_alloc() Allocates rx_free	93	* iwl_rxq_alloc() Allocates rx_free
107	* iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls	94	* iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls
108	* iwl_pcie_rxq_restock.	95	* iwl_pcie_rxq_restock
109	* Used only during initialization.
110	* iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx	96	* iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx
111	* queue, updates firmware pointers, and updates	97	* queue, updates firmware pointers, and updates
112	* the WRITE index.	98	* the WRITE index. If insufficient rx_free buffers
113	* iwl_pcie_rx_allocator() Background work for allocating pages.	99	* are available, schedules iwl_pcie_rx_replenish
114	*	100	*
115	* -- enable interrupts --	101	* -- enable interrupts --
116	* ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the	102	* ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
117	* READ INDEX, detaching the SKB from the pool.	103	* READ INDEX, detaching the SKB from the pool.
118	* Moves the packet buffer from queue to rx_used.	104	* Moves the packet buffer from queue to rx_used.
119	* Posts and claims requests to the allocator.
120	* Calls iwl_pcie_rxq_restock to refill any empty	105	* Calls iwl_pcie_rxq_restock to refill any empty
121	* slots.	106	* slots.
122	*
123	* RBD life-cycle:
124	*
125	* Init:
126	* rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue
127	*
128	* Regular Receive interrupt:
129	* Page Stolen:
130	* rxq.queue -> rxq.rx_used -> allocator.rbd_empty ->
131	* allocator.rbd_allocated -> rxq.rx_free -> rxq.queue
132	* Page not Stolen:
133	* rxq.queue -> rxq.rx_free -> rxq.queue
134	* ...	107	* ...
135	*	108	*
136	*/	109	*/
@@ -267,6 +240,10 @@ static void iwl_pcie_rxq_restock(struct iwl_trans *trans) · 130 unmodified lines
267	rxq->free_count--;	240	rxq->free_count--;
268	}	241	}
269	spin_unlock(&rxq->lock);	242	spin_unlock(&rxq->lock);
		243	/* If the pre-allocated buffer pool is dropping low, schedule to
		244	* refill it */
		245	if (rxq->free_count <= RX_LOW_WATERMARK)
		246	schedule_work(&trans_pcie->rx_replenish);
270		247
271	/* If we've added more space for the firmware to place data, tell it.	248	/* If we've added more space for the firmware to place data, tell it.
272	* Increment device's write pointer in multiples of 8. */	249	* Increment device's write pointer in multiples of 8. */
@@ -277,44 +254,6 @@ static void iwl_pcie_rxq_restock(struct iwl_trans *trans) · 4 unmodified lines
277	}	254	}
278	}	255	}
279		256
280	/*
281	* iwl_pcie_rx_alloc_page - allocates and returns a page.
282	*
283	*/
284	static struct page iwl_pcie_rx_alloc_page(struct iwl_trans trans)
285	{
286	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
287	struct iwl_rxq *rxq = &trans_pcie->rxq;
288	struct page *page;
289	gfp_t gfp_mask = GFP_KERNEL;
290
291	if (rxq->free_count > RX_LOW_WATERMARK)
292	gfp_mask \|= __GFP_NOWARN;
293
294	if (trans_pcie->rx_page_order > 0)
295	gfp_mask \|= __GFP_COMP;
296
297	/* Alloc a new receive buffer */
298	page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
299	if (!page) {
300	if (net_ratelimit())
301	IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n",
302	trans_pcie->rx_page_order);
303	/* Issue an error if the hardware has consumed more than half
304	* of its free buffer list and we don't have enough
305	* pre-allocated buffers.
306	` */
307	if (rxq->free_count <= RX_LOW_WATERMARK &&
308	iwl_rxq_space(rxq) > (RX_QUEUE_SIZE / 2) &&
309	net_ratelimit())
310	IWL_CRIT(trans,
311	"Failed to alloc_pages with GFP_KERNEL. Only %u free buffers remaining.\n",
312	rxq->free_count);
313	return NULL;
314	}
315	return page;
316	}
317
318	/*	257	/*
319	* iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD	258	* iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
320	*	259	*
@@ -324,12 +263,13 @@ static struct page iwl_pcie_rx_alloc_page(struct iwl_trans trans) · 3 unmodified lines
324	* iwl_pcie_rxq_restock. The latter function will update the HW to use the newly	263	* iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
325	* allocated buffers.	264	* allocated buffers.
326	*/	265	*/
327	static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans)	266	static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority)
328	{	267	{
329	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);	268	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
330	struct iwl_rxq *rxq = &trans_pcie->rxq;	269	struct iwl_rxq *rxq = &trans_pcie->rxq;
331	struct iwl_rx_mem_buffer *rxb;	270	struct iwl_rx_mem_buffer *rxb;
332	struct page *page;	271	struct page *page;
		272	gfp_t gfp_mask = priority;
333		273
334	while (1) {	274	while (1) {
335	spin_lock(&rxq->lock);	275	spin_lock(&rxq->lock);
@@ -339,10 +279,32 @@ static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans) · 3 unmodified lines
339	}	279	}
340	spin_unlock(&rxq->lock);	280	spin_unlock(&rxq->lock);
341		281
		282	if (rxq->free_count > RX_LOW_WATERMARK)
		283	gfp_mask \|= __GFP_NOWARN;
		284
		285	if (trans_pcie->rx_page_order > 0)
		286	gfp_mask \|= __GFP_COMP;
		287
342	/* Alloc a new receive buffer */	288	/* Alloc a new receive buffer */
343	page = iwl_pcie_rx_alloc_page(trans);	289	page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
344	if (!page)	290	if (!page) {
		291	if (net_ratelimit())
		292	IWL_DEBUG_INFO(trans, "alloc_pages failed, "
		293	"order: %d\n",
		294	trans_pcie->rx_page_order);
		295
		296	if ((rxq->free_count <= RX_LOW_WATERMARK) &&
		297	net_ratelimit())
		298	IWL_CRIT(trans, "Failed to alloc_pages with %s."
		299	"Only %u free buffers remaining.\n",
		300	priority == GFP_ATOMIC ?
		301	"GFP_ATOMIC" : "GFP_KERNEL",
		302	rxq->free_count);
		303	/* We don't reschedule replenish work here -- we will
		304	* call the restock method and if it still needs
		305	* more buffers it will schedule replenish */
345	return;	306	return;
		307	}
346		308
347	spin_lock(&rxq->lock);	309	spin_lock(&rxq->lock);
348		310
@@ -393,7 +355,7 @@ static void iwl_pcie_rxq_free_rbs(struct iwl_trans *trans) · 44 unmodified lines
393		355
394	lockdep_assert_held(&rxq->lock);	356	lockdep_assert_held(&rxq->lock);
395		357
396	for (i = 0; i < RX_QUEUE_SIZE; i++) {	358	for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
397	if (!rxq->pool[i].page)	359	if (!rxq->pool[i].page)
398	continue;	360	continue;
399	dma_unmap_page(trans->dev, rxq->pool[i].page_dma,	361	dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
@@ -410,144 +372,32 @@ static void iwl_pcie_rxq_free_rbs(struct iwl_trans *trans) · 10 unmodified lines
410	* When moving to rx_free an page is allocated for the slot.	372	* When moving to rx_free an page is allocated for the slot.
411	*	373	*
412	* Also restock the Rx queue via iwl_pcie_rxq_restock.	374	* Also restock the Rx queue via iwl_pcie_rxq_restock.
413	* This is called only during initialization	375	* This is called as a scheduled work item (except for during initialization)
414	*/	376	*/
415	static void iwl_pcie_rx_replenish(struct iwl_trans *trans)	377	static void iwl_pcie_rx_replenish(struct iwl_trans *trans, gfp_t gfp)
416	{	378	{
417	iwl_pcie_rxq_alloc_rbs(trans);	379	iwl_pcie_rxq_alloc_rbs(trans, gfp);
418		380
419	iwl_pcie_rxq_restock(trans);	381	iwl_pcie_rxq_restock(trans);
420	}	382	}
421		383
422	/*	384	static void iwl_pcie_rx_replenish_work(struct work_struct *data)
423	* iwl_pcie_rx_allocator - Allocates pages in the background for RX queues
424	*
425	* Allocates for each received request 8 pages
426	* Called as a scheduled work item.
427	*/
428	static void iwl_pcie_rx_allocator(struct iwl_trans *trans)
429	{
430	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
431	struct iwl_rb_allocator *rba = &trans_pcie->rba;
432
433	while (atomic_read(&rba->req_pending)) {
434	int i;
435	struct list_head local_empty;
436	struct list_head local_allocated;
437
438	INIT_LIST_HEAD(&local_allocated);
439	spin_lock(&rba->lock);
440	/* swap out the entire rba->rbd_empty to a local list */
441	list_replace_init(&rba->rbd_empty, &local_empty);
442	spin_unlock(&rba->lock);
443
444	for (i = 0; i < RX_CLAIM_REQ_ALLOC;) {
445	struct iwl_rx_mem_buffer *rxb;
446	struct page *page;
447
448	/* List should never be empty - each reused RBD is
449	* returned to the list, and initial pool covers any
450	* possible gap between the time the page is allocated
451	* to the time the RBD is added.
452	*/
453	BUG_ON(list_empty(&local_empty));
454	/* Get the first rxb from the rbd list */
455	rxb = list_first_entry(&local_empty,
456	struct iwl_rx_mem_buffer, list);
457	BUG_ON(rxb->page);
458
459	/* Alloc a new receive buffer */
460	page = iwl_pcie_rx_alloc_page(trans);
461	if (!page)
462	continue;
463	rxb->page = page;
464
465	/* Get physical address of the RB */
466	rxb->page_dma = dma_map_page(trans->dev, page, 0,
467	PAGE_SIZE << trans_pcie->rx_page_order,
468	DMA_FROM_DEVICE);
469	if (dma_mapping_error(trans->dev, rxb->page_dma)) {
470	rxb->page = NULL;
471	__free_pages(page, trans_pcie->rx_page_order);
472	continue;
473	}
474	/* dma address must be no more than 36 bits */
475	BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
476	/* and also 256 byte aligned! */
477	BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
478
479	/* move the allocated entry to the out list */
480	list_move(&rxb->list, &local_allocated);
481	i++;
482	}
483
484	spin_lock(&rba->lock);
485	/* add the allocated rbds to the allocator allocated list */
486	list_splice_tail(&local_allocated, &rba->rbd_allocated);
487	/* add the unused rbds back to the allocator empty list */
488	list_splice_tail(&local_empty, &rba->rbd_empty);
489	spin_unlock(&rba->lock);
490
491	atomic_dec(&rba->req_pending);
492	atomic_inc(&rba->req_ready);
493	}
494	}
495
496	/*
497	* iwl_pcie_rx_allocator_get - Returns the pre-allocated pages
498	.*
499	.* Called by queue when the queue posted allocation request and
500	* has freed 8 RBDs in order to restock itself.
501	*/
502	static int iwl_pcie_rx_allocator_get(struct iwl_trans *trans,
503	struct iwl_rx_mem_buffer
504	*out[RX_CLAIM_REQ_ALLOC])
505	{
506	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
507	struct iwl_rb_allocator *rba = &trans_pcie->rba;
508	int i;
509
510	if (atomic_dec_return(&rba->req_ready) < 0) {
511	atomic_inc(&rba->req_ready);
512	IWL_DEBUG_RX(trans,
513	"Allocation request not ready, pending requests = %d\n",
514	atomic_read(&rba->req_pending));
515	return -ENOMEM;
516	}
517
518	spin_lock(&rba->lock);
519	for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) {
520	/* Get next free Rx buffer, remove it from free list */
521	out[i] = list_first_entry(&rba->rbd_allocated,
522	struct iwl_rx_mem_buffer, list);
523	list_del(&out[i]->list);
524	}
525	spin_unlock(&rba->lock);
526
527	return 0;
528	}
529
530	static void iwl_pcie_rx_allocator_work(struct work_struct *data)
531	{	385	{
532	struct iwl_rb_allocator *rba_p =
533	container_of(data, struct iwl_rb_allocator, rx_alloc);
534	struct iwl_trans_pcie *trans_pcie =	386	struct iwl_trans_pcie *trans_pcie =
535	container_of(rba_p, struct iwl_trans_pcie, rba);	387	container_of(data, struct iwl_trans_pcie, rx_replenish);
536		388
537	iwl_pcie_rx_allocator(trans_pcie->trans);	389	iwl_pcie_rx_replenish(trans_pcie->trans, GFP_KERNEL);
538	}	390	}
539		391
540	static int iwl_pcie_rx_alloc(struct iwl_trans *trans)	392	static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
541	{	393	{
542	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);	394	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
543	struct iwl_rxq *rxq = &trans_pcie->rxq;	395	struct iwl_rxq *rxq = &trans_pcie->rxq;
544	struct iwl_rb_allocator *rba = &trans_pcie->rba;
545	struct device *dev = trans->dev;	396	struct device *dev = trans->dev;
546		397
547	memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));	398	memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
548		399
549	spin_lock_init(&rxq->lock);	400	spin_lock_init(&rxq->lock);
550	spin_lock_init(&rba->lock);
551		401
552	if (WARN_ON(rxq->bd \|\| rxq->rb_stts))	402	if (WARN_ON(rxq->bd \|\| rxq->rb_stts))
553	return -EINVAL;	403	return -EINVAL;
@@ -637,49 +487,15 @@ static void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq) · 83 unmodified lines
637	INIT_LIST_HEAD(&rxq->rx_free);	487	INIT_LIST_HEAD(&rxq->rx_free);
638	INIT_LIST_HEAD(&rxq->rx_used);	488	INIT_LIST_HEAD(&rxq->rx_used);
639	rxq->free_count = 0;	489	rxq->free_count = 0;
640	rxq->used_count = 0;
641		490
642	for (i = 0; i < RX_QUEUE_SIZE; i++)	491	for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
643	list_add(&rxq->pool[i].list, &rxq->rx_used);	492	list_add(&rxq->pool[i].list, &rxq->rx_used);
644	}	493	}
645		494
646	static void iwl_pcie_rx_init_rba(struct iwl_rb_allocator *rba)
647	{
648	int i;
649
650	lockdep_assert_held(&rba->lock);
651
652	INIT_LIST_HEAD(&rba->rbd_allocated);
653	INIT_LIST_HEAD(&rba->rbd_empty);
654
655	for (i = 0; i < RX_POOL_SIZE; i++)
656	list_add(&rba->pool[i].list, &rba->rbd_empty);
657	}
658
659	static void iwl_pcie_rx_free_rba(struct iwl_trans *trans)
660	{
661	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
662	struct iwl_rb_allocator *rba = &trans_pcie->rba;
663	int i;
664
665	lockdep_assert_held(&rba->lock);
666
667	for (i = 0; i < RX_POOL_SIZE; i++) {
668	if (!rba->pool[i].page)
669	continue;
670	dma_unmap_page(trans->dev, rba->pool[i].page_dma,
671	PAGE_SIZE << trans_pcie->rx_page_order,
672	DMA_FROM_DEVICE);
673	__free_pages(rba->pool[i].page, trans_pcie->rx_page_order);
674	rba->pool[i].page = NULL;
675	}
676	}
677
678	int iwl_pcie_rx_init(struct iwl_trans *trans)	495	int iwl_pcie_rx_init(struct iwl_trans *trans)
679	{	496	{
680	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);	497	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
681	struct iwl_rxq *rxq = &trans_pcie->rxq;	498	struct iwl_rxq *rxq = &trans_pcie->rxq;
682	struct iwl_rb_allocator *rba = &trans_pcie->rba;
683	int i, err;	499	int i, err;
684		500
685	if (!rxq->bd) {	501	if (!rxq->bd) {
@@ -687,21 +503,11 @@ int iwl_pcie_rx_init(struct iwl_trans *trans) · 1 unmodified line
687	if (err)	503	if (err)
688	return err;	504	return err;
689	}	505	}
690	if (!rba->alloc_wq)
691	rba->alloc_wq = alloc_workqueue("rb_allocator",
692	WQ_HIGHPRI \| WQ_UNBOUND, 1);
693	INIT_WORK(&rba->rx_alloc, iwl_pcie_rx_allocator_work);
694
695	spin_lock(&rba->lock);
696	atomic_set(&rba->req_pending, 0);
697	atomic_set(&rba->req_ready, 0);
698	/* free all first - we might be reconfigured for a different size */
699	iwl_pcie_rx_free_rba(trans);
700	iwl_pcie_rx_init_rba(rba);
701	spin_unlock(&rba->lock);
702		506
703	spin_lock(&rxq->lock);	507	spin_lock(&rxq->lock);
704		508
		509	INIT_WORK(&trans_pcie->rx_replenish, iwl_pcie_rx_replenish_work);
		510
705	/* free all first - we might be reconfigured for a different size */	511	/* free all first - we might be reconfigured for a different size */
706	iwl_pcie_rxq_free_rbs(trans);	512	iwl_pcie_rxq_free_rbs(trans);
707	iwl_pcie_rx_init_rxb_lists(rxq);	513	iwl_pcie_rx_init_rxb_lists(rxq);
@@ -716,7 +522,7 @@ int iwl_pcie_rx_init(struct iwl_trans *trans) · 8 unmodified lines
716	memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));	522	memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
717	spin_unlock(&rxq->lock);	523	spin_unlock(&rxq->lock);
718		524
719	iwl_pcie_rx_replenish(trans);	525	iwl_pcie_rx_replenish(trans, GFP_KERNEL);
720		526
721	iwl_pcie_rx_hw_init(trans, rxq);	527	iwl_pcie_rx_hw_init(trans, rxq);
722		528
@@ -731,7 +537,6 @@ void iwl_pcie_rx_free(struct iwl_trans *trans) · 8 unmodified lines
731	{	537	{
732	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);	538	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
733	struct iwl_rxq *rxq = &trans_pcie->rxq;	539	struct iwl_rxq *rxq = &trans_pcie->rxq;
734	struct iwl_rb_allocator *rba = &trans_pcie->rba;
735		540
736	/*if rxq->bd is NULL, it means that nothing has been allocated,	541	/*if rxq->bd is NULL, it means that nothing has been allocated,
737	* exit now */	542	* exit now */
@@ -740,15 +545,7 @@ void iwl_pcie_rx_free(struct iwl_trans *trans) · 2 unmodified lines
740	return;	545	return;
741	}	546	}
742		547
743	cancel_work_sync(&rba->rx_alloc);	548	cancel_work_sync(&trans_pcie->rx_replenish);
744	if (rba->alloc_wq) {
745	destroy_workqueue(rba->alloc_wq);
746	rba->alloc_wq = NULL;
747	}
748
749	spin_lock(&rba->lock);
750	iwl_pcie_rx_free_rba(trans);
751	spin_unlock(&rba->lock);
752		549
753	spin_lock(&rxq->lock);	550	spin_lock(&rxq->lock);
754	iwl_pcie_rxq_free_rbs(trans);	551	iwl_pcie_rxq_free_rbs(trans);
@@ -769,43 +566,6 @@ void iwl_pcie_rx_free(struct iwl_trans *trans) · 14 unmodified lines
769	rxq->rb_stts = NULL;	566	rxq->rb_stts = NULL;
770	}	567	}
771		568
772	/*
773	* iwl_pcie_rx_reuse_rbd - Recycle used RBDs
774	*
775	* Called when a RBD can be reused. The RBD is transferred to the allocator.
776	* When there are 2 empty RBDs - a request for allocation is posted
777	*/
778	static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans,
779	struct iwl_rx_mem_buffer *rxb,
780	struct iwl_rxq *rxq)
781	{
782	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
783	struct iwl_rb_allocator *rba = &trans_pcie->rba;
784
785	/* Count the used RBDs */
786	rxq->used_count++;
787
788	/* Move the RBD to the used list, will be moved to allocator in batches
789	* before claiming or posting a request*/
790	list_add_tail(&rxb->list, &rxq->rx_used);
791
792	/* If we have RX_POST_REQ_ALLOC new released rx buffers -
793	* issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is
794	* used for the case we failed to claim RX_CLAIM_REQ_ALLOC,
795	* after but we still need to post another request.
796	*/
797	if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) {
798	/* Move the 2 RBDs to the allocator ownership.
799	Allocator has another 6 from pool for the request completion*/
800	spin_lock(&rba->lock);
801	list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty);
802	spin_unlock(&rba->lock);
803
804	atomic_inc(&rba->req_pending);
805	queue_work(rba->alloc_wq, &rba->rx_alloc);
806	}
807	}
808
809	static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,	569	static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
810	struct iwl_rx_mem_buffer *rxb)	570	struct iwl_rx_mem_buffer *rxb)
811	{	571	{
@@ -928,13 +688,13 @@ static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans, · 116 unmodified lines
928	*/	688	*/
929	__free_pages(rxb->page, trans_pcie->rx_page_order);	689	__free_pages(rxb->page, trans_pcie->rx_page_order);
930	rxb->page = NULL;	690	rxb->page = NULL;
931	iwl_pcie_rx_reuse_rbd(trans, rxb, rxq);	691	list_add_tail(&rxb->list, &rxq->rx_used);
932	} else {	692	} else {
933	list_add_tail(&rxb->list, &rxq->rx_free);	693	list_add_tail(&rxb->list, &rxq->rx_free);
934	rxq->free_count++;	694	rxq->free_count++;
935	}	695	}
936	} else	696	} else
937	iwl_pcie_rx_reuse_rbd(trans, rxb, rxq);	697	list_add_tail(&rxb->list, &rxq->rx_used);
938	}	698	}
939		699
940	/*	700	/*
@@ -944,7 +704,10 @@ static void iwl_pcie_rx_handle(struct iwl_trans *trans) · 3 unmodified lines
944	{	704	{
945	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);	705	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
946	struct iwl_rxq *rxq = &trans_pcie->rxq;	706	struct iwl_rxq *rxq = &trans_pcie->rxq;
947	u32 r, i, j;	707	u32 r, i;
		708	u8 fill_rx = 0;
		709	u32 count = 8;
		710	int total_empty;
948		711
949	restart:	712	restart:
950	spin_lock(&rxq->lock);	713	spin_lock(&rxq->lock);
@@ -957,6 +720,14 @@ restart: · 6 unmodified lines
957	if (i == r)	720	if (i == r)
958	IWL_DEBUG_RX(trans, "HW = SW = %d\n", r);	721	IWL_DEBUG_RX(trans, "HW = SW = %d\n", r);
959		722
		723	/* calculate total frames need to be restock after handling RX */
		724	total_empty = r - rxq->write_actual;
		725	if (total_empty < 0)
		726	total_empty += RX_QUEUE_SIZE;
		727
		728	if (total_empty > (RX_QUEUE_SIZE / 2))
		729	fill_rx = 1;
		730
960	while (i != r) {	731	while (i != r) {
961	struct iwl_rx_mem_buffer *rxb;	732	struct iwl_rx_mem_buffer *rxb;
962		733
@@ -968,48 +739,29 @@ restart: · 5 unmodified lines
968	iwl_pcie_rx_handle_rb(trans, rxb);	739	iwl_pcie_rx_handle_rb(trans, rxb);
969		740
970	i = (i + 1) & RX_QUEUE_MASK;	741	i = (i + 1) & RX_QUEUE_MASK;
971		742	/* If there are a lot of unused frames,
972	/* If we have RX_CLAIM_REQ_ALLOC released rx buffers -	743	* restock the Rx queue so ucode wont assert. */
973	* try to claim the pre-allocated buffers from the allocator */	744	if (fill_rx) {
974	if (rxq->used_count >= RX_CLAIM_REQ_ALLOC) {	745	count++;
975	struct iwl_rb_allocator *rba = &trans_pcie->rba;	746	if (count >= 8) {
976	struct iwl_rx_mem_buffer *out[RX_CLAIM_REQ_ALLOC];	747	rxq->read = i;
977		748	spin_unlock(&rxq->lock);
978	/* Add the remaining 6 empty RBDs for allocator use */	749	iwl_pcie_rx_replenish(trans, GFP_ATOMIC);
979	spin_lock(&rba->lock);	750	count = 0;
980	list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty);	751	goto restart;
981	spin_unlock(&rba->lock);
982
983	/* If not ready - continue, will try to reclaim later.
984	* No need to reschedule work - allocator exits only on
985	* success */
986	if (!iwl_pcie_rx_allocator_get(trans, out)) {
987	/* If success - then RX_CLAIM_REQ_ALLOC
988	* buffers were retrieved and should be added
989	* to free list */
990	rxq->used_count -= RX_CLAIM_REQ_ALLOC;
991	for (j = 0; j < RX_CLAIM_REQ_ALLOC; j++) {
992	list_add_tail(&out[j]->list,
993	&rxq->rx_free);
994	rxq->free_count++;
995	}
996	}	752	}
997	}	753	}
998	/* handle restock for two cases:
999	* - we just pulled buffers from the allocator
1000	* - we have 8+ unstolen pages accumulated */
1001	if (rxq->free_count >= RX_CLAIM_REQ_ALLOC) {
1002	rxq->read = i;
1003	spin_unlock(&rxq->lock);
1004	iwl_pcie_rxq_restock(trans);
1005	goto restart;
1006	}
1007	}	754	}
1008		755
1009	/* Backtrack one entry */	756	/* Backtrack one entry */
1010	rxq->read = i;	757	rxq->read = i;
1011	spin_unlock(&rxq->lock);	758	spin_unlock(&rxq->lock);
1012		759
		760	if (fill_rx)
		761	iwl_pcie_rx_replenish(trans, GFP_ATOMIC);
		762	else
		763	iwl_pcie_rxq_restock(trans);
		764
1013	if (trans_pcie->napi.poll)	765	if (trans_pcie->napi.poll)
1014	napi_gro_flush(&trans_pcie->napi, false);	766	napi_gro_flush(&trans_pcie->napi, false);
1015	}	767	}

drivers/net/wireless/iwlwifi/pcie/trans.c+48−26

 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 {
-	if (!trans->cfg->apmg_not_supported)
+	if (trans->cfg->apmg_not_supported)
 		return;
 	if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 		if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
 			iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 					  APMG_PCIDEV_STT_VAL_WAKE_ME);
-		else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
+		else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
+			iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
+				    CSR_RESET_LINK_PWR_MGMT_DISABLED);
 			iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 				    CSR_HW_IF_CONFIG_REG_PREPARE |
 				    CSR_HW_IF_CONFIG_REG_ENABLE_PME);
+			mdelay(1);
+			iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
+				      CSR_RESET_LINK_PWR_MGMT_DISABLED);
+		}
 		mdelay(5);
 	}
 	if (ret >= 0)
 		return 0;
+	iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
+		    CSR_RESET_LINK_PWR_MGMT_DISABLED);
+	msleep(1);
 	for (iter = 0; iter < 10; iter++) {
 		/* If HW is not ready, prepare the conditions to check again */
 		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 		do {
 			ret = iwl_pcie_set_hw_ready(trans);
-			if (ret >= 0)
+			if (ret >= 0) {
-				return 0;
+				ret = 0;
+				goto out;
+			}
 			usleep_range(200, 1000);
 			t += 200;
 	IWL_ERR(trans, "Couldn't prepare the card\n");
+out:
+	iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
+		      CSR_RESET_LINK_PWR_MGMT_DISABLED);
 	return ret;
 }
 	struct iwl_trans_pcie *trans_pcie;
 	struct iwl_trans *trans;
 	u16 pci_cmd;
-	int err;
+	int ret;
 	trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
 				&pdev->dev, cfg, &trans_ops_pcie, 0);
 	spin_lock_init(&trans_pcie->ref_lock);
 	init_waitqueue_head(&trans_pcie->ucode_write_waitq);
-	err = pci_enable_device(pdev);
+	ret = pci_enable_device(pdev);
-	if (err)
+	if (ret)
 		goto out_no_pci;
 	if (!cfg->base_params->pcie_l1_allowed) {
 	pci_set_master(pdev);
-	err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
+	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
-	if (!err)
+	if (!ret)
-		err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
+		ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
-	if (err) {
+	if (ret) {
-		err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
+		ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
-		if (!err)
+		if (!ret)
-			err = pci_set_consistent_dma_mask(pdev,
+			ret = pci_set_consistent_dma_mask(pdev,
 							  DMA_BIT_MASK(32));
 		/* both attempts failed: */
-		if (err) {
+		if (ret) {
 			dev_err(&pdev->dev, "No suitable DMA available\n");
 			goto out_pci_disable_device;
 		}
 	}
-	err = pci_request_regions(pdev, DRV_NAME);
+	ret = pci_request_regions(pdev, DRV_NAME);
-	if (err) {
+	if (ret) {
 		dev_err(&pdev->dev, "pci_request_regions failed\n");
 		goto out_pci_disable_device;
 	}
 	trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
 	if (!trans_pcie->hw_base) {
 		dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
-		err = -ENODEV;
+		ret = -ENODEV;
 		goto out_pci_release_regions;
 	}
 	trans_pcie->pci_dev = pdev;
 	iwl_disable_interrupts(trans);
-	err = pci_enable_msi(pdev);
+	ret = pci_enable_msi(pdev);
-	if (err) {
+	if (ret) {
-		dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
+		dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", ret);
 		/* enable rfkill interrupt: hw bug w/a */
 		pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
 		if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
 	 */
 	if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
 		unsigned long flags;
-		int ret;
 		trans->hw_rev = (trans->hw_rev & 0xfff0) |
 				(CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
+		ret = iwl_pcie_prepare_card_hw(trans);
+		if (ret) {
+			IWL_WARN(trans, "Exit HW not ready\n");
+			goto out_pci_disable_msi;
+		}
 		/*
 		 * in-order to recognize C step driver should read chip version
 		 * id located at the AUX bus MISC address space.
 	/* Initialize the wait queue for commands */
 	init_waitqueue_head(&trans_pcie->wait_command_queue);
-	if (iwl_pcie_alloc_ict(trans))
+	ret = iwl_pcie_alloc_ict(trans);
+	if (ret)
 		goto out_pci_disable_msi;
-	err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
+	ret = request_threaded_irq(pdev->irq, iwl_pcie_isr,
 				   iwl_pcie_irq_handler,
 				   IRQF_SHARED, DRV_NAME, trans);
-	if (err) {
+	if (ret) {
 		IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
 		goto out_free_ict;
 	}
 	pci_disable_device(pdev);
 out_no_pci:
 	iwl_trans_free(trans);
-	return ERR_PTR(err);
+	return ERR_PTR(ret);
 }

drivers/net/wireless/iwlwifi/pcie/tx.c+13−2

@@ -1875,8 +1875,19 @@ int iwl_trans_pcie_tx(struct iwl_trans trans, struct sk_buff skb, · 1874 unmodified lines
1875		1875
1876	/* start timer if queue currently empty */	1876	/* start timer if queue currently empty */
1877	if (q->read_ptr == q->write_ptr) {	1877	if (q->read_ptr == q->write_ptr) {
1878	if (txq->wd_timeout)	1878	if (txq->wd_timeout) {
1879	mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);	1879	/*
		1880	* If the TXQ is active, then set the timer, if not,
		1881	* set the timer in remainder so that the timer will
		1882	* be armed with the right value when the station will
		1883	* wake up.
		1884	*/
		1885	if (!txq->frozen)
		1886	mod_timer(&txq->stuck_timer,
		1887	jiffies + txq->wd_timeout);
		1888	else
		1889	txq->frozen_expiry_remainder = txq->wd_timeout;
		1890	}
1880	IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", q->id);	1891	IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", q->id);
1881	iwl_trans_pcie_ref(trans);	1892	iwl_trans_pcie_ref(trans);
1882	}	1893	}

drivers/net/wireless/rsi/rsi_91x_sdio_ops.c+7−1

 		(struct rsi_91x_sdiodev *)adapter->rsi_dev;
 	u32 len;
 	u32 num_blocks;
+	const u8 *fw;
 	const struct firmware *fw_entry = NULL;
 	u32 block_size = dev->tx_blk_size;
 	int status = 0;
 		return status;
 	}
+	/* Copy firmware into DMA-accessible memory */
+	fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL);
+	if (!fw)
+		return -ENOMEM;
 	len = fw_entry->size;
 	if (len % 4)
 	rsi_dbg(INIT_ZONE, "%s: Instruction size:%d\n", __func__, len);
 	rsi_dbg(INIT_ZONE, "%s: num blocks: %d\n", __func__, num_blocks);
-	status = rsi_copy_to_card(common, fw_entry->data, len, num_blocks);
+	status = rsi_copy_to_card(common, fw, len, num_blocks);
+	kfree(fw);
 	release_firmware(fw_entry);
 	return status;
 }

drivers/net/wireless/rsi/rsi_91x_usb_ops.c+4−0

 		return status;
 	}
+	/* Copy firmware into DMA-accessible memory */
 	fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL);
+	if (!fw)
+		return -ENOMEM;
 	len = fw_entry->size;
 	if (len % 4)
 	rsi_dbg(INIT_ZONE, "%s: num blocks: %d\n", __func__, num_blocks);
 	status = rsi_copy_to_card(common, fw, len, num_blocks);
+	kfree(fw);
 	release_firmware(fw_entry);
 	return status;
 }

drivers/net/wireless/rtlwifi/core.c+5−2

 {
 	struct rtl_priv *rtlpriv = rtl_priv(hw);
 	struct sk_buff *skb = ieee80211_beacon_get(hw, vif);
+	struct rtl_tcb_desc tcb_desc;
-	if (skb)
+	if (skb) {
-		rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, NULL);
+		memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
+		rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
+	}
 }
 static void rtl_op_bss_info_changed(struct ieee80211_hw *hw,

drivers/net/wireless/rtlwifi/rtl8723be/sw.c+1−0

@@ -385,6 +385,7 @@ module_param_named(debug, rtl8723be_mod_params.debug, int, 0444); · 384 unmodified lines
385	module_param_named(ips, rtl8723be_mod_params.inactiveps, bool, 0444);	385	module_param_named(ips, rtl8723be_mod_params.inactiveps, bool, 0444);
386	module_param_named(swlps, rtl8723be_mod_params.swctrl_lps, bool, 0444);	386	module_param_named(swlps, rtl8723be_mod_params.swctrl_lps, bool, 0444);
387	module_param_named(fwlps, rtl8723be_mod_params.fwctrl_lps, bool, 0444);	387	module_param_named(fwlps, rtl8723be_mod_params.fwctrl_lps, bool, 0444);
		388	module_param_named(msi, rtl8723be_mod_params.msi_support, bool, 0444);
388	module_param_named(disable_watchdog, rtl8723be_mod_params.disable_watchdog,	389	module_param_named(disable_watchdog, rtl8723be_mod_params.disable_watchdog,
389	bool, 0444);	390	bool, 0444);
390	MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");	391	MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");

drivers/net/xen-netback/interface.c+6−0

 void xenvif_skb_zerocopy_complete(struct xenvif_queue *queue)
 {
 	atomic_dec(&queue->inflight_packets);
+	/* Wake the dealloc thread _after_ decrementing inflight_packets so
+	 * that if kthread_stop() has already been called, the dealloc thread
+	 * does not wait forever with nothing to wake it.
+	 */
+	wake_up(&queue->dealloc_wq);
 }
 int xenvif_schedulable(struct xenvif *vif)

drivers/net/xen-netback/netback.c+36−32

 static struct gnttab_map_grant_ref *xenvif_get_requests(struct xenvif_queue *queue,
 							struct sk_buff *skb,
 							struct xen_netif_tx_request *txp,
-							struct gnttab_map_grant_ref *gop)
+							struct gnttab_map_grant_ref *gop,
+							unsigned int frag_overflow,
+							struct sk_buff *nskb)
 {
 	struct skb_shared_info *shinfo = skb_shinfo(skb);
 	skb_frag_t *frags = shinfo->frags;
 	u16 pending_idx = XENVIF_TX_CB(skb)->pending_idx;
 	int start;
 	pending_ring_idx_t index;
-	unsigned int nr_slots, frag_overflow = 0;
+	unsigned int nr_slots;
-	/* At this point shinfo->nr_frags is in fact the number of
-	 * slots, which can be as large as XEN_NETBK_LEGACY_SLOTS_MAX.
-	 */
-	if (shinfo->nr_frags > MAX_SKB_FRAGS) {
-		frag_overflow = shinfo->nr_frags - MAX_SKB_FRAGS;
-		BUG_ON(frag_overflow > MAX_SKB_FRAGS);
-		shinfo->nr_frags = MAX_SKB_FRAGS;
-	}
 	nr_slots = shinfo->nr_frags;
 	/* Skip first skb fragment if it is on same page as header fragment. */
 	}
 	if (frag_overflow) {
-		struct sk_buff *nskb = xenvif_alloc_skb(0);
-		if (unlikely(nskb == NULL)) {
-			if (net_ratelimit())
-				netdev_err(queue->vif->dev,
-					   "Can't allocate the frag_list skb.\n");
-			return NULL;
-		}
 		shinfo = skb_shinfo(nskb);
 		frags = shinfo->frags;
 				     unsigned *copy_ops,
 				     unsigned *map_ops)
 {
-	struct gnttab_map_grant_ref *gop = queue->tx_map_ops, *request_gop;
+	struct gnttab_map_grant_ref *gop = queue->tx_map_ops;
-	struct sk_buff *skb;
+	struct sk_buff *skb, *nskb;
 	int ret;
+	unsigned int frag_overflow;
 	while (skb_queue_len(&queue->tx_queue) < budget) {
 		struct xen_netif_tx_request txreq;
 			break;
 		}
+		skb_shinfo(skb)->nr_frags = ret;
+		if (data_len < txreq.size)
+			skb_shinfo(skb)->nr_frags++;
+		/* At this point shinfo->nr_frags is in fact the number of
+		 * slots, which can be as large as XEN_NETBK_LEGACY_SLOTS_MAX.
+		 */
+		frag_overflow = 0;
+		nskb = NULL;
+		if (skb_shinfo(skb)->nr_frags > MAX_SKB_FRAGS) {
+			frag_overflow = skb_shinfo(skb)->nr_frags - MAX_SKB_FRAGS;
+			BUG_ON(frag_overflow > MAX_SKB_FRAGS);
+			skb_shinfo(skb)->nr_frags = MAX_SKB_FRAGS;
+			nskb = xenvif_alloc_skb(0);
+			if (unlikely(nskb == NULL)) {
+				kfree_skb(skb);
+				xenvif_tx_err(queue, &txreq, idx);
+				if (net_ratelimit())
+					netdev_err(queue->vif->dev,
+						   "Can't allocate the frag_list skb.\n");
+				break;
+			}
+		}
 		if (extras[XEN_NETIF_EXTRA_TYPE_GSO - 1].type) {
 			struct xen_netif_extra_info *gso;
 			gso = &extras[XEN_NETIF_EXTRA_TYPE_GSO - 1];
 			if (xenvif_set_skb_gso(queue->vif, skb, gso)) {
 				/* Failure in xenvif_set_skb_gso is fatal. */
 				kfree_skb(skb);
+				kfree_skb(nskb);
 				break;
 			}
 		}
 		(*copy_ops)++;
-		skb_shinfo(skb)->nr_frags = ret;
 		if (data_len < txreq.size) {
-			skb_shinfo(skb)->nr_frags++;
 			frag_set_pending_idx(&skb_shinfo(skb)->frags[0],
 					     pending_idx);
 			xenvif_tx_create_map_op(queue, pending_idx, &txreq, gop);
 		queue->pending_cons++;
-		request_gop = xenvif_get_requests(queue, skb, txfrags, gop);
+		gop = xenvif_get_requests(queue, skb, txfrags, gop,
-		if (request_gop == NULL) {
+				          frag_overflow, nskb);
-			kfree_skb(skb);
-			xenvif_tx_err(queue, &txreq, idx);
-			break;
-		}
-		gop = request_gop;
 		__skb_queue_tail(&queue->tx_queue, skb);
 		smp_wmb();
 		queue->dealloc_prod++;
 	} while (ubuf);
-	wake_up(&queue->dealloc_wq);
 	spin_unlock_irqrestore(&queue->callback_lock, flags);
 	if (likely(zerocopy_success))
 		smp_rmb();
 		while (dc != dp) {
-			BUG_ON(gop - queue->tx_unmap_ops > MAX_PENDING_REQS);
+			BUG_ON(gop - queue->tx_unmap_ops >= MAX_PENDING_REQS);
 			pending_idx =
 				queue->dealloc_ring[pending_index(dc++)];
-			pending_idx_release[gop-queue->tx_unmap_ops] =
+			pending_idx_release[gop - queue->tx_unmap_ops] =
 				pending_idx;
-			queue->pages_to_unmap[gop-queue->tx_unmap_ops] =
+			queue->pages_to_unmap[gop - queue->tx_unmap_ops] =
 				queue->mmap_pages[pending_idx];
 			gnttab_set_unmap_op(gop,
 					    idx_to_kaddr(queue, pending_idx),

drivers/ntb/ntb.c+1−1

@@ -114,7 +114,7 @@ int ntb_register_device(struct ntb_dev *ntb) · 113 unmodified lines
114	ntb->dev.bus = &ntb_bus;	114	ntb->dev.bus = &ntb_bus;
115	ntb->dev.parent = &ntb->pdev->dev;	115	ntb->dev.parent = &ntb->pdev->dev;
116	ntb->dev.release = ntb_dev_release;	116	ntb->dev.release = ntb_dev_release;
117	dev_set_name(&ntb->dev, pci_name(ntb->pdev));	117	dev_set_name(&ntb->dev, "%s", pci_name(ntb->pdev));
118		118
119	ntb->ctx = NULL;	119	ntb->ctx = NULL;
120	ntb->ctx_ops = NULL;	120	ntb->ctx_ops = NULL;

drivers/ntb/ntb_transport.c+124−77

@@ -142,10 +142,11 @@ struct ntb_transport_qp { · 141 unmodified lines
142		142
143	void (rx_handler)(struct ntb_transport_qp qp, void *qp_data,	143	void (rx_handler)(struct ntb_transport_qp qp, void *qp_data,
144	void *data, int len);	144	void *data, int len);
		145	struct list_head rx_post_q;
145	struct list_head rx_pend_q;	146	struct list_head rx_pend_q;
146	struct list_head rx_free_q;	147	struct list_head rx_free_q;
147	spinlock_t ntb_rx_pend_q_lock;	148	/* ntb_rx_q_lock: synchronize access to rx_XXXX_q */
148	spinlock_t ntb_rx_free_q_lock;	149	spinlock_t ntb_rx_q_lock;
149	void *rx_buff;	150	void *rx_buff;
150	unsigned int rx_index;	151	unsigned int rx_index;
151	unsigned int rx_max_entry;	152	unsigned int rx_max_entry;
@@ -211,6 +212,8 @@ struct ntb_transport_ctx { · 59 unmodified lines
211	bool link_is_up;	212	bool link_is_up;
212	struct delayed_work link_work;	213	struct delayed_work link_work;
213	struct work_struct link_cleanup;	214	struct work_struct link_cleanup;
		215
		216	struct dentry *debugfs_node_dir;
214	};	217	};
215		218
216	enum {	219	enum {
@@ -436,13 +439,17 @@ static ssize_t debugfs_read(struct file filp, char __user ubuf, size_t count, · 219 unmodified lines
436	char *buf;	439	char *buf;
437	ssize_t ret, out_offset, out_count;	440	ssize_t ret, out_offset, out_count;
438		441
		442	qp = filp->private_data;
		443
		444	if (!qp \|\| !qp->link_is_up)
		445	return 0;
		446
439	out_count = 1000;	447	out_count = 1000;
440		448
441	buf = kmalloc(out_count, GFP_KERNEL);	449	buf = kmalloc(out_count, GFP_KERNEL);
442	if (!buf)	450	if (!buf)
443	return -ENOMEM;	451	return -ENOMEM;
444		452
445	qp = filp->private_data;
446	out_offset = 0;	453	out_offset = 0;
447	out_offset += snprintf(buf + out_offset, out_count - out_offset,	454	out_offset += snprintf(buf + out_offset, out_count - out_offset,
448	"NTB QP stats\n");	455	"NTB QP stats\n");
@@ -534,6 +541,27 @@ out: · 85 unmodified lines
534	return entry;	541	return entry;
535	}	542	}
536		543
		544	static struct ntb_queue_entry ntb_list_mv(spinlock_t lock,
		545	struct list_head *list,
		546	struct list_head *to_list)
		547	{
		548	struct ntb_queue_entry *entry;
		549	unsigned long flags;
		550
		551	spin_lock_irqsave(lock, flags);
		552
		553	if (list_empty(list)) {
		554	entry = NULL;
		555	} else {
		556	entry = list_first_entry(list, struct ntb_queue_entry, entry);
		557	list_move_tail(&entry->entry, to_list);
		558	}
		559
		560	spin_unlock_irqrestore(lock, flags);
		561
		562	return entry;
		563	}
		564
537	static int ntb_transport_setup_qp_mw(struct ntb_transport_ctx *nt,	565	static int ntb_transport_setup_qp_mw(struct ntb_transport_ctx *nt,
538	unsigned int qp_num)	566	unsigned int qp_num)
539	{	567	{
@@ -601,13 +629,16 @@ static void ntb_free_mw(struct ntb_transport_ctx *nt, int num_mw) · 61 unmodified lines
601	}	629	}
602		630
603	static int ntb_set_mw(struct ntb_transport_ctx *nt, int num_mw,	631	static int ntb_set_mw(struct ntb_transport_ctx *nt, int num_mw,
604	unsigned int size)	632	resource_size_t size)
605	{	633	{
606	struct ntb_transport_mw *mw = &nt->mw_vec[num_mw];	634	struct ntb_transport_mw *mw = &nt->mw_vec[num_mw];
607	struct pci_dev *pdev = nt->ndev->pdev;	635	struct pci_dev *pdev = nt->ndev->pdev;
608	unsigned int xlat_size, buff_size;	636	size_t xlat_size, buff_size;
609	int rc;	637	int rc;
610		638
		639	if (!size)
		640	return -EINVAL;
		641
611	xlat_size = round_up(size, mw->xlat_align_size);	642	xlat_size = round_up(size, mw->xlat_align_size);
612	buff_size = round_up(size, mw->xlat_align);	643	buff_size = round_up(size, mw->xlat_align);
613		644
@@ -627,7 +658,7 @@ static int ntb_set_mw(struct ntb_transport_ctx *nt, int num_mw, · 13 unmodified lines
627	if (!mw->virt_addr) {	658	if (!mw->virt_addr) {
628	mw->xlat_size = 0;	659	mw->xlat_size = 0;
629	mw->buff_size = 0;	660	mw->buff_size = 0;
630	dev_err(&pdev->dev, "Unable to alloc MW buff of size %d\n",	661	dev_err(&pdev->dev, "Unable to alloc MW buff of size %zu\n",
631	buff_size);	662	buff_size);
632	return -ENOMEM;	663	return -ENOMEM;
633	}	664	}
@@ -867,6 +898,8 @@ static void ntb_qp_link_work(struct work_struct *work) · 233 unmodified lines
867		898
868	if (qp->event_handler)	899	if (qp->event_handler)
869	qp->event_handler(qp->cb_data, qp->link_is_up);	900	qp->event_handler(qp->cb_data, qp->link_is_up);
		901
		902	tasklet_schedule(&qp->rxc_db_work);
870	} else if (nt->link_is_up)	903	} else if (nt->link_is_up)
871	schedule_delayed_work(&qp->link_work,	904	schedule_delayed_work(&qp->link_work,
872	msecs_to_jiffies(NTB_LINK_DOWN_TIMEOUT));	905	msecs_to_jiffies(NTB_LINK_DOWN_TIMEOUT));
@@ -923,12 +956,12 @@ static int ntb_transport_init_queue(struct ntb_transport_ctx *nt, · 50 unmodified lines
923	qp->tx_max_frame = min(transport_mtu, tx_size / 2);	956	qp->tx_max_frame = min(transport_mtu, tx_size / 2);
924	qp->tx_max_entry = tx_size / qp->tx_max_frame;	957	qp->tx_max_entry = tx_size / qp->tx_max_frame;
925		958
926	if (nt_debugfs_dir) {	959	if (nt->debugfs_node_dir) {
927	char debugfs_name[4];	960	char debugfs_name[4];
928		961
929	snprintf(debugfs_name, 4, "qp%d", qp_num);	962	snprintf(debugfs_name, 4, "qp%d", qp_num);
930	qp->debugfs_dir = debugfs_create_dir(debugfs_name,	963	qp->debugfs_dir = debugfs_create_dir(debugfs_name,
931	nt_debugfs_dir);	964	nt->debugfs_node_dir);
932		965
933	qp->debugfs_stats = debugfs_create_file("stats", S_IRUSR,	966	qp->debugfs_stats = debugfs_create_file("stats", S_IRUSR,
934	qp->debugfs_dir, qp,	967	qp->debugfs_dir, qp,
@@ -941,10 +974,10 @@ static int ntb_transport_init_queue(struct ntb_transport_ctx *nt, · 6 unmodified lines
941	INIT_DELAYED_WORK(&qp->link_work, ntb_qp_link_work);	974	INIT_DELAYED_WORK(&qp->link_work, ntb_qp_link_work);
942	INIT_WORK(&qp->link_cleanup, ntb_qp_link_cleanup_work);	975	INIT_WORK(&qp->link_cleanup, ntb_qp_link_cleanup_work);
943		976
944	spin_lock_init(&qp->ntb_rx_pend_q_lock);	977	spin_lock_init(&qp->ntb_rx_q_lock);
945	spin_lock_init(&qp->ntb_rx_free_q_lock);
946	spin_lock_init(&qp->ntb_tx_free_q_lock);	978	spin_lock_init(&qp->ntb_tx_free_q_lock);
947		979
		980	INIT_LIST_HEAD(&qp->rx_post_q);
948	INIT_LIST_HEAD(&qp->rx_pend_q);	981	INIT_LIST_HEAD(&qp->rx_pend_q);
949	INIT_LIST_HEAD(&qp->rx_free_q);	982	INIT_LIST_HEAD(&qp->rx_free_q);
950	INIT_LIST_HEAD(&qp->tx_free_q);	983	INIT_LIST_HEAD(&qp->tx_free_q);
@@ -1031,6 +1064,12 @@ static int ntb_transport_probe(struct ntb_client self, struct ntb_dev ndev) · 80 unmodified lines
1031	goto err2;	1064	goto err2;
1032	}	1065	}
1033		1066
		1067	if (nt_debugfs_dir) {
		1068	nt->debugfs_node_dir =
		1069	debugfs_create_dir(pci_name(ndev->pdev),
		1070	nt_debugfs_dir);
		1071	}
		1072
1034	for (i = 0; i < qp_count; i++) {	1073	for (i = 0; i < qp_count; i++) {
1035	rc = ntb_transport_init_queue(nt, i);	1074	rc = ntb_transport_init_queue(nt, i);
1036	if (rc)	1075	if (rc)
@@ -1107,22 +1146,47 @@ static void ntb_transport_free(struct ntb_client self, struct ntb_dev ndev) · 70 unmodified lines
1107	kfree(nt);	1146	kfree(nt);
1108	}	1147	}
1109		1148
1110	static void ntb_rx_copy_callback(void *data)	1149	static void ntb_complete_rxc(struct ntb_transport_qp *qp)
1111	{	1150	{
1112	struct ntb_queue_entry *entry = data;	1151	struct ntb_queue_entry *entry;
1113	struct ntb_transport_qp *qp = entry->qp;	1152	void *cb_data;
1114	void *cb_data = entry->cb_data;	1153	unsigned int len;
1115	unsigned int len = entry->len;	1154	unsigned long irqflags;
1116	struct ntb_payload_header *hdr = entry->rx_hdr;	1155
		1156	spin_lock_irqsave(&qp->ntb_rx_q_lock, irqflags);
		1157
		1158	while (!list_empty(&qp->rx_post_q)) {
		1159	entry = list_first_entry(&qp->rx_post_q,
		1160	struct ntb_queue_entry, entry);
		1161	if (!(entry->flags & DESC_DONE_FLAG))
		1162	break;
		1163
		1164	entry->rx_hdr->flags = 0;
		1165	iowrite32(entry->index, &qp->rx_info->entry);
1117		1166
1118	hdr->flags = 0;	1167	cb_data = entry->cb_data;
		1168	len = entry->len;
1119		1169
1120	iowrite32(entry->index, &qp->rx_info->entry);	1170	list_move_tail(&entry->entry, &qp->rx_free_q);
1121		1171
1122	ntb_list_add(&qp->ntb_rx_free_q_lock, &entry->entry, &qp->rx_free_q);	1172	spin_unlock_irqrestore(&qp->ntb_rx_q_lock, irqflags);
1123		1173
1124	if (qp->rx_handler && qp->client_ready)	1174	if (qp->rx_handler && qp->client_ready)
1125	qp->rx_handler(qp, qp->cb_data, cb_data, len);	1175	qp->rx_handler(qp, qp->cb_data, cb_data, len);
		1176
		1177	spin_lock_irqsave(&qp->ntb_rx_q_lock, irqflags);
		1178	}
		1179
		1180	spin_unlock_irqrestore(&qp->ntb_rx_q_lock, irqflags);
		1181	}
		1182
		1183	static void ntb_rx_copy_callback(void *data)
		1184	{
		1185	struct ntb_queue_entry *entry = data;
		1186
		1187	entry->flags \|= DESC_DONE_FLAG;
		1188
		1189	ntb_complete_rxc(entry->qp);
1126	}	1190	}
1127		1191
1128	static void ntb_memcpy_rx(struct ntb_queue_entry entry, void offset)	1192	static void ntb_memcpy_rx(struct ntb_queue_entry entry, void offset)
@@ -1138,19 +1202,18 @@ static void ntb_memcpy_rx(struct ntb_queue_entry entry, void offset) · 9 unmodified lines
1138	ntb_rx_copy_callback(entry);	1202	ntb_rx_copy_callback(entry);
1139	}	1203	}
1140		1204
1141	static void ntb_async_rx(struct ntb_queue_entry entry, void offset,	1205	static void ntb_async_rx(struct ntb_queue_entry entry, void offset)
1142	size_t len)
1143	{	1206	{
1144	struct dma_async_tx_descriptor *txd;	1207	struct dma_async_tx_descriptor *txd;
1145	struct ntb_transport_qp *qp = entry->qp;	1208	struct ntb_transport_qp *qp = entry->qp;
1146	struct dma_chan *chan = qp->dma_chan;	1209	struct dma_chan *chan = qp->dma_chan;
1147	struct dma_device *device;	1210	struct dma_device *device;
1148	size_t pay_off, buff_off;	1211	size_t pay_off, buff_off, len;
1149	struct dmaengine_unmap_data *unmap;	1212	struct dmaengine_unmap_data *unmap;
1150	dma_cookie_t cookie;	1213	dma_cookie_t cookie;
1151	void *buf = entry->buf;	1214	void *buf = entry->buf;
1152		1215
1153	entry->len = len;	1216	len = entry->len;
1154		1217
1155	if (!chan)	1218	if (!chan)
1156	goto err;	1219	goto err;
@@ -1226,7 +1289,6 @@ static int ntb_process_rxc(struct ntb_transport_qp *qp) · 69 unmodified lines
1226	struct ntb_payload_header *hdr;	1289	struct ntb_payload_header *hdr;
1227	struct ntb_queue_entry *entry;	1290	struct ntb_queue_entry *entry;
1228	void *offset;	1291	void *offset;
1229	int rc;
1230		1292
1231	offset = qp->rx_buff + qp->rx_max_frame * qp->rx_index;	1293	offset = qp->rx_buff + qp->rx_max_frame * qp->rx_index;
1232	hdr = offset + qp->rx_max_frame - sizeof(struct ntb_payload_header);	1294	hdr = offset + qp->rx_max_frame - sizeof(struct ntb_payload_header);
@@ -1255,65 +1317,43 @@ static int ntb_process_rxc(struct ntb_transport_qp *qp) · 22 unmodified lines
1255	return -EIO;	1317	return -EIO;
1256	}	1318	}
1257		1319
1258	entry = ntb_list_rm(&qp->ntb_rx_pend_q_lock, &qp->rx_pend_q);	1320	entry = ntb_list_mv(&qp->ntb_rx_q_lock, &qp->rx_pend_q, &qp->rx_post_q);
1259	if (!entry) {	1321	if (!entry) {
1260	dev_dbg(&qp->ndev->pdev->dev, "no receive buffer\n");	1322	dev_dbg(&qp->ndev->pdev->dev, "no receive buffer\n");
1261	qp->rx_err_no_buf++;	1323	qp->rx_err_no_buf++;
1262		1324	return -EAGAIN;
1263	rc = -ENOMEM;
1264	goto err;
1265	}	1325	}
1266		1326
		1327	entry->rx_hdr = hdr;
		1328	entry->index = qp->rx_index;
		1329
1267	if (hdr->len > entry->len) {	1330	if (hdr->len > entry->len) {
1268	dev_dbg(&qp->ndev->pdev->dev,	1331	dev_dbg(&qp->ndev->pdev->dev,
1269	"receive buffer overflow! Wanted %d got %d\n",	1332	"receive buffer overflow! Wanted %d got %d\n",
1270	hdr->len, entry->len);	1333	hdr->len, entry->len);
1271	qp->rx_err_oflow++;	1334	qp->rx_err_oflow++;
1272		1335
1273	rc = -EIO;	1336	entry->len = -EIO;
1274	goto err;	1337	entry->flags \|= DESC_DONE_FLAG;
1275	}
1276		1338
1277	dev_dbg(&qp->ndev->pdev->dev,	1339	ntb_complete_rxc(qp);
1278	"RX OK index %u ver %u size %d into buf size %d\n",	1340	} else {
1279	qp->rx_index, hdr->ver, hdr->len, entry->len);	1341	dev_dbg(&qp->ndev->pdev->dev,
		1342	"RX OK index %u ver %u size %d into buf size %d\n",
		1343	qp->rx_index, hdr->ver, hdr->len, entry->len);
1280		1344
1281	qp->rx_bytes += hdr->len;	1345	qp->rx_bytes += hdr->len;
1282	qp->rx_pkts++;	1346	qp->rx_pkts++;
1283		1347
1284	entry->index = qp->rx_index;	1348	entry->len = hdr->len;
1285	entry->rx_hdr = hdr;
1286		1349
1287	ntb_async_rx(entry, offset, hdr->len);	1350	ntb_async_rx(entry, offset);
		1351	}
1288		1352
1289	qp->rx_index++;	1353	qp->rx_index++;
1290	qp->rx_index %= qp->rx_max_entry;	1354	qp->rx_index %= qp->rx_max_entry;
1291		1355
1292	return 0;	1356	return 0;
1293
1294	err:
1295	/* FIXME: if this syncrhonous update of the rx_index gets ahead of
1296	* asyncrhonous ntb_rx_copy_callback of previous entry, there are three
1297	* scenarios:
1298	*
1299	* 1) The peer might miss this update, but observe the update
1300	* from the memcpy completion callback. In this case, the buffer will
1301	* not be freed on the peer to be reused for a different packet. The
1302	* successful rx of a later packet would clear the condition, but the
1303	* condition could persist if several rx fail in a row.
1304	*
1305	* 2) The peer may observe this update before the asyncrhonous copy of
1306	* prior packets is completed. The peer may overwrite the buffers of
1307	* the prior packets before they are copied.
1308	*
1309	* 3) Both: the peer may observe the update, and then observe the index
1310	* decrement by the asynchronous completion callback. Who knows what
1311	* badness that will cause.
1312	*/
1313	hdr->flags = 0;
1314	iowrite32(qp->rx_index, &qp->rx_info->entry);
1315
1316	return rc;
1317	}	1357	}
1318		1358
1319	static void ntb_transport_rxc_db(unsigned long data)	1359	static void ntb_transport_rxc_db(unsigned long data)
@@ -1333,7 +1373,7 @@ static void ntb_transport_rxc_db(unsigned long data) · 13 unmodified lines
1333	break;	1373	break;
1334	}	1374	}
1335		1375
1336	if (qp->dma_chan)	1376	if (i && qp->dma_chan)
1337	dma_async_issue_pending(qp->dma_chan);	1377	dma_async_issue_pending(qp->dma_chan);
1338		1378
1339	if (i == qp->rx_max_entry) {	1379	if (i == qp->rx_max_entry) {
@@ -1609,7 +1649,7 @@ ntb_transport_create_queue(void data, struct device client_dev, · 269 unmodified lines
1609	goto err1;	1649	goto err1;
1610		1650
1611	entry->qp = qp;	1651	entry->qp = qp;
1612	ntb_list_add(&qp->ntb_rx_free_q_lock, &entry->entry,	1652	ntb_list_add(&qp->ntb_rx_q_lock, &entry->entry,
1613	&qp->rx_free_q);	1653	&qp->rx_free_q);
1614	}	1654	}
1615		1655
@@ -1634,7 +1674,7 @@ err2: · 18 unmodified lines
1634	while ((entry = ntb_list_rm(&qp->ntb_tx_free_q_lock, &qp->tx_free_q)))	1674	while ((entry = ntb_list_rm(&qp->ntb_tx_free_q_lock, &qp->tx_free_q)))
1635	kfree(entry);	1675	kfree(entry);
1636	err1:	1676	err1:
1637	while ((entry = ntb_list_rm(&qp->ntb_rx_free_q_lock, &qp->rx_free_q)))	1677	while ((entry = ntb_list_rm(&qp->ntb_rx_q_lock, &qp->rx_free_q)))
1638	kfree(entry);	1678	kfree(entry);
1639	if (qp->dma_chan)	1679	if (qp->dma_chan)
1640	dma_release_channel(qp->dma_chan);	1680	dma_release_channel(qp->dma_chan);
@@ -1652,7 +1692,6 @@ EXPORT_SYMBOL_GPL(ntb_transport_create_queue); · 11 unmodified lines
1652	*/	1692	*/
1653	void ntb_transport_free_queue(struct ntb_transport_qp *qp)	1693	void ntb_transport_free_queue(struct ntb_transport_qp *qp)
1654	{	1694	{
1655	struct ntb_transport_ctx *nt = qp->transport;
1656	struct pci_dev *pdev;	1695	struct pci_dev *pdev;
1657	struct ntb_queue_entry *entry;	1696	struct ntb_queue_entry *entry;
1658	u64 qp_bit;	1697	u64 qp_bit;
@@ -1689,18 +1728,23 @@ void ntb_transport_free_queue(struct ntb_transport_qp *qp) · 30 unmodified lines
1689	qp->tx_handler = NULL;	1728	qp->tx_handler = NULL;
1690	qp->event_handler = NULL;	1729	qp->event_handler = NULL;
1691		1730
1692	while ((entry = ntb_list_rm(&qp->ntb_rx_free_q_lock, &qp->rx_free_q)))	1731	while ((entry = ntb_list_rm(&qp->ntb_rx_q_lock, &qp->rx_free_q)))
1693	kfree(entry);	1732	kfree(entry);
1694		1733
1695	while ((entry = ntb_list_rm(&qp->ntb_rx_pend_q_lock, &qp->rx_pend_q))) {	1734	while ((entry = ntb_list_rm(&qp->ntb_rx_q_lock, &qp->rx_pend_q))) {
1696	dev_warn(&pdev->dev, "Freeing item from a non-empty queue\n");	1735	dev_warn(&pdev->dev, "Freeing item from non-empty rx_pend_q\n");
		1736	kfree(entry);
		1737	}
		1738
		1739	while ((entry = ntb_list_rm(&qp->ntb_rx_q_lock, &qp->rx_post_q))) {
		1740	dev_warn(&pdev->dev, "Freeing item from non-empty rx_post_q\n");
1697	kfree(entry);	1741	kfree(entry);
1698	}	1742	}
1699		1743
1700	while ((entry = ntb_list_rm(&qp->ntb_tx_free_q_lock, &qp->tx_free_q)))	1744	while ((entry = ntb_list_rm(&qp->ntb_tx_free_q_lock, &qp->tx_free_q)))
1701	kfree(entry);	1745	kfree(entry);
1702		1746
1703	nt->qp_bitmap_free \|= qp_bit;	1747	qp->transport->qp_bitmap_free \|= qp_bit;
1704		1748
1705	dev_info(&pdev->dev, "NTB Transport QP %d freed\n", qp->qp_num);	1749	dev_info(&pdev->dev, "NTB Transport QP %d freed\n", qp->qp_num);
1706	}	1750	}
@@ -1724,14 +1768,14 @@ void ntb_transport_rx_remove(struct ntb_transport_qp qp, unsigned int *len) · 17 unmodified lines
1724	if (!qp \|\| qp->client_ready)	1768	if (!qp \|\| qp->client_ready)
1725	return NULL;	1769	return NULL;
1726		1770
1727	entry = ntb_list_rm(&qp->ntb_rx_pend_q_lock, &qp->rx_pend_q);	1771	entry = ntb_list_rm(&qp->ntb_rx_q_lock, &qp->rx_pend_q);
1728	if (!entry)	1772	if (!entry)
1729	return NULL;	1773	return NULL;
1730		1774
1731	buf = entry->cb_data;	1775	buf = entry->cb_data;
1732	*len = entry->len;	1776	*len = entry->len;
1733		1777
1734	ntb_list_add(&qp->ntb_rx_free_q_lock, &entry->entry, &qp->rx_free_q);	1778	ntb_list_add(&qp->ntb_rx_q_lock, &entry->entry, &qp->rx_free_q);
1735		1779
1736	return buf;	1780	return buf;
1737	}	1781	}
@@ -1757,15 +1801,18 @@ int ntb_transport_rx_enqueue(struct ntb_transport_qp qp, void cb, void *data, · 19 unmodified lines
1757	if (!qp)	1801	if (!qp)
1758	return -EINVAL;	1802	return -EINVAL;
1759		1803
1760	entry = ntb_list_rm(&qp->ntb_rx_free_q_lock, &qp->rx_free_q);	1804	entry = ntb_list_rm(&qp->ntb_rx_q_lock, &qp->rx_free_q);
1761	if (!entry)	1805	if (!entry)
1762	return -ENOMEM;	1806	return -ENOMEM;
1763		1807
1764	entry->cb_data = cb;	1808	entry->cb_data = cb;
1765	entry->buf = data;	1809	entry->buf = data;
1766	entry->len = len;	1810	entry->len = len;
		1811	entry->flags = 0;
		1812
		1813	ntb_list_add(&qp->ntb_rx_q_lock, &entry->entry, &qp->rx_pend_q);
1767		1814
1768	ntb_list_add(&qp->ntb_rx_pend_q_lock, &entry->entry, &qp->rx_pend_q);	1815	tasklet_schedule(&qp->rxc_db_work);
1769		1816
1770	return 0;	1817	return 0;
1771	}	1818	}

drivers/nvdimm/region_devs.c+5−0

 		nvdimm_bus_unlock(dev);
 	}
 	if (is_nd_btt(dev) && probe) {
+		struct nd_btt *nd_btt = to_nd_btt(dev);
 		nd_region = to_nd_region(dev->parent);
 		nvdimm_bus_lock(dev);
 		if (nd_region->btt_seed == dev)
 			nd_region_create_btt_seed(nd_region);
+		if (nd_region->ns_seed == &nd_btt->ndns->dev &&
+				is_nd_blk(dev->parent))
+			nd_region_create_blk_seed(nd_region);
 		nvdimm_bus_unlock(dev);
 	}
 }

drivers/of/Kconfig+1−1

@@ -47,7 +47,7 @@ config OF_DYNAMIC · 46 unmodified lines
47		47
48	config OF_ADDRESS	48	config OF_ADDRESS
49	def_bool y	49	def_bool y
50	depends on !SPARC	50	depends on !SPARC && HAS_IOMEM
51	select OF_ADDRESS_PCI if PCI	51	select OF_ADDRESS_PCI if PCI
52		52
53	config OF_ADDRESS_PCI	53	config OF_ADDRESS_PCI

drivers/of/unittest.c+0−3

 	.remove			= unittest_remove,
 	.driver = {
 		.name		= "unittest",
-		.owner		= THIS_MODULE,
 		.of_match_table	= of_match_ptr(unittest_match),
 	},
 };
 static struct i2c_driver unittest_i2c_dev_driver = {
 	.driver = {
 		.name = "unittest-i2c-dev",
-		.owner = THIS_MODULE,
 	},
 	.probe = unittest_i2c_dev_probe,
 	.remove = unittest_i2c_dev_remove,
 static struct i2c_driver unittest_i2c_mux_driver = {
 	.driver = {
 		.name = "unittest-i2c-mux",
-		.owner = THIS_MODULE,
 	},
 	.probe = unittest_i2c_mux_probe,
 	.remove = unittest_i2c_mux_remove,

drivers/parport/share.c+6−5

 	par_dev->dev.release = free_pardevice;
 	par_dev->devmodel = true;
 	ret = device_register(&par_dev->dev);
-	if (ret)
+	if (ret) {
-		goto err_put_dev;
+		put_device(&par_dev->dev);
+		goto err_put_port;
+	}
 	/* Chain this onto the list */
 	par_dev->prev = NULL;
 			spin_unlock(&port->physport->pardevice_lock);
 			pr_debug("%s: cannot grant exclusive access for device %s\n",
 				 port->name, name);
-			goto err_put_dev;
+			device_unregister(&par_dev->dev);
+			goto err_put_port;
 		}
 		port->flags |= PARPORT_FLAG_EXCL;
 	}
 	return par_dev;
-err_put_dev:
-	put_device(&par_dev->dev);
 err_free_devname:
 	kfree(devname);
 err_free_par_dev:

drivers/phy/Kconfig+2−0

 config PHY_PXA_28NM_HSIC
 	tristate "Marvell USB HSIC 28nm PHY Driver"
+	depends on HAS_IOMEM
 	select GENERIC_PHY
 	help
 	  Enable this to support Marvell USB HSIC PHY driver for Marvell
 config PHY_PXA_28NM_USB2
 	tristate "Marvell USB 2.0 28nm PHY Driver"
+	depends on HAS_IOMEM
 	select GENERIC_PHY
 	help
 	  Enable this to support Marvell USB 2.0 PHY driver for Marvell

drivers/phy/phy-berlin-usb.c+2−2

 static const u32 phy_berlin_pll_dividers[] = {
 	/* Berlin 2 */
-	CLK_REF_DIV(0xc) | FEEDBACK_CLK_DIV(0x54),
-	/* Berlin 2CD */
 	CLK_REF_DIV(0x6) | FEEDBACK_CLK_DIV(0x55),
+	/* Berlin 2CD/Q */
+	CLK_REF_DIV(0xc) | FEEDBACK_CLK_DIV(0x54),
 };
 struct phy_berlin_usb_priv {

drivers/phy/phy-sun4i-usb.c+1−0

@@ -212,6 +212,7 @@ void sun4i_usb_phy_set_squelch_detect(struct phy *_phy, bool enabled) · 211 unmodified lines
212		212
213	sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2);	213	sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2);
214	}	214	}
		215	EXPORT_SYMBOL_GPL(sun4i_usb_phy_set_squelch_detect);
215		216
216	static struct phy_ops sun4i_usb_phy_ops = {	217	static struct phy_ops sun4i_usb_phy_ops = {
217	.init = sun4i_usb_phy_init,	218	.init = sun4i_usb_phy_init,

drivers/phy/phy-ti-pipe3.c+88−129

 #include <linux/delay.h>
 #include <linux/phy/omap_control_phy.h>
 #include <linux/of_platform.h>
-#include <linux/spinlock.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
 #define	PLL_STATUS		0x00000004
 #define	PLL_GO			0x00000008
 #define	PLL_LOCK		0x2
 #define	PLL_IDLE		0x1
+#define SATA_PLL_SOFT_RESET	BIT(18)
 /*
  * This is an Empirical value that works, need to confirm the actual
  * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
 	struct clk		*refclk;
 	struct clk		*div_clk;
 	struct pipe3_dpll_map	*dpll_map;
-	bool			enabled;
+	struct regmap		*dpll_reset_syscon; /* ctrl. reg. acces */
-	spinlock_t		lock;	/* serialize clock enable/disable */
+	unsigned int		dpll_reset_reg; /* reg. index within syscon */
-	/* the below flag is needed specifically for SATA */
+	bool			sata_refclk_enabled;
-	bool			refclk_enabled;
 };
 static struct pipe3_dpll_map dpll_map_usb[] = {
 	return NULL;
 }
+static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy);
+static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy);
 static int ti_pipe3_power_off(struct phy *x)
 {
 	struct ti_pipe3 *phy = phy_get_drvdata(x);
 	u32 val;
 	int ret = 0;
+	ti_pipe3_enable_clocks(phy);
 	/*
 	 * Set pcie_pcs register to 0x96 for proper functioning of phy
 	 * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
 	u32 val;
 	unsigned long timeout;
-	/* SATA DPLL can't be powered down due to Errata i783 and PCIe
+	/* If dpll_reset_syscon is not present we wont power down SATA DPLL
-	 * does not have internal DPLL
+	 * due to Errata i783
 	 */
-	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") ||
+	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") &&
-	    of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
+	    !phy->dpll_reset_syscon)
 		return 0;
-	/* Put DPLL in IDLE mode */
+	/* PCIe doesn't have internal DPLL */
-	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
+	if (!of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
-	val |= PLL_IDLE;
+		/* Put DPLL in IDLE mode */
-	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
+		val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
+		val |= PLL_IDLE;
+		ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
-	/* wait for LDO and Oscillator to power down */
+		/* wait for LDO and Oscillator to power down */
-	timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
+		timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
-	do {
+		do {
-		cpu_relax();
+			cpu_relax();
-		val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
+			val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
-		if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
+			if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
-			break;
+				break;
-	} while (!time_after(jiffies, timeout));
+		} while (!time_after(jiffies, timeout));
+		if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
+			dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
+				val);
+			return -EBUSY;
+		}
+	}
-	if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
+	/* i783: SATA needs control bit toggle after PLL unlock */
-		dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
+	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata")) {
-			val);
+		regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
-		return -EBUSY;
+				   SATA_PLL_SOFT_RESET, SATA_PLL_SOFT_RESET);
+		regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
+				   SATA_PLL_SOFT_RESET, 0);
 	}
+	ti_pipe3_disable_clocks(phy);
 	return 0;
 }
 static struct phy_ops ops = {
 		return -ENOMEM;
 	phy->dev		= &pdev->dev;
-	spin_lock_init(&phy->lock);
 	if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
 		match = of_match_device(ti_pipe3_id_table, &pdev->dev);
 		}
 	} else {
 		phy->wkupclk = ERR_PTR(-ENODEV);
+		phy->dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node,
+							"syscon-pllreset");
+		if (IS_ERR(phy->dpll_reset_syscon)) {
+			dev_info(&pdev->dev,
+				 "can't get syscon-pllreset, sata dpll won't idle\n");
+			phy->dpll_reset_syscon = NULL;
+		} else {
+			if (of_property_read_u32_index(node,
+						       "syscon-pllreset", 1,
+						       &phy->dpll_reset_reg)) {
+				dev_err(&pdev->dev,
+					"couldn't get pllreset reg. offset\n");
+				return -EINVAL;
+			}
+		}
 	}
 	if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
 	platform_set_drvdata(pdev, phy);
 	pm_runtime_enable(phy->dev);
+	/*
+	 * Prevent auto-disable of refclk for SATA PHY due to Errata i783
+	 */
+	if (of_device_is_compatible(node, "ti,phy-pipe3-sata")) {
+		if (!IS_ERR(phy->refclk)) {
+			clk_prepare_enable(phy->refclk);
+			phy->sata_refclk_enabled = true;
+		}
+	}
 	generic_phy = devm_phy_create(phy->dev, NULL, &ops);
 	if (IS_ERR(generic_phy))
 		return PTR_ERR(generic_phy);
 	if (IS_ERR(phy_provider))
 		return PTR_ERR(phy_provider);
-	pm_runtime_get(&pdev->dev);
 	return 0;
 }
 static int ti_pipe3_remove(struct platform_device *pdev)
 {
-	if (!pm_runtime_suspended(&pdev->dev))
-		pm_runtime_put(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
 	return 0;
 }
-#ifdef CONFIG_PM
+static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy)
-static int ti_pipe3_enable_refclk(struct ti_pipe3 *phy)
 {
-	if (!IS_ERR(phy->refclk) && !phy->refclk_enabled) {
+	int ret = 0;
-		int ret;
+	if (!IS_ERR(phy->refclk)) {
 		ret = clk_prepare_enable(phy->refclk);
 		if (ret) {
 			dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
 			return ret;
 		}
-		phy->refclk_enabled = true;
 	}
-	return 0;
-}
-static void ti_pipe3_disable_refclk(struct ti_pipe3 *phy)
-{
-	if (!IS_ERR(phy->refclk))
-		clk_disable_unprepare(phy->refclk);
-	phy->refclk_enabled = false;
-}
-static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy)
-{
-	int ret = 0;
-	unsigned long flags;
-	spin_lock_irqsave(&phy->lock, flags);
-	if (phy->enabled)
-		goto err1;
-	ret = ti_pipe3_enable_refclk(phy);
-	if (ret)
-		goto err1;
 	if (!IS_ERR(phy->wkupclk)) {
 		ret = clk_prepare_enable(phy->wkupclk);
 		if (ret) {
 			dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
-			goto err2;
+			goto disable_refclk;
 		}
 	}
 		ret = clk_prepare_enable(phy->div_clk);
 		if (ret) {
 			dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);
-			goto err3;
+			goto disable_wkupclk;
 		}
 	}
-	phy->enabled = true;
-	spin_unlock_irqrestore(&phy->lock, flags);
 	return 0;
-err3:
+disable_wkupclk:
 	if (!IS_ERR(phy->wkupclk))
 		clk_disable_unprepare(phy->wkupclk);
-err2:
+disable_refclk:
 	if (!IS_ERR(phy->refclk))
 		clk_disable_unprepare(phy->refclk);
-	ti_pipe3_disable_refclk(phy);
-err1:
-	spin_unlock_irqrestore(&phy->lock, flags);
 	return ret;
 }
 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy)
 {
-	unsigned long flags;
-	spin_lock_irqsave(&phy->lock, flags);
-	if (!phy->enabled) {
-		spin_unlock_irqrestore(&phy->lock, flags);
-		return;
-	}
 	if (!IS_ERR(phy->wkupclk))
 		clk_disable_unprepare(phy->wkupclk);
-	/* Don't disable refclk for SATA PHY due to Errata i783 */
+	if (!IS_ERR(phy->refclk)) {
-	if (!of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata"))
+		clk_disable_unprepare(phy->refclk);
-		ti_pipe3_disable_refclk(phy);
+		/*
+		 * SATA refclk needs an additional disable as we left it
+		 * on in probe to avoid Errata i783
+		 */
+		if (phy->sata_refclk_enabled) {
+			clk_disable_unprepare(phy->refclk);
+			phy->sata_refclk_enabled = false;
+		}
+	}
 	if (!IS_ERR(phy->div_clk))
 		clk_disable_unprepare(phy->div_clk);
-	phy->enabled = false;
-	spin_unlock_irqrestore(&phy->lock, flags);
 }
-static int ti_pipe3_runtime_suspend(struct device *dev)
-{
-	struct ti_pipe3	*phy = dev_get_drvdata(dev);
-	ti_pipe3_disable_clocks(phy);
-	return 0;
-}
-static int ti_pipe3_runtime_resume(struct device *dev)
-{
-	struct ti_pipe3	*phy = dev_get_drvdata(dev);
-	int ret = 0;
-	ret = ti_pipe3_enable_clocks(phy);
-	return ret;
-}
-static int ti_pipe3_suspend(struct device *dev)
-{
-	struct ti_pipe3	*phy = dev_get_drvdata(dev);
-	ti_pipe3_disable_clocks(phy);
-	return 0;
-}
-static int ti_pipe3_resume(struct device *dev)
-{
-	struct ti_pipe3	*phy = dev_get_drvdata(dev);
-	int ret;
-	ret = ti_pipe3_enable_clocks(phy);
-	if (ret)
-		return ret;
-	pm_runtime_disable(dev);
-	pm_runtime_set_active(dev);
-	pm_runtime_enable(dev);
-	return 0;
-}
-#endif
-static const struct dev_pm_ops ti_pipe3_pm_ops = {
-	SET_RUNTIME_PM_OPS(ti_pipe3_runtime_suspend,
-			   ti_pipe3_runtime_resume, NULL)
-	SET_SYSTEM_SLEEP_PM_OPS(ti_pipe3_suspend, ti_pipe3_resume)
-};
 static const struct of_device_id ti_pipe3_id_table[] = {
 	{
 		.compatible = "ti,phy-usb3",
 	.remove		= ti_pipe3_remove,
 	.driver		= {
 		.name	= "ti-pipe3",
-		.pm	= &ti_pipe3_pm_ops,
 		.of_match_table = ti_pipe3_id_table,
 	},
 };

drivers/pinctrl/bcm/pinctrl-bcm2835.c+2−0

@@ -473,6 +473,8 @@ static void bcm2835_gpio_irq_disable(struct irq_data *data) · 472 unmodified lines
473		473
474	spin_lock_irqsave(&pc->irq_lock[bank], flags);	474	spin_lock_irqsave(&pc->irq_lock[bank], flags);
475	bcm2835_gpio_irq_config(pc, gpio, false);	475	bcm2835_gpio_irq_config(pc, gpio, false);
		476	/* Clear events that were latched prior to clearing event sources */
		477	bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
476	clear_bit(offset, &pc->enabled_irq_map[bank]);	478	clear_bit(offset, &pc->enabled_irq_map[bank]);
477	spin_unlock_irqrestore(&pc->irq_lock[bank], flags);	479	spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
478	}	480	}

drivers/pinctrl/freescale/pinctrl-imx1-core.c+1−2

 			     unsigned num_configs)
 {
 	struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
-	const struct imx1_pinctrl_soc_info *info = ipctl->info;
 	int i;
 	for (i = 0; i != num_configs; ++i) {
 		imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN);
 		dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n",
-			info->pins[pin_id].name);
+			pin_desc_get(pctldev, pin_id)->name);
 	}
 	return 0;

drivers/pinctrl/nomadik/pinctrl-abx500.c+0−1

@@ -787,7 +787,6 @@ static const struct pinmux_ops abx500_pinmux_ops = { · 786 unmodified lines
787	.set_mux = abx500_pmx_set,	787	.set_mux = abx500_pmx_set,
788	.gpio_request_enable = abx500_gpio_request_enable,	788	.gpio_request_enable = abx500_gpio_request_enable,
789	.gpio_disable_free = abx500_gpio_disable_free,	789	.gpio_disable_free = abx500_gpio_disable_free,
790	.strict = true,
791	};	790	};
792		791
793	static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev)	792	static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev)

drivers/pinctrl/pinctrl-lpc18xx.c+2−2

@@ -823,7 +823,7 @@ static int lpc18xx_pconf_set_i2c0(struct pinctrl_dev *pctldev, · 822 unmodified lines
823	break;	823	break;
824		824
825	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:	825	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
826	if (param)	826	if (param_val)
827	*reg &= ~(LPC18XX_SCU_I2C0_ZIF << shift);	827	*reg &= ~(LPC18XX_SCU_I2C0_ZIF << shift);
828	else	828	else
829	*reg \|= (LPC18XX_SCU_I2C0_ZIF << shift);	829	*reg \|= (LPC18XX_SCU_I2C0_ZIF << shift);
@@ -876,7 +876,7 @@ static int lpc18xx_pconf_set_pin(struct pinctrl_dev *pctldev, · 46 unmodified lines
876	break;	876	break;
877		877
878	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:	878	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
879	if (param)	879	if (param_val)
880	*reg &= ~LPC18XX_SCU_PIN_ZIF;	880	*reg &= ~LPC18XX_SCU_PIN_ZIF;
881	else	881	else
882	*reg \|= LPC18XX_SCU_PIN_ZIF;	882	*reg \|= LPC18XX_SCU_PIN_ZIF;

drivers/pinctrl/pinctrl-single.c+2−1

@@ -1760,7 +1760,8 @@ static int pcs_irq_init_chained_handler(struct pcs_device *pcs, · 1759 unmodified lines
1760	int res;	1760	int res;
1761		1761
1762	res = request_irq(pcs_soc->irq, pcs_irq_handler,	1762	res = request_irq(pcs_soc->irq, pcs_irq_handler,
1763	IRQF_SHARED \| IRQF_NO_SUSPEND,	1763	IRQF_SHARED \| IRQF_NO_SUSPEND \|
		1764	IRQF_NO_THREAD,
1764	name, pcs_soc);	1765	name, pcs_soc);
1765	if (res) {	1766	if (res) {
1766	pcs_soc->irq = -1;	1767	pcs_soc->irq = -1;

drivers/pinctrl/samsung/pinctrl-samsung.c+0−5

 #include "../core.h"
 #include "pinctrl-samsung.h"
-#define GROUP_SUFFIX		"-grp"
-#define GSUFFIX_LEN		sizeof(GROUP_SUFFIX)
-#define FUNCTION_SUFFIX		"-mux"
-#define FSUFFIX_LEN		sizeof(FUNCTION_SUFFIX)
 /* list of all possible config options supported */
 static struct pin_config {
 	const char *property;

drivers/pinctrl/sh-pfc/sh_pfc.h+1−1

@@ -224,7 +224,7 @@ struct sh_pfc_soc_info { · 223 unmodified lines
224		224
225	/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */	225	/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
226	#define _GP_GPIO(bank, _pin, _name, sfx) \	226	#define _GP_GPIO(bank, _pin, _name, sfx) \
227	[(bank * 32) + _pin] = { \	227	{ \
228	.pin = (bank * 32) + _pin, \	228	.pin = (bank * 32) + _pin, \
229	.name = __stringify(_name), \	229	.name = __stringify(_name), \
230	.enum_id = _name##_DATA, \	230	.enum_id = _name##_DATA, \

drivers/platform/chrome/Kconfig+0−1

@@ -4,7 +4,6 @@ · 3 unmodified lines
4		4
5	menuconfig CHROME_PLATFORMS	5	menuconfig CHROME_PLATFORMS
6	bool "Platform support for Chrome hardware"	6	bool "Platform support for Chrome hardware"
7	depends on X86 \|\| ARM
8	---help---	7	---help---
9	Say Y here to get to see options for platform support for	8	Say Y here to get to see options for platform support for
10	various Chromebooks and Chromeboxes. This option alone does	9	various Chromebooks and Chromeboxes. This option alone does

drivers/regulator/88pm800.c+1−1

@@ -130,7 +130,7 @@ struct pm800_regulators { · 129 unmodified lines
130	.owner = THIS_MODULE, \	130	.owner = THIS_MODULE, \
131	.n_voltages = ARRAY_SIZE(ldo_volt_table), \	131	.n_voltages = ARRAY_SIZE(ldo_volt_table), \
132	.vsel_reg = PM800_##vreg##_VOUT, \	132	.vsel_reg = PM800_##vreg##_VOUT, \
133	.vsel_mask = 0x1f, \	133	.vsel_mask = 0xf, \
134	.enable_reg = PM800_##ereg, \	134	.enable_reg = PM800_##ereg, \
135	.enable_mask = 1 << (ebit), \	135	.enable_mask = 1 << (ebit), \
136	.volt_table = ldo_volt_table, \	136	.volt_table = ldo_volt_table, \

drivers/regulator/core.c+15−4

 static struct regulator *create_regulator(struct regulator_dev *rdev,
 					  struct device *dev,
 					  const char *supply_name);
+static void _regulator_put(struct regulator *regulator);
 static const char *rdev_get_name(struct regulator_dev *rdev)
 {
 	rdev_info(rdev, "supplied by %s\n", rdev_get_name(supply_rdev));
+	if (!try_module_get(supply_rdev->owner))
+		return -ENODEV;
 	rdev->supply = create_regulator(supply_rdev, &rdev->dev, "SUPPLY");
 	if (rdev->supply == NULL) {
 		err = -ENOMEM;
 	}
 	if (!r) {
-		dev_err(dev, "Failed to resolve %s-supply for %s\n",
+		if (have_full_constraints()) {
-			rdev->supply_name, rdev->desc->name);
+			r = dummy_regulator_rdev;
-		return -EPROBE_DEFER;
+		} else {
+			dev_err(dev, "Failed to resolve %s-supply for %s\n",
+				rdev->supply_name, rdev->desc->name);
+			return -EPROBE_DEFER;
+		}
 	}
 	/* Recursively resolve the supply of the supply */
 	/* Cascade always-on state to supply */
 	if (_regulator_is_enabled(rdev)) {
 		ret = regulator_enable(rdev->supply);
-		if (ret < 0)
+		if (ret < 0) {
+			if (rdev->supply)
+				_regulator_put(rdev->supply);
 			return ret;
+		}
 	}
 	return 0;

drivers/regulator/max8973-regulator.c+1−1

@@ -450,7 +450,7 @@ static struct max8973_regulator_platform_data *max8973_parse_dt( · 449 unmodified lines
450	pdata->control_flags \|= MAX8973_CONTROL_FREQ_SHIFT_9PER_ENABLE;	450	pdata->control_flags \|= MAX8973_CONTROL_FREQ_SHIFT_9PER_ENABLE;
451		451
452	if (of_property_read_bool(np, "maxim,enable-bias-control"))	452	if (of_property_read_bool(np, "maxim,enable-bias-control"))
453	pdata->control_flags \|= MAX8973_BIAS_ENABLE;	453	pdata->control_flags \|= MAX8973_CONTROL_BIAS_ENABLE;
454		454
455	return pdata;	455	return pdata;
456	}	456	}

drivers/regulator/s2mps11.c+10−4

 #include <linux/mfd/samsung/s2mps14.h>
 #include <linux/mfd/samsung/s2mpu02.h>
+/* The highest number of possible regulators for supported devices. */
+#define S2MPS_REGULATOR_MAX		S2MPS13_REGULATOR_MAX
 struct s2mps11_info {
 	unsigned int rdev_num;
 	int ramp_delay2;
 	 * One bit for each S2MPS13/S2MPS14/S2MPU02 regulator whether
 	 * the suspend mode was enabled.
 	 */
-	unsigned long long s2mps14_suspend_state:50;

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drivers/s390/virtio/Makefilerenamed from drivers/s390/kvm/Makefile+0−0

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drivers/s390/virtio/kvm_virtio.crenamed from drivers/s390/kvm/kvm_virtio.c+0−0

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drivers/s390/virtio/virtio_ccw.crenamed from drivers/s390/kvm/virtio_ccw.c+0−0

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drivers/xen/xenbus/xenbus_client.c+3−1

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include/linux/platform_data/mmc-esdhc-imx.h+0−1

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net/batman-adv/distributed-arp-table.c+13−5

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net/bridge/br_mdb.c+1−1

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net/bridge/br_multicast.c+56−31

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net/bridge/br_netlink.c+13−1

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net/bridge/br_stp_if.c+12−1

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net/bridge/br_stp_timer.c+3−1

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net/caif/caif_socket.c+8−11

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net/core/datagram.c+48−9

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net/core/dst.c+3−1

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net/core/request_sock.c+7−1

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net/core/rtnetlink.c+7−4

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net/core/sock.c+5−3

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net/dccp/proto.c+1−1

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net/ieee802154/6lowpan/reassembly.c+3−3

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net/ipv4/arp.c+9−7

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net/ipv4/datagram.c+12−4

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net/ipv4/devinet.c+0−1

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net/ipv4/fib_semantics.c+30−11

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net/ipv4/fib_trie.c+2−5

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net/ipv4/inet_connection_sock.c+1−1

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net/ipv4/inet_fragment.c+15−25

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net/ipv4/inet_hashtables.c+5−6

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net/ipv4/ip_fragment.c+10−8

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net/ipv4/netfilter/ipt_SYNPROXY.c+2−1

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net/ipv4/route.c+1−1

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net/ipv4/tcp_input.c+1−2

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net/ipv4/udp.c+10−3

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net/ipv6/ndisc.c+6−0

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net/ipv6/netfilter/ip6t_SYNPROXY.c+11−8

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net/ipv6/netfilter/nf_conntrack_reasm.c+3−3

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net/ipv6/reassembly.c+4−4

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net/ipv6/tcp_ipv6.c+1−1

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net/mac80211/debugfs_netdev.c+1−0

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net/mac80211/mesh_plink.c+4−1

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net/mac80211/tdls.c+3−3

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net/mac80211/tx.c+3−1

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net/netfilter/ipvs/ip_vs_core.c+14−2

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net/netfilter/ipvs/ip_vs_ctl.c+49−29

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net/netfilter/ipvs/ip_vs_sched.c+6−6

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net/netfilter/ipvs/ip_vs_sync.c+1−1

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net/netfilter/ipvs/ip_vs_xmit.c+40−1

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net/netfilter/nf_conntrack_core.c+45−26

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net/netfilter/nf_conntrack_expect.c+2−1

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net/netfilter/nf_conntrack_netlink.c+0−5

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net/netfilter/nf_synproxy_core.c+4−7

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net/netfilter/xt_CT.c+6−7

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net/netfilter/xt_IDLETIMER.c+1−0

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net/netlink/af_netlink.c+52−32

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net/openvswitch/actions.c+12−4

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net/openvswitch/flow_table.c+1−1

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net/packet/af_packet.c+5−6

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net/sched/act_bpf.c+35−15

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net/sunrpc/xprtsock.c+17−8

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net/wireless/chan.c+34−11

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net/wireless/nl80211.c+8−6

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net/wireless/reg.c+4−4

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net/wireless/trace.h+7−4

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samples/trace_events/trace-events-sample.h+5−2

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scripts/kconfig/streamline_config.pl+1−1

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security/keys/keyring.c+5−3

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security/yama/yama_lsm.c+1−0

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sound/core/pcm_native.c+1−1

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sound/firewire/amdtp.c+3−2

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sound/firewire/fireworks/fireworks.c+8−0

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sound/hda/ext/hdac_ext_controller.c+0−6

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sound/hda/ext/hdac_ext_stream.c+1−1

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sound/hda/hdac_i915.c+4−1

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sound/pci/hda/hda_intel.c+21−11

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sound/pci/hda/patch_cirrus.c+1−3

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sound/pci/hda/patch_realtek.c+67−13

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sound/soc/codecs/cs4265.c+5−5

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@@ -160,18 +160,18 @@ static inline void setup_protection_map(void) · 159 unmodified lines
160	protection_map[1] = __pgprot(_page_cachable_default \| _PAGE_PRESENT \| _PAGE_NO_EXEC);	160	protection_map[1] = __pgprot(_page_cachable_default \| _PAGE_PRESENT \| _PAGE_NO_EXEC);
161	protection_map[2] = __pgprot(_page_cachable_default \| _PAGE_PRESENT \| _PAGE_NO_EXEC \| _PAGE_NO_READ);	161	protection_map[2] = __pgprot(_page_cachable_default \| _PAGE_PRESENT \| _PAGE_NO_EXEC \| _PAGE_NO_READ);
162	protection_map[3] = __pgprot(_page_cachable_default \| _PAGE_PRESENT \| _PAGE_NO_EXEC);	162	protection_map[3] = __pgprot(_page_cachable_default \| _PAGE_PRESENT \| _PAGE_NO_EXEC);
163	protection_map[4] = __pgprot(_page_cachable_default \| _PAGE_PRESENT \| _PAGE_NO_READ);	163	protection_map[4] = __pgprot(_page_cachable_default \| _PAGE_PRESENT);
164	protection_map[5] = __pgprot(_page_cachable_default \| _PAGE_PRESENT);	164	protection_map[5] = __pgprot(_page_cachable_default \| _PAGE_PRESENT);
165	protection_map[6] = __pgprot(_page_cachable_default \| _PAGE_PRESENT \| _PAGE_NO_READ);	165	protection_map[6] = __pgprot(_page_cachable_default \| _PAGE_PRESENT);
166	protection_map[7] = __pgprot(_page_cachable_default \| _PAGE_PRESENT);	166	protection_map[7] = __pgprot(_page_cachable_default \| _PAGE_PRESENT);
167		167
168	protection_map[8] = __pgprot(_page_cachable_default \| _PAGE_PRESENT \| _PAGE_NO_EXEC \| _PAGE_NO_READ);	168	protection_map[8] = __pgprot(_page_cachable_default \| _PAGE_PRESENT \| _PAGE_NO_EXEC \| _PAGE_NO_READ);
169	protection_map[9] = __pgprot(_page_cachable_default \| _PAGE_PRESENT \| _PAGE_NO_EXEC);	169	protection_map[9] = __pgprot(_page_cachable_default \| _PAGE_PRESENT \| _PAGE_NO_EXEC);
170	protection_map[10] = __pgprot(_page_cachable_default \| _PAGE_PRESENT \| _PAGE_NO_EXEC \| _PAGE_WRITE \| _PAGE_NO_READ);	170	protection_map[10] = __pgprot(_page_cachable_default \| _PAGE_PRESENT \| _PAGE_NO_EXEC \| _PAGE_WRITE \| _PAGE_NO_READ);
171	protection_map[11] = __pgprot(_page_cachable_default \| _PAGE_PRESENT \| _PAGE_NO_EXEC \| _PAGE_WRITE);	171	protection_map[11] = __pgprot(_page_cachable_default \| _PAGE_PRESENT \| _PAGE_NO_EXEC \| _PAGE_WRITE);
172	protection_map[12] = __pgprot(_page_cachable_default \| _PAGE_PRESENT \| _PAGE_NO_READ);	172	protection_map[12] = __pgprot(_page_cachable_default \| _PAGE_PRESENT);
173	protection_map[13] = __pgprot(_page_cachable_default \| _PAGE_PRESENT);	173	protection_map[13] = __pgprot(_page_cachable_default \| _PAGE_PRESENT);
174	protection_map[14] = __pgprot(_page_cachable_default \| _PAGE_PRESENT \| _PAGE_WRITE \| _PAGE_NO_READ);	174	protection_map[14] = __pgprot(_page_cachable_default \| _PAGE_PRESENT \| _PAGE_WRITE);
175	protection_map[15] = __pgprot(_page_cachable_default \| _PAGE_PRESENT \| _PAGE_WRITE);	175	protection_map[15] = __pgprot(_page_cachable_default \| _PAGE_PRESENT \| _PAGE_WRITE);
176		176
177	} else {	177	} else {

@@ -269,7 +269,7 @@ static void emit_bpf_tail_call(u8 **pprog) · 268 unmodified lines
269	EMIT4(0x48, 0x8B, 0x46, /* mov rax, qword ptr [rsi + 16] */	269	EMIT4(0x48, 0x8B, 0x46, /* mov rax, qword ptr [rsi + 16] */
270	offsetof(struct bpf_array, map.max_entries));	270	offsetof(struct bpf_array, map.max_entries));
271	EMIT3(0x48, 0x39, 0xD0); /* cmp rax, rdx */	271	EMIT3(0x48, 0x39, 0xD0); /* cmp rax, rdx */
272	#define OFFSET1 44 /* number of bytes to jump */	272	#define OFFSET1 47 /* number of bytes to jump */
273	EMIT2(X86_JBE, OFFSET1); /* jbe out */	273	EMIT2(X86_JBE, OFFSET1); /* jbe out */
274	label1 = cnt;	274	label1 = cnt;
275		275
@@ -278,15 +278,15 @@ static void emit_bpf_tail_call(u8 **pprog) · 2 unmodified lines
278	*/	278	*/
279	EMIT2_off32(0x8B, 0x85, -STACKSIZE + 36); /* mov eax, dword ptr [rbp - 516] */	279	EMIT2_off32(0x8B, 0x85, -STACKSIZE + 36); /* mov eax, dword ptr [rbp - 516] */
280	EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */	280	EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */
281	#define OFFSET2 33	281	#define OFFSET2 36
282	EMIT2(X86_JA, OFFSET2); /* ja out */	282	EMIT2(X86_JA, OFFSET2); /* ja out */
283	label2 = cnt;	283	label2 = cnt;
284	EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */	284	EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */
285	EMIT2_off32(0x89, 0x85, -STACKSIZE + 36); /* mov dword ptr [rbp - 516], eax */	285	EMIT2_off32(0x89, 0x85, -STACKSIZE + 36); /* mov dword ptr [rbp - 516], eax */
286		286
287	/* prog = array->prog[index]; */	287	/* prog = array->prog[index]; */
288	EMIT4(0x48, 0x8D, 0x44, 0xD6); /* lea rax, [rsi + rdx * 8 + 0x50] */	288	EMIT4_off32(0x48, 0x8D, 0x84, 0xD6, /* lea rax, [rsi + rdx * 8 + offsetof(...)] */
289	EMIT1(offsetof(struct bpf_array, prog));	289	offsetof(struct bpf_array, prog));
290	EMIT3(0x48, 0x8B, 0x00); /* mov rax, qword ptr [rax] */	290	EMIT3(0x48, 0x8B, 0x00); /* mov rax, qword ptr [rax] */
291		291
292	/* if (prog == NULL)	292	/* if (prog == NULL)